1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
6 #include <rte_cycles.h>
7 #include <rte_eal_paging.h>
9 #include <mlx5_malloc.h>
10 #include <mlx5_common_os.h>
11 #include <mlx5_common_devx.h>
14 #include "mlx5_flow.h"
17 * Destroy Completion Queue used for ASO access.
23 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
26 mlx5_devx_cq_destroy(&cq->cq_obj);
27 memset(cq, 0, sizeof(*cq));
31 * Create Completion Queue used for ASO access.
34 * Context returned from mlx5 open_device() glue function.
36 * Pointer to CQ to create.
37 * @param[in] log_desc_n
38 * Log of number of descriptors in queue.
40 * Socket to use for allocation.
41 * @param[in] uar_page_id
45 * 0 on success, a negative errno value otherwise and rte_errno is set.
48 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
49 int socket, int uar_page_id)
51 struct mlx5_devx_cq_attr attr = {
52 .uar_page_id = uar_page_id,
55 cq->log_desc_n = log_desc_n;
57 return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
64 * Pointer to shared device context.
69 mlx5_aso_dereg_mr(struct mlx5_dev_ctx_shared *sh, struct mlx5_pmd_mr *mr)
71 void *addr = mr->addr;
73 sh->share_cache.dereg_mr_cb(mr);
75 memset(mr, 0, sizeof(*mr));
79 * Register Memory Region.
82 * Pointer to shared device context.
86 * Pointer to MR to create.
88 * Socket to use for allocation.
91 * 0 on success, a negative errno value otherwise and rte_errno is set.
94 mlx5_aso_reg_mr(struct mlx5_dev_ctx_shared *sh, size_t length,
95 struct mlx5_pmd_mr *mr, int socket)
100 mr->addr = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
103 DRV_LOG(ERR, "Failed to create ASO bits mem for MR.");
106 ret = sh->share_cache.reg_mr_cb(sh->pd, mr->addr, length, mr);
108 DRV_LOG(ERR, "Failed to create direct Mkey.");
116 * Destroy Send Queue used for ASO access.
122 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
124 mlx5_devx_sq_destroy(&sq->sq_obj);
125 mlx5_aso_cq_destroy(&sq->cq);
126 memset(sq, 0, sizeof(*sq));
130 * Initialize Send Queue used for ASO access.
133 * ASO SQ to initialize.
136 mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
138 volatile struct mlx5_aso_wqe *restrict wqe;
140 int size = 1 << sq->log_desc_n;
143 /* All the next fields state should stay constant. */
144 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
145 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
146 (sizeof(*wqe) >> 4));
147 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey);
148 addr = (uint64_t)((uint64_t *)sq->mr.addr + i *
149 MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
150 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
151 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
152 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
154 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
155 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
156 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
157 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
158 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
163 * Initialize Send Queue used for ASO flow meter access.
166 * ASO SQ to initialize.
169 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
171 volatile struct mlx5_aso_wqe *restrict wqe;
173 int size = 1 << sq->log_desc_n;
175 /* All the next fields state should stay constant. */
176 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
177 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
178 (sizeof(*wqe) >> 4));
179 wqe->aso_cseg.operand_masks = RTE_BE32(0u |
180 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
181 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
182 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
183 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
184 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
185 MLX5_COMP_MODE_OFFSET);
190 * Initialize Send Queue used for ASO connection tracking.
193 * ASO SQ to initialize.
196 mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)
198 volatile struct mlx5_aso_wqe *restrict wqe;
200 int size = 1 << sq->log_desc_n;
203 /* All the next fields state should stay constant. */
204 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
205 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
206 (sizeof(*wqe) >> 4));
207 /* One unique MR for the query data. */
208 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey);
209 /* Magic number 64 represents the length of a ASO CT obj. */
210 addr = (uint64_t)((uintptr_t)sq->mr.addr + i * 64);
211 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
212 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
214 * The values of operand_masks are different for modify
216 * And data_mask may be different for each modification. In
217 * query, it could be zero and ignored.
218 * CQE generation is always needed, in order to decide when
219 * it is available to create the flow or read the data.
221 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
222 MLX5_COMP_MODE_OFFSET);
227 * Create Send Queue used for ASO access.
230 * Context returned from mlx5 open_device() glue function.
232 * Pointer to SQ to create.
234 * Socket to use for allocation.
236 * User Access Region object.
238 * Protection Domain number to use.
239 * @param[in] log_desc_n
240 * Log of number of descriptors in queue.
241 * @param[in] ts_format
242 * timestamp format supported by the queue.
245 * 0 on success, a negative errno value otherwise and rte_errno is set.
248 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, void *uar,
249 uint32_t pdn, uint16_t log_desc_n, uint32_t ts_format)
251 struct mlx5_devx_create_sq_attr attr = {
252 .user_index = 0xFFFF,
253 .wq_attr = (struct mlx5_devx_wq_attr){
255 .uar_page = mlx5_os_get_devx_uar_page_id(uar),
257 .ts_format = mlx5_ts_format_conv(ts_format),
259 struct mlx5_devx_modify_sq_attr modify_attr = {
260 .state = MLX5_SQC_STATE_RDY,
265 if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
266 mlx5_os_get_devx_uar_page_id(uar)))
268 sq->log_desc_n = log_desc_n;
269 attr.cqn = sq->cq.cq_obj.cq->id;
270 /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
271 log_wqbb_n = log_desc_n + 1;
272 ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
274 DRV_LOG(ERR, "Can't create SQ object.");
278 ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
280 DRV_LOG(ERR, "Can't change SQ state to ready.");
287 sq->sqn = sq->sq_obj.sq->id;
288 sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
289 rte_spinlock_init(&sq->sqsl);
292 mlx5_aso_destroy_sq(sq);
297 * API to create and initialize Send Queue used for ASO access.
300 * Pointer to shared device context.
301 * @param[in] aso_opc_mod
302 * Mode of ASO feature.
305 * 0 on success, a negative errno value otherwise and rte_errno is set.
308 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
309 enum mlx5_access_aso_opc_mod aso_opc_mod)
311 uint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;
313 switch (aso_opc_mod) {
314 case ASO_OPC_MOD_FLOW_HIT:
315 if (mlx5_aso_reg_mr(sh, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
316 sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0))
318 if (mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
319 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
321 mlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);
324 mlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);
326 case ASO_OPC_MOD_POLICER:
327 if (mlx5_aso_sq_create(sh->ctx, &sh->mtrmng->pools_mng.sq, 0,
328 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
331 mlx5_aso_mtr_init_sq(&sh->mtrmng->pools_mng.sq);
333 case ASO_OPC_MOD_CONNECTION_TRACKING:
334 /* 64B per object for query. */
335 if (mlx5_aso_reg_mr(sh, 64 * sq_desc_n,
336 &sh->ct_mng->aso_sq.mr, 0))
338 if (mlx5_aso_sq_create(sh->ctx, &sh->ct_mng->aso_sq, 0,
339 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
341 mlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);
344 mlx5_aso_ct_init_sq(&sh->ct_mng->aso_sq);
347 DRV_LOG(ERR, "Unknown ASO operation mode");
354 * API to destroy Send Queue used for ASO access.
357 * Pointer to shared device context.
358 * @param[in] aso_opc_mod
359 * Mode of ASO feature.
362 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
363 enum mlx5_access_aso_opc_mod aso_opc_mod)
365 struct mlx5_aso_sq *sq;
367 switch (aso_opc_mod) {
368 case ASO_OPC_MOD_FLOW_HIT:
369 mlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);
370 sq = &sh->aso_age_mng->aso_sq;
372 case ASO_OPC_MOD_POLICER:
373 sq = &sh->mtrmng->pools_mng.sq;
375 case ASO_OPC_MOD_CONNECTION_TRACKING:
376 mlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);
377 sq = &sh->ct_mng->aso_sq;
380 DRV_LOG(ERR, "Unknown ASO operation mode");
383 mlx5_aso_destroy_sq(sq);
387 * Write a burst of WQEs to ASO SQ.
390 * ASO management data, contains the SQ.
392 * Index of the last valid pool.
395 * Number of WQEs in burst.
398 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
400 volatile struct mlx5_aso_wqe *wqe;
401 struct mlx5_aso_sq *sq = &mng->aso_sq;
402 struct mlx5_aso_age_pool *pool;
403 uint16_t size = 1 << sq->log_desc_n;
404 uint16_t mask = size - 1;
406 uint16_t start_head = sq->head;
408 max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
411 sq->elts[start_head & mask].burst_size = max;
413 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
414 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
416 rte_spinlock_lock(&mng->resize_sl);
417 pool = mng->pools[sq->next];
418 rte_spinlock_unlock(&mng->resize_sl);
419 sq->elts[sq->head & mask].pool = pool;
420 wqe->general_cseg.misc =
421 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
422 (pool->flow_hit_aso_obj))->id);
423 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
424 MLX5_COMP_MODE_OFFSET);
425 wqe->general_cseg.opcode = rte_cpu_to_be_32
426 (MLX5_OPCODE_ACCESS_ASO |
427 (ASO_OPC_MOD_FLOW_HIT <<
428 WQE_CSEG_OPC_MOD_OFFSET) |
430 WQE_CSEG_WQE_INDEX_OFFSET));
431 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
436 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
437 MLX5_COMP_MODE_OFFSET);
439 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
441 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
443 return sq->elts[start_head & mask].burst_size;
447 * Debug utility function. Dump contents of error CQE and WQE.
455 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
459 DRV_LOG(ERR, "Error cqe:");
460 for (i = 0; i < 16; i += 4)
461 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
462 cqe[i + 2], cqe[i + 3]);
463 DRV_LOG(ERR, "\nError wqe:");
464 for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
465 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
466 wqe[i + 2], wqe[i + 3]);
470 * Handle case of error CQE.
476 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
478 struct mlx5_aso_cq *cq = &sq->cq;
479 uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
480 volatile struct mlx5_err_cqe *cqe =
481 (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
484 idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
485 mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
486 (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
490 * Update ASO objects upon completion.
493 * Shared device context.
495 * Number of completed ASO objects.
498 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
500 struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
501 struct mlx5_aso_sq *sq = &mng->aso_sq;
502 struct mlx5_age_info *age_info;
503 const uint16_t size = 1 << sq->log_desc_n;
504 const uint16_t mask = size - 1;
505 const uint64_t curr = MLX5_CURR_TIME_SEC;
506 uint16_t expected = AGE_CANDIDATE;
509 for (i = 0; i < n; ++i) {
510 uint16_t idx = (sq->tail + i) & mask;
511 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
512 uint64_t diff = curr - pool->time_of_last_age_check;
513 uint64_t *addr = sq->mr.addr;
516 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
517 pool->time_of_last_age_check = curr;
518 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
519 struct mlx5_aso_age_action *act = &pool->actions[j];
520 struct mlx5_age_param *ap = &act->age_params;
526 if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
531 u8addr = (uint8_t *)addr;
532 hit = (u8addr[byte] >> offset) & 0x1;
534 __atomic_store_n(&ap->sec_since_last_hit, 0,
537 struct mlx5_priv *priv;
539 __atomic_fetch_add(&ap->sec_since_last_hit,
540 diff, __ATOMIC_RELAXED);
541 /* If timeout passed add to aged-out list. */
542 if (ap->sec_since_last_hit <= ap->timeout)
545 rte_eth_devices[ap->port_id].data->dev_private;
546 age_info = GET_PORT_AGE_INFO(priv);
547 rte_spinlock_lock(&age_info->aged_sl);
548 if (__atomic_compare_exchange_n(&ap->state,
554 LIST_INSERT_HEAD(&age_info->aged_aso,
556 MLX5_AGE_SET(age_info,
559 rte_spinlock_unlock(&age_info->aged_sl);
563 mlx5_age_event_prepare(sh);
567 * Handle completions from WQEs sent to ASO SQ.
570 * Shared device context.
573 * Number of CQEs handled.
576 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
578 struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
579 struct mlx5_aso_sq *sq = &mng->aso_sq;
580 struct mlx5_aso_cq *cq = &sq->cq;
581 volatile struct mlx5_cqe *restrict cqe;
582 const unsigned int cq_size = 1 << cq->log_desc_n;
583 const unsigned int mask = cq_size - 1;
585 uint32_t next_idx = cq->cq_ci & mask;
586 const uint16_t max = (uint16_t)(sq->head - sq->tail);
593 next_idx = (cq->cq_ci + 1) & mask;
594 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
595 cqe = &cq->cq_obj.cqes[idx];
596 ret = check_cqe(cqe, cq_size, cq->cq_ci);
598 * Be sure owner read is done before any other cookie field or
602 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
603 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
605 mlx5_aso_cqe_err_handle(sq);
607 i += sq->elts[(sq->tail + i) & mask].burst_size;
612 mlx5_aso_age_action_update(sh, i);
615 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
621 * Periodically read CQEs and send WQEs to ASO SQ.
624 * Shared device context containing the ASO SQ.
627 mlx5_flow_aso_alarm(void *arg)
629 struct mlx5_dev_ctx_shared *sh = arg;
630 struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
634 rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
635 n = sh->aso_age_mng->next;
636 rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
637 mlx5_aso_completion_handle(sh);
639 /* End of loop: wait 1 second. */
643 mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
644 if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
645 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
649 * API to start ASO access using ASO SQ.
652 * Pointer to shared device context.
655 * 0 on success, a negative errno value otherwise and rte_errno is set.
658 mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh)
660 if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
661 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
668 * API to stop ASO access using ASO SQ.
671 * Pointer to shared device context.
674 * 0 on success, a negative errno value otherwise and rte_errno is set.
677 mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh)
681 if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
685 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
686 if (rte_errno != EINPROGRESS)
694 mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
695 struct mlx5_aso_mtr *aso_mtr)
697 volatile struct mlx5_aso_wqe *wqe = NULL;
698 struct mlx5_flow_meter_info *fm = NULL;
699 struct mlx5_flow_meter_profile *fmp;
700 uint16_t size = 1 << sq->log_desc_n;
701 uint16_t mask = size - 1;
703 uint32_t dseg_idx = 0;
704 struct mlx5_aso_mtr_pool *pool = NULL;
706 rte_spinlock_lock(&sq->sqsl);
707 res = size - (uint16_t)(sq->head - sq->tail);
708 if (unlikely(!res)) {
709 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
710 rte_spinlock_unlock(&sq->sqsl);
713 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
714 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
717 sq->elts[sq->head & mask].mtr = aso_mtr;
718 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
719 mtrs[aso_mtr->offset]);
720 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
721 (aso_mtr->offset >> 1));
722 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
723 (ASO_OPC_MOD_POLICER <<
724 WQE_CSEG_OPC_MOD_OFFSET) |
725 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
726 /* There are 2 meters in one ASO cache line. */
727 dseg_idx = aso_mtr->offset & 0x1;
728 wqe->aso_cseg.data_mask =
729 RTE_BE64(MLX5_IFC_FLOW_METER_PARAM_MASK << (32 * !dseg_idx));
731 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
732 fm->profile->srtcm_prm.cbs_cir;
733 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir =
734 fm->profile->srtcm_prm.ebs_eir;
736 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
737 RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL);
738 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir = 0;
741 if (fmp->profile.packet_mode)
742 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
743 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
744 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET) |
745 (MLX5_METER_MODE_PKT << ASO_DSEG_MTR_MODE));
747 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
748 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
749 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
751 sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
753 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
755 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
757 rte_spinlock_unlock(&sq->sqsl);
762 mlx5_aso_mtrs_status_update(struct mlx5_aso_sq *sq, uint16_t aso_mtrs_nums)
764 uint16_t size = 1 << sq->log_desc_n;
765 uint16_t mask = size - 1;
767 struct mlx5_aso_mtr *aso_mtr = NULL;
768 uint8_t exp_state = ASO_METER_WAIT;
770 for (i = 0; i < aso_mtrs_nums; ++i) {
771 aso_mtr = sq->elts[(sq->tail + i) & mask].mtr;
772 MLX5_ASSERT(aso_mtr);
773 (void)__atomic_compare_exchange_n(&aso_mtr->state,
774 &exp_state, ASO_METER_READY,
775 false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
780 mlx5_aso_mtr_completion_handle(struct mlx5_aso_sq *sq)
782 struct mlx5_aso_cq *cq = &sq->cq;
783 volatile struct mlx5_cqe *restrict cqe;
784 const unsigned int cq_size = 1 << cq->log_desc_n;
785 const unsigned int mask = cq_size - 1;
787 uint32_t next_idx = cq->cq_ci & mask;
792 rte_spinlock_lock(&sq->sqsl);
793 max = (uint16_t)(sq->head - sq->tail);
794 if (unlikely(!max)) {
795 rte_spinlock_unlock(&sq->sqsl);
800 next_idx = (cq->cq_ci + 1) & mask;
801 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
802 cqe = &cq->cq_obj.cqes[idx];
803 ret = check_cqe(cqe, cq_size, cq->cq_ci);
805 * Be sure owner read is done before any other cookie field or
809 if (ret != MLX5_CQE_STATUS_SW_OWN) {
810 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
812 mlx5_aso_cqe_err_handle(sq);
819 mlx5_aso_mtrs_status_update(sq, n);
822 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
824 rte_spinlock_unlock(&sq->sqsl);
828 * Update meter parameter by send WQE.
831 * Pointer to Ethernet device.
833 * Pointer to mlx5 private data structure.
835 * Pointer to flow meter to be modified.
838 * 0 on success, a negative errno value otherwise and rte_errno is set.
841 mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
842 struct mlx5_aso_mtr *mtr)
844 struct mlx5_aso_sq *sq = &sh->mtrmng->pools_mng.sq;
845 uint32_t poll_wqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
848 mlx5_aso_mtr_completion_handle(sq);
849 if (mlx5_aso_mtr_sq_enqueue_single(sq, mtr))
851 /* Waiting for wqe resource. */
852 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
853 } while (--poll_wqe_times);
854 DRV_LOG(ERR, "Fail to send WQE for ASO meter offset %d",
860 * Wait for meter to be ready.
863 * Pointer to Ethernet device.
865 * Pointer to mlx5 private data structure.
867 * Pointer to flow meter to be modified.
870 * 0 on success, a negative errno value otherwise and rte_errno is set.
873 mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
874 struct mlx5_aso_mtr *mtr)
876 struct mlx5_aso_sq *sq = &sh->mtrmng->pools_mng.sq;
877 uint32_t poll_cqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
879 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
883 mlx5_aso_mtr_completion_handle(sq);
884 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
887 /* Waiting for CQE ready. */
888 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
889 } while (--poll_cqe_times);
890 DRV_LOG(ERR, "Fail to poll CQE ready for ASO meter offset %d",
896 * Post a WQE to the ASO CT SQ to modify the context.
899 * Pointer to the CT pools management structure.
901 * Pointer to the generic CT structure related to the context.
903 * Pointer to configuration profile.
906 * 1 on success (WQE number), 0 on failure.
909 mlx5_aso_ct_sq_enqueue_single(struct mlx5_aso_ct_pools_mng *mng,
910 struct mlx5_aso_ct_action *ct,
911 const struct rte_flow_action_conntrack *profile)
913 volatile struct mlx5_aso_wqe *wqe = NULL;
914 struct mlx5_aso_sq *sq = &mng->aso_sq;
915 uint16_t size = 1 << sq->log_desc_n;
916 uint16_t mask = size - 1;
918 struct mlx5_aso_ct_pool *pool;
923 rte_spinlock_lock(&sq->sqsl);
924 /* Prevent other threads to update the index. */
925 res = size - (uint16_t)(sq->head - sq->tail);
926 if (unlikely(!res)) {
927 rte_spinlock_unlock(&sq->sqsl);
928 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
931 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
932 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
934 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_WAIT);
935 sq->elts[sq->head & mask].ct = ct;
936 sq->elts[sq->head & mask].query_data = NULL;
937 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
938 /* Each WQE will have a single CT object. */
939 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
941 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
942 (ASO_OPC_MOD_CONNECTION_TRACKING <<
943 WQE_CSEG_OPC_MOD_OFFSET) |
944 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
945 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
947 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
948 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
949 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
950 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
951 wqe->aso_cseg.data_mask = UINT64_MAX;
952 /* To make compiler happy. */
953 desg = (void *)(uintptr_t)wqe->aso_dseg.data;
954 MLX5_SET(conn_track_aso, desg, valid, 1);
955 MLX5_SET(conn_track_aso, desg, state, profile->state);
956 MLX5_SET(conn_track_aso, desg, freeze_track, !profile->enable);
957 MLX5_SET(conn_track_aso, desg, connection_assured,
958 profile->live_connection);
959 MLX5_SET(conn_track_aso, desg, sack_permitted, profile->selective_ack);
960 MLX5_SET(conn_track_aso, desg, challenged_acked,
961 profile->challenge_ack_passed);
962 /* Heartbeat, retransmission_counter, retranmission_limit_exceeded: 0 */
963 MLX5_SET(conn_track_aso, desg, heartbeat, 0);
964 MLX5_SET(conn_track_aso, desg, max_ack_window,
965 profile->max_ack_window);
966 MLX5_SET(conn_track_aso, desg, retransmission_counter, 0);
967 MLX5_SET(conn_track_aso, desg, retranmission_limit_exceeded, 0);
968 MLX5_SET(conn_track_aso, desg, retranmission_limit,
969 profile->retransmission_limit);
970 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_scale,
971 profile->reply_dir.scale);
972 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_close_initiated,
973 profile->reply_dir.close_initiated);
974 /* Both directions will use the same liberal mode. */
975 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_liberal_enabled,
976 profile->liberal_mode);
977 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_data_unacked,
978 profile->reply_dir.data_unacked);
979 MLX5_SET(conn_track_aso, desg, reply_direction_tcp_max_ack,
980 profile->reply_dir.last_ack_seen);
981 MLX5_SET(conn_track_aso, desg, original_direction_tcp_scale,
982 profile->original_dir.scale);
983 MLX5_SET(conn_track_aso, desg, original_direction_tcp_close_initiated,
984 profile->original_dir.close_initiated);
985 MLX5_SET(conn_track_aso, desg, original_direction_tcp_liberal_enabled,
986 profile->liberal_mode);
987 MLX5_SET(conn_track_aso, desg, original_direction_tcp_data_unacked,
988 profile->original_dir.data_unacked);
989 MLX5_SET(conn_track_aso, desg, original_direction_tcp_max_ack,
990 profile->original_dir.last_ack_seen);
991 MLX5_SET(conn_track_aso, desg, last_win, profile->last_window);
992 MLX5_SET(conn_track_aso, desg, last_dir, profile->last_direction);
993 MLX5_SET(conn_track_aso, desg, last_index, profile->last_index);
994 MLX5_SET(conn_track_aso, desg, last_seq, profile->last_seq);
995 MLX5_SET(conn_track_aso, desg, last_ack, profile->last_ack);
996 MLX5_SET(conn_track_aso, desg, last_end, profile->last_end);
997 orig_dir = MLX5_ADDR_OF(conn_track_aso, desg, original_dir);
998 MLX5_SET(tcp_window_params, orig_dir, sent_end,
999 profile->original_dir.sent_end);
1000 MLX5_SET(tcp_window_params, orig_dir, reply_end,
1001 profile->original_dir.reply_end);
1002 MLX5_SET(tcp_window_params, orig_dir, max_win,
1003 profile->original_dir.max_win);
1004 MLX5_SET(tcp_window_params, orig_dir, max_ack,
1005 profile->original_dir.max_ack);
1006 reply_dir = MLX5_ADDR_OF(conn_track_aso, desg, reply_dir);
1007 MLX5_SET(tcp_window_params, reply_dir, sent_end,
1008 profile->reply_dir.sent_end);
1009 MLX5_SET(tcp_window_params, reply_dir, reply_end,
1010 profile->reply_dir.reply_end);
1011 MLX5_SET(tcp_window_params, reply_dir, max_win,
1012 profile->reply_dir.max_win);
1013 MLX5_SET(tcp_window_params, reply_dir, max_ack,
1014 profile->reply_dir.max_ack);
1016 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
1018 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
1020 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
1022 rte_spinlock_unlock(&sq->sqsl);
1027 * Update the status field of CTs to indicate ready to be used by flows.
1028 * A continuous number of CTs since last update.
1031 * Pointer to ASO CT SQ.
1033 * Number of CT structures to be updated.
1036 * 0 on success, a negative value.
1039 mlx5_aso_ct_status_update(struct mlx5_aso_sq *sq, uint16_t num)
1041 uint16_t size = 1 << sq->log_desc_n;
1042 uint16_t mask = size - 1;
1044 struct mlx5_aso_ct_action *ct = NULL;
1047 for (i = 0; i < num; i++) {
1048 idx = (uint16_t)((sq->tail + i) & mask);
1049 ct = sq->elts[idx].ct;
1051 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_READY);
1052 if (sq->elts[idx].query_data)
1053 rte_memcpy(sq->elts[idx].query_data,
1054 (char *)((uintptr_t)sq->mr.addr + idx * 64),
1060 * Post a WQE to the ASO CT SQ to query the current context.
1063 * Pointer to the CT pools management structure.
1065 * Pointer to the generic CT structure related to the context.
1067 * Pointer to data area to be filled.
1070 * 1 on success (WQE number), 0 on failure.
1073 mlx5_aso_ct_sq_query_single(struct mlx5_aso_ct_pools_mng *mng,
1074 struct mlx5_aso_ct_action *ct, char *data)
1076 volatile struct mlx5_aso_wqe *wqe = NULL;
1077 struct mlx5_aso_sq *sq = &mng->aso_sq;
1078 uint16_t size = 1 << sq->log_desc_n;
1079 uint16_t mask = size - 1;
1082 struct mlx5_aso_ct_pool *pool;
1083 enum mlx5_aso_ct_state state =
1084 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
1086 if (state == ASO_CONNTRACK_FREE) {
1087 DRV_LOG(ERR, "Fail: No context to query");
1089 } else if (state == ASO_CONNTRACK_WAIT) {
1092 rte_spinlock_lock(&sq->sqsl);
1093 res = size - (uint16_t)(sq->head - sq->tail);
1094 if (unlikely(!res)) {
1095 rte_spinlock_unlock(&sq->sqsl);
1096 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
1099 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_QUERY);
1100 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
1101 /* Confirm the location and address of the prefetch instruction. */
1102 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
1103 /* Fill next WQE. */
1104 wqe_idx = sq->head & mask;
1105 sq->elts[wqe_idx].ct = ct;
1106 sq->elts[wqe_idx].query_data = data;
1107 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1108 /* Each WQE will have a single CT object. */
1109 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
1111 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
1112 (ASO_OPC_MOD_CONNECTION_TRACKING <<
1113 WQE_CSEG_OPC_MOD_OFFSET) |
1114 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
1116 * There is no write request is required.
1117 * ASO_OPER_LOGICAL_AND and ASO_OP_ALWAYS_FALSE are both 0.
1118 * "BYTEWISE_64BYTE" is needed for a whole context.
1119 * Set to 0 directly to reduce an endian swap. (Modify should rewrite.)
1120 * "data_mask" is ignored.
1121 * Buffer address was already filled during initialization.
1123 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32(BYTEWISE_64BYTE <<
1124 ASO_CSEG_DATA_MASK_MODE_OFFSET);
1125 wqe->aso_cseg.data_mask = 0;
1128 * Each WQE contains 2 WQEBB's, even though
1129 * data segment is not used in this case.
1133 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
1135 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
1137 rte_spinlock_unlock(&sq->sqsl);
1142 * Handle completions from WQEs sent to ASO CT.
1145 * Pointer to the CT pools management structure.
1148 mlx5_aso_ct_completion_handle(struct mlx5_aso_ct_pools_mng *mng)
1150 struct mlx5_aso_sq *sq = &mng->aso_sq;
1151 struct mlx5_aso_cq *cq = &sq->cq;
1152 volatile struct mlx5_cqe *restrict cqe;
1153 const uint32_t cq_size = 1 << cq->log_desc_n;
1154 const uint32_t mask = cq_size - 1;
1161 rte_spinlock_lock(&sq->sqsl);
1162 max = (uint16_t)(sq->head - sq->tail);
1163 if (unlikely(!max)) {
1164 rte_spinlock_unlock(&sq->sqsl);
1167 next_idx = cq->cq_ci & mask;
1170 next_idx = (cq->cq_ci + 1) & mask;
1171 /* Need to confirm the position of the prefetch. */
1172 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
1173 cqe = &cq->cq_obj.cqes[idx];
1174 ret = check_cqe(cqe, cq_size, cq->cq_ci);
1176 * Be sure owner read is done before any other cookie field or
1180 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1181 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
1183 mlx5_aso_cqe_err_handle(sq);
1190 mlx5_aso_ct_status_update(sq, n);
1193 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
1195 rte_spinlock_unlock(&sq->sqsl);
1199 * Update connection tracking ASO context by sending WQE.
1202 * Pointer to mlx5_dev_ctx_shared object.
1204 * Pointer to connection tracking offload object.
1205 * @param[in] profile
1206 * Pointer to connection tracking TCP parameter.
1209 * 0 on success, -1 on failure.
1212 mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1213 struct mlx5_aso_ct_action *ct,
1214 const struct rte_flow_action_conntrack *profile)
1216 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1217 uint32_t poll_wqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1218 struct mlx5_aso_ct_pool *pool;
1222 mlx5_aso_ct_completion_handle(mng);
1223 if (mlx5_aso_ct_sq_enqueue_single(mng, ct, profile))
1225 /* Waiting for wqe resource. */
1226 rte_delay_us_sleep(10u);
1227 } while (--poll_wqe_times);
1228 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1229 DRV_LOG(ERR, "Fail to send WQE for ASO CT %d in pool %d",
1230 ct->offset, pool->index);
1235 * The routine is used to wait for WQE completion to continue with queried data.
1238 * Pointer to mlx5_dev_ctx_shared object.
1240 * Pointer to connection tracking offload object.
1243 * 0 on success, -1 on failure.
1246 mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh,
1247 struct mlx5_aso_ct_action *ct)
1249 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1250 uint32_t poll_cqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1251 struct mlx5_aso_ct_pool *pool;
1253 if (__atomic_load_n(&ct->state, __ATOMIC_RELAXED) ==
1254 ASO_CONNTRACK_READY)
1257 mlx5_aso_ct_completion_handle(mng);
1258 if (__atomic_load_n(&ct->state, __ATOMIC_RELAXED) ==
1259 ASO_CONNTRACK_READY)
1261 /* Waiting for CQE ready, consider should block or sleep. */
1262 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
1263 } while (--poll_cqe_times);
1264 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1265 DRV_LOG(ERR, "Fail to poll CQE for ASO CT %d in pool %d",
1266 ct->offset, pool->index);
1271 * Convert the hardware conntrack data format into the profile.
1273 * @param[in] profile
1274 * Pointer to conntrack profile to be filled after query.
1276 * Pointer to data fetched from hardware.
1279 mlx5_aso_ct_obj_analyze(struct rte_flow_action_conntrack *profile,
1282 void *o_dir = MLX5_ADDR_OF(conn_track_aso, wdata, original_dir);
1283 void *r_dir = MLX5_ADDR_OF(conn_track_aso, wdata, reply_dir);
1285 /* MLX5_GET16 should be taken into consideration. */
1286 profile->state = (enum rte_flow_conntrack_state)
1287 MLX5_GET(conn_track_aso, wdata, state);
1288 profile->enable = !MLX5_GET(conn_track_aso, wdata, freeze_track);
1289 profile->selective_ack = MLX5_GET(conn_track_aso, wdata,
1291 profile->live_connection = MLX5_GET(conn_track_aso, wdata,
1292 connection_assured);
1293 profile->challenge_ack_passed = MLX5_GET(conn_track_aso, wdata,
1295 profile->max_ack_window = MLX5_GET(conn_track_aso, wdata,
1297 profile->retransmission_limit = MLX5_GET(conn_track_aso, wdata,
1298 retranmission_limit);
1299 profile->last_window = MLX5_GET(conn_track_aso, wdata, last_win);
1300 profile->last_direction = MLX5_GET(conn_track_aso, wdata, last_dir);
1301 profile->last_index = (enum rte_flow_conntrack_tcp_last_index)
1302 MLX5_GET(conn_track_aso, wdata, last_index);
1303 profile->last_seq = MLX5_GET(conn_track_aso, wdata, last_seq);
1304 profile->last_ack = MLX5_GET(conn_track_aso, wdata, last_ack);
1305 profile->last_end = MLX5_GET(conn_track_aso, wdata, last_end);
1306 profile->liberal_mode = MLX5_GET(conn_track_aso, wdata,
1307 reply_direction_tcp_liberal_enabled) |
1308 MLX5_GET(conn_track_aso, wdata,
1309 original_direction_tcp_liberal_enabled);
1310 /* No liberal in the RTE structure profile. */
1311 profile->reply_dir.scale = MLX5_GET(conn_track_aso, wdata,
1312 reply_direction_tcp_scale);
1313 profile->reply_dir.close_initiated = MLX5_GET(conn_track_aso, wdata,
1314 reply_direction_tcp_close_initiated);
1315 profile->reply_dir.data_unacked = MLX5_GET(conn_track_aso, wdata,
1316 reply_direction_tcp_data_unacked);
1317 profile->reply_dir.last_ack_seen = MLX5_GET(conn_track_aso, wdata,
1318 reply_direction_tcp_max_ack);
1319 profile->reply_dir.sent_end = MLX5_GET(tcp_window_params,
1321 profile->reply_dir.reply_end = MLX5_GET(tcp_window_params,
1323 profile->reply_dir.max_win = MLX5_GET(tcp_window_params,
1325 profile->reply_dir.max_ack = MLX5_GET(tcp_window_params,
1327 profile->original_dir.scale = MLX5_GET(conn_track_aso, wdata,
1328 original_direction_tcp_scale);
1329 profile->original_dir.close_initiated = MLX5_GET(conn_track_aso, wdata,
1330 original_direction_tcp_close_initiated);
1331 profile->original_dir.data_unacked = MLX5_GET(conn_track_aso, wdata,
1332 original_direction_tcp_data_unacked);
1333 profile->original_dir.last_ack_seen = MLX5_GET(conn_track_aso, wdata,
1334 original_direction_tcp_max_ack);
1335 profile->original_dir.sent_end = MLX5_GET(tcp_window_params,
1337 profile->original_dir.reply_end = MLX5_GET(tcp_window_params,
1339 profile->original_dir.max_win = MLX5_GET(tcp_window_params,
1341 profile->original_dir.max_ack = MLX5_GET(tcp_window_params,
1346 * Query connection tracking information parameter by send WQE.
1349 * Pointer to Ethernet device.
1351 * Pointer to connection tracking offload object.
1352 * @param[out] profile
1353 * Pointer to connection tracking TCP information.
1356 * 0 on success, -1 on failure.
1359 mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
1360 struct mlx5_aso_ct_action *ct,
1361 struct rte_flow_action_conntrack *profile)
1363 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1364 uint32_t poll_wqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1365 struct mlx5_aso_ct_pool *pool;
1366 char out_data[64 * 2];
1371 mlx5_aso_ct_completion_handle(mng);
1372 ret = mlx5_aso_ct_sq_query_single(mng, ct, out_data);
1377 /* Waiting for wqe resource or state. */
1379 rte_delay_us_sleep(10u);
1380 } while (--poll_wqe_times);
1381 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1382 DRV_LOG(ERR, "Fail to send WQE for ASO CT %d in pool %d",
1383 ct->offset, pool->index);
1386 ret = mlx5_aso_ct_wait_ready(sh, ct);
1388 mlx5_aso_ct_obj_analyze(profile, out_data);