1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
6 #include <rte_cycles.h>
7 #include <rte_eal_paging.h>
9 #include <mlx5_malloc.h>
10 #include <mlx5_common_os.h>
11 #include <mlx5_common_devx.h>
14 #include "mlx5_flow.h"
17 * Destroy Completion Queue used for ASO access.
23 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
26 mlx5_devx_cq_destroy(&cq->cq_obj);
27 memset(cq, 0, sizeof(*cq));
31 * Create Completion Queue used for ASO access.
34 * Context returned from mlx5 open_device() glue function.
36 * Pointer to CQ to create.
37 * @param[in] log_desc_n
38 * Log of number of descriptors in queue.
40 * Socket to use for allocation.
41 * @param[in] uar_page_id
45 * 0 on success, a negative errno value otherwise and rte_errno is set.
48 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
49 int socket, int uar_page_id)
51 struct mlx5_devx_cq_attr attr = {
52 .uar_page_id = uar_page_id,
55 cq->log_desc_n = log_desc_n;
57 return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
67 mlx5_aso_devx_dereg_mr(struct mlx5_aso_devx_mr *mr)
69 claim_zero(mlx5_devx_cmd_destroy(mr->mkey));
70 if (!mr->is_indirect && mr->umem)
71 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
73 memset(mr, 0, sizeof(*mr));
77 * Register Memory Region.
80 * Context returned from mlx5 open_device() glue function.
84 * Pointer to MR to create.
86 * Socket to use for allocation.
88 * Protection Domain number to use.
91 * 0 on success, a negative errno value otherwise and rte_errno is set.
94 mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr,
97 struct mlx5_devx_mkey_attr mkey_attr;
99 mr->buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
102 DRV_LOG(ERR, "Failed to create ASO bits mem for MR by Devx.");
105 mr->umem = mlx5_os_umem_reg(ctx, mr->buf, length,
106 IBV_ACCESS_LOCAL_WRITE);
108 DRV_LOG(ERR, "Failed to register Umem for MR by Devx.");
111 mkey_attr.addr = (uintptr_t)mr->buf;
112 mkey_attr.size = length;
113 mkey_attr.umem_id = mlx5_os_get_umem_id(mr->umem);
115 mkey_attr.pg_access = 1;
116 mkey_attr.klm_array = NULL;
117 mkey_attr.klm_num = 0;
118 mkey_attr.relaxed_ordering_read = 0;
119 mkey_attr.relaxed_ordering_write = 0;
120 mr->mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr);
122 DRV_LOG(ERR, "Failed to create direct Mkey.");
126 mr->is_indirect = false;
130 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
136 * Destroy Send Queue used for ASO access.
142 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
144 mlx5_devx_sq_destroy(&sq->sq_obj);
145 mlx5_aso_cq_destroy(&sq->cq);
146 memset(sq, 0, sizeof(*sq));
150 * Initialize Send Queue used for ASO access.
153 * ASO SQ to initialize.
156 mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
158 volatile struct mlx5_aso_wqe *restrict wqe;
160 int size = 1 << sq->log_desc_n;
163 /* All the next fields state should stay constant. */
164 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
165 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
166 (sizeof(*wqe) >> 4));
167 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);
168 addr = (uint64_t)((uint64_t *)sq->mr.buf + i *
169 MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
170 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
171 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
172 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
174 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
175 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
176 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
177 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
178 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
183 * Initialize Send Queue used for ASO flow meter access.
186 * ASO SQ to initialize.
189 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
191 volatile struct mlx5_aso_wqe *restrict wqe;
193 int size = 1 << sq->log_desc_n;
196 /* All the next fields state should stay constant. */
197 for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
198 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
199 (sizeof(*wqe) >> 4));
200 wqe->aso_cseg.operand_masks = RTE_BE32(0u |
201 (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
202 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
203 (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
204 (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
205 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
206 MLX5_COMP_MODE_OFFSET);
207 for (idx = 0; idx < MLX5_ASO_METERS_PER_WQE;
209 wqe->aso_dseg.mtrs[idx].v_bo_sc_bbog_mm =
210 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
211 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
216 * Create Send Queue used for ASO access.
219 * Context returned from mlx5 open_device() glue function.
221 * Pointer to SQ to create.
223 * Socket to use for allocation.
225 * User Access Region object.
227 * Protection Domain number to use.
228 * @param[in] log_desc_n
229 * Log of number of descriptors in queue.
232 * 0 on success, a negative errno value otherwise and rte_errno is set.
235 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
236 void *uar, uint32_t pdn, uint16_t log_desc_n,
239 struct mlx5_devx_create_sq_attr attr = {
240 .user_index = 0xFFFF,
241 .wq_attr = (struct mlx5_devx_wq_attr){
243 .uar_page = mlx5_os_get_devx_uar_page_id(uar),
245 .ts_format = mlx5_ts_format_conv(ts_format),
247 struct mlx5_devx_modify_sq_attr modify_attr = {
248 .state = MLX5_SQC_STATE_RDY,
253 if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
254 mlx5_os_get_devx_uar_page_id(uar)))
256 sq->log_desc_n = log_desc_n;
257 attr.cqn = sq->cq.cq_obj.cq->id;
258 /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
259 log_wqbb_n = log_desc_n + 1;
260 ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
262 DRV_LOG(ERR, "Can't create SQ object.");
266 ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
268 DRV_LOG(ERR, "Can't change SQ state to ready.");
275 sq->sqn = sq->sq_obj.sq->id;
276 sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
277 rte_spinlock_init(&sq->sqsl);
280 mlx5_aso_destroy_sq(sq);
285 * API to create and initialize Send Queue used for ASO access.
288 * Pointer to shared device context.
291 * 0 on success, a negative errno value otherwise and rte_errno is set.
294 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
295 enum mlx5_access_aso_opc_mod aso_opc_mod)
297 uint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;
299 switch (aso_opc_mod) {
300 case ASO_OPC_MOD_FLOW_HIT:
301 if (mlx5_aso_devx_reg_mr(sh->ctx,
302 (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
303 sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0, sh->pdn))
305 if (mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
306 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
308 mlx5_aso_devx_dereg_mr(&sh->aso_age_mng->aso_sq.mr);
311 mlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);
313 case ASO_OPC_MOD_POLICER:
314 if (mlx5_aso_sq_create(sh->ctx, &sh->mtrmng->sq, 0,
315 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
318 mlx5_aso_mtr_init_sq(&sh->mtrmng->sq);
321 DRV_LOG(ERR, "Unknown ASO operation mode");
328 * API to destroy Send Queue used for ASO access.
331 * Pointer to shared device context.
334 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
335 enum mlx5_access_aso_opc_mod aso_opc_mod)
337 struct mlx5_aso_sq *sq;
339 switch (aso_opc_mod) {
340 case ASO_OPC_MOD_FLOW_HIT:
341 mlx5_aso_devx_dereg_mr(&sh->aso_age_mng->aso_sq.mr);
342 sq = &sh->aso_age_mng->aso_sq;
344 case ASO_OPC_MOD_POLICER:
345 sq = &sh->mtrmng->sq;
348 DRV_LOG(ERR, "Unknown ASO operation mode");
351 mlx5_aso_destroy_sq(sq);
355 * Write a burst of WQEs to ASO SQ.
358 * ASO management data, contains the SQ.
360 * Index of the last valid pool.
363 * Number of WQEs in burst.
366 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
368 volatile struct mlx5_aso_wqe *wqe;
369 struct mlx5_aso_sq *sq = &mng->aso_sq;
370 struct mlx5_aso_age_pool *pool;
371 uint16_t size = 1 << sq->log_desc_n;
372 uint16_t mask = size - 1;
374 uint16_t start_head = sq->head;
376 max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
379 sq->elts[start_head & mask].burst_size = max;
381 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
382 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
384 rte_spinlock_lock(&mng->resize_sl);
385 pool = mng->pools[sq->next];
386 rte_spinlock_unlock(&mng->resize_sl);
387 sq->elts[sq->head & mask].pool = pool;
388 wqe->general_cseg.misc =
389 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
390 (pool->flow_hit_aso_obj))->id);
391 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
392 MLX5_COMP_MODE_OFFSET);
393 wqe->general_cseg.opcode = rte_cpu_to_be_32
394 (MLX5_OPCODE_ACCESS_ASO |
395 (ASO_OPC_MOD_FLOW_HIT <<
396 WQE_CSEG_OPC_MOD_OFFSET) |
398 WQE_CSEG_WQE_INDEX_OFFSET));
399 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
404 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
405 MLX5_COMP_MODE_OFFSET);
407 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
409 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
411 return sq->elts[start_head & mask].burst_size;
415 * Debug utility function. Dump contents of error CQE and WQE.
423 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
427 DRV_LOG(ERR, "Error cqe:");
428 for (i = 0; i < 16; i += 4)
429 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
430 cqe[i + 2], cqe[i + 3]);
431 DRV_LOG(ERR, "\nError wqe:");
432 for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
433 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
434 wqe[i + 2], wqe[i + 3]);
438 * Handle case of error CQE.
444 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
446 struct mlx5_aso_cq *cq = &sq->cq;
447 uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
448 volatile struct mlx5_err_cqe *cqe =
449 (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
452 idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
453 mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
454 (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
458 * Update ASO objects upon completion.
461 * Shared device context.
463 * Number of completed ASO objects.
466 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
468 struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
469 struct mlx5_aso_sq *sq = &mng->aso_sq;
470 struct mlx5_age_info *age_info;
471 const uint16_t size = 1 << sq->log_desc_n;
472 const uint16_t mask = size - 1;
473 const uint64_t curr = MLX5_CURR_TIME_SEC;
474 uint16_t expected = AGE_CANDIDATE;
477 for (i = 0; i < n; ++i) {
478 uint16_t idx = (sq->tail + i) & mask;
479 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
480 uint64_t diff = curr - pool->time_of_last_age_check;
481 uint64_t *addr = sq->mr.buf;
484 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
485 pool->time_of_last_age_check = curr;
486 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
487 struct mlx5_aso_age_action *act = &pool->actions[j];
488 struct mlx5_age_param *ap = &act->age_params;
494 if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
499 u8addr = (uint8_t *)addr;
500 hit = (u8addr[byte] >> offset) & 0x1;
502 __atomic_store_n(&ap->sec_since_last_hit, 0,
505 struct mlx5_priv *priv;
507 __atomic_fetch_add(&ap->sec_since_last_hit,
508 diff, __ATOMIC_RELAXED);
509 /* If timeout passed add to aged-out list. */
510 if (ap->sec_since_last_hit <= ap->timeout)
513 rte_eth_devices[ap->port_id].data->dev_private;
514 age_info = GET_PORT_AGE_INFO(priv);
515 rte_spinlock_lock(&age_info->aged_sl);
516 if (__atomic_compare_exchange_n(&ap->state,
522 LIST_INSERT_HEAD(&age_info->aged_aso,
524 MLX5_AGE_SET(age_info,
527 rte_spinlock_unlock(&age_info->aged_sl);
531 mlx5_age_event_prepare(sh);
535 * Handle completions from WQEs sent to ASO SQ.
538 * Shared device context.
541 * Number of CQEs handled.
544 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
546 struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
547 struct mlx5_aso_sq *sq = &mng->aso_sq;
548 struct mlx5_aso_cq *cq = &sq->cq;
549 volatile struct mlx5_cqe *restrict cqe;
550 const unsigned int cq_size = 1 << cq->log_desc_n;
551 const unsigned int mask = cq_size - 1;
553 uint32_t next_idx = cq->cq_ci & mask;
554 const uint16_t max = (uint16_t)(sq->head - sq->tail);
561 next_idx = (cq->cq_ci + 1) & mask;
562 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
563 cqe = &cq->cq_obj.cqes[idx];
564 ret = check_cqe(cqe, cq_size, cq->cq_ci);
566 * Be sure owner read is done before any other cookie field or
570 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
571 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
573 mlx5_aso_cqe_err_handle(sq);
575 i += sq->elts[(sq->tail + i) & mask].burst_size;
580 mlx5_aso_age_action_update(sh, i);
583 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
589 * Periodically read CQEs and send WQEs to ASO SQ.
592 * Shared device context containing the ASO SQ.
595 mlx5_flow_aso_alarm(void *arg)
597 struct mlx5_dev_ctx_shared *sh = arg;
598 struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
602 rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
603 n = sh->aso_age_mng->next;
604 rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
605 mlx5_aso_completion_handle(sh);
607 /* End of loop: wait 1 second. */
611 mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
612 if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
613 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
617 * API to start ASO access using ASO SQ.
620 * Pointer to shared device context.
623 * 0 on success, a negative errno value otherwise and rte_errno is set.
626 mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh)
628 if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
629 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
636 * API to stop ASO access using ASO SQ.
639 * Pointer to shared device context.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh)
649 if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
653 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
654 if (rte_errno != EINPROGRESS)
662 mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
663 struct mlx5_aso_mtr *aso_mtr)
665 volatile struct mlx5_aso_wqe *wqe = NULL;
666 struct mlx5_flow_meter_info *fm = NULL;
667 uint16_t size = 1 << sq->log_desc_n;
668 uint16_t mask = size - 1;
670 uint32_t dseg_idx = 0;
671 struct mlx5_aso_mtr_pool *pool = NULL;
673 rte_spinlock_lock(&sq->sqsl);
674 res = size - (uint16_t)(sq->head - sq->tail);
675 if (unlikely(!res)) {
676 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
677 rte_spinlock_unlock(&sq->sqsl);
680 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
681 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
684 sq->elts[sq->head & mask].mtr = aso_mtr;
685 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
686 mtrs[aso_mtr->offset]);
687 wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
688 (aso_mtr->offset >> 1));
689 wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
690 (ASO_OPC_MOD_POLICER <<
691 WQE_CSEG_OPC_MOD_OFFSET) |
692 sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
693 /* There are 2 meters in one ASO cache line. */
694 dseg_idx = aso_mtr->offset & 0x1;
695 wqe->aso_cseg.data_mask =
696 RTE_BE64(MLX5_IFC_FLOW_METER_PARAM_MASK << (32 * !dseg_idx));
698 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
699 fm->profile->srtcm_prm.cbs_cir;
700 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir =
701 fm->profile->srtcm_prm.ebs_eir;
703 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
704 RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL);
705 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir = 0;
708 sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
710 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
712 *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
714 rte_spinlock_unlock(&sq->sqsl);
719 mlx5_aso_mtrs_status_update(struct mlx5_aso_sq *sq, uint16_t aso_mtrs_nums)
721 uint16_t size = 1 << sq->log_desc_n;
722 uint16_t mask = size - 1;
724 struct mlx5_aso_mtr *aso_mtr = NULL;
725 uint8_t exp_state = ASO_METER_WAIT;
727 for (i = 0; i < aso_mtrs_nums; ++i) {
728 aso_mtr = sq->elts[(sq->tail + i) & mask].mtr;
729 MLX5_ASSERT(aso_mtr);
730 (void)__atomic_compare_exchange_n(&aso_mtr->state,
731 &exp_state, ASO_METER_READY,
732 false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
737 mlx5_aso_mtr_completion_handle(struct mlx5_aso_sq *sq)
739 struct mlx5_aso_cq *cq = &sq->cq;
740 volatile struct mlx5_cqe *restrict cqe;
741 const unsigned int cq_size = 1 << cq->log_desc_n;
742 const unsigned int mask = cq_size - 1;
744 uint32_t next_idx = cq->cq_ci & mask;
749 rte_spinlock_lock(&sq->sqsl);
750 max = (uint16_t)(sq->head - sq->tail);
751 if (unlikely(!max)) {
752 rte_spinlock_unlock(&sq->sqsl);
757 next_idx = (cq->cq_ci + 1) & mask;
758 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
759 cqe = &cq->cq_obj.cqes[idx];
760 ret = check_cqe(cqe, cq_size, cq->cq_ci);
762 * Be sure owner read is done before any other cookie field or
766 if (ret != MLX5_CQE_STATUS_SW_OWN) {
767 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
769 mlx5_aso_cqe_err_handle(sq);
776 mlx5_aso_mtrs_status_update(sq, n);
779 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
781 rte_spinlock_unlock(&sq->sqsl);
785 * Update meter parameter by send WQE.
788 * Pointer to Ethernet device.
790 * Pointer to mlx5 private data structure.
792 * Pointer to flow meter to be modified.
795 * 0 on success, a negative errno value otherwise and rte_errno is set.
798 mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
799 struct mlx5_aso_mtr *mtr)
801 struct mlx5_aso_sq *sq = &sh->mtrmng->sq;
802 uint32_t poll_wqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
805 mlx5_aso_mtr_completion_handle(sq);
806 if (mlx5_aso_mtr_sq_enqueue_single(sq, mtr))
808 /* Waiting for wqe resource. */
809 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
810 } while (--poll_wqe_times);
811 DRV_LOG(ERR, "Fail to send WQE for ASO meter %d",
817 * Wait for meter to be ready.
820 * Pointer to Ethernet device.
822 * Pointer to mlx5 private data structure.
824 * Pointer to flow meter to be modified.
827 * 0 on success, a negative errno value otherwise and rte_errno is set.
830 mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
831 struct mlx5_aso_mtr *mtr)
833 struct mlx5_aso_sq *sq = &sh->mtrmng->sq;
834 uint32_t poll_cqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
836 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
840 mlx5_aso_mtr_completion_handle(sq);
841 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
844 /* Waiting for CQE ready. */
845 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
846 } while (--poll_cqe_times);
847 DRV_LOG(ERR, "Fail to poll CQE ready for ASO meter %d",