drivers/net/mlx5/mlx5_flow_aso.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4 #include <mlx5_prm.h>
   5 #include <rte_malloc.h>
   6 #include <rte_cycles.h>
   7 #include <rte_eal_paging.h>
   8
   9 #include <mlx5_malloc.h>
  10 #include <mlx5_common_os.h>
  11 #include <mlx5_common_devx.h>
  12
  13 #include "mlx5.h"
  14 #include "mlx5_flow.h"
  15
  16 /**
  17  * Destroy Completion Queue used for ASO access.
  18  *
  19  * @param[in] cq
  20  *   ASO CQ to destroy.
  21  */
  22 static void
  23 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
  24 {
  25         if (cq->cq_obj.cq)
  26                 mlx5_devx_cq_destroy(&cq->cq_obj);
  27         memset(cq, 0, sizeof(*cq));
  28 }
  29
  30 /**
  31  * Create Completion Queue used for ASO access.
  32  *
  33  * @param[in] ctx
  34  *   Context returned from mlx5 open_device() glue function.
  35  * @param[in/out] cq
  36  *   Pointer to CQ to create.
  37  * @param[in] log_desc_n
  38  *   Log of number of descriptors in queue.
  39  * @param[in] socket
  40  *   Socket to use for allocation.
  41  * @param[in] uar_page_id
  42  *   UAR page ID to use.
  43  *
  44  * @return
  45  *   0 on success, a negative errno value otherwise and rte_errno is set.
  46  */
  47 static int
  48 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
  49                    int socket, int uar_page_id)
  50 {
  51         struct mlx5_devx_cq_attr attr = {
  52                 .uar_page_id = uar_page_id,
  53         };
  54
  55         cq->log_desc_n = log_desc_n;
  56         cq->cq_ci = 0;
  57         return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
  58 }
  59
  60 /**
  61  * Free MR resources.
  62  *
  63  * @param[in] sh
  64  *   Pointer to shared device context.
  65  * @param[in] mr
  66  *   MR to free.
  67  */
  68 static void
  69 mlx5_aso_dereg_mr(struct mlx5_dev_ctx_shared *sh, struct mlx5_pmd_mr *mr)
  70 {
  71         void *addr = mr->addr;
  72
  73         sh->share_cache.dereg_mr_cb(mr);
  74         mlx5_free(addr);
  75         memset(mr, 0, sizeof(*mr));
  76 }
  77
  78 /**
  79  * Register Memory Region.
  80  *
  81  * @param[in] sh
  82  *   Pointer to shared device context.
  83  * @param[in] length
  84  *   Size of MR buffer.
  85  * @param[in/out] mr
  86  *   Pointer to MR to create.
  87  * @param[in] socket
  88  *   Socket to use for allocation.
  89  *
  90  * @return
  91  *   0 on success, a negative errno value otherwise and rte_errno is set.
  92  */
  93 static int
  94 mlx5_aso_reg_mr(struct mlx5_dev_ctx_shared *sh, size_t length,
  95                 struct mlx5_pmd_mr *mr, int socket)
  96 {
  97
  98         int ret;
  99
 100         mr->addr = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
 101                                socket);
 102         if (!mr->addr) {
 103                 DRV_LOG(ERR, "Failed to create ASO bits mem for MR.");
 104                 return -1;
 105         }
 106         ret = sh->share_cache.reg_mr_cb(sh->pd, mr->addr, length, mr);
 107         if (ret) {
 108                 DRV_LOG(ERR, "Failed to create direct Mkey.");
 109                 mlx5_free(mr->addr);
 110                 return -1;
 111         }
 112         return 0;
 113 }
 114
 115 /**
 116  * Destroy Send Queue used for ASO access.
 117  *
 118  * @param[in] sq
 119  *   ASO SQ to destroy.
 120  */
 121 static void
 122 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 123 {
 124         mlx5_devx_sq_destroy(&sq->sq_obj);
 125         mlx5_aso_cq_destroy(&sq->cq);
 126         memset(sq, 0, sizeof(*sq));
 127 }
 128
 129 /**
 130  * Initialize Send Queue used for ASO access.
 131  *
 132  * @param[in] sq
 133  *   ASO SQ to initialize.
 134  */
 135 static void
 136 mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
 137 {
 138         volatile struct mlx5_aso_wqe *restrict wqe;
 139         int i;
 140         int size = 1 << sq->log_desc_n;
 141         uint64_t addr;
 142
 143         /* All the next fields state should stay constant. */
 144         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 145                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 146                                                           (sizeof(*wqe) >> 4));
 147                 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey);
 148                 addr = (uint64_t)((uint64_t *)sq->mr.addr + i *
 149                                             MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
 150                 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
 151                 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
 152                 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
 153                         (0u |
 154                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 155                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 156                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 157                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 158                 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
 159         }
 160 }
 161
 162 /**
 163  * Initialize Send Queue used for ASO flow meter access.
 164  *
 165  * @param[in] sq
 166  *   ASO SQ to initialize.
 167  */
 168 static void
 169 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
 170 {
 171         volatile struct mlx5_aso_wqe *restrict wqe;
 172         int i;
 173         int size = 1 << sq->log_desc_n;
 174
 175         /* All the next fields state should stay constant. */
 176         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 177                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 178                                                           (sizeof(*wqe) >> 4));
 179                 wqe->aso_cseg.operand_masks = RTE_BE32(0u |
 180                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 181                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 182                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 183                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 184                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 185                                                          MLX5_COMP_MODE_OFFSET);
 186         }
 187 }
 188
 189 /*
 190  * Initialize Send Queue used for ASO connection tracking.
 191  *
 192  * @param[in] sq
 193  *   ASO SQ to initialize.
 194  */
 195 static void
 196 mlx5_aso_ct_init_sq(struct mlx5_aso_sq *sq)
 197 {
 198         volatile struct mlx5_aso_wqe *restrict wqe;
 199         int i;
 200         int size = 1 << sq->log_desc_n;
 201         uint64_t addr;
 202
 203         /* All the next fields state should stay constant. */
 204         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 205                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 206                                                           (sizeof(*wqe) >> 4));
 207                 /* One unique MR for the query data. */
 208                 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.lkey);
 209                 /* Magic number 64 represents the length of a ASO CT obj. */
 210                 addr = (uint64_t)((uintptr_t)sq->mr.addr + i * 64);
 211                 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
 212                 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
 213                 /*
 214                  * The values of operand_masks are different for modify
 215                  * and query.
 216                  * And data_mask may be different for each modification. In
 217                  * query, it could be zero and ignored.
 218                  * CQE generation is always needed, in order to decide when
 219                  * it is available to create the flow or read the data.
 220                  */
 221                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 222                                                    MLX5_COMP_MODE_OFFSET);
 223         }
 224 }
 225
 226 /**
 227  * Create Send Queue used for ASO access.
 228  *
 229  * @param[in] ctx
 230  *   Context returned from mlx5 open_device() glue function.
 231  * @param[in/out] sq
 232  *   Pointer to SQ to create.
 233  * @param[in] socket
 234  *   Socket to use for allocation.
 235  * @param[in] uar
 236  *   User Access Region object.
 237  * @param[in] pdn
 238  *   Protection Domain number to use.
 239  * @param[in] log_desc_n
 240  *   Log of number of descriptors in queue.
 241  * @param[in] ts_format
 242  *   timestamp format supported by the queue.
 243  *
 244  * @return
 245  *   0 on success, a negative errno value otherwise and rte_errno is set.
 246  */
 247 static int
 248 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket, void *uar,
 249                    uint32_t pdn, uint16_t log_desc_n, uint32_t ts_format)
 250 {
 251         struct mlx5_devx_create_sq_attr attr = {
 252                 .user_index = 0xFFFF,
 253                 .wq_attr = (struct mlx5_devx_wq_attr){
 254                         .pd = pdn,
 255                         .uar_page = mlx5_os_get_devx_uar_page_id(uar),
 256                 },
 257                 .ts_format = mlx5_ts_format_conv(ts_format),
 258         };
 259         struct mlx5_devx_modify_sq_attr modify_attr = {
 260                 .state = MLX5_SQC_STATE_RDY,
 261         };
 262         uint16_t log_wqbb_n;
 263         int ret;
 264
 265         if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
 266                                mlx5_os_get_devx_uar_page_id(uar)))
 267                 goto error;
 268         sq->log_desc_n = log_desc_n;
 269         attr.cqn = sq->cq.cq_obj.cq->id;
 270         /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
 271         log_wqbb_n = log_desc_n + 1;
 272         ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
 273         if (ret) {
 274                 DRV_LOG(ERR, "Can't create SQ object.");
 275                 rte_errno = ENOMEM;
 276                 goto error;
 277         }
 278         ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
 279         if (ret) {
 280                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 281                 rte_errno = ENOMEM;
 282                 goto error;
 283         }
 284         sq->pi = 0;
 285         sq->head = 0;
 286         sq->tail = 0;
 287         sq->sqn = sq->sq_obj.sq->id;
 288         sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
 289         rte_spinlock_init(&sq->sqsl);
 290         return 0;
 291 error:
 292         mlx5_aso_destroy_sq(sq);
 293         return -1;
 294 }
 295
 296 /**
 297  * API to create and initialize Send Queue used for ASO access.
 298  *
 299  * @param[in] sh
 300  *   Pointer to shared device context.
 301  * @param[in] aso_opc_mod
 302  *   Mode of ASO feature.
 303  *
 304  * @return
 305  *   0 on success, a negative errno value otherwise and rte_errno is set.
 306  */
 307 int
 308 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
 309                     enum mlx5_access_aso_opc_mod aso_opc_mod)
 310 {
 311         uint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;
 312
 313         switch (aso_opc_mod) {
 314         case ASO_OPC_MOD_FLOW_HIT:
 315                 if (mlx5_aso_reg_mr(sh, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
 316                                     sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0))
 317                         return -1;
 318                 if (mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
 319                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 320                                   sh->sq_ts_format)) {
 321                         mlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);
 322                         return -1;
 323                 }
 324                 mlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);
 325                 break;
 326         case ASO_OPC_MOD_POLICER:
 327                 if (mlx5_aso_sq_create(sh->ctx, &sh->mtrmng->pools_mng.sq, 0,
 328                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 329                                   sh->sq_ts_format))
 330                         return -1;
 331                 mlx5_aso_mtr_init_sq(&sh->mtrmng->pools_mng.sq);
 332                 break;
 333         case ASO_OPC_MOD_CONNECTION_TRACKING:
 334                 /* 64B per object for query. */
 335                 if (mlx5_aso_reg_mr(sh, 64 * sq_desc_n,
 336                                     &sh->ct_mng->aso_sq.mr, 0))
 337                         return -1;
 338                 if (mlx5_aso_sq_create(sh->ctx, &sh->ct_mng->aso_sq, 0,
 339                                 sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 340                                 sh->sq_ts_format)) {
 341                         mlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);
 342                         return -1;
 343                 }
 344                 mlx5_aso_ct_init_sq(&sh->ct_mng->aso_sq);
 345                 break;
 346         default:
 347                 DRV_LOG(ERR, "Unknown ASO operation mode");
 348                 return -1;
 349         }
 350         return 0;
 351 }
 352
 353 /**
 354  * API to destroy Send Queue used for ASO access.
 355  *
 356  * @param[in] sh
 357  *   Pointer to shared device context.
 358  * @param[in] aso_opc_mod
 359  *   Mode of ASO feature.
 360  */
 361 void
 362 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
 363                       enum mlx5_access_aso_opc_mod aso_opc_mod)
 364 {
 365         struct mlx5_aso_sq *sq;
 366
 367         switch (aso_opc_mod) {
 368         case ASO_OPC_MOD_FLOW_HIT:
 369                 mlx5_aso_dereg_mr(sh, &sh->aso_age_mng->aso_sq.mr);
 370                 sq = &sh->aso_age_mng->aso_sq;
 371                 break;
 372         case ASO_OPC_MOD_POLICER:
 373                 sq = &sh->mtrmng->pools_mng.sq;
 374                 break;
 375         case ASO_OPC_MOD_CONNECTION_TRACKING:
 376                 mlx5_aso_dereg_mr(sh, &sh->ct_mng->aso_sq.mr);
 377                 sq = &sh->ct_mng->aso_sq;
 378                 break;
 379         default:
 380                 DRV_LOG(ERR, "Unknown ASO operation mode");
 381                 return;
 382         }
 383         mlx5_aso_destroy_sq(sq);
 384 }
 385
 386 /**
 387  * Write a burst of WQEs to ASO SQ.
 388  *
 389  * @param[in] mng
 390  *   ASO management data, contains the SQ.
 391  * @param[in] n
 392  *   Index of the last valid pool.
 393  *
 394  * @return
 395  *   Number of WQEs in burst.
 396  */
 397 static uint16_t
 398 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
 399 {
 400         volatile struct mlx5_aso_wqe *wqe;
 401         struct mlx5_aso_sq *sq = &mng->aso_sq;
 402         struct mlx5_aso_age_pool *pool;
 403         uint16_t size = 1 << sq->log_desc_n;
 404         uint16_t mask = size - 1;
 405         uint16_t max;
 406         uint16_t start_head = sq->head;
 407
 408         max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
 409         if (unlikely(!max))
 410                 return 0;
 411         sq->elts[start_head & mask].burst_size = max;
 412         do {
 413                 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 414                 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 415                 /* Fill next WQE. */
 416                 rte_spinlock_lock(&mng->resize_sl);
 417                 pool = mng->pools[sq->next];
 418                 rte_spinlock_unlock(&mng->resize_sl);
 419                 sq->elts[sq->head & mask].pool = pool;
 420                 wqe->general_cseg.misc =
 421                                 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
 422                                                  (pool->flow_hit_aso_obj))->id);
 423                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
 424                                                          MLX5_COMP_MODE_OFFSET);
 425                 wqe->general_cseg.opcode = rte_cpu_to_be_32
 426                                                 (MLX5_OPCODE_ACCESS_ASO |
 427                                                  (ASO_OPC_MOD_FLOW_HIT <<
 428                                                   WQE_CSEG_OPC_MOD_OFFSET) |
 429                                                  (sq->pi <<
 430                                                   WQE_CSEG_WQE_INDEX_OFFSET));
 431                 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
 432                 sq->head++;
 433                 sq->next++;
 434                 max--;
 435         } while (max);
 436         wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 437                                                          MLX5_COMP_MODE_OFFSET);
 438         rte_io_wmb();
 439         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 440         rte_wmb();
 441         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
 442         rte_wmb();
 443         return sq->elts[start_head & mask].burst_size;
 444 }
 445
 446 /**
 447  * Debug utility function. Dump contents of error CQE and WQE.
 448  *
 449  * @param[in] cqe
 450  *   Error CQE to dump.
 451  * @param[in] wqe
 452  *   Error WQE to dump.
 453  */
 454 static void
 455 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
 456 {
 457         int i;
 458
 459         DRV_LOG(ERR, "Error cqe:");
 460         for (i = 0; i < 16; i += 4)
 461                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 462                         cqe[i + 2], cqe[i + 3]);
 463         DRV_LOG(ERR, "\nError wqe:");
 464         for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
 465                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 466                         wqe[i + 2], wqe[i + 3]);
 467 }
 468
 469 /**
 470  * Handle case of error CQE.
 471  *
 472  * @param[in] sq
 473  *   ASO SQ to use.
 474  */
 475 static void
 476 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 477 {
 478         struct mlx5_aso_cq *cq = &sq->cq;
 479         uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
 480         volatile struct mlx5_err_cqe *cqe =
 481                         (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
 482
 483         cq->errors++;
 484         idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
 485         mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
 486                                (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
 487 }
 488
 489 /**
 490  * Update ASO objects upon completion.
 491  *
 492  * @param[in] sh
 493  *   Shared device context.
 494  * @param[in] n
 495  *   Number of completed ASO objects.
 496  */
 497 static void
 498 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
 499 {
 500         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 501         struct mlx5_aso_sq *sq = &mng->aso_sq;
 502         struct mlx5_age_info *age_info;
 503         const uint16_t size = 1 << sq->log_desc_n;
 504         const uint16_t mask = size - 1;
 505         const uint64_t curr = MLX5_CURR_TIME_SEC;
 506         uint16_t expected = AGE_CANDIDATE;
 507         uint16_t i;
 508
 509         for (i = 0; i < n; ++i) {
 510                 uint16_t idx = (sq->tail + i) & mask;
 511                 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
 512                 uint64_t diff = curr - pool->time_of_last_age_check;
 513                 uint64_t *addr = sq->mr.addr;
 514                 int j;
 515
 516                 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
 517                 pool->time_of_last_age_check = curr;
 518                 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
 519                         struct mlx5_aso_age_action *act = &pool->actions[j];
 520                         struct mlx5_age_param *ap = &act->age_params;
 521                         uint8_t byte;
 522                         uint8_t offset;
 523                         uint8_t *u8addr;
 524                         uint8_t hit;
 525
 526                         if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
 527                                             AGE_CANDIDATE)
 528                                 continue;
 529                         byte = 63 - (j / 8);
 530                         offset = j % 8;
 531                         u8addr = (uint8_t *)addr;
 532                         hit = (u8addr[byte] >> offset) & 0x1;
 533                         if (hit) {
 534                                 __atomic_store_n(&ap->sec_since_last_hit, 0,
 535                                                  __ATOMIC_RELAXED);
 536                         } else {
 537                                 struct mlx5_priv *priv;
 538
 539                                 __atomic_fetch_add(&ap->sec_since_last_hit,
 540                                                    diff, __ATOMIC_RELAXED);
 541                                 /* If timeout passed add to aged-out list. */
 542                                 if (ap->sec_since_last_hit <= ap->timeout)
 543                                         continue;
 544                                 priv =
 545                                 rte_eth_devices[ap->port_id].data->dev_private;
 546                                 age_info = GET_PORT_AGE_INFO(priv);
 547                                 rte_spinlock_lock(&age_info->aged_sl);
 548                                 if (__atomic_compare_exchange_n(&ap->state,
 549                                                                 &expected,
 550                                                                 AGE_TMOUT,
 551                                                                 false,
 552                                                                __ATOMIC_RELAXED,
 553                                                             __ATOMIC_RELAXED)) {
 554                                         LIST_INSERT_HEAD(&age_info->aged_aso,
 555                                                          act, next);
 556                                         MLX5_AGE_SET(age_info,
 557                                                      MLX5_AGE_EVENT_NEW);
 558                                 }
 559                                 rte_spinlock_unlock(&age_info->aged_sl);
 560                         }
 561                 }
 562         }
 563         mlx5_age_event_prepare(sh);
 564 }
 565
 566 /**
 567  * Handle completions from WQEs sent to ASO SQ.
 568  *
 569  * @param[in] sh
 570  *   Shared device context.
 571  *
 572  * @return
 573  *   Number of CQEs handled.
 574  */
 575 static uint16_t
 576 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
 577 {
 578         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 579         struct mlx5_aso_sq *sq = &mng->aso_sq;
 580         struct mlx5_aso_cq *cq = &sq->cq;
 581         volatile struct mlx5_cqe *restrict cqe;
 582         const unsigned int cq_size = 1 << cq->log_desc_n;
 583         const unsigned int mask = cq_size - 1;
 584         uint32_t idx;
 585         uint32_t next_idx = cq->cq_ci & mask;
 586         const uint16_t max = (uint16_t)(sq->head - sq->tail);
 587         uint16_t i = 0;
 588         int ret;
 589         if (unlikely(!max))
 590                 return 0;
 591         do {
 592                 idx = next_idx;
 593                 next_idx = (cq->cq_ci + 1) & mask;
 594                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 595                 cqe = &cq->cq_obj.cqes[idx];
 596                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 597                 /*
 598                  * Be sure owner read is done before any other cookie field or
 599                  * opaque field.
 600                  */
 601                 rte_io_rmb();
 602                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 603                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 604                                 break;
 605                         mlx5_aso_cqe_err_handle(sq);
 606                 } else {
 607                         i += sq->elts[(sq->tail + i) & mask].burst_size;
 608                 }
 609                 cq->cq_ci++;
 610         } while (1);
 611         if (likely(i)) {
 612                 mlx5_aso_age_action_update(sh, i);
 613                 sq->tail += i;
 614                 rte_io_wmb();
 615                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 616         }
 617         return i;
 618 }
 619
 620 /**
 621  * Periodically read CQEs and send WQEs to ASO SQ.
 622  *
 623  * @param[in] arg
 624  *   Shared device context containing the ASO SQ.
 625  */
 626 static void
 627 mlx5_flow_aso_alarm(void *arg)
 628 {
 629         struct mlx5_dev_ctx_shared *sh = arg;
 630         struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
 631         uint32_t us = 100u;
 632         uint16_t n;
 633
 634         rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
 635         n = sh->aso_age_mng->next;
 636         rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
 637         mlx5_aso_completion_handle(sh);
 638         if (sq->next == n) {
 639                 /* End of loop: wait 1 second. */
 640                 us = US_PER_S;
 641                 sq->next = 0;
 642         }
 643         mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
 644         if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
 645                 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
 646 }
 647
 648 /**
 649  * API to start ASO access using ASO SQ.
 650  *
 651  * @param[in] sh
 652  *   Pointer to shared device context.
 653  *
 654  * @return
 655  *   0 on success, a negative errno value otherwise and rte_errno is set.
 656  */
 657 int
 658 mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh)
 659 {
 660         if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
 661                 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
 662                 return -rte_errno;
 663         }
 664         return 0;
 665 }
 666
 667 /**
 668  * API to stop ASO access using ASO SQ.
 669  *
 670  * @param[in] sh
 671  *   Pointer to shared device context.
 672  *
 673  * @return
 674  *   0 on success, a negative errno value otherwise and rte_errno is set.
 675  */
 676 int
 677 mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh)
 678 {
 679         int retries = 1024;
 680
 681         if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
 682                 return -EINVAL;
 683         rte_errno = 0;
 684         while (--retries) {
 685                 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
 686                 if (rte_errno != EINPROGRESS)
 687                         break;
 688                 rte_pause();
 689         }
 690         return -rte_errno;
 691 }
 692
 693 static uint16_t
 694 mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
 695                 struct mlx5_aso_mtr *aso_mtr)
 696 {
 697         volatile struct mlx5_aso_wqe *wqe = NULL;
 698         struct mlx5_flow_meter_info *fm = NULL;
 699         struct mlx5_flow_meter_profile *fmp;
 700         uint16_t size = 1 << sq->log_desc_n;
 701         uint16_t mask = size - 1;
 702         uint16_t res;
 703         uint32_t dseg_idx = 0;
 704         struct mlx5_aso_mtr_pool *pool = NULL;
 705
 706         rte_spinlock_lock(&sq->sqsl);
 707         res = size - (uint16_t)(sq->head - sq->tail);
 708         if (unlikely(!res)) {
 709                 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
 710                 rte_spinlock_unlock(&sq->sqsl);
 711                 return 0;
 712         }
 713         wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 714         rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 715         /* Fill next WQE. */
 716         fm = &aso_mtr->fm;
 717         sq->elts[sq->head & mask].mtr = aso_mtr;
 718         pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
 719                         mtrs[aso_mtr->offset]);
 720         wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
 721                         (aso_mtr->offset >> 1));
 722         wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
 723                         (ASO_OPC_MOD_POLICER <<
 724                         WQE_CSEG_OPC_MOD_OFFSET) |
 725                         sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
 726         /* There are 2 meters in one ASO cache line. */
 727         dseg_idx = aso_mtr->offset & 0x1;
 728         wqe->aso_cseg.data_mask =
 729                 RTE_BE64(MLX5_IFC_FLOW_METER_PARAM_MASK << (32 * !dseg_idx));
 730         if (fm->is_enable) {
 731                 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
 732                         fm->profile->srtcm_prm.cbs_cir;
 733                 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir =
 734                         fm->profile->srtcm_prm.ebs_eir;
 735         } else {
 736                 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
 737                         RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL);
 738                 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir = 0;
 739         }
 740         fmp = fm->profile;
 741         if (fmp->profile.packet_mode)
 742                 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
 743                                 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
 744                                 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET) |
 745                                 (MLX5_METER_MODE_PKT << ASO_DSEG_MTR_MODE));
 746         else
 747                 wqe->aso_dseg.mtrs[dseg_idx].v_bo_sc_bbog_mm =
 748                                 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
 749                                 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
 750         sq->head++;
 751         sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
 752         rte_io_wmb();
 753         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 754         rte_wmb();
 755         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
 756         rte_wmb();
 757         rte_spinlock_unlock(&sq->sqsl);
 758         return 1;
 759 }
 760
 761 static void
 762 mlx5_aso_mtrs_status_update(struct mlx5_aso_sq *sq, uint16_t aso_mtrs_nums)
 763 {
 764         uint16_t size = 1 << sq->log_desc_n;
 765         uint16_t mask = size - 1;
 766         uint16_t i;
 767         struct mlx5_aso_mtr *aso_mtr = NULL;
 768         uint8_t exp_state = ASO_METER_WAIT;
 769
 770         for (i = 0; i < aso_mtrs_nums; ++i) {
 771                 aso_mtr = sq->elts[(sq->tail + i) & mask].mtr;
 772                 MLX5_ASSERT(aso_mtr);
 773                 (void)__atomic_compare_exchange_n(&aso_mtr->state,
 774                                 &exp_state, ASO_METER_READY,
 775                                 false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
 776         }
 777 }
 778
 779 static void
 780 mlx5_aso_mtr_completion_handle(struct mlx5_aso_sq *sq)
 781 {
 782         struct mlx5_aso_cq *cq = &sq->cq;
 783         volatile struct mlx5_cqe *restrict cqe;
 784         const unsigned int cq_size = 1 << cq->log_desc_n;
 785         const unsigned int mask = cq_size - 1;
 786         uint32_t idx;
 787         uint32_t next_idx = cq->cq_ci & mask;
 788         uint16_t max;
 789         uint16_t n = 0;
 790         int ret;
 791
 792         rte_spinlock_lock(&sq->sqsl);
 793         max = (uint16_t)(sq->head - sq->tail);
 794         if (unlikely(!max)) {
 795                 rte_spinlock_unlock(&sq->sqsl);
 796                 return;
 797         }
 798         do {
 799                 idx = next_idx;
 800                 next_idx = (cq->cq_ci + 1) & mask;
 801                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 802                 cqe = &cq->cq_obj.cqes[idx];
 803                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 804                 /*
 805                  * Be sure owner read is done before any other cookie field or
 806                  * opaque field.
 807                  */
 808                 rte_io_rmb();
 809                 if (ret != MLX5_CQE_STATUS_SW_OWN) {
 810                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 811                                 break;
 812                         mlx5_aso_cqe_err_handle(sq);
 813                 } else {
 814                         n++;
 815                 }
 816                 cq->cq_ci++;
 817         } while (1);
 818         if (likely(n)) {
 819                 mlx5_aso_mtrs_status_update(sq, n);
 820                 sq->tail += n;
 821                 rte_io_wmb();
 822                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 823         }
 824         rte_spinlock_unlock(&sq->sqsl);
 825 }
 826
 827 /**
 828  * Update meter parameter by send WQE.
 829  *
 830  * @param[in] dev
 831  *   Pointer to Ethernet device.
 832  * @param[in] priv
 833  *   Pointer to mlx5 private data structure.
 834  * @param[in] fm
 835  *   Pointer to flow meter to be modified.
 836  *
 837  * @return
 838  *   0 on success, a negative errno value otherwise and rte_errno is set.
 839  */
 840 int
 841 mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
 842                         struct mlx5_aso_mtr *mtr)
 843 {
 844         struct mlx5_aso_sq *sq = &sh->mtrmng->pools_mng.sq;
 845         uint32_t poll_wqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
 846
 847         do {
 848                 mlx5_aso_mtr_completion_handle(sq);
 849                 if (mlx5_aso_mtr_sq_enqueue_single(sq, mtr))
 850                         return 0;
 851                 /* Waiting for wqe resource. */
 852                 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
 853         } while (--poll_wqe_times);
 854         DRV_LOG(ERR, "Fail to send WQE for ASO meter offset %d",
 855                         mtr->offset);
 856         return -1;
 857 }
 858
 859 /**
 860  * Wait for meter to be ready.
 861  *
 862  * @param[in] dev
 863  *   Pointer to Ethernet device.
 864  * @param[in] priv
 865  *   Pointer to mlx5 private data structure.
 866  * @param[in] fm
 867  *   Pointer to flow meter to be modified.
 868  *
 869  * @return
 870  *   0 on success, a negative errno value otherwise and rte_errno is set.
 871  */
 872 int
 873 mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
 874                         struct mlx5_aso_mtr *mtr)
 875 {
 876         struct mlx5_aso_sq *sq = &sh->mtrmng->pools_mng.sq;
 877         uint32_t poll_cqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
 878
 879         if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
 880                                             ASO_METER_READY)
 881                 return 0;
 882         do {
 883                 mlx5_aso_mtr_completion_handle(sq);
 884                 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
 885                                             ASO_METER_READY)
 886                         return 0;
 887                 /* Waiting for CQE ready. */
 888                 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
 889         } while (--poll_cqe_times);
 890         DRV_LOG(ERR, "Fail to poll CQE ready for ASO meter offset %d",
 891                         mtr->offset);
 892         return -1;
 893 }
 894
 895 /*
 896  * Post a WQE to the ASO CT SQ to modify the context.
 897  *
 898  * @param[in] mng
 899  *   Pointer to the CT pools management structure.
 900  * @param[in] ct
 901  *   Pointer to the generic CT structure related to the context.
 902  * @param[in] profile
 903  *   Pointer to configuration profile.
 904  *
 905  * @return
 906  *   1 on success (WQE number), 0 on failure.
 907  */
 908 static uint16_t
 909 mlx5_aso_ct_sq_enqueue_single(struct mlx5_aso_ct_pools_mng *mng,
 910                               struct mlx5_aso_ct_action *ct,
 911                               const struct rte_flow_action_conntrack *profile)
 912 {
 913         volatile struct mlx5_aso_wqe *wqe = NULL;
 914         struct mlx5_aso_sq *sq = &mng->aso_sq;
 915         uint16_t size = 1 << sq->log_desc_n;
 916         uint16_t mask = size - 1;
 917         uint16_t res;
 918         struct mlx5_aso_ct_pool *pool;
 919         void *desg;
 920         void *orig_dir;
 921         void *reply_dir;
 922
 923         rte_spinlock_lock(&sq->sqsl);
 924         /* Prevent other threads to update the index. */
 925         res = size - (uint16_t)(sq->head - sq->tail);
 926         if (unlikely(!res)) {
 927                 rte_spinlock_unlock(&sq->sqsl);
 928                 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
 929                 return 0;
 930         }
 931         wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 932         rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 933         /* Fill next WQE. */
 934         MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_WAIT);
 935         sq->elts[sq->head & mask].ct = ct;
 936         pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
 937         /* Each WQE will have a single CT object. */
 938         wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
 939                                                   ct->offset);
 940         wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
 941                         (ASO_OPC_MOD_CONNECTION_TRACKING <<
 942                          WQE_CSEG_OPC_MOD_OFFSET) |
 943                         sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
 944         wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
 945                         (0u |
 946                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 947                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 948                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 949                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 950         wqe->aso_cseg.data_mask = UINT64_MAX;
 951         /* To make compiler happy. */
 952         desg = (void *)(uintptr_t)wqe->aso_dseg.data;
 953         MLX5_SET(conn_track_aso, desg, valid, 1);
 954         MLX5_SET(conn_track_aso, desg, state, profile->state);
 955         MLX5_SET(conn_track_aso, desg, freeze_track, !profile->enable);
 956         MLX5_SET(conn_track_aso, desg, connection_assured,
 957                  profile->live_connection);
 958         MLX5_SET(conn_track_aso, desg, sack_permitted, profile->selective_ack);
 959         MLX5_SET(conn_track_aso, desg, challenged_acked,
 960                  profile->challenge_ack_passed);
 961         /* Heartbeat, retransmission_counter, retranmission_limit_exceeded: 0 */
 962         MLX5_SET(conn_track_aso, desg, heartbeat, 0);
 963         MLX5_SET(conn_track_aso, desg, max_ack_window,
 964                  profile->max_ack_window);
 965         MLX5_SET(conn_track_aso, desg, retransmission_counter, 0);
 966         MLX5_SET(conn_track_aso, desg, retranmission_limit_exceeded, 0);
 967         MLX5_SET(conn_track_aso, desg, retranmission_limit,
 968                  profile->retransmission_limit);
 969         MLX5_SET(conn_track_aso, desg, reply_direction_tcp_scale,
 970                  profile->reply_dir.scale);
 971         MLX5_SET(conn_track_aso, desg, reply_direction_tcp_close_initiated,
 972                  profile->reply_dir.close_initiated);
 973         /* Both directions will use the same liberal mode. */
 974         MLX5_SET(conn_track_aso, desg, reply_direction_tcp_liberal_enabled,
 975                  profile->liberal_mode);
 976         MLX5_SET(conn_track_aso, desg, reply_direction_tcp_data_unacked,
 977                  profile->reply_dir.data_unacked);
 978         MLX5_SET(conn_track_aso, desg, reply_direction_tcp_max_ack,
 979                  profile->reply_dir.last_ack_seen);
 980         MLX5_SET(conn_track_aso, desg, original_direction_tcp_scale,
 981                  profile->original_dir.scale);
 982         MLX5_SET(conn_track_aso, desg, original_direction_tcp_close_initiated,
 983                  profile->original_dir.close_initiated);
 984         MLX5_SET(conn_track_aso, desg, original_direction_tcp_liberal_enabled,
 985                  profile->liberal_mode);
 986         MLX5_SET(conn_track_aso, desg, original_direction_tcp_data_unacked,
 987                  profile->original_dir.data_unacked);
 988         MLX5_SET(conn_track_aso, desg, original_direction_tcp_max_ack,
 989                  profile->original_dir.last_ack_seen);
 990         MLX5_SET(conn_track_aso, desg, last_win, profile->last_window);
 991         MLX5_SET(conn_track_aso, desg, last_dir, profile->last_direction);
 992         MLX5_SET(conn_track_aso, desg, last_index, profile->last_index);
 993         MLX5_SET(conn_track_aso, desg, last_seq, profile->last_seq);
 994         MLX5_SET(conn_track_aso, desg, last_ack, profile->last_ack);
 995         MLX5_SET(conn_track_aso, desg, last_end, profile->last_end);
 996         orig_dir = MLX5_ADDR_OF(conn_track_aso, desg, original_dir);
 997         MLX5_SET(tcp_window_params, orig_dir, sent_end,
 998                  profile->original_dir.sent_end);
 999         MLX5_SET(tcp_window_params, orig_dir, reply_end,
1000                  profile->original_dir.reply_end);
1001         MLX5_SET(tcp_window_params, orig_dir, max_win,
1002                  profile->original_dir.max_win);
1003         MLX5_SET(tcp_window_params, orig_dir, max_ack,
1004                  profile->original_dir.max_ack);
1005         reply_dir = MLX5_ADDR_OF(conn_track_aso, desg, reply_dir);
1006         MLX5_SET(tcp_window_params, reply_dir, sent_end,
1007                  profile->reply_dir.sent_end);
1008         MLX5_SET(tcp_window_params, reply_dir, reply_end,
1009                  profile->reply_dir.reply_end);
1010         MLX5_SET(tcp_window_params, reply_dir, max_win,
1011                  profile->reply_dir.max_win);
1012         MLX5_SET(tcp_window_params, reply_dir, max_ack,
1013                  profile->reply_dir.max_ack);
1014         sq->head++;
1015         sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
1016         rte_io_wmb();
1017         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
1018         rte_wmb();
1019         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
1020         rte_wmb();
1021         rte_spinlock_unlock(&sq->sqsl);
1022         return 1;
1023 }
1024
1025 /*
1026  * Update the status field of CTs to indicate ready to be used by flows.
1027  * A continuous number of CTs since last update.
1028  *
1029  * @param[in] sq
1030  *   Pointer to ASO CT SQ.
1031  * @param[in] num
1032  *   Number of CT structures to be updated.
1033  *
1034  * @return
1035  *   0 on success, a negative value.
1036  */
1037 static void
1038 mlx5_aso_ct_status_update(struct mlx5_aso_sq *sq, uint16_t num)
1039 {
1040         uint16_t size = 1 << sq->log_desc_n;
1041         uint16_t mask = size - 1;
1042         uint16_t i;
1043         struct mlx5_aso_ct_action *ct = NULL;
1044         uint16_t idx;
1045
1046         for (i = 0; i < num; i++) {
1047                 idx = (uint16_t)((sq->tail + i) & mask);
1048                 ct = sq->elts[idx].ct;
1049                 MLX5_ASSERT(ct);
1050                 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_READY);
1051         }
1052 }
1053
1054 /*
1055  * Handle completions from WQEs sent to ASO CT.
1056  *
1057  * @param[in] mng
1058  *   Pointer to the CT pools management structure.
1059  */
1060 static void
1061 mlx5_aso_ct_completion_handle(struct mlx5_aso_ct_pools_mng *mng)
1062 {
1063         struct mlx5_aso_sq *sq = &mng->aso_sq;
1064         struct mlx5_aso_cq *cq = &sq->cq;
1065         volatile struct mlx5_cqe *restrict cqe;
1066         const uint32_t cq_size = 1 << cq->log_desc_n;
1067         const uint32_t mask = cq_size - 1;
1068         uint32_t idx;
1069         uint32_t next_idx;
1070         uint16_t max;
1071         uint16_t n = 0;
1072         int ret;
1073
1074         rte_spinlock_lock(&sq->sqsl);
1075         max = (uint16_t)(sq->head - sq->tail);
1076         if (unlikely(!max)) {
1077                 rte_spinlock_unlock(&sq->sqsl);
1078                 return;
1079         }
1080         next_idx = cq->cq_ci & mask;
1081         do {
1082                 idx = next_idx;
1083                 next_idx = (cq->cq_ci + 1) & mask;
1084                 /* Need to confirm the position of the prefetch. */
1085                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
1086                 cqe = &cq->cq_obj.cqes[idx];
1087                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
1088                 /*
1089                  * Be sure owner read is done before any other cookie field or
1090                  * opaque field.
1091                  */
1092                 rte_io_rmb();
1093                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1094                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
1095                                 break;
1096                         mlx5_aso_cqe_err_handle(sq);
1097                 } else {
1098                         n++;
1099                 }
1100                 cq->cq_ci++;
1101         } while (1);
1102         if (likely(n)) {
1103                 mlx5_aso_ct_status_update(sq, n);
1104                 sq->tail += n;
1105                 rte_io_wmb();
1106                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
1107         }
1108         rte_spinlock_unlock(&sq->sqsl);
1109 }
1110
1111 /*
1112  * Update connection tracking ASO context by sending WQE.
1113  *
1114  * @param[in] sh
1115  *   Pointer to mlx5_dev_ctx_shared object.
1116  * @param[in] ct
1117  *   Pointer to connection tracking offload object.
1118  * @param[in] profile
1119  *   Pointer to connection tracking TCP parameter.
1120  *
1121  * @return
1122  *   0 on success, -1 on failure.
1123  */
1124 int
1125 mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
1126                           struct mlx5_aso_ct_action *ct,
1127                           const struct rte_flow_action_conntrack *profile)
1128 {
1129         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
1130         uint32_t poll_wqe_times = MLX5_CT_POLL_WQE_CQE_TIMES;
1131         struct mlx5_aso_ct_pool *pool;
1132
1133         MLX5_ASSERT(ct);
1134         do {
1135                 mlx5_aso_ct_completion_handle(mng);
1136                 if (mlx5_aso_ct_sq_enqueue_single(mng, ct, profile))
1137                         return 0;
1138                 /* Waiting for wqe resource. */
1139                 rte_delay_us_sleep(10u);
1140         } while (--poll_wqe_times);
1141         pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
1142         DRV_LOG(ERR, "Fail to send WQE for ASO CT %d in pool %d",
1143                 ct->offset, pool->index);
1144         return -1;
1145 }