1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
101 if (priv->pci_dev == NULL)
103 switch (priv->pci_dev->id.device_id) {
104 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
105 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
106 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
107 return (int16_t)0xfffe;
114 * Initialize flow attributes structure according to flow items' types.
116 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
117 * mode. For tunnel mode, the items to be modified are the outermost ones.
120 * Pointer to item specification.
122 * Pointer to flow attributes structure.
123 * @param[in] dev_flow
124 * Pointer to the sub flow.
125 * @param[in] tunnel_decap
126 * Whether action is after tunnel decapsulation.
129 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
130 struct mlx5_flow *dev_flow, bool tunnel_decap)
132 uint64_t layers = dev_flow->handle->layers;
135 * If layers is already initialized, it means this dev_flow is the
136 * suffix flow, the layers flags is set by the prefix flow. Need to
137 * use the layer flags from prefix flow as the suffix flow may not
138 * have the user defined items as the flow is split.
141 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
143 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
145 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
152 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
153 uint8_t next_protocol = 0xff;
154 switch (item->type) {
155 case RTE_FLOW_ITEM_TYPE_GRE:
156 case RTE_FLOW_ITEM_TYPE_NVGRE:
157 case RTE_FLOW_ITEM_TYPE_VXLAN:
158 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
159 case RTE_FLOW_ITEM_TYPE_GENEVE:
160 case RTE_FLOW_ITEM_TYPE_MPLS:
164 case RTE_FLOW_ITEM_TYPE_IPV4:
167 if (item->mask != NULL &&
168 ((const struct rte_flow_item_ipv4 *)
169 item->mask)->hdr.next_proto_id)
171 ((const struct rte_flow_item_ipv4 *)
172 (item->spec))->hdr.next_proto_id &
173 ((const struct rte_flow_item_ipv4 *)
174 (item->mask))->hdr.next_proto_id;
175 if ((next_protocol == IPPROTO_IPIP ||
176 next_protocol == IPPROTO_IPV6) && tunnel_decap)
179 case RTE_FLOW_ITEM_TYPE_IPV6:
182 if (item->mask != NULL &&
183 ((const struct rte_flow_item_ipv6 *)
184 item->mask)->hdr.proto)
186 ((const struct rte_flow_item_ipv6 *)
187 (item->spec))->hdr.proto &
188 ((const struct rte_flow_item_ipv6 *)
189 (item->mask))->hdr.proto;
190 if ((next_protocol == IPPROTO_IPIP ||
191 next_protocol == IPPROTO_IPV6) && tunnel_decap)
194 case RTE_FLOW_ITEM_TYPE_UDP:
198 case RTE_FLOW_ITEM_TYPE_TCP:
210 * Convert rte_mtr_color to mlx5 color.
219 rte_col_2_mlx5_col(enum rte_color rcol)
222 case RTE_COLOR_GREEN:
223 return MLX5_FLOW_COLOR_GREEN;
224 case RTE_COLOR_YELLOW:
225 return MLX5_FLOW_COLOR_YELLOW;
227 return MLX5_FLOW_COLOR_RED;
231 return MLX5_FLOW_COLOR_UNDEFINED;
234 struct field_modify_info {
235 uint32_t size; /* Size of field in protocol header, in bytes. */
236 uint32_t offset; /* Offset of field in protocol header, in bytes. */
237 enum mlx5_modification_field id;
240 struct field_modify_info modify_eth[] = {
241 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
242 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
243 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
244 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
248 struct field_modify_info modify_vlan_out_first_vid[] = {
249 /* Size in bits !!! */
250 {12, 0, MLX5_MODI_OUT_FIRST_VID},
254 struct field_modify_info modify_ipv4[] = {
255 {1, 1, MLX5_MODI_OUT_IP_DSCP},
256 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
257 {4, 12, MLX5_MODI_OUT_SIPV4},
258 {4, 16, MLX5_MODI_OUT_DIPV4},
262 struct field_modify_info modify_ipv6[] = {
263 {1, 0, MLX5_MODI_OUT_IP_DSCP},
264 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
265 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
266 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
267 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
268 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
269 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
270 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
271 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
272 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
276 struct field_modify_info modify_udp[] = {
277 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
278 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
282 struct field_modify_info modify_tcp[] = {
283 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
284 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
285 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
286 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
291 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
292 uint8_t next_protocol, uint64_t *item_flags,
295 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
296 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
297 if (next_protocol == IPPROTO_IPIP) {
298 *item_flags |= MLX5_FLOW_LAYER_IPIP;
301 if (next_protocol == IPPROTO_IPV6) {
302 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
307 static inline struct mlx5_hlist *
308 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
309 const char *name, uint32_t size, bool direct_key,
310 bool lcores_share, void *ctx,
311 mlx5_list_create_cb cb_create,
312 mlx5_list_match_cb cb_match,
313 mlx5_list_remove_cb cb_remove,
314 mlx5_list_clone_cb cb_clone,
315 mlx5_list_clone_free_cb cb_clone_free)
317 struct mlx5_hlist *hl;
318 struct mlx5_hlist *expected = NULL;
319 char s[MLX5_NAME_SIZE];
321 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
324 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
325 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
326 ctx, cb_create, cb_match, cb_remove, cb_clone,
329 DRV_LOG(ERR, "%s hash creation failed", name);
333 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
336 mlx5_hlist_destroy(hl);
337 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
342 /* Update VLAN's VID/PCP based on input rte_flow_action.
345 * Pointer to struct rte_flow_action.
347 * Pointer to struct rte_vlan_hdr.
350 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
351 struct rte_vlan_hdr *vlan)
354 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
356 ((const struct rte_flow_action_of_set_vlan_pcp *)
357 action->conf)->vlan_pcp;
358 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
359 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
360 vlan->vlan_tci |= vlan_tci;
361 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
362 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
363 vlan->vlan_tci |= rte_be_to_cpu_16
364 (((const struct rte_flow_action_of_set_vlan_vid *)
365 action->conf)->vlan_vid);
370 * Fetch 1, 2, 3 or 4 byte field from the byte array
371 * and return as unsigned integer in host-endian format.
374 * Pointer to data array.
376 * Size of field to extract.
379 * converted field in host endian format.
381 static inline uint32_t
382 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
391 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
394 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
395 ret = (ret << 8) | *(data + sizeof(uint16_t));
398 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
409 * Convert modify-header action to DV specification.
411 * Data length of each action is determined by provided field description
412 * and the item mask. Data bit offset and width of each action is determined
413 * by provided item mask.
416 * Pointer to item specification.
418 * Pointer to field modification information.
419 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
420 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
421 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
423 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
424 * Negative offset value sets the same offset as source offset.
425 * size field is ignored, value is taken from source field.
426 * @param[in,out] resource
427 * Pointer to the modify-header resource.
429 * Type of modification.
431 * Pointer to the error structure.
434 * 0 on success, a negative errno value otherwise and rte_errno is set.
437 flow_dv_convert_modify_action(struct rte_flow_item *item,
438 struct field_modify_info *field,
439 struct field_modify_info *dcopy,
440 struct mlx5_flow_dv_modify_hdr_resource *resource,
441 uint32_t type, struct rte_flow_error *error)
443 uint32_t i = resource->actions_num;
444 struct mlx5_modification_cmd *actions = resource->actions;
445 uint32_t carry_b = 0;
448 * The item and mask are provided in big-endian format.
449 * The fields should be presented as in big-endian format either.
450 * Mask must be always present, it defines the actual field width.
452 MLX5_ASSERT(item->mask);
453 MLX5_ASSERT(field->size);
459 bool next_field = true;
460 bool next_dcopy = true;
462 if (i >= MLX5_MAX_MODIFY_NUM)
463 return rte_flow_error_set(error, EINVAL,
464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
465 "too many items to modify");
466 /* Fetch variable byte size mask from the array. */
467 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
468 field->offset, field->size);
473 /* Deduce actual data width in bits from mask value. */
474 off_b = rte_bsf32(mask) + carry_b;
475 size_b = sizeof(uint32_t) * CHAR_BIT -
476 off_b - __builtin_clz(mask);
478 actions[i] = (struct mlx5_modification_cmd) {
482 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
485 if (type == MLX5_MODIFICATION_TYPE_COPY) {
487 actions[i].dst_field = dcopy->id;
488 actions[i].dst_offset =
489 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
490 /* Convert entire record to big-endian format. */
491 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
493 * Destination field overflow. Copy leftovers of
494 * a source field to the next destination field.
497 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
500 dcopy->size * CHAR_BIT - dcopy->offset;
501 carry_b = actions[i].length;
505 * Not enough bits in a source filed to fill a
506 * destination field. Switch to the next source.
508 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
509 (size_b == field->size * CHAR_BIT - off_b)) {
511 field->size * CHAR_BIT - off_b;
512 dcopy->offset += actions[i].length;
518 MLX5_ASSERT(item->spec);
519 data = flow_dv_fetch_field((const uint8_t *)item->spec +
520 field->offset, field->size);
521 /* Shift out the trailing masked bits from data. */
522 data = (data & mask) >> off_b;
523 actions[i].data1 = rte_cpu_to_be_32(data);
525 /* Convert entire record to expected big-endian format. */
526 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
530 } while (field->size);
531 if (resource->actions_num == i)
532 return rte_flow_error_set(error, EINVAL,
533 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
534 "invalid modification flow item");
535 resource->actions_num = i;
540 * Convert modify-header set IPv4 address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_ipv4
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_ipv4 *conf =
559 (const struct rte_flow_action_set_ipv4 *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
561 struct rte_flow_item_ipv4 ipv4;
562 struct rte_flow_item_ipv4 ipv4_mask;
564 memset(&ipv4, 0, sizeof(ipv4));
565 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
567 ipv4.hdr.src_addr = conf->ipv4_addr;
568 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
570 ipv4.hdr.dst_addr = conf->ipv4_addr;
571 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
574 item.mask = &ipv4_mask;
575 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
576 MLX5_MODIFICATION_TYPE_SET, error);
580 * Convert modify-header set IPv6 address action to DV specification.
582 * @param[in,out] resource
583 * Pointer to the modify-header resource.
585 * Pointer to action specification.
587 * Pointer to the error structure.
590 * 0 on success, a negative errno value otherwise and rte_errno is set.
593 flow_dv_convert_action_modify_ipv6
594 (struct mlx5_flow_dv_modify_hdr_resource *resource,
595 const struct rte_flow_action *action,
596 struct rte_flow_error *error)
598 const struct rte_flow_action_set_ipv6 *conf =
599 (const struct rte_flow_action_set_ipv6 *)(action->conf);
600 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
601 struct rte_flow_item_ipv6 ipv6;
602 struct rte_flow_item_ipv6 ipv6_mask;
604 memset(&ipv6, 0, sizeof(ipv6));
605 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
606 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
607 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
608 sizeof(ipv6.hdr.src_addr));
609 memcpy(&ipv6_mask.hdr.src_addr,
610 &rte_flow_item_ipv6_mask.hdr.src_addr,
611 sizeof(ipv6.hdr.src_addr));
613 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
614 sizeof(ipv6.hdr.dst_addr));
615 memcpy(&ipv6_mask.hdr.dst_addr,
616 &rte_flow_item_ipv6_mask.hdr.dst_addr,
617 sizeof(ipv6.hdr.dst_addr));
620 item.mask = &ipv6_mask;
621 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
622 MLX5_MODIFICATION_TYPE_SET, error);
626 * Convert modify-header set MAC address action to DV specification.
628 * @param[in,out] resource
629 * Pointer to the modify-header resource.
631 * Pointer to action specification.
633 * Pointer to the error structure.
636 * 0 on success, a negative errno value otherwise and rte_errno is set.
639 flow_dv_convert_action_modify_mac
640 (struct mlx5_flow_dv_modify_hdr_resource *resource,
641 const struct rte_flow_action *action,
642 struct rte_flow_error *error)
644 const struct rte_flow_action_set_mac *conf =
645 (const struct rte_flow_action_set_mac *)(action->conf);
646 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
647 struct rte_flow_item_eth eth;
648 struct rte_flow_item_eth eth_mask;
650 memset(ð, 0, sizeof(eth));
651 memset(ð_mask, 0, sizeof(eth_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
653 memcpy(ð.src.addr_bytes, &conf->mac_addr,
654 sizeof(eth.src.addr_bytes));
655 memcpy(ð_mask.src.addr_bytes,
656 &rte_flow_item_eth_mask.src.addr_bytes,
657 sizeof(eth_mask.src.addr_bytes));
659 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
660 sizeof(eth.dst.addr_bytes));
661 memcpy(ð_mask.dst.addr_bytes,
662 &rte_flow_item_eth_mask.dst.addr_bytes,
663 sizeof(eth_mask.dst.addr_bytes));
666 item.mask = ð_mask;
667 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
668 MLX5_MODIFICATION_TYPE_SET, error);
672 * Convert modify-header set VLAN VID action to DV specification.
674 * @param[in,out] resource
675 * Pointer to the modify-header resource.
677 * Pointer to action specification.
679 * Pointer to the error structure.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 flow_dv_convert_action_modify_vlan_vid
686 (struct mlx5_flow_dv_modify_hdr_resource *resource,
687 const struct rte_flow_action *action,
688 struct rte_flow_error *error)
690 const struct rte_flow_action_of_set_vlan_vid *conf =
691 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
692 int i = resource->actions_num;
693 struct mlx5_modification_cmd *actions = resource->actions;
694 struct field_modify_info *field = modify_vlan_out_first_vid;
696 if (i >= MLX5_MAX_MODIFY_NUM)
697 return rte_flow_error_set(error, EINVAL,
698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
699 "too many items to modify");
700 actions[i] = (struct mlx5_modification_cmd) {
701 .action_type = MLX5_MODIFICATION_TYPE_SET,
703 .length = field->size,
704 .offset = field->offset,
706 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
707 actions[i].data1 = conf->vlan_vid;
708 actions[i].data1 = actions[i].data1 << 16;
709 resource->actions_num = ++i;
714 * Convert modify-header set TP action to DV specification.
716 * @param[in,out] resource
717 * Pointer to the modify-header resource.
719 * Pointer to action specification.
721 * Pointer to rte_flow_item objects list.
723 * Pointer to flow attributes structure.
724 * @param[in] dev_flow
725 * Pointer to the sub flow.
726 * @param[in] tunnel_decap
727 * Whether action is after tunnel decapsulation.
729 * Pointer to the error structure.
732 * 0 on success, a negative errno value otherwise and rte_errno is set.
735 flow_dv_convert_action_modify_tp
736 (struct mlx5_flow_dv_modify_hdr_resource *resource,
737 const struct rte_flow_action *action,
738 const struct rte_flow_item *items,
739 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
740 bool tunnel_decap, struct rte_flow_error *error)
742 const struct rte_flow_action_set_tp *conf =
743 (const struct rte_flow_action_set_tp *)(action->conf);
744 struct rte_flow_item item;
745 struct rte_flow_item_udp udp;
746 struct rte_flow_item_udp udp_mask;
747 struct rte_flow_item_tcp tcp;
748 struct rte_flow_item_tcp tcp_mask;
749 struct field_modify_info *field;
752 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
754 memset(&udp, 0, sizeof(udp));
755 memset(&udp_mask, 0, sizeof(udp_mask));
756 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
757 udp.hdr.src_port = conf->port;
758 udp_mask.hdr.src_port =
759 rte_flow_item_udp_mask.hdr.src_port;
761 udp.hdr.dst_port = conf->port;
762 udp_mask.hdr.dst_port =
763 rte_flow_item_udp_mask.hdr.dst_port;
765 item.type = RTE_FLOW_ITEM_TYPE_UDP;
767 item.mask = &udp_mask;
770 MLX5_ASSERT(attr->tcp);
771 memset(&tcp, 0, sizeof(tcp));
772 memset(&tcp_mask, 0, sizeof(tcp_mask));
773 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
774 tcp.hdr.src_port = conf->port;
775 tcp_mask.hdr.src_port =
776 rte_flow_item_tcp_mask.hdr.src_port;
778 tcp.hdr.dst_port = conf->port;
779 tcp_mask.hdr.dst_port =
780 rte_flow_item_tcp_mask.hdr.dst_port;
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header set TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_action *action,
816 const struct rte_flow_item *items,
817 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
818 bool tunnel_decap, struct rte_flow_error *error)
820 const struct rte_flow_action_set_ttl *conf =
821 (const struct rte_flow_action_set_ttl *)(action->conf);
822 struct rte_flow_item item;
823 struct rte_flow_item_ipv4 ipv4;
824 struct rte_flow_item_ipv4 ipv4_mask;
825 struct rte_flow_item_ipv6 ipv6;
826 struct rte_flow_item_ipv6 ipv6_mask;
827 struct field_modify_info *field;
830 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
832 memset(&ipv4, 0, sizeof(ipv4));
833 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
834 ipv4.hdr.time_to_live = conf->ttl_value;
835 ipv4_mask.hdr.time_to_live = 0xFF;
836 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
838 item.mask = &ipv4_mask;
841 MLX5_ASSERT(attr->ipv6);
842 memset(&ipv6, 0, sizeof(ipv6));
843 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
844 ipv6.hdr.hop_limits = conf->ttl_value;
845 ipv6_mask.hdr.hop_limits = 0xFF;
846 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
848 item.mask = &ipv6_mask;
851 return flow_dv_convert_modify_action(&item, field, NULL, resource,
852 MLX5_MODIFICATION_TYPE_SET, error);
856 * Convert modify-header decrement TTL action to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to rte_flow_item objects list.
865 * Pointer to flow attributes structure.
866 * @param[in] dev_flow
867 * Pointer to the sub flow.
868 * @param[in] tunnel_decap
869 * Whether action is after tunnel decapsulation.
871 * Pointer to the error structure.
874 * 0 on success, a negative errno value otherwise and rte_errno is set.
877 flow_dv_convert_action_modify_dec_ttl
878 (struct mlx5_flow_dv_modify_hdr_resource *resource,
879 const struct rte_flow_item *items,
880 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
881 bool tunnel_decap, struct rte_flow_error *error)
883 struct rte_flow_item item;
884 struct rte_flow_item_ipv4 ipv4;
885 struct rte_flow_item_ipv4 ipv4_mask;
886 struct rte_flow_item_ipv6 ipv6;
887 struct rte_flow_item_ipv6 ipv6_mask;
888 struct field_modify_info *field;
891 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
893 memset(&ipv4, 0, sizeof(ipv4));
894 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
895 ipv4.hdr.time_to_live = 0xFF;
896 ipv4_mask.hdr.time_to_live = 0xFF;
897 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
899 item.mask = &ipv4_mask;
902 MLX5_ASSERT(attr->ipv6);
903 memset(&ipv6, 0, sizeof(ipv6));
904 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
905 ipv6.hdr.hop_limits = 0xFF;
906 ipv6_mask.hdr.hop_limits = 0xFF;
907 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
909 item.mask = &ipv6_mask;
912 return flow_dv_convert_modify_action(&item, field, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
917 * Convert modify-header increment/decrement TCP Sequence number
918 * to DV specification.
920 * @param[in,out] resource
921 * Pointer to the modify-header resource.
923 * Pointer to action specification.
925 * Pointer to the error structure.
928 * 0 on success, a negative errno value otherwise and rte_errno is set.
931 flow_dv_convert_action_modify_tcp_seq
932 (struct mlx5_flow_dv_modify_hdr_resource *resource,
933 const struct rte_flow_action *action,
934 struct rte_flow_error *error)
936 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
937 uint64_t value = rte_be_to_cpu_32(*conf);
938 struct rte_flow_item item;
939 struct rte_flow_item_tcp tcp;
940 struct rte_flow_item_tcp tcp_mask;
942 memset(&tcp, 0, sizeof(tcp));
943 memset(&tcp_mask, 0, sizeof(tcp_mask));
944 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
946 * The HW has no decrement operation, only increment operation.
947 * To simulate decrement X from Y using increment operation
948 * we need to add UINT32_MAX X times to Y.
949 * Each adding of UINT32_MAX decrements Y by 1.
952 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
953 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
954 item.type = RTE_FLOW_ITEM_TYPE_TCP;
956 item.mask = &tcp_mask;
957 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
958 MLX5_MODIFICATION_TYPE_ADD, error);
962 * Convert modify-header increment/decrement TCP Acknowledgment number
963 * to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_modify_tcp_ack
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
982 uint64_t value = rte_be_to_cpu_32(*conf);
983 struct rte_flow_item item;
984 struct rte_flow_item_tcp tcp;
985 struct rte_flow_item_tcp tcp_mask;
987 memset(&tcp, 0, sizeof(tcp));
988 memset(&tcp_mask, 0, sizeof(tcp_mask));
989 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
991 * The HW has no decrement operation, only increment operation.
992 * To simulate decrement X from Y using increment operation
993 * we need to add UINT32_MAX X times to Y.
994 * Each adding of UINT32_MAX decrements Y by 1.
997 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
998 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
999 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1001 item.mask = &tcp_mask;
1002 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1003 MLX5_MODIFICATION_TYPE_ADD, error);
1006 static enum mlx5_modification_field reg_to_field[] = {
1007 [REG_NON] = MLX5_MODI_OUT_NONE,
1008 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1009 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1010 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1011 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1012 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1013 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1014 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1015 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1016 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1017 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1021 * Convert register set to DV specification.
1023 * @param[in,out] resource
1024 * Pointer to the modify-header resource.
1026 * Pointer to action specification.
1028 * Pointer to the error structure.
1031 * 0 on success, a negative errno value otherwise and rte_errno is set.
1034 flow_dv_convert_action_set_reg
1035 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1036 const struct rte_flow_action *action,
1037 struct rte_flow_error *error)
1039 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1040 struct mlx5_modification_cmd *actions = resource->actions;
1041 uint32_t i = resource->actions_num;
1043 if (i >= MLX5_MAX_MODIFY_NUM)
1044 return rte_flow_error_set(error, EINVAL,
1045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1046 "too many items to modify");
1047 MLX5_ASSERT(conf->id != REG_NON);
1048 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1049 actions[i] = (struct mlx5_modification_cmd) {
1050 .action_type = MLX5_MODIFICATION_TYPE_SET,
1051 .field = reg_to_field[conf->id],
1052 .offset = conf->offset,
1053 .length = conf->length,
1055 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1056 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1058 resource->actions_num = i;
1063 * Convert SET_TAG action to DV specification.
1066 * Pointer to the rte_eth_dev structure.
1067 * @param[in,out] resource
1068 * Pointer to the modify-header resource.
1070 * Pointer to action specification.
1072 * Pointer to the error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_convert_action_set_tag
1079 (struct rte_eth_dev *dev,
1080 struct mlx5_flow_dv_modify_hdr_resource *resource,
1081 const struct rte_flow_action_set_tag *conf,
1082 struct rte_flow_error *error)
1084 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1085 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1086 struct rte_flow_item item = {
1090 struct field_modify_info reg_c_x[] = {
1093 enum mlx5_modification_field reg_type;
1096 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1099 MLX5_ASSERT(ret != REG_NON);
1100 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1101 reg_type = reg_to_field[ret];
1102 MLX5_ASSERT(reg_type > 0);
1103 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1104 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1105 MLX5_MODIFICATION_TYPE_SET, error);
1109 * Convert internal COPY_REG action to DV specification.
1112 * Pointer to the rte_eth_dev structure.
1113 * @param[in,out] res
1114 * Pointer to the modify-header resource.
1116 * Pointer to action specification.
1118 * Pointer to the error structure.
1121 * 0 on success, a negative errno value otherwise and rte_errno is set.
1124 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1125 struct mlx5_flow_dv_modify_hdr_resource *res,
1126 const struct rte_flow_action *action,
1127 struct rte_flow_error *error)
1129 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1130 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1131 struct rte_flow_item item = {
1135 struct field_modify_info reg_src[] = {
1136 {4, 0, reg_to_field[conf->src]},
1139 struct field_modify_info reg_dst = {
1141 .id = reg_to_field[conf->dst],
1143 /* Adjust reg_c[0] usage according to reported mask. */
1144 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1145 struct mlx5_priv *priv = dev->data->dev_private;
1146 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1148 MLX5_ASSERT(reg_c0);
1149 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1150 if (conf->dst == REG_C_0) {
1151 /* Copy to reg_c[0], within mask only. */
1152 reg_dst.offset = rte_bsf32(reg_c0);
1153 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1156 mask = rte_cpu_to_be_32(reg_c0);
1159 return flow_dv_convert_modify_action(&item,
1160 reg_src, ®_dst, res,
1161 MLX5_MODIFICATION_TYPE_COPY,
1166 * Convert MARK action to DV specification. This routine is used
1167 * in extensive metadata only and requires metadata register to be
1168 * handled. In legacy mode hardware tag resource is engaged.
1171 * Pointer to the rte_eth_dev structure.
1173 * Pointer to MARK action specification.
1174 * @param[in,out] resource
1175 * Pointer to the modify-header resource.
1177 * Pointer to the error structure.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1184 const struct rte_flow_action_mark *conf,
1185 struct mlx5_flow_dv_modify_hdr_resource *resource,
1186 struct rte_flow_error *error)
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1190 priv->sh->dv_mark_mask);
1191 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1192 struct rte_flow_item item = {
1196 struct field_modify_info reg_c_x[] = {
1202 return rte_flow_error_set(error, EINVAL,
1203 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1204 NULL, "zero mark action mask");
1205 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1208 MLX5_ASSERT(reg > 0);
1209 if (reg == REG_C_0) {
1210 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1211 uint32_t shl_c0 = rte_bsf32(msk_c0);
1213 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1214 mask = rte_cpu_to_be_32(mask) & msk_c0;
1215 mask = rte_cpu_to_be_32(mask << shl_c0);
1217 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1218 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1219 MLX5_MODIFICATION_TYPE_SET, error);
1223 * Get metadata register index for specified steering domain.
1226 * Pointer to the rte_eth_dev structure.
1228 * Attributes of flow to determine steering domain.
1230 * Pointer to the error structure.
1233 * positive index on success, a negative errno value otherwise
1234 * and rte_errno is set.
1236 static enum modify_reg
1237 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1238 const struct rte_flow_attr *attr,
1239 struct rte_flow_error *error)
1242 mlx5_flow_get_reg_id(dev, attr->transfer ?
1246 MLX5_METADATA_RX, 0, error);
1248 return rte_flow_error_set(error,
1249 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1250 NULL, "unavailable "
1251 "metadata register");
1256 * Convert SET_META action to DV specification.
1259 * Pointer to the rte_eth_dev structure.
1260 * @param[in,out] resource
1261 * Pointer to the modify-header resource.
1263 * Attributes of flow that includes this item.
1265 * Pointer to action specification.
1267 * Pointer to the error structure.
1270 * 0 on success, a negative errno value otherwise and rte_errno is set.
1273 flow_dv_convert_action_set_meta
1274 (struct rte_eth_dev *dev,
1275 struct mlx5_flow_dv_modify_hdr_resource *resource,
1276 const struct rte_flow_attr *attr,
1277 const struct rte_flow_action_set_meta *conf,
1278 struct rte_flow_error *error)
1280 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1281 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1282 struct rte_flow_item item = {
1286 struct field_modify_info reg_c_x[] = {
1289 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1293 MLX5_ASSERT(reg != REG_NON);
1294 if (reg == REG_C_0) {
1295 struct mlx5_priv *priv = dev->data->dev_private;
1296 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1297 uint32_t shl_c0 = rte_bsf32(msk_c0);
1299 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1300 mask = rte_cpu_to_be_32(mask) & msk_c0;
1301 mask = rte_cpu_to_be_32(mask << shl_c0);
1303 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1304 /* The routine expects parameters in memory as big-endian ones. */
1305 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1306 MLX5_MODIFICATION_TYPE_SET, error);
1310 * Convert modify-header set IPv4 DSCP action to DV specification.
1312 * @param[in,out] resource
1313 * Pointer to the modify-header resource.
1315 * Pointer to action specification.
1317 * Pointer to the error structure.
1320 * 0 on success, a negative errno value otherwise and rte_errno is set.
1323 flow_dv_convert_action_modify_ipv4_dscp
1324 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1325 const struct rte_flow_action *action,
1326 struct rte_flow_error *error)
1328 const struct rte_flow_action_set_dscp *conf =
1329 (const struct rte_flow_action_set_dscp *)(action->conf);
1330 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1331 struct rte_flow_item_ipv4 ipv4;
1332 struct rte_flow_item_ipv4 ipv4_mask;
1334 memset(&ipv4, 0, sizeof(ipv4));
1335 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1336 ipv4.hdr.type_of_service = conf->dscp;
1337 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1339 item.mask = &ipv4_mask;
1340 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1341 MLX5_MODIFICATION_TYPE_SET, error);
1345 * Convert modify-header set IPv6 DSCP action to DV specification.
1347 * @param[in,out] resource
1348 * Pointer to the modify-header resource.
1350 * Pointer to action specification.
1352 * Pointer to the error structure.
1355 * 0 on success, a negative errno value otherwise and rte_errno is set.
1358 flow_dv_convert_action_modify_ipv6_dscp
1359 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1360 const struct rte_flow_action *action,
1361 struct rte_flow_error *error)
1363 const struct rte_flow_action_set_dscp *conf =
1364 (const struct rte_flow_action_set_dscp *)(action->conf);
1365 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1366 struct rte_flow_item_ipv6 ipv6;
1367 struct rte_flow_item_ipv6 ipv6_mask;
1369 memset(&ipv6, 0, sizeof(ipv6));
1370 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1372 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1373 * rdma-core only accept the DSCP bits byte aligned start from
1374 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1375 * bits in IPv6 case as rdma-core requires byte aligned value.
1377 ipv6.hdr.vtc_flow = conf->dscp;
1378 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1380 item.mask = &ipv6_mask;
1381 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1382 MLX5_MODIFICATION_TYPE_SET, error);
1386 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1387 enum rte_flow_field_id field, int inherit,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error)
1391 struct mlx5_priv *priv = dev->data->dev_private;
1394 case RTE_FLOW_FIELD_START:
1396 case RTE_FLOW_FIELD_MAC_DST:
1397 case RTE_FLOW_FIELD_MAC_SRC:
1399 case RTE_FLOW_FIELD_VLAN_TYPE:
1401 case RTE_FLOW_FIELD_VLAN_ID:
1403 case RTE_FLOW_FIELD_MAC_TYPE:
1405 case RTE_FLOW_FIELD_IPV4_DSCP:
1407 case RTE_FLOW_FIELD_IPV4_TTL:
1409 case RTE_FLOW_FIELD_IPV4_SRC:
1410 case RTE_FLOW_FIELD_IPV4_DST:
1412 case RTE_FLOW_FIELD_IPV6_DSCP:
1414 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1416 case RTE_FLOW_FIELD_IPV6_SRC:
1417 case RTE_FLOW_FIELD_IPV6_DST:
1419 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1420 case RTE_FLOW_FIELD_TCP_PORT_DST:
1422 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1423 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1425 case RTE_FLOW_FIELD_TCP_FLAGS:
1427 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1428 case RTE_FLOW_FIELD_UDP_PORT_DST:
1430 case RTE_FLOW_FIELD_VXLAN_VNI:
1431 case RTE_FLOW_FIELD_GENEVE_VNI:
1433 case RTE_FLOW_FIELD_GTP_TEID:
1434 case RTE_FLOW_FIELD_TAG:
1436 case RTE_FLOW_FIELD_MARK:
1437 return __builtin_popcount(priv->sh->dv_mark_mask);
1438 case RTE_FLOW_FIELD_META:
1439 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1440 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1441 case RTE_FLOW_FIELD_POINTER:
1442 case RTE_FLOW_FIELD_VALUE:
1443 return inherit < 0 ? 0 : inherit;
1451 mlx5_flow_field_id_to_modify_info
1452 (const struct rte_flow_action_modify_data *data,
1453 struct field_modify_info *info, uint32_t *mask,
1454 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1455 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1457 struct mlx5_priv *priv = dev->data->dev_private;
1461 switch (data->field) {
1462 case RTE_FLOW_FIELD_START:
1463 /* not supported yet */
1466 case RTE_FLOW_FIELD_MAC_DST:
1467 off = data->offset > 16 ? data->offset - 16 : 0;
1469 if (data->offset < 16) {
1470 info[idx] = (struct field_modify_info){2, 4,
1471 MLX5_MODI_OUT_DMAC_15_0};
1473 mask[idx] = rte_cpu_to_be_16(0xffff >>
1477 mask[idx] = RTE_BE16(0xffff);
1484 info[idx] = (struct field_modify_info){4, 0,
1485 MLX5_MODI_OUT_DMAC_47_16};
1486 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1487 (32 - width)) << off);
1489 if (data->offset < 16)
1490 info[idx++] = (struct field_modify_info){2, 4,
1491 MLX5_MODI_OUT_DMAC_15_0};
1492 info[idx] = (struct field_modify_info){4, 0,
1493 MLX5_MODI_OUT_DMAC_47_16};
1496 case RTE_FLOW_FIELD_MAC_SRC:
1497 off = data->offset > 16 ? data->offset - 16 : 0;
1499 if (data->offset < 16) {
1500 info[idx] = (struct field_modify_info){2, 4,
1501 MLX5_MODI_OUT_SMAC_15_0};
1503 mask[idx] = rte_cpu_to_be_16(0xffff >>
1507 mask[idx] = RTE_BE16(0xffff);
1514 info[idx] = (struct field_modify_info){4, 0,
1515 MLX5_MODI_OUT_SMAC_47_16};
1516 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1517 (32 - width)) << off);
1519 if (data->offset < 16)
1520 info[idx++] = (struct field_modify_info){2, 4,
1521 MLX5_MODI_OUT_SMAC_15_0};
1522 info[idx] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SMAC_47_16};
1526 case RTE_FLOW_FIELD_VLAN_TYPE:
1527 /* not supported yet */
1529 case RTE_FLOW_FIELD_VLAN_ID:
1530 info[idx] = (struct field_modify_info){2, 0,
1531 MLX5_MODI_OUT_FIRST_VID};
1533 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1535 case RTE_FLOW_FIELD_MAC_TYPE:
1536 info[idx] = (struct field_modify_info){2, 0,
1537 MLX5_MODI_OUT_ETHERTYPE};
1539 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1541 case RTE_FLOW_FIELD_IPV4_DSCP:
1542 info[idx] = (struct field_modify_info){1, 0,
1543 MLX5_MODI_OUT_IP_DSCP};
1545 mask[idx] = 0x3f >> (6 - width);
1547 case RTE_FLOW_FIELD_IPV4_TTL:
1548 info[idx] = (struct field_modify_info){1, 0,
1549 MLX5_MODI_OUT_IPV4_TTL};
1551 mask[idx] = 0xff >> (8 - width);
1553 case RTE_FLOW_FIELD_IPV4_SRC:
1554 info[idx] = (struct field_modify_info){4, 0,
1555 MLX5_MODI_OUT_SIPV4};
1557 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1560 case RTE_FLOW_FIELD_IPV4_DST:
1561 info[idx] = (struct field_modify_info){4, 0,
1562 MLX5_MODI_OUT_DIPV4};
1564 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1567 case RTE_FLOW_FIELD_IPV6_DSCP:
1568 info[idx] = (struct field_modify_info){1, 0,
1569 MLX5_MODI_OUT_IP_DSCP};
1571 mask[idx] = 0x3f >> (6 - width);
1573 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1574 info[idx] = (struct field_modify_info){1, 0,
1575 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1577 mask[idx] = 0xff >> (8 - width);
1579 case RTE_FLOW_FIELD_IPV6_SRC:
1581 if (data->offset < 32) {
1582 info[idx] = (struct field_modify_info){4, 12,
1583 MLX5_MODI_OUT_SIPV6_31_0};
1586 rte_cpu_to_be_32(0xffffffff >>
1590 mask[idx] = RTE_BE32(0xffffffff);
1597 if (data->offset < 64) {
1598 info[idx] = (struct field_modify_info){4, 8,
1599 MLX5_MODI_OUT_SIPV6_63_32};
1602 rte_cpu_to_be_32(0xffffffff >>
1606 mask[idx] = RTE_BE32(0xffffffff);
1613 if (data->offset < 96) {
1614 info[idx] = (struct field_modify_info){4, 4,
1615 MLX5_MODI_OUT_SIPV6_95_64};
1618 rte_cpu_to_be_32(0xffffffff >>
1622 mask[idx] = RTE_BE32(0xffffffff);
1629 info[idx] = (struct field_modify_info){4, 0,
1630 MLX5_MODI_OUT_SIPV6_127_96};
1631 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1634 if (data->offset < 32)
1635 info[idx++] = (struct field_modify_info){4, 12,
1636 MLX5_MODI_OUT_SIPV6_31_0};
1637 if (data->offset < 64)
1638 info[idx++] = (struct field_modify_info){4, 8,
1639 MLX5_MODI_OUT_SIPV6_63_32};
1640 if (data->offset < 96)
1641 info[idx++] = (struct field_modify_info){4, 4,
1642 MLX5_MODI_OUT_SIPV6_95_64};
1643 if (data->offset < 128)
1644 info[idx++] = (struct field_modify_info){4, 0,
1645 MLX5_MODI_OUT_SIPV6_127_96};
1648 case RTE_FLOW_FIELD_IPV6_DST:
1650 if (data->offset < 32) {
1651 info[idx] = (struct field_modify_info){4, 12,
1652 MLX5_MODI_OUT_DIPV6_31_0};
1655 rte_cpu_to_be_32(0xffffffff >>
1659 mask[idx] = RTE_BE32(0xffffffff);
1666 if (data->offset < 64) {
1667 info[idx] = (struct field_modify_info){4, 8,
1668 MLX5_MODI_OUT_DIPV6_63_32};
1671 rte_cpu_to_be_32(0xffffffff >>
1675 mask[idx] = RTE_BE32(0xffffffff);
1682 if (data->offset < 96) {
1683 info[idx] = (struct field_modify_info){4, 4,
1684 MLX5_MODI_OUT_DIPV6_95_64};
1687 rte_cpu_to_be_32(0xffffffff >>
1691 mask[idx] = RTE_BE32(0xffffffff);
1698 info[idx] = (struct field_modify_info){4, 0,
1699 MLX5_MODI_OUT_DIPV6_127_96};
1700 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1703 if (data->offset < 32)
1704 info[idx++] = (struct field_modify_info){4, 12,
1705 MLX5_MODI_OUT_DIPV6_31_0};
1706 if (data->offset < 64)
1707 info[idx++] = (struct field_modify_info){4, 8,
1708 MLX5_MODI_OUT_DIPV6_63_32};
1709 if (data->offset < 96)
1710 info[idx++] = (struct field_modify_info){4, 4,
1711 MLX5_MODI_OUT_DIPV6_95_64};
1712 if (data->offset < 128)
1713 info[idx++] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_OUT_DIPV6_127_96};
1717 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1718 info[idx] = (struct field_modify_info){2, 0,
1719 MLX5_MODI_OUT_TCP_SPORT};
1721 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1723 case RTE_FLOW_FIELD_TCP_PORT_DST:
1724 info[idx] = (struct field_modify_info){2, 0,
1725 MLX5_MODI_OUT_TCP_DPORT};
1727 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1729 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1730 info[idx] = (struct field_modify_info){4, 0,
1731 MLX5_MODI_OUT_TCP_SEQ_NUM};
1733 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1736 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1737 info[idx] = (struct field_modify_info){4, 0,
1738 MLX5_MODI_OUT_TCP_ACK_NUM};
1740 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1743 case RTE_FLOW_FIELD_TCP_FLAGS:
1744 info[idx] = (struct field_modify_info){2, 0,
1745 MLX5_MODI_OUT_TCP_FLAGS};
1747 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1749 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1750 info[idx] = (struct field_modify_info){2, 0,
1751 MLX5_MODI_OUT_UDP_SPORT};
1753 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1755 case RTE_FLOW_FIELD_UDP_PORT_DST:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_UDP_DPORT};
1759 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1761 case RTE_FLOW_FIELD_VXLAN_VNI:
1762 /* not supported yet */
1764 case RTE_FLOW_FIELD_GENEVE_VNI:
1765 /* not supported yet*/
1767 case RTE_FLOW_FIELD_GTP_TEID:
1768 info[idx] = (struct field_modify_info){4, 0,
1769 MLX5_MODI_GTP_TEID};
1771 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1774 case RTE_FLOW_FIELD_TAG:
1776 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1777 data->level, error);
1780 MLX5_ASSERT(reg != REG_NON);
1781 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1782 info[idx] = (struct field_modify_info){4, 0,
1786 rte_cpu_to_be_32(0xffffffff >>
1790 case RTE_FLOW_FIELD_MARK:
1792 uint32_t mark_mask = priv->sh->dv_mark_mask;
1793 uint32_t mark_count = __builtin_popcount(mark_mask);
1794 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1798 MLX5_ASSERT(reg != REG_NON);
1799 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1800 info[idx] = (struct field_modify_info){4, 0,
1803 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1804 (mark_count - width)) & mark_mask);
1807 case RTE_FLOW_FIELD_META:
1809 uint32_t meta_mask = priv->sh->dv_meta_mask;
1810 uint32_t meta_count = __builtin_popcount(meta_mask);
1812 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1813 uint32_t shl_c0 = rte_bsf32(msk_c0);
1814 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1817 MLX5_ASSERT(reg != REG_NON);
1818 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1821 info[idx] = (struct field_modify_info){4, 0,
1824 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1825 (meta_count - width)) & meta_mask);
1828 case RTE_FLOW_FIELD_POINTER:
1829 case RTE_FLOW_FIELD_VALUE:
1837 * Convert modify_field action to DV specification.
1840 * Pointer to the rte_eth_dev structure.
1841 * @param[in,out] resource
1842 * Pointer to the modify-header resource.
1844 * Pointer to action specification.
1846 * Attributes of flow that includes this item.
1848 * Pointer to the error structure.
1851 * 0 on success, a negative errno value otherwise and rte_errno is set.
1854 flow_dv_convert_action_modify_field
1855 (struct rte_eth_dev *dev,
1856 struct mlx5_flow_dv_modify_hdr_resource *resource,
1857 const struct rte_flow_action *action,
1858 const struct rte_flow_attr *attr,
1859 struct rte_flow_error *error)
1861 const struct rte_flow_action_modify_field *conf =
1862 (const struct rte_flow_action_modify_field *)(action->conf);
1863 struct rte_flow_item item = {
1867 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1869 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1871 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1875 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1876 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1877 type = MLX5_MODIFICATION_TYPE_SET;
1878 /** For SET fill the destination field (field) first. */
1879 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1880 conf->width, &shift, dev,
1882 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1883 (void *)(uintptr_t)conf->src.pvalue :
1884 (void *)(uintptr_t)&conf->src.value;
1886 type = MLX5_MODIFICATION_TYPE_COPY;
1887 /** For COPY fill the destination field (dcopy) without mask. */
1888 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1889 conf->width, &shift, dev,
1891 /** Then construct the source field (field) with mask. */
1892 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1893 conf->width, &shift,
1897 return flow_dv_convert_modify_action(&item,
1898 field, dcopy, resource, type, error);
1902 * Validate MARK item.
1905 * Pointer to the rte_eth_dev structure.
1907 * Item specification.
1909 * Attributes of flow that includes this item.
1911 * Pointer to error structure.
1914 * 0 on success, a negative errno value otherwise and rte_errno is set.
1917 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1918 const struct rte_flow_item *item,
1919 const struct rte_flow_attr *attr __rte_unused,
1920 struct rte_flow_error *error)
1922 struct mlx5_priv *priv = dev->data->dev_private;
1923 struct mlx5_dev_config *config = &priv->config;
1924 const struct rte_flow_item_mark *spec = item->spec;
1925 const struct rte_flow_item_mark *mask = item->mask;
1926 const struct rte_flow_item_mark nic_mask = {
1927 .id = priv->sh->dv_mark_mask,
1931 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1932 return rte_flow_error_set(error, ENOTSUP,
1933 RTE_FLOW_ERROR_TYPE_ITEM, item,
1934 "extended metadata feature"
1936 if (!mlx5_flow_ext_mreg_supported(dev))
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ITEM, item,
1939 "extended metadata register"
1940 " isn't supported");
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM, item,
1944 "extended metadata register"
1945 " isn't available");
1946 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1950 return rte_flow_error_set(error, EINVAL,
1951 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1953 "data cannot be empty");
1954 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1955 return rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1958 "mark id exceeds the limit");
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1964 "mask cannot be zero");
1966 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1967 (const uint8_t *)&nic_mask,
1968 sizeof(struct rte_flow_item_mark),
1969 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1976 * Validate META item.
1979 * Pointer to the rte_eth_dev structure.
1981 * Item specification.
1983 * Attributes of flow that includes this item.
1985 * Pointer to error structure.
1988 * 0 on success, a negative errno value otherwise and rte_errno is set.
1991 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1992 const struct rte_flow_item *item,
1993 const struct rte_flow_attr *attr,
1994 struct rte_flow_error *error)
1996 struct mlx5_priv *priv = dev->data->dev_private;
1997 struct mlx5_dev_config *config = &priv->config;
1998 const struct rte_flow_item_meta *spec = item->spec;
1999 const struct rte_flow_item_meta *mask = item->mask;
2000 struct rte_flow_item_meta nic_mask = {
2007 return rte_flow_error_set(error, EINVAL,
2008 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2010 "data cannot be empty");
2011 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2012 if (!mlx5_flow_ext_mreg_supported(dev))
2013 return rte_flow_error_set(error, ENOTSUP,
2014 RTE_FLOW_ERROR_TYPE_ITEM, item,
2015 "extended metadata register"
2016 " isn't supported");
2017 reg = flow_dv_get_metadata_reg(dev, attr, error);
2021 return rte_flow_error_set(error, ENOTSUP,
2022 RTE_FLOW_ERROR_TYPE_ITEM, item,
2023 "unavalable extended metadata register");
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2030 nic_mask.data = priv->sh->dv_meta_mask;
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "extended metadata feature "
2036 "should be enabled when "
2037 "meta item is requested "
2038 "with e-switch mode ");
2040 return rte_flow_error_set(error, ENOTSUP,
2041 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 "match on metadata for ingress "
2043 "is not supported in legacy "
2047 mask = &rte_flow_item_meta_mask;
2049 return rte_flow_error_set(error, EINVAL,
2050 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2051 "mask cannot be zero");
2053 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2054 (const uint8_t *)&nic_mask,
2055 sizeof(struct rte_flow_item_meta),
2056 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2061 * Validate TAG item.
2064 * Pointer to the rte_eth_dev structure.
2066 * Item specification.
2068 * Attributes of flow that includes this item.
2070 * Pointer to error structure.
2073 * 0 on success, a negative errno value otherwise and rte_errno is set.
2076 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2077 const struct rte_flow_item *item,
2078 const struct rte_flow_attr *attr __rte_unused,
2079 struct rte_flow_error *error)
2081 const struct rte_flow_item_tag *spec = item->spec;
2082 const struct rte_flow_item_tag *mask = item->mask;
2083 const struct rte_flow_item_tag nic_mask = {
2084 .data = RTE_BE32(UINT32_MAX),
2089 if (!mlx5_flow_ext_mreg_supported(dev))
2090 return rte_flow_error_set(error, ENOTSUP,
2091 RTE_FLOW_ERROR_TYPE_ITEM, item,
2092 "extensive metadata register"
2093 " isn't supported");
2095 return rte_flow_error_set(error, EINVAL,
2096 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2098 "data cannot be empty");
2100 mask = &rte_flow_item_tag_mask;
2102 return rte_flow_error_set(error, EINVAL,
2103 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2104 "mask cannot be zero");
2106 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2107 (const uint8_t *)&nic_mask,
2108 sizeof(struct rte_flow_item_tag),
2109 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2112 if (mask->index != 0xff)
2113 return rte_flow_error_set(error, EINVAL,
2114 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2115 "partial mask for tag index"
2116 " is not supported");
2117 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2120 MLX5_ASSERT(ret != REG_NON);
2125 * Validate vport item.
2128 * Pointer to the rte_eth_dev structure.
2130 * Item specification.
2132 * Attributes of flow that includes this item.
2133 * @param[in] item_flags
2134 * Bit-fields that holds the items detected until now.
2136 * Pointer to error structure.
2139 * 0 on success, a negative errno value otherwise and rte_errno is set.
2142 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2143 const struct rte_flow_item *item,
2144 const struct rte_flow_attr *attr,
2145 uint64_t item_flags,
2146 struct rte_flow_error *error)
2148 const struct rte_flow_item_port_id *spec = item->spec;
2149 const struct rte_flow_item_port_id *mask = item->mask;
2150 const struct rte_flow_item_port_id switch_mask = {
2153 struct mlx5_priv *esw_priv;
2154 struct mlx5_priv *dev_priv;
2157 if (!attr->transfer)
2158 return rte_flow_error_set(error, EINVAL,
2159 RTE_FLOW_ERROR_TYPE_ITEM,
2161 "match on port id is valid only"
2162 " when transfer flag is enabled");
2163 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2164 return rte_flow_error_set(error, ENOTSUP,
2165 RTE_FLOW_ERROR_TYPE_ITEM, item,
2166 "multiple source ports are not"
2169 mask = &switch_mask;
2170 if (mask->id != 0xffffffff)
2171 return rte_flow_error_set(error, ENOTSUP,
2172 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2174 "no support for partial mask on"
2176 ret = mlx5_flow_item_acceptable
2177 (item, (const uint8_t *)mask,
2178 (const uint8_t *)&rte_flow_item_port_id_mask,
2179 sizeof(struct rte_flow_item_port_id),
2180 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2185 if (spec->id == MLX5_PORT_ESW_MGR)
2187 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2189 return rte_flow_error_set(error, rte_errno,
2190 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2191 "failed to obtain E-Switch info for"
2193 dev_priv = mlx5_dev_to_eswitch_info(dev);
2195 return rte_flow_error_set(error, rte_errno,
2196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2198 "failed to obtain E-Switch info");
2199 if (esw_priv->domain_id != dev_priv->domain_id)
2200 return rte_flow_error_set(error, EINVAL,
2201 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2202 "cannot match on a port from a"
2203 " different E-Switch");
2208 * Validate VLAN item.
2211 * Item specification.
2212 * @param[in] item_flags
2213 * Bit-fields that holds the items detected until now.
2215 * Ethernet device flow is being created on.
2217 * Pointer to error structure.
2220 * 0 on success, a negative errno value otherwise and rte_errno is set.
2223 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2224 uint64_t item_flags,
2225 struct rte_eth_dev *dev,
2226 struct rte_flow_error *error)
2228 const struct rte_flow_item_vlan *mask = item->mask;
2229 const struct rte_flow_item_vlan nic_mask = {
2230 .tci = RTE_BE16(UINT16_MAX),
2231 .inner_type = RTE_BE16(UINT16_MAX),
2234 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2236 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2237 MLX5_FLOW_LAYER_INNER_L4) :
2238 (MLX5_FLOW_LAYER_OUTER_L3 |
2239 MLX5_FLOW_LAYER_OUTER_L4);
2240 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2241 MLX5_FLOW_LAYER_OUTER_VLAN;
2243 if (item_flags & vlanm)
2244 return rte_flow_error_set(error, EINVAL,
2245 RTE_FLOW_ERROR_TYPE_ITEM, item,
2246 "multiple VLAN layers not supported");
2247 else if ((item_flags & l34m) != 0)
2248 return rte_flow_error_set(error, EINVAL,
2249 RTE_FLOW_ERROR_TYPE_ITEM, item,
2250 "VLAN cannot follow L3/L4 layer");
2252 mask = &rte_flow_item_vlan_mask;
2253 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2254 (const uint8_t *)&nic_mask,
2255 sizeof(struct rte_flow_item_vlan),
2256 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2259 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2260 struct mlx5_priv *priv = dev->data->dev_private;
2262 if (priv->vmwa_context) {
2264 * Non-NULL context means we have a virtual machine
2265 * and SR-IOV enabled, we have to create VLAN interface
2266 * to make hypervisor to setup E-Switch vport
2267 * context correctly. We avoid creating the multiple
2268 * VLAN interfaces, so we cannot support VLAN tag mask.
2270 return rte_flow_error_set(error, EINVAL,
2271 RTE_FLOW_ERROR_TYPE_ITEM,
2273 "VLAN tag mask is not"
2274 " supported in virtual"
2282 * GTP flags are contained in 1 byte of the format:
2283 * -------------------------------------------
2284 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2285 * |-----------------------------------------|
2286 * | value | Version | PT | Res | E | S | PN |
2287 * -------------------------------------------
2289 * Matching is supported only for GTP flags E, S, PN.
2291 #define MLX5_GTP_FLAGS_MASK 0x07
2294 * Validate GTP item.
2297 * Pointer to the rte_eth_dev structure.
2299 * Item specification.
2300 * @param[in] item_flags
2301 * Bit-fields that holds the items detected until now.
2303 * Pointer to error structure.
2306 * 0 on success, a negative errno value otherwise and rte_errno is set.
2309 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2310 const struct rte_flow_item *item,
2311 uint64_t item_flags,
2312 struct rte_flow_error *error)
2314 struct mlx5_priv *priv = dev->data->dev_private;
2315 const struct rte_flow_item_gtp *spec = item->spec;
2316 const struct rte_flow_item_gtp *mask = item->mask;
2317 const struct rte_flow_item_gtp nic_mask = {
2318 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2320 .teid = RTE_BE32(0xffffffff),
2323 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2324 return rte_flow_error_set(error, ENOTSUP,
2325 RTE_FLOW_ERROR_TYPE_ITEM, item,
2326 "GTP support is not enabled");
2327 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2328 return rte_flow_error_set(error, ENOTSUP,
2329 RTE_FLOW_ERROR_TYPE_ITEM, item,
2330 "multiple tunnel layers not"
2332 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2333 return rte_flow_error_set(error, EINVAL,
2334 RTE_FLOW_ERROR_TYPE_ITEM, item,
2335 "no outer UDP layer found");
2337 mask = &rte_flow_item_gtp_mask;
2338 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2339 return rte_flow_error_set(error, ENOTSUP,
2340 RTE_FLOW_ERROR_TYPE_ITEM, item,
2341 "Match is supported for GTP"
2343 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2344 (const uint8_t *)&nic_mask,
2345 sizeof(struct rte_flow_item_gtp),
2346 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2350 * Validate GTP PSC item.
2353 * Item specification.
2354 * @param[in] last_item
2355 * Previous validated item in the pattern items.
2356 * @param[in] gtp_item
2357 * Previous GTP item specification.
2359 * Pointer to flow attributes.
2361 * Pointer to error structure.
2364 * 0 on success, a negative errno value otherwise and rte_errno is set.
2367 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2369 const struct rte_flow_item *gtp_item,
2370 const struct rte_flow_attr *attr,
2371 struct rte_flow_error *error)
2373 const struct rte_flow_item_gtp *gtp_spec;
2374 const struct rte_flow_item_gtp *gtp_mask;
2375 const struct rte_flow_item_gtp_psc *mask;
2376 const struct rte_flow_item_gtp_psc nic_mask = {
2381 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2382 return rte_flow_error_set
2383 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2384 "GTP PSC item must be preceded with GTP item");
2385 gtp_spec = gtp_item->spec;
2386 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2387 /* GTP spec and E flag is requested to match zero. */
2389 (gtp_mask->v_pt_rsv_flags &
2390 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2391 return rte_flow_error_set
2392 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2393 "GTP E flag must be 1 to match GTP PSC");
2394 /* Check the flow is not created in group zero. */
2395 if (!attr->transfer && !attr->group)
2396 return rte_flow_error_set
2397 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2398 "GTP PSC is not supported for group 0");
2399 /* GTP spec is here and E flag is requested to match zero. */
2402 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2403 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2404 (const uint8_t *)&nic_mask,
2405 sizeof(struct rte_flow_item_gtp_psc),
2406 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2410 * Validate IPV4 item.
2411 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2412 * add specific validation of fragment_offset field,
2415 * Item specification.
2416 * @param[in] item_flags
2417 * Bit-fields that holds the items detected until now.
2419 * Pointer to error structure.
2422 * 0 on success, a negative errno value otherwise and rte_errno is set.
2425 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2426 const struct rte_flow_item *item,
2427 uint64_t item_flags, uint64_t last_item,
2428 uint16_t ether_type, struct rte_flow_error *error)
2431 struct mlx5_priv *priv = dev->data->dev_private;
2432 const struct rte_flow_item_ipv4 *spec = item->spec;
2433 const struct rte_flow_item_ipv4 *last = item->last;
2434 const struct rte_flow_item_ipv4 *mask = item->mask;
2435 rte_be16_t fragment_offset_spec = 0;
2436 rte_be16_t fragment_offset_last = 0;
2437 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2439 .src_addr = RTE_BE32(0xffffffff),
2440 .dst_addr = RTE_BE32(0xffffffff),
2441 .type_of_service = 0xff,
2442 .fragment_offset = RTE_BE16(0xffff),
2443 .next_proto_id = 0xff,
2444 .time_to_live = 0xff,
2448 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2449 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2451 priv->config.hca_attr.inner_ipv4_ihl;
2453 return rte_flow_error_set(error, ENOTSUP,
2454 RTE_FLOW_ERROR_TYPE_ITEM,
2456 "IPV4 ihl offload not supported");
2457 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2459 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2460 ether_type, &nic_ipv4_mask,
2461 MLX5_ITEM_RANGE_ACCEPTED, error);
2465 fragment_offset_spec = spec->hdr.fragment_offset &
2466 mask->hdr.fragment_offset;
2467 if (!fragment_offset_spec)
2470 * spec and mask are valid, enforce using full mask to make sure the
2471 * complete value is used correctly.
2473 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2474 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2475 return rte_flow_error_set(error, EINVAL,
2476 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2477 item, "must use full mask for"
2478 " fragment_offset");
2480 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2481 * indicating this is 1st fragment of fragmented packet.
2482 * This is not yet supported in MLX5, return appropriate error message.
2484 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2485 return rte_flow_error_set(error, ENOTSUP,
2486 RTE_FLOW_ERROR_TYPE_ITEM, item,
2487 "match on first fragment not "
2489 if (fragment_offset_spec && !last)
2490 return rte_flow_error_set(error, ENOTSUP,
2491 RTE_FLOW_ERROR_TYPE_ITEM, item,
2492 "specified value not supported");
2493 /* spec and last are valid, validate the specified range. */
2494 fragment_offset_last = last->hdr.fragment_offset &
2495 mask->hdr.fragment_offset;
2497 * Match on fragment_offset spec 0x2001 and last 0x3fff
2498 * means MF is 1 and frag-offset is > 0.
2499 * This packet is fragment 2nd and onward, excluding last.
2500 * This is not yet supported in MLX5, return appropriate
2503 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2504 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2505 return rte_flow_error_set(error, ENOTSUP,
2506 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2507 last, "match on following "
2508 "fragments not supported");
2510 * Match on fragment_offset spec 0x0001 and last 0x1fff
2511 * means MF is 0 and frag-offset is > 0.
2512 * This packet is last fragment of fragmented packet.
2513 * This is not yet supported in MLX5, return appropriate
2516 if (fragment_offset_spec == RTE_BE16(1) &&
2517 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2518 return rte_flow_error_set(error, ENOTSUP,
2519 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2520 last, "match on last "
2521 "fragment not supported");
2523 * Match on fragment_offset spec 0x0001 and last 0x3fff
2524 * means MF and/or frag-offset is not 0.
2525 * This is a fragmented packet.
2526 * Other range values are invalid and rejected.
2528 if (!(fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2532 "specified range not supported");
2537 * Validate IPV6 fragment extension item.
2540 * Item specification.
2541 * @param[in] item_flags
2542 * Bit-fields that holds the items detected until now.
2544 * Pointer to error structure.
2547 * 0 on success, a negative errno value otherwise and rte_errno is set.
2550 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2551 uint64_t item_flags,
2552 struct rte_flow_error *error)
2554 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2555 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2556 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2557 rte_be16_t frag_data_spec = 0;
2558 rte_be16_t frag_data_last = 0;
2559 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2560 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2561 MLX5_FLOW_LAYER_OUTER_L4;
2563 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2565 .next_header = 0xff,
2566 .frag_data = RTE_BE16(0xffff),
2570 if (item_flags & l4m)
2571 return rte_flow_error_set(error, EINVAL,
2572 RTE_FLOW_ERROR_TYPE_ITEM, item,
2573 "ipv6 fragment extension item cannot "
2575 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2576 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2577 return rte_flow_error_set(error, EINVAL,
2578 RTE_FLOW_ERROR_TYPE_ITEM, item,
2579 "ipv6 fragment extension item must "
2580 "follow ipv6 item");
2582 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2583 if (!frag_data_spec)
2586 * spec and mask are valid, enforce using full mask to make sure the
2587 * complete value is used correctly.
2589 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2590 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2591 return rte_flow_error_set(error, EINVAL,
2592 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2593 item, "must use full mask for"
2596 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2597 * This is 1st fragment of fragmented packet.
2599 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2600 return rte_flow_error_set(error, ENOTSUP,
2601 RTE_FLOW_ERROR_TYPE_ITEM, item,
2602 "match on first fragment not "
2604 if (frag_data_spec && !last)
2605 return rte_flow_error_set(error, EINVAL,
2606 RTE_FLOW_ERROR_TYPE_ITEM, item,
2607 "specified value not supported");
2608 ret = mlx5_flow_item_acceptable
2609 (item, (const uint8_t *)mask,
2610 (const uint8_t *)&nic_mask,
2611 sizeof(struct rte_flow_item_ipv6_frag_ext),
2612 MLX5_ITEM_RANGE_ACCEPTED, error);
2615 /* spec and last are valid, validate the specified range. */
2616 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2618 * Match on frag_data spec 0x0009 and last 0xfff9
2619 * means M is 1 and frag-offset is > 0.
2620 * This packet is fragment 2nd and onward, excluding last.
2621 * This is not yet supported in MLX5, return appropriate
2624 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2625 RTE_IPV6_EHDR_MF_MASK) &&
2626 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2627 return rte_flow_error_set(error, ENOTSUP,
2628 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2629 last, "match on following "
2630 "fragments not supported");
2632 * Match on frag_data spec 0x0008 and last 0xfff8
2633 * means M is 0 and frag-offset is > 0.
2634 * This packet is last fragment of fragmented packet.
2635 * This is not yet supported in MLX5, return appropriate
2638 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2639 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2640 return rte_flow_error_set(error, ENOTSUP,
2641 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2642 last, "match on last "
2643 "fragment not supported");
2644 /* Other range values are invalid and rejected. */
2645 return rte_flow_error_set(error, EINVAL,
2646 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2647 "specified range not supported");
2651 * Validate ASO CT item.
2654 * Pointer to the rte_eth_dev structure.
2656 * Item specification.
2657 * @param[in] item_flags
2658 * Pointer to bit-fields that holds the items detected until now.
2660 * Pointer to error structure.
2663 * 0 on success, a negative errno value otherwise and rte_errno is set.
2666 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2667 const struct rte_flow_item *item,
2668 uint64_t *item_flags,
2669 struct rte_flow_error *error)
2671 const struct rte_flow_item_conntrack *spec = item->spec;
2672 const struct rte_flow_item_conntrack *mask = item->mask;
2676 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2677 return rte_flow_error_set(error, EINVAL,
2678 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2679 "Only one CT is supported");
2681 mask = &rte_flow_item_conntrack_mask;
2682 flags = spec->flags & mask->flags;
2683 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2684 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2685 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2686 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2687 return rte_flow_error_set(error, EINVAL,
2688 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2689 "Conflict status bits");
2690 /* State change also needs to be considered. */
2691 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2696 * Validate the pop VLAN action.
2699 * Pointer to the rte_eth_dev structure.
2700 * @param[in] action_flags
2701 * Holds the actions detected until now.
2703 * Pointer to the pop vlan action.
2704 * @param[in] item_flags
2705 * The items found in this flow rule.
2707 * Pointer to flow attributes.
2709 * Pointer to error structure.
2712 * 0 on success, a negative errno value otherwise and rte_errno is set.
2715 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2716 uint64_t action_flags,
2717 const struct rte_flow_action *action,
2718 uint64_t item_flags,
2719 const struct rte_flow_attr *attr,
2720 struct rte_flow_error *error)
2722 const struct mlx5_priv *priv = dev->data->dev_private;
2723 struct mlx5_dev_ctx_shared *sh = priv->sh;
2724 bool direction_error = false;
2726 if (!priv->sh->pop_vlan_action)
2727 return rte_flow_error_set(error, ENOTSUP,
2728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2730 "pop vlan action is not supported");
2731 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2732 if (attr->transfer) {
2733 bool fdb_tx = priv->representor_id != UINT16_MAX;
2734 bool is_cx5 = sh->steering_format_version ==
2735 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2737 if (fdb_tx && is_cx5)
2738 direction_error = true;
2739 } else if (attr->egress) {
2740 direction_error = true;
2742 if (direction_error)
2743 return rte_flow_error_set(error, ENOTSUP,
2744 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2746 "pop vlan action not supported for egress");
2747 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2748 return rte_flow_error_set(error, ENOTSUP,
2749 RTE_FLOW_ERROR_TYPE_ACTION, action,
2750 "no support for multiple VLAN "
2752 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2753 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2754 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2758 "cannot pop vlan after decap without "
2759 "match on inner vlan in the flow");
2760 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2761 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2762 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2763 return rte_flow_error_set(error, ENOTSUP,
2764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2766 "cannot pop vlan without a "
2767 "match on (outer) vlan in the flow");
2768 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2769 return rte_flow_error_set(error, EINVAL,
2770 RTE_FLOW_ERROR_TYPE_ACTION, action,
2771 "wrong action order, port_id should "
2772 "be after pop VLAN action");
2773 if (!attr->transfer && priv->representor)
2774 return rte_flow_error_set(error, ENOTSUP,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776 "pop vlan action for VF representor "
2777 "not supported on NIC table");
2782 * Get VLAN default info from vlan match info.
2785 * the list of item specifications.
2787 * pointer VLAN info to fill to.
2790 * 0 on success, a negative errno value otherwise and rte_errno is set.
2793 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2794 struct rte_vlan_hdr *vlan)
2796 const struct rte_flow_item_vlan nic_mask = {
2797 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2798 MLX5DV_FLOW_VLAN_VID_MASK),
2799 .inner_type = RTE_BE16(0xffff),
2804 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2805 int type = items->type;
2807 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2808 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2811 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2812 const struct rte_flow_item_vlan *vlan_m = items->mask;
2813 const struct rte_flow_item_vlan *vlan_v = items->spec;
2815 /* If VLAN item in pattern doesn't contain data, return here. */
2820 /* Only full match values are accepted */
2821 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2822 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2823 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2825 rte_be_to_cpu_16(vlan_v->tci &
2826 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2828 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2829 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2830 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2832 rte_be_to_cpu_16(vlan_v->tci &
2833 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2835 if (vlan_m->inner_type == nic_mask.inner_type)
2836 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2837 vlan_m->inner_type);
2842 * Validate the push VLAN action.
2845 * Pointer to the rte_eth_dev structure.
2846 * @param[in] action_flags
2847 * Holds the actions detected until now.
2848 * @param[in] item_flags
2849 * The items found in this flow rule.
2851 * Pointer to the action structure.
2853 * Pointer to flow attributes
2855 * Pointer to error structure.
2858 * 0 on success, a negative errno value otherwise and rte_errno is set.
2861 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2862 uint64_t action_flags,
2863 const struct rte_flow_item_vlan *vlan_m,
2864 const struct rte_flow_action *action,
2865 const struct rte_flow_attr *attr,
2866 struct rte_flow_error *error)
2868 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2869 const struct mlx5_priv *priv = dev->data->dev_private;
2870 struct mlx5_dev_ctx_shared *sh = priv->sh;
2871 bool direction_error = false;
2873 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2874 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2875 return rte_flow_error_set(error, EINVAL,
2876 RTE_FLOW_ERROR_TYPE_ACTION, action,
2877 "invalid vlan ethertype");
2878 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2879 return rte_flow_error_set(error, EINVAL,
2880 RTE_FLOW_ERROR_TYPE_ACTION, action,
2881 "wrong action order, port_id should "
2882 "be after push VLAN");
2883 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2884 if (attr->transfer) {
2885 bool fdb_tx = priv->representor_id != UINT16_MAX;
2886 bool is_cx5 = sh->steering_format_version ==
2887 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2889 if (!fdb_tx && is_cx5)
2890 direction_error = true;
2891 } else if (attr->ingress) {
2892 direction_error = true;
2894 if (direction_error)
2895 return rte_flow_error_set(error, ENOTSUP,
2896 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2898 "push vlan action not supported for ingress");
2899 if (!attr->transfer && priv->representor)
2900 return rte_flow_error_set(error, ENOTSUP,
2901 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2902 "push vlan action for VF representor "
2903 "not supported on NIC table");
2905 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2906 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2907 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2908 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2909 !(mlx5_flow_find_action
2910 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2911 return rte_flow_error_set(error, EINVAL,
2912 RTE_FLOW_ERROR_TYPE_ACTION, action,
2913 "not full match mask on VLAN PCP and "
2914 "there is no of_set_vlan_pcp action, "
2915 "push VLAN action cannot figure out "
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2919 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2920 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2921 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2922 !(mlx5_flow_find_action
2923 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2924 return rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ACTION, action,
2926 "not full match mask on VLAN VID and "
2927 "there is no of_set_vlan_vid action, "
2928 "push VLAN action cannot figure out "
2935 * Validate the set VLAN PCP.
2937 * @param[in] action_flags
2938 * Holds the actions detected until now.
2939 * @param[in] actions
2940 * Pointer to the list of actions remaining in the flow rule.
2942 * Pointer to error structure.
2945 * 0 on success, a negative errno value otherwise and rte_errno is set.
2948 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2949 const struct rte_flow_action actions[],
2950 struct rte_flow_error *error)
2952 const struct rte_flow_action *action = actions;
2953 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2955 if (conf->vlan_pcp > 7)
2956 return rte_flow_error_set(error, EINVAL,
2957 RTE_FLOW_ERROR_TYPE_ACTION, action,
2958 "VLAN PCP value is too big");
2959 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2960 return rte_flow_error_set(error, ENOTSUP,
2961 RTE_FLOW_ERROR_TYPE_ACTION, action,
2962 "set VLAN PCP action must follow "
2963 "the push VLAN action");
2964 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2965 return rte_flow_error_set(error, ENOTSUP,
2966 RTE_FLOW_ERROR_TYPE_ACTION, action,
2967 "Multiple VLAN PCP modification are "
2969 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2970 return rte_flow_error_set(error, EINVAL,
2971 RTE_FLOW_ERROR_TYPE_ACTION, action,
2972 "wrong action order, port_id should "
2973 "be after set VLAN PCP");
2978 * Validate the set VLAN VID.
2980 * @param[in] item_flags
2981 * Holds the items detected in this rule.
2982 * @param[in] action_flags
2983 * Holds the actions detected until now.
2984 * @param[in] actions
2985 * Pointer to the list of actions remaining in the flow rule.
2987 * Pointer to error structure.
2990 * 0 on success, a negative errno value otherwise and rte_errno is set.
2993 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2994 uint64_t action_flags,
2995 const struct rte_flow_action actions[],
2996 struct rte_flow_error *error)
2998 const struct rte_flow_action *action = actions;
2999 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3001 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3002 return rte_flow_error_set(error, EINVAL,
3003 RTE_FLOW_ERROR_TYPE_ACTION, action,
3004 "VLAN VID value is too big");
3005 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3006 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3007 return rte_flow_error_set(error, ENOTSUP,
3008 RTE_FLOW_ERROR_TYPE_ACTION, action,
3009 "set VLAN VID action must follow push"
3010 " VLAN action or match on VLAN item");
3011 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3012 return rte_flow_error_set(error, ENOTSUP,
3013 RTE_FLOW_ERROR_TYPE_ACTION, action,
3014 "Multiple VLAN VID modifications are "
3016 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3017 return rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION, action,
3019 "wrong action order, port_id should "
3020 "be after set VLAN VID");
3025 * Validate the FLAG action.
3028 * Pointer to the rte_eth_dev structure.
3029 * @param[in] action_flags
3030 * Holds the actions detected until now.
3032 * Pointer to flow attributes
3034 * Pointer to error structure.
3037 * 0 on success, a negative errno value otherwise and rte_errno is set.
3040 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3041 uint64_t action_flags,
3042 const struct rte_flow_attr *attr,
3043 struct rte_flow_error *error)
3045 struct mlx5_priv *priv = dev->data->dev_private;
3046 struct mlx5_dev_config *config = &priv->config;
3049 /* Fall back if no extended metadata register support. */
3050 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3051 return mlx5_flow_validate_action_flag(action_flags, attr,
3053 /* Extensive metadata mode requires registers. */
3054 if (!mlx5_flow_ext_mreg_supported(dev))
3055 return rte_flow_error_set(error, ENOTSUP,
3056 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3057 "no metadata registers "
3058 "to support flag action");
3059 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3060 return rte_flow_error_set(error, ENOTSUP,
3061 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3062 "extended metadata register"
3063 " isn't available");
3064 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3067 MLX5_ASSERT(ret > 0);
3068 if (action_flags & MLX5_FLOW_ACTION_MARK)
3069 return rte_flow_error_set(error, EINVAL,
3070 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3071 "can't mark and flag in same flow");
3072 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3073 return rte_flow_error_set(error, EINVAL,
3074 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3076 " actions in same flow");
3081 * Validate MARK action.
3084 * Pointer to the rte_eth_dev structure.
3086 * Pointer to action.
3087 * @param[in] action_flags
3088 * Holds the actions detected until now.
3090 * Pointer to flow attributes
3092 * Pointer to error structure.
3095 * 0 on success, a negative errno value otherwise and rte_errno is set.
3098 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3099 const struct rte_flow_action *action,
3100 uint64_t action_flags,
3101 const struct rte_flow_attr *attr,
3102 struct rte_flow_error *error)
3104 struct mlx5_priv *priv = dev->data->dev_private;
3105 struct mlx5_dev_config *config = &priv->config;
3106 const struct rte_flow_action_mark *mark = action->conf;
3109 if (is_tunnel_offload_active(dev))
3110 return rte_flow_error_set(error, ENOTSUP,
3111 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3113 "if tunnel offload active");
3114 /* Fall back if no extended metadata register support. */
3115 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3116 return mlx5_flow_validate_action_mark(action, action_flags,
3118 /* Extensive metadata mode requires registers. */
3119 if (!mlx5_flow_ext_mreg_supported(dev))
3120 return rte_flow_error_set(error, ENOTSUP,
3121 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3122 "no metadata registers "
3123 "to support mark action");
3124 if (!priv->sh->dv_mark_mask)
3125 return rte_flow_error_set(error, ENOTSUP,
3126 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3127 "extended metadata register"
3128 " isn't available");
3129 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3132 MLX5_ASSERT(ret > 0);
3134 return rte_flow_error_set(error, EINVAL,
3135 RTE_FLOW_ERROR_TYPE_ACTION, action,
3136 "configuration cannot be null");
3137 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3138 return rte_flow_error_set(error, EINVAL,
3139 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3141 "mark id exceeds the limit");
3142 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3143 return rte_flow_error_set(error, EINVAL,
3144 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3145 "can't flag and mark in same flow");
3146 if (action_flags & MLX5_FLOW_ACTION_MARK)
3147 return rte_flow_error_set(error, EINVAL,
3148 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3149 "can't have 2 mark actions in same"
3155 * Validate SET_META action.
3158 * Pointer to the rte_eth_dev structure.
3160 * Pointer to the action structure.
3161 * @param[in] action_flags
3162 * Holds the actions detected until now.
3164 * Pointer to flow attributes
3166 * Pointer to error structure.
3169 * 0 on success, a negative errno value otherwise and rte_errno is set.
3172 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3173 const struct rte_flow_action *action,
3174 uint64_t action_flags __rte_unused,
3175 const struct rte_flow_attr *attr,
3176 struct rte_flow_error *error)
3178 struct mlx5_priv *priv = dev->data->dev_private;
3179 struct mlx5_dev_config *config = &priv->config;
3180 const struct rte_flow_action_set_meta *conf;
3181 uint32_t nic_mask = UINT32_MAX;
3184 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3185 !mlx5_flow_ext_mreg_supported(dev))
3186 return rte_flow_error_set(error, ENOTSUP,
3187 RTE_FLOW_ERROR_TYPE_ACTION, action,
3188 "extended metadata register"
3189 " isn't supported");
3190 reg = flow_dv_get_metadata_reg(dev, attr, error);
3194 return rte_flow_error_set(error, ENOTSUP,
3195 RTE_FLOW_ERROR_TYPE_ACTION, action,
3196 "unavalable extended metadata register");
3197 if (reg != REG_A && reg != REG_B) {
3198 struct mlx5_priv *priv = dev->data->dev_private;
3200 nic_mask = priv->sh->dv_meta_mask;
3202 if (!(action->conf))
3203 return rte_flow_error_set(error, EINVAL,
3204 RTE_FLOW_ERROR_TYPE_ACTION, action,
3205 "configuration cannot be null");
3206 conf = (const struct rte_flow_action_set_meta *)action->conf;
3208 return rte_flow_error_set(error, EINVAL,
3209 RTE_FLOW_ERROR_TYPE_ACTION, action,
3210 "zero mask doesn't have any effect");
3211 if (conf->mask & ~nic_mask)
3212 return rte_flow_error_set(error, EINVAL,
3213 RTE_FLOW_ERROR_TYPE_ACTION, action,
3214 "meta data must be within reg C0");
3219 * Validate SET_TAG action.
3222 * Pointer to the rte_eth_dev structure.
3224 * Pointer to the action structure.
3225 * @param[in] action_flags
3226 * Holds the actions detected until now.
3228 * Pointer to flow attributes
3230 * Pointer to error structure.
3233 * 0 on success, a negative errno value otherwise and rte_errno is set.
3236 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3237 const struct rte_flow_action *action,
3238 uint64_t action_flags,
3239 const struct rte_flow_attr *attr,
3240 struct rte_flow_error *error)
3242 const struct rte_flow_action_set_tag *conf;
3243 const uint64_t terminal_action_flags =
3244 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3245 MLX5_FLOW_ACTION_RSS;
3248 if (!mlx5_flow_ext_mreg_supported(dev))
3249 return rte_flow_error_set(error, ENOTSUP,
3250 RTE_FLOW_ERROR_TYPE_ACTION, action,
3251 "extensive metadata register"
3252 " isn't supported");
3253 if (!(action->conf))
3254 return rte_flow_error_set(error, EINVAL,
3255 RTE_FLOW_ERROR_TYPE_ACTION, action,
3256 "configuration cannot be null");
3257 conf = (const struct rte_flow_action_set_tag *)action->conf;
3259 return rte_flow_error_set(error, EINVAL,
3260 RTE_FLOW_ERROR_TYPE_ACTION, action,
3261 "zero mask doesn't have any effect");
3262 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3265 if (!attr->transfer && attr->ingress &&
3266 (action_flags & terminal_action_flags))
3267 return rte_flow_error_set(error, EINVAL,
3268 RTE_FLOW_ERROR_TYPE_ACTION, action,
3269 "set_tag has no effect"
3270 " with terminal actions");
3275 * Validate count action.
3278 * Pointer to rte_eth_dev structure.
3280 * Indicator if action is shared.
3281 * @param[in] action_flags
3282 * Holds the actions detected until now.
3284 * Pointer to error structure.
3287 * 0 on success, a negative errno value otherwise and rte_errno is set.
3290 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3291 uint64_t action_flags,
3292 struct rte_flow_error *error)
3294 struct mlx5_priv *priv = dev->data->dev_private;
3296 if (!priv->sh->devx)
3298 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3299 return rte_flow_error_set(error, EINVAL,
3300 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3301 "duplicate count actions set");
3302 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3303 !priv->sh->flow_hit_aso_en)
3304 return rte_flow_error_set(error, EINVAL,
3305 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3306 "old age and shared count combination is not supported");
3307 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3311 return rte_flow_error_set
3313 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3315 "count action not supported");
3319 * Validate the L2 encap action.
3322 * Pointer to the rte_eth_dev structure.
3323 * @param[in] action_flags
3324 * Holds the actions detected until now.
3326 * Pointer to the action structure.
3328 * Pointer to flow attributes.
3330 * Pointer to error structure.
3333 * 0 on success, a negative errno value otherwise and rte_errno is set.
3336 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3337 uint64_t action_flags,
3338 const struct rte_flow_action *action,
3339 const struct rte_flow_attr *attr,
3340 struct rte_flow_error *error)
3342 const struct mlx5_priv *priv = dev->data->dev_private;
3344 if (!(action->conf))
3345 return rte_flow_error_set(error, EINVAL,
3346 RTE_FLOW_ERROR_TYPE_ACTION, action,
3347 "configuration cannot be null");
3348 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3349 return rte_flow_error_set(error, EINVAL,
3350 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3351 "can only have a single encap action "
3353 if (!attr->transfer && priv->representor)
3354 return rte_flow_error_set(error, ENOTSUP,
3355 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3356 "encap action for VF representor "
3357 "not supported on NIC table");
3362 * Validate a decap action.
3365 * Pointer to the rte_eth_dev structure.
3366 * @param[in] action_flags
3367 * Holds the actions detected until now.
3369 * Pointer to the action structure.
3370 * @param[in] item_flags
3371 * Holds the items detected.
3373 * Pointer to flow attributes
3375 * Pointer to error structure.
3378 * 0 on success, a negative errno value otherwise and rte_errno is set.
3381 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3382 uint64_t action_flags,
3383 const struct rte_flow_action *action,
3384 const uint64_t item_flags,
3385 const struct rte_flow_attr *attr,
3386 struct rte_flow_error *error)
3388 const struct mlx5_priv *priv = dev->data->dev_private;
3390 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3391 !priv->config.decap_en)
3392 return rte_flow_error_set(error, ENOTSUP,
3393 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3394 "decap is not enabled");
3395 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3396 return rte_flow_error_set(error, ENOTSUP,
3397 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3399 MLX5_FLOW_ACTION_DECAP ? "can only "
3400 "have a single decap action" : "decap "
3401 "after encap is not supported");
3402 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3403 return rte_flow_error_set(error, EINVAL,
3404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3405 "can't have decap action after"
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3411 "decap action not supported for "
3413 if (!attr->transfer && priv->representor)
3414 return rte_flow_error_set(error, ENOTSUP,
3415 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3416 "decap action for VF representor "
3417 "not supported on NIC table");
3418 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3419 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3422 "VXLAN item should be present for VXLAN decap");
3426 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3429 * Validate the raw encap and decap actions.
3432 * Pointer to the rte_eth_dev structure.
3434 * Pointer to the decap action.
3436 * Pointer to the encap action.
3438 * Pointer to flow attributes
3439 * @param[in/out] action_flags
3440 * Holds the actions detected until now.
3441 * @param[out] actions_n
3442 * pointer to the number of actions counter.
3444 * Pointer to the action structure.
3445 * @param[in] item_flags
3446 * Holds the items detected.
3448 * Pointer to error structure.
3451 * 0 on success, a negative errno value otherwise and rte_errno is set.
3454 flow_dv_validate_action_raw_encap_decap
3455 (struct rte_eth_dev *dev,
3456 const struct rte_flow_action_raw_decap *decap,
3457 const struct rte_flow_action_raw_encap *encap,
3458 const struct rte_flow_attr *attr, uint64_t *action_flags,
3459 int *actions_n, const struct rte_flow_action *action,
3460 uint64_t item_flags, struct rte_flow_error *error)
3462 const struct mlx5_priv *priv = dev->data->dev_private;
3465 if (encap && (!encap->size || !encap->data))
3466 return rte_flow_error_set(error, EINVAL,
3467 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3468 "raw encap data cannot be empty");
3469 if (decap && encap) {
3470 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3471 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3474 else if (encap->size <=
3475 MLX5_ENCAPSULATION_DECISION_SIZE &&
3477 MLX5_ENCAPSULATION_DECISION_SIZE)
3480 else if (encap->size >
3481 MLX5_ENCAPSULATION_DECISION_SIZE &&
3483 MLX5_ENCAPSULATION_DECISION_SIZE)
3484 /* 2 L2 actions: encap and decap. */
3487 return rte_flow_error_set(error,
3489 RTE_FLOW_ERROR_TYPE_ACTION,
3490 NULL, "unsupported too small "
3491 "raw decap and too small raw "
3492 "encap combination");
3495 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3496 item_flags, attr, error);
3499 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3503 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3504 return rte_flow_error_set(error, ENOTSUP,
3505 RTE_FLOW_ERROR_TYPE_ACTION,
3507 "small raw encap size");
3508 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3509 return rte_flow_error_set(error, EINVAL,
3510 RTE_FLOW_ERROR_TYPE_ACTION,
3512 "more than one encap action");
3513 if (!attr->transfer && priv->representor)
3514 return rte_flow_error_set
3516 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3517 "encap action for VF representor "
3518 "not supported on NIC table");
3519 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3526 * Validate the ASO CT action.
3529 * Pointer to the rte_eth_dev structure.
3530 * @param[in] action_flags
3531 * Holds the actions detected until now.
3532 * @param[in] item_flags
3533 * The items found in this flow rule.
3535 * Pointer to flow attributes.
3537 * Pointer to error structure.
3540 * 0 on success, a negative errno value otherwise and rte_errno is set.
3543 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3544 uint64_t action_flags,
3545 uint64_t item_flags,
3546 const struct rte_flow_attr *attr,
3547 struct rte_flow_error *error)
3551 if (attr->group == 0 && !attr->transfer)
3552 return rte_flow_error_set(error, ENOTSUP,
3553 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3555 "Only support non-root table");
3556 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3557 return rte_flow_error_set(error, ENOTSUP,
3558 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3559 "CT cannot follow a fate action");
3560 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3561 (action_flags & MLX5_FLOW_ACTION_AGE))
3562 return rte_flow_error_set(error, EINVAL,
3563 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3564 "Only one ASO action is supported");
3565 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3566 return rte_flow_error_set(error, EINVAL,
3567 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3568 "Encap cannot exist before CT");
3569 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3570 return rte_flow_error_set(error, EINVAL,
3571 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3572 "Not a outer TCP packet");
3577 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3578 struct mlx5_list_entry *entry, void *cb_ctx)
3580 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3581 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3582 struct mlx5_flow_dv_encap_decap_resource *resource;
3584 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3586 if (resource->reformat_type == ctx_resource->reformat_type &&
3587 resource->ft_type == ctx_resource->ft_type &&
3588 resource->flags == ctx_resource->flags &&
3589 resource->size == ctx_resource->size &&
3590 !memcmp((const void *)resource->buf,
3591 (const void *)ctx_resource->buf,
3597 struct mlx5_list_entry *
3598 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3600 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3601 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3602 struct mlx5dv_dr_domain *domain;
3603 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3604 struct mlx5_flow_dv_encap_decap_resource *resource;
3608 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3609 domain = sh->fdb_domain;
3610 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3611 domain = sh->rx_domain;
3613 domain = sh->tx_domain;
3614 /* Register new encap/decap resource. */
3615 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3617 rte_flow_error_set(ctx->error, ENOMEM,
3618 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3619 "cannot allocate resource memory");
3622 *resource = *ctx_resource;
3623 resource->idx = idx;
3624 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3628 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3629 rte_flow_error_set(ctx->error, ENOMEM,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3631 NULL, "cannot create action");
3635 return &resource->entry;
3638 struct mlx5_list_entry *
3639 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3642 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3643 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3644 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3647 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3649 if (!cache_resource) {
3650 rte_flow_error_set(ctx->error, ENOMEM,
3651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3652 "cannot allocate resource memory");
3655 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3656 cache_resource->idx = idx;
3657 return &cache_resource->entry;
3661 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3663 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3664 struct mlx5_flow_dv_encap_decap_resource *res =
3665 container_of(entry, typeof(*res), entry);
3667 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3671 * Find existing encap/decap resource or create and register a new one.
3673 * @param[in, out] dev
3674 * Pointer to rte_eth_dev structure.
3675 * @param[in, out] resource
3676 * Pointer to encap/decap resource.
3677 * @parm[in, out] dev_flow
3678 * Pointer to the dev_flow.
3680 * pointer to error structure.
3683 * 0 on success otherwise -errno and errno is set.
3686 flow_dv_encap_decap_resource_register
3687 (struct rte_eth_dev *dev,
3688 struct mlx5_flow_dv_encap_decap_resource *resource,
3689 struct mlx5_flow *dev_flow,
3690 struct rte_flow_error *error)
3692 struct mlx5_priv *priv = dev->data->dev_private;
3693 struct mlx5_dev_ctx_shared *sh = priv->sh;
3694 struct mlx5_list_entry *entry;
3698 uint32_t refmt_type:8;
3700 * Header reformat actions can be shared between
3701 * non-root tables. One bit to indicate non-root
3705 uint32_t reserve:15;
3708 } encap_decap_key = {
3710 .ft_type = resource->ft_type,
3711 .refmt_type = resource->reformat_type,
3712 .is_root = !!dev_flow->dv.group,
3716 struct mlx5_flow_cb_ctx ctx = {
3720 struct mlx5_hlist *encaps_decaps;
3723 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3725 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3727 flow_dv_encap_decap_create_cb,
3728 flow_dv_encap_decap_match_cb,
3729 flow_dv_encap_decap_remove_cb,
3730 flow_dv_encap_decap_clone_cb,
3731 flow_dv_encap_decap_clone_free_cb);
3732 if (unlikely(!encaps_decaps))
3734 resource->flags = dev_flow->dv.group ? 0 : 1;
3735 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3736 sizeof(encap_decap_key.v32), 0);
3737 if (resource->reformat_type !=
3738 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3740 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3741 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3744 resource = container_of(entry, typeof(*resource), entry);
3745 dev_flow->dv.encap_decap = resource;
3746 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3751 * Find existing table jump resource or create and register a new one.
3753 * @param[in, out] dev
3754 * Pointer to rte_eth_dev structure.
3755 * @param[in, out] tbl
3756 * Pointer to flow table resource.
3757 * @parm[in, out] dev_flow
3758 * Pointer to the dev_flow.
3760 * pointer to error structure.
3763 * 0 on success otherwise -errno and errno is set.
3766 flow_dv_jump_tbl_resource_register
3767 (struct rte_eth_dev *dev __rte_unused,
3768 struct mlx5_flow_tbl_resource *tbl,
3769 struct mlx5_flow *dev_flow,
3770 struct rte_flow_error *error __rte_unused)
3772 struct mlx5_flow_tbl_data_entry *tbl_data =
3773 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3776 MLX5_ASSERT(tbl_data->jump.action);
3777 dev_flow->handle->rix_jump = tbl_data->idx;
3778 dev_flow->dv.jump = &tbl_data->jump;
3783 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3784 struct mlx5_list_entry *entry, void *cb_ctx)
3786 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3787 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3788 struct mlx5_flow_dv_port_id_action_resource *res =
3789 container_of(entry, typeof(*res), entry);
3791 return ref->port_id != res->port_id;
3794 struct mlx5_list_entry *
3795 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3797 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3798 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3799 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3800 struct mlx5_flow_dv_port_id_action_resource *resource;
3804 /* Register new port id action resource. */
3805 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3807 rte_flow_error_set(ctx->error, ENOMEM,
3808 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3809 "cannot allocate port_id action memory");
3813 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3817 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3818 rte_flow_error_set(ctx->error, ENOMEM,
3819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3820 "cannot create action");
3823 resource->idx = idx;
3824 return &resource->entry;
3827 struct mlx5_list_entry *
3828 flow_dv_port_id_clone_cb(void *tool_ctx,
3829 struct mlx5_list_entry *entry __rte_unused,
3832 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3833 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3834 struct mlx5_flow_dv_port_id_action_resource *resource;
3837 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3839 rte_flow_error_set(ctx->error, ENOMEM,
3840 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3841 "cannot allocate port_id action memory");
3844 memcpy(resource, entry, sizeof(*resource));
3845 resource->idx = idx;
3846 return &resource->entry;
3850 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3852 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3853 struct mlx5_flow_dv_port_id_action_resource *resource =
3854 container_of(entry, typeof(*resource), entry);
3856 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3860 * Find existing table port ID resource or create and register a new one.
3862 * @param[in, out] dev
3863 * Pointer to rte_eth_dev structure.
3864 * @param[in, out] ref
3865 * Pointer to port ID action resource reference.
3866 * @parm[in, out] dev_flow
3867 * Pointer to the dev_flow.
3869 * pointer to error structure.
3872 * 0 on success otherwise -errno and errno is set.
3875 flow_dv_port_id_action_resource_register
3876 (struct rte_eth_dev *dev,
3877 struct mlx5_flow_dv_port_id_action_resource *ref,
3878 struct mlx5_flow *dev_flow,
3879 struct rte_flow_error *error)
3881 struct mlx5_priv *priv = dev->data->dev_private;
3882 struct mlx5_list_entry *entry;
3883 struct mlx5_flow_dv_port_id_action_resource *resource;
3884 struct mlx5_flow_cb_ctx ctx = {
3889 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3892 resource = container_of(entry, typeof(*resource), entry);
3893 dev_flow->dv.port_id_action = resource;
3894 dev_flow->handle->rix_port_id_action = resource->idx;
3899 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3900 struct mlx5_list_entry *entry, void *cb_ctx)
3902 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3903 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3904 struct mlx5_flow_dv_push_vlan_action_resource *res =
3905 container_of(entry, typeof(*res), entry);
3907 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3910 struct mlx5_list_entry *
3911 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3913 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3914 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3915 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3916 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3917 struct mlx5dv_dr_domain *domain;
3921 /* Register new port id action resource. */
3922 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3924 rte_flow_error_set(ctx->error, ENOMEM,
3925 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3926 "cannot allocate push_vlan action memory");
3930 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3931 domain = sh->fdb_domain;
3932 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3933 domain = sh->rx_domain;
3935 domain = sh->tx_domain;
3936 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3939 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3940 rte_flow_error_set(ctx->error, ENOMEM,
3941 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3942 "cannot create push vlan action");
3945 resource->idx = idx;
3946 return &resource->entry;
3949 struct mlx5_list_entry *
3950 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3951 struct mlx5_list_entry *entry __rte_unused,
3954 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3955 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3956 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3959 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3961 rte_flow_error_set(ctx->error, ENOMEM,
3962 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3963 "cannot allocate push_vlan action memory");
3966 memcpy(resource, entry, sizeof(*resource));
3967 resource->idx = idx;
3968 return &resource->entry;
3972 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3974 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3975 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3976 container_of(entry, typeof(*resource), entry);
3978 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3982 * Find existing push vlan resource or create and register a new one.
3984 * @param [in, out] dev
3985 * Pointer to rte_eth_dev structure.
3986 * @param[in, out] ref
3987 * Pointer to port ID action resource reference.
3988 * @parm[in, out] dev_flow
3989 * Pointer to the dev_flow.
3991 * pointer to error structure.
3994 * 0 on success otherwise -errno and errno is set.
3997 flow_dv_push_vlan_action_resource_register
3998 (struct rte_eth_dev *dev,
3999 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4000 struct mlx5_flow *dev_flow,
4001 struct rte_flow_error *error)
4003 struct mlx5_priv *priv = dev->data->dev_private;
4004 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4005 struct mlx5_list_entry *entry;
4006 struct mlx5_flow_cb_ctx ctx = {
4011 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4014 resource = container_of(entry, typeof(*resource), entry);
4016 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4017 dev_flow->dv.push_vlan_res = resource;
4022 * Get the size of specific rte_flow_item_type hdr size
4024 * @param[in] item_type
4025 * Tested rte_flow_item_type.
4028 * sizeof struct item_type, 0 if void or irrelevant.
4031 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4035 switch (item_type) {
4036 case RTE_FLOW_ITEM_TYPE_ETH:
4037 retval = sizeof(struct rte_ether_hdr);
4039 case RTE_FLOW_ITEM_TYPE_VLAN:
4040 retval = sizeof(struct rte_vlan_hdr);
4042 case RTE_FLOW_ITEM_TYPE_IPV4:
4043 retval = sizeof(struct rte_ipv4_hdr);
4045 case RTE_FLOW_ITEM_TYPE_IPV6:
4046 retval = sizeof(struct rte_ipv6_hdr);
4048 case RTE_FLOW_ITEM_TYPE_UDP:
4049 retval = sizeof(struct rte_udp_hdr);
4051 case RTE_FLOW_ITEM_TYPE_TCP:
4052 retval = sizeof(struct rte_tcp_hdr);
4054 case RTE_FLOW_ITEM_TYPE_VXLAN:
4055 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4056 retval = sizeof(struct rte_vxlan_hdr);
4058 case RTE_FLOW_ITEM_TYPE_GRE:
4059 case RTE_FLOW_ITEM_TYPE_NVGRE:
4060 retval = sizeof(struct rte_gre_hdr);
4062 case RTE_FLOW_ITEM_TYPE_MPLS:
4063 retval = sizeof(struct rte_mpls_hdr);
4065 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4073 #define MLX5_ENCAP_IPV4_VERSION 0x40
4074 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4075 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4076 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4077 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4078 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4079 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4082 * Convert the encap action data from list of rte_flow_item to raw buffer
4085 * Pointer to rte_flow_item objects list.
4087 * Pointer to the output buffer.
4089 * Pointer to the output buffer size.
4091 * Pointer to the error structure.
4094 * 0 on success, a negative errno value otherwise and rte_errno is set.
4097 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4098 size_t *size, struct rte_flow_error *error)
4100 struct rte_ether_hdr *eth = NULL;
4101 struct rte_vlan_hdr *vlan = NULL;
4102 struct rte_ipv4_hdr *ipv4 = NULL;
4103 struct rte_ipv6_hdr *ipv6 = NULL;
4104 struct rte_udp_hdr *udp = NULL;
4105 struct rte_vxlan_hdr *vxlan = NULL;
4106 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4107 struct rte_gre_hdr *gre = NULL;
4109 size_t temp_size = 0;
4112 return rte_flow_error_set(error, EINVAL,
4113 RTE_FLOW_ERROR_TYPE_ACTION,
4114 NULL, "invalid empty data");
4115 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4116 len = flow_dv_get_item_hdr_len(items->type);
4117 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4118 return rte_flow_error_set(error, EINVAL,
4119 RTE_FLOW_ERROR_TYPE_ACTION,
4120 (void *)items->type,
4121 "items total size is too big"
4122 " for encap action");
4123 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4124 switch (items->type) {
4125 case RTE_FLOW_ITEM_TYPE_ETH:
4126 eth = (struct rte_ether_hdr *)&buf[temp_size];
4128 case RTE_FLOW_ITEM_TYPE_VLAN:
4129 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4131 return rte_flow_error_set(error, EINVAL,
4132 RTE_FLOW_ERROR_TYPE_ACTION,
4133 (void *)items->type,
4134 "eth header not found");
4135 if (!eth->ether_type)
4136 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4138 case RTE_FLOW_ITEM_TYPE_IPV4:
4139 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4141 return rte_flow_error_set(error, EINVAL,
4142 RTE_FLOW_ERROR_TYPE_ACTION,
4143 (void *)items->type,
4144 "neither eth nor vlan"
4146 if (vlan && !vlan->eth_proto)
4147 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4148 else if (eth && !eth->ether_type)
4149 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4150 if (!ipv4->version_ihl)
4151 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4152 MLX5_ENCAP_IPV4_IHL_MIN;
4153 if (!ipv4->time_to_live)
4154 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4156 case RTE_FLOW_ITEM_TYPE_IPV6:
4157 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4159 return rte_flow_error_set(error, EINVAL,
4160 RTE_FLOW_ERROR_TYPE_ACTION,
4161 (void *)items->type,
4162 "neither eth nor vlan"
4164 if (vlan && !vlan->eth_proto)
4165 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4166 else if (eth && !eth->ether_type)
4167 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4168 if (!ipv6->vtc_flow)
4170 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4171 if (!ipv6->hop_limits)
4172 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4174 case RTE_FLOW_ITEM_TYPE_UDP:
4175 udp = (struct rte_udp_hdr *)&buf[temp_size];
4177 return rte_flow_error_set(error, EINVAL,
4178 RTE_FLOW_ERROR_TYPE_ACTION,
4179 (void *)items->type,
4180 "ip header not found");
4181 if (ipv4 && !ipv4->next_proto_id)
4182 ipv4->next_proto_id = IPPROTO_UDP;
4183 else if (ipv6 && !ipv6->proto)
4184 ipv6->proto = IPPROTO_UDP;
4186 case RTE_FLOW_ITEM_TYPE_VXLAN:
4187 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4189 return rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ACTION,
4191 (void *)items->type,
4192 "udp header not found");
4194 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4195 if (!vxlan->vx_flags)
4197 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4199 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4200 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4202 return rte_flow_error_set(error, EINVAL,
4203 RTE_FLOW_ERROR_TYPE_ACTION,
4204 (void *)items->type,
4205 "udp header not found");
4206 if (!vxlan_gpe->proto)
4207 return rte_flow_error_set(error, EINVAL,
4208 RTE_FLOW_ERROR_TYPE_ACTION,
4209 (void *)items->type,
4210 "next protocol not found");
4213 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4214 if (!vxlan_gpe->vx_flags)
4215 vxlan_gpe->vx_flags =
4216 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4218 case RTE_FLOW_ITEM_TYPE_GRE:
4219 case RTE_FLOW_ITEM_TYPE_NVGRE:
4220 gre = (struct rte_gre_hdr *)&buf[temp_size];
4222 return rte_flow_error_set(error, EINVAL,
4223 RTE_FLOW_ERROR_TYPE_ACTION,
4224 (void *)items->type,
4225 "next protocol not found");
4227 return rte_flow_error_set(error, EINVAL,
4228 RTE_FLOW_ERROR_TYPE_ACTION,
4229 (void *)items->type,
4230 "ip header not found");
4231 if (ipv4 && !ipv4->next_proto_id)
4232 ipv4->next_proto_id = IPPROTO_GRE;
4233 else if (ipv6 && !ipv6->proto)
4234 ipv6->proto = IPPROTO_GRE;
4236 case RTE_FLOW_ITEM_TYPE_VOID:
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION,
4241 (void *)items->type,
4242 "unsupported item type");
4252 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4254 struct rte_ether_hdr *eth = NULL;
4255 struct rte_vlan_hdr *vlan = NULL;
4256 struct rte_ipv6_hdr *ipv6 = NULL;
4257 struct rte_udp_hdr *udp = NULL;
4261 eth = (struct rte_ether_hdr *)data;
4262 next_hdr = (char *)(eth + 1);
4263 proto = RTE_BE16(eth->ether_type);
4266 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4267 vlan = (struct rte_vlan_hdr *)next_hdr;
4268 proto = RTE_BE16(vlan->eth_proto);
4269 next_hdr += sizeof(struct rte_vlan_hdr);
4272 /* HW calculates IPv4 csum. no need to proceed */
4273 if (proto == RTE_ETHER_TYPE_IPV4)
4276 /* non IPv4/IPv6 header. not supported */
4277 if (proto != RTE_ETHER_TYPE_IPV6) {
4278 return rte_flow_error_set(error, ENOTSUP,
4279 RTE_FLOW_ERROR_TYPE_ACTION,
4280 NULL, "Cannot offload non IPv4/IPv6");
4283 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4285 /* ignore non UDP */
4286 if (ipv6->proto != IPPROTO_UDP)
4289 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4290 udp->dgram_cksum = 0;
4296 * Convert L2 encap action to DV specification.
4299 * Pointer to rte_eth_dev structure.
4301 * Pointer to action structure.
4302 * @param[in, out] dev_flow
4303 * Pointer to the mlx5_flow.
4304 * @param[in] transfer
4305 * Mark if the flow is E-Switch flow.
4307 * Pointer to the error structure.
4310 * 0 on success, a negative errno value otherwise and rte_errno is set.
4313 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4314 const struct rte_flow_action *action,
4315 struct mlx5_flow *dev_flow,
4317 struct rte_flow_error *error)
4319 const struct rte_flow_item *encap_data;
4320 const struct rte_flow_action_raw_encap *raw_encap_data;
4321 struct mlx5_flow_dv_encap_decap_resource res = {
4323 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4324 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4325 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4328 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4330 (const struct rte_flow_action_raw_encap *)action->conf;
4331 res.size = raw_encap_data->size;
4332 memcpy(res.buf, raw_encap_data->data, res.size);
4334 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4336 ((const struct rte_flow_action_vxlan_encap *)
4337 action->conf)->definition;
4340 ((const struct rte_flow_action_nvgre_encap *)
4341 action->conf)->definition;
4342 if (flow_dv_convert_encap_data(encap_data, res.buf,
4346 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4348 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4349 return rte_flow_error_set(error, EINVAL,
4350 RTE_FLOW_ERROR_TYPE_ACTION,
4351 NULL, "can't create L2 encap action");
4356 * Convert L2 decap action to DV specification.
4359 * Pointer to rte_eth_dev structure.
4360 * @param[in, out] dev_flow
4361 * Pointer to the mlx5_flow.
4362 * @param[in] transfer
4363 * Mark if the flow is E-Switch flow.
4365 * Pointer to the error structure.
4368 * 0 on success, a negative errno value otherwise and rte_errno is set.
4371 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4372 struct mlx5_flow *dev_flow,
4374 struct rte_flow_error *error)
4376 struct mlx5_flow_dv_encap_decap_resource res = {
4379 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4380 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4381 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4384 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4385 return rte_flow_error_set(error, EINVAL,
4386 RTE_FLOW_ERROR_TYPE_ACTION,
4387 NULL, "can't create L2 decap action");
4392 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4395 * Pointer to rte_eth_dev structure.
4397 * Pointer to action structure.
4398 * @param[in, out] dev_flow
4399 * Pointer to the mlx5_flow.
4401 * Pointer to the flow attributes.
4403 * Pointer to the error structure.
4406 * 0 on success, a negative errno value otherwise and rte_errno is set.
4409 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4410 const struct rte_flow_action *action,
4411 struct mlx5_flow *dev_flow,
4412 const struct rte_flow_attr *attr,
4413 struct rte_flow_error *error)
4415 const struct rte_flow_action_raw_encap *encap_data;
4416 struct mlx5_flow_dv_encap_decap_resource res;
4418 memset(&res, 0, sizeof(res));
4419 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4420 res.size = encap_data->size;
4421 memcpy(res.buf, encap_data->data, res.size);
4422 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4423 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4424 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4426 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4428 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4429 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4430 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4431 return rte_flow_error_set(error, EINVAL,
4432 RTE_FLOW_ERROR_TYPE_ACTION,
4433 NULL, "can't create encap action");
4438 * Create action push VLAN.
4441 * Pointer to rte_eth_dev structure.
4443 * Pointer to the flow attributes.
4445 * Pointer to the vlan to push to the Ethernet header.
4446 * @param[in, out] dev_flow
4447 * Pointer to the mlx5_flow.
4449 * Pointer to the error structure.
4452 * 0 on success, a negative errno value otherwise and rte_errno is set.
4455 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4456 const struct rte_flow_attr *attr,
4457 const struct rte_vlan_hdr *vlan,
4458 struct mlx5_flow *dev_flow,
4459 struct rte_flow_error *error)
4461 struct mlx5_flow_dv_push_vlan_action_resource res;
4463 memset(&res, 0, sizeof(res));
4465 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4468 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4470 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4471 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4472 return flow_dv_push_vlan_action_resource_register
4473 (dev, &res, dev_flow, error);
4477 * Validate the modify-header actions.
4479 * @param[in] action_flags
4480 * Holds the actions detected until now.
4482 * Pointer to the modify action.
4484 * Pointer to error structure.
4487 * 0 on success, a negative errno value otherwise and rte_errno is set.
4490 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4491 const struct rte_flow_action *action,
4492 struct rte_flow_error *error)
4494 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4495 return rte_flow_error_set(error, EINVAL,
4496 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4497 NULL, "action configuration not set");
4498 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4499 return rte_flow_error_set(error, EINVAL,
4500 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4501 "can't have encap action before"
4507 * Validate the modify-header MAC address actions.
4509 * @param[in] action_flags
4510 * Holds the actions detected until now.
4512 * Pointer to the modify action.
4513 * @param[in] item_flags
4514 * Holds the items detected.
4516 * Pointer to error structure.
4519 * 0 on success, a negative errno value otherwise and rte_errno is set.
4522 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4523 const struct rte_flow_action *action,
4524 const uint64_t item_flags,
4525 struct rte_flow_error *error)
4529 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4531 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4532 return rte_flow_error_set(error, EINVAL,
4533 RTE_FLOW_ERROR_TYPE_ACTION,
4535 "no L2 item in pattern");
4541 * Validate the modify-header IPv4 address actions.
4543 * @param[in] action_flags
4544 * Holds the actions detected until now.
4546 * Pointer to the modify action.
4547 * @param[in] item_flags
4548 * Holds the items detected.
4550 * Pointer to error structure.
4553 * 0 on success, a negative errno value otherwise and rte_errno is set.
4556 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4557 const struct rte_flow_action *action,
4558 const uint64_t item_flags,
4559 struct rte_flow_error *error)
4564 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4566 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4567 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4568 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4569 if (!(item_flags & layer))
4570 return rte_flow_error_set(error, EINVAL,
4571 RTE_FLOW_ERROR_TYPE_ACTION,
4573 "no ipv4 item in pattern");
4579 * Validate the modify-header IPv6 address actions.
4581 * @param[in] action_flags
4582 * Holds the actions detected until now.
4584 * Pointer to the modify action.
4585 * @param[in] item_flags
4586 * Holds the items detected.
4588 * Pointer to error structure.
4591 * 0 on success, a negative errno value otherwise and rte_errno is set.
4594 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4595 const struct rte_flow_action *action,
4596 const uint64_t item_flags,
4597 struct rte_flow_error *error)
4602 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4604 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4605 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4606 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4607 if (!(item_flags & layer))
4608 return rte_flow_error_set(error, EINVAL,
4609 RTE_FLOW_ERROR_TYPE_ACTION,
4611 "no ipv6 item in pattern");
4617 * Validate the modify-header TP actions.
4619 * @param[in] action_flags
4620 * Holds the actions detected until now.
4622 * Pointer to the modify action.
4623 * @param[in] item_flags
4624 * Holds the items detected.
4626 * Pointer to error structure.
4629 * 0 on success, a negative errno value otherwise and rte_errno is set.
4632 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4633 const struct rte_flow_action *action,
4634 const uint64_t item_flags,
4635 struct rte_flow_error *error)
4640 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4642 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4643 MLX5_FLOW_LAYER_INNER_L4 :
4644 MLX5_FLOW_LAYER_OUTER_L4;
4645 if (!(item_flags & layer))
4646 return rte_flow_error_set(error, EINVAL,
4647 RTE_FLOW_ERROR_TYPE_ACTION,
4648 NULL, "no transport layer "
4655 * Validate the modify-header actions of increment/decrement
4656 * TCP Sequence-number.
4658 * @param[in] action_flags
4659 * Holds the actions detected until now.
4661 * Pointer to the modify action.
4662 * @param[in] item_flags
4663 * Holds the items detected.
4665 * Pointer to error structure.
4668 * 0 on success, a negative errno value otherwise and rte_errno is set.
4671 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4672 const struct rte_flow_action *action,
4673 const uint64_t item_flags,
4674 struct rte_flow_error *error)
4679 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4681 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4682 MLX5_FLOW_LAYER_INNER_L4_TCP :
4683 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4684 if (!(item_flags & layer))
4685 return rte_flow_error_set(error, EINVAL,
4686 RTE_FLOW_ERROR_TYPE_ACTION,
4687 NULL, "no TCP item in"
4689 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4690 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4691 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4692 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4693 return rte_flow_error_set(error, EINVAL,
4694 RTE_FLOW_ERROR_TYPE_ACTION,
4696 "cannot decrease and increase"
4697 " TCP sequence number"
4698 " at the same time");
4704 * Validate the modify-header actions of increment/decrement
4705 * TCP Acknowledgment number.
4707 * @param[in] action_flags
4708 * Holds the actions detected until now.
4710 * Pointer to the modify action.
4711 * @param[in] item_flags
4712 * Holds the items detected.
4714 * Pointer to error structure.
4717 * 0 on success, a negative errno value otherwise and rte_errno is set.
4720 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4721 const struct rte_flow_action *action,
4722 const uint64_t item_flags,
4723 struct rte_flow_error *error)
4728 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4730 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4731 MLX5_FLOW_LAYER_INNER_L4_TCP :
4732 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4733 if (!(item_flags & layer))
4734 return rte_flow_error_set(error, EINVAL,
4735 RTE_FLOW_ERROR_TYPE_ACTION,
4736 NULL, "no TCP item in"
4738 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4739 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4740 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4741 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4742 return rte_flow_error_set(error, EINVAL,
4743 RTE_FLOW_ERROR_TYPE_ACTION,
4745 "cannot decrease and increase"
4746 " TCP acknowledgment number"
4747 " at the same time");
4753 * Validate the modify-header TTL actions.
4755 * @param[in] action_flags
4756 * Holds the actions detected until now.
4758 * Pointer to the modify action.
4759 * @param[in] item_flags
4760 * Holds the items detected.
4762 * Pointer to error structure.
4765 * 0 on success, a negative errno value otherwise and rte_errno is set.
4768 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4769 const struct rte_flow_action *action,
4770 const uint64_t item_flags,
4771 struct rte_flow_error *error)
4776 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4778 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4779 MLX5_FLOW_LAYER_INNER_L3 :
4780 MLX5_FLOW_LAYER_OUTER_L3;
4781 if (!(item_flags & layer))
4782 return rte_flow_error_set(error, EINVAL,
4783 RTE_FLOW_ERROR_TYPE_ACTION,
4785 "no IP protocol in pattern");
4791 * Validate the generic modify field actions.
4793 * Pointer to the rte_eth_dev structure.
4794 * @param[in] action_flags
4795 * Holds the actions detected until now.
4797 * Pointer to the modify action.
4799 * Pointer to the flow attributes.
4801 * Pointer to error structure.
4804 * Number of header fields to modify (0 or more) on success,
4805 * a negative errno value otherwise and rte_errno is set.
4808 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4809 const uint64_t action_flags,
4810 const struct rte_flow_action *action,
4811 const struct rte_flow_attr *attr,
4812 struct rte_flow_error *error)
4815 struct mlx5_priv *priv = dev->data->dev_private;
4816 struct mlx5_dev_config *config = &priv->config;
4817 const struct rte_flow_action_modify_field *action_modify_field =
4819 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4820 action_modify_field->dst.field,
4822 uint32_t src_width = mlx5_flow_item_field_width(dev,
4823 action_modify_field->src.field,
4824 dst_width, attr, error);
4826 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4830 if (action_modify_field->width == 0)
4831 return rte_flow_error_set(error, EINVAL,
4832 RTE_FLOW_ERROR_TYPE_ACTION, action,
4833 "no bits are requested to be modified");
4834 else if (action_modify_field->width > dst_width ||
4835 action_modify_field->width > src_width)
4836 return rte_flow_error_set(error, EINVAL,
4837 RTE_FLOW_ERROR_TYPE_ACTION, action,
4838 "cannot modify more bits than"
4839 " the width of a field");
4840 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4841 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4842 if ((action_modify_field->dst.offset +
4843 action_modify_field->width > dst_width) ||
4844 (action_modify_field->dst.offset % 32))
4845 return rte_flow_error_set(error, EINVAL,
4846 RTE_FLOW_ERROR_TYPE_ACTION, action,
4847 "destination offset is too big"
4848 " or not aligned to 4 bytes");
4849 if (action_modify_field->dst.level &&
4850 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4851 return rte_flow_error_set(error, ENOTSUP,
4852 RTE_FLOW_ERROR_TYPE_ACTION, action,
4853 "inner header fields modification"
4854 " is not supported");
4856 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4857 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4858 if (!attr->transfer && !attr->group)
4859 return rte_flow_error_set(error, ENOTSUP,
4860 RTE_FLOW_ERROR_TYPE_ACTION, action,
4861 "modify field action is not"
4862 " supported for group 0");
4863 if ((action_modify_field->src.offset +
4864 action_modify_field->width > src_width) ||
4865 (action_modify_field->src.offset % 32))
4866 return rte_flow_error_set(error, EINVAL,
4867 RTE_FLOW_ERROR_TYPE_ACTION, action,
4868 "source offset is too big"
4869 " or not aligned to 4 bytes");
4870 if (action_modify_field->src.level &&
4871 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4872 return rte_flow_error_set(error, ENOTSUP,
4873 RTE_FLOW_ERROR_TYPE_ACTION, action,
4874 "inner header fields modification"
4875 " is not supported");
4877 if ((action_modify_field->dst.field ==
4878 action_modify_field->src.field) &&
4879 (action_modify_field->dst.level ==
4880 action_modify_field->src.level))
4881 return rte_flow_error_set(error, EINVAL,
4882 RTE_FLOW_ERROR_TYPE_ACTION, action,
4883 "source and destination fields"
4884 " cannot be the same");
4885 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4886 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4887 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4888 return rte_flow_error_set(error, EINVAL,
4889 RTE_FLOW_ERROR_TYPE_ACTION, action,
4890 "mark, immediate value or a pointer to it"
4891 " cannot be used as a destination");
4892 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4893 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4894 return rte_flow_error_set(error, ENOTSUP,
4895 RTE_FLOW_ERROR_TYPE_ACTION, action,
4896 "modifications of an arbitrary"
4897 " place in a packet is not supported");
4898 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4899 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4900 return rte_flow_error_set(error, ENOTSUP,
4901 RTE_FLOW_ERROR_TYPE_ACTION, action,
4902 "modifications of the 802.1Q Tag"
4903 " Identifier is not supported");
4904 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4905 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4906 return rte_flow_error_set(error, ENOTSUP,
4907 RTE_FLOW_ERROR_TYPE_ACTION, action,
4908 "modifications of the VXLAN Network"
4909 " Identifier is not supported");
4910 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4911 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION, action,
4914 "modifications of the GENEVE Network"
4915 " Identifier is not supported");
4916 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4917 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4918 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4919 !mlx5_flow_ext_mreg_supported(dev))
4920 return rte_flow_error_set(error, ENOTSUP,
4921 RTE_FLOW_ERROR_TYPE_ACTION, action,
4922 "cannot modify mark in legacy mode"
4923 " or without extensive registers");
4924 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4925 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4926 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4927 !mlx5_flow_ext_mreg_supported(dev))
4928 return rte_flow_error_set(error, ENOTSUP,
4929 RTE_FLOW_ERROR_TYPE_ACTION, action,
4930 "cannot modify meta without"
4931 " extensive registers support");
4932 ret = flow_dv_get_metadata_reg(dev, attr, error);
4933 if (ret < 0 || ret == REG_NON)
4934 return rte_flow_error_set(error, ENOTSUP,
4935 RTE_FLOW_ERROR_TYPE_ACTION, action,
4936 "cannot modify meta without"
4937 " extensive registers available");
4939 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4940 return rte_flow_error_set(error, ENOTSUP,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "add and sub operations"
4943 " are not supported");
4944 return (action_modify_field->width / 32) +
4945 !!(action_modify_field->width % 32);
4949 * Validate jump action.
4952 * Pointer to the jump action.
4953 * @param[in] action_flags
4954 * Holds the actions detected until now.
4955 * @param[in] attributes
4956 * Pointer to flow attributes
4957 * @param[in] external
4958 * Action belongs to flow rule created by request external to PMD.
4960 * Pointer to error structure.
4963 * 0 on success, a negative errno value otherwise and rte_errno is set.
4966 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4967 const struct mlx5_flow_tunnel *tunnel,
4968 const struct rte_flow_action *action,
4969 uint64_t action_flags,
4970 const struct rte_flow_attr *attributes,
4971 bool external, struct rte_flow_error *error)
4973 uint32_t target_group, table;
4975 struct flow_grp_info grp_info = {
4976 .external = !!external,
4977 .transfer = !!attributes->transfer,
4981 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4982 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4983 return rte_flow_error_set(error, EINVAL,
4984 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4985 "can't have 2 fate actions in"
4988 return rte_flow_error_set(error, EINVAL,
4989 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4990 NULL, "action configuration not set");
4992 ((const struct rte_flow_action_jump *)action->conf)->group;
4993 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4997 if (attributes->group == target_group &&
4998 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4999 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5000 return rte_flow_error_set(error, EINVAL,
5001 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5002 "target group must be other than"
5003 " the current flow group");
5008 * Validate action PORT_ID / REPRESENTED_PORT.
5011 * Pointer to rte_eth_dev structure.
5012 * @param[in] action_flags
5013 * Bit-fields that holds the actions detected until now.
5015 * PORT_ID / REPRESENTED_PORT action structure.
5017 * Attributes of flow that includes this action.
5019 * Pointer to error structure.
5022 * 0 on success, a negative errno value otherwise and rte_errno is set.
5025 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5026 uint64_t action_flags,
5027 const struct rte_flow_action *action,
5028 const struct rte_flow_attr *attr,
5029 struct rte_flow_error *error)
5031 const struct rte_flow_action_port_id *port_id;
5032 const struct rte_flow_action_ethdev *ethdev;
5033 struct mlx5_priv *act_priv;
5034 struct mlx5_priv *dev_priv;
5037 if (!attr->transfer)
5038 return rte_flow_error_set(error, ENOTSUP,
5039 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5041 "port action is valid in transfer"
5043 if (!action || !action->conf)
5044 return rte_flow_error_set(error, ENOTSUP,
5045 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5047 "port action parameters must be"
5049 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5050 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5051 return rte_flow_error_set(error, EINVAL,
5052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5053 "can have only one fate actions in"
5055 dev_priv = mlx5_dev_to_eswitch_info(dev);
5057 return rte_flow_error_set(error, rte_errno,
5058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5060 "failed to obtain E-Switch info");
5061 switch (action->type) {
5062 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5063 port_id = action->conf;
5064 port = port_id->original ? dev->data->port_id : port_id->id;
5066 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5067 ethdev = action->conf;
5068 port = ethdev->port_id;
5072 return rte_flow_error_set
5074 RTE_FLOW_ERROR_TYPE_ACTION, action,
5075 "unknown E-Switch action");
5077 act_priv = mlx5_port_to_eswitch_info(port, false);
5079 return rte_flow_error_set
5081 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5082 "failed to obtain E-Switch port id for port");
5083 if (act_priv->domain_id != dev_priv->domain_id)
5084 return rte_flow_error_set
5086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5087 "port does not belong to"
5088 " E-Switch being configured");
5093 * Get the maximum number of modify header actions.
5096 * Pointer to rte_eth_dev structure.
5098 * Whether action is on root table.
5101 * Max number of modify header actions device can support.
5103 static inline unsigned int
5104 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5108 * There's no way to directly query the max capacity from FW.
5109 * The maximal value on root table should be assumed to be supported.
5112 return MLX5_MAX_MODIFY_NUM;
5114 return MLX5_ROOT_TBL_MODIFY_NUM;
5118 * Validate the meter action.
5121 * Pointer to rte_eth_dev structure.
5122 * @param[in] action_flags
5123 * Bit-fields that holds the actions detected until now.
5125 * Pointer to the meter action.
5127 * Attributes of flow that includes this action.
5128 * @param[in] port_id_item
5129 * Pointer to item indicating port id.
5131 * Pointer to error structure.
5134 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5137 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5138 uint64_t action_flags,
5139 const struct rte_flow_action *action,
5140 const struct rte_flow_attr *attr,
5141 const struct rte_flow_item *port_id_item,
5143 struct rte_flow_error *error)
5145 struct mlx5_priv *priv = dev->data->dev_private;
5146 const struct rte_flow_action_meter *am = action->conf;
5147 struct mlx5_flow_meter_info *fm;
5148 struct mlx5_flow_meter_policy *mtr_policy;
5149 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5152 return rte_flow_error_set(error, EINVAL,
5153 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5154 "meter action conf is NULL");
5156 if (action_flags & MLX5_FLOW_ACTION_METER)
5157 return rte_flow_error_set(error, ENOTSUP,
5158 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5159 "meter chaining not support");
5160 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5161 return rte_flow_error_set(error, ENOTSUP,
5162 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5163 "meter with jump not support");
5165 return rte_flow_error_set(error, ENOTSUP,
5166 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5168 "meter action not supported");
5169 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5171 return rte_flow_error_set(error, EINVAL,
5172 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5174 /* aso meter can always be shared by different domains */
5175 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5176 !(fm->transfer == attr->transfer ||
5177 (!fm->ingress && !attr->ingress && attr->egress) ||
5178 (!fm->egress && !attr->egress && attr->ingress)))
5179 return rte_flow_error_set(error, EINVAL,
5180 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5181 "Flow attributes domain are either invalid "
5182 "or have a domain conflict with current "
5183 "meter attributes");
5184 if (fm->def_policy) {
5185 if (!((attr->transfer &&
5186 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5188 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5190 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5191 return rte_flow_error_set(error, EINVAL,
5192 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5193 "Flow attributes domain "
5194 "have a conflict with current "
5195 "meter domain attributes");
5198 mtr_policy = mlx5_flow_meter_policy_find(dev,
5199 fm->policy_id, NULL);
5201 return rte_flow_error_set(error, EINVAL,
5202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5203 "Invalid policy id for meter ");
5204 if (!((attr->transfer && mtr_policy->transfer) ||
5205 (attr->egress && mtr_policy->egress) ||
5206 (attr->ingress && mtr_policy->ingress)))
5207 return rte_flow_error_set(error, EINVAL,
5208 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5209 "Flow attributes domain "
5210 "have a conflict with current "
5211 "meter domain attributes");
5212 if (attr->transfer && mtr_policy->dev) {
5214 * When policy has fate action of port_id,
5215 * the flow should have the same src port as policy.
5217 struct mlx5_priv *policy_port_priv =
5218 mtr_policy->dev->data->dev_private;
5219 int32_t flow_src_port = priv->representor_id;
5222 const struct rte_flow_item_port_id *spec =
5224 struct mlx5_priv *port_priv =
5225 mlx5_port_to_eswitch_info(spec->id,
5228 return rte_flow_error_set(error,
5230 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5232 "Failed to get port info.");
5233 flow_src_port = port_priv->representor_id;
5235 if (flow_src_port != policy_port_priv->representor_id)
5236 return rte_flow_error_set(error,
5238 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5240 "Flow and meter policy "
5241 "have different src port.");
5243 *def_policy = false;
5249 * Validate the age action.
5251 * @param[in] action_flags
5252 * Holds the actions detected until now.
5254 * Pointer to the age action.
5256 * Pointer to the Ethernet device structure.
5258 * Pointer to error structure.
5261 * 0 on success, a negative errno value otherwise and rte_errno is set.
5264 flow_dv_validate_action_age(uint64_t action_flags,
5265 const struct rte_flow_action *action,
5266 struct rte_eth_dev *dev,
5267 struct rte_flow_error *error)
5269 struct mlx5_priv *priv = dev->data->dev_private;
5270 const struct rte_flow_action_age *age = action->conf;
5272 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5273 !priv->sh->aso_age_mng))
5274 return rte_flow_error_set(error, ENOTSUP,
5275 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5277 "age action not supported");
5278 if (!(action->conf))
5279 return rte_flow_error_set(error, EINVAL,
5280 RTE_FLOW_ERROR_TYPE_ACTION, action,
5281 "configuration cannot be null");
5282 if (!(age->timeout))
5283 return rte_flow_error_set(error, EINVAL,
5284 RTE_FLOW_ERROR_TYPE_ACTION, action,
5285 "invalid timeout value 0");
5286 if (action_flags & MLX5_FLOW_ACTION_AGE)
5287 return rte_flow_error_set(error, EINVAL,
5288 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5289 "duplicate age actions set");
5294 * Validate the modify-header IPv4 DSCP actions.
5296 * @param[in] action_flags
5297 * Holds the actions detected until now.
5299 * Pointer to the modify action.
5300 * @param[in] item_flags
5301 * Holds the items detected.
5303 * Pointer to error structure.
5306 * 0 on success, a negative errno value otherwise and rte_errno is set.
5309 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5310 const struct rte_flow_action *action,
5311 const uint64_t item_flags,
5312 struct rte_flow_error *error)
5316 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5318 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5319 return rte_flow_error_set(error, EINVAL,
5320 RTE_FLOW_ERROR_TYPE_ACTION,
5322 "no ipv4 item in pattern");
5328 * Validate the modify-header IPv6 DSCP actions.
5330 * @param[in] action_flags
5331 * Holds the actions detected until now.
5333 * Pointer to the modify action.
5334 * @param[in] item_flags
5335 * Holds the items detected.
5337 * Pointer to error structure.
5340 * 0 on success, a negative errno value otherwise and rte_errno is set.
5343 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5344 const struct rte_flow_action *action,
5345 const uint64_t item_flags,
5346 struct rte_flow_error *error)
5350 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5352 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5353 return rte_flow_error_set(error, EINVAL,
5354 RTE_FLOW_ERROR_TYPE_ACTION,
5356 "no ipv6 item in pattern");
5362 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5363 struct mlx5_list_entry *entry, void *cb_ctx)
5365 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5366 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5367 struct mlx5_flow_dv_modify_hdr_resource *resource =
5368 container_of(entry, typeof(*resource), entry);
5369 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5371 key_len += ref->actions_num * sizeof(ref->actions[0]);
5372 return ref->actions_num != resource->actions_num ||
5373 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5376 static struct mlx5_indexed_pool *
5377 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5379 struct mlx5_indexed_pool *ipool = __atomic_load_n
5380 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5383 struct mlx5_indexed_pool *expected = NULL;
5384 struct mlx5_indexed_pool_config cfg =
5385 (struct mlx5_indexed_pool_config) {
5386 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5388 sizeof(struct mlx5_modification_cmd),
5393 .release_mem_en = !!sh->reclaim_mode,
5394 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5395 .malloc = mlx5_malloc,
5397 .type = "mlx5_modify_action_resource",
5400 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5401 ipool = mlx5_ipool_create(&cfg);
5404 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5405 &expected, ipool, false,
5407 __ATOMIC_SEQ_CST)) {
5408 mlx5_ipool_destroy(ipool);
5409 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5416 struct mlx5_list_entry *
5417 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5419 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5420 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5421 struct mlx5dv_dr_domain *ns;
5422 struct mlx5_flow_dv_modify_hdr_resource *entry;
5423 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5424 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5425 ref->actions_num - 1);
5427 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5428 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5431 if (unlikely(!ipool)) {
5432 rte_flow_error_set(ctx->error, ENOMEM,
5433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5434 NULL, "cannot allocate modify ipool");
5437 entry = mlx5_ipool_zmalloc(ipool, &idx);
5439 rte_flow_error_set(ctx->error, ENOMEM,
5440 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5441 "cannot allocate resource memory");
5444 rte_memcpy(&entry->ft_type,
5445 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5446 key_len + data_len);
5447 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5448 ns = sh->fdb_domain;
5449 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5453 ret = mlx5_flow_os_create_flow_action_modify_header
5454 (sh->cdev->ctx, ns, entry,
5455 data_len, &entry->action);
5457 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5458 rte_flow_error_set(ctx->error, ENOMEM,
5459 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5460 NULL, "cannot create modification action");
5464 return &entry->entry;
5467 struct mlx5_list_entry *
5468 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5471 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5472 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5473 struct mlx5_flow_dv_modify_hdr_resource *entry;
5474 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5475 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5478 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5481 rte_flow_error_set(ctx->error, ENOMEM,
5482 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5483 "cannot allocate resource memory");
5486 memcpy(entry, oentry, sizeof(*entry) + data_len);
5488 return &entry->entry;
5492 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5494 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5495 struct mlx5_flow_dv_modify_hdr_resource *res =
5496 container_of(entry, typeof(*res), entry);
5498 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5502 * Validate the sample action.
5504 * @param[in, out] action_flags
5505 * Holds the actions detected until now.
5507 * Pointer to the sample action.
5509 * Pointer to the Ethernet device structure.
5511 * Attributes of flow that includes this action.
5512 * @param[in] item_flags
5513 * Holds the items detected.
5515 * Pointer to the RSS action.
5516 * @param[out] sample_rss
5517 * Pointer to the RSS action in sample action list.
5519 * Pointer to the COUNT action in sample action list.
5520 * @param[out] fdb_mirror_limit
5521 * Pointer to the FDB mirror limitation flag.
5523 * Pointer to error structure.
5526 * 0 on success, a negative errno value otherwise and rte_errno is set.
5529 flow_dv_validate_action_sample(uint64_t *action_flags,
5530 const struct rte_flow_action *action,
5531 struct rte_eth_dev *dev,
5532 const struct rte_flow_attr *attr,
5533 uint64_t item_flags,
5534 const struct rte_flow_action_rss *rss,
5535 const struct rte_flow_action_rss **sample_rss,
5536 const struct rte_flow_action_count **count,
5537 int *fdb_mirror_limit,
5538 struct rte_flow_error *error)
5540 struct mlx5_priv *priv = dev->data->dev_private;
5541 struct mlx5_dev_config *dev_conf = &priv->config;
5542 const struct rte_flow_action_sample *sample = action->conf;
5543 const struct rte_flow_action *act;
5544 uint64_t sub_action_flags = 0;
5545 uint16_t queue_index = 0xFFFF;
5550 return rte_flow_error_set(error, EINVAL,
5551 RTE_FLOW_ERROR_TYPE_ACTION, action,
5552 "configuration cannot be NULL");
5553 if (sample->ratio == 0)
5554 return rte_flow_error_set(error, EINVAL,
5555 RTE_FLOW_ERROR_TYPE_ACTION, action,
5556 "ratio value starts from 1");
5557 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5558 return rte_flow_error_set(error, ENOTSUP,
5559 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5561 "sample action not supported");
5562 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5563 return rte_flow_error_set(error, EINVAL,
5564 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5565 "Multiple sample actions not "
5567 if (*action_flags & MLX5_FLOW_ACTION_METER)
5568 return rte_flow_error_set(error, EINVAL,
5569 RTE_FLOW_ERROR_TYPE_ACTION, action,
5570 "wrong action order, meter should "
5571 "be after sample action");
5572 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5573 return rte_flow_error_set(error, EINVAL,
5574 RTE_FLOW_ERROR_TYPE_ACTION, action,
5575 "wrong action order, jump should "
5576 "be after sample action");
5577 if (*action_flags & MLX5_FLOW_ACTION_CT)
5578 return rte_flow_error_set(error, EINVAL,
5579 RTE_FLOW_ERROR_TYPE_ACTION, action,
5580 "Sample after CT not supported");
5581 act = sample->actions;
5582 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5583 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5584 return rte_flow_error_set(error, ENOTSUP,
5585 RTE_FLOW_ERROR_TYPE_ACTION,
5586 act, "too many actions");
5587 switch (act->type) {
5588 case RTE_FLOW_ACTION_TYPE_QUEUE:
5589 ret = mlx5_flow_validate_action_queue(act,
5595 queue_index = ((const struct rte_flow_action_queue *)
5596 (act->conf))->index;
5597 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5600 case RTE_FLOW_ACTION_TYPE_RSS:
5601 *sample_rss = act->conf;
5602 ret = mlx5_flow_validate_action_rss(act,
5609 if (rss && *sample_rss &&
5610 ((*sample_rss)->level != rss->level ||
5611 (*sample_rss)->types != rss->types))
5612 return rte_flow_error_set(error, ENOTSUP,
5613 RTE_FLOW_ERROR_TYPE_ACTION,
5615 "Can't use the different RSS types "
5616 "or level in the same flow");
5617 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5618 queue_index = (*sample_rss)->queue[0];
5619 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5622 case RTE_FLOW_ACTION_TYPE_MARK:
5623 ret = flow_dv_validate_action_mark(dev, act,
5628 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5629 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5630 MLX5_FLOW_ACTION_MARK_EXT;
5632 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5635 case RTE_FLOW_ACTION_TYPE_COUNT:
5636 ret = flow_dv_validate_action_count
5637 (dev, false, *action_flags | sub_action_flags,
5642 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5643 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5646 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5647 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5648 ret = flow_dv_validate_action_port_id(dev,
5655 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5658 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5659 ret = flow_dv_validate_action_raw_encap_decap
5660 (dev, NULL, act->conf, attr, &sub_action_flags,
5661 &actions_n, action, item_flags, error);
5666 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5667 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5668 ret = flow_dv_validate_action_l2_encap(dev,
5674 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5678 return rte_flow_error_set(error, ENOTSUP,
5679 RTE_FLOW_ERROR_TYPE_ACTION,
5681 "Doesn't support optional "
5685 if (attr->ingress && !attr->transfer) {
5686 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5687 MLX5_FLOW_ACTION_RSS)))
5688 return rte_flow_error_set(error, EINVAL,
5689 RTE_FLOW_ERROR_TYPE_ACTION,
5691 "Ingress must has a dest "
5692 "QUEUE for Sample");
5693 } else if (attr->egress && !attr->transfer) {
5694 return rte_flow_error_set(error, ENOTSUP,
5695 RTE_FLOW_ERROR_TYPE_ACTION,
5697 "Sample Only support Ingress "
5699 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5700 MLX5_ASSERT(attr->transfer);
5701 if (sample->ratio > 1)
5702 return rte_flow_error_set(error, ENOTSUP,
5703 RTE_FLOW_ERROR_TYPE_ACTION,
5705 "E-Switch doesn't support "
5706 "any optional action "
5708 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5709 return rte_flow_error_set(error, ENOTSUP,
5710 RTE_FLOW_ERROR_TYPE_ACTION,
5712 "unsupported action QUEUE");
5713 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5714 return rte_flow_error_set(error, ENOTSUP,
5715 RTE_FLOW_ERROR_TYPE_ACTION,
5717 "unsupported action QUEUE");
5718 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5719 return rte_flow_error_set(error, EINVAL,
5720 RTE_FLOW_ERROR_TYPE_ACTION,
5722 "E-Switch must has a dest "
5723 "port for mirroring");
5724 if (!priv->config.hca_attr.reg_c_preserve &&
5725 priv->representor_id != UINT16_MAX)
5726 *fdb_mirror_limit = 1;
5728 /* Continue validation for Xcap actions.*/
5729 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5730 (queue_index == 0xFFFF ||
5731 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5732 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5733 MLX5_FLOW_XCAP_ACTIONS)
5734 return rte_flow_error_set(error, ENOTSUP,
5735 RTE_FLOW_ERROR_TYPE_ACTION,
5736 NULL, "encap and decap "
5737 "combination aren't "
5739 if (!attr->transfer && attr->ingress && (sub_action_flags &
5740 MLX5_FLOW_ACTION_ENCAP))
5741 return rte_flow_error_set(error, ENOTSUP,
5742 RTE_FLOW_ERROR_TYPE_ACTION,
5743 NULL, "encap is not supported"
5744 " for ingress traffic");
5750 * Find existing modify-header resource or create and register a new one.
5752 * @param dev[in, out]
5753 * Pointer to rte_eth_dev structure.
5754 * @param[in, out] resource
5755 * Pointer to modify-header resource.
5756 * @parm[in, out] dev_flow
5757 * Pointer to the dev_flow.
5759 * pointer to error structure.
5762 * 0 on success otherwise -errno and errno is set.
5765 flow_dv_modify_hdr_resource_register
5766 (struct rte_eth_dev *dev,
5767 struct mlx5_flow_dv_modify_hdr_resource *resource,
5768 struct mlx5_flow *dev_flow,
5769 struct rte_flow_error *error)
5771 struct mlx5_priv *priv = dev->data->dev_private;
5772 struct mlx5_dev_ctx_shared *sh = priv->sh;
5773 uint32_t key_len = sizeof(*resource) -
5774 offsetof(typeof(*resource), ft_type) +
5775 resource->actions_num * sizeof(resource->actions[0]);
5776 struct mlx5_list_entry *entry;
5777 struct mlx5_flow_cb_ctx ctx = {
5781 struct mlx5_hlist *modify_cmds;
5784 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5786 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5788 flow_dv_modify_create_cb,
5789 flow_dv_modify_match_cb,
5790 flow_dv_modify_remove_cb,
5791 flow_dv_modify_clone_cb,
5792 flow_dv_modify_clone_free_cb);
5793 if (unlikely(!modify_cmds))
5795 resource->root = !dev_flow->dv.group;
5796 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5798 return rte_flow_error_set(error, EOVERFLOW,
5799 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5800 "too many modify header items");
5801 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5802 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5805 resource = container_of(entry, typeof(*resource), entry);
5806 dev_flow->handle->dvh.modify_hdr = resource;
5811 * Get DV flow counter by index.
5814 * Pointer to the Ethernet device structure.
5816 * mlx5 flow counter index in the container.
5818 * mlx5 flow counter pool in the container.
5821 * Pointer to the counter, NULL otherwise.
5823 static struct mlx5_flow_counter *
5824 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5826 struct mlx5_flow_counter_pool **ppool)
5828 struct mlx5_priv *priv = dev->data->dev_private;
5829 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5830 struct mlx5_flow_counter_pool *pool;
5832 /* Decrease to original index and clear shared bit. */
5833 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5834 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5835 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5839 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5843 * Check the devx counter belongs to the pool.
5846 * Pointer to the counter pool.
5848 * The counter devx ID.
5851 * True if counter belongs to the pool, false otherwise.
5854 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5856 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5857 MLX5_COUNTERS_PER_POOL;
5859 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5865 * Get a pool by devx counter ID.
5868 * Pointer to the counter management.
5870 * The counter devx ID.
5873 * The counter pool pointer if exists, NULL otherwise,
5875 static struct mlx5_flow_counter_pool *
5876 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5879 struct mlx5_flow_counter_pool *pool = NULL;
5881 rte_spinlock_lock(&cmng->pool_update_sl);
5882 /* Check last used pool. */
5883 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5884 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5885 pool = cmng->pools[cmng->last_pool_idx];
5888 /* ID out of range means no suitable pool in the container. */
5889 if (id > cmng->max_id || id < cmng->min_id)
5892 * Find the pool from the end of the container, since mostly counter
5893 * ID is sequence increasing, and the last pool should be the needed
5898 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5900 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5906 rte_spinlock_unlock(&cmng->pool_update_sl);
5911 * Resize a counter container.
5914 * Pointer to the Ethernet device structure.
5917 * 0 on success, otherwise negative errno value and rte_errno is set.
5920 flow_dv_container_resize(struct rte_eth_dev *dev)
5922 struct mlx5_priv *priv = dev->data->dev_private;
5923 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5924 void *old_pools = cmng->pools;
5925 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5926 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5927 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5934 memcpy(pools, old_pools, cmng->n *
5935 sizeof(struct mlx5_flow_counter_pool *));
5937 cmng->pools = pools;
5939 mlx5_free(old_pools);
5944 * Query a devx flow counter.
5947 * Pointer to the Ethernet device structure.
5948 * @param[in] counter
5949 * Index to the flow counter.
5951 * The statistics value of packets.
5953 * The statistics value of bytes.
5956 * 0 on success, otherwise a negative errno value and rte_errno is set.
5959 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5962 struct mlx5_priv *priv = dev->data->dev_private;
5963 struct mlx5_flow_counter_pool *pool = NULL;
5964 struct mlx5_flow_counter *cnt;
5967 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5969 if (priv->sh->cmng.counter_fallback)
5970 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5971 0, pkts, bytes, 0, NULL, NULL, 0);
5972 rte_spinlock_lock(&pool->sl);
5977 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5978 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5979 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5981 rte_spinlock_unlock(&pool->sl);
5986 * Create and initialize a new counter pool.
5989 * Pointer to the Ethernet device structure.
5991 * The devX counter handle.
5993 * Whether the pool is for counter that was allocated for aging.
5994 * @param[in/out] cont_cur
5995 * Pointer to the container pointer, it will be update in pool resize.
5998 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6000 static struct mlx5_flow_counter_pool *
6001 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6004 struct mlx5_priv *priv = dev->data->dev_private;
6005 struct mlx5_flow_counter_pool *pool;
6006 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6007 bool fallback = priv->sh->cmng.counter_fallback;
6008 uint32_t size = sizeof(*pool);
6010 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6011 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6012 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6018 pool->is_aged = !!age;
6019 pool->query_gen = 0;
6020 pool->min_dcs = dcs;
6021 rte_spinlock_init(&pool->sl);
6022 rte_spinlock_init(&pool->csl);
6023 TAILQ_INIT(&pool->counters[0]);
6024 TAILQ_INIT(&pool->counters[1]);
6025 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6026 rte_spinlock_lock(&cmng->pool_update_sl);
6027 pool->index = cmng->n_valid;
6028 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6030 rte_spinlock_unlock(&cmng->pool_update_sl);
6033 cmng->pools[pool->index] = pool;
6035 if (unlikely(fallback)) {
6036 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6038 if (base < cmng->min_id)
6039 cmng->min_id = base;
6040 if (base > cmng->max_id)
6041 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6042 cmng->last_pool_idx = pool->index;
6044 rte_spinlock_unlock(&cmng->pool_update_sl);
6049 * Prepare a new counter and/or a new counter pool.
6052 * Pointer to the Ethernet device structure.
6053 * @param[out] cnt_free
6054 * Where to put the pointer of a new counter.
6056 * Whether the pool is for counter that was allocated for aging.
6059 * The counter pool pointer and @p cnt_free is set on success,
6060 * NULL otherwise and rte_errno is set.
6062 static struct mlx5_flow_counter_pool *
6063 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6064 struct mlx5_flow_counter **cnt_free,
6067 struct mlx5_priv *priv = dev->data->dev_private;
6068 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6069 struct mlx5_flow_counter_pool *pool;
6070 struct mlx5_counters tmp_tq;
6071 struct mlx5_devx_obj *dcs = NULL;
6072 struct mlx5_flow_counter *cnt;
6073 enum mlx5_counter_type cnt_type =
6074 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6075 bool fallback = priv->sh->cmng.counter_fallback;
6079 /* bulk_bitmap must be 0 for single counter allocation. */
6080 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6083 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6085 pool = flow_dv_pool_create(dev, dcs, age);
6087 mlx5_devx_cmd_destroy(dcs);
6091 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6092 cnt = MLX5_POOL_GET_CNT(pool, i);
6094 cnt->dcs_when_free = dcs;
6098 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6100 rte_errno = ENODATA;
6103 pool = flow_dv_pool_create(dev, dcs, age);
6105 mlx5_devx_cmd_destroy(dcs);
6108 TAILQ_INIT(&tmp_tq);
6109 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6110 cnt = MLX5_POOL_GET_CNT(pool, i);
6112 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6114 rte_spinlock_lock(&cmng->csl[cnt_type]);
6115 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6116 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6117 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6118 (*cnt_free)->pool = pool;
6123 * Allocate a flow counter.
6126 * Pointer to the Ethernet device structure.
6128 * Whether the counter was allocated for aging.
6131 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6134 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6136 struct mlx5_priv *priv = dev->data->dev_private;
6137 struct mlx5_flow_counter_pool *pool = NULL;
6138 struct mlx5_flow_counter *cnt_free = NULL;
6139 bool fallback = priv->sh->cmng.counter_fallback;
6140 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6141 enum mlx5_counter_type cnt_type =
6142 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6145 if (!priv->sh->devx) {
6146 rte_errno = ENOTSUP;
6149 /* Get free counters from container. */
6150 rte_spinlock_lock(&cmng->csl[cnt_type]);
6151 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6153 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6154 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6155 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6157 pool = cnt_free->pool;
6159 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6160 /* Create a DV counter action only in the first time usage. */
6161 if (!cnt_free->action) {
6163 struct mlx5_devx_obj *dcs;
6167 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6168 dcs = pool->min_dcs;
6171 dcs = cnt_free->dcs_when_free;
6173 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6180 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6181 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6182 /* Update the counter reset values. */
6183 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6186 if (!fallback && !priv->sh->cmng.query_thread_on)
6187 /* Start the asynchronous batch query by the host thread. */
6188 mlx5_set_query_alarm(priv->sh);
6190 * When the count action isn't shared (by ID), shared_info field is
6191 * used for indirect action API's refcnt.
6192 * When the counter action is not shared neither by ID nor by indirect
6193 * action API, shared info must be 1.
6195 cnt_free->shared_info.refcnt = 1;
6199 cnt_free->pool = pool;
6201 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6202 rte_spinlock_lock(&cmng->csl[cnt_type]);
6203 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6204 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6210 * Get age param from counter index.
6213 * Pointer to the Ethernet device structure.
6214 * @param[in] counter
6215 * Index to the counter handler.
6218 * The aging parameter specified for the counter index.
6220 static struct mlx5_age_param*
6221 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6224 struct mlx5_flow_counter *cnt;
6225 struct mlx5_flow_counter_pool *pool = NULL;
6227 flow_dv_counter_get_by_idx(dev, counter, &pool);
6228 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6229 cnt = MLX5_POOL_GET_CNT(pool, counter);
6230 return MLX5_CNT_TO_AGE(cnt);
6234 * Remove a flow counter from aged counter list.
6237 * Pointer to the Ethernet device structure.
6238 * @param[in] counter
6239 * Index to the counter handler.
6241 * Pointer to the counter handler.
6244 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6245 uint32_t counter, struct mlx5_flow_counter *cnt)
6247 struct mlx5_age_info *age_info;
6248 struct mlx5_age_param *age_param;
6249 struct mlx5_priv *priv = dev->data->dev_private;
6250 uint16_t expected = AGE_CANDIDATE;
6252 age_info = GET_PORT_AGE_INFO(priv);
6253 age_param = flow_dv_counter_idx_get_age(dev, counter);
6254 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6255 AGE_FREE, false, __ATOMIC_RELAXED,
6256 __ATOMIC_RELAXED)) {
6258 * We need the lock even it is age timeout,
6259 * since counter may still in process.
6261 rte_spinlock_lock(&age_info->aged_sl);
6262 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6263 rte_spinlock_unlock(&age_info->aged_sl);
6264 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6269 * Release a flow counter.
6272 * Pointer to the Ethernet device structure.
6273 * @param[in] counter
6274 * Index to the counter handler.
6277 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6279 struct mlx5_priv *priv = dev->data->dev_private;
6280 struct mlx5_flow_counter_pool *pool = NULL;
6281 struct mlx5_flow_counter *cnt;
6282 enum mlx5_counter_type cnt_type;
6286 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6288 if (pool->is_aged) {
6289 flow_dv_counter_remove_from_age(dev, counter, cnt);
6292 * If the counter action is shared by indirect action API,
6293 * the atomic function reduces its references counter.
6294 * If after the reduction the action is still referenced, the
6295 * function returns here and does not release it.
6296 * When the counter action is not shared by
6297 * indirect action API, shared info is 1 before the reduction,
6298 * so this condition is failed and function doesn't return here.
6300 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6306 * Put the counter back to list to be updated in none fallback mode.
6307 * Currently, we are using two list alternately, while one is in query,
6308 * add the freed counter to the other list based on the pool query_gen
6309 * value. After query finishes, add counter the list to the global
6310 * container counter list. The list changes while query starts. In
6311 * this case, lock will not be needed as query callback and release
6312 * function both operate with the different list.
6314 if (!priv->sh->cmng.counter_fallback) {
6315 rte_spinlock_lock(&pool->csl);
6316 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6317 rte_spinlock_unlock(&pool->csl);
6319 cnt->dcs_when_free = cnt->dcs_when_active;
6320 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6321 MLX5_COUNTER_TYPE_ORIGIN;
6322 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6323 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6325 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6330 * Resize a meter id container.
6333 * Pointer to the Ethernet device structure.
6336 * 0 on success, otherwise negative errno value and rte_errno is set.
6339 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6341 struct mlx5_priv *priv = dev->data->dev_private;
6342 struct mlx5_aso_mtr_pools_mng *pools_mng =
6343 &priv->sh->mtrmng->pools_mng;
6344 void *old_pools = pools_mng->pools;
6345 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6346 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6347 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6354 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6359 memcpy(pools, old_pools, pools_mng->n *
6360 sizeof(struct mlx5_aso_mtr_pool *));
6361 pools_mng->n = resize;
6362 pools_mng->pools = pools;
6364 mlx5_free(old_pools);
6369 * Prepare a new meter and/or a new meter pool.
6372 * Pointer to the Ethernet device structure.
6373 * @param[out] mtr_free
6374 * Where to put the pointer of a new meter.g.
6377 * The meter pool pointer and @mtr_free is set on success,
6378 * NULL otherwise and rte_errno is set.
6380 static struct mlx5_aso_mtr_pool *
6381 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6383 struct mlx5_priv *priv = dev->data->dev_private;
6384 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6385 struct mlx5_aso_mtr_pool *pool = NULL;
6386 struct mlx5_devx_obj *dcs = NULL;
6388 uint32_t log_obj_size;
6390 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6391 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6392 priv->sh->cdev->pdn,
6395 rte_errno = ENODATA;
6398 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6401 claim_zero(mlx5_devx_cmd_destroy(dcs));
6404 pool->devx_obj = dcs;
6405 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6406 pool->index = pools_mng->n_valid;
6407 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6409 claim_zero(mlx5_devx_cmd_destroy(dcs));
6410 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6413 pools_mng->pools[pool->index] = pool;
6414 pools_mng->n_valid++;
6415 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6416 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6417 pool->mtrs[i].offset = i;
6418 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6420 pool->mtrs[0].offset = 0;
6421 *mtr_free = &pool->mtrs[0];
6426 * Release a flow meter into pool.
6429 * Pointer to the Ethernet device structure.
6430 * @param[in] mtr_idx
6431 * Index to aso flow meter.
6434 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6436 struct mlx5_priv *priv = dev->data->dev_private;
6437 struct mlx5_aso_mtr_pools_mng *pools_mng =
6438 &priv->sh->mtrmng->pools_mng;
6439 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6441 MLX5_ASSERT(aso_mtr);
6442 rte_spinlock_lock(&pools_mng->mtrsl);
6443 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6444 aso_mtr->state = ASO_METER_FREE;
6445 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6446 rte_spinlock_unlock(&pools_mng->mtrsl);
6450 * Allocate a aso flow meter.
6453 * Pointer to the Ethernet device structure.
6456 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6459 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6461 struct mlx5_priv *priv = dev->data->dev_private;
6462 struct mlx5_aso_mtr *mtr_free = NULL;
6463 struct mlx5_aso_mtr_pools_mng *pools_mng =
6464 &priv->sh->mtrmng->pools_mng;
6465 struct mlx5_aso_mtr_pool *pool;
6466 uint32_t mtr_idx = 0;
6468 if (!priv->sh->devx) {
6469 rte_errno = ENOTSUP;
6472 /* Allocate the flow meter memory. */
6473 /* Get free meters from management. */
6474 rte_spinlock_lock(&pools_mng->mtrsl);
6475 mtr_free = LIST_FIRST(&pools_mng->meters);
6477 LIST_REMOVE(mtr_free, next);
6478 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6479 rte_spinlock_unlock(&pools_mng->mtrsl);
6482 mtr_free->state = ASO_METER_WAIT;
6483 rte_spinlock_unlock(&pools_mng->mtrsl);
6484 pool = container_of(mtr_free,
6485 struct mlx5_aso_mtr_pool,
6486 mtrs[mtr_free->offset]);
6487 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6488 if (!mtr_free->fm.meter_action) {
6489 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6490 struct rte_flow_error error;
6493 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6494 mtr_free->fm.meter_action =
6495 mlx5_glue->dv_create_flow_action_aso
6496 (priv->sh->rx_domain,
6497 pool->devx_obj->obj,
6499 (1 << MLX5_FLOW_COLOR_GREEN),
6501 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6502 if (!mtr_free->fm.meter_action) {
6503 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6511 * Verify the @p attributes will be correctly understood by the NIC and store
6512 * them in the @p flow if everything is correct.
6515 * Pointer to dev struct.
6516 * @param[in] attributes
6517 * Pointer to flow attributes
6518 * @param[in] external
6519 * This flow rule is created by request external to PMD.
6521 * Pointer to error structure.
6524 * - 0 on success and non root table.
6525 * - 1 on success and root table.
6526 * - a negative errno value otherwise and rte_errno is set.
6529 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6530 const struct mlx5_flow_tunnel *tunnel,
6531 const struct rte_flow_attr *attributes,
6532 const struct flow_grp_info *grp_info,
6533 struct rte_flow_error *error)
6535 struct mlx5_priv *priv = dev->data->dev_private;
6536 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6539 #ifndef HAVE_MLX5DV_DR
6540 RTE_SET_USED(tunnel);
6541 RTE_SET_USED(grp_info);
6542 if (attributes->group)
6543 return rte_flow_error_set(error, ENOTSUP,
6544 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6546 "groups are not supported");
6550 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6555 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6557 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6558 attributes->priority > lowest_priority)
6559 return rte_flow_error_set(error, ENOTSUP,
6560 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6562 "priority out of range");
6563 if (attributes->transfer) {
6564 if (!priv->config.dv_esw_en)
6565 return rte_flow_error_set
6567 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6568 "E-Switch dr is not supported");
6569 if (!(priv->representor || priv->master))
6570 return rte_flow_error_set
6571 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6572 NULL, "E-Switch configuration can only be"
6573 " done by a master or a representor device");
6574 if (attributes->egress)
6575 return rte_flow_error_set
6577 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6578 "egress is not supported");
6580 if (!(attributes->egress ^ attributes->ingress))
6581 return rte_flow_error_set(error, ENOTSUP,
6582 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6583 "must specify exactly one of "
6584 "ingress or egress");
6589 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6590 int64_t pattern_flags, uint64_t l3_flags,
6591 uint64_t l4_flags, uint64_t ip4_flag,
6592 struct rte_flow_error *error)
6594 if (mask->l3_ok && !(pattern_flags & l3_flags))
6595 return rte_flow_error_set(error, EINVAL,
6596 RTE_FLOW_ERROR_TYPE_ITEM,
6597 NULL, "missing L3 protocol");
6599 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6600 return rte_flow_error_set(error, EINVAL,
6601 RTE_FLOW_ERROR_TYPE_ITEM,
6602 NULL, "missing IPv4 protocol");
6604 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6605 return rte_flow_error_set(error, EINVAL,
6606 RTE_FLOW_ERROR_TYPE_ITEM,
6607 NULL, "missing L4 protocol");
6613 flow_dv_validate_item_integrity_post(const struct
6614 rte_flow_item *integrity_items[2],
6615 int64_t pattern_flags,
6616 struct rte_flow_error *error)
6618 const struct rte_flow_item_integrity *mask;
6621 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6622 mask = (typeof(mask))integrity_items[0]->mask;
6623 ret = validate_integrity_bits(mask, pattern_flags,
6624 MLX5_FLOW_LAYER_OUTER_L3,
6625 MLX5_FLOW_LAYER_OUTER_L4,
6626 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6631 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6632 mask = (typeof(mask))integrity_items[1]->mask;
6633 ret = validate_integrity_bits(mask, pattern_flags,
6634 MLX5_FLOW_LAYER_INNER_L3,
6635 MLX5_FLOW_LAYER_INNER_L4,
6636 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6645 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6646 const struct rte_flow_item *integrity_item,
6647 uint64_t pattern_flags, uint64_t *last_item,
6648 const struct rte_flow_item *integrity_items[2],
6649 struct rte_flow_error *error)
6651 struct mlx5_priv *priv = dev->data->dev_private;
6652 const struct rte_flow_item_integrity *mask = (typeof(mask))
6653 integrity_item->mask;
6654 const struct rte_flow_item_integrity *spec = (typeof(spec))
6655 integrity_item->spec;
6657 if (!priv->config.hca_attr.pkt_integrity_match)
6658 return rte_flow_error_set(error, ENOTSUP,
6659 RTE_FLOW_ERROR_TYPE_ITEM,
6661 "packet integrity integrity_item not supported");
6663 return rte_flow_error_set(error, ENOTSUP,
6664 RTE_FLOW_ERROR_TYPE_ITEM,
6666 "no spec for integrity item");
6668 mask = &rte_flow_item_integrity_mask;
6669 if (!mlx5_validate_integrity_item(mask))
6670 return rte_flow_error_set(error, ENOTSUP,
6671 RTE_FLOW_ERROR_TYPE_ITEM,
6673 "unsupported integrity filter");
6674 if (spec->level > 1) {
6675 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6676 return rte_flow_error_set
6678 RTE_FLOW_ERROR_TYPE_ITEM,
6679 NULL, "multiple inner integrity items not supported");
6680 integrity_items[1] = integrity_item;
6681 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6683 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6684 return rte_flow_error_set
6686 RTE_FLOW_ERROR_TYPE_ITEM,
6687 NULL, "multiple outer integrity items not supported");
6688 integrity_items[0] = integrity_item;
6689 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6695 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6696 const struct rte_flow_item *item,
6697 uint64_t item_flags,
6698 uint64_t *last_item,
6700 struct rte_flow_error *error)
6702 const struct rte_flow_item_flex *flow_spec = item->spec;
6703 const struct rte_flow_item_flex *flow_mask = item->mask;
6704 struct mlx5_flex_item *flex;
6707 return rte_flow_error_set(error, EINVAL,
6708 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6709 "flex flow item spec cannot be NULL");
6711 return rte_flow_error_set(error, EINVAL,
6712 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6713 "flex flow item mask cannot be NULL");
6715 return rte_flow_error_set(error, ENOTSUP,
6716 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6717 "flex flow item last not supported");
6718 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6719 return rte_flow_error_set(error, EINVAL,
6720 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6721 "invalid flex flow item handle");
6722 flex = (struct mlx5_flex_item *)flow_spec->handle;
6723 switch (flex->tunnel_mode) {
6724 case FLEX_TUNNEL_MODE_SINGLE:
6726 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6727 rte_flow_error_set(error, EINVAL,
6728 RTE_FLOW_ERROR_TYPE_ITEM,
6729 NULL, "multiple flex items not supported");
6731 case FLEX_TUNNEL_MODE_OUTER:
6733 rte_flow_error_set(error, EINVAL,
6734 RTE_FLOW_ERROR_TYPE_ITEM,
6735 NULL, "inner flex item was not configured");
6736 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6737 rte_flow_error_set(error, ENOTSUP,
6738 RTE_FLOW_ERROR_TYPE_ITEM,
6739 NULL, "multiple flex items not supported");
6741 case FLEX_TUNNEL_MODE_INNER:
6743 rte_flow_error_set(error, EINVAL,
6744 RTE_FLOW_ERROR_TYPE_ITEM,
6745 NULL, "outer flex item was not configured");
6746 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6747 rte_flow_error_set(error, EINVAL,
6748 RTE_FLOW_ERROR_TYPE_ITEM,
6749 NULL, "multiple flex items not supported");
6751 case FLEX_TUNNEL_MODE_MULTI:
6752 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6753 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6754 rte_flow_error_set(error, EINVAL,
6755 RTE_FLOW_ERROR_TYPE_ITEM,
6756 NULL, "multiple flex items not supported");
6759 case FLEX_TUNNEL_MODE_TUNNEL:
6760 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6761 rte_flow_error_set(error, EINVAL,
6762 RTE_FLOW_ERROR_TYPE_ITEM,
6763 NULL, "multiple flex tunnel items not supported");
6766 rte_flow_error_set(error, EINVAL,
6767 RTE_FLOW_ERROR_TYPE_ITEM,
6768 NULL, "invalid flex item configuration");
6770 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6771 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6772 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6777 * Internal validation function. For validating both actions and items.
6780 * Pointer to the rte_eth_dev structure.
6782 * Pointer to the flow attributes.
6784 * Pointer to the list of items.
6785 * @param[in] actions
6786 * Pointer to the list of actions.
6787 * @param[in] external
6788 * This flow rule is created by request external to PMD.
6789 * @param[in] hairpin
6790 * Number of hairpin TX actions, 0 means classic flow.
6792 * Pointer to the error structure.
6795 * 0 on success, a negative errno value otherwise and rte_errno is set.
6798 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6799 const struct rte_flow_item items[],
6800 const struct rte_flow_action actions[],
6801 bool external, int hairpin, struct rte_flow_error *error)
6804 uint64_t action_flags = 0;
6805 uint64_t item_flags = 0;
6806 uint64_t last_item = 0;
6807 uint8_t next_protocol = 0xff;
6808 uint16_t ether_type = 0;
6810 uint8_t item_ipv6_proto = 0;
6811 int fdb_mirror_limit = 0;
6812 int modify_after_mirror = 0;
6813 const struct rte_flow_item *geneve_item = NULL;
6814 const struct rte_flow_item *gre_item = NULL;
6815 const struct rte_flow_item *gtp_item = NULL;
6816 const struct rte_flow_action_raw_decap *decap;
6817 const struct rte_flow_action_raw_encap *encap;
6818 const struct rte_flow_action_rss *rss = NULL;
6819 const struct rte_flow_action_rss *sample_rss = NULL;
6820 const struct rte_flow_action_count *sample_count = NULL;
6821 const struct rte_flow_item_tcp nic_tcp_mask = {
6824 .src_port = RTE_BE16(UINT16_MAX),
6825 .dst_port = RTE_BE16(UINT16_MAX),
6828 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6831 "\xff\xff\xff\xff\xff\xff\xff\xff"
6832 "\xff\xff\xff\xff\xff\xff\xff\xff",
6834 "\xff\xff\xff\xff\xff\xff\xff\xff"
6835 "\xff\xff\xff\xff\xff\xff\xff\xff",
6836 .vtc_flow = RTE_BE32(0xffffffff),
6842 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6846 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6850 .dummy[0] = 0xffffffff,
6853 struct mlx5_priv *priv = dev->data->dev_private;
6854 struct mlx5_dev_config *dev_conf = &priv->config;
6855 uint16_t queue_index = 0xFFFF;
6856 const struct rte_flow_item_vlan *vlan_m = NULL;
6857 uint32_t rw_act_num = 0;
6859 const struct mlx5_flow_tunnel *tunnel;
6860 enum mlx5_tof_rule_type tof_rule_type;
6861 struct flow_grp_info grp_info = {
6862 .external = !!external,
6863 .transfer = !!attr->transfer,
6864 .fdb_def_rule = !!priv->fdb_def_rule,
6865 .std_tbl_fix = true,
6867 const struct rte_eth_hairpin_conf *conf;
6868 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6869 const struct rte_flow_item *port_id_item = NULL;
6870 bool def_policy = false;
6871 uint16_t udp_dport = 0;
6875 tunnel = is_tunnel_offload_active(dev) ?
6876 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6878 if (!priv->config.dv_flow_en)
6879 return rte_flow_error_set
6881 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6882 NULL, "tunnel offload requires DV flow interface");
6883 if (priv->representor)
6884 return rte_flow_error_set
6886 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6887 NULL, "decap not supported for VF representor");
6888 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6889 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6890 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6891 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6892 MLX5_FLOW_ACTION_DECAP;
6893 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6894 (dev, attr, tunnel, tof_rule_type);
6896 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6899 is_root = (uint64_t)ret;
6900 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6901 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6902 int type = items->type;
6904 if (!mlx5_flow_os_item_supported(type))
6905 return rte_flow_error_set(error, ENOTSUP,
6906 RTE_FLOW_ERROR_TYPE_ITEM,
6907 NULL, "item not supported");
6909 case RTE_FLOW_ITEM_TYPE_VOID:
6911 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6912 ret = flow_dv_validate_item_port_id
6913 (dev, items, attr, item_flags, error);
6916 last_item = MLX5_FLOW_ITEM_PORT_ID;
6917 port_id_item = items;
6919 case RTE_FLOW_ITEM_TYPE_ETH:
6920 ret = mlx5_flow_validate_item_eth(items, item_flags,
6924 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6925 MLX5_FLOW_LAYER_OUTER_L2;
6926 if (items->mask != NULL && items->spec != NULL) {
6928 ((const struct rte_flow_item_eth *)
6931 ((const struct rte_flow_item_eth *)
6933 ether_type = rte_be_to_cpu_16(ether_type);
6938 case RTE_FLOW_ITEM_TYPE_VLAN:
6939 ret = flow_dv_validate_item_vlan(items, item_flags,
6943 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6944 MLX5_FLOW_LAYER_OUTER_VLAN;
6945 if (items->mask != NULL && items->spec != NULL) {
6947 ((const struct rte_flow_item_vlan *)
6948 items->spec)->inner_type;
6950 ((const struct rte_flow_item_vlan *)
6951 items->mask)->inner_type;
6952 ether_type = rte_be_to_cpu_16(ether_type);
6956 /* Store outer VLAN mask for of_push_vlan action. */
6958 vlan_m = items->mask;
6960 case RTE_FLOW_ITEM_TYPE_IPV4:
6961 mlx5_flow_tunnel_ip_check(items, next_protocol,
6962 &item_flags, &tunnel);
6963 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6964 last_item, ether_type,
6968 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6969 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6970 if (items->mask != NULL &&
6971 ((const struct rte_flow_item_ipv4 *)
6972 items->mask)->hdr.next_proto_id) {
6974 ((const struct rte_flow_item_ipv4 *)
6975 (items->spec))->hdr.next_proto_id;
6977 ((const struct rte_flow_item_ipv4 *)
6978 (items->mask))->hdr.next_proto_id;
6980 /* Reset for inner layer. */
6981 next_protocol = 0xff;
6984 case RTE_FLOW_ITEM_TYPE_IPV6:
6985 mlx5_flow_tunnel_ip_check(items, next_protocol,
6986 &item_flags, &tunnel);
6987 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6994 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6995 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6996 if (items->mask != NULL &&
6997 ((const struct rte_flow_item_ipv6 *)
6998 items->mask)->hdr.proto) {
7000 ((const struct rte_flow_item_ipv6 *)
7001 items->spec)->hdr.proto;
7003 ((const struct rte_flow_item_ipv6 *)
7004 items->spec)->hdr.proto;
7006 ((const struct rte_flow_item_ipv6 *)
7007 items->mask)->hdr.proto;
7009 /* Reset for inner layer. */
7010 next_protocol = 0xff;
7013 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7014 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7019 last_item = tunnel ?
7020 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7021 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7022 if (items->mask != NULL &&
7023 ((const struct rte_flow_item_ipv6_frag_ext *)
7024 items->mask)->hdr.next_header) {
7026 ((const struct rte_flow_item_ipv6_frag_ext *)
7027 items->spec)->hdr.next_header;
7029 ((const struct rte_flow_item_ipv6_frag_ext *)
7030 items->mask)->hdr.next_header;
7032 /* Reset for inner layer. */
7033 next_protocol = 0xff;
7036 case RTE_FLOW_ITEM_TYPE_TCP:
7037 ret = mlx5_flow_validate_item_tcp
7044 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7045 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7047 case RTE_FLOW_ITEM_TYPE_UDP:
7048 ret = mlx5_flow_validate_item_udp(items, item_flags,
7051 const struct rte_flow_item_udp *spec = items->spec;
7052 const struct rte_flow_item_udp *mask = items->mask;
7054 mask = &rte_flow_item_udp_mask;
7056 udp_dport = rte_be_to_cpu_16
7057 (spec->hdr.dst_port &
7058 mask->hdr.dst_port);
7061 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7062 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7064 case RTE_FLOW_ITEM_TYPE_GRE:
7065 ret = mlx5_flow_validate_item_gre(items, item_flags,
7066 next_protocol, error);
7070 last_item = MLX5_FLOW_LAYER_GRE;
7072 case RTE_FLOW_ITEM_TYPE_NVGRE:
7073 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7078 last_item = MLX5_FLOW_LAYER_NVGRE;
7080 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7081 ret = mlx5_flow_validate_item_gre_key
7082 (items, item_flags, gre_item, error);
7085 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7087 case RTE_FLOW_ITEM_TYPE_VXLAN:
7088 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7093 last_item = MLX5_FLOW_LAYER_VXLAN;
7095 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7096 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7101 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7103 case RTE_FLOW_ITEM_TYPE_GENEVE:
7104 ret = mlx5_flow_validate_item_geneve(items,
7109 geneve_item = items;
7110 last_item = MLX5_FLOW_LAYER_GENEVE;
7112 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7113 ret = mlx5_flow_validate_item_geneve_opt(items,
7120 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7122 case RTE_FLOW_ITEM_TYPE_MPLS:
7123 ret = mlx5_flow_validate_item_mpls(dev, items,
7128 last_item = MLX5_FLOW_LAYER_MPLS;
7131 case RTE_FLOW_ITEM_TYPE_MARK:
7132 ret = flow_dv_validate_item_mark(dev, items, attr,
7136 last_item = MLX5_FLOW_ITEM_MARK;
7138 case RTE_FLOW_ITEM_TYPE_META:
7139 ret = flow_dv_validate_item_meta(dev, items, attr,
7143 last_item = MLX5_FLOW_ITEM_METADATA;
7145 case RTE_FLOW_ITEM_TYPE_ICMP:
7146 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7151 last_item = MLX5_FLOW_LAYER_ICMP;
7153 case RTE_FLOW_ITEM_TYPE_ICMP6:
7154 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7159 item_ipv6_proto = IPPROTO_ICMPV6;
7160 last_item = MLX5_FLOW_LAYER_ICMP6;
7162 case RTE_FLOW_ITEM_TYPE_TAG:
7163 ret = flow_dv_validate_item_tag(dev, items,
7167 last_item = MLX5_FLOW_ITEM_TAG;
7169 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7170 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7172 case RTE_FLOW_ITEM_TYPE_GTP:
7173 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7178 last_item = MLX5_FLOW_LAYER_GTP;
7180 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7181 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7186 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7188 case RTE_FLOW_ITEM_TYPE_ECPRI:
7189 /* Capacity will be checked in the translate stage. */
7190 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7197 last_item = MLX5_FLOW_LAYER_ECPRI;
7199 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7200 ret = flow_dv_validate_item_integrity(dev, items,
7208 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7209 ret = flow_dv_validate_item_aso_ct(dev, items,
7210 &item_flags, error);
7214 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7215 /* tunnel offload item was processed before
7216 * list it here as a supported type
7219 case RTE_FLOW_ITEM_TYPE_FLEX:
7220 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7222 tunnel != 0, error);
7227 return rte_flow_error_set(error, ENOTSUP,
7228 RTE_FLOW_ERROR_TYPE_ITEM,
7229 NULL, "item not supported");
7231 item_flags |= last_item;
7233 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7234 ret = flow_dv_validate_item_integrity_post(integrity_items,
7239 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7240 int type = actions->type;
7241 bool shared_count = false;
7243 if (!mlx5_flow_os_action_supported(type))
7244 return rte_flow_error_set(error, ENOTSUP,
7245 RTE_FLOW_ERROR_TYPE_ACTION,
7247 "action not supported");
7248 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7249 return rte_flow_error_set(error, ENOTSUP,
7250 RTE_FLOW_ERROR_TYPE_ACTION,
7251 actions, "too many actions");
7253 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7254 return rte_flow_error_set(error, ENOTSUP,
7255 RTE_FLOW_ERROR_TYPE_ACTION,
7256 NULL, "meter action with policy "
7257 "must be the last action");
7259 case RTE_FLOW_ACTION_TYPE_VOID:
7261 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7262 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7263 ret = flow_dv_validate_action_port_id(dev,
7270 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7273 case RTE_FLOW_ACTION_TYPE_FLAG:
7274 ret = flow_dv_validate_action_flag(dev, action_flags,
7278 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7279 /* Count all modify-header actions as one. */
7280 if (!(action_flags &
7281 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7283 action_flags |= MLX5_FLOW_ACTION_FLAG |
7284 MLX5_FLOW_ACTION_MARK_EXT;
7285 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7286 modify_after_mirror = 1;
7289 action_flags |= MLX5_FLOW_ACTION_FLAG;
7292 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7294 case RTE_FLOW_ACTION_TYPE_MARK:
7295 ret = flow_dv_validate_action_mark(dev, actions,
7300 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7301 /* Count all modify-header actions as one. */
7302 if (!(action_flags &
7303 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7305 action_flags |= MLX5_FLOW_ACTION_MARK |
7306 MLX5_FLOW_ACTION_MARK_EXT;
7307 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7308 modify_after_mirror = 1;
7310 action_flags |= MLX5_FLOW_ACTION_MARK;
7313 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7315 case RTE_FLOW_ACTION_TYPE_SET_META:
7316 ret = flow_dv_validate_action_set_meta(dev, actions,
7321 /* Count all modify-header actions as one action. */
7322 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7324 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7325 modify_after_mirror = 1;
7326 action_flags |= MLX5_FLOW_ACTION_SET_META;
7327 rw_act_num += MLX5_ACT_NUM_SET_META;
7329 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7330 ret = flow_dv_validate_action_set_tag(dev, actions,
7335 /* Count all modify-header actions as one action. */
7336 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7338 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7339 modify_after_mirror = 1;
7340 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7341 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7343 case RTE_FLOW_ACTION_TYPE_DROP:
7344 ret = mlx5_flow_validate_action_drop(action_flags,
7348 action_flags |= MLX5_FLOW_ACTION_DROP;
7351 case RTE_FLOW_ACTION_TYPE_QUEUE:
7352 ret = mlx5_flow_validate_action_queue(actions,
7357 queue_index = ((const struct rte_flow_action_queue *)
7358 (actions->conf))->index;
7359 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7362 case RTE_FLOW_ACTION_TYPE_RSS:
7363 rss = actions->conf;
7364 ret = mlx5_flow_validate_action_rss(actions,
7370 if (rss && sample_rss &&
7371 (sample_rss->level != rss->level ||
7372 sample_rss->types != rss->types))
7373 return rte_flow_error_set(error, ENOTSUP,
7374 RTE_FLOW_ERROR_TYPE_ACTION,
7376 "Can't use the different RSS types "
7377 "or level in the same flow");
7378 if (rss != NULL && rss->queue_num)
7379 queue_index = rss->queue[0];
7380 action_flags |= MLX5_FLOW_ACTION_RSS;
7383 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7385 mlx5_flow_validate_action_default_miss(action_flags,
7389 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7392 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7393 shared_count = true;
7395 case RTE_FLOW_ACTION_TYPE_COUNT:
7396 ret = flow_dv_validate_action_count(dev, shared_count,
7401 action_flags |= MLX5_FLOW_ACTION_COUNT;
7404 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7405 if (flow_dv_validate_action_pop_vlan(dev,
7411 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7412 modify_after_mirror = 1;
7413 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7416 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7417 ret = flow_dv_validate_action_push_vlan(dev,
7424 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7425 modify_after_mirror = 1;
7426 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7429 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7430 ret = flow_dv_validate_action_set_vlan_pcp
7431 (action_flags, actions, error);
7434 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7435 modify_after_mirror = 1;
7436 /* Count PCP with push_vlan command. */
7437 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7439 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7440 ret = flow_dv_validate_action_set_vlan_vid
7441 (item_flags, action_flags,
7445 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7446 modify_after_mirror = 1;
7447 /* Count VID with push_vlan command. */
7448 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7449 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7451 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7452 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7453 ret = flow_dv_validate_action_l2_encap(dev,
7459 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7462 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7463 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7464 ret = flow_dv_validate_action_decap(dev, action_flags,
7465 actions, item_flags,
7469 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7470 modify_after_mirror = 1;
7471 action_flags |= MLX5_FLOW_ACTION_DECAP;
7474 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7475 ret = flow_dv_validate_action_raw_encap_decap
7476 (dev, NULL, actions->conf, attr, &action_flags,
7477 &actions_n, actions, item_flags, error);
7481 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7482 decap = actions->conf;
7483 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7485 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7489 encap = actions->conf;
7491 ret = flow_dv_validate_action_raw_encap_decap
7493 decap ? decap : &empty_decap, encap,
7494 attr, &action_flags, &actions_n,
7495 actions, item_flags, error);
7498 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7499 (action_flags & MLX5_FLOW_ACTION_DECAP))
7500 modify_after_mirror = 1;
7502 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7503 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7504 ret = flow_dv_validate_action_modify_mac(action_flags,
7510 /* Count all modify-header actions as one action. */
7511 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7513 action_flags |= actions->type ==
7514 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7515 MLX5_FLOW_ACTION_SET_MAC_SRC :
7516 MLX5_FLOW_ACTION_SET_MAC_DST;
7517 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7518 modify_after_mirror = 1;
7520 * Even if the source and destination MAC addresses have
7521 * overlap in the header with 4B alignment, the convert
7522 * function will handle them separately and 4 SW actions
7523 * will be created. And 2 actions will be added each
7524 * time no matter how many bytes of address will be set.
7526 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7528 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7529 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7530 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7536 /* Count all modify-header actions as one action. */
7537 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7539 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7540 modify_after_mirror = 1;
7541 action_flags |= actions->type ==
7542 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7543 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7544 MLX5_FLOW_ACTION_SET_IPV4_DST;
7545 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7547 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7548 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7549 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7555 if (item_ipv6_proto == IPPROTO_ICMPV6)
7556 return rte_flow_error_set(error, ENOTSUP,
7557 RTE_FLOW_ERROR_TYPE_ACTION,
7559 "Can't change header "
7560 "with ICMPv6 proto");
7561 /* Count all modify-header actions as one action. */
7562 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7564 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7565 modify_after_mirror = 1;
7566 action_flags |= actions->type ==
7567 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7568 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7569 MLX5_FLOW_ACTION_SET_IPV6_DST;
7570 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7572 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7573 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7574 ret = flow_dv_validate_action_modify_tp(action_flags,
7580 /* Count all modify-header actions as one action. */
7581 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7583 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7584 modify_after_mirror = 1;
7585 action_flags |= actions->type ==
7586 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7587 MLX5_FLOW_ACTION_SET_TP_SRC :
7588 MLX5_FLOW_ACTION_SET_TP_DST;
7589 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7591 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7592 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7593 ret = flow_dv_validate_action_modify_ttl(action_flags,
7599 /* Count all modify-header actions as one action. */
7600 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7602 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7603 modify_after_mirror = 1;
7604 action_flags |= actions->type ==
7605 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7606 MLX5_FLOW_ACTION_SET_TTL :
7607 MLX5_FLOW_ACTION_DEC_TTL;
7608 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7610 case RTE_FLOW_ACTION_TYPE_JUMP:
7611 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7617 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7619 return rte_flow_error_set(error, EINVAL,
7620 RTE_FLOW_ERROR_TYPE_ACTION,
7622 "sample and jump action combination is not supported");
7624 action_flags |= MLX5_FLOW_ACTION_JUMP;
7626 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7627 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7628 ret = flow_dv_validate_action_modify_tcp_seq
7635 /* Count all modify-header actions as one action. */
7636 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7638 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7639 modify_after_mirror = 1;
7640 action_flags |= actions->type ==
7641 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7642 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7643 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7644 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7646 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7647 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7648 ret = flow_dv_validate_action_modify_tcp_ack
7655 /* Count all modify-header actions as one action. */
7656 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7658 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7659 modify_after_mirror = 1;
7660 action_flags |= actions->type ==
7661 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7662 MLX5_FLOW_ACTION_INC_TCP_ACK :
7663 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7664 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7666 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7668 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7669 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7670 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7672 case RTE_FLOW_ACTION_TYPE_METER:
7673 ret = mlx5_flow_validate_action_meter(dev,
7681 action_flags |= MLX5_FLOW_ACTION_METER;
7684 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7686 /* Meter action will add one more TAG action. */
7687 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7689 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7690 if (!attr->transfer && !attr->group)
7691 return rte_flow_error_set(error, ENOTSUP,
7692 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7694 "Shared ASO age action is not supported for group 0");
7695 if (action_flags & MLX5_FLOW_ACTION_AGE)
7696 return rte_flow_error_set
7698 RTE_FLOW_ERROR_TYPE_ACTION,
7700 "duplicate age actions set");
7701 action_flags |= MLX5_FLOW_ACTION_AGE;
7704 case RTE_FLOW_ACTION_TYPE_AGE:
7705 ret = flow_dv_validate_action_age(action_flags,
7711 * Validate the regular AGE action (using counter)
7712 * mutual exclusion with share counter actions.
7714 if (!priv->sh->flow_hit_aso_en) {
7716 return rte_flow_error_set
7718 RTE_FLOW_ERROR_TYPE_ACTION,
7720 "old age and shared count combination is not supported");
7722 return rte_flow_error_set
7724 RTE_FLOW_ERROR_TYPE_ACTION,
7726 "old age action and count must be in the same sub flow");
7728 action_flags |= MLX5_FLOW_ACTION_AGE;
7731 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7732 ret = flow_dv_validate_action_modify_ipv4_dscp
7739 /* Count all modify-header actions as one action. */
7740 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7742 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7743 modify_after_mirror = 1;
7744 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7745 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7747 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7748 ret = flow_dv_validate_action_modify_ipv6_dscp
7755 /* Count all modify-header actions as one action. */
7756 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7758 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7759 modify_after_mirror = 1;
7760 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7761 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7763 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7764 ret = flow_dv_validate_action_sample(&action_flags,
7773 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7776 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7777 ret = flow_dv_validate_action_modify_field(dev,
7784 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7785 modify_after_mirror = 1;
7786 /* Count all modify-header actions as one action. */
7787 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7789 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7792 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7793 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7798 action_flags |= MLX5_FLOW_ACTION_CT;
7800 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7801 /* tunnel offload action was processed before
7802 * list it here as a supported type
7806 return rte_flow_error_set(error, ENOTSUP,
7807 RTE_FLOW_ERROR_TYPE_ACTION,
7809 "action not supported");
7813 * Validate actions in flow rules
7814 * - Explicit decap action is prohibited by the tunnel offload API.
7815 * - Drop action in tunnel steer rule is prohibited by the API.
7816 * - Application cannot use MARK action because it's value can mask
7817 * tunnel default miss nitification.
7818 * - JUMP in tunnel match rule has no support in current PMD
7820 * - TAG & META are reserved for future uses.
7822 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7823 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7824 MLX5_FLOW_ACTION_MARK |
7825 MLX5_FLOW_ACTION_SET_TAG |
7826 MLX5_FLOW_ACTION_SET_META |
7827 MLX5_FLOW_ACTION_DROP;
7829 if (action_flags & bad_actions_mask)
7830 return rte_flow_error_set
7832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7833 "Invalid RTE action in tunnel "
7835 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7836 return rte_flow_error_set
7838 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7839 "tunnel set decap rule must terminate "
7842 return rte_flow_error_set
7844 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7845 "tunnel flows for ingress traffic only");
7847 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7848 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7849 MLX5_FLOW_ACTION_MARK |
7850 MLX5_FLOW_ACTION_SET_TAG |
7851 MLX5_FLOW_ACTION_SET_META;
7853 if (action_flags & bad_actions_mask)
7854 return rte_flow_error_set
7856 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7857 "Invalid RTE action in tunnel "
7861 * Validate the drop action mutual exclusion with other actions.
7862 * Drop action is mutually-exclusive with any other action, except for
7864 * Drop action compatibility with tunnel offload was already validated.
7866 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7867 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7868 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7869 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7870 return rte_flow_error_set(error, EINVAL,
7871 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7872 "Drop action is mutually-exclusive "
7873 "with any other action, except for "
7875 /* Eswitch has few restrictions on using items and actions */
7876 if (attr->transfer) {
7877 if (!mlx5_flow_ext_mreg_supported(dev) &&
7878 action_flags & MLX5_FLOW_ACTION_FLAG)
7879 return rte_flow_error_set(error, ENOTSUP,
7880 RTE_FLOW_ERROR_TYPE_ACTION,
7882 "unsupported action FLAG");
7883 if (!mlx5_flow_ext_mreg_supported(dev) &&
7884 action_flags & MLX5_FLOW_ACTION_MARK)
7885 return rte_flow_error_set(error, ENOTSUP,
7886 RTE_FLOW_ERROR_TYPE_ACTION,
7888 "unsupported action MARK");
7889 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7890 return rte_flow_error_set(error, ENOTSUP,
7891 RTE_FLOW_ERROR_TYPE_ACTION,
7893 "unsupported action QUEUE");
7894 if (action_flags & MLX5_FLOW_ACTION_RSS)
7895 return rte_flow_error_set(error, ENOTSUP,
7896 RTE_FLOW_ERROR_TYPE_ACTION,
7898 "unsupported action RSS");
7899 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7900 return rte_flow_error_set(error, EINVAL,
7901 RTE_FLOW_ERROR_TYPE_ACTION,
7903 "no fate action is found");
7905 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7906 return rte_flow_error_set(error, EINVAL,
7907 RTE_FLOW_ERROR_TYPE_ACTION,
7909 "no fate action is found");
7912 * Continue validation for Xcap and VLAN actions.
7913 * If hairpin is working in explicit TX rule mode, there is no actions
7914 * splitting and the validation of hairpin ingress flow should be the
7915 * same as other standard flows.
7917 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7918 MLX5_FLOW_VLAN_ACTIONS)) &&
7919 (queue_index == 0xFFFF ||
7920 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7921 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7922 conf->tx_explicit != 0))) {
7923 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7924 MLX5_FLOW_XCAP_ACTIONS)
7925 return rte_flow_error_set(error, ENOTSUP,
7926 RTE_FLOW_ERROR_TYPE_ACTION,
7927 NULL, "encap and decap "
7928 "combination aren't supported");
7929 if (!attr->transfer && attr->ingress) {
7930 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7931 return rte_flow_error_set
7933 RTE_FLOW_ERROR_TYPE_ACTION,
7934 NULL, "encap is not supported"
7935 " for ingress traffic");
7936 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7937 return rte_flow_error_set
7939 RTE_FLOW_ERROR_TYPE_ACTION,
7940 NULL, "push VLAN action not "
7941 "supported for ingress");
7942 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7943 MLX5_FLOW_VLAN_ACTIONS)
7944 return rte_flow_error_set
7946 RTE_FLOW_ERROR_TYPE_ACTION,
7947 NULL, "no support for "
7948 "multiple VLAN actions");
7951 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7952 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7953 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7955 return rte_flow_error_set
7957 RTE_FLOW_ERROR_TYPE_ACTION,
7958 NULL, "fate action not supported for "
7959 "meter with policy");
7961 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7962 return rte_flow_error_set
7964 RTE_FLOW_ERROR_TYPE_ACTION,
7965 NULL, "modify header action in egress "
7966 "cannot be done before meter action");
7967 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7968 return rte_flow_error_set
7970 RTE_FLOW_ERROR_TYPE_ACTION,
7971 NULL, "encap action in egress "
7972 "cannot be done before meter action");
7973 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7974 return rte_flow_error_set
7976 RTE_FLOW_ERROR_TYPE_ACTION,
7977 NULL, "push vlan action in egress "
7978 "cannot be done before meter action");
7982 * Hairpin flow will add one more TAG action in TX implicit mode.
7983 * In TX explicit mode, there will be no hairpin flow ID.
7986 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7987 /* extra metadata enabled: one more TAG action will be add. */
7988 if (dev_conf->dv_flow_en &&
7989 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7990 mlx5_flow_ext_mreg_supported(dev))
7991 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7993 flow_dv_modify_hdr_action_max(dev, is_root)) {
7994 return rte_flow_error_set(error, ENOTSUP,
7995 RTE_FLOW_ERROR_TYPE_ACTION,
7996 NULL, "too many header modify"
7997 " actions to support");
7999 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8000 if (fdb_mirror_limit && modify_after_mirror)
8001 return rte_flow_error_set(error, EINVAL,
8002 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8003 "sample before modify action is not supported");
8008 * Internal preparation function. Allocates the DV flow size,
8009 * this size is constant.
8012 * Pointer to the rte_eth_dev structure.
8014 * Pointer to the flow attributes.
8016 * Pointer to the list of items.
8017 * @param[in] actions
8018 * Pointer to the list of actions.
8020 * Pointer to the error structure.
8023 * Pointer to mlx5_flow object on success,
8024 * otherwise NULL and rte_errno is set.
8026 static struct mlx5_flow *
8027 flow_dv_prepare(struct rte_eth_dev *dev,
8028 const struct rte_flow_attr *attr __rte_unused,
8029 const struct rte_flow_item items[] __rte_unused,
8030 const struct rte_flow_action actions[] __rte_unused,
8031 struct rte_flow_error *error)
8033 uint32_t handle_idx = 0;
8034 struct mlx5_flow *dev_flow;
8035 struct mlx5_flow_handle *dev_handle;
8036 struct mlx5_priv *priv = dev->data->dev_private;
8037 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8040 wks->skip_matcher_reg = 0;
8042 wks->final_policy = NULL;
8043 /* In case of corrupting the memory. */
8044 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8045 rte_flow_error_set(error, ENOSPC,
8046 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8047 "not free temporary device flow");
8050 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8053 rte_flow_error_set(error, ENOMEM,
8054 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8055 "not enough memory to create flow handle");
8058 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8059 dev_flow = &wks->flows[wks->flow_idx++];
8060 memset(dev_flow, 0, sizeof(*dev_flow));
8061 dev_flow->handle = dev_handle;
8062 dev_flow->handle_idx = handle_idx;
8063 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8064 dev_flow->ingress = attr->ingress;
8065 dev_flow->dv.transfer = attr->transfer;
8069 #ifdef RTE_LIBRTE_MLX5_DEBUG
8071 * Sanity check for match mask and value. Similar to check_valid_spec() in
8072 * kernel driver. If unmasked bit is present in value, it returns failure.
8075 * pointer to match mask buffer.
8076 * @param match_value
8077 * pointer to match value buffer.
8080 * 0 if valid, -EINVAL otherwise.
8083 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8085 uint8_t *m = match_mask;
8086 uint8_t *v = match_value;
8089 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8092 "match_value differs from match_criteria"
8093 " %p[%u] != %p[%u]",
8094 match_value, i, match_mask, i);
8103 * Add match of ip_version.
8107 * @param[in] headers_v
8108 * Values header pointer.
8109 * @param[in] headers_m
8110 * Masks header pointer.
8111 * @param[in] ip_version
8112 * The IP version to set.
8115 flow_dv_set_match_ip_version(uint32_t group,
8121 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8123 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8125 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8127 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8131 * Add Ethernet item to matcher and to the value.
8133 * @param[in, out] matcher
8135 * @param[in, out] key
8136 * Flow matcher value.
8138 * Flow pattern to translate.
8140 * Item is inner pattern.
8143 flow_dv_translate_item_eth(void *matcher, void *key,
8144 const struct rte_flow_item *item, int inner,
8147 const struct rte_flow_item_eth *eth_m = item->mask;
8148 const struct rte_flow_item_eth *eth_v = item->spec;
8149 const struct rte_flow_item_eth nic_mask = {
8150 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8151 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8152 .type = RTE_BE16(0xffff),
8165 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8167 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8169 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8171 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8173 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8174 ð_m->dst, sizeof(eth_m->dst));
8175 /* The value must be in the range of the mask. */
8176 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8177 for (i = 0; i < sizeof(eth_m->dst); ++i)
8178 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8179 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8180 ð_m->src, sizeof(eth_m->src));
8181 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8182 /* The value must be in the range of the mask. */
8183 for (i = 0; i < sizeof(eth_m->dst); ++i)
8184 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8186 * HW supports match on one Ethertype, the Ethertype following the last
8187 * VLAN tag of the packet (see PRM).
8188 * Set match on ethertype only if ETH header is not followed by VLAN.
8189 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8190 * ethertype, and use ip_version field instead.
8191 * eCPRI over Ether layer will use type value 0xAEFE.
8193 if (eth_m->type == 0xFFFF) {
8194 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8195 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8196 switch (eth_v->type) {
8197 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8198 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8200 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8201 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8202 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8204 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8205 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8207 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8208 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8214 if (eth_m->has_vlan) {
8215 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8216 if (eth_v->has_vlan) {
8218 * Here, when also has_more_vlan field in VLAN item is
8219 * not set, only single-tagged packets will be matched.
8221 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8225 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8226 rte_be_to_cpu_16(eth_m->type));
8227 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8228 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8232 * Add VLAN item to matcher and to the value.
8234 * @param[in, out] dev_flow
8236 * @param[in, out] matcher
8238 * @param[in, out] key
8239 * Flow matcher value.
8241 * Flow pattern to translate.
8243 * Item is inner pattern.
8246 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8247 void *matcher, void *key,
8248 const struct rte_flow_item *item,
8249 int inner, uint32_t group)
8251 const struct rte_flow_item_vlan *vlan_m = item->mask;
8252 const struct rte_flow_item_vlan *vlan_v = item->spec;
8259 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8261 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8263 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8265 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8267 * This is workaround, masks are not supported,
8268 * and pre-validated.
8271 dev_flow->handle->vf_vlan.tag =
8272 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8275 * When VLAN item exists in flow, mark packet as tagged,
8276 * even if TCI is not specified.
8278 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8279 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8280 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8285 vlan_m = &rte_flow_item_vlan_mask;
8286 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8287 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8288 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8289 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8290 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8291 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8292 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8293 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8295 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8296 * ethertype, and use ip_version field instead.
8298 if (vlan_m->inner_type == 0xFFFF) {
8299 switch (vlan_v->inner_type) {
8300 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8301 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8302 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8303 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8305 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8306 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8308 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8309 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8315 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8316 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8317 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8318 /* Only one vlan_tag bit can be set. */
8319 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8322 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8323 rte_be_to_cpu_16(vlan_m->inner_type));
8324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8325 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8329 * Add IPV4 item to matcher and to the value.
8331 * @param[in, out] matcher
8333 * @param[in, out] key
8334 * Flow matcher value.
8336 * Flow pattern to translate.
8338 * Item is inner pattern.
8340 * The group to insert the rule.
8343 flow_dv_translate_item_ipv4(void *matcher, void *key,
8344 const struct rte_flow_item *item,
8345 int inner, uint32_t group)
8347 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8348 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8349 const struct rte_flow_item_ipv4 nic_mask = {
8351 .src_addr = RTE_BE32(0xffffffff),
8352 .dst_addr = RTE_BE32(0xffffffff),
8353 .type_of_service = 0xff,
8354 .next_proto_id = 0xff,
8355 .time_to_live = 0xff,
8362 uint8_t tos, ihl_m, ihl_v;
8365 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8367 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8369 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8371 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8373 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8378 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8379 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8380 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8381 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8382 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8383 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8384 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8385 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8386 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8387 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8388 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8389 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8390 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8391 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8392 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8393 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8394 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8395 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8396 ipv4_m->hdr.type_of_service);
8397 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8398 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8399 ipv4_m->hdr.type_of_service >> 2);
8400 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8401 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8402 ipv4_m->hdr.next_proto_id);
8403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8404 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8405 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8406 ipv4_m->hdr.time_to_live);
8407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8408 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8409 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8410 !!(ipv4_m->hdr.fragment_offset));
8411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8412 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8416 * Add IPV6 item to matcher and to the value.
8418 * @param[in, out] matcher
8420 * @param[in, out] key
8421 * Flow matcher value.
8423 * Flow pattern to translate.
8425 * Item is inner pattern.
8427 * The group to insert the rule.
8430 flow_dv_translate_item_ipv6(void *matcher, void *key,
8431 const struct rte_flow_item *item,
8432 int inner, uint32_t group)
8434 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8435 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8436 const struct rte_flow_item_ipv6 nic_mask = {
8439 "\xff\xff\xff\xff\xff\xff\xff\xff"
8440 "\xff\xff\xff\xff\xff\xff\xff\xff",
8442 "\xff\xff\xff\xff\xff\xff\xff\xff"
8443 "\xff\xff\xff\xff\xff\xff\xff\xff",
8444 .vtc_flow = RTE_BE32(0xffffffff),
8451 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8452 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8461 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8463 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8465 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8467 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8469 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8474 size = sizeof(ipv6_m->hdr.dst_addr);
8475 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8476 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8477 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8478 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8479 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8480 for (i = 0; i < size; ++i)
8481 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8482 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8483 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8484 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8485 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8486 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8487 for (i = 0; i < size; ++i)
8488 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8490 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8491 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8492 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8498 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8500 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8503 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8505 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8509 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8512 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8514 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8515 ipv6_m->hdr.hop_limits);
8516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8517 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8518 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8519 !!(ipv6_m->has_frag_ext));
8520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8521 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8525 * Add IPV6 fragment extension item to matcher and to the value.
8527 * @param[in, out] matcher
8529 * @param[in, out] key
8530 * Flow matcher value.
8532 * Flow pattern to translate.
8534 * Item is inner pattern.
8537 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8538 const struct rte_flow_item *item,
8541 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8542 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8543 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8545 .next_header = 0xff,
8546 .frag_data = RTE_BE16(0xffff),
8553 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8555 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8557 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8559 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8561 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8562 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8563 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8564 if (!ipv6_frag_ext_v)
8566 if (!ipv6_frag_ext_m)
8567 ipv6_frag_ext_m = &nic_mask;
8568 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8569 ipv6_frag_ext_m->hdr.next_header);
8570 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8571 ipv6_frag_ext_v->hdr.next_header &
8572 ipv6_frag_ext_m->hdr.next_header);
8576 * Add TCP item to matcher and to the value.
8578 * @param[in, out] matcher
8580 * @param[in, out] key
8581 * Flow matcher value.
8583 * Flow pattern to translate.
8585 * Item is inner pattern.
8588 flow_dv_translate_item_tcp(void *matcher, void *key,
8589 const struct rte_flow_item *item,
8592 const struct rte_flow_item_tcp *tcp_m = item->mask;
8593 const struct rte_flow_item_tcp *tcp_v = item->spec;
8598 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8600 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8602 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8604 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8606 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8607 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8611 tcp_m = &rte_flow_item_tcp_mask;
8612 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8613 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8614 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8615 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8616 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8617 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8618 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8619 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8621 tcp_m->hdr.tcp_flags);
8622 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8623 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8627 * Add UDP item to matcher and to the value.
8629 * @param[in, out] matcher
8631 * @param[in, out] key
8632 * Flow matcher value.
8634 * Flow pattern to translate.
8636 * Item is inner pattern.
8639 flow_dv_translate_item_udp(void *matcher, void *key,
8640 const struct rte_flow_item *item,
8643 const struct rte_flow_item_udp *udp_m = item->mask;
8644 const struct rte_flow_item_udp *udp_v = item->spec;
8649 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8651 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8653 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8655 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8657 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8662 udp_m = &rte_flow_item_udp_mask;
8663 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8664 rte_be_to_cpu_16(udp_m->hdr.src_port));
8665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8666 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8667 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8668 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8670 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8674 * Add GRE optional Key item to matcher and to the value.
8676 * @param[in, out] matcher
8678 * @param[in, out] key
8679 * Flow matcher value.
8681 * Flow pattern to translate.
8683 * Item is inner pattern.
8686 flow_dv_translate_item_gre_key(void *matcher, void *key,
8687 const struct rte_flow_item *item)
8689 const rte_be32_t *key_m = item->mask;
8690 const rte_be32_t *key_v = item->spec;
8691 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8692 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8693 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8695 /* GRE K bit must be on and should already be validated */
8696 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8697 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8701 key_m = &gre_key_default_mask;
8702 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8703 rte_be_to_cpu_32(*key_m) >> 8);
8704 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8705 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8706 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8707 rte_be_to_cpu_32(*key_m) & 0xFF);
8708 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8709 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8713 * Add GRE item to matcher and to the value.
8715 * @param[in, out] matcher
8717 * @param[in, out] key
8718 * Flow matcher value.
8720 * Flow pattern to translate.
8722 * Item is inner pattern.
8725 flow_dv_translate_item_gre(void *matcher, void *key,
8726 const struct rte_flow_item *item,
8729 const struct rte_flow_item_gre *gre_m = item->mask;
8730 const struct rte_flow_item_gre *gre_v = item->spec;
8733 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8734 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8741 uint16_t s_present:1;
8742 uint16_t k_present:1;
8743 uint16_t rsvd_bit1:1;
8744 uint16_t c_present:1;
8748 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8751 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8753 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8755 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8757 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8759 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8760 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8764 gre_m = &rte_flow_item_gre_mask;
8765 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8766 rte_be_to_cpu_16(gre_m->protocol));
8767 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8768 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8769 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8770 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8771 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8772 gre_crks_rsvd0_ver_m.c_present);
8773 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8774 gre_crks_rsvd0_ver_v.c_present &
8775 gre_crks_rsvd0_ver_m.c_present);
8776 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8777 gre_crks_rsvd0_ver_m.k_present);
8778 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8779 gre_crks_rsvd0_ver_v.k_present &
8780 gre_crks_rsvd0_ver_m.k_present);
8781 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8782 gre_crks_rsvd0_ver_m.s_present);
8783 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8784 gre_crks_rsvd0_ver_v.s_present &
8785 gre_crks_rsvd0_ver_m.s_present);
8789 * Add NVGRE item to matcher and to the value.
8791 * @param[in, out] matcher
8793 * @param[in, out] key
8794 * Flow matcher value.
8796 * Flow pattern to translate.
8798 * Item is inner pattern.
8801 flow_dv_translate_item_nvgre(void *matcher, void *key,
8802 const struct rte_flow_item *item,
8805 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8806 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8807 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8808 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8809 const char *tni_flow_id_m;
8810 const char *tni_flow_id_v;
8816 /* For NVGRE, GRE header fields must be set with defined values. */
8817 const struct rte_flow_item_gre gre_spec = {
8818 .c_rsvd0_ver = RTE_BE16(0x2000),
8819 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8821 const struct rte_flow_item_gre gre_mask = {
8822 .c_rsvd0_ver = RTE_BE16(0xB000),
8823 .protocol = RTE_BE16(UINT16_MAX),
8825 const struct rte_flow_item gre_item = {
8830 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8834 nvgre_m = &rte_flow_item_nvgre_mask;
8835 tni_flow_id_m = (const char *)nvgre_m->tni;
8836 tni_flow_id_v = (const char *)nvgre_v->tni;
8837 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8838 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8839 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8840 memcpy(gre_key_m, tni_flow_id_m, size);
8841 for (i = 0; i < size; ++i)
8842 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8846 * Add VXLAN item to matcher and to the value.
8849 * Pointer to the Ethernet device structure.
8851 * Flow rule attributes.
8852 * @param[in, out] matcher
8854 * @param[in, out] key
8855 * Flow matcher value.
8857 * Flow pattern to translate.
8859 * Item is inner pattern.
8862 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8863 const struct rte_flow_attr *attr,
8864 void *matcher, void *key,
8865 const struct rte_flow_item *item,
8868 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8869 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8874 uint32_t *tunnel_header_v;
8875 uint32_t *tunnel_header_m;
8877 struct mlx5_priv *priv = dev->data->dev_private;
8878 const struct rte_flow_item_vxlan nic_mask = {
8879 .vni = "\xff\xff\xff",
8884 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8886 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8888 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8890 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8892 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8893 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8894 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8895 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8896 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8898 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8902 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8903 (attr->group && !priv->sh->misc5_cap))
8904 vxlan_m = &rte_flow_item_vxlan_mask;
8906 vxlan_m = &nic_mask;
8908 if ((priv->sh->steering_format_version ==
8909 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8910 dport != MLX5_UDP_PORT_VXLAN) ||
8911 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8912 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8919 misc_m = MLX5_ADDR_OF(fte_match_param,
8920 matcher, misc_parameters);
8921 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8922 size = sizeof(vxlan_m->vni);
8923 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8924 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8925 memcpy(vni_m, vxlan_m->vni, size);
8926 for (i = 0; i < size; ++i)
8927 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8930 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8931 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8932 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8935 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8938 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8939 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8940 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8941 if (*tunnel_header_v)
8942 *tunnel_header_m = vxlan_m->vni[0] |
8943 vxlan_m->vni[1] << 8 |
8944 vxlan_m->vni[2] << 16;
8946 *tunnel_header_m = 0x0;
8947 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8948 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8949 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8953 * Add VXLAN-GPE item to matcher and to the value.
8955 * @param[in, out] matcher
8957 * @param[in, out] key
8958 * Flow matcher value.
8960 * Flow pattern to translate.
8962 * Item is inner pattern.
8966 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8967 const struct rte_flow_item *item, int inner)
8969 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8970 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8974 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8976 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8982 uint8_t flags_m = 0xff;
8983 uint8_t flags_v = 0xc;
8986 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8988 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8990 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8992 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8994 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8995 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8996 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8997 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8998 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9003 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9004 size = sizeof(vxlan_m->vni);
9005 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9006 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9007 memcpy(vni_m, vxlan_m->vni, size);
9008 for (i = 0; i < size; ++i)
9009 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9010 if (vxlan_m->flags) {
9011 flags_m = vxlan_m->flags;
9012 flags_v = vxlan_v->flags;
9014 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9015 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9016 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
9018 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
9023 * Add Geneve item to matcher and to the value.
9025 * @param[in, out] matcher
9027 * @param[in, out] key
9028 * Flow matcher value.
9030 * Flow pattern to translate.
9032 * Item is inner pattern.
9036 flow_dv_translate_item_geneve(void *matcher, void *key,
9037 const struct rte_flow_item *item, int inner)
9039 const struct rte_flow_item_geneve *geneve_m = item->mask;
9040 const struct rte_flow_item_geneve *geneve_v = item->spec;
9043 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9044 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9053 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9055 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9059 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9061 dport = MLX5_UDP_PORT_GENEVE;
9062 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9063 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9064 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9069 geneve_m = &rte_flow_item_geneve_mask;
9070 size = sizeof(geneve_m->vni);
9071 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9072 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9073 memcpy(vni_m, geneve_m->vni, size);
9074 for (i = 0; i < size; ++i)
9075 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9076 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
9077 rte_be_to_cpu_16(geneve_m->protocol));
9078 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9079 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
9080 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9081 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9082 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9083 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9084 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9085 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9086 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9087 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9088 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9089 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9090 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9094 * Create Geneve TLV option resource.
9096 * @param dev[in, out]
9097 * Pointer to rte_eth_dev structure.
9098 * @param[in, out] tag_be24
9099 * Tag value in big endian then R-shift 8.
9100 * @parm[in, out] dev_flow
9101 * Pointer to the dev_flow.
9103 * pointer to error structure.
9106 * 0 on success otherwise -errno and errno is set.
9110 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9111 const struct rte_flow_item *item,
9112 struct rte_flow_error *error)
9114 struct mlx5_priv *priv = dev->data->dev_private;
9115 struct mlx5_dev_ctx_shared *sh = priv->sh;
9116 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9117 sh->geneve_tlv_option_resource;
9118 struct mlx5_devx_obj *obj;
9119 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9124 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9125 if (geneve_opt_resource != NULL) {
9126 if (geneve_opt_resource->option_class ==
9127 geneve_opt_v->option_class &&
9128 geneve_opt_resource->option_type ==
9129 geneve_opt_v->option_type &&
9130 geneve_opt_resource->length ==
9131 geneve_opt_v->option_len) {
9132 /* We already have GENVE TLV option obj allocated. */
9133 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9136 ret = rte_flow_error_set(error, ENOMEM,
9137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9138 "Only one GENEVE TLV option supported");
9142 /* Create a GENEVE TLV object and resource. */
9143 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9144 geneve_opt_v->option_class,
9145 geneve_opt_v->option_type,
9146 geneve_opt_v->option_len);
9148 ret = rte_flow_error_set(error, ENODATA,
9149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9150 "Failed to create GENEVE TLV Devx object");
9153 sh->geneve_tlv_option_resource =
9154 mlx5_malloc(MLX5_MEM_ZERO,
9155 sizeof(*geneve_opt_resource),
9157 if (!sh->geneve_tlv_option_resource) {
9158 claim_zero(mlx5_devx_cmd_destroy(obj));
9159 ret = rte_flow_error_set(error, ENOMEM,
9160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9161 "GENEVE TLV object memory allocation failed");
9164 geneve_opt_resource = sh->geneve_tlv_option_resource;
9165 geneve_opt_resource->obj = obj;
9166 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9167 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9168 geneve_opt_resource->length = geneve_opt_v->option_len;
9169 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9173 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9178 * Add Geneve TLV option item to matcher.
9180 * @param[in, out] dev
9181 * Pointer to rte_eth_dev structure.
9182 * @param[in, out] matcher
9184 * @param[in, out] key
9185 * Flow matcher value.
9187 * Flow pattern to translate.
9189 * Pointer to error structure.
9192 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9193 void *key, const struct rte_flow_item *item,
9194 struct rte_flow_error *error)
9196 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9197 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9198 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9199 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9200 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9202 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9203 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9209 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9210 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9213 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9217 * Set the option length in GENEVE header if not requested.
9218 * The GENEVE TLV option length is expressed by the option length field
9219 * in the GENEVE header.
9220 * If the option length was not requested but the GENEVE TLV option item
9221 * is present we set the option length field implicitly.
9223 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9224 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9225 MLX5_GENEVE_OPTLEN_MASK);
9226 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9227 geneve_opt_v->option_len + 1);
9229 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9230 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9232 if (geneve_opt_v->data) {
9233 memcpy(&opt_data_key, geneve_opt_v->data,
9234 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9235 sizeof(opt_data_key)));
9236 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9237 sizeof(opt_data_key));
9238 memcpy(&opt_data_mask, geneve_opt_m->data,
9239 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9240 sizeof(opt_data_mask)));
9241 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9242 sizeof(opt_data_mask));
9243 MLX5_SET(fte_match_set_misc3, misc3_m,
9244 geneve_tlv_option_0_data,
9245 rte_be_to_cpu_32(opt_data_mask));
9246 MLX5_SET(fte_match_set_misc3, misc3_v,
9247 geneve_tlv_option_0_data,
9248 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9254 * Add MPLS item to matcher and to the value.
9256 * @param[in, out] matcher
9258 * @param[in, out] key
9259 * Flow matcher value.
9261 * Flow pattern to translate.
9262 * @param[in] prev_layer
9263 * The protocol layer indicated in previous item.
9265 * Item is inner pattern.
9268 flow_dv_translate_item_mpls(void *matcher, void *key,
9269 const struct rte_flow_item *item,
9270 uint64_t prev_layer,
9273 const uint32_t *in_mpls_m = item->mask;
9274 const uint32_t *in_mpls_v = item->spec;
9275 uint32_t *out_mpls_m = 0;
9276 uint32_t *out_mpls_v = 0;
9277 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9278 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9279 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9281 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9282 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9283 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9285 switch (prev_layer) {
9286 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9287 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9288 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9289 MLX5_UDP_PORT_MPLS);
9291 case MLX5_FLOW_LAYER_GRE:
9293 case MLX5_FLOW_LAYER_GRE_KEY:
9294 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9295 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9296 RTE_ETHER_TYPE_MPLS);
9304 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9305 switch (prev_layer) {
9306 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9308 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9309 outer_first_mpls_over_udp);
9311 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9312 outer_first_mpls_over_udp);
9314 case MLX5_FLOW_LAYER_GRE:
9316 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9317 outer_first_mpls_over_gre);
9319 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9320 outer_first_mpls_over_gre);
9323 /* Inner MPLS not over GRE is not supported. */
9326 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9330 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9336 if (out_mpls_m && out_mpls_v) {
9337 *out_mpls_m = *in_mpls_m;
9338 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9343 * Add metadata register item to matcher
9345 * @param[in, out] matcher
9347 * @param[in, out] key
9348 * Flow matcher value.
9349 * @param[in] reg_type
9350 * Type of device metadata register
9357 flow_dv_match_meta_reg(void *matcher, void *key,
9358 enum modify_reg reg_type,
9359 uint32_t data, uint32_t mask)
9362 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9364 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9370 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9371 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9374 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9375 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9379 * The metadata register C0 field might be divided into
9380 * source vport index and META item value, we should set
9381 * this field according to specified mask, not as whole one.
9383 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9385 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9386 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9389 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9392 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9393 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9396 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9397 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9400 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9401 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9404 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9405 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9408 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9409 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9412 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9413 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9416 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9417 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9426 * Add MARK item to matcher
9429 * The device to configure through.
9430 * @param[in, out] matcher
9432 * @param[in, out] key
9433 * Flow matcher value.
9435 * Flow pattern to translate.
9438 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9439 void *matcher, void *key,
9440 const struct rte_flow_item *item)
9442 struct mlx5_priv *priv = dev->data->dev_private;
9443 const struct rte_flow_item_mark *mark;
9447 mark = item->mask ? (const void *)item->mask :
9448 &rte_flow_item_mark_mask;
9449 mask = mark->id & priv->sh->dv_mark_mask;
9450 mark = (const void *)item->spec;
9452 value = mark->id & priv->sh->dv_mark_mask & mask;
9454 enum modify_reg reg;
9456 /* Get the metadata register index for the mark. */
9457 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9458 MLX5_ASSERT(reg > 0);
9459 if (reg == REG_C_0) {
9460 struct mlx5_priv *priv = dev->data->dev_private;
9461 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9462 uint32_t shl_c0 = rte_bsf32(msk_c0);
9468 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9473 * Add META item to matcher
9476 * The devich to configure through.
9477 * @param[in, out] matcher
9479 * @param[in, out] key
9480 * Flow matcher value.
9482 * Attributes of flow that includes this item.
9484 * Flow pattern to translate.
9487 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9488 void *matcher, void *key,
9489 const struct rte_flow_attr *attr,
9490 const struct rte_flow_item *item)
9492 const struct rte_flow_item_meta *meta_m;
9493 const struct rte_flow_item_meta *meta_v;
9495 meta_m = (const void *)item->mask;
9497 meta_m = &rte_flow_item_meta_mask;
9498 meta_v = (const void *)item->spec;
9501 uint32_t value = meta_v->data;
9502 uint32_t mask = meta_m->data;
9504 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9507 MLX5_ASSERT(reg != REG_NON);
9508 if (reg == REG_C_0) {
9509 struct mlx5_priv *priv = dev->data->dev_private;
9510 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9511 uint32_t shl_c0 = rte_bsf32(msk_c0);
9517 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9522 * Add vport metadata Reg C0 item to matcher
9524 * @param[in, out] matcher
9526 * @param[in, out] key
9527 * Flow matcher value.
9529 * Flow pattern to translate.
9532 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9533 uint32_t value, uint32_t mask)
9535 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9539 * Add tag item to matcher
9542 * The devich to configure through.
9543 * @param[in, out] matcher
9545 * @param[in, out] key
9546 * Flow matcher value.
9548 * Flow pattern to translate.
9551 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9552 void *matcher, void *key,
9553 const struct rte_flow_item *item)
9555 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9556 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9557 uint32_t mask, value;
9560 value = tag_v->data;
9561 mask = tag_m ? tag_m->data : UINT32_MAX;
9562 if (tag_v->id == REG_C_0) {
9563 struct mlx5_priv *priv = dev->data->dev_private;
9564 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9565 uint32_t shl_c0 = rte_bsf32(msk_c0);
9571 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9575 * Add TAG item to matcher
9578 * The devich to configure through.
9579 * @param[in, out] matcher
9581 * @param[in, out] key
9582 * Flow matcher value.
9584 * Flow pattern to translate.
9587 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9588 void *matcher, void *key,
9589 const struct rte_flow_item *item)
9591 const struct rte_flow_item_tag *tag_v = item->spec;
9592 const struct rte_flow_item_tag *tag_m = item->mask;
9593 enum modify_reg reg;
9596 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9597 /* Get the metadata register index for the tag. */
9598 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9599 MLX5_ASSERT(reg > 0);
9600 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9604 * Add source vport match to the specified matcher.
9606 * @param[in, out] matcher
9608 * @param[in, out] key
9609 * Flow matcher value.
9611 * Source vport value to match
9616 flow_dv_translate_item_source_vport(void *matcher, void *key,
9617 int16_t port, uint16_t mask)
9619 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9620 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9622 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9623 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9627 * Translate port-id item to eswitch match on port-id.
9630 * The devich to configure through.
9631 * @param[in, out] matcher
9633 * @param[in, out] key
9634 * Flow matcher value.
9636 * Flow pattern to translate.
9641 * 0 on success, a negative errno value otherwise.
9644 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9645 void *key, const struct rte_flow_item *item,
9646 const struct rte_flow_attr *attr)
9648 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9649 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9650 struct mlx5_priv *priv;
9653 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9654 flow_dv_translate_item_source_vport(matcher, key,
9655 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9658 mask = pid_m ? pid_m->id : 0xffff;
9659 id = pid_v ? pid_v->id : dev->data->port_id;
9660 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9664 * Translate to vport field or to metadata, depending on mode.
9665 * Kernel can use either misc.source_port or half of C0 metadata
9668 if (priv->vport_meta_mask) {
9670 * Provide the hint for SW steering library
9671 * to insert the flow into ingress domain and
9672 * save the extra vport match.
9674 if (mask == 0xffff && priv->vport_id == 0xffff &&
9675 priv->pf_bond < 0 && attr->transfer)
9676 flow_dv_translate_item_source_vport
9677 (matcher, key, priv->vport_id, mask);
9679 * We should always set the vport metadata register,
9680 * otherwise the SW steering library can drop
9681 * the rule if wire vport metadata value is not zero,
9682 * it depends on kernel configuration.
9684 flow_dv_translate_item_meta_vport(matcher, key,
9685 priv->vport_meta_tag,
9686 priv->vport_meta_mask);
9688 flow_dv_translate_item_source_vport(matcher, key,
9689 priv->vport_id, mask);
9695 * Add ICMP6 item to matcher and to the value.
9697 * @param[in, out] matcher
9699 * @param[in, out] key
9700 * Flow matcher value.
9702 * Flow pattern to translate.
9704 * Item is inner pattern.
9707 flow_dv_translate_item_icmp6(void *matcher, void *key,
9708 const struct rte_flow_item *item,
9711 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9712 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9715 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9717 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9719 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9721 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9723 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9725 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9732 icmp6_m = &rte_flow_item_icmp6_mask;
9733 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9734 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9735 icmp6_v->type & icmp6_m->type);
9736 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9737 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9738 icmp6_v->code & icmp6_m->code);
9742 * Add ICMP item to matcher and to the value.
9744 * @param[in, out] matcher
9746 * @param[in, out] key
9747 * Flow matcher value.
9749 * Flow pattern to translate.
9751 * Item is inner pattern.
9754 flow_dv_translate_item_icmp(void *matcher, void *key,
9755 const struct rte_flow_item *item,
9758 const struct rte_flow_item_icmp *icmp_m = item->mask;
9759 const struct rte_flow_item_icmp *icmp_v = item->spec;
9760 uint32_t icmp_header_data_m = 0;
9761 uint32_t icmp_header_data_v = 0;
9764 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9766 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9768 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9770 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9772 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9774 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9776 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9777 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9781 icmp_m = &rte_flow_item_icmp_mask;
9782 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9783 icmp_m->hdr.icmp_type);
9784 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9785 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9786 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9787 icmp_m->hdr.icmp_code);
9788 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9789 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9790 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9791 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9792 if (icmp_header_data_m) {
9793 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9794 icmp_header_data_v |=
9795 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9796 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9797 icmp_header_data_m);
9798 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9799 icmp_header_data_v & icmp_header_data_m);
9804 * Add GTP item to matcher and to the value.
9806 * @param[in, out] matcher
9808 * @param[in, out] key
9809 * Flow matcher value.
9811 * Flow pattern to translate.
9813 * Item is inner pattern.
9816 flow_dv_translate_item_gtp(void *matcher, void *key,
9817 const struct rte_flow_item *item, int inner)
9819 const struct rte_flow_item_gtp *gtp_m = item->mask;
9820 const struct rte_flow_item_gtp *gtp_v = item->spec;
9823 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9825 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9826 uint16_t dport = RTE_GTPU_UDP_PORT;
9829 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9831 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9833 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9835 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9837 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9838 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9839 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9844 gtp_m = &rte_flow_item_gtp_mask;
9845 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9846 gtp_m->v_pt_rsv_flags);
9847 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9848 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9849 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9850 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9851 gtp_v->msg_type & gtp_m->msg_type);
9852 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9853 rte_be_to_cpu_32(gtp_m->teid));
9854 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9855 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9859 * Add GTP PSC item to matcher.
9861 * @param[in, out] matcher
9863 * @param[in, out] key
9864 * Flow matcher value.
9866 * Flow pattern to translate.
9869 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9870 const struct rte_flow_item *item)
9872 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9873 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9874 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9876 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9882 uint8_t next_ext_header_type;
9887 /* Always set E-flag match on one, regardless of GTP item settings. */
9888 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9889 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9890 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9891 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9892 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9893 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9894 /*Set next extension header type. */
9897 dw_2.next_ext_header_type = 0xff;
9898 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9899 rte_cpu_to_be_32(dw_2.w32));
9902 dw_2.next_ext_header_type = 0x85;
9903 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9904 rte_cpu_to_be_32(dw_2.w32));
9916 /*Set extension header PDU type and Qos. */
9918 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9920 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9921 dw_0.qfi = gtp_psc_m->hdr.qfi;
9922 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9923 rte_cpu_to_be_32(dw_0.w32));
9925 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9926 gtp_psc_m->hdr.type);
9927 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9928 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9929 rte_cpu_to_be_32(dw_0.w32));
9935 * Add eCPRI item to matcher and to the value.
9938 * The devich to configure through.
9939 * @param[in, out] matcher
9941 * @param[in, out] key
9942 * Flow matcher value.
9944 * Flow pattern to translate.
9945 * @param[in] last_item
9949 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9950 void *key, const struct rte_flow_item *item,
9953 struct mlx5_priv *priv = dev->data->dev_private;
9954 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9955 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9956 struct rte_ecpri_common_hdr common;
9957 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9959 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9965 * In case of eCPRI over Ethernet, if EtherType is not specified,
9966 * match on eCPRI EtherType implicitly.
9968 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
9969 void *hdrs_m, *hdrs_v, *l2m, *l2v;
9971 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9972 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9973 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
9974 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
9975 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
9976 *(uint16_t *)l2m = UINT16_MAX;
9977 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
9983 ecpri_m = &rte_flow_item_ecpri_mask;
9985 * Maximal four DW samples are supported in a single matching now.
9986 * Two are used now for a eCPRI matching:
9987 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9988 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9991 if (!ecpri_m->hdr.common.u32)
9993 samples = priv->sh->ecpri_parser.ids;
9994 /* Need to take the whole DW as the mask to fill the entry. */
9995 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9996 prog_sample_field_value_0);
9997 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9998 prog_sample_field_value_0);
9999 /* Already big endian (network order) in the header. */
10000 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10001 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10002 /* Sample#0, used for matching type, offset 0. */
10003 MLX5_SET(fte_match_set_misc4, misc4_m,
10004 prog_sample_field_id_0, samples[0]);
10005 /* It makes no sense to set the sample ID in the mask field. */
10006 MLX5_SET(fte_match_set_misc4, misc4_v,
10007 prog_sample_field_id_0, samples[0]);
10009 * Checking if message body part needs to be matched.
10010 * Some wildcard rules only matching type field should be supported.
10012 if (ecpri_m->hdr.dummy[0]) {
10013 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10014 switch (common.type) {
10015 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10016 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10017 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10018 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10019 prog_sample_field_value_1);
10020 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10021 prog_sample_field_value_1);
10022 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10023 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10024 ecpri_m->hdr.dummy[0];
10025 /* Sample#1, to match message body, offset 4. */
10026 MLX5_SET(fte_match_set_misc4, misc4_m,
10027 prog_sample_field_id_1, samples[1]);
10028 MLX5_SET(fte_match_set_misc4, misc4_v,
10029 prog_sample_field_id_1, samples[1]);
10032 /* Others, do not match any sample ID. */
10039 * Add connection tracking status item to matcher
10042 * The devich to configure through.
10043 * @param[in, out] matcher
10045 * @param[in, out] key
10046 * Flow matcher value.
10048 * Flow pattern to translate.
10051 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10052 void *matcher, void *key,
10053 const struct rte_flow_item *item)
10055 uint32_t reg_value = 0;
10057 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10058 uint32_t reg_mask = 0;
10059 const struct rte_flow_item_conntrack *spec = item->spec;
10060 const struct rte_flow_item_conntrack *mask = item->mask;
10062 struct rte_flow_error error;
10065 mask = &rte_flow_item_conntrack_mask;
10066 if (!spec || !mask->flags)
10068 flags = spec->flags & mask->flags;
10069 /* The conflict should be checked in the validation. */
10070 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10071 reg_value |= MLX5_CT_SYNDROME_VALID;
10072 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10073 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10074 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10075 reg_value |= MLX5_CT_SYNDROME_INVALID;
10076 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10077 reg_value |= MLX5_CT_SYNDROME_TRAP;
10078 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10079 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10080 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10081 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10082 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10084 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10085 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10086 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10087 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10088 /* The REG_C_x value could be saved during startup. */
10089 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10090 if (reg_id == REG_NON)
10092 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10093 reg_value, reg_mask);
10097 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10098 const struct rte_flow_item *item,
10099 struct mlx5_flow *dev_flow, bool is_inner)
10101 const struct rte_flow_item_flex *spec =
10102 (const struct rte_flow_item_flex *)item->spec;
10103 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10105 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10108 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10109 /* Don't count both inner and outer flex items in one rule. */
10110 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10111 MLX5_ASSERT(false);
10112 dev_flow->handle->flex_item |= RTE_BIT32(index);
10114 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10117 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10119 #define HEADER_IS_ZERO(match_criteria, headers) \
10120 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10121 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10124 * Calculate flow matcher enable bitmap.
10126 * @param match_criteria
10127 * Pointer to flow matcher criteria.
10130 * Bitmap of enabled fields.
10133 flow_dv_matcher_enable(uint32_t *match_criteria)
10135 uint8_t match_criteria_enable;
10137 match_criteria_enable =
10138 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10139 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10140 match_criteria_enable |=
10141 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10142 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10143 match_criteria_enable |=
10144 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10145 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10146 match_criteria_enable |=
10147 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10148 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10149 match_criteria_enable |=
10150 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10151 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10152 match_criteria_enable |=
10153 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10154 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10155 match_criteria_enable |=
10156 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10157 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10158 return match_criteria_enable;
10162 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10165 * Check flow matching criteria first, subtract misc5/4 length if flow
10166 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10167 * misc5/4 are not supported, and matcher creation failure is expected
10168 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10169 * misc5 is right after misc4.
10171 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10172 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10173 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10174 if (!(match_criteria & (1 <<
10175 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10176 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10181 static struct mlx5_list_entry *
10182 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10183 struct mlx5_list_entry *entry, void *cb_ctx)
10185 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10186 struct mlx5_flow_dv_matcher *ref = ctx->data;
10187 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10188 typeof(*tbl), tbl);
10189 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10194 rte_flow_error_set(ctx->error, ENOMEM,
10195 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10196 "cannot create matcher");
10199 memcpy(resource, entry, sizeof(*resource));
10200 resource->tbl = &tbl->tbl;
10201 return &resource->entry;
10205 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10206 struct mlx5_list_entry *entry)
10211 struct mlx5_list_entry *
10212 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10214 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10215 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10216 struct rte_eth_dev *dev = ctx->dev;
10217 struct mlx5_flow_tbl_data_entry *tbl_data;
10218 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10219 struct rte_flow_error *error = ctx->error;
10220 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10221 struct mlx5_flow_tbl_resource *tbl;
10226 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10228 rte_flow_error_set(error, ENOMEM,
10229 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10231 "cannot allocate flow table data entry");
10234 tbl_data->idx = idx;
10235 tbl_data->tunnel = tt_prm->tunnel;
10236 tbl_data->group_id = tt_prm->group_id;
10237 tbl_data->external = !!tt_prm->external;
10238 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10239 tbl_data->is_egress = !!key.is_egress;
10240 tbl_data->is_transfer = !!key.is_fdb;
10241 tbl_data->dummy = !!key.dummy;
10242 tbl_data->level = key.level;
10243 tbl_data->id = key.id;
10244 tbl = &tbl_data->tbl;
10246 return &tbl_data->entry;
10248 domain = sh->fdb_domain;
10249 else if (key.is_egress)
10250 domain = sh->tx_domain;
10252 domain = sh->rx_domain;
10253 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10255 rte_flow_error_set(error, ENOMEM,
10256 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10257 NULL, "cannot create flow table object");
10258 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10261 if (key.level != 0) {
10262 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10263 (tbl->obj, &tbl_data->jump.action);
10265 rte_flow_error_set(error, ENOMEM,
10266 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10268 "cannot create flow jump action");
10269 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10270 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10274 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10275 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10276 key.level, key.id);
10277 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10278 flow_dv_matcher_create_cb,
10279 flow_dv_matcher_match_cb,
10280 flow_dv_matcher_remove_cb,
10281 flow_dv_matcher_clone_cb,
10282 flow_dv_matcher_clone_free_cb);
10283 if (!tbl_data->matchers) {
10284 rte_flow_error_set(error, ENOMEM,
10285 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10287 "cannot create tbl matcher list");
10288 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10289 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10290 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10293 return &tbl_data->entry;
10297 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10300 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10301 struct mlx5_flow_tbl_data_entry *tbl_data =
10302 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10303 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10305 return tbl_data->level != key.level ||
10306 tbl_data->id != key.id ||
10307 tbl_data->dummy != key.dummy ||
10308 tbl_data->is_transfer != !!key.is_fdb ||
10309 tbl_data->is_egress != !!key.is_egress;
10312 struct mlx5_list_entry *
10313 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10316 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10317 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10318 struct mlx5_flow_tbl_data_entry *tbl_data;
10319 struct rte_flow_error *error = ctx->error;
10322 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10324 rte_flow_error_set(error, ENOMEM,
10325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10327 "cannot allocate flow table data entry");
10330 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10331 tbl_data->idx = idx;
10332 return &tbl_data->entry;
10336 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10338 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10339 struct mlx5_flow_tbl_data_entry *tbl_data =
10340 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10342 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10346 * Get a flow table.
10348 * @param[in, out] dev
10349 * Pointer to rte_eth_dev structure.
10350 * @param[in] table_level
10351 * Table level to use.
10352 * @param[in] egress
10353 * Direction of the table.
10354 * @param[in] transfer
10355 * E-Switch or NIC flow.
10357 * Dummy entry for dv API.
10358 * @param[in] table_id
10360 * @param[out] error
10361 * pointer to error structure.
10364 * Returns tables resource based on the index, NULL in case of failed.
10366 struct mlx5_flow_tbl_resource *
10367 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10368 uint32_t table_level, uint8_t egress,
10371 const struct mlx5_flow_tunnel *tunnel,
10372 uint32_t group_id, uint8_t dummy,
10374 struct rte_flow_error *error)
10376 struct mlx5_priv *priv = dev->data->dev_private;
10377 union mlx5_flow_tbl_key table_key = {
10379 .level = table_level,
10383 .is_fdb = !!transfer,
10384 .is_egress = !!egress,
10387 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10389 .group_id = group_id,
10390 .external = external,
10392 struct mlx5_flow_cb_ctx ctx = {
10395 .data = &table_key.v64,
10398 struct mlx5_list_entry *entry;
10399 struct mlx5_flow_tbl_data_entry *tbl_data;
10401 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10403 rte_flow_error_set(error, ENOMEM,
10404 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10405 "cannot get table");
10408 DRV_LOG(DEBUG, "table_level %u table_id %u "
10409 "tunnel %u group %u registered.",
10410 table_level, table_id,
10411 tunnel ? tunnel->tunnel_id : 0, group_id);
10412 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10413 return &tbl_data->tbl;
10417 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10419 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10420 struct mlx5_flow_tbl_data_entry *tbl_data =
10421 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10423 MLX5_ASSERT(entry && sh);
10424 if (tbl_data->jump.action)
10425 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10426 if (tbl_data->tbl.obj)
10427 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10428 if (tbl_data->tunnel_offload && tbl_data->external) {
10429 struct mlx5_list_entry *he;
10430 struct mlx5_hlist *tunnel_grp_hash;
10431 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10432 union tunnel_tbl_key tunnel_key = {
10433 .tunnel_id = tbl_data->tunnel ?
10434 tbl_data->tunnel->tunnel_id : 0,
10435 .group = tbl_data->group_id
10437 uint32_t table_level = tbl_data->level;
10438 struct mlx5_flow_cb_ctx ctx = {
10439 .data = (void *)&tunnel_key.val,
10442 tunnel_grp_hash = tbl_data->tunnel ?
10443 tbl_data->tunnel->groups :
10445 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10447 mlx5_hlist_unregister(tunnel_grp_hash, he);
10449 "table_level %u id %u tunnel %u group %u released.",
10453 tbl_data->tunnel->tunnel_id : 0,
10454 tbl_data->group_id);
10456 mlx5_list_destroy(tbl_data->matchers);
10457 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10461 * Release a flow table.
10464 * Pointer to device shared structure.
10466 * Table resource to be released.
10469 * Returns 0 if table was released, else return 1;
10472 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10473 struct mlx5_flow_tbl_resource *tbl)
10475 struct mlx5_flow_tbl_data_entry *tbl_data =
10476 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10480 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10484 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10485 struct mlx5_list_entry *entry, void *cb_ctx)
10487 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10488 struct mlx5_flow_dv_matcher *ref = ctx->data;
10489 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10492 return cur->crc != ref->crc ||
10493 cur->priority != ref->priority ||
10494 memcmp((const void *)cur->mask.buf,
10495 (const void *)ref->mask.buf, ref->mask.size);
10498 struct mlx5_list_entry *
10499 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10501 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10502 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10503 struct mlx5_flow_dv_matcher *ref = ctx->data;
10504 struct mlx5_flow_dv_matcher *resource;
10505 struct mlx5dv_flow_matcher_attr dv_attr = {
10506 .type = IBV_FLOW_ATTR_NORMAL,
10507 .match_mask = (void *)&ref->mask,
10509 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10510 typeof(*tbl), tbl);
10513 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10516 rte_flow_error_set(ctx->error, ENOMEM,
10517 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10518 "cannot create matcher");
10522 dv_attr.match_criteria_enable =
10523 flow_dv_matcher_enable(resource->mask.buf);
10524 __flow_dv_adjust_buf_size(&ref->mask.size,
10525 dv_attr.match_criteria_enable);
10526 dv_attr.priority = ref->priority;
10527 if (tbl->is_egress)
10528 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10529 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10531 &resource->matcher_object);
10533 mlx5_free(resource);
10534 rte_flow_error_set(ctx->error, ENOMEM,
10535 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10536 "cannot create matcher");
10539 return &resource->entry;
10543 * Register the flow matcher.
10545 * @param[in, out] dev
10546 * Pointer to rte_eth_dev structure.
10547 * @param[in, out] matcher
10548 * Pointer to flow matcher.
10549 * @param[in, out] key
10550 * Pointer to flow table key.
10551 * @parm[in, out] dev_flow
10552 * Pointer to the dev_flow.
10553 * @param[out] error
10554 * pointer to error structure.
10557 * 0 on success otherwise -errno and errno is set.
10560 flow_dv_matcher_register(struct rte_eth_dev *dev,
10561 struct mlx5_flow_dv_matcher *ref,
10562 union mlx5_flow_tbl_key *key,
10563 struct mlx5_flow *dev_flow,
10564 const struct mlx5_flow_tunnel *tunnel,
10566 struct rte_flow_error *error)
10568 struct mlx5_list_entry *entry;
10569 struct mlx5_flow_dv_matcher *resource;
10570 struct mlx5_flow_tbl_resource *tbl;
10571 struct mlx5_flow_tbl_data_entry *tbl_data;
10572 struct mlx5_flow_cb_ctx ctx = {
10577 * tunnel offload API requires this registration for cases when
10578 * tunnel match rule was inserted before tunnel set rule.
10580 tbl = flow_dv_tbl_resource_get(dev, key->level,
10581 key->is_egress, key->is_fdb,
10582 dev_flow->external, tunnel,
10583 group_id, 0, key->id, error);
10585 return -rte_errno; /* No need to refill the error info */
10586 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10588 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10590 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10591 return rte_flow_error_set(error, ENOMEM,
10592 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10593 "cannot allocate ref memory");
10595 resource = container_of(entry, typeof(*resource), entry);
10596 dev_flow->handle->dvh.matcher = resource;
10600 struct mlx5_list_entry *
10601 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10603 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10604 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10605 struct mlx5_flow_dv_tag_resource *entry;
10609 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10611 rte_flow_error_set(ctx->error, ENOMEM,
10612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10613 "cannot allocate resource memory");
10617 entry->tag_id = *(uint32_t *)(ctx->data);
10618 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10621 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10622 rte_flow_error_set(ctx->error, ENOMEM,
10623 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10624 NULL, "cannot create action");
10627 return &entry->entry;
10631 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10634 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10635 struct mlx5_flow_dv_tag_resource *tag =
10636 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10638 return *(uint32_t *)(ctx->data) != tag->tag_id;
10641 struct mlx5_list_entry *
10642 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10645 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10646 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10647 struct mlx5_flow_dv_tag_resource *entry;
10650 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10652 rte_flow_error_set(ctx->error, ENOMEM,
10653 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10654 "cannot allocate tag resource memory");
10657 memcpy(entry, oentry, sizeof(*entry));
10659 return &entry->entry;
10663 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10665 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10666 struct mlx5_flow_dv_tag_resource *tag =
10667 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10669 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10673 * Find existing tag resource or create and register a new one.
10675 * @param dev[in, out]
10676 * Pointer to rte_eth_dev structure.
10677 * @param[in, out] tag_be24
10678 * Tag value in big endian then R-shift 8.
10679 * @parm[in, out] dev_flow
10680 * Pointer to the dev_flow.
10681 * @param[out] error
10682 * pointer to error structure.
10685 * 0 on success otherwise -errno and errno is set.
10688 flow_dv_tag_resource_register
10689 (struct rte_eth_dev *dev,
10691 struct mlx5_flow *dev_flow,
10692 struct rte_flow_error *error)
10694 struct mlx5_priv *priv = dev->data->dev_private;
10695 struct mlx5_flow_dv_tag_resource *resource;
10696 struct mlx5_list_entry *entry;
10697 struct mlx5_flow_cb_ctx ctx = {
10701 struct mlx5_hlist *tag_table;
10703 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10705 MLX5_TAGS_HLIST_ARRAY_SIZE,
10706 false, false, priv->sh,
10707 flow_dv_tag_create_cb,
10708 flow_dv_tag_match_cb,
10709 flow_dv_tag_remove_cb,
10710 flow_dv_tag_clone_cb,
10711 flow_dv_tag_clone_free_cb);
10712 if (unlikely(!tag_table))
10714 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10716 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10718 dev_flow->handle->dvh.rix_tag = resource->idx;
10719 dev_flow->dv.tag_resource = resource;
10726 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10728 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10729 struct mlx5_flow_dv_tag_resource *tag =
10730 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10732 MLX5_ASSERT(tag && sh && tag->action);
10733 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10734 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10735 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10742 * Pointer to Ethernet device.
10747 * 1 while a reference on it exists, 0 when freed.
10750 flow_dv_tag_release(struct rte_eth_dev *dev,
10753 struct mlx5_priv *priv = dev->data->dev_private;
10754 struct mlx5_flow_dv_tag_resource *tag;
10756 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10759 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10760 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10761 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10765 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10768 * Pointer to rte_eth_dev structure.
10769 * @param[in] action
10770 * Pointer to action PORT_ID / REPRESENTED_PORT.
10771 * @param[out] dst_port_id
10772 * The target port ID.
10773 * @param[out] error
10774 * Pointer to the error structure.
10777 * 0 on success, a negative errno value otherwise and rte_errno is set.
10780 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10781 const struct rte_flow_action *action,
10782 uint32_t *dst_port_id,
10783 struct rte_flow_error *error)
10786 struct mlx5_priv *priv;
10788 switch (action->type) {
10789 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10790 const struct rte_flow_action_port_id *conf;
10792 conf = (const struct rte_flow_action_port_id *)action->conf;
10793 port = conf->original ? dev->data->port_id : conf->id;
10796 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10797 const struct rte_flow_action_ethdev *ethdev;
10799 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10800 port = ethdev->port_id;
10804 MLX5_ASSERT(false);
10805 return rte_flow_error_set(error, EINVAL,
10806 RTE_FLOW_ERROR_TYPE_ACTION, action,
10807 "unknown E-Switch action");
10810 priv = mlx5_port_to_eswitch_info(port, false);
10812 return rte_flow_error_set(error, -rte_errno,
10813 RTE_FLOW_ERROR_TYPE_ACTION,
10815 "No eswitch info was found for port");
10816 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10818 * This parameter is transferred to
10819 * mlx5dv_dr_action_create_dest_ib_port().
10821 *dst_port_id = priv->dev_port;
10824 * Legacy mode, no LAG configurations is supported.
10825 * This parameter is transferred to
10826 * mlx5dv_dr_action_create_dest_vport().
10828 *dst_port_id = priv->vport_id;
10834 * Create a counter with aging configuration.
10837 * Pointer to rte_eth_dev structure.
10838 * @param[in] dev_flow
10839 * Pointer to the mlx5_flow.
10840 * @param[out] count
10841 * Pointer to the counter action configuration.
10843 * Pointer to the aging action configuration.
10846 * Index to flow counter on success, 0 otherwise.
10849 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10850 struct mlx5_flow *dev_flow,
10851 const struct rte_flow_action_count *count
10853 const struct rte_flow_action_age *age)
10856 struct mlx5_age_param *age_param;
10858 counter = flow_dv_counter_alloc(dev, !!age);
10859 if (!counter || age == NULL)
10861 age_param = flow_dv_counter_idx_get_age(dev, counter);
10862 age_param->context = age->context ? age->context :
10863 (void *)(uintptr_t)(dev_flow->flow_idx);
10864 age_param->timeout = age->timeout;
10865 age_param->port_id = dev->data->port_id;
10866 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10867 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10872 * Add Tx queue matcher
10875 * Pointer to the dev struct.
10876 * @param[in, out] matcher
10878 * @param[in, out] key
10879 * Flow matcher value.
10881 * Flow pattern to translate.
10883 * Item is inner pattern.
10886 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10887 void *matcher, void *key,
10888 const struct rte_flow_item *item)
10890 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10891 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10893 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10895 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10896 struct mlx5_txq_ctrl *txq;
10897 uint32_t queue, mask;
10899 queue_m = (const void *)item->mask;
10900 queue_v = (const void *)item->spec;
10903 txq = mlx5_txq_get(dev, queue_v->queue);
10906 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10907 queue = txq->obj->sq->id;
10909 queue = txq->obj->sq_obj.sq->id;
10910 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10911 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10912 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10913 mlx5_txq_release(dev, queue_v->queue);
10917 * Set the hash fields according to the @p flow information.
10919 * @param[in] dev_flow
10920 * Pointer to the mlx5_flow.
10921 * @param[in] rss_desc
10922 * Pointer to the mlx5_flow_rss_desc.
10925 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10926 struct mlx5_flow_rss_desc *rss_desc)
10928 uint64_t items = dev_flow->handle->layers;
10930 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10932 dev_flow->hash_fields = 0;
10933 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10934 if (rss_desc->level >= 2)
10937 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10938 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10939 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10940 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10941 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10942 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10943 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10945 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10947 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10948 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10949 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10950 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10951 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10952 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10953 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10955 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10958 if (dev_flow->hash_fields == 0)
10960 * There is no match between the RSS types and the
10961 * L3 protocol (IPv4/IPv6) defined in the flow rule.
10964 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10965 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10966 if (rss_types & RTE_ETH_RSS_UDP) {
10967 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10968 dev_flow->hash_fields |=
10969 IBV_RX_HASH_SRC_PORT_UDP;
10970 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10971 dev_flow->hash_fields |=
10972 IBV_RX_HASH_DST_PORT_UDP;
10974 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10976 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10977 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10978 if (rss_types & RTE_ETH_RSS_TCP) {
10979 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10980 dev_flow->hash_fields |=
10981 IBV_RX_HASH_SRC_PORT_TCP;
10982 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10983 dev_flow->hash_fields |=
10984 IBV_RX_HASH_DST_PORT_TCP;
10986 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10990 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
10994 * Prepare an Rx Hash queue.
10997 * Pointer to Ethernet device.
10998 * @param[in] dev_flow
10999 * Pointer to the mlx5_flow.
11000 * @param[in] rss_desc
11001 * Pointer to the mlx5_flow_rss_desc.
11002 * @param[out] hrxq_idx
11003 * Hash Rx queue index.
11006 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11008 static struct mlx5_hrxq *
11009 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11010 struct mlx5_flow *dev_flow,
11011 struct mlx5_flow_rss_desc *rss_desc,
11012 uint32_t *hrxq_idx)
11014 struct mlx5_priv *priv = dev->data->dev_private;
11015 struct mlx5_flow_handle *dh = dev_flow->handle;
11016 struct mlx5_hrxq *hrxq;
11018 MLX5_ASSERT(rss_desc->queue_num);
11019 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11020 rss_desc->hash_fields = dev_flow->hash_fields;
11021 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11022 rss_desc->shared_rss = 0;
11023 if (rss_desc->hash_fields == 0)
11024 rss_desc->queue_num = 1;
11025 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11028 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11034 * Release sample sub action resource.
11036 * @param[in, out] dev
11037 * Pointer to rte_eth_dev structure.
11038 * @param[in] act_res
11039 * Pointer to sample sub action resource.
11042 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11043 struct mlx5_flow_sub_actions_idx *act_res)
11045 if (act_res->rix_hrxq) {
11046 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11047 act_res->rix_hrxq = 0;
11049 if (act_res->rix_encap_decap) {
11050 flow_dv_encap_decap_resource_release(dev,
11051 act_res->rix_encap_decap);
11052 act_res->rix_encap_decap = 0;
11054 if (act_res->rix_port_id_action) {
11055 flow_dv_port_id_action_resource_release(dev,
11056 act_res->rix_port_id_action);
11057 act_res->rix_port_id_action = 0;
11059 if (act_res->rix_tag) {
11060 flow_dv_tag_release(dev, act_res->rix_tag);
11061 act_res->rix_tag = 0;
11063 if (act_res->rix_jump) {
11064 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11065 act_res->rix_jump = 0;
11070 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11071 struct mlx5_list_entry *entry, void *cb_ctx)
11073 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11074 struct rte_eth_dev *dev = ctx->dev;
11075 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11076 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11080 if (ctx_resource->ratio == resource->ratio &&
11081 ctx_resource->ft_type == resource->ft_type &&
11082 ctx_resource->ft_id == resource->ft_id &&
11083 ctx_resource->set_action == resource->set_action &&
11084 !memcmp((void *)&ctx_resource->sample_act,
11085 (void *)&resource->sample_act,
11086 sizeof(struct mlx5_flow_sub_actions_list))) {
11088 * Existing sample action should release the prepared
11089 * sub-actions reference counter.
11091 flow_dv_sample_sub_actions_release(dev,
11092 &ctx_resource->sample_idx);
11098 struct mlx5_list_entry *
11099 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11101 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11102 struct rte_eth_dev *dev = ctx->dev;
11103 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11104 void **sample_dv_actions = ctx_resource->sub_actions;
11105 struct mlx5_flow_dv_sample_resource *resource;
11106 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11107 struct mlx5_priv *priv = dev->data->dev_private;
11108 struct mlx5_dev_ctx_shared *sh = priv->sh;
11109 struct mlx5_flow_tbl_resource *tbl;
11111 const uint32_t next_ft_step = 1;
11112 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11113 uint8_t is_egress = 0;
11114 uint8_t is_transfer = 0;
11115 struct rte_flow_error *error = ctx->error;
11117 /* Register new sample resource. */
11118 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11120 rte_flow_error_set(error, ENOMEM,
11121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11123 "cannot allocate resource memory");
11126 *resource = *ctx_resource;
11127 /* Create normal path table level */
11128 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11130 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11132 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11133 is_egress, is_transfer,
11134 true, NULL, 0, 0, 0, error);
11136 rte_flow_error_set(error, ENOMEM,
11137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11139 "fail to create normal path table "
11143 resource->normal_path_tbl = tbl;
11144 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11145 if (!sh->default_miss_action) {
11146 rte_flow_error_set(error, ENOMEM,
11147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11149 "default miss action was not "
11153 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11154 sh->default_miss_action;
11156 /* Create a DR sample action */
11157 sampler_attr.sample_ratio = resource->ratio;
11158 sampler_attr.default_next_table = tbl->obj;
11159 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11160 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11161 &sample_dv_actions[0];
11162 sampler_attr.action = resource->set_action;
11163 if (mlx5_os_flow_dr_create_flow_action_sampler
11164 (&sampler_attr, &resource->verbs_action)) {
11165 rte_flow_error_set(error, ENOMEM,
11166 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11167 NULL, "cannot create sample action");
11170 resource->idx = idx;
11171 resource->dev = dev;
11172 return &resource->entry;
11174 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11175 flow_dv_sample_sub_actions_release(dev,
11176 &resource->sample_idx);
11177 if (resource->normal_path_tbl)
11178 flow_dv_tbl_resource_release(MLX5_SH(dev),
11179 resource->normal_path_tbl);
11180 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11185 struct mlx5_list_entry *
11186 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11187 struct mlx5_list_entry *entry __rte_unused,
11190 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11191 struct rte_eth_dev *dev = ctx->dev;
11192 struct mlx5_flow_dv_sample_resource *resource;
11193 struct mlx5_priv *priv = dev->data->dev_private;
11194 struct mlx5_dev_ctx_shared *sh = priv->sh;
11197 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11199 rte_flow_error_set(ctx->error, ENOMEM,
11200 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11202 "cannot allocate resource memory");
11205 memcpy(resource, entry, sizeof(*resource));
11206 resource->idx = idx;
11207 resource->dev = dev;
11208 return &resource->entry;
11212 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11213 struct mlx5_list_entry *entry)
11215 struct mlx5_flow_dv_sample_resource *resource =
11216 container_of(entry, typeof(*resource), entry);
11217 struct rte_eth_dev *dev = resource->dev;
11218 struct mlx5_priv *priv = dev->data->dev_private;
11220 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11224 * Find existing sample resource or create and register a new one.
11226 * @param[in, out] dev
11227 * Pointer to rte_eth_dev structure.
11229 * Pointer to sample resource reference.
11230 * @parm[in, out] dev_flow
11231 * Pointer to the dev_flow.
11232 * @param[out] error
11233 * pointer to error structure.
11236 * 0 on success otherwise -errno and errno is set.
11239 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11240 struct mlx5_flow_dv_sample_resource *ref,
11241 struct mlx5_flow *dev_flow,
11242 struct rte_flow_error *error)
11244 struct mlx5_flow_dv_sample_resource *resource;
11245 struct mlx5_list_entry *entry;
11246 struct mlx5_priv *priv = dev->data->dev_private;
11247 struct mlx5_flow_cb_ctx ctx = {
11253 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11256 resource = container_of(entry, typeof(*resource), entry);
11257 dev_flow->handle->dvh.rix_sample = resource->idx;
11258 dev_flow->dv.sample_res = resource;
11263 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11264 struct mlx5_list_entry *entry, void *cb_ctx)
11266 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11267 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11268 struct rte_eth_dev *dev = ctx->dev;
11269 struct mlx5_flow_dv_dest_array_resource *resource =
11270 container_of(entry, typeof(*resource), entry);
11273 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11274 ctx_resource->ft_type == resource->ft_type &&
11275 !memcmp((void *)resource->sample_act,
11276 (void *)ctx_resource->sample_act,
11277 (ctx_resource->num_of_dest *
11278 sizeof(struct mlx5_flow_sub_actions_list)))) {
11280 * Existing sample action should release the prepared
11281 * sub-actions reference counter.
11283 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11284 flow_dv_sample_sub_actions_release(dev,
11285 &ctx_resource->sample_idx[idx]);
11291 struct mlx5_list_entry *
11292 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11294 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11295 struct rte_eth_dev *dev = ctx->dev;
11296 struct mlx5_flow_dv_dest_array_resource *resource;
11297 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11298 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11299 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11300 struct mlx5_priv *priv = dev->data->dev_private;
11301 struct mlx5_dev_ctx_shared *sh = priv->sh;
11302 struct mlx5_flow_sub_actions_list *sample_act;
11303 struct mlx5dv_dr_domain *domain;
11304 uint32_t idx = 0, res_idx = 0;
11305 struct rte_flow_error *error = ctx->error;
11306 uint64_t action_flags;
11309 /* Register new destination array resource. */
11310 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11313 rte_flow_error_set(error, ENOMEM,
11314 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11316 "cannot allocate resource memory");
11319 *resource = *ctx_resource;
11320 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11321 domain = sh->fdb_domain;
11322 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11323 domain = sh->rx_domain;
11325 domain = sh->tx_domain;
11326 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11327 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11328 mlx5_malloc(MLX5_MEM_ZERO,
11329 sizeof(struct mlx5dv_dr_action_dest_attr),
11331 if (!dest_attr[idx]) {
11332 rte_flow_error_set(error, ENOMEM,
11333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11335 "cannot allocate resource memory");
11338 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11339 sample_act = &ctx_resource->sample_act[idx];
11340 action_flags = sample_act->action_flags;
11341 switch (action_flags) {
11342 case MLX5_FLOW_ACTION_QUEUE:
11343 dest_attr[idx]->dest = sample_act->dr_queue_action;
11345 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11346 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11347 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11348 dest_attr[idx]->dest_reformat->reformat =
11349 sample_act->dr_encap_action;
11350 dest_attr[idx]->dest_reformat->dest =
11351 sample_act->dr_port_id_action;
11353 case MLX5_FLOW_ACTION_PORT_ID:
11354 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11356 case MLX5_FLOW_ACTION_JUMP:
11357 dest_attr[idx]->dest = sample_act->dr_jump_action;
11360 rte_flow_error_set(error, EINVAL,
11361 RTE_FLOW_ERROR_TYPE_ACTION,
11363 "unsupported actions type");
11367 /* create a dest array actioin */
11368 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11370 resource->num_of_dest,
11372 &resource->action);
11374 rte_flow_error_set(error, ENOMEM,
11375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11377 "cannot create destination array action");
11380 resource->idx = res_idx;
11381 resource->dev = dev;
11382 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11383 mlx5_free(dest_attr[idx]);
11384 return &resource->entry;
11386 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11387 flow_dv_sample_sub_actions_release(dev,
11388 &resource->sample_idx[idx]);
11389 if (dest_attr[idx])
11390 mlx5_free(dest_attr[idx]);
11392 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11396 struct mlx5_list_entry *
11397 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11398 struct mlx5_list_entry *entry __rte_unused,
11401 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11402 struct rte_eth_dev *dev = ctx->dev;
11403 struct mlx5_flow_dv_dest_array_resource *resource;
11404 struct mlx5_priv *priv = dev->data->dev_private;
11405 struct mlx5_dev_ctx_shared *sh = priv->sh;
11406 uint32_t res_idx = 0;
11407 struct rte_flow_error *error = ctx->error;
11409 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11412 rte_flow_error_set(error, ENOMEM,
11413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11415 "cannot allocate dest-array memory");
11418 memcpy(resource, entry, sizeof(*resource));
11419 resource->idx = res_idx;
11420 resource->dev = dev;
11421 return &resource->entry;
11425 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11426 struct mlx5_list_entry *entry)
11428 struct mlx5_flow_dv_dest_array_resource *resource =
11429 container_of(entry, typeof(*resource), entry);
11430 struct rte_eth_dev *dev = resource->dev;
11431 struct mlx5_priv *priv = dev->data->dev_private;
11433 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11437 * Find existing destination array resource or create and register a new one.
11439 * @param[in, out] dev
11440 * Pointer to rte_eth_dev structure.
11442 * Pointer to destination array resource reference.
11443 * @parm[in, out] dev_flow
11444 * Pointer to the dev_flow.
11445 * @param[out] error
11446 * pointer to error structure.
11449 * 0 on success otherwise -errno and errno is set.
11452 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11453 struct mlx5_flow_dv_dest_array_resource *ref,
11454 struct mlx5_flow *dev_flow,
11455 struct rte_flow_error *error)
11457 struct mlx5_flow_dv_dest_array_resource *resource;
11458 struct mlx5_priv *priv = dev->data->dev_private;
11459 struct mlx5_list_entry *entry;
11460 struct mlx5_flow_cb_ctx ctx = {
11466 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11469 resource = container_of(entry, typeof(*resource), entry);
11470 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11471 dev_flow->dv.dest_array_res = resource;
11476 * Convert Sample action to DV specification.
11479 * Pointer to rte_eth_dev structure.
11480 * @param[in] action
11481 * Pointer to sample action structure.
11482 * @param[in, out] dev_flow
11483 * Pointer to the mlx5_flow.
11485 * Pointer to the flow attributes.
11486 * @param[in, out] num_of_dest
11487 * Pointer to the num of destination.
11488 * @param[in, out] sample_actions
11489 * Pointer to sample actions list.
11490 * @param[in, out] res
11491 * Pointer to sample resource.
11492 * @param[out] error
11493 * Pointer to the error structure.
11496 * 0 on success, a negative errno value otherwise and rte_errno is set.
11499 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11500 const struct rte_flow_action_sample *action,
11501 struct mlx5_flow *dev_flow,
11502 const struct rte_flow_attr *attr,
11503 uint32_t *num_of_dest,
11504 void **sample_actions,
11505 struct mlx5_flow_dv_sample_resource *res,
11506 struct rte_flow_error *error)
11508 struct mlx5_priv *priv = dev->data->dev_private;
11509 const struct rte_flow_action *sub_actions;
11510 struct mlx5_flow_sub_actions_list *sample_act;
11511 struct mlx5_flow_sub_actions_idx *sample_idx;
11512 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11513 struct rte_flow *flow = dev_flow->flow;
11514 struct mlx5_flow_rss_desc *rss_desc;
11515 uint64_t action_flags = 0;
11518 rss_desc = &wks->rss_desc;
11519 sample_act = &res->sample_act;
11520 sample_idx = &res->sample_idx;
11521 res->ratio = action->ratio;
11522 sub_actions = action->actions;
11523 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11524 int type = sub_actions->type;
11525 uint32_t pre_rix = 0;
11528 case RTE_FLOW_ACTION_TYPE_QUEUE:
11530 const struct rte_flow_action_queue *queue;
11531 struct mlx5_hrxq *hrxq;
11534 queue = sub_actions->conf;
11535 rss_desc->queue_num = 1;
11536 rss_desc->queue[0] = queue->index;
11537 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11538 rss_desc, &hrxq_idx);
11540 return rte_flow_error_set
11542 RTE_FLOW_ERROR_TYPE_ACTION,
11544 "cannot create fate queue");
11545 sample_act->dr_queue_action = hrxq->action;
11546 sample_idx->rix_hrxq = hrxq_idx;
11547 sample_actions[sample_act->actions_num++] =
11550 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11551 if (action_flags & MLX5_FLOW_ACTION_MARK)
11552 dev_flow->handle->rix_hrxq = hrxq_idx;
11553 dev_flow->handle->fate_action =
11554 MLX5_FLOW_FATE_QUEUE;
11557 case RTE_FLOW_ACTION_TYPE_RSS:
11559 struct mlx5_hrxq *hrxq;
11561 const struct rte_flow_action_rss *rss;
11562 const uint8_t *rss_key;
11564 rss = sub_actions->conf;
11565 memcpy(rss_desc->queue, rss->queue,
11566 rss->queue_num * sizeof(uint16_t));
11567 rss_desc->queue_num = rss->queue_num;
11568 /* NULL RSS key indicates default RSS key. */
11569 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11570 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11572 * rss->level and rss.types should be set in advance
11573 * when expanding items for RSS.
11575 flow_dv_hashfields_set(dev_flow, rss_desc);
11576 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11577 rss_desc, &hrxq_idx);
11579 return rte_flow_error_set
11581 RTE_FLOW_ERROR_TYPE_ACTION,
11583 "cannot create fate queue");
11584 sample_act->dr_queue_action = hrxq->action;
11585 sample_idx->rix_hrxq = hrxq_idx;
11586 sample_actions[sample_act->actions_num++] =
11589 action_flags |= MLX5_FLOW_ACTION_RSS;
11590 if (action_flags & MLX5_FLOW_ACTION_MARK)
11591 dev_flow->handle->rix_hrxq = hrxq_idx;
11592 dev_flow->handle->fate_action =
11593 MLX5_FLOW_FATE_QUEUE;
11596 case RTE_FLOW_ACTION_TYPE_MARK:
11598 uint32_t tag_be = mlx5_flow_mark_set
11599 (((const struct rte_flow_action_mark *)
11600 (sub_actions->conf))->id);
11602 dev_flow->handle->mark = 1;
11603 pre_rix = dev_flow->handle->dvh.rix_tag;
11604 /* Save the mark resource before sample */
11605 pre_r = dev_flow->dv.tag_resource;
11606 if (flow_dv_tag_resource_register(dev, tag_be,
11609 MLX5_ASSERT(dev_flow->dv.tag_resource);
11610 sample_act->dr_tag_action =
11611 dev_flow->dv.tag_resource->action;
11612 sample_idx->rix_tag =
11613 dev_flow->handle->dvh.rix_tag;
11614 sample_actions[sample_act->actions_num++] =
11615 sample_act->dr_tag_action;
11616 /* Recover the mark resource after sample */
11617 dev_flow->dv.tag_resource = pre_r;
11618 dev_flow->handle->dvh.rix_tag = pre_rix;
11619 action_flags |= MLX5_FLOW_ACTION_MARK;
11622 case RTE_FLOW_ACTION_TYPE_COUNT:
11624 if (!flow->counter) {
11626 flow_dv_translate_create_counter(dev,
11627 dev_flow, sub_actions->conf,
11629 if (!flow->counter)
11630 return rte_flow_error_set
11632 RTE_FLOW_ERROR_TYPE_ACTION,
11634 "cannot create counter"
11637 sample_act->dr_cnt_action =
11638 (flow_dv_counter_get_by_idx(dev,
11639 flow->counter, NULL))->action;
11640 sample_actions[sample_act->actions_num++] =
11641 sample_act->dr_cnt_action;
11642 action_flags |= MLX5_FLOW_ACTION_COUNT;
11645 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11646 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11648 struct mlx5_flow_dv_port_id_action_resource
11650 uint32_t port_id = 0;
11652 memset(&port_id_resource, 0, sizeof(port_id_resource));
11653 /* Save the port id resource before sample */
11654 pre_rix = dev_flow->handle->rix_port_id_action;
11655 pre_r = dev_flow->dv.port_id_action;
11656 if (flow_dv_translate_action_port_id(dev, sub_actions,
11659 port_id_resource.port_id = port_id;
11660 if (flow_dv_port_id_action_resource_register
11661 (dev, &port_id_resource, dev_flow, error))
11663 sample_act->dr_port_id_action =
11664 dev_flow->dv.port_id_action->action;
11665 sample_idx->rix_port_id_action =
11666 dev_flow->handle->rix_port_id_action;
11667 sample_actions[sample_act->actions_num++] =
11668 sample_act->dr_port_id_action;
11669 /* Recover the port id resource after sample */
11670 dev_flow->dv.port_id_action = pre_r;
11671 dev_flow->handle->rix_port_id_action = pre_rix;
11673 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11676 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11677 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11678 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11679 /* Save the encap resource before sample */
11680 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11681 pre_r = dev_flow->dv.encap_decap;
11682 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11687 sample_act->dr_encap_action =
11688 dev_flow->dv.encap_decap->action;
11689 sample_idx->rix_encap_decap =
11690 dev_flow->handle->dvh.rix_encap_decap;
11691 sample_actions[sample_act->actions_num++] =
11692 sample_act->dr_encap_action;
11693 /* Recover the encap resource after sample */
11694 dev_flow->dv.encap_decap = pre_r;
11695 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11696 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11699 return rte_flow_error_set(error, EINVAL,
11700 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11702 "Not support for sampler action");
11705 sample_act->action_flags = action_flags;
11706 res->ft_id = dev_flow->dv.group;
11707 if (attr->transfer) {
11709 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11710 uint64_t set_action;
11711 } action_ctx = { .set_action = 0 };
11713 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11714 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11715 MLX5_MODIFICATION_TYPE_SET);
11716 MLX5_SET(set_action_in, action_ctx.action_in, field,
11717 MLX5_MODI_META_REG_C_0);
11718 MLX5_SET(set_action_in, action_ctx.action_in, data,
11719 priv->vport_meta_tag);
11720 res->set_action = action_ctx.set_action;
11721 } else if (attr->ingress) {
11722 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11724 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11730 * Convert Sample action to DV specification.
11733 * Pointer to rte_eth_dev structure.
11734 * @param[in, out] dev_flow
11735 * Pointer to the mlx5_flow.
11736 * @param[in] num_of_dest
11737 * The num of destination.
11738 * @param[in, out] res
11739 * Pointer to sample resource.
11740 * @param[in, out] mdest_res
11741 * Pointer to destination array resource.
11742 * @param[in] sample_actions
11743 * Pointer to sample path actions list.
11744 * @param[in] action_flags
11745 * Holds the actions detected until now.
11746 * @param[out] error
11747 * Pointer to the error structure.
11750 * 0 on success, a negative errno value otherwise and rte_errno is set.
11753 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11754 struct mlx5_flow *dev_flow,
11755 uint32_t num_of_dest,
11756 struct mlx5_flow_dv_sample_resource *res,
11757 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11758 void **sample_actions,
11759 uint64_t action_flags,
11760 struct rte_flow_error *error)
11762 /* update normal path action resource into last index of array */
11763 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11764 struct mlx5_flow_sub_actions_list *sample_act =
11765 &mdest_res->sample_act[dest_index];
11766 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11767 struct mlx5_flow_rss_desc *rss_desc;
11768 uint32_t normal_idx = 0;
11769 struct mlx5_hrxq *hrxq;
11773 rss_desc = &wks->rss_desc;
11774 if (num_of_dest > 1) {
11775 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11776 /* Handle QP action for mirroring */
11777 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11778 rss_desc, &hrxq_idx);
11780 return rte_flow_error_set
11782 RTE_FLOW_ERROR_TYPE_ACTION,
11784 "cannot create rx queue");
11786 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11787 sample_act->dr_queue_action = hrxq->action;
11788 if (action_flags & MLX5_FLOW_ACTION_MARK)
11789 dev_flow->handle->rix_hrxq = hrxq_idx;
11790 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11792 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11794 mdest_res->sample_idx[dest_index].rix_encap_decap =
11795 dev_flow->handle->dvh.rix_encap_decap;
11796 sample_act->dr_encap_action =
11797 dev_flow->dv.encap_decap->action;
11798 dev_flow->handle->dvh.rix_encap_decap = 0;
11800 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11802 mdest_res->sample_idx[dest_index].rix_port_id_action =
11803 dev_flow->handle->rix_port_id_action;
11804 sample_act->dr_port_id_action =
11805 dev_flow->dv.port_id_action->action;
11806 dev_flow->handle->rix_port_id_action = 0;
11808 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11810 mdest_res->sample_idx[dest_index].rix_jump =
11811 dev_flow->handle->rix_jump;
11812 sample_act->dr_jump_action =
11813 dev_flow->dv.jump->action;
11814 dev_flow->handle->rix_jump = 0;
11816 sample_act->actions_num = normal_idx;
11817 /* update sample action resource into first index of array */
11818 mdest_res->ft_type = res->ft_type;
11819 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11820 sizeof(struct mlx5_flow_sub_actions_idx));
11821 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11822 sizeof(struct mlx5_flow_sub_actions_list));
11823 mdest_res->num_of_dest = num_of_dest;
11824 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11826 return rte_flow_error_set(error, EINVAL,
11827 RTE_FLOW_ERROR_TYPE_ACTION,
11828 NULL, "can't create sample "
11831 res->sub_actions = sample_actions;
11832 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11833 return rte_flow_error_set(error, EINVAL,
11834 RTE_FLOW_ERROR_TYPE_ACTION,
11836 "can't create sample action");
11842 * Remove an ASO age action from age actions list.
11845 * Pointer to the Ethernet device structure.
11847 * Pointer to the aso age action handler.
11850 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11851 struct mlx5_aso_age_action *age)
11853 struct mlx5_age_info *age_info;
11854 struct mlx5_age_param *age_param = &age->age_params;
11855 struct mlx5_priv *priv = dev->data->dev_private;
11856 uint16_t expected = AGE_CANDIDATE;
11858 age_info = GET_PORT_AGE_INFO(priv);
11859 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11860 AGE_FREE, false, __ATOMIC_RELAXED,
11861 __ATOMIC_RELAXED)) {
11863 * We need the lock even it is age timeout,
11864 * since age action may still in process.
11866 rte_spinlock_lock(&age_info->aged_sl);
11867 LIST_REMOVE(age, next);
11868 rte_spinlock_unlock(&age_info->aged_sl);
11869 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11874 * Release an ASO age action.
11877 * Pointer to the Ethernet device structure.
11878 * @param[in] age_idx
11879 * Index of ASO age action to release.
11881 * True if the release operation is during flow destroy operation.
11882 * False if the release operation is during action destroy operation.
11885 * 0 when age action was removed, otherwise the number of references.
11888 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11890 struct mlx5_priv *priv = dev->data->dev_private;
11891 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11892 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11893 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11896 flow_dv_aso_age_remove_from_age(dev, age);
11897 rte_spinlock_lock(&mng->free_sl);
11898 LIST_INSERT_HEAD(&mng->free, age, next);
11899 rte_spinlock_unlock(&mng->free_sl);
11905 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11908 * Pointer to the Ethernet device structure.
11911 * 0 on success, otherwise negative errno value and rte_errno is set.
11914 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11916 struct mlx5_priv *priv = dev->data->dev_private;
11917 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11918 void *old_pools = mng->pools;
11919 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11920 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11921 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11924 rte_errno = ENOMEM;
11928 memcpy(pools, old_pools,
11929 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11930 mlx5_free(old_pools);
11932 /* First ASO flow hit allocation - starting ASO data-path. */
11933 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11941 mng->pools = pools;
11946 * Create and initialize a new ASO aging pool.
11949 * Pointer to the Ethernet device structure.
11950 * @param[out] age_free
11951 * Where to put the pointer of a new age action.
11954 * The age actions pool pointer and @p age_free is set on success,
11955 * NULL otherwise and rte_errno is set.
11957 static struct mlx5_aso_age_pool *
11958 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11959 struct mlx5_aso_age_action **age_free)
11961 struct mlx5_priv *priv = dev->data->dev_private;
11962 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11963 struct mlx5_aso_age_pool *pool = NULL;
11964 struct mlx5_devx_obj *obj = NULL;
11967 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
11968 priv->sh->cdev->pdn);
11970 rte_errno = ENODATA;
11971 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11974 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11976 claim_zero(mlx5_devx_cmd_destroy(obj));
11977 rte_errno = ENOMEM;
11980 pool->flow_hit_aso_obj = obj;
11981 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
11982 rte_rwlock_write_lock(&mng->resize_rwl);
11983 pool->index = mng->next;
11984 /* Resize pools array if there is no room for the new pool in it. */
11985 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
11986 claim_zero(mlx5_devx_cmd_destroy(obj));
11988 rte_rwlock_write_unlock(&mng->resize_rwl);
11991 mng->pools[pool->index] = pool;
11993 rte_rwlock_write_unlock(&mng->resize_rwl);
11994 /* Assign the first action in the new pool, the rest go to free list. */
11995 *age_free = &pool->actions[0];
11996 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
11997 pool->actions[i].offset = i;
11998 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12004 * Allocate a ASO aging bit.
12007 * Pointer to the Ethernet device structure.
12008 * @param[out] error
12009 * Pointer to the error structure.
12012 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12015 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12017 struct mlx5_priv *priv = dev->data->dev_private;
12018 const struct mlx5_aso_age_pool *pool;
12019 struct mlx5_aso_age_action *age_free = NULL;
12020 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12023 /* Try to get the next free age action bit. */
12024 rte_spinlock_lock(&mng->free_sl);
12025 age_free = LIST_FIRST(&mng->free);
12027 LIST_REMOVE(age_free, next);
12028 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12029 rte_spinlock_unlock(&mng->free_sl);
12030 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12031 NULL, "failed to create ASO age pool");
12032 return 0; /* 0 is an error. */
12034 rte_spinlock_unlock(&mng->free_sl);
12035 pool = container_of
12036 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12037 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12039 if (!age_free->dr_action) {
12040 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12044 rte_flow_error_set(error, rte_errno,
12045 RTE_FLOW_ERROR_TYPE_ACTION,
12046 NULL, "failed to get reg_c "
12047 "for ASO flow hit");
12048 return 0; /* 0 is an error. */
12050 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12051 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12052 (priv->sh->rx_domain,
12053 pool->flow_hit_aso_obj->obj, age_free->offset,
12054 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12055 (reg_c - REG_C_0));
12056 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12057 if (!age_free->dr_action) {
12059 rte_spinlock_lock(&mng->free_sl);
12060 LIST_INSERT_HEAD(&mng->free, age_free, next);
12061 rte_spinlock_unlock(&mng->free_sl);
12062 rte_flow_error_set(error, rte_errno,
12063 RTE_FLOW_ERROR_TYPE_ACTION,
12064 NULL, "failed to create ASO "
12065 "flow hit action");
12066 return 0; /* 0 is an error. */
12069 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12070 return pool->index | ((age_free->offset + 1) << 16);
12074 * Initialize flow ASO age parameters.
12077 * Pointer to rte_eth_dev structure.
12078 * @param[in] age_idx
12079 * Index of ASO age action.
12080 * @param[in] context
12081 * Pointer to flow counter age context.
12082 * @param[in] timeout
12083 * Aging timeout in seconds.
12087 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12092 struct mlx5_aso_age_action *aso_age;
12094 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12095 MLX5_ASSERT(aso_age);
12096 aso_age->age_params.context = context;
12097 aso_age->age_params.timeout = timeout;
12098 aso_age->age_params.port_id = dev->data->port_id;
12099 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12101 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12106 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12107 const struct rte_flow_item_integrity *value,
12108 void *headers_m, void *headers_v)
12111 /* application l4_ok filter aggregates all hardware l4 filters
12112 * therefore hw l4_checksum_ok must be implicitly added here.
12114 struct rte_flow_item_integrity local_item;
12116 local_item.l4_csum_ok = 1;
12117 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
12118 local_item.l4_csum_ok);
12119 if (value->l4_ok) {
12120 /* application l4_ok = 1 matches sets both hw flags
12121 * l4_ok and l4_checksum_ok flags to 1.
12123 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12124 l4_checksum_ok, local_item.l4_csum_ok);
12125 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok,
12127 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok,
12130 /* application l4_ok = 0 matches on hw flag
12131 * l4_checksum_ok = 0 only.
12133 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12134 l4_checksum_ok, 0);
12136 } else if (mask->l4_csum_ok) {
12137 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
12139 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12140 value->l4_csum_ok);
12145 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12146 const struct rte_flow_item_integrity *value,
12147 void *headers_m, void *headers_v, bool is_ipv4)
12150 /* application l3_ok filter aggregates all hardware l3 filters
12151 * therefore hw ipv4_checksum_ok must be implicitly added here.
12153 struct rte_flow_item_integrity local_item;
12155 local_item.ipv4_csum_ok = !!is_ipv4;
12156 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
12157 local_item.ipv4_csum_ok);
12158 if (value->l3_ok) {
12159 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12160 ipv4_checksum_ok, local_item.ipv4_csum_ok);
12161 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok,
12163 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12166 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12167 ipv4_checksum_ok, 0);
12169 } else if (mask->ipv4_csum_ok) {
12170 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
12171 mask->ipv4_csum_ok);
12172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12173 value->ipv4_csum_ok);
12178 set_integrity_bits(void *headers_m, void *headers_v,
12179 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12181 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12182 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12184 /* Integrity bits validation cleared spec pointer */
12185 MLX5_ASSERT(spec != NULL);
12187 mask = &rte_flow_item_integrity_mask;
12188 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12190 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12194 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12196 struct rte_flow_item *integrity_items[2],
12197 uint64_t pattern_flags)
12199 void *headers_m, *headers_v;
12202 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12203 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12205 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12206 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12208 set_integrity_bits(headers_m, headers_v,
12209 integrity_items[1], is_l3_ip4);
12211 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12212 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12214 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12215 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12217 set_integrity_bits(headers_m, headers_v,
12218 integrity_items[0], is_l3_ip4);
12223 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12224 const struct rte_flow_item *integrity_items[2],
12225 uint64_t *last_item)
12227 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12229 /* integrity bits validation cleared spec pointer */
12230 MLX5_ASSERT(spec != NULL);
12231 if (spec->level > 1) {
12232 integrity_items[1] = item;
12233 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12235 integrity_items[0] = item;
12236 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12241 * Prepares DV flow counter with aging configuration.
12242 * Gets it by index when exists, creates a new one when doesn't.
12245 * Pointer to rte_eth_dev structure.
12246 * @param[in] dev_flow
12247 * Pointer to the mlx5_flow.
12248 * @param[in, out] flow
12249 * Pointer to the sub flow.
12251 * Pointer to the counter action configuration.
12253 * Pointer to the aging action configuration.
12254 * @param[out] error
12255 * Pointer to the error structure.
12258 * Pointer to the counter, NULL otherwise.
12260 static struct mlx5_flow_counter *
12261 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12262 struct mlx5_flow *dev_flow,
12263 struct rte_flow *flow,
12264 const struct rte_flow_action_count *count,
12265 const struct rte_flow_action_age *age,
12266 struct rte_flow_error *error)
12268 if (!flow->counter) {
12269 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12271 if (!flow->counter) {
12272 rte_flow_error_set(error, rte_errno,
12273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12274 "cannot create counter object.");
12278 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12282 * Release an ASO CT action by its own device.
12285 * Pointer to the Ethernet device structure.
12287 * Index of ASO CT action to release.
12290 * 0 when CT action was removed, otherwise the number of references.
12293 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12295 struct mlx5_priv *priv = dev->data->dev_private;
12296 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12298 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12299 enum mlx5_aso_ct_state state =
12300 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12302 /* Cannot release when CT is in the ASO SQ. */
12303 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12305 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12307 if (ct->dr_action_orig) {
12308 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12309 claim_zero(mlx5_glue->destroy_flow_action
12310 (ct->dr_action_orig));
12312 ct->dr_action_orig = NULL;
12314 if (ct->dr_action_rply) {
12315 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12316 claim_zero(mlx5_glue->destroy_flow_action
12317 (ct->dr_action_rply));
12319 ct->dr_action_rply = NULL;
12321 /* Clear the state to free, no need in 1st allocation. */
12322 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12323 rte_spinlock_lock(&mng->ct_sl);
12324 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12325 rte_spinlock_unlock(&mng->ct_sl);
12331 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12332 struct rte_flow_error *error)
12334 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12335 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12336 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12339 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12340 if (dev->data->dev_started != 1)
12341 return rte_flow_error_set(error, EAGAIN,
12342 RTE_FLOW_ERROR_TYPE_ACTION,
12344 "Indirect CT action cannot be destroyed when the port is stopped");
12345 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12347 return rte_flow_error_set(error, EAGAIN,
12348 RTE_FLOW_ERROR_TYPE_ACTION,
12350 "Current state prevents indirect CT action from being destroyed");
12355 * Resize the ASO CT pools array by 64 pools.
12358 * Pointer to the Ethernet device structure.
12361 * 0 on success, otherwise negative errno value and rte_errno is set.
12364 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12366 struct mlx5_priv *priv = dev->data->dev_private;
12367 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12368 void *old_pools = mng->pools;
12369 /* Magic number now, need a macro. */
12370 uint32_t resize = mng->n + 64;
12371 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12372 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12375 rte_errno = ENOMEM;
12378 rte_rwlock_write_lock(&mng->resize_rwl);
12379 /* ASO SQ/QP was already initialized in the startup. */
12381 /* Realloc could be an alternative choice. */
12382 rte_memcpy(pools, old_pools,
12383 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12384 mlx5_free(old_pools);
12387 mng->pools = pools;
12388 rte_rwlock_write_unlock(&mng->resize_rwl);
12393 * Create and initialize a new ASO CT pool.
12396 * Pointer to the Ethernet device structure.
12397 * @param[out] ct_free
12398 * Where to put the pointer of a new CT action.
12401 * The CT actions pool pointer and @p ct_free is set on success,
12402 * NULL otherwise and rte_errno is set.
12404 static struct mlx5_aso_ct_pool *
12405 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12406 struct mlx5_aso_ct_action **ct_free)
12408 struct mlx5_priv *priv = dev->data->dev_private;
12409 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12410 struct mlx5_aso_ct_pool *pool = NULL;
12411 struct mlx5_devx_obj *obj = NULL;
12413 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12415 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12416 priv->sh->cdev->pdn,
12419 rte_errno = ENODATA;
12420 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12423 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12425 rte_errno = ENOMEM;
12426 claim_zero(mlx5_devx_cmd_destroy(obj));
12429 pool->devx_obj = obj;
12430 pool->index = mng->next;
12431 /* Resize pools array if there is no room for the new pool in it. */
12432 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12433 claim_zero(mlx5_devx_cmd_destroy(obj));
12437 mng->pools[pool->index] = pool;
12439 /* Assign the first action in the new pool, the rest go to free list. */
12440 *ct_free = &pool->actions[0];
12441 /* Lock outside, the list operation is safe here. */
12442 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12443 /* refcnt is 0 when allocating the memory. */
12444 pool->actions[i].offset = i;
12445 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12451 * Allocate a ASO CT action from free list.
12454 * Pointer to the Ethernet device structure.
12455 * @param[out] error
12456 * Pointer to the error structure.
12459 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12462 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12464 struct mlx5_priv *priv = dev->data->dev_private;
12465 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12466 struct mlx5_aso_ct_action *ct = NULL;
12467 struct mlx5_aso_ct_pool *pool;
12472 if (!priv->sh->devx) {
12473 rte_errno = ENOTSUP;
12476 /* Get a free CT action, if no, a new pool will be created. */
12477 rte_spinlock_lock(&mng->ct_sl);
12478 ct = LIST_FIRST(&mng->free_cts);
12480 LIST_REMOVE(ct, next);
12481 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12482 rte_spinlock_unlock(&mng->ct_sl);
12483 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12484 NULL, "failed to create ASO CT pool");
12487 rte_spinlock_unlock(&mng->ct_sl);
12488 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12489 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12490 /* 0: inactive, 1: created, 2+: used by flows. */
12491 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12492 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12493 if (!ct->dr_action_orig) {
12494 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12495 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12496 (priv->sh->rx_domain, pool->devx_obj->obj,
12498 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12501 RTE_SET_USED(reg_c);
12503 if (!ct->dr_action_orig) {
12504 flow_dv_aso_ct_dev_release(dev, ct_idx);
12505 rte_flow_error_set(error, rte_errno,
12506 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12507 "failed to create ASO CT action");
12511 if (!ct->dr_action_rply) {
12512 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12513 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12514 (priv->sh->rx_domain, pool->devx_obj->obj,
12516 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12519 if (!ct->dr_action_rply) {
12520 flow_dv_aso_ct_dev_release(dev, ct_idx);
12521 rte_flow_error_set(error, rte_errno,
12522 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12523 "failed to create ASO CT action");
12531 * Create a conntrack object with context and actions by using ASO mechanism.
12534 * Pointer to rte_eth_dev structure.
12536 * Pointer to conntrack information profile.
12537 * @param[out] error
12538 * Pointer to the error structure.
12541 * Index to conntrack object on success, 0 otherwise.
12544 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12545 const struct rte_flow_action_conntrack *pro,
12546 struct rte_flow_error *error)
12548 struct mlx5_priv *priv = dev->data->dev_private;
12549 struct mlx5_dev_ctx_shared *sh = priv->sh;
12550 struct mlx5_aso_ct_action *ct;
12553 if (!sh->ct_aso_en)
12554 return rte_flow_error_set(error, ENOTSUP,
12555 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12556 "Connection is not supported");
12557 idx = flow_dv_aso_ct_alloc(dev, error);
12559 return rte_flow_error_set(error, rte_errno,
12560 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12561 "Failed to allocate CT object");
12562 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12563 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12564 return rte_flow_error_set(error, EBUSY,
12565 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12566 "Failed to update CT");
12567 ct->is_original = !!pro->is_original_dir;
12568 ct->peer = pro->peer_port;
12573 * Fill the flow with DV spec, lock free
12574 * (mutex should be acquired by caller).
12577 * Pointer to rte_eth_dev structure.
12578 * @param[in, out] dev_flow
12579 * Pointer to the sub flow.
12581 * Pointer to the flow attributes.
12583 * Pointer to the list of items.
12584 * @param[in] actions
12585 * Pointer to the list of actions.
12586 * @param[out] error
12587 * Pointer to the error structure.
12590 * 0 on success, a negative errno value otherwise and rte_errno is set.
12593 flow_dv_translate(struct rte_eth_dev *dev,
12594 struct mlx5_flow *dev_flow,
12595 const struct rte_flow_attr *attr,
12596 const struct rte_flow_item items[],
12597 const struct rte_flow_action actions[],
12598 struct rte_flow_error *error)
12600 struct mlx5_priv *priv = dev->data->dev_private;
12601 struct mlx5_dev_config *dev_conf = &priv->config;
12602 struct rte_flow *flow = dev_flow->flow;
12603 struct mlx5_flow_handle *handle = dev_flow->handle;
12604 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12605 struct mlx5_flow_rss_desc *rss_desc;
12606 uint64_t item_flags = 0;
12607 uint64_t last_item = 0;
12608 uint64_t action_flags = 0;
12609 struct mlx5_flow_dv_matcher matcher = {
12611 .size = sizeof(matcher.mask.buf),
12615 bool actions_end = false;
12617 struct mlx5_flow_dv_modify_hdr_resource res;
12618 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12619 sizeof(struct mlx5_modification_cmd) *
12620 (MLX5_MAX_MODIFY_NUM + 1)];
12622 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12623 const struct rte_flow_action_count *count = NULL;
12624 const struct rte_flow_action_age *non_shared_age = NULL;
12625 union flow_dv_attr flow_attr = { .attr = 0 };
12627 union mlx5_flow_tbl_key tbl_key;
12628 uint32_t modify_action_position = UINT32_MAX;
12629 void *match_mask = matcher.mask.buf;
12630 void *match_value = dev_flow->dv.value.buf;
12631 uint8_t next_protocol = 0xff;
12632 struct rte_vlan_hdr vlan = { 0 };
12633 struct mlx5_flow_dv_dest_array_resource mdest_res;
12634 struct mlx5_flow_dv_sample_resource sample_res;
12635 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12636 const struct rte_flow_action_sample *sample = NULL;
12637 struct mlx5_flow_sub_actions_list *sample_act;
12638 uint32_t sample_act_pos = UINT32_MAX;
12639 uint32_t age_act_pos = UINT32_MAX;
12640 uint32_t num_of_dest = 0;
12641 int tmp_actions_n = 0;
12644 const struct mlx5_flow_tunnel *tunnel = NULL;
12645 struct flow_grp_info grp_info = {
12646 .external = !!dev_flow->external,
12647 .transfer = !!attr->transfer,
12648 .fdb_def_rule = !!priv->fdb_def_rule,
12649 .skip_scale = dev_flow->skip_scale &
12650 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12651 .std_tbl_fix = true,
12653 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12656 return rte_flow_error_set(error, ENOMEM,
12657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12659 "failed to push flow workspace");
12660 rss_desc = &wks->rss_desc;
12661 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12662 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12663 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12664 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12665 /* update normal path action resource into last index of array */
12666 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12667 if (is_tunnel_offload_active(dev)) {
12668 if (dev_flow->tunnel) {
12669 RTE_VERIFY(dev_flow->tof_type ==
12670 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12671 tunnel = dev_flow->tunnel;
12673 tunnel = mlx5_get_tof(items, actions,
12674 &dev_flow->tof_type);
12675 dev_flow->tunnel = tunnel;
12677 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12678 (dev, attr, tunnel, dev_flow->tof_type);
12680 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12681 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12682 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12686 dev_flow->dv.group = table;
12687 if (attr->transfer)
12688 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12689 /* number of actions must be set to 0 in case of dirty stack. */
12690 mhdr_res->actions_num = 0;
12691 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12693 * do not add decap action if match rule drops packet
12694 * HW rejects rules with decap & drop
12696 * if tunnel match rule was inserted before matching tunnel set
12697 * rule flow table used in the match rule must be registered.
12698 * current implementation handles that in the
12699 * flow_dv_match_register() at the function end.
12701 bool add_decap = true;
12702 const struct rte_flow_action *ptr = actions;
12704 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12705 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12711 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12715 dev_flow->dv.actions[actions_n++] =
12716 dev_flow->dv.encap_decap->action;
12717 action_flags |= MLX5_FLOW_ACTION_DECAP;
12720 for (; !actions_end ; actions++) {
12721 const struct rte_flow_action_queue *queue;
12722 const struct rte_flow_action_rss *rss;
12723 const struct rte_flow_action *action = actions;
12724 const uint8_t *rss_key;
12725 struct mlx5_flow_tbl_resource *tbl;
12726 struct mlx5_aso_age_action *age_act;
12727 struct mlx5_flow_counter *cnt_act;
12728 uint32_t port_id = 0;
12729 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12730 int action_type = actions->type;
12731 const struct rte_flow_action *found_action = NULL;
12732 uint32_t jump_group = 0;
12733 uint32_t owner_idx;
12734 struct mlx5_aso_ct_action *ct;
12736 if (!mlx5_flow_os_action_supported(action_type))
12737 return rte_flow_error_set(error, ENOTSUP,
12738 RTE_FLOW_ERROR_TYPE_ACTION,
12740 "action not supported");
12741 switch (action_type) {
12742 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12743 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12745 case RTE_FLOW_ACTION_TYPE_VOID:
12747 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12748 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12749 if (flow_dv_translate_action_port_id(dev, action,
12752 port_id_resource.port_id = port_id;
12753 MLX5_ASSERT(!handle->rix_port_id_action);
12754 if (flow_dv_port_id_action_resource_register
12755 (dev, &port_id_resource, dev_flow, error))
12757 dev_flow->dv.actions[actions_n++] =
12758 dev_flow->dv.port_id_action->action;
12759 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12760 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12761 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12764 case RTE_FLOW_ACTION_TYPE_FLAG:
12765 action_flags |= MLX5_FLOW_ACTION_FLAG;
12766 dev_flow->handle->mark = 1;
12767 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12768 struct rte_flow_action_mark mark = {
12769 .id = MLX5_FLOW_MARK_DEFAULT,
12772 if (flow_dv_convert_action_mark(dev, &mark,
12776 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12779 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12781 * Only one FLAG or MARK is supported per device flow
12782 * right now. So the pointer to the tag resource must be
12783 * zero before the register process.
12785 MLX5_ASSERT(!handle->dvh.rix_tag);
12786 if (flow_dv_tag_resource_register(dev, tag_be,
12789 MLX5_ASSERT(dev_flow->dv.tag_resource);
12790 dev_flow->dv.actions[actions_n++] =
12791 dev_flow->dv.tag_resource->action;
12793 case RTE_FLOW_ACTION_TYPE_MARK:
12794 action_flags |= MLX5_FLOW_ACTION_MARK;
12795 dev_flow->handle->mark = 1;
12796 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12797 const struct rte_flow_action_mark *mark =
12798 (const struct rte_flow_action_mark *)
12801 if (flow_dv_convert_action_mark(dev, mark,
12805 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12809 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12810 /* Legacy (non-extensive) MARK action. */
12811 tag_be = mlx5_flow_mark_set
12812 (((const struct rte_flow_action_mark *)
12813 (actions->conf))->id);
12814 MLX5_ASSERT(!handle->dvh.rix_tag);
12815 if (flow_dv_tag_resource_register(dev, tag_be,
12818 MLX5_ASSERT(dev_flow->dv.tag_resource);
12819 dev_flow->dv.actions[actions_n++] =
12820 dev_flow->dv.tag_resource->action;
12822 case RTE_FLOW_ACTION_TYPE_SET_META:
12823 if (flow_dv_convert_action_set_meta
12824 (dev, mhdr_res, attr,
12825 (const struct rte_flow_action_set_meta *)
12826 actions->conf, error))
12828 action_flags |= MLX5_FLOW_ACTION_SET_META;
12830 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12831 if (flow_dv_convert_action_set_tag
12833 (const struct rte_flow_action_set_tag *)
12834 actions->conf, error))
12836 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12838 case RTE_FLOW_ACTION_TYPE_DROP:
12839 action_flags |= MLX5_FLOW_ACTION_DROP;
12840 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12842 case RTE_FLOW_ACTION_TYPE_QUEUE:
12843 queue = actions->conf;
12844 rss_desc->queue_num = 1;
12845 rss_desc->queue[0] = queue->index;
12846 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12847 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12848 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12851 case RTE_FLOW_ACTION_TYPE_RSS:
12852 rss = actions->conf;
12853 memcpy(rss_desc->queue, rss->queue,
12854 rss->queue_num * sizeof(uint16_t));
12855 rss_desc->queue_num = rss->queue_num;
12856 /* NULL RSS key indicates default RSS key. */
12857 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12858 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12860 * rss->level and rss.types should be set in advance
12861 * when expanding items for RSS.
12863 action_flags |= MLX5_FLOW_ACTION_RSS;
12864 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12865 MLX5_FLOW_FATE_SHARED_RSS :
12866 MLX5_FLOW_FATE_QUEUE;
12868 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12869 owner_idx = (uint32_t)(uintptr_t)action->conf;
12870 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12871 if (flow->age == 0) {
12872 flow->age = owner_idx;
12873 __atomic_fetch_add(&age_act->refcnt, 1,
12876 age_act_pos = actions_n++;
12877 action_flags |= MLX5_FLOW_ACTION_AGE;
12879 case RTE_FLOW_ACTION_TYPE_AGE:
12880 non_shared_age = action->conf;
12881 age_act_pos = actions_n++;
12882 action_flags |= MLX5_FLOW_ACTION_AGE;
12884 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12885 owner_idx = (uint32_t)(uintptr_t)action->conf;
12886 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12888 MLX5_ASSERT(cnt_act != NULL);
12890 * When creating meter drop flow in drop table, the
12891 * counter should not overwrite the rte flow counter.
12893 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12894 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12895 dev_flow->dv.actions[actions_n++] =
12898 if (flow->counter == 0) {
12899 flow->counter = owner_idx;
12901 (&cnt_act->shared_info.refcnt,
12902 1, __ATOMIC_RELAXED);
12904 /* Save information first, will apply later. */
12905 action_flags |= MLX5_FLOW_ACTION_COUNT;
12908 case RTE_FLOW_ACTION_TYPE_COUNT:
12909 if (!priv->sh->devx) {
12910 return rte_flow_error_set
12912 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12914 "count action not supported");
12916 /* Save information first, will apply later. */
12917 count = action->conf;
12918 action_flags |= MLX5_FLOW_ACTION_COUNT;
12920 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12921 dev_flow->dv.actions[actions_n++] =
12922 priv->sh->pop_vlan_action;
12923 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12925 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12926 if (!(action_flags &
12927 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12928 flow_dev_get_vlan_info_from_items(items, &vlan);
12929 vlan.eth_proto = rte_be_to_cpu_16
12930 ((((const struct rte_flow_action_of_push_vlan *)
12931 actions->conf)->ethertype));
12932 found_action = mlx5_flow_find_action
12934 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12936 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12937 found_action = mlx5_flow_find_action
12939 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12941 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12942 if (flow_dv_create_action_push_vlan
12943 (dev, attr, &vlan, dev_flow, error))
12945 dev_flow->dv.actions[actions_n++] =
12946 dev_flow->dv.push_vlan_res->action;
12947 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12949 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12950 /* of_vlan_push action handled this action */
12951 MLX5_ASSERT(action_flags &
12952 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12954 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12955 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12957 flow_dev_get_vlan_info_from_items(items, &vlan);
12958 mlx5_update_vlan_vid_pcp(actions, &vlan);
12959 /* If no VLAN push - this is a modify header action */
12960 if (flow_dv_convert_action_modify_vlan_vid
12961 (mhdr_res, actions, error))
12963 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12965 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12966 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12967 if (flow_dv_create_action_l2_encap(dev, actions,
12972 dev_flow->dv.actions[actions_n++] =
12973 dev_flow->dv.encap_decap->action;
12974 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12975 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12976 sample_act->action_flags |=
12977 MLX5_FLOW_ACTION_ENCAP;
12979 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12980 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12981 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12985 dev_flow->dv.actions[actions_n++] =
12986 dev_flow->dv.encap_decap->action;
12987 action_flags |= MLX5_FLOW_ACTION_DECAP;
12989 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
12990 /* Handle encap with preceding decap. */
12991 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
12992 if (flow_dv_create_action_raw_encap
12993 (dev, actions, dev_flow, attr, error))
12995 dev_flow->dv.actions[actions_n++] =
12996 dev_flow->dv.encap_decap->action;
12998 /* Handle encap without preceding decap. */
12999 if (flow_dv_create_action_l2_encap
13000 (dev, actions, dev_flow, attr->transfer,
13003 dev_flow->dv.actions[actions_n++] =
13004 dev_flow->dv.encap_decap->action;
13006 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13007 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13008 sample_act->action_flags |=
13009 MLX5_FLOW_ACTION_ENCAP;
13011 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13012 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13014 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13015 if (flow_dv_create_action_l2_decap
13016 (dev, dev_flow, attr->transfer, error))
13018 dev_flow->dv.actions[actions_n++] =
13019 dev_flow->dv.encap_decap->action;
13021 /* If decap is followed by encap, handle it at encap. */
13022 action_flags |= MLX5_FLOW_ACTION_DECAP;
13024 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13025 dev_flow->dv.actions[actions_n++] =
13026 (void *)(uintptr_t)action->conf;
13027 action_flags |= MLX5_FLOW_ACTION_JUMP;
13029 case RTE_FLOW_ACTION_TYPE_JUMP:
13030 jump_group = ((const struct rte_flow_action_jump *)
13031 action->conf)->group;
13032 grp_info.std_tbl_fix = 0;
13033 if (dev_flow->skip_scale &
13034 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13035 grp_info.skip_scale = 1;
13037 grp_info.skip_scale = 0;
13038 ret = mlx5_flow_group_to_table(dev, tunnel,
13044 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13046 !!dev_flow->external,
13047 tunnel, jump_group, 0,
13050 return rte_flow_error_set
13052 RTE_FLOW_ERROR_TYPE_ACTION,
13054 "cannot create jump action.");
13055 if (flow_dv_jump_tbl_resource_register
13056 (dev, tbl, dev_flow, error)) {
13057 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13058 return rte_flow_error_set
13060 RTE_FLOW_ERROR_TYPE_ACTION,
13062 "cannot create jump action.");
13064 dev_flow->dv.actions[actions_n++] =
13065 dev_flow->dv.jump->action;
13066 action_flags |= MLX5_FLOW_ACTION_JUMP;
13067 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13068 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13071 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13072 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13073 if (flow_dv_convert_action_modify_mac
13074 (mhdr_res, actions, error))
13076 action_flags |= actions->type ==
13077 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13078 MLX5_FLOW_ACTION_SET_MAC_SRC :
13079 MLX5_FLOW_ACTION_SET_MAC_DST;
13081 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13082 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13083 if (flow_dv_convert_action_modify_ipv4
13084 (mhdr_res, actions, error))
13086 action_flags |= actions->type ==
13087 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13088 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13089 MLX5_FLOW_ACTION_SET_IPV4_DST;
13091 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13092 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13093 if (flow_dv_convert_action_modify_ipv6
13094 (mhdr_res, actions, error))
13096 action_flags |= actions->type ==
13097 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13098 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13099 MLX5_FLOW_ACTION_SET_IPV6_DST;
13101 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13102 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13103 if (flow_dv_convert_action_modify_tp
13104 (mhdr_res, actions, items,
13105 &flow_attr, dev_flow, !!(action_flags &
13106 MLX5_FLOW_ACTION_DECAP), error))
13108 action_flags |= actions->type ==
13109 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13110 MLX5_FLOW_ACTION_SET_TP_SRC :
13111 MLX5_FLOW_ACTION_SET_TP_DST;
13113 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13114 if (flow_dv_convert_action_modify_dec_ttl
13115 (mhdr_res, items, &flow_attr, dev_flow,
13117 MLX5_FLOW_ACTION_DECAP), error))
13119 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13121 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13122 if (flow_dv_convert_action_modify_ttl
13123 (mhdr_res, actions, items, &flow_attr,
13124 dev_flow, !!(action_flags &
13125 MLX5_FLOW_ACTION_DECAP), error))
13127 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13129 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13130 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13131 if (flow_dv_convert_action_modify_tcp_seq
13132 (mhdr_res, actions, error))
13134 action_flags |= actions->type ==
13135 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13136 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13137 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13140 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13141 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13142 if (flow_dv_convert_action_modify_tcp_ack
13143 (mhdr_res, actions, error))
13145 action_flags |= actions->type ==
13146 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13147 MLX5_FLOW_ACTION_INC_TCP_ACK :
13148 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13150 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13151 if (flow_dv_convert_action_set_reg
13152 (mhdr_res, actions, error))
13154 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13156 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13157 if (flow_dv_convert_action_copy_mreg
13158 (dev, mhdr_res, actions, error))
13160 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13162 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13163 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13164 dev_flow->handle->fate_action =
13165 MLX5_FLOW_FATE_DEFAULT_MISS;
13167 case RTE_FLOW_ACTION_TYPE_METER:
13169 return rte_flow_error_set(error, rte_errno,
13170 RTE_FLOW_ERROR_TYPE_ACTION,
13171 NULL, "Failed to get meter in flow.");
13172 /* Set the meter action. */
13173 dev_flow->dv.actions[actions_n++] =
13174 wks->fm->meter_action;
13175 action_flags |= MLX5_FLOW_ACTION_METER;
13177 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13178 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13181 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13183 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13184 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13187 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13189 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13190 sample_act_pos = actions_n;
13191 sample = (const struct rte_flow_action_sample *)
13194 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13195 /* put encap action into group if work with port id */
13196 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13197 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13198 sample_act->action_flags |=
13199 MLX5_FLOW_ACTION_ENCAP;
13201 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13202 if (flow_dv_convert_action_modify_field
13203 (dev, mhdr_res, actions, attr, error))
13205 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13207 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13208 owner_idx = (uint32_t)(uintptr_t)action->conf;
13209 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13211 return rte_flow_error_set(error, EINVAL,
13212 RTE_FLOW_ERROR_TYPE_ACTION,
13214 "Failed to get CT object.");
13215 if (mlx5_aso_ct_available(priv->sh, ct))
13216 return rte_flow_error_set(error, rte_errno,
13217 RTE_FLOW_ERROR_TYPE_ACTION,
13219 "CT is unavailable.");
13220 if (ct->is_original)
13221 dev_flow->dv.actions[actions_n] =
13222 ct->dr_action_orig;
13224 dev_flow->dv.actions[actions_n] =
13225 ct->dr_action_rply;
13226 if (flow->ct == 0) {
13227 flow->indirect_type =
13228 MLX5_INDIRECT_ACTION_TYPE_CT;
13229 flow->ct = owner_idx;
13230 __atomic_fetch_add(&ct->refcnt, 1,
13234 action_flags |= MLX5_FLOW_ACTION_CT;
13236 case RTE_FLOW_ACTION_TYPE_END:
13237 actions_end = true;
13238 if (mhdr_res->actions_num) {
13239 /* create modify action if needed. */
13240 if (flow_dv_modify_hdr_resource_register
13241 (dev, mhdr_res, dev_flow, error))
13243 dev_flow->dv.actions[modify_action_position] =
13244 handle->dvh.modify_hdr->action;
13247 * Handle AGE and COUNT action by single HW counter
13248 * when they are not shared.
13250 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13251 if ((non_shared_age && count) ||
13252 !(priv->sh->flow_hit_aso_en &&
13253 (attr->group || attr->transfer))) {
13254 /* Creates age by counters. */
13255 cnt_act = flow_dv_prepare_counter
13262 dev_flow->dv.actions[age_act_pos] =
13266 if (!flow->age && non_shared_age) {
13267 flow->age = flow_dv_aso_age_alloc
13271 flow_dv_aso_age_params_init
13273 non_shared_age->context ?
13274 non_shared_age->context :
13275 (void *)(uintptr_t)
13276 (dev_flow->flow_idx),
13277 non_shared_age->timeout);
13279 age_act = flow_aso_age_get_by_idx(dev,
13281 dev_flow->dv.actions[age_act_pos] =
13282 age_act->dr_action;
13284 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13286 * Create one count action, to be used
13287 * by all sub-flows.
13289 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13294 dev_flow->dv.actions[actions_n++] =
13300 if (mhdr_res->actions_num &&
13301 modify_action_position == UINT32_MAX)
13302 modify_action_position = actions_n++;
13304 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13305 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13306 int item_type = items->type;
13308 if (!mlx5_flow_os_item_supported(item_type))
13309 return rte_flow_error_set(error, ENOTSUP,
13310 RTE_FLOW_ERROR_TYPE_ITEM,
13311 NULL, "item not supported");
13312 switch (item_type) {
13313 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13314 flow_dv_translate_item_port_id
13315 (dev, match_mask, match_value, items, attr);
13316 last_item = MLX5_FLOW_ITEM_PORT_ID;
13318 case RTE_FLOW_ITEM_TYPE_ETH:
13319 flow_dv_translate_item_eth(match_mask, match_value,
13321 dev_flow->dv.group);
13322 matcher.priority = action_flags &
13323 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13324 !dev_flow->external ?
13325 MLX5_PRIORITY_MAP_L3 :
13326 MLX5_PRIORITY_MAP_L2;
13327 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13328 MLX5_FLOW_LAYER_OUTER_L2;
13330 case RTE_FLOW_ITEM_TYPE_VLAN:
13331 flow_dv_translate_item_vlan(dev_flow,
13332 match_mask, match_value,
13334 dev_flow->dv.group);
13335 matcher.priority = MLX5_PRIORITY_MAP_L2;
13336 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13337 MLX5_FLOW_LAYER_INNER_VLAN) :
13338 (MLX5_FLOW_LAYER_OUTER_L2 |
13339 MLX5_FLOW_LAYER_OUTER_VLAN);
13341 case RTE_FLOW_ITEM_TYPE_IPV4:
13342 mlx5_flow_tunnel_ip_check(items, next_protocol,
13343 &item_flags, &tunnel);
13344 flow_dv_translate_item_ipv4(match_mask, match_value,
13346 dev_flow->dv.group);
13347 matcher.priority = MLX5_PRIORITY_MAP_L3;
13348 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13349 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13350 if (items->mask != NULL &&
13351 ((const struct rte_flow_item_ipv4 *)
13352 items->mask)->hdr.next_proto_id) {
13354 ((const struct rte_flow_item_ipv4 *)
13355 (items->spec))->hdr.next_proto_id;
13357 ((const struct rte_flow_item_ipv4 *)
13358 (items->mask))->hdr.next_proto_id;
13360 /* Reset for inner layer. */
13361 next_protocol = 0xff;
13364 case RTE_FLOW_ITEM_TYPE_IPV6:
13365 mlx5_flow_tunnel_ip_check(items, next_protocol,
13366 &item_flags, &tunnel);
13367 flow_dv_translate_item_ipv6(match_mask, match_value,
13369 dev_flow->dv.group);
13370 matcher.priority = MLX5_PRIORITY_MAP_L3;
13371 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13372 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13373 if (items->mask != NULL &&
13374 ((const struct rte_flow_item_ipv6 *)
13375 items->mask)->hdr.proto) {
13377 ((const struct rte_flow_item_ipv6 *)
13378 items->spec)->hdr.proto;
13380 ((const struct rte_flow_item_ipv6 *)
13381 items->mask)->hdr.proto;
13383 /* Reset for inner layer. */
13384 next_protocol = 0xff;
13387 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13388 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13391 last_item = tunnel ?
13392 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13393 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13394 if (items->mask != NULL &&
13395 ((const struct rte_flow_item_ipv6_frag_ext *)
13396 items->mask)->hdr.next_header) {
13398 ((const struct rte_flow_item_ipv6_frag_ext *)
13399 items->spec)->hdr.next_header;
13401 ((const struct rte_flow_item_ipv6_frag_ext *)
13402 items->mask)->hdr.next_header;
13404 /* Reset for inner layer. */
13405 next_protocol = 0xff;
13408 case RTE_FLOW_ITEM_TYPE_TCP:
13409 flow_dv_translate_item_tcp(match_mask, match_value,
13411 matcher.priority = MLX5_PRIORITY_MAP_L4;
13412 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13413 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13415 case RTE_FLOW_ITEM_TYPE_UDP:
13416 flow_dv_translate_item_udp(match_mask, match_value,
13418 matcher.priority = MLX5_PRIORITY_MAP_L4;
13419 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13420 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13422 case RTE_FLOW_ITEM_TYPE_GRE:
13423 flow_dv_translate_item_gre(match_mask, match_value,
13425 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13426 last_item = MLX5_FLOW_LAYER_GRE;
13428 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13429 flow_dv_translate_item_gre_key(match_mask,
13430 match_value, items);
13431 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13433 case RTE_FLOW_ITEM_TYPE_NVGRE:
13434 flow_dv_translate_item_nvgre(match_mask, match_value,
13436 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13437 last_item = MLX5_FLOW_LAYER_GRE;
13439 case RTE_FLOW_ITEM_TYPE_VXLAN:
13440 flow_dv_translate_item_vxlan(dev, attr,
13441 match_mask, match_value,
13443 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13444 last_item = MLX5_FLOW_LAYER_VXLAN;
13446 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13447 flow_dv_translate_item_vxlan_gpe(match_mask,
13448 match_value, items,
13450 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13451 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13453 case RTE_FLOW_ITEM_TYPE_GENEVE:
13454 flow_dv_translate_item_geneve(match_mask, match_value,
13456 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13457 last_item = MLX5_FLOW_LAYER_GENEVE;
13459 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13460 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13464 return rte_flow_error_set(error, -ret,
13465 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13466 "cannot create GENEVE TLV option");
13467 flow->geneve_tlv_option = 1;
13468 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13470 case RTE_FLOW_ITEM_TYPE_MPLS:
13471 flow_dv_translate_item_mpls(match_mask, match_value,
13472 items, last_item, tunnel);
13473 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13474 last_item = MLX5_FLOW_LAYER_MPLS;
13476 case RTE_FLOW_ITEM_TYPE_MARK:
13477 flow_dv_translate_item_mark(dev, match_mask,
13478 match_value, items);
13479 last_item = MLX5_FLOW_ITEM_MARK;
13481 case RTE_FLOW_ITEM_TYPE_META:
13482 flow_dv_translate_item_meta(dev, match_mask,
13483 match_value, attr, items);
13484 last_item = MLX5_FLOW_ITEM_METADATA;
13486 case RTE_FLOW_ITEM_TYPE_ICMP:
13487 flow_dv_translate_item_icmp(match_mask, match_value,
13489 last_item = MLX5_FLOW_LAYER_ICMP;
13491 case RTE_FLOW_ITEM_TYPE_ICMP6:
13492 flow_dv_translate_item_icmp6(match_mask, match_value,
13494 last_item = MLX5_FLOW_LAYER_ICMP6;
13496 case RTE_FLOW_ITEM_TYPE_TAG:
13497 flow_dv_translate_item_tag(dev, match_mask,
13498 match_value, items);
13499 last_item = MLX5_FLOW_ITEM_TAG;
13501 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13502 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13503 match_value, items);
13504 last_item = MLX5_FLOW_ITEM_TAG;
13506 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13507 flow_dv_translate_item_tx_queue(dev, match_mask,
13510 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13512 case RTE_FLOW_ITEM_TYPE_GTP:
13513 flow_dv_translate_item_gtp(match_mask, match_value,
13515 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13516 last_item = MLX5_FLOW_LAYER_GTP;
13518 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13519 ret = flow_dv_translate_item_gtp_psc(match_mask,
13523 return rte_flow_error_set(error, -ret,
13524 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13525 "cannot create GTP PSC item");
13526 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13528 case RTE_FLOW_ITEM_TYPE_ECPRI:
13529 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13530 /* Create it only the first time to be used. */
13531 ret = mlx5_flex_parser_ecpri_alloc(dev);
13533 return rte_flow_error_set
13535 RTE_FLOW_ERROR_TYPE_ITEM,
13537 "cannot create eCPRI parser");
13539 flow_dv_translate_item_ecpri(dev, match_mask,
13540 match_value, items,
13542 /* No other protocol should follow eCPRI layer. */
13543 last_item = MLX5_FLOW_LAYER_ECPRI;
13545 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13546 flow_dv_translate_item_integrity(items, integrity_items,
13549 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13550 flow_dv_translate_item_aso_ct(dev, match_mask,
13551 match_value, items);
13553 case RTE_FLOW_ITEM_TYPE_FLEX:
13554 flow_dv_translate_item_flex(dev, match_mask,
13555 match_value, items,
13556 dev_flow, tunnel != 0);
13557 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13558 MLX5_FLOW_ITEM_OUTER_FLEX;
13563 item_flags |= last_item;
13566 * When E-Switch mode is enabled, we have two cases where we need to
13567 * set the source port manually.
13568 * The first one, is in case of Nic steering rule, and the second is
13569 * E-Switch rule where no port_id item was found. In both cases
13570 * the source port is set according the current port in use.
13572 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13573 (priv->representor || priv->master)) {
13574 if (flow_dv_translate_item_port_id(dev, match_mask,
13575 match_value, NULL, attr))
13578 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13579 flow_dv_translate_item_integrity_post(match_mask, match_value,
13583 #ifdef RTE_LIBRTE_MLX5_DEBUG
13584 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13585 dev_flow->dv.value.buf));
13588 * Layers may be already initialized from prefix flow if this dev_flow
13589 * is the suffix flow.
13591 handle->layers |= item_flags;
13592 if (action_flags & MLX5_FLOW_ACTION_RSS)
13593 flow_dv_hashfields_set(dev_flow, rss_desc);
13594 /* If has RSS action in the sample action, the Sample/Mirror resource
13595 * should be registered after the hash filed be update.
13597 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13598 ret = flow_dv_translate_action_sample(dev,
13607 ret = flow_dv_create_action_sample(dev,
13616 return rte_flow_error_set
13618 RTE_FLOW_ERROR_TYPE_ACTION,
13620 "cannot create sample action");
13621 if (num_of_dest > 1) {
13622 dev_flow->dv.actions[sample_act_pos] =
13623 dev_flow->dv.dest_array_res->action;
13625 dev_flow->dv.actions[sample_act_pos] =
13626 dev_flow->dv.sample_res->verbs_action;
13630 * For multiple destination (sample action with ratio=1), the encap
13631 * action and port id action will be combined into group action.
13632 * So need remove the original these actions in the flow and only
13633 * use the sample action instead of.
13635 if (num_of_dest > 1 &&
13636 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13638 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13640 for (i = 0; i < actions_n; i++) {
13641 if ((sample_act->dr_encap_action &&
13642 sample_act->dr_encap_action ==
13643 dev_flow->dv.actions[i]) ||
13644 (sample_act->dr_port_id_action &&
13645 sample_act->dr_port_id_action ==
13646 dev_flow->dv.actions[i]) ||
13647 (sample_act->dr_jump_action &&
13648 sample_act->dr_jump_action ==
13649 dev_flow->dv.actions[i]))
13651 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13653 memcpy((void *)dev_flow->dv.actions,
13654 (void *)temp_actions,
13655 tmp_actions_n * sizeof(void *));
13656 actions_n = tmp_actions_n;
13658 dev_flow->dv.actions_n = actions_n;
13659 dev_flow->act_flags = action_flags;
13660 if (wks->skip_matcher_reg)
13662 /* Register matcher. */
13663 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13664 matcher.mask.size);
13665 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13667 dev_flow->external);
13669 * When creating meter drop flow in drop table, using original
13670 * 5-tuple match, the matcher priority should be lower than
13673 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13674 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13675 matcher.priority <= MLX5_REG_BITS)
13676 matcher.priority += MLX5_REG_BITS;
13677 /* reserved field no needs to be set to 0 here. */
13678 tbl_key.is_fdb = attr->transfer;
13679 tbl_key.is_egress = attr->egress;
13680 tbl_key.level = dev_flow->dv.group;
13681 tbl_key.id = dev_flow->dv.table_id;
13682 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13683 tunnel, attr->group, error))
13689 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13692 * @param[in, out] action
13693 * Shred RSS action holding hash RX queue objects.
13694 * @param[in] hash_fields
13695 * Defines combination of packet fields to participate in RX hash.
13696 * @param[in] tunnel
13698 * @param[in] hrxq_idx
13699 * Hash RX queue index to set.
13702 * 0 on success, otherwise negative errno value.
13705 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13706 const uint64_t hash_fields,
13709 uint32_t *hrxqs = action->hrxq;
13711 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13712 case MLX5_RSS_HASH_IPV4:
13713 /* fall-through. */
13714 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13715 /* fall-through. */
13716 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13717 hrxqs[0] = hrxq_idx;
13719 case MLX5_RSS_HASH_IPV4_TCP:
13720 /* fall-through. */
13721 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13722 /* fall-through. */
13723 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13724 hrxqs[1] = hrxq_idx;
13726 case MLX5_RSS_HASH_IPV4_UDP:
13727 /* fall-through. */
13728 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13729 /* fall-through. */
13730 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13731 hrxqs[2] = hrxq_idx;
13733 case MLX5_RSS_HASH_IPV6:
13734 /* fall-through. */
13735 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13736 /* fall-through. */
13737 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13738 hrxqs[3] = hrxq_idx;
13740 case MLX5_RSS_HASH_IPV6_TCP:
13741 /* fall-through. */
13742 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13743 /* fall-through. */
13744 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13745 hrxqs[4] = hrxq_idx;
13747 case MLX5_RSS_HASH_IPV6_UDP:
13748 /* fall-through. */
13749 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13750 /* fall-through. */
13751 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13752 hrxqs[5] = hrxq_idx;
13754 case MLX5_RSS_HASH_NONE:
13755 hrxqs[6] = hrxq_idx;
13763 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13767 * Pointer to the Ethernet device structure.
13769 * Shared RSS action ID holding hash RX queue objects.
13770 * @param[in] hash_fields
13771 * Defines combination of packet fields to participate in RX hash.
13772 * @param[in] tunnel
13776 * Valid hash RX queue index, otherwise 0.
13779 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13780 const uint64_t hash_fields)
13782 struct mlx5_priv *priv = dev->data->dev_private;
13783 struct mlx5_shared_action_rss *shared_rss =
13784 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13785 const uint32_t *hrxqs = shared_rss->hrxq;
13787 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13788 case MLX5_RSS_HASH_IPV4:
13789 /* fall-through. */
13790 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13791 /* fall-through. */
13792 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13794 case MLX5_RSS_HASH_IPV4_TCP:
13795 /* fall-through. */
13796 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13797 /* fall-through. */
13798 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13800 case MLX5_RSS_HASH_IPV4_UDP:
13801 /* fall-through. */
13802 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13803 /* fall-through. */
13804 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13806 case MLX5_RSS_HASH_IPV6:
13807 /* fall-through. */
13808 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13809 /* fall-through. */
13810 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13812 case MLX5_RSS_HASH_IPV6_TCP:
13813 /* fall-through. */
13814 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13815 /* fall-through. */
13816 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13818 case MLX5_RSS_HASH_IPV6_UDP:
13819 /* fall-through. */
13820 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13821 /* fall-through. */
13822 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13824 case MLX5_RSS_HASH_NONE:
13833 * Apply the flow to the NIC, lock free,
13834 * (mutex should be acquired by caller).
13837 * Pointer to the Ethernet device structure.
13838 * @param[in, out] flow
13839 * Pointer to flow structure.
13840 * @param[out] error
13841 * Pointer to error structure.
13844 * 0 on success, a negative errno value otherwise and rte_errno is set.
13847 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13848 struct rte_flow_error *error)
13850 struct mlx5_flow_dv_workspace *dv;
13851 struct mlx5_flow_handle *dh;
13852 struct mlx5_flow_handle_dv *dv_h;
13853 struct mlx5_flow *dev_flow;
13854 struct mlx5_priv *priv = dev->data->dev_private;
13855 uint32_t handle_idx;
13859 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13860 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13864 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13865 dev_flow = &wks->flows[idx];
13866 dv = &dev_flow->dv;
13867 dh = dev_flow->handle;
13870 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13871 if (dv->transfer) {
13872 MLX5_ASSERT(priv->sh->dr_drop_action);
13873 dv->actions[n++] = priv->sh->dr_drop_action;
13875 #ifdef HAVE_MLX5DV_DR
13876 /* DR supports drop action placeholder. */
13877 MLX5_ASSERT(priv->sh->dr_drop_action);
13878 dv->actions[n++] = dv->group ?
13879 priv->sh->dr_drop_action :
13880 priv->root_drop_action;
13882 /* For DV we use the explicit drop queue. */
13883 MLX5_ASSERT(priv->drop_queue.hrxq);
13885 priv->drop_queue.hrxq->action;
13888 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13889 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13890 struct mlx5_hrxq *hrxq;
13893 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13899 "cannot get hash queue");
13902 dh->rix_hrxq = hrxq_idx;
13903 dv->actions[n++] = hrxq->action;
13904 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13905 struct mlx5_hrxq *hrxq = NULL;
13908 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13909 rss_desc->shared_rss,
13910 dev_flow->hash_fields);
13912 hrxq = mlx5_ipool_get
13913 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13918 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13919 "cannot get hash queue");
13922 dh->rix_srss = rss_desc->shared_rss;
13923 dv->actions[n++] = hrxq->action;
13924 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13925 if (!priv->sh->default_miss_action) {
13928 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13929 "default miss action not be created.");
13932 dv->actions[n++] = priv->sh->default_miss_action;
13934 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13935 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13936 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13937 (void *)&dv->value, n,
13938 dv->actions, &dh->drv_flow);
13942 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13944 (!priv->config.allow_duplicate_pattern &&
13946 "duplicating pattern is not allowed" :
13947 "hardware refuses to create flow");
13950 if (priv->vmwa_context &&
13951 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13953 * The rule contains the VLAN pattern.
13954 * For VF we are going to create VLAN
13955 * interface to make hypervisor set correct
13956 * e-Switch vport context.
13958 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13963 err = rte_errno; /* Save rte_errno before cleanup. */
13964 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13965 handle_idx, dh, next) {
13966 /* hrxq is union, don't clear it if the flag is not set. */
13967 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13968 mlx5_hrxq_release(dev, dh->rix_hrxq);
13970 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13973 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13974 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13976 rte_errno = err; /* Restore rte_errno. */
13981 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
13982 struct mlx5_list_entry *entry)
13984 struct mlx5_flow_dv_matcher *resource = container_of(entry,
13988 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
13989 mlx5_free(resource);
13993 * Release the flow matcher.
13996 * Pointer to Ethernet device.
13998 * Index to port ID action resource.
14001 * 1 while a reference on it exists, 0 when freed.
14004 flow_dv_matcher_release(struct rte_eth_dev *dev,
14005 struct mlx5_flow_handle *handle)
14007 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14008 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14009 typeof(*tbl), tbl);
14012 MLX5_ASSERT(matcher->matcher_object);
14013 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14014 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14019 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14021 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14022 struct mlx5_flow_dv_encap_decap_resource *res =
14023 container_of(entry, typeof(*res), entry);
14025 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14026 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14030 * Release an encap/decap resource.
14033 * Pointer to Ethernet device.
14034 * @param encap_decap_idx
14035 * Index of encap decap resource.
14038 * 1 while a reference on it exists, 0 when freed.
14041 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14042 uint32_t encap_decap_idx)
14044 struct mlx5_priv *priv = dev->data->dev_private;
14045 struct mlx5_flow_dv_encap_decap_resource *resource;
14047 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14051 MLX5_ASSERT(resource->action);
14052 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14056 * Release an jump to table action resource.
14059 * Pointer to Ethernet device.
14061 * Index to the jump action resource.
14064 * 1 while a reference on it exists, 0 when freed.
14067 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14070 struct mlx5_priv *priv = dev->data->dev_private;
14071 struct mlx5_flow_tbl_data_entry *tbl_data;
14073 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14077 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14081 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14083 struct mlx5_flow_dv_modify_hdr_resource *res =
14084 container_of(entry, typeof(*res), entry);
14085 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14087 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14088 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14092 * Release a modify-header resource.
14095 * Pointer to Ethernet device.
14097 * Pointer to mlx5_flow_handle.
14100 * 1 while a reference on it exists, 0 when freed.
14103 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14104 struct mlx5_flow_handle *handle)
14106 struct mlx5_priv *priv = dev->data->dev_private;
14107 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14109 MLX5_ASSERT(entry->action);
14110 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14114 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14116 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14117 struct mlx5_flow_dv_port_id_action_resource *resource =
14118 container_of(entry, typeof(*resource), entry);
14120 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14121 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14125 * Release port ID action resource.
14128 * Pointer to Ethernet device.
14130 * Pointer to mlx5_flow_handle.
14133 * 1 while a reference on it exists, 0 when freed.
14136 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14139 struct mlx5_priv *priv = dev->data->dev_private;
14140 struct mlx5_flow_dv_port_id_action_resource *resource;
14142 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14145 MLX5_ASSERT(resource->action);
14146 return mlx5_list_unregister(priv->sh->port_id_action_list,
14151 * Release shared RSS action resource.
14154 * Pointer to Ethernet device.
14156 * Shared RSS action index.
14159 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14161 struct mlx5_priv *priv = dev->data->dev_private;
14162 struct mlx5_shared_action_rss *shared_rss;
14164 shared_rss = mlx5_ipool_get
14165 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14166 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14170 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14172 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14173 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14174 container_of(entry, typeof(*resource), entry);
14176 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14177 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14181 * Release push vlan action resource.
14184 * Pointer to Ethernet device.
14186 * Pointer to mlx5_flow_handle.
14189 * 1 while a reference on it exists, 0 when freed.
14192 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14193 struct mlx5_flow_handle *handle)
14195 struct mlx5_priv *priv = dev->data->dev_private;
14196 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14197 uint32_t idx = handle->dvh.rix_push_vlan;
14199 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14202 MLX5_ASSERT(resource->action);
14203 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14208 * Release the fate resource.
14211 * Pointer to Ethernet device.
14213 * Pointer to mlx5_flow_handle.
14216 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14217 struct mlx5_flow_handle *handle)
14219 if (!handle->rix_fate)
14221 switch (handle->fate_action) {
14222 case MLX5_FLOW_FATE_QUEUE:
14223 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14224 mlx5_hrxq_release(dev, handle->rix_hrxq);
14226 case MLX5_FLOW_FATE_JUMP:
14227 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14229 case MLX5_FLOW_FATE_PORT_ID:
14230 flow_dv_port_id_action_resource_release(dev,
14231 handle->rix_port_id_action);
14234 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14237 handle->rix_fate = 0;
14241 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14242 struct mlx5_list_entry *entry)
14244 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14247 struct rte_eth_dev *dev = resource->dev;
14248 struct mlx5_priv *priv = dev->data->dev_private;
14250 if (resource->verbs_action)
14251 claim_zero(mlx5_flow_os_destroy_flow_action
14252 (resource->verbs_action));
14253 if (resource->normal_path_tbl)
14254 flow_dv_tbl_resource_release(MLX5_SH(dev),
14255 resource->normal_path_tbl);
14256 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14257 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14258 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14262 * Release an sample resource.
14265 * Pointer to Ethernet device.
14267 * Pointer to mlx5_flow_handle.
14270 * 1 while a reference on it exists, 0 when freed.
14273 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14274 struct mlx5_flow_handle *handle)
14276 struct mlx5_priv *priv = dev->data->dev_private;
14277 struct mlx5_flow_dv_sample_resource *resource;
14279 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14280 handle->dvh.rix_sample);
14283 MLX5_ASSERT(resource->verbs_action);
14284 return mlx5_list_unregister(priv->sh->sample_action_list,
14289 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14290 struct mlx5_list_entry *entry)
14292 struct mlx5_flow_dv_dest_array_resource *resource =
14293 container_of(entry, typeof(*resource), entry);
14294 struct rte_eth_dev *dev = resource->dev;
14295 struct mlx5_priv *priv = dev->data->dev_private;
14298 MLX5_ASSERT(resource->action);
14299 if (resource->action)
14300 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14301 for (; i < resource->num_of_dest; i++)
14302 flow_dv_sample_sub_actions_release(dev,
14303 &resource->sample_idx[i]);
14304 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14305 DRV_LOG(DEBUG, "destination array resource %p: removed",
14310 * Release an destination array resource.
14313 * Pointer to Ethernet device.
14315 * Pointer to mlx5_flow_handle.
14318 * 1 while a reference on it exists, 0 when freed.
14321 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14322 struct mlx5_flow_handle *handle)
14324 struct mlx5_priv *priv = dev->data->dev_private;
14325 struct mlx5_flow_dv_dest_array_resource *resource;
14327 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14328 handle->dvh.rix_dest_array);
14331 MLX5_ASSERT(resource->action);
14332 return mlx5_list_unregister(priv->sh->dest_array_list,
14337 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14339 struct mlx5_priv *priv = dev->data->dev_private;
14340 struct mlx5_dev_ctx_shared *sh = priv->sh;
14341 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14342 sh->geneve_tlv_option_resource;
14343 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14344 if (geneve_opt_resource) {
14345 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14346 __ATOMIC_RELAXED))) {
14347 claim_zero(mlx5_devx_cmd_destroy
14348 (geneve_opt_resource->obj));
14349 mlx5_free(sh->geneve_tlv_option_resource);
14350 sh->geneve_tlv_option_resource = NULL;
14353 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14357 * Remove the flow from the NIC but keeps it in memory.
14358 * Lock free, (mutex should be acquired by caller).
14361 * Pointer to Ethernet device.
14362 * @param[in, out] flow
14363 * Pointer to flow structure.
14366 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14368 struct mlx5_flow_handle *dh;
14369 uint32_t handle_idx;
14370 struct mlx5_priv *priv = dev->data->dev_private;
14374 handle_idx = flow->dev_handles;
14375 while (handle_idx) {
14376 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14380 if (dh->drv_flow) {
14381 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14382 dh->drv_flow = NULL;
14384 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14385 flow_dv_fate_resource_release(dev, dh);
14386 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14387 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14388 handle_idx = dh->next.next;
14393 * Remove the flow from the NIC and the memory.
14394 * Lock free, (mutex should be acquired by caller).
14397 * Pointer to the Ethernet device structure.
14398 * @param[in, out] flow
14399 * Pointer to flow structure.
14402 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14404 struct mlx5_flow_handle *dev_handle;
14405 struct mlx5_priv *priv = dev->data->dev_private;
14406 struct mlx5_flow_meter_info *fm = NULL;
14411 flow_dv_remove(dev, flow);
14412 if (flow->counter) {
14413 flow_dv_counter_free(dev, flow->counter);
14417 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14419 mlx5_flow_meter_detach(priv, fm);
14422 /* Keep the current age handling by default. */
14423 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14424 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14425 else if (flow->age)
14426 flow_dv_aso_age_release(dev, flow->age);
14427 if (flow->geneve_tlv_option) {
14428 flow_dv_geneve_tlv_option_resource_release(dev);
14429 flow->geneve_tlv_option = 0;
14431 while (flow->dev_handles) {
14432 uint32_t tmp_idx = flow->dev_handles;
14434 dev_handle = mlx5_ipool_get(priv->sh->ipool
14435 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14438 flow->dev_handles = dev_handle->next.next;
14439 while (dev_handle->flex_item) {
14440 int index = rte_bsf32(dev_handle->flex_item);
14442 mlx5_flex_release_index(dev, index);
14443 dev_handle->flex_item &= ~RTE_BIT32(index);
14445 if (dev_handle->dvh.matcher)
14446 flow_dv_matcher_release(dev, dev_handle);
14447 if (dev_handle->dvh.rix_sample)
14448 flow_dv_sample_resource_release(dev, dev_handle);
14449 if (dev_handle->dvh.rix_dest_array)
14450 flow_dv_dest_array_resource_release(dev, dev_handle);
14451 if (dev_handle->dvh.rix_encap_decap)
14452 flow_dv_encap_decap_resource_release(dev,
14453 dev_handle->dvh.rix_encap_decap);
14454 if (dev_handle->dvh.modify_hdr)
14455 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14456 if (dev_handle->dvh.rix_push_vlan)
14457 flow_dv_push_vlan_action_resource_release(dev,
14459 if (dev_handle->dvh.rix_tag)
14460 flow_dv_tag_release(dev,
14461 dev_handle->dvh.rix_tag);
14462 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14463 flow_dv_fate_resource_release(dev, dev_handle);
14465 srss = dev_handle->rix_srss;
14466 if (fm && dev_handle->is_meter_flow_id &&
14467 dev_handle->split_flow_id)
14468 mlx5_ipool_free(fm->flow_ipool,
14469 dev_handle->split_flow_id);
14470 else if (dev_handle->split_flow_id &&
14471 !dev_handle->is_meter_flow_id)
14472 mlx5_ipool_free(priv->sh->ipool
14473 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14474 dev_handle->split_flow_id);
14475 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14479 flow_dv_shared_rss_action_release(dev, srss);
14483 * Release array of hash RX queue objects.
14487 * Pointer to the Ethernet device structure.
14488 * @param[in, out] hrxqs
14489 * Array of hash RX queue objects.
14492 * Total number of references to hash RX queue objects in *hrxqs* array
14493 * after this operation.
14496 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14497 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14502 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14503 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14513 * Release all hash RX queue objects representing shared RSS action.
14516 * Pointer to the Ethernet device structure.
14517 * @param[in, out] action
14518 * Shared RSS action to remove hash RX queue objects from.
14521 * Total number of references to hash RX queue objects stored in *action*
14522 * after this operation.
14523 * Expected to be 0 if no external references held.
14526 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14527 struct mlx5_shared_action_rss *shared_rss)
14529 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14533 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14536 * Only one hash value is available for one L3+L4 combination:
14538 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14539 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14540 * same slot in mlx5_rss_hash_fields.
14543 * Pointer to the shared action RSS conf.
14544 * @param[in, out] hash_field
14545 * hash_field variable needed to be adjusted.
14551 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14552 uint64_t *hash_field)
14554 uint64_t rss_types = rss->origin.types;
14556 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14557 case MLX5_RSS_HASH_IPV4:
14558 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14559 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14560 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14561 *hash_field |= IBV_RX_HASH_DST_IPV4;
14562 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14563 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14565 *hash_field |= MLX5_RSS_HASH_IPV4;
14568 case MLX5_RSS_HASH_IPV6:
14569 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14570 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14571 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14572 *hash_field |= IBV_RX_HASH_DST_IPV6;
14573 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14574 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14576 *hash_field |= MLX5_RSS_HASH_IPV6;
14579 case MLX5_RSS_HASH_IPV4_UDP:
14580 /* fall-through. */
14581 case MLX5_RSS_HASH_IPV6_UDP:
14582 if (rss_types & RTE_ETH_RSS_UDP) {
14583 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14584 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14585 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14586 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14587 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14589 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14592 case MLX5_RSS_HASH_IPV4_TCP:
14593 /* fall-through. */
14594 case MLX5_RSS_HASH_IPV6_TCP:
14595 if (rss_types & RTE_ETH_RSS_TCP) {
14596 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14597 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14598 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14599 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14600 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14602 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14611 * Setup shared RSS action.
14612 * Prepare set of hash RX queue objects sufficient to handle all valid
14613 * hash_fields combinations (see enum ibv_rx_hash_fields).
14616 * Pointer to the Ethernet device structure.
14617 * @param[in] action_idx
14618 * Shared RSS action ipool index.
14619 * @param[in, out] action
14620 * Partially initialized shared RSS action.
14621 * @param[out] error
14622 * Perform verbose error reporting if not NULL. Initialized in case of
14626 * 0 on success, otherwise negative errno value.
14629 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14630 uint32_t action_idx,
14631 struct mlx5_shared_action_rss *shared_rss,
14632 struct rte_flow_error *error)
14634 struct mlx5_flow_rss_desc rss_desc = { 0 };
14638 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14639 return rte_flow_error_set(error, rte_errno,
14640 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14641 "cannot setup indirection table");
14643 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14644 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14645 rss_desc.const_q = shared_rss->origin.queue;
14646 rss_desc.queue_num = shared_rss->origin.queue_num;
14647 /* Set non-zero value to indicate a shared RSS. */
14648 rss_desc.shared_rss = action_idx;
14649 rss_desc.ind_tbl = shared_rss->ind_tbl;
14650 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14652 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14655 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14656 if (shared_rss->origin.level > 1) {
14657 hash_fields |= IBV_RX_HASH_INNER;
14660 rss_desc.tunnel = tunnel;
14661 rss_desc.hash_fields = hash_fields;
14662 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14666 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14667 "cannot get hash queue");
14668 goto error_hrxq_new;
14670 err = __flow_dv_action_rss_hrxq_set
14671 (shared_rss, hash_fields, hrxq_idx);
14677 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14678 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14679 shared_rss->ind_tbl = NULL;
14685 * Create shared RSS action.
14688 * Pointer to the Ethernet device structure.
14690 * Shared action configuration.
14692 * RSS action specification used to create shared action.
14693 * @param[out] error
14694 * Perform verbose error reporting if not NULL. Initialized in case of
14698 * A valid shared action ID in case of success, 0 otherwise and
14699 * rte_errno is set.
14702 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14703 const struct rte_flow_indir_action_conf *conf,
14704 const struct rte_flow_action_rss *rss,
14705 struct rte_flow_error *error)
14707 struct mlx5_priv *priv = dev->data->dev_private;
14708 struct mlx5_shared_action_rss *shared_rss = NULL;
14709 void *queue = NULL;
14710 struct rte_flow_action_rss *origin;
14711 const uint8_t *rss_key;
14712 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14715 RTE_SET_USED(conf);
14716 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14718 shared_rss = mlx5_ipool_zmalloc
14719 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14720 if (!shared_rss || !queue) {
14721 rte_flow_error_set(error, ENOMEM,
14722 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14723 "cannot allocate resource memory");
14724 goto error_rss_init;
14726 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14727 rte_flow_error_set(error, E2BIG,
14728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14729 "rss action number out of range");
14730 goto error_rss_init;
14732 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14733 sizeof(*shared_rss->ind_tbl),
14735 if (!shared_rss->ind_tbl) {
14736 rte_flow_error_set(error, ENOMEM,
14737 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14738 "cannot allocate resource memory");
14739 goto error_rss_init;
14741 memcpy(queue, rss->queue, queue_size);
14742 shared_rss->ind_tbl->queues = queue;
14743 shared_rss->ind_tbl->queues_n = rss->queue_num;
14744 origin = &shared_rss->origin;
14745 origin->func = rss->func;
14746 origin->level = rss->level;
14747 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14748 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14749 /* NULL RSS key indicates default RSS key. */
14750 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14751 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14752 origin->key = &shared_rss->key[0];
14753 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14754 origin->queue = queue;
14755 origin->queue_num = rss->queue_num;
14756 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14757 goto error_rss_init;
14758 rte_spinlock_init(&shared_rss->action_rss_sl);
14759 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14760 rte_spinlock_lock(&priv->shared_act_sl);
14761 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14762 &priv->rss_shared_actions, idx, shared_rss, next);
14763 rte_spinlock_unlock(&priv->shared_act_sl);
14767 if (shared_rss->ind_tbl)
14768 mlx5_free(shared_rss->ind_tbl);
14769 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14778 * Destroy the shared RSS action.
14779 * Release related hash RX queue objects.
14782 * Pointer to the Ethernet device structure.
14784 * The shared RSS action object ID to be removed.
14785 * @param[out] error
14786 * Perform verbose error reporting if not NULL. Initialized in case of
14790 * 0 on success, otherwise negative errno value.
14793 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14794 struct rte_flow_error *error)
14796 struct mlx5_priv *priv = dev->data->dev_private;
14797 struct mlx5_shared_action_rss *shared_rss =
14798 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14799 uint32_t old_refcnt = 1;
14801 uint16_t *queue = NULL;
14804 return rte_flow_error_set(error, EINVAL,
14805 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14806 "invalid shared action");
14807 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14808 0, 0, __ATOMIC_ACQUIRE,
14810 return rte_flow_error_set(error, EBUSY,
14811 RTE_FLOW_ERROR_TYPE_ACTION,
14813 "shared rss has references");
14814 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14816 return rte_flow_error_set(error, EBUSY,
14817 RTE_FLOW_ERROR_TYPE_ACTION,
14819 "shared rss hrxq has references");
14820 queue = shared_rss->ind_tbl->queues;
14821 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14823 return rte_flow_error_set(error, EBUSY,
14824 RTE_FLOW_ERROR_TYPE_ACTION,
14826 "shared rss indirection table has"
14829 rte_spinlock_lock(&priv->shared_act_sl);
14830 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14831 &priv->rss_shared_actions, idx, shared_rss, next);
14832 rte_spinlock_unlock(&priv->shared_act_sl);
14833 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14839 * Create indirect action, lock free,
14840 * (mutex should be acquired by caller).
14841 * Dispatcher for action type specific call.
14844 * Pointer to the Ethernet device structure.
14846 * Shared action configuration.
14847 * @param[in] action
14848 * Action specification used to create indirect action.
14849 * @param[out] error
14850 * Perform verbose error reporting if not NULL. Initialized in case of
14854 * A valid shared action handle in case of success, NULL otherwise and
14855 * rte_errno is set.
14857 static struct rte_flow_action_handle *
14858 flow_dv_action_create(struct rte_eth_dev *dev,
14859 const struct rte_flow_indir_action_conf *conf,
14860 const struct rte_flow_action *action,
14861 struct rte_flow_error *err)
14863 struct mlx5_priv *priv = dev->data->dev_private;
14864 uint32_t age_idx = 0;
14868 switch (action->type) {
14869 case RTE_FLOW_ACTION_TYPE_RSS:
14870 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14871 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14872 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14874 case RTE_FLOW_ACTION_TYPE_AGE:
14875 age_idx = flow_dv_aso_age_alloc(dev, err);
14880 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14881 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14882 flow_dv_aso_age_params_init(dev, age_idx,
14883 ((const struct rte_flow_action_age *)
14884 action->conf)->context ?
14885 ((const struct rte_flow_action_age *)
14886 action->conf)->context :
14887 (void *)(uintptr_t)idx,
14888 ((const struct rte_flow_action_age *)
14889 action->conf)->timeout);
14892 case RTE_FLOW_ACTION_TYPE_COUNT:
14893 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14894 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14895 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14897 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14898 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14900 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14903 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14904 NULL, "action type not supported");
14907 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14911 * Destroy the indirect action.
14912 * Release action related resources on the NIC and the memory.
14913 * Lock free, (mutex should be acquired by caller).
14914 * Dispatcher for action type specific call.
14917 * Pointer to the Ethernet device structure.
14918 * @param[in] handle
14919 * The indirect action object handle to be removed.
14920 * @param[out] error
14921 * Perform verbose error reporting if not NULL. Initialized in case of
14925 * 0 on success, otherwise negative errno value.
14928 flow_dv_action_destroy(struct rte_eth_dev *dev,
14929 struct rte_flow_action_handle *handle,
14930 struct rte_flow_error *error)
14932 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14933 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14934 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14935 struct mlx5_flow_counter *cnt;
14936 uint32_t no_flow_refcnt = 1;
14940 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14941 return __flow_dv_action_rss_release(dev, idx, error);
14942 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14943 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14944 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14945 &no_flow_refcnt, 1, false,
14948 return rte_flow_error_set(error, EBUSY,
14949 RTE_FLOW_ERROR_TYPE_ACTION,
14951 "Indirect count action has references");
14952 flow_dv_counter_free(dev, idx);
14954 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14955 ret = flow_dv_aso_age_release(dev, idx);
14958 * In this case, the last flow has a reference will
14959 * actually release the age action.
14961 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14962 " released with references %d.", idx, ret);
14964 case MLX5_INDIRECT_ACTION_TYPE_CT:
14965 ret = flow_dv_aso_ct_release(dev, idx, error);
14969 DRV_LOG(DEBUG, "Connection tracking object %u still "
14970 "has references %d.", idx, ret);
14973 return rte_flow_error_set(error, ENOTSUP,
14974 RTE_FLOW_ERROR_TYPE_ACTION,
14976 "action type not supported");
14981 * Updates in place shared RSS action configuration.
14984 * Pointer to the Ethernet device structure.
14986 * The shared RSS action object ID to be updated.
14987 * @param[in] action_conf
14988 * RSS action specification used to modify *shared_rss*.
14989 * @param[out] error
14990 * Perform verbose error reporting if not NULL. Initialized in case of
14994 * 0 on success, otherwise negative errno value.
14995 * @note: currently only support update of RSS queues.
14998 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
14999 const struct rte_flow_action_rss *action_conf,
15000 struct rte_flow_error *error)
15002 struct mlx5_priv *priv = dev->data->dev_private;
15003 struct mlx5_shared_action_rss *shared_rss =
15004 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15006 void *queue = NULL;
15007 uint16_t *queue_old = NULL;
15008 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15011 return rte_flow_error_set(error, EINVAL,
15012 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15013 "invalid shared action to update");
15014 if (priv->obj_ops.ind_table_modify == NULL)
15015 return rte_flow_error_set(error, ENOTSUP,
15016 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15017 "cannot modify indirection table");
15018 queue = mlx5_malloc(MLX5_MEM_ZERO,
15019 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15022 return rte_flow_error_set(error, ENOMEM,
15023 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15025 "cannot allocate resource memory");
15026 memcpy(queue, action_conf->queue, queue_size);
15027 MLX5_ASSERT(shared_rss->ind_tbl);
15028 rte_spinlock_lock(&shared_rss->action_rss_sl);
15029 queue_old = shared_rss->ind_tbl->queues;
15030 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15031 queue, action_conf->queue_num, true);
15034 ret = rte_flow_error_set(error, rte_errno,
15035 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15036 "cannot update indirection table");
15038 mlx5_free(queue_old);
15039 shared_rss->origin.queue = queue;
15040 shared_rss->origin.queue_num = action_conf->queue_num;
15042 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15047 * Updates in place conntrack context or direction.
15048 * Context update should be synchronized.
15051 * Pointer to the Ethernet device structure.
15053 * The conntrack object ID to be updated.
15054 * @param[in] update
15055 * Pointer to the structure of information to update.
15056 * @param[out] error
15057 * Perform verbose error reporting if not NULL. Initialized in case of
15061 * 0 on success, otherwise negative errno value.
15064 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15065 const struct rte_flow_modify_conntrack *update,
15066 struct rte_flow_error *error)
15068 struct mlx5_priv *priv = dev->data->dev_private;
15069 struct mlx5_aso_ct_action *ct;
15070 const struct rte_flow_action_conntrack *new_prf;
15072 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15075 if (PORT_ID(priv) != owner)
15076 return rte_flow_error_set(error, EACCES,
15077 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15079 "CT object owned by another port");
15080 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15081 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15083 return rte_flow_error_set(error, ENOMEM,
15084 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15086 "CT object is inactive");
15087 new_prf = &update->new_ct;
15088 if (update->direction)
15089 ct->is_original = !!new_prf->is_original_dir;
15090 if (update->state) {
15091 /* Only validate the profile when it needs to be updated. */
15092 ret = mlx5_validate_action_ct(dev, new_prf, error);
15095 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15097 return rte_flow_error_set(error, EIO,
15098 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15100 "Failed to send CT context update WQE");
15101 /* Block until ready or a failure. */
15102 ret = mlx5_aso_ct_available(priv->sh, ct);
15104 rte_flow_error_set(error, rte_errno,
15105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15107 "Timeout to get the CT update");
15113 * Updates in place shared action configuration, lock free,
15114 * (mutex should be acquired by caller).
15117 * Pointer to the Ethernet device structure.
15118 * @param[in] handle
15119 * The indirect action object handle to be updated.
15120 * @param[in] update
15121 * Action specification used to modify the action pointed by *handle*.
15122 * *update* could be of same type with the action pointed by the *handle*
15123 * handle argument, or some other structures like a wrapper, depending on
15124 * the indirect action type.
15125 * @param[out] error
15126 * Perform verbose error reporting if not NULL. Initialized in case of
15130 * 0 on success, otherwise negative errno value.
15133 flow_dv_action_update(struct rte_eth_dev *dev,
15134 struct rte_flow_action_handle *handle,
15135 const void *update,
15136 struct rte_flow_error *err)
15138 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15139 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15140 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15141 const void *action_conf;
15144 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15145 action_conf = ((const struct rte_flow_action *)update)->conf;
15146 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15147 case MLX5_INDIRECT_ACTION_TYPE_CT:
15148 return __flow_dv_action_ct_update(dev, idx, update, err);
15150 return rte_flow_error_set(err, ENOTSUP,
15151 RTE_FLOW_ERROR_TYPE_ACTION,
15153 "action type update not supported");
15158 * Destroy the meter sub policy table rules.
15159 * Lock free, (mutex should be acquired by caller).
15162 * Pointer to Ethernet device.
15163 * @param[in] sub_policy
15164 * Pointer to meter sub policy table.
15167 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15168 struct mlx5_flow_meter_sub_policy *sub_policy)
15170 struct mlx5_priv *priv = dev->data->dev_private;
15171 struct mlx5_flow_tbl_data_entry *tbl;
15172 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15173 struct mlx5_flow_meter_info *next_fm;
15174 struct mlx5_sub_policy_color_rule *color_rule;
15178 for (i = 0; i < RTE_COLORS; i++) {
15180 if (i == RTE_COLOR_GREEN && policy &&
15181 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15182 next_fm = mlx5_flow_meter_find(priv,
15183 policy->act_cnt[i].next_mtr_id, NULL);
15184 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15186 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15187 tbl = container_of(color_rule->matcher->tbl,
15188 typeof(*tbl), tbl);
15189 mlx5_list_unregister(tbl->matchers,
15190 &color_rule->matcher->entry);
15191 TAILQ_REMOVE(&sub_policy->color_rules[i],
15192 color_rule, next_port);
15193 mlx5_free(color_rule);
15195 mlx5_flow_meter_detach(priv, next_fm);
15198 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15199 if (sub_policy->rix_hrxq[i]) {
15200 if (policy && !policy->is_hierarchy)
15201 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15202 sub_policy->rix_hrxq[i] = 0;
15204 if (sub_policy->jump_tbl[i]) {
15205 flow_dv_tbl_resource_release(MLX5_SH(dev),
15206 sub_policy->jump_tbl[i]);
15207 sub_policy->jump_tbl[i] = NULL;
15210 if (sub_policy->tbl_rsc) {
15211 flow_dv_tbl_resource_release(MLX5_SH(dev),
15212 sub_policy->tbl_rsc);
15213 sub_policy->tbl_rsc = NULL;
15218 * Destroy policy rules, lock free,
15219 * (mutex should be acquired by caller).
15220 * Dispatcher for action type specific call.
15223 * Pointer to the Ethernet device structure.
15224 * @param[in] mtr_policy
15225 * Meter policy struct.
15228 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15229 struct mlx5_flow_meter_policy *mtr_policy)
15232 struct mlx5_flow_meter_sub_policy *sub_policy;
15233 uint16_t sub_policy_num;
15235 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15236 sub_policy_num = (mtr_policy->sub_policy_num >>
15237 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15238 MLX5_MTR_SUB_POLICY_NUM_MASK;
15239 for (j = 0; j < sub_policy_num; j++) {
15240 sub_policy = mtr_policy->sub_policys[i][j];
15242 __flow_dv_destroy_sub_policy_rules(dev,
15249 * Destroy policy action, lock free,
15250 * (mutex should be acquired by caller).
15251 * Dispatcher for action type specific call.
15254 * Pointer to the Ethernet device structure.
15255 * @param[in] mtr_policy
15256 * Meter policy struct.
15259 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15260 struct mlx5_flow_meter_policy *mtr_policy)
15262 struct rte_flow_action *rss_action;
15263 struct mlx5_flow_handle dev_handle;
15266 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15267 if (mtr_policy->act_cnt[i].rix_mark) {
15268 flow_dv_tag_release(dev,
15269 mtr_policy->act_cnt[i].rix_mark);
15270 mtr_policy->act_cnt[i].rix_mark = 0;
15272 if (mtr_policy->act_cnt[i].modify_hdr) {
15273 dev_handle.dvh.modify_hdr =
15274 mtr_policy->act_cnt[i].modify_hdr;
15275 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15277 switch (mtr_policy->act_cnt[i].fate_action) {
15278 case MLX5_FLOW_FATE_SHARED_RSS:
15279 rss_action = mtr_policy->act_cnt[i].rss;
15280 mlx5_free(rss_action);
15282 case MLX5_FLOW_FATE_PORT_ID:
15283 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15284 flow_dv_port_id_action_resource_release(dev,
15285 mtr_policy->act_cnt[i].rix_port_id_action);
15286 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15289 case MLX5_FLOW_FATE_DROP:
15290 case MLX5_FLOW_FATE_JUMP:
15291 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15292 mtr_policy->act_cnt[i].dr_jump_action[j] =
15296 /*Queue action do nothing*/
15300 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15301 mtr_policy->dr_drop_action[j] = NULL;
15305 * Create policy action per domain, lock free,
15306 * (mutex should be acquired by caller).
15307 * Dispatcher for action type specific call.
15310 * Pointer to the Ethernet device structure.
15311 * @param[in] mtr_policy
15312 * Meter policy struct.
15313 * @param[in] action
15314 * Action specification used to create meter actions.
15315 * @param[out] error
15316 * Perform verbose error reporting if not NULL. Initialized in case of
15320 * 0 on success, otherwise negative errno value.
15323 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15324 struct mlx5_flow_meter_policy *mtr_policy,
15325 const struct rte_flow_action *actions[RTE_COLORS],
15326 enum mlx5_meter_domain domain,
15327 struct rte_mtr_error *error)
15329 struct mlx5_priv *priv = dev->data->dev_private;
15330 struct rte_flow_error flow_err;
15331 const struct rte_flow_action *act;
15332 uint64_t action_flags;
15333 struct mlx5_flow_handle dh;
15334 struct mlx5_flow dev_flow;
15335 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15337 uint8_t egress, transfer;
15338 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15340 struct mlx5_flow_dv_modify_hdr_resource res;
15341 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15342 sizeof(struct mlx5_modification_cmd) *
15343 (MLX5_MAX_MODIFY_NUM + 1)];
15345 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15347 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15348 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15349 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15350 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15351 memset(&port_id_action, 0,
15352 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15353 memset(mhdr_res, 0, sizeof(*mhdr_res));
15354 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15355 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15356 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15357 dev_flow.handle = &dh;
15358 dev_flow.dv.port_id_action = &port_id_action;
15359 dev_flow.external = true;
15360 for (i = 0; i < RTE_COLORS; i++) {
15361 if (i < MLX5_MTR_RTE_COLORS)
15362 act_cnt = &mtr_policy->act_cnt[i];
15363 /* Skip the color policy actions creation. */
15364 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15365 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15368 for (act = actions[i];
15369 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15370 switch (act->type) {
15371 case RTE_FLOW_ACTION_TYPE_MARK:
15373 uint32_t tag_be = mlx5_flow_mark_set
15374 (((const struct rte_flow_action_mark *)
15377 if (i >= MLX5_MTR_RTE_COLORS)
15378 return -rte_mtr_error_set(error,
15380 RTE_MTR_ERROR_TYPE_METER_POLICY,
15382 "cannot create policy "
15383 "mark action for this color");
15384 dev_flow.handle->mark = 1;
15385 if (flow_dv_tag_resource_register(dev, tag_be,
15386 &dev_flow, &flow_err))
15387 return -rte_mtr_error_set(error,
15389 RTE_MTR_ERROR_TYPE_METER_POLICY,
15391 "cannot setup policy mark action");
15392 MLX5_ASSERT(dev_flow.dv.tag_resource);
15393 act_cnt->rix_mark =
15394 dev_flow.handle->dvh.rix_tag;
15395 action_flags |= MLX5_FLOW_ACTION_MARK;
15398 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15399 if (i >= MLX5_MTR_RTE_COLORS)
15400 return -rte_mtr_error_set(error,
15402 RTE_MTR_ERROR_TYPE_METER_POLICY,
15404 "cannot create policy "
15405 "set tag action for this color");
15406 if (flow_dv_convert_action_set_tag
15408 (const struct rte_flow_action_set_tag *)
15409 act->conf, &flow_err))
15410 return -rte_mtr_error_set(error,
15412 RTE_MTR_ERROR_TYPE_METER_POLICY,
15413 NULL, "cannot convert policy "
15415 if (!mhdr_res->actions_num)
15416 return -rte_mtr_error_set(error,
15418 RTE_MTR_ERROR_TYPE_METER_POLICY,
15419 NULL, "cannot find policy "
15421 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15423 case RTE_FLOW_ACTION_TYPE_DROP:
15425 struct mlx5_flow_mtr_mng *mtrmng =
15427 struct mlx5_flow_tbl_data_entry *tbl_data;
15430 * Create the drop table with
15431 * METER DROP level.
15433 if (!mtrmng->drop_tbl[domain]) {
15434 mtrmng->drop_tbl[domain] =
15435 flow_dv_tbl_resource_get(dev,
15436 MLX5_FLOW_TABLE_LEVEL_METER,
15437 egress, transfer, false, NULL, 0,
15438 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15439 if (!mtrmng->drop_tbl[domain])
15440 return -rte_mtr_error_set
15442 RTE_MTR_ERROR_TYPE_METER_POLICY,
15444 "Failed to create meter drop table");
15446 tbl_data = container_of
15447 (mtrmng->drop_tbl[domain],
15448 struct mlx5_flow_tbl_data_entry, tbl);
15449 if (i < MLX5_MTR_RTE_COLORS) {
15450 act_cnt->dr_jump_action[domain] =
15451 tbl_data->jump.action;
15452 act_cnt->fate_action =
15453 MLX5_FLOW_FATE_DROP;
15455 if (i == RTE_COLOR_RED)
15456 mtr_policy->dr_drop_action[domain] =
15457 tbl_data->jump.action;
15458 action_flags |= MLX5_FLOW_ACTION_DROP;
15461 case RTE_FLOW_ACTION_TYPE_QUEUE:
15463 if (i >= MLX5_MTR_RTE_COLORS)
15464 return -rte_mtr_error_set(error,
15466 RTE_MTR_ERROR_TYPE_METER_POLICY,
15467 NULL, "cannot create policy "
15468 "fate queue for this color");
15470 ((const struct rte_flow_action_queue *)
15471 (act->conf))->index;
15472 act_cnt->fate_action =
15473 MLX5_FLOW_FATE_QUEUE;
15474 dev_flow.handle->fate_action =
15475 MLX5_FLOW_FATE_QUEUE;
15476 mtr_policy->is_queue = 1;
15477 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15480 case RTE_FLOW_ACTION_TYPE_RSS:
15484 if (i >= MLX5_MTR_RTE_COLORS)
15485 return -rte_mtr_error_set(error,
15487 RTE_MTR_ERROR_TYPE_METER_POLICY,
15489 "cannot create policy "
15490 "rss action for this color");
15492 * Save RSS conf into policy struct
15493 * for translate stage.
15495 rss_size = (int)rte_flow_conv
15496 (RTE_FLOW_CONV_OP_ACTION,
15497 NULL, 0, act, &flow_err);
15499 return -rte_mtr_error_set(error,
15501 RTE_MTR_ERROR_TYPE_METER_POLICY,
15502 NULL, "Get the wrong "
15503 "rss action struct size");
15504 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15505 rss_size, 0, SOCKET_ID_ANY);
15507 return -rte_mtr_error_set(error,
15509 RTE_MTR_ERROR_TYPE_METER_POLICY,
15511 "Fail to malloc rss action memory");
15512 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15513 act_cnt->rss, rss_size,
15516 return -rte_mtr_error_set(error,
15518 RTE_MTR_ERROR_TYPE_METER_POLICY,
15519 NULL, "Fail to save "
15520 "rss action into policy struct");
15521 act_cnt->fate_action =
15522 MLX5_FLOW_FATE_SHARED_RSS;
15523 action_flags |= MLX5_FLOW_ACTION_RSS;
15526 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15527 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15529 struct mlx5_flow_dv_port_id_action_resource
15531 uint32_t port_id = 0;
15533 if (i >= MLX5_MTR_RTE_COLORS)
15534 return -rte_mtr_error_set(error,
15536 RTE_MTR_ERROR_TYPE_METER_POLICY,
15537 NULL, "cannot create policy "
15538 "port action for this color");
15539 memset(&port_id_resource, 0,
15540 sizeof(port_id_resource));
15541 if (flow_dv_translate_action_port_id(dev, act,
15542 &port_id, &flow_err))
15543 return -rte_mtr_error_set(error,
15545 RTE_MTR_ERROR_TYPE_METER_POLICY,
15546 NULL, "cannot translate "
15547 "policy port action");
15548 port_id_resource.port_id = port_id;
15549 if (flow_dv_port_id_action_resource_register
15550 (dev, &port_id_resource,
15551 &dev_flow, &flow_err))
15552 return -rte_mtr_error_set(error,
15554 RTE_MTR_ERROR_TYPE_METER_POLICY,
15555 NULL, "cannot setup "
15556 "policy port action");
15557 act_cnt->rix_port_id_action =
15558 dev_flow.handle->rix_port_id_action;
15559 act_cnt->fate_action =
15560 MLX5_FLOW_FATE_PORT_ID;
15561 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15564 case RTE_FLOW_ACTION_TYPE_JUMP:
15566 uint32_t jump_group = 0;
15567 uint32_t table = 0;
15568 struct mlx5_flow_tbl_data_entry *tbl_data;
15569 struct flow_grp_info grp_info = {
15570 .external = !!dev_flow.external,
15571 .transfer = !!transfer,
15572 .fdb_def_rule = !!priv->fdb_def_rule,
15574 .skip_scale = dev_flow.skip_scale &
15575 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15577 struct mlx5_flow_meter_sub_policy *sub_policy =
15578 mtr_policy->sub_policys[domain][0];
15580 if (i >= MLX5_MTR_RTE_COLORS)
15581 return -rte_mtr_error_set(error,
15583 RTE_MTR_ERROR_TYPE_METER_POLICY,
15585 "cannot create policy "
15586 "jump action for this color");
15588 ((const struct rte_flow_action_jump *)
15590 if (mlx5_flow_group_to_table(dev, NULL,
15593 &grp_info, &flow_err))
15594 return -rte_mtr_error_set(error,
15596 RTE_MTR_ERROR_TYPE_METER_POLICY,
15597 NULL, "cannot setup "
15598 "policy jump action");
15599 sub_policy->jump_tbl[i] =
15600 flow_dv_tbl_resource_get(dev,
15603 !!dev_flow.external,
15604 NULL, jump_group, 0,
15607 (!sub_policy->jump_tbl[i])
15608 return -rte_mtr_error_set(error,
15610 RTE_MTR_ERROR_TYPE_METER_POLICY,
15611 NULL, "cannot create jump action.");
15612 tbl_data = container_of
15613 (sub_policy->jump_tbl[i],
15614 struct mlx5_flow_tbl_data_entry, tbl);
15615 act_cnt->dr_jump_action[domain] =
15616 tbl_data->jump.action;
15617 act_cnt->fate_action =
15618 MLX5_FLOW_FATE_JUMP;
15619 action_flags |= MLX5_FLOW_ACTION_JUMP;
15623 * No need to check meter hierarchy for Y or R colors
15624 * here since it is done in the validation stage.
15626 case RTE_FLOW_ACTION_TYPE_METER:
15628 const struct rte_flow_action_meter *mtr;
15629 struct mlx5_flow_meter_info *next_fm;
15630 struct mlx5_flow_meter_policy *next_policy;
15631 struct rte_flow_action tag_action;
15632 struct mlx5_rte_flow_action_set_tag set_tag;
15633 uint32_t next_mtr_idx = 0;
15636 next_fm = mlx5_flow_meter_find(priv,
15640 return -rte_mtr_error_set(error, EINVAL,
15641 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15642 "Fail to find next meter.");
15643 if (next_fm->def_policy)
15644 return -rte_mtr_error_set(error, EINVAL,
15645 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15646 "Hierarchy only supports termination meter.");
15647 next_policy = mlx5_flow_meter_policy_find(dev,
15648 next_fm->policy_id, NULL);
15649 MLX5_ASSERT(next_policy);
15650 if (next_fm->drop_cnt) {
15653 mlx5_flow_get_reg_id(dev,
15656 (struct rte_flow_error *)error);
15657 set_tag.offset = (priv->mtr_reg_share ?
15658 MLX5_MTR_COLOR_BITS : 0);
15659 set_tag.length = (priv->mtr_reg_share ?
15660 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15662 set_tag.data = next_mtr_idx;
15664 (enum rte_flow_action_type)
15665 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15666 tag_action.conf = &set_tag;
15667 if (flow_dv_convert_action_set_reg
15668 (mhdr_res, &tag_action,
15669 (struct rte_flow_error *)error))
15672 MLX5_FLOW_ACTION_SET_TAG;
15674 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15675 act_cnt->next_mtr_id = next_fm->meter_id;
15676 act_cnt->next_sub_policy = NULL;
15677 mtr_policy->is_hierarchy = 1;
15678 mtr_policy->dev = next_policy->dev;
15680 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15684 return -rte_mtr_error_set(error, ENOTSUP,
15685 RTE_MTR_ERROR_TYPE_METER_POLICY,
15686 NULL, "action type not supported");
15688 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15689 /* create modify action if needed. */
15690 dev_flow.dv.group = 1;
15691 if (flow_dv_modify_hdr_resource_register
15692 (dev, mhdr_res, &dev_flow, &flow_err))
15693 return -rte_mtr_error_set(error,
15695 RTE_MTR_ERROR_TYPE_METER_POLICY,
15696 NULL, "cannot register policy "
15698 act_cnt->modify_hdr =
15699 dev_flow.handle->dvh.modify_hdr;
15707 * Create policy action per domain, lock free,
15708 * (mutex should be acquired by caller).
15709 * Dispatcher for action type specific call.
15712 * Pointer to the Ethernet device structure.
15713 * @param[in] mtr_policy
15714 * Meter policy struct.
15715 * @param[in] action
15716 * Action specification used to create meter actions.
15717 * @param[out] error
15718 * Perform verbose error reporting if not NULL. Initialized in case of
15722 * 0 on success, otherwise negative errno value.
15725 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15726 struct mlx5_flow_meter_policy *mtr_policy,
15727 const struct rte_flow_action *actions[RTE_COLORS],
15728 struct rte_mtr_error *error)
15731 uint16_t sub_policy_num;
15733 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15734 sub_policy_num = (mtr_policy->sub_policy_num >>
15735 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15736 MLX5_MTR_SUB_POLICY_NUM_MASK;
15737 if (sub_policy_num) {
15738 ret = __flow_dv_create_domain_policy_acts(dev,
15739 mtr_policy, actions,
15740 (enum mlx5_meter_domain)i, error);
15741 /* Cleaning resource is done in the caller level. */
15750 * Query a DV flow rule for its statistics via DevX.
15753 * Pointer to Ethernet device.
15754 * @param[in] cnt_idx
15755 * Index to the flow counter.
15757 * Data retrieved by the query.
15758 * @param[out] error
15759 * Perform verbose error reporting if not NULL.
15762 * 0 on success, a negative errno value otherwise and rte_errno is set.
15765 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15766 struct rte_flow_error *error)
15768 struct mlx5_priv *priv = dev->data->dev_private;
15769 struct rte_flow_query_count *qc = data;
15771 if (!priv->sh->devx)
15772 return rte_flow_error_set(error, ENOTSUP,
15773 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15775 "counters are not supported");
15777 uint64_t pkts, bytes;
15778 struct mlx5_flow_counter *cnt;
15779 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15782 return rte_flow_error_set(error, -err,
15783 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15784 NULL, "cannot read counters");
15785 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15788 qc->hits = pkts - cnt->hits;
15789 qc->bytes = bytes - cnt->bytes;
15792 cnt->bytes = bytes;
15796 return rte_flow_error_set(error, EINVAL,
15797 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15799 "counters are not available");
15804 * Query counter's action pointer for a DV flow rule via DevX.
15807 * Pointer to Ethernet device.
15808 * @param[in] cnt_idx
15809 * Index to the flow counter.
15810 * @param[out] action_ptr
15811 * Action pointer for counter.
15812 * @param[out] error
15813 * Perform verbose error reporting if not NULL.
15816 * 0 on success, a negative errno value otherwise and rte_errno is set.
15819 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15820 void **action_ptr, struct rte_flow_error *error)
15822 struct mlx5_priv *priv = dev->data->dev_private;
15824 if (!priv->sh->devx || !action_ptr)
15825 return rte_flow_error_set(error, ENOTSUP,
15826 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15828 "counters are not supported");
15831 struct mlx5_flow_counter *cnt = NULL;
15832 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15834 *action_ptr = cnt->action;
15838 return rte_flow_error_set(error, EINVAL,
15839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15841 "counters are not available");
15845 flow_dv_action_query(struct rte_eth_dev *dev,
15846 const struct rte_flow_action_handle *handle, void *data,
15847 struct rte_flow_error *error)
15849 struct mlx5_age_param *age_param;
15850 struct rte_flow_query_age *resp;
15851 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15852 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15853 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15854 struct mlx5_priv *priv = dev->data->dev_private;
15855 struct mlx5_aso_ct_action *ct;
15860 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15861 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15863 resp->aged = __atomic_load_n(&age_param->state,
15864 __ATOMIC_RELAXED) == AGE_TMOUT ?
15866 resp->sec_since_last_hit_valid = !resp->aged;
15867 if (resp->sec_since_last_hit_valid)
15868 resp->sec_since_last_hit = __atomic_load_n
15869 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15871 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15872 return flow_dv_query_count(dev, idx, data, error);
15873 case MLX5_INDIRECT_ACTION_TYPE_CT:
15874 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15875 if (owner != PORT_ID(priv))
15876 return rte_flow_error_set(error, EACCES,
15877 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15879 "CT object owned by another port");
15880 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15881 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15884 return rte_flow_error_set(error, EFAULT,
15885 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15887 "CT object is inactive");
15888 ((struct rte_flow_action_conntrack *)data)->peer_port =
15890 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15892 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15893 return rte_flow_error_set(error, EIO,
15894 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15896 "Failed to query CT context");
15899 return rte_flow_error_set(error, ENOTSUP,
15900 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15901 "action type query not supported");
15906 * Query a flow rule AGE action for aging information.
15909 * Pointer to Ethernet device.
15911 * Pointer to the sub flow.
15913 * data retrieved by the query.
15914 * @param[out] error
15915 * Perform verbose error reporting if not NULL.
15918 * 0 on success, a negative errno value otherwise and rte_errno is set.
15921 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15922 void *data, struct rte_flow_error *error)
15924 struct rte_flow_query_age *resp = data;
15925 struct mlx5_age_param *age_param;
15928 struct mlx5_aso_age_action *act =
15929 flow_aso_age_get_by_idx(dev, flow->age);
15931 age_param = &act->age_params;
15932 } else if (flow->counter) {
15933 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15935 if (!age_param || !age_param->timeout)
15936 return rte_flow_error_set
15938 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15939 NULL, "cannot read age data");
15941 return rte_flow_error_set(error, EINVAL,
15942 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15943 NULL, "age data not available");
15945 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15947 resp->sec_since_last_hit_valid = !resp->aged;
15948 if (resp->sec_since_last_hit_valid)
15949 resp->sec_since_last_hit = __atomic_load_n
15950 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15957 * @see rte_flow_query()
15958 * @see rte_flow_ops
15961 flow_dv_query(struct rte_eth_dev *dev,
15962 struct rte_flow *flow __rte_unused,
15963 const struct rte_flow_action *actions __rte_unused,
15964 void *data __rte_unused,
15965 struct rte_flow_error *error __rte_unused)
15969 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15970 switch (actions->type) {
15971 case RTE_FLOW_ACTION_TYPE_VOID:
15973 case RTE_FLOW_ACTION_TYPE_COUNT:
15974 ret = flow_dv_query_count(dev, flow->counter, data,
15977 case RTE_FLOW_ACTION_TYPE_AGE:
15978 ret = flow_dv_query_age(dev, flow, data, error);
15981 return rte_flow_error_set(error, ENOTSUP,
15982 RTE_FLOW_ERROR_TYPE_ACTION,
15984 "action not supported");
15991 * Destroy the meter table set.
15992 * Lock free, (mutex should be acquired by caller).
15995 * Pointer to Ethernet device.
15997 * Meter information table.
16000 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16001 struct mlx5_flow_meter_info *fm)
16003 struct mlx5_priv *priv = dev->data->dev_private;
16006 if (!fm || !priv->config.dv_flow_en)
16008 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16009 if (fm->drop_rule[i]) {
16010 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16011 fm->drop_rule[i] = NULL;
16017 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16019 struct mlx5_priv *priv = dev->data->dev_private;
16020 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16021 struct mlx5_flow_tbl_data_entry *tbl;
16024 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16025 if (mtrmng->def_rule[i]) {
16026 claim_zero(mlx5_flow_os_destroy_flow
16027 (mtrmng->def_rule[i]));
16028 mtrmng->def_rule[i] = NULL;
16030 if (mtrmng->def_matcher[i]) {
16031 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16032 struct mlx5_flow_tbl_data_entry, tbl);
16033 mlx5_list_unregister(tbl->matchers,
16034 &mtrmng->def_matcher[i]->entry);
16035 mtrmng->def_matcher[i] = NULL;
16037 for (j = 0; j < MLX5_REG_BITS; j++) {
16038 if (mtrmng->drop_matcher[i][j]) {
16040 container_of(mtrmng->drop_matcher[i][j]->tbl,
16041 struct mlx5_flow_tbl_data_entry,
16043 mlx5_list_unregister(tbl->matchers,
16044 &mtrmng->drop_matcher[i][j]->entry);
16045 mtrmng->drop_matcher[i][j] = NULL;
16048 if (mtrmng->drop_tbl[i]) {
16049 flow_dv_tbl_resource_release(MLX5_SH(dev),
16050 mtrmng->drop_tbl[i]);
16051 mtrmng->drop_tbl[i] = NULL;
16056 /* Number of meter flow actions, count and jump or count and drop. */
16057 #define METER_ACTIONS 2
16060 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16061 enum mlx5_meter_domain domain)
16063 struct mlx5_priv *priv = dev->data->dev_private;
16064 struct mlx5_flow_meter_def_policy *def_policy =
16065 priv->sh->mtrmng->def_policy[domain];
16067 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16068 mlx5_free(def_policy);
16069 priv->sh->mtrmng->def_policy[domain] = NULL;
16073 * Destroy the default policy table set.
16076 * Pointer to Ethernet device.
16079 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16081 struct mlx5_priv *priv = dev->data->dev_private;
16084 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16085 if (priv->sh->mtrmng->def_policy[i])
16086 __flow_dv_destroy_domain_def_policy(dev,
16087 (enum mlx5_meter_domain)i);
16088 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16092 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16093 uint32_t color_reg_c_idx,
16094 enum rte_color color, void *matcher_object,
16095 int actions_n, void *actions,
16096 bool match_src_port, const struct rte_flow_item *item,
16097 void **rule, const struct rte_flow_attr *attr)
16100 struct mlx5_flow_dv_match_params value = {
16101 .size = sizeof(value.buf),
16103 struct mlx5_flow_dv_match_params matcher = {
16104 .size = sizeof(matcher.buf),
16106 struct mlx5_priv *priv = dev->data->dev_private;
16109 if (match_src_port && (priv->representor || priv->master)) {
16110 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16111 value.buf, item, attr)) {
16112 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16113 " value with port.", color);
16117 flow_dv_match_meta_reg(matcher.buf, value.buf,
16118 (enum modify_reg)color_reg_c_idx,
16119 rte_col_2_mlx5_col(color), UINT32_MAX);
16120 misc_mask = flow_dv_matcher_enable(value.buf);
16121 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16122 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16123 actions_n, actions, rule);
16125 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16132 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16133 uint32_t color_reg_c_idx,
16135 struct mlx5_flow_meter_sub_policy *sub_policy,
16136 const struct rte_flow_attr *attr,
16137 bool match_src_port,
16138 const struct rte_flow_item *item,
16139 struct mlx5_flow_dv_matcher **policy_matcher,
16140 struct rte_flow_error *error)
16142 struct mlx5_list_entry *entry;
16143 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16144 struct mlx5_flow_dv_matcher matcher = {
16146 .size = sizeof(matcher.mask.buf),
16150 struct mlx5_flow_dv_match_params value = {
16151 .size = sizeof(value.buf),
16153 struct mlx5_flow_cb_ctx ctx = {
16157 struct mlx5_flow_tbl_data_entry *tbl_data;
16158 struct mlx5_priv *priv = dev->data->dev_private;
16159 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16161 if (match_src_port && (priv->representor || priv->master)) {
16162 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16163 value.buf, item, attr)) {
16164 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16165 " with port.", priority);
16169 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16170 if (priority < RTE_COLOR_RED)
16171 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16172 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16173 matcher.priority = priority;
16174 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16175 matcher.mask.size);
16176 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16178 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16182 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16187 * Create the policy rules per domain.
16190 * Pointer to Ethernet device.
16191 * @param[in] sub_policy
16192 * Pointer to sub policy table..
16193 * @param[in] egress
16194 * Direction of the table.
16195 * @param[in] transfer
16196 * E-Switch or NIC flow.
16198 * Pointer to policy action list per color.
16201 * 0 on success, -1 otherwise.
16204 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16205 struct mlx5_flow_meter_sub_policy *sub_policy,
16206 uint8_t egress, uint8_t transfer, bool match_src_port,
16207 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16209 struct mlx5_priv *priv = dev->data->dev_private;
16210 struct rte_flow_error flow_err;
16211 uint32_t color_reg_c_idx;
16212 struct rte_flow_attr attr = {
16213 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16216 .egress = !!egress,
16217 .transfer = !!transfer,
16221 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16222 struct mlx5_sub_policy_color_rule *color_rule;
16224 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16228 /* Create policy table with POLICY level. */
16229 if (!sub_policy->tbl_rsc)
16230 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16231 MLX5_FLOW_TABLE_LEVEL_POLICY,
16232 egress, transfer, false, NULL, 0, 0,
16233 sub_policy->idx, &flow_err);
16234 if (!sub_policy->tbl_rsc) {
16236 "Failed to create meter sub policy table.");
16239 /* Prepare matchers. */
16240 color_reg_c_idx = ret;
16241 for (i = 0; i < RTE_COLORS; i++) {
16242 TAILQ_INIT(&sub_policy->color_rules[i]);
16243 if (!acts[i].actions_n)
16245 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16246 sizeof(struct mlx5_sub_policy_color_rule),
16249 DRV_LOG(ERR, "No memory to create color rule.");
16252 tmp_rules[i] = color_rule;
16253 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16254 color_rule, next_port);
16255 color_rule->src_port = priv->representor_id;
16258 /* Create matchers for colors. */
16259 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16260 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16261 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16262 &attr, svport_match, NULL,
16263 &color_rule->matcher, &flow_err)) {
16264 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16267 /* Create flow, matching color. */
16268 if (__flow_dv_create_policy_flow(dev,
16269 color_reg_c_idx, (enum rte_color)i,
16270 color_rule->matcher->matcher_object,
16271 acts[i].actions_n, acts[i].dv_actions,
16272 svport_match, NULL, &color_rule->rule,
16274 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16280 /* All the policy rules will be cleared. */
16282 color_rule = tmp_rules[i];
16284 if (color_rule->rule)
16285 mlx5_flow_os_destroy_flow(color_rule->rule);
16286 if (color_rule->matcher) {
16287 struct mlx5_flow_tbl_data_entry *tbl =
16288 container_of(color_rule->matcher->tbl,
16289 typeof(*tbl), tbl);
16290 mlx5_list_unregister(tbl->matchers,
16291 &color_rule->matcher->entry);
16293 TAILQ_REMOVE(&sub_policy->color_rules[i],
16294 color_rule, next_port);
16295 mlx5_free(color_rule);
16302 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16303 struct mlx5_flow_meter_policy *mtr_policy,
16304 struct mlx5_flow_meter_sub_policy *sub_policy,
16307 struct mlx5_priv *priv = dev->data->dev_private;
16308 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16309 struct mlx5_flow_dv_tag_resource *tag;
16310 struct mlx5_flow_dv_port_id_action_resource *port_action;
16311 struct mlx5_hrxq *hrxq;
16312 struct mlx5_flow_meter_info *next_fm = NULL;
16313 struct mlx5_flow_meter_policy *next_policy;
16314 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16315 struct mlx5_flow_tbl_data_entry *tbl_data;
16316 struct rte_flow_error error;
16317 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16318 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16319 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16320 bool match_src_port = false;
16323 /* If RSS or Queue, no previous actions / rules is created. */
16324 for (i = 0; i < RTE_COLORS; i++) {
16325 acts[i].actions_n = 0;
16326 if (i == RTE_COLOR_RED) {
16327 /* Only support drop on red. */
16328 acts[i].dv_actions[0] =
16329 mtr_policy->dr_drop_action[domain];
16330 acts[i].actions_n = 1;
16333 if (i == RTE_COLOR_GREEN &&
16334 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16335 struct rte_flow_attr attr = {
16336 .transfer = transfer
16339 next_fm = mlx5_flow_meter_find(priv,
16340 mtr_policy->act_cnt[i].next_mtr_id,
16344 "Failed to get next hierarchy meter.");
16347 if (mlx5_flow_meter_attach(priv, next_fm,
16349 DRV_LOG(ERR, "%s", error.message);
16353 /* Meter action must be the first for TX. */
16355 acts[i].dv_actions[acts[i].actions_n] =
16356 next_fm->meter_action;
16357 acts[i].actions_n++;
16360 if (mtr_policy->act_cnt[i].rix_mark) {
16361 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16362 mtr_policy->act_cnt[i].rix_mark);
16364 DRV_LOG(ERR, "Failed to find "
16365 "mark action for policy.");
16368 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16369 acts[i].actions_n++;
16371 if (mtr_policy->act_cnt[i].modify_hdr) {
16372 acts[i].dv_actions[acts[i].actions_n] =
16373 mtr_policy->act_cnt[i].modify_hdr->action;
16374 acts[i].actions_n++;
16376 if (mtr_policy->act_cnt[i].fate_action) {
16377 switch (mtr_policy->act_cnt[i].fate_action) {
16378 case MLX5_FLOW_FATE_PORT_ID:
16379 port_action = mlx5_ipool_get
16380 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16381 mtr_policy->act_cnt[i].rix_port_id_action);
16382 if (!port_action) {
16383 DRV_LOG(ERR, "Failed to find "
16384 "port action for policy.");
16387 acts[i].dv_actions[acts[i].actions_n] =
16388 port_action->action;
16389 acts[i].actions_n++;
16390 mtr_policy->dev = dev;
16391 match_src_port = true;
16393 case MLX5_FLOW_FATE_DROP:
16394 case MLX5_FLOW_FATE_JUMP:
16395 acts[i].dv_actions[acts[i].actions_n] =
16396 mtr_policy->act_cnt[i].dr_jump_action[domain];
16397 acts[i].actions_n++;
16399 case MLX5_FLOW_FATE_SHARED_RSS:
16400 case MLX5_FLOW_FATE_QUEUE:
16401 hrxq = mlx5_ipool_get
16402 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16403 sub_policy->rix_hrxq[i]);
16405 DRV_LOG(ERR, "Failed to find "
16406 "queue action for policy.");
16409 acts[i].dv_actions[acts[i].actions_n] =
16411 acts[i].actions_n++;
16413 case MLX5_FLOW_FATE_MTR:
16416 "No next hierarchy meter.");
16420 acts[i].dv_actions[acts[i].actions_n] =
16421 next_fm->meter_action;
16422 acts[i].actions_n++;
16424 if (mtr_policy->act_cnt[i].next_sub_policy) {
16426 mtr_policy->act_cnt[i].next_sub_policy;
16429 mlx5_flow_meter_policy_find(dev,
16430 next_fm->policy_id, NULL);
16431 MLX5_ASSERT(next_policy);
16433 next_policy->sub_policys[domain][0];
16436 container_of(next_sub_policy->tbl_rsc,
16437 struct mlx5_flow_tbl_data_entry, tbl);
16438 acts[i].dv_actions[acts[i].actions_n++] =
16439 tbl_data->jump.action;
16440 if (mtr_policy->act_cnt[i].modify_hdr)
16441 match_src_port = !!transfer;
16444 /*Queue action do nothing*/
16449 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16450 egress, transfer, match_src_port, acts)) {
16452 "Failed to create policy rules per domain.");
16458 mlx5_flow_meter_detach(priv, next_fm);
16463 * Create the policy rules.
16466 * Pointer to Ethernet device.
16467 * @param[in,out] mtr_policy
16468 * Pointer to meter policy table.
16471 * 0 on success, -1 otherwise.
16474 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16475 struct mlx5_flow_meter_policy *mtr_policy)
16478 uint16_t sub_policy_num;
16480 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16481 sub_policy_num = (mtr_policy->sub_policy_num >>
16482 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16483 MLX5_MTR_SUB_POLICY_NUM_MASK;
16484 if (!sub_policy_num)
16486 /* Prepare actions list and create policy rules. */
16487 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16488 mtr_policy->sub_policys[i][0], i)) {
16489 DRV_LOG(ERR, "Failed to create policy action "
16490 "list per domain.");
16498 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16500 struct mlx5_priv *priv = dev->data->dev_private;
16501 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16502 struct mlx5_flow_meter_def_policy *def_policy;
16503 struct mlx5_flow_tbl_resource *jump_tbl;
16504 struct mlx5_flow_tbl_data_entry *tbl_data;
16505 uint8_t egress, transfer;
16506 struct rte_flow_error error;
16507 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16510 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16511 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16512 def_policy = mtrmng->def_policy[domain];
16514 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16515 sizeof(struct mlx5_flow_meter_def_policy),
16516 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16518 DRV_LOG(ERR, "Failed to alloc default policy table.");
16519 goto def_policy_error;
16521 mtrmng->def_policy[domain] = def_policy;
16522 /* Create the meter suffix table with SUFFIX level. */
16523 jump_tbl = flow_dv_tbl_resource_get(dev,
16524 MLX5_FLOW_TABLE_LEVEL_METER,
16525 egress, transfer, false, NULL, 0,
16526 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16529 "Failed to create meter suffix table.");
16530 goto def_policy_error;
16532 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16533 tbl_data = container_of(jump_tbl,
16534 struct mlx5_flow_tbl_data_entry, tbl);
16535 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16536 tbl_data->jump.action;
16537 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16538 acts[RTE_COLOR_GREEN].actions_n = 1;
16540 * YELLOW has the same default policy as GREEN does.
16541 * G & Y share the same table and action. The 2nd time of table
16542 * resource getting is just to update the reference count for
16543 * the releasing stage.
16545 jump_tbl = flow_dv_tbl_resource_get(dev,
16546 MLX5_FLOW_TABLE_LEVEL_METER,
16547 egress, transfer, false, NULL, 0,
16548 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16551 "Failed to get meter suffix table.");
16552 goto def_policy_error;
16554 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16555 tbl_data = container_of(jump_tbl,
16556 struct mlx5_flow_tbl_data_entry, tbl);
16557 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16558 tbl_data->jump.action;
16559 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16560 acts[RTE_COLOR_YELLOW].actions_n = 1;
16561 /* Create jump action to the drop table. */
16562 if (!mtrmng->drop_tbl[domain]) {
16563 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16564 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16565 egress, transfer, false, NULL, 0,
16566 0, MLX5_MTR_TABLE_ID_DROP, &error);
16567 if (!mtrmng->drop_tbl[domain]) {
16568 DRV_LOG(ERR, "Failed to create meter "
16569 "drop table for default policy.");
16570 goto def_policy_error;
16573 /* all RED: unique Drop table for jump action. */
16574 tbl_data = container_of(mtrmng->drop_tbl[domain],
16575 struct mlx5_flow_tbl_data_entry, tbl);
16576 def_policy->dr_jump_action[RTE_COLOR_RED] =
16577 tbl_data->jump.action;
16578 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16579 acts[RTE_COLOR_RED].actions_n = 1;
16580 /* Create default policy rules. */
16581 ret = __flow_dv_create_domain_policy_rules(dev,
16582 &def_policy->sub_policy,
16583 egress, transfer, false, acts);
16585 DRV_LOG(ERR, "Failed to create default policy rules.");
16586 goto def_policy_error;
16591 __flow_dv_destroy_domain_def_policy(dev,
16592 (enum mlx5_meter_domain)domain);
16597 * Create the default policy table set.
16600 * Pointer to Ethernet device.
16602 * 0 on success, -1 otherwise.
16605 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16607 struct mlx5_priv *priv = dev->data->dev_private;
16610 /* Non-termination policy table. */
16611 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16612 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16614 if (__flow_dv_create_domain_def_policy(dev, i)) {
16615 DRV_LOG(ERR, "Failed to create default policy");
16616 /* Rollback the created default policies for others. */
16617 flow_dv_destroy_def_policy(dev);
16625 * Create the needed meter tables.
16626 * Lock free, (mutex should be acquired by caller).
16629 * Pointer to Ethernet device.
16631 * Meter information table.
16632 * @param[in] mtr_idx
16634 * @param[in] domain_bitmap
16637 * 0 on success, -1 otherwise.
16640 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16641 struct mlx5_flow_meter_info *fm,
16643 uint8_t domain_bitmap)
16645 struct mlx5_priv *priv = dev->data->dev_private;
16646 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16647 struct rte_flow_error error;
16648 struct mlx5_flow_tbl_data_entry *tbl_data;
16649 uint8_t egress, transfer;
16650 void *actions[METER_ACTIONS];
16651 int domain, ret, i;
16652 struct mlx5_flow_counter *cnt;
16653 struct mlx5_flow_dv_match_params value = {
16654 .size = sizeof(value.buf),
16656 struct mlx5_flow_dv_match_params matcher_para = {
16657 .size = sizeof(matcher_para.buf),
16659 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16661 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16662 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16663 struct mlx5_list_entry *entry;
16664 struct mlx5_flow_dv_matcher matcher = {
16666 .size = sizeof(matcher.mask.buf),
16669 struct mlx5_flow_dv_matcher *drop_matcher;
16670 struct mlx5_flow_cb_ctx ctx = {
16676 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16677 rte_errno = ENOTSUP;
16680 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16681 if (!(domain_bitmap & (1 << domain)) ||
16682 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16684 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16685 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16686 /* Create the drop table with METER DROP level. */
16687 if (!mtrmng->drop_tbl[domain]) {
16688 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16689 MLX5_FLOW_TABLE_LEVEL_METER,
16690 egress, transfer, false, NULL, 0,
16691 0, MLX5_MTR_TABLE_ID_DROP, &error);
16692 if (!mtrmng->drop_tbl[domain]) {
16693 DRV_LOG(ERR, "Failed to create meter drop table.");
16697 /* Create default matcher in drop table. */
16698 matcher.tbl = mtrmng->drop_tbl[domain],
16699 tbl_data = container_of(mtrmng->drop_tbl[domain],
16700 struct mlx5_flow_tbl_data_entry, tbl);
16701 if (!mtrmng->def_matcher[domain]) {
16702 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16703 (enum modify_reg)mtr_id_reg_c,
16705 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16706 matcher.crc = rte_raw_cksum
16707 ((const void *)matcher.mask.buf,
16708 matcher.mask.size);
16709 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16711 DRV_LOG(ERR, "Failed to register meter "
16712 "drop default matcher.");
16715 mtrmng->def_matcher[domain] = container_of(entry,
16716 struct mlx5_flow_dv_matcher, entry);
16718 /* Create default rule in drop table. */
16719 if (!mtrmng->def_rule[domain]) {
16721 actions[i++] = priv->sh->dr_drop_action;
16722 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16723 (enum modify_reg)mtr_id_reg_c, 0, 0);
16724 misc_mask = flow_dv_matcher_enable(value.buf);
16725 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16726 ret = mlx5_flow_os_create_flow
16727 (mtrmng->def_matcher[domain]->matcher_object,
16728 (void *)&value, i, actions,
16729 &mtrmng->def_rule[domain]);
16731 DRV_LOG(ERR, "Failed to create meter "
16732 "default drop rule for drop table.");
16738 MLX5_ASSERT(mtrmng->max_mtr_bits);
16739 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16740 /* Create matchers for Drop. */
16741 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16742 (enum modify_reg)mtr_id_reg_c, 0,
16743 (mtr_id_mask << mtr_id_offset));
16744 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16745 matcher.crc = rte_raw_cksum
16746 ((const void *)matcher.mask.buf,
16747 matcher.mask.size);
16748 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16751 "Failed to register meter drop matcher.");
16754 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16755 container_of(entry, struct mlx5_flow_dv_matcher,
16759 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16760 /* Create drop rule, matching meter_id only. */
16761 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16762 (enum modify_reg)mtr_id_reg_c,
16763 (mtr_idx << mtr_id_offset), UINT32_MAX);
16765 cnt = flow_dv_counter_get_by_idx(dev,
16766 fm->drop_cnt, NULL);
16767 actions[i++] = cnt->action;
16768 actions[i++] = priv->sh->dr_drop_action;
16769 misc_mask = flow_dv_matcher_enable(value.buf);
16770 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16771 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16772 (void *)&value, i, actions,
16773 &fm->drop_rule[domain]);
16775 DRV_LOG(ERR, "Failed to create meter "
16776 "drop rule for drop table.");
16782 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16783 if (fm->drop_rule[i]) {
16784 claim_zero(mlx5_flow_os_destroy_flow
16785 (fm->drop_rule[i]));
16786 fm->drop_rule[i] = NULL;
16792 static struct mlx5_flow_meter_sub_policy *
16793 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16794 struct mlx5_flow_meter_policy *mtr_policy,
16795 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16796 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16799 struct mlx5_priv *priv = dev->data->dev_private;
16800 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16801 uint32_t sub_policy_idx = 0;
16802 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16804 struct mlx5_hrxq *hrxq;
16805 struct mlx5_flow_handle dh;
16806 struct mlx5_meter_policy_action_container *act_cnt;
16807 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16808 uint16_t sub_policy_num;
16810 rte_spinlock_lock(&mtr_policy->sl);
16811 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16814 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16815 if (!hrxq_idx[i]) {
16816 rte_spinlock_unlock(&mtr_policy->sl);
16820 sub_policy_num = (mtr_policy->sub_policy_num >>
16821 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16822 MLX5_MTR_SUB_POLICY_NUM_MASK;
16823 for (j = 0; j < sub_policy_num; j++) {
16824 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16827 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16830 if (i >= MLX5_MTR_RTE_COLORS) {
16832 * Found the sub policy table with
16833 * the same queue per color.
16835 rte_spinlock_unlock(&mtr_policy->sl);
16836 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16837 mlx5_hrxq_release(dev, hrxq_idx[i]);
16839 return mtr_policy->sub_policys[domain][j];
16842 /* Create sub policy. */
16843 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16844 /* Reuse the first pre-allocated sub_policy. */
16845 sub_policy = mtr_policy->sub_policys[domain][0];
16846 sub_policy_idx = sub_policy->idx;
16848 sub_policy = mlx5_ipool_zmalloc
16849 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16852 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16853 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16854 mlx5_hrxq_release(dev, hrxq_idx[i]);
16855 goto rss_sub_policy_error;
16857 sub_policy->idx = sub_policy_idx;
16858 sub_policy->main_policy = mtr_policy;
16860 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16863 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16864 if (mtr_policy->is_hierarchy) {
16865 act_cnt = &mtr_policy->act_cnt[i];
16866 act_cnt->next_sub_policy = next_sub_policy;
16867 mlx5_hrxq_release(dev, hrxq_idx[i]);
16870 * Overwrite the last action from
16871 * RSS action to Queue action.
16873 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16876 DRV_LOG(ERR, "Failed to get policy hrxq");
16877 goto rss_sub_policy_error;
16879 act_cnt = &mtr_policy->act_cnt[i];
16880 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16881 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16882 if (act_cnt->rix_mark)
16884 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16885 dh.rix_hrxq = hrxq_idx[i];
16886 flow_drv_rxq_flags_set(dev, &dh);
16890 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16891 sub_policy, domain)) {
16892 DRV_LOG(ERR, "Failed to create policy "
16893 "rules for ingress domain.");
16894 goto rss_sub_policy_error;
16896 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16897 i = (mtr_policy->sub_policy_num >>
16898 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16899 MLX5_MTR_SUB_POLICY_NUM_MASK;
16900 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16901 DRV_LOG(ERR, "No free sub-policy slot.");
16902 goto rss_sub_policy_error;
16904 mtr_policy->sub_policys[domain][i] = sub_policy;
16906 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16907 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16908 mtr_policy->sub_policy_num |=
16909 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16910 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16912 rte_spinlock_unlock(&mtr_policy->sl);
16915 rss_sub_policy_error:
16917 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16918 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16919 i = (mtr_policy->sub_policy_num >>
16920 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16921 MLX5_MTR_SUB_POLICY_NUM_MASK;
16922 mtr_policy->sub_policys[domain][i] = NULL;
16923 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16927 rte_spinlock_unlock(&mtr_policy->sl);
16932 * Find the policy table for prefix table with RSS.
16935 * Pointer to Ethernet device.
16936 * @param[in] mtr_policy
16937 * Pointer to meter policy table.
16938 * @param[in] rss_desc
16939 * Pointer to rss_desc
16941 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16943 static struct mlx5_flow_meter_sub_policy *
16944 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16945 struct mlx5_flow_meter_policy *mtr_policy,
16946 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16948 struct mlx5_priv *priv = dev->data->dev_private;
16949 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16950 struct mlx5_flow_meter_info *next_fm;
16951 struct mlx5_flow_meter_policy *next_policy;
16952 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16953 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16954 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16955 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16956 bool reuse_sub_policy;
16961 /* Iterate hierarchy to get all policies in this hierarchy. */
16962 policies[i++] = mtr_policy;
16963 if (!mtr_policy->is_hierarchy)
16965 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16966 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16969 next_fm = mlx5_flow_meter_find(priv,
16970 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16972 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
16976 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
16978 MLX5_ASSERT(next_policy);
16979 mtr_policy = next_policy;
16983 * From last policy to the first one in hierarchy,
16984 * create / get the sub policy for each of them.
16986 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
16990 &reuse_sub_policy);
16992 DRV_LOG(ERR, "Failed to get the sub policy.");
16995 if (!reuse_sub_policy)
16996 sub_policies[j++] = sub_policy;
16997 next_sub_policy = sub_policy;
17002 uint16_t sub_policy_num;
17004 sub_policy = sub_policies[--j];
17005 mtr_policy = sub_policy->main_policy;
17006 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17007 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17008 sub_policy_num = (mtr_policy->sub_policy_num >>
17009 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17010 MLX5_MTR_SUB_POLICY_NUM_MASK;
17011 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17014 mtr_policy->sub_policy_num &=
17015 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17016 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17017 mtr_policy->sub_policy_num |=
17018 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17019 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17020 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17028 * Create the sub policy tag rule for all meters in hierarchy.
17031 * Pointer to Ethernet device.
17033 * Meter information table.
17034 * @param[in] src_port
17035 * The src port this extra rule should use.
17037 * The src port match item.
17038 * @param[out] error
17039 * Perform verbose error reporting if not NULL.
17041 * 0 on success, a negative errno value otherwise and rte_errno is set.
17044 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17045 struct mlx5_flow_meter_info *fm,
17047 const struct rte_flow_item *item,
17048 struct rte_flow_error *error)
17050 struct mlx5_priv *priv = dev->data->dev_private;
17051 struct mlx5_flow_meter_policy *mtr_policy;
17052 struct mlx5_flow_meter_sub_policy *sub_policy;
17053 struct mlx5_flow_meter_info *next_fm = NULL;
17054 struct mlx5_flow_meter_policy *next_policy;
17055 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17056 struct mlx5_flow_tbl_data_entry *tbl_data;
17057 struct mlx5_sub_policy_color_rule *color_rule;
17058 struct mlx5_meter_policy_acts acts;
17059 uint32_t color_reg_c_idx;
17060 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17061 struct rte_flow_attr attr = {
17062 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17069 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17072 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17073 MLX5_ASSERT(mtr_policy);
17074 if (!mtr_policy->is_hierarchy)
17076 next_fm = mlx5_flow_meter_find(priv,
17077 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17079 return rte_flow_error_set(error, EINVAL,
17080 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17081 "Failed to find next meter in hierarchy.");
17083 if (!next_fm->drop_cnt)
17085 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17086 sub_policy = mtr_policy->sub_policys[domain][0];
17087 for (i = 0; i < RTE_COLORS; i++) {
17088 bool rule_exist = false;
17089 struct mlx5_meter_policy_action_container *act_cnt;
17091 if (i >= RTE_COLOR_YELLOW)
17093 TAILQ_FOREACH(color_rule,
17094 &sub_policy->color_rules[i], next_port)
17095 if (color_rule->src_port == src_port) {
17101 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17102 sizeof(struct mlx5_sub_policy_color_rule),
17105 return rte_flow_error_set(error, ENOMEM,
17106 RTE_FLOW_ERROR_TYPE_ACTION,
17107 NULL, "No memory to create tag color rule.");
17108 color_rule->src_port = src_port;
17110 next_policy = mlx5_flow_meter_policy_find(dev,
17111 next_fm->policy_id, NULL);
17112 MLX5_ASSERT(next_policy);
17113 next_sub_policy = next_policy->sub_policys[domain][0];
17114 tbl_data = container_of(next_sub_policy->tbl_rsc,
17115 struct mlx5_flow_tbl_data_entry, tbl);
17116 act_cnt = &mtr_policy->act_cnt[i];
17118 acts.dv_actions[0] = next_fm->meter_action;
17119 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17121 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17122 acts.dv_actions[1] = next_fm->meter_action;
17124 acts.dv_actions[2] = tbl_data->jump.action;
17125 acts.actions_n = 3;
17126 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17130 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17131 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17133 &color_rule->matcher, error)) {
17134 rte_flow_error_set(error, errno,
17135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17136 "Failed to create hierarchy meter matcher.");
17139 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17141 color_rule->matcher->matcher_object,
17142 acts.actions_n, acts.dv_actions,
17144 &color_rule->rule, &attr)) {
17145 rte_flow_error_set(error, errno,
17146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17147 "Failed to create hierarchy meter rule.");
17150 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17151 color_rule, next_port);
17155 * Recursive call to iterate all meters in hierarchy and
17156 * create needed rules.
17158 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17159 src_port, item, error);
17162 if (color_rule->rule)
17163 mlx5_flow_os_destroy_flow(color_rule->rule);
17164 if (color_rule->matcher) {
17165 struct mlx5_flow_tbl_data_entry *tbl =
17166 container_of(color_rule->matcher->tbl,
17167 typeof(*tbl), tbl);
17168 mlx5_list_unregister(tbl->matchers,
17169 &color_rule->matcher->entry);
17171 mlx5_free(color_rule);
17174 mlx5_flow_meter_detach(priv, next_fm);
17179 * Destroy the sub policy table with RX queue.
17182 * Pointer to Ethernet device.
17183 * @param[in] mtr_policy
17184 * Pointer to meter policy table.
17187 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17188 struct mlx5_flow_meter_policy *mtr_policy)
17190 struct mlx5_priv *priv = dev->data->dev_private;
17191 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17192 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17194 uint16_t sub_policy_num, new_policy_num;
17196 rte_spinlock_lock(&mtr_policy->sl);
17197 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17198 switch (mtr_policy->act_cnt[i].fate_action) {
17199 case MLX5_FLOW_FATE_SHARED_RSS:
17200 sub_policy_num = (mtr_policy->sub_policy_num >>
17201 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17202 MLX5_MTR_SUB_POLICY_NUM_MASK;
17203 new_policy_num = sub_policy_num;
17204 for (j = 0; j < sub_policy_num; j++) {
17206 mtr_policy->sub_policys[domain][j];
17208 __flow_dv_destroy_sub_policy_rules(dev,
17211 mtr_policy->sub_policys[domain][0]) {
17212 mtr_policy->sub_policys[domain][j] =
17215 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17221 if (new_policy_num != sub_policy_num) {
17222 mtr_policy->sub_policy_num &=
17223 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17224 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17225 mtr_policy->sub_policy_num |=
17227 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17228 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17231 case MLX5_FLOW_FATE_QUEUE:
17232 sub_policy = mtr_policy->sub_policys[domain][0];
17233 __flow_dv_destroy_sub_policy_rules(dev,
17237 /*Other actions without queue and do nothing*/
17241 rte_spinlock_unlock(&mtr_policy->sl);
17244 * Check whether the DR drop action is supported on the root table or not.
17246 * Create a simple flow with DR drop action on root table to validate
17247 * if DR drop action on root table is supported or not.
17250 * Pointer to rte_eth_dev structure.
17253 * 0 on success, a negative errno value otherwise and rte_errno is set.
17256 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17258 struct mlx5_priv *priv = dev->data->dev_private;
17259 struct mlx5_dev_ctx_shared *sh = priv->sh;
17260 struct mlx5_flow_dv_match_params mask = {
17261 .size = sizeof(mask.buf),
17263 struct mlx5_flow_dv_match_params value = {
17264 .size = sizeof(value.buf),
17266 struct mlx5dv_flow_matcher_attr dv_attr = {
17267 .type = IBV_FLOW_ATTR_NORMAL,
17269 .match_criteria_enable = 0,
17270 .match_mask = (void *)&mask,
17272 struct mlx5_flow_tbl_resource *tbl = NULL;
17273 void *matcher = NULL;
17277 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17281 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17282 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17283 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17284 tbl->obj, &matcher);
17287 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17288 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17289 &sh->dr_drop_action, &flow);
17292 * If DR drop action is not supported on root table, flow create will
17293 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17297 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17298 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17300 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17303 claim_zero(mlx5_flow_os_destroy_flow(flow));
17306 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17308 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17313 * Validate the batch counter support in root table.
17315 * Create a simple flow with invalid counter and drop action on root table to
17316 * validate if batch counter with offset on root table is supported or not.
17319 * Pointer to rte_eth_dev structure.
17322 * 0 on success, a negative errno value otherwise and rte_errno is set.
17325 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17327 struct mlx5_priv *priv = dev->data->dev_private;
17328 struct mlx5_dev_ctx_shared *sh = priv->sh;
17329 struct mlx5_flow_dv_match_params mask = {
17330 .size = sizeof(mask.buf),
17332 struct mlx5_flow_dv_match_params value = {
17333 .size = sizeof(value.buf),
17335 struct mlx5dv_flow_matcher_attr dv_attr = {
17336 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17338 .match_criteria_enable = 0,
17339 .match_mask = (void *)&mask,
17341 void *actions[2] = { 0 };
17342 struct mlx5_flow_tbl_resource *tbl = NULL;
17343 struct mlx5_devx_obj *dcs = NULL;
17344 void *matcher = NULL;
17348 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17352 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17355 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17359 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17360 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17361 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17362 tbl->obj, &matcher);
17365 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17366 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17370 * If batch counter with offset is not supported, the driver will not
17371 * validate the invalid offset value, flow create should success.
17372 * In this case, it means batch counter is not supported in root table.
17374 * Otherwise, if flow create is failed, counter offset is supported.
17377 DRV_LOG(INFO, "Batch counter is not supported in root "
17378 "table. Switch to fallback mode.");
17379 rte_errno = ENOTSUP;
17381 claim_zero(mlx5_flow_os_destroy_flow(flow));
17383 /* Check matcher to make sure validate fail at flow create. */
17384 if (!matcher || (matcher && errno != EINVAL))
17385 DRV_LOG(ERR, "Unexpected error in counter offset "
17386 "support detection");
17390 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17392 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17394 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17396 claim_zero(mlx5_devx_cmd_destroy(dcs));
17401 * Query a devx counter.
17404 * Pointer to the Ethernet device structure.
17406 * Index to the flow counter.
17408 * Set to clear the counter statistics.
17410 * The statistics value of packets.
17411 * @param[out] bytes
17412 * The statistics value of bytes.
17415 * 0 on success, otherwise return -1.
17418 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17419 uint64_t *pkts, uint64_t *bytes)
17421 struct mlx5_priv *priv = dev->data->dev_private;
17422 struct mlx5_flow_counter *cnt;
17423 uint64_t inn_pkts, inn_bytes;
17426 if (!priv->sh->devx)
17429 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17432 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17433 *pkts = inn_pkts - cnt->hits;
17434 *bytes = inn_bytes - cnt->bytes;
17436 cnt->hits = inn_pkts;
17437 cnt->bytes = inn_bytes;
17443 * Get aged-out flows.
17446 * Pointer to the Ethernet device structure.
17447 * @param[in] context
17448 * The address of an array of pointers to the aged-out flows contexts.
17449 * @param[in] nb_contexts
17450 * The length of context array pointers.
17451 * @param[out] error
17452 * Perform verbose error reporting if not NULL. Initialized in case of
17456 * how many contexts get in success, otherwise negative errno value.
17457 * if nb_contexts is 0, return the amount of all aged contexts.
17458 * if nb_contexts is not 0 , return the amount of aged flows reported
17459 * in the context array.
17460 * @note: only stub for now
17463 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17465 uint32_t nb_contexts,
17466 struct rte_flow_error *error)
17468 struct mlx5_priv *priv = dev->data->dev_private;
17469 struct mlx5_age_info *age_info;
17470 struct mlx5_age_param *age_param;
17471 struct mlx5_flow_counter *counter;
17472 struct mlx5_aso_age_action *act;
17475 if (nb_contexts && !context)
17476 return rte_flow_error_set(error, EINVAL,
17477 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17478 NULL, "empty context");
17479 age_info = GET_PORT_AGE_INFO(priv);
17480 rte_spinlock_lock(&age_info->aged_sl);
17481 LIST_FOREACH(act, &age_info->aged_aso, next) {
17484 context[nb_flows - 1] =
17485 act->age_params.context;
17486 if (!(--nb_contexts))
17490 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17493 age_param = MLX5_CNT_TO_AGE(counter);
17494 context[nb_flows - 1] = age_param->context;
17495 if (!(--nb_contexts))
17499 rte_spinlock_unlock(&age_info->aged_sl);
17500 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17505 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17508 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17510 return flow_dv_counter_alloc(dev, 0);
17514 * Validate indirect action.
17515 * Dispatcher for action type specific validation.
17518 * Pointer to the Ethernet device structure.
17520 * Indirect action configuration.
17521 * @param[in] action
17522 * The indirect action object to validate.
17523 * @param[out] error
17524 * Perform verbose error reporting if not NULL. Initialized in case of
17528 * 0 on success, otherwise negative errno value.
17531 flow_dv_action_validate(struct rte_eth_dev *dev,
17532 const struct rte_flow_indir_action_conf *conf,
17533 const struct rte_flow_action *action,
17534 struct rte_flow_error *err)
17536 struct mlx5_priv *priv = dev->data->dev_private;
17538 RTE_SET_USED(conf);
17539 switch (action->type) {
17540 case RTE_FLOW_ACTION_TYPE_RSS:
17542 * priv->obj_ops is set according to driver capabilities.
17543 * When DevX capabilities are
17544 * sufficient, it is set to devx_obj_ops.
17545 * Otherwise, it is set to ibv_obj_ops.
17546 * ibv_obj_ops doesn't support ind_table_modify operation.
17547 * In this case the indirect RSS action can't be used.
17549 if (priv->obj_ops.ind_table_modify == NULL)
17550 return rte_flow_error_set
17552 RTE_FLOW_ERROR_TYPE_ACTION,
17554 "Indirect RSS action not supported");
17555 return mlx5_validate_action_rss(dev, action, err);
17556 case RTE_FLOW_ACTION_TYPE_AGE:
17557 if (!priv->sh->aso_age_mng)
17558 return rte_flow_error_set(err, ENOTSUP,
17559 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17561 "Indirect age action not supported");
17562 return flow_dv_validate_action_age(0, action, dev, err);
17563 case RTE_FLOW_ACTION_TYPE_COUNT:
17564 return flow_dv_validate_action_count(dev, true, 0, err);
17565 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17566 if (!priv->sh->ct_aso_en)
17567 return rte_flow_error_set(err, ENOTSUP,
17568 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17569 "ASO CT is not supported");
17570 return mlx5_validate_action_ct(dev, action->conf, err);
17572 return rte_flow_error_set(err, ENOTSUP,
17573 RTE_FLOW_ERROR_TYPE_ACTION,
17575 "action type not supported");
17580 * Check if the RSS configurations for colors of a meter policy match
17581 * each other, except the queues.
17584 * Pointer to the first RSS flow action.
17586 * Pointer to the second RSS flow action.
17589 * 0 on match, 1 on conflict.
17592 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17593 const struct rte_flow_action_rss *r2)
17595 if (r1 == NULL || r2 == NULL)
17597 if (!(r1->level <= 1 && r2->level <= 1) &&
17598 !(r1->level > 1 && r2->level > 1))
17600 if (r1->types != r2->types &&
17601 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17602 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17604 if (r1->key || r2->key) {
17605 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17606 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17608 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17615 * Validate the meter hierarchy chain for meter policy.
17618 * Pointer to the Ethernet device structure.
17619 * @param[in] meter_id
17621 * @param[in] action_flags
17622 * Holds the actions detected until now.
17623 * @param[out] is_rss
17625 * @param[out] hierarchy_domain
17626 * The domain bitmap for hierarchy policy.
17627 * @param[out] error
17628 * Perform verbose error reporting if not NULL. Initialized in case of
17632 * 0 on success, otherwise negative errno value with error set.
17635 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17637 uint64_t action_flags,
17639 uint8_t *hierarchy_domain,
17640 struct rte_mtr_error *error)
17642 struct mlx5_priv *priv = dev->data->dev_private;
17643 struct mlx5_flow_meter_info *fm;
17644 struct mlx5_flow_meter_policy *policy;
17647 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17648 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17649 return -rte_mtr_error_set(error, EINVAL,
17650 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17652 "Multiple fate actions not supported.");
17653 *hierarchy_domain = 0;
17655 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17657 return -rte_mtr_error_set(error, EINVAL,
17658 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17659 "Meter not found in meter hierarchy.");
17660 if (fm->def_policy)
17661 return -rte_mtr_error_set(error, EINVAL,
17662 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17663 "Non termination meter not supported in hierarchy.");
17664 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17665 MLX5_ASSERT(policy);
17667 * Only inherit the supported domains of the first meter in
17669 * One meter supports at least one domain.
17671 if (!*hierarchy_domain) {
17672 if (policy->transfer)
17673 *hierarchy_domain |=
17674 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17675 if (policy->ingress)
17676 *hierarchy_domain |=
17677 MLX5_MTR_DOMAIN_INGRESS_BIT;
17678 if (policy->egress)
17679 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17681 if (!policy->is_hierarchy) {
17682 *is_rss = policy->is_rss;
17685 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17686 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17687 return -rte_mtr_error_set(error, EINVAL,
17688 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17689 "Exceed max hierarchy meter number.");
17695 * Validate meter policy actions.
17696 * Dispatcher for action type specific validation.
17699 * Pointer to the Ethernet device structure.
17700 * @param[in] action
17701 * The meter policy action object to validate.
17703 * Attributes of flow to determine steering domain.
17704 * @param[out] error
17705 * Perform verbose error reporting if not NULL. Initialized in case of
17709 * 0 on success, otherwise negative errno value.
17712 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17713 const struct rte_flow_action *actions[RTE_COLORS],
17714 struct rte_flow_attr *attr,
17716 uint8_t *domain_bitmap,
17717 uint8_t *policy_mode,
17718 struct rte_mtr_error *error)
17720 struct mlx5_priv *priv = dev->data->dev_private;
17721 struct mlx5_dev_config *dev_conf = &priv->config;
17722 const struct rte_flow_action *act;
17723 uint64_t action_flags[RTE_COLORS] = {0};
17726 struct rte_flow_error flow_err;
17727 uint8_t domain_color[RTE_COLORS] = {0};
17728 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17729 uint8_t hierarchy_domain = 0;
17730 const struct rte_flow_action_meter *mtr;
17731 bool def_green = false;
17732 bool def_yellow = false;
17733 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17735 if (!priv->config.dv_esw_en)
17736 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17737 *domain_bitmap = def_domain;
17738 /* Red color could only support DROP action. */
17739 if (!actions[RTE_COLOR_RED] ||
17740 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17741 return -rte_mtr_error_set(error, ENOTSUP,
17742 RTE_MTR_ERROR_TYPE_METER_POLICY,
17743 NULL, "Red color only supports drop action.");
17745 * Check default policy actions:
17746 * Green / Yellow: no action, Red: drop action
17747 * Either G or Y will trigger default policy actions to be created.
17749 if (!actions[RTE_COLOR_GREEN] ||
17750 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17752 if (!actions[RTE_COLOR_YELLOW] ||
17753 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17755 if (def_green && def_yellow) {
17756 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17758 } else if (!def_green && def_yellow) {
17759 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17760 } else if (def_green && !def_yellow) {
17761 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17763 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17765 /* Set to empty string in case of NULL pointer access by user. */
17766 flow_err.message = "";
17767 for (i = 0; i < RTE_COLORS; i++) {
17769 for (action_flags[i] = 0, actions_n = 0;
17770 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17772 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17773 return -rte_mtr_error_set(error, ENOTSUP,
17774 RTE_MTR_ERROR_TYPE_METER_POLICY,
17775 NULL, "too many actions");
17776 switch (act->type) {
17777 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17778 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17779 if (!priv->config.dv_esw_en)
17780 return -rte_mtr_error_set(error,
17782 RTE_MTR_ERROR_TYPE_METER_POLICY,
17783 NULL, "PORT action validate check"
17784 " fail for ESW disable");
17785 ret = flow_dv_validate_action_port_id(dev,
17787 act, attr, &flow_err);
17789 return -rte_mtr_error_set(error,
17791 RTE_MTR_ERROR_TYPE_METER_POLICY,
17792 NULL, flow_err.message ?
17794 "PORT action validate check fail");
17796 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17798 case RTE_FLOW_ACTION_TYPE_MARK:
17799 ret = flow_dv_validate_action_mark(dev, act,
17803 return -rte_mtr_error_set(error,
17805 RTE_MTR_ERROR_TYPE_METER_POLICY,
17806 NULL, flow_err.message ?
17808 "Mark action validate check fail");
17809 if (dev_conf->dv_xmeta_en !=
17810 MLX5_XMETA_MODE_LEGACY)
17811 return -rte_mtr_error_set(error,
17813 RTE_MTR_ERROR_TYPE_METER_POLICY,
17814 NULL, "Extend MARK action is "
17815 "not supported. Please try use "
17816 "default policy for meter.");
17817 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17820 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17821 ret = flow_dv_validate_action_set_tag(dev,
17822 act, action_flags[i],
17825 return -rte_mtr_error_set(error,
17827 RTE_MTR_ERROR_TYPE_METER_POLICY,
17828 NULL, flow_err.message ?
17830 "Set tag action validate check fail");
17831 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17834 case RTE_FLOW_ACTION_TYPE_DROP:
17835 ret = mlx5_flow_validate_action_drop
17836 (action_flags[i], attr, &flow_err);
17838 return -rte_mtr_error_set(error,
17840 RTE_MTR_ERROR_TYPE_METER_POLICY,
17841 NULL, flow_err.message ?
17843 "Drop action validate check fail");
17844 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17847 case RTE_FLOW_ACTION_TYPE_QUEUE:
17849 * Check whether extensive
17850 * metadata feature is engaged.
17852 if (dev_conf->dv_flow_en &&
17853 (dev_conf->dv_xmeta_en !=
17854 MLX5_XMETA_MODE_LEGACY) &&
17855 mlx5_flow_ext_mreg_supported(dev))
17856 return -rte_mtr_error_set(error,
17858 RTE_MTR_ERROR_TYPE_METER_POLICY,
17859 NULL, "Queue action with meta "
17860 "is not supported. Please try use "
17861 "default policy for meter.");
17862 ret = mlx5_flow_validate_action_queue(act,
17863 action_flags[i], dev,
17866 return -rte_mtr_error_set(error,
17868 RTE_MTR_ERROR_TYPE_METER_POLICY,
17869 NULL, flow_err.message ?
17871 "Queue action validate check fail");
17872 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17875 case RTE_FLOW_ACTION_TYPE_RSS:
17876 if (dev_conf->dv_flow_en &&
17877 (dev_conf->dv_xmeta_en !=
17878 MLX5_XMETA_MODE_LEGACY) &&
17879 mlx5_flow_ext_mreg_supported(dev))
17880 return -rte_mtr_error_set(error,
17882 RTE_MTR_ERROR_TYPE_METER_POLICY,
17883 NULL, "RSS action with meta "
17884 "is not supported. Please try use "
17885 "default policy for meter.");
17886 ret = mlx5_validate_action_rss(dev, act,
17889 return -rte_mtr_error_set(error,
17891 RTE_MTR_ERROR_TYPE_METER_POLICY,
17892 NULL, flow_err.message ?
17894 "RSS action validate check fail");
17895 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17897 /* Either G or Y will set the RSS. */
17898 rss_color[i] = act->conf;
17900 case RTE_FLOW_ACTION_TYPE_JUMP:
17901 ret = flow_dv_validate_action_jump(dev,
17902 NULL, act, action_flags[i],
17903 attr, true, &flow_err);
17905 return -rte_mtr_error_set(error,
17907 RTE_MTR_ERROR_TYPE_METER_POLICY,
17908 NULL, flow_err.message ?
17910 "Jump action validate check fail");
17912 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17915 * Only the last meter in the hierarchy will support
17916 * the YELLOW color steering. Then in the meter policy
17917 * actions list, there should be no other meter inside.
17919 case RTE_FLOW_ACTION_TYPE_METER:
17920 if (i != RTE_COLOR_GREEN)
17921 return -rte_mtr_error_set(error,
17923 RTE_MTR_ERROR_TYPE_METER_POLICY,
17925 "Meter hierarchy only supports GREEN color.");
17926 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17927 return -rte_mtr_error_set(error,
17929 RTE_MTR_ERROR_TYPE_METER_POLICY,
17931 "No yellow policy should be provided in meter hierarchy.");
17933 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17943 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17946 return -rte_mtr_error_set(error, ENOTSUP,
17947 RTE_MTR_ERROR_TYPE_METER_POLICY,
17949 "Doesn't support optional action");
17952 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
17953 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17954 } else if ((action_flags[i] &
17955 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17956 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
17958 * Only support MLX5_XMETA_MODE_LEGACY
17959 * so MARK action is only in ingress domain.
17961 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17963 domain_color[i] = def_domain;
17964 if (action_flags[i] &&
17965 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17967 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17969 if (action_flags[i] &
17970 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
17971 domain_color[i] &= hierarchy_domain;
17973 * Non-termination actions only support NIC Tx domain.
17974 * The adjustion should be skipped when there is no
17975 * action or only END is provided. The default domains
17976 * bit-mask is set to find the MIN intersection.
17977 * The action flags checking should also be skipped.
17979 if ((def_green && i == RTE_COLOR_GREEN) ||
17980 (def_yellow && i == RTE_COLOR_YELLOW))
17983 * Validate the drop action mutual exclusion
17984 * with other actions. Drop action is mutually-exclusive
17985 * with any other action, except for Count action.
17987 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
17988 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
17989 return -rte_mtr_error_set(error, ENOTSUP,
17990 RTE_MTR_ERROR_TYPE_METER_POLICY,
17991 NULL, "Drop action is mutually-exclusive "
17992 "with any other action");
17994 /* Eswitch has few restrictions on using items and actions */
17995 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
17996 if (!mlx5_flow_ext_mreg_supported(dev) &&
17997 action_flags[i] & MLX5_FLOW_ACTION_MARK)
17998 return -rte_mtr_error_set(error, ENOTSUP,
17999 RTE_MTR_ERROR_TYPE_METER_POLICY,
18000 NULL, "unsupported action MARK");
18001 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18002 return -rte_mtr_error_set(error, ENOTSUP,
18003 RTE_MTR_ERROR_TYPE_METER_POLICY,
18004 NULL, "unsupported action QUEUE");
18005 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18006 return -rte_mtr_error_set(error, ENOTSUP,
18007 RTE_MTR_ERROR_TYPE_METER_POLICY,
18008 NULL, "unsupported action RSS");
18009 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18010 return -rte_mtr_error_set(error, ENOTSUP,
18011 RTE_MTR_ERROR_TYPE_METER_POLICY,
18012 NULL, "no fate action is found");
18014 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18015 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18016 if ((domain_color[i] &
18017 MLX5_MTR_DOMAIN_EGRESS_BIT))
18019 MLX5_MTR_DOMAIN_EGRESS_BIT;
18021 return -rte_mtr_error_set(error,
18023 RTE_MTR_ERROR_TYPE_METER_POLICY,
18025 "no fate action is found");
18029 /* If both colors have RSS, the attributes should be the same. */
18030 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18031 rss_color[RTE_COLOR_YELLOW]))
18032 return -rte_mtr_error_set(error, EINVAL,
18033 RTE_MTR_ERROR_TYPE_METER_POLICY,
18034 NULL, "policy RSS attr conflict");
18035 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18037 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18038 if (!def_green && !def_yellow &&
18039 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18040 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18041 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18042 return -rte_mtr_error_set(error, EINVAL,
18043 RTE_MTR_ERROR_TYPE_METER_POLICY,
18044 NULL, "policy domains conflict");
18046 * At least one color policy is listed in the actions, the domains
18047 * to be supported should be the intersection.
18049 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18050 domain_color[RTE_COLOR_YELLOW];
18055 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18057 struct mlx5_priv *priv = dev->data->dev_private;
18060 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18061 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18066 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18067 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18071 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18072 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18080 * Discover the number of available flow priorities
18081 * by trying to create a flow with the highest priority value
18082 * for each possible number.
18087 * List of possible number of available priorities.
18088 * @param[in] vprio_n
18089 * Size of @p vprio array.
18091 * On success, number of available flow priorities.
18092 * On failure, a negative errno-style code and rte_errno is set.
18095 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18096 const uint16_t *vprio, int vprio_n)
18098 struct mlx5_priv *priv = dev->data->dev_private;
18099 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18100 struct rte_flow_item_eth eth;
18101 struct rte_flow_item item = {
18102 .type = RTE_FLOW_ITEM_TYPE_ETH,
18106 struct mlx5_flow_dv_matcher matcher = {
18108 .size = sizeof(matcher.mask.buf),
18111 union mlx5_flow_tbl_key tbl_key;
18112 struct mlx5_flow flow;
18114 struct rte_flow_error error;
18116 int i, err, ret = -ENOTSUP;
18119 * Prepare a flow with a catch-all pattern and a drop action.
18120 * Use drop queue, because shared drop action may be unavailable.
18122 action = priv->drop_queue.hrxq->action;
18123 if (action == NULL) {
18124 DRV_LOG(ERR, "Priority discovery requires a drop action");
18125 rte_errno = ENOTSUP;
18128 memset(&flow, 0, sizeof(flow));
18129 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18130 if (flow.handle == NULL) {
18131 DRV_LOG(ERR, "Cannot create flow handle");
18132 rte_errno = ENOMEM;
18135 flow.ingress = true;
18136 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18137 flow.dv.actions[0] = action;
18138 flow.dv.actions_n = 1;
18139 memset(ð, 0, sizeof(eth));
18140 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18141 &item, /* inner */ false, /* group */ 0);
18142 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18143 for (i = 0; i < vprio_n; i++) {
18144 /* Configure the next proposed maximum priority. */
18145 matcher.priority = vprio[i] - 1;
18146 memset(&tbl_key, 0, sizeof(tbl_key));
18147 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18152 /* This action is pure SW and must always succeed. */
18153 DRV_LOG(ERR, "Cannot register matcher");
18157 /* Try to apply the flow to HW. */
18158 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18159 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18160 err = mlx5_flow_os_create_flow
18161 (flow.handle->dvh.matcher->matcher_object,
18162 (void *)&flow.dv.value, flow.dv.actions_n,
18163 flow.dv.actions, &flow.handle->drv_flow);
18165 claim_zero(mlx5_flow_os_destroy_flow
18166 (flow.handle->drv_flow));
18167 flow.handle->drv_flow = NULL;
18169 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18174 mlx5_ipool_free(pool, flow.handle_idx);
18175 /* Set rte_errno if no expected priority value matched. */
18181 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18182 .validate = flow_dv_validate,
18183 .prepare = flow_dv_prepare,
18184 .translate = flow_dv_translate,
18185 .apply = flow_dv_apply,
18186 .remove = flow_dv_remove,
18187 .destroy = flow_dv_destroy,
18188 .query = flow_dv_query,
18189 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18190 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18191 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18192 .create_meter = flow_dv_mtr_alloc,
18193 .free_meter = flow_dv_aso_mtr_release_to_pool,
18194 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18195 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18196 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18197 .create_policy_rules = flow_dv_create_policy_rules,
18198 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18199 .create_def_policy = flow_dv_create_def_policy,
18200 .destroy_def_policy = flow_dv_destroy_def_policy,
18201 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18202 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18203 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18204 .counter_alloc = flow_dv_counter_allocate,
18205 .counter_free = flow_dv_counter_free,
18206 .counter_query = flow_dv_counter_query,
18207 .get_aged_flows = flow_dv_get_aged_flows,
18208 .action_validate = flow_dv_action_validate,
18209 .action_create = flow_dv_action_create,
18210 .action_destroy = flow_dv_action_destroy,
18211 .action_update = flow_dv_action_update,
18212 .action_query = flow_dv_action_query,
18213 .sync_domain = flow_dv_sync_domain,
18214 .discover_priorities = flow_dv_discover_priorities,
18215 .item_create = flow_dv_item_create,
18216 .item_release = flow_dv_item_release,
18219 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */