1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <rte_mtr_driver.h>
26 #include <rte_tailq.h>
28 #include <mlx5_glue.h>
29 #include <mlx5_devx_cmds.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_common_os.h"
36 #include "mlx5_flow.h"
37 #include "mlx5_flow_os.h"
40 #include "rte_pmd_mlx5.h"
42 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
48 #ifndef HAVE_MLX5DV_DR_ESWITCH
49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
54 #ifndef HAVE_MLX5DV_DR
55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
58 /* VLAN header definitions */
59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
78 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
79 struct mlx5_flow_tbl_resource *tbl);
82 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
83 uint32_t encap_decap_idx);
86 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
89 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
92 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 * Initialize flow attributes structure according to flow items' types.
98 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
99 * mode. For tunnel mode, the items to be modified are the outermost ones.
102 * Pointer to item specification.
104 * Pointer to flow attributes structure.
105 * @param[in] dev_flow
106 * Pointer to the sub flow.
107 * @param[in] tunnel_decap
108 * Whether action is after tunnel decapsulation.
111 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
112 struct mlx5_flow *dev_flow, bool tunnel_decap)
114 uint64_t layers = dev_flow->handle->layers;
117 * If layers is already initialized, it means this dev_flow is the
118 * suffix flow, the layers flags is set by the prefix flow. Need to
119 * use the layer flags from prefix flow as the suffix flow may not
120 * have the user defined items as the flow is split.
123 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
127 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
129 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
134 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
135 uint8_t next_protocol = 0xff;
136 switch (item->type) {
137 case RTE_FLOW_ITEM_TYPE_GRE:
138 case RTE_FLOW_ITEM_TYPE_NVGRE:
139 case RTE_FLOW_ITEM_TYPE_VXLAN:
140 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
141 case RTE_FLOW_ITEM_TYPE_GENEVE:
142 case RTE_FLOW_ITEM_TYPE_MPLS:
146 case RTE_FLOW_ITEM_TYPE_IPV4:
149 if (item->mask != NULL &&
150 ((const struct rte_flow_item_ipv4 *)
151 item->mask)->hdr.next_proto_id)
153 ((const struct rte_flow_item_ipv4 *)
154 (item->spec))->hdr.next_proto_id &
155 ((const struct rte_flow_item_ipv4 *)
156 (item->mask))->hdr.next_proto_id;
157 if ((next_protocol == IPPROTO_IPIP ||
158 next_protocol == IPPROTO_IPV6) && tunnel_decap)
161 case RTE_FLOW_ITEM_TYPE_IPV6:
164 if (item->mask != NULL &&
165 ((const struct rte_flow_item_ipv6 *)
166 item->mask)->hdr.proto)
168 ((const struct rte_flow_item_ipv6 *)
169 (item->spec))->hdr.proto &
170 ((const struct rte_flow_item_ipv6 *)
171 (item->mask))->hdr.proto;
172 if ((next_protocol == IPPROTO_IPIP ||
173 next_protocol == IPPROTO_IPV6) && tunnel_decap)
176 case RTE_FLOW_ITEM_TYPE_UDP:
180 case RTE_FLOW_ITEM_TYPE_TCP:
192 * Convert rte_mtr_color to mlx5 color.
201 rte_col_2_mlx5_col(enum rte_color rcol)
204 case RTE_COLOR_GREEN:
205 return MLX5_FLOW_COLOR_GREEN;
206 case RTE_COLOR_YELLOW:
207 return MLX5_FLOW_COLOR_YELLOW;
209 return MLX5_FLOW_COLOR_RED;
213 return MLX5_FLOW_COLOR_UNDEFINED;
216 struct field_modify_info {
217 uint32_t size; /* Size of field in protocol header, in bytes. */
218 uint32_t offset; /* Offset of field in protocol header, in bytes. */
219 enum mlx5_modification_field id;
222 struct field_modify_info modify_eth[] = {
223 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
224 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
225 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
226 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
230 struct field_modify_info modify_vlan_out_first_vid[] = {
231 /* Size in bits !!! */
232 {12, 0, MLX5_MODI_OUT_FIRST_VID},
236 struct field_modify_info modify_ipv4[] = {
237 {1, 1, MLX5_MODI_OUT_IP_DSCP},
238 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
239 {4, 12, MLX5_MODI_OUT_SIPV4},
240 {4, 16, MLX5_MODI_OUT_DIPV4},
244 struct field_modify_info modify_ipv6[] = {
245 {1, 0, MLX5_MODI_OUT_IP_DSCP},
246 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
247 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
248 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
249 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
250 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
251 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
252 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
253 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
254 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
258 struct field_modify_info modify_udp[] = {
259 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
260 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
264 struct field_modify_info modify_tcp[] = {
265 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
266 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
267 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
268 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
272 static const struct rte_flow_item *
273 mlx5_flow_find_tunnel_item(const struct rte_flow_item *item)
275 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
276 switch (item->type) {
279 case RTE_FLOW_ITEM_TYPE_VXLAN:
280 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
281 case RTE_FLOW_ITEM_TYPE_GRE:
282 case RTE_FLOW_ITEM_TYPE_MPLS:
283 case RTE_FLOW_ITEM_TYPE_NVGRE:
284 case RTE_FLOW_ITEM_TYPE_GENEVE:
286 case RTE_FLOW_ITEM_TYPE_IPV4:
287 case RTE_FLOW_ITEM_TYPE_IPV6:
288 if (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 ||
289 item[1].type == RTE_FLOW_ITEM_TYPE_IPV6)
298 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
299 uint8_t next_protocol, uint64_t *item_flags,
302 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
303 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
304 if (next_protocol == IPPROTO_IPIP) {
305 *item_flags |= MLX5_FLOW_LAYER_IPIP;
308 if (next_protocol == IPPROTO_IPV6) {
309 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
314 static inline struct mlx5_hlist *
315 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
316 const char *name, uint32_t size, bool direct_key,
317 bool lcores_share, void *ctx,
318 mlx5_list_create_cb cb_create,
319 mlx5_list_match_cb cb_match,
320 mlx5_list_remove_cb cb_remove,
321 mlx5_list_clone_cb cb_clone,
322 mlx5_list_clone_free_cb cb_clone_free)
324 struct mlx5_hlist *hl;
325 struct mlx5_hlist *expected = NULL;
326 char s[MLX5_NAME_SIZE];
328 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
331 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
332 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
333 ctx, cb_create, cb_match, cb_remove, cb_clone,
336 DRV_LOG(ERR, "%s hash creation failed", name);
340 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
343 mlx5_hlist_destroy(hl);
344 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
349 /* Update VLAN's VID/PCP based on input rte_flow_action.
352 * Pointer to struct rte_flow_action.
354 * Pointer to struct rte_vlan_hdr.
357 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
358 struct rte_vlan_hdr *vlan)
361 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
363 ((const struct rte_flow_action_of_set_vlan_pcp *)
364 action->conf)->vlan_pcp;
365 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
366 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
367 vlan->vlan_tci |= vlan_tci;
368 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
369 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
370 vlan->vlan_tci |= rte_be_to_cpu_16
371 (((const struct rte_flow_action_of_set_vlan_vid *)
372 action->conf)->vlan_vid);
377 * Fetch 1, 2, 3 or 4 byte field from the byte array
378 * and return as unsigned integer in host-endian format.
381 * Pointer to data array.
383 * Size of field to extract.
386 * converted field in host endian format.
388 static inline uint32_t
389 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
398 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
401 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
402 ret = (ret << 8) | *(data + sizeof(uint16_t));
405 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
416 * Convert modify-header action to DV specification.
418 * Data length of each action is determined by provided field description
419 * and the item mask. Data bit offset and width of each action is determined
420 * by provided item mask.
423 * Pointer to item specification.
425 * Pointer to field modification information.
426 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
427 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
428 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
430 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
431 * Negative offset value sets the same offset as source offset.
432 * size field is ignored, value is taken from source field.
433 * @param[in,out] resource
434 * Pointer to the modify-header resource.
436 * Type of modification.
438 * Pointer to the error structure.
441 * 0 on success, a negative errno value otherwise and rte_errno is set.
444 flow_dv_convert_modify_action(struct rte_flow_item *item,
445 struct field_modify_info *field,
446 struct field_modify_info *dcopy,
447 struct mlx5_flow_dv_modify_hdr_resource *resource,
448 uint32_t type, struct rte_flow_error *error)
450 uint32_t i = resource->actions_num;
451 struct mlx5_modification_cmd *actions = resource->actions;
452 uint32_t carry_b = 0;
455 * The item and mask are provided in big-endian format.
456 * The fields should be presented as in big-endian format either.
457 * Mask must be always present, it defines the actual field width.
459 MLX5_ASSERT(item->mask);
460 MLX5_ASSERT(field->size);
466 bool next_field = true;
467 bool next_dcopy = true;
469 if (i >= MLX5_MAX_MODIFY_NUM)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "too many items to modify");
473 /* Fetch variable byte size mask from the array. */
474 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
475 field->offset, field->size);
480 /* Deduce actual data width in bits from mask value. */
481 off_b = rte_bsf32(mask) + carry_b;
482 size_b = sizeof(uint32_t) * CHAR_BIT -
483 off_b - __builtin_clz(mask);
485 actions[i] = (struct mlx5_modification_cmd) {
489 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
492 if (type == MLX5_MODIFICATION_TYPE_COPY) {
494 actions[i].dst_field = dcopy->id;
495 actions[i].dst_offset =
496 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
497 /* Convert entire record to big-endian format. */
498 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
500 * Destination field overflow. Copy leftovers of
501 * a source field to the next destination field.
504 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
507 dcopy->size * CHAR_BIT - dcopy->offset;
508 carry_b = actions[i].length;
512 * Not enough bits in a source filed to fill a
513 * destination field. Switch to the next source.
515 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
516 (size_b == field->size * CHAR_BIT - off_b)) {
518 field->size * CHAR_BIT - off_b;
519 dcopy->offset += actions[i].length;
525 MLX5_ASSERT(item->spec);
526 data = flow_dv_fetch_field((const uint8_t *)item->spec +
527 field->offset, field->size);
528 /* Shift out the trailing masked bits from data. */
529 data = (data & mask) >> off_b;
530 actions[i].data1 = rte_cpu_to_be_32(data);
532 /* Convert entire record to expected big-endian format. */
533 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
537 } while (field->size);
538 if (resource->actions_num == i)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "invalid modification flow item");
542 resource->actions_num = i;
547 * Convert modify-header set IPv4 address action to DV specification.
549 * @param[in,out] resource
550 * Pointer to the modify-header resource.
552 * Pointer to action specification.
554 * Pointer to the error structure.
557 * 0 on success, a negative errno value otherwise and rte_errno is set.
560 flow_dv_convert_action_modify_ipv4
561 (struct mlx5_flow_dv_modify_hdr_resource *resource,
562 const struct rte_flow_action *action,
563 struct rte_flow_error *error)
565 const struct rte_flow_action_set_ipv4 *conf =
566 (const struct rte_flow_action_set_ipv4 *)(action->conf);
567 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
568 struct rte_flow_item_ipv4 ipv4;
569 struct rte_flow_item_ipv4 ipv4_mask;
571 memset(&ipv4, 0, sizeof(ipv4));
572 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
573 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
574 ipv4.hdr.src_addr = conf->ipv4_addr;
575 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
577 ipv4.hdr.dst_addr = conf->ipv4_addr;
578 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
581 item.mask = &ipv4_mask;
582 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set IPv6 address action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_ipv6
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_set_ipv6 *conf =
606 (const struct rte_flow_action_set_ipv6 *)(action->conf);
607 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
608 struct rte_flow_item_ipv6 ipv6;
609 struct rte_flow_item_ipv6 ipv6_mask;
611 memset(&ipv6, 0, sizeof(ipv6));
612 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
613 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
614 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
615 sizeof(ipv6.hdr.src_addr));
616 memcpy(&ipv6_mask.hdr.src_addr,
617 &rte_flow_item_ipv6_mask.hdr.src_addr,
618 sizeof(ipv6.hdr.src_addr));
620 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
621 sizeof(ipv6.hdr.dst_addr));
622 memcpy(&ipv6_mask.hdr.dst_addr,
623 &rte_flow_item_ipv6_mask.hdr.dst_addr,
624 sizeof(ipv6.hdr.dst_addr));
627 item.mask = &ipv6_mask;
628 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
629 MLX5_MODIFICATION_TYPE_SET, error);
633 * Convert modify-header set MAC address action to DV specification.
635 * @param[in,out] resource
636 * Pointer to the modify-header resource.
638 * Pointer to action specification.
640 * Pointer to the error structure.
643 * 0 on success, a negative errno value otherwise and rte_errno is set.
646 flow_dv_convert_action_modify_mac
647 (struct mlx5_flow_dv_modify_hdr_resource *resource,
648 const struct rte_flow_action *action,
649 struct rte_flow_error *error)
651 const struct rte_flow_action_set_mac *conf =
652 (const struct rte_flow_action_set_mac *)(action->conf);
653 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
654 struct rte_flow_item_eth eth;
655 struct rte_flow_item_eth eth_mask;
657 memset(ð, 0, sizeof(eth));
658 memset(ð_mask, 0, sizeof(eth_mask));
659 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
660 memcpy(ð.src.addr_bytes, &conf->mac_addr,
661 sizeof(eth.src.addr_bytes));
662 memcpy(ð_mask.src.addr_bytes,
663 &rte_flow_item_eth_mask.src.addr_bytes,
664 sizeof(eth_mask.src.addr_bytes));
666 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
667 sizeof(eth.dst.addr_bytes));
668 memcpy(ð_mask.dst.addr_bytes,
669 &rte_flow_item_eth_mask.dst.addr_bytes,
670 sizeof(eth_mask.dst.addr_bytes));
673 item.mask = ð_mask;
674 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
675 MLX5_MODIFICATION_TYPE_SET, error);
679 * Convert modify-header set VLAN VID action to DV specification.
681 * @param[in,out] resource
682 * Pointer to the modify-header resource.
684 * Pointer to action specification.
686 * Pointer to the error structure.
689 * 0 on success, a negative errno value otherwise and rte_errno is set.
692 flow_dv_convert_action_modify_vlan_vid
693 (struct mlx5_flow_dv_modify_hdr_resource *resource,
694 const struct rte_flow_action *action,
695 struct rte_flow_error *error)
697 const struct rte_flow_action_of_set_vlan_vid *conf =
698 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
699 int i = resource->actions_num;
700 struct mlx5_modification_cmd *actions = resource->actions;
701 struct field_modify_info *field = modify_vlan_out_first_vid;
703 if (i >= MLX5_MAX_MODIFY_NUM)
704 return rte_flow_error_set(error, EINVAL,
705 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
706 "too many items to modify");
707 actions[i] = (struct mlx5_modification_cmd) {
708 .action_type = MLX5_MODIFICATION_TYPE_SET,
710 .length = field->size,
711 .offset = field->offset,
713 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
714 actions[i].data1 = conf->vlan_vid;
715 actions[i].data1 = actions[i].data1 << 16;
716 resource->actions_num = ++i;
721 * Convert modify-header set TP action to DV specification.
723 * @param[in,out] resource
724 * Pointer to the modify-header resource.
726 * Pointer to action specification.
728 * Pointer to rte_flow_item objects list.
730 * Pointer to flow attributes structure.
731 * @param[in] dev_flow
732 * Pointer to the sub flow.
733 * @param[in] tunnel_decap
734 * Whether action is after tunnel decapsulation.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_tp
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_action *action,
745 const struct rte_flow_item *items,
746 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
747 bool tunnel_decap, struct rte_flow_error *error)
749 const struct rte_flow_action_set_tp *conf =
750 (const struct rte_flow_action_set_tp *)(action->conf);
751 struct rte_flow_item item;
752 struct rte_flow_item_udp udp;
753 struct rte_flow_item_udp udp_mask;
754 struct rte_flow_item_tcp tcp;
755 struct rte_flow_item_tcp tcp_mask;
756 struct field_modify_info *field;
759 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
761 memset(&udp, 0, sizeof(udp));
762 memset(&udp_mask, 0, sizeof(udp_mask));
763 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
764 udp.hdr.src_port = conf->port;
765 udp_mask.hdr.src_port =
766 rte_flow_item_udp_mask.hdr.src_port;
768 udp.hdr.dst_port = conf->port;
769 udp_mask.hdr.dst_port =
770 rte_flow_item_udp_mask.hdr.dst_port;
772 item.type = RTE_FLOW_ITEM_TYPE_UDP;
774 item.mask = &udp_mask;
777 MLX5_ASSERT(attr->tcp);
778 memset(&tcp, 0, sizeof(tcp));
779 memset(&tcp_mask, 0, sizeof(tcp_mask));
780 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
781 tcp.hdr.src_port = conf->port;
782 tcp_mask.hdr.src_port =
783 rte_flow_item_tcp_mask.hdr.src_port;
785 tcp.hdr.dst_port = conf->port;
786 tcp_mask.hdr.dst_port =
787 rte_flow_item_tcp_mask.hdr.dst_port;
789 item.type = RTE_FLOW_ITEM_TYPE_TCP;
791 item.mask = &tcp_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header set TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_action *action,
823 const struct rte_flow_item *items,
824 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
825 bool tunnel_decap, struct rte_flow_error *error)
827 const struct rte_flow_action_set_ttl *conf =
828 (const struct rte_flow_action_set_ttl *)(action->conf);
829 struct rte_flow_item item;
830 struct rte_flow_item_ipv4 ipv4;
831 struct rte_flow_item_ipv4 ipv4_mask;
832 struct rte_flow_item_ipv6 ipv6;
833 struct rte_flow_item_ipv6 ipv6_mask;
834 struct field_modify_info *field;
837 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
839 memset(&ipv4, 0, sizeof(ipv4));
840 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
841 ipv4.hdr.time_to_live = conf->ttl_value;
842 ipv4_mask.hdr.time_to_live = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
845 item.mask = &ipv4_mask;
848 MLX5_ASSERT(attr->ipv6);
849 memset(&ipv6, 0, sizeof(ipv6));
850 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
851 ipv6.hdr.hop_limits = conf->ttl_value;
852 ipv6_mask.hdr.hop_limits = 0xFF;
853 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
855 item.mask = &ipv6_mask;
858 return flow_dv_convert_modify_action(&item, field, NULL, resource,
859 MLX5_MODIFICATION_TYPE_SET, error);
863 * Convert modify-header decrement TTL action to DV specification.
865 * @param[in,out] resource
866 * Pointer to the modify-header resource.
868 * Pointer to action specification.
870 * Pointer to rte_flow_item objects list.
872 * Pointer to flow attributes structure.
873 * @param[in] dev_flow
874 * Pointer to the sub flow.
875 * @param[in] tunnel_decap
876 * Whether action is after tunnel decapsulation.
878 * Pointer to the error structure.
881 * 0 on success, a negative errno value otherwise and rte_errno is set.
884 flow_dv_convert_action_modify_dec_ttl
885 (struct mlx5_flow_dv_modify_hdr_resource *resource,
886 const struct rte_flow_item *items,
887 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
888 bool tunnel_decap, struct rte_flow_error *error)
890 struct rte_flow_item item;
891 struct rte_flow_item_ipv4 ipv4;
892 struct rte_flow_item_ipv4 ipv4_mask;
893 struct rte_flow_item_ipv6 ipv6;
894 struct rte_flow_item_ipv6 ipv6_mask;
895 struct field_modify_info *field;
898 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
900 memset(&ipv4, 0, sizeof(ipv4));
901 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
902 ipv4.hdr.time_to_live = 0xFF;
903 ipv4_mask.hdr.time_to_live = 0xFF;
904 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
906 item.mask = &ipv4_mask;
909 MLX5_ASSERT(attr->ipv6);
910 memset(&ipv6, 0, sizeof(ipv6));
911 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
912 ipv6.hdr.hop_limits = 0xFF;
913 ipv6_mask.hdr.hop_limits = 0xFF;
914 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
916 item.mask = &ipv6_mask;
919 return flow_dv_convert_modify_action(&item, field, NULL, resource,
920 MLX5_MODIFICATION_TYPE_ADD, error);
924 * Convert modify-header increment/decrement TCP Sequence number
925 * to DV specification.
927 * @param[in,out] resource
928 * Pointer to the modify-header resource.
930 * Pointer to action specification.
932 * Pointer to the error structure.
935 * 0 on success, a negative errno value otherwise and rte_errno is set.
938 flow_dv_convert_action_modify_tcp_seq
939 (struct mlx5_flow_dv_modify_hdr_resource *resource,
940 const struct rte_flow_action *action,
941 struct rte_flow_error *error)
943 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
944 uint64_t value = rte_be_to_cpu_32(*conf);
945 struct rte_flow_item item;
946 struct rte_flow_item_tcp tcp;
947 struct rte_flow_item_tcp tcp_mask;
949 memset(&tcp, 0, sizeof(tcp));
950 memset(&tcp_mask, 0, sizeof(tcp_mask));
951 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
953 * The HW has no decrement operation, only increment operation.
954 * To simulate decrement X from Y using increment operation
955 * we need to add UINT32_MAX X times to Y.
956 * Each adding of UINT32_MAX decrements Y by 1.
959 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
960 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
961 item.type = RTE_FLOW_ITEM_TYPE_TCP;
963 item.mask = &tcp_mask;
964 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
965 MLX5_MODIFICATION_TYPE_ADD, error);
969 * Convert modify-header increment/decrement TCP Acknowledgment number
970 * to DV specification.
972 * @param[in,out] resource
973 * Pointer to the modify-header resource.
975 * Pointer to action specification.
977 * Pointer to the error structure.
980 * 0 on success, a negative errno value otherwise and rte_errno is set.
983 flow_dv_convert_action_modify_tcp_ack
984 (struct mlx5_flow_dv_modify_hdr_resource *resource,
985 const struct rte_flow_action *action,
986 struct rte_flow_error *error)
988 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
989 uint64_t value = rte_be_to_cpu_32(*conf);
990 struct rte_flow_item item;
991 struct rte_flow_item_tcp tcp;
992 struct rte_flow_item_tcp tcp_mask;
994 memset(&tcp, 0, sizeof(tcp));
995 memset(&tcp_mask, 0, sizeof(tcp_mask));
996 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
998 * The HW has no decrement operation, only increment operation.
999 * To simulate decrement X from Y using increment operation
1000 * we need to add UINT32_MAX X times to Y.
1001 * Each adding of UINT32_MAX decrements Y by 1.
1003 value *= UINT32_MAX;
1004 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1005 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1006 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1008 item.mask = &tcp_mask;
1009 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1010 MLX5_MODIFICATION_TYPE_ADD, error);
1013 static enum mlx5_modification_field reg_to_field[] = {
1014 [REG_NON] = MLX5_MODI_OUT_NONE,
1015 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1016 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1017 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1018 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1019 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1020 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1021 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1022 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1023 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1024 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1028 * Convert register set to DV specification.
1030 * @param[in,out] resource
1031 * Pointer to the modify-header resource.
1033 * Pointer to action specification.
1035 * Pointer to the error structure.
1038 * 0 on success, a negative errno value otherwise and rte_errno is set.
1041 flow_dv_convert_action_set_reg
1042 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1043 const struct rte_flow_action *action,
1044 struct rte_flow_error *error)
1046 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1047 struct mlx5_modification_cmd *actions = resource->actions;
1048 uint32_t i = resource->actions_num;
1050 if (i >= MLX5_MAX_MODIFY_NUM)
1051 return rte_flow_error_set(error, EINVAL,
1052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1053 "too many items to modify");
1054 MLX5_ASSERT(conf->id != REG_NON);
1055 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1056 actions[i] = (struct mlx5_modification_cmd) {
1057 .action_type = MLX5_MODIFICATION_TYPE_SET,
1058 .field = reg_to_field[conf->id],
1059 .offset = conf->offset,
1060 .length = conf->length,
1062 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1063 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1065 resource->actions_num = i;
1070 * Convert SET_TAG action to DV specification.
1073 * Pointer to the rte_eth_dev structure.
1074 * @param[in,out] resource
1075 * Pointer to the modify-header resource.
1077 * Pointer to action specification.
1079 * Pointer to the error structure.
1082 * 0 on success, a negative errno value otherwise and rte_errno is set.
1085 flow_dv_convert_action_set_tag
1086 (struct rte_eth_dev *dev,
1087 struct mlx5_flow_dv_modify_hdr_resource *resource,
1088 const struct rte_flow_action_set_tag *conf,
1089 struct rte_flow_error *error)
1091 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1092 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1093 struct rte_flow_item item = {
1097 struct field_modify_info reg_c_x[] = {
1100 enum mlx5_modification_field reg_type;
1103 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1106 MLX5_ASSERT(ret != REG_NON);
1107 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1108 reg_type = reg_to_field[ret];
1109 MLX5_ASSERT(reg_type > 0);
1110 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1111 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1112 MLX5_MODIFICATION_TYPE_SET, error);
1116 * Convert internal COPY_REG action to DV specification.
1119 * Pointer to the rte_eth_dev structure.
1120 * @param[in,out] res
1121 * Pointer to the modify-header resource.
1123 * Pointer to action specification.
1125 * Pointer to the error structure.
1128 * 0 on success, a negative errno value otherwise and rte_errno is set.
1131 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1132 struct mlx5_flow_dv_modify_hdr_resource *res,
1133 const struct rte_flow_action *action,
1134 struct rte_flow_error *error)
1136 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1137 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1138 struct rte_flow_item item = {
1142 struct field_modify_info reg_src[] = {
1143 {4, 0, reg_to_field[conf->src]},
1146 struct field_modify_info reg_dst = {
1148 .id = reg_to_field[conf->dst],
1150 /* Adjust reg_c[0] usage according to reported mask. */
1151 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1152 struct mlx5_priv *priv = dev->data->dev_private;
1153 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1155 MLX5_ASSERT(reg_c0);
1156 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1157 if (conf->dst == REG_C_0) {
1158 /* Copy to reg_c[0], within mask only. */
1159 reg_dst.offset = rte_bsf32(reg_c0);
1161 * Mask is ignoring the enianness, because
1162 * there is no conversion in datapath.
1164 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1165 /* Copy from destination lower bits to reg_c[0]. */
1166 mask = reg_c0 >> reg_dst.offset;
1168 /* Copy from destination upper bits to reg_c[0]. */
1169 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1170 rte_fls_u32(reg_c0));
1173 mask = rte_cpu_to_be_32(reg_c0);
1174 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1175 /* Copy from reg_c[0] to destination lower bits. */
1178 /* Copy from reg_c[0] to destination upper bits. */
1179 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1180 (rte_fls_u32(reg_c0) -
1185 return flow_dv_convert_modify_action(&item,
1186 reg_src, ®_dst, res,
1187 MLX5_MODIFICATION_TYPE_COPY,
1192 * Convert MARK action to DV specification. This routine is used
1193 * in extensive metadata only and requires metadata register to be
1194 * handled. In legacy mode hardware tag resource is engaged.
1197 * Pointer to the rte_eth_dev structure.
1199 * Pointer to MARK action specification.
1200 * @param[in,out] resource
1201 * Pointer to the modify-header resource.
1203 * Pointer to the error structure.
1206 * 0 on success, a negative errno value otherwise and rte_errno is set.
1209 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1210 const struct rte_flow_action_mark *conf,
1211 struct mlx5_flow_dv_modify_hdr_resource *resource,
1212 struct rte_flow_error *error)
1214 struct mlx5_priv *priv = dev->data->dev_private;
1215 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1216 priv->sh->dv_mark_mask);
1217 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1218 struct rte_flow_item item = {
1222 struct field_modify_info reg_c_x[] = {
1228 return rte_flow_error_set(error, EINVAL,
1229 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1230 NULL, "zero mark action mask");
1231 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1234 MLX5_ASSERT(reg > 0);
1235 if (reg == REG_C_0) {
1236 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1237 uint32_t shl_c0 = rte_bsf32(msk_c0);
1239 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1240 mask = rte_cpu_to_be_32(mask) & msk_c0;
1241 mask = rte_cpu_to_be_32(mask << shl_c0);
1243 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1244 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1245 MLX5_MODIFICATION_TYPE_SET, error);
1249 * Get metadata register index for specified steering domain.
1252 * Pointer to the rte_eth_dev structure.
1254 * Attributes of flow to determine steering domain.
1256 * Pointer to the error structure.
1259 * positive index on success, a negative errno value otherwise
1260 * and rte_errno is set.
1262 static enum modify_reg
1263 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1264 const struct rte_flow_attr *attr,
1265 struct rte_flow_error *error)
1268 mlx5_flow_get_reg_id(dev, attr->transfer ?
1272 MLX5_METADATA_RX, 0, error);
1274 return rte_flow_error_set(error,
1275 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1276 NULL, "unavailable "
1277 "metadata register");
1282 * Convert SET_META action to DV specification.
1285 * Pointer to the rte_eth_dev structure.
1286 * @param[in,out] resource
1287 * Pointer to the modify-header resource.
1289 * Attributes of flow that includes this item.
1291 * Pointer to action specification.
1293 * Pointer to the error structure.
1296 * 0 on success, a negative errno value otherwise and rte_errno is set.
1299 flow_dv_convert_action_set_meta
1300 (struct rte_eth_dev *dev,
1301 struct mlx5_flow_dv_modify_hdr_resource *resource,
1302 const struct rte_flow_attr *attr,
1303 const struct rte_flow_action_set_meta *conf,
1304 struct rte_flow_error *error)
1306 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1307 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1308 struct rte_flow_item item = {
1312 struct field_modify_info reg_c_x[] = {
1315 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1319 MLX5_ASSERT(reg != REG_NON);
1320 if (reg == REG_C_0) {
1321 struct mlx5_priv *priv = dev->data->dev_private;
1322 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1323 uint32_t shl_c0 = rte_bsf32(msk_c0);
1325 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1326 mask = rte_cpu_to_be_32(mask) & msk_c0;
1327 mask = rte_cpu_to_be_32(mask << shl_c0);
1329 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1330 /* The routine expects parameters in memory as big-endian ones. */
1331 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1332 MLX5_MODIFICATION_TYPE_SET, error);
1336 * Convert modify-header set IPv4 DSCP action to DV specification.
1338 * @param[in,out] resource
1339 * Pointer to the modify-header resource.
1341 * Pointer to action specification.
1343 * Pointer to the error structure.
1346 * 0 on success, a negative errno value otherwise and rte_errno is set.
1349 flow_dv_convert_action_modify_ipv4_dscp
1350 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1351 const struct rte_flow_action *action,
1352 struct rte_flow_error *error)
1354 const struct rte_flow_action_set_dscp *conf =
1355 (const struct rte_flow_action_set_dscp *)(action->conf);
1356 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1357 struct rte_flow_item_ipv4 ipv4;
1358 struct rte_flow_item_ipv4 ipv4_mask;
1360 memset(&ipv4, 0, sizeof(ipv4));
1361 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1362 ipv4.hdr.type_of_service = conf->dscp;
1363 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1365 item.mask = &ipv4_mask;
1366 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1367 MLX5_MODIFICATION_TYPE_SET, error);
1371 * Convert modify-header set IPv6 DSCP action to DV specification.
1373 * @param[in,out] resource
1374 * Pointer to the modify-header resource.
1376 * Pointer to action specification.
1378 * Pointer to the error structure.
1381 * 0 on success, a negative errno value otherwise and rte_errno is set.
1384 flow_dv_convert_action_modify_ipv6_dscp
1385 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1386 const struct rte_flow_action *action,
1387 struct rte_flow_error *error)
1389 const struct rte_flow_action_set_dscp *conf =
1390 (const struct rte_flow_action_set_dscp *)(action->conf);
1391 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1392 struct rte_flow_item_ipv6 ipv6;
1393 struct rte_flow_item_ipv6 ipv6_mask;
1395 memset(&ipv6, 0, sizeof(ipv6));
1396 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1398 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1399 * rdma-core only accept the DSCP bits byte aligned start from
1400 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1401 * bits in IPv6 case as rdma-core requires byte aligned value.
1403 ipv6.hdr.vtc_flow = conf->dscp;
1404 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1406 item.mask = &ipv6_mask;
1407 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1408 MLX5_MODIFICATION_TYPE_SET, error);
1412 mlx5_flow_item_field_width(struct mlx5_dev_config *config,
1413 enum rte_flow_field_id field)
1416 case RTE_FLOW_FIELD_START:
1418 case RTE_FLOW_FIELD_MAC_DST:
1419 case RTE_FLOW_FIELD_MAC_SRC:
1421 case RTE_FLOW_FIELD_VLAN_TYPE:
1423 case RTE_FLOW_FIELD_VLAN_ID:
1425 case RTE_FLOW_FIELD_MAC_TYPE:
1427 case RTE_FLOW_FIELD_IPV4_DSCP:
1429 case RTE_FLOW_FIELD_IPV4_TTL:
1431 case RTE_FLOW_FIELD_IPV4_SRC:
1432 case RTE_FLOW_FIELD_IPV4_DST:
1434 case RTE_FLOW_FIELD_IPV6_DSCP:
1436 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1438 case RTE_FLOW_FIELD_IPV6_SRC:
1439 case RTE_FLOW_FIELD_IPV6_DST:
1441 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1442 case RTE_FLOW_FIELD_TCP_PORT_DST:
1444 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1445 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1447 case RTE_FLOW_FIELD_TCP_FLAGS:
1449 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1450 case RTE_FLOW_FIELD_UDP_PORT_DST:
1452 case RTE_FLOW_FIELD_VXLAN_VNI:
1453 case RTE_FLOW_FIELD_GENEVE_VNI:
1455 case RTE_FLOW_FIELD_GTP_TEID:
1456 case RTE_FLOW_FIELD_TAG:
1458 case RTE_FLOW_FIELD_MARK:
1460 case RTE_FLOW_FIELD_META:
1461 if (config->dv_xmeta_en == MLX5_XMETA_MODE_META16)
1463 else if (config->dv_xmeta_en == MLX5_XMETA_MODE_META32)
1467 case RTE_FLOW_FIELD_POINTER:
1468 case RTE_FLOW_FIELD_VALUE:
1477 mlx5_flow_field_id_to_modify_info
1478 (const struct rte_flow_action_modify_data *data,
1479 struct field_modify_info *info,
1480 uint32_t *mask, uint32_t *value,
1481 uint32_t width, uint32_t dst_width,
1482 struct rte_eth_dev *dev,
1483 const struct rte_flow_attr *attr,
1484 struct rte_flow_error *error)
1486 struct mlx5_priv *priv = dev->data->dev_private;
1487 struct mlx5_dev_config *config = &priv->config;
1491 switch (data->field) {
1492 case RTE_FLOW_FIELD_START:
1493 /* not supported yet */
1496 case RTE_FLOW_FIELD_MAC_DST:
1497 off = data->offset > 16 ? data->offset - 16 : 0;
1499 if (data->offset < 16) {
1500 info[idx] = (struct field_modify_info){2, 0,
1501 MLX5_MODI_OUT_DMAC_15_0};
1503 mask[idx] = rte_cpu_to_be_16(0xffff >>
1507 mask[idx] = RTE_BE16(0xffff);
1514 info[idx] = (struct field_modify_info){4, 4 * idx,
1515 MLX5_MODI_OUT_DMAC_47_16};
1516 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1517 (32 - width)) << off);
1519 if (data->offset < 16)
1520 info[idx++] = (struct field_modify_info){2, 0,
1521 MLX5_MODI_OUT_DMAC_15_0};
1522 info[idx] = (struct field_modify_info){4, off,
1523 MLX5_MODI_OUT_DMAC_47_16};
1526 case RTE_FLOW_FIELD_MAC_SRC:
1527 off = data->offset > 16 ? data->offset - 16 : 0;
1529 if (data->offset < 16) {
1530 info[idx] = (struct field_modify_info){2, 0,
1531 MLX5_MODI_OUT_SMAC_15_0};
1533 mask[idx] = rte_cpu_to_be_16(0xffff >>
1537 mask[idx] = RTE_BE16(0xffff);
1544 info[idx] = (struct field_modify_info){4, 4 * idx,
1545 MLX5_MODI_OUT_SMAC_47_16};
1546 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1547 (32 - width)) << off);
1549 if (data->offset < 16)
1550 info[idx++] = (struct field_modify_info){2, 0,
1551 MLX5_MODI_OUT_SMAC_15_0};
1552 info[idx] = (struct field_modify_info){4, off,
1553 MLX5_MODI_OUT_SMAC_47_16};
1556 case RTE_FLOW_FIELD_VLAN_TYPE:
1557 /* not supported yet */
1559 case RTE_FLOW_FIELD_VLAN_ID:
1560 info[idx] = (struct field_modify_info){2, 0,
1561 MLX5_MODI_OUT_FIRST_VID};
1563 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1565 case RTE_FLOW_FIELD_MAC_TYPE:
1566 info[idx] = (struct field_modify_info){2, 0,
1567 MLX5_MODI_OUT_ETHERTYPE};
1569 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1571 case RTE_FLOW_FIELD_IPV4_DSCP:
1572 info[idx] = (struct field_modify_info){1, 0,
1573 MLX5_MODI_OUT_IP_DSCP};
1575 mask[idx] = 0x3f >> (6 - width);
1577 case RTE_FLOW_FIELD_IPV4_TTL:
1578 info[idx] = (struct field_modify_info){1, 0,
1579 MLX5_MODI_OUT_IPV4_TTL};
1581 mask[idx] = 0xff >> (8 - width);
1583 case RTE_FLOW_FIELD_IPV4_SRC:
1584 info[idx] = (struct field_modify_info){4, 0,
1585 MLX5_MODI_OUT_SIPV4};
1587 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1590 case RTE_FLOW_FIELD_IPV4_DST:
1591 info[idx] = (struct field_modify_info){4, 0,
1592 MLX5_MODI_OUT_DIPV4};
1594 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1597 case RTE_FLOW_FIELD_IPV6_DSCP:
1598 info[idx] = (struct field_modify_info){1, 0,
1599 MLX5_MODI_OUT_IP_DSCP};
1601 mask[idx] = 0x3f >> (6 - width);
1603 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1604 info[idx] = (struct field_modify_info){1, 0,
1605 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1607 mask[idx] = 0xff >> (8 - width);
1609 case RTE_FLOW_FIELD_IPV6_SRC:
1611 if (data->offset < 32) {
1612 info[idx] = (struct field_modify_info){4,
1614 MLX5_MODI_OUT_SIPV6_31_0};
1617 rte_cpu_to_be_32(0xffffffff >>
1621 mask[idx] = RTE_BE32(0xffffffff);
1628 if (data->offset < 64) {
1629 info[idx] = (struct field_modify_info){4,
1631 MLX5_MODI_OUT_SIPV6_63_32};
1634 rte_cpu_to_be_32(0xffffffff >>
1638 mask[idx] = RTE_BE32(0xffffffff);
1645 if (data->offset < 96) {
1646 info[idx] = (struct field_modify_info){4,
1648 MLX5_MODI_OUT_SIPV6_95_64};
1651 rte_cpu_to_be_32(0xffffffff >>
1655 mask[idx] = RTE_BE32(0xffffffff);
1662 info[idx] = (struct field_modify_info){4, 4 * idx,
1663 MLX5_MODI_OUT_SIPV6_127_96};
1664 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1667 if (data->offset < 32)
1668 info[idx++] = (struct field_modify_info){4, 0,
1669 MLX5_MODI_OUT_SIPV6_31_0};
1670 if (data->offset < 64)
1671 info[idx++] = (struct field_modify_info){4, 0,
1672 MLX5_MODI_OUT_SIPV6_63_32};
1673 if (data->offset < 96)
1674 info[idx++] = (struct field_modify_info){4, 0,
1675 MLX5_MODI_OUT_SIPV6_95_64};
1676 if (data->offset < 128)
1677 info[idx++] = (struct field_modify_info){4, 0,
1678 MLX5_MODI_OUT_SIPV6_127_96};
1681 case RTE_FLOW_FIELD_IPV6_DST:
1683 if (data->offset < 32) {
1684 info[idx] = (struct field_modify_info){4,
1686 MLX5_MODI_OUT_DIPV6_31_0};
1689 rte_cpu_to_be_32(0xffffffff >>
1693 mask[idx] = RTE_BE32(0xffffffff);
1700 if (data->offset < 64) {
1701 info[idx] = (struct field_modify_info){4,
1703 MLX5_MODI_OUT_DIPV6_63_32};
1706 rte_cpu_to_be_32(0xffffffff >>
1710 mask[idx] = RTE_BE32(0xffffffff);
1717 if (data->offset < 96) {
1718 info[idx] = (struct field_modify_info){4,
1720 MLX5_MODI_OUT_DIPV6_95_64};
1723 rte_cpu_to_be_32(0xffffffff >>
1727 mask[idx] = RTE_BE32(0xffffffff);
1734 info[idx] = (struct field_modify_info){4, 4 * idx,
1735 MLX5_MODI_OUT_DIPV6_127_96};
1736 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1739 if (data->offset < 32)
1740 info[idx++] = (struct field_modify_info){4, 0,
1741 MLX5_MODI_OUT_DIPV6_31_0};
1742 if (data->offset < 64)
1743 info[idx++] = (struct field_modify_info){4, 0,
1744 MLX5_MODI_OUT_DIPV6_63_32};
1745 if (data->offset < 96)
1746 info[idx++] = (struct field_modify_info){4, 0,
1747 MLX5_MODI_OUT_DIPV6_95_64};
1748 if (data->offset < 128)
1749 info[idx++] = (struct field_modify_info){4, 0,
1750 MLX5_MODI_OUT_DIPV6_127_96};
1753 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1754 info[idx] = (struct field_modify_info){2, 0,
1755 MLX5_MODI_OUT_TCP_SPORT};
1757 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1759 case RTE_FLOW_FIELD_TCP_PORT_DST:
1760 info[idx] = (struct field_modify_info){2, 0,
1761 MLX5_MODI_OUT_TCP_DPORT};
1763 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1765 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1766 info[idx] = (struct field_modify_info){4, 0,
1767 MLX5_MODI_OUT_TCP_SEQ_NUM};
1769 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1772 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1773 info[idx] = (struct field_modify_info){4, 0,
1774 MLX5_MODI_OUT_TCP_ACK_NUM};
1776 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1779 case RTE_FLOW_FIELD_TCP_FLAGS:
1780 info[idx] = (struct field_modify_info){2, 0,
1781 MLX5_MODI_OUT_TCP_FLAGS};
1783 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1785 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1786 info[idx] = (struct field_modify_info){2, 0,
1787 MLX5_MODI_OUT_UDP_SPORT};
1789 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1791 case RTE_FLOW_FIELD_UDP_PORT_DST:
1792 info[idx] = (struct field_modify_info){2, 0,
1793 MLX5_MODI_OUT_UDP_DPORT};
1795 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1797 case RTE_FLOW_FIELD_VXLAN_VNI:
1798 /* not supported yet */
1800 case RTE_FLOW_FIELD_GENEVE_VNI:
1801 /* not supported yet*/
1803 case RTE_FLOW_FIELD_GTP_TEID:
1804 info[idx] = (struct field_modify_info){4, 0,
1805 MLX5_MODI_GTP_TEID};
1807 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1810 case RTE_FLOW_FIELD_TAG:
1812 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1813 data->level, error);
1816 MLX5_ASSERT(reg != REG_NON);
1817 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1818 info[idx] = (struct field_modify_info){4, 0,
1822 rte_cpu_to_be_32(0xffffffff >>
1826 case RTE_FLOW_FIELD_MARK:
1828 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1832 MLX5_ASSERT(reg != REG_NON);
1833 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1834 info[idx] = (struct field_modify_info){4, 0,
1838 rte_cpu_to_be_32(0xffffffff >>
1842 case RTE_FLOW_FIELD_META:
1844 unsigned int xmeta = config->dv_xmeta_en;
1845 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1848 MLX5_ASSERT(reg != REG_NON);
1849 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1850 if (xmeta == MLX5_XMETA_MODE_META16) {
1851 info[idx] = (struct field_modify_info){2, 0,
1854 mask[idx] = rte_cpu_to_be_16(0xffff >>
1856 } else if (xmeta == MLX5_XMETA_MODE_META32) {
1857 info[idx] = (struct field_modify_info){4, 0,
1861 rte_cpu_to_be_32(0xffffffff >>
1868 case RTE_FLOW_FIELD_POINTER:
1869 case RTE_FLOW_FIELD_VALUE:
1870 if (data->field == RTE_FLOW_FIELD_POINTER)
1871 memcpy(&val, (void *)(uintptr_t)data->value,
1875 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1877 if (dst_width == 48) {
1878 /*special case for MAC addresses */
1879 value[idx] = rte_cpu_to_be_16(val);
1882 } else if (dst_width > 16) {
1883 value[idx] = rte_cpu_to_be_32(val);
1885 } else if (dst_width > 8) {
1886 value[idx] = rte_cpu_to_be_16(val);
1889 value[idx] = (uint8_t)val;
1904 * Convert modify_field action to DV specification.
1907 * Pointer to the rte_eth_dev structure.
1908 * @param[in,out] resource
1909 * Pointer to the modify-header resource.
1911 * Pointer to action specification.
1913 * Attributes of flow that includes this item.
1915 * Pointer to the error structure.
1918 * 0 on success, a negative errno value otherwise and rte_errno is set.
1921 flow_dv_convert_action_modify_field
1922 (struct rte_eth_dev *dev,
1923 struct mlx5_flow_dv_modify_hdr_resource *resource,
1924 const struct rte_flow_action *action,
1925 const struct rte_flow_attr *attr,
1926 struct rte_flow_error *error)
1928 struct mlx5_priv *priv = dev->data->dev_private;
1929 struct mlx5_dev_config *config = &priv->config;
1930 const struct rte_flow_action_modify_field *conf =
1931 (const struct rte_flow_action_modify_field *)(action->conf);
1932 struct rte_flow_item item;
1933 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1935 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1937 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1938 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1940 uint32_t dst_width = mlx5_flow_item_field_width(config,
1943 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1944 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1945 type = MLX5_MODIFICATION_TYPE_SET;
1946 /** For SET fill the destination field (field) first. */
1947 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1948 value, conf->width, dst_width, dev, attr, error);
1949 /** Then copy immediate value from source as per mask. */
1950 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1951 value, conf->width, dst_width, dev, attr, error);
1954 type = MLX5_MODIFICATION_TYPE_COPY;
1955 /** For COPY fill the destination field (dcopy) without mask. */
1956 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1957 value, conf->width, dst_width, dev, attr, error);
1958 /** Then construct the source field (field) with mask. */
1959 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1960 value, conf->width, dst_width, dev, attr, error);
1963 return flow_dv_convert_modify_action(&item,
1964 field, dcopy, resource, type, error);
1968 * Validate MARK item.
1971 * Pointer to the rte_eth_dev structure.
1973 * Item specification.
1975 * Attributes of flow that includes this item.
1977 * Pointer to error structure.
1980 * 0 on success, a negative errno value otherwise and rte_errno is set.
1983 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1984 const struct rte_flow_item *item,
1985 const struct rte_flow_attr *attr __rte_unused,
1986 struct rte_flow_error *error)
1988 struct mlx5_priv *priv = dev->data->dev_private;
1989 struct mlx5_dev_config *config = &priv->config;
1990 const struct rte_flow_item_mark *spec = item->spec;
1991 const struct rte_flow_item_mark *mask = item->mask;
1992 const struct rte_flow_item_mark nic_mask = {
1993 .id = priv->sh->dv_mark_mask,
1997 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1998 return rte_flow_error_set(error, ENOTSUP,
1999 RTE_FLOW_ERROR_TYPE_ITEM, item,
2000 "extended metadata feature"
2002 if (!mlx5_flow_ext_mreg_supported(dev))
2003 return rte_flow_error_set(error, ENOTSUP,
2004 RTE_FLOW_ERROR_TYPE_ITEM, item,
2005 "extended metadata register"
2006 " isn't supported");
2008 return rte_flow_error_set(error, ENOTSUP,
2009 RTE_FLOW_ERROR_TYPE_ITEM, item,
2010 "extended metadata register"
2011 " isn't available");
2012 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2016 return rte_flow_error_set(error, EINVAL,
2017 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2019 "data cannot be empty");
2020 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
2021 return rte_flow_error_set(error, EINVAL,
2022 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2024 "mark id exceeds the limit");
2028 return rte_flow_error_set(error, EINVAL,
2029 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2030 "mask cannot be zero");
2032 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2033 (const uint8_t *)&nic_mask,
2034 sizeof(struct rte_flow_item_mark),
2035 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2042 * Validate META item.
2045 * Pointer to the rte_eth_dev structure.
2047 * Item specification.
2049 * Attributes of flow that includes this item.
2051 * Pointer to error structure.
2054 * 0 on success, a negative errno value otherwise and rte_errno is set.
2057 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2058 const struct rte_flow_item *item,
2059 const struct rte_flow_attr *attr,
2060 struct rte_flow_error *error)
2062 struct mlx5_priv *priv = dev->data->dev_private;
2063 struct mlx5_dev_config *config = &priv->config;
2064 const struct rte_flow_item_meta *spec = item->spec;
2065 const struct rte_flow_item_meta *mask = item->mask;
2066 struct rte_flow_item_meta nic_mask = {
2073 return rte_flow_error_set(error, EINVAL,
2074 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2076 "data cannot be empty");
2077 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2078 if (!mlx5_flow_ext_mreg_supported(dev))
2079 return rte_flow_error_set(error, ENOTSUP,
2080 RTE_FLOW_ERROR_TYPE_ITEM, item,
2081 "extended metadata register"
2082 " isn't supported");
2083 reg = flow_dv_get_metadata_reg(dev, attr, error);
2087 return rte_flow_error_set(error, ENOTSUP,
2088 RTE_FLOW_ERROR_TYPE_ITEM, item,
2089 "unavalable extended metadata register");
2091 return rte_flow_error_set(error, ENOTSUP,
2092 RTE_FLOW_ERROR_TYPE_ITEM, item,
2096 nic_mask.data = priv->sh->dv_meta_mask;
2099 return rte_flow_error_set(error, ENOTSUP,
2100 RTE_FLOW_ERROR_TYPE_ITEM, item,
2101 "extended metadata feature "
2102 "should be enabled when "
2103 "meta item is requested "
2104 "with e-switch mode ");
2106 return rte_flow_error_set(error, ENOTSUP,
2107 RTE_FLOW_ERROR_TYPE_ITEM, item,
2108 "match on metadata for ingress "
2109 "is not supported in legacy "
2113 mask = &rte_flow_item_meta_mask;
2115 return rte_flow_error_set(error, EINVAL,
2116 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2117 "mask cannot be zero");
2119 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2120 (const uint8_t *)&nic_mask,
2121 sizeof(struct rte_flow_item_meta),
2122 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2127 * Validate TAG item.
2130 * Pointer to the rte_eth_dev structure.
2132 * Item specification.
2134 * Attributes of flow that includes this item.
2136 * Pointer to error structure.
2139 * 0 on success, a negative errno value otherwise and rte_errno is set.
2142 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2143 const struct rte_flow_item *item,
2144 const struct rte_flow_attr *attr __rte_unused,
2145 struct rte_flow_error *error)
2147 const struct rte_flow_item_tag *spec = item->spec;
2148 const struct rte_flow_item_tag *mask = item->mask;
2149 const struct rte_flow_item_tag nic_mask = {
2150 .data = RTE_BE32(UINT32_MAX),
2155 if (!mlx5_flow_ext_mreg_supported(dev))
2156 return rte_flow_error_set(error, ENOTSUP,
2157 RTE_FLOW_ERROR_TYPE_ITEM, item,
2158 "extensive metadata register"
2159 " isn't supported");
2161 return rte_flow_error_set(error, EINVAL,
2162 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2164 "data cannot be empty");
2166 mask = &rte_flow_item_tag_mask;
2168 return rte_flow_error_set(error, EINVAL,
2169 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2170 "mask cannot be zero");
2172 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2173 (const uint8_t *)&nic_mask,
2174 sizeof(struct rte_flow_item_tag),
2175 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2178 if (mask->index != 0xff)
2179 return rte_flow_error_set(error, EINVAL,
2180 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2181 "partial mask for tag index"
2182 " is not supported");
2183 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2186 MLX5_ASSERT(ret != REG_NON);
2191 * Validate vport item.
2194 * Pointer to the rte_eth_dev structure.
2196 * Item specification.
2198 * Attributes of flow that includes this item.
2199 * @param[in] item_flags
2200 * Bit-fields that holds the items detected until now.
2202 * Pointer to error structure.
2205 * 0 on success, a negative errno value otherwise and rte_errno is set.
2208 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2209 const struct rte_flow_item *item,
2210 const struct rte_flow_attr *attr,
2211 uint64_t item_flags,
2212 struct rte_flow_error *error)
2214 const struct rte_flow_item_port_id *spec = item->spec;
2215 const struct rte_flow_item_port_id *mask = item->mask;
2216 const struct rte_flow_item_port_id switch_mask = {
2219 struct mlx5_priv *esw_priv;
2220 struct mlx5_priv *dev_priv;
2223 if (!attr->transfer)
2224 return rte_flow_error_set(error, EINVAL,
2225 RTE_FLOW_ERROR_TYPE_ITEM,
2227 "match on port id is valid only"
2228 " when transfer flag is enabled");
2229 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2230 return rte_flow_error_set(error, ENOTSUP,
2231 RTE_FLOW_ERROR_TYPE_ITEM, item,
2232 "multiple source ports are not"
2235 mask = &switch_mask;
2236 if (mask->id != 0xffffffff)
2237 return rte_flow_error_set(error, ENOTSUP,
2238 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2240 "no support for partial mask on"
2242 ret = mlx5_flow_item_acceptable
2243 (item, (const uint8_t *)mask,
2244 (const uint8_t *)&rte_flow_item_port_id_mask,
2245 sizeof(struct rte_flow_item_port_id),
2246 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2251 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2253 return rte_flow_error_set(error, rte_errno,
2254 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2255 "failed to obtain E-Switch info for"
2257 dev_priv = mlx5_dev_to_eswitch_info(dev);
2259 return rte_flow_error_set(error, rte_errno,
2260 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2262 "failed to obtain E-Switch info");
2263 if (esw_priv->domain_id != dev_priv->domain_id)
2264 return rte_flow_error_set(error, EINVAL,
2265 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2266 "cannot match on a port from a"
2267 " different E-Switch");
2272 * Validate VLAN item.
2275 * Item specification.
2276 * @param[in] item_flags
2277 * Bit-fields that holds the items detected until now.
2279 * Ethernet device flow is being created on.
2281 * Pointer to error structure.
2284 * 0 on success, a negative errno value otherwise and rte_errno is set.
2287 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2288 uint64_t item_flags,
2289 struct rte_eth_dev *dev,
2290 struct rte_flow_error *error)
2292 const struct rte_flow_item_vlan *mask = item->mask;
2293 const struct rte_flow_item_vlan nic_mask = {
2294 .tci = RTE_BE16(UINT16_MAX),
2295 .inner_type = RTE_BE16(UINT16_MAX),
2298 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2300 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2301 MLX5_FLOW_LAYER_INNER_L4) :
2302 (MLX5_FLOW_LAYER_OUTER_L3 |
2303 MLX5_FLOW_LAYER_OUTER_L4);
2304 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2305 MLX5_FLOW_LAYER_OUTER_VLAN;
2307 if (item_flags & vlanm)
2308 return rte_flow_error_set(error, EINVAL,
2309 RTE_FLOW_ERROR_TYPE_ITEM, item,
2310 "multiple VLAN layers not supported");
2311 else if ((item_flags & l34m) != 0)
2312 return rte_flow_error_set(error, EINVAL,
2313 RTE_FLOW_ERROR_TYPE_ITEM, item,
2314 "VLAN cannot follow L3/L4 layer");
2316 mask = &rte_flow_item_vlan_mask;
2317 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2318 (const uint8_t *)&nic_mask,
2319 sizeof(struct rte_flow_item_vlan),
2320 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2323 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2324 struct mlx5_priv *priv = dev->data->dev_private;
2326 if (priv->vmwa_context) {
2328 * Non-NULL context means we have a virtual machine
2329 * and SR-IOV enabled, we have to create VLAN interface
2330 * to make hypervisor to setup E-Switch vport
2331 * context correctly. We avoid creating the multiple
2332 * VLAN interfaces, so we cannot support VLAN tag mask.
2334 return rte_flow_error_set(error, EINVAL,
2335 RTE_FLOW_ERROR_TYPE_ITEM,
2337 "VLAN tag mask is not"
2338 " supported in virtual"
2346 * GTP flags are contained in 1 byte of the format:
2347 * -------------------------------------------
2348 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2349 * |-----------------------------------------|
2350 * | value | Version | PT | Res | E | S | PN |
2351 * -------------------------------------------
2353 * Matching is supported only for GTP flags E, S, PN.
2355 #define MLX5_GTP_FLAGS_MASK 0x07
2358 * Validate GTP item.
2361 * Pointer to the rte_eth_dev structure.
2363 * Item specification.
2364 * @param[in] item_flags
2365 * Bit-fields that holds the items detected until now.
2367 * Pointer to error structure.
2370 * 0 on success, a negative errno value otherwise and rte_errno is set.
2373 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2374 const struct rte_flow_item *item,
2375 uint64_t item_flags,
2376 struct rte_flow_error *error)
2378 struct mlx5_priv *priv = dev->data->dev_private;
2379 const struct rte_flow_item_gtp *spec = item->spec;
2380 const struct rte_flow_item_gtp *mask = item->mask;
2381 const struct rte_flow_item_gtp nic_mask = {
2382 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2384 .teid = RTE_BE32(0xffffffff),
2387 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2388 return rte_flow_error_set(error, ENOTSUP,
2389 RTE_FLOW_ERROR_TYPE_ITEM, item,
2390 "GTP support is not enabled");
2391 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2392 return rte_flow_error_set(error, ENOTSUP,
2393 RTE_FLOW_ERROR_TYPE_ITEM, item,
2394 "multiple tunnel layers not"
2396 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2397 return rte_flow_error_set(error, EINVAL,
2398 RTE_FLOW_ERROR_TYPE_ITEM, item,
2399 "no outer UDP layer found");
2401 mask = &rte_flow_item_gtp_mask;
2402 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2403 return rte_flow_error_set(error, ENOTSUP,
2404 RTE_FLOW_ERROR_TYPE_ITEM, item,
2405 "Match is supported for GTP"
2407 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2408 (const uint8_t *)&nic_mask,
2409 sizeof(struct rte_flow_item_gtp),
2410 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2414 * Validate GTP PSC item.
2417 * Item specification.
2418 * @param[in] last_item
2419 * Previous validated item in the pattern items.
2420 * @param[in] gtp_item
2421 * Previous GTP item specification.
2423 * Pointer to flow attributes.
2425 * Pointer to error structure.
2428 * 0 on success, a negative errno value otherwise and rte_errno is set.
2431 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2433 const struct rte_flow_item *gtp_item,
2434 const struct rte_flow_attr *attr,
2435 struct rte_flow_error *error)
2437 const struct rte_flow_item_gtp *gtp_spec;
2438 const struct rte_flow_item_gtp *gtp_mask;
2439 const struct rte_flow_item_gtp_psc *spec;
2440 const struct rte_flow_item_gtp_psc *mask;
2441 const struct rte_flow_item_gtp_psc nic_mask = {
2446 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2447 return rte_flow_error_set
2448 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2449 "GTP PSC item must be preceded with GTP item");
2450 gtp_spec = gtp_item->spec;
2451 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2452 /* GTP spec and E flag is requested to match zero. */
2454 (gtp_mask->v_pt_rsv_flags &
2455 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2456 return rte_flow_error_set
2457 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2458 "GTP E flag must be 1 to match GTP PSC");
2459 /* Check the flow is not created in group zero. */
2460 if (!attr->transfer && !attr->group)
2461 return rte_flow_error_set
2462 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2463 "GTP PSC is not supported for group 0");
2464 /* GTP spec is here and E flag is requested to match zero. */
2468 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2469 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2470 return rte_flow_error_set
2471 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2472 "PDU type should be smaller than 16");
2473 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2474 (const uint8_t *)&nic_mask,
2475 sizeof(struct rte_flow_item_gtp_psc),
2476 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2480 * Validate IPV4 item.
2481 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2482 * add specific validation of fragment_offset field,
2485 * Item specification.
2486 * @param[in] item_flags
2487 * Bit-fields that holds the items detected until now.
2489 * Pointer to error structure.
2492 * 0 on success, a negative errno value otherwise and rte_errno is set.
2495 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2496 const struct rte_flow_item *item,
2497 uint64_t item_flags, uint64_t last_item,
2498 uint16_t ether_type, struct rte_flow_error *error)
2501 struct mlx5_priv *priv = dev->data->dev_private;
2502 const struct rte_flow_item_ipv4 *spec = item->spec;
2503 const struct rte_flow_item_ipv4 *last = item->last;
2504 const struct rte_flow_item_ipv4 *mask = item->mask;
2505 rte_be16_t fragment_offset_spec = 0;
2506 rte_be16_t fragment_offset_last = 0;
2507 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2509 .src_addr = RTE_BE32(0xffffffff),
2510 .dst_addr = RTE_BE32(0xffffffff),
2511 .type_of_service = 0xff,
2512 .fragment_offset = RTE_BE16(0xffff),
2513 .next_proto_id = 0xff,
2514 .time_to_live = 0xff,
2518 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2519 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2520 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2521 priv->config.hca_attr.inner_ipv4_ihl;
2523 return rte_flow_error_set(error, ENOTSUP,
2524 RTE_FLOW_ERROR_TYPE_ITEM,
2526 "IPV4 ihl offload not supported");
2527 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2529 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2530 ether_type, &nic_ipv4_mask,
2531 MLX5_ITEM_RANGE_ACCEPTED, error);
2535 fragment_offset_spec = spec->hdr.fragment_offset &
2536 mask->hdr.fragment_offset;
2537 if (!fragment_offset_spec)
2540 * spec and mask are valid, enforce using full mask to make sure the
2541 * complete value is used correctly.
2543 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2544 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2545 return rte_flow_error_set(error, EINVAL,
2546 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2547 item, "must use full mask for"
2548 " fragment_offset");
2550 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2551 * indicating this is 1st fragment of fragmented packet.
2552 * This is not yet supported in MLX5, return appropriate error message.
2554 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2555 return rte_flow_error_set(error, ENOTSUP,
2556 RTE_FLOW_ERROR_TYPE_ITEM, item,
2557 "match on first fragment not "
2559 if (fragment_offset_spec && !last)
2560 return rte_flow_error_set(error, ENOTSUP,
2561 RTE_FLOW_ERROR_TYPE_ITEM, item,
2562 "specified value not supported");
2563 /* spec and last are valid, validate the specified range. */
2564 fragment_offset_last = last->hdr.fragment_offset &
2565 mask->hdr.fragment_offset;
2567 * Match on fragment_offset spec 0x2001 and last 0x3fff
2568 * means MF is 1 and frag-offset is > 0.
2569 * This packet is fragment 2nd and onward, excluding last.
2570 * This is not yet supported in MLX5, return appropriate
2573 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2574 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2575 return rte_flow_error_set(error, ENOTSUP,
2576 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2577 last, "match on following "
2578 "fragments not supported");
2580 * Match on fragment_offset spec 0x0001 and last 0x1fff
2581 * means MF is 0 and frag-offset is > 0.
2582 * This packet is last fragment of fragmented packet.
2583 * This is not yet supported in MLX5, return appropriate
2586 if (fragment_offset_spec == RTE_BE16(1) &&
2587 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2588 return rte_flow_error_set(error, ENOTSUP,
2589 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2590 last, "match on last "
2591 "fragment not supported");
2593 * Match on fragment_offset spec 0x0001 and last 0x3fff
2594 * means MF and/or frag-offset is not 0.
2595 * This is a fragmented packet.
2596 * Other range values are invalid and rejected.
2598 if (!(fragment_offset_spec == RTE_BE16(1) &&
2599 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2600 return rte_flow_error_set(error, ENOTSUP,
2601 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2602 "specified range not supported");
2607 * Validate IPV6 fragment extension item.
2610 * Item specification.
2611 * @param[in] item_flags
2612 * Bit-fields that holds the items detected until now.
2614 * Pointer to error structure.
2617 * 0 on success, a negative errno value otherwise and rte_errno is set.
2620 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2621 uint64_t item_flags,
2622 struct rte_flow_error *error)
2624 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2625 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2626 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2627 rte_be16_t frag_data_spec = 0;
2628 rte_be16_t frag_data_last = 0;
2629 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2630 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2631 MLX5_FLOW_LAYER_OUTER_L4;
2633 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2635 .next_header = 0xff,
2636 .frag_data = RTE_BE16(0xffff),
2640 if (item_flags & l4m)
2641 return rte_flow_error_set(error, EINVAL,
2642 RTE_FLOW_ERROR_TYPE_ITEM, item,
2643 "ipv6 fragment extension item cannot "
2645 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2646 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2647 return rte_flow_error_set(error, EINVAL,
2648 RTE_FLOW_ERROR_TYPE_ITEM, item,
2649 "ipv6 fragment extension item must "
2650 "follow ipv6 item");
2652 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2653 if (!frag_data_spec)
2656 * spec and mask are valid, enforce using full mask to make sure the
2657 * complete value is used correctly.
2659 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2660 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2661 return rte_flow_error_set(error, EINVAL,
2662 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2663 item, "must use full mask for"
2666 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2667 * This is 1st fragment of fragmented packet.
2669 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2670 return rte_flow_error_set(error, ENOTSUP,
2671 RTE_FLOW_ERROR_TYPE_ITEM, item,
2672 "match on first fragment not "
2674 if (frag_data_spec && !last)
2675 return rte_flow_error_set(error, EINVAL,
2676 RTE_FLOW_ERROR_TYPE_ITEM, item,
2677 "specified value not supported");
2678 ret = mlx5_flow_item_acceptable
2679 (item, (const uint8_t *)mask,
2680 (const uint8_t *)&nic_mask,
2681 sizeof(struct rte_flow_item_ipv6_frag_ext),
2682 MLX5_ITEM_RANGE_ACCEPTED, error);
2685 /* spec and last are valid, validate the specified range. */
2686 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2688 * Match on frag_data spec 0x0009 and last 0xfff9
2689 * means M is 1 and frag-offset is > 0.
2690 * This packet is fragment 2nd and onward, excluding last.
2691 * This is not yet supported in MLX5, return appropriate
2694 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2695 RTE_IPV6_EHDR_MF_MASK) &&
2696 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2697 return rte_flow_error_set(error, ENOTSUP,
2698 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2699 last, "match on following "
2700 "fragments not supported");
2702 * Match on frag_data spec 0x0008 and last 0xfff8
2703 * means M is 0 and frag-offset is > 0.
2704 * This packet is last fragment of fragmented packet.
2705 * This is not yet supported in MLX5, return appropriate
2708 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2709 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2710 return rte_flow_error_set(error, ENOTSUP,
2711 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2712 last, "match on last "
2713 "fragment not supported");
2714 /* Other range values are invalid and rejected. */
2715 return rte_flow_error_set(error, EINVAL,
2716 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2717 "specified range not supported");
2721 * Validate ASO CT item.
2724 * Pointer to the rte_eth_dev structure.
2726 * Item specification.
2727 * @param[in] item_flags
2728 * Pointer to bit-fields that holds the items detected until now.
2730 * Pointer to error structure.
2733 * 0 on success, a negative errno value otherwise and rte_errno is set.
2736 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2737 const struct rte_flow_item *item,
2738 uint64_t *item_flags,
2739 struct rte_flow_error *error)
2741 const struct rte_flow_item_conntrack *spec = item->spec;
2742 const struct rte_flow_item_conntrack *mask = item->mask;
2746 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2747 return rte_flow_error_set(error, EINVAL,
2748 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2749 "Only one CT is supported");
2751 mask = &rte_flow_item_conntrack_mask;
2752 flags = spec->flags & mask->flags;
2753 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2754 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2755 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2756 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2757 return rte_flow_error_set(error, EINVAL,
2758 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2759 "Conflict status bits");
2760 /* State change also needs to be considered. */
2761 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2766 * Validate the pop VLAN action.
2769 * Pointer to the rte_eth_dev structure.
2770 * @param[in] action_flags
2771 * Holds the actions detected until now.
2773 * Pointer to the pop vlan action.
2774 * @param[in] item_flags
2775 * The items found in this flow rule.
2777 * Pointer to flow attributes.
2779 * Pointer to error structure.
2782 * 0 on success, a negative errno value otherwise and rte_errno is set.
2785 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2786 uint64_t action_flags,
2787 const struct rte_flow_action *action,
2788 uint64_t item_flags,
2789 const struct rte_flow_attr *attr,
2790 struct rte_flow_error *error)
2792 const struct mlx5_priv *priv = dev->data->dev_private;
2796 if (!priv->sh->pop_vlan_action)
2797 return rte_flow_error_set(error, ENOTSUP,
2798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2800 "pop vlan action is not supported");
2802 return rte_flow_error_set(error, ENOTSUP,
2803 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2805 "pop vlan action not supported for "
2807 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2808 return rte_flow_error_set(error, ENOTSUP,
2809 RTE_FLOW_ERROR_TYPE_ACTION, action,
2810 "no support for multiple VLAN "
2812 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2813 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2814 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2815 return rte_flow_error_set(error, ENOTSUP,
2816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2818 "cannot pop vlan after decap without "
2819 "match on inner vlan in the flow");
2820 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2821 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2822 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2823 return rte_flow_error_set(error, ENOTSUP,
2824 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2826 "cannot pop vlan without a "
2827 "match on (outer) vlan in the flow");
2828 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2829 return rte_flow_error_set(error, EINVAL,
2830 RTE_FLOW_ERROR_TYPE_ACTION, action,
2831 "wrong action order, port_id should "
2832 "be after pop VLAN action");
2833 if (!attr->transfer && priv->representor)
2834 return rte_flow_error_set(error, ENOTSUP,
2835 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2836 "pop vlan action for VF representor "
2837 "not supported on NIC table");
2842 * Get VLAN default info from vlan match info.
2845 * the list of item specifications.
2847 * pointer VLAN info to fill to.
2850 * 0 on success, a negative errno value otherwise and rte_errno is set.
2853 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2854 struct rte_vlan_hdr *vlan)
2856 const struct rte_flow_item_vlan nic_mask = {
2857 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2858 MLX5DV_FLOW_VLAN_VID_MASK),
2859 .inner_type = RTE_BE16(0xffff),
2864 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2865 int type = items->type;
2867 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2868 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2871 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2872 const struct rte_flow_item_vlan *vlan_m = items->mask;
2873 const struct rte_flow_item_vlan *vlan_v = items->spec;
2875 /* If VLAN item in pattern doesn't contain data, return here. */
2880 /* Only full match values are accepted */
2881 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2882 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2883 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2885 rte_be_to_cpu_16(vlan_v->tci &
2886 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2888 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2889 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2890 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2892 rte_be_to_cpu_16(vlan_v->tci &
2893 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2895 if (vlan_m->inner_type == nic_mask.inner_type)
2896 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2897 vlan_m->inner_type);
2902 * Validate the push VLAN action.
2905 * Pointer to the rte_eth_dev structure.
2906 * @param[in] action_flags
2907 * Holds the actions detected until now.
2908 * @param[in] item_flags
2909 * The items found in this flow rule.
2911 * Pointer to the action structure.
2913 * Pointer to flow attributes
2915 * Pointer to error structure.
2918 * 0 on success, a negative errno value otherwise and rte_errno is set.
2921 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2922 uint64_t action_flags,
2923 const struct rte_flow_item_vlan *vlan_m,
2924 const struct rte_flow_action *action,
2925 const struct rte_flow_attr *attr,
2926 struct rte_flow_error *error)
2928 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2929 const struct mlx5_priv *priv = dev->data->dev_private;
2931 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2932 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2933 return rte_flow_error_set(error, EINVAL,
2934 RTE_FLOW_ERROR_TYPE_ACTION, action,
2935 "invalid vlan ethertype");
2936 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2937 return rte_flow_error_set(error, EINVAL,
2938 RTE_FLOW_ERROR_TYPE_ACTION, action,
2939 "wrong action order, port_id should "
2940 "be after push VLAN");
2941 if (!attr->transfer && priv->representor)
2942 return rte_flow_error_set(error, ENOTSUP,
2943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2944 "push vlan action for VF representor "
2945 "not supported on NIC table");
2947 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2948 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2949 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2950 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2951 !(mlx5_flow_find_action
2952 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2953 return rte_flow_error_set(error, EINVAL,
2954 RTE_FLOW_ERROR_TYPE_ACTION, action,
2955 "not full match mask on VLAN PCP and "
2956 "there is no of_set_vlan_pcp action, "
2957 "push VLAN action cannot figure out "
2960 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2961 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2962 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2963 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2964 !(mlx5_flow_find_action
2965 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION, action,
2968 "not full match mask on VLAN VID and "
2969 "there is no of_set_vlan_vid action, "
2970 "push VLAN action cannot figure out "
2977 * Validate the set VLAN PCP.
2979 * @param[in] action_flags
2980 * Holds the actions detected until now.
2981 * @param[in] actions
2982 * Pointer to the list of actions remaining in the flow rule.
2984 * Pointer to error structure.
2987 * 0 on success, a negative errno value otherwise and rte_errno is set.
2990 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2991 const struct rte_flow_action actions[],
2992 struct rte_flow_error *error)
2994 const struct rte_flow_action *action = actions;
2995 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2997 if (conf->vlan_pcp > 7)
2998 return rte_flow_error_set(error, EINVAL,
2999 RTE_FLOW_ERROR_TYPE_ACTION, action,
3000 "VLAN PCP value is too big");
3001 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
3002 return rte_flow_error_set(error, ENOTSUP,
3003 RTE_FLOW_ERROR_TYPE_ACTION, action,
3004 "set VLAN PCP action must follow "
3005 "the push VLAN action");
3006 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
3007 return rte_flow_error_set(error, ENOTSUP,
3008 RTE_FLOW_ERROR_TYPE_ACTION, action,
3009 "Multiple VLAN PCP modification are "
3011 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3012 return rte_flow_error_set(error, EINVAL,
3013 RTE_FLOW_ERROR_TYPE_ACTION, action,
3014 "wrong action order, port_id should "
3015 "be after set VLAN PCP");
3020 * Validate the set VLAN VID.
3022 * @param[in] item_flags
3023 * Holds the items detected in this rule.
3024 * @param[in] action_flags
3025 * Holds the actions detected until now.
3026 * @param[in] actions
3027 * Pointer to the list of actions remaining in the flow rule.
3029 * Pointer to error structure.
3032 * 0 on success, a negative errno value otherwise and rte_errno is set.
3035 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3036 uint64_t action_flags,
3037 const struct rte_flow_action actions[],
3038 struct rte_flow_error *error)
3040 const struct rte_flow_action *action = actions;
3041 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3043 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3044 return rte_flow_error_set(error, EINVAL,
3045 RTE_FLOW_ERROR_TYPE_ACTION, action,
3046 "VLAN VID value is too big");
3047 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3048 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3049 return rte_flow_error_set(error, ENOTSUP,
3050 RTE_FLOW_ERROR_TYPE_ACTION, action,
3051 "set VLAN VID action must follow push"
3052 " VLAN action or match on VLAN item");
3053 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3054 return rte_flow_error_set(error, ENOTSUP,
3055 RTE_FLOW_ERROR_TYPE_ACTION, action,
3056 "Multiple VLAN VID modifications are "
3058 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3059 return rte_flow_error_set(error, EINVAL,
3060 RTE_FLOW_ERROR_TYPE_ACTION, action,
3061 "wrong action order, port_id should "
3062 "be after set VLAN VID");
3067 * Validate the FLAG action.
3070 * Pointer to the rte_eth_dev structure.
3071 * @param[in] action_flags
3072 * Holds the actions detected until now.
3074 * Pointer to flow attributes
3076 * Pointer to error structure.
3079 * 0 on success, a negative errno value otherwise and rte_errno is set.
3082 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3083 uint64_t action_flags,
3084 const struct rte_flow_attr *attr,
3085 struct rte_flow_error *error)
3087 struct mlx5_priv *priv = dev->data->dev_private;
3088 struct mlx5_dev_config *config = &priv->config;
3091 /* Fall back if no extended metadata register support. */
3092 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3093 return mlx5_flow_validate_action_flag(action_flags, attr,
3095 /* Extensive metadata mode requires registers. */
3096 if (!mlx5_flow_ext_mreg_supported(dev))
3097 return rte_flow_error_set(error, ENOTSUP,
3098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3099 "no metadata registers "
3100 "to support flag action");
3101 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3102 return rte_flow_error_set(error, ENOTSUP,
3103 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3104 "extended metadata register"
3105 " isn't available");
3106 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3109 MLX5_ASSERT(ret > 0);
3110 if (action_flags & MLX5_FLOW_ACTION_MARK)
3111 return rte_flow_error_set(error, EINVAL,
3112 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3113 "can't mark and flag in same flow");
3114 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3115 return rte_flow_error_set(error, EINVAL,
3116 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3118 " actions in same flow");
3123 * Validate MARK action.
3126 * Pointer to the rte_eth_dev structure.
3128 * Pointer to action.
3129 * @param[in] action_flags
3130 * Holds the actions detected until now.
3132 * Pointer to flow attributes
3134 * Pointer to error structure.
3137 * 0 on success, a negative errno value otherwise and rte_errno is set.
3140 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3141 const struct rte_flow_action *action,
3142 uint64_t action_flags,
3143 const struct rte_flow_attr *attr,
3144 struct rte_flow_error *error)
3146 struct mlx5_priv *priv = dev->data->dev_private;
3147 struct mlx5_dev_config *config = &priv->config;
3148 const struct rte_flow_action_mark *mark = action->conf;
3151 if (is_tunnel_offload_active(dev))
3152 return rte_flow_error_set(error, ENOTSUP,
3153 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3155 "if tunnel offload active");
3156 /* Fall back if no extended metadata register support. */
3157 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3158 return mlx5_flow_validate_action_mark(action, action_flags,
3160 /* Extensive metadata mode requires registers. */
3161 if (!mlx5_flow_ext_mreg_supported(dev))
3162 return rte_flow_error_set(error, ENOTSUP,
3163 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3164 "no metadata registers "
3165 "to support mark action");
3166 if (!priv->sh->dv_mark_mask)
3167 return rte_flow_error_set(error, ENOTSUP,
3168 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3169 "extended metadata register"
3170 " isn't available");
3171 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3174 MLX5_ASSERT(ret > 0);
3176 return rte_flow_error_set(error, EINVAL,
3177 RTE_FLOW_ERROR_TYPE_ACTION, action,
3178 "configuration cannot be null");
3179 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3180 return rte_flow_error_set(error, EINVAL,
3181 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3183 "mark id exceeds the limit");
3184 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3185 return rte_flow_error_set(error, EINVAL,
3186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3187 "can't flag and mark in same flow");
3188 if (action_flags & MLX5_FLOW_ACTION_MARK)
3189 return rte_flow_error_set(error, EINVAL,
3190 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3191 "can't have 2 mark actions in same"
3197 * Validate SET_META action.
3200 * Pointer to the rte_eth_dev structure.
3202 * Pointer to the action structure.
3203 * @param[in] action_flags
3204 * Holds the actions detected until now.
3206 * Pointer to flow attributes
3208 * Pointer to error structure.
3211 * 0 on success, a negative errno value otherwise and rte_errno is set.
3214 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3215 const struct rte_flow_action *action,
3216 uint64_t action_flags __rte_unused,
3217 const struct rte_flow_attr *attr,
3218 struct rte_flow_error *error)
3220 const struct rte_flow_action_set_meta *conf;
3221 uint32_t nic_mask = UINT32_MAX;
3224 if (!mlx5_flow_ext_mreg_supported(dev))
3225 return rte_flow_error_set(error, ENOTSUP,
3226 RTE_FLOW_ERROR_TYPE_ACTION, action,
3227 "extended metadata register"
3228 " isn't supported");
3229 reg = flow_dv_get_metadata_reg(dev, attr, error);
3233 return rte_flow_error_set(error, ENOTSUP,
3234 RTE_FLOW_ERROR_TYPE_ACTION, action,
3235 "unavalable extended metadata register");
3236 if (reg != REG_A && reg != REG_B) {
3237 struct mlx5_priv *priv = dev->data->dev_private;
3239 nic_mask = priv->sh->dv_meta_mask;
3241 if (!(action->conf))
3242 return rte_flow_error_set(error, EINVAL,
3243 RTE_FLOW_ERROR_TYPE_ACTION, action,
3244 "configuration cannot be null");
3245 conf = (const struct rte_flow_action_set_meta *)action->conf;
3247 return rte_flow_error_set(error, EINVAL,
3248 RTE_FLOW_ERROR_TYPE_ACTION, action,
3249 "zero mask doesn't have any effect");
3250 if (conf->mask & ~nic_mask)
3251 return rte_flow_error_set(error, EINVAL,
3252 RTE_FLOW_ERROR_TYPE_ACTION, action,
3253 "meta data must be within reg C0");
3258 * Validate SET_TAG action.
3261 * Pointer to the rte_eth_dev structure.
3263 * Pointer to the action structure.
3264 * @param[in] action_flags
3265 * Holds the actions detected until now.
3267 * Pointer to flow attributes
3269 * Pointer to error structure.
3272 * 0 on success, a negative errno value otherwise and rte_errno is set.
3275 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3276 const struct rte_flow_action *action,
3277 uint64_t action_flags,
3278 const struct rte_flow_attr *attr,
3279 struct rte_flow_error *error)
3281 const struct rte_flow_action_set_tag *conf;
3282 const uint64_t terminal_action_flags =
3283 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3284 MLX5_FLOW_ACTION_RSS;
3287 if (!mlx5_flow_ext_mreg_supported(dev))
3288 return rte_flow_error_set(error, ENOTSUP,
3289 RTE_FLOW_ERROR_TYPE_ACTION, action,
3290 "extensive metadata register"
3291 " isn't supported");
3292 if (!(action->conf))
3293 return rte_flow_error_set(error, EINVAL,
3294 RTE_FLOW_ERROR_TYPE_ACTION, action,
3295 "configuration cannot be null");
3296 conf = (const struct rte_flow_action_set_tag *)action->conf;
3298 return rte_flow_error_set(error, EINVAL,
3299 RTE_FLOW_ERROR_TYPE_ACTION, action,
3300 "zero mask doesn't have any effect");
3301 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3304 if (!attr->transfer && attr->ingress &&
3305 (action_flags & terminal_action_flags))
3306 return rte_flow_error_set(error, EINVAL,
3307 RTE_FLOW_ERROR_TYPE_ACTION, action,
3308 "set_tag has no effect"
3309 " with terminal actions");
3314 * Check if action counter is shared by either old or new mechanism.
3317 * Pointer to the action structure.
3320 * True when counter is shared, false otherwise.
3323 is_shared_action_count(const struct rte_flow_action *action)
3325 const struct rte_flow_action_count *count =
3326 (const struct rte_flow_action_count *)action->conf;
3328 if ((int)action->type == MLX5_RTE_FLOW_ACTION_TYPE_COUNT)
3330 return !!(count && count->shared);
3334 * Validate count action.
3337 * Pointer to rte_eth_dev structure.
3339 * Indicator if action is shared.
3340 * @param[in] action_flags
3341 * Holds the actions detected until now.
3343 * Pointer to error structure.
3346 * 0 on success, a negative errno value otherwise and rte_errno is set.
3349 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3350 uint64_t action_flags,
3351 struct rte_flow_error *error)
3353 struct mlx5_priv *priv = dev->data->dev_private;
3355 if (!priv->config.devx)
3357 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3358 return rte_flow_error_set(error, EINVAL,
3359 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3360 "duplicate count actions set");
3361 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3362 !priv->sh->flow_hit_aso_en)
3363 return rte_flow_error_set(error, EINVAL,
3364 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3365 "old age and shared count combination is not supported");
3366 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3370 return rte_flow_error_set
3372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3374 "count action not supported");
3378 * Validate the L2 encap action.
3381 * Pointer to the rte_eth_dev structure.
3382 * @param[in] action_flags
3383 * Holds the actions detected until now.
3385 * Pointer to the action structure.
3387 * Pointer to flow attributes.
3389 * Pointer to error structure.
3392 * 0 on success, a negative errno value otherwise and rte_errno is set.
3395 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3396 uint64_t action_flags,
3397 const struct rte_flow_action *action,
3398 const struct rte_flow_attr *attr,
3399 struct rte_flow_error *error)
3401 const struct mlx5_priv *priv = dev->data->dev_private;
3403 if (!(action->conf))
3404 return rte_flow_error_set(error, EINVAL,
3405 RTE_FLOW_ERROR_TYPE_ACTION, action,
3406 "configuration cannot be null");
3407 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3408 return rte_flow_error_set(error, EINVAL,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3410 "can only have a single encap action "
3412 if (!attr->transfer && priv->representor)
3413 return rte_flow_error_set(error, ENOTSUP,
3414 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3415 "encap action for VF representor "
3416 "not supported on NIC table");
3421 * Validate a decap action.
3424 * Pointer to the rte_eth_dev structure.
3425 * @param[in] action_flags
3426 * Holds the actions detected until now.
3428 * Pointer to the action structure.
3429 * @param[in] item_flags
3430 * Holds the items detected.
3432 * Pointer to flow attributes
3434 * Pointer to error structure.
3437 * 0 on success, a negative errno value otherwise and rte_errno is set.
3440 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3441 uint64_t action_flags,
3442 const struct rte_flow_action *action,
3443 const uint64_t item_flags,
3444 const struct rte_flow_attr *attr,
3445 struct rte_flow_error *error)
3447 const struct mlx5_priv *priv = dev->data->dev_private;
3449 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3450 !priv->config.decap_en)
3451 return rte_flow_error_set(error, ENOTSUP,
3452 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3453 "decap is not enabled");
3454 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3455 return rte_flow_error_set(error, ENOTSUP,
3456 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3458 MLX5_FLOW_ACTION_DECAP ? "can only "
3459 "have a single decap action" : "decap "
3460 "after encap is not supported");
3461 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3462 return rte_flow_error_set(error, EINVAL,
3463 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3464 "can't have decap action after"
3467 return rte_flow_error_set(error, ENOTSUP,
3468 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3470 "decap action not supported for "
3472 if (!attr->transfer && priv->representor)
3473 return rte_flow_error_set(error, ENOTSUP,
3474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3475 "decap action for VF representor "
3476 "not supported on NIC table");
3477 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3478 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3479 return rte_flow_error_set(error, ENOTSUP,
3480 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3481 "VXLAN item should be present for VXLAN decap");
3485 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3488 * Validate the raw encap and decap actions.
3491 * Pointer to the rte_eth_dev structure.
3493 * Pointer to the decap action.
3495 * Pointer to the encap action.
3497 * Pointer to flow attributes
3498 * @param[in/out] action_flags
3499 * Holds the actions detected until now.
3500 * @param[out] actions_n
3501 * pointer to the number of actions counter.
3503 * Pointer to the action structure.
3504 * @param[in] item_flags
3505 * Holds the items detected.
3507 * Pointer to error structure.
3510 * 0 on success, a negative errno value otherwise and rte_errno is set.
3513 flow_dv_validate_action_raw_encap_decap
3514 (struct rte_eth_dev *dev,
3515 const struct rte_flow_action_raw_decap *decap,
3516 const struct rte_flow_action_raw_encap *encap,
3517 const struct rte_flow_attr *attr, uint64_t *action_flags,
3518 int *actions_n, const struct rte_flow_action *action,
3519 uint64_t item_flags, struct rte_flow_error *error)
3521 const struct mlx5_priv *priv = dev->data->dev_private;
3524 if (encap && (!encap->size || !encap->data))
3525 return rte_flow_error_set(error, EINVAL,
3526 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3527 "raw encap data cannot be empty");
3528 if (decap && encap) {
3529 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3530 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3533 else if (encap->size <=
3534 MLX5_ENCAPSULATION_DECISION_SIZE &&
3536 MLX5_ENCAPSULATION_DECISION_SIZE)
3539 else if (encap->size >
3540 MLX5_ENCAPSULATION_DECISION_SIZE &&
3542 MLX5_ENCAPSULATION_DECISION_SIZE)
3543 /* 2 L2 actions: encap and decap. */
3546 return rte_flow_error_set(error,
3548 RTE_FLOW_ERROR_TYPE_ACTION,
3549 NULL, "unsupported too small "
3550 "raw decap and too small raw "
3551 "encap combination");
3554 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3555 item_flags, attr, error);
3558 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3562 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3563 return rte_flow_error_set(error, ENOTSUP,
3564 RTE_FLOW_ERROR_TYPE_ACTION,
3566 "small raw encap size");
3567 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3568 return rte_flow_error_set(error, EINVAL,
3569 RTE_FLOW_ERROR_TYPE_ACTION,
3571 "more than one encap action");
3572 if (!attr->transfer && priv->representor)
3573 return rte_flow_error_set
3575 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3576 "encap action for VF representor "
3577 "not supported on NIC table");
3578 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3585 * Validate the ASO CT action.
3588 * Pointer to the rte_eth_dev structure.
3589 * @param[in] action_flags
3590 * Holds the actions detected until now.
3591 * @param[in] item_flags
3592 * The items found in this flow rule.
3594 * Pointer to flow attributes.
3596 * Pointer to error structure.
3599 * 0 on success, a negative errno value otherwise and rte_errno is set.
3602 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3603 uint64_t action_flags,
3604 uint64_t item_flags,
3605 const struct rte_flow_attr *attr,
3606 struct rte_flow_error *error)
3610 if (attr->group == 0 && !attr->transfer)
3611 return rte_flow_error_set(error, ENOTSUP,
3612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3614 "Only support non-root table");
3615 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3616 return rte_flow_error_set(error, ENOTSUP,
3617 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3618 "CT cannot follow a fate action");
3619 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3620 (action_flags & MLX5_FLOW_ACTION_AGE))
3621 return rte_flow_error_set(error, EINVAL,
3622 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3623 "Only one ASO action is supported");
3624 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3625 return rte_flow_error_set(error, EINVAL,
3626 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3627 "Encap cannot exist before CT");
3628 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3629 return rte_flow_error_set(error, EINVAL,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3631 "Not a outer TCP packet");
3636 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3637 struct mlx5_list_entry *entry, void *cb_ctx)
3639 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3640 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3641 struct mlx5_flow_dv_encap_decap_resource *resource;
3643 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3645 if (resource->reformat_type == ctx_resource->reformat_type &&
3646 resource->ft_type == ctx_resource->ft_type &&
3647 resource->flags == ctx_resource->flags &&
3648 resource->size == ctx_resource->size &&
3649 !memcmp((const void *)resource->buf,
3650 (const void *)ctx_resource->buf,
3656 struct mlx5_list_entry *
3657 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3659 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3660 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3661 struct mlx5dv_dr_domain *domain;
3662 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3663 struct mlx5_flow_dv_encap_decap_resource *resource;
3667 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3668 domain = sh->fdb_domain;
3669 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3670 domain = sh->rx_domain;
3672 domain = sh->tx_domain;
3673 /* Register new encap/decap resource. */
3674 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3676 rte_flow_error_set(ctx->error, ENOMEM,
3677 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3678 "cannot allocate resource memory");
3681 *resource = *ctx_resource;
3682 resource->idx = idx;
3683 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->ctx, domain,
3687 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3688 rte_flow_error_set(ctx->error, ENOMEM,
3689 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3690 NULL, "cannot create action");
3694 return &resource->entry;
3697 struct mlx5_list_entry *
3698 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3701 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3702 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3703 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3706 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3708 if (!cache_resource) {
3709 rte_flow_error_set(ctx->error, ENOMEM,
3710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3711 "cannot allocate resource memory");
3714 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3715 cache_resource->idx = idx;
3716 return &cache_resource->entry;
3720 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3722 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3723 struct mlx5_flow_dv_encap_decap_resource *res =
3724 container_of(entry, typeof(*res), entry);
3726 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3730 * Find existing encap/decap resource or create and register a new one.
3732 * @param[in, out] dev
3733 * Pointer to rte_eth_dev structure.
3734 * @param[in, out] resource
3735 * Pointer to encap/decap resource.
3736 * @parm[in, out] dev_flow
3737 * Pointer to the dev_flow.
3739 * pointer to error structure.
3742 * 0 on success otherwise -errno and errno is set.
3745 flow_dv_encap_decap_resource_register
3746 (struct rte_eth_dev *dev,
3747 struct mlx5_flow_dv_encap_decap_resource *resource,
3748 struct mlx5_flow *dev_flow,
3749 struct rte_flow_error *error)
3751 struct mlx5_priv *priv = dev->data->dev_private;
3752 struct mlx5_dev_ctx_shared *sh = priv->sh;
3753 struct mlx5_list_entry *entry;
3757 uint32_t refmt_type:8;
3759 * Header reformat actions can be shared between
3760 * non-root tables. One bit to indicate non-root
3764 uint32_t reserve:15;
3767 } encap_decap_key = {
3769 .ft_type = resource->ft_type,
3770 .refmt_type = resource->reformat_type,
3771 .is_root = !!dev_flow->dv.group,
3775 struct mlx5_flow_cb_ctx ctx = {
3779 struct mlx5_hlist *encaps_decaps;
3782 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3784 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3786 flow_dv_encap_decap_create_cb,
3787 flow_dv_encap_decap_match_cb,
3788 flow_dv_encap_decap_remove_cb,
3789 flow_dv_encap_decap_clone_cb,
3790 flow_dv_encap_decap_clone_free_cb);
3791 if (unlikely(!encaps_decaps))
3793 resource->flags = dev_flow->dv.group ? 0 : 1;
3794 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3795 sizeof(encap_decap_key.v32), 0);
3796 if (resource->reformat_type !=
3797 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3799 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3800 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3803 resource = container_of(entry, typeof(*resource), entry);
3804 dev_flow->dv.encap_decap = resource;
3805 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3810 * Find existing table jump resource or create and register a new one.
3812 * @param[in, out] dev
3813 * Pointer to rte_eth_dev structure.
3814 * @param[in, out] tbl
3815 * Pointer to flow table resource.
3816 * @parm[in, out] dev_flow
3817 * Pointer to the dev_flow.
3819 * pointer to error structure.
3822 * 0 on success otherwise -errno and errno is set.
3825 flow_dv_jump_tbl_resource_register
3826 (struct rte_eth_dev *dev __rte_unused,
3827 struct mlx5_flow_tbl_resource *tbl,
3828 struct mlx5_flow *dev_flow,
3829 struct rte_flow_error *error __rte_unused)
3831 struct mlx5_flow_tbl_data_entry *tbl_data =
3832 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3835 MLX5_ASSERT(tbl_data->jump.action);
3836 dev_flow->handle->rix_jump = tbl_data->idx;
3837 dev_flow->dv.jump = &tbl_data->jump;
3842 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3843 struct mlx5_list_entry *entry, void *cb_ctx)
3845 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3846 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3847 struct mlx5_flow_dv_port_id_action_resource *res =
3848 container_of(entry, typeof(*res), entry);
3850 return ref->port_id != res->port_id;
3853 struct mlx5_list_entry *
3854 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3856 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3857 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3858 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3859 struct mlx5_flow_dv_port_id_action_resource *resource;
3863 /* Register new port id action resource. */
3864 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3866 rte_flow_error_set(ctx->error, ENOMEM,
3867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3868 "cannot allocate port_id action memory");
3872 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3876 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3877 rte_flow_error_set(ctx->error, ENOMEM,
3878 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3879 "cannot create action");
3882 resource->idx = idx;
3883 return &resource->entry;
3886 struct mlx5_list_entry *
3887 flow_dv_port_id_clone_cb(void *tool_ctx,
3888 struct mlx5_list_entry *entry __rte_unused,
3891 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3892 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3893 struct mlx5_flow_dv_port_id_action_resource *resource;
3896 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3898 rte_flow_error_set(ctx->error, ENOMEM,
3899 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3900 "cannot allocate port_id action memory");
3903 memcpy(resource, entry, sizeof(*resource));
3904 resource->idx = idx;
3905 return &resource->entry;
3909 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3911 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3912 struct mlx5_flow_dv_port_id_action_resource *resource =
3913 container_of(entry, typeof(*resource), entry);
3915 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3919 * Find existing table port ID resource or create and register a new one.
3921 * @param[in, out] dev
3922 * Pointer to rte_eth_dev structure.
3923 * @param[in, out] ref
3924 * Pointer to port ID action resource reference.
3925 * @parm[in, out] dev_flow
3926 * Pointer to the dev_flow.
3928 * pointer to error structure.
3931 * 0 on success otherwise -errno and errno is set.
3934 flow_dv_port_id_action_resource_register
3935 (struct rte_eth_dev *dev,
3936 struct mlx5_flow_dv_port_id_action_resource *ref,
3937 struct mlx5_flow *dev_flow,
3938 struct rte_flow_error *error)
3940 struct mlx5_priv *priv = dev->data->dev_private;
3941 struct mlx5_list_entry *entry;
3942 struct mlx5_flow_dv_port_id_action_resource *resource;
3943 struct mlx5_flow_cb_ctx ctx = {
3948 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3951 resource = container_of(entry, typeof(*resource), entry);
3952 dev_flow->dv.port_id_action = resource;
3953 dev_flow->handle->rix_port_id_action = resource->idx;
3958 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3959 struct mlx5_list_entry *entry, void *cb_ctx)
3961 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3962 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3963 struct mlx5_flow_dv_push_vlan_action_resource *res =
3964 container_of(entry, typeof(*res), entry);
3966 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3969 struct mlx5_list_entry *
3970 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3972 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3973 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3974 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3975 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3976 struct mlx5dv_dr_domain *domain;
3980 /* Register new port id action resource. */
3981 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3983 rte_flow_error_set(ctx->error, ENOMEM,
3984 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3985 "cannot allocate push_vlan action memory");
3989 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3990 domain = sh->fdb_domain;
3991 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3992 domain = sh->rx_domain;
3994 domain = sh->tx_domain;
3995 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3998 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3999 rte_flow_error_set(ctx->error, ENOMEM,
4000 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4001 "cannot create push vlan action");
4004 resource->idx = idx;
4005 return &resource->entry;
4008 struct mlx5_list_entry *
4009 flow_dv_push_vlan_clone_cb(void *tool_ctx,
4010 struct mlx5_list_entry *entry __rte_unused,
4013 struct mlx5_dev_ctx_shared *sh = tool_ctx;
4014 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4015 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4018 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
4020 rte_flow_error_set(ctx->error, ENOMEM,
4021 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4022 "cannot allocate push_vlan action memory");
4025 memcpy(resource, entry, sizeof(*resource));
4026 resource->idx = idx;
4027 return &resource->entry;
4031 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
4033 struct mlx5_dev_ctx_shared *sh = tool_ctx;
4034 struct mlx5_flow_dv_push_vlan_action_resource *resource =
4035 container_of(entry, typeof(*resource), entry);
4037 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
4041 * Find existing push vlan resource or create and register a new one.
4043 * @param [in, out] dev
4044 * Pointer to rte_eth_dev structure.
4045 * @param[in, out] ref
4046 * Pointer to port ID action resource reference.
4047 * @parm[in, out] dev_flow
4048 * Pointer to the dev_flow.
4050 * pointer to error structure.
4053 * 0 on success otherwise -errno and errno is set.
4056 flow_dv_push_vlan_action_resource_register
4057 (struct rte_eth_dev *dev,
4058 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4059 struct mlx5_flow *dev_flow,
4060 struct rte_flow_error *error)
4062 struct mlx5_priv *priv = dev->data->dev_private;
4063 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4064 struct mlx5_list_entry *entry;
4065 struct mlx5_flow_cb_ctx ctx = {
4070 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4073 resource = container_of(entry, typeof(*resource), entry);
4075 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4076 dev_flow->dv.push_vlan_res = resource;
4081 * Get the size of specific rte_flow_item_type hdr size
4083 * @param[in] item_type
4084 * Tested rte_flow_item_type.
4087 * sizeof struct item_type, 0 if void or irrelevant.
4090 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4094 switch (item_type) {
4095 case RTE_FLOW_ITEM_TYPE_ETH:
4096 retval = sizeof(struct rte_ether_hdr);
4098 case RTE_FLOW_ITEM_TYPE_VLAN:
4099 retval = sizeof(struct rte_vlan_hdr);
4101 case RTE_FLOW_ITEM_TYPE_IPV4:
4102 retval = sizeof(struct rte_ipv4_hdr);
4104 case RTE_FLOW_ITEM_TYPE_IPV6:
4105 retval = sizeof(struct rte_ipv6_hdr);
4107 case RTE_FLOW_ITEM_TYPE_UDP:
4108 retval = sizeof(struct rte_udp_hdr);
4110 case RTE_FLOW_ITEM_TYPE_TCP:
4111 retval = sizeof(struct rte_tcp_hdr);
4113 case RTE_FLOW_ITEM_TYPE_VXLAN:
4114 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4115 retval = sizeof(struct rte_vxlan_hdr);
4117 case RTE_FLOW_ITEM_TYPE_GRE:
4118 case RTE_FLOW_ITEM_TYPE_NVGRE:
4119 retval = sizeof(struct rte_gre_hdr);
4121 case RTE_FLOW_ITEM_TYPE_MPLS:
4122 retval = sizeof(struct rte_mpls_hdr);
4124 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4132 #define MLX5_ENCAP_IPV4_VERSION 0x40
4133 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4134 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4135 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4136 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4137 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4138 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4141 * Convert the encap action data from list of rte_flow_item to raw buffer
4144 * Pointer to rte_flow_item objects list.
4146 * Pointer to the output buffer.
4148 * Pointer to the output buffer size.
4150 * Pointer to the error structure.
4153 * 0 on success, a negative errno value otherwise and rte_errno is set.
4156 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4157 size_t *size, struct rte_flow_error *error)
4159 struct rte_ether_hdr *eth = NULL;
4160 struct rte_vlan_hdr *vlan = NULL;
4161 struct rte_ipv4_hdr *ipv4 = NULL;
4162 struct rte_ipv6_hdr *ipv6 = NULL;
4163 struct rte_udp_hdr *udp = NULL;
4164 struct rte_vxlan_hdr *vxlan = NULL;
4165 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4166 struct rte_gre_hdr *gre = NULL;
4168 size_t temp_size = 0;
4171 return rte_flow_error_set(error, EINVAL,
4172 RTE_FLOW_ERROR_TYPE_ACTION,
4173 NULL, "invalid empty data");
4174 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4175 len = flow_dv_get_item_hdr_len(items->type);
4176 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4177 return rte_flow_error_set(error, EINVAL,
4178 RTE_FLOW_ERROR_TYPE_ACTION,
4179 (void *)items->type,
4180 "items total size is too big"
4181 " for encap action");
4182 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4183 switch (items->type) {
4184 case RTE_FLOW_ITEM_TYPE_ETH:
4185 eth = (struct rte_ether_hdr *)&buf[temp_size];
4187 case RTE_FLOW_ITEM_TYPE_VLAN:
4188 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4190 return rte_flow_error_set(error, EINVAL,
4191 RTE_FLOW_ERROR_TYPE_ACTION,
4192 (void *)items->type,
4193 "eth header not found");
4194 if (!eth->ether_type)
4195 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4197 case RTE_FLOW_ITEM_TYPE_IPV4:
4198 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4200 return rte_flow_error_set(error, EINVAL,
4201 RTE_FLOW_ERROR_TYPE_ACTION,
4202 (void *)items->type,
4203 "neither eth nor vlan"
4205 if (vlan && !vlan->eth_proto)
4206 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4207 else if (eth && !eth->ether_type)
4208 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4209 if (!ipv4->version_ihl)
4210 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4211 MLX5_ENCAP_IPV4_IHL_MIN;
4212 if (!ipv4->time_to_live)
4213 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4215 case RTE_FLOW_ITEM_TYPE_IPV6:
4216 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4218 return rte_flow_error_set(error, EINVAL,
4219 RTE_FLOW_ERROR_TYPE_ACTION,
4220 (void *)items->type,
4221 "neither eth nor vlan"
4223 if (vlan && !vlan->eth_proto)
4224 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4225 else if (eth && !eth->ether_type)
4226 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4227 if (!ipv6->vtc_flow)
4229 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4230 if (!ipv6->hop_limits)
4231 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4233 case RTE_FLOW_ITEM_TYPE_UDP:
4234 udp = (struct rte_udp_hdr *)&buf[temp_size];
4236 return rte_flow_error_set(error, EINVAL,
4237 RTE_FLOW_ERROR_TYPE_ACTION,
4238 (void *)items->type,
4239 "ip header not found");
4240 if (ipv4 && !ipv4->next_proto_id)
4241 ipv4->next_proto_id = IPPROTO_UDP;
4242 else if (ipv6 && !ipv6->proto)
4243 ipv6->proto = IPPROTO_UDP;
4245 case RTE_FLOW_ITEM_TYPE_VXLAN:
4246 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4248 return rte_flow_error_set(error, EINVAL,
4249 RTE_FLOW_ERROR_TYPE_ACTION,
4250 (void *)items->type,
4251 "udp header not found");
4253 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4254 if (!vxlan->vx_flags)
4256 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4258 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4259 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4261 return rte_flow_error_set(error, EINVAL,
4262 RTE_FLOW_ERROR_TYPE_ACTION,
4263 (void *)items->type,
4264 "udp header not found");
4265 if (!vxlan_gpe->proto)
4266 return rte_flow_error_set(error, EINVAL,
4267 RTE_FLOW_ERROR_TYPE_ACTION,
4268 (void *)items->type,
4269 "next protocol not found");
4272 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4273 if (!vxlan_gpe->vx_flags)
4274 vxlan_gpe->vx_flags =
4275 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4277 case RTE_FLOW_ITEM_TYPE_GRE:
4278 case RTE_FLOW_ITEM_TYPE_NVGRE:
4279 gre = (struct rte_gre_hdr *)&buf[temp_size];
4281 return rte_flow_error_set(error, EINVAL,
4282 RTE_FLOW_ERROR_TYPE_ACTION,
4283 (void *)items->type,
4284 "next protocol not found");
4286 return rte_flow_error_set(error, EINVAL,
4287 RTE_FLOW_ERROR_TYPE_ACTION,
4288 (void *)items->type,
4289 "ip header not found");
4290 if (ipv4 && !ipv4->next_proto_id)
4291 ipv4->next_proto_id = IPPROTO_GRE;
4292 else if (ipv6 && !ipv6->proto)
4293 ipv6->proto = IPPROTO_GRE;
4295 case RTE_FLOW_ITEM_TYPE_VOID:
4298 return rte_flow_error_set(error, EINVAL,
4299 RTE_FLOW_ERROR_TYPE_ACTION,
4300 (void *)items->type,
4301 "unsupported item type");
4311 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4313 struct rte_ether_hdr *eth = NULL;
4314 struct rte_vlan_hdr *vlan = NULL;
4315 struct rte_ipv6_hdr *ipv6 = NULL;
4316 struct rte_udp_hdr *udp = NULL;
4320 eth = (struct rte_ether_hdr *)data;
4321 next_hdr = (char *)(eth + 1);
4322 proto = RTE_BE16(eth->ether_type);
4325 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4326 vlan = (struct rte_vlan_hdr *)next_hdr;
4327 proto = RTE_BE16(vlan->eth_proto);
4328 next_hdr += sizeof(struct rte_vlan_hdr);
4331 /* HW calculates IPv4 csum. no need to proceed */
4332 if (proto == RTE_ETHER_TYPE_IPV4)
4335 /* non IPv4/IPv6 header. not supported */
4336 if (proto != RTE_ETHER_TYPE_IPV6) {
4337 return rte_flow_error_set(error, ENOTSUP,
4338 RTE_FLOW_ERROR_TYPE_ACTION,
4339 NULL, "Cannot offload non IPv4/IPv6");
4342 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4344 /* ignore non UDP */
4345 if (ipv6->proto != IPPROTO_UDP)
4348 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4349 udp->dgram_cksum = 0;
4355 * Convert L2 encap action to DV specification.
4358 * Pointer to rte_eth_dev structure.
4360 * Pointer to action structure.
4361 * @param[in, out] dev_flow
4362 * Pointer to the mlx5_flow.
4363 * @param[in] transfer
4364 * Mark if the flow is E-Switch flow.
4366 * Pointer to the error structure.
4369 * 0 on success, a negative errno value otherwise and rte_errno is set.
4372 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4373 const struct rte_flow_action *action,
4374 struct mlx5_flow *dev_flow,
4376 struct rte_flow_error *error)
4378 const struct rte_flow_item *encap_data;
4379 const struct rte_flow_action_raw_encap *raw_encap_data;
4380 struct mlx5_flow_dv_encap_decap_resource res = {
4382 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4383 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4384 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4387 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4389 (const struct rte_flow_action_raw_encap *)action->conf;
4390 res.size = raw_encap_data->size;
4391 memcpy(res.buf, raw_encap_data->data, res.size);
4393 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4395 ((const struct rte_flow_action_vxlan_encap *)
4396 action->conf)->definition;
4399 ((const struct rte_flow_action_nvgre_encap *)
4400 action->conf)->definition;
4401 if (flow_dv_convert_encap_data(encap_data, res.buf,
4405 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4407 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4408 return rte_flow_error_set(error, EINVAL,
4409 RTE_FLOW_ERROR_TYPE_ACTION,
4410 NULL, "can't create L2 encap action");
4415 * Convert L2 decap action to DV specification.
4418 * Pointer to rte_eth_dev structure.
4419 * @param[in, out] dev_flow
4420 * Pointer to the mlx5_flow.
4421 * @param[in] transfer
4422 * Mark if the flow is E-Switch flow.
4424 * Pointer to the error structure.
4427 * 0 on success, a negative errno value otherwise and rte_errno is set.
4430 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4431 struct mlx5_flow *dev_flow,
4433 struct rte_flow_error *error)
4435 struct mlx5_flow_dv_encap_decap_resource res = {
4438 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4439 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4440 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4443 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4444 return rte_flow_error_set(error, EINVAL,
4445 RTE_FLOW_ERROR_TYPE_ACTION,
4446 NULL, "can't create L2 decap action");
4451 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4454 * Pointer to rte_eth_dev structure.
4456 * Pointer to action structure.
4457 * @param[in, out] dev_flow
4458 * Pointer to the mlx5_flow.
4460 * Pointer to the flow attributes.
4462 * Pointer to the error structure.
4465 * 0 on success, a negative errno value otherwise and rte_errno is set.
4468 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4469 const struct rte_flow_action *action,
4470 struct mlx5_flow *dev_flow,
4471 const struct rte_flow_attr *attr,
4472 struct rte_flow_error *error)
4474 const struct rte_flow_action_raw_encap *encap_data;
4475 struct mlx5_flow_dv_encap_decap_resource res;
4477 memset(&res, 0, sizeof(res));
4478 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4479 res.size = encap_data->size;
4480 memcpy(res.buf, encap_data->data, res.size);
4481 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4482 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4483 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4485 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4487 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4488 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4489 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4490 return rte_flow_error_set(error, EINVAL,
4491 RTE_FLOW_ERROR_TYPE_ACTION,
4492 NULL, "can't create encap action");
4497 * Create action push VLAN.
4500 * Pointer to rte_eth_dev structure.
4502 * Pointer to the flow attributes.
4504 * Pointer to the vlan to push to the Ethernet header.
4505 * @param[in, out] dev_flow
4506 * Pointer to the mlx5_flow.
4508 * Pointer to the error structure.
4511 * 0 on success, a negative errno value otherwise and rte_errno is set.
4514 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4515 const struct rte_flow_attr *attr,
4516 const struct rte_vlan_hdr *vlan,
4517 struct mlx5_flow *dev_flow,
4518 struct rte_flow_error *error)
4520 struct mlx5_flow_dv_push_vlan_action_resource res;
4522 memset(&res, 0, sizeof(res));
4524 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4527 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4529 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4530 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4531 return flow_dv_push_vlan_action_resource_register
4532 (dev, &res, dev_flow, error);
4536 * Validate the modify-header actions.
4538 * @param[in] action_flags
4539 * Holds the actions detected until now.
4541 * Pointer to the modify action.
4543 * Pointer to error structure.
4546 * 0 on success, a negative errno value otherwise and rte_errno is set.
4549 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4550 const struct rte_flow_action *action,
4551 struct rte_flow_error *error)
4553 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4554 return rte_flow_error_set(error, EINVAL,
4555 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4556 NULL, "action configuration not set");
4557 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4558 return rte_flow_error_set(error, EINVAL,
4559 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4560 "can't have encap action before"
4566 * Validate the modify-header MAC address actions.
4568 * @param[in] action_flags
4569 * Holds the actions detected until now.
4571 * Pointer to the modify action.
4572 * @param[in] item_flags
4573 * Holds the items detected.
4575 * Pointer to error structure.
4578 * 0 on success, a negative errno value otherwise and rte_errno is set.
4581 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4582 const struct rte_flow_action *action,
4583 const uint64_t item_flags,
4584 struct rte_flow_error *error)
4588 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4590 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4591 return rte_flow_error_set(error, EINVAL,
4592 RTE_FLOW_ERROR_TYPE_ACTION,
4594 "no L2 item in pattern");
4600 * Validate the modify-header IPv4 address actions.
4602 * @param[in] action_flags
4603 * Holds the actions detected until now.
4605 * Pointer to the modify action.
4606 * @param[in] item_flags
4607 * Holds the items detected.
4609 * Pointer to error structure.
4612 * 0 on success, a negative errno value otherwise and rte_errno is set.
4615 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4616 const struct rte_flow_action *action,
4617 const uint64_t item_flags,
4618 struct rte_flow_error *error)
4623 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4625 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4626 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4627 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4628 if (!(item_flags & layer))
4629 return rte_flow_error_set(error, EINVAL,
4630 RTE_FLOW_ERROR_TYPE_ACTION,
4632 "no ipv4 item in pattern");
4638 * Validate the modify-header IPv6 address actions.
4640 * @param[in] action_flags
4641 * Holds the actions detected until now.
4643 * Pointer to the modify action.
4644 * @param[in] item_flags
4645 * Holds the items detected.
4647 * Pointer to error structure.
4650 * 0 on success, a negative errno value otherwise and rte_errno is set.
4653 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4654 const struct rte_flow_action *action,
4655 const uint64_t item_flags,
4656 struct rte_flow_error *error)
4661 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4663 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4664 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4665 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4666 if (!(item_flags & layer))
4667 return rte_flow_error_set(error, EINVAL,
4668 RTE_FLOW_ERROR_TYPE_ACTION,
4670 "no ipv6 item in pattern");
4676 * Validate the modify-header TP actions.
4678 * @param[in] action_flags
4679 * Holds the actions detected until now.
4681 * Pointer to the modify action.
4682 * @param[in] item_flags
4683 * Holds the items detected.
4685 * Pointer to error structure.
4688 * 0 on success, a negative errno value otherwise and rte_errno is set.
4691 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4692 const struct rte_flow_action *action,
4693 const uint64_t item_flags,
4694 struct rte_flow_error *error)
4699 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4701 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4702 MLX5_FLOW_LAYER_INNER_L4 :
4703 MLX5_FLOW_LAYER_OUTER_L4;
4704 if (!(item_flags & layer))
4705 return rte_flow_error_set(error, EINVAL,
4706 RTE_FLOW_ERROR_TYPE_ACTION,
4707 NULL, "no transport layer "
4714 * Validate the modify-header actions of increment/decrement
4715 * TCP Sequence-number.
4717 * @param[in] action_flags
4718 * Holds the actions detected until now.
4720 * Pointer to the modify action.
4721 * @param[in] item_flags
4722 * Holds the items detected.
4724 * Pointer to error structure.
4727 * 0 on success, a negative errno value otherwise and rte_errno is set.
4730 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4731 const struct rte_flow_action *action,
4732 const uint64_t item_flags,
4733 struct rte_flow_error *error)
4738 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4740 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4741 MLX5_FLOW_LAYER_INNER_L4_TCP :
4742 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4743 if (!(item_flags & layer))
4744 return rte_flow_error_set(error, EINVAL,
4745 RTE_FLOW_ERROR_TYPE_ACTION,
4746 NULL, "no TCP item in"
4748 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4749 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4750 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4751 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4752 return rte_flow_error_set(error, EINVAL,
4753 RTE_FLOW_ERROR_TYPE_ACTION,
4755 "cannot decrease and increase"
4756 " TCP sequence number"
4757 " at the same time");
4763 * Validate the modify-header actions of increment/decrement
4764 * TCP Acknowledgment number.
4766 * @param[in] action_flags
4767 * Holds the actions detected until now.
4769 * Pointer to the modify action.
4770 * @param[in] item_flags
4771 * Holds the items detected.
4773 * Pointer to error structure.
4776 * 0 on success, a negative errno value otherwise and rte_errno is set.
4779 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4780 const struct rte_flow_action *action,
4781 const uint64_t item_flags,
4782 struct rte_flow_error *error)
4787 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4789 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4790 MLX5_FLOW_LAYER_INNER_L4_TCP :
4791 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4792 if (!(item_flags & layer))
4793 return rte_flow_error_set(error, EINVAL,
4794 RTE_FLOW_ERROR_TYPE_ACTION,
4795 NULL, "no TCP item in"
4797 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4798 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4799 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4800 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4801 return rte_flow_error_set(error, EINVAL,
4802 RTE_FLOW_ERROR_TYPE_ACTION,
4804 "cannot decrease and increase"
4805 " TCP acknowledgment number"
4806 " at the same time");
4812 * Validate the modify-header TTL actions.
4814 * @param[in] action_flags
4815 * Holds the actions detected until now.
4817 * Pointer to the modify action.
4818 * @param[in] item_flags
4819 * Holds the items detected.
4821 * Pointer to error structure.
4824 * 0 on success, a negative errno value otherwise and rte_errno is set.
4827 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4828 const struct rte_flow_action *action,
4829 const uint64_t item_flags,
4830 struct rte_flow_error *error)
4835 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4837 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4838 MLX5_FLOW_LAYER_INNER_L3 :
4839 MLX5_FLOW_LAYER_OUTER_L3;
4840 if (!(item_flags & layer))
4841 return rte_flow_error_set(error, EINVAL,
4842 RTE_FLOW_ERROR_TYPE_ACTION,
4844 "no IP protocol in pattern");
4850 * Validate the generic modify field actions.
4852 * Pointer to the rte_eth_dev structure.
4853 * @param[in] action_flags
4854 * Holds the actions detected until now.
4856 * Pointer to the modify action.
4858 * Pointer to the flow attributes.
4860 * Pointer to error structure.
4863 * Number of header fields to modify (0 or more) on success,
4864 * a negative errno value otherwise and rte_errno is set.
4867 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4868 const uint64_t action_flags,
4869 const struct rte_flow_action *action,
4870 const struct rte_flow_attr *attr,
4871 struct rte_flow_error *error)
4874 struct mlx5_priv *priv = dev->data->dev_private;
4875 struct mlx5_dev_config *config = &priv->config;
4876 const struct rte_flow_action_modify_field *action_modify_field =
4878 uint32_t dst_width = mlx5_flow_item_field_width(config,
4879 action_modify_field->dst.field);
4880 uint32_t src_width = mlx5_flow_item_field_width(config,
4881 action_modify_field->src.field);
4883 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4887 if (action_modify_field->width == 0)
4888 return rte_flow_error_set(error, EINVAL,
4889 RTE_FLOW_ERROR_TYPE_ACTION, action,
4890 "no bits are requested to be modified");
4891 else if (action_modify_field->width > dst_width ||
4892 action_modify_field->width > src_width)
4893 return rte_flow_error_set(error, EINVAL,
4894 RTE_FLOW_ERROR_TYPE_ACTION, action,
4895 "cannot modify more bits than"
4896 " the width of a field");
4897 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4898 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4899 if ((action_modify_field->dst.offset +
4900 action_modify_field->width > dst_width) ||
4901 (action_modify_field->dst.offset % 32))
4902 return rte_flow_error_set(error, EINVAL,
4903 RTE_FLOW_ERROR_TYPE_ACTION, action,
4904 "destination offset is too big"
4905 " or not aligned to 4 bytes");
4906 if (action_modify_field->dst.level &&
4907 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4908 return rte_flow_error_set(error, ENOTSUP,
4909 RTE_FLOW_ERROR_TYPE_ACTION, action,
4910 "inner header fields modification"
4911 " is not supported");
4913 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4914 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4915 if (!attr->transfer && !attr->group)
4916 return rte_flow_error_set(error, ENOTSUP,
4917 RTE_FLOW_ERROR_TYPE_ACTION, action,
4918 "modify field action is not"
4919 " supported for group 0");
4920 if ((action_modify_field->src.offset +
4921 action_modify_field->width > src_width) ||
4922 (action_modify_field->src.offset % 32))
4923 return rte_flow_error_set(error, EINVAL,
4924 RTE_FLOW_ERROR_TYPE_ACTION, action,
4925 "source offset is too big"
4926 " or not aligned to 4 bytes");
4927 if (action_modify_field->src.level &&
4928 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4929 return rte_flow_error_set(error, ENOTSUP,
4930 RTE_FLOW_ERROR_TYPE_ACTION, action,
4931 "inner header fields modification"
4932 " is not supported");
4934 if ((action_modify_field->dst.field ==
4935 action_modify_field->src.field) &&
4936 (action_modify_field->dst.level ==
4937 action_modify_field->src.level))
4938 return rte_flow_error_set(error, EINVAL,
4939 RTE_FLOW_ERROR_TYPE_ACTION, action,
4940 "source and destination fields"
4941 " cannot be the same");
4942 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4943 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4944 return rte_flow_error_set(error, EINVAL,
4945 RTE_FLOW_ERROR_TYPE_ACTION, action,
4946 "immediate value or a pointer to it"
4947 " cannot be used as a destination");
4948 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4949 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4950 return rte_flow_error_set(error, ENOTSUP,
4951 RTE_FLOW_ERROR_TYPE_ACTION, action,
4952 "modifications of an arbitrary"
4953 " place in a packet is not supported");
4954 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4955 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4956 return rte_flow_error_set(error, ENOTSUP,
4957 RTE_FLOW_ERROR_TYPE_ACTION, action,
4958 "modifications of the 802.1Q Tag"
4959 " Identifier is not supported");
4960 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4961 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4962 return rte_flow_error_set(error, ENOTSUP,
4963 RTE_FLOW_ERROR_TYPE_ACTION, action,
4964 "modifications of the VXLAN Network"
4965 " Identifier is not supported");
4966 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4967 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4968 return rte_flow_error_set(error, ENOTSUP,
4969 RTE_FLOW_ERROR_TYPE_ACTION, action,
4970 "modifications of the GENEVE Network"
4971 " Identifier is not supported");
4972 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4973 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4974 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4975 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4976 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4977 !mlx5_flow_ext_mreg_supported(dev))
4978 return rte_flow_error_set(error, ENOTSUP,
4979 RTE_FLOW_ERROR_TYPE_ACTION, action,
4980 "cannot modify mark or metadata without"
4981 " extended metadata register support");
4983 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4984 return rte_flow_error_set(error, ENOTSUP,
4985 RTE_FLOW_ERROR_TYPE_ACTION, action,
4986 "add and sub operations"
4987 " are not supported");
4988 return (action_modify_field->width / 32) +
4989 !!(action_modify_field->width % 32);
4993 * Validate jump action.
4996 * Pointer to the jump action.
4997 * @param[in] action_flags
4998 * Holds the actions detected until now.
4999 * @param[in] attributes
5000 * Pointer to flow attributes
5001 * @param[in] external
5002 * Action belongs to flow rule created by request external to PMD.
5004 * Pointer to error structure.
5007 * 0 on success, a negative errno value otherwise and rte_errno is set.
5010 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
5011 const struct mlx5_flow_tunnel *tunnel,
5012 const struct rte_flow_action *action,
5013 uint64_t action_flags,
5014 const struct rte_flow_attr *attributes,
5015 bool external, struct rte_flow_error *error)
5017 uint32_t target_group, table;
5019 struct flow_grp_info grp_info = {
5020 .external = !!external,
5021 .transfer = !!attributes->transfer,
5025 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5026 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5027 return rte_flow_error_set(error, EINVAL,
5028 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5029 "can't have 2 fate actions in"
5032 return rte_flow_error_set(error, EINVAL,
5033 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5034 NULL, "action configuration not set");
5036 ((const struct rte_flow_action_jump *)action->conf)->group;
5037 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5041 if (attributes->group == target_group &&
5042 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5043 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5044 return rte_flow_error_set(error, EINVAL,
5045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5046 "target group must be other than"
5047 " the current flow group");
5052 * Validate the port_id action.
5055 * Pointer to rte_eth_dev structure.
5056 * @param[in] action_flags
5057 * Bit-fields that holds the actions detected until now.
5059 * Port_id RTE action structure.
5061 * Attributes of flow that includes this action.
5063 * Pointer to error structure.
5066 * 0 on success, a negative errno value otherwise and rte_errno is set.
5069 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5070 uint64_t action_flags,
5071 const struct rte_flow_action *action,
5072 const struct rte_flow_attr *attr,
5073 struct rte_flow_error *error)
5075 const struct rte_flow_action_port_id *port_id;
5076 struct mlx5_priv *act_priv;
5077 struct mlx5_priv *dev_priv;
5080 if (!attr->transfer)
5081 return rte_flow_error_set(error, ENOTSUP,
5082 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5084 "port id action is valid in transfer"
5086 if (!action || !action->conf)
5087 return rte_flow_error_set(error, ENOTSUP,
5088 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5090 "port id action parameters must be"
5092 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5093 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5094 return rte_flow_error_set(error, EINVAL,
5095 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5096 "can have only one fate actions in"
5098 dev_priv = mlx5_dev_to_eswitch_info(dev);
5100 return rte_flow_error_set(error, rte_errno,
5101 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5103 "failed to obtain E-Switch info");
5104 port_id = action->conf;
5105 port = port_id->original ? dev->data->port_id : port_id->id;
5106 act_priv = mlx5_port_to_eswitch_info(port, false);
5108 return rte_flow_error_set
5110 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
5111 "failed to obtain E-Switch port id for port");
5112 if (act_priv->domain_id != dev_priv->domain_id)
5113 return rte_flow_error_set
5115 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5116 "port does not belong to"
5117 " E-Switch being configured");
5122 * Get the maximum number of modify header actions.
5125 * Pointer to rte_eth_dev structure.
5127 * Whether action is on root table.
5130 * Max number of modify header actions device can support.
5132 static inline unsigned int
5133 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5137 * There's no way to directly query the max capacity from FW.
5138 * The maximal value on root table should be assumed to be supported.
5141 return MLX5_MAX_MODIFY_NUM;
5143 return MLX5_ROOT_TBL_MODIFY_NUM;
5147 * Validate the meter action.
5150 * Pointer to rte_eth_dev structure.
5151 * @param[in] action_flags
5152 * Bit-fields that holds the actions detected until now.
5154 * Pointer to the meter action.
5156 * Attributes of flow that includes this action.
5157 * @param[in] port_id_item
5158 * Pointer to item indicating port id.
5160 * Pointer to error structure.
5163 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5166 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5167 uint64_t action_flags,
5168 const struct rte_flow_action *action,
5169 const struct rte_flow_attr *attr,
5170 const struct rte_flow_item *port_id_item,
5172 struct rte_flow_error *error)
5174 struct mlx5_priv *priv = dev->data->dev_private;
5175 const struct rte_flow_action_meter *am = action->conf;
5176 struct mlx5_flow_meter_info *fm;
5177 struct mlx5_flow_meter_policy *mtr_policy;
5178 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5181 return rte_flow_error_set(error, EINVAL,
5182 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5183 "meter action conf is NULL");
5185 if (action_flags & MLX5_FLOW_ACTION_METER)
5186 return rte_flow_error_set(error, ENOTSUP,
5187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5188 "meter chaining not support");
5189 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5190 return rte_flow_error_set(error, ENOTSUP,
5191 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5192 "meter with jump not support");
5194 return rte_flow_error_set(error, ENOTSUP,
5195 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5197 "meter action not supported");
5198 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5200 return rte_flow_error_set(error, EINVAL,
5201 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5203 /* aso meter can always be shared by different domains */
5204 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5205 !(fm->transfer == attr->transfer ||
5206 (!fm->ingress && !attr->ingress && attr->egress) ||
5207 (!fm->egress && !attr->egress && attr->ingress)))
5208 return rte_flow_error_set(error, EINVAL,
5209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5210 "Flow attributes domain are either invalid "
5211 "or have a domain conflict with current "
5212 "meter attributes");
5213 if (fm->def_policy) {
5214 if (!((attr->transfer &&
5215 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5217 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5219 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5220 return rte_flow_error_set(error, EINVAL,
5221 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5222 "Flow attributes domain "
5223 "have a conflict with current "
5224 "meter domain attributes");
5227 mtr_policy = mlx5_flow_meter_policy_find(dev,
5228 fm->policy_id, NULL);
5230 return rte_flow_error_set(error, EINVAL,
5231 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5232 "Invalid policy id for meter ");
5233 if (!((attr->transfer && mtr_policy->transfer) ||
5234 (attr->egress && mtr_policy->egress) ||
5235 (attr->ingress && mtr_policy->ingress)))
5236 return rte_flow_error_set(error, EINVAL,
5237 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5238 "Flow attributes domain "
5239 "have a conflict with current "
5240 "meter domain attributes");
5241 if (attr->transfer && mtr_policy->dev) {
5243 * When policy has fate action of port_id,
5244 * the flow should have the same src port as policy.
5246 struct mlx5_priv *policy_port_priv =
5247 mtr_policy->dev->data->dev_private;
5248 int32_t flow_src_port = priv->representor_id;
5251 const struct rte_flow_item_port_id *spec =
5253 struct mlx5_priv *port_priv =
5254 mlx5_port_to_eswitch_info(spec->id,
5257 return rte_flow_error_set(error,
5259 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5261 "Failed to get port info.");
5262 flow_src_port = port_priv->representor_id;
5264 if (flow_src_port != policy_port_priv->representor_id)
5265 return rte_flow_error_set(error,
5267 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5269 "Flow and meter policy "
5270 "have different src port.");
5272 *def_policy = false;
5278 * Validate the age action.
5280 * @param[in] action_flags
5281 * Holds the actions detected until now.
5283 * Pointer to the age action.
5285 * Pointer to the Ethernet device structure.
5287 * Pointer to error structure.
5290 * 0 on success, a negative errno value otherwise and rte_errno is set.
5293 flow_dv_validate_action_age(uint64_t action_flags,
5294 const struct rte_flow_action *action,
5295 struct rte_eth_dev *dev,
5296 struct rte_flow_error *error)
5298 struct mlx5_priv *priv = dev->data->dev_private;
5299 const struct rte_flow_action_age *age = action->conf;
5301 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
5302 !priv->sh->aso_age_mng))
5303 return rte_flow_error_set(error, ENOTSUP,
5304 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5306 "age action not supported");
5307 if (!(action->conf))
5308 return rte_flow_error_set(error, EINVAL,
5309 RTE_FLOW_ERROR_TYPE_ACTION, action,
5310 "configuration cannot be null");
5311 if (!(age->timeout))
5312 return rte_flow_error_set(error, EINVAL,
5313 RTE_FLOW_ERROR_TYPE_ACTION, action,
5314 "invalid timeout value 0");
5315 if (action_flags & MLX5_FLOW_ACTION_AGE)
5316 return rte_flow_error_set(error, EINVAL,
5317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5318 "duplicate age actions set");
5323 * Validate the modify-header IPv4 DSCP actions.
5325 * @param[in] action_flags
5326 * Holds the actions detected until now.
5328 * Pointer to the modify action.
5329 * @param[in] item_flags
5330 * Holds the items detected.
5332 * Pointer to error structure.
5335 * 0 on success, a negative errno value otherwise and rte_errno is set.
5338 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5339 const struct rte_flow_action *action,
5340 const uint64_t item_flags,
5341 struct rte_flow_error *error)
5345 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5347 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5348 return rte_flow_error_set(error, EINVAL,
5349 RTE_FLOW_ERROR_TYPE_ACTION,
5351 "no ipv4 item in pattern");
5357 * Validate the modify-header IPv6 DSCP actions.
5359 * @param[in] action_flags
5360 * Holds the actions detected until now.
5362 * Pointer to the modify action.
5363 * @param[in] item_flags
5364 * Holds the items detected.
5366 * Pointer to error structure.
5369 * 0 on success, a negative errno value otherwise and rte_errno is set.
5372 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5373 const struct rte_flow_action *action,
5374 const uint64_t item_flags,
5375 struct rte_flow_error *error)
5379 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5381 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5382 return rte_flow_error_set(error, EINVAL,
5383 RTE_FLOW_ERROR_TYPE_ACTION,
5385 "no ipv6 item in pattern");
5391 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5392 struct mlx5_list_entry *entry, void *cb_ctx)
5394 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5395 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5396 struct mlx5_flow_dv_modify_hdr_resource *resource =
5397 container_of(entry, typeof(*resource), entry);
5398 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5400 key_len += ref->actions_num * sizeof(ref->actions[0]);
5401 return ref->actions_num != resource->actions_num ||
5402 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5405 static struct mlx5_indexed_pool *
5406 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5408 struct mlx5_indexed_pool *ipool = __atomic_load_n
5409 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5412 struct mlx5_indexed_pool *expected = NULL;
5413 struct mlx5_indexed_pool_config cfg =
5414 (struct mlx5_indexed_pool_config) {
5415 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5417 sizeof(struct mlx5_modification_cmd),
5422 .release_mem_en = !!sh->reclaim_mode,
5423 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5424 .malloc = mlx5_malloc,
5426 .type = "mlx5_modify_action_resource",
5429 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5430 ipool = mlx5_ipool_create(&cfg);
5433 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5434 &expected, ipool, false,
5436 __ATOMIC_SEQ_CST)) {
5437 mlx5_ipool_destroy(ipool);
5438 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5445 struct mlx5_list_entry *
5446 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5448 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5449 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5450 struct mlx5dv_dr_domain *ns;
5451 struct mlx5_flow_dv_modify_hdr_resource *entry;
5452 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5453 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5454 ref->actions_num - 1);
5456 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5457 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5460 if (unlikely(!ipool)) {
5461 rte_flow_error_set(ctx->error, ENOMEM,
5462 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5463 NULL, "cannot allocate modify ipool");
5466 entry = mlx5_ipool_zmalloc(ipool, &idx);
5468 rte_flow_error_set(ctx->error, ENOMEM,
5469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5470 "cannot allocate resource memory");
5473 rte_memcpy(&entry->ft_type,
5474 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5475 key_len + data_len);
5476 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5477 ns = sh->fdb_domain;
5478 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5482 ret = mlx5_flow_os_create_flow_action_modify_header
5483 (sh->ctx, ns, entry,
5484 data_len, &entry->action);
5486 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5487 rte_flow_error_set(ctx->error, ENOMEM,
5488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5489 NULL, "cannot create modification action");
5493 return &entry->entry;
5496 struct mlx5_list_entry *
5497 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5500 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5501 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5502 struct mlx5_flow_dv_modify_hdr_resource *entry;
5503 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5504 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5507 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5510 rte_flow_error_set(ctx->error, ENOMEM,
5511 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5512 "cannot allocate resource memory");
5515 memcpy(entry, oentry, sizeof(*entry) + data_len);
5517 return &entry->entry;
5521 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5523 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5524 struct mlx5_flow_dv_modify_hdr_resource *res =
5525 container_of(entry, typeof(*res), entry);
5527 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5531 * Validate the sample action.
5533 * @param[in, out] action_flags
5534 * Holds the actions detected until now.
5536 * Pointer to the sample action.
5538 * Pointer to the Ethernet device structure.
5540 * Attributes of flow that includes this action.
5541 * @param[in] item_flags
5542 * Holds the items detected.
5544 * Pointer to the RSS action.
5545 * @param[out] sample_rss
5546 * Pointer to the RSS action in sample action list.
5548 * Pointer to the COUNT action in sample action list.
5549 * @param[out] fdb_mirror_limit
5550 * Pointer to the FDB mirror limitation flag.
5552 * Pointer to error structure.
5555 * 0 on success, a negative errno value otherwise and rte_errno is set.
5558 flow_dv_validate_action_sample(uint64_t *action_flags,
5559 const struct rte_flow_action *action,
5560 struct rte_eth_dev *dev,
5561 const struct rte_flow_attr *attr,
5562 uint64_t item_flags,
5563 const struct rte_flow_action_rss *rss,
5564 const struct rte_flow_action_rss **sample_rss,
5565 const struct rte_flow_action_count **count,
5566 int *fdb_mirror_limit,
5567 struct rte_flow_error *error)
5569 struct mlx5_priv *priv = dev->data->dev_private;
5570 struct mlx5_dev_config *dev_conf = &priv->config;
5571 const struct rte_flow_action_sample *sample = action->conf;
5572 const struct rte_flow_action *act;
5573 uint64_t sub_action_flags = 0;
5574 uint16_t queue_index = 0xFFFF;
5579 return rte_flow_error_set(error, EINVAL,
5580 RTE_FLOW_ERROR_TYPE_ACTION, action,
5581 "configuration cannot be NULL");
5582 if (sample->ratio == 0)
5583 return rte_flow_error_set(error, EINVAL,
5584 RTE_FLOW_ERROR_TYPE_ACTION, action,
5585 "ratio value starts from 1");
5586 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5587 return rte_flow_error_set(error, ENOTSUP,
5588 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5590 "sample action not supported");
5591 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5592 return rte_flow_error_set(error, EINVAL,
5593 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5594 "Multiple sample actions not "
5596 if (*action_flags & MLX5_FLOW_ACTION_METER)
5597 return rte_flow_error_set(error, EINVAL,
5598 RTE_FLOW_ERROR_TYPE_ACTION, action,
5599 "wrong action order, meter should "
5600 "be after sample action");
5601 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5602 return rte_flow_error_set(error, EINVAL,
5603 RTE_FLOW_ERROR_TYPE_ACTION, action,
5604 "wrong action order, jump should "
5605 "be after sample action");
5606 act = sample->actions;
5607 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5608 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5609 return rte_flow_error_set(error, ENOTSUP,
5610 RTE_FLOW_ERROR_TYPE_ACTION,
5611 act, "too many actions");
5612 switch (act->type) {
5613 case RTE_FLOW_ACTION_TYPE_QUEUE:
5614 ret = mlx5_flow_validate_action_queue(act,
5620 queue_index = ((const struct rte_flow_action_queue *)
5621 (act->conf))->index;
5622 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5625 case RTE_FLOW_ACTION_TYPE_RSS:
5626 *sample_rss = act->conf;
5627 ret = mlx5_flow_validate_action_rss(act,
5634 if (rss && *sample_rss &&
5635 ((*sample_rss)->level != rss->level ||
5636 (*sample_rss)->types != rss->types))
5637 return rte_flow_error_set(error, ENOTSUP,
5638 RTE_FLOW_ERROR_TYPE_ACTION,
5640 "Can't use the different RSS types "
5641 "or level in the same flow");
5642 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5643 queue_index = (*sample_rss)->queue[0];
5644 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5647 case RTE_FLOW_ACTION_TYPE_MARK:
5648 ret = flow_dv_validate_action_mark(dev, act,
5653 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5654 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5655 MLX5_FLOW_ACTION_MARK_EXT;
5657 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5660 case RTE_FLOW_ACTION_TYPE_COUNT:
5661 ret = flow_dv_validate_action_count
5662 (dev, is_shared_action_count(act),
5663 *action_flags | sub_action_flags,
5668 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5669 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5672 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5673 ret = flow_dv_validate_action_port_id(dev,
5680 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5683 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5684 ret = flow_dv_validate_action_raw_encap_decap
5685 (dev, NULL, act->conf, attr, &sub_action_flags,
5686 &actions_n, action, item_flags, error);
5691 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5692 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5693 ret = flow_dv_validate_action_l2_encap(dev,
5699 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5703 return rte_flow_error_set(error, ENOTSUP,
5704 RTE_FLOW_ERROR_TYPE_ACTION,
5706 "Doesn't support optional "
5710 if (attr->ingress && !attr->transfer) {
5711 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5712 MLX5_FLOW_ACTION_RSS)))
5713 return rte_flow_error_set(error, EINVAL,
5714 RTE_FLOW_ERROR_TYPE_ACTION,
5716 "Ingress must has a dest "
5717 "QUEUE for Sample");
5718 } else if (attr->egress && !attr->transfer) {
5719 return rte_flow_error_set(error, ENOTSUP,
5720 RTE_FLOW_ERROR_TYPE_ACTION,
5722 "Sample Only support Ingress "
5724 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5725 MLX5_ASSERT(attr->transfer);
5726 if (sample->ratio > 1)
5727 return rte_flow_error_set(error, ENOTSUP,
5728 RTE_FLOW_ERROR_TYPE_ACTION,
5730 "E-Switch doesn't support "
5731 "any optional action "
5733 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5734 return rte_flow_error_set(error, ENOTSUP,
5735 RTE_FLOW_ERROR_TYPE_ACTION,
5737 "unsupported action QUEUE");
5738 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5739 return rte_flow_error_set(error, ENOTSUP,
5740 RTE_FLOW_ERROR_TYPE_ACTION,
5742 "unsupported action QUEUE");
5743 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5744 return rte_flow_error_set(error, EINVAL,
5745 RTE_FLOW_ERROR_TYPE_ACTION,
5747 "E-Switch must has a dest "
5748 "port for mirroring");
5749 if (!priv->config.hca_attr.reg_c_preserve &&
5750 priv->representor_id != UINT16_MAX)
5751 *fdb_mirror_limit = 1;
5753 /* Continue validation for Xcap actions.*/
5754 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5755 (queue_index == 0xFFFF ||
5756 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5757 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5758 MLX5_FLOW_XCAP_ACTIONS)
5759 return rte_flow_error_set(error, ENOTSUP,
5760 RTE_FLOW_ERROR_TYPE_ACTION,
5761 NULL, "encap and decap "
5762 "combination aren't "
5764 if (!attr->transfer && attr->ingress && (sub_action_flags &
5765 MLX5_FLOW_ACTION_ENCAP))
5766 return rte_flow_error_set(error, ENOTSUP,
5767 RTE_FLOW_ERROR_TYPE_ACTION,
5768 NULL, "encap is not supported"
5769 " for ingress traffic");
5775 * Find existing modify-header resource or create and register a new one.
5777 * @param dev[in, out]
5778 * Pointer to rte_eth_dev structure.
5779 * @param[in, out] resource
5780 * Pointer to modify-header resource.
5781 * @parm[in, out] dev_flow
5782 * Pointer to the dev_flow.
5784 * pointer to error structure.
5787 * 0 on success otherwise -errno and errno is set.
5790 flow_dv_modify_hdr_resource_register
5791 (struct rte_eth_dev *dev,
5792 struct mlx5_flow_dv_modify_hdr_resource *resource,
5793 struct mlx5_flow *dev_flow,
5794 struct rte_flow_error *error)
5796 struct mlx5_priv *priv = dev->data->dev_private;
5797 struct mlx5_dev_ctx_shared *sh = priv->sh;
5798 uint32_t key_len = sizeof(*resource) -
5799 offsetof(typeof(*resource), ft_type) +
5800 resource->actions_num * sizeof(resource->actions[0]);
5801 struct mlx5_list_entry *entry;
5802 struct mlx5_flow_cb_ctx ctx = {
5806 struct mlx5_hlist *modify_cmds;
5809 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5811 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5813 flow_dv_modify_create_cb,
5814 flow_dv_modify_match_cb,
5815 flow_dv_modify_remove_cb,
5816 flow_dv_modify_clone_cb,
5817 flow_dv_modify_clone_free_cb);
5818 if (unlikely(!modify_cmds))
5820 resource->root = !dev_flow->dv.group;
5821 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5823 return rte_flow_error_set(error, EOVERFLOW,
5824 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5825 "too many modify header items");
5826 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5827 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5830 resource = container_of(entry, typeof(*resource), entry);
5831 dev_flow->handle->dvh.modify_hdr = resource;
5836 * Get DV flow counter by index.
5839 * Pointer to the Ethernet device structure.
5841 * mlx5 flow counter index in the container.
5843 * mlx5 flow counter pool in the container.
5846 * Pointer to the counter, NULL otherwise.
5848 static struct mlx5_flow_counter *
5849 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5851 struct mlx5_flow_counter_pool **ppool)
5853 struct mlx5_priv *priv = dev->data->dev_private;
5854 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5855 struct mlx5_flow_counter_pool *pool;
5857 /* Decrease to original index and clear shared bit. */
5858 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5859 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5860 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5864 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5868 * Check the devx counter belongs to the pool.
5871 * Pointer to the counter pool.
5873 * The counter devx ID.
5876 * True if counter belongs to the pool, false otherwise.
5879 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5881 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5882 MLX5_COUNTERS_PER_POOL;
5884 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5890 * Get a pool by devx counter ID.
5893 * Pointer to the counter management.
5895 * The counter devx ID.
5898 * The counter pool pointer if exists, NULL otherwise,
5900 static struct mlx5_flow_counter_pool *
5901 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5904 struct mlx5_flow_counter_pool *pool = NULL;
5906 rte_spinlock_lock(&cmng->pool_update_sl);
5907 /* Check last used pool. */
5908 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5909 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5910 pool = cmng->pools[cmng->last_pool_idx];
5913 /* ID out of range means no suitable pool in the container. */
5914 if (id > cmng->max_id || id < cmng->min_id)
5917 * Find the pool from the end of the container, since mostly counter
5918 * ID is sequence increasing, and the last pool should be the needed
5923 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5925 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5931 rte_spinlock_unlock(&cmng->pool_update_sl);
5936 * Resize a counter container.
5939 * Pointer to the Ethernet device structure.
5942 * 0 on success, otherwise negative errno value and rte_errno is set.
5945 flow_dv_container_resize(struct rte_eth_dev *dev)
5947 struct mlx5_priv *priv = dev->data->dev_private;
5948 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5949 void *old_pools = cmng->pools;
5950 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5951 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5952 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5959 memcpy(pools, old_pools, cmng->n *
5960 sizeof(struct mlx5_flow_counter_pool *));
5962 cmng->pools = pools;
5964 mlx5_free(old_pools);
5969 * Query a devx flow counter.
5972 * Pointer to the Ethernet device structure.
5973 * @param[in] counter
5974 * Index to the flow counter.
5976 * The statistics value of packets.
5978 * The statistics value of bytes.
5981 * 0 on success, otherwise a negative errno value and rte_errno is set.
5984 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5987 struct mlx5_priv *priv = dev->data->dev_private;
5988 struct mlx5_flow_counter_pool *pool = NULL;
5989 struct mlx5_flow_counter *cnt;
5992 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5994 if (priv->sh->cmng.counter_fallback)
5995 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5996 0, pkts, bytes, 0, NULL, NULL, 0);
5997 rte_spinlock_lock(&pool->sl);
6002 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6003 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6004 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6006 rte_spinlock_unlock(&pool->sl);
6011 * Create and initialize a new counter pool.
6014 * Pointer to the Ethernet device structure.
6016 * The devX counter handle.
6018 * Whether the pool is for counter that was allocated for aging.
6019 * @param[in/out] cont_cur
6020 * Pointer to the container pointer, it will be update in pool resize.
6023 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6025 static struct mlx5_flow_counter_pool *
6026 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6029 struct mlx5_priv *priv = dev->data->dev_private;
6030 struct mlx5_flow_counter_pool *pool;
6031 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6032 bool fallback = priv->sh->cmng.counter_fallback;
6033 uint32_t size = sizeof(*pool);
6035 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6036 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6037 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6043 pool->is_aged = !!age;
6044 pool->query_gen = 0;
6045 pool->min_dcs = dcs;
6046 rte_spinlock_init(&pool->sl);
6047 rte_spinlock_init(&pool->csl);
6048 TAILQ_INIT(&pool->counters[0]);
6049 TAILQ_INIT(&pool->counters[1]);
6050 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6051 rte_spinlock_lock(&cmng->pool_update_sl);
6052 pool->index = cmng->n_valid;
6053 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6055 rte_spinlock_unlock(&cmng->pool_update_sl);
6058 cmng->pools[pool->index] = pool;
6060 if (unlikely(fallback)) {
6061 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6063 if (base < cmng->min_id)
6064 cmng->min_id = base;
6065 if (base > cmng->max_id)
6066 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6067 cmng->last_pool_idx = pool->index;
6069 rte_spinlock_unlock(&cmng->pool_update_sl);
6074 * Prepare a new counter and/or a new counter pool.
6077 * Pointer to the Ethernet device structure.
6078 * @param[out] cnt_free
6079 * Where to put the pointer of a new counter.
6081 * Whether the pool is for counter that was allocated for aging.
6084 * The counter pool pointer and @p cnt_free is set on success,
6085 * NULL otherwise and rte_errno is set.
6087 static struct mlx5_flow_counter_pool *
6088 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6089 struct mlx5_flow_counter **cnt_free,
6092 struct mlx5_priv *priv = dev->data->dev_private;
6093 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6094 struct mlx5_flow_counter_pool *pool;
6095 struct mlx5_counters tmp_tq;
6096 struct mlx5_devx_obj *dcs = NULL;
6097 struct mlx5_flow_counter *cnt;
6098 enum mlx5_counter_type cnt_type =
6099 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6100 bool fallback = priv->sh->cmng.counter_fallback;
6104 /* bulk_bitmap must be 0 for single counter allocation. */
6105 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
6108 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6110 pool = flow_dv_pool_create(dev, dcs, age);
6112 mlx5_devx_cmd_destroy(dcs);
6116 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6117 cnt = MLX5_POOL_GET_CNT(pool, i);
6119 cnt->dcs_when_free = dcs;
6123 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
6125 rte_errno = ENODATA;
6128 pool = flow_dv_pool_create(dev, dcs, age);
6130 mlx5_devx_cmd_destroy(dcs);
6133 TAILQ_INIT(&tmp_tq);
6134 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6135 cnt = MLX5_POOL_GET_CNT(pool, i);
6137 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6139 rte_spinlock_lock(&cmng->csl[cnt_type]);
6140 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6141 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6142 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6143 (*cnt_free)->pool = pool;
6148 * Allocate a flow counter.
6151 * Pointer to the Ethernet device structure.
6153 * Whether the counter was allocated for aging.
6156 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6159 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6161 struct mlx5_priv *priv = dev->data->dev_private;
6162 struct mlx5_flow_counter_pool *pool = NULL;
6163 struct mlx5_flow_counter *cnt_free = NULL;
6164 bool fallback = priv->sh->cmng.counter_fallback;
6165 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6166 enum mlx5_counter_type cnt_type =
6167 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6170 if (!priv->config.devx) {
6171 rte_errno = ENOTSUP;
6174 /* Get free counters from container. */
6175 rte_spinlock_lock(&cmng->csl[cnt_type]);
6176 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6178 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6179 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6180 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6182 pool = cnt_free->pool;
6184 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6185 /* Create a DV counter action only in the first time usage. */
6186 if (!cnt_free->action) {
6188 struct mlx5_devx_obj *dcs;
6192 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6193 dcs = pool->min_dcs;
6196 dcs = cnt_free->dcs_when_free;
6198 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6205 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6206 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6207 /* Update the counter reset values. */
6208 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6211 if (!fallback && !priv->sh->cmng.query_thread_on)
6212 /* Start the asynchronous batch query by the host thread. */
6213 mlx5_set_query_alarm(priv->sh);
6215 * When the count action isn't shared (by ID), shared_info field is
6216 * used for indirect action API's refcnt.
6217 * When the counter action is not shared neither by ID nor by indirect
6218 * action API, shared info must be 1.
6220 cnt_free->shared_info.refcnt = 1;
6224 cnt_free->pool = pool;
6226 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6227 rte_spinlock_lock(&cmng->csl[cnt_type]);
6228 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6229 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6235 * Allocate a shared flow counter.
6238 * Pointer to the shared counter configuration.
6240 * Pointer to save the allocated counter index.
6243 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6247 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
6249 struct mlx5_shared_counter_conf *conf = ctx;
6250 struct rte_eth_dev *dev = conf->dev;
6251 struct mlx5_flow_counter *cnt;
6253 data->dword = flow_dv_counter_alloc(dev, 0);
6254 data->dword |= MLX5_CNT_SHARED_OFFSET;
6255 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
6256 cnt->shared_info.id = conf->id;
6261 * Get a shared flow counter.
6264 * Pointer to the Ethernet device structure.
6266 * Counter identifier.
6269 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6272 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
6274 struct mlx5_priv *priv = dev->data->dev_private;
6275 struct mlx5_shared_counter_conf conf = {
6279 union mlx5_l3t_data data = {
6283 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
6284 flow_dv_counter_alloc_shared_cb, &conf);
6289 * Get age param from counter index.
6292 * Pointer to the Ethernet device structure.
6293 * @param[in] counter
6294 * Index to the counter handler.
6297 * The aging parameter specified for the counter index.
6299 static struct mlx5_age_param*
6300 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6303 struct mlx5_flow_counter *cnt;
6304 struct mlx5_flow_counter_pool *pool = NULL;
6306 flow_dv_counter_get_by_idx(dev, counter, &pool);
6307 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6308 cnt = MLX5_POOL_GET_CNT(pool, counter);
6309 return MLX5_CNT_TO_AGE(cnt);
6313 * Remove a flow counter from aged counter list.
6316 * Pointer to the Ethernet device structure.
6317 * @param[in] counter
6318 * Index to the counter handler.
6320 * Pointer to the counter handler.
6323 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6324 uint32_t counter, struct mlx5_flow_counter *cnt)
6326 struct mlx5_age_info *age_info;
6327 struct mlx5_age_param *age_param;
6328 struct mlx5_priv *priv = dev->data->dev_private;
6329 uint16_t expected = AGE_CANDIDATE;
6331 age_info = GET_PORT_AGE_INFO(priv);
6332 age_param = flow_dv_counter_idx_get_age(dev, counter);
6333 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6334 AGE_FREE, false, __ATOMIC_RELAXED,
6335 __ATOMIC_RELAXED)) {
6337 * We need the lock even it is age timeout,
6338 * since counter may still in process.
6340 rte_spinlock_lock(&age_info->aged_sl);
6341 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6342 rte_spinlock_unlock(&age_info->aged_sl);
6343 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6348 * Release a flow counter.
6351 * Pointer to the Ethernet device structure.
6352 * @param[in] counter
6353 * Index to the counter handler.
6356 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6358 struct mlx5_priv *priv = dev->data->dev_private;
6359 struct mlx5_flow_counter_pool *pool = NULL;
6360 struct mlx5_flow_counter *cnt;
6361 enum mlx5_counter_type cnt_type;
6365 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6367 if (pool->is_aged) {
6368 flow_dv_counter_remove_from_age(dev, counter, cnt);
6371 * If the counter action is shared by ID, the l3t_clear_entry
6372 * function reduces its references counter. If after the
6373 * reduction the action is still referenced, the function
6374 * returns here and does not release it.
6376 if (IS_LEGACY_SHARED_CNT(counter) &&
6377 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
6378 cnt->shared_info.id))
6381 * If the counter action is shared by indirect action API,
6382 * the atomic function reduces its references counter.
6383 * If after the reduction the action is still referenced, the
6384 * function returns here and does not release it.
6385 * When the counter action is not shared neither by ID nor by
6386 * indirect action API, shared info is 1 before the reduction,
6387 * so this condition is failed and function doesn't return here.
6389 if (!IS_LEGACY_SHARED_CNT(counter) &&
6390 __atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6396 * Put the counter back to list to be updated in none fallback mode.
6397 * Currently, we are using two list alternately, while one is in query,
6398 * add the freed counter to the other list based on the pool query_gen
6399 * value. After query finishes, add counter the list to the global
6400 * container counter list. The list changes while query starts. In
6401 * this case, lock will not be needed as query callback and release
6402 * function both operate with the different list.
6404 if (!priv->sh->cmng.counter_fallback) {
6405 rte_spinlock_lock(&pool->csl);
6406 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6407 rte_spinlock_unlock(&pool->csl);
6409 cnt->dcs_when_free = cnt->dcs_when_active;
6410 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6411 MLX5_COUNTER_TYPE_ORIGIN;
6412 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6413 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6415 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6420 * Resize a meter id container.
6423 * Pointer to the Ethernet device structure.
6426 * 0 on success, otherwise negative errno value and rte_errno is set.
6429 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6431 struct mlx5_priv *priv = dev->data->dev_private;
6432 struct mlx5_aso_mtr_pools_mng *pools_mng =
6433 &priv->sh->mtrmng->pools_mng;
6434 void *old_pools = pools_mng->pools;
6435 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6436 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6437 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6444 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6449 memcpy(pools, old_pools, pools_mng->n *
6450 sizeof(struct mlx5_aso_mtr_pool *));
6451 pools_mng->n = resize;
6452 pools_mng->pools = pools;
6454 mlx5_free(old_pools);
6459 * Prepare a new meter and/or a new meter pool.
6462 * Pointer to the Ethernet device structure.
6463 * @param[out] mtr_free
6464 * Where to put the pointer of a new meter.g.
6467 * The meter pool pointer and @mtr_free is set on success,
6468 * NULL otherwise and rte_errno is set.
6470 static struct mlx5_aso_mtr_pool *
6471 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
6472 struct mlx5_aso_mtr **mtr_free)
6474 struct mlx5_priv *priv = dev->data->dev_private;
6475 struct mlx5_aso_mtr_pools_mng *pools_mng =
6476 &priv->sh->mtrmng->pools_mng;
6477 struct mlx5_aso_mtr_pool *pool = NULL;
6478 struct mlx5_devx_obj *dcs = NULL;
6480 uint32_t log_obj_size;
6482 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6483 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6484 priv->sh->pdn, log_obj_size);
6486 rte_errno = ENODATA;
6489 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6492 claim_zero(mlx5_devx_cmd_destroy(dcs));
6495 pool->devx_obj = dcs;
6496 pool->index = pools_mng->n_valid;
6497 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6499 claim_zero(mlx5_devx_cmd_destroy(dcs));
6502 pools_mng->pools[pool->index] = pool;
6503 pools_mng->n_valid++;
6504 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6505 pool->mtrs[i].offset = i;
6506 LIST_INSERT_HEAD(&pools_mng->meters,
6507 &pool->mtrs[i], next);
6509 pool->mtrs[0].offset = 0;
6510 *mtr_free = &pool->mtrs[0];
6515 * Release a flow meter into pool.
6518 * Pointer to the Ethernet device structure.
6519 * @param[in] mtr_idx
6520 * Index to aso flow meter.
6523 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6525 struct mlx5_priv *priv = dev->data->dev_private;
6526 struct mlx5_aso_mtr_pools_mng *pools_mng =
6527 &priv->sh->mtrmng->pools_mng;
6528 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6530 MLX5_ASSERT(aso_mtr);
6531 rte_spinlock_lock(&pools_mng->mtrsl);
6532 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6533 aso_mtr->state = ASO_METER_FREE;
6534 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6535 rte_spinlock_unlock(&pools_mng->mtrsl);
6539 * Allocate a aso flow meter.
6542 * Pointer to the Ethernet device structure.
6545 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6548 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6550 struct mlx5_priv *priv = dev->data->dev_private;
6551 struct mlx5_aso_mtr *mtr_free = NULL;
6552 struct mlx5_aso_mtr_pools_mng *pools_mng =
6553 &priv->sh->mtrmng->pools_mng;
6554 struct mlx5_aso_mtr_pool *pool;
6555 uint32_t mtr_idx = 0;
6557 if (!priv->config.devx) {
6558 rte_errno = ENOTSUP;
6561 /* Allocate the flow meter memory. */
6562 /* Get free meters from management. */
6563 rte_spinlock_lock(&pools_mng->mtrsl);
6564 mtr_free = LIST_FIRST(&pools_mng->meters);
6566 LIST_REMOVE(mtr_free, next);
6567 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6568 rte_spinlock_unlock(&pools_mng->mtrsl);
6571 mtr_free->state = ASO_METER_WAIT;
6572 rte_spinlock_unlock(&pools_mng->mtrsl);
6573 pool = container_of(mtr_free,
6574 struct mlx5_aso_mtr_pool,
6575 mtrs[mtr_free->offset]);
6576 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6577 if (!mtr_free->fm.meter_action) {
6578 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6579 struct rte_flow_error error;
6582 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6583 mtr_free->fm.meter_action =
6584 mlx5_glue->dv_create_flow_action_aso
6585 (priv->sh->rx_domain,
6586 pool->devx_obj->obj,
6588 (1 << MLX5_FLOW_COLOR_GREEN),
6590 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6591 if (!mtr_free->fm.meter_action) {
6592 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6600 * Verify the @p attributes will be correctly understood by the NIC and store
6601 * them in the @p flow if everything is correct.
6604 * Pointer to dev struct.
6605 * @param[in] attributes
6606 * Pointer to flow attributes
6607 * @param[in] external
6608 * This flow rule is created by request external to PMD.
6610 * Pointer to error structure.
6613 * - 0 on success and non root table.
6614 * - 1 on success and root table.
6615 * - a negative errno value otherwise and rte_errno is set.
6618 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6619 const struct mlx5_flow_tunnel *tunnel,
6620 const struct rte_flow_attr *attributes,
6621 const struct flow_grp_info *grp_info,
6622 struct rte_flow_error *error)
6624 struct mlx5_priv *priv = dev->data->dev_private;
6625 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6628 #ifndef HAVE_MLX5DV_DR
6629 RTE_SET_USED(tunnel);
6630 RTE_SET_USED(grp_info);
6631 if (attributes->group)
6632 return rte_flow_error_set(error, ENOTSUP,
6633 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6635 "groups are not supported");
6639 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6644 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6646 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6647 attributes->priority > lowest_priority)
6648 return rte_flow_error_set(error, ENOTSUP,
6649 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6651 "priority out of range");
6652 if (attributes->transfer) {
6653 if (!priv->config.dv_esw_en)
6654 return rte_flow_error_set
6656 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6657 "E-Switch dr is not supported");
6658 if (!(priv->representor || priv->master))
6659 return rte_flow_error_set
6660 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6661 NULL, "E-Switch configuration can only be"
6662 " done by a master or a representor device");
6663 if (attributes->egress)
6664 return rte_flow_error_set
6666 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6667 "egress is not supported");
6669 if (!(attributes->egress ^ attributes->ingress))
6670 return rte_flow_error_set(error, ENOTSUP,
6671 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6672 "must specify exactly one of "
6673 "ingress or egress");
6678 mlx5_flow_locate_proto_l3(const struct rte_flow_item **head,
6679 const struct rte_flow_item *end)
6681 const struct rte_flow_item *item = *head;
6682 uint16_t l3_protocol;
6684 for (; item != end; item++) {
6685 switch (item->type) {
6688 case RTE_FLOW_ITEM_TYPE_IPV4:
6689 l3_protocol = RTE_ETHER_TYPE_IPV4;
6691 case RTE_FLOW_ITEM_TYPE_IPV6:
6692 l3_protocol = RTE_ETHER_TYPE_IPV6;
6694 case RTE_FLOW_ITEM_TYPE_ETH:
6695 if (item->mask && item->spec) {
6696 MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_eth,
6699 if (l3_protocol == RTE_ETHER_TYPE_IPV4 ||
6700 l3_protocol == RTE_ETHER_TYPE_IPV6)
6704 case RTE_FLOW_ITEM_TYPE_VLAN:
6705 if (item->mask && item->spec) {
6706 MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_vlan,
6709 if (l3_protocol == RTE_ETHER_TYPE_IPV4 ||
6710 l3_protocol == RTE_ETHER_TYPE_IPV6)
6723 mlx5_flow_locate_proto_l4(const struct rte_flow_item **head,
6724 const struct rte_flow_item *end)
6726 const struct rte_flow_item *item = *head;
6727 uint8_t l4_protocol;
6729 for (; item != end; item++) {
6730 switch (item->type) {
6733 case RTE_FLOW_ITEM_TYPE_TCP:
6734 l4_protocol = IPPROTO_TCP;
6736 case RTE_FLOW_ITEM_TYPE_UDP:
6737 l4_protocol = IPPROTO_UDP;
6739 case RTE_FLOW_ITEM_TYPE_IPV4:
6740 if (item->mask && item->spec) {
6741 const struct rte_flow_item_ipv4 *mask, *spec;
6743 mask = (typeof(mask))item->mask;
6744 spec = (typeof(spec))item->spec;
6745 l4_protocol = mask->hdr.next_proto_id &
6746 spec->hdr.next_proto_id;
6747 if (l4_protocol == IPPROTO_TCP ||
6748 l4_protocol == IPPROTO_UDP)
6752 case RTE_FLOW_ITEM_TYPE_IPV6:
6753 if (item->mask && item->spec) {
6754 const struct rte_flow_item_ipv6 *mask, *spec;
6755 mask = (typeof(mask))item->mask;
6756 spec = (typeof(spec))item->spec;
6757 l4_protocol = mask->hdr.proto & spec->hdr.proto;
6758 if (l4_protocol == IPPROTO_TCP ||
6759 l4_protocol == IPPROTO_UDP)
6772 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6773 const struct rte_flow_item *rule_items,
6774 const struct rte_flow_item *integrity_item,
6775 struct rte_flow_error *error)
6777 struct mlx5_priv *priv = dev->data->dev_private;
6778 const struct rte_flow_item *tunnel_item, *end_item, *item = rule_items;
6779 const struct rte_flow_item_integrity *mask = (typeof(mask))
6780 integrity_item->mask;
6781 const struct rte_flow_item_integrity *spec = (typeof(spec))
6782 integrity_item->spec;
6785 if (!priv->config.hca_attr.pkt_integrity_match)
6786 return rte_flow_error_set(error, ENOTSUP,
6787 RTE_FLOW_ERROR_TYPE_ITEM,
6789 "packet integrity integrity_item not supported");
6791 mask = &rte_flow_item_integrity_mask;
6792 if (!mlx5_validate_integrity_item(mask))
6793 return rte_flow_error_set(error, ENOTSUP,
6794 RTE_FLOW_ERROR_TYPE_ITEM,
6796 "unsupported integrity filter");
6797 tunnel_item = mlx5_flow_find_tunnel_item(rule_items);
6798 if (spec->level > 1) {
6800 return rte_flow_error_set(error, ENOTSUP,
6801 RTE_FLOW_ERROR_TYPE_ITEM,
6803 "missing tunnel item");
6805 end_item = mlx5_find_end_item(tunnel_item);
6807 end_item = tunnel_item ? tunnel_item :
6808 mlx5_find_end_item(integrity_item);
6810 if (mask->l3_ok || mask->ipv4_csum_ok) {
6811 protocol = mlx5_flow_locate_proto_l3(&item, end_item);
6813 return rte_flow_error_set(error, EINVAL,
6814 RTE_FLOW_ERROR_TYPE_ITEM,
6816 "missing L3 protocol");
6818 if (mask->l4_ok || mask->l4_csum_ok) {
6819 protocol = mlx5_flow_locate_proto_l4(&item, end_item);
6821 return rte_flow_error_set(error, EINVAL,
6822 RTE_FLOW_ERROR_TYPE_ITEM,
6824 "missing L4 protocol");
6830 * Internal validation function. For validating both actions and items.
6833 * Pointer to the rte_eth_dev structure.
6835 * Pointer to the flow attributes.
6837 * Pointer to the list of items.
6838 * @param[in] actions
6839 * Pointer to the list of actions.
6840 * @param[in] external
6841 * This flow rule is created by request external to PMD.
6842 * @param[in] hairpin
6843 * Number of hairpin TX actions, 0 means classic flow.
6845 * Pointer to the error structure.
6848 * 0 on success, a negative errno value otherwise and rte_errno is set.
6851 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6852 const struct rte_flow_item items[],
6853 const struct rte_flow_action actions[],
6854 bool external, int hairpin, struct rte_flow_error *error)
6857 uint64_t action_flags = 0;
6858 uint64_t item_flags = 0;
6859 uint64_t last_item = 0;
6860 uint8_t next_protocol = 0xff;
6861 uint16_t ether_type = 0;
6863 uint8_t item_ipv6_proto = 0;
6864 int fdb_mirror_limit = 0;
6865 int modify_after_mirror = 0;
6866 const struct rte_flow_item *geneve_item = NULL;
6867 const struct rte_flow_item *gre_item = NULL;
6868 const struct rte_flow_item *gtp_item = NULL;
6869 const struct rte_flow_action_raw_decap *decap;
6870 const struct rte_flow_action_raw_encap *encap;
6871 const struct rte_flow_action_rss *rss = NULL;
6872 const struct rte_flow_action_rss *sample_rss = NULL;
6873 const struct rte_flow_action_count *sample_count = NULL;
6874 const struct rte_flow_item_tcp nic_tcp_mask = {
6877 .src_port = RTE_BE16(UINT16_MAX),
6878 .dst_port = RTE_BE16(UINT16_MAX),
6881 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6884 "\xff\xff\xff\xff\xff\xff\xff\xff"
6885 "\xff\xff\xff\xff\xff\xff\xff\xff",
6887 "\xff\xff\xff\xff\xff\xff\xff\xff"
6888 "\xff\xff\xff\xff\xff\xff\xff\xff",
6889 .vtc_flow = RTE_BE32(0xffffffff),
6895 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6899 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6903 .dummy[0] = 0xffffffff,
6906 struct mlx5_priv *priv = dev->data->dev_private;
6907 struct mlx5_dev_config *dev_conf = &priv->config;
6908 uint16_t queue_index = 0xFFFF;
6909 const struct rte_flow_item_vlan *vlan_m = NULL;
6910 uint32_t rw_act_num = 0;
6912 const struct mlx5_flow_tunnel *tunnel;
6913 enum mlx5_tof_rule_type tof_rule_type;
6914 struct flow_grp_info grp_info = {
6915 .external = !!external,
6916 .transfer = !!attr->transfer,
6917 .fdb_def_rule = !!priv->fdb_def_rule,
6918 .std_tbl_fix = true,
6920 const struct rte_eth_hairpin_conf *conf;
6921 const struct rte_flow_item *rule_items = items;
6922 const struct rte_flow_item *port_id_item = NULL;
6923 bool def_policy = false;
6927 tunnel = is_tunnel_offload_active(dev) ?
6928 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6930 if (priv->representor)
6931 return rte_flow_error_set
6933 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6934 NULL, "decap not supported for VF representor");
6935 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6936 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6937 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6938 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6939 MLX5_FLOW_ACTION_DECAP;
6940 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6941 (dev, attr, tunnel, tof_rule_type);
6943 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6946 is_root = (uint64_t)ret;
6947 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6948 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6949 int type = items->type;
6951 if (!mlx5_flow_os_item_supported(type))
6952 return rte_flow_error_set(error, ENOTSUP,
6953 RTE_FLOW_ERROR_TYPE_ITEM,
6954 NULL, "item not supported");
6956 case RTE_FLOW_ITEM_TYPE_VOID:
6958 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6959 ret = flow_dv_validate_item_port_id
6960 (dev, items, attr, item_flags, error);
6963 last_item = MLX5_FLOW_ITEM_PORT_ID;
6964 port_id_item = items;
6966 case RTE_FLOW_ITEM_TYPE_ETH:
6967 ret = mlx5_flow_validate_item_eth(items, item_flags,
6971 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6972 MLX5_FLOW_LAYER_OUTER_L2;
6973 if (items->mask != NULL && items->spec != NULL) {
6975 ((const struct rte_flow_item_eth *)
6978 ((const struct rte_flow_item_eth *)
6980 ether_type = rte_be_to_cpu_16(ether_type);
6985 case RTE_FLOW_ITEM_TYPE_VLAN:
6986 ret = flow_dv_validate_item_vlan(items, item_flags,
6990 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6991 MLX5_FLOW_LAYER_OUTER_VLAN;
6992 if (items->mask != NULL && items->spec != NULL) {
6994 ((const struct rte_flow_item_vlan *)
6995 items->spec)->inner_type;
6997 ((const struct rte_flow_item_vlan *)
6998 items->mask)->inner_type;
6999 ether_type = rte_be_to_cpu_16(ether_type);
7003 /* Store outer VLAN mask for of_push_vlan action. */
7005 vlan_m = items->mask;
7007 case RTE_FLOW_ITEM_TYPE_IPV4:
7008 mlx5_flow_tunnel_ip_check(items, next_protocol,
7009 &item_flags, &tunnel);
7010 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
7011 last_item, ether_type,
7015 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7016 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7017 if (items->mask != NULL &&
7018 ((const struct rte_flow_item_ipv4 *)
7019 items->mask)->hdr.next_proto_id) {
7021 ((const struct rte_flow_item_ipv4 *)
7022 (items->spec))->hdr.next_proto_id;
7024 ((const struct rte_flow_item_ipv4 *)
7025 (items->mask))->hdr.next_proto_id;
7027 /* Reset for inner layer. */
7028 next_protocol = 0xff;
7031 case RTE_FLOW_ITEM_TYPE_IPV6:
7032 mlx5_flow_tunnel_ip_check(items, next_protocol,
7033 &item_flags, &tunnel);
7034 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7041 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7042 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7043 if (items->mask != NULL &&
7044 ((const struct rte_flow_item_ipv6 *)
7045 items->mask)->hdr.proto) {
7047 ((const struct rte_flow_item_ipv6 *)
7048 items->spec)->hdr.proto;
7050 ((const struct rte_flow_item_ipv6 *)
7051 items->spec)->hdr.proto;
7053 ((const struct rte_flow_item_ipv6 *)
7054 items->mask)->hdr.proto;
7056 /* Reset for inner layer. */
7057 next_protocol = 0xff;
7060 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7061 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7066 last_item = tunnel ?
7067 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7068 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7069 if (items->mask != NULL &&
7070 ((const struct rte_flow_item_ipv6_frag_ext *)
7071 items->mask)->hdr.next_header) {
7073 ((const struct rte_flow_item_ipv6_frag_ext *)
7074 items->spec)->hdr.next_header;
7076 ((const struct rte_flow_item_ipv6_frag_ext *)
7077 items->mask)->hdr.next_header;
7079 /* Reset for inner layer. */
7080 next_protocol = 0xff;
7083 case RTE_FLOW_ITEM_TYPE_TCP:
7084 ret = mlx5_flow_validate_item_tcp
7091 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7092 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7094 case RTE_FLOW_ITEM_TYPE_UDP:
7095 ret = mlx5_flow_validate_item_udp(items, item_flags,
7100 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7101 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7103 case RTE_FLOW_ITEM_TYPE_GRE:
7104 ret = mlx5_flow_validate_item_gre(items, item_flags,
7105 next_protocol, error);
7109 last_item = MLX5_FLOW_LAYER_GRE;
7111 case RTE_FLOW_ITEM_TYPE_NVGRE:
7112 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7117 last_item = MLX5_FLOW_LAYER_NVGRE;
7119 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7120 ret = mlx5_flow_validate_item_gre_key
7121 (items, item_flags, gre_item, error);
7124 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7126 case RTE_FLOW_ITEM_TYPE_VXLAN:
7127 ret = mlx5_flow_validate_item_vxlan(dev, items,
7132 last_item = MLX5_FLOW_LAYER_VXLAN;
7134 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7135 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7140 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7142 case RTE_FLOW_ITEM_TYPE_GENEVE:
7143 ret = mlx5_flow_validate_item_geneve(items,
7148 geneve_item = items;
7149 last_item = MLX5_FLOW_LAYER_GENEVE;
7151 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7152 ret = mlx5_flow_validate_item_geneve_opt(items,
7159 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7161 case RTE_FLOW_ITEM_TYPE_MPLS:
7162 ret = mlx5_flow_validate_item_mpls(dev, items,
7167 last_item = MLX5_FLOW_LAYER_MPLS;
7170 case RTE_FLOW_ITEM_TYPE_MARK:
7171 ret = flow_dv_validate_item_mark(dev, items, attr,
7175 last_item = MLX5_FLOW_ITEM_MARK;
7177 case RTE_FLOW_ITEM_TYPE_META:
7178 ret = flow_dv_validate_item_meta(dev, items, attr,
7182 last_item = MLX5_FLOW_ITEM_METADATA;
7184 case RTE_FLOW_ITEM_TYPE_ICMP:
7185 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7190 last_item = MLX5_FLOW_LAYER_ICMP;
7192 case RTE_FLOW_ITEM_TYPE_ICMP6:
7193 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7198 item_ipv6_proto = IPPROTO_ICMPV6;
7199 last_item = MLX5_FLOW_LAYER_ICMP6;
7201 case RTE_FLOW_ITEM_TYPE_TAG:
7202 ret = flow_dv_validate_item_tag(dev, items,
7206 last_item = MLX5_FLOW_ITEM_TAG;
7208 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7209 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7211 case RTE_FLOW_ITEM_TYPE_GTP:
7212 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7217 last_item = MLX5_FLOW_LAYER_GTP;
7219 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7220 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7225 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7227 case RTE_FLOW_ITEM_TYPE_ECPRI:
7228 /* Capacity will be checked in the translate stage. */
7229 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7236 last_item = MLX5_FLOW_LAYER_ECPRI;
7238 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7239 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY)
7240 return rte_flow_error_set
7242 RTE_FLOW_ERROR_TYPE_ITEM,
7243 NULL, "multiple integrity items not supported");
7244 ret = flow_dv_validate_item_integrity(dev, rule_items,
7248 last_item = MLX5_FLOW_ITEM_INTEGRITY;
7250 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7251 ret = flow_dv_validate_item_aso_ct(dev, items,
7252 &item_flags, error);
7256 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7257 /* tunnel offload item was processed before
7258 * list it here as a supported type
7262 return rte_flow_error_set(error, ENOTSUP,
7263 RTE_FLOW_ERROR_TYPE_ITEM,
7264 NULL, "item not supported");
7266 item_flags |= last_item;
7268 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7269 int type = actions->type;
7270 bool shared_count = false;
7272 if (!mlx5_flow_os_action_supported(type))
7273 return rte_flow_error_set(error, ENOTSUP,
7274 RTE_FLOW_ERROR_TYPE_ACTION,
7276 "action not supported");
7277 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7278 return rte_flow_error_set(error, ENOTSUP,
7279 RTE_FLOW_ERROR_TYPE_ACTION,
7280 actions, "too many actions");
7282 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7283 return rte_flow_error_set(error, ENOTSUP,
7284 RTE_FLOW_ERROR_TYPE_ACTION,
7285 NULL, "meter action with policy "
7286 "must be the last action");
7288 case RTE_FLOW_ACTION_TYPE_VOID:
7290 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7291 ret = flow_dv_validate_action_port_id(dev,
7298 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7301 case RTE_FLOW_ACTION_TYPE_FLAG:
7302 ret = flow_dv_validate_action_flag(dev, action_flags,
7306 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7307 /* Count all modify-header actions as one. */
7308 if (!(action_flags &
7309 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7311 action_flags |= MLX5_FLOW_ACTION_FLAG |
7312 MLX5_FLOW_ACTION_MARK_EXT;
7313 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7314 modify_after_mirror = 1;
7317 action_flags |= MLX5_FLOW_ACTION_FLAG;
7320 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7322 case RTE_FLOW_ACTION_TYPE_MARK:
7323 ret = flow_dv_validate_action_mark(dev, actions,
7328 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7329 /* Count all modify-header actions as one. */
7330 if (!(action_flags &
7331 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7333 action_flags |= MLX5_FLOW_ACTION_MARK |
7334 MLX5_FLOW_ACTION_MARK_EXT;
7335 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7336 modify_after_mirror = 1;
7338 action_flags |= MLX5_FLOW_ACTION_MARK;
7341 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7343 case RTE_FLOW_ACTION_TYPE_SET_META:
7344 ret = flow_dv_validate_action_set_meta(dev, actions,
7349 /* Count all modify-header actions as one action. */
7350 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7352 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7353 modify_after_mirror = 1;
7354 action_flags |= MLX5_FLOW_ACTION_SET_META;
7355 rw_act_num += MLX5_ACT_NUM_SET_META;
7357 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7358 ret = flow_dv_validate_action_set_tag(dev, actions,
7363 /* Count all modify-header actions as one action. */
7364 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7366 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7367 modify_after_mirror = 1;
7368 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7369 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7371 case RTE_FLOW_ACTION_TYPE_DROP:
7372 ret = mlx5_flow_validate_action_drop(action_flags,
7376 action_flags |= MLX5_FLOW_ACTION_DROP;
7379 case RTE_FLOW_ACTION_TYPE_QUEUE:
7380 ret = mlx5_flow_validate_action_queue(actions,
7385 queue_index = ((const struct rte_flow_action_queue *)
7386 (actions->conf))->index;
7387 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7390 case RTE_FLOW_ACTION_TYPE_RSS:
7391 rss = actions->conf;
7392 ret = mlx5_flow_validate_action_rss(actions,
7398 if (rss && sample_rss &&
7399 (sample_rss->level != rss->level ||
7400 sample_rss->types != rss->types))
7401 return rte_flow_error_set(error, ENOTSUP,
7402 RTE_FLOW_ERROR_TYPE_ACTION,
7404 "Can't use the different RSS types "
7405 "or level in the same flow");
7406 if (rss != NULL && rss->queue_num)
7407 queue_index = rss->queue[0];
7408 action_flags |= MLX5_FLOW_ACTION_RSS;
7411 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7413 mlx5_flow_validate_action_default_miss(action_flags,
7417 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7420 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7421 case RTE_FLOW_ACTION_TYPE_COUNT:
7422 shared_count = is_shared_action_count(actions);
7423 ret = flow_dv_validate_action_count(dev, shared_count,
7428 action_flags |= MLX5_FLOW_ACTION_COUNT;
7431 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7432 if (flow_dv_validate_action_pop_vlan(dev,
7438 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7439 modify_after_mirror = 1;
7440 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7443 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7444 ret = flow_dv_validate_action_push_vlan(dev,
7451 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7452 modify_after_mirror = 1;
7453 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7456 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7457 ret = flow_dv_validate_action_set_vlan_pcp
7458 (action_flags, actions, error);
7461 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7462 modify_after_mirror = 1;
7463 /* Count PCP with push_vlan command. */
7464 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7466 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7467 ret = flow_dv_validate_action_set_vlan_vid
7468 (item_flags, action_flags,
7472 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7473 modify_after_mirror = 1;
7474 /* Count VID with push_vlan command. */
7475 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7476 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7478 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7479 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7480 ret = flow_dv_validate_action_l2_encap(dev,
7486 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7489 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7490 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7491 ret = flow_dv_validate_action_decap(dev, action_flags,
7492 actions, item_flags,
7496 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7497 modify_after_mirror = 1;
7498 action_flags |= MLX5_FLOW_ACTION_DECAP;
7501 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7502 ret = flow_dv_validate_action_raw_encap_decap
7503 (dev, NULL, actions->conf, attr, &action_flags,
7504 &actions_n, actions, item_flags, error);
7508 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7509 decap = actions->conf;
7510 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7512 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7516 encap = actions->conf;
7518 ret = flow_dv_validate_action_raw_encap_decap
7520 decap ? decap : &empty_decap, encap,
7521 attr, &action_flags, &actions_n,
7522 actions, item_flags, error);
7525 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7526 (action_flags & MLX5_FLOW_ACTION_DECAP))
7527 modify_after_mirror = 1;
7529 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7530 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7531 ret = flow_dv_validate_action_modify_mac(action_flags,
7537 /* Count all modify-header actions as one action. */
7538 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7540 action_flags |= actions->type ==
7541 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7542 MLX5_FLOW_ACTION_SET_MAC_SRC :
7543 MLX5_FLOW_ACTION_SET_MAC_DST;
7544 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7545 modify_after_mirror = 1;
7547 * Even if the source and destination MAC addresses have
7548 * overlap in the header with 4B alignment, the convert
7549 * function will handle them separately and 4 SW actions
7550 * will be created. And 2 actions will be added each
7551 * time no matter how many bytes of address will be set.
7553 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7555 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7556 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7557 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7563 /* Count all modify-header actions as one action. */
7564 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7566 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7567 modify_after_mirror = 1;
7568 action_flags |= actions->type ==
7569 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7570 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7571 MLX5_FLOW_ACTION_SET_IPV4_DST;
7572 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7574 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7575 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7576 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7582 if (item_ipv6_proto == IPPROTO_ICMPV6)
7583 return rte_flow_error_set(error, ENOTSUP,
7584 RTE_FLOW_ERROR_TYPE_ACTION,
7586 "Can't change header "
7587 "with ICMPv6 proto");
7588 /* Count all modify-header actions as one action. */
7589 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7591 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7592 modify_after_mirror = 1;
7593 action_flags |= actions->type ==
7594 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7595 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7596 MLX5_FLOW_ACTION_SET_IPV6_DST;
7597 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7599 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7600 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7601 ret = flow_dv_validate_action_modify_tp(action_flags,
7607 /* Count all modify-header actions as one action. */
7608 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7610 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7611 modify_after_mirror = 1;
7612 action_flags |= actions->type ==
7613 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7614 MLX5_FLOW_ACTION_SET_TP_SRC :
7615 MLX5_FLOW_ACTION_SET_TP_DST;
7616 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7618 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7619 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7620 ret = flow_dv_validate_action_modify_ttl(action_flags,
7626 /* Count all modify-header actions as one action. */
7627 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7629 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7630 modify_after_mirror = 1;
7631 action_flags |= actions->type ==
7632 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7633 MLX5_FLOW_ACTION_SET_TTL :
7634 MLX5_FLOW_ACTION_DEC_TTL;
7635 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7637 case RTE_FLOW_ACTION_TYPE_JUMP:
7638 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7644 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7646 return rte_flow_error_set(error, EINVAL,
7647 RTE_FLOW_ERROR_TYPE_ACTION,
7649 "sample and jump action combination is not supported");
7651 action_flags |= MLX5_FLOW_ACTION_JUMP;
7653 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7654 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7655 ret = flow_dv_validate_action_modify_tcp_seq
7662 /* Count all modify-header actions as one action. */
7663 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7665 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7666 modify_after_mirror = 1;
7667 action_flags |= actions->type ==
7668 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7669 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7670 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7671 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7673 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7674 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7675 ret = flow_dv_validate_action_modify_tcp_ack
7682 /* Count all modify-header actions as one action. */
7683 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7685 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7686 modify_after_mirror = 1;
7687 action_flags |= actions->type ==
7688 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7689 MLX5_FLOW_ACTION_INC_TCP_ACK :
7690 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7691 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7693 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7695 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7696 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7697 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7699 case RTE_FLOW_ACTION_TYPE_METER:
7700 ret = mlx5_flow_validate_action_meter(dev,
7708 action_flags |= MLX5_FLOW_ACTION_METER;
7711 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7713 /* Meter action will add one more TAG action. */
7714 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7716 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7717 if (!attr->transfer && !attr->group)
7718 return rte_flow_error_set(error, ENOTSUP,
7719 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7721 "Shared ASO age action is not supported for group 0");
7722 if (action_flags & MLX5_FLOW_ACTION_AGE)
7723 return rte_flow_error_set
7725 RTE_FLOW_ERROR_TYPE_ACTION,
7727 "duplicate age actions set");
7728 action_flags |= MLX5_FLOW_ACTION_AGE;
7731 case RTE_FLOW_ACTION_TYPE_AGE:
7732 ret = flow_dv_validate_action_age(action_flags,
7738 * Validate the regular AGE action (using counter)
7739 * mutual exclusion with share counter actions.
7741 if (!priv->sh->flow_hit_aso_en) {
7743 return rte_flow_error_set
7745 RTE_FLOW_ERROR_TYPE_ACTION,
7747 "old age and shared count combination is not supported");
7749 return rte_flow_error_set
7751 RTE_FLOW_ERROR_TYPE_ACTION,
7753 "old age action and count must be in the same sub flow");
7755 action_flags |= MLX5_FLOW_ACTION_AGE;
7758 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7759 ret = flow_dv_validate_action_modify_ipv4_dscp
7766 /* Count all modify-header actions as one action. */
7767 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7769 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7770 modify_after_mirror = 1;
7771 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7772 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7774 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7775 ret = flow_dv_validate_action_modify_ipv6_dscp
7782 /* Count all modify-header actions as one action. */
7783 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7785 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7786 modify_after_mirror = 1;
7787 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7788 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7790 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7791 ret = flow_dv_validate_action_sample(&action_flags,
7800 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7803 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7804 ret = flow_dv_validate_action_modify_field(dev,
7811 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7812 modify_after_mirror = 1;
7813 /* Count all modify-header actions as one action. */
7814 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7816 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7819 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7820 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7825 action_flags |= MLX5_FLOW_ACTION_CT;
7827 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7828 /* tunnel offload action was processed before
7829 * list it here as a supported type
7833 return rte_flow_error_set(error, ENOTSUP,
7834 RTE_FLOW_ERROR_TYPE_ACTION,
7836 "action not supported");
7840 * Validate actions in flow rules
7841 * - Explicit decap action is prohibited by the tunnel offload API.
7842 * - Drop action in tunnel steer rule is prohibited by the API.
7843 * - Application cannot use MARK action because it's value can mask
7844 * tunnel default miss nitification.
7845 * - JUMP in tunnel match rule has no support in current PMD
7847 * - TAG & META are reserved for future uses.
7849 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7850 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7851 MLX5_FLOW_ACTION_MARK |
7852 MLX5_FLOW_ACTION_SET_TAG |
7853 MLX5_FLOW_ACTION_SET_META |
7854 MLX5_FLOW_ACTION_DROP;
7856 if (action_flags & bad_actions_mask)
7857 return rte_flow_error_set
7859 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7860 "Invalid RTE action in tunnel "
7862 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7863 return rte_flow_error_set
7865 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7866 "tunnel set decap rule must terminate "
7869 return rte_flow_error_set
7871 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7872 "tunnel flows for ingress traffic only");
7874 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7875 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7876 MLX5_FLOW_ACTION_MARK |
7877 MLX5_FLOW_ACTION_SET_TAG |
7878 MLX5_FLOW_ACTION_SET_META;
7880 if (action_flags & bad_actions_mask)
7881 return rte_flow_error_set
7883 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7884 "Invalid RTE action in tunnel "
7888 * Validate the drop action mutual exclusion with other actions.
7889 * Drop action is mutually-exclusive with any other action, except for
7891 * Drop action compatibility with tunnel offload was already validated.
7893 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7894 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7895 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7896 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7897 return rte_flow_error_set(error, EINVAL,
7898 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7899 "Drop action is mutually-exclusive "
7900 "with any other action, except for "
7902 /* Eswitch has few restrictions on using items and actions */
7903 if (attr->transfer) {
7904 if (!mlx5_flow_ext_mreg_supported(dev) &&
7905 action_flags & MLX5_FLOW_ACTION_FLAG)
7906 return rte_flow_error_set(error, ENOTSUP,
7907 RTE_FLOW_ERROR_TYPE_ACTION,
7909 "unsupported action FLAG");
7910 if (!mlx5_flow_ext_mreg_supported(dev) &&
7911 action_flags & MLX5_FLOW_ACTION_MARK)
7912 return rte_flow_error_set(error, ENOTSUP,
7913 RTE_FLOW_ERROR_TYPE_ACTION,
7915 "unsupported action MARK");
7916 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7917 return rte_flow_error_set(error, ENOTSUP,
7918 RTE_FLOW_ERROR_TYPE_ACTION,
7920 "unsupported action QUEUE");
7921 if (action_flags & MLX5_FLOW_ACTION_RSS)
7922 return rte_flow_error_set(error, ENOTSUP,
7923 RTE_FLOW_ERROR_TYPE_ACTION,
7925 "unsupported action RSS");
7926 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7927 return rte_flow_error_set(error, EINVAL,
7928 RTE_FLOW_ERROR_TYPE_ACTION,
7930 "no fate action is found");
7932 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7933 return rte_flow_error_set(error, EINVAL,
7934 RTE_FLOW_ERROR_TYPE_ACTION,
7936 "no fate action is found");
7939 * Continue validation for Xcap and VLAN actions.
7940 * If hairpin is working in explicit TX rule mode, there is no actions
7941 * splitting and the validation of hairpin ingress flow should be the
7942 * same as other standard flows.
7944 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7945 MLX5_FLOW_VLAN_ACTIONS)) &&
7946 (queue_index == 0xFFFF ||
7947 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7948 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7949 conf->tx_explicit != 0))) {
7950 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7951 MLX5_FLOW_XCAP_ACTIONS)
7952 return rte_flow_error_set(error, ENOTSUP,
7953 RTE_FLOW_ERROR_TYPE_ACTION,
7954 NULL, "encap and decap "
7955 "combination aren't supported");
7956 if (!attr->transfer && attr->ingress) {
7957 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7958 return rte_flow_error_set
7960 RTE_FLOW_ERROR_TYPE_ACTION,
7961 NULL, "encap is not supported"
7962 " for ingress traffic");
7963 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7964 return rte_flow_error_set
7966 RTE_FLOW_ERROR_TYPE_ACTION,
7967 NULL, "push VLAN action not "
7968 "supported for ingress");
7969 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7970 MLX5_FLOW_VLAN_ACTIONS)
7971 return rte_flow_error_set
7973 RTE_FLOW_ERROR_TYPE_ACTION,
7974 NULL, "no support for "
7975 "multiple VLAN actions");
7978 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7979 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7980 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7982 return rte_flow_error_set
7984 RTE_FLOW_ERROR_TYPE_ACTION,
7985 NULL, "fate action not supported for "
7986 "meter with policy");
7988 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7989 return rte_flow_error_set
7991 RTE_FLOW_ERROR_TYPE_ACTION,
7992 NULL, "modify header action in egress "
7993 "cannot be done before meter action");
7994 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7995 return rte_flow_error_set
7997 RTE_FLOW_ERROR_TYPE_ACTION,
7998 NULL, "encap action in egress "
7999 "cannot be done before meter action");
8000 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8001 return rte_flow_error_set
8003 RTE_FLOW_ERROR_TYPE_ACTION,
8004 NULL, "push vlan action in egress "
8005 "cannot be done before meter action");
8009 * Hairpin flow will add one more TAG action in TX implicit mode.
8010 * In TX explicit mode, there will be no hairpin flow ID.
8013 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8014 /* extra metadata enabled: one more TAG action will be add. */
8015 if (dev_conf->dv_flow_en &&
8016 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8017 mlx5_flow_ext_mreg_supported(dev))
8018 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8020 flow_dv_modify_hdr_action_max(dev, is_root)) {
8021 return rte_flow_error_set(error, ENOTSUP,
8022 RTE_FLOW_ERROR_TYPE_ACTION,
8023 NULL, "too many header modify"
8024 " actions to support");
8026 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8027 if (fdb_mirror_limit && modify_after_mirror)
8028 return rte_flow_error_set(error, EINVAL,
8029 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8030 "sample before modify action is not supported");
8035 * Internal preparation function. Allocates the DV flow size,
8036 * this size is constant.
8039 * Pointer to the rte_eth_dev structure.
8041 * Pointer to the flow attributes.
8043 * Pointer to the list of items.
8044 * @param[in] actions
8045 * Pointer to the list of actions.
8047 * Pointer to the error structure.
8050 * Pointer to mlx5_flow object on success,
8051 * otherwise NULL and rte_errno is set.
8053 static struct mlx5_flow *
8054 flow_dv_prepare(struct rte_eth_dev *dev,
8055 const struct rte_flow_attr *attr __rte_unused,
8056 const struct rte_flow_item items[] __rte_unused,
8057 const struct rte_flow_action actions[] __rte_unused,
8058 struct rte_flow_error *error)
8060 uint32_t handle_idx = 0;
8061 struct mlx5_flow *dev_flow;
8062 struct mlx5_flow_handle *dev_handle;
8063 struct mlx5_priv *priv = dev->data->dev_private;
8064 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8067 wks->skip_matcher_reg = 0;
8069 wks->final_policy = NULL;
8070 /* In case of corrupting the memory. */
8071 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8072 rte_flow_error_set(error, ENOSPC,
8073 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8074 "not free temporary device flow");
8077 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8080 rte_flow_error_set(error, ENOMEM,
8081 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8082 "not enough memory to create flow handle");
8085 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8086 dev_flow = &wks->flows[wks->flow_idx++];
8087 memset(dev_flow, 0, sizeof(*dev_flow));
8088 dev_flow->handle = dev_handle;
8089 dev_flow->handle_idx = handle_idx;
8090 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8091 dev_flow->ingress = attr->ingress;
8092 dev_flow->dv.transfer = attr->transfer;
8096 #ifdef RTE_LIBRTE_MLX5_DEBUG
8098 * Sanity check for match mask and value. Similar to check_valid_spec() in
8099 * kernel driver. If unmasked bit is present in value, it returns failure.
8102 * pointer to match mask buffer.
8103 * @param match_value
8104 * pointer to match value buffer.
8107 * 0 if valid, -EINVAL otherwise.
8110 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8112 uint8_t *m = match_mask;
8113 uint8_t *v = match_value;
8116 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8119 "match_value differs from match_criteria"
8120 " %p[%u] != %p[%u]",
8121 match_value, i, match_mask, i);
8130 * Add match of ip_version.
8134 * @param[in] headers_v
8135 * Values header pointer.
8136 * @param[in] headers_m
8137 * Masks header pointer.
8138 * @param[in] ip_version
8139 * The IP version to set.
8142 flow_dv_set_match_ip_version(uint32_t group,
8148 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8150 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8152 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8153 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8154 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8158 * Add Ethernet item to matcher and to the value.
8160 * @param[in, out] matcher
8162 * @param[in, out] key
8163 * Flow matcher value.
8165 * Flow pattern to translate.
8167 * Item is inner pattern.
8170 flow_dv_translate_item_eth(void *matcher, void *key,
8171 const struct rte_flow_item *item, int inner,
8174 const struct rte_flow_item_eth *eth_m = item->mask;
8175 const struct rte_flow_item_eth *eth_v = item->spec;
8176 const struct rte_flow_item_eth nic_mask = {
8177 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8178 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8179 .type = RTE_BE16(0xffff),
8192 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8194 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8196 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8198 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8200 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8201 ð_m->dst, sizeof(eth_m->dst));
8202 /* The value must be in the range of the mask. */
8203 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8204 for (i = 0; i < sizeof(eth_m->dst); ++i)
8205 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8206 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8207 ð_m->src, sizeof(eth_m->src));
8208 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8209 /* The value must be in the range of the mask. */
8210 for (i = 0; i < sizeof(eth_m->dst); ++i)
8211 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8213 * HW supports match on one Ethertype, the Ethertype following the last
8214 * VLAN tag of the packet (see PRM).
8215 * Set match on ethertype only if ETH header is not followed by VLAN.
8216 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8217 * ethertype, and use ip_version field instead.
8218 * eCPRI over Ether layer will use type value 0xAEFE.
8220 if (eth_m->type == 0xFFFF) {
8221 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8222 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8223 switch (eth_v->type) {
8224 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8225 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8227 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8228 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8229 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8231 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8232 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8234 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8235 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8241 if (eth_m->has_vlan) {
8242 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8243 if (eth_v->has_vlan) {
8245 * Here, when also has_more_vlan field in VLAN item is
8246 * not set, only single-tagged packets will be matched.
8248 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8252 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8253 rte_be_to_cpu_16(eth_m->type));
8254 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8255 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8259 * Add VLAN item to matcher and to the value.
8261 * @param[in, out] dev_flow
8263 * @param[in, out] matcher
8265 * @param[in, out] key
8266 * Flow matcher value.
8268 * Flow pattern to translate.
8270 * Item is inner pattern.
8273 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8274 void *matcher, void *key,
8275 const struct rte_flow_item *item,
8276 int inner, uint32_t group)
8278 const struct rte_flow_item_vlan *vlan_m = item->mask;
8279 const struct rte_flow_item_vlan *vlan_v = item->spec;
8286 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8288 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8290 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8292 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8294 * This is workaround, masks are not supported,
8295 * and pre-validated.
8298 dev_flow->handle->vf_vlan.tag =
8299 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8302 * When VLAN item exists in flow, mark packet as tagged,
8303 * even if TCI is not specified.
8305 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8306 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8307 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8312 vlan_m = &rte_flow_item_vlan_mask;
8313 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8314 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8315 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8316 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8317 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8318 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8319 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8320 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8322 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8323 * ethertype, and use ip_version field instead.
8325 if (vlan_m->inner_type == 0xFFFF) {
8326 switch (vlan_v->inner_type) {
8327 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8328 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8329 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8330 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8332 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8333 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8335 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8336 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8342 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8343 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8344 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8345 /* Only one vlan_tag bit can be set. */
8346 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8349 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8350 rte_be_to_cpu_16(vlan_m->inner_type));
8351 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8352 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8356 * Add IPV4 item to matcher and to the value.
8358 * @param[in, out] matcher
8360 * @param[in, out] key
8361 * Flow matcher value.
8363 * Flow pattern to translate.
8365 * Item is inner pattern.
8367 * The group to insert the rule.
8370 flow_dv_translate_item_ipv4(void *matcher, void *key,
8371 const struct rte_flow_item *item,
8372 int inner, uint32_t group)
8374 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8375 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8376 const struct rte_flow_item_ipv4 nic_mask = {
8378 .src_addr = RTE_BE32(0xffffffff),
8379 .dst_addr = RTE_BE32(0xffffffff),
8380 .type_of_service = 0xff,
8381 .next_proto_id = 0xff,
8382 .time_to_live = 0xff,
8389 uint8_t tos, ihl_m, ihl_v;
8392 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8394 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8396 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8398 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8400 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8405 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8406 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8407 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8408 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8409 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8410 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8411 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8412 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8413 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8414 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8415 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8416 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8417 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8418 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8419 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8420 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8421 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8422 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8423 ipv4_m->hdr.type_of_service);
8424 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8425 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8426 ipv4_m->hdr.type_of_service >> 2);
8427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8429 ipv4_m->hdr.next_proto_id);
8430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8431 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8432 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8433 ipv4_m->hdr.time_to_live);
8434 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8435 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8436 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8437 !!(ipv4_m->hdr.fragment_offset));
8438 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8439 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8443 * Add IPV6 item to matcher and to the value.
8445 * @param[in, out] matcher
8447 * @param[in, out] key
8448 * Flow matcher value.
8450 * Flow pattern to translate.
8452 * Item is inner pattern.
8454 * The group to insert the rule.
8457 flow_dv_translate_item_ipv6(void *matcher, void *key,
8458 const struct rte_flow_item *item,
8459 int inner, uint32_t group)
8461 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8462 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8463 const struct rte_flow_item_ipv6 nic_mask = {
8466 "\xff\xff\xff\xff\xff\xff\xff\xff"
8467 "\xff\xff\xff\xff\xff\xff\xff\xff",
8469 "\xff\xff\xff\xff\xff\xff\xff\xff"
8470 "\xff\xff\xff\xff\xff\xff\xff\xff",
8471 .vtc_flow = RTE_BE32(0xffffffff),
8478 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8479 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8488 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8490 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8492 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8494 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8496 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8501 size = sizeof(ipv6_m->hdr.dst_addr);
8502 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8503 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8504 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8505 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8506 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8507 for (i = 0; i < size; ++i)
8508 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8509 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8510 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8511 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8512 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8513 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8514 for (i = 0; i < size; ++i)
8515 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8517 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8518 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8519 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8521 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8522 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8525 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8527 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8530 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8532 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8536 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8538 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8539 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8542 ipv6_m->hdr.hop_limits);
8543 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8544 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8545 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8546 !!(ipv6_m->has_frag_ext));
8547 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8548 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8552 * Add IPV6 fragment extension item to matcher and to the value.
8554 * @param[in, out] matcher
8556 * @param[in, out] key
8557 * Flow matcher value.
8559 * Flow pattern to translate.
8561 * Item is inner pattern.
8564 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8565 const struct rte_flow_item *item,
8568 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8569 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8570 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8572 .next_header = 0xff,
8573 .frag_data = RTE_BE16(0xffff),
8580 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8582 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8584 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8586 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8588 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8589 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8590 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8591 if (!ipv6_frag_ext_v)
8593 if (!ipv6_frag_ext_m)
8594 ipv6_frag_ext_m = &nic_mask;
8595 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8596 ipv6_frag_ext_m->hdr.next_header);
8597 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8598 ipv6_frag_ext_v->hdr.next_header &
8599 ipv6_frag_ext_m->hdr.next_header);
8603 * Add TCP item to matcher and to the value.
8605 * @param[in, out] matcher
8607 * @param[in, out] key
8608 * Flow matcher value.
8610 * Flow pattern to translate.
8612 * Item is inner pattern.
8615 flow_dv_translate_item_tcp(void *matcher, void *key,
8616 const struct rte_flow_item *item,
8619 const struct rte_flow_item_tcp *tcp_m = item->mask;
8620 const struct rte_flow_item_tcp *tcp_v = item->spec;
8625 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8627 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8629 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8631 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8633 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8638 tcp_m = &rte_flow_item_tcp_mask;
8639 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8640 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8641 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8642 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8643 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8644 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8645 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8646 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8647 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8648 tcp_m->hdr.tcp_flags);
8649 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8650 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8654 * Add UDP item to matcher and to the value.
8656 * @param[in, out] matcher
8658 * @param[in, out] key
8659 * Flow matcher value.
8661 * Flow pattern to translate.
8663 * Item is inner pattern.
8666 flow_dv_translate_item_udp(void *matcher, void *key,
8667 const struct rte_flow_item *item,
8670 const struct rte_flow_item_udp *udp_m = item->mask;
8671 const struct rte_flow_item_udp *udp_v = item->spec;
8676 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8678 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8680 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8682 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8689 udp_m = &rte_flow_item_udp_mask;
8690 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8691 rte_be_to_cpu_16(udp_m->hdr.src_port));
8692 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8693 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8695 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8696 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8697 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8701 * Add GRE optional Key item to matcher and to the value.
8703 * @param[in, out] matcher
8705 * @param[in, out] key
8706 * Flow matcher value.
8708 * Flow pattern to translate.
8710 * Item is inner pattern.
8713 flow_dv_translate_item_gre_key(void *matcher, void *key,
8714 const struct rte_flow_item *item)
8716 const rte_be32_t *key_m = item->mask;
8717 const rte_be32_t *key_v = item->spec;
8718 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8719 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8720 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8722 /* GRE K bit must be on and should already be validated */
8723 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8724 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8728 key_m = &gre_key_default_mask;
8729 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8730 rte_be_to_cpu_32(*key_m) >> 8);
8731 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8732 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8733 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8734 rte_be_to_cpu_32(*key_m) & 0xFF);
8735 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8736 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8740 * Add GRE item to matcher and to the value.
8742 * @param[in, out] matcher
8744 * @param[in, out] key
8745 * Flow matcher value.
8747 * Flow pattern to translate.
8749 * Item is inner pattern.
8752 flow_dv_translate_item_gre(void *matcher, void *key,
8753 const struct rte_flow_item *item,
8756 const struct rte_flow_item_gre *gre_m = item->mask;
8757 const struct rte_flow_item_gre *gre_v = item->spec;
8760 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8761 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8768 uint16_t s_present:1;
8769 uint16_t k_present:1;
8770 uint16_t rsvd_bit1:1;
8771 uint16_t c_present:1;
8775 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8778 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8780 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8782 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8784 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8786 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8791 gre_m = &rte_flow_item_gre_mask;
8792 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8793 rte_be_to_cpu_16(gre_m->protocol));
8794 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8795 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8796 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8797 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8798 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8799 gre_crks_rsvd0_ver_m.c_present);
8800 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8801 gre_crks_rsvd0_ver_v.c_present &
8802 gre_crks_rsvd0_ver_m.c_present);
8803 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8804 gre_crks_rsvd0_ver_m.k_present);
8805 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8806 gre_crks_rsvd0_ver_v.k_present &
8807 gre_crks_rsvd0_ver_m.k_present);
8808 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8809 gre_crks_rsvd0_ver_m.s_present);
8810 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8811 gre_crks_rsvd0_ver_v.s_present &
8812 gre_crks_rsvd0_ver_m.s_present);
8816 * Add NVGRE item to matcher and to the value.
8818 * @param[in, out] matcher
8820 * @param[in, out] key
8821 * Flow matcher value.
8823 * Flow pattern to translate.
8825 * Item is inner pattern.
8828 flow_dv_translate_item_nvgre(void *matcher, void *key,
8829 const struct rte_flow_item *item,
8832 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8833 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8834 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8835 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8836 const char *tni_flow_id_m;
8837 const char *tni_flow_id_v;
8843 /* For NVGRE, GRE header fields must be set with defined values. */
8844 const struct rte_flow_item_gre gre_spec = {
8845 .c_rsvd0_ver = RTE_BE16(0x2000),
8846 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8848 const struct rte_flow_item_gre gre_mask = {
8849 .c_rsvd0_ver = RTE_BE16(0xB000),
8850 .protocol = RTE_BE16(UINT16_MAX),
8852 const struct rte_flow_item gre_item = {
8857 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8861 nvgre_m = &rte_flow_item_nvgre_mask;
8862 tni_flow_id_m = (const char *)nvgre_m->tni;
8863 tni_flow_id_v = (const char *)nvgre_v->tni;
8864 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8865 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8866 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8867 memcpy(gre_key_m, tni_flow_id_m, size);
8868 for (i = 0; i < size; ++i)
8869 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8873 * Add VXLAN item to matcher and to the value.
8876 * Pointer to the Ethernet device structure.
8878 * Flow rule attributes.
8879 * @param[in, out] matcher
8881 * @param[in, out] key
8882 * Flow matcher value.
8884 * Flow pattern to translate.
8886 * Item is inner pattern.
8889 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8890 const struct rte_flow_attr *attr,
8891 void *matcher, void *key,
8892 const struct rte_flow_item *item,
8895 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8896 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8901 uint32_t *tunnel_header_v;
8902 uint32_t *tunnel_header_m;
8904 struct mlx5_priv *priv = dev->data->dev_private;
8905 const struct rte_flow_item_vxlan nic_mask = {
8906 .vni = "\xff\xff\xff",
8911 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8913 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8915 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8917 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8919 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8920 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8921 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8922 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8923 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8928 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8929 (attr->group && !priv->sh->misc5_cap))
8930 vxlan_m = &rte_flow_item_vxlan_mask;
8932 vxlan_m = &nic_mask;
8934 if ((!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8935 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8942 misc_m = MLX5_ADDR_OF(fte_match_param,
8943 matcher, misc_parameters);
8944 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8945 size = sizeof(vxlan_m->vni);
8946 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8947 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8948 memcpy(vni_m, vxlan_m->vni, size);
8949 for (i = 0; i < size; ++i)
8950 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8953 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8954 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8955 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8958 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8961 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8962 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8963 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8964 if (*tunnel_header_v)
8965 *tunnel_header_m = vxlan_m->vni[0] |
8966 vxlan_m->vni[1] << 8 |
8967 vxlan_m->vni[2] << 16;
8969 *tunnel_header_m = 0x0;
8970 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8971 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8972 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8976 * Add VXLAN-GPE item to matcher and to the value.
8978 * @param[in, out] matcher
8980 * @param[in, out] key
8981 * Flow matcher value.
8983 * Flow pattern to translate.
8985 * Item is inner pattern.
8989 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8990 const struct rte_flow_item *item, int inner)
8992 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8993 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8997 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8999 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9005 uint8_t flags_m = 0xff;
9006 uint8_t flags_v = 0xc;
9009 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9011 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9013 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9015 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9017 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
9018 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
9019 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9020 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9021 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9026 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9027 size = sizeof(vxlan_m->vni);
9028 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9029 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9030 memcpy(vni_m, vxlan_m->vni, size);
9031 for (i = 0; i < size; ++i)
9032 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9033 if (vxlan_m->flags) {
9034 flags_m = vxlan_m->flags;
9035 flags_v = vxlan_v->flags;
9037 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9038 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9039 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
9041 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
9046 * Add Geneve item to matcher and to the value.
9048 * @param[in, out] matcher
9050 * @param[in, out] key
9051 * Flow matcher value.
9053 * Flow pattern to translate.
9055 * Item is inner pattern.
9059 flow_dv_translate_item_geneve(void *matcher, void *key,
9060 const struct rte_flow_item *item, int inner)
9062 const struct rte_flow_item_geneve *geneve_m = item->mask;
9063 const struct rte_flow_item_geneve *geneve_v = item->spec;
9066 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9067 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9076 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9078 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9080 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9082 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9084 dport = MLX5_UDP_PORT_GENEVE;
9085 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9086 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9087 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9092 geneve_m = &rte_flow_item_geneve_mask;
9093 size = sizeof(geneve_m->vni);
9094 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9095 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9096 memcpy(vni_m, geneve_m->vni, size);
9097 for (i = 0; i < size; ++i)
9098 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9099 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
9100 rte_be_to_cpu_16(geneve_m->protocol));
9101 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9102 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
9103 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9104 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9105 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9106 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9107 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9108 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9109 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9110 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9111 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9112 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9113 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9117 * Create Geneve TLV option resource.
9119 * @param dev[in, out]
9120 * Pointer to rte_eth_dev structure.
9121 * @param[in, out] tag_be24
9122 * Tag value in big endian then R-shift 8.
9123 * @parm[in, out] dev_flow
9124 * Pointer to the dev_flow.
9126 * pointer to error structure.
9129 * 0 on success otherwise -errno and errno is set.
9133 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9134 const struct rte_flow_item *item,
9135 struct rte_flow_error *error)
9137 struct mlx5_priv *priv = dev->data->dev_private;
9138 struct mlx5_dev_ctx_shared *sh = priv->sh;
9139 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9140 sh->geneve_tlv_option_resource;
9141 struct mlx5_devx_obj *obj;
9142 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9147 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9148 if (geneve_opt_resource != NULL) {
9149 if (geneve_opt_resource->option_class ==
9150 geneve_opt_v->option_class &&
9151 geneve_opt_resource->option_type ==
9152 geneve_opt_v->option_type &&
9153 geneve_opt_resource->length ==
9154 geneve_opt_v->option_len) {
9155 /* We already have GENVE TLV option obj allocated. */
9156 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9159 ret = rte_flow_error_set(error, ENOMEM,
9160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9161 "Only one GENEVE TLV option supported");
9165 /* Create a GENEVE TLV object and resource. */
9166 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
9167 geneve_opt_v->option_class,
9168 geneve_opt_v->option_type,
9169 geneve_opt_v->option_len);
9171 ret = rte_flow_error_set(error, ENODATA,
9172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9173 "Failed to create GENEVE TLV Devx object");
9176 sh->geneve_tlv_option_resource =
9177 mlx5_malloc(MLX5_MEM_ZERO,
9178 sizeof(*geneve_opt_resource),
9180 if (!sh->geneve_tlv_option_resource) {
9181 claim_zero(mlx5_devx_cmd_destroy(obj));
9182 ret = rte_flow_error_set(error, ENOMEM,
9183 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9184 "GENEVE TLV object memory allocation failed");
9187 geneve_opt_resource = sh->geneve_tlv_option_resource;
9188 geneve_opt_resource->obj = obj;
9189 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9190 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9191 geneve_opt_resource->length = geneve_opt_v->option_len;
9192 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9196 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9201 * Add Geneve TLV option item to matcher.
9203 * @param[in, out] dev
9204 * Pointer to rte_eth_dev structure.
9205 * @param[in, out] matcher
9207 * @param[in, out] key
9208 * Flow matcher value.
9210 * Flow pattern to translate.
9212 * Pointer to error structure.
9215 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9216 void *key, const struct rte_flow_item *item,
9217 struct rte_flow_error *error)
9219 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9220 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9221 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9222 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9223 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9225 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9226 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9232 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9233 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9236 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9240 * Set the option length in GENEVE header if not requested.
9241 * The GENEVE TLV option length is expressed by the option length field
9242 * in the GENEVE header.
9243 * If the option length was not requested but the GENEVE TLV option item
9244 * is present we set the option length field implicitly.
9246 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9247 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9248 MLX5_GENEVE_OPTLEN_MASK);
9249 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9250 geneve_opt_v->option_len + 1);
9253 if (geneve_opt_v->data) {
9254 memcpy(&opt_data_key, geneve_opt_v->data,
9255 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9256 sizeof(opt_data_key)));
9257 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9258 sizeof(opt_data_key));
9259 memcpy(&opt_data_mask, geneve_opt_m->data,
9260 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9261 sizeof(opt_data_mask)));
9262 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9263 sizeof(opt_data_mask));
9264 MLX5_SET(fte_match_set_misc3, misc3_m,
9265 geneve_tlv_option_0_data,
9266 rte_be_to_cpu_32(opt_data_mask));
9267 MLX5_SET(fte_match_set_misc3, misc3_v,
9268 geneve_tlv_option_0_data,
9269 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9275 * Add MPLS item to matcher and to the value.
9277 * @param[in, out] matcher
9279 * @param[in, out] key
9280 * Flow matcher value.
9282 * Flow pattern to translate.
9283 * @param[in] prev_layer
9284 * The protocol layer indicated in previous item.
9286 * Item is inner pattern.
9289 flow_dv_translate_item_mpls(void *matcher, void *key,
9290 const struct rte_flow_item *item,
9291 uint64_t prev_layer,
9294 const uint32_t *in_mpls_m = item->mask;
9295 const uint32_t *in_mpls_v = item->spec;
9296 uint32_t *out_mpls_m = 0;
9297 uint32_t *out_mpls_v = 0;
9298 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9299 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9300 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9302 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9303 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9304 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9306 switch (prev_layer) {
9307 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9308 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9309 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9310 MLX5_UDP_PORT_MPLS);
9312 case MLX5_FLOW_LAYER_GRE:
9314 case MLX5_FLOW_LAYER_GRE_KEY:
9315 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9316 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9317 RTE_ETHER_TYPE_MPLS);
9325 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9326 switch (prev_layer) {
9327 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9329 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9330 outer_first_mpls_over_udp);
9332 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9333 outer_first_mpls_over_udp);
9335 case MLX5_FLOW_LAYER_GRE:
9337 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9338 outer_first_mpls_over_gre);
9340 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9341 outer_first_mpls_over_gre);
9344 /* Inner MPLS not over GRE is not supported. */
9347 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9351 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9357 if (out_mpls_m && out_mpls_v) {
9358 *out_mpls_m = *in_mpls_m;
9359 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9364 * Add metadata register item to matcher
9366 * @param[in, out] matcher
9368 * @param[in, out] key
9369 * Flow matcher value.
9370 * @param[in] reg_type
9371 * Type of device metadata register
9378 flow_dv_match_meta_reg(void *matcher, void *key,
9379 enum modify_reg reg_type,
9380 uint32_t data, uint32_t mask)
9383 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9385 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9391 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9392 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9395 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9396 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9400 * The metadata register C0 field might be divided into
9401 * source vport index and META item value, we should set
9402 * this field according to specified mask, not as whole one.
9404 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9406 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9407 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9410 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9413 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9414 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9417 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9418 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9421 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9422 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9425 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9426 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9429 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9430 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9433 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9434 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9437 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9438 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9447 * Add MARK item to matcher
9450 * The device to configure through.
9451 * @param[in, out] matcher
9453 * @param[in, out] key
9454 * Flow matcher value.
9456 * Flow pattern to translate.
9459 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9460 void *matcher, void *key,
9461 const struct rte_flow_item *item)
9463 struct mlx5_priv *priv = dev->data->dev_private;
9464 const struct rte_flow_item_mark *mark;
9468 mark = item->mask ? (const void *)item->mask :
9469 &rte_flow_item_mark_mask;
9470 mask = mark->id & priv->sh->dv_mark_mask;
9471 mark = (const void *)item->spec;
9473 value = mark->id & priv->sh->dv_mark_mask & mask;
9475 enum modify_reg reg;
9477 /* Get the metadata register index for the mark. */
9478 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9479 MLX5_ASSERT(reg > 0);
9480 if (reg == REG_C_0) {
9481 struct mlx5_priv *priv = dev->data->dev_private;
9482 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9483 uint32_t shl_c0 = rte_bsf32(msk_c0);
9489 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9494 * Add META item to matcher
9497 * The devich to configure through.
9498 * @param[in, out] matcher
9500 * @param[in, out] key
9501 * Flow matcher value.
9503 * Attributes of flow that includes this item.
9505 * Flow pattern to translate.
9508 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9509 void *matcher, void *key,
9510 const struct rte_flow_attr *attr,
9511 const struct rte_flow_item *item)
9513 const struct rte_flow_item_meta *meta_m;
9514 const struct rte_flow_item_meta *meta_v;
9516 meta_m = (const void *)item->mask;
9518 meta_m = &rte_flow_item_meta_mask;
9519 meta_v = (const void *)item->spec;
9522 uint32_t value = meta_v->data;
9523 uint32_t mask = meta_m->data;
9525 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9528 MLX5_ASSERT(reg != REG_NON);
9529 if (reg == REG_C_0) {
9530 struct mlx5_priv *priv = dev->data->dev_private;
9531 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9532 uint32_t shl_c0 = rte_bsf32(msk_c0);
9538 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9543 * Add vport metadata Reg C0 item to matcher
9545 * @param[in, out] matcher
9547 * @param[in, out] key
9548 * Flow matcher value.
9550 * Flow pattern to translate.
9553 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9554 uint32_t value, uint32_t mask)
9556 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9560 * Add tag item to matcher
9563 * The devich to configure through.
9564 * @param[in, out] matcher
9566 * @param[in, out] key
9567 * Flow matcher value.
9569 * Flow pattern to translate.
9572 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9573 void *matcher, void *key,
9574 const struct rte_flow_item *item)
9576 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9577 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9578 uint32_t mask, value;
9581 value = tag_v->data;
9582 mask = tag_m ? tag_m->data : UINT32_MAX;
9583 if (tag_v->id == REG_C_0) {
9584 struct mlx5_priv *priv = dev->data->dev_private;
9585 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9586 uint32_t shl_c0 = rte_bsf32(msk_c0);
9592 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9596 * Add TAG item to matcher
9599 * The devich to configure through.
9600 * @param[in, out] matcher
9602 * @param[in, out] key
9603 * Flow matcher value.
9605 * Flow pattern to translate.
9608 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9609 void *matcher, void *key,
9610 const struct rte_flow_item *item)
9612 const struct rte_flow_item_tag *tag_v = item->spec;
9613 const struct rte_flow_item_tag *tag_m = item->mask;
9614 enum modify_reg reg;
9617 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9618 /* Get the metadata register index for the tag. */
9619 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9620 MLX5_ASSERT(reg > 0);
9621 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9625 * Add source vport match to the specified matcher.
9627 * @param[in, out] matcher
9629 * @param[in, out] key
9630 * Flow matcher value.
9632 * Source vport value to match
9637 flow_dv_translate_item_source_vport(void *matcher, void *key,
9638 int16_t port, uint16_t mask)
9640 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9641 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9643 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9644 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9648 * Translate port-id item to eswitch match on port-id.
9651 * The devich to configure through.
9652 * @param[in, out] matcher
9654 * @param[in, out] key
9655 * Flow matcher value.
9657 * Flow pattern to translate.
9662 * 0 on success, a negative errno value otherwise.
9665 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9666 void *key, const struct rte_flow_item *item,
9667 const struct rte_flow_attr *attr)
9669 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9670 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9671 struct mlx5_priv *priv;
9674 mask = pid_m ? pid_m->id : 0xffff;
9675 id = pid_v ? pid_v->id : dev->data->port_id;
9676 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9680 * Translate to vport field or to metadata, depending on mode.
9681 * Kernel can use either misc.source_port or half of C0 metadata
9684 if (priv->vport_meta_mask) {
9686 * Provide the hint for SW steering library
9687 * to insert the flow into ingress domain and
9688 * save the extra vport match.
9690 if (mask == 0xffff && priv->vport_id == 0xffff &&
9691 priv->pf_bond < 0 && attr->transfer)
9692 flow_dv_translate_item_source_vport
9693 (matcher, key, priv->vport_id, mask);
9695 * We should always set the vport metadata register,
9696 * otherwise the SW steering library can drop
9697 * the rule if wire vport metadata value is not zero,
9698 * it depends on kernel configuration.
9700 flow_dv_translate_item_meta_vport(matcher, key,
9701 priv->vport_meta_tag,
9702 priv->vport_meta_mask);
9704 flow_dv_translate_item_source_vport(matcher, key,
9705 priv->vport_id, mask);
9711 * Add ICMP6 item to matcher and to the value.
9713 * @param[in, out] matcher
9715 * @param[in, out] key
9716 * Flow matcher value.
9718 * Flow pattern to translate.
9720 * Item is inner pattern.
9723 flow_dv_translate_item_icmp6(void *matcher, void *key,
9724 const struct rte_flow_item *item,
9727 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9728 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9731 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9733 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9735 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9737 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9739 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9741 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9743 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9748 icmp6_m = &rte_flow_item_icmp6_mask;
9749 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9750 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9751 icmp6_v->type & icmp6_m->type);
9752 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9753 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9754 icmp6_v->code & icmp6_m->code);
9758 * Add ICMP item to matcher and to the value.
9760 * @param[in, out] matcher
9762 * @param[in, out] key
9763 * Flow matcher value.
9765 * Flow pattern to translate.
9767 * Item is inner pattern.
9770 flow_dv_translate_item_icmp(void *matcher, void *key,
9771 const struct rte_flow_item *item,
9774 const struct rte_flow_item_icmp *icmp_m = item->mask;
9775 const struct rte_flow_item_icmp *icmp_v = item->spec;
9776 uint32_t icmp_header_data_m = 0;
9777 uint32_t icmp_header_data_v = 0;
9780 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9782 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9784 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9786 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9788 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9790 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9792 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9793 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9797 icmp_m = &rte_flow_item_icmp_mask;
9798 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9799 icmp_m->hdr.icmp_type);
9800 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9801 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9802 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9803 icmp_m->hdr.icmp_code);
9804 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9805 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9806 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9807 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9808 if (icmp_header_data_m) {
9809 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9810 icmp_header_data_v |=
9811 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9812 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9813 icmp_header_data_m);
9814 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9815 icmp_header_data_v & icmp_header_data_m);
9820 * Add GTP item to matcher and to the value.
9822 * @param[in, out] matcher
9824 * @param[in, out] key
9825 * Flow matcher value.
9827 * Flow pattern to translate.
9829 * Item is inner pattern.
9832 flow_dv_translate_item_gtp(void *matcher, void *key,
9833 const struct rte_flow_item *item, int inner)
9835 const struct rte_flow_item_gtp *gtp_m = item->mask;
9836 const struct rte_flow_item_gtp *gtp_v = item->spec;
9839 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9841 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9842 uint16_t dport = RTE_GTPU_UDP_PORT;
9845 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9847 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9849 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9851 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9853 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9854 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9855 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9860 gtp_m = &rte_flow_item_gtp_mask;
9861 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9862 gtp_m->v_pt_rsv_flags);
9863 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9864 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9865 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9866 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9867 gtp_v->msg_type & gtp_m->msg_type);
9868 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9869 rte_be_to_cpu_32(gtp_m->teid));
9870 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9871 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9875 * Add GTP PSC item to matcher.
9877 * @param[in, out] matcher
9879 * @param[in, out] key
9880 * Flow matcher value.
9882 * Flow pattern to translate.
9885 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9886 const struct rte_flow_item *item)
9888 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9889 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9890 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9892 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9898 uint8_t next_ext_header_type;
9903 /* Always set E-flag match on one, regardless of GTP item settings. */
9904 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9905 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9906 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9907 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9908 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9909 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9910 /*Set next extension header type. */
9913 dw_2.next_ext_header_type = 0xff;
9914 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9915 rte_cpu_to_be_32(dw_2.w32));
9918 dw_2.next_ext_header_type = 0x85;
9919 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9920 rte_cpu_to_be_32(dw_2.w32));
9932 /*Set extension header PDU type and Qos. */
9934 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9936 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9937 dw_0.qfi = gtp_psc_m->qfi;
9938 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9939 rte_cpu_to_be_32(dw_0.w32));
9941 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9942 gtp_psc_m->pdu_type);
9943 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9944 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9945 rte_cpu_to_be_32(dw_0.w32));
9951 * Add eCPRI item to matcher and to the value.
9954 * The devich to configure through.
9955 * @param[in, out] matcher
9957 * @param[in, out] key
9958 * Flow matcher value.
9960 * Flow pattern to translate.
9961 * @param[in] samples
9962 * Sample IDs to be used in the matching.
9965 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9966 void *key, const struct rte_flow_item *item)
9968 struct mlx5_priv *priv = dev->data->dev_private;
9969 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9970 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9971 struct rte_ecpri_common_hdr common;
9972 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9974 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9982 ecpri_m = &rte_flow_item_ecpri_mask;
9984 * Maximal four DW samples are supported in a single matching now.
9985 * Two are used now for a eCPRI matching:
9986 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9987 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9990 if (!ecpri_m->hdr.common.u32)
9992 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9993 /* Need to take the whole DW as the mask to fill the entry. */
9994 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9995 prog_sample_field_value_0);
9996 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9997 prog_sample_field_value_0);
9998 /* Already big endian (network order) in the header. */
9999 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10000 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10001 /* Sample#0, used for matching type, offset 0. */
10002 MLX5_SET(fte_match_set_misc4, misc4_m,
10003 prog_sample_field_id_0, samples[0]);
10004 /* It makes no sense to set the sample ID in the mask field. */
10005 MLX5_SET(fte_match_set_misc4, misc4_v,
10006 prog_sample_field_id_0, samples[0]);
10008 * Checking if message body part needs to be matched.
10009 * Some wildcard rules only matching type field should be supported.
10011 if (ecpri_m->hdr.dummy[0]) {
10012 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10013 switch (common.type) {
10014 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10015 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10016 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10017 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10018 prog_sample_field_value_1);
10019 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10020 prog_sample_field_value_1);
10021 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10022 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10023 ecpri_m->hdr.dummy[0];
10024 /* Sample#1, to match message body, offset 4. */
10025 MLX5_SET(fte_match_set_misc4, misc4_m,
10026 prog_sample_field_id_1, samples[1]);
10027 MLX5_SET(fte_match_set_misc4, misc4_v,
10028 prog_sample_field_id_1, samples[1]);
10031 /* Others, do not match any sample ID. */
10038 * Add connection tracking status item to matcher
10041 * The devich to configure through.
10042 * @param[in, out] matcher
10044 * @param[in, out] key
10045 * Flow matcher value.
10047 * Flow pattern to translate.
10050 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10051 void *matcher, void *key,
10052 const struct rte_flow_item *item)
10054 uint32_t reg_value = 0;
10056 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10057 uint32_t reg_mask = 0;
10058 const struct rte_flow_item_conntrack *spec = item->spec;
10059 const struct rte_flow_item_conntrack *mask = item->mask;
10061 struct rte_flow_error error;
10064 mask = &rte_flow_item_conntrack_mask;
10065 if (!spec || !mask->flags)
10067 flags = spec->flags & mask->flags;
10068 /* The conflict should be checked in the validation. */
10069 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10070 reg_value |= MLX5_CT_SYNDROME_VALID;
10071 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10072 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10073 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10074 reg_value |= MLX5_CT_SYNDROME_INVALID;
10075 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10076 reg_value |= MLX5_CT_SYNDROME_TRAP;
10077 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10078 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10079 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10080 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10081 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10083 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10084 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10085 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10086 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10087 /* The REG_C_x value could be saved during startup. */
10088 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10089 if (reg_id == REG_NON)
10091 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10092 reg_value, reg_mask);
10095 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10097 #define HEADER_IS_ZERO(match_criteria, headers) \
10098 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10099 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10102 * Calculate flow matcher enable bitmap.
10104 * @param match_criteria
10105 * Pointer to flow matcher criteria.
10108 * Bitmap of enabled fields.
10111 flow_dv_matcher_enable(uint32_t *match_criteria)
10113 uint8_t match_criteria_enable;
10115 match_criteria_enable =
10116 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10117 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10118 match_criteria_enable |=
10119 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10120 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10121 match_criteria_enable |=
10122 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10123 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10124 match_criteria_enable |=
10125 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10126 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10127 match_criteria_enable |=
10128 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10129 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10130 match_criteria_enable |=
10131 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10132 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10133 match_criteria_enable |=
10134 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10135 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10136 return match_criteria_enable;
10140 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10143 * Check flow matching criteria first, subtract misc5/4 length if flow
10144 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10145 * misc5/4 are not supported, and matcher creation failure is expected
10146 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10147 * misc5 is right after misc4.
10149 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10150 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10151 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10152 if (!(match_criteria & (1 <<
10153 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10154 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10159 static struct mlx5_list_entry *
10160 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10161 struct mlx5_list_entry *entry, void *cb_ctx)
10163 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10164 struct mlx5_flow_dv_matcher *ref = ctx->data;
10165 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10166 typeof(*tbl), tbl);
10167 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10172 rte_flow_error_set(ctx->error, ENOMEM,
10173 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10174 "cannot create matcher");
10177 memcpy(resource, entry, sizeof(*resource));
10178 resource->tbl = &tbl->tbl;
10179 return &resource->entry;
10183 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10184 struct mlx5_list_entry *entry)
10189 struct mlx5_list_entry *
10190 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10192 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10193 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10194 struct rte_eth_dev *dev = ctx->dev;
10195 struct mlx5_flow_tbl_data_entry *tbl_data;
10196 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10197 struct rte_flow_error *error = ctx->error;
10198 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10199 struct mlx5_flow_tbl_resource *tbl;
10204 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10206 rte_flow_error_set(error, ENOMEM,
10207 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10209 "cannot allocate flow table data entry");
10212 tbl_data->idx = idx;
10213 tbl_data->tunnel = tt_prm->tunnel;
10214 tbl_data->group_id = tt_prm->group_id;
10215 tbl_data->external = !!tt_prm->external;
10216 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10217 tbl_data->is_egress = !!key.is_egress;
10218 tbl_data->is_transfer = !!key.is_fdb;
10219 tbl_data->dummy = !!key.dummy;
10220 tbl_data->level = key.level;
10221 tbl_data->id = key.id;
10222 tbl = &tbl_data->tbl;
10224 return &tbl_data->entry;
10226 domain = sh->fdb_domain;
10227 else if (key.is_egress)
10228 domain = sh->tx_domain;
10230 domain = sh->rx_domain;
10231 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10233 rte_flow_error_set(error, ENOMEM,
10234 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10235 NULL, "cannot create flow table object");
10236 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10239 if (key.level != 0) {
10240 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10241 (tbl->obj, &tbl_data->jump.action);
10243 rte_flow_error_set(error, ENOMEM,
10244 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10246 "cannot create flow jump action");
10247 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10248 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10252 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10253 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10254 key.level, key.id);
10255 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10256 flow_dv_matcher_create_cb,
10257 flow_dv_matcher_match_cb,
10258 flow_dv_matcher_remove_cb,
10259 flow_dv_matcher_clone_cb,
10260 flow_dv_matcher_clone_free_cb);
10261 if (!tbl_data->matchers) {
10262 rte_flow_error_set(error, ENOMEM,
10263 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10265 "cannot create tbl matcher list");
10266 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10267 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10268 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10271 return &tbl_data->entry;
10275 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10278 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10279 struct mlx5_flow_tbl_data_entry *tbl_data =
10280 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10281 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10283 return tbl_data->level != key.level ||
10284 tbl_data->id != key.id ||
10285 tbl_data->dummy != key.dummy ||
10286 tbl_data->is_transfer != !!key.is_fdb ||
10287 tbl_data->is_egress != !!key.is_egress;
10290 struct mlx5_list_entry *
10291 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10294 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10295 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10296 struct mlx5_flow_tbl_data_entry *tbl_data;
10297 struct rte_flow_error *error = ctx->error;
10300 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10302 rte_flow_error_set(error, ENOMEM,
10303 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10305 "cannot allocate flow table data entry");
10308 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10309 tbl_data->idx = idx;
10310 return &tbl_data->entry;
10314 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10316 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10317 struct mlx5_flow_tbl_data_entry *tbl_data =
10318 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10320 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10324 * Get a flow table.
10326 * @param[in, out] dev
10327 * Pointer to rte_eth_dev structure.
10328 * @param[in] table_level
10329 * Table level to use.
10330 * @param[in] egress
10331 * Direction of the table.
10332 * @param[in] transfer
10333 * E-Switch or NIC flow.
10335 * Dummy entry for dv API.
10336 * @param[in] table_id
10338 * @param[out] error
10339 * pointer to error structure.
10342 * Returns tables resource based on the index, NULL in case of failed.
10344 struct mlx5_flow_tbl_resource *
10345 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10346 uint32_t table_level, uint8_t egress,
10349 const struct mlx5_flow_tunnel *tunnel,
10350 uint32_t group_id, uint8_t dummy,
10352 struct rte_flow_error *error)
10354 struct mlx5_priv *priv = dev->data->dev_private;
10355 union mlx5_flow_tbl_key table_key = {
10357 .level = table_level,
10361 .is_fdb = !!transfer,
10362 .is_egress = !!egress,
10365 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10367 .group_id = group_id,
10368 .external = external,
10370 struct mlx5_flow_cb_ctx ctx = {
10373 .data = &table_key.v64,
10376 struct mlx5_list_entry *entry;
10377 struct mlx5_flow_tbl_data_entry *tbl_data;
10379 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10381 rte_flow_error_set(error, ENOMEM,
10382 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10383 "cannot get table");
10386 DRV_LOG(DEBUG, "table_level %u table_id %u "
10387 "tunnel %u group %u registered.",
10388 table_level, table_id,
10389 tunnel ? tunnel->tunnel_id : 0, group_id);
10390 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10391 return &tbl_data->tbl;
10395 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10397 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10398 struct mlx5_flow_tbl_data_entry *tbl_data =
10399 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10401 MLX5_ASSERT(entry && sh);
10402 if (tbl_data->jump.action)
10403 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10404 if (tbl_data->tbl.obj)
10405 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10406 if (tbl_data->tunnel_offload && tbl_data->external) {
10407 struct mlx5_list_entry *he;
10408 struct mlx5_hlist *tunnel_grp_hash;
10409 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10410 union tunnel_tbl_key tunnel_key = {
10411 .tunnel_id = tbl_data->tunnel ?
10412 tbl_data->tunnel->tunnel_id : 0,
10413 .group = tbl_data->group_id
10415 uint32_t table_level = tbl_data->level;
10416 struct mlx5_flow_cb_ctx ctx = {
10417 .data = (void *)&tunnel_key.val,
10420 tunnel_grp_hash = tbl_data->tunnel ?
10421 tbl_data->tunnel->groups :
10423 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10425 mlx5_hlist_unregister(tunnel_grp_hash, he);
10427 "table_level %u id %u tunnel %u group %u released.",
10431 tbl_data->tunnel->tunnel_id : 0,
10432 tbl_data->group_id);
10434 mlx5_list_destroy(tbl_data->matchers);
10435 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10439 * Release a flow table.
10442 * Pointer to device shared structure.
10444 * Table resource to be released.
10447 * Returns 0 if table was released, else return 1;
10450 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10451 struct mlx5_flow_tbl_resource *tbl)
10453 struct mlx5_flow_tbl_data_entry *tbl_data =
10454 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10458 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10462 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10463 struct mlx5_list_entry *entry, void *cb_ctx)
10465 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10466 struct mlx5_flow_dv_matcher *ref = ctx->data;
10467 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10470 return cur->crc != ref->crc ||
10471 cur->priority != ref->priority ||
10472 memcmp((const void *)cur->mask.buf,
10473 (const void *)ref->mask.buf, ref->mask.size);
10476 struct mlx5_list_entry *
10477 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10479 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10480 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10481 struct mlx5_flow_dv_matcher *ref = ctx->data;
10482 struct mlx5_flow_dv_matcher *resource;
10483 struct mlx5dv_flow_matcher_attr dv_attr = {
10484 .type = IBV_FLOW_ATTR_NORMAL,
10485 .match_mask = (void *)&ref->mask,
10487 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10488 typeof(*tbl), tbl);
10491 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10494 rte_flow_error_set(ctx->error, ENOMEM,
10495 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10496 "cannot create matcher");
10500 dv_attr.match_criteria_enable =
10501 flow_dv_matcher_enable(resource->mask.buf);
10502 __flow_dv_adjust_buf_size(&ref->mask.size,
10503 dv_attr.match_criteria_enable);
10504 dv_attr.priority = ref->priority;
10505 if (tbl->is_egress)
10506 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10507 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
10508 &resource->matcher_object);
10510 mlx5_free(resource);
10511 rte_flow_error_set(ctx->error, ENOMEM,
10512 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10513 "cannot create matcher");
10516 return &resource->entry;
10520 * Register the flow matcher.
10522 * @param[in, out] dev
10523 * Pointer to rte_eth_dev structure.
10524 * @param[in, out] matcher
10525 * Pointer to flow matcher.
10526 * @param[in, out] key
10527 * Pointer to flow table key.
10528 * @parm[in, out] dev_flow
10529 * Pointer to the dev_flow.
10530 * @param[out] error
10531 * pointer to error structure.
10534 * 0 on success otherwise -errno and errno is set.
10537 flow_dv_matcher_register(struct rte_eth_dev *dev,
10538 struct mlx5_flow_dv_matcher *ref,
10539 union mlx5_flow_tbl_key *key,
10540 struct mlx5_flow *dev_flow,
10541 const struct mlx5_flow_tunnel *tunnel,
10543 struct rte_flow_error *error)
10545 struct mlx5_list_entry *entry;
10546 struct mlx5_flow_dv_matcher *resource;
10547 struct mlx5_flow_tbl_resource *tbl;
10548 struct mlx5_flow_tbl_data_entry *tbl_data;
10549 struct mlx5_flow_cb_ctx ctx = {
10554 * tunnel offload API requires this registration for cases when
10555 * tunnel match rule was inserted before tunnel set rule.
10557 tbl = flow_dv_tbl_resource_get(dev, key->level,
10558 key->is_egress, key->is_fdb,
10559 dev_flow->external, tunnel,
10560 group_id, 0, key->id, error);
10562 return -rte_errno; /* No need to refill the error info */
10563 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10565 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10567 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10568 return rte_flow_error_set(error, ENOMEM,
10569 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10570 "cannot allocate ref memory");
10572 resource = container_of(entry, typeof(*resource), entry);
10573 dev_flow->handle->dvh.matcher = resource;
10577 struct mlx5_list_entry *
10578 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10580 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10581 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10582 struct mlx5_flow_dv_tag_resource *entry;
10586 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10588 rte_flow_error_set(ctx->error, ENOMEM,
10589 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10590 "cannot allocate resource memory");
10594 entry->tag_id = *(uint32_t *)(ctx->data);
10595 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10598 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10599 rte_flow_error_set(ctx->error, ENOMEM,
10600 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10601 NULL, "cannot create action");
10604 return &entry->entry;
10608 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10611 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10612 struct mlx5_flow_dv_tag_resource *tag =
10613 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10615 return *(uint32_t *)(ctx->data) != tag->tag_id;
10618 struct mlx5_list_entry *
10619 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10622 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10623 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10624 struct mlx5_flow_dv_tag_resource *entry;
10627 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10629 rte_flow_error_set(ctx->error, ENOMEM,
10630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10631 "cannot allocate tag resource memory");
10634 memcpy(entry, oentry, sizeof(*entry));
10636 return &entry->entry;
10640 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10642 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10643 struct mlx5_flow_dv_tag_resource *tag =
10644 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10646 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10650 * Find existing tag resource or create and register a new one.
10652 * @param dev[in, out]
10653 * Pointer to rte_eth_dev structure.
10654 * @param[in, out] tag_be24
10655 * Tag value in big endian then R-shift 8.
10656 * @parm[in, out] dev_flow
10657 * Pointer to the dev_flow.
10658 * @param[out] error
10659 * pointer to error structure.
10662 * 0 on success otherwise -errno and errno is set.
10665 flow_dv_tag_resource_register
10666 (struct rte_eth_dev *dev,
10668 struct mlx5_flow *dev_flow,
10669 struct rte_flow_error *error)
10671 struct mlx5_priv *priv = dev->data->dev_private;
10672 struct mlx5_flow_dv_tag_resource *resource;
10673 struct mlx5_list_entry *entry;
10674 struct mlx5_flow_cb_ctx ctx = {
10678 struct mlx5_hlist *tag_table;
10680 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10682 MLX5_TAGS_HLIST_ARRAY_SIZE,
10683 false, false, priv->sh,
10684 flow_dv_tag_create_cb,
10685 flow_dv_tag_match_cb,
10686 flow_dv_tag_remove_cb,
10687 flow_dv_tag_clone_cb,
10688 flow_dv_tag_clone_free_cb);
10689 if (unlikely(!tag_table))
10691 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10693 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10695 dev_flow->handle->dvh.rix_tag = resource->idx;
10696 dev_flow->dv.tag_resource = resource;
10703 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10705 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10706 struct mlx5_flow_dv_tag_resource *tag =
10707 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10709 MLX5_ASSERT(tag && sh && tag->action);
10710 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10711 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10712 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10719 * Pointer to Ethernet device.
10724 * 1 while a reference on it exists, 0 when freed.
10727 flow_dv_tag_release(struct rte_eth_dev *dev,
10730 struct mlx5_priv *priv = dev->data->dev_private;
10731 struct mlx5_flow_dv_tag_resource *tag;
10733 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10736 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10737 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10738 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10742 * Translate port ID action to vport.
10745 * Pointer to rte_eth_dev structure.
10746 * @param[in] action
10747 * Pointer to the port ID action.
10748 * @param[out] dst_port_id
10749 * The target port ID.
10750 * @param[out] error
10751 * Pointer to the error structure.
10754 * 0 on success, a negative errno value otherwise and rte_errno is set.
10757 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10758 const struct rte_flow_action *action,
10759 uint32_t *dst_port_id,
10760 struct rte_flow_error *error)
10763 struct mlx5_priv *priv;
10764 const struct rte_flow_action_port_id *conf =
10765 (const struct rte_flow_action_port_id *)action->conf;
10767 port = conf->original ? dev->data->port_id : conf->id;
10768 priv = mlx5_port_to_eswitch_info(port, false);
10770 return rte_flow_error_set(error, -rte_errno,
10771 RTE_FLOW_ERROR_TYPE_ACTION,
10773 "No eswitch info was found for port");
10774 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10776 * This parameter is transferred to
10777 * mlx5dv_dr_action_create_dest_ib_port().
10779 *dst_port_id = priv->dev_port;
10782 * Legacy mode, no LAG configurations is supported.
10783 * This parameter is transferred to
10784 * mlx5dv_dr_action_create_dest_vport().
10786 *dst_port_id = priv->vport_id;
10792 * Create a counter with aging configuration.
10795 * Pointer to rte_eth_dev structure.
10796 * @param[in] dev_flow
10797 * Pointer to the mlx5_flow.
10798 * @param[out] count
10799 * Pointer to the counter action configuration.
10801 * Pointer to the aging action configuration.
10804 * Index to flow counter on success, 0 otherwise.
10807 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10808 struct mlx5_flow *dev_flow,
10809 const struct rte_flow_action_count *count,
10810 const struct rte_flow_action_age *age)
10813 struct mlx5_age_param *age_param;
10815 if (count && count->shared)
10816 counter = flow_dv_counter_get_shared(dev, count->id);
10818 counter = flow_dv_counter_alloc(dev, !!age);
10819 if (!counter || age == NULL)
10821 age_param = flow_dv_counter_idx_get_age(dev, counter);
10822 age_param->context = age->context ? age->context :
10823 (void *)(uintptr_t)(dev_flow->flow_idx);
10824 age_param->timeout = age->timeout;
10825 age_param->port_id = dev->data->port_id;
10826 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10827 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10832 * Add Tx queue matcher
10835 * Pointer to the dev struct.
10836 * @param[in, out] matcher
10838 * @param[in, out] key
10839 * Flow matcher value.
10841 * Flow pattern to translate.
10843 * Item is inner pattern.
10846 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10847 void *matcher, void *key,
10848 const struct rte_flow_item *item)
10850 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10851 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10853 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10855 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10856 struct mlx5_txq_ctrl *txq;
10860 queue_m = (const void *)item->mask;
10863 queue_v = (const void *)item->spec;
10866 txq = mlx5_txq_get(dev, queue_v->queue);
10869 queue = txq->obj->sq->id;
10870 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
10871 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
10872 queue & queue_m->queue);
10873 mlx5_txq_release(dev, queue_v->queue);
10877 * Set the hash fields according to the @p flow information.
10879 * @param[in] dev_flow
10880 * Pointer to the mlx5_flow.
10881 * @param[in] rss_desc
10882 * Pointer to the mlx5_flow_rss_desc.
10885 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10886 struct mlx5_flow_rss_desc *rss_desc)
10888 uint64_t items = dev_flow->handle->layers;
10890 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10892 dev_flow->hash_fields = 0;
10893 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10894 if (rss_desc->level >= 2) {
10895 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
10899 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10900 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10901 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10902 if (rss_types & ETH_RSS_L3_SRC_ONLY)
10903 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10904 else if (rss_types & ETH_RSS_L3_DST_ONLY)
10905 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10907 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10909 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10910 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10911 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10912 if (rss_types & ETH_RSS_L3_SRC_ONLY)
10913 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10914 else if (rss_types & ETH_RSS_L3_DST_ONLY)
10915 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10917 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10920 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10921 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10922 if (rss_types & ETH_RSS_UDP) {
10923 if (rss_types & ETH_RSS_L4_SRC_ONLY)
10924 dev_flow->hash_fields |=
10925 IBV_RX_HASH_SRC_PORT_UDP;
10926 else if (rss_types & ETH_RSS_L4_DST_ONLY)
10927 dev_flow->hash_fields |=
10928 IBV_RX_HASH_DST_PORT_UDP;
10930 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10932 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10933 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10934 if (rss_types & ETH_RSS_TCP) {
10935 if (rss_types & ETH_RSS_L4_SRC_ONLY)
10936 dev_flow->hash_fields |=
10937 IBV_RX_HASH_SRC_PORT_TCP;
10938 else if (rss_types & ETH_RSS_L4_DST_ONLY)
10939 dev_flow->hash_fields |=
10940 IBV_RX_HASH_DST_PORT_TCP;
10942 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10948 * Prepare an Rx Hash queue.
10951 * Pointer to Ethernet device.
10952 * @param[in] dev_flow
10953 * Pointer to the mlx5_flow.
10954 * @param[in] rss_desc
10955 * Pointer to the mlx5_flow_rss_desc.
10956 * @param[out] hrxq_idx
10957 * Hash Rx queue index.
10960 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
10962 static struct mlx5_hrxq *
10963 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
10964 struct mlx5_flow *dev_flow,
10965 struct mlx5_flow_rss_desc *rss_desc,
10966 uint32_t *hrxq_idx)
10968 struct mlx5_priv *priv = dev->data->dev_private;
10969 struct mlx5_flow_handle *dh = dev_flow->handle;
10970 struct mlx5_hrxq *hrxq;
10972 MLX5_ASSERT(rss_desc->queue_num);
10973 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10974 rss_desc->hash_fields = dev_flow->hash_fields;
10975 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10976 rss_desc->shared_rss = 0;
10977 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10980 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10986 * Release sample sub action resource.
10988 * @param[in, out] dev
10989 * Pointer to rte_eth_dev structure.
10990 * @param[in] act_res
10991 * Pointer to sample sub action resource.
10994 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10995 struct mlx5_flow_sub_actions_idx *act_res)
10997 if (act_res->rix_hrxq) {
10998 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10999 act_res->rix_hrxq = 0;
11001 if (act_res->rix_encap_decap) {
11002 flow_dv_encap_decap_resource_release(dev,
11003 act_res->rix_encap_decap);
11004 act_res->rix_encap_decap = 0;
11006 if (act_res->rix_port_id_action) {
11007 flow_dv_port_id_action_resource_release(dev,
11008 act_res->rix_port_id_action);
11009 act_res->rix_port_id_action = 0;
11011 if (act_res->rix_tag) {
11012 flow_dv_tag_release(dev, act_res->rix_tag);
11013 act_res->rix_tag = 0;
11015 if (act_res->rix_jump) {
11016 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11017 act_res->rix_jump = 0;
11022 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11023 struct mlx5_list_entry *entry, void *cb_ctx)
11025 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11026 struct rte_eth_dev *dev = ctx->dev;
11027 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11028 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11032 if (ctx_resource->ratio == resource->ratio &&
11033 ctx_resource->ft_type == resource->ft_type &&
11034 ctx_resource->ft_id == resource->ft_id &&
11035 ctx_resource->set_action == resource->set_action &&
11036 !memcmp((void *)&ctx_resource->sample_act,
11037 (void *)&resource->sample_act,
11038 sizeof(struct mlx5_flow_sub_actions_list))) {
11040 * Existing sample action should release the prepared
11041 * sub-actions reference counter.
11043 flow_dv_sample_sub_actions_release(dev,
11044 &ctx_resource->sample_idx);
11050 struct mlx5_list_entry *
11051 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11053 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11054 struct rte_eth_dev *dev = ctx->dev;
11055 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11056 void **sample_dv_actions = ctx_resource->sub_actions;
11057 struct mlx5_flow_dv_sample_resource *resource;
11058 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11059 struct mlx5_priv *priv = dev->data->dev_private;
11060 struct mlx5_dev_ctx_shared *sh = priv->sh;
11061 struct mlx5_flow_tbl_resource *tbl;
11063 const uint32_t next_ft_step = 1;
11064 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11065 uint8_t is_egress = 0;
11066 uint8_t is_transfer = 0;
11067 struct rte_flow_error *error = ctx->error;
11069 /* Register new sample resource. */
11070 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11072 rte_flow_error_set(error, ENOMEM,
11073 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11075 "cannot allocate resource memory");
11078 *resource = *ctx_resource;
11079 /* Create normal path table level */
11080 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11082 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11084 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11085 is_egress, is_transfer,
11086 true, NULL, 0, 0, 0, error);
11088 rte_flow_error_set(error, ENOMEM,
11089 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11091 "fail to create normal path table "
11095 resource->normal_path_tbl = tbl;
11096 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11097 if (!sh->default_miss_action) {
11098 rte_flow_error_set(error, ENOMEM,
11099 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11101 "default miss action was not "
11105 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11106 sh->default_miss_action;
11108 /* Create a DR sample action */
11109 sampler_attr.sample_ratio = resource->ratio;
11110 sampler_attr.default_next_table = tbl->obj;
11111 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11112 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11113 &sample_dv_actions[0];
11114 sampler_attr.action = resource->set_action;
11115 if (mlx5_os_flow_dr_create_flow_action_sampler
11116 (&sampler_attr, &resource->verbs_action)) {
11117 rte_flow_error_set(error, ENOMEM,
11118 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11119 NULL, "cannot create sample action");
11122 resource->idx = idx;
11123 resource->dev = dev;
11124 return &resource->entry;
11126 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11127 flow_dv_sample_sub_actions_release(dev,
11128 &resource->sample_idx);
11129 if (resource->normal_path_tbl)
11130 flow_dv_tbl_resource_release(MLX5_SH(dev),
11131 resource->normal_path_tbl);
11132 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11137 struct mlx5_list_entry *
11138 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11139 struct mlx5_list_entry *entry __rte_unused,
11142 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11143 struct rte_eth_dev *dev = ctx->dev;
11144 struct mlx5_flow_dv_sample_resource *resource;
11145 struct mlx5_priv *priv = dev->data->dev_private;
11146 struct mlx5_dev_ctx_shared *sh = priv->sh;
11149 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11151 rte_flow_error_set(ctx->error, ENOMEM,
11152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11154 "cannot allocate resource memory");
11157 memcpy(resource, entry, sizeof(*resource));
11158 resource->idx = idx;
11159 resource->dev = dev;
11160 return &resource->entry;
11164 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11165 struct mlx5_list_entry *entry)
11167 struct mlx5_flow_dv_sample_resource *resource =
11168 container_of(entry, typeof(*resource), entry);
11169 struct rte_eth_dev *dev = resource->dev;
11170 struct mlx5_priv *priv = dev->data->dev_private;
11172 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11176 * Find existing sample resource or create and register a new one.
11178 * @param[in, out] dev
11179 * Pointer to rte_eth_dev structure.
11181 * Pointer to sample resource reference.
11182 * @parm[in, out] dev_flow
11183 * Pointer to the dev_flow.
11184 * @param[out] error
11185 * pointer to error structure.
11188 * 0 on success otherwise -errno and errno is set.
11191 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11192 struct mlx5_flow_dv_sample_resource *ref,
11193 struct mlx5_flow *dev_flow,
11194 struct rte_flow_error *error)
11196 struct mlx5_flow_dv_sample_resource *resource;
11197 struct mlx5_list_entry *entry;
11198 struct mlx5_priv *priv = dev->data->dev_private;
11199 struct mlx5_flow_cb_ctx ctx = {
11205 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11208 resource = container_of(entry, typeof(*resource), entry);
11209 dev_flow->handle->dvh.rix_sample = resource->idx;
11210 dev_flow->dv.sample_res = resource;
11215 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11216 struct mlx5_list_entry *entry, void *cb_ctx)
11218 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11219 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11220 struct rte_eth_dev *dev = ctx->dev;
11221 struct mlx5_flow_dv_dest_array_resource *resource =
11222 container_of(entry, typeof(*resource), entry);
11225 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11226 ctx_resource->ft_type == resource->ft_type &&
11227 !memcmp((void *)resource->sample_act,
11228 (void *)ctx_resource->sample_act,
11229 (ctx_resource->num_of_dest *
11230 sizeof(struct mlx5_flow_sub_actions_list)))) {
11232 * Existing sample action should release the prepared
11233 * sub-actions reference counter.
11235 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11236 flow_dv_sample_sub_actions_release(dev,
11237 &ctx_resource->sample_idx[idx]);
11243 struct mlx5_list_entry *
11244 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11246 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11247 struct rte_eth_dev *dev = ctx->dev;
11248 struct mlx5_flow_dv_dest_array_resource *resource;
11249 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11250 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11251 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11252 struct mlx5_priv *priv = dev->data->dev_private;
11253 struct mlx5_dev_ctx_shared *sh = priv->sh;
11254 struct mlx5_flow_sub_actions_list *sample_act;
11255 struct mlx5dv_dr_domain *domain;
11256 uint32_t idx = 0, res_idx = 0;
11257 struct rte_flow_error *error = ctx->error;
11258 uint64_t action_flags;
11261 /* Register new destination array resource. */
11262 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11265 rte_flow_error_set(error, ENOMEM,
11266 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11268 "cannot allocate resource memory");
11271 *resource = *ctx_resource;
11272 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11273 domain = sh->fdb_domain;
11274 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11275 domain = sh->rx_domain;
11277 domain = sh->tx_domain;
11278 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11279 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11280 mlx5_malloc(MLX5_MEM_ZERO,
11281 sizeof(struct mlx5dv_dr_action_dest_attr),
11283 if (!dest_attr[idx]) {
11284 rte_flow_error_set(error, ENOMEM,
11285 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11287 "cannot allocate resource memory");
11290 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11291 sample_act = &ctx_resource->sample_act[idx];
11292 action_flags = sample_act->action_flags;
11293 switch (action_flags) {
11294 case MLX5_FLOW_ACTION_QUEUE:
11295 dest_attr[idx]->dest = sample_act->dr_queue_action;
11297 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11298 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11299 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11300 dest_attr[idx]->dest_reformat->reformat =
11301 sample_act->dr_encap_action;
11302 dest_attr[idx]->dest_reformat->dest =
11303 sample_act->dr_port_id_action;
11305 case MLX5_FLOW_ACTION_PORT_ID:
11306 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11308 case MLX5_FLOW_ACTION_JUMP:
11309 dest_attr[idx]->dest = sample_act->dr_jump_action;
11312 rte_flow_error_set(error, EINVAL,
11313 RTE_FLOW_ERROR_TYPE_ACTION,
11315 "unsupported actions type");
11319 /* create a dest array actioin */
11320 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11322 resource->num_of_dest,
11324 &resource->action);
11326 rte_flow_error_set(error, ENOMEM,
11327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11329 "cannot create destination array action");
11332 resource->idx = res_idx;
11333 resource->dev = dev;
11334 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11335 mlx5_free(dest_attr[idx]);
11336 return &resource->entry;
11338 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11339 flow_dv_sample_sub_actions_release(dev,
11340 &resource->sample_idx[idx]);
11341 if (dest_attr[idx])
11342 mlx5_free(dest_attr[idx]);
11344 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11348 struct mlx5_list_entry *
11349 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11350 struct mlx5_list_entry *entry __rte_unused,
11353 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11354 struct rte_eth_dev *dev = ctx->dev;
11355 struct mlx5_flow_dv_dest_array_resource *resource;
11356 struct mlx5_priv *priv = dev->data->dev_private;
11357 struct mlx5_dev_ctx_shared *sh = priv->sh;
11358 uint32_t res_idx = 0;
11359 struct rte_flow_error *error = ctx->error;
11361 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11364 rte_flow_error_set(error, ENOMEM,
11365 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11367 "cannot allocate dest-array memory");
11370 memcpy(resource, entry, sizeof(*resource));
11371 resource->idx = res_idx;
11372 resource->dev = dev;
11373 return &resource->entry;
11377 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11378 struct mlx5_list_entry *entry)
11380 struct mlx5_flow_dv_dest_array_resource *resource =
11381 container_of(entry, typeof(*resource), entry);
11382 struct rte_eth_dev *dev = resource->dev;
11383 struct mlx5_priv *priv = dev->data->dev_private;
11385 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11389 * Find existing destination array resource or create and register a new one.
11391 * @param[in, out] dev
11392 * Pointer to rte_eth_dev structure.
11394 * Pointer to destination array resource reference.
11395 * @parm[in, out] dev_flow
11396 * Pointer to the dev_flow.
11397 * @param[out] error
11398 * pointer to error structure.
11401 * 0 on success otherwise -errno and errno is set.
11404 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11405 struct mlx5_flow_dv_dest_array_resource *ref,
11406 struct mlx5_flow *dev_flow,
11407 struct rte_flow_error *error)
11409 struct mlx5_flow_dv_dest_array_resource *resource;
11410 struct mlx5_priv *priv = dev->data->dev_private;
11411 struct mlx5_list_entry *entry;
11412 struct mlx5_flow_cb_ctx ctx = {
11418 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11421 resource = container_of(entry, typeof(*resource), entry);
11422 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11423 dev_flow->dv.dest_array_res = resource;
11428 * Convert Sample action to DV specification.
11431 * Pointer to rte_eth_dev structure.
11432 * @param[in] action
11433 * Pointer to sample action structure.
11434 * @param[in, out] dev_flow
11435 * Pointer to the mlx5_flow.
11437 * Pointer to the flow attributes.
11438 * @param[in, out] num_of_dest
11439 * Pointer to the num of destination.
11440 * @param[in, out] sample_actions
11441 * Pointer to sample actions list.
11442 * @param[in, out] res
11443 * Pointer to sample resource.
11444 * @param[out] error
11445 * Pointer to the error structure.
11448 * 0 on success, a negative errno value otherwise and rte_errno is set.
11451 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11452 const struct rte_flow_action_sample *action,
11453 struct mlx5_flow *dev_flow,
11454 const struct rte_flow_attr *attr,
11455 uint32_t *num_of_dest,
11456 void **sample_actions,
11457 struct mlx5_flow_dv_sample_resource *res,
11458 struct rte_flow_error *error)
11460 struct mlx5_priv *priv = dev->data->dev_private;
11461 const struct rte_flow_action *sub_actions;
11462 struct mlx5_flow_sub_actions_list *sample_act;
11463 struct mlx5_flow_sub_actions_idx *sample_idx;
11464 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11465 struct rte_flow *flow = dev_flow->flow;
11466 struct mlx5_flow_rss_desc *rss_desc;
11467 uint64_t action_flags = 0;
11470 rss_desc = &wks->rss_desc;
11471 sample_act = &res->sample_act;
11472 sample_idx = &res->sample_idx;
11473 res->ratio = action->ratio;
11474 sub_actions = action->actions;
11475 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11476 int type = sub_actions->type;
11477 uint32_t pre_rix = 0;
11480 case RTE_FLOW_ACTION_TYPE_QUEUE:
11482 const struct rte_flow_action_queue *queue;
11483 struct mlx5_hrxq *hrxq;
11486 queue = sub_actions->conf;
11487 rss_desc->queue_num = 1;
11488 rss_desc->queue[0] = queue->index;
11489 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11490 rss_desc, &hrxq_idx);
11492 return rte_flow_error_set
11494 RTE_FLOW_ERROR_TYPE_ACTION,
11496 "cannot create fate queue");
11497 sample_act->dr_queue_action = hrxq->action;
11498 sample_idx->rix_hrxq = hrxq_idx;
11499 sample_actions[sample_act->actions_num++] =
11502 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11503 if (action_flags & MLX5_FLOW_ACTION_MARK)
11504 dev_flow->handle->rix_hrxq = hrxq_idx;
11505 dev_flow->handle->fate_action =
11506 MLX5_FLOW_FATE_QUEUE;
11509 case RTE_FLOW_ACTION_TYPE_RSS:
11511 struct mlx5_hrxq *hrxq;
11513 const struct rte_flow_action_rss *rss;
11514 const uint8_t *rss_key;
11516 rss = sub_actions->conf;
11517 memcpy(rss_desc->queue, rss->queue,
11518 rss->queue_num * sizeof(uint16_t));
11519 rss_desc->queue_num = rss->queue_num;
11520 /* NULL RSS key indicates default RSS key. */
11521 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11522 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11524 * rss->level and rss.types should be set in advance
11525 * when expanding items for RSS.
11527 flow_dv_hashfields_set(dev_flow, rss_desc);
11528 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11529 rss_desc, &hrxq_idx);
11531 return rte_flow_error_set
11533 RTE_FLOW_ERROR_TYPE_ACTION,
11535 "cannot create fate queue");
11536 sample_act->dr_queue_action = hrxq->action;
11537 sample_idx->rix_hrxq = hrxq_idx;
11538 sample_actions[sample_act->actions_num++] =
11541 action_flags |= MLX5_FLOW_ACTION_RSS;
11542 if (action_flags & MLX5_FLOW_ACTION_MARK)
11543 dev_flow->handle->rix_hrxq = hrxq_idx;
11544 dev_flow->handle->fate_action =
11545 MLX5_FLOW_FATE_QUEUE;
11548 case RTE_FLOW_ACTION_TYPE_MARK:
11550 uint32_t tag_be = mlx5_flow_mark_set
11551 (((const struct rte_flow_action_mark *)
11552 (sub_actions->conf))->id);
11554 dev_flow->handle->mark = 1;
11555 pre_rix = dev_flow->handle->dvh.rix_tag;
11556 /* Save the mark resource before sample */
11557 pre_r = dev_flow->dv.tag_resource;
11558 if (flow_dv_tag_resource_register(dev, tag_be,
11561 MLX5_ASSERT(dev_flow->dv.tag_resource);
11562 sample_act->dr_tag_action =
11563 dev_flow->dv.tag_resource->action;
11564 sample_idx->rix_tag =
11565 dev_flow->handle->dvh.rix_tag;
11566 sample_actions[sample_act->actions_num++] =
11567 sample_act->dr_tag_action;
11568 /* Recover the mark resource after sample */
11569 dev_flow->dv.tag_resource = pre_r;
11570 dev_flow->handle->dvh.rix_tag = pre_rix;
11571 action_flags |= MLX5_FLOW_ACTION_MARK;
11574 case RTE_FLOW_ACTION_TYPE_COUNT:
11576 if (!flow->counter) {
11578 flow_dv_translate_create_counter(dev,
11579 dev_flow, sub_actions->conf,
11581 if (!flow->counter)
11582 return rte_flow_error_set
11584 RTE_FLOW_ERROR_TYPE_ACTION,
11586 "cannot create counter"
11589 sample_act->dr_cnt_action =
11590 (flow_dv_counter_get_by_idx(dev,
11591 flow->counter, NULL))->action;
11592 sample_actions[sample_act->actions_num++] =
11593 sample_act->dr_cnt_action;
11594 action_flags |= MLX5_FLOW_ACTION_COUNT;
11597 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11599 struct mlx5_flow_dv_port_id_action_resource
11601 uint32_t port_id = 0;
11603 memset(&port_id_resource, 0, sizeof(port_id_resource));
11604 /* Save the port id resource before sample */
11605 pre_rix = dev_flow->handle->rix_port_id_action;
11606 pre_r = dev_flow->dv.port_id_action;
11607 if (flow_dv_translate_action_port_id(dev, sub_actions,
11610 port_id_resource.port_id = port_id;
11611 if (flow_dv_port_id_action_resource_register
11612 (dev, &port_id_resource, dev_flow, error))
11614 sample_act->dr_port_id_action =
11615 dev_flow->dv.port_id_action->action;
11616 sample_idx->rix_port_id_action =
11617 dev_flow->handle->rix_port_id_action;
11618 sample_actions[sample_act->actions_num++] =
11619 sample_act->dr_port_id_action;
11620 /* Recover the port id resource after sample */
11621 dev_flow->dv.port_id_action = pre_r;
11622 dev_flow->handle->rix_port_id_action = pre_rix;
11624 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11627 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11628 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11629 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11630 /* Save the encap resource before sample */
11631 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11632 pre_r = dev_flow->dv.encap_decap;
11633 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11638 sample_act->dr_encap_action =
11639 dev_flow->dv.encap_decap->action;
11640 sample_idx->rix_encap_decap =
11641 dev_flow->handle->dvh.rix_encap_decap;
11642 sample_actions[sample_act->actions_num++] =
11643 sample_act->dr_encap_action;
11644 /* Recover the encap resource after sample */
11645 dev_flow->dv.encap_decap = pre_r;
11646 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11647 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11650 return rte_flow_error_set(error, EINVAL,
11651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11653 "Not support for sampler action");
11656 sample_act->action_flags = action_flags;
11657 res->ft_id = dev_flow->dv.group;
11658 if (attr->transfer) {
11660 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11661 uint64_t set_action;
11662 } action_ctx = { .set_action = 0 };
11664 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11665 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11666 MLX5_MODIFICATION_TYPE_SET);
11667 MLX5_SET(set_action_in, action_ctx.action_in, field,
11668 MLX5_MODI_META_REG_C_0);
11669 MLX5_SET(set_action_in, action_ctx.action_in, data,
11670 priv->vport_meta_tag);
11671 res->set_action = action_ctx.set_action;
11672 } else if (attr->ingress) {
11673 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11675 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11681 * Convert Sample action to DV specification.
11684 * Pointer to rte_eth_dev structure.
11685 * @param[in, out] dev_flow
11686 * Pointer to the mlx5_flow.
11687 * @param[in] num_of_dest
11688 * The num of destination.
11689 * @param[in, out] res
11690 * Pointer to sample resource.
11691 * @param[in, out] mdest_res
11692 * Pointer to destination array resource.
11693 * @param[in] sample_actions
11694 * Pointer to sample path actions list.
11695 * @param[in] action_flags
11696 * Holds the actions detected until now.
11697 * @param[out] error
11698 * Pointer to the error structure.
11701 * 0 on success, a negative errno value otherwise and rte_errno is set.
11704 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11705 struct mlx5_flow *dev_flow,
11706 uint32_t num_of_dest,
11707 struct mlx5_flow_dv_sample_resource *res,
11708 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11709 void **sample_actions,
11710 uint64_t action_flags,
11711 struct rte_flow_error *error)
11713 /* update normal path action resource into last index of array */
11714 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11715 struct mlx5_flow_sub_actions_list *sample_act =
11716 &mdest_res->sample_act[dest_index];
11717 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11718 struct mlx5_flow_rss_desc *rss_desc;
11719 uint32_t normal_idx = 0;
11720 struct mlx5_hrxq *hrxq;
11724 rss_desc = &wks->rss_desc;
11725 if (num_of_dest > 1) {
11726 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11727 /* Handle QP action for mirroring */
11728 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11729 rss_desc, &hrxq_idx);
11731 return rte_flow_error_set
11733 RTE_FLOW_ERROR_TYPE_ACTION,
11735 "cannot create rx queue");
11737 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11738 sample_act->dr_queue_action = hrxq->action;
11739 if (action_flags & MLX5_FLOW_ACTION_MARK)
11740 dev_flow->handle->rix_hrxq = hrxq_idx;
11741 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11743 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11745 mdest_res->sample_idx[dest_index].rix_encap_decap =
11746 dev_flow->handle->dvh.rix_encap_decap;
11747 sample_act->dr_encap_action =
11748 dev_flow->dv.encap_decap->action;
11749 dev_flow->handle->dvh.rix_encap_decap = 0;
11751 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11753 mdest_res->sample_idx[dest_index].rix_port_id_action =
11754 dev_flow->handle->rix_port_id_action;
11755 sample_act->dr_port_id_action =
11756 dev_flow->dv.port_id_action->action;
11757 dev_flow->handle->rix_port_id_action = 0;
11759 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11761 mdest_res->sample_idx[dest_index].rix_jump =
11762 dev_flow->handle->rix_jump;
11763 sample_act->dr_jump_action =
11764 dev_flow->dv.jump->action;
11765 dev_flow->handle->rix_jump = 0;
11767 sample_act->actions_num = normal_idx;
11768 /* update sample action resource into first index of array */
11769 mdest_res->ft_type = res->ft_type;
11770 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11771 sizeof(struct mlx5_flow_sub_actions_idx));
11772 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11773 sizeof(struct mlx5_flow_sub_actions_list));
11774 mdest_res->num_of_dest = num_of_dest;
11775 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11777 return rte_flow_error_set(error, EINVAL,
11778 RTE_FLOW_ERROR_TYPE_ACTION,
11779 NULL, "can't create sample "
11782 res->sub_actions = sample_actions;
11783 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11784 return rte_flow_error_set(error, EINVAL,
11785 RTE_FLOW_ERROR_TYPE_ACTION,
11787 "can't create sample action");
11793 * Remove an ASO age action from age actions list.
11796 * Pointer to the Ethernet device structure.
11798 * Pointer to the aso age action handler.
11801 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11802 struct mlx5_aso_age_action *age)
11804 struct mlx5_age_info *age_info;
11805 struct mlx5_age_param *age_param = &age->age_params;
11806 struct mlx5_priv *priv = dev->data->dev_private;
11807 uint16_t expected = AGE_CANDIDATE;
11809 age_info = GET_PORT_AGE_INFO(priv);
11810 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11811 AGE_FREE, false, __ATOMIC_RELAXED,
11812 __ATOMIC_RELAXED)) {
11814 * We need the lock even it is age timeout,
11815 * since age action may still in process.
11817 rte_spinlock_lock(&age_info->aged_sl);
11818 LIST_REMOVE(age, next);
11819 rte_spinlock_unlock(&age_info->aged_sl);
11820 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11825 * Release an ASO age action.
11828 * Pointer to the Ethernet device structure.
11829 * @param[in] age_idx
11830 * Index of ASO age action to release.
11832 * True if the release operation is during flow destroy operation.
11833 * False if the release operation is during action destroy operation.
11836 * 0 when age action was removed, otherwise the number of references.
11839 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11841 struct mlx5_priv *priv = dev->data->dev_private;
11842 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11843 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11844 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11847 flow_dv_aso_age_remove_from_age(dev, age);
11848 rte_spinlock_lock(&mng->free_sl);
11849 LIST_INSERT_HEAD(&mng->free, age, next);
11850 rte_spinlock_unlock(&mng->free_sl);
11856 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11859 * Pointer to the Ethernet device structure.
11862 * 0 on success, otherwise negative errno value and rte_errno is set.
11865 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11867 struct mlx5_priv *priv = dev->data->dev_private;
11868 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11869 void *old_pools = mng->pools;
11870 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11871 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11872 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11875 rte_errno = ENOMEM;
11879 memcpy(pools, old_pools,
11880 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11881 mlx5_free(old_pools);
11883 /* First ASO flow hit allocation - starting ASO data-path. */
11884 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11892 mng->pools = pools;
11897 * Create and initialize a new ASO aging pool.
11900 * Pointer to the Ethernet device structure.
11901 * @param[out] age_free
11902 * Where to put the pointer of a new age action.
11905 * The age actions pool pointer and @p age_free is set on success,
11906 * NULL otherwise and rte_errno is set.
11908 static struct mlx5_aso_age_pool *
11909 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11910 struct mlx5_aso_age_action **age_free)
11912 struct mlx5_priv *priv = dev->data->dev_private;
11913 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11914 struct mlx5_aso_age_pool *pool = NULL;
11915 struct mlx5_devx_obj *obj = NULL;
11918 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
11921 rte_errno = ENODATA;
11922 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11925 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11927 claim_zero(mlx5_devx_cmd_destroy(obj));
11928 rte_errno = ENOMEM;
11931 pool->flow_hit_aso_obj = obj;
11932 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
11933 rte_spinlock_lock(&mng->resize_sl);
11934 pool->index = mng->next;
11935 /* Resize pools array if there is no room for the new pool in it. */
11936 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
11937 claim_zero(mlx5_devx_cmd_destroy(obj));
11939 rte_spinlock_unlock(&mng->resize_sl);
11942 mng->pools[pool->index] = pool;
11944 rte_spinlock_unlock(&mng->resize_sl);
11945 /* Assign the first action in the new pool, the rest go to free list. */
11946 *age_free = &pool->actions[0];
11947 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
11948 pool->actions[i].offset = i;
11949 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
11955 * Allocate a ASO aging bit.
11958 * Pointer to the Ethernet device structure.
11959 * @param[out] error
11960 * Pointer to the error structure.
11963 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
11966 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
11968 struct mlx5_priv *priv = dev->data->dev_private;
11969 const struct mlx5_aso_age_pool *pool;
11970 struct mlx5_aso_age_action *age_free = NULL;
11971 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11974 /* Try to get the next free age action bit. */
11975 rte_spinlock_lock(&mng->free_sl);
11976 age_free = LIST_FIRST(&mng->free);
11978 LIST_REMOVE(age_free, next);
11979 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
11980 rte_spinlock_unlock(&mng->free_sl);
11981 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
11982 NULL, "failed to create ASO age pool");
11983 return 0; /* 0 is an error. */
11985 rte_spinlock_unlock(&mng->free_sl);
11986 pool = container_of
11987 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
11988 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
11990 if (!age_free->dr_action) {
11991 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
11995 rte_flow_error_set(error, rte_errno,
11996 RTE_FLOW_ERROR_TYPE_ACTION,
11997 NULL, "failed to get reg_c "
11998 "for ASO flow hit");
11999 return 0; /* 0 is an error. */
12001 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12002 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12003 (priv->sh->rx_domain,
12004 pool->flow_hit_aso_obj->obj, age_free->offset,
12005 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12006 (reg_c - REG_C_0));
12007 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12008 if (!age_free->dr_action) {
12010 rte_spinlock_lock(&mng->free_sl);
12011 LIST_INSERT_HEAD(&mng->free, age_free, next);
12012 rte_spinlock_unlock(&mng->free_sl);
12013 rte_flow_error_set(error, rte_errno,
12014 RTE_FLOW_ERROR_TYPE_ACTION,
12015 NULL, "failed to create ASO "
12016 "flow hit action");
12017 return 0; /* 0 is an error. */
12020 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12021 return pool->index | ((age_free->offset + 1) << 16);
12025 * Initialize flow ASO age parameters.
12028 * Pointer to rte_eth_dev structure.
12029 * @param[in] age_idx
12030 * Index of ASO age action.
12031 * @param[in] context
12032 * Pointer to flow counter age context.
12033 * @param[in] timeout
12034 * Aging timeout in seconds.
12038 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12043 struct mlx5_aso_age_action *aso_age;
12045 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12046 MLX5_ASSERT(aso_age);
12047 aso_age->age_params.context = context;
12048 aso_age->age_params.timeout = timeout;
12049 aso_age->age_params.port_id = dev->data->port_id;
12050 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12052 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12057 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12058 const struct rte_flow_item_integrity *value,
12059 void *headers_m, void *headers_v)
12062 /* application l4_ok filter aggregates all hardware l4 filters
12063 * therefore hw l4_checksum_ok must be implicitly added here.
12065 struct rte_flow_item_integrity local_item;
12067 local_item.l4_csum_ok = 1;
12068 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
12069 local_item.l4_csum_ok);
12070 if (value->l4_ok) {
12071 /* application l4_ok = 1 matches sets both hw flags
12072 * l4_ok and l4_checksum_ok flags to 1.
12074 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12075 l4_checksum_ok, local_item.l4_csum_ok);
12076 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok,
12078 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok,
12081 /* application l4_ok = 0 matches on hw flag
12082 * l4_checksum_ok = 0 only.
12084 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12085 l4_checksum_ok, 0);
12087 } else if (mask->l4_csum_ok) {
12088 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
12090 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12091 value->l4_csum_ok);
12096 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12097 const struct rte_flow_item_integrity *value,
12098 void *headers_m, void *headers_v,
12102 /* application l3_ok filter aggregates all hardware l3 filters
12103 * therefore hw ipv4_checksum_ok must be implicitly added here.
12105 struct rte_flow_item_integrity local_item;
12107 local_item.ipv4_csum_ok = !!is_ipv4;
12108 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
12109 local_item.ipv4_csum_ok);
12110 if (value->l3_ok) {
12111 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12112 ipv4_checksum_ok, local_item.ipv4_csum_ok);
12113 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok,
12115 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12118 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12119 ipv4_checksum_ok, 0);
12121 } else if (mask->ipv4_csum_ok) {
12122 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
12123 mask->ipv4_csum_ok);
12124 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12125 value->ipv4_csum_ok);
12130 flow_dv_translate_item_integrity(void *matcher, void *key,
12131 const struct rte_flow_item *head_item,
12132 const struct rte_flow_item *integrity_item)
12134 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12135 const struct rte_flow_item_integrity *value = integrity_item->spec;
12136 const struct rte_flow_item *tunnel_item, *end_item, *item;
12139 uint32_t l3_protocol;
12144 mask = &rte_flow_item_integrity_mask;
12145 if (value->level > 1) {
12146 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12148 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12150 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12152 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12154 tunnel_item = mlx5_flow_find_tunnel_item(head_item);
12155 if (value->level > 1) {
12156 /* tunnel item was verified during the item validation */
12157 item = tunnel_item;
12158 end_item = mlx5_find_end_item(tunnel_item);
12161 end_item = tunnel_item ? tunnel_item :
12162 mlx5_find_end_item(integrity_item);
12164 l3_protocol = mask->l3_ok ?
12165 mlx5_flow_locate_proto_l3(&item, end_item) : 0;
12166 flow_dv_translate_integrity_l3(mask, value, headers_m, headers_v,
12167 l3_protocol == RTE_ETHER_TYPE_IPV4);
12168 flow_dv_translate_integrity_l4(mask, value, headers_m, headers_v);
12172 * Prepares DV flow counter with aging configuration.
12173 * Gets it by index when exists, creates a new one when doesn't.
12176 * Pointer to rte_eth_dev structure.
12177 * @param[in] dev_flow
12178 * Pointer to the mlx5_flow.
12179 * @param[in, out] flow
12180 * Pointer to the sub flow.
12182 * Pointer to the counter action configuration.
12184 * Pointer to the aging action configuration.
12185 * @param[out] error
12186 * Pointer to the error structure.
12189 * Pointer to the counter, NULL otherwise.
12191 static struct mlx5_flow_counter *
12192 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12193 struct mlx5_flow *dev_flow,
12194 struct rte_flow *flow,
12195 const struct rte_flow_action_count *count,
12196 const struct rte_flow_action_age *age,
12197 struct rte_flow_error *error)
12199 if (!flow->counter) {
12200 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12202 if (!flow->counter) {
12203 rte_flow_error_set(error, rte_errno,
12204 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12205 "cannot create counter object.");
12209 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12213 * Release an ASO CT action by its own device.
12216 * Pointer to the Ethernet device structure.
12218 * Index of ASO CT action to release.
12221 * 0 when CT action was removed, otherwise the number of references.
12224 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12226 struct mlx5_priv *priv = dev->data->dev_private;
12227 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12229 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12230 enum mlx5_aso_ct_state state =
12231 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12233 /* Cannot release when CT is in the ASO SQ. */
12234 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12236 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12238 if (ct->dr_action_orig) {
12239 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12240 claim_zero(mlx5_glue->destroy_flow_action
12241 (ct->dr_action_orig));
12243 ct->dr_action_orig = NULL;
12245 if (ct->dr_action_rply) {
12246 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12247 claim_zero(mlx5_glue->destroy_flow_action
12248 (ct->dr_action_rply));
12250 ct->dr_action_rply = NULL;
12252 /* Clear the state to free, no need in 1st allocation. */
12253 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12254 rte_spinlock_lock(&mng->ct_sl);
12255 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12256 rte_spinlock_unlock(&mng->ct_sl);
12262 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx)
12264 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12265 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12266 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12269 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12270 if (dev->data->dev_started != 1)
12272 return flow_dv_aso_ct_dev_release(owndev, idx);
12276 * Resize the ASO CT pools array by 64 pools.
12279 * Pointer to the Ethernet device structure.
12282 * 0 on success, otherwise negative errno value and rte_errno is set.
12285 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12287 struct mlx5_priv *priv = dev->data->dev_private;
12288 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12289 void *old_pools = mng->pools;
12290 /* Magic number now, need a macro. */
12291 uint32_t resize = mng->n + 64;
12292 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12293 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12296 rte_errno = ENOMEM;
12299 rte_rwlock_write_lock(&mng->resize_rwl);
12300 /* ASO SQ/QP was already initialized in the startup. */
12302 /* Realloc could be an alternative choice. */
12303 rte_memcpy(pools, old_pools,
12304 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12305 mlx5_free(old_pools);
12308 mng->pools = pools;
12309 rte_rwlock_write_unlock(&mng->resize_rwl);
12314 * Create and initialize a new ASO CT pool.
12317 * Pointer to the Ethernet device structure.
12318 * @param[out] ct_free
12319 * Where to put the pointer of a new CT action.
12322 * The CT actions pool pointer and @p ct_free is set on success,
12323 * NULL otherwise and rte_errno is set.
12325 static struct mlx5_aso_ct_pool *
12326 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12327 struct mlx5_aso_ct_action **ct_free)
12329 struct mlx5_priv *priv = dev->data->dev_private;
12330 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12331 struct mlx5_aso_ct_pool *pool = NULL;
12332 struct mlx5_devx_obj *obj = NULL;
12334 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12336 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->ctx,
12337 priv->sh->pdn, log_obj_size);
12339 rte_errno = ENODATA;
12340 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12343 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12345 rte_errno = ENOMEM;
12346 claim_zero(mlx5_devx_cmd_destroy(obj));
12349 pool->devx_obj = obj;
12350 pool->index = mng->next;
12351 /* Resize pools array if there is no room for the new pool in it. */
12352 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12353 claim_zero(mlx5_devx_cmd_destroy(obj));
12357 mng->pools[pool->index] = pool;
12359 /* Assign the first action in the new pool, the rest go to free list. */
12360 *ct_free = &pool->actions[0];
12361 /* Lock outside, the list operation is safe here. */
12362 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12363 /* refcnt is 0 when allocating the memory. */
12364 pool->actions[i].offset = i;
12365 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12371 * Allocate a ASO CT action from free list.
12374 * Pointer to the Ethernet device structure.
12375 * @param[out] error
12376 * Pointer to the error structure.
12379 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12382 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12384 struct mlx5_priv *priv = dev->data->dev_private;
12385 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12386 struct mlx5_aso_ct_action *ct = NULL;
12387 struct mlx5_aso_ct_pool *pool;
12392 if (!priv->config.devx) {
12393 rte_errno = ENOTSUP;
12396 /* Get a free CT action, if no, a new pool will be created. */
12397 rte_spinlock_lock(&mng->ct_sl);
12398 ct = LIST_FIRST(&mng->free_cts);
12400 LIST_REMOVE(ct, next);
12401 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12402 rte_spinlock_unlock(&mng->ct_sl);
12403 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12404 NULL, "failed to create ASO CT pool");
12407 rte_spinlock_unlock(&mng->ct_sl);
12408 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12409 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12410 /* 0: inactive, 1: created, 2+: used by flows. */
12411 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12412 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12413 if (!ct->dr_action_orig) {
12414 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12415 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12416 (priv->sh->rx_domain, pool->devx_obj->obj,
12418 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12421 RTE_SET_USED(reg_c);
12423 if (!ct->dr_action_orig) {
12424 flow_dv_aso_ct_dev_release(dev, ct_idx);
12425 rte_flow_error_set(error, rte_errno,
12426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12427 "failed to create ASO CT action");
12431 if (!ct->dr_action_rply) {
12432 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12433 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12434 (priv->sh->rx_domain, pool->devx_obj->obj,
12436 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12439 if (!ct->dr_action_rply) {
12440 flow_dv_aso_ct_dev_release(dev, ct_idx);
12441 rte_flow_error_set(error, rte_errno,
12442 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12443 "failed to create ASO CT action");
12451 * Create a conntrack object with context and actions by using ASO mechanism.
12454 * Pointer to rte_eth_dev structure.
12456 * Pointer to conntrack information profile.
12457 * @param[out] error
12458 * Pointer to the error structure.
12461 * Index to conntrack object on success, 0 otherwise.
12464 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12465 const struct rte_flow_action_conntrack *pro,
12466 struct rte_flow_error *error)
12468 struct mlx5_priv *priv = dev->data->dev_private;
12469 struct mlx5_dev_ctx_shared *sh = priv->sh;
12470 struct mlx5_aso_ct_action *ct;
12473 if (!sh->ct_aso_en)
12474 return rte_flow_error_set(error, ENOTSUP,
12475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12476 "Connection is not supported");
12477 idx = flow_dv_aso_ct_alloc(dev, error);
12479 return rte_flow_error_set(error, rte_errno,
12480 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12481 "Failed to allocate CT object");
12482 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12483 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12484 return rte_flow_error_set(error, EBUSY,
12485 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12486 "Failed to update CT");
12487 ct->is_original = !!pro->is_original_dir;
12488 ct->peer = pro->peer_port;
12493 * Fill the flow with DV spec, lock free
12494 * (mutex should be acquired by caller).
12497 * Pointer to rte_eth_dev structure.
12498 * @param[in, out] dev_flow
12499 * Pointer to the sub flow.
12501 * Pointer to the flow attributes.
12503 * Pointer to the list of items.
12504 * @param[in] actions
12505 * Pointer to the list of actions.
12506 * @param[out] error
12507 * Pointer to the error structure.
12510 * 0 on success, a negative errno value otherwise and rte_errno is set.
12513 flow_dv_translate(struct rte_eth_dev *dev,
12514 struct mlx5_flow *dev_flow,
12515 const struct rte_flow_attr *attr,
12516 const struct rte_flow_item items[],
12517 const struct rte_flow_action actions[],
12518 struct rte_flow_error *error)
12520 struct mlx5_priv *priv = dev->data->dev_private;
12521 struct mlx5_dev_config *dev_conf = &priv->config;
12522 struct rte_flow *flow = dev_flow->flow;
12523 struct mlx5_flow_handle *handle = dev_flow->handle;
12524 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12525 struct mlx5_flow_rss_desc *rss_desc;
12526 uint64_t item_flags = 0;
12527 uint64_t last_item = 0;
12528 uint64_t action_flags = 0;
12529 struct mlx5_flow_dv_matcher matcher = {
12531 .size = sizeof(matcher.mask.buf),
12535 bool actions_end = false;
12537 struct mlx5_flow_dv_modify_hdr_resource res;
12538 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12539 sizeof(struct mlx5_modification_cmd) *
12540 (MLX5_MAX_MODIFY_NUM + 1)];
12542 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12543 const struct rte_flow_action_count *count = NULL;
12544 const struct rte_flow_action_age *non_shared_age = NULL;
12545 union flow_dv_attr flow_attr = { .attr = 0 };
12547 union mlx5_flow_tbl_key tbl_key;
12548 uint32_t modify_action_position = UINT32_MAX;
12549 void *match_mask = matcher.mask.buf;
12550 void *match_value = dev_flow->dv.value.buf;
12551 uint8_t next_protocol = 0xff;
12552 struct rte_vlan_hdr vlan = { 0 };
12553 struct mlx5_flow_dv_dest_array_resource mdest_res;
12554 struct mlx5_flow_dv_sample_resource sample_res;
12555 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12556 const struct rte_flow_action_sample *sample = NULL;
12557 struct mlx5_flow_sub_actions_list *sample_act;
12558 uint32_t sample_act_pos = UINT32_MAX;
12559 uint32_t age_act_pos = UINT32_MAX;
12560 uint32_t num_of_dest = 0;
12561 int tmp_actions_n = 0;
12564 const struct mlx5_flow_tunnel *tunnel = NULL;
12565 struct flow_grp_info grp_info = {
12566 .external = !!dev_flow->external,
12567 .transfer = !!attr->transfer,
12568 .fdb_def_rule = !!priv->fdb_def_rule,
12569 .skip_scale = dev_flow->skip_scale &
12570 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12571 .std_tbl_fix = true,
12573 const struct rte_flow_item *head_item = items;
12576 return rte_flow_error_set(error, ENOMEM,
12577 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12579 "failed to push flow workspace");
12580 rss_desc = &wks->rss_desc;
12581 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12582 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12583 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12584 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12585 /* update normal path action resource into last index of array */
12586 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12587 if (is_tunnel_offload_active(dev)) {
12588 if (dev_flow->tunnel) {
12589 RTE_VERIFY(dev_flow->tof_type ==
12590 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12591 tunnel = dev_flow->tunnel;
12593 tunnel = mlx5_get_tof(items, actions,
12594 &dev_flow->tof_type);
12595 dev_flow->tunnel = tunnel;
12597 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12598 (dev, attr, tunnel, dev_flow->tof_type);
12600 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12601 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12602 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12606 dev_flow->dv.group = table;
12607 if (attr->transfer)
12608 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12609 /* number of actions must be set to 0 in case of dirty stack. */
12610 mhdr_res->actions_num = 0;
12611 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12613 * do not add decap action if match rule drops packet
12614 * HW rejects rules with decap & drop
12616 * if tunnel match rule was inserted before matching tunnel set
12617 * rule flow table used in the match rule must be registered.
12618 * current implementation handles that in the
12619 * flow_dv_match_register() at the function end.
12621 bool add_decap = true;
12622 const struct rte_flow_action *ptr = actions;
12624 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12625 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12631 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12635 dev_flow->dv.actions[actions_n++] =
12636 dev_flow->dv.encap_decap->action;
12637 action_flags |= MLX5_FLOW_ACTION_DECAP;
12640 for (; !actions_end ; actions++) {
12641 const struct rte_flow_action_queue *queue;
12642 const struct rte_flow_action_rss *rss;
12643 const struct rte_flow_action *action = actions;
12644 const uint8_t *rss_key;
12645 struct mlx5_flow_tbl_resource *tbl;
12646 struct mlx5_aso_age_action *age_act;
12647 struct mlx5_flow_counter *cnt_act;
12648 uint32_t port_id = 0;
12649 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12650 int action_type = actions->type;
12651 const struct rte_flow_action *found_action = NULL;
12652 uint32_t jump_group = 0;
12653 uint32_t owner_idx;
12654 struct mlx5_aso_ct_action *ct;
12656 if (!mlx5_flow_os_action_supported(action_type))
12657 return rte_flow_error_set(error, ENOTSUP,
12658 RTE_FLOW_ERROR_TYPE_ACTION,
12660 "action not supported");
12661 switch (action_type) {
12662 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12663 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12665 case RTE_FLOW_ACTION_TYPE_VOID:
12667 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12668 if (flow_dv_translate_action_port_id(dev, action,
12671 port_id_resource.port_id = port_id;
12672 MLX5_ASSERT(!handle->rix_port_id_action);
12673 if (flow_dv_port_id_action_resource_register
12674 (dev, &port_id_resource, dev_flow, error))
12676 dev_flow->dv.actions[actions_n++] =
12677 dev_flow->dv.port_id_action->action;
12678 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12679 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12680 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12683 case RTE_FLOW_ACTION_TYPE_FLAG:
12684 action_flags |= MLX5_FLOW_ACTION_FLAG;
12685 dev_flow->handle->mark = 1;
12686 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12687 struct rte_flow_action_mark mark = {
12688 .id = MLX5_FLOW_MARK_DEFAULT,
12691 if (flow_dv_convert_action_mark(dev, &mark,
12695 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12698 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12700 * Only one FLAG or MARK is supported per device flow
12701 * right now. So the pointer to the tag resource must be
12702 * zero before the register process.
12704 MLX5_ASSERT(!handle->dvh.rix_tag);
12705 if (flow_dv_tag_resource_register(dev, tag_be,
12708 MLX5_ASSERT(dev_flow->dv.tag_resource);
12709 dev_flow->dv.actions[actions_n++] =
12710 dev_flow->dv.tag_resource->action;
12712 case RTE_FLOW_ACTION_TYPE_MARK:
12713 action_flags |= MLX5_FLOW_ACTION_MARK;
12714 dev_flow->handle->mark = 1;
12715 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12716 const struct rte_flow_action_mark *mark =
12717 (const struct rte_flow_action_mark *)
12720 if (flow_dv_convert_action_mark(dev, mark,
12724 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12728 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12729 /* Legacy (non-extensive) MARK action. */
12730 tag_be = mlx5_flow_mark_set
12731 (((const struct rte_flow_action_mark *)
12732 (actions->conf))->id);
12733 MLX5_ASSERT(!handle->dvh.rix_tag);
12734 if (flow_dv_tag_resource_register(dev, tag_be,
12737 MLX5_ASSERT(dev_flow->dv.tag_resource);
12738 dev_flow->dv.actions[actions_n++] =
12739 dev_flow->dv.tag_resource->action;
12741 case RTE_FLOW_ACTION_TYPE_SET_META:
12742 if (flow_dv_convert_action_set_meta
12743 (dev, mhdr_res, attr,
12744 (const struct rte_flow_action_set_meta *)
12745 actions->conf, error))
12747 action_flags |= MLX5_FLOW_ACTION_SET_META;
12749 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12750 if (flow_dv_convert_action_set_tag
12752 (const struct rte_flow_action_set_tag *)
12753 actions->conf, error))
12755 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12757 case RTE_FLOW_ACTION_TYPE_DROP:
12758 action_flags |= MLX5_FLOW_ACTION_DROP;
12759 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12761 case RTE_FLOW_ACTION_TYPE_QUEUE:
12762 queue = actions->conf;
12763 rss_desc->queue_num = 1;
12764 rss_desc->queue[0] = queue->index;
12765 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12766 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12767 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12770 case RTE_FLOW_ACTION_TYPE_RSS:
12771 rss = actions->conf;
12772 memcpy(rss_desc->queue, rss->queue,
12773 rss->queue_num * sizeof(uint16_t));
12774 rss_desc->queue_num = rss->queue_num;
12775 /* NULL RSS key indicates default RSS key. */
12776 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12777 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12779 * rss->level and rss.types should be set in advance
12780 * when expanding items for RSS.
12782 action_flags |= MLX5_FLOW_ACTION_RSS;
12783 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12784 MLX5_FLOW_FATE_SHARED_RSS :
12785 MLX5_FLOW_FATE_QUEUE;
12787 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12788 flow->age = (uint32_t)(uintptr_t)(action->conf);
12789 age_act = flow_aso_age_get_by_idx(dev, flow->age);
12790 __atomic_fetch_add(&age_act->refcnt, 1,
12792 age_act_pos = actions_n++;
12793 action_flags |= MLX5_FLOW_ACTION_AGE;
12795 case RTE_FLOW_ACTION_TYPE_AGE:
12796 non_shared_age = action->conf;
12797 age_act_pos = actions_n++;
12798 action_flags |= MLX5_FLOW_ACTION_AGE;
12800 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12801 flow->counter = (uint32_t)(uintptr_t)(action->conf);
12802 cnt_act = flow_dv_counter_get_by_idx(dev, flow->counter,
12804 __atomic_fetch_add(&cnt_act->shared_info.refcnt, 1,
12806 /* Save information first, will apply later. */
12807 action_flags |= MLX5_FLOW_ACTION_COUNT;
12809 case RTE_FLOW_ACTION_TYPE_COUNT:
12810 if (!dev_conf->devx) {
12811 return rte_flow_error_set
12813 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12815 "count action not supported");
12817 /* Save information first, will apply later. */
12818 count = action->conf;
12819 action_flags |= MLX5_FLOW_ACTION_COUNT;
12821 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12822 dev_flow->dv.actions[actions_n++] =
12823 priv->sh->pop_vlan_action;
12824 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12826 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12827 if (!(action_flags &
12828 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12829 flow_dev_get_vlan_info_from_items(items, &vlan);
12830 vlan.eth_proto = rte_be_to_cpu_16
12831 ((((const struct rte_flow_action_of_push_vlan *)
12832 actions->conf)->ethertype));
12833 found_action = mlx5_flow_find_action
12835 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12837 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12838 found_action = mlx5_flow_find_action
12840 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12842 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12843 if (flow_dv_create_action_push_vlan
12844 (dev, attr, &vlan, dev_flow, error))
12846 dev_flow->dv.actions[actions_n++] =
12847 dev_flow->dv.push_vlan_res->action;
12848 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12850 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12851 /* of_vlan_push action handled this action */
12852 MLX5_ASSERT(action_flags &
12853 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12855 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12856 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12858 flow_dev_get_vlan_info_from_items(items, &vlan);
12859 mlx5_update_vlan_vid_pcp(actions, &vlan);
12860 /* If no VLAN push - this is a modify header action */
12861 if (flow_dv_convert_action_modify_vlan_vid
12862 (mhdr_res, actions, error))
12864 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12866 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12867 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12868 if (flow_dv_create_action_l2_encap(dev, actions,
12873 dev_flow->dv.actions[actions_n++] =
12874 dev_flow->dv.encap_decap->action;
12875 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12876 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12877 sample_act->action_flags |=
12878 MLX5_FLOW_ACTION_ENCAP;
12880 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12881 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12882 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12886 dev_flow->dv.actions[actions_n++] =
12887 dev_flow->dv.encap_decap->action;
12888 action_flags |= MLX5_FLOW_ACTION_DECAP;
12890 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
12891 /* Handle encap with preceding decap. */
12892 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
12893 if (flow_dv_create_action_raw_encap
12894 (dev, actions, dev_flow, attr, error))
12896 dev_flow->dv.actions[actions_n++] =
12897 dev_flow->dv.encap_decap->action;
12899 /* Handle encap without preceding decap. */
12900 if (flow_dv_create_action_l2_encap
12901 (dev, actions, dev_flow, attr->transfer,
12904 dev_flow->dv.actions[actions_n++] =
12905 dev_flow->dv.encap_decap->action;
12907 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12908 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12909 sample_act->action_flags |=
12910 MLX5_FLOW_ACTION_ENCAP;
12912 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
12913 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
12915 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
12916 if (flow_dv_create_action_l2_decap
12917 (dev, dev_flow, attr->transfer, error))
12919 dev_flow->dv.actions[actions_n++] =
12920 dev_flow->dv.encap_decap->action;
12922 /* If decap is followed by encap, handle it at encap. */
12923 action_flags |= MLX5_FLOW_ACTION_DECAP;
12925 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
12926 dev_flow->dv.actions[actions_n++] =
12927 (void *)(uintptr_t)action->conf;
12928 action_flags |= MLX5_FLOW_ACTION_JUMP;
12930 case RTE_FLOW_ACTION_TYPE_JUMP:
12931 jump_group = ((const struct rte_flow_action_jump *)
12932 action->conf)->group;
12933 grp_info.std_tbl_fix = 0;
12934 if (dev_flow->skip_scale &
12935 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
12936 grp_info.skip_scale = 1;
12938 grp_info.skip_scale = 0;
12939 ret = mlx5_flow_group_to_table(dev, tunnel,
12945 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
12947 !!dev_flow->external,
12948 tunnel, jump_group, 0,
12951 return rte_flow_error_set
12953 RTE_FLOW_ERROR_TYPE_ACTION,
12955 "cannot create jump action.");
12956 if (flow_dv_jump_tbl_resource_register
12957 (dev, tbl, dev_flow, error)) {
12958 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12959 return rte_flow_error_set
12961 RTE_FLOW_ERROR_TYPE_ACTION,
12963 "cannot create jump action.");
12965 dev_flow->dv.actions[actions_n++] =
12966 dev_flow->dv.jump->action;
12967 action_flags |= MLX5_FLOW_ACTION_JUMP;
12968 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
12969 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
12972 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
12973 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
12974 if (flow_dv_convert_action_modify_mac
12975 (mhdr_res, actions, error))
12977 action_flags |= actions->type ==
12978 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
12979 MLX5_FLOW_ACTION_SET_MAC_SRC :
12980 MLX5_FLOW_ACTION_SET_MAC_DST;
12982 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
12983 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
12984 if (flow_dv_convert_action_modify_ipv4
12985 (mhdr_res, actions, error))
12987 action_flags |= actions->type ==
12988 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
12989 MLX5_FLOW_ACTION_SET_IPV4_SRC :
12990 MLX5_FLOW_ACTION_SET_IPV4_DST;
12992 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
12993 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
12994 if (flow_dv_convert_action_modify_ipv6
12995 (mhdr_res, actions, error))
12997 action_flags |= actions->type ==
12998 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
12999 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13000 MLX5_FLOW_ACTION_SET_IPV6_DST;
13002 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13003 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13004 if (flow_dv_convert_action_modify_tp
13005 (mhdr_res, actions, items,
13006 &flow_attr, dev_flow, !!(action_flags &
13007 MLX5_FLOW_ACTION_DECAP), error))
13009 action_flags |= actions->type ==
13010 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13011 MLX5_FLOW_ACTION_SET_TP_SRC :
13012 MLX5_FLOW_ACTION_SET_TP_DST;
13014 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13015 if (flow_dv_convert_action_modify_dec_ttl
13016 (mhdr_res, items, &flow_attr, dev_flow,
13018 MLX5_FLOW_ACTION_DECAP), error))
13020 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13022 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13023 if (flow_dv_convert_action_modify_ttl
13024 (mhdr_res, actions, items, &flow_attr,
13025 dev_flow, !!(action_flags &
13026 MLX5_FLOW_ACTION_DECAP), error))
13028 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13030 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13031 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13032 if (flow_dv_convert_action_modify_tcp_seq
13033 (mhdr_res, actions, error))
13035 action_flags |= actions->type ==
13036 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13037 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13038 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13041 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13042 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13043 if (flow_dv_convert_action_modify_tcp_ack
13044 (mhdr_res, actions, error))
13046 action_flags |= actions->type ==
13047 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13048 MLX5_FLOW_ACTION_INC_TCP_ACK :
13049 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13051 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13052 if (flow_dv_convert_action_set_reg
13053 (mhdr_res, actions, error))
13055 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13057 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13058 if (flow_dv_convert_action_copy_mreg
13059 (dev, mhdr_res, actions, error))
13061 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13063 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13064 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13065 dev_flow->handle->fate_action =
13066 MLX5_FLOW_FATE_DEFAULT_MISS;
13068 case RTE_FLOW_ACTION_TYPE_METER:
13070 return rte_flow_error_set(error, rte_errno,
13071 RTE_FLOW_ERROR_TYPE_ACTION,
13072 NULL, "Failed to get meter in flow.");
13073 /* Set the meter action. */
13074 dev_flow->dv.actions[actions_n++] =
13075 wks->fm->meter_action;
13076 action_flags |= MLX5_FLOW_ACTION_METER;
13078 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13079 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13082 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13084 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13085 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13088 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13090 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13091 sample_act_pos = actions_n;
13092 sample = (const struct rte_flow_action_sample *)
13095 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13096 /* put encap action into group if work with port id */
13097 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13098 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13099 sample_act->action_flags |=
13100 MLX5_FLOW_ACTION_ENCAP;
13102 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13103 if (flow_dv_convert_action_modify_field
13104 (dev, mhdr_res, actions, attr, error))
13106 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13108 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13109 owner_idx = (uint32_t)(uintptr_t)action->conf;
13110 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13112 return rte_flow_error_set(error, EINVAL,
13113 RTE_FLOW_ERROR_TYPE_ACTION,
13115 "Failed to get CT object.");
13116 if (mlx5_aso_ct_available(priv->sh, ct))
13117 return rte_flow_error_set(error, rte_errno,
13118 RTE_FLOW_ERROR_TYPE_ACTION,
13120 "CT is unavailable.");
13121 if (ct->is_original)
13122 dev_flow->dv.actions[actions_n] =
13123 ct->dr_action_orig;
13125 dev_flow->dv.actions[actions_n] =
13126 ct->dr_action_rply;
13127 flow->indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
13128 flow->ct = owner_idx;
13129 __atomic_fetch_add(&ct->refcnt, 1, __ATOMIC_RELAXED);
13131 action_flags |= MLX5_FLOW_ACTION_CT;
13133 case RTE_FLOW_ACTION_TYPE_END:
13134 actions_end = true;
13135 if (mhdr_res->actions_num) {
13136 /* create modify action if needed. */
13137 if (flow_dv_modify_hdr_resource_register
13138 (dev, mhdr_res, dev_flow, error))
13140 dev_flow->dv.actions[modify_action_position] =
13141 handle->dvh.modify_hdr->action;
13144 * Handle AGE and COUNT action by single HW counter
13145 * when they are not shared.
13147 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13148 if ((non_shared_age &&
13149 count && !count->shared) ||
13150 !(priv->sh->flow_hit_aso_en &&
13151 (attr->group || attr->transfer))) {
13152 /* Creates age by counters. */
13153 cnt_act = flow_dv_prepare_counter
13160 dev_flow->dv.actions[age_act_pos] =
13164 if (!flow->age && non_shared_age) {
13165 flow->age = flow_dv_aso_age_alloc
13169 flow_dv_aso_age_params_init
13171 non_shared_age->context ?
13172 non_shared_age->context :
13173 (void *)(uintptr_t)
13174 (dev_flow->flow_idx),
13175 non_shared_age->timeout);
13177 age_act = flow_aso_age_get_by_idx(dev,
13179 dev_flow->dv.actions[age_act_pos] =
13180 age_act->dr_action;
13182 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13184 * Create one count action, to be used
13185 * by all sub-flows.
13187 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13192 dev_flow->dv.actions[actions_n++] =
13198 if (mhdr_res->actions_num &&
13199 modify_action_position == UINT32_MAX)
13200 modify_action_position = actions_n++;
13202 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13203 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13204 int item_type = items->type;
13206 if (!mlx5_flow_os_item_supported(item_type))
13207 return rte_flow_error_set(error, ENOTSUP,
13208 RTE_FLOW_ERROR_TYPE_ITEM,
13209 NULL, "item not supported");
13210 switch (item_type) {
13211 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13212 flow_dv_translate_item_port_id
13213 (dev, match_mask, match_value, items, attr);
13214 last_item = MLX5_FLOW_ITEM_PORT_ID;
13216 case RTE_FLOW_ITEM_TYPE_ETH:
13217 flow_dv_translate_item_eth(match_mask, match_value,
13219 dev_flow->dv.group);
13220 matcher.priority = action_flags &
13221 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13222 !dev_flow->external ?
13223 MLX5_PRIORITY_MAP_L3 :
13224 MLX5_PRIORITY_MAP_L2;
13225 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13226 MLX5_FLOW_LAYER_OUTER_L2;
13228 case RTE_FLOW_ITEM_TYPE_VLAN:
13229 flow_dv_translate_item_vlan(dev_flow,
13230 match_mask, match_value,
13232 dev_flow->dv.group);
13233 matcher.priority = MLX5_PRIORITY_MAP_L2;
13234 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13235 MLX5_FLOW_LAYER_INNER_VLAN) :
13236 (MLX5_FLOW_LAYER_OUTER_L2 |
13237 MLX5_FLOW_LAYER_OUTER_VLAN);
13239 case RTE_FLOW_ITEM_TYPE_IPV4:
13240 mlx5_flow_tunnel_ip_check(items, next_protocol,
13241 &item_flags, &tunnel);
13242 flow_dv_translate_item_ipv4(match_mask, match_value,
13244 dev_flow->dv.group);
13245 matcher.priority = MLX5_PRIORITY_MAP_L3;
13246 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13247 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13248 if (items->mask != NULL &&
13249 ((const struct rte_flow_item_ipv4 *)
13250 items->mask)->hdr.next_proto_id) {
13252 ((const struct rte_flow_item_ipv4 *)
13253 (items->spec))->hdr.next_proto_id;
13255 ((const struct rte_flow_item_ipv4 *)
13256 (items->mask))->hdr.next_proto_id;
13258 /* Reset for inner layer. */
13259 next_protocol = 0xff;
13262 case RTE_FLOW_ITEM_TYPE_IPV6:
13263 mlx5_flow_tunnel_ip_check(items, next_protocol,
13264 &item_flags, &tunnel);
13265 flow_dv_translate_item_ipv6(match_mask, match_value,
13267 dev_flow->dv.group);
13268 matcher.priority = MLX5_PRIORITY_MAP_L3;
13269 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13270 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13271 if (items->mask != NULL &&
13272 ((const struct rte_flow_item_ipv6 *)
13273 items->mask)->hdr.proto) {
13275 ((const struct rte_flow_item_ipv6 *)
13276 items->spec)->hdr.proto;
13278 ((const struct rte_flow_item_ipv6 *)
13279 items->mask)->hdr.proto;
13281 /* Reset for inner layer. */
13282 next_protocol = 0xff;
13285 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13286 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13289 last_item = tunnel ?
13290 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13291 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13292 if (items->mask != NULL &&
13293 ((const struct rte_flow_item_ipv6_frag_ext *)
13294 items->mask)->hdr.next_header) {
13296 ((const struct rte_flow_item_ipv6_frag_ext *)
13297 items->spec)->hdr.next_header;
13299 ((const struct rte_flow_item_ipv6_frag_ext *)
13300 items->mask)->hdr.next_header;
13302 /* Reset for inner layer. */
13303 next_protocol = 0xff;
13306 case RTE_FLOW_ITEM_TYPE_TCP:
13307 flow_dv_translate_item_tcp(match_mask, match_value,
13309 matcher.priority = MLX5_PRIORITY_MAP_L4;
13310 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13311 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13313 case RTE_FLOW_ITEM_TYPE_UDP:
13314 flow_dv_translate_item_udp(match_mask, match_value,
13316 matcher.priority = MLX5_PRIORITY_MAP_L4;
13317 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13318 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13320 case RTE_FLOW_ITEM_TYPE_GRE:
13321 flow_dv_translate_item_gre(match_mask, match_value,
13323 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13324 last_item = MLX5_FLOW_LAYER_GRE;
13326 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13327 flow_dv_translate_item_gre_key(match_mask,
13328 match_value, items);
13329 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13331 case RTE_FLOW_ITEM_TYPE_NVGRE:
13332 flow_dv_translate_item_nvgre(match_mask, match_value,
13334 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13335 last_item = MLX5_FLOW_LAYER_GRE;
13337 case RTE_FLOW_ITEM_TYPE_VXLAN:
13338 flow_dv_translate_item_vxlan(dev, attr,
13339 match_mask, match_value,
13341 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13342 last_item = MLX5_FLOW_LAYER_VXLAN;
13344 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13345 flow_dv_translate_item_vxlan_gpe(match_mask,
13346 match_value, items,
13348 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13349 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13351 case RTE_FLOW_ITEM_TYPE_GENEVE:
13352 flow_dv_translate_item_geneve(match_mask, match_value,
13354 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13355 last_item = MLX5_FLOW_LAYER_GENEVE;
13357 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13358 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13362 return rte_flow_error_set(error, -ret,
13363 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13364 "cannot create GENEVE TLV option");
13365 flow->geneve_tlv_option = 1;
13366 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13368 case RTE_FLOW_ITEM_TYPE_MPLS:
13369 flow_dv_translate_item_mpls(match_mask, match_value,
13370 items, last_item, tunnel);
13371 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13372 last_item = MLX5_FLOW_LAYER_MPLS;
13374 case RTE_FLOW_ITEM_TYPE_MARK:
13375 flow_dv_translate_item_mark(dev, match_mask,
13376 match_value, items);
13377 last_item = MLX5_FLOW_ITEM_MARK;
13379 case RTE_FLOW_ITEM_TYPE_META:
13380 flow_dv_translate_item_meta(dev, match_mask,
13381 match_value, attr, items);
13382 last_item = MLX5_FLOW_ITEM_METADATA;
13384 case RTE_FLOW_ITEM_TYPE_ICMP:
13385 flow_dv_translate_item_icmp(match_mask, match_value,
13387 last_item = MLX5_FLOW_LAYER_ICMP;
13389 case RTE_FLOW_ITEM_TYPE_ICMP6:
13390 flow_dv_translate_item_icmp6(match_mask, match_value,
13392 last_item = MLX5_FLOW_LAYER_ICMP6;
13394 case RTE_FLOW_ITEM_TYPE_TAG:
13395 flow_dv_translate_item_tag(dev, match_mask,
13396 match_value, items);
13397 last_item = MLX5_FLOW_ITEM_TAG;
13399 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13400 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13401 match_value, items);
13402 last_item = MLX5_FLOW_ITEM_TAG;
13404 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13405 flow_dv_translate_item_tx_queue(dev, match_mask,
13408 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13410 case RTE_FLOW_ITEM_TYPE_GTP:
13411 flow_dv_translate_item_gtp(match_mask, match_value,
13413 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13414 last_item = MLX5_FLOW_LAYER_GTP;
13416 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13417 ret = flow_dv_translate_item_gtp_psc(match_mask,
13421 return rte_flow_error_set(error, -ret,
13422 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13423 "cannot create GTP PSC item");
13424 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13426 case RTE_FLOW_ITEM_TYPE_ECPRI:
13427 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13428 /* Create it only the first time to be used. */
13429 ret = mlx5_flex_parser_ecpri_alloc(dev);
13431 return rte_flow_error_set
13433 RTE_FLOW_ERROR_TYPE_ITEM,
13435 "cannot create eCPRI parser");
13437 flow_dv_translate_item_ecpri(dev, match_mask,
13438 match_value, items);
13439 /* No other protocol should follow eCPRI layer. */
13440 last_item = MLX5_FLOW_LAYER_ECPRI;
13442 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13443 flow_dv_translate_item_integrity(match_mask,
13447 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13448 flow_dv_translate_item_aso_ct(dev, match_mask,
13449 match_value, items);
13454 item_flags |= last_item;
13457 * When E-Switch mode is enabled, we have two cases where we need to
13458 * set the source port manually.
13459 * The first one, is in case of Nic steering rule, and the second is
13460 * E-Switch rule where no port_id item was found. In both cases
13461 * the source port is set according the current port in use.
13463 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13464 (priv->representor || priv->master)) {
13465 if (flow_dv_translate_item_port_id(dev, match_mask,
13466 match_value, NULL, attr))
13469 #ifdef RTE_LIBRTE_MLX5_DEBUG
13470 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13471 dev_flow->dv.value.buf));
13474 * Layers may be already initialized from prefix flow if this dev_flow
13475 * is the suffix flow.
13477 handle->layers |= item_flags;
13478 if (action_flags & MLX5_FLOW_ACTION_RSS)
13479 flow_dv_hashfields_set(dev_flow, rss_desc);
13480 /* If has RSS action in the sample action, the Sample/Mirror resource
13481 * should be registered after the hash filed be update.
13483 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13484 ret = flow_dv_translate_action_sample(dev,
13493 ret = flow_dv_create_action_sample(dev,
13502 return rte_flow_error_set
13504 RTE_FLOW_ERROR_TYPE_ACTION,
13506 "cannot create sample action");
13507 if (num_of_dest > 1) {
13508 dev_flow->dv.actions[sample_act_pos] =
13509 dev_flow->dv.dest_array_res->action;
13511 dev_flow->dv.actions[sample_act_pos] =
13512 dev_flow->dv.sample_res->verbs_action;
13516 * For multiple destination (sample action with ratio=1), the encap
13517 * action and port id action will be combined into group action.
13518 * So need remove the original these actions in the flow and only
13519 * use the sample action instead of.
13521 if (num_of_dest > 1 &&
13522 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13524 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13526 for (i = 0; i < actions_n; i++) {
13527 if ((sample_act->dr_encap_action &&
13528 sample_act->dr_encap_action ==
13529 dev_flow->dv.actions[i]) ||
13530 (sample_act->dr_port_id_action &&
13531 sample_act->dr_port_id_action ==
13532 dev_flow->dv.actions[i]) ||
13533 (sample_act->dr_jump_action &&
13534 sample_act->dr_jump_action ==
13535 dev_flow->dv.actions[i]))
13537 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13539 memcpy((void *)dev_flow->dv.actions,
13540 (void *)temp_actions,
13541 tmp_actions_n * sizeof(void *));
13542 actions_n = tmp_actions_n;
13544 dev_flow->dv.actions_n = actions_n;
13545 dev_flow->act_flags = action_flags;
13546 if (wks->skip_matcher_reg)
13548 /* Register matcher. */
13549 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13550 matcher.mask.size);
13551 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13554 * When creating meter drop flow in drop table, using original
13555 * 5-tuple match, the matcher priority should be lower than
13558 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13559 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13560 matcher.priority <= MLX5_REG_BITS)
13561 matcher.priority += MLX5_REG_BITS;
13562 /* reserved field no needs to be set to 0 here. */
13563 tbl_key.is_fdb = attr->transfer;
13564 tbl_key.is_egress = attr->egress;
13565 tbl_key.level = dev_flow->dv.group;
13566 tbl_key.id = dev_flow->dv.table_id;
13567 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13568 tunnel, attr->group, error))
13574 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13577 * @param[in, out] action
13578 * Shred RSS action holding hash RX queue objects.
13579 * @param[in] hash_fields
13580 * Defines combination of packet fields to participate in RX hash.
13581 * @param[in] tunnel
13583 * @param[in] hrxq_idx
13584 * Hash RX queue index to set.
13587 * 0 on success, otherwise negative errno value.
13590 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13591 const uint64_t hash_fields,
13594 uint32_t *hrxqs = action->hrxq;
13596 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13597 case MLX5_RSS_HASH_IPV4:
13598 /* fall-through. */
13599 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13600 /* fall-through. */
13601 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13602 hrxqs[0] = hrxq_idx;
13604 case MLX5_RSS_HASH_IPV4_TCP:
13605 /* fall-through. */
13606 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13607 /* fall-through. */
13608 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13609 hrxqs[1] = hrxq_idx;
13611 case MLX5_RSS_HASH_IPV4_UDP:
13612 /* fall-through. */
13613 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13614 /* fall-through. */
13615 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13616 hrxqs[2] = hrxq_idx;
13618 case MLX5_RSS_HASH_IPV6:
13619 /* fall-through. */
13620 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13621 /* fall-through. */
13622 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13623 hrxqs[3] = hrxq_idx;
13625 case MLX5_RSS_HASH_IPV6_TCP:
13626 /* fall-through. */
13627 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13628 /* fall-through. */
13629 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13630 hrxqs[4] = hrxq_idx;
13632 case MLX5_RSS_HASH_IPV6_UDP:
13633 /* fall-through. */
13634 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13635 /* fall-through. */
13636 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13637 hrxqs[5] = hrxq_idx;
13639 case MLX5_RSS_HASH_NONE:
13640 hrxqs[6] = hrxq_idx;
13648 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13652 * Pointer to the Ethernet device structure.
13654 * Shared RSS action ID holding hash RX queue objects.
13655 * @param[in] hash_fields
13656 * Defines combination of packet fields to participate in RX hash.
13657 * @param[in] tunnel
13661 * Valid hash RX queue index, otherwise 0.
13664 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13665 const uint64_t hash_fields)
13667 struct mlx5_priv *priv = dev->data->dev_private;
13668 struct mlx5_shared_action_rss *shared_rss =
13669 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13670 const uint32_t *hrxqs = shared_rss->hrxq;
13672 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13673 case MLX5_RSS_HASH_IPV4:
13674 /* fall-through. */
13675 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13676 /* fall-through. */
13677 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13679 case MLX5_RSS_HASH_IPV4_TCP:
13680 /* fall-through. */
13681 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13682 /* fall-through. */
13683 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13685 case MLX5_RSS_HASH_IPV4_UDP:
13686 /* fall-through. */
13687 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13688 /* fall-through. */
13689 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13691 case MLX5_RSS_HASH_IPV6:
13692 /* fall-through. */
13693 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13694 /* fall-through. */
13695 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13697 case MLX5_RSS_HASH_IPV6_TCP:
13698 /* fall-through. */
13699 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13700 /* fall-through. */
13701 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13703 case MLX5_RSS_HASH_IPV6_UDP:
13704 /* fall-through. */
13705 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13706 /* fall-through. */
13707 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13709 case MLX5_RSS_HASH_NONE:
13718 * Apply the flow to the NIC, lock free,
13719 * (mutex should be acquired by caller).
13722 * Pointer to the Ethernet device structure.
13723 * @param[in, out] flow
13724 * Pointer to flow structure.
13725 * @param[out] error
13726 * Pointer to error structure.
13729 * 0 on success, a negative errno value otherwise and rte_errno is set.
13732 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13733 struct rte_flow_error *error)
13735 struct mlx5_flow_dv_workspace *dv;
13736 struct mlx5_flow_handle *dh;
13737 struct mlx5_flow_handle_dv *dv_h;
13738 struct mlx5_flow *dev_flow;
13739 struct mlx5_priv *priv = dev->data->dev_private;
13740 uint32_t handle_idx;
13744 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13745 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13749 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13750 dev_flow = &wks->flows[idx];
13751 dv = &dev_flow->dv;
13752 dh = dev_flow->handle;
13755 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13756 if (dv->transfer) {
13757 MLX5_ASSERT(priv->sh->dr_drop_action);
13758 dv->actions[n++] = priv->sh->dr_drop_action;
13760 #ifdef HAVE_MLX5DV_DR
13761 /* DR supports drop action placeholder. */
13762 MLX5_ASSERT(priv->sh->dr_drop_action);
13763 dv->actions[n++] = priv->sh->dr_drop_action;
13765 /* For DV we use the explicit drop queue. */
13766 MLX5_ASSERT(priv->drop_queue.hrxq);
13768 priv->drop_queue.hrxq->action;
13771 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13772 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13773 struct mlx5_hrxq *hrxq;
13776 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13782 "cannot get hash queue");
13785 dh->rix_hrxq = hrxq_idx;
13786 dv->actions[n++] = hrxq->action;
13787 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13788 struct mlx5_hrxq *hrxq = NULL;
13791 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13792 rss_desc->shared_rss,
13793 dev_flow->hash_fields);
13795 hrxq = mlx5_ipool_get
13796 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13801 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13802 "cannot get hash queue");
13805 dh->rix_srss = rss_desc->shared_rss;
13806 dv->actions[n++] = hrxq->action;
13807 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13808 if (!priv->sh->default_miss_action) {
13811 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13812 "default miss action not be created.");
13815 dv->actions[n++] = priv->sh->default_miss_action;
13817 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13818 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13819 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13820 (void *)&dv->value, n,
13821 dv->actions, &dh->drv_flow);
13825 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13827 (!priv->config.allow_duplicate_pattern &&
13829 "duplicating pattern is not allowed" :
13830 "hardware refuses to create flow");
13833 if (priv->vmwa_context &&
13834 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13836 * The rule contains the VLAN pattern.
13837 * For VF we are going to create VLAN
13838 * interface to make hypervisor set correct
13839 * e-Switch vport context.
13841 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13846 err = rte_errno; /* Save rte_errno before cleanup. */
13847 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13848 handle_idx, dh, next) {
13849 /* hrxq is union, don't clear it if the flag is not set. */
13850 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13851 mlx5_hrxq_release(dev, dh->rix_hrxq);
13853 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13856 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13857 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13859 rte_errno = err; /* Restore rte_errno. */
13864 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
13865 struct mlx5_list_entry *entry)
13867 struct mlx5_flow_dv_matcher *resource = container_of(entry,
13871 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
13872 mlx5_free(resource);
13876 * Release the flow matcher.
13879 * Pointer to Ethernet device.
13881 * Index to port ID action resource.
13884 * 1 while a reference on it exists, 0 when freed.
13887 flow_dv_matcher_release(struct rte_eth_dev *dev,
13888 struct mlx5_flow_handle *handle)
13890 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
13891 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
13892 typeof(*tbl), tbl);
13895 MLX5_ASSERT(matcher->matcher_object);
13896 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
13897 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
13902 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
13904 struct mlx5_dev_ctx_shared *sh = tool_ctx;
13905 struct mlx5_flow_dv_encap_decap_resource *res =
13906 container_of(entry, typeof(*res), entry);
13908 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
13909 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
13913 * Release an encap/decap resource.
13916 * Pointer to Ethernet device.
13917 * @param encap_decap_idx
13918 * Index of encap decap resource.
13921 * 1 while a reference on it exists, 0 when freed.
13924 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
13925 uint32_t encap_decap_idx)
13927 struct mlx5_priv *priv = dev->data->dev_private;
13928 struct mlx5_flow_dv_encap_decap_resource *resource;
13930 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
13934 MLX5_ASSERT(resource->action);
13935 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
13939 * Release an jump to table action resource.
13942 * Pointer to Ethernet device.
13944 * Index to the jump action resource.
13947 * 1 while a reference on it exists, 0 when freed.
13950 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
13953 struct mlx5_priv *priv = dev->data->dev_private;
13954 struct mlx5_flow_tbl_data_entry *tbl_data;
13956 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
13960 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
13964 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
13966 struct mlx5_flow_dv_modify_hdr_resource *res =
13967 container_of(entry, typeof(*res), entry);
13968 struct mlx5_dev_ctx_shared *sh = tool_ctx;
13970 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
13971 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
13975 * Release a modify-header resource.
13978 * Pointer to Ethernet device.
13980 * Pointer to mlx5_flow_handle.
13983 * 1 while a reference on it exists, 0 when freed.
13986 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
13987 struct mlx5_flow_handle *handle)
13989 struct mlx5_priv *priv = dev->data->dev_private;
13990 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
13992 MLX5_ASSERT(entry->action);
13993 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
13997 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
13999 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14000 struct mlx5_flow_dv_port_id_action_resource *resource =
14001 container_of(entry, typeof(*resource), entry);
14003 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14004 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14008 * Release port ID action resource.
14011 * Pointer to Ethernet device.
14013 * Pointer to mlx5_flow_handle.
14016 * 1 while a reference on it exists, 0 when freed.
14019 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14022 struct mlx5_priv *priv = dev->data->dev_private;
14023 struct mlx5_flow_dv_port_id_action_resource *resource;
14025 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14028 MLX5_ASSERT(resource->action);
14029 return mlx5_list_unregister(priv->sh->port_id_action_list,
14034 * Release shared RSS action resource.
14037 * Pointer to Ethernet device.
14039 * Shared RSS action index.
14042 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14044 struct mlx5_priv *priv = dev->data->dev_private;
14045 struct mlx5_shared_action_rss *shared_rss;
14047 shared_rss = mlx5_ipool_get
14048 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14049 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14053 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14055 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14056 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14057 container_of(entry, typeof(*resource), entry);
14059 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14060 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14064 * Release push vlan action resource.
14067 * Pointer to Ethernet device.
14069 * Pointer to mlx5_flow_handle.
14072 * 1 while a reference on it exists, 0 when freed.
14075 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14076 struct mlx5_flow_handle *handle)
14078 struct mlx5_priv *priv = dev->data->dev_private;
14079 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14080 uint32_t idx = handle->dvh.rix_push_vlan;
14082 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14085 MLX5_ASSERT(resource->action);
14086 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14091 * Release the fate resource.
14094 * Pointer to Ethernet device.
14096 * Pointer to mlx5_flow_handle.
14099 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14100 struct mlx5_flow_handle *handle)
14102 if (!handle->rix_fate)
14104 switch (handle->fate_action) {
14105 case MLX5_FLOW_FATE_QUEUE:
14106 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14107 mlx5_hrxq_release(dev, handle->rix_hrxq);
14109 case MLX5_FLOW_FATE_JUMP:
14110 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14112 case MLX5_FLOW_FATE_PORT_ID:
14113 flow_dv_port_id_action_resource_release(dev,
14114 handle->rix_port_id_action);
14117 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14120 handle->rix_fate = 0;
14124 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14125 struct mlx5_list_entry *entry)
14127 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14130 struct rte_eth_dev *dev = resource->dev;
14131 struct mlx5_priv *priv = dev->data->dev_private;
14133 if (resource->verbs_action)
14134 claim_zero(mlx5_flow_os_destroy_flow_action
14135 (resource->verbs_action));
14136 if (resource->normal_path_tbl)
14137 flow_dv_tbl_resource_release(MLX5_SH(dev),
14138 resource->normal_path_tbl);
14139 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14140 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14141 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14145 * Release an sample resource.
14148 * Pointer to Ethernet device.
14150 * Pointer to mlx5_flow_handle.
14153 * 1 while a reference on it exists, 0 when freed.
14156 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14157 struct mlx5_flow_handle *handle)
14159 struct mlx5_priv *priv = dev->data->dev_private;
14160 struct mlx5_flow_dv_sample_resource *resource;
14162 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14163 handle->dvh.rix_sample);
14166 MLX5_ASSERT(resource->verbs_action);
14167 return mlx5_list_unregister(priv->sh->sample_action_list,
14172 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14173 struct mlx5_list_entry *entry)
14175 struct mlx5_flow_dv_dest_array_resource *resource =
14176 container_of(entry, typeof(*resource), entry);
14177 struct rte_eth_dev *dev = resource->dev;
14178 struct mlx5_priv *priv = dev->data->dev_private;
14181 MLX5_ASSERT(resource->action);
14182 if (resource->action)
14183 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14184 for (; i < resource->num_of_dest; i++)
14185 flow_dv_sample_sub_actions_release(dev,
14186 &resource->sample_idx[i]);
14187 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14188 DRV_LOG(DEBUG, "destination array resource %p: removed",
14193 * Release an destination array resource.
14196 * Pointer to Ethernet device.
14198 * Pointer to mlx5_flow_handle.
14201 * 1 while a reference on it exists, 0 when freed.
14204 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14205 struct mlx5_flow_handle *handle)
14207 struct mlx5_priv *priv = dev->data->dev_private;
14208 struct mlx5_flow_dv_dest_array_resource *resource;
14210 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14211 handle->dvh.rix_dest_array);
14214 MLX5_ASSERT(resource->action);
14215 return mlx5_list_unregister(priv->sh->dest_array_list,
14220 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14222 struct mlx5_priv *priv = dev->data->dev_private;
14223 struct mlx5_dev_ctx_shared *sh = priv->sh;
14224 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14225 sh->geneve_tlv_option_resource;
14226 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14227 if (geneve_opt_resource) {
14228 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14229 __ATOMIC_RELAXED))) {
14230 claim_zero(mlx5_devx_cmd_destroy
14231 (geneve_opt_resource->obj));
14232 mlx5_free(sh->geneve_tlv_option_resource);
14233 sh->geneve_tlv_option_resource = NULL;
14236 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14240 * Remove the flow from the NIC but keeps it in memory.
14241 * Lock free, (mutex should be acquired by caller).
14244 * Pointer to Ethernet device.
14245 * @param[in, out] flow
14246 * Pointer to flow structure.
14249 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14251 struct mlx5_flow_handle *dh;
14252 uint32_t handle_idx;
14253 struct mlx5_priv *priv = dev->data->dev_private;
14257 handle_idx = flow->dev_handles;
14258 while (handle_idx) {
14259 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14263 if (dh->drv_flow) {
14264 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14265 dh->drv_flow = NULL;
14267 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14268 flow_dv_fate_resource_release(dev, dh);
14269 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14270 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14271 handle_idx = dh->next.next;
14276 * Remove the flow from the NIC and the memory.
14277 * Lock free, (mutex should be acquired by caller).
14280 * Pointer to the Ethernet device structure.
14281 * @param[in, out] flow
14282 * Pointer to flow structure.
14285 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14287 struct mlx5_flow_handle *dev_handle;
14288 struct mlx5_priv *priv = dev->data->dev_private;
14289 struct mlx5_flow_meter_info *fm = NULL;
14294 flow_dv_remove(dev, flow);
14295 if (flow->counter) {
14296 flow_dv_counter_free(dev, flow->counter);
14300 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14302 mlx5_flow_meter_detach(priv, fm);
14305 /* Keep the current age handling by default. */
14306 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14307 flow_dv_aso_ct_release(dev, flow->ct);
14308 else if (flow->age)
14309 flow_dv_aso_age_release(dev, flow->age);
14310 if (flow->geneve_tlv_option) {
14311 flow_dv_geneve_tlv_option_resource_release(dev);
14312 flow->geneve_tlv_option = 0;
14314 while (flow->dev_handles) {
14315 uint32_t tmp_idx = flow->dev_handles;
14317 dev_handle = mlx5_ipool_get(priv->sh->ipool
14318 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14321 flow->dev_handles = dev_handle->next.next;
14322 if (dev_handle->dvh.matcher)
14323 flow_dv_matcher_release(dev, dev_handle);
14324 if (dev_handle->dvh.rix_sample)
14325 flow_dv_sample_resource_release(dev, dev_handle);
14326 if (dev_handle->dvh.rix_dest_array)
14327 flow_dv_dest_array_resource_release(dev, dev_handle);
14328 if (dev_handle->dvh.rix_encap_decap)
14329 flow_dv_encap_decap_resource_release(dev,
14330 dev_handle->dvh.rix_encap_decap);
14331 if (dev_handle->dvh.modify_hdr)
14332 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14333 if (dev_handle->dvh.rix_push_vlan)
14334 flow_dv_push_vlan_action_resource_release(dev,
14336 if (dev_handle->dvh.rix_tag)
14337 flow_dv_tag_release(dev,
14338 dev_handle->dvh.rix_tag);
14339 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14340 flow_dv_fate_resource_release(dev, dev_handle);
14342 srss = dev_handle->rix_srss;
14343 if (fm && dev_handle->is_meter_flow_id &&
14344 dev_handle->split_flow_id)
14345 mlx5_ipool_free(fm->flow_ipool,
14346 dev_handle->split_flow_id);
14347 else if (dev_handle->split_flow_id &&
14348 !dev_handle->is_meter_flow_id)
14349 mlx5_ipool_free(priv->sh->ipool
14350 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14351 dev_handle->split_flow_id);
14352 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14356 flow_dv_shared_rss_action_release(dev, srss);
14360 * Release array of hash RX queue objects.
14364 * Pointer to the Ethernet device structure.
14365 * @param[in, out] hrxqs
14366 * Array of hash RX queue objects.
14369 * Total number of references to hash RX queue objects in *hrxqs* array
14370 * after this operation.
14373 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14374 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14379 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14380 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14390 * Release all hash RX queue objects representing shared RSS action.
14393 * Pointer to the Ethernet device structure.
14394 * @param[in, out] action
14395 * Shared RSS action to remove hash RX queue objects from.
14398 * Total number of references to hash RX queue objects stored in *action*
14399 * after this operation.
14400 * Expected to be 0 if no external references held.
14403 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14404 struct mlx5_shared_action_rss *shared_rss)
14406 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14410 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14413 * Only one hash value is available for one L3+L4 combination:
14415 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14416 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14417 * same slot in mlx5_rss_hash_fields.
14420 * Pointer to the shared action RSS conf.
14421 * @param[in, out] hash_field
14422 * hash_field variable needed to be adjusted.
14428 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14429 uint64_t *hash_field)
14431 uint64_t rss_types = rss->origin.types;
14433 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14434 case MLX5_RSS_HASH_IPV4:
14435 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14436 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14437 if (rss_types & ETH_RSS_L3_DST_ONLY)
14438 *hash_field |= IBV_RX_HASH_DST_IPV4;
14439 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
14440 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14442 *hash_field |= MLX5_RSS_HASH_IPV4;
14445 case MLX5_RSS_HASH_IPV6:
14446 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14447 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14448 if (rss_types & ETH_RSS_L3_DST_ONLY)
14449 *hash_field |= IBV_RX_HASH_DST_IPV6;
14450 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
14451 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14453 *hash_field |= MLX5_RSS_HASH_IPV6;
14456 case MLX5_RSS_HASH_IPV4_UDP:
14457 /* fall-through. */
14458 case MLX5_RSS_HASH_IPV6_UDP:
14459 if (rss_types & ETH_RSS_UDP) {
14460 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14461 if (rss_types & ETH_RSS_L4_DST_ONLY)
14462 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14463 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
14464 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14466 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14469 case MLX5_RSS_HASH_IPV4_TCP:
14470 /* fall-through. */
14471 case MLX5_RSS_HASH_IPV6_TCP:
14472 if (rss_types & ETH_RSS_TCP) {
14473 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14474 if (rss_types & ETH_RSS_L4_DST_ONLY)
14475 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14476 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
14477 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14479 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14488 * Setup shared RSS action.
14489 * Prepare set of hash RX queue objects sufficient to handle all valid
14490 * hash_fields combinations (see enum ibv_rx_hash_fields).
14493 * Pointer to the Ethernet device structure.
14494 * @param[in] action_idx
14495 * Shared RSS action ipool index.
14496 * @param[in, out] action
14497 * Partially initialized shared RSS action.
14498 * @param[out] error
14499 * Perform verbose error reporting if not NULL. Initialized in case of
14503 * 0 on success, otherwise negative errno value.
14506 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14507 uint32_t action_idx,
14508 struct mlx5_shared_action_rss *shared_rss,
14509 struct rte_flow_error *error)
14511 struct mlx5_flow_rss_desc rss_desc = { 0 };
14515 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14516 return rte_flow_error_set(error, rte_errno,
14517 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14518 "cannot setup indirection table");
14520 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14521 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14522 rss_desc.const_q = shared_rss->origin.queue;
14523 rss_desc.queue_num = shared_rss->origin.queue_num;
14524 /* Set non-zero value to indicate a shared RSS. */
14525 rss_desc.shared_rss = action_idx;
14526 rss_desc.ind_tbl = shared_rss->ind_tbl;
14527 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14529 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14532 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14533 if (shared_rss->origin.level > 1) {
14534 hash_fields |= IBV_RX_HASH_INNER;
14537 rss_desc.tunnel = tunnel;
14538 rss_desc.hash_fields = hash_fields;
14539 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14543 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14544 "cannot get hash queue");
14545 goto error_hrxq_new;
14547 err = __flow_dv_action_rss_hrxq_set
14548 (shared_rss, hash_fields, hrxq_idx);
14554 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14555 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14556 shared_rss->ind_tbl = NULL;
14562 * Create shared RSS action.
14565 * Pointer to the Ethernet device structure.
14567 * Shared action configuration.
14569 * RSS action specification used to create shared action.
14570 * @param[out] error
14571 * Perform verbose error reporting if not NULL. Initialized in case of
14575 * A valid shared action ID in case of success, 0 otherwise and
14576 * rte_errno is set.
14579 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14580 const struct rte_flow_indir_action_conf *conf,
14581 const struct rte_flow_action_rss *rss,
14582 struct rte_flow_error *error)
14584 struct mlx5_priv *priv = dev->data->dev_private;
14585 struct mlx5_shared_action_rss *shared_rss = NULL;
14586 void *queue = NULL;
14587 struct rte_flow_action_rss *origin;
14588 const uint8_t *rss_key;
14589 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14592 RTE_SET_USED(conf);
14593 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14595 shared_rss = mlx5_ipool_zmalloc
14596 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14597 if (!shared_rss || !queue) {
14598 rte_flow_error_set(error, ENOMEM,
14599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14600 "cannot allocate resource memory");
14601 goto error_rss_init;
14603 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14604 rte_flow_error_set(error, E2BIG,
14605 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14606 "rss action number out of range");
14607 goto error_rss_init;
14609 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14610 sizeof(*shared_rss->ind_tbl),
14612 if (!shared_rss->ind_tbl) {
14613 rte_flow_error_set(error, ENOMEM,
14614 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14615 "cannot allocate resource memory");
14616 goto error_rss_init;
14618 memcpy(queue, rss->queue, queue_size);
14619 shared_rss->ind_tbl->queues = queue;
14620 shared_rss->ind_tbl->queues_n = rss->queue_num;
14621 origin = &shared_rss->origin;
14622 origin->func = rss->func;
14623 origin->level = rss->level;
14624 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
14625 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
14626 /* NULL RSS key indicates default RSS key. */
14627 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14628 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14629 origin->key = &shared_rss->key[0];
14630 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14631 origin->queue = queue;
14632 origin->queue_num = rss->queue_num;
14633 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14634 goto error_rss_init;
14635 rte_spinlock_init(&shared_rss->action_rss_sl);
14636 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14637 rte_spinlock_lock(&priv->shared_act_sl);
14638 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14639 &priv->rss_shared_actions, idx, shared_rss, next);
14640 rte_spinlock_unlock(&priv->shared_act_sl);
14644 if (shared_rss->ind_tbl)
14645 mlx5_free(shared_rss->ind_tbl);
14646 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14655 * Destroy the shared RSS action.
14656 * Release related hash RX queue objects.
14659 * Pointer to the Ethernet device structure.
14661 * The shared RSS action object ID to be removed.
14662 * @param[out] error
14663 * Perform verbose error reporting if not NULL. Initialized in case of
14667 * 0 on success, otherwise negative errno value.
14670 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14671 struct rte_flow_error *error)
14673 struct mlx5_priv *priv = dev->data->dev_private;
14674 struct mlx5_shared_action_rss *shared_rss =
14675 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14676 uint32_t old_refcnt = 1;
14678 uint16_t *queue = NULL;
14681 return rte_flow_error_set(error, EINVAL,
14682 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14683 "invalid shared action");
14684 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14686 return rte_flow_error_set(error, EBUSY,
14687 RTE_FLOW_ERROR_TYPE_ACTION,
14689 "shared rss hrxq has references");
14690 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14691 0, 0, __ATOMIC_ACQUIRE,
14693 return rte_flow_error_set(error, EBUSY,
14694 RTE_FLOW_ERROR_TYPE_ACTION,
14696 "shared rss has references");
14697 queue = shared_rss->ind_tbl->queues;
14698 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14700 return rte_flow_error_set(error, EBUSY,
14701 RTE_FLOW_ERROR_TYPE_ACTION,
14703 "shared rss indirection table has"
14706 rte_spinlock_lock(&priv->shared_act_sl);
14707 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14708 &priv->rss_shared_actions, idx, shared_rss, next);
14709 rte_spinlock_unlock(&priv->shared_act_sl);
14710 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14716 * Create indirect action, lock free,
14717 * (mutex should be acquired by caller).
14718 * Dispatcher for action type specific call.
14721 * Pointer to the Ethernet device structure.
14723 * Shared action configuration.
14724 * @param[in] action
14725 * Action specification used to create indirect action.
14726 * @param[out] error
14727 * Perform verbose error reporting if not NULL. Initialized in case of
14731 * A valid shared action handle in case of success, NULL otherwise and
14732 * rte_errno is set.
14734 static struct rte_flow_action_handle *
14735 flow_dv_action_create(struct rte_eth_dev *dev,
14736 const struct rte_flow_indir_action_conf *conf,
14737 const struct rte_flow_action *action,
14738 struct rte_flow_error *err)
14740 struct mlx5_priv *priv = dev->data->dev_private;
14741 uint32_t age_idx = 0;
14745 switch (action->type) {
14746 case RTE_FLOW_ACTION_TYPE_RSS:
14747 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14748 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14749 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14751 case RTE_FLOW_ACTION_TYPE_AGE:
14752 age_idx = flow_dv_aso_age_alloc(dev, err);
14757 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14758 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14759 flow_dv_aso_age_params_init(dev, age_idx,
14760 ((const struct rte_flow_action_age *)
14761 action->conf)->context ?
14762 ((const struct rte_flow_action_age *)
14763 action->conf)->context :
14764 (void *)(uintptr_t)idx,
14765 ((const struct rte_flow_action_age *)
14766 action->conf)->timeout);
14769 case RTE_FLOW_ACTION_TYPE_COUNT:
14770 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14771 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14772 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14774 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14775 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14777 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14780 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14781 NULL, "action type not supported");
14784 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14788 * Destroy the indirect action.
14789 * Release action related resources on the NIC and the memory.
14790 * Lock free, (mutex should be acquired by caller).
14791 * Dispatcher for action type specific call.
14794 * Pointer to the Ethernet device structure.
14795 * @param[in] handle
14796 * The indirect action object handle to be removed.
14797 * @param[out] error
14798 * Perform verbose error reporting if not NULL. Initialized in case of
14802 * 0 on success, otherwise negative errno value.
14805 flow_dv_action_destroy(struct rte_eth_dev *dev,
14806 struct rte_flow_action_handle *handle,
14807 struct rte_flow_error *error)
14809 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14810 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14811 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14812 struct mlx5_flow_counter *cnt;
14813 uint32_t no_flow_refcnt = 1;
14817 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14818 return __flow_dv_action_rss_release(dev, idx, error);
14819 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14820 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14821 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14822 &no_flow_refcnt, 1, false,
14825 return rte_flow_error_set(error, EBUSY,
14826 RTE_FLOW_ERROR_TYPE_ACTION,
14828 "Indirect count action has references");
14829 flow_dv_counter_free(dev, idx);
14831 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14832 ret = flow_dv_aso_age_release(dev, idx);
14835 * In this case, the last flow has a reference will
14836 * actually release the age action.
14838 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14839 " released with references %d.", idx, ret);
14841 case MLX5_INDIRECT_ACTION_TYPE_CT:
14842 ret = flow_dv_aso_ct_release(dev, idx);
14846 DRV_LOG(DEBUG, "Connection tracking object %u still "
14847 "has references %d.", idx, ret);
14850 return rte_flow_error_set(error, ENOTSUP,
14851 RTE_FLOW_ERROR_TYPE_ACTION,
14853 "action type not supported");
14858 * Updates in place shared RSS action configuration.
14861 * Pointer to the Ethernet device structure.
14863 * The shared RSS action object ID to be updated.
14864 * @param[in] action_conf
14865 * RSS action specification used to modify *shared_rss*.
14866 * @param[out] error
14867 * Perform verbose error reporting if not NULL. Initialized in case of
14871 * 0 on success, otherwise negative errno value.
14872 * @note: currently only support update of RSS queues.
14875 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
14876 const struct rte_flow_action_rss *action_conf,
14877 struct rte_flow_error *error)
14879 struct mlx5_priv *priv = dev->data->dev_private;
14880 struct mlx5_shared_action_rss *shared_rss =
14881 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14883 void *queue = NULL;
14884 uint16_t *queue_old = NULL;
14885 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
14888 return rte_flow_error_set(error, EINVAL,
14889 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14890 "invalid shared action to update");
14891 if (priv->obj_ops.ind_table_modify == NULL)
14892 return rte_flow_error_set(error, ENOTSUP,
14893 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14894 "cannot modify indirection table");
14895 queue = mlx5_malloc(MLX5_MEM_ZERO,
14896 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14899 return rte_flow_error_set(error, ENOMEM,
14900 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14902 "cannot allocate resource memory");
14903 memcpy(queue, action_conf->queue, queue_size);
14904 MLX5_ASSERT(shared_rss->ind_tbl);
14905 rte_spinlock_lock(&shared_rss->action_rss_sl);
14906 queue_old = shared_rss->ind_tbl->queues;
14907 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
14908 queue, action_conf->queue_num, true);
14911 ret = rte_flow_error_set(error, rte_errno,
14912 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14913 "cannot update indirection table");
14915 mlx5_free(queue_old);
14916 shared_rss->origin.queue = queue;
14917 shared_rss->origin.queue_num = action_conf->queue_num;
14919 rte_spinlock_unlock(&shared_rss->action_rss_sl);
14924 * Updates in place conntrack context or direction.
14925 * Context update should be synchronized.
14928 * Pointer to the Ethernet device structure.
14930 * The conntrack object ID to be updated.
14931 * @param[in] update
14932 * Pointer to the structure of information to update.
14933 * @param[out] error
14934 * Perform verbose error reporting if not NULL. Initialized in case of
14938 * 0 on success, otherwise negative errno value.
14941 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
14942 const struct rte_flow_modify_conntrack *update,
14943 struct rte_flow_error *error)
14945 struct mlx5_priv *priv = dev->data->dev_private;
14946 struct mlx5_aso_ct_action *ct;
14947 const struct rte_flow_action_conntrack *new_prf;
14949 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
14952 if (PORT_ID(priv) != owner)
14953 return rte_flow_error_set(error, EACCES,
14954 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14956 "CT object owned by another port");
14957 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
14958 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
14960 return rte_flow_error_set(error, ENOMEM,
14961 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14963 "CT object is inactive");
14964 new_prf = &update->new_ct;
14965 if (update->direction)
14966 ct->is_original = !!new_prf->is_original_dir;
14967 if (update->state) {
14968 /* Only validate the profile when it needs to be updated. */
14969 ret = mlx5_validate_action_ct(dev, new_prf, error);
14972 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
14974 return rte_flow_error_set(error, EIO,
14975 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14977 "Failed to send CT context update WQE");
14978 /* Block until ready or a failure. */
14979 ret = mlx5_aso_ct_available(priv->sh, ct);
14981 rte_flow_error_set(error, rte_errno,
14982 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14984 "Timeout to get the CT update");
14990 * Updates in place shared action configuration, lock free,
14991 * (mutex should be acquired by caller).
14994 * Pointer to the Ethernet device structure.
14995 * @param[in] handle
14996 * The indirect action object handle to be updated.
14997 * @param[in] update
14998 * Action specification used to modify the action pointed by *handle*.
14999 * *update* could be of same type with the action pointed by the *handle*
15000 * handle argument, or some other structures like a wrapper, depending on
15001 * the indirect action type.
15002 * @param[out] error
15003 * Perform verbose error reporting if not NULL. Initialized in case of
15007 * 0 on success, otherwise negative errno value.
15010 flow_dv_action_update(struct rte_eth_dev *dev,
15011 struct rte_flow_action_handle *handle,
15012 const void *update,
15013 struct rte_flow_error *err)
15015 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15016 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15017 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15018 const void *action_conf;
15021 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15022 action_conf = ((const struct rte_flow_action *)update)->conf;
15023 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15024 case MLX5_INDIRECT_ACTION_TYPE_CT:
15025 return __flow_dv_action_ct_update(dev, idx, update, err);
15027 return rte_flow_error_set(err, ENOTSUP,
15028 RTE_FLOW_ERROR_TYPE_ACTION,
15030 "action type update not supported");
15035 * Destroy the meter sub policy table rules.
15036 * Lock free, (mutex should be acquired by caller).
15039 * Pointer to Ethernet device.
15040 * @param[in] sub_policy
15041 * Pointer to meter sub policy table.
15044 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15045 struct mlx5_flow_meter_sub_policy *sub_policy)
15047 struct mlx5_priv *priv = dev->data->dev_private;
15048 struct mlx5_flow_tbl_data_entry *tbl;
15049 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15050 struct mlx5_flow_meter_info *next_fm;
15051 struct mlx5_sub_policy_color_rule *color_rule;
15055 for (i = 0; i < RTE_COLORS; i++) {
15057 if (i == RTE_COLOR_GREEN && policy &&
15058 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15059 next_fm = mlx5_flow_meter_find(priv,
15060 policy->act_cnt[i].next_mtr_id, NULL);
15061 TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15063 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15064 tbl = container_of(color_rule->matcher->tbl,
15065 typeof(*tbl), tbl);
15066 mlx5_list_unregister(tbl->matchers,
15067 &color_rule->matcher->entry);
15068 TAILQ_REMOVE(&sub_policy->color_rules[i],
15069 color_rule, next_port);
15070 mlx5_free(color_rule);
15072 mlx5_flow_meter_detach(priv, next_fm);
15075 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15076 if (sub_policy->rix_hrxq[i]) {
15077 if (policy && !policy->is_hierarchy)
15078 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15079 sub_policy->rix_hrxq[i] = 0;
15081 if (sub_policy->jump_tbl[i]) {
15082 flow_dv_tbl_resource_release(MLX5_SH(dev),
15083 sub_policy->jump_tbl[i]);
15084 sub_policy->jump_tbl[i] = NULL;
15087 if (sub_policy->tbl_rsc) {
15088 flow_dv_tbl_resource_release(MLX5_SH(dev),
15089 sub_policy->tbl_rsc);
15090 sub_policy->tbl_rsc = NULL;
15095 * Destroy policy rules, lock free,
15096 * (mutex should be acquired by caller).
15097 * Dispatcher for action type specific call.
15100 * Pointer to the Ethernet device structure.
15101 * @param[in] mtr_policy
15102 * Meter policy struct.
15105 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15106 struct mlx5_flow_meter_policy *mtr_policy)
15109 struct mlx5_flow_meter_sub_policy *sub_policy;
15110 uint16_t sub_policy_num;
15112 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15113 sub_policy_num = (mtr_policy->sub_policy_num >>
15114 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15115 MLX5_MTR_SUB_POLICY_NUM_MASK;
15116 for (j = 0; j < sub_policy_num; j++) {
15117 sub_policy = mtr_policy->sub_policys[i][j];
15119 __flow_dv_destroy_sub_policy_rules(dev,
15126 * Destroy policy action, lock free,
15127 * (mutex should be acquired by caller).
15128 * Dispatcher for action type specific call.
15131 * Pointer to the Ethernet device structure.
15132 * @param[in] mtr_policy
15133 * Meter policy struct.
15136 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15137 struct mlx5_flow_meter_policy *mtr_policy)
15139 struct rte_flow_action *rss_action;
15140 struct mlx5_flow_handle dev_handle;
15143 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15144 if (mtr_policy->act_cnt[i].rix_mark) {
15145 flow_dv_tag_release(dev,
15146 mtr_policy->act_cnt[i].rix_mark);
15147 mtr_policy->act_cnt[i].rix_mark = 0;
15149 if (mtr_policy->act_cnt[i].modify_hdr) {
15150 dev_handle.dvh.modify_hdr =
15151 mtr_policy->act_cnt[i].modify_hdr;
15152 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15154 switch (mtr_policy->act_cnt[i].fate_action) {
15155 case MLX5_FLOW_FATE_SHARED_RSS:
15156 rss_action = mtr_policy->act_cnt[i].rss;
15157 mlx5_free(rss_action);
15159 case MLX5_FLOW_FATE_PORT_ID:
15160 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15161 flow_dv_port_id_action_resource_release(dev,
15162 mtr_policy->act_cnt[i].rix_port_id_action);
15163 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15166 case MLX5_FLOW_FATE_DROP:
15167 case MLX5_FLOW_FATE_JUMP:
15168 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15169 mtr_policy->act_cnt[i].dr_jump_action[j] =
15173 /*Queue action do nothing*/
15177 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15178 mtr_policy->dr_drop_action[j] = NULL;
15182 * Create policy action per domain, lock free,
15183 * (mutex should be acquired by caller).
15184 * Dispatcher for action type specific call.
15187 * Pointer to the Ethernet device structure.
15188 * @param[in] mtr_policy
15189 * Meter policy struct.
15190 * @param[in] action
15191 * Action specification used to create meter actions.
15192 * @param[out] error
15193 * Perform verbose error reporting if not NULL. Initialized in case of
15197 * 0 on success, otherwise negative errno value.
15200 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15201 struct mlx5_flow_meter_policy *mtr_policy,
15202 const struct rte_flow_action *actions[RTE_COLORS],
15203 enum mlx5_meter_domain domain,
15204 struct rte_mtr_error *error)
15206 struct mlx5_priv *priv = dev->data->dev_private;
15207 struct rte_flow_error flow_err;
15208 const struct rte_flow_action *act;
15209 uint64_t action_flags;
15210 struct mlx5_flow_handle dh;
15211 struct mlx5_flow dev_flow;
15212 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15214 uint8_t egress, transfer;
15215 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15217 struct mlx5_flow_dv_modify_hdr_resource res;
15218 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15219 sizeof(struct mlx5_modification_cmd) *
15220 (MLX5_MAX_MODIFY_NUM + 1)];
15222 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15224 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15225 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15226 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15227 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15228 memset(&port_id_action, 0,
15229 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15230 memset(mhdr_res, 0, sizeof(*mhdr_res));
15231 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15232 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15233 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15234 dev_flow.handle = &dh;
15235 dev_flow.dv.port_id_action = &port_id_action;
15236 dev_flow.external = true;
15237 for (i = 0; i < RTE_COLORS; i++) {
15238 if (i < MLX5_MTR_RTE_COLORS)
15239 act_cnt = &mtr_policy->act_cnt[i];
15241 for (act = actions[i];
15242 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15243 switch (act->type) {
15244 case RTE_FLOW_ACTION_TYPE_MARK:
15246 uint32_t tag_be = mlx5_flow_mark_set
15247 (((const struct rte_flow_action_mark *)
15250 if (i >= MLX5_MTR_RTE_COLORS)
15251 return -rte_mtr_error_set(error,
15253 RTE_MTR_ERROR_TYPE_METER_POLICY,
15255 "cannot create policy "
15256 "mark action for this color");
15257 dev_flow.handle->mark = 1;
15258 if (flow_dv_tag_resource_register(dev, tag_be,
15259 &dev_flow, &flow_err))
15260 return -rte_mtr_error_set(error,
15262 RTE_MTR_ERROR_TYPE_METER_POLICY,
15264 "cannot setup policy mark action");
15265 MLX5_ASSERT(dev_flow.dv.tag_resource);
15266 act_cnt->rix_mark =
15267 dev_flow.handle->dvh.rix_tag;
15268 action_flags |= MLX5_FLOW_ACTION_MARK;
15271 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15272 if (i >= MLX5_MTR_RTE_COLORS)
15273 return -rte_mtr_error_set(error,
15275 RTE_MTR_ERROR_TYPE_METER_POLICY,
15277 "cannot create policy "
15278 "set tag action for this color");
15279 if (flow_dv_convert_action_set_tag
15281 (const struct rte_flow_action_set_tag *)
15282 act->conf, &flow_err))
15283 return -rte_mtr_error_set(error,
15285 RTE_MTR_ERROR_TYPE_METER_POLICY,
15286 NULL, "cannot convert policy "
15288 if (!mhdr_res->actions_num)
15289 return -rte_mtr_error_set(error,
15291 RTE_MTR_ERROR_TYPE_METER_POLICY,
15292 NULL, "cannot find policy "
15294 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15296 case RTE_FLOW_ACTION_TYPE_DROP:
15298 struct mlx5_flow_mtr_mng *mtrmng =
15300 struct mlx5_flow_tbl_data_entry *tbl_data;
15303 * Create the drop table with
15304 * METER DROP level.
15306 if (!mtrmng->drop_tbl[domain]) {
15307 mtrmng->drop_tbl[domain] =
15308 flow_dv_tbl_resource_get(dev,
15309 MLX5_FLOW_TABLE_LEVEL_METER,
15310 egress, transfer, false, NULL, 0,
15311 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15312 if (!mtrmng->drop_tbl[domain])
15313 return -rte_mtr_error_set
15315 RTE_MTR_ERROR_TYPE_METER_POLICY,
15317 "Failed to create meter drop table");
15319 tbl_data = container_of
15320 (mtrmng->drop_tbl[domain],
15321 struct mlx5_flow_tbl_data_entry, tbl);
15322 if (i < MLX5_MTR_RTE_COLORS) {
15323 act_cnt->dr_jump_action[domain] =
15324 tbl_data->jump.action;
15325 act_cnt->fate_action =
15326 MLX5_FLOW_FATE_DROP;
15328 if (i == RTE_COLOR_RED)
15329 mtr_policy->dr_drop_action[domain] =
15330 tbl_data->jump.action;
15331 action_flags |= MLX5_FLOW_ACTION_DROP;
15334 case RTE_FLOW_ACTION_TYPE_QUEUE:
15336 if (i >= MLX5_MTR_RTE_COLORS)
15337 return -rte_mtr_error_set(error,
15339 RTE_MTR_ERROR_TYPE_METER_POLICY,
15340 NULL, "cannot create policy "
15341 "fate queue for this color");
15343 ((const struct rte_flow_action_queue *)
15344 (act->conf))->index;
15345 act_cnt->fate_action =
15346 MLX5_FLOW_FATE_QUEUE;
15347 dev_flow.handle->fate_action =
15348 MLX5_FLOW_FATE_QUEUE;
15349 mtr_policy->is_queue = 1;
15350 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15353 case RTE_FLOW_ACTION_TYPE_RSS:
15357 if (i >= MLX5_MTR_RTE_COLORS)
15358 return -rte_mtr_error_set(error,
15360 RTE_MTR_ERROR_TYPE_METER_POLICY,
15362 "cannot create policy "
15363 "rss action for this color");
15365 * Save RSS conf into policy struct
15366 * for translate stage.
15368 rss_size = (int)rte_flow_conv
15369 (RTE_FLOW_CONV_OP_ACTION,
15370 NULL, 0, act, &flow_err);
15372 return -rte_mtr_error_set(error,
15374 RTE_MTR_ERROR_TYPE_METER_POLICY,
15375 NULL, "Get the wrong "
15376 "rss action struct size");
15377 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15378 rss_size, 0, SOCKET_ID_ANY);
15380 return -rte_mtr_error_set(error,
15382 RTE_MTR_ERROR_TYPE_METER_POLICY,
15384 "Fail to malloc rss action memory");
15385 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15386 act_cnt->rss, rss_size,
15389 return -rte_mtr_error_set(error,
15391 RTE_MTR_ERROR_TYPE_METER_POLICY,
15392 NULL, "Fail to save "
15393 "rss action into policy struct");
15394 act_cnt->fate_action =
15395 MLX5_FLOW_FATE_SHARED_RSS;
15396 action_flags |= MLX5_FLOW_ACTION_RSS;
15399 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15401 struct mlx5_flow_dv_port_id_action_resource
15403 uint32_t port_id = 0;
15405 if (i >= MLX5_MTR_RTE_COLORS)
15406 return -rte_mtr_error_set(error,
15408 RTE_MTR_ERROR_TYPE_METER_POLICY,
15409 NULL, "cannot create policy "
15410 "port action for this color");
15411 memset(&port_id_resource, 0,
15412 sizeof(port_id_resource));
15413 if (flow_dv_translate_action_port_id(dev, act,
15414 &port_id, &flow_err))
15415 return -rte_mtr_error_set(error,
15417 RTE_MTR_ERROR_TYPE_METER_POLICY,
15418 NULL, "cannot translate "
15419 "policy port action");
15420 port_id_resource.port_id = port_id;
15421 if (flow_dv_port_id_action_resource_register
15422 (dev, &port_id_resource,
15423 &dev_flow, &flow_err))
15424 return -rte_mtr_error_set(error,
15426 RTE_MTR_ERROR_TYPE_METER_POLICY,
15427 NULL, "cannot setup "
15428 "policy port action");
15429 act_cnt->rix_port_id_action =
15430 dev_flow.handle->rix_port_id_action;
15431 act_cnt->fate_action =
15432 MLX5_FLOW_FATE_PORT_ID;
15433 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15436 case RTE_FLOW_ACTION_TYPE_JUMP:
15438 uint32_t jump_group = 0;
15439 uint32_t table = 0;
15440 struct mlx5_flow_tbl_data_entry *tbl_data;
15441 struct flow_grp_info grp_info = {
15442 .external = !!dev_flow.external,
15443 .transfer = !!transfer,
15444 .fdb_def_rule = !!priv->fdb_def_rule,
15446 .skip_scale = dev_flow.skip_scale &
15447 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15449 struct mlx5_flow_meter_sub_policy *sub_policy =
15450 mtr_policy->sub_policys[domain][0];
15452 if (i >= MLX5_MTR_RTE_COLORS)
15453 return -rte_mtr_error_set(error,
15455 RTE_MTR_ERROR_TYPE_METER_POLICY,
15457 "cannot create policy "
15458 "jump action for this color");
15460 ((const struct rte_flow_action_jump *)
15462 if (mlx5_flow_group_to_table(dev, NULL,
15465 &grp_info, &flow_err))
15466 return -rte_mtr_error_set(error,
15468 RTE_MTR_ERROR_TYPE_METER_POLICY,
15469 NULL, "cannot setup "
15470 "policy jump action");
15471 sub_policy->jump_tbl[i] =
15472 flow_dv_tbl_resource_get(dev,
15475 !!dev_flow.external,
15476 NULL, jump_group, 0,
15479 (!sub_policy->jump_tbl[i])
15480 return -rte_mtr_error_set(error,
15482 RTE_MTR_ERROR_TYPE_METER_POLICY,
15483 NULL, "cannot create jump action.");
15484 tbl_data = container_of
15485 (sub_policy->jump_tbl[i],
15486 struct mlx5_flow_tbl_data_entry, tbl);
15487 act_cnt->dr_jump_action[domain] =
15488 tbl_data->jump.action;
15489 act_cnt->fate_action =
15490 MLX5_FLOW_FATE_JUMP;
15491 action_flags |= MLX5_FLOW_ACTION_JUMP;
15495 * No need to check meter hierarchy for Y or R colors
15496 * here since it is done in the validation stage.
15498 case RTE_FLOW_ACTION_TYPE_METER:
15500 const struct rte_flow_action_meter *mtr;
15501 struct mlx5_flow_meter_info *next_fm;
15502 struct mlx5_flow_meter_policy *next_policy;
15503 struct rte_flow_action tag_action;
15504 struct mlx5_rte_flow_action_set_tag set_tag;
15505 uint32_t next_mtr_idx = 0;
15508 next_fm = mlx5_flow_meter_find(priv,
15512 return -rte_mtr_error_set(error, EINVAL,
15513 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15514 "Fail to find next meter.");
15515 if (next_fm->def_policy)
15516 return -rte_mtr_error_set(error, EINVAL,
15517 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15518 "Hierarchy only supports termination meter.");
15519 next_policy = mlx5_flow_meter_policy_find(dev,
15520 next_fm->policy_id, NULL);
15521 MLX5_ASSERT(next_policy);
15522 if (next_fm->drop_cnt) {
15525 mlx5_flow_get_reg_id(dev,
15528 (struct rte_flow_error *)error);
15529 set_tag.offset = (priv->mtr_reg_share ?
15530 MLX5_MTR_COLOR_BITS : 0);
15531 set_tag.length = (priv->mtr_reg_share ?
15532 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15534 set_tag.data = next_mtr_idx;
15536 (enum rte_flow_action_type)
15537 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15538 tag_action.conf = &set_tag;
15539 if (flow_dv_convert_action_set_reg
15540 (mhdr_res, &tag_action,
15541 (struct rte_flow_error *)error))
15544 MLX5_FLOW_ACTION_SET_TAG;
15546 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15547 act_cnt->next_mtr_id = next_fm->meter_id;
15548 act_cnt->next_sub_policy = NULL;
15549 mtr_policy->is_hierarchy = 1;
15550 mtr_policy->dev = next_policy->dev;
15552 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15556 return -rte_mtr_error_set(error, ENOTSUP,
15557 RTE_MTR_ERROR_TYPE_METER_POLICY,
15558 NULL, "action type not supported");
15560 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15561 /* create modify action if needed. */
15562 dev_flow.dv.group = 1;
15563 if (flow_dv_modify_hdr_resource_register
15564 (dev, mhdr_res, &dev_flow, &flow_err))
15565 return -rte_mtr_error_set(error,
15567 RTE_MTR_ERROR_TYPE_METER_POLICY,
15568 NULL, "cannot register policy "
15570 act_cnt->modify_hdr =
15571 dev_flow.handle->dvh.modify_hdr;
15579 * Create policy action per domain, lock free,
15580 * (mutex should be acquired by caller).
15581 * Dispatcher for action type specific call.
15584 * Pointer to the Ethernet device structure.
15585 * @param[in] mtr_policy
15586 * Meter policy struct.
15587 * @param[in] action
15588 * Action specification used to create meter actions.
15589 * @param[out] error
15590 * Perform verbose error reporting if not NULL. Initialized in case of
15594 * 0 on success, otherwise negative errno value.
15597 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15598 struct mlx5_flow_meter_policy *mtr_policy,
15599 const struct rte_flow_action *actions[RTE_COLORS],
15600 struct rte_mtr_error *error)
15603 uint16_t sub_policy_num;
15605 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15606 sub_policy_num = (mtr_policy->sub_policy_num >>
15607 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15608 MLX5_MTR_SUB_POLICY_NUM_MASK;
15609 if (sub_policy_num) {
15610 ret = __flow_dv_create_domain_policy_acts(dev,
15611 mtr_policy, actions,
15612 (enum mlx5_meter_domain)i, error);
15613 /* Cleaning resource is done in the caller level. */
15622 * Query a DV flow rule for its statistics via DevX.
15625 * Pointer to Ethernet device.
15626 * @param[in] cnt_idx
15627 * Index to the flow counter.
15629 * Data retrieved by the query.
15630 * @param[out] error
15631 * Perform verbose error reporting if not NULL.
15634 * 0 on success, a negative errno value otherwise and rte_errno is set.
15637 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15638 struct rte_flow_error *error)
15640 struct mlx5_priv *priv = dev->data->dev_private;
15641 struct rte_flow_query_count *qc = data;
15643 if (!priv->config.devx)
15644 return rte_flow_error_set(error, ENOTSUP,
15645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15647 "counters are not supported");
15649 uint64_t pkts, bytes;
15650 struct mlx5_flow_counter *cnt;
15651 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15654 return rte_flow_error_set(error, -err,
15655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15656 NULL, "cannot read counters");
15657 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15660 qc->hits = pkts - cnt->hits;
15661 qc->bytes = bytes - cnt->bytes;
15664 cnt->bytes = bytes;
15668 return rte_flow_error_set(error, EINVAL,
15669 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15671 "counters are not available");
15675 flow_dv_action_query(struct rte_eth_dev *dev,
15676 const struct rte_flow_action_handle *handle, void *data,
15677 struct rte_flow_error *error)
15679 struct mlx5_age_param *age_param;
15680 struct rte_flow_query_age *resp;
15681 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15682 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15683 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15684 struct mlx5_priv *priv = dev->data->dev_private;
15685 struct mlx5_aso_ct_action *ct;
15690 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15691 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15693 resp->aged = __atomic_load_n(&age_param->state,
15694 __ATOMIC_RELAXED) == AGE_TMOUT ?
15696 resp->sec_since_last_hit_valid = !resp->aged;
15697 if (resp->sec_since_last_hit_valid)
15698 resp->sec_since_last_hit = __atomic_load_n
15699 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15701 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15702 return flow_dv_query_count(dev, idx, data, error);
15703 case MLX5_INDIRECT_ACTION_TYPE_CT:
15704 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15705 if (owner != PORT_ID(priv))
15706 return rte_flow_error_set(error, EACCES,
15707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15709 "CT object owned by another port");
15710 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15711 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15714 return rte_flow_error_set(error, EFAULT,
15715 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15717 "CT object is inactive");
15718 ((struct rte_flow_action_conntrack *)data)->peer_port =
15720 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15722 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15723 return rte_flow_error_set(error, EIO,
15724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15726 "Failed to query CT context");
15729 return rte_flow_error_set(error, ENOTSUP,
15730 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15731 "action type query not supported");
15736 * Query a flow rule AGE action for aging information.
15739 * Pointer to Ethernet device.
15741 * Pointer to the sub flow.
15743 * data retrieved by the query.
15744 * @param[out] error
15745 * Perform verbose error reporting if not NULL.
15748 * 0 on success, a negative errno value otherwise and rte_errno is set.
15751 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15752 void *data, struct rte_flow_error *error)
15754 struct rte_flow_query_age *resp = data;
15755 struct mlx5_age_param *age_param;
15758 struct mlx5_aso_age_action *act =
15759 flow_aso_age_get_by_idx(dev, flow->age);
15761 age_param = &act->age_params;
15762 } else if (flow->counter) {
15763 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15765 if (!age_param || !age_param->timeout)
15766 return rte_flow_error_set
15768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15769 NULL, "cannot read age data");
15771 return rte_flow_error_set(error, EINVAL,
15772 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15773 NULL, "age data not available");
15775 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15777 resp->sec_since_last_hit_valid = !resp->aged;
15778 if (resp->sec_since_last_hit_valid)
15779 resp->sec_since_last_hit = __atomic_load_n
15780 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15787 * @see rte_flow_query()
15788 * @see rte_flow_ops
15791 flow_dv_query(struct rte_eth_dev *dev,
15792 struct rte_flow *flow __rte_unused,
15793 const struct rte_flow_action *actions __rte_unused,
15794 void *data __rte_unused,
15795 struct rte_flow_error *error __rte_unused)
15799 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15800 switch (actions->type) {
15801 case RTE_FLOW_ACTION_TYPE_VOID:
15803 case RTE_FLOW_ACTION_TYPE_COUNT:
15804 ret = flow_dv_query_count(dev, flow->counter, data,
15807 case RTE_FLOW_ACTION_TYPE_AGE:
15808 ret = flow_dv_query_age(dev, flow, data, error);
15811 return rte_flow_error_set(error, ENOTSUP,
15812 RTE_FLOW_ERROR_TYPE_ACTION,
15814 "action not supported");
15821 * Destroy the meter table set.
15822 * Lock free, (mutex should be acquired by caller).
15825 * Pointer to Ethernet device.
15827 * Meter information table.
15830 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
15831 struct mlx5_flow_meter_info *fm)
15833 struct mlx5_priv *priv = dev->data->dev_private;
15836 if (!fm || !priv->config.dv_flow_en)
15838 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15839 if (fm->drop_rule[i]) {
15840 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
15841 fm->drop_rule[i] = NULL;
15847 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
15849 struct mlx5_priv *priv = dev->data->dev_private;
15850 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15851 struct mlx5_flow_tbl_data_entry *tbl;
15854 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15855 if (mtrmng->def_rule[i]) {
15856 claim_zero(mlx5_flow_os_destroy_flow
15857 (mtrmng->def_rule[i]));
15858 mtrmng->def_rule[i] = NULL;
15860 if (mtrmng->def_matcher[i]) {
15861 tbl = container_of(mtrmng->def_matcher[i]->tbl,
15862 struct mlx5_flow_tbl_data_entry, tbl);
15863 mlx5_list_unregister(tbl->matchers,
15864 &mtrmng->def_matcher[i]->entry);
15865 mtrmng->def_matcher[i] = NULL;
15867 for (j = 0; j < MLX5_REG_BITS; j++) {
15868 if (mtrmng->drop_matcher[i][j]) {
15870 container_of(mtrmng->drop_matcher[i][j]->tbl,
15871 struct mlx5_flow_tbl_data_entry,
15873 mlx5_list_unregister(tbl->matchers,
15874 &mtrmng->drop_matcher[i][j]->entry);
15875 mtrmng->drop_matcher[i][j] = NULL;
15878 if (mtrmng->drop_tbl[i]) {
15879 flow_dv_tbl_resource_release(MLX5_SH(dev),
15880 mtrmng->drop_tbl[i]);
15881 mtrmng->drop_tbl[i] = NULL;
15886 /* Number of meter flow actions, count and jump or count and drop. */
15887 #define METER_ACTIONS 2
15890 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
15891 enum mlx5_meter_domain domain)
15893 struct mlx5_priv *priv = dev->data->dev_private;
15894 struct mlx5_flow_meter_def_policy *def_policy =
15895 priv->sh->mtrmng->def_policy[domain];
15897 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
15898 mlx5_free(def_policy);
15899 priv->sh->mtrmng->def_policy[domain] = NULL;
15903 * Destroy the default policy table set.
15906 * Pointer to Ethernet device.
15909 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
15911 struct mlx5_priv *priv = dev->data->dev_private;
15914 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
15915 if (priv->sh->mtrmng->def_policy[i])
15916 __flow_dv_destroy_domain_def_policy(dev,
15917 (enum mlx5_meter_domain)i);
15918 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
15922 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
15923 uint32_t color_reg_c_idx,
15924 enum rte_color color, void *matcher_object,
15925 int actions_n, void *actions,
15926 bool match_src_port, const struct rte_flow_item *item,
15927 void **rule, const struct rte_flow_attr *attr)
15930 struct mlx5_flow_dv_match_params value = {
15931 .size = sizeof(value.buf),
15933 struct mlx5_flow_dv_match_params matcher = {
15934 .size = sizeof(matcher.buf),
15936 struct mlx5_priv *priv = dev->data->dev_private;
15939 if (match_src_port && (priv->representor || priv->master)) {
15940 if (flow_dv_translate_item_port_id(dev, matcher.buf,
15941 value.buf, item, attr)) {
15942 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
15943 " value with port.", color);
15947 flow_dv_match_meta_reg(matcher.buf, value.buf,
15948 (enum modify_reg)color_reg_c_idx,
15949 rte_col_2_mlx5_col(color), UINT32_MAX);
15950 misc_mask = flow_dv_matcher_enable(value.buf);
15951 __flow_dv_adjust_buf_size(&value.size, misc_mask);
15952 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
15953 actions_n, actions, rule);
15955 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
15962 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
15963 uint32_t color_reg_c_idx,
15965 struct mlx5_flow_meter_sub_policy *sub_policy,
15966 const struct rte_flow_attr *attr,
15967 bool match_src_port,
15968 const struct rte_flow_item *item,
15969 struct mlx5_flow_dv_matcher **policy_matcher,
15970 struct rte_flow_error *error)
15972 struct mlx5_list_entry *entry;
15973 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
15974 struct mlx5_flow_dv_matcher matcher = {
15976 .size = sizeof(matcher.mask.buf),
15980 struct mlx5_flow_dv_match_params value = {
15981 .size = sizeof(value.buf),
15983 struct mlx5_flow_cb_ctx ctx = {
15987 struct mlx5_flow_tbl_data_entry *tbl_data;
15988 struct mlx5_priv *priv = dev->data->dev_private;
15989 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
15991 if (match_src_port && (priv->representor || priv->master)) {
15992 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
15993 value.buf, item, attr)) {
15994 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
15995 " with port.", priority);
15999 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16000 if (priority < RTE_COLOR_RED)
16001 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16002 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16003 matcher.priority = priority;
16004 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16005 matcher.mask.size);
16006 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16008 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16012 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16017 * Create the policy rules per domain.
16020 * Pointer to Ethernet device.
16021 * @param[in] sub_policy
16022 * Pointer to sub policy table..
16023 * @param[in] egress
16024 * Direction of the table.
16025 * @param[in] transfer
16026 * E-Switch or NIC flow.
16028 * Pointer to policy action list per color.
16031 * 0 on success, -1 otherwise.
16034 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16035 struct mlx5_flow_meter_sub_policy *sub_policy,
16036 uint8_t egress, uint8_t transfer, bool match_src_port,
16037 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16039 struct mlx5_priv *priv = dev->data->dev_private;
16040 struct rte_flow_error flow_err;
16041 uint32_t color_reg_c_idx;
16042 struct rte_flow_attr attr = {
16043 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16046 .egress = !!egress,
16047 .transfer = !!transfer,
16051 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16052 struct mlx5_sub_policy_color_rule *color_rule;
16054 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16058 /* Create policy table with POLICY level. */
16059 if (!sub_policy->tbl_rsc)
16060 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16061 MLX5_FLOW_TABLE_LEVEL_POLICY,
16062 egress, transfer, false, NULL, 0, 0,
16063 sub_policy->idx, &flow_err);
16064 if (!sub_policy->tbl_rsc) {
16066 "Failed to create meter sub policy table.");
16069 /* Prepare matchers. */
16070 color_reg_c_idx = ret;
16071 for (i = 0; i < RTE_COLORS; i++) {
16072 TAILQ_INIT(&sub_policy->color_rules[i]);
16073 if (!acts[i].actions_n)
16075 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16076 sizeof(struct mlx5_sub_policy_color_rule),
16079 DRV_LOG(ERR, "No memory to create color rule.");
16082 tmp_rules[i] = color_rule;
16083 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16084 color_rule, next_port);
16085 color_rule->src_port = priv->representor_id;
16088 /* Create matchers for colors. */
16089 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16090 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16091 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16092 &attr, svport_match, NULL,
16093 &color_rule->matcher, &flow_err)) {
16094 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16097 /* Create flow, matching color. */
16098 if (__flow_dv_create_policy_flow(dev,
16099 color_reg_c_idx, (enum rte_color)i,
16100 color_rule->matcher->matcher_object,
16101 acts[i].actions_n, acts[i].dv_actions,
16102 svport_match, NULL, &color_rule->rule,
16104 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16110 /* All the policy rules will be cleared. */
16112 color_rule = tmp_rules[i];
16114 if (color_rule->rule)
16115 mlx5_flow_os_destroy_flow(color_rule->rule);
16116 if (color_rule->matcher) {
16117 struct mlx5_flow_tbl_data_entry *tbl =
16118 container_of(color_rule->matcher->tbl,
16119 typeof(*tbl), tbl);
16120 mlx5_list_unregister(tbl->matchers,
16121 &color_rule->matcher->entry);
16123 TAILQ_REMOVE(&sub_policy->color_rules[i],
16124 color_rule, next_port);
16125 mlx5_free(color_rule);
16132 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16133 struct mlx5_flow_meter_policy *mtr_policy,
16134 struct mlx5_flow_meter_sub_policy *sub_policy,
16137 struct mlx5_priv *priv = dev->data->dev_private;
16138 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16139 struct mlx5_flow_dv_tag_resource *tag;
16140 struct mlx5_flow_dv_port_id_action_resource *port_action;
16141 struct mlx5_hrxq *hrxq;
16142 struct mlx5_flow_meter_info *next_fm = NULL;
16143 struct mlx5_flow_meter_policy *next_policy;
16144 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16145 struct mlx5_flow_tbl_data_entry *tbl_data;
16146 struct rte_flow_error error;
16147 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16148 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16149 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16150 bool match_src_port = false;
16153 /* If RSS or Queue, no previous actions / rules is created. */
16154 for (i = 0; i < RTE_COLORS; i++) {
16155 acts[i].actions_n = 0;
16156 if (i == RTE_COLOR_RED) {
16157 /* Only support drop on red. */
16158 acts[i].dv_actions[0] =
16159 mtr_policy->dr_drop_action[domain];
16160 acts[i].actions_n = 1;
16163 if (i == RTE_COLOR_GREEN &&
16164 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16165 struct rte_flow_attr attr = {
16166 .transfer = transfer
16169 next_fm = mlx5_flow_meter_find(priv,
16170 mtr_policy->act_cnt[i].next_mtr_id,
16174 "Failed to get next hierarchy meter.");
16177 if (mlx5_flow_meter_attach(priv, next_fm,
16179 DRV_LOG(ERR, "%s", error.message);
16183 /* Meter action must be the first for TX. */
16185 acts[i].dv_actions[acts[i].actions_n] =
16186 next_fm->meter_action;
16187 acts[i].actions_n++;
16190 if (mtr_policy->act_cnt[i].rix_mark) {
16191 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16192 mtr_policy->act_cnt[i].rix_mark);
16194 DRV_LOG(ERR, "Failed to find "
16195 "mark action for policy.");
16198 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16199 acts[i].actions_n++;
16201 if (mtr_policy->act_cnt[i].modify_hdr) {
16202 acts[i].dv_actions[acts[i].actions_n] =
16203 mtr_policy->act_cnt[i].modify_hdr->action;
16204 acts[i].actions_n++;
16206 if (mtr_policy->act_cnt[i].fate_action) {
16207 switch (mtr_policy->act_cnt[i].fate_action) {
16208 case MLX5_FLOW_FATE_PORT_ID:
16209 port_action = mlx5_ipool_get
16210 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16211 mtr_policy->act_cnt[i].rix_port_id_action);
16212 if (!port_action) {
16213 DRV_LOG(ERR, "Failed to find "
16214 "port action for policy.");
16217 acts[i].dv_actions[acts[i].actions_n] =
16218 port_action->action;
16219 acts[i].actions_n++;
16220 mtr_policy->dev = dev;
16221 match_src_port = true;
16223 case MLX5_FLOW_FATE_DROP:
16224 case MLX5_FLOW_FATE_JUMP:
16225 acts[i].dv_actions[acts[i].actions_n] =
16226 mtr_policy->act_cnt[i].dr_jump_action[domain];
16227 acts[i].actions_n++;
16229 case MLX5_FLOW_FATE_SHARED_RSS:
16230 case MLX5_FLOW_FATE_QUEUE:
16231 hrxq = mlx5_ipool_get
16232 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16233 sub_policy->rix_hrxq[i]);
16235 DRV_LOG(ERR, "Failed to find "
16236 "queue action for policy.");
16239 acts[i].dv_actions[acts[i].actions_n] =
16241 acts[i].actions_n++;
16243 case MLX5_FLOW_FATE_MTR:
16246 "No next hierarchy meter.");
16250 acts[i].dv_actions[acts[i].actions_n] =
16251 next_fm->meter_action;
16252 acts[i].actions_n++;
16254 if (mtr_policy->act_cnt[i].next_sub_policy) {
16256 mtr_policy->act_cnt[i].next_sub_policy;
16259 mlx5_flow_meter_policy_find(dev,
16260 next_fm->policy_id, NULL);
16261 MLX5_ASSERT(next_policy);
16263 next_policy->sub_policys[domain][0];
16266 container_of(next_sub_policy->tbl_rsc,
16267 struct mlx5_flow_tbl_data_entry, tbl);
16268 acts[i].dv_actions[acts[i].actions_n++] =
16269 tbl_data->jump.action;
16270 if (mtr_policy->act_cnt[i].modify_hdr)
16271 match_src_port = !!transfer;
16274 /*Queue action do nothing*/
16279 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16280 egress, transfer, match_src_port, acts)) {
16282 "Failed to create policy rules per domain.");
16288 mlx5_flow_meter_detach(priv, next_fm);
16293 * Create the policy rules.
16296 * Pointer to Ethernet device.
16297 * @param[in,out] mtr_policy
16298 * Pointer to meter policy table.
16301 * 0 on success, -1 otherwise.
16304 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16305 struct mlx5_flow_meter_policy *mtr_policy)
16308 uint16_t sub_policy_num;
16310 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16311 sub_policy_num = (mtr_policy->sub_policy_num >>
16312 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16313 MLX5_MTR_SUB_POLICY_NUM_MASK;
16314 if (!sub_policy_num)
16316 /* Prepare actions list and create policy rules. */
16317 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16318 mtr_policy->sub_policys[i][0], i)) {
16319 DRV_LOG(ERR, "Failed to create policy action "
16320 "list per domain.");
16328 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16330 struct mlx5_priv *priv = dev->data->dev_private;
16331 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16332 struct mlx5_flow_meter_def_policy *def_policy;
16333 struct mlx5_flow_tbl_resource *jump_tbl;
16334 struct mlx5_flow_tbl_data_entry *tbl_data;
16335 uint8_t egress, transfer;
16336 struct rte_flow_error error;
16337 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16340 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16341 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16342 def_policy = mtrmng->def_policy[domain];
16344 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16345 sizeof(struct mlx5_flow_meter_def_policy),
16346 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16348 DRV_LOG(ERR, "Failed to alloc default policy table.");
16349 goto def_policy_error;
16351 mtrmng->def_policy[domain] = def_policy;
16352 /* Create the meter suffix table with SUFFIX level. */
16353 jump_tbl = flow_dv_tbl_resource_get(dev,
16354 MLX5_FLOW_TABLE_LEVEL_METER,
16355 egress, transfer, false, NULL, 0,
16356 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16359 "Failed to create meter suffix table.");
16360 goto def_policy_error;
16362 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16363 tbl_data = container_of(jump_tbl,
16364 struct mlx5_flow_tbl_data_entry, tbl);
16365 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16366 tbl_data->jump.action;
16367 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16368 acts[RTE_COLOR_GREEN].actions_n = 1;
16370 * YELLOW has the same default policy as GREEN does.
16371 * G & Y share the same table and action. The 2nd time of table
16372 * resource getting is just to update the reference count for
16373 * the releasing stage.
16375 jump_tbl = flow_dv_tbl_resource_get(dev,
16376 MLX5_FLOW_TABLE_LEVEL_METER,
16377 egress, transfer, false, NULL, 0,
16378 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16381 "Failed to get meter suffix table.");
16382 goto def_policy_error;
16384 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16385 tbl_data = container_of(jump_tbl,
16386 struct mlx5_flow_tbl_data_entry, tbl);
16387 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16388 tbl_data->jump.action;
16389 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16390 acts[RTE_COLOR_YELLOW].actions_n = 1;
16391 /* Create jump action to the drop table. */
16392 if (!mtrmng->drop_tbl[domain]) {
16393 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16394 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16395 egress, transfer, false, NULL, 0,
16396 0, MLX5_MTR_TABLE_ID_DROP, &error);
16397 if (!mtrmng->drop_tbl[domain]) {
16398 DRV_LOG(ERR, "Failed to create meter "
16399 "drop table for default policy.");
16400 goto def_policy_error;
16403 /* all RED: unique Drop table for jump action. */
16404 tbl_data = container_of(mtrmng->drop_tbl[domain],
16405 struct mlx5_flow_tbl_data_entry, tbl);
16406 def_policy->dr_jump_action[RTE_COLOR_RED] =
16407 tbl_data->jump.action;
16408 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16409 acts[RTE_COLOR_RED].actions_n = 1;
16410 /* Create default policy rules. */
16411 ret = __flow_dv_create_domain_policy_rules(dev,
16412 &def_policy->sub_policy,
16413 egress, transfer, false, acts);
16415 DRV_LOG(ERR, "Failed to create default policy rules.");
16416 goto def_policy_error;
16421 __flow_dv_destroy_domain_def_policy(dev,
16422 (enum mlx5_meter_domain)domain);
16427 * Create the default policy table set.
16430 * Pointer to Ethernet device.
16432 * 0 on success, -1 otherwise.
16435 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16437 struct mlx5_priv *priv = dev->data->dev_private;
16440 /* Non-termination policy table. */
16441 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16442 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16444 if (__flow_dv_create_domain_def_policy(dev, i)) {
16445 DRV_LOG(ERR, "Failed to create default policy");
16446 /* Rollback the created default policies for others. */
16447 flow_dv_destroy_def_policy(dev);
16455 * Create the needed meter tables.
16456 * Lock free, (mutex should be acquired by caller).
16459 * Pointer to Ethernet device.
16461 * Meter information table.
16462 * @param[in] mtr_idx
16464 * @param[in] domain_bitmap
16467 * 0 on success, -1 otherwise.
16470 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16471 struct mlx5_flow_meter_info *fm,
16473 uint8_t domain_bitmap)
16475 struct mlx5_priv *priv = dev->data->dev_private;
16476 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16477 struct rte_flow_error error;
16478 struct mlx5_flow_tbl_data_entry *tbl_data;
16479 uint8_t egress, transfer;
16480 void *actions[METER_ACTIONS];
16481 int domain, ret, i;
16482 struct mlx5_flow_counter *cnt;
16483 struct mlx5_flow_dv_match_params value = {
16484 .size = sizeof(value.buf),
16486 struct mlx5_flow_dv_match_params matcher_para = {
16487 .size = sizeof(matcher_para.buf),
16489 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16491 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16492 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16493 struct mlx5_list_entry *entry;
16494 struct mlx5_flow_dv_matcher matcher = {
16496 .size = sizeof(matcher.mask.buf),
16499 struct mlx5_flow_dv_matcher *drop_matcher;
16500 struct mlx5_flow_cb_ctx ctx = {
16506 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16507 rte_errno = ENOTSUP;
16510 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16511 if (!(domain_bitmap & (1 << domain)) ||
16512 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16514 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16515 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16516 /* Create the drop table with METER DROP level. */
16517 if (!mtrmng->drop_tbl[domain]) {
16518 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16519 MLX5_FLOW_TABLE_LEVEL_METER,
16520 egress, transfer, false, NULL, 0,
16521 0, MLX5_MTR_TABLE_ID_DROP, &error);
16522 if (!mtrmng->drop_tbl[domain]) {
16523 DRV_LOG(ERR, "Failed to create meter drop table.");
16527 /* Create default matcher in drop table. */
16528 matcher.tbl = mtrmng->drop_tbl[domain],
16529 tbl_data = container_of(mtrmng->drop_tbl[domain],
16530 struct mlx5_flow_tbl_data_entry, tbl);
16531 if (!mtrmng->def_matcher[domain]) {
16532 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16533 (enum modify_reg)mtr_id_reg_c,
16535 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16536 matcher.crc = rte_raw_cksum
16537 ((const void *)matcher.mask.buf,
16538 matcher.mask.size);
16539 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16541 DRV_LOG(ERR, "Failed to register meter "
16542 "drop default matcher.");
16545 mtrmng->def_matcher[domain] = container_of(entry,
16546 struct mlx5_flow_dv_matcher, entry);
16548 /* Create default rule in drop table. */
16549 if (!mtrmng->def_rule[domain]) {
16551 actions[i++] = priv->sh->dr_drop_action;
16552 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16553 (enum modify_reg)mtr_id_reg_c, 0, 0);
16554 misc_mask = flow_dv_matcher_enable(value.buf);
16555 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16556 ret = mlx5_flow_os_create_flow
16557 (mtrmng->def_matcher[domain]->matcher_object,
16558 (void *)&value, i, actions,
16559 &mtrmng->def_rule[domain]);
16561 DRV_LOG(ERR, "Failed to create meter "
16562 "default drop rule for drop table.");
16568 MLX5_ASSERT(mtrmng->max_mtr_bits);
16569 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16570 /* Create matchers for Drop. */
16571 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16572 (enum modify_reg)mtr_id_reg_c, 0,
16573 (mtr_id_mask << mtr_id_offset));
16574 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16575 matcher.crc = rte_raw_cksum
16576 ((const void *)matcher.mask.buf,
16577 matcher.mask.size);
16578 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16581 "Failed to register meter drop matcher.");
16584 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16585 container_of(entry, struct mlx5_flow_dv_matcher,
16589 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16590 /* Create drop rule, matching meter_id only. */
16591 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16592 (enum modify_reg)mtr_id_reg_c,
16593 (mtr_idx << mtr_id_offset), UINT32_MAX);
16595 cnt = flow_dv_counter_get_by_idx(dev,
16596 fm->drop_cnt, NULL);
16597 actions[i++] = cnt->action;
16598 actions[i++] = priv->sh->dr_drop_action;
16599 misc_mask = flow_dv_matcher_enable(value.buf);
16600 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16601 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16602 (void *)&value, i, actions,
16603 &fm->drop_rule[domain]);
16605 DRV_LOG(ERR, "Failed to create meter "
16606 "drop rule for drop table.");
16612 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16613 if (fm->drop_rule[i]) {
16614 claim_zero(mlx5_flow_os_destroy_flow
16615 (fm->drop_rule[i]));
16616 fm->drop_rule[i] = NULL;
16622 static struct mlx5_flow_meter_sub_policy *
16623 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16624 struct mlx5_flow_meter_policy *mtr_policy,
16625 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16626 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16629 struct mlx5_priv *priv = dev->data->dev_private;
16630 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16631 uint32_t sub_policy_idx = 0;
16632 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16634 struct mlx5_hrxq *hrxq;
16635 struct mlx5_flow_handle dh;
16636 struct mlx5_meter_policy_action_container *act_cnt;
16637 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16638 uint16_t sub_policy_num;
16640 rte_spinlock_lock(&mtr_policy->sl);
16641 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16644 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16645 if (!hrxq_idx[i]) {
16646 rte_spinlock_unlock(&mtr_policy->sl);
16650 sub_policy_num = (mtr_policy->sub_policy_num >>
16651 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16652 MLX5_MTR_SUB_POLICY_NUM_MASK;
16653 for (j = 0; j < sub_policy_num; j++) {
16654 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16657 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16660 if (i >= MLX5_MTR_RTE_COLORS) {
16662 * Found the sub policy table with
16663 * the same queue per color.
16665 rte_spinlock_unlock(&mtr_policy->sl);
16666 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16667 mlx5_hrxq_release(dev, hrxq_idx[i]);
16669 return mtr_policy->sub_policys[domain][j];
16672 /* Create sub policy. */
16673 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16674 /* Reuse the first pre-allocated sub_policy. */
16675 sub_policy = mtr_policy->sub_policys[domain][0];
16676 sub_policy_idx = sub_policy->idx;
16678 sub_policy = mlx5_ipool_zmalloc
16679 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16682 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16683 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16684 mlx5_hrxq_release(dev, hrxq_idx[i]);
16685 goto rss_sub_policy_error;
16687 sub_policy->idx = sub_policy_idx;
16688 sub_policy->main_policy = mtr_policy;
16690 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16693 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16694 if (mtr_policy->is_hierarchy) {
16695 act_cnt = &mtr_policy->act_cnt[i];
16696 act_cnt->next_sub_policy = next_sub_policy;
16697 mlx5_hrxq_release(dev, hrxq_idx[i]);
16700 * Overwrite the last action from
16701 * RSS action to Queue action.
16703 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16706 DRV_LOG(ERR, "Failed to get policy hrxq");
16707 goto rss_sub_policy_error;
16709 act_cnt = &mtr_policy->act_cnt[i];
16710 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16711 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16712 if (act_cnt->rix_mark)
16714 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16715 dh.rix_hrxq = hrxq_idx[i];
16716 flow_drv_rxq_flags_set(dev, &dh);
16720 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16721 sub_policy, domain)) {
16722 DRV_LOG(ERR, "Failed to create policy "
16723 "rules for ingress domain.");
16724 goto rss_sub_policy_error;
16726 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16727 i = (mtr_policy->sub_policy_num >>
16728 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16729 MLX5_MTR_SUB_POLICY_NUM_MASK;
16730 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16731 DRV_LOG(ERR, "No free sub-policy slot.");
16732 goto rss_sub_policy_error;
16734 mtr_policy->sub_policys[domain][i] = sub_policy;
16736 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16737 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16738 mtr_policy->sub_policy_num |=
16739 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16740 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16742 rte_spinlock_unlock(&mtr_policy->sl);
16745 rss_sub_policy_error:
16747 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16748 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16749 i = (mtr_policy->sub_policy_num >>
16750 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16751 MLX5_MTR_SUB_POLICY_NUM_MASK;
16752 mtr_policy->sub_policys[domain][i] = NULL;
16753 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16757 rte_spinlock_unlock(&mtr_policy->sl);
16762 * Find the policy table for prefix table with RSS.
16765 * Pointer to Ethernet device.
16766 * @param[in] mtr_policy
16767 * Pointer to meter policy table.
16768 * @param[in] rss_desc
16769 * Pointer to rss_desc
16771 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16773 static struct mlx5_flow_meter_sub_policy *
16774 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16775 struct mlx5_flow_meter_policy *mtr_policy,
16776 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16778 struct mlx5_priv *priv = dev->data->dev_private;
16779 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16780 struct mlx5_flow_meter_info *next_fm;
16781 struct mlx5_flow_meter_policy *next_policy;
16782 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16783 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16784 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16785 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16786 bool reuse_sub_policy;
16791 /* Iterate hierarchy to get all policies in this hierarchy. */
16792 policies[i++] = mtr_policy;
16793 if (!mtr_policy->is_hierarchy)
16795 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16796 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16799 next_fm = mlx5_flow_meter_find(priv,
16800 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16802 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
16806 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
16808 MLX5_ASSERT(next_policy);
16809 mtr_policy = next_policy;
16813 * From last policy to the first one in hierarchy,
16814 * create / get the sub policy for each of them.
16816 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
16820 &reuse_sub_policy);
16822 DRV_LOG(ERR, "Failed to get the sub policy.");
16825 if (!reuse_sub_policy)
16826 sub_policies[j++] = sub_policy;
16827 next_sub_policy = sub_policy;
16832 uint16_t sub_policy_num;
16834 sub_policy = sub_policies[--j];
16835 mtr_policy = sub_policy->main_policy;
16836 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16837 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16838 sub_policy_num = (mtr_policy->sub_policy_num >>
16839 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16840 MLX5_MTR_SUB_POLICY_NUM_MASK;
16841 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
16844 mtr_policy->sub_policy_num &=
16845 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16846 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
16847 mtr_policy->sub_policy_num |=
16848 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16849 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
16850 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16858 * Create the sub policy tag rule for all meters in hierarchy.
16861 * Pointer to Ethernet device.
16863 * Meter information table.
16864 * @param[in] src_port
16865 * The src port this extra rule should use.
16867 * The src port match item.
16868 * @param[out] error
16869 * Perform verbose error reporting if not NULL.
16871 * 0 on success, a negative errno value otherwise and rte_errno is set.
16874 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
16875 struct mlx5_flow_meter_info *fm,
16877 const struct rte_flow_item *item,
16878 struct rte_flow_error *error)
16880 struct mlx5_priv *priv = dev->data->dev_private;
16881 struct mlx5_flow_meter_policy *mtr_policy;
16882 struct mlx5_flow_meter_sub_policy *sub_policy;
16883 struct mlx5_flow_meter_info *next_fm = NULL;
16884 struct mlx5_flow_meter_policy *next_policy;
16885 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16886 struct mlx5_flow_tbl_data_entry *tbl_data;
16887 struct mlx5_sub_policy_color_rule *color_rule;
16888 struct mlx5_meter_policy_acts acts;
16889 uint32_t color_reg_c_idx;
16890 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
16891 struct rte_flow_attr attr = {
16892 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16899 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
16902 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
16903 MLX5_ASSERT(mtr_policy);
16904 if (!mtr_policy->is_hierarchy)
16906 next_fm = mlx5_flow_meter_find(priv,
16907 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16909 return rte_flow_error_set(error, EINVAL,
16910 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
16911 "Failed to find next meter in hierarchy.");
16913 if (!next_fm->drop_cnt)
16915 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
16916 sub_policy = mtr_policy->sub_policys[domain][0];
16917 for (i = 0; i < RTE_COLORS; i++) {
16918 bool rule_exist = false;
16919 struct mlx5_meter_policy_action_container *act_cnt;
16921 if (i >= RTE_COLOR_YELLOW)
16923 TAILQ_FOREACH(color_rule,
16924 &sub_policy->color_rules[i], next_port)
16925 if (color_rule->src_port == src_port) {
16931 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16932 sizeof(struct mlx5_sub_policy_color_rule),
16935 return rte_flow_error_set(error, ENOMEM,
16936 RTE_FLOW_ERROR_TYPE_ACTION,
16937 NULL, "No memory to create tag color rule.");
16938 color_rule->src_port = src_port;
16940 next_policy = mlx5_flow_meter_policy_find(dev,
16941 next_fm->policy_id, NULL);
16942 MLX5_ASSERT(next_policy);
16943 next_sub_policy = next_policy->sub_policys[domain][0];
16944 tbl_data = container_of(next_sub_policy->tbl_rsc,
16945 struct mlx5_flow_tbl_data_entry, tbl);
16946 act_cnt = &mtr_policy->act_cnt[i];
16948 acts.dv_actions[0] = next_fm->meter_action;
16949 acts.dv_actions[1] = act_cnt->modify_hdr->action;
16951 acts.dv_actions[0] = act_cnt->modify_hdr->action;
16952 acts.dv_actions[1] = next_fm->meter_action;
16954 acts.dv_actions[2] = tbl_data->jump.action;
16955 acts.actions_n = 3;
16956 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
16960 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16961 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16963 &color_rule->matcher, error)) {
16964 rte_flow_error_set(error, errno,
16965 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16966 "Failed to create hierarchy meter matcher.");
16969 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
16971 color_rule->matcher->matcher_object,
16972 acts.actions_n, acts.dv_actions,
16974 &color_rule->rule, &attr)) {
16975 rte_flow_error_set(error, errno,
16976 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16977 "Failed to create hierarchy meter rule.");
16980 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16981 color_rule, next_port);
16985 * Recursive call to iterate all meters in hierarchy and
16986 * create needed rules.
16988 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
16989 src_port, item, error);
16992 if (color_rule->rule)
16993 mlx5_flow_os_destroy_flow(color_rule->rule);
16994 if (color_rule->matcher) {
16995 struct mlx5_flow_tbl_data_entry *tbl =
16996 container_of(color_rule->matcher->tbl,
16997 typeof(*tbl), tbl);
16998 mlx5_list_unregister(tbl->matchers,
16999 &color_rule->matcher->entry);
17001 mlx5_free(color_rule);
17004 mlx5_flow_meter_detach(priv, next_fm);
17009 * Destroy the sub policy table with RX queue.
17012 * Pointer to Ethernet device.
17013 * @param[in] mtr_policy
17014 * Pointer to meter policy table.
17017 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17018 struct mlx5_flow_meter_policy *mtr_policy)
17020 struct mlx5_priv *priv = dev->data->dev_private;
17021 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17022 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17024 uint16_t sub_policy_num, new_policy_num;
17026 rte_spinlock_lock(&mtr_policy->sl);
17027 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17028 switch (mtr_policy->act_cnt[i].fate_action) {
17029 case MLX5_FLOW_FATE_SHARED_RSS:
17030 sub_policy_num = (mtr_policy->sub_policy_num >>
17031 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17032 MLX5_MTR_SUB_POLICY_NUM_MASK;
17033 new_policy_num = sub_policy_num;
17034 for (j = 0; j < sub_policy_num; j++) {
17036 mtr_policy->sub_policys[domain][j];
17038 __flow_dv_destroy_sub_policy_rules(dev,
17041 mtr_policy->sub_policys[domain][0]) {
17042 mtr_policy->sub_policys[domain][j] =
17045 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17051 if (new_policy_num != sub_policy_num) {
17052 mtr_policy->sub_policy_num &=
17053 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17054 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17055 mtr_policy->sub_policy_num |=
17057 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17058 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17061 case MLX5_FLOW_FATE_QUEUE:
17062 sub_policy = mtr_policy->sub_policys[domain][0];
17063 __flow_dv_destroy_sub_policy_rules(dev,
17067 /*Other actions without queue and do nothing*/
17071 rte_spinlock_unlock(&mtr_policy->sl);
17075 * Validate the batch counter support in root table.
17077 * Create a simple flow with invalid counter and drop action on root table to
17078 * validate if batch counter with offset on root table is supported or not.
17081 * Pointer to rte_eth_dev structure.
17084 * 0 on success, a negative errno value otherwise and rte_errno is set.
17087 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17089 struct mlx5_priv *priv = dev->data->dev_private;
17090 struct mlx5_dev_ctx_shared *sh = priv->sh;
17091 struct mlx5_flow_dv_match_params mask = {
17092 .size = sizeof(mask.buf),
17094 struct mlx5_flow_dv_match_params value = {
17095 .size = sizeof(value.buf),
17097 struct mlx5dv_flow_matcher_attr dv_attr = {
17098 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17100 .match_criteria_enable = 0,
17101 .match_mask = (void *)&mask,
17103 void *actions[2] = { 0 };
17104 struct mlx5_flow_tbl_resource *tbl = NULL;
17105 struct mlx5_devx_obj *dcs = NULL;
17106 void *matcher = NULL;
17110 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17114 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
17117 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17121 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17122 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17123 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
17127 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17128 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17132 * If batch counter with offset is not supported, the driver will not
17133 * validate the invalid offset value, flow create should success.
17134 * In this case, it means batch counter is not supported in root table.
17136 * Otherwise, if flow create is failed, counter offset is supported.
17139 DRV_LOG(INFO, "Batch counter is not supported in root "
17140 "table. Switch to fallback mode.");
17141 rte_errno = ENOTSUP;
17143 claim_zero(mlx5_flow_os_destroy_flow(flow));
17145 /* Check matcher to make sure validate fail at flow create. */
17146 if (!matcher || (matcher && errno != EINVAL))
17147 DRV_LOG(ERR, "Unexpected error in counter offset "
17148 "support detection");
17152 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17154 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17156 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17158 claim_zero(mlx5_devx_cmd_destroy(dcs));
17163 * Query a devx counter.
17166 * Pointer to the Ethernet device structure.
17168 * Index to the flow counter.
17170 * Set to clear the counter statistics.
17172 * The statistics value of packets.
17173 * @param[out] bytes
17174 * The statistics value of bytes.
17177 * 0 on success, otherwise return -1.
17180 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17181 uint64_t *pkts, uint64_t *bytes)
17183 struct mlx5_priv *priv = dev->data->dev_private;
17184 struct mlx5_flow_counter *cnt;
17185 uint64_t inn_pkts, inn_bytes;
17188 if (!priv->config.devx)
17191 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17194 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17195 *pkts = inn_pkts - cnt->hits;
17196 *bytes = inn_bytes - cnt->bytes;
17198 cnt->hits = inn_pkts;
17199 cnt->bytes = inn_bytes;
17205 * Get aged-out flows.
17208 * Pointer to the Ethernet device structure.
17209 * @param[in] context
17210 * The address of an array of pointers to the aged-out flows contexts.
17211 * @param[in] nb_contexts
17212 * The length of context array pointers.
17213 * @param[out] error
17214 * Perform verbose error reporting if not NULL. Initialized in case of
17218 * how many contexts get in success, otherwise negative errno value.
17219 * if nb_contexts is 0, return the amount of all aged contexts.
17220 * if nb_contexts is not 0 , return the amount of aged flows reported
17221 * in the context array.
17222 * @note: only stub for now
17225 flow_get_aged_flows(struct rte_eth_dev *dev,
17227 uint32_t nb_contexts,
17228 struct rte_flow_error *error)
17230 struct mlx5_priv *priv = dev->data->dev_private;
17231 struct mlx5_age_info *age_info;
17232 struct mlx5_age_param *age_param;
17233 struct mlx5_flow_counter *counter;
17234 struct mlx5_aso_age_action *act;
17237 if (nb_contexts && !context)
17238 return rte_flow_error_set(error, EINVAL,
17239 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17240 NULL, "empty context");
17241 age_info = GET_PORT_AGE_INFO(priv);
17242 rte_spinlock_lock(&age_info->aged_sl);
17243 LIST_FOREACH(act, &age_info->aged_aso, next) {
17246 context[nb_flows - 1] =
17247 act->age_params.context;
17248 if (!(--nb_contexts))
17252 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17255 age_param = MLX5_CNT_TO_AGE(counter);
17256 context[nb_flows - 1] = age_param->context;
17257 if (!(--nb_contexts))
17261 rte_spinlock_unlock(&age_info->aged_sl);
17262 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17267 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17270 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17272 return flow_dv_counter_alloc(dev, 0);
17276 * Validate indirect action.
17277 * Dispatcher for action type specific validation.
17280 * Pointer to the Ethernet device structure.
17282 * Indirect action configuration.
17283 * @param[in] action
17284 * The indirect action object to validate.
17285 * @param[out] error
17286 * Perform verbose error reporting if not NULL. Initialized in case of
17290 * 0 on success, otherwise negative errno value.
17293 flow_dv_action_validate(struct rte_eth_dev *dev,
17294 const struct rte_flow_indir_action_conf *conf,
17295 const struct rte_flow_action *action,
17296 struct rte_flow_error *err)
17298 struct mlx5_priv *priv = dev->data->dev_private;
17300 RTE_SET_USED(conf);
17301 switch (action->type) {
17302 case RTE_FLOW_ACTION_TYPE_RSS:
17304 * priv->obj_ops is set according to driver capabilities.
17305 * When DevX capabilities are
17306 * sufficient, it is set to devx_obj_ops.
17307 * Otherwise, it is set to ibv_obj_ops.
17308 * ibv_obj_ops doesn't support ind_table_modify operation.
17309 * In this case the indirect RSS action can't be used.
17311 if (priv->obj_ops.ind_table_modify == NULL)
17312 return rte_flow_error_set
17314 RTE_FLOW_ERROR_TYPE_ACTION,
17316 "Indirect RSS action not supported");
17317 return mlx5_validate_action_rss(dev, action, err);
17318 case RTE_FLOW_ACTION_TYPE_AGE:
17319 if (!priv->sh->aso_age_mng)
17320 return rte_flow_error_set(err, ENOTSUP,
17321 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17323 "Indirect age action not supported");
17324 return flow_dv_validate_action_age(0, action, dev, err);
17325 case RTE_FLOW_ACTION_TYPE_COUNT:
17327 * There are two mechanisms to share the action count.
17328 * The old mechanism uses the shared field to share, while the
17329 * new mechanism uses the indirect action API.
17330 * This validation comes to make sure that the two mechanisms
17331 * are not combined.
17333 if (is_shared_action_count(action))
17334 return rte_flow_error_set(err, ENOTSUP,
17335 RTE_FLOW_ERROR_TYPE_ACTION,
17337 "Mix shared and indirect counter is not supported");
17338 return flow_dv_validate_action_count(dev, true, 0, err);
17339 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17340 if (!priv->sh->ct_aso_en)
17341 return rte_flow_error_set(err, ENOTSUP,
17342 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17343 "ASO CT is not supported");
17344 return mlx5_validate_action_ct(dev, action->conf, err);
17346 return rte_flow_error_set(err, ENOTSUP,
17347 RTE_FLOW_ERROR_TYPE_ACTION,
17349 "action type not supported");
17354 * Check if the RSS configurations for colors of a meter policy match
17355 * each other, except the queues.
17358 * Pointer to the first RSS flow action.
17360 * Pointer to the second RSS flow action.
17363 * 0 on match, 1 on conflict.
17366 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17367 const struct rte_flow_action_rss *r2)
17371 if (r1->func != r2->func || r1->level != r2->level ||
17372 r1->types != r2->types || r1->key_len != r2->key_len ||
17373 memcmp(r1->key, r2->key, r1->key_len))
17379 * Validate the meter hierarchy chain for meter policy.
17382 * Pointer to the Ethernet device structure.
17383 * @param[in] meter_id
17385 * @param[in] action_flags
17386 * Holds the actions detected until now.
17387 * @param[out] is_rss
17389 * @param[out] hierarchy_domain
17390 * The domain bitmap for hierarchy policy.
17391 * @param[out] error
17392 * Perform verbose error reporting if not NULL. Initialized in case of
17396 * 0 on success, otherwise negative errno value with error set.
17399 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17401 uint64_t action_flags,
17403 uint8_t *hierarchy_domain,
17404 struct rte_mtr_error *error)
17406 struct mlx5_priv *priv = dev->data->dev_private;
17407 struct mlx5_flow_meter_info *fm;
17408 struct mlx5_flow_meter_policy *policy;
17411 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17412 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17413 return -rte_mtr_error_set(error, EINVAL,
17414 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17416 "Multiple fate actions not supported.");
17418 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17420 return -rte_mtr_error_set(error, EINVAL,
17421 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17422 "Meter not found in meter hierarchy.");
17423 if (fm->def_policy)
17424 return -rte_mtr_error_set(error, EINVAL,
17425 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17426 "Non termination meter not supported in hierarchy.");
17427 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17428 MLX5_ASSERT(policy);
17429 if (!policy->is_hierarchy) {
17430 if (policy->transfer)
17431 *hierarchy_domain |=
17432 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17433 if (policy->ingress)
17434 *hierarchy_domain |=
17435 MLX5_MTR_DOMAIN_INGRESS_BIT;
17436 if (policy->egress)
17437 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17438 *is_rss = policy->is_rss;
17441 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17442 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17443 return -rte_mtr_error_set(error, EINVAL,
17444 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17445 "Exceed max hierarchy meter number.");
17451 * Validate meter policy actions.
17452 * Dispatcher for action type specific validation.
17455 * Pointer to the Ethernet device structure.
17456 * @param[in] action
17457 * The meter policy action object to validate.
17459 * Attributes of flow to determine steering domain.
17460 * @param[out] error
17461 * Perform verbose error reporting if not NULL. Initialized in case of
17465 * 0 on success, otherwise negative errno value.
17468 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17469 const struct rte_flow_action *actions[RTE_COLORS],
17470 struct rte_flow_attr *attr,
17472 uint8_t *domain_bitmap,
17473 uint8_t *policy_mode,
17474 struct rte_mtr_error *error)
17476 struct mlx5_priv *priv = dev->data->dev_private;
17477 struct mlx5_dev_config *dev_conf = &priv->config;
17478 const struct rte_flow_action *act;
17479 uint64_t action_flags[RTE_COLORS] = {0};
17482 struct rte_flow_error flow_err;
17483 uint8_t domain_color[RTE_COLORS] = {0};
17484 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17485 uint8_t hierarchy_domain = 0;
17486 const struct rte_flow_action_meter *mtr;
17487 bool def_green = false;
17488 bool def_yellow = false;
17489 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17491 if (!priv->config.dv_esw_en)
17492 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17493 *domain_bitmap = def_domain;
17494 /* Red color could only support DROP action. */
17495 if (!actions[RTE_COLOR_RED] ||
17496 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17497 return -rte_mtr_error_set(error, ENOTSUP,
17498 RTE_MTR_ERROR_TYPE_METER_POLICY,
17499 NULL, "Red color only supports drop action.");
17501 * Check default policy actions:
17502 * Green / Yellow: no action, Red: drop action
17503 * Either G or Y will trigger default policy actions to be created.
17505 if (!actions[RTE_COLOR_GREEN] ||
17506 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17508 if (!actions[RTE_COLOR_YELLOW] ||
17509 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17511 if (def_green && def_yellow) {
17512 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17514 } else if (!def_green && def_yellow) {
17515 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17516 } else if (def_green && !def_yellow) {
17517 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17519 /* Set to empty string in case of NULL pointer access by user. */
17520 flow_err.message = "";
17521 for (i = 0; i < RTE_COLORS; i++) {
17523 for (action_flags[i] = 0, actions_n = 0;
17524 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17526 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17527 return -rte_mtr_error_set(error, ENOTSUP,
17528 RTE_MTR_ERROR_TYPE_METER_POLICY,
17529 NULL, "too many actions");
17530 switch (act->type) {
17531 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17532 if (!priv->config.dv_esw_en)
17533 return -rte_mtr_error_set(error,
17535 RTE_MTR_ERROR_TYPE_METER_POLICY,
17536 NULL, "PORT action validate check"
17537 " fail for ESW disable");
17538 ret = flow_dv_validate_action_port_id(dev,
17540 act, attr, &flow_err);
17542 return -rte_mtr_error_set(error,
17544 RTE_MTR_ERROR_TYPE_METER_POLICY,
17545 NULL, flow_err.message ?
17547 "PORT action validate check fail");
17549 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17551 case RTE_FLOW_ACTION_TYPE_MARK:
17552 ret = flow_dv_validate_action_mark(dev, act,
17556 return -rte_mtr_error_set(error,
17558 RTE_MTR_ERROR_TYPE_METER_POLICY,
17559 NULL, flow_err.message ?
17561 "Mark action validate check fail");
17562 if (dev_conf->dv_xmeta_en !=
17563 MLX5_XMETA_MODE_LEGACY)
17564 return -rte_mtr_error_set(error,
17566 RTE_MTR_ERROR_TYPE_METER_POLICY,
17567 NULL, "Extend MARK action is "
17568 "not supported. Please try use "
17569 "default policy for meter.");
17570 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17573 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17574 ret = flow_dv_validate_action_set_tag(dev,
17575 act, action_flags[i],
17578 return -rte_mtr_error_set(error,
17580 RTE_MTR_ERROR_TYPE_METER_POLICY,
17581 NULL, flow_err.message ?
17583 "Set tag action validate check fail");
17584 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17587 case RTE_FLOW_ACTION_TYPE_DROP:
17588 ret = mlx5_flow_validate_action_drop
17589 (action_flags[i], attr, &flow_err);
17591 return -rte_mtr_error_set(error,
17593 RTE_MTR_ERROR_TYPE_METER_POLICY,
17594 NULL, flow_err.message ?
17596 "Drop action validate check fail");
17597 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17600 case RTE_FLOW_ACTION_TYPE_QUEUE:
17602 * Check whether extensive
17603 * metadata feature is engaged.
17605 if (dev_conf->dv_flow_en &&
17606 (dev_conf->dv_xmeta_en !=
17607 MLX5_XMETA_MODE_LEGACY) &&
17608 mlx5_flow_ext_mreg_supported(dev))
17609 return -rte_mtr_error_set(error,
17611 RTE_MTR_ERROR_TYPE_METER_POLICY,
17612 NULL, "Queue action with meta "
17613 "is not supported. Please try use "
17614 "default policy for meter.");
17615 ret = mlx5_flow_validate_action_queue(act,
17616 action_flags[i], dev,
17619 return -rte_mtr_error_set(error,
17621 RTE_MTR_ERROR_TYPE_METER_POLICY,
17622 NULL, flow_err.message ?
17624 "Queue action validate check fail");
17625 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17628 case RTE_FLOW_ACTION_TYPE_RSS:
17629 if (dev_conf->dv_flow_en &&
17630 (dev_conf->dv_xmeta_en !=
17631 MLX5_XMETA_MODE_LEGACY) &&
17632 mlx5_flow_ext_mreg_supported(dev))
17633 return -rte_mtr_error_set(error,
17635 RTE_MTR_ERROR_TYPE_METER_POLICY,
17636 NULL, "RSS action with meta "
17637 "is not supported. Please try use "
17638 "default policy for meter.");
17639 ret = mlx5_validate_action_rss(dev, act,
17642 return -rte_mtr_error_set(error,
17644 RTE_MTR_ERROR_TYPE_METER_POLICY,
17645 NULL, flow_err.message ?
17647 "RSS action validate check fail");
17648 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17650 /* Either G or Y will set the RSS. */
17651 rss_color[i] = act->conf;
17653 case RTE_FLOW_ACTION_TYPE_JUMP:
17654 ret = flow_dv_validate_action_jump(dev,
17655 NULL, act, action_flags[i],
17656 attr, true, &flow_err);
17658 return -rte_mtr_error_set(error,
17660 RTE_MTR_ERROR_TYPE_METER_POLICY,
17661 NULL, flow_err.message ?
17663 "Jump action validate check fail");
17665 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17668 * Only the last meter in the hierarchy will support
17669 * the YELLOW color steering. Then in the meter policy
17670 * actions list, there should be no other meter inside.
17672 case RTE_FLOW_ACTION_TYPE_METER:
17673 if (i != RTE_COLOR_GREEN)
17674 return -rte_mtr_error_set(error,
17676 RTE_MTR_ERROR_TYPE_METER_POLICY,
17677 NULL, flow_err.message ?
17679 "Meter hierarchy only supports GREEN color.");
17681 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17691 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17694 return -rte_mtr_error_set(error, ENOTSUP,
17695 RTE_MTR_ERROR_TYPE_METER_POLICY,
17697 "Doesn't support optional action");
17700 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID)
17701 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17702 else if ((action_flags[i] &
17703 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17704 (action_flags[i] & MLX5_FLOW_ACTION_MARK))
17706 * Only support MLX5_XMETA_MODE_LEGACY
17707 * so MARK action is only in ingress domain.
17709 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17710 else if (action_flags[i] &
17711 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
17712 domain_color[i] = hierarchy_domain;
17714 domain_color[i] = def_domain;
17716 * Non-termination actions only support NIC Tx domain.
17717 * The adjustion should be skipped when there is no
17718 * action or only END is provided. The default domains
17719 * bit-mask is set to find the MIN intersection.
17720 * The action flags checking should also be skipped.
17722 if ((def_green && i == RTE_COLOR_GREEN) ||
17723 (def_yellow && i == RTE_COLOR_YELLOW))
17726 * Validate the drop action mutual exclusion
17727 * with other actions. Drop action is mutually-exclusive
17728 * with any other action, except for Count action.
17730 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
17731 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
17732 return -rte_mtr_error_set(error, ENOTSUP,
17733 RTE_MTR_ERROR_TYPE_METER_POLICY,
17734 NULL, "Drop action is mutually-exclusive "
17735 "with any other action");
17737 /* Eswitch has few restrictions on using items and actions */
17738 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
17739 if (!mlx5_flow_ext_mreg_supported(dev) &&
17740 action_flags[i] & MLX5_FLOW_ACTION_MARK)
17741 return -rte_mtr_error_set(error, ENOTSUP,
17742 RTE_MTR_ERROR_TYPE_METER_POLICY,
17743 NULL, "unsupported action MARK");
17744 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
17745 return -rte_mtr_error_set(error, ENOTSUP,
17746 RTE_MTR_ERROR_TYPE_METER_POLICY,
17747 NULL, "unsupported action QUEUE");
17748 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
17749 return -rte_mtr_error_set(error, ENOTSUP,
17750 RTE_MTR_ERROR_TYPE_METER_POLICY,
17751 NULL, "unsupported action RSS");
17752 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17753 return -rte_mtr_error_set(error, ENOTSUP,
17754 RTE_MTR_ERROR_TYPE_METER_POLICY,
17755 NULL, "no fate action is found");
17757 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
17758 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
17759 if ((domain_color[i] &
17760 MLX5_MTR_DOMAIN_EGRESS_BIT))
17762 MLX5_MTR_DOMAIN_EGRESS_BIT;
17764 return -rte_mtr_error_set(error,
17766 RTE_MTR_ERROR_TYPE_METER_POLICY,
17768 "no fate action is found");
17772 /* If both colors have RSS, the attributes should be the same. */
17773 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
17774 rss_color[RTE_COLOR_YELLOW]))
17775 return -rte_mtr_error_set(error, EINVAL,
17776 RTE_MTR_ERROR_TYPE_METER_POLICY,
17777 NULL, "policy RSS attr conflict");
17778 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
17780 /* "domain_color[C]" is non-zero for each color, default is ALL. */
17781 if (!def_green && !def_yellow &&
17782 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
17783 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
17784 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
17785 return -rte_mtr_error_set(error, EINVAL,
17786 RTE_MTR_ERROR_TYPE_METER_POLICY,
17787 NULL, "policy domains conflict");
17789 * At least one color policy is listed in the actions, the domains
17790 * to be supported should be the intersection.
17792 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
17793 domain_color[RTE_COLOR_YELLOW];
17798 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
17800 struct mlx5_priv *priv = dev->data->dev_private;
17803 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
17804 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
17809 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
17810 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
17814 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
17815 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
17822 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
17823 .validate = flow_dv_validate,
17824 .prepare = flow_dv_prepare,
17825 .translate = flow_dv_translate,
17826 .apply = flow_dv_apply,
17827 .remove = flow_dv_remove,
17828 .destroy = flow_dv_destroy,
17829 .query = flow_dv_query,
17830 .create_mtr_tbls = flow_dv_create_mtr_tbls,
17831 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
17832 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
17833 .create_meter = flow_dv_mtr_alloc,
17834 .free_meter = flow_dv_aso_mtr_release_to_pool,
17835 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
17836 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
17837 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
17838 .create_policy_rules = flow_dv_create_policy_rules,
17839 .destroy_policy_rules = flow_dv_destroy_policy_rules,
17840 .create_def_policy = flow_dv_create_def_policy,
17841 .destroy_def_policy = flow_dv_destroy_def_policy,
17842 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
17843 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
17844 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
17845 .counter_alloc = flow_dv_counter_allocate,
17846 .counter_free = flow_dv_counter_free,
17847 .counter_query = flow_dv_counter_query,
17848 .get_aged_flows = flow_get_aged_flows,
17849 .action_validate = flow_dv_action_validate,
17850 .action_create = flow_dv_action_create,
17851 .action_destroy = flow_dv_action_destroy,
17852 .action_update = flow_dv_action_update,
17853 .action_query = flow_dv_action_query,
17854 .sync_domain = flow_dv_sync_domain,
17857 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */