1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
92 * Initialize flow attributes structure according to flow items' types.
94 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
95 * mode. For tunnel mode, the items to be modified are the outermost ones.
98 * Pointer to item specification.
100 * Pointer to flow attributes structure.
101 * @param[in] dev_flow
102 * Pointer to the sub flow.
103 * @param[in] tunnel_decap
104 * Whether action is after tunnel decapsulation.
107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
108 struct mlx5_flow *dev_flow, bool tunnel_decap)
110 uint64_t layers = dev_flow->handle->layers;
113 * If layers is already initialized, it means this dev_flow is the
114 * suffix flow, the layers flags is set by the prefix flow. Need to
115 * use the layer flags from prefix flow as the suffix flow may not
116 * have the user defined items as the flow is split.
119 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
123 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
130 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
131 uint8_t next_protocol = 0xff;
132 switch (item->type) {
133 case RTE_FLOW_ITEM_TYPE_GRE:
134 case RTE_FLOW_ITEM_TYPE_NVGRE:
135 case RTE_FLOW_ITEM_TYPE_VXLAN:
136 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
137 case RTE_FLOW_ITEM_TYPE_GENEVE:
138 case RTE_FLOW_ITEM_TYPE_MPLS:
142 case RTE_FLOW_ITEM_TYPE_IPV4:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv4 *)
147 item->mask)->hdr.next_proto_id)
149 ((const struct rte_flow_item_ipv4 *)
150 (item->spec))->hdr.next_proto_id &
151 ((const struct rte_flow_item_ipv4 *)
152 (item->mask))->hdr.next_proto_id;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_IPV6:
160 if (item->mask != NULL &&
161 ((const struct rte_flow_item_ipv6 *)
162 item->mask)->hdr.proto)
164 ((const struct rte_flow_item_ipv6 *)
165 (item->spec))->hdr.proto &
166 ((const struct rte_flow_item_ipv6 *)
167 (item->mask))->hdr.proto;
168 if ((next_protocol == IPPROTO_IPIP ||
169 next_protocol == IPPROTO_IPV6) && tunnel_decap)
172 case RTE_FLOW_ITEM_TYPE_UDP:
176 case RTE_FLOW_ITEM_TYPE_TCP:
188 * Convert rte_mtr_color to mlx5 color.
197 rte_col_2_mlx5_col(enum rte_color rcol)
200 case RTE_COLOR_GREEN:
201 return MLX5_FLOW_COLOR_GREEN;
202 case RTE_COLOR_YELLOW:
203 return MLX5_FLOW_COLOR_YELLOW;
205 return MLX5_FLOW_COLOR_RED;
209 return MLX5_FLOW_COLOR_UNDEFINED;
212 struct field_modify_info {
213 uint32_t size; /* Size of field in protocol header, in bytes. */
214 uint32_t offset; /* Offset of field in protocol header, in bytes. */
215 enum mlx5_modification_field id;
218 struct field_modify_info modify_eth[] = {
219 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
220 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
221 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
222 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
226 struct field_modify_info modify_vlan_out_first_vid[] = {
227 /* Size in bits !!! */
228 {12, 0, MLX5_MODI_OUT_FIRST_VID},
232 struct field_modify_info modify_ipv4[] = {
233 {1, 1, MLX5_MODI_OUT_IP_DSCP},
234 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
235 {4, 12, MLX5_MODI_OUT_SIPV4},
236 {4, 16, MLX5_MODI_OUT_DIPV4},
240 struct field_modify_info modify_ipv6[] = {
241 {1, 0, MLX5_MODI_OUT_IP_DSCP},
242 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
243 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
244 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
245 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
246 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
247 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
248 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
249 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
250 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
254 struct field_modify_info modify_udp[] = {
255 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
256 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
260 struct field_modify_info modify_tcp[] = {
261 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
262 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
263 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
264 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
270 uint8_t next_protocol, uint64_t *item_flags,
273 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
274 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
275 if (next_protocol == IPPROTO_IPIP) {
276 *item_flags |= MLX5_FLOW_LAYER_IPIP;
279 if (next_protocol == IPPROTO_IPV6) {
280 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
285 /* Update VLAN's VID/PCP based on input rte_flow_action.
288 * Pointer to struct rte_flow_action.
290 * Pointer to struct rte_vlan_hdr.
293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
294 struct rte_vlan_hdr *vlan)
297 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
299 ((const struct rte_flow_action_of_set_vlan_pcp *)
300 action->conf)->vlan_pcp;
301 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
302 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
303 vlan->vlan_tci |= vlan_tci;
304 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
305 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
306 vlan->vlan_tci |= rte_be_to_cpu_16
307 (((const struct rte_flow_action_of_set_vlan_vid *)
308 action->conf)->vlan_vid);
313 * Fetch 1, 2, 3 or 4 byte field from the byte array
314 * and return as unsigned integer in host-endian format.
317 * Pointer to data array.
319 * Size of field to extract.
322 * converted field in host endian format.
324 static inline uint32_t
325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
334 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
337 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = (ret << 8) | *(data + sizeof(uint16_t));
341 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
352 * Convert modify-header action to DV specification.
354 * Data length of each action is determined by provided field description
355 * and the item mask. Data bit offset and width of each action is determined
356 * by provided item mask.
359 * Pointer to item specification.
361 * Pointer to field modification information.
362 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
363 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
366 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
367 * Negative offset value sets the same offset as source offset.
368 * size field is ignored, value is taken from source field.
369 * @param[in,out] resource
370 * Pointer to the modify-header resource.
372 * Type of modification.
374 * Pointer to the error structure.
377 * 0 on success, a negative errno value otherwise and rte_errno is set.
380 flow_dv_convert_modify_action(struct rte_flow_item *item,
381 struct field_modify_info *field,
382 struct field_modify_info *dcopy,
383 struct mlx5_flow_dv_modify_hdr_resource *resource,
384 uint32_t type, struct rte_flow_error *error)
386 uint32_t i = resource->actions_num;
387 struct mlx5_modification_cmd *actions = resource->actions;
390 * The item and mask are provided in big-endian format.
391 * The fields should be presented as in big-endian format either.
392 * Mask must be always present, it defines the actual field width.
394 MLX5_ASSERT(item->mask);
395 MLX5_ASSERT(field->size);
402 if (i >= MLX5_MAX_MODIFY_NUM)
403 return rte_flow_error_set(error, EINVAL,
404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
405 "too many items to modify");
406 /* Fetch variable byte size mask from the array. */
407 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
408 field->offset, field->size);
413 /* Deduce actual data width in bits from mask value. */
414 off_b = rte_bsf32(mask);
415 size_b = sizeof(uint32_t) * CHAR_BIT -
416 off_b - __builtin_clz(mask);
418 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
419 actions[i] = (struct mlx5_modification_cmd) {
425 /* Convert entire record to expected big-endian format. */
426 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
427 if (type == MLX5_MODIFICATION_TYPE_COPY) {
429 actions[i].dst_field = dcopy->id;
430 actions[i].dst_offset =
431 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
432 /* Convert entire record to big-endian format. */
433 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
436 MLX5_ASSERT(item->spec);
437 data = flow_dv_fetch_field((const uint8_t *)item->spec +
438 field->offset, field->size);
439 /* Shift out the trailing masked bits from data. */
440 data = (data & mask) >> off_b;
441 actions[i].data1 = rte_cpu_to_be_32(data);
445 } while (field->size);
446 if (resource->actions_num == i)
447 return rte_flow_error_set(error, EINVAL,
448 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
449 "invalid modification flow item");
450 resource->actions_num = i;
455 * Convert modify-header set IPv4 address action to DV specification.
457 * @param[in,out] resource
458 * Pointer to the modify-header resource.
460 * Pointer to action specification.
462 * Pointer to the error structure.
465 * 0 on success, a negative errno value otherwise and rte_errno is set.
468 flow_dv_convert_action_modify_ipv4
469 (struct mlx5_flow_dv_modify_hdr_resource *resource,
470 const struct rte_flow_action *action,
471 struct rte_flow_error *error)
473 const struct rte_flow_action_set_ipv4 *conf =
474 (const struct rte_flow_action_set_ipv4 *)(action->conf);
475 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
476 struct rte_flow_item_ipv4 ipv4;
477 struct rte_flow_item_ipv4 ipv4_mask;
479 memset(&ipv4, 0, sizeof(ipv4));
480 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
481 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
482 ipv4.hdr.src_addr = conf->ipv4_addr;
483 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
485 ipv4.hdr.dst_addr = conf->ipv4_addr;
486 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
489 item.mask = &ipv4_mask;
490 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
491 MLX5_MODIFICATION_TYPE_SET, error);
495 * Convert modify-header set IPv6 address action to DV specification.
497 * @param[in,out] resource
498 * Pointer to the modify-header resource.
500 * Pointer to action specification.
502 * Pointer to the error structure.
505 * 0 on success, a negative errno value otherwise and rte_errno is set.
508 flow_dv_convert_action_modify_ipv6
509 (struct mlx5_flow_dv_modify_hdr_resource *resource,
510 const struct rte_flow_action *action,
511 struct rte_flow_error *error)
513 const struct rte_flow_action_set_ipv6 *conf =
514 (const struct rte_flow_action_set_ipv6 *)(action->conf);
515 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
516 struct rte_flow_item_ipv6 ipv6;
517 struct rte_flow_item_ipv6 ipv6_mask;
519 memset(&ipv6, 0, sizeof(ipv6));
520 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
521 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
522 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
523 sizeof(ipv6.hdr.src_addr));
524 memcpy(&ipv6_mask.hdr.src_addr,
525 &rte_flow_item_ipv6_mask.hdr.src_addr,
526 sizeof(ipv6.hdr.src_addr));
528 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
529 sizeof(ipv6.hdr.dst_addr));
530 memcpy(&ipv6_mask.hdr.dst_addr,
531 &rte_flow_item_ipv6_mask.hdr.dst_addr,
532 sizeof(ipv6.hdr.dst_addr));
535 item.mask = &ipv6_mask;
536 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
537 MLX5_MODIFICATION_TYPE_SET, error);
541 * Convert modify-header set MAC address action to DV specification.
543 * @param[in,out] resource
544 * Pointer to the modify-header resource.
546 * Pointer to action specification.
548 * Pointer to the error structure.
551 * 0 on success, a negative errno value otherwise and rte_errno is set.
554 flow_dv_convert_action_modify_mac
555 (struct mlx5_flow_dv_modify_hdr_resource *resource,
556 const struct rte_flow_action *action,
557 struct rte_flow_error *error)
559 const struct rte_flow_action_set_mac *conf =
560 (const struct rte_flow_action_set_mac *)(action->conf);
561 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
562 struct rte_flow_item_eth eth;
563 struct rte_flow_item_eth eth_mask;
565 memset(ð, 0, sizeof(eth));
566 memset(ð_mask, 0, sizeof(eth_mask));
567 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
568 memcpy(ð.src.addr_bytes, &conf->mac_addr,
569 sizeof(eth.src.addr_bytes));
570 memcpy(ð_mask.src.addr_bytes,
571 &rte_flow_item_eth_mask.src.addr_bytes,
572 sizeof(eth_mask.src.addr_bytes));
574 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
575 sizeof(eth.dst.addr_bytes));
576 memcpy(ð_mask.dst.addr_bytes,
577 &rte_flow_item_eth_mask.dst.addr_bytes,
578 sizeof(eth_mask.dst.addr_bytes));
581 item.mask = ð_mask;
582 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set VLAN VID action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_vlan_vid
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_of_set_vlan_vid *conf =
606 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
607 int i = resource->actions_num;
608 struct mlx5_modification_cmd *actions = resource->actions;
609 struct field_modify_info *field = modify_vlan_out_first_vid;
611 if (i >= MLX5_MAX_MODIFY_NUM)
612 return rte_flow_error_set(error, EINVAL,
613 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
614 "too many items to modify");
615 actions[i] = (struct mlx5_modification_cmd) {
616 .action_type = MLX5_MODIFICATION_TYPE_SET,
618 .length = field->size,
619 .offset = field->offset,
621 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
622 actions[i].data1 = conf->vlan_vid;
623 actions[i].data1 = actions[i].data1 << 16;
624 resource->actions_num = ++i;
629 * Convert modify-header set TP action to DV specification.
631 * @param[in,out] resource
632 * Pointer to the modify-header resource.
634 * Pointer to action specification.
636 * Pointer to rte_flow_item objects list.
638 * Pointer to flow attributes structure.
639 * @param[in] dev_flow
640 * Pointer to the sub flow.
641 * @param[in] tunnel_decap
642 * Whether action is after tunnel decapsulation.
644 * Pointer to the error structure.
647 * 0 on success, a negative errno value otherwise and rte_errno is set.
650 flow_dv_convert_action_modify_tp
651 (struct mlx5_flow_dv_modify_hdr_resource *resource,
652 const struct rte_flow_action *action,
653 const struct rte_flow_item *items,
654 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
655 bool tunnel_decap, struct rte_flow_error *error)
657 const struct rte_flow_action_set_tp *conf =
658 (const struct rte_flow_action_set_tp *)(action->conf);
659 struct rte_flow_item item;
660 struct rte_flow_item_udp udp;
661 struct rte_flow_item_udp udp_mask;
662 struct rte_flow_item_tcp tcp;
663 struct rte_flow_item_tcp tcp_mask;
664 struct field_modify_info *field;
667 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
669 memset(&udp, 0, sizeof(udp));
670 memset(&udp_mask, 0, sizeof(udp_mask));
671 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
672 udp.hdr.src_port = conf->port;
673 udp_mask.hdr.src_port =
674 rte_flow_item_udp_mask.hdr.src_port;
676 udp.hdr.dst_port = conf->port;
677 udp_mask.hdr.dst_port =
678 rte_flow_item_udp_mask.hdr.dst_port;
680 item.type = RTE_FLOW_ITEM_TYPE_UDP;
682 item.mask = &udp_mask;
685 MLX5_ASSERT(attr->tcp);
686 memset(&tcp, 0, sizeof(tcp));
687 memset(&tcp_mask, 0, sizeof(tcp_mask));
688 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
689 tcp.hdr.src_port = conf->port;
690 tcp_mask.hdr.src_port =
691 rte_flow_item_tcp_mask.hdr.src_port;
693 tcp.hdr.dst_port = conf->port;
694 tcp_mask.hdr.dst_port =
695 rte_flow_item_tcp_mask.hdr.dst_port;
697 item.type = RTE_FLOW_ITEM_TYPE_TCP;
699 item.mask = &tcp_mask;
702 return flow_dv_convert_modify_action(&item, field, NULL, resource,
703 MLX5_MODIFICATION_TYPE_SET, error);
707 * Convert modify-header set TTL action to DV specification.
709 * @param[in,out] resource
710 * Pointer to the modify-header resource.
712 * Pointer to action specification.
714 * Pointer to rte_flow_item objects list.
716 * Pointer to flow attributes structure.
717 * @param[in] dev_flow
718 * Pointer to the sub flow.
719 * @param[in] tunnel_decap
720 * Whether action is after tunnel decapsulation.
722 * Pointer to the error structure.
725 * 0 on success, a negative errno value otherwise and rte_errno is set.
728 flow_dv_convert_action_modify_ttl
729 (struct mlx5_flow_dv_modify_hdr_resource *resource,
730 const struct rte_flow_action *action,
731 const struct rte_flow_item *items,
732 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
733 bool tunnel_decap, struct rte_flow_error *error)
735 const struct rte_flow_action_set_ttl *conf =
736 (const struct rte_flow_action_set_ttl *)(action->conf);
737 struct rte_flow_item item;
738 struct rte_flow_item_ipv4 ipv4;
739 struct rte_flow_item_ipv4 ipv4_mask;
740 struct rte_flow_item_ipv6 ipv6;
741 struct rte_flow_item_ipv6 ipv6_mask;
742 struct field_modify_info *field;
745 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
747 memset(&ipv4, 0, sizeof(ipv4));
748 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
749 ipv4.hdr.time_to_live = conf->ttl_value;
750 ipv4_mask.hdr.time_to_live = 0xFF;
751 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
753 item.mask = &ipv4_mask;
756 MLX5_ASSERT(attr->ipv6);
757 memset(&ipv6, 0, sizeof(ipv6));
758 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
759 ipv6.hdr.hop_limits = conf->ttl_value;
760 ipv6_mask.hdr.hop_limits = 0xFF;
761 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
763 item.mask = &ipv6_mask;
766 return flow_dv_convert_modify_action(&item, field, NULL, resource,
767 MLX5_MODIFICATION_TYPE_SET, error);
771 * Convert modify-header decrement TTL action to DV specification.
773 * @param[in,out] resource
774 * Pointer to the modify-header resource.
776 * Pointer to action specification.
778 * Pointer to rte_flow_item objects list.
780 * Pointer to flow attributes structure.
781 * @param[in] dev_flow
782 * Pointer to the sub flow.
783 * @param[in] tunnel_decap
784 * Whether action is after tunnel decapsulation.
786 * Pointer to the error structure.
789 * 0 on success, a negative errno value otherwise and rte_errno is set.
792 flow_dv_convert_action_modify_dec_ttl
793 (struct mlx5_flow_dv_modify_hdr_resource *resource,
794 const struct rte_flow_item *items,
795 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
796 bool tunnel_decap, struct rte_flow_error *error)
798 struct rte_flow_item item;
799 struct rte_flow_item_ipv4 ipv4;
800 struct rte_flow_item_ipv4 ipv4_mask;
801 struct rte_flow_item_ipv6 ipv6;
802 struct rte_flow_item_ipv6 ipv6_mask;
803 struct field_modify_info *field;
806 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
808 memset(&ipv4, 0, sizeof(ipv4));
809 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
810 ipv4.hdr.time_to_live = 0xFF;
811 ipv4_mask.hdr.time_to_live = 0xFF;
812 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
814 item.mask = &ipv4_mask;
817 MLX5_ASSERT(attr->ipv6);
818 memset(&ipv6, 0, sizeof(ipv6));
819 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
820 ipv6.hdr.hop_limits = 0xFF;
821 ipv6_mask.hdr.hop_limits = 0xFF;
822 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
824 item.mask = &ipv6_mask;
827 return flow_dv_convert_modify_action(&item, field, NULL, resource,
828 MLX5_MODIFICATION_TYPE_ADD, error);
832 * Convert modify-header increment/decrement TCP Sequence number
833 * to DV specification.
835 * @param[in,out] resource
836 * Pointer to the modify-header resource.
838 * Pointer to action specification.
840 * Pointer to the error structure.
843 * 0 on success, a negative errno value otherwise and rte_errno is set.
846 flow_dv_convert_action_modify_tcp_seq
847 (struct mlx5_flow_dv_modify_hdr_resource *resource,
848 const struct rte_flow_action *action,
849 struct rte_flow_error *error)
851 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
852 uint64_t value = rte_be_to_cpu_32(*conf);
853 struct rte_flow_item item;
854 struct rte_flow_item_tcp tcp;
855 struct rte_flow_item_tcp tcp_mask;
857 memset(&tcp, 0, sizeof(tcp));
858 memset(&tcp_mask, 0, sizeof(tcp_mask));
859 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
861 * The HW has no decrement operation, only increment operation.
862 * To simulate decrement X from Y using increment operation
863 * we need to add UINT32_MAX X times to Y.
864 * Each adding of UINT32_MAX decrements Y by 1.
867 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
868 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
869 item.type = RTE_FLOW_ITEM_TYPE_TCP;
871 item.mask = &tcp_mask;
872 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
873 MLX5_MODIFICATION_TYPE_ADD, error);
877 * Convert modify-header increment/decrement TCP Acknowledgment number
878 * to DV specification.
880 * @param[in,out] resource
881 * Pointer to the modify-header resource.
883 * Pointer to action specification.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_tcp_ack
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_action *action,
894 struct rte_flow_error *error)
896 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
897 uint64_t value = rte_be_to_cpu_32(*conf);
898 struct rte_flow_item item;
899 struct rte_flow_item_tcp tcp;
900 struct rte_flow_item_tcp tcp_mask;
902 memset(&tcp, 0, sizeof(tcp));
903 memset(&tcp_mask, 0, sizeof(tcp_mask));
904 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
906 * The HW has no decrement operation, only increment operation.
907 * To simulate decrement X from Y using increment operation
908 * we need to add UINT32_MAX X times to Y.
909 * Each adding of UINT32_MAX decrements Y by 1.
912 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
913 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
914 item.type = RTE_FLOW_ITEM_TYPE_TCP;
916 item.mask = &tcp_mask;
917 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
918 MLX5_MODIFICATION_TYPE_ADD, error);
921 static enum mlx5_modification_field reg_to_field[] = {
922 [REG_NON] = MLX5_MODI_OUT_NONE,
923 [REG_A] = MLX5_MODI_META_DATA_REG_A,
924 [REG_B] = MLX5_MODI_META_DATA_REG_B,
925 [REG_C_0] = MLX5_MODI_META_REG_C_0,
926 [REG_C_1] = MLX5_MODI_META_REG_C_1,
927 [REG_C_2] = MLX5_MODI_META_REG_C_2,
928 [REG_C_3] = MLX5_MODI_META_REG_C_3,
929 [REG_C_4] = MLX5_MODI_META_REG_C_4,
930 [REG_C_5] = MLX5_MODI_META_REG_C_5,
931 [REG_C_6] = MLX5_MODI_META_REG_C_6,
932 [REG_C_7] = MLX5_MODI_META_REG_C_7,
936 * Convert register set to DV specification.
938 * @param[in,out] resource
939 * Pointer to the modify-header resource.
941 * Pointer to action specification.
943 * Pointer to the error structure.
946 * 0 on success, a negative errno value otherwise and rte_errno is set.
949 flow_dv_convert_action_set_reg
950 (struct mlx5_flow_dv_modify_hdr_resource *resource,
951 const struct rte_flow_action *action,
952 struct rte_flow_error *error)
954 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
955 struct mlx5_modification_cmd *actions = resource->actions;
956 uint32_t i = resource->actions_num;
958 if (i >= MLX5_MAX_MODIFY_NUM)
959 return rte_flow_error_set(error, EINVAL,
960 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
961 "too many items to modify");
962 MLX5_ASSERT(conf->id != REG_NON);
963 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
964 actions[i] = (struct mlx5_modification_cmd) {
965 .action_type = MLX5_MODIFICATION_TYPE_SET,
966 .field = reg_to_field[conf->id],
968 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
969 actions[i].data1 = rte_cpu_to_be_32(conf->data);
971 resource->actions_num = i;
976 * Convert SET_TAG action to DV specification.
979 * Pointer to the rte_eth_dev structure.
980 * @param[in,out] resource
981 * Pointer to the modify-header resource.
983 * Pointer to action specification.
985 * Pointer to the error structure.
988 * 0 on success, a negative errno value otherwise and rte_errno is set.
991 flow_dv_convert_action_set_tag
992 (struct rte_eth_dev *dev,
993 struct mlx5_flow_dv_modify_hdr_resource *resource,
994 const struct rte_flow_action_set_tag *conf,
995 struct rte_flow_error *error)
997 rte_be32_t data = rte_cpu_to_be_32(conf->data);
998 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
999 struct rte_flow_item item = {
1003 struct field_modify_info reg_c_x[] = {
1006 enum mlx5_modification_field reg_type;
1009 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1012 MLX5_ASSERT(ret != REG_NON);
1013 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014 reg_type = reg_to_field[ret];
1015 MLX5_ASSERT(reg_type > 0);
1016 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018 MLX5_MODIFICATION_TYPE_SET, error);
1022 * Convert internal COPY_REG action to DV specification.
1025 * Pointer to the rte_eth_dev structure.
1026 * @param[in,out] res
1027 * Pointer to the modify-header resource.
1029 * Pointer to action specification.
1031 * Pointer to the error structure.
1034 * 0 on success, a negative errno value otherwise and rte_errno is set.
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038 struct mlx5_flow_dv_modify_hdr_resource *res,
1039 const struct rte_flow_action *action,
1040 struct rte_flow_error *error)
1042 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044 struct rte_flow_item item = {
1048 struct field_modify_info reg_src[] = {
1049 {4, 0, reg_to_field[conf->src]},
1052 struct field_modify_info reg_dst = {
1054 .id = reg_to_field[conf->dst],
1056 /* Adjust reg_c[0] usage according to reported mask. */
1057 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058 struct mlx5_priv *priv = dev->data->dev_private;
1059 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1061 MLX5_ASSERT(reg_c0);
1062 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063 if (conf->dst == REG_C_0) {
1064 /* Copy to reg_c[0], within mask only. */
1065 reg_dst.offset = rte_bsf32(reg_c0);
1067 * Mask is ignoring the enianness, because
1068 * there is no conversion in datapath.
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071 /* Copy from destination lower bits to reg_c[0]. */
1072 mask = reg_c0 >> reg_dst.offset;
1074 /* Copy from destination upper bits to reg_c[0]. */
1075 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076 rte_fls_u32(reg_c0));
1079 mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081 /* Copy from reg_c[0] to destination lower bits. */
1084 /* Copy from reg_c[0] to destination upper bits. */
1085 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086 (rte_fls_u32(reg_c0) -
1091 return flow_dv_convert_modify_action(&item,
1092 reg_src, ®_dst, res,
1093 MLX5_MODIFICATION_TYPE_COPY,
1098 * Convert MARK action to DV specification. This routine is used
1099 * in extensive metadata only and requires metadata register to be
1100 * handled. In legacy mode hardware tag resource is engaged.
1103 * Pointer to the rte_eth_dev structure.
1105 * Pointer to MARK action specification.
1106 * @param[in,out] resource
1107 * Pointer to the modify-header resource.
1109 * Pointer to the error structure.
1112 * 0 on success, a negative errno value otherwise and rte_errno is set.
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116 const struct rte_flow_action_mark *conf,
1117 struct mlx5_flow_dv_modify_hdr_resource *resource,
1118 struct rte_flow_error *error)
1120 struct mlx5_priv *priv = dev->data->dev_private;
1121 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122 priv->sh->dv_mark_mask);
1123 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124 struct rte_flow_item item = {
1128 struct field_modify_info reg_c_x[] = {
1134 return rte_flow_error_set(error, EINVAL,
1135 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136 NULL, "zero mark action mask");
1137 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1140 MLX5_ASSERT(reg > 0);
1141 if (reg == REG_C_0) {
1142 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143 uint32_t shl_c0 = rte_bsf32(msk_c0);
1145 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147 mask = rte_cpu_to_be_32(mask << shl_c0);
1149 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151 MLX5_MODIFICATION_TYPE_SET, error);
1155 * Get metadata register index for specified steering domain.
1158 * Pointer to the rte_eth_dev structure.
1160 * Attributes of flow to determine steering domain.
1162 * Pointer to the error structure.
1165 * positive index on success, a negative errno value otherwise
1166 * and rte_errno is set.
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170 const struct rte_flow_attr *attr,
1171 struct rte_flow_error *error)
1174 mlx5_flow_get_reg_id(dev, attr->transfer ?
1178 MLX5_METADATA_RX, 0, error);
1180 return rte_flow_error_set(error,
1181 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182 NULL, "unavailable "
1183 "metadata register");
1188 * Convert SET_META action to DV specification.
1191 * Pointer to the rte_eth_dev structure.
1192 * @param[in,out] resource
1193 * Pointer to the modify-header resource.
1195 * Attributes of flow that includes this item.
1197 * Pointer to action specification.
1199 * Pointer to the error structure.
1202 * 0 on success, a negative errno value otherwise and rte_errno is set.
1205 flow_dv_convert_action_set_meta
1206 (struct rte_eth_dev *dev,
1207 struct mlx5_flow_dv_modify_hdr_resource *resource,
1208 const struct rte_flow_attr *attr,
1209 const struct rte_flow_action_set_meta *conf,
1210 struct rte_flow_error *error)
1212 uint32_t data = conf->data;
1213 uint32_t mask = conf->mask;
1214 struct rte_flow_item item = {
1218 struct field_modify_info reg_c_x[] = {
1221 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225 MLX5_ASSERT(reg != REG_NON);
1227 * In datapath code there is no endianness
1228 * coversions for perfromance reasons, all
1229 * pattern conversions are done in rte_flow.
1231 if (reg == REG_C_0) {
1232 struct mlx5_priv *priv = dev->data->dev_private;
1233 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1236 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238 shl_c0 = rte_bsf32(msk_c0);
1240 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1244 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1246 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247 /* The routine expects parameters in memory as big-endian ones. */
1248 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249 MLX5_MODIFICATION_TYPE_SET, error);
1253 * Convert modify-header set IPv4 DSCP action to DV specification.
1255 * @param[in,out] resource
1256 * Pointer to the modify-header resource.
1258 * Pointer to action specification.
1260 * Pointer to the error structure.
1263 * 0 on success, a negative errno value otherwise and rte_errno is set.
1266 flow_dv_convert_action_modify_ipv4_dscp
1267 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268 const struct rte_flow_action *action,
1269 struct rte_flow_error *error)
1271 const struct rte_flow_action_set_dscp *conf =
1272 (const struct rte_flow_action_set_dscp *)(action->conf);
1273 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274 struct rte_flow_item_ipv4 ipv4;
1275 struct rte_flow_item_ipv4 ipv4_mask;
1277 memset(&ipv4, 0, sizeof(ipv4));
1278 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279 ipv4.hdr.type_of_service = conf->dscp;
1280 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1282 item.mask = &ipv4_mask;
1283 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284 MLX5_MODIFICATION_TYPE_SET, error);
1288 * Convert modify-header set IPv6 DSCP action to DV specification.
1290 * @param[in,out] resource
1291 * Pointer to the modify-header resource.
1293 * Pointer to action specification.
1295 * Pointer to the error structure.
1298 * 0 on success, a negative errno value otherwise and rte_errno is set.
1301 flow_dv_convert_action_modify_ipv6_dscp
1302 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303 const struct rte_flow_action *action,
1304 struct rte_flow_error *error)
1306 const struct rte_flow_action_set_dscp *conf =
1307 (const struct rte_flow_action_set_dscp *)(action->conf);
1308 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309 struct rte_flow_item_ipv6 ipv6;
1310 struct rte_flow_item_ipv6 ipv6_mask;
1312 memset(&ipv6, 0, sizeof(ipv6));
1313 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1315 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316 * rdma-core only accept the DSCP bits byte aligned start from
1317 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318 * bits in IPv6 case as rdma-core requires byte aligned value.
1320 ipv6.hdr.vtc_flow = conf->dscp;
1321 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1323 item.mask = &ipv6_mask;
1324 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325 MLX5_MODIFICATION_TYPE_SET, error);
1329 mlx5_flow_field_id_to_modify_info
1330 (const struct rte_flow_action_modify_data *data,
1331 struct field_modify_info *info,
1332 uint32_t *mask, uint32_t *value, uint32_t width,
1333 struct rte_eth_dev *dev,
1334 const struct rte_flow_attr *attr,
1335 struct rte_flow_error *error)
1338 switch (data->field) {
1339 case RTE_FLOW_FIELD_START:
1340 /* not supported yet */
1343 case RTE_FLOW_FIELD_MAC_DST:
1345 if (data->offset < 32) {
1346 info[idx] = (struct field_modify_info){4, 0,
1347 MLX5_MODI_OUT_DMAC_47_16};
1350 rte_cpu_to_be_32(0xffffffff >>
1354 mask[idx] = RTE_BE32(0xffffffff);
1361 info[idx] = (struct field_modify_info){2, 4 * idx,
1362 MLX5_MODI_OUT_DMAC_15_0};
1363 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1365 if (data->offset < 32)
1366 info[idx++] = (struct field_modify_info){4, 0,
1367 MLX5_MODI_OUT_DMAC_47_16};
1368 info[idx] = (struct field_modify_info){2, 0,
1369 MLX5_MODI_OUT_DMAC_15_0};
1372 case RTE_FLOW_FIELD_MAC_SRC:
1374 if (data->offset < 32) {
1375 info[idx] = (struct field_modify_info){4, 0,
1376 MLX5_MODI_OUT_SMAC_47_16};
1379 rte_cpu_to_be_32(0xffffffff >>
1383 mask[idx] = RTE_BE32(0xffffffff);
1390 info[idx] = (struct field_modify_info){2, 4 * idx,
1391 MLX5_MODI_OUT_SMAC_15_0};
1392 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1394 if (data->offset < 32)
1395 info[idx++] = (struct field_modify_info){4, 0,
1396 MLX5_MODI_OUT_SMAC_47_16};
1397 info[idx] = (struct field_modify_info){2, 0,
1398 MLX5_MODI_OUT_SMAC_15_0};
1401 case RTE_FLOW_FIELD_VLAN_TYPE:
1402 /* not supported yet */
1404 case RTE_FLOW_FIELD_VLAN_ID:
1405 info[idx] = (struct field_modify_info){2, 0,
1406 MLX5_MODI_OUT_FIRST_VID};
1408 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1410 case RTE_FLOW_FIELD_MAC_TYPE:
1411 info[idx] = (struct field_modify_info){2, 0,
1412 MLX5_MODI_OUT_ETHERTYPE};
1414 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1416 case RTE_FLOW_FIELD_IPV4_DSCP:
1417 info[idx] = (struct field_modify_info){1, 0,
1418 MLX5_MODI_OUT_IP_DSCP};
1420 mask[idx] = 0x3f >> (6 - width);
1422 case RTE_FLOW_FIELD_IPV4_TTL:
1423 info[idx] = (struct field_modify_info){1, 0,
1424 MLX5_MODI_OUT_IPV4_TTL};
1426 mask[idx] = 0xff >> (8 - width);
1428 case RTE_FLOW_FIELD_IPV4_SRC:
1429 info[idx] = (struct field_modify_info){4, 0,
1430 MLX5_MODI_OUT_SIPV4};
1432 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1435 case RTE_FLOW_FIELD_IPV4_DST:
1436 info[idx] = (struct field_modify_info){4, 0,
1437 MLX5_MODI_OUT_DIPV4};
1439 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1442 case RTE_FLOW_FIELD_IPV6_DSCP:
1443 info[idx] = (struct field_modify_info){1, 0,
1444 MLX5_MODI_OUT_IP_DSCP};
1446 mask[idx] = 0x3f >> (6 - width);
1448 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1449 info[idx] = (struct field_modify_info){1, 0,
1450 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1452 mask[idx] = 0xff >> (8 - width);
1454 case RTE_FLOW_FIELD_IPV6_SRC:
1456 if (data->offset < 32) {
1457 info[idx] = (struct field_modify_info){4,
1459 MLX5_MODI_OUT_SIPV6_31_0};
1462 rte_cpu_to_be_32(0xffffffff >>
1466 mask[idx] = RTE_BE32(0xffffffff);
1473 if (data->offset < 64) {
1474 info[idx] = (struct field_modify_info){4,
1476 MLX5_MODI_OUT_SIPV6_63_32};
1479 rte_cpu_to_be_32(0xffffffff >>
1483 mask[idx] = RTE_BE32(0xffffffff);
1490 if (data->offset < 96) {
1491 info[idx] = (struct field_modify_info){4,
1493 MLX5_MODI_OUT_SIPV6_95_64};
1496 rte_cpu_to_be_32(0xffffffff >>
1500 mask[idx] = RTE_BE32(0xffffffff);
1507 info[idx] = (struct field_modify_info){4, 4 * idx,
1508 MLX5_MODI_OUT_SIPV6_127_96};
1509 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1512 if (data->offset < 32)
1513 info[idx++] = (struct field_modify_info){4, 0,
1514 MLX5_MODI_OUT_SIPV6_31_0};
1515 if (data->offset < 64)
1516 info[idx++] = (struct field_modify_info){4, 0,
1517 MLX5_MODI_OUT_SIPV6_63_32};
1518 if (data->offset < 96)
1519 info[idx++] = (struct field_modify_info){4, 0,
1520 MLX5_MODI_OUT_SIPV6_95_64};
1521 if (data->offset < 128)
1522 info[idx++] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SIPV6_127_96};
1526 case RTE_FLOW_FIELD_IPV6_DST:
1528 if (data->offset < 32) {
1529 info[idx] = (struct field_modify_info){4,
1531 MLX5_MODI_OUT_DIPV6_31_0};
1534 rte_cpu_to_be_32(0xffffffff >>
1538 mask[idx] = RTE_BE32(0xffffffff);
1545 if (data->offset < 64) {
1546 info[idx] = (struct field_modify_info){4,
1548 MLX5_MODI_OUT_DIPV6_63_32};
1551 rte_cpu_to_be_32(0xffffffff >>
1555 mask[idx] = RTE_BE32(0xffffffff);
1562 if (data->offset < 96) {
1563 info[idx] = (struct field_modify_info){4,
1565 MLX5_MODI_OUT_DIPV6_95_64};
1568 rte_cpu_to_be_32(0xffffffff >>
1572 mask[idx] = RTE_BE32(0xffffffff);
1579 info[idx] = (struct field_modify_info){4, 4 * idx,
1580 MLX5_MODI_OUT_DIPV6_127_96};
1581 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1584 if (data->offset < 32)
1585 info[idx++] = (struct field_modify_info){4, 0,
1586 MLX5_MODI_OUT_DIPV6_31_0};
1587 if (data->offset < 64)
1588 info[idx++] = (struct field_modify_info){4, 0,
1589 MLX5_MODI_OUT_DIPV6_63_32};
1590 if (data->offset < 96)
1591 info[idx++] = (struct field_modify_info){4, 0,
1592 MLX5_MODI_OUT_DIPV6_95_64};
1593 if (data->offset < 128)
1594 info[idx++] = (struct field_modify_info){4, 0,
1595 MLX5_MODI_OUT_DIPV6_127_96};
1598 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1599 info[idx] = (struct field_modify_info){2, 0,
1600 MLX5_MODI_OUT_TCP_SPORT};
1602 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1604 case RTE_FLOW_FIELD_TCP_PORT_DST:
1605 info[idx] = (struct field_modify_info){2, 0,
1606 MLX5_MODI_OUT_TCP_DPORT};
1608 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1610 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1611 info[idx] = (struct field_modify_info){4, 0,
1612 MLX5_MODI_OUT_TCP_SEQ_NUM};
1614 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1617 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1618 info[idx] = (struct field_modify_info){4, 0,
1619 MLX5_MODI_OUT_TCP_ACK_NUM};
1621 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1624 case RTE_FLOW_FIELD_TCP_FLAGS:
1625 info[idx] = (struct field_modify_info){1, 0,
1626 MLX5_MODI_OUT_TCP_FLAGS};
1628 mask[idx] = 0x3f >> (6 - width);
1630 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1631 info[idx] = (struct field_modify_info){2, 0,
1632 MLX5_MODI_OUT_UDP_SPORT};
1634 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1636 case RTE_FLOW_FIELD_UDP_PORT_DST:
1637 info[idx] = (struct field_modify_info){2, 0,
1638 MLX5_MODI_OUT_UDP_DPORT};
1640 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1642 case RTE_FLOW_FIELD_VXLAN_VNI:
1643 /* not supported yet */
1645 case RTE_FLOW_FIELD_GENEVE_VNI:
1646 /* not supported yet*/
1648 case RTE_FLOW_FIELD_GTP_TEID:
1649 info[idx] = (struct field_modify_info){4, 0,
1650 MLX5_MODI_GTP_TEID};
1652 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1655 case RTE_FLOW_FIELD_TAG:
1657 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1658 data->level, error);
1661 MLX5_ASSERT(reg != REG_NON);
1662 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1663 info[idx] = (struct field_modify_info){4, 0,
1667 rte_cpu_to_be_32(0xffffffff >>
1671 case RTE_FLOW_FIELD_MARK:
1673 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1677 MLX5_ASSERT(reg != REG_NON);
1678 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1679 info[idx] = (struct field_modify_info){4, 0,
1683 rte_cpu_to_be_32(0xffffffff >>
1687 case RTE_FLOW_FIELD_META:
1689 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1692 MLX5_ASSERT(reg != REG_NON);
1693 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1694 info[idx] = (struct field_modify_info){4, 0,
1698 rte_cpu_to_be_32(0xffffffff >>
1702 case RTE_FLOW_FIELD_POINTER:
1703 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1706 (void *)(uintptr_t)data->value, 32);
1707 value[idx] = rte_cpu_to_be_32(value[idx]);
1712 case RTE_FLOW_FIELD_VALUE:
1713 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1716 rte_cpu_to_be_32((uint32_t)data->value);
1728 * Convert modify_field action to DV specification.
1731 * Pointer to the rte_eth_dev structure.
1732 * @param[in,out] resource
1733 * Pointer to the modify-header resource.
1735 * Pointer to action specification.
1737 * Attributes of flow that includes this item.
1739 * Pointer to the error structure.
1742 * 0 on success, a negative errno value otherwise and rte_errno is set.
1745 flow_dv_convert_action_modify_field
1746 (struct rte_eth_dev *dev,
1747 struct mlx5_flow_dv_modify_hdr_resource *resource,
1748 const struct rte_flow_action *action,
1749 const struct rte_flow_attr *attr,
1750 struct rte_flow_error *error)
1752 const struct rte_flow_action_modify_field *conf =
1753 (const struct rte_flow_action_modify_field *)(action->conf);
1754 struct rte_flow_item item;
1755 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1757 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1759 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1760 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1763 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1764 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1765 type = MLX5_MODIFICATION_TYPE_SET;
1766 /** For SET fill the destination field (field) first. */
1767 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1768 value, conf->width, dev, attr, error);
1769 /** Then copy immediate value from source as per mask. */
1770 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1771 value, conf->width, dev, attr, error);
1774 type = MLX5_MODIFICATION_TYPE_COPY;
1775 /** For COPY fill the destination field (dcopy) without mask. */
1776 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1777 value, conf->width, dev, attr, error);
1778 /** Then construct the source field (field) with mask. */
1779 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1780 value, conf->width, dev, attr, error);
1783 return flow_dv_convert_modify_action(&item,
1784 field, dcopy, resource, type, error);
1788 * Validate MARK item.
1791 * Pointer to the rte_eth_dev structure.
1793 * Item specification.
1795 * Attributes of flow that includes this item.
1797 * Pointer to error structure.
1800 * 0 on success, a negative errno value otherwise and rte_errno is set.
1803 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1804 const struct rte_flow_item *item,
1805 const struct rte_flow_attr *attr __rte_unused,
1806 struct rte_flow_error *error)
1808 struct mlx5_priv *priv = dev->data->dev_private;
1809 struct mlx5_dev_config *config = &priv->config;
1810 const struct rte_flow_item_mark *spec = item->spec;
1811 const struct rte_flow_item_mark *mask = item->mask;
1812 const struct rte_flow_item_mark nic_mask = {
1813 .id = priv->sh->dv_mark_mask,
1817 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1818 return rte_flow_error_set(error, ENOTSUP,
1819 RTE_FLOW_ERROR_TYPE_ITEM, item,
1820 "extended metadata feature"
1822 if (!mlx5_flow_ext_mreg_supported(dev))
1823 return rte_flow_error_set(error, ENOTSUP,
1824 RTE_FLOW_ERROR_TYPE_ITEM, item,
1825 "extended metadata register"
1826 " isn't supported");
1828 return rte_flow_error_set(error, ENOTSUP,
1829 RTE_FLOW_ERROR_TYPE_ITEM, item,
1830 "extended metadata register"
1831 " isn't available");
1832 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1836 return rte_flow_error_set(error, EINVAL,
1837 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1839 "data cannot be empty");
1840 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1841 return rte_flow_error_set(error, EINVAL,
1842 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1844 "mark id exceeds the limit");
1848 return rte_flow_error_set(error, EINVAL,
1849 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1850 "mask cannot be zero");
1852 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1853 (const uint8_t *)&nic_mask,
1854 sizeof(struct rte_flow_item_mark),
1855 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1862 * Validate META item.
1865 * Pointer to the rte_eth_dev structure.
1867 * Item specification.
1869 * Attributes of flow that includes this item.
1871 * Pointer to error structure.
1874 * 0 on success, a negative errno value otherwise and rte_errno is set.
1877 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1878 const struct rte_flow_item *item,
1879 const struct rte_flow_attr *attr,
1880 struct rte_flow_error *error)
1882 struct mlx5_priv *priv = dev->data->dev_private;
1883 struct mlx5_dev_config *config = &priv->config;
1884 const struct rte_flow_item_meta *spec = item->spec;
1885 const struct rte_flow_item_meta *mask = item->mask;
1886 struct rte_flow_item_meta nic_mask = {
1893 return rte_flow_error_set(error, EINVAL,
1894 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1896 "data cannot be empty");
1897 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1898 if (!mlx5_flow_ext_mreg_supported(dev))
1899 return rte_flow_error_set(error, ENOTSUP,
1900 RTE_FLOW_ERROR_TYPE_ITEM, item,
1901 "extended metadata register"
1902 " isn't supported");
1903 reg = flow_dv_get_metadata_reg(dev, attr, error);
1907 return rte_flow_error_set(error, ENOTSUP,
1908 RTE_FLOW_ERROR_TYPE_ITEM, item,
1909 "unavalable extended metadata register");
1911 return rte_flow_error_set(error, ENOTSUP,
1912 RTE_FLOW_ERROR_TYPE_ITEM, item,
1916 nic_mask.data = priv->sh->dv_meta_mask;
1919 return rte_flow_error_set(error, ENOTSUP,
1920 RTE_FLOW_ERROR_TYPE_ITEM, item,
1921 "extended metadata feature "
1922 "should be enabled when "
1923 "meta item is requested "
1924 "with e-switch mode ");
1926 return rte_flow_error_set(error, ENOTSUP,
1927 RTE_FLOW_ERROR_TYPE_ITEM, item,
1928 "match on metadata for ingress "
1929 "is not supported in legacy "
1933 mask = &rte_flow_item_meta_mask;
1935 return rte_flow_error_set(error, EINVAL,
1936 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1937 "mask cannot be zero");
1939 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1940 (const uint8_t *)&nic_mask,
1941 sizeof(struct rte_flow_item_meta),
1942 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1947 * Validate TAG item.
1950 * Pointer to the rte_eth_dev structure.
1952 * Item specification.
1954 * Attributes of flow that includes this item.
1956 * Pointer to error structure.
1959 * 0 on success, a negative errno value otherwise and rte_errno is set.
1962 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1963 const struct rte_flow_item *item,
1964 const struct rte_flow_attr *attr __rte_unused,
1965 struct rte_flow_error *error)
1967 const struct rte_flow_item_tag *spec = item->spec;
1968 const struct rte_flow_item_tag *mask = item->mask;
1969 const struct rte_flow_item_tag nic_mask = {
1970 .data = RTE_BE32(UINT32_MAX),
1975 if (!mlx5_flow_ext_mreg_supported(dev))
1976 return rte_flow_error_set(error, ENOTSUP,
1977 RTE_FLOW_ERROR_TYPE_ITEM, item,
1978 "extensive metadata register"
1979 " isn't supported");
1981 return rte_flow_error_set(error, EINVAL,
1982 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1984 "data cannot be empty");
1986 mask = &rte_flow_item_tag_mask;
1988 return rte_flow_error_set(error, EINVAL,
1989 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1990 "mask cannot be zero");
1992 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1993 (const uint8_t *)&nic_mask,
1994 sizeof(struct rte_flow_item_tag),
1995 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1998 if (mask->index != 0xff)
1999 return rte_flow_error_set(error, EINVAL,
2000 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001 "partial mask for tag index"
2002 " is not supported");
2003 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2006 MLX5_ASSERT(ret != REG_NON);
2011 * Validate vport item.
2014 * Pointer to the rte_eth_dev structure.
2016 * Item specification.
2018 * Attributes of flow that includes this item.
2019 * @param[in] item_flags
2020 * Bit-fields that holds the items detected until now.
2022 * Pointer to error structure.
2025 * 0 on success, a negative errno value otherwise and rte_errno is set.
2028 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2029 const struct rte_flow_item *item,
2030 const struct rte_flow_attr *attr,
2031 uint64_t item_flags,
2032 struct rte_flow_error *error)
2034 const struct rte_flow_item_port_id *spec = item->spec;
2035 const struct rte_flow_item_port_id *mask = item->mask;
2036 const struct rte_flow_item_port_id switch_mask = {
2039 struct mlx5_priv *esw_priv;
2040 struct mlx5_priv *dev_priv;
2043 if (!attr->transfer)
2044 return rte_flow_error_set(error, EINVAL,
2045 RTE_FLOW_ERROR_TYPE_ITEM,
2047 "match on port id is valid only"
2048 " when transfer flag is enabled");
2049 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2050 return rte_flow_error_set(error, ENOTSUP,
2051 RTE_FLOW_ERROR_TYPE_ITEM, item,
2052 "multiple source ports are not"
2055 mask = &switch_mask;
2056 if (mask->id != 0xffffffff)
2057 return rte_flow_error_set(error, ENOTSUP,
2058 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2060 "no support for partial mask on"
2062 ret = mlx5_flow_item_acceptable
2063 (item, (const uint8_t *)mask,
2064 (const uint8_t *)&rte_flow_item_port_id_mask,
2065 sizeof(struct rte_flow_item_port_id),
2066 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2071 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2073 return rte_flow_error_set(error, rte_errno,
2074 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2075 "failed to obtain E-Switch info for"
2077 dev_priv = mlx5_dev_to_eswitch_info(dev);
2079 return rte_flow_error_set(error, rte_errno,
2080 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2082 "failed to obtain E-Switch info");
2083 if (esw_priv->domain_id != dev_priv->domain_id)
2084 return rte_flow_error_set(error, EINVAL,
2085 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086 "cannot match on a port from a"
2087 " different E-Switch");
2092 * Validate VLAN item.
2095 * Item specification.
2096 * @param[in] item_flags
2097 * Bit-fields that holds the items detected until now.
2099 * Ethernet device flow is being created on.
2101 * Pointer to error structure.
2104 * 0 on success, a negative errno value otherwise and rte_errno is set.
2107 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2108 uint64_t item_flags,
2109 struct rte_eth_dev *dev,
2110 struct rte_flow_error *error)
2112 const struct rte_flow_item_vlan *mask = item->mask;
2113 const struct rte_flow_item_vlan nic_mask = {
2114 .tci = RTE_BE16(UINT16_MAX),
2115 .inner_type = RTE_BE16(UINT16_MAX),
2118 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2120 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2121 MLX5_FLOW_LAYER_INNER_L4) :
2122 (MLX5_FLOW_LAYER_OUTER_L3 |
2123 MLX5_FLOW_LAYER_OUTER_L4);
2124 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2125 MLX5_FLOW_LAYER_OUTER_VLAN;
2127 if (item_flags & vlanm)
2128 return rte_flow_error_set(error, EINVAL,
2129 RTE_FLOW_ERROR_TYPE_ITEM, item,
2130 "multiple VLAN layers not supported");
2131 else if ((item_flags & l34m) != 0)
2132 return rte_flow_error_set(error, EINVAL,
2133 RTE_FLOW_ERROR_TYPE_ITEM, item,
2134 "VLAN cannot follow L3/L4 layer");
2136 mask = &rte_flow_item_vlan_mask;
2137 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2138 (const uint8_t *)&nic_mask,
2139 sizeof(struct rte_flow_item_vlan),
2140 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2143 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2144 struct mlx5_priv *priv = dev->data->dev_private;
2146 if (priv->vmwa_context) {
2148 * Non-NULL context means we have a virtual machine
2149 * and SR-IOV enabled, we have to create VLAN interface
2150 * to make hypervisor to setup E-Switch vport
2151 * context correctly. We avoid creating the multiple
2152 * VLAN interfaces, so we cannot support VLAN tag mask.
2154 return rte_flow_error_set(error, EINVAL,
2155 RTE_FLOW_ERROR_TYPE_ITEM,
2157 "VLAN tag mask is not"
2158 " supported in virtual"
2166 * GTP flags are contained in 1 byte of the format:
2167 * -------------------------------------------
2168 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2169 * |-----------------------------------------|
2170 * | value | Version | PT | Res | E | S | PN |
2171 * -------------------------------------------
2173 * Matching is supported only for GTP flags E, S, PN.
2175 #define MLX5_GTP_FLAGS_MASK 0x07
2178 * Validate GTP item.
2181 * Pointer to the rte_eth_dev structure.
2183 * Item specification.
2184 * @param[in] item_flags
2185 * Bit-fields that holds the items detected until now.
2187 * Pointer to error structure.
2190 * 0 on success, a negative errno value otherwise and rte_errno is set.
2193 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2194 const struct rte_flow_item *item,
2195 uint64_t item_flags,
2196 struct rte_flow_error *error)
2198 struct mlx5_priv *priv = dev->data->dev_private;
2199 const struct rte_flow_item_gtp *spec = item->spec;
2200 const struct rte_flow_item_gtp *mask = item->mask;
2201 const struct rte_flow_item_gtp nic_mask = {
2202 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2204 .teid = RTE_BE32(0xffffffff),
2207 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2208 return rte_flow_error_set(error, ENOTSUP,
2209 RTE_FLOW_ERROR_TYPE_ITEM, item,
2210 "GTP support is not enabled");
2211 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2212 return rte_flow_error_set(error, ENOTSUP,
2213 RTE_FLOW_ERROR_TYPE_ITEM, item,
2214 "multiple tunnel layers not"
2216 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2217 return rte_flow_error_set(error, EINVAL,
2218 RTE_FLOW_ERROR_TYPE_ITEM, item,
2219 "no outer UDP layer found");
2221 mask = &rte_flow_item_gtp_mask;
2222 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2223 return rte_flow_error_set(error, ENOTSUP,
2224 RTE_FLOW_ERROR_TYPE_ITEM, item,
2225 "Match is supported for GTP"
2227 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2228 (const uint8_t *)&nic_mask,
2229 sizeof(struct rte_flow_item_gtp),
2230 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2234 * Validate GTP PSC item.
2237 * Item specification.
2238 * @param[in] last_item
2239 * Previous validated item in the pattern items.
2240 * @param[in] gtp_item
2241 * Previous GTP item specification.
2243 * Pointer to flow attributes.
2245 * Pointer to error structure.
2248 * 0 on success, a negative errno value otherwise and rte_errno is set.
2251 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2253 const struct rte_flow_item *gtp_item,
2254 const struct rte_flow_attr *attr,
2255 struct rte_flow_error *error)
2257 const struct rte_flow_item_gtp *gtp_spec;
2258 const struct rte_flow_item_gtp *gtp_mask;
2259 const struct rte_flow_item_gtp_psc *spec;
2260 const struct rte_flow_item_gtp_psc *mask;
2261 const struct rte_flow_item_gtp_psc nic_mask = {
2266 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2267 return rte_flow_error_set
2268 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2269 "GTP PSC item must be preceded with GTP item");
2270 gtp_spec = gtp_item->spec;
2271 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2272 /* GTP spec and E flag is requested to match zero. */
2274 (gtp_mask->v_pt_rsv_flags &
2275 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2276 return rte_flow_error_set
2277 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2278 "GTP E flag must be 1 to match GTP PSC");
2279 /* Check the flow is not created in group zero. */
2280 if (!attr->transfer && !attr->group)
2281 return rte_flow_error_set
2282 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2283 "GTP PSC is not supported for group 0");
2284 /* GTP spec is here and E flag is requested to match zero. */
2288 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2289 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2290 return rte_flow_error_set
2291 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2292 "PDU type should be smaller than 16");
2293 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2294 (const uint8_t *)&nic_mask,
2295 sizeof(struct rte_flow_item_gtp_psc),
2296 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2300 * Validate IPV4 item.
2301 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2302 * add specific validation of fragment_offset field,
2305 * Item specification.
2306 * @param[in] item_flags
2307 * Bit-fields that holds the items detected until now.
2309 * Pointer to error structure.
2312 * 0 on success, a negative errno value otherwise and rte_errno is set.
2315 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2316 uint64_t item_flags,
2318 uint16_t ether_type,
2319 struct rte_flow_error *error)
2322 const struct rte_flow_item_ipv4 *spec = item->spec;
2323 const struct rte_flow_item_ipv4 *last = item->last;
2324 const struct rte_flow_item_ipv4 *mask = item->mask;
2325 rte_be16_t fragment_offset_spec = 0;
2326 rte_be16_t fragment_offset_last = 0;
2327 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2329 .src_addr = RTE_BE32(0xffffffff),
2330 .dst_addr = RTE_BE32(0xffffffff),
2331 .type_of_service = 0xff,
2332 .fragment_offset = RTE_BE16(0xffff),
2333 .next_proto_id = 0xff,
2334 .time_to_live = 0xff,
2338 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2339 ether_type, &nic_ipv4_mask,
2340 MLX5_ITEM_RANGE_ACCEPTED, error);
2344 fragment_offset_spec = spec->hdr.fragment_offset &
2345 mask->hdr.fragment_offset;
2346 if (!fragment_offset_spec)
2349 * spec and mask are valid, enforce using full mask to make sure the
2350 * complete value is used correctly.
2352 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2353 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2354 return rte_flow_error_set(error, EINVAL,
2355 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2356 item, "must use full mask for"
2357 " fragment_offset");
2359 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2360 * indicating this is 1st fragment of fragmented packet.
2361 * This is not yet supported in MLX5, return appropriate error message.
2363 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2364 return rte_flow_error_set(error, ENOTSUP,
2365 RTE_FLOW_ERROR_TYPE_ITEM, item,
2366 "match on first fragment not "
2368 if (fragment_offset_spec && !last)
2369 return rte_flow_error_set(error, ENOTSUP,
2370 RTE_FLOW_ERROR_TYPE_ITEM, item,
2371 "specified value not supported");
2372 /* spec and last are valid, validate the specified range. */
2373 fragment_offset_last = last->hdr.fragment_offset &
2374 mask->hdr.fragment_offset;
2376 * Match on fragment_offset spec 0x2001 and last 0x3fff
2377 * means MF is 1 and frag-offset is > 0.
2378 * This packet is fragment 2nd and onward, excluding last.
2379 * This is not yet supported in MLX5, return appropriate
2382 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2383 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2384 return rte_flow_error_set(error, ENOTSUP,
2385 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2386 last, "match on following "
2387 "fragments not supported");
2389 * Match on fragment_offset spec 0x0001 and last 0x1fff
2390 * means MF is 0 and frag-offset is > 0.
2391 * This packet is last fragment of fragmented packet.
2392 * This is not yet supported in MLX5, return appropriate
2395 if (fragment_offset_spec == RTE_BE16(1) &&
2396 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2397 return rte_flow_error_set(error, ENOTSUP,
2398 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2399 last, "match on last "
2400 "fragment not supported");
2402 * Match on fragment_offset spec 0x0001 and last 0x3fff
2403 * means MF and/or frag-offset is not 0.
2404 * This is a fragmented packet.
2405 * Other range values are invalid and rejected.
2407 if (!(fragment_offset_spec == RTE_BE16(1) &&
2408 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2409 return rte_flow_error_set(error, ENOTSUP,
2410 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2411 "specified range not supported");
2416 * Validate IPV6 fragment extension item.
2419 * Item specification.
2420 * @param[in] item_flags
2421 * Bit-fields that holds the items detected until now.
2423 * Pointer to error structure.
2426 * 0 on success, a negative errno value otherwise and rte_errno is set.
2429 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2430 uint64_t item_flags,
2431 struct rte_flow_error *error)
2433 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2434 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2435 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2436 rte_be16_t frag_data_spec = 0;
2437 rte_be16_t frag_data_last = 0;
2438 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2439 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2440 MLX5_FLOW_LAYER_OUTER_L4;
2442 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2444 .next_header = 0xff,
2445 .frag_data = RTE_BE16(0xffff),
2449 if (item_flags & l4m)
2450 return rte_flow_error_set(error, EINVAL,
2451 RTE_FLOW_ERROR_TYPE_ITEM, item,
2452 "ipv6 fragment extension item cannot "
2454 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2455 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2456 return rte_flow_error_set(error, EINVAL,
2457 RTE_FLOW_ERROR_TYPE_ITEM, item,
2458 "ipv6 fragment extension item must "
2459 "follow ipv6 item");
2461 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2462 if (!frag_data_spec)
2465 * spec and mask are valid, enforce using full mask to make sure the
2466 * complete value is used correctly.
2468 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2469 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2470 return rte_flow_error_set(error, EINVAL,
2471 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2472 item, "must use full mask for"
2475 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2476 * This is 1st fragment of fragmented packet.
2478 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2479 return rte_flow_error_set(error, ENOTSUP,
2480 RTE_FLOW_ERROR_TYPE_ITEM, item,
2481 "match on first fragment not "
2483 if (frag_data_spec && !last)
2484 return rte_flow_error_set(error, EINVAL,
2485 RTE_FLOW_ERROR_TYPE_ITEM, item,
2486 "specified value not supported");
2487 ret = mlx5_flow_item_acceptable
2488 (item, (const uint8_t *)mask,
2489 (const uint8_t *)&nic_mask,
2490 sizeof(struct rte_flow_item_ipv6_frag_ext),
2491 MLX5_ITEM_RANGE_ACCEPTED, error);
2494 /* spec and last are valid, validate the specified range. */
2495 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2497 * Match on frag_data spec 0x0009 and last 0xfff9
2498 * means M is 1 and frag-offset is > 0.
2499 * This packet is fragment 2nd and onward, excluding last.
2500 * This is not yet supported in MLX5, return appropriate
2503 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2504 RTE_IPV6_EHDR_MF_MASK) &&
2505 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2506 return rte_flow_error_set(error, ENOTSUP,
2507 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2508 last, "match on following "
2509 "fragments not supported");
2511 * Match on frag_data spec 0x0008 and last 0xfff8
2512 * means M is 0 and frag-offset is > 0.
2513 * This packet is last fragment of fragmented packet.
2514 * This is not yet supported in MLX5, return appropriate
2517 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2518 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2519 return rte_flow_error_set(error, ENOTSUP,
2520 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2521 last, "match on last "
2522 "fragment not supported");
2523 /* Other range values are invalid and rejected. */
2524 return rte_flow_error_set(error, EINVAL,
2525 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2526 "specified range not supported");
2530 * Validate the pop VLAN action.
2533 * Pointer to the rte_eth_dev structure.
2534 * @param[in] action_flags
2535 * Holds the actions detected until now.
2537 * Pointer to the pop vlan action.
2538 * @param[in] item_flags
2539 * The items found in this flow rule.
2541 * Pointer to flow attributes.
2543 * Pointer to error structure.
2546 * 0 on success, a negative errno value otherwise and rte_errno is set.
2549 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2550 uint64_t action_flags,
2551 const struct rte_flow_action *action,
2552 uint64_t item_flags,
2553 const struct rte_flow_attr *attr,
2554 struct rte_flow_error *error)
2556 const struct mlx5_priv *priv = dev->data->dev_private;
2560 if (!priv->sh->pop_vlan_action)
2561 return rte_flow_error_set(error, ENOTSUP,
2562 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2564 "pop vlan action is not supported");
2566 return rte_flow_error_set(error, ENOTSUP,
2567 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2569 "pop vlan action not supported for "
2571 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2572 return rte_flow_error_set(error, ENOTSUP,
2573 RTE_FLOW_ERROR_TYPE_ACTION, action,
2574 "no support for multiple VLAN "
2576 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2577 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2578 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2579 return rte_flow_error_set(error, ENOTSUP,
2580 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2582 "cannot pop vlan after decap without "
2583 "match on inner vlan in the flow");
2584 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2585 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2586 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2587 return rte_flow_error_set(error, ENOTSUP,
2588 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2590 "cannot pop vlan without a "
2591 "match on (outer) vlan in the flow");
2592 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2593 return rte_flow_error_set(error, EINVAL,
2594 RTE_FLOW_ERROR_TYPE_ACTION, action,
2595 "wrong action order, port_id should "
2596 "be after pop VLAN action");
2597 if (!attr->transfer && priv->representor)
2598 return rte_flow_error_set(error, ENOTSUP,
2599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2600 "pop vlan action for VF representor "
2601 "not supported on NIC table");
2606 * Get VLAN default info from vlan match info.
2609 * the list of item specifications.
2611 * pointer VLAN info to fill to.
2614 * 0 on success, a negative errno value otherwise and rte_errno is set.
2617 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2618 struct rte_vlan_hdr *vlan)
2620 const struct rte_flow_item_vlan nic_mask = {
2621 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2622 MLX5DV_FLOW_VLAN_VID_MASK),
2623 .inner_type = RTE_BE16(0xffff),
2628 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2629 int type = items->type;
2631 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2632 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2635 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2636 const struct rte_flow_item_vlan *vlan_m = items->mask;
2637 const struct rte_flow_item_vlan *vlan_v = items->spec;
2639 /* If VLAN item in pattern doesn't contain data, return here. */
2644 /* Only full match values are accepted */
2645 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2646 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2647 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2649 rte_be_to_cpu_16(vlan_v->tci &
2650 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2652 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2653 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2654 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2656 rte_be_to_cpu_16(vlan_v->tci &
2657 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2659 if (vlan_m->inner_type == nic_mask.inner_type)
2660 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2661 vlan_m->inner_type);
2666 * Validate the push VLAN action.
2669 * Pointer to the rte_eth_dev structure.
2670 * @param[in] action_flags
2671 * Holds the actions detected until now.
2672 * @param[in] item_flags
2673 * The items found in this flow rule.
2675 * Pointer to the action structure.
2677 * Pointer to flow attributes
2679 * Pointer to error structure.
2682 * 0 on success, a negative errno value otherwise and rte_errno is set.
2685 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2686 uint64_t action_flags,
2687 const struct rte_flow_item_vlan *vlan_m,
2688 const struct rte_flow_action *action,
2689 const struct rte_flow_attr *attr,
2690 struct rte_flow_error *error)
2692 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2693 const struct mlx5_priv *priv = dev->data->dev_private;
2695 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2696 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2697 return rte_flow_error_set(error, EINVAL,
2698 RTE_FLOW_ERROR_TYPE_ACTION, action,
2699 "invalid vlan ethertype");
2700 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2701 return rte_flow_error_set(error, EINVAL,
2702 RTE_FLOW_ERROR_TYPE_ACTION, action,
2703 "wrong action order, port_id should "
2704 "be after push VLAN");
2705 if (!attr->transfer && priv->representor)
2706 return rte_flow_error_set(error, ENOTSUP,
2707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2708 "push vlan action for VF representor "
2709 "not supported on NIC table");
2711 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2712 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2713 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2714 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2715 !(mlx5_flow_find_action
2716 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2717 return rte_flow_error_set(error, EINVAL,
2718 RTE_FLOW_ERROR_TYPE_ACTION, action,
2719 "not full match mask on VLAN PCP and "
2720 "there is no of_set_vlan_pcp action, "
2721 "push VLAN action cannot figure out "
2724 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2725 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2726 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2727 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2728 !(mlx5_flow_find_action
2729 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2730 return rte_flow_error_set(error, EINVAL,
2731 RTE_FLOW_ERROR_TYPE_ACTION, action,
2732 "not full match mask on VLAN VID and "
2733 "there is no of_set_vlan_vid action, "
2734 "push VLAN action cannot figure out "
2741 * Validate the set VLAN PCP.
2743 * @param[in] action_flags
2744 * Holds the actions detected until now.
2745 * @param[in] actions
2746 * Pointer to the list of actions remaining in the flow rule.
2748 * Pointer to error structure.
2751 * 0 on success, a negative errno value otherwise and rte_errno is set.
2754 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2755 const struct rte_flow_action actions[],
2756 struct rte_flow_error *error)
2758 const struct rte_flow_action *action = actions;
2759 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2761 if (conf->vlan_pcp > 7)
2762 return rte_flow_error_set(error, EINVAL,
2763 RTE_FLOW_ERROR_TYPE_ACTION, action,
2764 "VLAN PCP value is too big");
2765 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2766 return rte_flow_error_set(error, ENOTSUP,
2767 RTE_FLOW_ERROR_TYPE_ACTION, action,
2768 "set VLAN PCP action must follow "
2769 "the push VLAN action");
2770 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2771 return rte_flow_error_set(error, ENOTSUP,
2772 RTE_FLOW_ERROR_TYPE_ACTION, action,
2773 "Multiple VLAN PCP modification are "
2775 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2776 return rte_flow_error_set(error, EINVAL,
2777 RTE_FLOW_ERROR_TYPE_ACTION, action,
2778 "wrong action order, port_id should "
2779 "be after set VLAN PCP");
2784 * Validate the set VLAN VID.
2786 * @param[in] item_flags
2787 * Holds the items detected in this rule.
2788 * @param[in] action_flags
2789 * Holds the actions detected until now.
2790 * @param[in] actions
2791 * Pointer to the list of actions remaining in the flow rule.
2793 * Pointer to error structure.
2796 * 0 on success, a negative errno value otherwise and rte_errno is set.
2799 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2800 uint64_t action_flags,
2801 const struct rte_flow_action actions[],
2802 struct rte_flow_error *error)
2804 const struct rte_flow_action *action = actions;
2805 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2807 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2808 return rte_flow_error_set(error, EINVAL,
2809 RTE_FLOW_ERROR_TYPE_ACTION, action,
2810 "VLAN VID value is too big");
2811 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2812 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2813 return rte_flow_error_set(error, ENOTSUP,
2814 RTE_FLOW_ERROR_TYPE_ACTION, action,
2815 "set VLAN VID action must follow push"
2816 " VLAN action or match on VLAN item");
2817 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2818 return rte_flow_error_set(error, ENOTSUP,
2819 RTE_FLOW_ERROR_TYPE_ACTION, action,
2820 "Multiple VLAN VID modifications are "
2822 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2823 return rte_flow_error_set(error, EINVAL,
2824 RTE_FLOW_ERROR_TYPE_ACTION, action,
2825 "wrong action order, port_id should "
2826 "be after set VLAN VID");
2831 * Validate the FLAG action.
2834 * Pointer to the rte_eth_dev structure.
2835 * @param[in] action_flags
2836 * Holds the actions detected until now.
2838 * Pointer to flow attributes
2840 * Pointer to error structure.
2843 * 0 on success, a negative errno value otherwise and rte_errno is set.
2846 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2847 uint64_t action_flags,
2848 const struct rte_flow_attr *attr,
2849 struct rte_flow_error *error)
2851 struct mlx5_priv *priv = dev->data->dev_private;
2852 struct mlx5_dev_config *config = &priv->config;
2855 /* Fall back if no extended metadata register support. */
2856 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2857 return mlx5_flow_validate_action_flag(action_flags, attr,
2859 /* Extensive metadata mode requires registers. */
2860 if (!mlx5_flow_ext_mreg_supported(dev))
2861 return rte_flow_error_set(error, ENOTSUP,
2862 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2863 "no metadata registers "
2864 "to support flag action");
2865 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2866 return rte_flow_error_set(error, ENOTSUP,
2867 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2868 "extended metadata register"
2869 " isn't available");
2870 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2873 MLX5_ASSERT(ret > 0);
2874 if (action_flags & MLX5_FLOW_ACTION_MARK)
2875 return rte_flow_error_set(error, EINVAL,
2876 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2877 "can't mark and flag in same flow");
2878 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2879 return rte_flow_error_set(error, EINVAL,
2880 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2882 " actions in same flow");
2887 * Validate MARK action.
2890 * Pointer to the rte_eth_dev structure.
2892 * Pointer to action.
2893 * @param[in] action_flags
2894 * Holds the actions detected until now.
2896 * Pointer to flow attributes
2898 * Pointer to error structure.
2901 * 0 on success, a negative errno value otherwise and rte_errno is set.
2904 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2905 const struct rte_flow_action *action,
2906 uint64_t action_flags,
2907 const struct rte_flow_attr *attr,
2908 struct rte_flow_error *error)
2910 struct mlx5_priv *priv = dev->data->dev_private;
2911 struct mlx5_dev_config *config = &priv->config;
2912 const struct rte_flow_action_mark *mark = action->conf;
2915 if (is_tunnel_offload_active(dev))
2916 return rte_flow_error_set(error, ENOTSUP,
2917 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2919 "if tunnel offload active");
2920 /* Fall back if no extended metadata register support. */
2921 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2922 return mlx5_flow_validate_action_mark(action, action_flags,
2924 /* Extensive metadata mode requires registers. */
2925 if (!mlx5_flow_ext_mreg_supported(dev))
2926 return rte_flow_error_set(error, ENOTSUP,
2927 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2928 "no metadata registers "
2929 "to support mark action");
2930 if (!priv->sh->dv_mark_mask)
2931 return rte_flow_error_set(error, ENOTSUP,
2932 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933 "extended metadata register"
2934 " isn't available");
2935 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2938 MLX5_ASSERT(ret > 0);
2940 return rte_flow_error_set(error, EINVAL,
2941 RTE_FLOW_ERROR_TYPE_ACTION, action,
2942 "configuration cannot be null");
2943 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2944 return rte_flow_error_set(error, EINVAL,
2945 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2947 "mark id exceeds the limit");
2948 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949 return rte_flow_error_set(error, EINVAL,
2950 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2951 "can't flag and mark in same flow");
2952 if (action_flags & MLX5_FLOW_ACTION_MARK)
2953 return rte_flow_error_set(error, EINVAL,
2954 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2955 "can't have 2 mark actions in same"
2961 * Validate SET_META action.
2964 * Pointer to the rte_eth_dev structure.
2966 * Pointer to the action structure.
2967 * @param[in] action_flags
2968 * Holds the actions detected until now.
2970 * Pointer to flow attributes
2972 * Pointer to error structure.
2975 * 0 on success, a negative errno value otherwise and rte_errno is set.
2978 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2979 const struct rte_flow_action *action,
2980 uint64_t action_flags __rte_unused,
2981 const struct rte_flow_attr *attr,
2982 struct rte_flow_error *error)
2984 const struct rte_flow_action_set_meta *conf;
2985 uint32_t nic_mask = UINT32_MAX;
2988 if (!mlx5_flow_ext_mreg_supported(dev))
2989 return rte_flow_error_set(error, ENOTSUP,
2990 RTE_FLOW_ERROR_TYPE_ACTION, action,
2991 "extended metadata register"
2992 " isn't supported");
2993 reg = flow_dv_get_metadata_reg(dev, attr, error);
2997 return rte_flow_error_set(error, ENOTSUP,
2998 RTE_FLOW_ERROR_TYPE_ACTION, action,
2999 "unavalable extended metadata register");
3000 if (reg != REG_A && reg != REG_B) {
3001 struct mlx5_priv *priv = dev->data->dev_private;
3003 nic_mask = priv->sh->dv_meta_mask;
3005 if (!(action->conf))
3006 return rte_flow_error_set(error, EINVAL,
3007 RTE_FLOW_ERROR_TYPE_ACTION, action,
3008 "configuration cannot be null");
3009 conf = (const struct rte_flow_action_set_meta *)action->conf;
3011 return rte_flow_error_set(error, EINVAL,
3012 RTE_FLOW_ERROR_TYPE_ACTION, action,
3013 "zero mask doesn't have any effect");
3014 if (conf->mask & ~nic_mask)
3015 return rte_flow_error_set(error, EINVAL,
3016 RTE_FLOW_ERROR_TYPE_ACTION, action,
3017 "meta data must be within reg C0");
3022 * Validate SET_TAG action.
3025 * Pointer to the rte_eth_dev structure.
3027 * Pointer to the action structure.
3028 * @param[in] action_flags
3029 * Holds the actions detected until now.
3031 * Pointer to flow attributes
3033 * Pointer to error structure.
3036 * 0 on success, a negative errno value otherwise and rte_errno is set.
3039 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3040 const struct rte_flow_action *action,
3041 uint64_t action_flags,
3042 const struct rte_flow_attr *attr,
3043 struct rte_flow_error *error)
3045 const struct rte_flow_action_set_tag *conf;
3046 const uint64_t terminal_action_flags =
3047 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3048 MLX5_FLOW_ACTION_RSS;
3051 if (!mlx5_flow_ext_mreg_supported(dev))
3052 return rte_flow_error_set(error, ENOTSUP,
3053 RTE_FLOW_ERROR_TYPE_ACTION, action,
3054 "extensive metadata register"
3055 " isn't supported");
3056 if (!(action->conf))
3057 return rte_flow_error_set(error, EINVAL,
3058 RTE_FLOW_ERROR_TYPE_ACTION, action,
3059 "configuration cannot be null");
3060 conf = (const struct rte_flow_action_set_tag *)action->conf;
3062 return rte_flow_error_set(error, EINVAL,
3063 RTE_FLOW_ERROR_TYPE_ACTION, action,
3064 "zero mask doesn't have any effect");
3065 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3068 if (!attr->transfer && attr->ingress &&
3069 (action_flags & terminal_action_flags))
3070 return rte_flow_error_set(error, EINVAL,
3071 RTE_FLOW_ERROR_TYPE_ACTION, action,
3072 "set_tag has no effect"
3073 " with terminal actions");
3078 * Validate count action.
3081 * Pointer to rte_eth_dev structure.
3083 * Pointer to the action structure.
3084 * @param[in] action_flags
3085 * Holds the actions detected until now.
3087 * Pointer to error structure.
3090 * 0 on success, a negative errno value otherwise and rte_errno is set.
3093 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3094 const struct rte_flow_action *action,
3095 uint64_t action_flags,
3096 struct rte_flow_error *error)
3098 struct mlx5_priv *priv = dev->data->dev_private;
3099 const struct rte_flow_action_count *count;
3101 if (!priv->config.devx)
3103 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3104 return rte_flow_error_set(error, EINVAL,
3105 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3106 "duplicate count actions set");
3107 count = (const struct rte_flow_action_count *)action->conf;
3108 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3109 !priv->sh->flow_hit_aso_en)
3110 return rte_flow_error_set(error, EINVAL,
3111 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3112 "old age and shared count combination is not supported");
3113 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3117 return rte_flow_error_set
3119 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3121 "count action not supported");
3125 * Validate the L2 encap action.
3128 * Pointer to the rte_eth_dev structure.
3129 * @param[in] action_flags
3130 * Holds the actions detected until now.
3132 * Pointer to the action structure.
3134 * Pointer to flow attributes.
3136 * Pointer to error structure.
3139 * 0 on success, a negative errno value otherwise and rte_errno is set.
3142 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3143 uint64_t action_flags,
3144 const struct rte_flow_action *action,
3145 const struct rte_flow_attr *attr,
3146 struct rte_flow_error *error)
3148 const struct mlx5_priv *priv = dev->data->dev_private;
3150 if (!(action->conf))
3151 return rte_flow_error_set(error, EINVAL,
3152 RTE_FLOW_ERROR_TYPE_ACTION, action,
3153 "configuration cannot be null");
3154 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "can only have a single encap action "
3159 if (!attr->transfer && priv->representor)
3160 return rte_flow_error_set(error, ENOTSUP,
3161 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3162 "encap action for VF representor "
3163 "not supported on NIC table");
3168 * Validate a decap action.
3171 * Pointer to the rte_eth_dev structure.
3172 * @param[in] action_flags
3173 * Holds the actions detected until now.
3175 * Pointer to the action structure.
3176 * @param[in] item_flags
3177 * Holds the items detected.
3179 * Pointer to flow attributes
3181 * Pointer to error structure.
3184 * 0 on success, a negative errno value otherwise and rte_errno is set.
3187 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3188 uint64_t action_flags,
3189 const struct rte_flow_action *action,
3190 const uint64_t item_flags,
3191 const struct rte_flow_attr *attr,
3192 struct rte_flow_error *error)
3194 const struct mlx5_priv *priv = dev->data->dev_private;
3196 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3197 !priv->config.decap_en)
3198 return rte_flow_error_set(error, ENOTSUP,
3199 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3200 "decap is not enabled");
3201 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3202 return rte_flow_error_set(error, ENOTSUP,
3203 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3205 MLX5_FLOW_ACTION_DECAP ? "can only "
3206 "have a single decap action" : "decap "
3207 "after encap is not supported");
3208 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3209 return rte_flow_error_set(error, EINVAL,
3210 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211 "can't have decap action after"
3214 return rte_flow_error_set(error, ENOTSUP,
3215 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3217 "decap action not supported for "
3219 if (!attr->transfer && priv->representor)
3220 return rte_flow_error_set(error, ENOTSUP,
3221 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3222 "decap action for VF representor "
3223 "not supported on NIC table");
3224 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3225 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3226 return rte_flow_error_set(error, ENOTSUP,
3227 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3228 "VXLAN item should be present for VXLAN decap");
3232 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3235 * Validate the raw encap and decap actions.
3238 * Pointer to the rte_eth_dev structure.
3240 * Pointer to the decap action.
3242 * Pointer to the encap action.
3244 * Pointer to flow attributes
3245 * @param[in/out] action_flags
3246 * Holds the actions detected until now.
3247 * @param[out] actions_n
3248 * pointer to the number of actions counter.
3250 * Pointer to the action structure.
3251 * @param[in] item_flags
3252 * Holds the items detected.
3254 * Pointer to error structure.
3257 * 0 on success, a negative errno value otherwise and rte_errno is set.
3260 flow_dv_validate_action_raw_encap_decap
3261 (struct rte_eth_dev *dev,
3262 const struct rte_flow_action_raw_decap *decap,
3263 const struct rte_flow_action_raw_encap *encap,
3264 const struct rte_flow_attr *attr, uint64_t *action_flags,
3265 int *actions_n, const struct rte_flow_action *action,
3266 uint64_t item_flags, struct rte_flow_error *error)
3268 const struct mlx5_priv *priv = dev->data->dev_private;
3271 if (encap && (!encap->size || !encap->data))
3272 return rte_flow_error_set(error, EINVAL,
3273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3274 "raw encap data cannot be empty");
3275 if (decap && encap) {
3276 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3277 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3280 else if (encap->size <=
3281 MLX5_ENCAPSULATION_DECISION_SIZE &&
3283 MLX5_ENCAPSULATION_DECISION_SIZE)
3286 else if (encap->size >
3287 MLX5_ENCAPSULATION_DECISION_SIZE &&
3289 MLX5_ENCAPSULATION_DECISION_SIZE)
3290 /* 2 L2 actions: encap and decap. */
3293 return rte_flow_error_set(error,
3295 RTE_FLOW_ERROR_TYPE_ACTION,
3296 NULL, "unsupported too small "
3297 "raw decap and too small raw "
3298 "encap combination");
3301 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3302 item_flags, attr, error);
3305 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3309 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3310 return rte_flow_error_set(error, ENOTSUP,
3311 RTE_FLOW_ERROR_TYPE_ACTION,
3313 "small raw encap size");
3314 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3315 return rte_flow_error_set(error, EINVAL,
3316 RTE_FLOW_ERROR_TYPE_ACTION,
3318 "more than one encap action");
3319 if (!attr->transfer && priv->representor)
3320 return rte_flow_error_set
3322 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3323 "encap action for VF representor "
3324 "not supported on NIC table");
3325 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3332 * Match encap_decap resource.
3335 * Pointer to the hash list.
3337 * Pointer to exist resource entry object.
3339 * Key of the new entry.
3341 * Pointer to new encap_decap resource.
3344 * 0 on matching, none-zero otherwise.
3347 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3348 struct mlx5_hlist_entry *entry,
3349 uint64_t key __rte_unused, void *cb_ctx)
3351 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3352 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3353 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3355 cache_resource = container_of(entry,
3356 struct mlx5_flow_dv_encap_decap_resource,
3358 if (resource->reformat_type == cache_resource->reformat_type &&
3359 resource->ft_type == cache_resource->ft_type &&
3360 resource->flags == cache_resource->flags &&
3361 resource->size == cache_resource->size &&
3362 !memcmp((const void *)resource->buf,
3363 (const void *)cache_resource->buf,
3370 * Allocate encap_decap resource.
3373 * Pointer to the hash list.
3375 * Pointer to exist resource entry object.
3377 * Pointer to new encap_decap resource.
3380 * 0 on matching, none-zero otherwise.
3382 struct mlx5_hlist_entry *
3383 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3384 uint64_t key __rte_unused,
3387 struct mlx5_dev_ctx_shared *sh = list->ctx;
3388 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3389 struct mlx5dv_dr_domain *domain;
3390 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3391 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3395 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3396 domain = sh->fdb_domain;
3397 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3398 domain = sh->rx_domain;
3400 domain = sh->tx_domain;
3401 /* Register new encap/decap resource. */
3402 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3404 if (!cache_resource) {
3405 rte_flow_error_set(ctx->error, ENOMEM,
3406 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3407 "cannot allocate resource memory");
3410 *cache_resource = *resource;
3411 cache_resource->idx = idx;
3412 ret = mlx5_flow_os_create_flow_action_packet_reformat
3413 (sh->ctx, domain, cache_resource,
3414 &cache_resource->action);
3416 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3417 rte_flow_error_set(ctx->error, ENOMEM,
3418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3419 NULL, "cannot create action");
3423 return &cache_resource->entry;
3427 * Find existing encap/decap resource or create and register a new one.
3429 * @param[in, out] dev
3430 * Pointer to rte_eth_dev structure.
3431 * @param[in, out] resource
3432 * Pointer to encap/decap resource.
3433 * @parm[in, out] dev_flow
3434 * Pointer to the dev_flow.
3436 * pointer to error structure.
3439 * 0 on success otherwise -errno and errno is set.
3442 flow_dv_encap_decap_resource_register
3443 (struct rte_eth_dev *dev,
3444 struct mlx5_flow_dv_encap_decap_resource *resource,
3445 struct mlx5_flow *dev_flow,
3446 struct rte_flow_error *error)
3448 struct mlx5_priv *priv = dev->data->dev_private;
3449 struct mlx5_dev_ctx_shared *sh = priv->sh;
3450 struct mlx5_hlist_entry *entry;
3454 uint32_t refmt_type:8;
3456 * Header reformat actions can be shared between
3457 * non-root tables. One bit to indicate non-root
3461 uint32_t reserve:15;
3464 } encap_decap_key = {
3466 .ft_type = resource->ft_type,
3467 .refmt_type = resource->reformat_type,
3468 .is_root = !!dev_flow->dv.group,
3472 struct mlx5_flow_cb_ctx ctx = {
3478 resource->flags = dev_flow->dv.group ? 0 : 1;
3479 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3480 sizeof(encap_decap_key.v32), 0);
3481 if (resource->reformat_type !=
3482 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3484 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3485 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3488 resource = container_of(entry, typeof(*resource), entry);
3489 dev_flow->dv.encap_decap = resource;
3490 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3495 * Find existing table jump resource or create and register a new one.
3497 * @param[in, out] dev
3498 * Pointer to rte_eth_dev structure.
3499 * @param[in, out] tbl
3500 * Pointer to flow table resource.
3501 * @parm[in, out] dev_flow
3502 * Pointer to the dev_flow.
3504 * pointer to error structure.
3507 * 0 on success otherwise -errno and errno is set.
3510 flow_dv_jump_tbl_resource_register
3511 (struct rte_eth_dev *dev __rte_unused,
3512 struct mlx5_flow_tbl_resource *tbl,
3513 struct mlx5_flow *dev_flow,
3514 struct rte_flow_error *error __rte_unused)
3516 struct mlx5_flow_tbl_data_entry *tbl_data =
3517 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3520 MLX5_ASSERT(tbl_data->jump.action);
3521 dev_flow->handle->rix_jump = tbl_data->idx;
3522 dev_flow->dv.jump = &tbl_data->jump;
3527 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3528 struct mlx5_cache_entry *entry, void *cb_ctx)
3530 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3531 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3532 struct mlx5_flow_dv_port_id_action_resource *res =
3533 container_of(entry, typeof(*res), entry);
3535 return ref->port_id != res->port_id;
3538 struct mlx5_cache_entry *
3539 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3540 struct mlx5_cache_entry *entry __rte_unused,
3543 struct mlx5_dev_ctx_shared *sh = list->ctx;
3544 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3545 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3546 struct mlx5_flow_dv_port_id_action_resource *cache;
3550 /* Register new port id action resource. */
3551 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3553 rte_flow_error_set(ctx->error, ENOMEM,
3554 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3555 "cannot allocate port_id action cache memory");
3559 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3563 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3564 rte_flow_error_set(ctx->error, ENOMEM,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566 "cannot create action");
3570 return &cache->entry;
3574 * Find existing table port ID resource or create and register a new one.
3576 * @param[in, out] dev
3577 * Pointer to rte_eth_dev structure.
3578 * @param[in, out] resource
3579 * Pointer to port ID action resource.
3580 * @parm[in, out] dev_flow
3581 * Pointer to the dev_flow.
3583 * pointer to error structure.
3586 * 0 on success otherwise -errno and errno is set.
3589 flow_dv_port_id_action_resource_register
3590 (struct rte_eth_dev *dev,
3591 struct mlx5_flow_dv_port_id_action_resource *resource,
3592 struct mlx5_flow *dev_flow,
3593 struct rte_flow_error *error)
3595 struct mlx5_priv *priv = dev->data->dev_private;
3596 struct mlx5_cache_entry *entry;
3597 struct mlx5_flow_dv_port_id_action_resource *cache;
3598 struct mlx5_flow_cb_ctx ctx = {
3603 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3606 cache = container_of(entry, typeof(*cache), entry);
3607 dev_flow->dv.port_id_action = cache;
3608 dev_flow->handle->rix_port_id_action = cache->idx;
3613 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3614 struct mlx5_cache_entry *entry, void *cb_ctx)
3616 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3617 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3618 struct mlx5_flow_dv_push_vlan_action_resource *res =
3619 container_of(entry, typeof(*res), entry);
3621 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3624 struct mlx5_cache_entry *
3625 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3626 struct mlx5_cache_entry *entry __rte_unused,
3629 struct mlx5_dev_ctx_shared *sh = list->ctx;
3630 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3631 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3632 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3633 struct mlx5dv_dr_domain *domain;
3637 /* Register new port id action resource. */
3638 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3640 rte_flow_error_set(ctx->error, ENOMEM,
3641 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3642 "cannot allocate push_vlan action cache memory");
3646 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3647 domain = sh->fdb_domain;
3648 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3649 domain = sh->rx_domain;
3651 domain = sh->tx_domain;
3652 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3655 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3656 rte_flow_error_set(ctx->error, ENOMEM,
3657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3658 "cannot create push vlan action");
3662 return &cache->entry;
3666 * Find existing push vlan resource or create and register a new one.
3668 * @param [in, out] dev
3669 * Pointer to rte_eth_dev structure.
3670 * @param[in, out] resource
3671 * Pointer to port ID action resource.
3672 * @parm[in, out] dev_flow
3673 * Pointer to the dev_flow.
3675 * pointer to error structure.
3678 * 0 on success otherwise -errno and errno is set.
3681 flow_dv_push_vlan_action_resource_register
3682 (struct rte_eth_dev *dev,
3683 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3684 struct mlx5_flow *dev_flow,
3685 struct rte_flow_error *error)
3687 struct mlx5_priv *priv = dev->data->dev_private;
3688 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3689 struct mlx5_cache_entry *entry;
3690 struct mlx5_flow_cb_ctx ctx = {
3695 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3698 cache = container_of(entry, typeof(*cache), entry);
3700 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3701 dev_flow->dv.push_vlan_res = cache;
3706 * Get the size of specific rte_flow_item_type hdr size
3708 * @param[in] item_type
3709 * Tested rte_flow_item_type.
3712 * sizeof struct item_type, 0 if void or irrelevant.
3715 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3719 switch (item_type) {
3720 case RTE_FLOW_ITEM_TYPE_ETH:
3721 retval = sizeof(struct rte_ether_hdr);
3723 case RTE_FLOW_ITEM_TYPE_VLAN:
3724 retval = sizeof(struct rte_vlan_hdr);
3726 case RTE_FLOW_ITEM_TYPE_IPV4:
3727 retval = sizeof(struct rte_ipv4_hdr);
3729 case RTE_FLOW_ITEM_TYPE_IPV6:
3730 retval = sizeof(struct rte_ipv6_hdr);
3732 case RTE_FLOW_ITEM_TYPE_UDP:
3733 retval = sizeof(struct rte_udp_hdr);
3735 case RTE_FLOW_ITEM_TYPE_TCP:
3736 retval = sizeof(struct rte_tcp_hdr);
3738 case RTE_FLOW_ITEM_TYPE_VXLAN:
3739 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3740 retval = sizeof(struct rte_vxlan_hdr);
3742 case RTE_FLOW_ITEM_TYPE_GRE:
3743 case RTE_FLOW_ITEM_TYPE_NVGRE:
3744 retval = sizeof(struct rte_gre_hdr);
3746 case RTE_FLOW_ITEM_TYPE_MPLS:
3747 retval = sizeof(struct rte_mpls_hdr);
3749 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3757 #define MLX5_ENCAP_IPV4_VERSION 0x40
3758 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3759 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3760 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3761 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3762 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3763 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3766 * Convert the encap action data from list of rte_flow_item to raw buffer
3769 * Pointer to rte_flow_item objects list.
3771 * Pointer to the output buffer.
3773 * Pointer to the output buffer size.
3775 * Pointer to the error structure.
3778 * 0 on success, a negative errno value otherwise and rte_errno is set.
3781 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3782 size_t *size, struct rte_flow_error *error)
3784 struct rte_ether_hdr *eth = NULL;
3785 struct rte_vlan_hdr *vlan = NULL;
3786 struct rte_ipv4_hdr *ipv4 = NULL;
3787 struct rte_ipv6_hdr *ipv6 = NULL;
3788 struct rte_udp_hdr *udp = NULL;
3789 struct rte_vxlan_hdr *vxlan = NULL;
3790 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3791 struct rte_gre_hdr *gre = NULL;
3793 size_t temp_size = 0;
3796 return rte_flow_error_set(error, EINVAL,
3797 RTE_FLOW_ERROR_TYPE_ACTION,
3798 NULL, "invalid empty data");
3799 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3800 len = flow_dv_get_item_hdr_len(items->type);
3801 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3802 return rte_flow_error_set(error, EINVAL,
3803 RTE_FLOW_ERROR_TYPE_ACTION,
3804 (void *)items->type,
3805 "items total size is too big"
3806 " for encap action");
3807 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3808 switch (items->type) {
3809 case RTE_FLOW_ITEM_TYPE_ETH:
3810 eth = (struct rte_ether_hdr *)&buf[temp_size];
3812 case RTE_FLOW_ITEM_TYPE_VLAN:
3813 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3815 return rte_flow_error_set(error, EINVAL,
3816 RTE_FLOW_ERROR_TYPE_ACTION,
3817 (void *)items->type,
3818 "eth header not found");
3819 if (!eth->ether_type)
3820 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3822 case RTE_FLOW_ITEM_TYPE_IPV4:
3823 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3825 return rte_flow_error_set(error, EINVAL,
3826 RTE_FLOW_ERROR_TYPE_ACTION,
3827 (void *)items->type,
3828 "neither eth nor vlan"
3830 if (vlan && !vlan->eth_proto)
3831 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3832 else if (eth && !eth->ether_type)
3833 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3834 if (!ipv4->version_ihl)
3835 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3836 MLX5_ENCAP_IPV4_IHL_MIN;
3837 if (!ipv4->time_to_live)
3838 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3840 case RTE_FLOW_ITEM_TYPE_IPV6:
3841 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3843 return rte_flow_error_set(error, EINVAL,
3844 RTE_FLOW_ERROR_TYPE_ACTION,
3845 (void *)items->type,
3846 "neither eth nor vlan"
3848 if (vlan && !vlan->eth_proto)
3849 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3850 else if (eth && !eth->ether_type)
3851 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3852 if (!ipv6->vtc_flow)
3854 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3855 if (!ipv6->hop_limits)
3856 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3858 case RTE_FLOW_ITEM_TYPE_UDP:
3859 udp = (struct rte_udp_hdr *)&buf[temp_size];
3861 return rte_flow_error_set(error, EINVAL,
3862 RTE_FLOW_ERROR_TYPE_ACTION,
3863 (void *)items->type,
3864 "ip header not found");
3865 if (ipv4 && !ipv4->next_proto_id)
3866 ipv4->next_proto_id = IPPROTO_UDP;
3867 else if (ipv6 && !ipv6->proto)
3868 ipv6->proto = IPPROTO_UDP;
3870 case RTE_FLOW_ITEM_TYPE_VXLAN:
3871 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3873 return rte_flow_error_set(error, EINVAL,
3874 RTE_FLOW_ERROR_TYPE_ACTION,
3875 (void *)items->type,
3876 "udp header not found");
3878 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3879 if (!vxlan->vx_flags)
3881 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3883 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3884 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3886 return rte_flow_error_set(error, EINVAL,
3887 RTE_FLOW_ERROR_TYPE_ACTION,
3888 (void *)items->type,
3889 "udp header not found");
3890 if (!vxlan_gpe->proto)
3891 return rte_flow_error_set(error, EINVAL,
3892 RTE_FLOW_ERROR_TYPE_ACTION,
3893 (void *)items->type,
3894 "next protocol not found");
3897 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3898 if (!vxlan_gpe->vx_flags)
3899 vxlan_gpe->vx_flags =
3900 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3902 case RTE_FLOW_ITEM_TYPE_GRE:
3903 case RTE_FLOW_ITEM_TYPE_NVGRE:
3904 gre = (struct rte_gre_hdr *)&buf[temp_size];
3906 return rte_flow_error_set(error, EINVAL,
3907 RTE_FLOW_ERROR_TYPE_ACTION,
3908 (void *)items->type,
3909 "next protocol not found");
3911 return rte_flow_error_set(error, EINVAL,
3912 RTE_FLOW_ERROR_TYPE_ACTION,
3913 (void *)items->type,
3914 "ip header not found");
3915 if (ipv4 && !ipv4->next_proto_id)
3916 ipv4->next_proto_id = IPPROTO_GRE;
3917 else if (ipv6 && !ipv6->proto)
3918 ipv6->proto = IPPROTO_GRE;
3920 case RTE_FLOW_ITEM_TYPE_VOID:
3923 return rte_flow_error_set(error, EINVAL,
3924 RTE_FLOW_ERROR_TYPE_ACTION,
3925 (void *)items->type,
3926 "unsupported item type");
3936 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3938 struct rte_ether_hdr *eth = NULL;
3939 struct rte_vlan_hdr *vlan = NULL;
3940 struct rte_ipv6_hdr *ipv6 = NULL;
3941 struct rte_udp_hdr *udp = NULL;
3945 eth = (struct rte_ether_hdr *)data;
3946 next_hdr = (char *)(eth + 1);
3947 proto = RTE_BE16(eth->ether_type);
3950 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3951 vlan = (struct rte_vlan_hdr *)next_hdr;
3952 proto = RTE_BE16(vlan->eth_proto);
3953 next_hdr += sizeof(struct rte_vlan_hdr);
3956 /* HW calculates IPv4 csum. no need to proceed */
3957 if (proto == RTE_ETHER_TYPE_IPV4)
3960 /* non IPv4/IPv6 header. not supported */
3961 if (proto != RTE_ETHER_TYPE_IPV6) {
3962 return rte_flow_error_set(error, ENOTSUP,
3963 RTE_FLOW_ERROR_TYPE_ACTION,
3964 NULL, "Cannot offload non IPv4/IPv6");
3967 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3969 /* ignore non UDP */
3970 if (ipv6->proto != IPPROTO_UDP)
3973 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3974 udp->dgram_cksum = 0;
3980 * Convert L2 encap action to DV specification.
3983 * Pointer to rte_eth_dev structure.
3985 * Pointer to action structure.
3986 * @param[in, out] dev_flow
3987 * Pointer to the mlx5_flow.
3988 * @param[in] transfer
3989 * Mark if the flow is E-Switch flow.
3991 * Pointer to the error structure.
3994 * 0 on success, a negative errno value otherwise and rte_errno is set.
3997 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3998 const struct rte_flow_action *action,
3999 struct mlx5_flow *dev_flow,
4001 struct rte_flow_error *error)
4003 const struct rte_flow_item *encap_data;
4004 const struct rte_flow_action_raw_encap *raw_encap_data;
4005 struct mlx5_flow_dv_encap_decap_resource res = {
4007 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4008 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4009 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4012 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4014 (const struct rte_flow_action_raw_encap *)action->conf;
4015 res.size = raw_encap_data->size;
4016 memcpy(res.buf, raw_encap_data->data, res.size);
4018 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4020 ((const struct rte_flow_action_vxlan_encap *)
4021 action->conf)->definition;
4024 ((const struct rte_flow_action_nvgre_encap *)
4025 action->conf)->definition;
4026 if (flow_dv_convert_encap_data(encap_data, res.buf,
4030 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4032 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4033 return rte_flow_error_set(error, EINVAL,
4034 RTE_FLOW_ERROR_TYPE_ACTION,
4035 NULL, "can't create L2 encap action");
4040 * Convert L2 decap action to DV specification.
4043 * Pointer to rte_eth_dev structure.
4044 * @param[in, out] dev_flow
4045 * Pointer to the mlx5_flow.
4046 * @param[in] transfer
4047 * Mark if the flow is E-Switch flow.
4049 * Pointer to the error structure.
4052 * 0 on success, a negative errno value otherwise and rte_errno is set.
4055 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4056 struct mlx5_flow *dev_flow,
4058 struct rte_flow_error *error)
4060 struct mlx5_flow_dv_encap_decap_resource res = {
4063 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4064 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4065 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4068 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4069 return rte_flow_error_set(error, EINVAL,
4070 RTE_FLOW_ERROR_TYPE_ACTION,
4071 NULL, "can't create L2 decap action");
4076 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4079 * Pointer to rte_eth_dev structure.
4081 * Pointer to action structure.
4082 * @param[in, out] dev_flow
4083 * Pointer to the mlx5_flow.
4085 * Pointer to the flow attributes.
4087 * Pointer to the error structure.
4090 * 0 on success, a negative errno value otherwise and rte_errno is set.
4093 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4094 const struct rte_flow_action *action,
4095 struct mlx5_flow *dev_flow,
4096 const struct rte_flow_attr *attr,
4097 struct rte_flow_error *error)
4099 const struct rte_flow_action_raw_encap *encap_data;
4100 struct mlx5_flow_dv_encap_decap_resource res;
4102 memset(&res, 0, sizeof(res));
4103 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4104 res.size = encap_data->size;
4105 memcpy(res.buf, encap_data->data, res.size);
4106 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4107 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4108 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4110 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4112 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4113 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4114 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4115 return rte_flow_error_set(error, EINVAL,
4116 RTE_FLOW_ERROR_TYPE_ACTION,
4117 NULL, "can't create encap action");
4122 * Create action push VLAN.
4125 * Pointer to rte_eth_dev structure.
4127 * Pointer to the flow attributes.
4129 * Pointer to the vlan to push to the Ethernet header.
4130 * @param[in, out] dev_flow
4131 * Pointer to the mlx5_flow.
4133 * Pointer to the error structure.
4136 * 0 on success, a negative errno value otherwise and rte_errno is set.
4139 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4140 const struct rte_flow_attr *attr,
4141 const struct rte_vlan_hdr *vlan,
4142 struct mlx5_flow *dev_flow,
4143 struct rte_flow_error *error)
4145 struct mlx5_flow_dv_push_vlan_action_resource res;
4147 memset(&res, 0, sizeof(res));
4149 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4152 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4154 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4155 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4156 return flow_dv_push_vlan_action_resource_register
4157 (dev, &res, dev_flow, error);
4161 * Validate the modify-header actions.
4163 * @param[in] action_flags
4164 * Holds the actions detected until now.
4166 * Pointer to the modify action.
4168 * Pointer to error structure.
4171 * 0 on success, a negative errno value otherwise and rte_errno is set.
4174 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4175 const struct rte_flow_action *action,
4176 struct rte_flow_error *error)
4178 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4179 return rte_flow_error_set(error, EINVAL,
4180 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4181 NULL, "action configuration not set");
4182 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4183 return rte_flow_error_set(error, EINVAL,
4184 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4185 "can't have encap action before"
4191 * Validate the modify-header MAC address actions.
4193 * @param[in] action_flags
4194 * Holds the actions detected until now.
4196 * Pointer to the modify action.
4197 * @param[in] item_flags
4198 * Holds the items detected.
4200 * Pointer to error structure.
4203 * 0 on success, a negative errno value otherwise and rte_errno is set.
4206 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4207 const struct rte_flow_action *action,
4208 const uint64_t item_flags,
4209 struct rte_flow_error *error)
4213 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4215 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4216 return rte_flow_error_set(error, EINVAL,
4217 RTE_FLOW_ERROR_TYPE_ACTION,
4219 "no L2 item in pattern");
4225 * Validate the modify-header IPv4 address actions.
4227 * @param[in] action_flags
4228 * Holds the actions detected until now.
4230 * Pointer to the modify action.
4231 * @param[in] item_flags
4232 * Holds the items detected.
4234 * Pointer to error structure.
4237 * 0 on success, a negative errno value otherwise and rte_errno is set.
4240 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4241 const struct rte_flow_action *action,
4242 const uint64_t item_flags,
4243 struct rte_flow_error *error)
4248 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4250 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4251 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4252 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4253 if (!(item_flags & layer))
4254 return rte_flow_error_set(error, EINVAL,
4255 RTE_FLOW_ERROR_TYPE_ACTION,
4257 "no ipv4 item in pattern");
4263 * Validate the modify-header IPv6 address actions.
4265 * @param[in] action_flags
4266 * Holds the actions detected until now.
4268 * Pointer to the modify action.
4269 * @param[in] item_flags
4270 * Holds the items detected.
4272 * Pointer to error structure.
4275 * 0 on success, a negative errno value otherwise and rte_errno is set.
4278 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4279 const struct rte_flow_action *action,
4280 const uint64_t item_flags,
4281 struct rte_flow_error *error)
4286 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4288 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4289 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4290 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4291 if (!(item_flags & layer))
4292 return rte_flow_error_set(error, EINVAL,
4293 RTE_FLOW_ERROR_TYPE_ACTION,
4295 "no ipv6 item in pattern");
4301 * Validate the modify-header TP actions.
4303 * @param[in] action_flags
4304 * Holds the actions detected until now.
4306 * Pointer to the modify action.
4307 * @param[in] item_flags
4308 * Holds the items detected.
4310 * Pointer to error structure.
4313 * 0 on success, a negative errno value otherwise and rte_errno is set.
4316 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4317 const struct rte_flow_action *action,
4318 const uint64_t item_flags,
4319 struct rte_flow_error *error)
4324 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4326 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4327 MLX5_FLOW_LAYER_INNER_L4 :
4328 MLX5_FLOW_LAYER_OUTER_L4;
4329 if (!(item_flags & layer))
4330 return rte_flow_error_set(error, EINVAL,
4331 RTE_FLOW_ERROR_TYPE_ACTION,
4332 NULL, "no transport layer "
4339 * Validate the modify-header actions of increment/decrement
4340 * TCP Sequence-number.
4342 * @param[in] action_flags
4343 * Holds the actions detected until now.
4345 * Pointer to the modify action.
4346 * @param[in] item_flags
4347 * Holds the items detected.
4349 * Pointer to error structure.
4352 * 0 on success, a negative errno value otherwise and rte_errno is set.
4355 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4356 const struct rte_flow_action *action,
4357 const uint64_t item_flags,
4358 struct rte_flow_error *error)
4363 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4365 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4366 MLX5_FLOW_LAYER_INNER_L4_TCP :
4367 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4368 if (!(item_flags & layer))
4369 return rte_flow_error_set(error, EINVAL,
4370 RTE_FLOW_ERROR_TYPE_ACTION,
4371 NULL, "no TCP item in"
4373 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4374 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4375 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4376 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4377 return rte_flow_error_set(error, EINVAL,
4378 RTE_FLOW_ERROR_TYPE_ACTION,
4380 "cannot decrease and increase"
4381 " TCP sequence number"
4382 " at the same time");
4388 * Validate the modify-header actions of increment/decrement
4389 * TCP Acknowledgment number.
4391 * @param[in] action_flags
4392 * Holds the actions detected until now.
4394 * Pointer to the modify action.
4395 * @param[in] item_flags
4396 * Holds the items detected.
4398 * Pointer to error structure.
4401 * 0 on success, a negative errno value otherwise and rte_errno is set.
4404 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4405 const struct rte_flow_action *action,
4406 const uint64_t item_flags,
4407 struct rte_flow_error *error)
4412 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4414 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4415 MLX5_FLOW_LAYER_INNER_L4_TCP :
4416 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4417 if (!(item_flags & layer))
4418 return rte_flow_error_set(error, EINVAL,
4419 RTE_FLOW_ERROR_TYPE_ACTION,
4420 NULL, "no TCP item in"
4422 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4423 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4424 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4425 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4426 return rte_flow_error_set(error, EINVAL,
4427 RTE_FLOW_ERROR_TYPE_ACTION,
4429 "cannot decrease and increase"
4430 " TCP acknowledgment number"
4431 " at the same time");
4437 * Validate the modify-header TTL actions.
4439 * @param[in] action_flags
4440 * Holds the actions detected until now.
4442 * Pointer to the modify action.
4443 * @param[in] item_flags
4444 * Holds the items detected.
4446 * Pointer to error structure.
4449 * 0 on success, a negative errno value otherwise and rte_errno is set.
4452 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4453 const struct rte_flow_action *action,
4454 const uint64_t item_flags,
4455 struct rte_flow_error *error)
4460 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4462 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4463 MLX5_FLOW_LAYER_INNER_L3 :
4464 MLX5_FLOW_LAYER_OUTER_L3;
4465 if (!(item_flags & layer))
4466 return rte_flow_error_set(error, EINVAL,
4467 RTE_FLOW_ERROR_TYPE_ACTION,
4469 "no IP protocol in pattern");
4475 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4478 case RTE_FLOW_FIELD_START:
4480 case RTE_FLOW_FIELD_MAC_DST:
4481 case RTE_FLOW_FIELD_MAC_SRC:
4483 case RTE_FLOW_FIELD_VLAN_TYPE:
4485 case RTE_FLOW_FIELD_VLAN_ID:
4487 case RTE_FLOW_FIELD_MAC_TYPE:
4489 case RTE_FLOW_FIELD_IPV4_DSCP:
4491 case RTE_FLOW_FIELD_IPV4_TTL:
4493 case RTE_FLOW_FIELD_IPV4_SRC:
4494 case RTE_FLOW_FIELD_IPV4_DST:
4496 case RTE_FLOW_FIELD_IPV6_DSCP:
4498 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4500 case RTE_FLOW_FIELD_IPV6_SRC:
4501 case RTE_FLOW_FIELD_IPV6_DST:
4503 case RTE_FLOW_FIELD_TCP_PORT_SRC:
4504 case RTE_FLOW_FIELD_TCP_PORT_DST:
4506 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4507 case RTE_FLOW_FIELD_TCP_ACK_NUM:
4509 case RTE_FLOW_FIELD_TCP_FLAGS:
4511 case RTE_FLOW_FIELD_UDP_PORT_SRC:
4512 case RTE_FLOW_FIELD_UDP_PORT_DST:
4514 case RTE_FLOW_FIELD_VXLAN_VNI:
4515 case RTE_FLOW_FIELD_GENEVE_VNI:
4517 case RTE_FLOW_FIELD_GTP_TEID:
4518 case RTE_FLOW_FIELD_TAG:
4520 case RTE_FLOW_FIELD_MARK:
4522 case RTE_FLOW_FIELD_META:
4523 case RTE_FLOW_FIELD_POINTER:
4524 case RTE_FLOW_FIELD_VALUE:
4533 * Validate the generic modify field actions.
4535 * Pointer to the rte_eth_dev structure.
4536 * @param[in] action_flags
4537 * Holds the actions detected until now.
4539 * Pointer to the modify action.
4541 * Pointer to the flow attributes.
4543 * Pointer to error structure.
4546 * Number of header fields to modify (0 or more) on success,
4547 * a negative errno value otherwise and rte_errno is set.
4550 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4551 const uint64_t action_flags,
4552 const struct rte_flow_action *action,
4553 const struct rte_flow_attr *attr,
4554 struct rte_flow_error *error)
4557 struct mlx5_priv *priv = dev->data->dev_private;
4558 struct mlx5_dev_config *config = &priv->config;
4559 const struct rte_flow_action_modify_field *action_modify_field =
4561 uint32_t dst_width =
4562 mlx5_flow_item_field_width(action_modify_field->dst.field);
4563 uint32_t src_width =
4564 mlx5_flow_item_field_width(action_modify_field->src.field);
4566 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4570 if (action_modify_field->width == 0)
4571 return rte_flow_error_set(error, EINVAL,
4572 RTE_FLOW_ERROR_TYPE_ACTION, action,
4573 "no bits are requested to be modified");
4574 else if (action_modify_field->width > dst_width ||
4575 action_modify_field->width > src_width)
4576 return rte_flow_error_set(error, EINVAL,
4577 RTE_FLOW_ERROR_TYPE_ACTION, action,
4578 "cannot modify more bits than"
4579 " the width of a field");
4580 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4581 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4582 if ((action_modify_field->dst.offset +
4583 action_modify_field->width > dst_width) ||
4584 (action_modify_field->dst.offset % 32))
4585 return rte_flow_error_set(error, EINVAL,
4586 RTE_FLOW_ERROR_TYPE_ACTION, action,
4587 "destination offset is too big"
4588 " or not aligned to 4 bytes");
4589 if (action_modify_field->dst.level &&
4590 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4591 return rte_flow_error_set(error, ENOTSUP,
4592 RTE_FLOW_ERROR_TYPE_ACTION, action,
4593 "inner header fields modification"
4594 " is not supported");
4596 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4597 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4598 if (!attr->transfer && !attr->group)
4599 return rte_flow_error_set(error, ENOTSUP,
4600 RTE_FLOW_ERROR_TYPE_ACTION, action,
4601 "modify field action is not"
4602 " supported for group 0");
4603 if ((action_modify_field->src.offset +
4604 action_modify_field->width > src_width) ||
4605 (action_modify_field->src.offset % 32))
4606 return rte_flow_error_set(error, EINVAL,
4607 RTE_FLOW_ERROR_TYPE_ACTION, action,
4608 "source offset is too big"
4609 " or not aligned to 4 bytes");
4610 if (action_modify_field->src.level &&
4611 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4612 return rte_flow_error_set(error, ENOTSUP,
4613 RTE_FLOW_ERROR_TYPE_ACTION, action,
4614 "inner header fields modification"
4615 " is not supported");
4617 if (action_modify_field->dst.field ==
4618 action_modify_field->src.field)
4619 return rte_flow_error_set(error, EINVAL,
4620 RTE_FLOW_ERROR_TYPE_ACTION, action,
4621 "source and destination fields"
4622 " cannot be the same");
4623 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4624 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4625 return rte_flow_error_set(error, EINVAL,
4626 RTE_FLOW_ERROR_TYPE_ACTION, action,
4627 "immediate value or a pointer to it"
4628 " cannot be used as a destination");
4629 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4630 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4631 return rte_flow_error_set(error, ENOTSUP,
4632 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633 "modifications of an arbitrary"
4634 " place in a packet is not supported");
4635 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4636 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4637 return rte_flow_error_set(error, ENOTSUP,
4638 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639 "modifications of the 802.1Q Tag"
4640 " Identifier is not supported");
4641 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4642 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4643 return rte_flow_error_set(error, ENOTSUP,
4644 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645 "modifications of the VXLAN Network"
4646 " Identifier is not supported");
4647 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4648 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4649 return rte_flow_error_set(error, ENOTSUP,
4650 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651 "modifications of the GENEVE Network"
4652 " Identifier is not supported");
4653 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4654 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4655 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4656 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4657 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4658 !mlx5_flow_ext_mreg_supported(dev))
4659 return rte_flow_error_set(error, ENOTSUP,
4660 RTE_FLOW_ERROR_TYPE_ACTION, action,
4661 "cannot modify mark or metadata without"
4662 " extended metadata register support");
4664 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4665 return rte_flow_error_set(error, ENOTSUP,
4666 RTE_FLOW_ERROR_TYPE_ACTION, action,
4667 "add and sub operations"
4668 " are not supported");
4669 return (action_modify_field->width / 32) +
4670 !!(action_modify_field->width % 32);
4674 * Validate jump action.
4677 * Pointer to the jump action.
4678 * @param[in] action_flags
4679 * Holds the actions detected until now.
4680 * @param[in] attributes
4681 * Pointer to flow attributes
4682 * @param[in] external
4683 * Action belongs to flow rule created by request external to PMD.
4685 * Pointer to error structure.
4688 * 0 on success, a negative errno value otherwise and rte_errno is set.
4691 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4692 const struct mlx5_flow_tunnel *tunnel,
4693 const struct rte_flow_action *action,
4694 uint64_t action_flags,
4695 const struct rte_flow_attr *attributes,
4696 bool external, struct rte_flow_error *error)
4698 uint32_t target_group, table;
4700 struct flow_grp_info grp_info = {
4701 .external = !!external,
4702 .transfer = !!attributes->transfer,
4706 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4707 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4708 return rte_flow_error_set(error, EINVAL,
4709 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4710 "can't have 2 fate actions in"
4712 if (action_flags & MLX5_FLOW_ACTION_METER)
4713 return rte_flow_error_set(error, ENOTSUP,
4714 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4715 "jump with meter not support");
4717 return rte_flow_error_set(error, EINVAL,
4718 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4719 NULL, "action configuration not set");
4721 ((const struct rte_flow_action_jump *)action->conf)->group;
4722 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4726 if (attributes->group == target_group &&
4727 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4728 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4729 return rte_flow_error_set(error, EINVAL,
4730 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4731 "target group must be other than"
4732 " the current flow group");
4737 * Validate the port_id action.
4740 * Pointer to rte_eth_dev structure.
4741 * @param[in] action_flags
4742 * Bit-fields that holds the actions detected until now.
4744 * Port_id RTE action structure.
4746 * Attributes of flow that includes this action.
4748 * Pointer to error structure.
4751 * 0 on success, a negative errno value otherwise and rte_errno is set.
4754 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4755 uint64_t action_flags,
4756 const struct rte_flow_action *action,
4757 const struct rte_flow_attr *attr,
4758 struct rte_flow_error *error)
4760 const struct rte_flow_action_port_id *port_id;
4761 struct mlx5_priv *act_priv;
4762 struct mlx5_priv *dev_priv;
4765 if (!attr->transfer)
4766 return rte_flow_error_set(error, ENOTSUP,
4767 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4769 "port id action is valid in transfer"
4771 if (!action || !action->conf)
4772 return rte_flow_error_set(error, ENOTSUP,
4773 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4775 "port id action parameters must be"
4777 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4778 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4779 return rte_flow_error_set(error, EINVAL,
4780 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4781 "can have only one fate actions in"
4783 dev_priv = mlx5_dev_to_eswitch_info(dev);
4785 return rte_flow_error_set(error, rte_errno,
4786 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4788 "failed to obtain E-Switch info");
4789 port_id = action->conf;
4790 port = port_id->original ? dev->data->port_id : port_id->id;
4791 act_priv = mlx5_port_to_eswitch_info(port, false);
4793 return rte_flow_error_set
4795 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4796 "failed to obtain E-Switch port id for port");
4797 if (act_priv->domain_id != dev_priv->domain_id)
4798 return rte_flow_error_set
4800 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4801 "port does not belong to"
4802 " E-Switch being configured");
4807 * Get the maximum number of modify header actions.
4810 * Pointer to rte_eth_dev structure.
4812 * Flags bits to check if root level.
4815 * Max number of modify header actions device can support.
4817 static inline unsigned int
4818 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4822 * There's no way to directly query the max capacity from FW.
4823 * The maximal value on root table should be assumed to be supported.
4825 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4826 return MLX5_MAX_MODIFY_NUM;
4828 return MLX5_ROOT_TBL_MODIFY_NUM;
4832 * Validate the meter action.
4835 * Pointer to rte_eth_dev structure.
4836 * @param[in] action_flags
4837 * Bit-fields that holds the actions detected until now.
4839 * Pointer to the meter action.
4841 * Attributes of flow that includes this action.
4843 * Pointer to error structure.
4846 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4849 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4850 uint64_t action_flags,
4851 const struct rte_flow_action *action,
4852 const struct rte_flow_attr *attr,
4853 struct rte_flow_error *error)
4855 struct mlx5_priv *priv = dev->data->dev_private;
4856 const struct rte_flow_action_meter *am = action->conf;
4857 struct mlx5_flow_meter *fm;
4860 return rte_flow_error_set(error, EINVAL,
4861 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4862 "meter action conf is NULL");
4864 if (action_flags & MLX5_FLOW_ACTION_METER)
4865 return rte_flow_error_set(error, ENOTSUP,
4866 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4867 "meter chaining not support");
4868 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4869 return rte_flow_error_set(error, ENOTSUP,
4870 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4871 "meter with jump not support");
4873 return rte_flow_error_set(error, ENOTSUP,
4874 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4876 "meter action not supported");
4877 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4879 return rte_flow_error_set(error, EINVAL,
4880 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4882 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4883 (!fm->ingress && !attr->ingress && attr->egress) ||
4884 (!fm->egress && !attr->egress && attr->ingress))))
4885 return rte_flow_error_set(error, EINVAL,
4886 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4887 "Flow attributes are either invalid "
4888 "or have a conflict with current "
4889 "meter attributes");
4894 * Validate the age action.
4896 * @param[in] action_flags
4897 * Holds the actions detected until now.
4899 * Pointer to the age action.
4901 * Pointer to the Ethernet device structure.
4903 * Pointer to error structure.
4906 * 0 on success, a negative errno value otherwise and rte_errno is set.
4909 flow_dv_validate_action_age(uint64_t action_flags,
4910 const struct rte_flow_action *action,
4911 struct rte_eth_dev *dev,
4912 struct rte_flow_error *error)
4914 struct mlx5_priv *priv = dev->data->dev_private;
4915 const struct rte_flow_action_age *age = action->conf;
4917 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4918 !priv->sh->aso_age_mng))
4919 return rte_flow_error_set(error, ENOTSUP,
4920 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4922 "age action not supported");
4923 if (!(action->conf))
4924 return rte_flow_error_set(error, EINVAL,
4925 RTE_FLOW_ERROR_TYPE_ACTION, action,
4926 "configuration cannot be null");
4927 if (!(age->timeout))
4928 return rte_flow_error_set(error, EINVAL,
4929 RTE_FLOW_ERROR_TYPE_ACTION, action,
4930 "invalid timeout value 0");
4931 if (action_flags & MLX5_FLOW_ACTION_AGE)
4932 return rte_flow_error_set(error, EINVAL,
4933 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4934 "duplicate age actions set");
4939 * Validate the modify-header IPv4 DSCP actions.
4941 * @param[in] action_flags
4942 * Holds the actions detected until now.
4944 * Pointer to the modify action.
4945 * @param[in] item_flags
4946 * Holds the items detected.
4948 * Pointer to error structure.
4951 * 0 on success, a negative errno value otherwise and rte_errno is set.
4954 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4955 const struct rte_flow_action *action,
4956 const uint64_t item_flags,
4957 struct rte_flow_error *error)
4961 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4963 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4964 return rte_flow_error_set(error, EINVAL,
4965 RTE_FLOW_ERROR_TYPE_ACTION,
4967 "no ipv4 item in pattern");
4973 * Validate the modify-header IPv6 DSCP actions.
4975 * @param[in] action_flags
4976 * Holds the actions detected until now.
4978 * Pointer to the modify action.
4979 * @param[in] item_flags
4980 * Holds the items detected.
4982 * Pointer to error structure.
4985 * 0 on success, a negative errno value otherwise and rte_errno is set.
4988 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4989 const struct rte_flow_action *action,
4990 const uint64_t item_flags,
4991 struct rte_flow_error *error)
4995 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4997 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4998 return rte_flow_error_set(error, EINVAL,
4999 RTE_FLOW_ERROR_TYPE_ACTION,
5001 "no ipv6 item in pattern");
5007 * Match modify-header resource.
5010 * Pointer to the hash list.
5012 * Pointer to exist resource entry object.
5014 * Key of the new entry.
5016 * Pointer to new modify-header resource.
5019 * 0 on matching, non-zero otherwise.
5022 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5023 struct mlx5_hlist_entry *entry,
5024 uint64_t key __rte_unused, void *cb_ctx)
5026 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5027 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5028 struct mlx5_flow_dv_modify_hdr_resource *resource =
5029 container_of(entry, typeof(*resource), entry);
5030 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5032 key_len += ref->actions_num * sizeof(ref->actions[0]);
5033 return ref->actions_num != resource->actions_num ||
5034 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5037 struct mlx5_hlist_entry *
5038 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5041 struct mlx5_dev_ctx_shared *sh = list->ctx;
5042 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5043 struct mlx5dv_dr_domain *ns;
5044 struct mlx5_flow_dv_modify_hdr_resource *entry;
5045 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5047 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5048 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5050 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5053 rte_flow_error_set(ctx->error, ENOMEM,
5054 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5055 "cannot allocate resource memory");
5058 rte_memcpy(&entry->ft_type,
5059 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5060 key_len + data_len);
5061 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5062 ns = sh->fdb_domain;
5063 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5067 ret = mlx5_flow_os_create_flow_action_modify_header
5068 (sh->ctx, ns, entry,
5069 data_len, &entry->action);
5072 rte_flow_error_set(ctx->error, ENOMEM,
5073 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5074 NULL, "cannot create modification action");
5077 return &entry->entry;
5081 * Validate the sample action.
5083 * @param[in, out] action_flags
5084 * Holds the actions detected until now.
5086 * Pointer to the sample action.
5088 * Pointer to the Ethernet device structure.
5090 * Attributes of flow that includes this action.
5091 * @param[in] item_flags
5092 * Holds the items detected.
5094 * Pointer to the RSS action.
5095 * @param[out] sample_rss
5096 * Pointer to the RSS action in sample action list.
5098 * Pointer to the COUNT action in sample action list.
5099 * @param[out] fdb_mirror_limit
5100 * Pointer to the FDB mirror limitation flag.
5102 * Pointer to error structure.
5105 * 0 on success, a negative errno value otherwise and rte_errno is set.
5108 flow_dv_validate_action_sample(uint64_t *action_flags,
5109 const struct rte_flow_action *action,
5110 struct rte_eth_dev *dev,
5111 const struct rte_flow_attr *attr,
5112 uint64_t item_flags,
5113 const struct rte_flow_action_rss *rss,
5114 const struct rte_flow_action_rss **sample_rss,
5115 const struct rte_flow_action_count **count,
5116 int *fdb_mirror_limit,
5117 struct rte_flow_error *error)
5119 struct mlx5_priv *priv = dev->data->dev_private;
5120 struct mlx5_dev_config *dev_conf = &priv->config;
5121 const struct rte_flow_action_sample *sample = action->conf;
5122 const struct rte_flow_action *act;
5123 uint64_t sub_action_flags = 0;
5124 uint16_t queue_index = 0xFFFF;
5129 return rte_flow_error_set(error, EINVAL,
5130 RTE_FLOW_ERROR_TYPE_ACTION, action,
5131 "configuration cannot be NULL");
5132 if (sample->ratio == 0)
5133 return rte_flow_error_set(error, EINVAL,
5134 RTE_FLOW_ERROR_TYPE_ACTION, action,
5135 "ratio value starts from 1");
5136 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5137 return rte_flow_error_set(error, ENOTSUP,
5138 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5140 "sample action not supported");
5141 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5142 return rte_flow_error_set(error, EINVAL,
5143 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5144 "Multiple sample actions not "
5146 if (*action_flags & MLX5_FLOW_ACTION_METER)
5147 return rte_flow_error_set(error, EINVAL,
5148 RTE_FLOW_ERROR_TYPE_ACTION, action,
5149 "wrong action order, meter should "
5150 "be after sample action");
5151 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5152 return rte_flow_error_set(error, EINVAL,
5153 RTE_FLOW_ERROR_TYPE_ACTION, action,
5154 "wrong action order, jump should "
5155 "be after sample action");
5156 act = sample->actions;
5157 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5158 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5159 return rte_flow_error_set(error, ENOTSUP,
5160 RTE_FLOW_ERROR_TYPE_ACTION,
5161 act, "too many actions");
5162 switch (act->type) {
5163 case RTE_FLOW_ACTION_TYPE_QUEUE:
5164 ret = mlx5_flow_validate_action_queue(act,
5170 queue_index = ((const struct rte_flow_action_queue *)
5171 (act->conf))->index;
5172 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5175 case RTE_FLOW_ACTION_TYPE_RSS:
5176 *sample_rss = act->conf;
5177 ret = mlx5_flow_validate_action_rss(act,
5184 if (rss && *sample_rss &&
5185 ((*sample_rss)->level != rss->level ||
5186 (*sample_rss)->types != rss->types))
5187 return rte_flow_error_set(error, ENOTSUP,
5188 RTE_FLOW_ERROR_TYPE_ACTION,
5190 "Can't use the different RSS types "
5191 "or level in the same flow");
5192 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5193 queue_index = (*sample_rss)->queue[0];
5194 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5197 case RTE_FLOW_ACTION_TYPE_MARK:
5198 ret = flow_dv_validate_action_mark(dev, act,
5203 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5204 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5205 MLX5_FLOW_ACTION_MARK_EXT;
5207 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5210 case RTE_FLOW_ACTION_TYPE_COUNT:
5211 ret = flow_dv_validate_action_count
5213 *action_flags | sub_action_flags,
5218 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5219 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5222 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5223 ret = flow_dv_validate_action_port_id(dev,
5230 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5233 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5234 ret = flow_dv_validate_action_raw_encap_decap
5235 (dev, NULL, act->conf, attr, &sub_action_flags,
5236 &actions_n, action, item_flags, error);
5241 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5242 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5243 ret = flow_dv_validate_action_l2_encap(dev,
5249 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5253 return rte_flow_error_set(error, ENOTSUP,
5254 RTE_FLOW_ERROR_TYPE_ACTION,
5256 "Doesn't support optional "
5260 if (attr->ingress && !attr->transfer) {
5261 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5262 MLX5_FLOW_ACTION_RSS)))
5263 return rte_flow_error_set(error, EINVAL,
5264 RTE_FLOW_ERROR_TYPE_ACTION,
5266 "Ingress must has a dest "
5267 "QUEUE for Sample");
5268 } else if (attr->egress && !attr->transfer) {
5269 return rte_flow_error_set(error, ENOTSUP,
5270 RTE_FLOW_ERROR_TYPE_ACTION,
5272 "Sample Only support Ingress "
5274 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5275 MLX5_ASSERT(attr->transfer);
5276 if (sample->ratio > 1)
5277 return rte_flow_error_set(error, ENOTSUP,
5278 RTE_FLOW_ERROR_TYPE_ACTION,
5280 "E-Switch doesn't support "
5281 "any optional action "
5283 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5284 return rte_flow_error_set(error, ENOTSUP,
5285 RTE_FLOW_ERROR_TYPE_ACTION,
5287 "unsupported action QUEUE");
5288 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5289 return rte_flow_error_set(error, ENOTSUP,
5290 RTE_FLOW_ERROR_TYPE_ACTION,
5292 "unsupported action QUEUE");
5293 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5294 return rte_flow_error_set(error, EINVAL,
5295 RTE_FLOW_ERROR_TYPE_ACTION,
5297 "E-Switch must has a dest "
5298 "port for mirroring");
5299 if (!priv->config.hca_attr.reg_c_preserve &&
5300 priv->representor_id != -1)
5301 *fdb_mirror_limit = 1;
5303 /* Continue validation for Xcap actions.*/
5304 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5305 (queue_index == 0xFFFF ||
5306 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5307 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5308 MLX5_FLOW_XCAP_ACTIONS)
5309 return rte_flow_error_set(error, ENOTSUP,
5310 RTE_FLOW_ERROR_TYPE_ACTION,
5311 NULL, "encap and decap "
5312 "combination aren't "
5314 if (!attr->transfer && attr->ingress && (sub_action_flags &
5315 MLX5_FLOW_ACTION_ENCAP))
5316 return rte_flow_error_set(error, ENOTSUP,
5317 RTE_FLOW_ERROR_TYPE_ACTION,
5318 NULL, "encap is not supported"
5319 " for ingress traffic");
5325 * Find existing modify-header resource or create and register a new one.
5327 * @param dev[in, out]
5328 * Pointer to rte_eth_dev structure.
5329 * @param[in, out] resource
5330 * Pointer to modify-header resource.
5331 * @parm[in, out] dev_flow
5332 * Pointer to the dev_flow.
5334 * pointer to error structure.
5337 * 0 on success otherwise -errno and errno is set.
5340 flow_dv_modify_hdr_resource_register
5341 (struct rte_eth_dev *dev,
5342 struct mlx5_flow_dv_modify_hdr_resource *resource,
5343 struct mlx5_flow *dev_flow,
5344 struct rte_flow_error *error)
5346 struct mlx5_priv *priv = dev->data->dev_private;
5347 struct mlx5_dev_ctx_shared *sh = priv->sh;
5348 uint32_t key_len = sizeof(*resource) -
5349 offsetof(typeof(*resource), ft_type) +
5350 resource->actions_num * sizeof(resource->actions[0]);
5351 struct mlx5_hlist_entry *entry;
5352 struct mlx5_flow_cb_ctx ctx = {
5358 resource->flags = dev_flow->dv.group ? 0 :
5359 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5360 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5362 return rte_flow_error_set(error, EOVERFLOW,
5363 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5364 "too many modify header items");
5365 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5366 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5369 resource = container_of(entry, typeof(*resource), entry);
5370 dev_flow->handle->dvh.modify_hdr = resource;
5375 * Get DV flow counter by index.
5378 * Pointer to the Ethernet device structure.
5380 * mlx5 flow counter index in the container.
5382 * mlx5 flow counter pool in the container,
5385 * Pointer to the counter, NULL otherwise.
5387 static struct mlx5_flow_counter *
5388 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5390 struct mlx5_flow_counter_pool **ppool)
5392 struct mlx5_priv *priv = dev->data->dev_private;
5393 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5394 struct mlx5_flow_counter_pool *pool;
5396 /* Decrease to original index and clear shared bit. */
5397 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5398 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5399 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5403 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5407 * Check the devx counter belongs to the pool.
5410 * Pointer to the counter pool.
5412 * The counter devx ID.
5415 * True if counter belongs to the pool, false otherwise.
5418 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5420 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5421 MLX5_COUNTERS_PER_POOL;
5423 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5429 * Get a pool by devx counter ID.
5432 * Pointer to the counter management.
5434 * The counter devx ID.
5437 * The counter pool pointer if exists, NULL otherwise,
5439 static struct mlx5_flow_counter_pool *
5440 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5443 struct mlx5_flow_counter_pool *pool = NULL;
5445 rte_spinlock_lock(&cmng->pool_update_sl);
5446 /* Check last used pool. */
5447 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5448 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5449 pool = cmng->pools[cmng->last_pool_idx];
5452 /* ID out of range means no suitable pool in the container. */
5453 if (id > cmng->max_id || id < cmng->min_id)
5456 * Find the pool from the end of the container, since mostly counter
5457 * ID is sequence increasing, and the last pool should be the needed
5462 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5464 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5470 rte_spinlock_unlock(&cmng->pool_update_sl);
5475 * Resize a counter container.
5478 * Pointer to the Ethernet device structure.
5481 * 0 on success, otherwise negative errno value and rte_errno is set.
5484 flow_dv_container_resize(struct rte_eth_dev *dev)
5486 struct mlx5_priv *priv = dev->data->dev_private;
5487 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5488 void *old_pools = cmng->pools;
5489 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5490 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5491 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5498 memcpy(pools, old_pools, cmng->n *
5499 sizeof(struct mlx5_flow_counter_pool *));
5501 cmng->pools = pools;
5503 mlx5_free(old_pools);
5508 * Query a devx flow counter.
5511 * Pointer to the Ethernet device structure.
5513 * Index to the flow counter.
5515 * The statistics value of packets.
5517 * The statistics value of bytes.
5520 * 0 on success, otherwise a negative errno value and rte_errno is set.
5523 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5526 struct mlx5_priv *priv = dev->data->dev_private;
5527 struct mlx5_flow_counter_pool *pool = NULL;
5528 struct mlx5_flow_counter *cnt;
5531 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5533 if (priv->sh->cmng.counter_fallback)
5534 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5535 0, pkts, bytes, 0, NULL, NULL, 0);
5536 rte_spinlock_lock(&pool->sl);
5541 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5542 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5543 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5545 rte_spinlock_unlock(&pool->sl);
5550 * Create and initialize a new counter pool.
5553 * Pointer to the Ethernet device structure.
5555 * The devX counter handle.
5557 * Whether the pool is for counter that was allocated for aging.
5558 * @param[in/out] cont_cur
5559 * Pointer to the container pointer, it will be update in pool resize.
5562 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5564 static struct mlx5_flow_counter_pool *
5565 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5568 struct mlx5_priv *priv = dev->data->dev_private;
5569 struct mlx5_flow_counter_pool *pool;
5570 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5571 bool fallback = priv->sh->cmng.counter_fallback;
5572 uint32_t size = sizeof(*pool);
5574 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5575 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5576 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5582 pool->is_aged = !!age;
5583 pool->query_gen = 0;
5584 pool->min_dcs = dcs;
5585 rte_spinlock_init(&pool->sl);
5586 rte_spinlock_init(&pool->csl);
5587 TAILQ_INIT(&pool->counters[0]);
5588 TAILQ_INIT(&pool->counters[1]);
5589 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5590 rte_spinlock_lock(&cmng->pool_update_sl);
5591 pool->index = cmng->n_valid;
5592 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5594 rte_spinlock_unlock(&cmng->pool_update_sl);
5597 cmng->pools[pool->index] = pool;
5599 if (unlikely(fallback)) {
5600 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5602 if (base < cmng->min_id)
5603 cmng->min_id = base;
5604 if (base > cmng->max_id)
5605 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5606 cmng->last_pool_idx = pool->index;
5608 rte_spinlock_unlock(&cmng->pool_update_sl);
5613 * Prepare a new counter and/or a new counter pool.
5616 * Pointer to the Ethernet device structure.
5617 * @param[out] cnt_free
5618 * Where to put the pointer of a new counter.
5620 * Whether the pool is for counter that was allocated for aging.
5623 * The counter pool pointer and @p cnt_free is set on success,
5624 * NULL otherwise and rte_errno is set.
5626 static struct mlx5_flow_counter_pool *
5627 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5628 struct mlx5_flow_counter **cnt_free,
5631 struct mlx5_priv *priv = dev->data->dev_private;
5632 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5633 struct mlx5_flow_counter_pool *pool;
5634 struct mlx5_counters tmp_tq;
5635 struct mlx5_devx_obj *dcs = NULL;
5636 struct mlx5_flow_counter *cnt;
5637 enum mlx5_counter_type cnt_type =
5638 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5639 bool fallback = priv->sh->cmng.counter_fallback;
5643 /* bulk_bitmap must be 0 for single counter allocation. */
5644 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5647 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5649 pool = flow_dv_pool_create(dev, dcs, age);
5651 mlx5_devx_cmd_destroy(dcs);
5655 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5656 cnt = MLX5_POOL_GET_CNT(pool, i);
5658 cnt->dcs_when_free = dcs;
5662 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5664 rte_errno = ENODATA;
5667 pool = flow_dv_pool_create(dev, dcs, age);
5669 mlx5_devx_cmd_destroy(dcs);
5672 TAILQ_INIT(&tmp_tq);
5673 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5674 cnt = MLX5_POOL_GET_CNT(pool, i);
5676 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5678 rte_spinlock_lock(&cmng->csl[cnt_type]);
5679 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5680 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5681 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5682 (*cnt_free)->pool = pool;
5687 * Allocate a flow counter.
5690 * Pointer to the Ethernet device structure.
5692 * Whether the counter was allocated for aging.
5695 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5698 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5700 struct mlx5_priv *priv = dev->data->dev_private;
5701 struct mlx5_flow_counter_pool *pool = NULL;
5702 struct mlx5_flow_counter *cnt_free = NULL;
5703 bool fallback = priv->sh->cmng.counter_fallback;
5704 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5705 enum mlx5_counter_type cnt_type =
5706 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5709 if (!priv->config.devx) {
5710 rte_errno = ENOTSUP;
5713 /* Get free counters from container. */
5714 rte_spinlock_lock(&cmng->csl[cnt_type]);
5715 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5717 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5718 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5719 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5721 pool = cnt_free->pool;
5723 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5724 /* Create a DV counter action only in the first time usage. */
5725 if (!cnt_free->action) {
5727 struct mlx5_devx_obj *dcs;
5731 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5732 dcs = pool->min_dcs;
5735 dcs = cnt_free->dcs_when_free;
5737 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5744 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5745 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5746 /* Update the counter reset values. */
5747 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5750 if (!fallback && !priv->sh->cmng.query_thread_on)
5751 /* Start the asynchronous batch query by the host thread. */
5752 mlx5_set_query_alarm(priv->sh);
5756 cnt_free->pool = pool;
5758 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5759 rte_spinlock_lock(&cmng->csl[cnt_type]);
5760 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5761 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5767 * Allocate a shared flow counter.
5770 * Pointer to the shared counter configuration.
5772 * Pointer to save the allocated counter index.
5775 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5779 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5781 struct mlx5_shared_counter_conf *conf = ctx;
5782 struct rte_eth_dev *dev = conf->dev;
5783 struct mlx5_flow_counter *cnt;
5785 data->dword = flow_dv_counter_alloc(dev, 0);
5786 data->dword |= MLX5_CNT_SHARED_OFFSET;
5787 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5788 cnt->shared_info.id = conf->id;
5793 * Get a shared flow counter.
5796 * Pointer to the Ethernet device structure.
5798 * Counter identifier.
5801 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5804 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5806 struct mlx5_priv *priv = dev->data->dev_private;
5807 struct mlx5_shared_counter_conf conf = {
5811 union mlx5_l3t_data data = {
5815 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5816 flow_dv_counter_alloc_shared_cb, &conf);
5821 * Get age param from counter index.
5824 * Pointer to the Ethernet device structure.
5825 * @param[in] counter
5826 * Index to the counter handler.
5829 * The aging parameter specified for the counter index.
5831 static struct mlx5_age_param*
5832 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5835 struct mlx5_flow_counter *cnt;
5836 struct mlx5_flow_counter_pool *pool = NULL;
5838 flow_dv_counter_get_by_idx(dev, counter, &pool);
5839 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5840 cnt = MLX5_POOL_GET_CNT(pool, counter);
5841 return MLX5_CNT_TO_AGE(cnt);
5845 * Remove a flow counter from aged counter list.
5848 * Pointer to the Ethernet device structure.
5849 * @param[in] counter
5850 * Index to the counter handler.
5852 * Pointer to the counter handler.
5855 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5856 uint32_t counter, struct mlx5_flow_counter *cnt)
5858 struct mlx5_age_info *age_info;
5859 struct mlx5_age_param *age_param;
5860 struct mlx5_priv *priv = dev->data->dev_private;
5861 uint16_t expected = AGE_CANDIDATE;
5863 age_info = GET_PORT_AGE_INFO(priv);
5864 age_param = flow_dv_counter_idx_get_age(dev, counter);
5865 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5866 AGE_FREE, false, __ATOMIC_RELAXED,
5867 __ATOMIC_RELAXED)) {
5869 * We need the lock even it is age timeout,
5870 * since counter may still in process.
5872 rte_spinlock_lock(&age_info->aged_sl);
5873 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5874 rte_spinlock_unlock(&age_info->aged_sl);
5875 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5880 * Release a flow counter.
5883 * Pointer to the Ethernet device structure.
5884 * @param[in] counter
5885 * Index to the counter handler.
5888 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5890 struct mlx5_priv *priv = dev->data->dev_private;
5891 struct mlx5_flow_counter_pool *pool = NULL;
5892 struct mlx5_flow_counter *cnt;
5893 enum mlx5_counter_type cnt_type;
5897 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5899 if (IS_SHARED_CNT(counter) &&
5900 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5903 flow_dv_counter_remove_from_age(dev, counter, cnt);
5906 * Put the counter back to list to be updated in none fallback mode.
5907 * Currently, we are using two list alternately, while one is in query,
5908 * add the freed counter to the other list based on the pool query_gen
5909 * value. After query finishes, add counter the list to the global
5910 * container counter list. The list changes while query starts. In
5911 * this case, lock will not be needed as query callback and release
5912 * function both operate with the different list.
5915 if (!priv->sh->cmng.counter_fallback) {
5916 rte_spinlock_lock(&pool->csl);
5917 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5918 rte_spinlock_unlock(&pool->csl);
5920 cnt->dcs_when_free = cnt->dcs_when_active;
5921 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5922 MLX5_COUNTER_TYPE_ORIGIN;
5923 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5924 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5926 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5931 * Verify the @p attributes will be correctly understood by the NIC and store
5932 * them in the @p flow if everything is correct.
5935 * Pointer to dev struct.
5936 * @param[in] attributes
5937 * Pointer to flow attributes
5938 * @param[in] external
5939 * This flow rule is created by request external to PMD.
5941 * Pointer to error structure.
5944 * - 0 on success and non root table.
5945 * - 1 on success and root table.
5946 * - a negative errno value otherwise and rte_errno is set.
5949 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5950 const struct mlx5_flow_tunnel *tunnel,
5951 const struct rte_flow_attr *attributes,
5952 const struct flow_grp_info *grp_info,
5953 struct rte_flow_error *error)
5955 struct mlx5_priv *priv = dev->data->dev_private;
5956 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5959 #ifndef HAVE_MLX5DV_DR
5960 RTE_SET_USED(tunnel);
5961 RTE_SET_USED(grp_info);
5962 if (attributes->group)
5963 return rte_flow_error_set(error, ENOTSUP,
5964 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5966 "groups are not supported");
5970 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5975 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5977 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5978 attributes->priority > lowest_priority)
5979 return rte_flow_error_set(error, ENOTSUP,
5980 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5982 "priority out of range");
5983 if (attributes->transfer) {
5984 if (!priv->config.dv_esw_en)
5985 return rte_flow_error_set
5987 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5988 "E-Switch dr is not supported");
5989 if (!(priv->representor || priv->master))
5990 return rte_flow_error_set
5991 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5992 NULL, "E-Switch configuration can only be"
5993 " done by a master or a representor device");
5994 if (attributes->egress)
5995 return rte_flow_error_set
5997 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5998 "egress is not supported");
6000 if (!(attributes->egress ^ attributes->ingress))
6001 return rte_flow_error_set(error, ENOTSUP,
6002 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6003 "must specify exactly one of "
6004 "ingress or egress");
6009 * Internal validation function. For validating both actions and items.
6012 * Pointer to the rte_eth_dev structure.
6014 * Pointer to the flow attributes.
6016 * Pointer to the list of items.
6017 * @param[in] actions
6018 * Pointer to the list of actions.
6019 * @param[in] external
6020 * This flow rule is created by request external to PMD.
6021 * @param[in] hairpin
6022 * Number of hairpin TX actions, 0 means classic flow.
6024 * Pointer to the error structure.
6027 * 0 on success, a negative errno value otherwise and rte_errno is set.
6030 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6031 const struct rte_flow_item items[],
6032 const struct rte_flow_action actions[],
6033 bool external, int hairpin, struct rte_flow_error *error)
6036 uint64_t action_flags = 0;
6037 uint64_t item_flags = 0;
6038 uint64_t last_item = 0;
6039 uint8_t next_protocol = 0xff;
6040 uint16_t ether_type = 0;
6042 uint8_t item_ipv6_proto = 0;
6043 int fdb_mirror_limit = 0;
6044 int modify_after_mirror = 0;
6045 const struct rte_flow_item *geneve_item = NULL;
6046 const struct rte_flow_item *gre_item = NULL;
6047 const struct rte_flow_item *gtp_item = NULL;
6048 const struct rte_flow_action_raw_decap *decap;
6049 const struct rte_flow_action_raw_encap *encap;
6050 const struct rte_flow_action_rss *rss = NULL;
6051 const struct rte_flow_action_rss *sample_rss = NULL;
6052 const struct rte_flow_action_count *count = NULL;
6053 const struct rte_flow_action_count *sample_count = NULL;
6054 const struct rte_flow_item_tcp nic_tcp_mask = {
6057 .src_port = RTE_BE16(UINT16_MAX),
6058 .dst_port = RTE_BE16(UINT16_MAX),
6061 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6064 "\xff\xff\xff\xff\xff\xff\xff\xff"
6065 "\xff\xff\xff\xff\xff\xff\xff\xff",
6067 "\xff\xff\xff\xff\xff\xff\xff\xff"
6068 "\xff\xff\xff\xff\xff\xff\xff\xff",
6069 .vtc_flow = RTE_BE32(0xffffffff),
6075 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6079 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6083 .dummy[0] = 0xffffffff,
6086 struct mlx5_priv *priv = dev->data->dev_private;
6087 struct mlx5_dev_config *dev_conf = &priv->config;
6088 uint16_t queue_index = 0xFFFF;
6089 const struct rte_flow_item_vlan *vlan_m = NULL;
6090 uint32_t rw_act_num = 0;
6092 const struct mlx5_flow_tunnel *tunnel;
6093 struct flow_grp_info grp_info = {
6094 .external = !!external,
6095 .transfer = !!attr->transfer,
6096 .fdb_def_rule = !!priv->fdb_def_rule,
6098 const struct rte_eth_hairpin_conf *conf;
6102 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6103 tunnel = flow_items_to_tunnel(items);
6104 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6105 MLX5_FLOW_ACTION_DECAP;
6106 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6107 tunnel = flow_actions_to_tunnel(actions);
6108 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6112 if (tunnel && priv->representor)
6113 return rte_flow_error_set(error, ENOTSUP,
6114 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6115 "decap not supported "
6116 "for VF representor");
6117 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6118 (dev, tunnel, attr, items, actions);
6119 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6122 is_root = (uint64_t)ret;
6123 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6124 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6125 int type = items->type;
6127 if (!mlx5_flow_os_item_supported(type))
6128 return rte_flow_error_set(error, ENOTSUP,
6129 RTE_FLOW_ERROR_TYPE_ITEM,
6130 NULL, "item not supported");
6132 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6133 if (items[0].type != (typeof(items[0].type))
6134 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6135 return rte_flow_error_set
6137 RTE_FLOW_ERROR_TYPE_ITEM,
6138 NULL, "MLX5 private items "
6139 "must be the first");
6141 case RTE_FLOW_ITEM_TYPE_VOID:
6143 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6144 ret = flow_dv_validate_item_port_id
6145 (dev, items, attr, item_flags, error);
6148 last_item = MLX5_FLOW_ITEM_PORT_ID;
6150 case RTE_FLOW_ITEM_TYPE_ETH:
6151 ret = mlx5_flow_validate_item_eth(items, item_flags,
6155 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6156 MLX5_FLOW_LAYER_OUTER_L2;
6157 if (items->mask != NULL && items->spec != NULL) {
6159 ((const struct rte_flow_item_eth *)
6162 ((const struct rte_flow_item_eth *)
6164 ether_type = rte_be_to_cpu_16(ether_type);
6169 case RTE_FLOW_ITEM_TYPE_VLAN:
6170 ret = flow_dv_validate_item_vlan(items, item_flags,
6174 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6175 MLX5_FLOW_LAYER_OUTER_VLAN;
6176 if (items->mask != NULL && items->spec != NULL) {
6178 ((const struct rte_flow_item_vlan *)
6179 items->spec)->inner_type;
6181 ((const struct rte_flow_item_vlan *)
6182 items->mask)->inner_type;
6183 ether_type = rte_be_to_cpu_16(ether_type);
6187 /* Store outer VLAN mask for of_push_vlan action. */
6189 vlan_m = items->mask;
6191 case RTE_FLOW_ITEM_TYPE_IPV4:
6192 mlx5_flow_tunnel_ip_check(items, next_protocol,
6193 &item_flags, &tunnel);
6194 ret = flow_dv_validate_item_ipv4(items, item_flags,
6195 last_item, ether_type,
6199 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6200 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6201 if (items->mask != NULL &&
6202 ((const struct rte_flow_item_ipv4 *)
6203 items->mask)->hdr.next_proto_id) {
6205 ((const struct rte_flow_item_ipv4 *)
6206 (items->spec))->hdr.next_proto_id;
6208 ((const struct rte_flow_item_ipv4 *)
6209 (items->mask))->hdr.next_proto_id;
6211 /* Reset for inner layer. */
6212 next_protocol = 0xff;
6215 case RTE_FLOW_ITEM_TYPE_IPV6:
6216 mlx5_flow_tunnel_ip_check(items, next_protocol,
6217 &item_flags, &tunnel);
6218 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6225 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6226 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6227 if (items->mask != NULL &&
6228 ((const struct rte_flow_item_ipv6 *)
6229 items->mask)->hdr.proto) {
6231 ((const struct rte_flow_item_ipv6 *)
6232 items->spec)->hdr.proto;
6234 ((const struct rte_flow_item_ipv6 *)
6235 items->spec)->hdr.proto;
6237 ((const struct rte_flow_item_ipv6 *)
6238 items->mask)->hdr.proto;
6240 /* Reset for inner layer. */
6241 next_protocol = 0xff;
6244 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6245 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6250 last_item = tunnel ?
6251 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6252 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6253 if (items->mask != NULL &&
6254 ((const struct rte_flow_item_ipv6_frag_ext *)
6255 items->mask)->hdr.next_header) {
6257 ((const struct rte_flow_item_ipv6_frag_ext *)
6258 items->spec)->hdr.next_header;
6260 ((const struct rte_flow_item_ipv6_frag_ext *)
6261 items->mask)->hdr.next_header;
6263 /* Reset for inner layer. */
6264 next_protocol = 0xff;
6267 case RTE_FLOW_ITEM_TYPE_TCP:
6268 ret = mlx5_flow_validate_item_tcp
6275 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6276 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6278 case RTE_FLOW_ITEM_TYPE_UDP:
6279 ret = mlx5_flow_validate_item_udp(items, item_flags,
6284 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6285 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6287 case RTE_FLOW_ITEM_TYPE_GRE:
6288 ret = mlx5_flow_validate_item_gre(items, item_flags,
6289 next_protocol, error);
6293 last_item = MLX5_FLOW_LAYER_GRE;
6295 case RTE_FLOW_ITEM_TYPE_NVGRE:
6296 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6301 last_item = MLX5_FLOW_LAYER_NVGRE;
6303 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6304 ret = mlx5_flow_validate_item_gre_key
6305 (items, item_flags, gre_item, error);
6308 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6310 case RTE_FLOW_ITEM_TYPE_VXLAN:
6311 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6315 last_item = MLX5_FLOW_LAYER_VXLAN;
6317 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6318 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6323 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6325 case RTE_FLOW_ITEM_TYPE_GENEVE:
6326 ret = mlx5_flow_validate_item_geneve(items,
6331 geneve_item = items;
6332 last_item = MLX5_FLOW_LAYER_GENEVE;
6334 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6335 ret = mlx5_flow_validate_item_geneve_opt(items,
6342 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6344 case RTE_FLOW_ITEM_TYPE_MPLS:
6345 ret = mlx5_flow_validate_item_mpls(dev, items,
6350 last_item = MLX5_FLOW_LAYER_MPLS;
6353 case RTE_FLOW_ITEM_TYPE_MARK:
6354 ret = flow_dv_validate_item_mark(dev, items, attr,
6358 last_item = MLX5_FLOW_ITEM_MARK;
6360 case RTE_FLOW_ITEM_TYPE_META:
6361 ret = flow_dv_validate_item_meta(dev, items, attr,
6365 last_item = MLX5_FLOW_ITEM_METADATA;
6367 case RTE_FLOW_ITEM_TYPE_ICMP:
6368 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6373 last_item = MLX5_FLOW_LAYER_ICMP;
6375 case RTE_FLOW_ITEM_TYPE_ICMP6:
6376 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6381 item_ipv6_proto = IPPROTO_ICMPV6;
6382 last_item = MLX5_FLOW_LAYER_ICMP6;
6384 case RTE_FLOW_ITEM_TYPE_TAG:
6385 ret = flow_dv_validate_item_tag(dev, items,
6389 last_item = MLX5_FLOW_ITEM_TAG;
6391 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6392 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6394 case RTE_FLOW_ITEM_TYPE_GTP:
6395 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6400 last_item = MLX5_FLOW_LAYER_GTP;
6402 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6403 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6408 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6410 case RTE_FLOW_ITEM_TYPE_ECPRI:
6411 /* Capacity will be checked in the translate stage. */
6412 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6419 last_item = MLX5_FLOW_LAYER_ECPRI;
6422 return rte_flow_error_set(error, ENOTSUP,
6423 RTE_FLOW_ERROR_TYPE_ITEM,
6424 NULL, "item not supported");
6426 item_flags |= last_item;
6428 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6429 int type = actions->type;
6431 if (!mlx5_flow_os_action_supported(type))
6432 return rte_flow_error_set(error, ENOTSUP,
6433 RTE_FLOW_ERROR_TYPE_ACTION,
6435 "action not supported");
6436 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6437 return rte_flow_error_set(error, ENOTSUP,
6438 RTE_FLOW_ERROR_TYPE_ACTION,
6439 actions, "too many actions");
6441 case RTE_FLOW_ACTION_TYPE_VOID:
6443 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6444 ret = flow_dv_validate_action_port_id(dev,
6451 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6454 case RTE_FLOW_ACTION_TYPE_FLAG:
6455 ret = flow_dv_validate_action_flag(dev, action_flags,
6459 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6460 /* Count all modify-header actions as one. */
6461 if (!(action_flags &
6462 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6464 action_flags |= MLX5_FLOW_ACTION_FLAG |
6465 MLX5_FLOW_ACTION_MARK_EXT;
6466 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6467 modify_after_mirror = 1;
6470 action_flags |= MLX5_FLOW_ACTION_FLAG;
6473 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6475 case RTE_FLOW_ACTION_TYPE_MARK:
6476 ret = flow_dv_validate_action_mark(dev, actions,
6481 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6482 /* Count all modify-header actions as one. */
6483 if (!(action_flags &
6484 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6486 action_flags |= MLX5_FLOW_ACTION_MARK |
6487 MLX5_FLOW_ACTION_MARK_EXT;
6488 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6489 modify_after_mirror = 1;
6491 action_flags |= MLX5_FLOW_ACTION_MARK;
6494 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6496 case RTE_FLOW_ACTION_TYPE_SET_META:
6497 ret = flow_dv_validate_action_set_meta(dev, actions,
6502 /* Count all modify-header actions as one action. */
6503 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6505 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6506 modify_after_mirror = 1;
6507 action_flags |= MLX5_FLOW_ACTION_SET_META;
6508 rw_act_num += MLX5_ACT_NUM_SET_META;
6510 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6511 ret = flow_dv_validate_action_set_tag(dev, actions,
6516 /* Count all modify-header actions as one action. */
6517 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6519 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6520 modify_after_mirror = 1;
6521 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6522 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6524 case RTE_FLOW_ACTION_TYPE_DROP:
6525 ret = mlx5_flow_validate_action_drop(action_flags,
6529 action_flags |= MLX5_FLOW_ACTION_DROP;
6532 case RTE_FLOW_ACTION_TYPE_QUEUE:
6533 ret = mlx5_flow_validate_action_queue(actions,
6538 queue_index = ((const struct rte_flow_action_queue *)
6539 (actions->conf))->index;
6540 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6543 case RTE_FLOW_ACTION_TYPE_RSS:
6544 rss = actions->conf;
6545 ret = mlx5_flow_validate_action_rss(actions,
6551 if (rss && sample_rss &&
6552 (sample_rss->level != rss->level ||
6553 sample_rss->types != rss->types))
6554 return rte_flow_error_set(error, ENOTSUP,
6555 RTE_FLOW_ERROR_TYPE_ACTION,
6557 "Can't use the different RSS types "
6558 "or level in the same flow");
6559 if (rss != NULL && rss->queue_num)
6560 queue_index = rss->queue[0];
6561 action_flags |= MLX5_FLOW_ACTION_RSS;
6564 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6566 mlx5_flow_validate_action_default_miss(action_flags,
6570 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6573 case RTE_FLOW_ACTION_TYPE_COUNT:
6574 ret = flow_dv_validate_action_count(dev, actions,
6579 count = actions->conf;
6580 action_flags |= MLX5_FLOW_ACTION_COUNT;
6583 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6584 if (flow_dv_validate_action_pop_vlan(dev,
6590 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6593 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6594 ret = flow_dv_validate_action_push_vlan(dev,
6601 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6604 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6605 ret = flow_dv_validate_action_set_vlan_pcp
6606 (action_flags, actions, error);
6609 /* Count PCP with push_vlan command. */
6610 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6612 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6613 ret = flow_dv_validate_action_set_vlan_vid
6614 (item_flags, action_flags,
6618 /* Count VID with push_vlan command. */
6619 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6620 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6622 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6623 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6624 ret = flow_dv_validate_action_l2_encap(dev,
6630 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6633 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6634 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6635 ret = flow_dv_validate_action_decap(dev, action_flags,
6636 actions, item_flags,
6640 action_flags |= MLX5_FLOW_ACTION_DECAP;
6643 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6644 ret = flow_dv_validate_action_raw_encap_decap
6645 (dev, NULL, actions->conf, attr, &action_flags,
6646 &actions_n, actions, item_flags, error);
6650 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6651 decap = actions->conf;
6652 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6654 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6658 encap = actions->conf;
6660 ret = flow_dv_validate_action_raw_encap_decap
6662 decap ? decap : &empty_decap, encap,
6663 attr, &action_flags, &actions_n,
6664 actions, item_flags, error);
6668 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6669 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6670 ret = flow_dv_validate_action_modify_mac(action_flags,
6676 /* Count all modify-header actions as one action. */
6677 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6679 action_flags |= actions->type ==
6680 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6681 MLX5_FLOW_ACTION_SET_MAC_SRC :
6682 MLX5_FLOW_ACTION_SET_MAC_DST;
6683 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6684 modify_after_mirror = 1;
6686 * Even if the source and destination MAC addresses have
6687 * overlap in the header with 4B alignment, the convert
6688 * function will handle them separately and 4 SW actions
6689 * will be created. And 2 actions will be added each
6690 * time no matter how many bytes of address will be set.
6692 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6694 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6695 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6696 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6702 /* Count all modify-header actions as one action. */
6703 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6705 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6706 modify_after_mirror = 1;
6707 action_flags |= actions->type ==
6708 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6709 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6710 MLX5_FLOW_ACTION_SET_IPV4_DST;
6711 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6713 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6714 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6715 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6721 if (item_ipv6_proto == IPPROTO_ICMPV6)
6722 return rte_flow_error_set(error, ENOTSUP,
6723 RTE_FLOW_ERROR_TYPE_ACTION,
6725 "Can't change header "
6726 "with ICMPv6 proto");
6727 /* Count all modify-header actions as one action. */
6728 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6730 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6731 modify_after_mirror = 1;
6732 action_flags |= actions->type ==
6733 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6734 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6735 MLX5_FLOW_ACTION_SET_IPV6_DST;
6736 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6738 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6739 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6740 ret = flow_dv_validate_action_modify_tp(action_flags,
6746 /* Count all modify-header actions as one action. */
6747 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6749 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6750 modify_after_mirror = 1;
6751 action_flags |= actions->type ==
6752 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6753 MLX5_FLOW_ACTION_SET_TP_SRC :
6754 MLX5_FLOW_ACTION_SET_TP_DST;
6755 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6757 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6758 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6759 ret = flow_dv_validate_action_modify_ttl(action_flags,
6765 /* Count all modify-header actions as one action. */
6766 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6768 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6769 modify_after_mirror = 1;
6770 action_flags |= actions->type ==
6771 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6772 MLX5_FLOW_ACTION_SET_TTL :
6773 MLX5_FLOW_ACTION_DEC_TTL;
6774 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6776 case RTE_FLOW_ACTION_TYPE_JUMP:
6777 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6783 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6785 return rte_flow_error_set(error, EINVAL,
6786 RTE_FLOW_ERROR_TYPE_ACTION,
6788 "sample and jump action combination is not supported");
6790 action_flags |= MLX5_FLOW_ACTION_JUMP;
6792 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6793 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6794 ret = flow_dv_validate_action_modify_tcp_seq
6801 /* Count all modify-header actions as one action. */
6802 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6804 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6805 modify_after_mirror = 1;
6806 action_flags |= actions->type ==
6807 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6808 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6809 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6810 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6812 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6813 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6814 ret = flow_dv_validate_action_modify_tcp_ack
6821 /* Count all modify-header actions as one action. */
6822 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6824 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6825 modify_after_mirror = 1;
6826 action_flags |= actions->type ==
6827 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6828 MLX5_FLOW_ACTION_INC_TCP_ACK :
6829 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6830 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6832 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6834 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6835 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6836 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6838 case RTE_FLOW_ACTION_TYPE_METER:
6839 ret = mlx5_flow_validate_action_meter(dev,
6845 action_flags |= MLX5_FLOW_ACTION_METER;
6847 /* Meter action will add one more TAG action. */
6848 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6850 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6851 if (!attr->transfer && !attr->group)
6852 return rte_flow_error_set(error, ENOTSUP,
6853 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6855 "Shared ASO age action is not supported for group 0");
6856 action_flags |= MLX5_FLOW_ACTION_AGE;
6859 case RTE_FLOW_ACTION_TYPE_AGE:
6860 ret = flow_dv_validate_action_age(action_flags,
6866 * Validate the regular AGE action (using counter)
6867 * mutual exclusion with share counter actions.
6869 if (!priv->sh->flow_hit_aso_en) {
6870 if (count && count->shared)
6871 return rte_flow_error_set
6873 RTE_FLOW_ERROR_TYPE_ACTION,
6875 "old age and shared count combination is not supported");
6877 return rte_flow_error_set
6879 RTE_FLOW_ERROR_TYPE_ACTION,
6881 "old age action and count must be in the same sub flow");
6883 action_flags |= MLX5_FLOW_ACTION_AGE;
6886 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6887 ret = flow_dv_validate_action_modify_ipv4_dscp
6894 /* Count all modify-header actions as one action. */
6895 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6897 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6898 modify_after_mirror = 1;
6899 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6900 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6902 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6903 ret = flow_dv_validate_action_modify_ipv6_dscp
6910 /* Count all modify-header actions as one action. */
6911 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6913 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6914 modify_after_mirror = 1;
6915 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6916 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6918 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6919 ret = flow_dv_validate_action_sample(&action_flags,
6928 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6931 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6932 if (actions[0].type != (typeof(actions[0].type))
6933 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6934 return rte_flow_error_set
6936 RTE_FLOW_ERROR_TYPE_ACTION,
6937 NULL, "MLX5 private action "
6938 "must be the first");
6940 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6942 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6943 ret = flow_dv_validate_action_modify_field(dev,
6950 /* Count all modify-header actions as one action. */
6951 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6953 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6957 return rte_flow_error_set(error, ENOTSUP,
6958 RTE_FLOW_ERROR_TYPE_ACTION,
6960 "action not supported");
6964 * Validate actions in flow rules
6965 * - Explicit decap action is prohibited by the tunnel offload API.
6966 * - Drop action in tunnel steer rule is prohibited by the API.
6967 * - Application cannot use MARK action because it's value can mask
6968 * tunnel default miss nitification.
6969 * - JUMP in tunnel match rule has no support in current PMD
6971 * - TAG & META are reserved for future uses.
6973 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6974 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6975 MLX5_FLOW_ACTION_MARK |
6976 MLX5_FLOW_ACTION_SET_TAG |
6977 MLX5_FLOW_ACTION_SET_META |
6978 MLX5_FLOW_ACTION_DROP;
6980 if (action_flags & bad_actions_mask)
6981 return rte_flow_error_set
6983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6984 "Invalid RTE action in tunnel "
6986 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6987 return rte_flow_error_set
6989 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6990 "tunnel set decap rule must terminate "
6993 return rte_flow_error_set
6995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6996 "tunnel flows for ingress traffic only");
6998 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6999 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7000 MLX5_FLOW_ACTION_MARK |
7001 MLX5_FLOW_ACTION_SET_TAG |
7002 MLX5_FLOW_ACTION_SET_META;
7004 if (action_flags & bad_actions_mask)
7005 return rte_flow_error_set
7007 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7008 "Invalid RTE action in tunnel "
7012 * Validate the drop action mutual exclusion with other actions.
7013 * Drop action is mutually-exclusive with any other action, except for
7015 * Drop action compatibility with tunnel offload was already validated.
7017 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7018 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7019 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7020 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7021 return rte_flow_error_set(error, EINVAL,
7022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7023 "Drop action is mutually-exclusive "
7024 "with any other action, except for "
7026 /* Eswitch has few restrictions on using items and actions */
7027 if (attr->transfer) {
7028 if (!mlx5_flow_ext_mreg_supported(dev) &&
7029 action_flags & MLX5_FLOW_ACTION_FLAG)
7030 return rte_flow_error_set(error, ENOTSUP,
7031 RTE_FLOW_ERROR_TYPE_ACTION,
7033 "unsupported action FLAG");
7034 if (!mlx5_flow_ext_mreg_supported(dev) &&
7035 action_flags & MLX5_FLOW_ACTION_MARK)
7036 return rte_flow_error_set(error, ENOTSUP,
7037 RTE_FLOW_ERROR_TYPE_ACTION,
7039 "unsupported action MARK");
7040 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7041 return rte_flow_error_set(error, ENOTSUP,
7042 RTE_FLOW_ERROR_TYPE_ACTION,
7044 "unsupported action QUEUE");
7045 if (action_flags & MLX5_FLOW_ACTION_RSS)
7046 return rte_flow_error_set(error, ENOTSUP,
7047 RTE_FLOW_ERROR_TYPE_ACTION,
7049 "unsupported action RSS");
7050 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7051 return rte_flow_error_set(error, EINVAL,
7052 RTE_FLOW_ERROR_TYPE_ACTION,
7054 "no fate action is found");
7056 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7057 return rte_flow_error_set(error, EINVAL,
7058 RTE_FLOW_ERROR_TYPE_ACTION,
7060 "no fate action is found");
7063 * Continue validation for Xcap and VLAN actions.
7064 * If hairpin is working in explicit TX rule mode, there is no actions
7065 * splitting and the validation of hairpin ingress flow should be the
7066 * same as other standard flows.
7068 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7069 MLX5_FLOW_VLAN_ACTIONS)) &&
7070 (queue_index == 0xFFFF ||
7071 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7072 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7073 conf->tx_explicit != 0))) {
7074 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7075 MLX5_FLOW_XCAP_ACTIONS)
7076 return rte_flow_error_set(error, ENOTSUP,
7077 RTE_FLOW_ERROR_TYPE_ACTION,
7078 NULL, "encap and decap "
7079 "combination aren't supported");
7080 if (!attr->transfer && attr->ingress) {
7081 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7082 return rte_flow_error_set
7084 RTE_FLOW_ERROR_TYPE_ACTION,
7085 NULL, "encap is not supported"
7086 " for ingress traffic");
7087 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7088 return rte_flow_error_set
7090 RTE_FLOW_ERROR_TYPE_ACTION,
7091 NULL, "push VLAN action not "
7092 "supported for ingress");
7093 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7094 MLX5_FLOW_VLAN_ACTIONS)
7095 return rte_flow_error_set
7097 RTE_FLOW_ERROR_TYPE_ACTION,
7098 NULL, "no support for "
7099 "multiple VLAN actions");
7103 * Hairpin flow will add one more TAG action in TX implicit mode.
7104 * In TX explicit mode, there will be no hairpin flow ID.
7107 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7108 /* extra metadata enabled: one more TAG action will be add. */
7109 if (dev_conf->dv_flow_en &&
7110 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7111 mlx5_flow_ext_mreg_supported(dev))
7112 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7114 flow_dv_modify_hdr_action_max(dev, is_root)) {
7115 return rte_flow_error_set(error, ENOTSUP,
7116 RTE_FLOW_ERROR_TYPE_ACTION,
7117 NULL, "too many header modify"
7118 " actions to support");
7120 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7121 if (fdb_mirror_limit && modify_after_mirror)
7122 return rte_flow_error_set(error, EINVAL,
7123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7124 "sample before modify action is not supported");
7129 * Internal preparation function. Allocates the DV flow size,
7130 * this size is constant.
7133 * Pointer to the rte_eth_dev structure.
7135 * Pointer to the flow attributes.
7137 * Pointer to the list of items.
7138 * @param[in] actions
7139 * Pointer to the list of actions.
7141 * Pointer to the error structure.
7144 * Pointer to mlx5_flow object on success,
7145 * otherwise NULL and rte_errno is set.
7147 static struct mlx5_flow *
7148 flow_dv_prepare(struct rte_eth_dev *dev,
7149 const struct rte_flow_attr *attr __rte_unused,
7150 const struct rte_flow_item items[] __rte_unused,
7151 const struct rte_flow_action actions[] __rte_unused,
7152 struct rte_flow_error *error)
7154 uint32_t handle_idx = 0;
7155 struct mlx5_flow *dev_flow;
7156 struct mlx5_flow_handle *dev_handle;
7157 struct mlx5_priv *priv = dev->data->dev_private;
7158 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7161 /* In case of corrupting the memory. */
7162 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7163 rte_flow_error_set(error, ENOSPC,
7164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7165 "not free temporary device flow");
7168 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7171 rte_flow_error_set(error, ENOMEM,
7172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7173 "not enough memory to create flow handle");
7176 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7177 dev_flow = &wks->flows[wks->flow_idx++];
7178 memset(dev_flow, 0, sizeof(*dev_flow));
7179 dev_flow->handle = dev_handle;
7180 dev_flow->handle_idx = handle_idx;
7182 * In some old rdma-core releases, before continuing, a check of the
7183 * length of matching parameter will be done at first. It needs to use
7184 * the length without misc4 param. If the flow has misc4 support, then
7185 * the length needs to be adjusted accordingly. Each param member is
7186 * aligned with a 64B boundary naturally.
7188 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7189 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7190 dev_flow->ingress = attr->ingress;
7191 dev_flow->dv.transfer = attr->transfer;
7195 #ifdef RTE_LIBRTE_MLX5_DEBUG
7197 * Sanity check for match mask and value. Similar to check_valid_spec() in
7198 * kernel driver. If unmasked bit is present in value, it returns failure.
7201 * pointer to match mask buffer.
7202 * @param match_value
7203 * pointer to match value buffer.
7206 * 0 if valid, -EINVAL otherwise.
7209 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7211 uint8_t *m = match_mask;
7212 uint8_t *v = match_value;
7215 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7218 "match_value differs from match_criteria"
7219 " %p[%u] != %p[%u]",
7220 match_value, i, match_mask, i);
7229 * Add match of ip_version.
7233 * @param[in] headers_v
7234 * Values header pointer.
7235 * @param[in] headers_m
7236 * Masks header pointer.
7237 * @param[in] ip_version
7238 * The IP version to set.
7241 flow_dv_set_match_ip_version(uint32_t group,
7247 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7249 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7251 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7252 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7253 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7257 * Add Ethernet item to matcher and to the value.
7259 * @param[in, out] matcher
7261 * @param[in, out] key
7262 * Flow matcher value.
7264 * Flow pattern to translate.
7266 * Item is inner pattern.
7269 flow_dv_translate_item_eth(void *matcher, void *key,
7270 const struct rte_flow_item *item, int inner,
7273 const struct rte_flow_item_eth *eth_m = item->mask;
7274 const struct rte_flow_item_eth *eth_v = item->spec;
7275 const struct rte_flow_item_eth nic_mask = {
7276 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7277 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7278 .type = RTE_BE16(0xffff),
7291 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7293 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7295 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7297 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7299 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7300 ð_m->dst, sizeof(eth_m->dst));
7301 /* The value must be in the range of the mask. */
7302 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7303 for (i = 0; i < sizeof(eth_m->dst); ++i)
7304 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7305 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7306 ð_m->src, sizeof(eth_m->src));
7307 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7308 /* The value must be in the range of the mask. */
7309 for (i = 0; i < sizeof(eth_m->dst); ++i)
7310 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7312 * HW supports match on one Ethertype, the Ethertype following the last
7313 * VLAN tag of the packet (see PRM).
7314 * Set match on ethertype only if ETH header is not followed by VLAN.
7315 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7316 * ethertype, and use ip_version field instead.
7317 * eCPRI over Ether layer will use type value 0xAEFE.
7319 if (eth_m->type == 0xFFFF) {
7320 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7321 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7322 switch (eth_v->type) {
7323 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7326 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7327 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7328 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7330 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7331 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7333 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7334 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7340 if (eth_m->has_vlan) {
7341 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7342 if (eth_v->has_vlan) {
7344 * Here, when also has_more_vlan field in VLAN item is
7345 * not set, only single-tagged packets will be matched.
7347 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7351 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7352 rte_be_to_cpu_16(eth_m->type));
7353 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7354 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7358 * Add VLAN item to matcher and to the value.
7360 * @param[in, out] dev_flow
7362 * @param[in, out] matcher
7364 * @param[in, out] key
7365 * Flow matcher value.
7367 * Flow pattern to translate.
7369 * Item is inner pattern.
7372 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7373 void *matcher, void *key,
7374 const struct rte_flow_item *item,
7375 int inner, uint32_t group)
7377 const struct rte_flow_item_vlan *vlan_m = item->mask;
7378 const struct rte_flow_item_vlan *vlan_v = item->spec;
7385 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7387 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7389 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7391 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7393 * This is workaround, masks are not supported,
7394 * and pre-validated.
7397 dev_flow->handle->vf_vlan.tag =
7398 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7401 * When VLAN item exists in flow, mark packet as tagged,
7402 * even if TCI is not specified.
7404 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7405 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7406 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7411 vlan_m = &rte_flow_item_vlan_mask;
7412 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7413 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7414 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7415 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7416 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7417 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7418 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7419 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7421 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7422 * ethertype, and use ip_version field instead.
7424 if (vlan_m->inner_type == 0xFFFF) {
7425 switch (vlan_v->inner_type) {
7426 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7427 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7428 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7429 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7431 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7432 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7434 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7435 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7441 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7442 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7443 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7444 /* Only one vlan_tag bit can be set. */
7445 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7448 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7449 rte_be_to_cpu_16(vlan_m->inner_type));
7450 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7451 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7455 * Add IPV4 item to matcher and to the value.
7457 * @param[in, out] matcher
7459 * @param[in, out] key
7460 * Flow matcher value.
7462 * Flow pattern to translate.
7464 * Item is inner pattern.
7466 * The group to insert the rule.
7469 flow_dv_translate_item_ipv4(void *matcher, void *key,
7470 const struct rte_flow_item *item,
7471 int inner, uint32_t group)
7473 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7474 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7475 const struct rte_flow_item_ipv4 nic_mask = {
7477 .src_addr = RTE_BE32(0xffffffff),
7478 .dst_addr = RTE_BE32(0xffffffff),
7479 .type_of_service = 0xff,
7480 .next_proto_id = 0xff,
7481 .time_to_live = 0xff,
7491 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7493 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7495 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7497 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7499 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7504 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7505 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7506 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7507 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7508 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7509 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7510 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7511 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7512 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7513 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7514 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7515 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7516 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7517 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7518 ipv4_m->hdr.type_of_service);
7519 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7520 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7521 ipv4_m->hdr.type_of_service >> 2);
7522 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7523 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7524 ipv4_m->hdr.next_proto_id);
7525 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7526 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7528 ipv4_m->hdr.time_to_live);
7529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7530 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7531 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7532 !!(ipv4_m->hdr.fragment_offset));
7533 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7534 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7538 * Add IPV6 item to matcher and to the value.
7540 * @param[in, out] matcher
7542 * @param[in, out] key
7543 * Flow matcher value.
7545 * Flow pattern to translate.
7547 * Item is inner pattern.
7549 * The group to insert the rule.
7552 flow_dv_translate_item_ipv6(void *matcher, void *key,
7553 const struct rte_flow_item *item,
7554 int inner, uint32_t group)
7556 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7557 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7558 const struct rte_flow_item_ipv6 nic_mask = {
7561 "\xff\xff\xff\xff\xff\xff\xff\xff"
7562 "\xff\xff\xff\xff\xff\xff\xff\xff",
7564 "\xff\xff\xff\xff\xff\xff\xff\xff"
7565 "\xff\xff\xff\xff\xff\xff\xff\xff",
7566 .vtc_flow = RTE_BE32(0xffffffff),
7573 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7574 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7583 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7585 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7587 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7589 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7591 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7596 size = sizeof(ipv6_m->hdr.dst_addr);
7597 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7598 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7599 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7600 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7601 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7602 for (i = 0; i < size; ++i)
7603 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7604 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7605 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7606 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7607 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7608 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7609 for (i = 0; i < size; ++i)
7610 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7612 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7613 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7614 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7615 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7616 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7617 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7620 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7622 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7625 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7627 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7631 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7633 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7634 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7636 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7637 ipv6_m->hdr.hop_limits);
7638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7639 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7640 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7641 !!(ipv6_m->has_frag_ext));
7642 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7643 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7647 * Add IPV6 fragment extension item to matcher and to the value.
7649 * @param[in, out] matcher
7651 * @param[in, out] key
7652 * Flow matcher value.
7654 * Flow pattern to translate.
7656 * Item is inner pattern.
7659 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7660 const struct rte_flow_item *item,
7663 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7664 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7665 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7667 .next_header = 0xff,
7668 .frag_data = RTE_BE16(0xffff),
7675 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7677 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7679 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7681 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7683 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7686 if (!ipv6_frag_ext_v)
7688 if (!ipv6_frag_ext_m)
7689 ipv6_frag_ext_m = &nic_mask;
7690 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7691 ipv6_frag_ext_m->hdr.next_header);
7692 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7693 ipv6_frag_ext_v->hdr.next_header &
7694 ipv6_frag_ext_m->hdr.next_header);
7698 * Add TCP item to matcher and to the value.
7700 * @param[in, out] matcher
7702 * @param[in, out] key
7703 * Flow matcher value.
7705 * Flow pattern to translate.
7707 * Item is inner pattern.
7710 flow_dv_translate_item_tcp(void *matcher, void *key,
7711 const struct rte_flow_item *item,
7714 const struct rte_flow_item_tcp *tcp_m = item->mask;
7715 const struct rte_flow_item_tcp *tcp_v = item->spec;
7720 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7722 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7724 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7726 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7728 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7729 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7733 tcp_m = &rte_flow_item_tcp_mask;
7734 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7735 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7737 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7738 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7739 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7740 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7741 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7742 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7743 tcp_m->hdr.tcp_flags);
7744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7745 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7749 * Add UDP item to matcher and to the value.
7751 * @param[in, out] matcher
7753 * @param[in, out] key
7754 * Flow matcher value.
7756 * Flow pattern to translate.
7758 * Item is inner pattern.
7761 flow_dv_translate_item_udp(void *matcher, void *key,
7762 const struct rte_flow_item *item,
7765 const struct rte_flow_item_udp *udp_m = item->mask;
7766 const struct rte_flow_item_udp *udp_v = item->spec;
7771 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7773 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7775 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7777 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7779 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7780 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7784 udp_m = &rte_flow_item_udp_mask;
7785 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7786 rte_be_to_cpu_16(udp_m->hdr.src_port));
7787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7788 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7789 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7790 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7791 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7792 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7796 * Add GRE optional Key item to matcher and to the value.
7798 * @param[in, out] matcher
7800 * @param[in, out] key
7801 * Flow matcher value.
7803 * Flow pattern to translate.
7805 * Item is inner pattern.
7808 flow_dv_translate_item_gre_key(void *matcher, void *key,
7809 const struct rte_flow_item *item)
7811 const rte_be32_t *key_m = item->mask;
7812 const rte_be32_t *key_v = item->spec;
7813 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7814 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7815 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7817 /* GRE K bit must be on and should already be validated */
7818 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7819 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7823 key_m = &gre_key_default_mask;
7824 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7825 rte_be_to_cpu_32(*key_m) >> 8);
7826 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7827 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7828 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7829 rte_be_to_cpu_32(*key_m) & 0xFF);
7830 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7831 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7835 * Add GRE item to matcher and to the value.
7837 * @param[in, out] matcher
7839 * @param[in, out] key
7840 * Flow matcher value.
7842 * Flow pattern to translate.
7844 * Item is inner pattern.
7847 flow_dv_translate_item_gre(void *matcher, void *key,
7848 const struct rte_flow_item *item,
7851 const struct rte_flow_item_gre *gre_m = item->mask;
7852 const struct rte_flow_item_gre *gre_v = item->spec;
7855 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7856 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7863 uint16_t s_present:1;
7864 uint16_t k_present:1;
7865 uint16_t rsvd_bit1:1;
7866 uint16_t c_present:1;
7870 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7873 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7875 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7877 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7879 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7881 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7886 gre_m = &rte_flow_item_gre_mask;
7887 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7888 rte_be_to_cpu_16(gre_m->protocol));
7889 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7890 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7891 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7892 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7893 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7894 gre_crks_rsvd0_ver_m.c_present);
7895 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7896 gre_crks_rsvd0_ver_v.c_present &
7897 gre_crks_rsvd0_ver_m.c_present);
7898 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7899 gre_crks_rsvd0_ver_m.k_present);
7900 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7901 gre_crks_rsvd0_ver_v.k_present &
7902 gre_crks_rsvd0_ver_m.k_present);
7903 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7904 gre_crks_rsvd0_ver_m.s_present);
7905 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7906 gre_crks_rsvd0_ver_v.s_present &
7907 gre_crks_rsvd0_ver_m.s_present);
7911 * Add NVGRE item to matcher and to the value.
7913 * @param[in, out] matcher
7915 * @param[in, out] key
7916 * Flow matcher value.
7918 * Flow pattern to translate.
7920 * Item is inner pattern.
7923 flow_dv_translate_item_nvgre(void *matcher, void *key,
7924 const struct rte_flow_item *item,
7927 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7928 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7929 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7930 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7931 const char *tni_flow_id_m;
7932 const char *tni_flow_id_v;
7938 /* For NVGRE, GRE header fields must be set with defined values. */
7939 const struct rte_flow_item_gre gre_spec = {
7940 .c_rsvd0_ver = RTE_BE16(0x2000),
7941 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7943 const struct rte_flow_item_gre gre_mask = {
7944 .c_rsvd0_ver = RTE_BE16(0xB000),
7945 .protocol = RTE_BE16(UINT16_MAX),
7947 const struct rte_flow_item gre_item = {
7952 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7956 nvgre_m = &rte_flow_item_nvgre_mask;
7957 tni_flow_id_m = (const char *)nvgre_m->tni;
7958 tni_flow_id_v = (const char *)nvgre_v->tni;
7959 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7960 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7961 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7962 memcpy(gre_key_m, tni_flow_id_m, size);
7963 for (i = 0; i < size; ++i)
7964 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7968 * Add VXLAN item to matcher and to the value.
7970 * @param[in, out] matcher
7972 * @param[in, out] key
7973 * Flow matcher value.
7975 * Flow pattern to translate.
7977 * Item is inner pattern.
7980 flow_dv_translate_item_vxlan(void *matcher, void *key,
7981 const struct rte_flow_item *item,
7984 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7985 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7988 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7989 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7997 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7999 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8001 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8003 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8005 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8006 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8007 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8008 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8009 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8014 vxlan_m = &rte_flow_item_vxlan_mask;
8015 size = sizeof(vxlan_m->vni);
8016 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8017 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8018 memcpy(vni_m, vxlan_m->vni, size);
8019 for (i = 0; i < size; ++i)
8020 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8024 * Add VXLAN-GPE item to matcher and to the value.
8026 * @param[in, out] matcher
8028 * @param[in, out] key
8029 * Flow matcher value.
8031 * Flow pattern to translate.
8033 * Item is inner pattern.
8037 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8038 const struct rte_flow_item *item, int inner)
8040 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8041 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8045 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8047 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8053 uint8_t flags_m = 0xff;
8054 uint8_t flags_v = 0xc;
8057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8059 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8061 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8063 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8065 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8066 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8067 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8068 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8069 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8074 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8075 size = sizeof(vxlan_m->vni);
8076 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8077 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8078 memcpy(vni_m, vxlan_m->vni, size);
8079 for (i = 0; i < size; ++i)
8080 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8081 if (vxlan_m->flags) {
8082 flags_m = vxlan_m->flags;
8083 flags_v = vxlan_v->flags;
8085 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8086 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8087 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8089 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8094 * Add Geneve item to matcher and to the value.
8096 * @param[in, out] matcher
8098 * @param[in, out] key
8099 * Flow matcher value.
8101 * Flow pattern to translate.
8103 * Item is inner pattern.
8107 flow_dv_translate_item_geneve(void *matcher, void *key,
8108 const struct rte_flow_item *item, int inner)
8110 const struct rte_flow_item_geneve *geneve_m = item->mask;
8111 const struct rte_flow_item_geneve *geneve_v = item->spec;
8114 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8115 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8124 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8126 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8128 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8130 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8132 dport = MLX5_UDP_PORT_GENEVE;
8133 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8134 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8135 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8140 geneve_m = &rte_flow_item_geneve_mask;
8141 size = sizeof(geneve_m->vni);
8142 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8143 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8144 memcpy(vni_m, geneve_m->vni, size);
8145 for (i = 0; i < size; ++i)
8146 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8147 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8148 rte_be_to_cpu_16(geneve_m->protocol));
8149 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8150 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8151 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8152 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8153 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8154 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8155 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8156 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8157 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8158 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8159 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8160 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8161 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8165 * Create Geneve TLV option resource.
8167 * @param dev[in, out]
8168 * Pointer to rte_eth_dev structure.
8169 * @param[in, out] tag_be24
8170 * Tag value in big endian then R-shift 8.
8171 * @parm[in, out] dev_flow
8172 * Pointer to the dev_flow.
8174 * pointer to error structure.
8177 * 0 on success otherwise -errno and errno is set.
8181 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8182 const struct rte_flow_item *item,
8183 struct rte_flow_error *error)
8185 struct mlx5_priv *priv = dev->data->dev_private;
8186 struct mlx5_dev_ctx_shared *sh = priv->sh;
8187 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8188 sh->geneve_tlv_option_resource;
8189 struct mlx5_devx_obj *obj;
8190 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8195 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8196 if (geneve_opt_resource != NULL) {
8197 if (geneve_opt_resource->option_class ==
8198 geneve_opt_v->option_class &&
8199 geneve_opt_resource->option_type ==
8200 geneve_opt_v->option_type &&
8201 geneve_opt_resource->length ==
8202 geneve_opt_v->option_len) {
8203 /* We already have GENVE TLV option obj allocated. */
8204 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8207 ret = rte_flow_error_set(error, ENOMEM,
8208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8209 "Only one GENEVE TLV option supported");
8213 /* Create a GENEVE TLV object and resource. */
8214 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8215 geneve_opt_v->option_class,
8216 geneve_opt_v->option_type,
8217 geneve_opt_v->option_len);
8219 ret = rte_flow_error_set(error, ENODATA,
8220 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8221 "Failed to create GENEVE TLV Devx object");
8224 sh->geneve_tlv_option_resource =
8225 mlx5_malloc(MLX5_MEM_ZERO,
8226 sizeof(*geneve_opt_resource),
8228 if (!sh->geneve_tlv_option_resource) {
8229 claim_zero(mlx5_devx_cmd_destroy(obj));
8230 ret = rte_flow_error_set(error, ENOMEM,
8231 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8232 "GENEVE TLV object memory allocation failed");
8235 geneve_opt_resource = sh->geneve_tlv_option_resource;
8236 geneve_opt_resource->obj = obj;
8237 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8238 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8239 geneve_opt_resource->length = geneve_opt_v->option_len;
8240 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8244 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8249 * Add Geneve TLV option item to matcher.
8251 * @param[in, out] dev
8252 * Pointer to rte_eth_dev structure.
8253 * @param[in, out] matcher
8255 * @param[in, out] key
8256 * Flow matcher value.
8258 * Flow pattern to translate.
8260 * Pointer to error structure.
8263 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8264 void *key, const struct rte_flow_item *item,
8265 struct rte_flow_error *error)
8267 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8268 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8269 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8270 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8271 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8273 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8274 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8280 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8281 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8284 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8288 * Set the option length in GENEVE header if not requested.
8289 * The GENEVE TLV option length is expressed by the option length field
8290 * in the GENEVE header.
8291 * If the option length was not requested but the GENEVE TLV option item
8292 * is present we set the option length field implicitly.
8294 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8295 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8296 MLX5_GENEVE_OPTLEN_MASK);
8297 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8298 geneve_opt_v->option_len + 1);
8301 if (geneve_opt_v->data) {
8302 memcpy(&opt_data_key, geneve_opt_v->data,
8303 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8304 sizeof(opt_data_key)));
8305 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8306 sizeof(opt_data_key));
8307 memcpy(&opt_data_mask, geneve_opt_m->data,
8308 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8309 sizeof(opt_data_mask)));
8310 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8311 sizeof(opt_data_mask));
8312 MLX5_SET(fte_match_set_misc3, misc3_m,
8313 geneve_tlv_option_0_data,
8314 rte_be_to_cpu_32(opt_data_mask));
8315 MLX5_SET(fte_match_set_misc3, misc3_v,
8316 geneve_tlv_option_0_data,
8317 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8323 * Add MPLS item to matcher and to the value.
8325 * @param[in, out] matcher
8327 * @param[in, out] key
8328 * Flow matcher value.
8330 * Flow pattern to translate.
8331 * @param[in] prev_layer
8332 * The protocol layer indicated in previous item.
8334 * Item is inner pattern.
8337 flow_dv_translate_item_mpls(void *matcher, void *key,
8338 const struct rte_flow_item *item,
8339 uint64_t prev_layer,
8342 const uint32_t *in_mpls_m = item->mask;
8343 const uint32_t *in_mpls_v = item->spec;
8344 uint32_t *out_mpls_m = 0;
8345 uint32_t *out_mpls_v = 0;
8346 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8347 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8348 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8350 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8351 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8352 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8354 switch (prev_layer) {
8355 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8356 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8357 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8358 MLX5_UDP_PORT_MPLS);
8360 case MLX5_FLOW_LAYER_GRE:
8361 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8362 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8363 RTE_ETHER_TYPE_MPLS);
8366 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8374 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8375 switch (prev_layer) {
8376 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8378 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8379 outer_first_mpls_over_udp);
8381 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8382 outer_first_mpls_over_udp);
8384 case MLX5_FLOW_LAYER_GRE:
8386 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8387 outer_first_mpls_over_gre);
8389 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8390 outer_first_mpls_over_gre);
8393 /* Inner MPLS not over GRE is not supported. */
8396 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8400 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8406 if (out_mpls_m && out_mpls_v) {
8407 *out_mpls_m = *in_mpls_m;
8408 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8413 * Add metadata register item to matcher
8415 * @param[in, out] matcher
8417 * @param[in, out] key
8418 * Flow matcher value.
8419 * @param[in] reg_type
8420 * Type of device metadata register
8427 flow_dv_match_meta_reg(void *matcher, void *key,
8428 enum modify_reg reg_type,
8429 uint32_t data, uint32_t mask)
8432 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8434 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8440 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8441 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8444 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8445 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8449 * The metadata register C0 field might be divided into
8450 * source vport index and META item value, we should set
8451 * this field according to specified mask, not as whole one.
8453 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8455 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8456 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8459 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8462 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8463 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8466 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8467 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8470 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8471 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8474 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8475 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8478 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8479 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8482 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8483 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8486 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8487 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8496 * Add MARK item to matcher
8499 * The device to configure through.
8500 * @param[in, out] matcher
8502 * @param[in, out] key
8503 * Flow matcher value.
8505 * Flow pattern to translate.
8508 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8509 void *matcher, void *key,
8510 const struct rte_flow_item *item)
8512 struct mlx5_priv *priv = dev->data->dev_private;
8513 const struct rte_flow_item_mark *mark;
8517 mark = item->mask ? (const void *)item->mask :
8518 &rte_flow_item_mark_mask;
8519 mask = mark->id & priv->sh->dv_mark_mask;
8520 mark = (const void *)item->spec;
8522 value = mark->id & priv->sh->dv_mark_mask & mask;
8524 enum modify_reg reg;
8526 /* Get the metadata register index for the mark. */
8527 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8528 MLX5_ASSERT(reg > 0);
8529 if (reg == REG_C_0) {
8530 struct mlx5_priv *priv = dev->data->dev_private;
8531 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8532 uint32_t shl_c0 = rte_bsf32(msk_c0);
8538 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8543 * Add META item to matcher
8546 * The devich to configure through.
8547 * @param[in, out] matcher
8549 * @param[in, out] key
8550 * Flow matcher value.
8552 * Attributes of flow that includes this item.
8554 * Flow pattern to translate.
8557 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8558 void *matcher, void *key,
8559 const struct rte_flow_attr *attr,
8560 const struct rte_flow_item *item)
8562 const struct rte_flow_item_meta *meta_m;
8563 const struct rte_flow_item_meta *meta_v;
8565 meta_m = (const void *)item->mask;
8567 meta_m = &rte_flow_item_meta_mask;
8568 meta_v = (const void *)item->spec;
8571 uint32_t value = meta_v->data;
8572 uint32_t mask = meta_m->data;
8574 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8577 MLX5_ASSERT(reg != REG_NON);
8579 * In datapath code there is no endianness
8580 * coversions for perfromance reasons, all
8581 * pattern conversions are done in rte_flow.
8583 value = rte_cpu_to_be_32(value);
8584 mask = rte_cpu_to_be_32(mask);
8585 if (reg == REG_C_0) {
8586 struct mlx5_priv *priv = dev->data->dev_private;
8587 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8588 uint32_t shl_c0 = rte_bsf32(msk_c0);
8589 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8590 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8597 MLX5_ASSERT(msk_c0);
8598 MLX5_ASSERT(!(~msk_c0 & mask));
8600 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8605 * Add vport metadata Reg C0 item to matcher
8607 * @param[in, out] matcher
8609 * @param[in, out] key
8610 * Flow matcher value.
8612 * Flow pattern to translate.
8615 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8616 uint32_t value, uint32_t mask)
8618 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8622 * Add tag item to matcher
8625 * The devich to configure through.
8626 * @param[in, out] matcher
8628 * @param[in, out] key
8629 * Flow matcher value.
8631 * Flow pattern to translate.
8634 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8635 void *matcher, void *key,
8636 const struct rte_flow_item *item)
8638 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8639 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8640 uint32_t mask, value;
8643 value = tag_v->data;
8644 mask = tag_m ? tag_m->data : UINT32_MAX;
8645 if (tag_v->id == REG_C_0) {
8646 struct mlx5_priv *priv = dev->data->dev_private;
8647 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8648 uint32_t shl_c0 = rte_bsf32(msk_c0);
8654 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8658 * Add TAG item to matcher
8661 * The devich to configure through.
8662 * @param[in, out] matcher
8664 * @param[in, out] key
8665 * Flow matcher value.
8667 * Flow pattern to translate.
8670 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8671 void *matcher, void *key,
8672 const struct rte_flow_item *item)
8674 const struct rte_flow_item_tag *tag_v = item->spec;
8675 const struct rte_flow_item_tag *tag_m = item->mask;
8676 enum modify_reg reg;
8679 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8680 /* Get the metadata register index for the tag. */
8681 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8682 MLX5_ASSERT(reg > 0);
8683 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8687 * Add source vport match to the specified matcher.
8689 * @param[in, out] matcher
8691 * @param[in, out] key
8692 * Flow matcher value.
8694 * Source vport value to match
8699 flow_dv_translate_item_source_vport(void *matcher, void *key,
8700 int16_t port, uint16_t mask)
8702 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8703 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8705 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8706 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8710 * Translate port-id item to eswitch match on port-id.
8713 * The devich to configure through.
8714 * @param[in, out] matcher
8716 * @param[in, out] key
8717 * Flow matcher value.
8719 * Flow pattern to translate.
8724 * 0 on success, a negative errno value otherwise.
8727 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8728 void *key, const struct rte_flow_item *item,
8729 const struct rte_flow_attr *attr)
8731 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8732 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8733 struct mlx5_priv *priv;
8736 mask = pid_m ? pid_m->id : 0xffff;
8737 id = pid_v ? pid_v->id : dev->data->port_id;
8738 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8742 * Translate to vport field or to metadata, depending on mode.
8743 * Kernel can use either misc.source_port or half of C0 metadata
8746 if (priv->vport_meta_mask) {
8748 * Provide the hint for SW steering library
8749 * to insert the flow into ingress domain and
8750 * save the extra vport match.
8752 if (mask == 0xffff && priv->vport_id == 0xffff &&
8753 priv->pf_bond < 0 && attr->transfer)
8754 flow_dv_translate_item_source_vport
8755 (matcher, key, priv->vport_id, mask);
8757 * We should always set the vport metadata register,
8758 * otherwise the SW steering library can drop
8759 * the rule if wire vport metadata value is not zero,
8760 * it depends on kernel configuration.
8762 flow_dv_translate_item_meta_vport(matcher, key,
8763 priv->vport_meta_tag,
8764 priv->vport_meta_mask);
8766 flow_dv_translate_item_source_vport(matcher, key,
8767 priv->vport_id, mask);
8773 * Add ICMP6 item to matcher and to the value.
8775 * @param[in, out] matcher
8777 * @param[in, out] key
8778 * Flow matcher value.
8780 * Flow pattern to translate.
8782 * Item is inner pattern.
8785 flow_dv_translate_item_icmp6(void *matcher, void *key,
8786 const struct rte_flow_item *item,
8789 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8790 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8793 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8795 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8797 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8799 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8801 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8803 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8805 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8806 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8810 icmp6_m = &rte_flow_item_icmp6_mask;
8811 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8812 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8813 icmp6_v->type & icmp6_m->type);
8814 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8815 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8816 icmp6_v->code & icmp6_m->code);
8820 * Add ICMP item to matcher and to the value.
8822 * @param[in, out] matcher
8824 * @param[in, out] key
8825 * Flow matcher value.
8827 * Flow pattern to translate.
8829 * Item is inner pattern.
8832 flow_dv_translate_item_icmp(void *matcher, void *key,
8833 const struct rte_flow_item *item,
8836 const struct rte_flow_item_icmp *icmp_m = item->mask;
8837 const struct rte_flow_item_icmp *icmp_v = item->spec;
8838 uint32_t icmp_header_data_m = 0;
8839 uint32_t icmp_header_data_v = 0;
8842 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8844 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8846 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8848 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8850 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8852 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8854 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8855 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8859 icmp_m = &rte_flow_item_icmp_mask;
8860 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8861 icmp_m->hdr.icmp_type);
8862 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8863 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8864 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8865 icmp_m->hdr.icmp_code);
8866 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8867 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8868 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8869 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8870 if (icmp_header_data_m) {
8871 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8872 icmp_header_data_v |=
8873 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8874 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8875 icmp_header_data_m);
8876 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8877 icmp_header_data_v & icmp_header_data_m);
8882 * Add GTP item to matcher and to the value.
8884 * @param[in, out] matcher
8886 * @param[in, out] key
8887 * Flow matcher value.
8889 * Flow pattern to translate.
8891 * Item is inner pattern.
8894 flow_dv_translate_item_gtp(void *matcher, void *key,
8895 const struct rte_flow_item *item, int inner)
8897 const struct rte_flow_item_gtp *gtp_m = item->mask;
8898 const struct rte_flow_item_gtp *gtp_v = item->spec;
8901 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8903 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8904 uint16_t dport = RTE_GTPU_UDP_PORT;
8907 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8909 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8911 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8913 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8915 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8916 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8922 gtp_m = &rte_flow_item_gtp_mask;
8923 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8924 gtp_m->v_pt_rsv_flags);
8925 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8926 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8927 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8928 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8929 gtp_v->msg_type & gtp_m->msg_type);
8930 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8931 rte_be_to_cpu_32(gtp_m->teid));
8932 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8933 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8937 * Add GTP PSC item to matcher.
8939 * @param[in, out] matcher
8941 * @param[in, out] key
8942 * Flow matcher value.
8944 * Flow pattern to translate.
8947 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8948 const struct rte_flow_item *item)
8950 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8951 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8952 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8954 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8960 uint8_t next_ext_header_type;
8965 /* Always set E-flag match on one, regardless of GTP item settings. */
8966 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8967 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8968 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8969 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8970 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8971 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8972 /*Set next extension header type. */
8975 dw_2.next_ext_header_type = 0xff;
8976 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8977 rte_cpu_to_be_32(dw_2.w32));
8980 dw_2.next_ext_header_type = 0x85;
8981 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8982 rte_cpu_to_be_32(dw_2.w32));
8994 /*Set extension header PDU type and Qos. */
8996 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8998 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8999 dw_0.qfi = gtp_psc_m->qfi;
9000 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9001 rte_cpu_to_be_32(dw_0.w32));
9003 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9004 gtp_psc_m->pdu_type);
9005 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9006 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9007 rte_cpu_to_be_32(dw_0.w32));
9013 * Add eCPRI item to matcher and to the value.
9016 * The devich to configure through.
9017 * @param[in, out] matcher
9019 * @param[in, out] key
9020 * Flow matcher value.
9022 * Flow pattern to translate.
9023 * @param[in] samples
9024 * Sample IDs to be used in the matching.
9027 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9028 void *key, const struct rte_flow_item *item)
9030 struct mlx5_priv *priv = dev->data->dev_private;
9031 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9032 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9033 struct rte_ecpri_common_hdr common;
9034 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9036 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9044 ecpri_m = &rte_flow_item_ecpri_mask;
9046 * Maximal four DW samples are supported in a single matching now.
9047 * Two are used now for a eCPRI matching:
9048 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9049 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9052 if (!ecpri_m->hdr.common.u32)
9054 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9055 /* Need to take the whole DW as the mask to fill the entry. */
9056 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9057 prog_sample_field_value_0);
9058 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9059 prog_sample_field_value_0);
9060 /* Already big endian (network order) in the header. */
9061 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9062 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9063 /* Sample#0, used for matching type, offset 0. */
9064 MLX5_SET(fte_match_set_misc4, misc4_m,
9065 prog_sample_field_id_0, samples[0]);
9066 /* It makes no sense to set the sample ID in the mask field. */
9067 MLX5_SET(fte_match_set_misc4, misc4_v,
9068 prog_sample_field_id_0, samples[0]);
9070 * Checking if message body part needs to be matched.
9071 * Some wildcard rules only matching type field should be supported.
9073 if (ecpri_m->hdr.dummy[0]) {
9074 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9075 switch (common.type) {
9076 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9077 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9078 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9079 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9080 prog_sample_field_value_1);
9081 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9082 prog_sample_field_value_1);
9083 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9084 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9085 ecpri_m->hdr.dummy[0];
9086 /* Sample#1, to match message body, offset 4. */
9087 MLX5_SET(fte_match_set_misc4, misc4_m,
9088 prog_sample_field_id_1, samples[1]);
9089 MLX5_SET(fte_match_set_misc4, misc4_v,
9090 prog_sample_field_id_1, samples[1]);
9093 /* Others, do not match any sample ID. */
9099 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9101 #define HEADER_IS_ZERO(match_criteria, headers) \
9102 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9103 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9106 * Calculate flow matcher enable bitmap.
9108 * @param match_criteria
9109 * Pointer to flow matcher criteria.
9112 * Bitmap of enabled fields.
9115 flow_dv_matcher_enable(uint32_t *match_criteria)
9117 uint8_t match_criteria_enable;
9119 match_criteria_enable =
9120 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9121 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9122 match_criteria_enable |=
9123 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9124 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9125 match_criteria_enable |=
9126 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9127 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9128 match_criteria_enable |=
9129 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9130 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9131 match_criteria_enable |=
9132 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9133 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9134 match_criteria_enable |=
9135 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9136 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9137 return match_criteria_enable;
9140 struct mlx5_hlist_entry *
9141 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9143 struct mlx5_dev_ctx_shared *sh = list->ctx;
9144 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9145 struct rte_eth_dev *dev = ctx->dev;
9146 struct mlx5_flow_tbl_data_entry *tbl_data;
9147 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9148 struct rte_flow_error *error = ctx->error;
9149 union mlx5_flow_tbl_key key = { .v64 = key64 };
9150 struct mlx5_flow_tbl_resource *tbl;
9155 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9157 rte_flow_error_set(error, ENOMEM,
9158 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9160 "cannot allocate flow table data entry");
9163 tbl_data->idx = idx;
9164 tbl_data->tunnel = tt_prm->tunnel;
9165 tbl_data->group_id = tt_prm->group_id;
9166 tbl_data->external = !!tt_prm->external;
9167 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9168 tbl_data->is_egress = !!key.direction;
9169 tbl_data->is_transfer = !!key.domain;
9170 tbl_data->dummy = !!key.dummy;
9171 tbl_data->table_id = key.table_id;
9172 tbl = &tbl_data->tbl;
9174 return &tbl_data->entry;
9176 domain = sh->fdb_domain;
9177 else if (key.direction)
9178 domain = sh->tx_domain;
9180 domain = sh->rx_domain;
9181 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9183 rte_flow_error_set(error, ENOMEM,
9184 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9185 NULL, "cannot create flow table object");
9186 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9190 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9191 (tbl->obj, &tbl_data->jump.action);
9193 rte_flow_error_set(error, ENOMEM,
9194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9196 "cannot create flow jump action");
9197 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9198 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9202 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9203 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9205 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9206 flow_dv_matcher_create_cb,
9207 flow_dv_matcher_match_cb,
9208 flow_dv_matcher_remove_cb);
9209 return &tbl_data->entry;
9213 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9214 struct mlx5_hlist_entry *entry, uint64_t key64,
9215 void *cb_ctx __rte_unused)
9217 struct mlx5_flow_tbl_data_entry *tbl_data =
9218 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9219 union mlx5_flow_tbl_key key = { .v64 = key64 };
9221 return tbl_data->table_id != key.table_id ||
9222 tbl_data->dummy != key.dummy ||
9223 tbl_data->is_transfer != key.domain ||
9224 tbl_data->is_egress != key.direction;
9230 * @param[in, out] dev
9231 * Pointer to rte_eth_dev structure.
9232 * @param[in] table_id
9235 * Direction of the table.
9236 * @param[in] transfer
9237 * E-Switch or NIC flow.
9239 * Dummy entry for dv API.
9241 * pointer to error structure.
9244 * Returns tables resource based on the index, NULL in case of failed.
9246 struct mlx5_flow_tbl_resource *
9247 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9248 uint32_t table_id, uint8_t egress,
9251 const struct mlx5_flow_tunnel *tunnel,
9252 uint32_t group_id, uint8_t dummy,
9253 struct rte_flow_error *error)
9255 struct mlx5_priv *priv = dev->data->dev_private;
9256 union mlx5_flow_tbl_key table_key = {
9258 .table_id = table_id,
9260 .domain = !!transfer,
9261 .direction = !!egress,
9264 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9266 .group_id = group_id,
9267 .external = external,
9269 struct mlx5_flow_cb_ctx ctx = {
9274 struct mlx5_hlist_entry *entry;
9275 struct mlx5_flow_tbl_data_entry *tbl_data;
9277 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9279 rte_flow_error_set(error, ENOMEM,
9280 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9281 "cannot get table");
9284 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9285 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9286 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9287 return &tbl_data->tbl;
9291 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9292 struct mlx5_hlist_entry *entry)
9294 struct mlx5_dev_ctx_shared *sh = list->ctx;
9295 struct mlx5_flow_tbl_data_entry *tbl_data =
9296 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9298 MLX5_ASSERT(entry && sh);
9299 if (tbl_data->jump.action)
9300 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9301 if (tbl_data->tbl.obj)
9302 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9303 if (tbl_data->tunnel_offload && tbl_data->external) {
9304 struct mlx5_hlist_entry *he;
9305 struct mlx5_hlist *tunnel_grp_hash;
9306 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9307 union tunnel_tbl_key tunnel_key = {
9308 .tunnel_id = tbl_data->tunnel ?
9309 tbl_data->tunnel->tunnel_id : 0,
9310 .group = tbl_data->group_id
9312 uint32_t table_id = tbl_data->table_id;
9314 tunnel_grp_hash = tbl_data->tunnel ?
9315 tbl_data->tunnel->groups :
9317 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9319 mlx5_hlist_unregister(tunnel_grp_hash, he);
9321 "Table_id %u tunnel %u group %u released.",
9324 tbl_data->tunnel->tunnel_id : 0,
9325 tbl_data->group_id);
9327 mlx5_cache_list_destroy(&tbl_data->matchers);
9328 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9332 * Release a flow table.
9335 * Pointer to device shared structure.
9337 * Table resource to be released.
9340 * Returns 0 if table was released, else return 1;
9343 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9344 struct mlx5_flow_tbl_resource *tbl)
9346 struct mlx5_flow_tbl_data_entry *tbl_data =
9347 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9351 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9355 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9356 struct mlx5_cache_entry *entry, void *cb_ctx)
9358 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9359 struct mlx5_flow_dv_matcher *ref = ctx->data;
9360 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9363 return cur->crc != ref->crc ||
9364 cur->priority != ref->priority ||
9365 memcmp((const void *)cur->mask.buf,
9366 (const void *)ref->mask.buf, ref->mask.size);
9369 struct mlx5_cache_entry *
9370 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9371 struct mlx5_cache_entry *entry __rte_unused,
9374 struct mlx5_dev_ctx_shared *sh = list->ctx;
9375 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9376 struct mlx5_flow_dv_matcher *ref = ctx->data;
9377 struct mlx5_flow_dv_matcher *cache;
9378 struct mlx5dv_flow_matcher_attr dv_attr = {
9379 .type = IBV_FLOW_ATTR_NORMAL,
9380 .match_mask = (void *)&ref->mask,
9382 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9386 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9388 rte_flow_error_set(ctx->error, ENOMEM,
9389 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9390 "cannot create matcher");
9394 dv_attr.match_criteria_enable =
9395 flow_dv_matcher_enable(cache->mask.buf);
9396 dv_attr.priority = ref->priority;
9398 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9399 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9400 &cache->matcher_object);
9403 rte_flow_error_set(ctx->error, ENOMEM,
9404 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9405 "cannot create matcher");
9408 return &cache->entry;
9412 * Register the flow matcher.
9414 * @param[in, out] dev
9415 * Pointer to rte_eth_dev structure.
9416 * @param[in, out] matcher
9417 * Pointer to flow matcher.
9418 * @param[in, out] key
9419 * Pointer to flow table key.
9420 * @parm[in, out] dev_flow
9421 * Pointer to the dev_flow.
9423 * pointer to error structure.
9426 * 0 on success otherwise -errno and errno is set.
9429 flow_dv_matcher_register(struct rte_eth_dev *dev,
9430 struct mlx5_flow_dv_matcher *ref,
9431 union mlx5_flow_tbl_key *key,
9432 struct mlx5_flow *dev_flow,
9433 const struct mlx5_flow_tunnel *tunnel,
9435 struct rte_flow_error *error)
9437 struct mlx5_cache_entry *entry;
9438 struct mlx5_flow_dv_matcher *cache;
9439 struct mlx5_flow_tbl_resource *tbl;
9440 struct mlx5_flow_tbl_data_entry *tbl_data;
9441 struct mlx5_flow_cb_ctx ctx = {
9447 * tunnel offload API requires this registration for cases when
9448 * tunnel match rule was inserted before tunnel set rule.
9450 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9451 key->direction, key->domain,
9452 dev_flow->external, tunnel,
9453 group_id, 0, error);
9455 return -rte_errno; /* No need to refill the error info */
9456 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9458 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9460 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9461 return rte_flow_error_set(error, ENOMEM,
9462 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9463 "cannot allocate ref memory");
9465 cache = container_of(entry, typeof(*cache), entry);
9466 dev_flow->handle->dvh.matcher = cache;
9470 struct mlx5_hlist_entry *
9471 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9473 struct mlx5_dev_ctx_shared *sh = list->ctx;
9474 struct rte_flow_error *error = ctx;
9475 struct mlx5_flow_dv_tag_resource *entry;
9479 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9481 rte_flow_error_set(error, ENOMEM,
9482 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9483 "cannot allocate resource memory");
9487 entry->tag_id = key;
9488 ret = mlx5_flow_os_create_flow_action_tag(key,
9491 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9492 rte_flow_error_set(error, ENOMEM,
9493 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9494 NULL, "cannot create action");
9497 return &entry->entry;
9501 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9502 struct mlx5_hlist_entry *entry, uint64_t key,
9503 void *cb_ctx __rte_unused)
9505 struct mlx5_flow_dv_tag_resource *tag =
9506 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9508 return key != tag->tag_id;
9512 * Find existing tag resource or create and register a new one.
9514 * @param dev[in, out]
9515 * Pointer to rte_eth_dev structure.
9516 * @param[in, out] tag_be24
9517 * Tag value in big endian then R-shift 8.
9518 * @parm[in, out] dev_flow
9519 * Pointer to the dev_flow.
9521 * pointer to error structure.
9524 * 0 on success otherwise -errno and errno is set.
9527 flow_dv_tag_resource_register
9528 (struct rte_eth_dev *dev,
9530 struct mlx5_flow *dev_flow,
9531 struct rte_flow_error *error)
9533 struct mlx5_priv *priv = dev->data->dev_private;
9534 struct mlx5_flow_dv_tag_resource *cache_resource;
9535 struct mlx5_hlist_entry *entry;
9537 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9539 cache_resource = container_of
9540 (entry, struct mlx5_flow_dv_tag_resource, entry);
9541 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9542 dev_flow->dv.tag_resource = cache_resource;
9549 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9550 struct mlx5_hlist_entry *entry)
9552 struct mlx5_dev_ctx_shared *sh = list->ctx;
9553 struct mlx5_flow_dv_tag_resource *tag =
9554 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9556 MLX5_ASSERT(tag && sh && tag->action);
9557 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9558 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9559 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9566 * Pointer to Ethernet device.
9571 * 1 while a reference on it exists, 0 when freed.
9574 flow_dv_tag_release(struct rte_eth_dev *dev,
9577 struct mlx5_priv *priv = dev->data->dev_private;
9578 struct mlx5_flow_dv_tag_resource *tag;
9580 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9583 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9584 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9585 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9589 * Translate port ID action to vport.
9592 * Pointer to rte_eth_dev structure.
9594 * Pointer to the port ID action.
9595 * @param[out] dst_port_id
9596 * The target port ID.
9598 * Pointer to the error structure.
9601 * 0 on success, a negative errno value otherwise and rte_errno is set.
9604 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9605 const struct rte_flow_action *action,
9606 uint32_t *dst_port_id,
9607 struct rte_flow_error *error)
9610 struct mlx5_priv *priv;
9611 const struct rte_flow_action_port_id *conf =
9612 (const struct rte_flow_action_port_id *)action->conf;
9614 port = conf->original ? dev->data->port_id : conf->id;
9615 priv = mlx5_port_to_eswitch_info(port, false);
9617 return rte_flow_error_set(error, -rte_errno,
9618 RTE_FLOW_ERROR_TYPE_ACTION,
9620 "No eswitch info was found for port");
9621 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9623 * This parameter is transferred to
9624 * mlx5dv_dr_action_create_dest_ib_port().
9626 *dst_port_id = priv->dev_port;
9629 * Legacy mode, no LAG configurations is supported.
9630 * This parameter is transferred to
9631 * mlx5dv_dr_action_create_dest_vport().
9633 *dst_port_id = priv->vport_id;
9639 * Create a counter with aging configuration.
9642 * Pointer to rte_eth_dev structure.
9644 * Pointer to the counter action configuration.
9646 * Pointer to the aging action configuration.
9649 * Index to flow counter on success, 0 otherwise.
9652 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9653 struct mlx5_flow *dev_flow,
9654 const struct rte_flow_action_count *count,
9655 const struct rte_flow_action_age *age)
9658 struct mlx5_age_param *age_param;
9660 if (count && count->shared)
9661 counter = flow_dv_counter_get_shared(dev, count->id);
9663 counter = flow_dv_counter_alloc(dev, !!age);
9664 if (!counter || age == NULL)
9666 age_param = flow_dv_counter_idx_get_age(dev, counter);
9667 age_param->context = age->context ? age->context :
9668 (void *)(uintptr_t)(dev_flow->flow_idx);
9669 age_param->timeout = age->timeout;
9670 age_param->port_id = dev->data->port_id;
9671 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9672 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9677 * Add Tx queue matcher
9680 * Pointer to the dev struct.
9681 * @param[in, out] matcher
9683 * @param[in, out] key
9684 * Flow matcher value.
9686 * Flow pattern to translate.
9688 * Item is inner pattern.
9691 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9692 void *matcher, void *key,
9693 const struct rte_flow_item *item)
9695 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9696 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9698 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9700 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9701 struct mlx5_txq_ctrl *txq;
9705 queue_m = (const void *)item->mask;
9708 queue_v = (const void *)item->spec;
9711 txq = mlx5_txq_get(dev, queue_v->queue);
9714 queue = txq->obj->sq->id;
9715 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9716 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9717 queue & queue_m->queue);
9718 mlx5_txq_release(dev, queue_v->queue);
9722 * Set the hash fields according to the @p flow information.
9724 * @param[in] dev_flow
9725 * Pointer to the mlx5_flow.
9726 * @param[in] rss_desc
9727 * Pointer to the mlx5_flow_rss_desc.
9730 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9731 struct mlx5_flow_rss_desc *rss_desc)
9733 uint64_t items = dev_flow->handle->layers;
9735 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9737 dev_flow->hash_fields = 0;
9738 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9739 if (rss_desc->level >= 2) {
9740 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9744 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9745 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9746 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9747 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9748 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9749 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9750 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9752 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9754 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9755 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9756 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9757 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9758 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9759 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9760 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9762 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9765 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9766 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9767 if (rss_types & ETH_RSS_UDP) {
9768 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9769 dev_flow->hash_fields |=
9770 IBV_RX_HASH_SRC_PORT_UDP;
9771 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9772 dev_flow->hash_fields |=
9773 IBV_RX_HASH_DST_PORT_UDP;
9775 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9777 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9778 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9779 if (rss_types & ETH_RSS_TCP) {
9780 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9781 dev_flow->hash_fields |=
9782 IBV_RX_HASH_SRC_PORT_TCP;
9783 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9784 dev_flow->hash_fields |=
9785 IBV_RX_HASH_DST_PORT_TCP;
9787 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9793 * Prepare an Rx Hash queue.
9796 * Pointer to Ethernet device.
9797 * @param[in] dev_flow
9798 * Pointer to the mlx5_flow.
9799 * @param[in] rss_desc
9800 * Pointer to the mlx5_flow_rss_desc.
9801 * @param[out] hrxq_idx
9802 * Hash Rx queue index.
9805 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9807 static struct mlx5_hrxq *
9808 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9809 struct mlx5_flow *dev_flow,
9810 struct mlx5_flow_rss_desc *rss_desc,
9813 struct mlx5_priv *priv = dev->data->dev_private;
9814 struct mlx5_flow_handle *dh = dev_flow->handle;
9815 struct mlx5_hrxq *hrxq;
9817 MLX5_ASSERT(rss_desc->queue_num);
9818 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9819 rss_desc->hash_fields = dev_flow->hash_fields;
9820 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9821 rss_desc->shared_rss = 0;
9822 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9825 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9831 * Release sample sub action resource.
9833 * @param[in, out] dev
9834 * Pointer to rte_eth_dev structure.
9835 * @param[in] act_res
9836 * Pointer to sample sub action resource.
9839 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9840 struct mlx5_flow_sub_actions_idx *act_res)
9842 if (act_res->rix_hrxq) {
9843 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9844 act_res->rix_hrxq = 0;
9846 if (act_res->rix_encap_decap) {
9847 flow_dv_encap_decap_resource_release(dev,
9848 act_res->rix_encap_decap);
9849 act_res->rix_encap_decap = 0;
9851 if (act_res->rix_port_id_action) {
9852 flow_dv_port_id_action_resource_release(dev,
9853 act_res->rix_port_id_action);
9854 act_res->rix_port_id_action = 0;
9856 if (act_res->rix_tag) {
9857 flow_dv_tag_release(dev, act_res->rix_tag);
9858 act_res->rix_tag = 0;
9860 if (act_res->rix_jump) {
9861 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9862 act_res->rix_jump = 0;
9867 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9868 struct mlx5_cache_entry *entry, void *cb_ctx)
9870 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9871 struct rte_eth_dev *dev = ctx->dev;
9872 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9873 struct mlx5_flow_dv_sample_resource *cache_resource =
9874 container_of(entry, typeof(*cache_resource), entry);
9876 if (resource->ratio == cache_resource->ratio &&
9877 resource->ft_type == cache_resource->ft_type &&
9878 resource->ft_id == cache_resource->ft_id &&
9879 resource->set_action == cache_resource->set_action &&
9880 !memcmp((void *)&resource->sample_act,
9881 (void *)&cache_resource->sample_act,
9882 sizeof(struct mlx5_flow_sub_actions_list))) {
9884 * Existing sample action should release the prepared
9885 * sub-actions reference counter.
9887 flow_dv_sample_sub_actions_release(dev,
9888 &resource->sample_idx);
9894 struct mlx5_cache_entry *
9895 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9896 struct mlx5_cache_entry *entry __rte_unused,
9899 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9900 struct rte_eth_dev *dev = ctx->dev;
9901 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9902 void **sample_dv_actions = resource->sub_actions;
9903 struct mlx5_flow_dv_sample_resource *cache_resource;
9904 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9905 struct mlx5_priv *priv = dev->data->dev_private;
9906 struct mlx5_dev_ctx_shared *sh = priv->sh;
9907 struct mlx5_flow_tbl_resource *tbl;
9909 const uint32_t next_ft_step = 1;
9910 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9911 uint8_t is_egress = 0;
9912 uint8_t is_transfer = 0;
9913 struct rte_flow_error *error = ctx->error;
9915 /* Register new sample resource. */
9916 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9917 if (!cache_resource) {
9918 rte_flow_error_set(error, ENOMEM,
9919 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9921 "cannot allocate resource memory");
9924 *cache_resource = *resource;
9925 /* Create normal path table level */
9926 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9928 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9930 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9931 is_egress, is_transfer,
9932 true, NULL, 0, 0, error);
9934 rte_flow_error_set(error, ENOMEM,
9935 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9937 "fail to create normal path table "
9941 cache_resource->normal_path_tbl = tbl;
9942 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9943 if (!sh->default_miss_action) {
9944 rte_flow_error_set(error, ENOMEM,
9945 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9947 "default miss action was not "
9951 sample_dv_actions[resource->sample_act.actions_num++] =
9952 sh->default_miss_action;
9954 /* Create a DR sample action */
9955 sampler_attr.sample_ratio = cache_resource->ratio;
9956 sampler_attr.default_next_table = tbl->obj;
9957 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9958 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9959 &sample_dv_actions[0];
9960 sampler_attr.action = cache_resource->set_action;
9961 if (mlx5_os_flow_dr_create_flow_action_sampler
9962 (&sampler_attr, &cache_resource->verbs_action)) {
9963 rte_flow_error_set(error, ENOMEM,
9964 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9965 NULL, "cannot create sample action");
9968 cache_resource->idx = idx;
9969 cache_resource->dev = dev;
9970 return &cache_resource->entry;
9972 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9973 flow_dv_sample_sub_actions_release(dev,
9974 &cache_resource->sample_idx);
9975 if (cache_resource->normal_path_tbl)
9976 flow_dv_tbl_resource_release(MLX5_SH(dev),
9977 cache_resource->normal_path_tbl);
9978 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9984 * Find existing sample resource or create and register a new one.
9986 * @param[in, out] dev
9987 * Pointer to rte_eth_dev structure.
9988 * @param[in] resource
9989 * Pointer to sample resource.
9990 * @parm[in, out] dev_flow
9991 * Pointer to the dev_flow.
9993 * pointer to error structure.
9996 * 0 on success otherwise -errno and errno is set.
9999 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10000 struct mlx5_flow_dv_sample_resource *resource,
10001 struct mlx5_flow *dev_flow,
10002 struct rte_flow_error *error)
10004 struct mlx5_flow_dv_sample_resource *cache_resource;
10005 struct mlx5_cache_entry *entry;
10006 struct mlx5_priv *priv = dev->data->dev_private;
10007 struct mlx5_flow_cb_ctx ctx = {
10013 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10016 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10017 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10018 dev_flow->dv.sample_res = cache_resource;
10023 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10024 struct mlx5_cache_entry *entry, void *cb_ctx)
10026 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10027 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10028 struct rte_eth_dev *dev = ctx->dev;
10029 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10030 container_of(entry, typeof(*cache_resource), entry);
10033 if (resource->num_of_dest == cache_resource->num_of_dest &&
10034 resource->ft_type == cache_resource->ft_type &&
10035 !memcmp((void *)cache_resource->sample_act,
10036 (void *)resource->sample_act,
10037 (resource->num_of_dest *
10038 sizeof(struct mlx5_flow_sub_actions_list)))) {
10040 * Existing sample action should release the prepared
10041 * sub-actions reference counter.
10043 for (idx = 0; idx < resource->num_of_dest; idx++)
10044 flow_dv_sample_sub_actions_release(dev,
10045 &resource->sample_idx[idx]);
10051 struct mlx5_cache_entry *
10052 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10053 struct mlx5_cache_entry *entry __rte_unused,
10056 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10057 struct rte_eth_dev *dev = ctx->dev;
10058 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10059 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10060 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10061 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10062 struct mlx5_priv *priv = dev->data->dev_private;
10063 struct mlx5_dev_ctx_shared *sh = priv->sh;
10064 struct mlx5_flow_sub_actions_list *sample_act;
10065 struct mlx5dv_dr_domain *domain;
10066 uint32_t idx = 0, res_idx = 0;
10067 struct rte_flow_error *error = ctx->error;
10068 uint64_t action_flags;
10071 /* Register new destination array resource. */
10072 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10074 if (!cache_resource) {
10075 rte_flow_error_set(error, ENOMEM,
10076 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10078 "cannot allocate resource memory");
10081 *cache_resource = *resource;
10082 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10083 domain = sh->fdb_domain;
10084 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10085 domain = sh->rx_domain;
10087 domain = sh->tx_domain;
10088 for (idx = 0; idx < resource->num_of_dest; idx++) {
10089 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10090 mlx5_malloc(MLX5_MEM_ZERO,
10091 sizeof(struct mlx5dv_dr_action_dest_attr),
10093 if (!dest_attr[idx]) {
10094 rte_flow_error_set(error, ENOMEM,
10095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10097 "cannot allocate resource memory");
10100 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10101 sample_act = &resource->sample_act[idx];
10102 action_flags = sample_act->action_flags;
10103 switch (action_flags) {
10104 case MLX5_FLOW_ACTION_QUEUE:
10105 dest_attr[idx]->dest = sample_act->dr_queue_action;
10107 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10108 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10109 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10110 dest_attr[idx]->dest_reformat->reformat =
10111 sample_act->dr_encap_action;
10112 dest_attr[idx]->dest_reformat->dest =
10113 sample_act->dr_port_id_action;
10115 case MLX5_FLOW_ACTION_PORT_ID:
10116 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10118 case MLX5_FLOW_ACTION_JUMP:
10119 dest_attr[idx]->dest = sample_act->dr_jump_action;
10122 rte_flow_error_set(error, EINVAL,
10123 RTE_FLOW_ERROR_TYPE_ACTION,
10125 "unsupported actions type");
10129 /* create a dest array actioin */
10130 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10132 cache_resource->num_of_dest,
10134 &cache_resource->action);
10136 rte_flow_error_set(error, ENOMEM,
10137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10139 "cannot create destination array action");
10142 cache_resource->idx = res_idx;
10143 cache_resource->dev = dev;
10144 for (idx = 0; idx < resource->num_of_dest; idx++)
10145 mlx5_free(dest_attr[idx]);
10146 return &cache_resource->entry;
10148 for (idx = 0; idx < resource->num_of_dest; idx++) {
10149 struct mlx5_flow_sub_actions_idx *act_res =
10150 &cache_resource->sample_idx[idx];
10151 if (act_res->rix_hrxq &&
10152 !mlx5_hrxq_release(dev,
10153 act_res->rix_hrxq))
10154 act_res->rix_hrxq = 0;
10155 if (act_res->rix_encap_decap &&
10156 !flow_dv_encap_decap_resource_release(dev,
10157 act_res->rix_encap_decap))
10158 act_res->rix_encap_decap = 0;
10159 if (act_res->rix_port_id_action &&
10160 !flow_dv_port_id_action_resource_release(dev,
10161 act_res->rix_port_id_action))
10162 act_res->rix_port_id_action = 0;
10163 if (act_res->rix_jump &&
10164 !flow_dv_jump_tbl_resource_release(dev,
10165 act_res->rix_jump))
10166 act_res->rix_jump = 0;
10167 if (dest_attr[idx])
10168 mlx5_free(dest_attr[idx]);
10171 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10176 * Find existing destination array resource or create and register a new one.
10178 * @param[in, out] dev
10179 * Pointer to rte_eth_dev structure.
10180 * @param[in] resource
10181 * Pointer to destination array resource.
10182 * @parm[in, out] dev_flow
10183 * Pointer to the dev_flow.
10184 * @param[out] error
10185 * pointer to error structure.
10188 * 0 on success otherwise -errno and errno is set.
10191 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10192 struct mlx5_flow_dv_dest_array_resource *resource,
10193 struct mlx5_flow *dev_flow,
10194 struct rte_flow_error *error)
10196 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10197 struct mlx5_priv *priv = dev->data->dev_private;
10198 struct mlx5_cache_entry *entry;
10199 struct mlx5_flow_cb_ctx ctx = {
10205 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10208 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10209 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10210 dev_flow->dv.dest_array_res = cache_resource;
10215 * Convert Sample action to DV specification.
10218 * Pointer to rte_eth_dev structure.
10219 * @param[in] action
10220 * Pointer to sample action structure.
10221 * @param[in, out] dev_flow
10222 * Pointer to the mlx5_flow.
10224 * Pointer to the flow attributes.
10225 * @param[in, out] num_of_dest
10226 * Pointer to the num of destination.
10227 * @param[in, out] sample_actions
10228 * Pointer to sample actions list.
10229 * @param[in, out] res
10230 * Pointer to sample resource.
10231 * @param[out] error
10232 * Pointer to the error structure.
10235 * 0 on success, a negative errno value otherwise and rte_errno is set.
10238 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10239 const struct rte_flow_action_sample *action,
10240 struct mlx5_flow *dev_flow,
10241 const struct rte_flow_attr *attr,
10242 uint32_t *num_of_dest,
10243 void **sample_actions,
10244 struct mlx5_flow_dv_sample_resource *res,
10245 struct rte_flow_error *error)
10247 struct mlx5_priv *priv = dev->data->dev_private;
10248 const struct rte_flow_action *sub_actions;
10249 struct mlx5_flow_sub_actions_list *sample_act;
10250 struct mlx5_flow_sub_actions_idx *sample_idx;
10251 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10252 struct rte_flow *flow = dev_flow->flow;
10253 struct mlx5_flow_rss_desc *rss_desc;
10254 uint64_t action_flags = 0;
10257 rss_desc = &wks->rss_desc;
10258 sample_act = &res->sample_act;
10259 sample_idx = &res->sample_idx;
10260 res->ratio = action->ratio;
10261 sub_actions = action->actions;
10262 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10263 int type = sub_actions->type;
10264 uint32_t pre_rix = 0;
10267 case RTE_FLOW_ACTION_TYPE_QUEUE:
10269 const struct rte_flow_action_queue *queue;
10270 struct mlx5_hrxq *hrxq;
10273 queue = sub_actions->conf;
10274 rss_desc->queue_num = 1;
10275 rss_desc->queue[0] = queue->index;
10276 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10277 rss_desc, &hrxq_idx);
10279 return rte_flow_error_set
10281 RTE_FLOW_ERROR_TYPE_ACTION,
10283 "cannot create fate queue");
10284 sample_act->dr_queue_action = hrxq->action;
10285 sample_idx->rix_hrxq = hrxq_idx;
10286 sample_actions[sample_act->actions_num++] =
10289 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10290 if (action_flags & MLX5_FLOW_ACTION_MARK)
10291 dev_flow->handle->rix_hrxq = hrxq_idx;
10292 dev_flow->handle->fate_action =
10293 MLX5_FLOW_FATE_QUEUE;
10296 case RTE_FLOW_ACTION_TYPE_RSS:
10298 struct mlx5_hrxq *hrxq;
10300 const struct rte_flow_action_rss *rss;
10301 const uint8_t *rss_key;
10303 rss = sub_actions->conf;
10304 memcpy(rss_desc->queue, rss->queue,
10305 rss->queue_num * sizeof(uint16_t));
10306 rss_desc->queue_num = rss->queue_num;
10307 /* NULL RSS key indicates default RSS key. */
10308 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10309 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10311 * rss->level and rss.types should be set in advance
10312 * when expanding items for RSS.
10314 flow_dv_hashfields_set(dev_flow, rss_desc);
10315 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10316 rss_desc, &hrxq_idx);
10318 return rte_flow_error_set
10320 RTE_FLOW_ERROR_TYPE_ACTION,
10322 "cannot create fate queue");
10323 sample_act->dr_queue_action = hrxq->action;
10324 sample_idx->rix_hrxq = hrxq_idx;
10325 sample_actions[sample_act->actions_num++] =
10328 action_flags |= MLX5_FLOW_ACTION_RSS;
10329 if (action_flags & MLX5_FLOW_ACTION_MARK)
10330 dev_flow->handle->rix_hrxq = hrxq_idx;
10331 dev_flow->handle->fate_action =
10332 MLX5_FLOW_FATE_QUEUE;
10335 case RTE_FLOW_ACTION_TYPE_MARK:
10337 uint32_t tag_be = mlx5_flow_mark_set
10338 (((const struct rte_flow_action_mark *)
10339 (sub_actions->conf))->id);
10341 dev_flow->handle->mark = 1;
10342 pre_rix = dev_flow->handle->dvh.rix_tag;
10343 /* Save the mark resource before sample */
10344 pre_r = dev_flow->dv.tag_resource;
10345 if (flow_dv_tag_resource_register(dev, tag_be,
10348 MLX5_ASSERT(dev_flow->dv.tag_resource);
10349 sample_act->dr_tag_action =
10350 dev_flow->dv.tag_resource->action;
10351 sample_idx->rix_tag =
10352 dev_flow->handle->dvh.rix_tag;
10353 sample_actions[sample_act->actions_num++] =
10354 sample_act->dr_tag_action;
10355 /* Recover the mark resource after sample */
10356 dev_flow->dv.tag_resource = pre_r;
10357 dev_flow->handle->dvh.rix_tag = pre_rix;
10358 action_flags |= MLX5_FLOW_ACTION_MARK;
10361 case RTE_FLOW_ACTION_TYPE_COUNT:
10363 if (!flow->counter) {
10365 flow_dv_translate_create_counter(dev,
10366 dev_flow, sub_actions->conf,
10368 if (!flow->counter)
10369 return rte_flow_error_set
10371 RTE_FLOW_ERROR_TYPE_ACTION,
10373 "cannot create counter"
10376 sample_act->dr_cnt_action =
10377 (flow_dv_counter_get_by_idx(dev,
10378 flow->counter, NULL))->action;
10379 sample_actions[sample_act->actions_num++] =
10380 sample_act->dr_cnt_action;
10381 action_flags |= MLX5_FLOW_ACTION_COUNT;
10384 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10386 struct mlx5_flow_dv_port_id_action_resource
10388 uint32_t port_id = 0;
10390 memset(&port_id_resource, 0, sizeof(port_id_resource));
10391 /* Save the port id resource before sample */
10392 pre_rix = dev_flow->handle->rix_port_id_action;
10393 pre_r = dev_flow->dv.port_id_action;
10394 if (flow_dv_translate_action_port_id(dev, sub_actions,
10397 port_id_resource.port_id = port_id;
10398 if (flow_dv_port_id_action_resource_register
10399 (dev, &port_id_resource, dev_flow, error))
10401 sample_act->dr_port_id_action =
10402 dev_flow->dv.port_id_action->action;
10403 sample_idx->rix_port_id_action =
10404 dev_flow->handle->rix_port_id_action;
10405 sample_actions[sample_act->actions_num++] =
10406 sample_act->dr_port_id_action;
10407 /* Recover the port id resource after sample */
10408 dev_flow->dv.port_id_action = pre_r;
10409 dev_flow->handle->rix_port_id_action = pre_rix;
10411 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10414 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10415 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10416 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10417 /* Save the encap resource before sample */
10418 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10419 pre_r = dev_flow->dv.encap_decap;
10420 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10425 sample_act->dr_encap_action =
10426 dev_flow->dv.encap_decap->action;
10427 sample_idx->rix_encap_decap =
10428 dev_flow->handle->dvh.rix_encap_decap;
10429 sample_actions[sample_act->actions_num++] =
10430 sample_act->dr_encap_action;
10431 /* Recover the encap resource after sample */
10432 dev_flow->dv.encap_decap = pre_r;
10433 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10434 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10437 return rte_flow_error_set(error, EINVAL,
10438 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10440 "Not support for sampler action");
10443 sample_act->action_flags = action_flags;
10444 res->ft_id = dev_flow->dv.group;
10445 if (attr->transfer) {
10447 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10448 uint64_t set_action;
10449 } action_ctx = { .set_action = 0 };
10451 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10452 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10453 MLX5_MODIFICATION_TYPE_SET);
10454 MLX5_SET(set_action_in, action_ctx.action_in, field,
10455 MLX5_MODI_META_REG_C_0);
10456 MLX5_SET(set_action_in, action_ctx.action_in, data,
10457 priv->vport_meta_tag);
10458 res->set_action = action_ctx.set_action;
10459 } else if (attr->ingress) {
10460 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10462 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10468 * Convert Sample action to DV specification.
10471 * Pointer to rte_eth_dev structure.
10472 * @param[in, out] dev_flow
10473 * Pointer to the mlx5_flow.
10474 * @param[in] num_of_dest
10475 * The num of destination.
10476 * @param[in, out] res
10477 * Pointer to sample resource.
10478 * @param[in, out] mdest_res
10479 * Pointer to destination array resource.
10480 * @param[in] sample_actions
10481 * Pointer to sample path actions list.
10482 * @param[in] action_flags
10483 * Holds the actions detected until now.
10484 * @param[out] error
10485 * Pointer to the error structure.
10488 * 0 on success, a negative errno value otherwise and rte_errno is set.
10491 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10492 struct mlx5_flow *dev_flow,
10493 uint32_t num_of_dest,
10494 struct mlx5_flow_dv_sample_resource *res,
10495 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10496 void **sample_actions,
10497 uint64_t action_flags,
10498 struct rte_flow_error *error)
10500 /* update normal path action resource into last index of array */
10501 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10502 struct mlx5_flow_sub_actions_list *sample_act =
10503 &mdest_res->sample_act[dest_index];
10504 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10505 struct mlx5_flow_rss_desc *rss_desc;
10506 uint32_t normal_idx = 0;
10507 struct mlx5_hrxq *hrxq;
10511 rss_desc = &wks->rss_desc;
10512 if (num_of_dest > 1) {
10513 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10514 /* Handle QP action for mirroring */
10515 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10516 rss_desc, &hrxq_idx);
10518 return rte_flow_error_set
10520 RTE_FLOW_ERROR_TYPE_ACTION,
10522 "cannot create rx queue");
10524 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10525 sample_act->dr_queue_action = hrxq->action;
10526 if (action_flags & MLX5_FLOW_ACTION_MARK)
10527 dev_flow->handle->rix_hrxq = hrxq_idx;
10528 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10530 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10532 mdest_res->sample_idx[dest_index].rix_encap_decap =
10533 dev_flow->handle->dvh.rix_encap_decap;
10534 sample_act->dr_encap_action =
10535 dev_flow->dv.encap_decap->action;
10537 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10539 mdest_res->sample_idx[dest_index].rix_port_id_action =
10540 dev_flow->handle->rix_port_id_action;
10541 sample_act->dr_port_id_action =
10542 dev_flow->dv.port_id_action->action;
10544 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10546 mdest_res->sample_idx[dest_index].rix_jump =
10547 dev_flow->handle->rix_jump;
10548 sample_act->dr_jump_action =
10549 dev_flow->dv.jump->action;
10550 dev_flow->handle->rix_jump = 0;
10552 sample_act->actions_num = normal_idx;
10553 /* update sample action resource into first index of array */
10554 mdest_res->ft_type = res->ft_type;
10555 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10556 sizeof(struct mlx5_flow_sub_actions_idx));
10557 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10558 sizeof(struct mlx5_flow_sub_actions_list));
10559 mdest_res->num_of_dest = num_of_dest;
10560 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10562 return rte_flow_error_set(error, EINVAL,
10563 RTE_FLOW_ERROR_TYPE_ACTION,
10564 NULL, "can't create sample "
10567 res->sub_actions = sample_actions;
10568 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10569 return rte_flow_error_set(error, EINVAL,
10570 RTE_FLOW_ERROR_TYPE_ACTION,
10572 "can't create sample action");
10578 * Remove an ASO age action from age actions list.
10581 * Pointer to the Ethernet device structure.
10583 * Pointer to the aso age action handler.
10586 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10587 struct mlx5_aso_age_action *age)
10589 struct mlx5_age_info *age_info;
10590 struct mlx5_age_param *age_param = &age->age_params;
10591 struct mlx5_priv *priv = dev->data->dev_private;
10592 uint16_t expected = AGE_CANDIDATE;
10594 age_info = GET_PORT_AGE_INFO(priv);
10595 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10596 AGE_FREE, false, __ATOMIC_RELAXED,
10597 __ATOMIC_RELAXED)) {
10599 * We need the lock even it is age timeout,
10600 * since age action may still in process.
10602 rte_spinlock_lock(&age_info->aged_sl);
10603 LIST_REMOVE(age, next);
10604 rte_spinlock_unlock(&age_info->aged_sl);
10605 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10610 * Release an ASO age action.
10613 * Pointer to the Ethernet device structure.
10614 * @param[in] age_idx
10615 * Index of ASO age action to release.
10617 * True if the release operation is during flow destroy operation.
10618 * False if the release operation is during action destroy operation.
10621 * 0 when age action was removed, otherwise the number of references.
10624 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10626 struct mlx5_priv *priv = dev->data->dev_private;
10627 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10628 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10629 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10632 flow_dv_aso_age_remove_from_age(dev, age);
10633 rte_spinlock_lock(&mng->free_sl);
10634 LIST_INSERT_HEAD(&mng->free, age, next);
10635 rte_spinlock_unlock(&mng->free_sl);
10641 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10644 * Pointer to the Ethernet device structure.
10647 * 0 on success, otherwise negative errno value and rte_errno is set.
10650 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10652 struct mlx5_priv *priv = dev->data->dev_private;
10653 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10654 void *old_pools = mng->pools;
10655 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10656 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10657 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10660 rte_errno = ENOMEM;
10664 memcpy(pools, old_pools,
10665 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10666 mlx5_free(old_pools);
10668 /* First ASO flow hit allocation - starting ASO data-path. */
10669 int ret = mlx5_aso_queue_start(priv->sh);
10677 mng->pools = pools;
10682 * Create and initialize a new ASO aging pool.
10685 * Pointer to the Ethernet device structure.
10686 * @param[out] age_free
10687 * Where to put the pointer of a new age action.
10690 * The age actions pool pointer and @p age_free is set on success,
10691 * NULL otherwise and rte_errno is set.
10693 static struct mlx5_aso_age_pool *
10694 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10695 struct mlx5_aso_age_action **age_free)
10697 struct mlx5_priv *priv = dev->data->dev_private;
10698 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10699 struct mlx5_aso_age_pool *pool = NULL;
10700 struct mlx5_devx_obj *obj = NULL;
10703 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10706 rte_errno = ENODATA;
10707 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10710 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10712 claim_zero(mlx5_devx_cmd_destroy(obj));
10713 rte_errno = ENOMEM;
10716 pool->flow_hit_aso_obj = obj;
10717 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10718 rte_spinlock_lock(&mng->resize_sl);
10719 pool->index = mng->next;
10720 /* Resize pools array if there is no room for the new pool in it. */
10721 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10722 claim_zero(mlx5_devx_cmd_destroy(obj));
10724 rte_spinlock_unlock(&mng->resize_sl);
10727 mng->pools[pool->index] = pool;
10729 rte_spinlock_unlock(&mng->resize_sl);
10730 /* Assign the first action in the new pool, the rest go to free list. */
10731 *age_free = &pool->actions[0];
10732 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10733 pool->actions[i].offset = i;
10734 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10740 * Allocate a ASO aging bit.
10743 * Pointer to the Ethernet device structure.
10744 * @param[out] error
10745 * Pointer to the error structure.
10748 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10751 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10753 struct mlx5_priv *priv = dev->data->dev_private;
10754 const struct mlx5_aso_age_pool *pool;
10755 struct mlx5_aso_age_action *age_free = NULL;
10756 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10759 /* Try to get the next free age action bit. */
10760 rte_spinlock_lock(&mng->free_sl);
10761 age_free = LIST_FIRST(&mng->free);
10763 LIST_REMOVE(age_free, next);
10764 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10765 rte_spinlock_unlock(&mng->free_sl);
10766 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10767 NULL, "failed to create ASO age pool");
10768 return 0; /* 0 is an error. */
10770 rte_spinlock_unlock(&mng->free_sl);
10771 pool = container_of
10772 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10773 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10775 if (!age_free->dr_action) {
10776 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10780 rte_flow_error_set(error, rte_errno,
10781 RTE_FLOW_ERROR_TYPE_ACTION,
10782 NULL, "failed to get reg_c "
10783 "for ASO flow hit");
10784 return 0; /* 0 is an error. */
10786 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10787 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10788 (priv->sh->rx_domain,
10789 pool->flow_hit_aso_obj->obj, age_free->offset,
10790 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10791 (reg_c - REG_C_0));
10792 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10793 if (!age_free->dr_action) {
10795 rte_spinlock_lock(&mng->free_sl);
10796 LIST_INSERT_HEAD(&mng->free, age_free, next);
10797 rte_spinlock_unlock(&mng->free_sl);
10798 rte_flow_error_set(error, rte_errno,
10799 RTE_FLOW_ERROR_TYPE_ACTION,
10800 NULL, "failed to create ASO "
10801 "flow hit action");
10802 return 0; /* 0 is an error. */
10805 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10806 return pool->index | ((age_free->offset + 1) << 16);
10810 * Create a age action using ASO mechanism.
10813 * Pointer to rte_eth_dev structure.
10815 * Pointer to the aging action configuration.
10816 * @param[out] error
10817 * Pointer to the error structure.
10820 * Index to flow counter on success, 0 otherwise.
10823 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10824 const struct rte_flow_action_age *age,
10825 struct rte_flow_error *error)
10827 uint32_t age_idx = 0;
10828 struct mlx5_aso_age_action *aso_age;
10830 age_idx = flow_dv_aso_age_alloc(dev, error);
10833 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10834 aso_age->age_params.context = age->context;
10835 aso_age->age_params.timeout = age->timeout;
10836 aso_age->age_params.port_id = dev->data->port_id;
10837 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10839 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10845 * Fill the flow with DV spec, lock free
10846 * (mutex should be acquired by caller).
10849 * Pointer to rte_eth_dev structure.
10850 * @param[in, out] dev_flow
10851 * Pointer to the sub flow.
10853 * Pointer to the flow attributes.
10855 * Pointer to the list of items.
10856 * @param[in] actions
10857 * Pointer to the list of actions.
10858 * @param[out] error
10859 * Pointer to the error structure.
10862 * 0 on success, a negative errno value otherwise and rte_errno is set.
10865 flow_dv_translate(struct rte_eth_dev *dev,
10866 struct mlx5_flow *dev_flow,
10867 const struct rte_flow_attr *attr,
10868 const struct rte_flow_item items[],
10869 const struct rte_flow_action actions[],
10870 struct rte_flow_error *error)
10872 struct mlx5_priv *priv = dev->data->dev_private;
10873 struct mlx5_dev_config *dev_conf = &priv->config;
10874 struct rte_flow *flow = dev_flow->flow;
10875 struct mlx5_flow_handle *handle = dev_flow->handle;
10876 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10877 struct mlx5_flow_rss_desc *rss_desc;
10878 uint64_t item_flags = 0;
10879 uint64_t last_item = 0;
10880 uint64_t action_flags = 0;
10881 struct mlx5_flow_dv_matcher matcher = {
10883 .size = sizeof(matcher.mask.buf) -
10884 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10888 bool actions_end = false;
10890 struct mlx5_flow_dv_modify_hdr_resource res;
10891 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10892 sizeof(struct mlx5_modification_cmd) *
10893 (MLX5_MAX_MODIFY_NUM + 1)];
10895 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10896 const struct rte_flow_action_count *count = NULL;
10897 const struct rte_flow_action_age *age = NULL;
10898 union flow_dv_attr flow_attr = { .attr = 0 };
10900 union mlx5_flow_tbl_key tbl_key;
10901 uint32_t modify_action_position = UINT32_MAX;
10902 void *match_mask = matcher.mask.buf;
10903 void *match_value = dev_flow->dv.value.buf;
10904 uint8_t next_protocol = 0xff;
10905 struct rte_vlan_hdr vlan = { 0 };
10906 struct mlx5_flow_dv_dest_array_resource mdest_res;
10907 struct mlx5_flow_dv_sample_resource sample_res;
10908 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10909 const struct rte_flow_action_sample *sample = NULL;
10910 struct mlx5_flow_sub_actions_list *sample_act;
10911 uint32_t sample_act_pos = UINT32_MAX;
10912 uint32_t num_of_dest = 0;
10913 int tmp_actions_n = 0;
10916 const struct mlx5_flow_tunnel *tunnel;
10917 struct flow_grp_info grp_info = {
10918 .external = !!dev_flow->external,
10919 .transfer = !!attr->transfer,
10920 .fdb_def_rule = !!priv->fdb_def_rule,
10921 .skip_scale = dev_flow->skip_scale &
10922 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10926 return rte_flow_error_set(error, ENOMEM,
10927 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10929 "failed to push flow workspace");
10930 rss_desc = &wks->rss_desc;
10931 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10932 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10933 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10934 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10935 /* update normal path action resource into last index of array */
10936 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10937 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10938 flow_items_to_tunnel(items) :
10939 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10940 flow_actions_to_tunnel(actions) :
10941 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10942 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10943 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10944 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10945 (dev, tunnel, attr, items, actions);
10946 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10950 dev_flow->dv.group = table;
10951 if (attr->transfer)
10952 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10953 /* number of actions must be set to 0 in case of dirty stack. */
10954 mhdr_res->actions_num = 0;
10955 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10957 * do not add decap action if match rule drops packet
10958 * HW rejects rules with decap & drop
10960 * if tunnel match rule was inserted before matching tunnel set
10961 * rule flow table used in the match rule must be registered.
10962 * current implementation handles that in the
10963 * flow_dv_match_register() at the function end.
10965 bool add_decap = true;
10966 const struct rte_flow_action *ptr = actions;
10968 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10969 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10975 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10979 dev_flow->dv.actions[actions_n++] =
10980 dev_flow->dv.encap_decap->action;
10981 action_flags |= MLX5_FLOW_ACTION_DECAP;
10984 for (; !actions_end ; actions++) {
10985 const struct rte_flow_action_queue *queue;
10986 const struct rte_flow_action_rss *rss;
10987 const struct rte_flow_action *action = actions;
10988 const uint8_t *rss_key;
10989 const struct rte_flow_action_meter *mtr;
10990 struct mlx5_flow_tbl_resource *tbl;
10991 struct mlx5_aso_age_action *age_act;
10992 uint32_t port_id = 0;
10993 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10994 int action_type = actions->type;
10995 const struct rte_flow_action *found_action = NULL;
10996 struct mlx5_flow_meter *fm = NULL;
10997 uint32_t jump_group = 0;
10999 if (!mlx5_flow_os_action_supported(action_type))
11000 return rte_flow_error_set(error, ENOTSUP,
11001 RTE_FLOW_ERROR_TYPE_ACTION,
11003 "action not supported");
11004 switch (action_type) {
11005 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11006 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11008 case RTE_FLOW_ACTION_TYPE_VOID:
11010 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11011 if (flow_dv_translate_action_port_id(dev, action,
11014 port_id_resource.port_id = port_id;
11015 MLX5_ASSERT(!handle->rix_port_id_action);
11016 if (flow_dv_port_id_action_resource_register
11017 (dev, &port_id_resource, dev_flow, error))
11019 dev_flow->dv.actions[actions_n++] =
11020 dev_flow->dv.port_id_action->action;
11021 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11022 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11023 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11026 case RTE_FLOW_ACTION_TYPE_FLAG:
11027 action_flags |= MLX5_FLOW_ACTION_FLAG;
11028 dev_flow->handle->mark = 1;
11029 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11030 struct rte_flow_action_mark mark = {
11031 .id = MLX5_FLOW_MARK_DEFAULT,
11034 if (flow_dv_convert_action_mark(dev, &mark,
11038 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11041 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11043 * Only one FLAG or MARK is supported per device flow
11044 * right now. So the pointer to the tag resource must be
11045 * zero before the register process.
11047 MLX5_ASSERT(!handle->dvh.rix_tag);
11048 if (flow_dv_tag_resource_register(dev, tag_be,
11051 MLX5_ASSERT(dev_flow->dv.tag_resource);
11052 dev_flow->dv.actions[actions_n++] =
11053 dev_flow->dv.tag_resource->action;
11055 case RTE_FLOW_ACTION_TYPE_MARK:
11056 action_flags |= MLX5_FLOW_ACTION_MARK;
11057 dev_flow->handle->mark = 1;
11058 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11059 const struct rte_flow_action_mark *mark =
11060 (const struct rte_flow_action_mark *)
11063 if (flow_dv_convert_action_mark(dev, mark,
11067 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11071 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11072 /* Legacy (non-extensive) MARK action. */
11073 tag_be = mlx5_flow_mark_set
11074 (((const struct rte_flow_action_mark *)
11075 (actions->conf))->id);
11076 MLX5_ASSERT(!handle->dvh.rix_tag);
11077 if (flow_dv_tag_resource_register(dev, tag_be,
11080 MLX5_ASSERT(dev_flow->dv.tag_resource);
11081 dev_flow->dv.actions[actions_n++] =
11082 dev_flow->dv.tag_resource->action;
11084 case RTE_FLOW_ACTION_TYPE_SET_META:
11085 if (flow_dv_convert_action_set_meta
11086 (dev, mhdr_res, attr,
11087 (const struct rte_flow_action_set_meta *)
11088 actions->conf, error))
11090 action_flags |= MLX5_FLOW_ACTION_SET_META;
11092 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11093 if (flow_dv_convert_action_set_tag
11095 (const struct rte_flow_action_set_tag *)
11096 actions->conf, error))
11098 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11100 case RTE_FLOW_ACTION_TYPE_DROP:
11101 action_flags |= MLX5_FLOW_ACTION_DROP;
11102 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11104 case RTE_FLOW_ACTION_TYPE_QUEUE:
11105 queue = actions->conf;
11106 rss_desc->queue_num = 1;
11107 rss_desc->queue[0] = queue->index;
11108 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11109 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11110 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11113 case RTE_FLOW_ACTION_TYPE_RSS:
11114 rss = actions->conf;
11115 memcpy(rss_desc->queue, rss->queue,
11116 rss->queue_num * sizeof(uint16_t));
11117 rss_desc->queue_num = rss->queue_num;
11118 /* NULL RSS key indicates default RSS key. */
11119 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11120 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11122 * rss->level and rss.types should be set in advance
11123 * when expanding items for RSS.
11125 action_flags |= MLX5_FLOW_ACTION_RSS;
11126 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11127 MLX5_FLOW_FATE_SHARED_RSS :
11128 MLX5_FLOW_FATE_QUEUE;
11130 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11131 flow->age = (uint32_t)(uintptr_t)(action->conf);
11132 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11133 __atomic_fetch_add(&age_act->refcnt, 1,
11135 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11136 action_flags |= MLX5_FLOW_ACTION_AGE;
11138 case RTE_FLOW_ACTION_TYPE_AGE:
11139 if (priv->sh->flow_hit_aso_en && attr->group) {
11141 * Create one shared age action, to be used
11142 * by all sub-flows.
11146 flow_dv_translate_create_aso_age
11147 (dev, action->conf,
11150 return rte_flow_error_set
11152 RTE_FLOW_ERROR_TYPE_ACTION,
11154 "can't create ASO age action");
11156 dev_flow->dv.actions[actions_n++] =
11157 (flow_aso_age_get_by_idx
11158 (dev, flow->age))->dr_action;
11159 action_flags |= MLX5_FLOW_ACTION_AGE;
11163 case RTE_FLOW_ACTION_TYPE_COUNT:
11164 if (!dev_conf->devx) {
11165 return rte_flow_error_set
11167 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11169 "count action not supported");
11171 /* Save information first, will apply later. */
11172 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11173 count = action->conf;
11175 age = action->conf;
11176 action_flags |= MLX5_FLOW_ACTION_COUNT;
11178 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11179 dev_flow->dv.actions[actions_n++] =
11180 priv->sh->pop_vlan_action;
11181 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11183 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11184 if (!(action_flags &
11185 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11186 flow_dev_get_vlan_info_from_items(items, &vlan);
11187 vlan.eth_proto = rte_be_to_cpu_16
11188 ((((const struct rte_flow_action_of_push_vlan *)
11189 actions->conf)->ethertype));
11190 found_action = mlx5_flow_find_action
11192 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11194 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11195 found_action = mlx5_flow_find_action
11197 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11199 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11200 if (flow_dv_create_action_push_vlan
11201 (dev, attr, &vlan, dev_flow, error))
11203 dev_flow->dv.actions[actions_n++] =
11204 dev_flow->dv.push_vlan_res->action;
11205 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11207 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11208 /* of_vlan_push action handled this action */
11209 MLX5_ASSERT(action_flags &
11210 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11212 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11213 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11215 flow_dev_get_vlan_info_from_items(items, &vlan);
11216 mlx5_update_vlan_vid_pcp(actions, &vlan);
11217 /* If no VLAN push - this is a modify header action */
11218 if (flow_dv_convert_action_modify_vlan_vid
11219 (mhdr_res, actions, error))
11221 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11223 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11224 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11225 if (flow_dv_create_action_l2_encap(dev, actions,
11230 dev_flow->dv.actions[actions_n++] =
11231 dev_flow->dv.encap_decap->action;
11232 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11233 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11234 sample_act->action_flags |=
11235 MLX5_FLOW_ACTION_ENCAP;
11237 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11238 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11239 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11243 dev_flow->dv.actions[actions_n++] =
11244 dev_flow->dv.encap_decap->action;
11245 action_flags |= MLX5_FLOW_ACTION_DECAP;
11247 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11248 /* Handle encap with preceding decap. */
11249 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11250 if (flow_dv_create_action_raw_encap
11251 (dev, actions, dev_flow, attr, error))
11253 dev_flow->dv.actions[actions_n++] =
11254 dev_flow->dv.encap_decap->action;
11256 /* Handle encap without preceding decap. */
11257 if (flow_dv_create_action_l2_encap
11258 (dev, actions, dev_flow, attr->transfer,
11261 dev_flow->dv.actions[actions_n++] =
11262 dev_flow->dv.encap_decap->action;
11264 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11265 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11266 sample_act->action_flags |=
11267 MLX5_FLOW_ACTION_ENCAP;
11269 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11270 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11272 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11273 if (flow_dv_create_action_l2_decap
11274 (dev, dev_flow, attr->transfer, error))
11276 dev_flow->dv.actions[actions_n++] =
11277 dev_flow->dv.encap_decap->action;
11279 /* If decap is followed by encap, handle it at encap. */
11280 action_flags |= MLX5_FLOW_ACTION_DECAP;
11282 case RTE_FLOW_ACTION_TYPE_JUMP:
11283 jump_group = ((const struct rte_flow_action_jump *)
11284 action->conf)->group;
11285 grp_info.std_tbl_fix = 0;
11286 if (dev_flow->skip_scale &
11287 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11288 grp_info.skip_scale = 1;
11290 grp_info.skip_scale = 0;
11291 ret = mlx5_flow_group_to_table(dev, tunnel,
11297 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11299 !!dev_flow->external,
11300 tunnel, jump_group, 0,
11303 return rte_flow_error_set
11305 RTE_FLOW_ERROR_TYPE_ACTION,
11307 "cannot create jump action.");
11308 if (flow_dv_jump_tbl_resource_register
11309 (dev, tbl, dev_flow, error)) {
11310 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11311 return rte_flow_error_set
11313 RTE_FLOW_ERROR_TYPE_ACTION,
11315 "cannot create jump action.");
11317 dev_flow->dv.actions[actions_n++] =
11318 dev_flow->dv.jump->action;
11319 action_flags |= MLX5_FLOW_ACTION_JUMP;
11320 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11321 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11324 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11325 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11326 if (flow_dv_convert_action_modify_mac
11327 (mhdr_res, actions, error))
11329 action_flags |= actions->type ==
11330 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11331 MLX5_FLOW_ACTION_SET_MAC_SRC :
11332 MLX5_FLOW_ACTION_SET_MAC_DST;
11334 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11335 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11336 if (flow_dv_convert_action_modify_ipv4
11337 (mhdr_res, actions, error))
11339 action_flags |= actions->type ==
11340 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11341 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11342 MLX5_FLOW_ACTION_SET_IPV4_DST;
11344 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11345 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11346 if (flow_dv_convert_action_modify_ipv6
11347 (mhdr_res, actions, error))
11349 action_flags |= actions->type ==
11350 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11351 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11352 MLX5_FLOW_ACTION_SET_IPV6_DST;
11354 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11355 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11356 if (flow_dv_convert_action_modify_tp
11357 (mhdr_res, actions, items,
11358 &flow_attr, dev_flow, !!(action_flags &
11359 MLX5_FLOW_ACTION_DECAP), error))
11361 action_flags |= actions->type ==
11362 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11363 MLX5_FLOW_ACTION_SET_TP_SRC :
11364 MLX5_FLOW_ACTION_SET_TP_DST;
11366 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11367 if (flow_dv_convert_action_modify_dec_ttl
11368 (mhdr_res, items, &flow_attr, dev_flow,
11370 MLX5_FLOW_ACTION_DECAP), error))
11372 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11374 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11375 if (flow_dv_convert_action_modify_ttl
11376 (mhdr_res, actions, items, &flow_attr,
11377 dev_flow, !!(action_flags &
11378 MLX5_FLOW_ACTION_DECAP), error))
11380 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11382 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11383 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11384 if (flow_dv_convert_action_modify_tcp_seq
11385 (mhdr_res, actions, error))
11387 action_flags |= actions->type ==
11388 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11389 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11390 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11393 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11394 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11395 if (flow_dv_convert_action_modify_tcp_ack
11396 (mhdr_res, actions, error))
11398 action_flags |= actions->type ==
11399 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11400 MLX5_FLOW_ACTION_INC_TCP_ACK :
11401 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11403 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11404 if (flow_dv_convert_action_set_reg
11405 (mhdr_res, actions, error))
11407 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11409 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11410 if (flow_dv_convert_action_copy_mreg
11411 (dev, mhdr_res, actions, error))
11413 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11415 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11416 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11417 dev_flow->handle->fate_action =
11418 MLX5_FLOW_FATE_DEFAULT_MISS;
11420 case RTE_FLOW_ACTION_TYPE_METER:
11421 mtr = actions->conf;
11422 if (!flow->meter) {
11423 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11426 return rte_flow_error_set(error,
11428 RTE_FLOW_ERROR_TYPE_ACTION,
11431 "or invalid parameters");
11432 flow->meter = fm->idx;
11434 /* Set the meter action. */
11436 fm = mlx5_ipool_get(priv->sh->ipool
11437 [MLX5_IPOOL_MTR], flow->meter);
11439 return rte_flow_error_set(error,
11441 RTE_FLOW_ERROR_TYPE_ACTION,
11444 "or invalid parameters");
11446 dev_flow->dv.actions[actions_n++] =
11447 fm->mfts->meter_action;
11448 action_flags |= MLX5_FLOW_ACTION_METER;
11450 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11451 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11454 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11456 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11457 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11460 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11462 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11463 sample_act_pos = actions_n;
11464 sample = (const struct rte_flow_action_sample *)
11467 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11468 /* put encap action into group if work with port id */
11469 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11470 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11471 sample_act->action_flags |=
11472 MLX5_FLOW_ACTION_ENCAP;
11474 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11475 if (flow_dv_convert_action_modify_field
11476 (dev, mhdr_res, actions, attr, error))
11478 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11480 case RTE_FLOW_ACTION_TYPE_END:
11481 actions_end = true;
11482 if (mhdr_res->actions_num) {
11483 /* create modify action if needed. */
11484 if (flow_dv_modify_hdr_resource_register
11485 (dev, mhdr_res, dev_flow, error))
11487 dev_flow->dv.actions[modify_action_position] =
11488 handle->dvh.modify_hdr->action;
11490 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11492 * Create one count action, to be used
11493 * by all sub-flows.
11495 if (!flow->counter) {
11497 flow_dv_translate_create_counter
11498 (dev, dev_flow, count,
11500 if (!flow->counter)
11501 return rte_flow_error_set
11503 RTE_FLOW_ERROR_TYPE_ACTION,
11504 NULL, "cannot create counter"
11507 dev_flow->dv.actions[actions_n] =
11508 (flow_dv_counter_get_by_idx(dev,
11509 flow->counter, NULL))->action;
11515 if (mhdr_res->actions_num &&
11516 modify_action_position == UINT32_MAX)
11517 modify_action_position = actions_n++;
11519 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11520 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11521 int item_type = items->type;
11523 if (!mlx5_flow_os_item_supported(item_type))
11524 return rte_flow_error_set(error, ENOTSUP,
11525 RTE_FLOW_ERROR_TYPE_ITEM,
11526 NULL, "item not supported");
11527 switch (item_type) {
11528 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11529 flow_dv_translate_item_port_id
11530 (dev, match_mask, match_value, items, attr);
11531 last_item = MLX5_FLOW_ITEM_PORT_ID;
11533 case RTE_FLOW_ITEM_TYPE_ETH:
11534 flow_dv_translate_item_eth(match_mask, match_value,
11536 dev_flow->dv.group);
11537 matcher.priority = action_flags &
11538 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11539 !dev_flow->external ?
11540 MLX5_PRIORITY_MAP_L3 :
11541 MLX5_PRIORITY_MAP_L2;
11542 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11543 MLX5_FLOW_LAYER_OUTER_L2;
11545 case RTE_FLOW_ITEM_TYPE_VLAN:
11546 flow_dv_translate_item_vlan(dev_flow,
11547 match_mask, match_value,
11549 dev_flow->dv.group);
11550 matcher.priority = MLX5_PRIORITY_MAP_L2;
11551 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11552 MLX5_FLOW_LAYER_INNER_VLAN) :
11553 (MLX5_FLOW_LAYER_OUTER_L2 |
11554 MLX5_FLOW_LAYER_OUTER_VLAN);
11556 case RTE_FLOW_ITEM_TYPE_IPV4:
11557 mlx5_flow_tunnel_ip_check(items, next_protocol,
11558 &item_flags, &tunnel);
11559 flow_dv_translate_item_ipv4(match_mask, match_value,
11561 dev_flow->dv.group);
11562 matcher.priority = MLX5_PRIORITY_MAP_L3;
11563 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11564 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11565 if (items->mask != NULL &&
11566 ((const struct rte_flow_item_ipv4 *)
11567 items->mask)->hdr.next_proto_id) {
11569 ((const struct rte_flow_item_ipv4 *)
11570 (items->spec))->hdr.next_proto_id;
11572 ((const struct rte_flow_item_ipv4 *)
11573 (items->mask))->hdr.next_proto_id;
11575 /* Reset for inner layer. */
11576 next_protocol = 0xff;
11579 case RTE_FLOW_ITEM_TYPE_IPV6:
11580 mlx5_flow_tunnel_ip_check(items, next_protocol,
11581 &item_flags, &tunnel);
11582 flow_dv_translate_item_ipv6(match_mask, match_value,
11584 dev_flow->dv.group);
11585 matcher.priority = MLX5_PRIORITY_MAP_L3;
11586 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11587 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11588 if (items->mask != NULL &&
11589 ((const struct rte_flow_item_ipv6 *)
11590 items->mask)->hdr.proto) {
11592 ((const struct rte_flow_item_ipv6 *)
11593 items->spec)->hdr.proto;
11595 ((const struct rte_flow_item_ipv6 *)
11596 items->mask)->hdr.proto;
11598 /* Reset for inner layer. */
11599 next_protocol = 0xff;
11602 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11603 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11606 last_item = tunnel ?
11607 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11608 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11609 if (items->mask != NULL &&
11610 ((const struct rte_flow_item_ipv6_frag_ext *)
11611 items->mask)->hdr.next_header) {
11613 ((const struct rte_flow_item_ipv6_frag_ext *)
11614 items->spec)->hdr.next_header;
11616 ((const struct rte_flow_item_ipv6_frag_ext *)
11617 items->mask)->hdr.next_header;
11619 /* Reset for inner layer. */
11620 next_protocol = 0xff;
11623 case RTE_FLOW_ITEM_TYPE_TCP:
11624 flow_dv_translate_item_tcp(match_mask, match_value,
11626 matcher.priority = MLX5_PRIORITY_MAP_L4;
11627 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11628 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11630 case RTE_FLOW_ITEM_TYPE_UDP:
11631 flow_dv_translate_item_udp(match_mask, match_value,
11633 matcher.priority = MLX5_PRIORITY_MAP_L4;
11634 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11635 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11637 case RTE_FLOW_ITEM_TYPE_GRE:
11638 flow_dv_translate_item_gre(match_mask, match_value,
11640 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11641 last_item = MLX5_FLOW_LAYER_GRE;
11643 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11644 flow_dv_translate_item_gre_key(match_mask,
11645 match_value, items);
11646 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11648 case RTE_FLOW_ITEM_TYPE_NVGRE:
11649 flow_dv_translate_item_nvgre(match_mask, match_value,
11651 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11652 last_item = MLX5_FLOW_LAYER_GRE;
11654 case RTE_FLOW_ITEM_TYPE_VXLAN:
11655 flow_dv_translate_item_vxlan(match_mask, match_value,
11657 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11658 last_item = MLX5_FLOW_LAYER_VXLAN;
11660 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11661 flow_dv_translate_item_vxlan_gpe(match_mask,
11662 match_value, items,
11664 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11665 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11667 case RTE_FLOW_ITEM_TYPE_GENEVE:
11668 flow_dv_translate_item_geneve(match_mask, match_value,
11670 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11671 last_item = MLX5_FLOW_LAYER_GENEVE;
11673 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11674 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11678 return rte_flow_error_set(error, -ret,
11679 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11680 "cannot create GENEVE TLV option");
11681 flow->geneve_tlv_option = 1;
11682 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11684 case RTE_FLOW_ITEM_TYPE_MPLS:
11685 flow_dv_translate_item_mpls(match_mask, match_value,
11686 items, last_item, tunnel);
11687 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11688 last_item = MLX5_FLOW_LAYER_MPLS;
11690 case RTE_FLOW_ITEM_TYPE_MARK:
11691 flow_dv_translate_item_mark(dev, match_mask,
11692 match_value, items);
11693 last_item = MLX5_FLOW_ITEM_MARK;
11695 case RTE_FLOW_ITEM_TYPE_META:
11696 flow_dv_translate_item_meta(dev, match_mask,
11697 match_value, attr, items);
11698 last_item = MLX5_FLOW_ITEM_METADATA;
11700 case RTE_FLOW_ITEM_TYPE_ICMP:
11701 flow_dv_translate_item_icmp(match_mask, match_value,
11703 last_item = MLX5_FLOW_LAYER_ICMP;
11705 case RTE_FLOW_ITEM_TYPE_ICMP6:
11706 flow_dv_translate_item_icmp6(match_mask, match_value,
11708 last_item = MLX5_FLOW_LAYER_ICMP6;
11710 case RTE_FLOW_ITEM_TYPE_TAG:
11711 flow_dv_translate_item_tag(dev, match_mask,
11712 match_value, items);
11713 last_item = MLX5_FLOW_ITEM_TAG;
11715 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11716 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11717 match_value, items);
11718 last_item = MLX5_FLOW_ITEM_TAG;
11720 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11721 flow_dv_translate_item_tx_queue(dev, match_mask,
11724 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11726 case RTE_FLOW_ITEM_TYPE_GTP:
11727 flow_dv_translate_item_gtp(match_mask, match_value,
11729 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11730 last_item = MLX5_FLOW_LAYER_GTP;
11732 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11733 ret = flow_dv_translate_item_gtp_psc(match_mask,
11737 return rte_flow_error_set(error, -ret,
11738 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11739 "cannot create GTP PSC item");
11740 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11742 case RTE_FLOW_ITEM_TYPE_ECPRI:
11743 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11744 /* Create it only the first time to be used. */
11745 ret = mlx5_flex_parser_ecpri_alloc(dev);
11747 return rte_flow_error_set
11749 RTE_FLOW_ERROR_TYPE_ITEM,
11751 "cannot create eCPRI parser");
11753 /* Adjust the length matcher and device flow value. */
11754 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11755 dev_flow->dv.value.size =
11756 MLX5_ST_SZ_BYTES(fte_match_param);
11757 flow_dv_translate_item_ecpri(dev, match_mask,
11758 match_value, items);
11759 /* No other protocol should follow eCPRI layer. */
11760 last_item = MLX5_FLOW_LAYER_ECPRI;
11765 item_flags |= last_item;
11768 * When E-Switch mode is enabled, we have two cases where we need to
11769 * set the source port manually.
11770 * The first one, is in case of Nic steering rule, and the second is
11771 * E-Switch rule where no port_id item was found. In both cases
11772 * the source port is set according the current port in use.
11774 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11775 (priv->representor || priv->master)) {
11776 if (flow_dv_translate_item_port_id(dev, match_mask,
11777 match_value, NULL, attr))
11780 #ifdef RTE_LIBRTE_MLX5_DEBUG
11781 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11782 dev_flow->dv.value.buf));
11785 * Layers may be already initialized from prefix flow if this dev_flow
11786 * is the suffix flow.
11788 handle->layers |= item_flags;
11789 if (action_flags & MLX5_FLOW_ACTION_RSS)
11790 flow_dv_hashfields_set(dev_flow, rss_desc);
11791 /* If has RSS action in the sample action, the Sample/Mirror resource
11792 * should be registered after the hash filed be update.
11794 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11795 ret = flow_dv_translate_action_sample(dev,
11804 ret = flow_dv_create_action_sample(dev,
11813 return rte_flow_error_set
11815 RTE_FLOW_ERROR_TYPE_ACTION,
11817 "cannot create sample action");
11818 if (num_of_dest > 1) {
11819 dev_flow->dv.actions[sample_act_pos] =
11820 dev_flow->dv.dest_array_res->action;
11822 dev_flow->dv.actions[sample_act_pos] =
11823 dev_flow->dv.sample_res->verbs_action;
11827 * For multiple destination (sample action with ratio=1), the encap
11828 * action and port id action will be combined into group action.
11829 * So need remove the original these actions in the flow and only
11830 * use the sample action instead of.
11832 if (num_of_dest > 1 &&
11833 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11835 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11837 for (i = 0; i < actions_n; i++) {
11838 if ((sample_act->dr_encap_action &&
11839 sample_act->dr_encap_action ==
11840 dev_flow->dv.actions[i]) ||
11841 (sample_act->dr_port_id_action &&
11842 sample_act->dr_port_id_action ==
11843 dev_flow->dv.actions[i]) ||
11844 (sample_act->dr_jump_action &&
11845 sample_act->dr_jump_action ==
11846 dev_flow->dv.actions[i]))
11848 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11850 memcpy((void *)dev_flow->dv.actions,
11851 (void *)temp_actions,
11852 tmp_actions_n * sizeof(void *));
11853 actions_n = tmp_actions_n;
11855 dev_flow->dv.actions_n = actions_n;
11856 dev_flow->act_flags = action_flags;
11857 /* Register matcher. */
11858 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11859 matcher.mask.size);
11860 matcher.priority = mlx5_get_matcher_priority(dev, attr,
11862 /* reserved field no needs to be set to 0 here. */
11863 tbl_key.domain = attr->transfer;
11864 tbl_key.direction = attr->egress;
11865 tbl_key.table_id = dev_flow->dv.group;
11866 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11867 tunnel, attr->group, error))
11873 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11876 * @param[in, out] action
11877 * Shred RSS action holding hash RX queue objects.
11878 * @param[in] hash_fields
11879 * Defines combination of packet fields to participate in RX hash.
11880 * @param[in] tunnel
11882 * @param[in] hrxq_idx
11883 * Hash RX queue index to set.
11886 * 0 on success, otherwise negative errno value.
11889 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11890 const uint64_t hash_fields,
11893 uint32_t *hrxqs = action->hrxq;
11895 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11896 case MLX5_RSS_HASH_IPV4:
11897 /* fall-through. */
11898 case MLX5_RSS_HASH_IPV4_DST_ONLY:
11899 /* fall-through. */
11900 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11901 hrxqs[0] = hrxq_idx;
11903 case MLX5_RSS_HASH_IPV4_TCP:
11904 /* fall-through. */
11905 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11906 /* fall-through. */
11907 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11908 hrxqs[1] = hrxq_idx;
11910 case MLX5_RSS_HASH_IPV4_UDP:
11911 /* fall-through. */
11912 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11913 /* fall-through. */
11914 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11915 hrxqs[2] = hrxq_idx;
11917 case MLX5_RSS_HASH_IPV6:
11918 /* fall-through. */
11919 case MLX5_RSS_HASH_IPV6_DST_ONLY:
11920 /* fall-through. */
11921 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11922 hrxqs[3] = hrxq_idx;
11924 case MLX5_RSS_HASH_IPV6_TCP:
11925 /* fall-through. */
11926 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11927 /* fall-through. */
11928 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11929 hrxqs[4] = hrxq_idx;
11931 case MLX5_RSS_HASH_IPV6_UDP:
11932 /* fall-through. */
11933 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11934 /* fall-through. */
11935 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11936 hrxqs[5] = hrxq_idx;
11938 case MLX5_RSS_HASH_NONE:
11939 hrxqs[6] = hrxq_idx;
11947 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11951 * Pointer to the Ethernet device structure.
11953 * Shared RSS action ID holding hash RX queue objects.
11954 * @param[in] hash_fields
11955 * Defines combination of packet fields to participate in RX hash.
11956 * @param[in] tunnel
11960 * Valid hash RX queue index, otherwise 0.
11963 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11964 const uint64_t hash_fields)
11966 struct mlx5_priv *priv = dev->data->dev_private;
11967 struct mlx5_shared_action_rss *shared_rss =
11968 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11969 const uint32_t *hrxqs = shared_rss->hrxq;
11971 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11972 case MLX5_RSS_HASH_IPV4:
11973 /* fall-through. */
11974 case MLX5_RSS_HASH_IPV4_DST_ONLY:
11975 /* fall-through. */
11976 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11978 case MLX5_RSS_HASH_IPV4_TCP:
11979 /* fall-through. */
11980 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11981 /* fall-through. */
11982 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11984 case MLX5_RSS_HASH_IPV4_UDP:
11985 /* fall-through. */
11986 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11987 /* fall-through. */
11988 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11990 case MLX5_RSS_HASH_IPV6:
11991 /* fall-through. */
11992 case MLX5_RSS_HASH_IPV6_DST_ONLY:
11993 /* fall-through. */
11994 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11996 case MLX5_RSS_HASH_IPV6_TCP:
11997 /* fall-through. */
11998 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11999 /* fall-through. */
12000 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12002 case MLX5_RSS_HASH_IPV6_UDP:
12003 /* fall-through. */
12004 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12005 /* fall-through. */
12006 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12008 case MLX5_RSS_HASH_NONE:
12017 * Apply the flow to the NIC, lock free,
12018 * (mutex should be acquired by caller).
12021 * Pointer to the Ethernet device structure.
12022 * @param[in, out] flow
12023 * Pointer to flow structure.
12024 * @param[out] error
12025 * Pointer to error structure.
12028 * 0 on success, a negative errno value otherwise and rte_errno is set.
12031 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12032 struct rte_flow_error *error)
12034 struct mlx5_flow_dv_workspace *dv;
12035 struct mlx5_flow_handle *dh;
12036 struct mlx5_flow_handle_dv *dv_h;
12037 struct mlx5_flow *dev_flow;
12038 struct mlx5_priv *priv = dev->data->dev_private;
12039 uint32_t handle_idx;
12043 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12044 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12047 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12048 dev_flow = &wks->flows[idx];
12049 dv = &dev_flow->dv;
12050 dh = dev_flow->handle;
12053 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12054 if (dv->transfer) {
12055 MLX5_ASSERT(priv->sh->dr_drop_action);
12056 dv->actions[n++] = priv->sh->dr_drop_action;
12058 #ifdef HAVE_MLX5DV_DR
12059 /* DR supports drop action placeholder. */
12060 MLX5_ASSERT(priv->sh->dr_drop_action);
12061 dv->actions[n++] = priv->sh->dr_drop_action;
12063 /* For DV we use the explicit drop queue. */
12064 MLX5_ASSERT(priv->drop_queue.hrxq);
12066 priv->drop_queue.hrxq->action;
12069 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12070 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12071 struct mlx5_hrxq *hrxq;
12074 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12079 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12080 "cannot get hash queue");
12083 dh->rix_hrxq = hrxq_idx;
12084 dv->actions[n++] = hrxq->action;
12085 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12086 struct mlx5_hrxq *hrxq = NULL;
12089 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12090 rss_desc->shared_rss,
12091 dev_flow->hash_fields);
12093 hrxq = mlx5_ipool_get
12094 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12099 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12100 "cannot get hash queue");
12103 dh->rix_srss = rss_desc->shared_rss;
12104 dv->actions[n++] = hrxq->action;
12105 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12106 if (!priv->sh->default_miss_action) {
12109 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12110 "default miss action not be created.");
12113 dv->actions[n++] = priv->sh->default_miss_action;
12115 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12116 (void *)&dv->value, n,
12117 dv->actions, &dh->drv_flow);
12119 rte_flow_error_set(error, errno,
12120 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12122 "hardware refuses to create flow");
12125 if (priv->vmwa_context &&
12126 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12128 * The rule contains the VLAN pattern.
12129 * For VF we are going to create VLAN
12130 * interface to make hypervisor set correct
12131 * e-Switch vport context.
12133 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12138 err = rte_errno; /* Save rte_errno before cleanup. */
12139 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12140 handle_idx, dh, next) {
12141 /* hrxq is union, don't clear it if the flag is not set. */
12142 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12143 mlx5_hrxq_release(dev, dh->rix_hrxq);
12145 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12148 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12149 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12151 rte_errno = err; /* Restore rte_errno. */
12156 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12157 struct mlx5_cache_entry *entry)
12159 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12162 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12167 * Release the flow matcher.
12170 * Pointer to Ethernet device.
12172 * Index to port ID action resource.
12175 * 1 while a reference on it exists, 0 when freed.
12178 flow_dv_matcher_release(struct rte_eth_dev *dev,
12179 struct mlx5_flow_handle *handle)
12181 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12182 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12183 typeof(*tbl), tbl);
12186 MLX5_ASSERT(matcher->matcher_object);
12187 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12188 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12193 * Release encap_decap resource.
12196 * Pointer to the hash list.
12198 * Pointer to exist resource entry object.
12201 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12202 struct mlx5_hlist_entry *entry)
12204 struct mlx5_dev_ctx_shared *sh = list->ctx;
12205 struct mlx5_flow_dv_encap_decap_resource *res =
12206 container_of(entry, typeof(*res), entry);
12208 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12209 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12213 * Release an encap/decap resource.
12216 * Pointer to Ethernet device.
12217 * @param encap_decap_idx
12218 * Index of encap decap resource.
12221 * 1 while a reference on it exists, 0 when freed.
12224 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12225 uint32_t encap_decap_idx)
12227 struct mlx5_priv *priv = dev->data->dev_private;
12228 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12230 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12232 if (!cache_resource)
12234 MLX5_ASSERT(cache_resource->action);
12235 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12236 &cache_resource->entry);
12240 * Release an jump to table action resource.
12243 * Pointer to Ethernet device.
12245 * Index to the jump action resource.
12248 * 1 while a reference on it exists, 0 when freed.
12251 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12254 struct mlx5_priv *priv = dev->data->dev_private;
12255 struct mlx5_flow_tbl_data_entry *tbl_data;
12257 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12261 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12265 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12266 struct mlx5_hlist_entry *entry)
12268 struct mlx5_flow_dv_modify_hdr_resource *res =
12269 container_of(entry, typeof(*res), entry);
12271 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12276 * Release a modify-header resource.
12279 * Pointer to Ethernet device.
12281 * Pointer to mlx5_flow_handle.
12284 * 1 while a reference on it exists, 0 when freed.
12287 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12288 struct mlx5_flow_handle *handle)
12290 struct mlx5_priv *priv = dev->data->dev_private;
12291 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12293 MLX5_ASSERT(entry->action);
12294 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12298 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12299 struct mlx5_cache_entry *entry)
12301 struct mlx5_dev_ctx_shared *sh = list->ctx;
12302 struct mlx5_flow_dv_port_id_action_resource *cache =
12303 container_of(entry, typeof(*cache), entry);
12305 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12306 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12310 * Release port ID action resource.
12313 * Pointer to Ethernet device.
12315 * Pointer to mlx5_flow_handle.
12318 * 1 while a reference on it exists, 0 when freed.
12321 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12324 struct mlx5_priv *priv = dev->data->dev_private;
12325 struct mlx5_flow_dv_port_id_action_resource *cache;
12327 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12330 MLX5_ASSERT(cache->action);
12331 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12336 * Release shared RSS action resource.
12339 * Pointer to Ethernet device.
12341 * Shared RSS action index.
12344 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12346 struct mlx5_priv *priv = dev->data->dev_private;
12347 struct mlx5_shared_action_rss *shared_rss;
12349 shared_rss = mlx5_ipool_get
12350 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12351 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12355 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12356 struct mlx5_cache_entry *entry)
12358 struct mlx5_dev_ctx_shared *sh = list->ctx;
12359 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12360 container_of(entry, typeof(*cache), entry);
12362 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12363 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12367 * Release push vlan action resource.
12370 * Pointer to Ethernet device.
12372 * Pointer to mlx5_flow_handle.
12375 * 1 while a reference on it exists, 0 when freed.
12378 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12379 struct mlx5_flow_handle *handle)
12381 struct mlx5_priv *priv = dev->data->dev_private;
12382 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12383 uint32_t idx = handle->dvh.rix_push_vlan;
12385 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12388 MLX5_ASSERT(cache->action);
12389 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12394 * Release the fate resource.
12397 * Pointer to Ethernet device.
12399 * Pointer to mlx5_flow_handle.
12402 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12403 struct mlx5_flow_handle *handle)
12405 if (!handle->rix_fate)
12407 switch (handle->fate_action) {
12408 case MLX5_FLOW_FATE_QUEUE:
12409 mlx5_hrxq_release(dev, handle->rix_hrxq);
12411 case MLX5_FLOW_FATE_JUMP:
12412 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12414 case MLX5_FLOW_FATE_PORT_ID:
12415 flow_dv_port_id_action_resource_release(dev,
12416 handle->rix_port_id_action);
12419 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12422 handle->rix_fate = 0;
12426 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12427 struct mlx5_cache_entry *entry)
12429 struct mlx5_flow_dv_sample_resource *cache_resource =
12430 container_of(entry, typeof(*cache_resource), entry);
12431 struct rte_eth_dev *dev = cache_resource->dev;
12432 struct mlx5_priv *priv = dev->data->dev_private;
12434 if (cache_resource->verbs_action)
12435 claim_zero(mlx5_flow_os_destroy_flow_action
12436 (cache_resource->verbs_action));
12437 if (cache_resource->normal_path_tbl)
12438 flow_dv_tbl_resource_release(MLX5_SH(dev),
12439 cache_resource->normal_path_tbl);
12440 flow_dv_sample_sub_actions_release(dev,
12441 &cache_resource->sample_idx);
12442 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12443 cache_resource->idx);
12444 DRV_LOG(DEBUG, "sample resource %p: removed",
12445 (void *)cache_resource);
12449 * Release an sample resource.
12452 * Pointer to Ethernet device.
12454 * Pointer to mlx5_flow_handle.
12457 * 1 while a reference on it exists, 0 when freed.
12460 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12461 struct mlx5_flow_handle *handle)
12463 struct mlx5_priv *priv = dev->data->dev_private;
12464 struct mlx5_flow_dv_sample_resource *cache_resource;
12466 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12467 handle->dvh.rix_sample);
12468 if (!cache_resource)
12470 MLX5_ASSERT(cache_resource->verbs_action);
12471 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12472 &cache_resource->entry);
12476 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12477 struct mlx5_cache_entry *entry)
12479 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12480 container_of(entry, typeof(*cache_resource), entry);
12481 struct rte_eth_dev *dev = cache_resource->dev;
12482 struct mlx5_priv *priv = dev->data->dev_private;
12485 MLX5_ASSERT(cache_resource->action);
12486 if (cache_resource->action)
12487 claim_zero(mlx5_flow_os_destroy_flow_action
12488 (cache_resource->action));
12489 for (; i < cache_resource->num_of_dest; i++)
12490 flow_dv_sample_sub_actions_release(dev,
12491 &cache_resource->sample_idx[i]);
12492 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12493 cache_resource->idx);
12494 DRV_LOG(DEBUG, "destination array resource %p: removed",
12495 (void *)cache_resource);
12499 * Release an destination array resource.
12502 * Pointer to Ethernet device.
12504 * Pointer to mlx5_flow_handle.
12507 * 1 while a reference on it exists, 0 when freed.
12510 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12511 struct mlx5_flow_handle *handle)
12513 struct mlx5_priv *priv = dev->data->dev_private;
12514 struct mlx5_flow_dv_dest_array_resource *cache;
12516 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12517 handle->dvh.rix_dest_array);
12520 MLX5_ASSERT(cache->action);
12521 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12526 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12528 struct mlx5_priv *priv = dev->data->dev_private;
12529 struct mlx5_dev_ctx_shared *sh = priv->sh;
12530 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12531 sh->geneve_tlv_option_resource;
12532 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12533 if (geneve_opt_resource) {
12534 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12535 __ATOMIC_RELAXED))) {
12536 claim_zero(mlx5_devx_cmd_destroy
12537 (geneve_opt_resource->obj));
12538 mlx5_free(sh->geneve_tlv_option_resource);
12539 sh->geneve_tlv_option_resource = NULL;
12542 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12546 * Remove the flow from the NIC but keeps it in memory.
12547 * Lock free, (mutex should be acquired by caller).
12550 * Pointer to Ethernet device.
12551 * @param[in, out] flow
12552 * Pointer to flow structure.
12555 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12557 struct mlx5_flow_handle *dh;
12558 uint32_t handle_idx;
12559 struct mlx5_priv *priv = dev->data->dev_private;
12563 handle_idx = flow->dev_handles;
12564 while (handle_idx) {
12565 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12569 if (dh->drv_flow) {
12570 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12571 dh->drv_flow = NULL;
12573 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12574 flow_dv_fate_resource_release(dev, dh);
12575 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12576 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12577 handle_idx = dh->next.next;
12582 * Remove the flow from the NIC and the memory.
12583 * Lock free, (mutex should be acquired by caller).
12586 * Pointer to the Ethernet device structure.
12587 * @param[in, out] flow
12588 * Pointer to flow structure.
12591 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12593 struct mlx5_flow_handle *dev_handle;
12594 struct mlx5_priv *priv = dev->data->dev_private;
12599 flow_dv_remove(dev, flow);
12600 if (flow->counter) {
12601 flow_dv_counter_free(dev, flow->counter);
12605 struct mlx5_flow_meter *fm;
12607 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12610 mlx5_flow_meter_detach(fm);
12614 flow_dv_aso_age_release(dev, flow->age);
12615 if (flow->geneve_tlv_option) {
12616 flow_dv_geneve_tlv_option_resource_release(dev);
12617 flow->geneve_tlv_option = 0;
12619 while (flow->dev_handles) {
12620 uint32_t tmp_idx = flow->dev_handles;
12622 dev_handle = mlx5_ipool_get(priv->sh->ipool
12623 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12626 flow->dev_handles = dev_handle->next.next;
12627 if (dev_handle->dvh.matcher)
12628 flow_dv_matcher_release(dev, dev_handle);
12629 if (dev_handle->dvh.rix_sample)
12630 flow_dv_sample_resource_release(dev, dev_handle);
12631 if (dev_handle->dvh.rix_dest_array)
12632 flow_dv_dest_array_resource_release(dev, dev_handle);
12633 if (dev_handle->dvh.rix_encap_decap)
12634 flow_dv_encap_decap_resource_release(dev,
12635 dev_handle->dvh.rix_encap_decap);
12636 if (dev_handle->dvh.modify_hdr)
12637 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12638 if (dev_handle->dvh.rix_push_vlan)
12639 flow_dv_push_vlan_action_resource_release(dev,
12641 if (dev_handle->dvh.rix_tag)
12642 flow_dv_tag_release(dev,
12643 dev_handle->dvh.rix_tag);
12644 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12645 flow_dv_fate_resource_release(dev, dev_handle);
12647 srss = dev_handle->rix_srss;
12648 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12652 flow_dv_shared_rss_action_release(dev, srss);
12656 * Release array of hash RX queue objects.
12660 * Pointer to the Ethernet device structure.
12661 * @param[in, out] hrxqs
12662 * Array of hash RX queue objects.
12665 * Total number of references to hash RX queue objects in *hrxqs* array
12666 * after this operation.
12669 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12670 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12675 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12676 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12686 * Release all hash RX queue objects representing shared RSS action.
12689 * Pointer to the Ethernet device structure.
12690 * @param[in, out] action
12691 * Shared RSS action to remove hash RX queue objects from.
12694 * Total number of references to hash RX queue objects stored in *action*
12695 * after this operation.
12696 * Expected to be 0 if no external references held.
12699 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12700 struct mlx5_shared_action_rss *shared_rss)
12702 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12706 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12709 * Only one hash value is available for one L3+L4 combination:
12711 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12712 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12713 * same slot in mlx5_rss_hash_fields.
12716 * Pointer to the shared action RSS conf.
12717 * @param[in, out] hash_field
12718 * hash_field variable needed to be adjusted.
12724 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12725 uint64_t *hash_field)
12727 uint64_t rss_types = rss->origin.types;
12729 switch (*hash_field & ~IBV_RX_HASH_INNER) {
12730 case MLX5_RSS_HASH_IPV4:
12731 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12732 *hash_field &= ~MLX5_RSS_HASH_IPV4;
12733 if (rss_types & ETH_RSS_L3_DST_ONLY)
12734 *hash_field |= IBV_RX_HASH_DST_IPV4;
12735 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12736 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12738 *hash_field |= MLX5_RSS_HASH_IPV4;
12741 case MLX5_RSS_HASH_IPV6:
12742 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12743 *hash_field &= ~MLX5_RSS_HASH_IPV6;
12744 if (rss_types & ETH_RSS_L3_DST_ONLY)
12745 *hash_field |= IBV_RX_HASH_DST_IPV6;
12746 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12747 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12749 *hash_field |= MLX5_RSS_HASH_IPV6;
12752 case MLX5_RSS_HASH_IPV4_UDP:
12753 /* fall-through. */
12754 case MLX5_RSS_HASH_IPV6_UDP:
12755 if (rss_types & ETH_RSS_UDP) {
12756 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12757 if (rss_types & ETH_RSS_L4_DST_ONLY)
12758 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12759 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12760 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12762 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12765 case MLX5_RSS_HASH_IPV4_TCP:
12766 /* fall-through. */
12767 case MLX5_RSS_HASH_IPV6_TCP:
12768 if (rss_types & ETH_RSS_TCP) {
12769 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12770 if (rss_types & ETH_RSS_L4_DST_ONLY)
12771 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12772 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12773 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12775 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12784 * Setup shared RSS action.
12785 * Prepare set of hash RX queue objects sufficient to handle all valid
12786 * hash_fields combinations (see enum ibv_rx_hash_fields).
12789 * Pointer to the Ethernet device structure.
12790 * @param[in] action_idx
12791 * Shared RSS action ipool index.
12792 * @param[in, out] action
12793 * Partially initialized shared RSS action.
12794 * @param[out] error
12795 * Perform verbose error reporting if not NULL. Initialized in case of
12799 * 0 on success, otherwise negative errno value.
12802 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12803 uint32_t action_idx,
12804 struct mlx5_shared_action_rss *shared_rss,
12805 struct rte_flow_error *error)
12807 struct mlx5_flow_rss_desc rss_desc = { 0 };
12811 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12812 return rte_flow_error_set(error, rte_errno,
12813 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12814 "cannot setup indirection table");
12816 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12817 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12818 rss_desc.const_q = shared_rss->origin.queue;
12819 rss_desc.queue_num = shared_rss->origin.queue_num;
12820 /* Set non-zero value to indicate a shared RSS. */
12821 rss_desc.shared_rss = action_idx;
12822 rss_desc.ind_tbl = shared_rss->ind_tbl;
12823 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12825 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12828 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12829 if (shared_rss->origin.level > 1) {
12830 hash_fields |= IBV_RX_HASH_INNER;
12833 rss_desc.tunnel = tunnel;
12834 rss_desc.hash_fields = hash_fields;
12835 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12840 "cannot get hash queue");
12841 goto error_hrxq_new;
12843 err = __flow_dv_action_rss_hrxq_set
12844 (shared_rss, hash_fields, hrxq_idx);
12850 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12851 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12852 shared_rss->ind_tbl = NULL;
12858 * Create shared RSS action.
12861 * Pointer to the Ethernet device structure.
12863 * Shared action configuration.
12865 * RSS action specification used to create shared action.
12866 * @param[out] error
12867 * Perform verbose error reporting if not NULL. Initialized in case of
12871 * A valid shared action ID in case of success, 0 otherwise and
12872 * rte_errno is set.
12875 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12876 const struct rte_flow_shared_action_conf *conf,
12877 const struct rte_flow_action_rss *rss,
12878 struct rte_flow_error *error)
12880 struct mlx5_priv *priv = dev->data->dev_private;
12881 struct mlx5_shared_action_rss *shared_rss = NULL;
12882 void *queue = NULL;
12883 struct rte_flow_action_rss *origin;
12884 const uint8_t *rss_key;
12885 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12888 RTE_SET_USED(conf);
12889 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12891 shared_rss = mlx5_ipool_zmalloc
12892 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12893 if (!shared_rss || !queue) {
12894 rte_flow_error_set(error, ENOMEM,
12895 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12896 "cannot allocate resource memory");
12897 goto error_rss_init;
12899 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12900 rte_flow_error_set(error, E2BIG,
12901 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12902 "rss action number out of range");
12903 goto error_rss_init;
12905 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12906 sizeof(*shared_rss->ind_tbl),
12908 if (!shared_rss->ind_tbl) {
12909 rte_flow_error_set(error, ENOMEM,
12910 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12911 "cannot allocate resource memory");
12912 goto error_rss_init;
12914 memcpy(queue, rss->queue, queue_size);
12915 shared_rss->ind_tbl->queues = queue;
12916 shared_rss->ind_tbl->queues_n = rss->queue_num;
12917 origin = &shared_rss->origin;
12918 origin->func = rss->func;
12919 origin->level = rss->level;
12920 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12921 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12922 /* NULL RSS key indicates default RSS key. */
12923 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12924 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12925 origin->key = &shared_rss->key[0];
12926 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12927 origin->queue = queue;
12928 origin->queue_num = rss->queue_num;
12929 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12930 goto error_rss_init;
12931 rte_spinlock_init(&shared_rss->action_rss_sl);
12932 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12933 rte_spinlock_lock(&priv->shared_act_sl);
12934 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12935 &priv->rss_shared_actions, idx, shared_rss, next);
12936 rte_spinlock_unlock(&priv->shared_act_sl);
12940 if (shared_rss->ind_tbl)
12941 mlx5_free(shared_rss->ind_tbl);
12942 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12951 * Destroy the shared RSS action.
12952 * Release related hash RX queue objects.
12955 * Pointer to the Ethernet device structure.
12957 * The shared RSS action object ID to be removed.
12958 * @param[out] error
12959 * Perform verbose error reporting if not NULL. Initialized in case of
12963 * 0 on success, otherwise negative errno value.
12966 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12967 struct rte_flow_error *error)
12969 struct mlx5_priv *priv = dev->data->dev_private;
12970 struct mlx5_shared_action_rss *shared_rss =
12971 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12972 uint32_t old_refcnt = 1;
12974 uint16_t *queue = NULL;
12977 return rte_flow_error_set(error, EINVAL,
12978 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12979 "invalid shared action");
12980 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12982 return rte_flow_error_set(error, EBUSY,
12983 RTE_FLOW_ERROR_TYPE_ACTION,
12985 "shared rss hrxq has references");
12986 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12987 0, 0, __ATOMIC_ACQUIRE,
12989 return rte_flow_error_set(error, EBUSY,
12990 RTE_FLOW_ERROR_TYPE_ACTION,
12992 "shared rss has references");
12993 queue = shared_rss->ind_tbl->queues;
12994 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12996 return rte_flow_error_set(error, EBUSY,
12997 RTE_FLOW_ERROR_TYPE_ACTION,
12999 "shared rss indirection table has"
13002 rte_spinlock_lock(&priv->shared_act_sl);
13003 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13004 &priv->rss_shared_actions, idx, shared_rss, next);
13005 rte_spinlock_unlock(&priv->shared_act_sl);
13006 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13012 * Create shared action, lock free,
13013 * (mutex should be acquired by caller).
13014 * Dispatcher for action type specific call.
13017 * Pointer to the Ethernet device structure.
13019 * Shared action configuration.
13020 * @param[in] action
13021 * Action specification used to create shared action.
13022 * @param[out] error
13023 * Perform verbose error reporting if not NULL. Initialized in case of
13027 * A valid shared action handle in case of success, NULL otherwise and
13028 * rte_errno is set.
13030 static struct rte_flow_shared_action *
13031 flow_dv_action_create(struct rte_eth_dev *dev,
13032 const struct rte_flow_shared_action_conf *conf,
13033 const struct rte_flow_action *action,
13034 struct rte_flow_error *err)
13039 switch (action->type) {
13040 case RTE_FLOW_ACTION_TYPE_RSS:
13041 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13042 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
13043 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13045 case RTE_FLOW_ACTION_TYPE_AGE:
13046 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13047 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
13048 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13050 struct mlx5_aso_age_action *aso_age =
13051 flow_aso_age_get_by_idx(dev, ret);
13053 if (!aso_age->age_params.context)
13054 aso_age->age_params.context =
13055 (void *)(uintptr_t)idx;
13059 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13060 NULL, "action type not supported");
13063 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
13067 * Destroy the shared action.
13068 * Release action related resources on the NIC and the memory.
13069 * Lock free, (mutex should be acquired by caller).
13070 * Dispatcher for action type specific call.
13073 * Pointer to the Ethernet device structure.
13074 * @param[in] action
13075 * The shared action object to be removed.
13076 * @param[out] error
13077 * Perform verbose error reporting if not NULL. Initialized in case of
13081 * 0 on success, otherwise negative errno value.
13084 flow_dv_action_destroy(struct rte_eth_dev *dev,
13085 struct rte_flow_shared_action *action,
13086 struct rte_flow_error *error)
13088 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13089 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13090 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13094 case MLX5_SHARED_ACTION_TYPE_RSS:
13095 return __flow_dv_action_rss_release(dev, idx, error);
13096 case MLX5_SHARED_ACTION_TYPE_AGE:
13097 ret = flow_dv_aso_age_release(dev, idx);
13100 * In this case, the last flow has a reference will
13101 * actually release the age action.
13103 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
13104 " released with references %d.", idx, ret);
13107 return rte_flow_error_set(error, ENOTSUP,
13108 RTE_FLOW_ERROR_TYPE_ACTION,
13110 "action type not supported");
13115 * Updates in place shared RSS action configuration.
13118 * Pointer to the Ethernet device structure.
13120 * The shared RSS action object ID to be updated.
13121 * @param[in] action_conf
13122 * RSS action specification used to modify *shared_rss*.
13123 * @param[out] error
13124 * Perform verbose error reporting if not NULL. Initialized in case of
13128 * 0 on success, otherwise negative errno value.
13129 * @note: currently only support update of RSS queues.
13132 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13133 const struct rte_flow_action_rss *action_conf,
13134 struct rte_flow_error *error)
13136 struct mlx5_priv *priv = dev->data->dev_private;
13137 struct mlx5_shared_action_rss *shared_rss =
13138 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13140 void *queue = NULL;
13141 uint16_t *queue_old = NULL;
13142 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13145 return rte_flow_error_set(error, EINVAL,
13146 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13147 "invalid shared action to update");
13148 if (priv->obj_ops.ind_table_modify == NULL)
13149 return rte_flow_error_set(error, ENOTSUP,
13150 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13151 "cannot modify indirection table");
13152 queue = mlx5_malloc(MLX5_MEM_ZERO,
13153 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13156 return rte_flow_error_set(error, ENOMEM,
13157 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13159 "cannot allocate resource memory");
13160 memcpy(queue, action_conf->queue, queue_size);
13161 MLX5_ASSERT(shared_rss->ind_tbl);
13162 rte_spinlock_lock(&shared_rss->action_rss_sl);
13163 queue_old = shared_rss->ind_tbl->queues;
13164 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13165 queue, action_conf->queue_num, true);
13168 ret = rte_flow_error_set(error, rte_errno,
13169 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13170 "cannot update indirection table");
13172 mlx5_free(queue_old);
13173 shared_rss->origin.queue = queue;
13174 shared_rss->origin.queue_num = action_conf->queue_num;
13176 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13181 * Updates in place shared action configuration, lock free,
13182 * (mutex should be acquired by caller).
13185 * Pointer to the Ethernet device structure.
13186 * @param[in] action
13187 * The shared action object to be updated.
13188 * @param[in] action_conf
13189 * Action specification used to modify *action*.
13190 * *action_conf* should be of type correlating with type of the *action*,
13191 * otherwise considered as invalid.
13192 * @param[out] error
13193 * Perform verbose error reporting if not NULL. Initialized in case of
13197 * 0 on success, otherwise negative errno value.
13200 flow_dv_action_update(struct rte_eth_dev *dev,
13201 struct rte_flow_shared_action *action,
13202 const void *action_conf,
13203 struct rte_flow_error *err)
13205 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13206 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13207 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13210 case MLX5_SHARED_ACTION_TYPE_RSS:
13211 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13213 return rte_flow_error_set(err, ENOTSUP,
13214 RTE_FLOW_ERROR_TYPE_ACTION,
13216 "action type update not supported");
13221 flow_dv_action_query(struct rte_eth_dev *dev,
13222 const struct rte_flow_shared_action *action, void *data,
13223 struct rte_flow_error *error)
13225 struct mlx5_age_param *age_param;
13226 struct rte_flow_query_age *resp;
13227 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13228 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13229 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13232 case MLX5_SHARED_ACTION_TYPE_AGE:
13233 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13235 resp->aged = __atomic_load_n(&age_param->state,
13236 __ATOMIC_RELAXED) == AGE_TMOUT ?
13238 resp->sec_since_last_hit_valid = !resp->aged;
13239 if (resp->sec_since_last_hit_valid)
13240 resp->sec_since_last_hit = __atomic_load_n
13241 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13244 return rte_flow_error_set(error, ENOTSUP,
13245 RTE_FLOW_ERROR_TYPE_ACTION,
13247 "action type query not supported");
13252 * Query a dv flow rule for its statistics via devx.
13255 * Pointer to Ethernet device.
13257 * Pointer to the sub flow.
13259 * data retrieved by the query.
13260 * @param[out] error
13261 * Perform verbose error reporting if not NULL.
13264 * 0 on success, a negative errno value otherwise and rte_errno is set.
13267 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13268 void *data, struct rte_flow_error *error)
13270 struct mlx5_priv *priv = dev->data->dev_private;
13271 struct rte_flow_query_count *qc = data;
13273 if (!priv->config.devx)
13274 return rte_flow_error_set(error, ENOTSUP,
13275 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13277 "counters are not supported");
13278 if (flow->counter) {
13279 uint64_t pkts, bytes;
13280 struct mlx5_flow_counter *cnt;
13282 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13284 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13288 return rte_flow_error_set(error, -err,
13289 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13290 NULL, "cannot read counters");
13293 qc->hits = pkts - cnt->hits;
13294 qc->bytes = bytes - cnt->bytes;
13297 cnt->bytes = bytes;
13301 return rte_flow_error_set(error, EINVAL,
13302 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13304 "counters are not available");
13308 * Query a flow rule AGE action for aging information.
13311 * Pointer to Ethernet device.
13313 * Pointer to the sub flow.
13315 * data retrieved by the query.
13316 * @param[out] error
13317 * Perform verbose error reporting if not NULL.
13320 * 0 on success, a negative errno value otherwise and rte_errno is set.
13323 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13324 void *data, struct rte_flow_error *error)
13326 struct rte_flow_query_age *resp = data;
13327 struct mlx5_age_param *age_param;
13330 struct mlx5_aso_age_action *act =
13331 flow_aso_age_get_by_idx(dev, flow->age);
13333 age_param = &act->age_params;
13334 } else if (flow->counter) {
13335 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13337 if (!age_param || !age_param->timeout)
13338 return rte_flow_error_set
13340 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13341 NULL, "cannot read age data");
13343 return rte_flow_error_set(error, EINVAL,
13344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13345 NULL, "age data not available");
13347 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13349 resp->sec_since_last_hit_valid = !resp->aged;
13350 if (resp->sec_since_last_hit_valid)
13351 resp->sec_since_last_hit = __atomic_load_n
13352 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13359 * @see rte_flow_query()
13360 * @see rte_flow_ops
13363 flow_dv_query(struct rte_eth_dev *dev,
13364 struct rte_flow *flow __rte_unused,
13365 const struct rte_flow_action *actions __rte_unused,
13366 void *data __rte_unused,
13367 struct rte_flow_error *error __rte_unused)
13371 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13372 switch (actions->type) {
13373 case RTE_FLOW_ACTION_TYPE_VOID:
13375 case RTE_FLOW_ACTION_TYPE_COUNT:
13376 ret = flow_dv_query_count(dev, flow, data, error);
13378 case RTE_FLOW_ACTION_TYPE_AGE:
13379 ret = flow_dv_query_age(dev, flow, data, error);
13382 return rte_flow_error_set(error, ENOTSUP,
13383 RTE_FLOW_ERROR_TYPE_ACTION,
13385 "action not supported");
13392 * Destroy the meter table set.
13393 * Lock free, (mutex should be acquired by caller).
13396 * Pointer to Ethernet device.
13398 * Pointer to the meter table set.
13404 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13405 struct mlx5_meter_domains_infos *tbl)
13407 struct mlx5_priv *priv = dev->data->dev_private;
13408 struct mlx5_meter_domains_infos *mtd =
13409 (struct mlx5_meter_domains_infos *)tbl;
13411 if (!mtd || !priv->config.dv_flow_en)
13413 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13414 claim_zero(mlx5_flow_os_destroy_flow
13415 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13416 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13417 claim_zero(mlx5_flow_os_destroy_flow
13418 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13419 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13420 claim_zero(mlx5_flow_os_destroy_flow
13421 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13422 if (mtd->egress.color_matcher)
13423 claim_zero(mlx5_flow_os_destroy_flow_matcher
13424 (mtd->egress.color_matcher));
13425 if (mtd->egress.any_matcher)
13426 claim_zero(mlx5_flow_os_destroy_flow_matcher
13427 (mtd->egress.any_matcher));
13428 if (mtd->egress.tbl)
13429 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13430 if (mtd->egress.sfx_tbl)
13431 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13432 if (mtd->ingress.color_matcher)
13433 claim_zero(mlx5_flow_os_destroy_flow_matcher
13434 (mtd->ingress.color_matcher));
13435 if (mtd->ingress.any_matcher)
13436 claim_zero(mlx5_flow_os_destroy_flow_matcher
13437 (mtd->ingress.any_matcher));
13438 if (mtd->ingress.tbl)
13439 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13440 if (mtd->ingress.sfx_tbl)
13441 flow_dv_tbl_resource_release(MLX5_SH(dev),
13442 mtd->ingress.sfx_tbl);
13443 if (mtd->transfer.color_matcher)
13444 claim_zero(mlx5_flow_os_destroy_flow_matcher
13445 (mtd->transfer.color_matcher));
13446 if (mtd->transfer.any_matcher)
13447 claim_zero(mlx5_flow_os_destroy_flow_matcher
13448 (mtd->transfer.any_matcher));
13449 if (mtd->transfer.tbl)
13450 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13451 if (mtd->transfer.sfx_tbl)
13452 flow_dv_tbl_resource_release(MLX5_SH(dev),
13453 mtd->transfer.sfx_tbl);
13454 if (mtd->drop_actn)
13455 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13460 /* Number of meter flow actions, count and jump or count and drop. */
13461 #define METER_ACTIONS 2
13464 * Create specify domain meter table and suffix table.
13467 * Pointer to Ethernet device.
13468 * @param[in,out] mtb
13469 * Pointer to DV meter table set.
13470 * @param[in] egress
13472 * @param[in] transfer
13474 * @param[in] color_reg_c_idx
13475 * Reg C index for color match.
13478 * 0 on success, -1 otherwise and rte_errno is set.
13481 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13482 struct mlx5_meter_domains_infos *mtb,
13483 uint8_t egress, uint8_t transfer,
13484 uint32_t color_reg_c_idx)
13486 struct mlx5_priv *priv = dev->data->dev_private;
13487 struct mlx5_dev_ctx_shared *sh = priv->sh;
13488 struct mlx5_flow_dv_match_params mask = {
13489 .size = sizeof(mask.buf),
13491 struct mlx5_flow_dv_match_params value = {
13492 .size = sizeof(value.buf),
13494 struct mlx5dv_flow_matcher_attr dv_attr = {
13495 .type = IBV_FLOW_ATTR_NORMAL,
13497 .match_criteria_enable = 0,
13498 .match_mask = (void *)&mask,
13500 void *actions[METER_ACTIONS];
13501 struct mlx5_meter_domain_info *dtb;
13502 struct rte_flow_error error;
13507 dtb = &mtb->transfer;
13509 dtb = &mtb->egress;
13511 dtb = &mtb->ingress;
13512 /* Create the meter table with METER level. */
13513 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13514 egress, transfer, false, NULL, 0,
13517 DRV_LOG(ERR, "Failed to create meter policer table.");
13520 /* Create the meter suffix table with SUFFIX level. */
13521 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13522 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13523 egress, transfer, false, NULL, 0,
13525 if (!dtb->sfx_tbl) {
13526 DRV_LOG(ERR, "Failed to create meter suffix table.");
13529 /* Create matchers, Any and Color. */
13530 dv_attr.priority = 3;
13531 dv_attr.match_criteria_enable = 0;
13532 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13533 &dtb->any_matcher);
13535 DRV_LOG(ERR, "Failed to create meter"
13536 " policer default matcher.");
13539 dv_attr.priority = 0;
13540 dv_attr.match_criteria_enable =
13541 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13542 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13543 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13544 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13545 &dtb->color_matcher);
13547 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13550 if (mtb->count_actns[RTE_MTR_DROPPED])
13551 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13552 actions[i++] = mtb->drop_actn;
13553 /* Default rule: lowest priority, match any, actions: drop. */
13554 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13556 &dtb->policer_rules[RTE_MTR_DROPPED]);
13558 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13567 * Create the needed meter and suffix tables.
13568 * Lock free, (mutex should be acquired by caller).
13571 * Pointer to Ethernet device.
13573 * Pointer to the flow meter.
13576 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13578 static struct mlx5_meter_domains_infos *
13579 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13580 const struct mlx5_flow_meter *fm)
13582 struct mlx5_priv *priv = dev->data->dev_private;
13583 struct mlx5_meter_domains_infos *mtb;
13587 if (!priv->mtr_en) {
13588 rte_errno = ENOTSUP;
13591 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13593 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13596 /* Create meter count actions */
13597 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13598 struct mlx5_flow_counter *cnt;
13599 if (!fm->policer_stats.cnt[i])
13601 cnt = flow_dv_counter_get_by_idx(dev,
13602 fm->policer_stats.cnt[i], NULL);
13603 mtb->count_actns[i] = cnt->action;
13605 /* Create drop action. */
13606 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13608 DRV_LOG(ERR, "Failed to create drop action.");
13611 /* Egress meter table. */
13612 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13614 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13617 /* Ingress meter table. */
13618 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13620 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13623 /* FDB meter table. */
13624 if (priv->config.dv_esw_en) {
13625 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13626 priv->mtr_color_reg);
13628 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13634 flow_dv_destroy_mtr_tbl(dev, mtb);
13639 * Destroy domain policer rule.
13642 * Pointer to domain table.
13645 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13649 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13650 if (dt->policer_rules[i]) {
13651 claim_zero(mlx5_flow_os_destroy_flow
13652 (dt->policer_rules[i]));
13653 dt->policer_rules[i] = NULL;
13656 if (dt->jump_actn) {
13657 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13658 dt->jump_actn = NULL;
13663 * Destroy policer rules.
13666 * Pointer to Ethernet device.
13668 * Pointer to flow meter structure.
13670 * Pointer to flow attributes.
13676 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13677 const struct mlx5_flow_meter *fm,
13678 const struct rte_flow_attr *attr)
13680 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13685 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13687 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13688 if (attr->transfer)
13689 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13694 * Create specify domain meter policer rule.
13697 * Pointer to flow meter structure.
13699 * Pointer to DV meter table set.
13700 * @param[in] mtr_reg_c
13701 * Color match REG_C.
13704 * 0 on success, -1 otherwise.
13707 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13708 struct mlx5_meter_domain_info *dtb,
13711 struct mlx5_flow_dv_match_params matcher = {
13712 .size = sizeof(matcher.buf),
13714 struct mlx5_flow_dv_match_params value = {
13715 .size = sizeof(value.buf),
13717 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13718 void *actions[METER_ACTIONS];
13722 /* Create jump action. */
13723 if (!dtb->jump_actn)
13724 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13725 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13727 DRV_LOG(ERR, "Failed to create policer jump action.");
13730 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13733 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13734 rte_col_2_mlx5_col(i), UINT8_MAX);
13735 if (mtb->count_actns[i])
13736 actions[j++] = mtb->count_actns[i];
13737 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13738 actions[j++] = mtb->drop_actn;
13740 actions[j++] = dtb->jump_actn;
13741 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13742 (void *)&value, j, actions,
13743 &dtb->policer_rules[i]);
13745 DRV_LOG(ERR, "Failed to create policer rule.");
13756 * Create policer rules.
13759 * Pointer to Ethernet device.
13761 * Pointer to flow meter structure.
13763 * Pointer to flow attributes.
13766 * 0 on success, -1 otherwise.
13769 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13770 struct mlx5_flow_meter *fm,
13771 const struct rte_flow_attr *attr)
13773 struct mlx5_priv *priv = dev->data->dev_private;
13774 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13777 if (attr->egress) {
13778 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13779 priv->mtr_color_reg);
13781 DRV_LOG(ERR, "Failed to create egress policer.");
13785 if (attr->ingress) {
13786 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13787 priv->mtr_color_reg);
13789 DRV_LOG(ERR, "Failed to create ingress policer.");
13793 if (attr->transfer) {
13794 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13795 priv->mtr_color_reg);
13797 DRV_LOG(ERR, "Failed to create transfer policer.");
13803 flow_dv_destroy_policer_rules(dev, fm, attr);
13808 * Validate the batch counter support in root table.
13810 * Create a simple flow with invalid counter and drop action on root table to
13811 * validate if batch counter with offset on root table is supported or not.
13814 * Pointer to rte_eth_dev structure.
13817 * 0 on success, a negative errno value otherwise and rte_errno is set.
13820 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13822 struct mlx5_priv *priv = dev->data->dev_private;
13823 struct mlx5_dev_ctx_shared *sh = priv->sh;
13824 struct mlx5_flow_dv_match_params mask = {
13825 .size = sizeof(mask.buf),
13827 struct mlx5_flow_dv_match_params value = {
13828 .size = sizeof(value.buf),
13830 struct mlx5dv_flow_matcher_attr dv_attr = {
13831 .type = IBV_FLOW_ATTR_NORMAL,
13833 .match_criteria_enable = 0,
13834 .match_mask = (void *)&mask,
13836 void *actions[2] = { 0 };
13837 struct mlx5_flow_tbl_resource *tbl = NULL;
13838 struct mlx5_devx_obj *dcs = NULL;
13839 void *matcher = NULL;
13843 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13846 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13849 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13853 actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13854 priv->drop_queue.hrxq->action;
13855 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13856 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13860 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13864 * If batch counter with offset is not supported, the driver will not
13865 * validate the invalid offset value, flow create should success.
13866 * In this case, it means batch counter is not supported in root table.
13868 * Otherwise, if flow create is failed, counter offset is supported.
13871 DRV_LOG(INFO, "Batch counter is not supported in root "
13872 "table. Switch to fallback mode.");
13873 rte_errno = ENOTSUP;
13875 claim_zero(mlx5_flow_os_destroy_flow(flow));
13877 /* Check matcher to make sure validate fail at flow create. */
13878 if (!matcher || (matcher && errno != EINVAL))
13879 DRV_LOG(ERR, "Unexpected error in counter offset "
13880 "support detection");
13884 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13886 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13888 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13890 claim_zero(mlx5_devx_cmd_destroy(dcs));
13895 * Query a devx counter.
13898 * Pointer to the Ethernet device structure.
13900 * Index to the flow counter.
13902 * Set to clear the counter statistics.
13904 * The statistics value of packets.
13905 * @param[out] bytes
13906 * The statistics value of bytes.
13909 * 0 on success, otherwise return -1.
13912 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13913 uint64_t *pkts, uint64_t *bytes)
13915 struct mlx5_priv *priv = dev->data->dev_private;
13916 struct mlx5_flow_counter *cnt;
13917 uint64_t inn_pkts, inn_bytes;
13920 if (!priv->config.devx)
13923 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13926 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13927 *pkts = inn_pkts - cnt->hits;
13928 *bytes = inn_bytes - cnt->bytes;
13930 cnt->hits = inn_pkts;
13931 cnt->bytes = inn_bytes;
13937 * Get aged-out flows.
13940 * Pointer to the Ethernet device structure.
13941 * @param[in] context
13942 * The address of an array of pointers to the aged-out flows contexts.
13943 * @param[in] nb_contexts
13944 * The length of context array pointers.
13945 * @param[out] error
13946 * Perform verbose error reporting if not NULL. Initialized in case of
13950 * how many contexts get in success, otherwise negative errno value.
13951 * if nb_contexts is 0, return the amount of all aged contexts.
13952 * if nb_contexts is not 0 , return the amount of aged flows reported
13953 * in the context array.
13954 * @note: only stub for now
13957 flow_get_aged_flows(struct rte_eth_dev *dev,
13959 uint32_t nb_contexts,
13960 struct rte_flow_error *error)
13962 struct mlx5_priv *priv = dev->data->dev_private;
13963 struct mlx5_age_info *age_info;
13964 struct mlx5_age_param *age_param;
13965 struct mlx5_flow_counter *counter;
13966 struct mlx5_aso_age_action *act;
13969 if (nb_contexts && !context)
13970 return rte_flow_error_set(error, EINVAL,
13971 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13972 NULL, "empty context");
13973 age_info = GET_PORT_AGE_INFO(priv);
13974 rte_spinlock_lock(&age_info->aged_sl);
13975 LIST_FOREACH(act, &age_info->aged_aso, next) {
13978 context[nb_flows - 1] =
13979 act->age_params.context;
13980 if (!(--nb_contexts))
13984 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13987 age_param = MLX5_CNT_TO_AGE(counter);
13988 context[nb_flows - 1] = age_param->context;
13989 if (!(--nb_contexts))
13993 rte_spinlock_unlock(&age_info->aged_sl);
13994 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13999 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14002 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14004 return flow_dv_counter_alloc(dev, 0);
14008 * Validate shared action.
14009 * Dispatcher for action type specific validation.
14012 * Pointer to the Ethernet device structure.
14014 * Shared action configuration.
14015 * @param[in] action
14016 * The shared action object to validate.
14017 * @param[out] error
14018 * Perform verbose error reporting if not NULL. Initialized in case of
14022 * 0 on success, otherwise negative errno value.
14025 flow_dv_action_validate(struct rte_eth_dev *dev,
14026 const struct rte_flow_shared_action_conf *conf,
14027 const struct rte_flow_action *action,
14028 struct rte_flow_error *err)
14030 struct mlx5_priv *priv = dev->data->dev_private;
14032 RTE_SET_USED(conf);
14033 switch (action->type) {
14034 case RTE_FLOW_ACTION_TYPE_RSS:
14036 * priv->obj_ops is set according to driver capabilities.
14037 * When DevX capabilities are
14038 * sufficient, it is set to devx_obj_ops.
14039 * Otherwise, it is set to ibv_obj_ops.
14040 * ibv_obj_ops doesn't support ind_table_modify operation.
14041 * In this case the shared RSS action can't be used.
14043 if (priv->obj_ops.ind_table_modify == NULL)
14044 return rte_flow_error_set
14046 RTE_FLOW_ERROR_TYPE_ACTION,
14048 "shared RSS action not supported");
14049 return mlx5_validate_action_rss(dev, action, err);
14050 case RTE_FLOW_ACTION_TYPE_AGE:
14051 if (!priv->sh->aso_age_mng)
14052 return rte_flow_error_set(err, ENOTSUP,
14053 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14055 "shared age action not supported");
14056 return flow_dv_validate_action_age(0, action, dev, err);
14058 return rte_flow_error_set(err, ENOTSUP,
14059 RTE_FLOW_ERROR_TYPE_ACTION,
14061 "action type not supported");
14066 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14068 struct mlx5_priv *priv = dev->data->dev_private;
14071 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14072 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14077 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14078 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14082 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14083 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14090 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14091 .validate = flow_dv_validate,
14092 .prepare = flow_dv_prepare,
14093 .translate = flow_dv_translate,
14094 .apply = flow_dv_apply,
14095 .remove = flow_dv_remove,
14096 .destroy = flow_dv_destroy,
14097 .query = flow_dv_query,
14098 .create_mtr_tbls = flow_dv_create_mtr_tbl,
14099 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14100 .create_policer_rules = flow_dv_create_policer_rules,
14101 .destroy_policer_rules = flow_dv_destroy_policer_rules,
14102 .counter_alloc = flow_dv_counter_allocate,
14103 .counter_free = flow_dv_counter_free,
14104 .counter_query = flow_dv_counter_query,
14105 .get_aged_flows = flow_get_aged_flows,
14106 .action_validate = flow_dv_action_validate,
14107 .action_create = flow_dv_action_create,
14108 .action_destroy = flow_dv_action_destroy,
14109 .action_update = flow_dv_action_update,
14110 .action_query = flow_dv_action_query,
14111 .sync_domain = flow_dv_sync_domain,
14114 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */