1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
92 * Initialize flow attributes structure according to flow items' types.
94 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
95 * mode. For tunnel mode, the items to be modified are the outermost ones.
98 * Pointer to item specification.
100 * Pointer to flow attributes structure.
101 * @param[in] dev_flow
102 * Pointer to the sub flow.
103 * @param[in] tunnel_decap
104 * Whether action is after tunnel decapsulation.
107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
108 struct mlx5_flow *dev_flow, bool tunnel_decap)
110 uint64_t layers = dev_flow->handle->layers;
113 * If layers is already initialized, it means this dev_flow is the
114 * suffix flow, the layers flags is set by the prefix flow. Need to
115 * use the layer flags from prefix flow as the suffix flow may not
116 * have the user defined items as the flow is split.
119 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
123 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
130 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
131 uint8_t next_protocol = 0xff;
132 switch (item->type) {
133 case RTE_FLOW_ITEM_TYPE_GRE:
134 case RTE_FLOW_ITEM_TYPE_NVGRE:
135 case RTE_FLOW_ITEM_TYPE_VXLAN:
136 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
137 case RTE_FLOW_ITEM_TYPE_GENEVE:
138 case RTE_FLOW_ITEM_TYPE_MPLS:
142 case RTE_FLOW_ITEM_TYPE_IPV4:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv4 *)
147 item->mask)->hdr.next_proto_id)
149 ((const struct rte_flow_item_ipv4 *)
150 (item->spec))->hdr.next_proto_id &
151 ((const struct rte_flow_item_ipv4 *)
152 (item->mask))->hdr.next_proto_id;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_IPV6:
160 if (item->mask != NULL &&
161 ((const struct rte_flow_item_ipv6 *)
162 item->mask)->hdr.proto)
164 ((const struct rte_flow_item_ipv6 *)
165 (item->spec))->hdr.proto &
166 ((const struct rte_flow_item_ipv6 *)
167 (item->mask))->hdr.proto;
168 if ((next_protocol == IPPROTO_IPIP ||
169 next_protocol == IPPROTO_IPV6) && tunnel_decap)
172 case RTE_FLOW_ITEM_TYPE_UDP:
176 case RTE_FLOW_ITEM_TYPE_TCP:
188 * Convert rte_mtr_color to mlx5 color.
197 rte_col_2_mlx5_col(enum rte_color rcol)
200 case RTE_COLOR_GREEN:
201 return MLX5_FLOW_COLOR_GREEN;
202 case RTE_COLOR_YELLOW:
203 return MLX5_FLOW_COLOR_YELLOW;
205 return MLX5_FLOW_COLOR_RED;
209 return MLX5_FLOW_COLOR_UNDEFINED;
212 struct field_modify_info {
213 uint32_t size; /* Size of field in protocol header, in bytes. */
214 uint32_t offset; /* Offset of field in protocol header, in bytes. */
215 enum mlx5_modification_field id;
218 struct field_modify_info modify_eth[] = {
219 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
220 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
221 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
222 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
226 struct field_modify_info modify_vlan_out_first_vid[] = {
227 /* Size in bits !!! */
228 {12, 0, MLX5_MODI_OUT_FIRST_VID},
232 struct field_modify_info modify_ipv4[] = {
233 {1, 1, MLX5_MODI_OUT_IP_DSCP},
234 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
235 {4, 12, MLX5_MODI_OUT_SIPV4},
236 {4, 16, MLX5_MODI_OUT_DIPV4},
240 struct field_modify_info modify_ipv6[] = {
241 {1, 0, MLX5_MODI_OUT_IP_DSCP},
242 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
243 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
244 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
245 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
246 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
247 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
248 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
249 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
250 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
254 struct field_modify_info modify_udp[] = {
255 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
256 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
260 struct field_modify_info modify_tcp[] = {
261 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
262 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
263 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
264 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
270 uint8_t next_protocol, uint64_t *item_flags,
273 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
274 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
275 if (next_protocol == IPPROTO_IPIP) {
276 *item_flags |= MLX5_FLOW_LAYER_IPIP;
279 if (next_protocol == IPPROTO_IPV6) {
280 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
285 /* Update VLAN's VID/PCP based on input rte_flow_action.
288 * Pointer to struct rte_flow_action.
290 * Pointer to struct rte_vlan_hdr.
293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
294 struct rte_vlan_hdr *vlan)
297 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
299 ((const struct rte_flow_action_of_set_vlan_pcp *)
300 action->conf)->vlan_pcp;
301 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
302 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
303 vlan->vlan_tci |= vlan_tci;
304 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
305 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
306 vlan->vlan_tci |= rte_be_to_cpu_16
307 (((const struct rte_flow_action_of_set_vlan_vid *)
308 action->conf)->vlan_vid);
313 * Fetch 1, 2, 3 or 4 byte field from the byte array
314 * and return as unsigned integer in host-endian format.
317 * Pointer to data array.
319 * Size of field to extract.
322 * converted field in host endian format.
324 static inline uint32_t
325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
334 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
337 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = (ret << 8) | *(data + sizeof(uint16_t));
341 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
352 * Convert modify-header action to DV specification.
354 * Data length of each action is determined by provided field description
355 * and the item mask. Data bit offset and width of each action is determined
356 * by provided item mask.
359 * Pointer to item specification.
361 * Pointer to field modification information.
362 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
363 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
366 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
367 * Negative offset value sets the same offset as source offset.
368 * size field is ignored, value is taken from source field.
369 * @param[in,out] resource
370 * Pointer to the modify-header resource.
372 * Type of modification.
374 * Pointer to the error structure.
377 * 0 on success, a negative errno value otherwise and rte_errno is set.
380 flow_dv_convert_modify_action(struct rte_flow_item *item,
381 struct field_modify_info *field,
382 struct field_modify_info *dcopy,
383 struct mlx5_flow_dv_modify_hdr_resource *resource,
384 uint32_t type, struct rte_flow_error *error)
386 uint32_t i = resource->actions_num;
387 struct mlx5_modification_cmd *actions = resource->actions;
390 * The item and mask are provided in big-endian format.
391 * The fields should be presented as in big-endian format either.
392 * Mask must be always present, it defines the actual field width.
394 MLX5_ASSERT(item->mask);
395 MLX5_ASSERT(field->size);
402 if (i >= MLX5_MAX_MODIFY_NUM)
403 return rte_flow_error_set(error, EINVAL,
404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
405 "too many items to modify");
406 /* Fetch variable byte size mask from the array. */
407 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
408 field->offset, field->size);
413 /* Deduce actual data width in bits from mask value. */
414 off_b = rte_bsf32(mask);
415 size_b = sizeof(uint32_t) * CHAR_BIT -
416 off_b - __builtin_clz(mask);
418 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
419 actions[i] = (struct mlx5_modification_cmd) {
425 /* Convert entire record to expected big-endian format. */
426 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
427 if (type == MLX5_MODIFICATION_TYPE_COPY) {
429 actions[i].dst_field = dcopy->id;
430 actions[i].dst_offset =
431 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
432 /* Convert entire record to big-endian format. */
433 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
436 MLX5_ASSERT(item->spec);
437 data = flow_dv_fetch_field((const uint8_t *)item->spec +
438 field->offset, field->size);
439 /* Shift out the trailing masked bits from data. */
440 data = (data & mask) >> off_b;
441 actions[i].data1 = rte_cpu_to_be_32(data);
445 } while (field->size);
446 if (resource->actions_num == i)
447 return rte_flow_error_set(error, EINVAL,
448 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
449 "invalid modification flow item");
450 resource->actions_num = i;
455 * Convert modify-header set IPv4 address action to DV specification.
457 * @param[in,out] resource
458 * Pointer to the modify-header resource.
460 * Pointer to action specification.
462 * Pointer to the error structure.
465 * 0 on success, a negative errno value otherwise and rte_errno is set.
468 flow_dv_convert_action_modify_ipv4
469 (struct mlx5_flow_dv_modify_hdr_resource *resource,
470 const struct rte_flow_action *action,
471 struct rte_flow_error *error)
473 const struct rte_flow_action_set_ipv4 *conf =
474 (const struct rte_flow_action_set_ipv4 *)(action->conf);
475 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
476 struct rte_flow_item_ipv4 ipv4;
477 struct rte_flow_item_ipv4 ipv4_mask;
479 memset(&ipv4, 0, sizeof(ipv4));
480 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
481 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
482 ipv4.hdr.src_addr = conf->ipv4_addr;
483 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
485 ipv4.hdr.dst_addr = conf->ipv4_addr;
486 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
489 item.mask = &ipv4_mask;
490 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
491 MLX5_MODIFICATION_TYPE_SET, error);
495 * Convert modify-header set IPv6 address action to DV specification.
497 * @param[in,out] resource
498 * Pointer to the modify-header resource.
500 * Pointer to action specification.
502 * Pointer to the error structure.
505 * 0 on success, a negative errno value otherwise and rte_errno is set.
508 flow_dv_convert_action_modify_ipv6
509 (struct mlx5_flow_dv_modify_hdr_resource *resource,
510 const struct rte_flow_action *action,
511 struct rte_flow_error *error)
513 const struct rte_flow_action_set_ipv6 *conf =
514 (const struct rte_flow_action_set_ipv6 *)(action->conf);
515 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
516 struct rte_flow_item_ipv6 ipv6;
517 struct rte_flow_item_ipv6 ipv6_mask;
519 memset(&ipv6, 0, sizeof(ipv6));
520 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
521 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
522 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
523 sizeof(ipv6.hdr.src_addr));
524 memcpy(&ipv6_mask.hdr.src_addr,
525 &rte_flow_item_ipv6_mask.hdr.src_addr,
526 sizeof(ipv6.hdr.src_addr));
528 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
529 sizeof(ipv6.hdr.dst_addr));
530 memcpy(&ipv6_mask.hdr.dst_addr,
531 &rte_flow_item_ipv6_mask.hdr.dst_addr,
532 sizeof(ipv6.hdr.dst_addr));
535 item.mask = &ipv6_mask;
536 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
537 MLX5_MODIFICATION_TYPE_SET, error);
541 * Convert modify-header set MAC address action to DV specification.
543 * @param[in,out] resource
544 * Pointer to the modify-header resource.
546 * Pointer to action specification.
548 * Pointer to the error structure.
551 * 0 on success, a negative errno value otherwise and rte_errno is set.
554 flow_dv_convert_action_modify_mac
555 (struct mlx5_flow_dv_modify_hdr_resource *resource,
556 const struct rte_flow_action *action,
557 struct rte_flow_error *error)
559 const struct rte_flow_action_set_mac *conf =
560 (const struct rte_flow_action_set_mac *)(action->conf);
561 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
562 struct rte_flow_item_eth eth;
563 struct rte_flow_item_eth eth_mask;
565 memset(ð, 0, sizeof(eth));
566 memset(ð_mask, 0, sizeof(eth_mask));
567 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
568 memcpy(ð.src.addr_bytes, &conf->mac_addr,
569 sizeof(eth.src.addr_bytes));
570 memcpy(ð_mask.src.addr_bytes,
571 &rte_flow_item_eth_mask.src.addr_bytes,
572 sizeof(eth_mask.src.addr_bytes));
574 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
575 sizeof(eth.dst.addr_bytes));
576 memcpy(ð_mask.dst.addr_bytes,
577 &rte_flow_item_eth_mask.dst.addr_bytes,
578 sizeof(eth_mask.dst.addr_bytes));
581 item.mask = ð_mask;
582 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set VLAN VID action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_vlan_vid
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_of_set_vlan_vid *conf =
606 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
607 int i = resource->actions_num;
608 struct mlx5_modification_cmd *actions = resource->actions;
609 struct field_modify_info *field = modify_vlan_out_first_vid;
611 if (i >= MLX5_MAX_MODIFY_NUM)
612 return rte_flow_error_set(error, EINVAL,
613 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
614 "too many items to modify");
615 actions[i] = (struct mlx5_modification_cmd) {
616 .action_type = MLX5_MODIFICATION_TYPE_SET,
618 .length = field->size,
619 .offset = field->offset,
621 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
622 actions[i].data1 = conf->vlan_vid;
623 actions[i].data1 = actions[i].data1 << 16;
624 resource->actions_num = ++i;
629 * Convert modify-header set TP action to DV specification.
631 * @param[in,out] resource
632 * Pointer to the modify-header resource.
634 * Pointer to action specification.
636 * Pointer to rte_flow_item objects list.
638 * Pointer to flow attributes structure.
639 * @param[in] dev_flow
640 * Pointer to the sub flow.
641 * @param[in] tunnel_decap
642 * Whether action is after tunnel decapsulation.
644 * Pointer to the error structure.
647 * 0 on success, a negative errno value otherwise and rte_errno is set.
650 flow_dv_convert_action_modify_tp
651 (struct mlx5_flow_dv_modify_hdr_resource *resource,
652 const struct rte_flow_action *action,
653 const struct rte_flow_item *items,
654 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
655 bool tunnel_decap, struct rte_flow_error *error)
657 const struct rte_flow_action_set_tp *conf =
658 (const struct rte_flow_action_set_tp *)(action->conf);
659 struct rte_flow_item item;
660 struct rte_flow_item_udp udp;
661 struct rte_flow_item_udp udp_mask;
662 struct rte_flow_item_tcp tcp;
663 struct rte_flow_item_tcp tcp_mask;
664 struct field_modify_info *field;
667 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
669 memset(&udp, 0, sizeof(udp));
670 memset(&udp_mask, 0, sizeof(udp_mask));
671 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
672 udp.hdr.src_port = conf->port;
673 udp_mask.hdr.src_port =
674 rte_flow_item_udp_mask.hdr.src_port;
676 udp.hdr.dst_port = conf->port;
677 udp_mask.hdr.dst_port =
678 rte_flow_item_udp_mask.hdr.dst_port;
680 item.type = RTE_FLOW_ITEM_TYPE_UDP;
682 item.mask = &udp_mask;
685 MLX5_ASSERT(attr->tcp);
686 memset(&tcp, 0, sizeof(tcp));
687 memset(&tcp_mask, 0, sizeof(tcp_mask));
688 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
689 tcp.hdr.src_port = conf->port;
690 tcp_mask.hdr.src_port =
691 rte_flow_item_tcp_mask.hdr.src_port;
693 tcp.hdr.dst_port = conf->port;
694 tcp_mask.hdr.dst_port =
695 rte_flow_item_tcp_mask.hdr.dst_port;
697 item.type = RTE_FLOW_ITEM_TYPE_TCP;
699 item.mask = &tcp_mask;
702 return flow_dv_convert_modify_action(&item, field, NULL, resource,
703 MLX5_MODIFICATION_TYPE_SET, error);
707 * Convert modify-header set TTL action to DV specification.
709 * @param[in,out] resource
710 * Pointer to the modify-header resource.
712 * Pointer to action specification.
714 * Pointer to rte_flow_item objects list.
716 * Pointer to flow attributes structure.
717 * @param[in] dev_flow
718 * Pointer to the sub flow.
719 * @param[in] tunnel_decap
720 * Whether action is after tunnel decapsulation.
722 * Pointer to the error structure.
725 * 0 on success, a negative errno value otherwise and rte_errno is set.
728 flow_dv_convert_action_modify_ttl
729 (struct mlx5_flow_dv_modify_hdr_resource *resource,
730 const struct rte_flow_action *action,
731 const struct rte_flow_item *items,
732 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
733 bool tunnel_decap, struct rte_flow_error *error)
735 const struct rte_flow_action_set_ttl *conf =
736 (const struct rte_flow_action_set_ttl *)(action->conf);
737 struct rte_flow_item item;
738 struct rte_flow_item_ipv4 ipv4;
739 struct rte_flow_item_ipv4 ipv4_mask;
740 struct rte_flow_item_ipv6 ipv6;
741 struct rte_flow_item_ipv6 ipv6_mask;
742 struct field_modify_info *field;
745 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
747 memset(&ipv4, 0, sizeof(ipv4));
748 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
749 ipv4.hdr.time_to_live = conf->ttl_value;
750 ipv4_mask.hdr.time_to_live = 0xFF;
751 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
753 item.mask = &ipv4_mask;
756 MLX5_ASSERT(attr->ipv6);
757 memset(&ipv6, 0, sizeof(ipv6));
758 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
759 ipv6.hdr.hop_limits = conf->ttl_value;
760 ipv6_mask.hdr.hop_limits = 0xFF;
761 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
763 item.mask = &ipv6_mask;
766 return flow_dv_convert_modify_action(&item, field, NULL, resource,
767 MLX5_MODIFICATION_TYPE_SET, error);
771 * Convert modify-header decrement TTL action to DV specification.
773 * @param[in,out] resource
774 * Pointer to the modify-header resource.
776 * Pointer to action specification.
778 * Pointer to rte_flow_item objects list.
780 * Pointer to flow attributes structure.
781 * @param[in] dev_flow
782 * Pointer to the sub flow.
783 * @param[in] tunnel_decap
784 * Whether action is after tunnel decapsulation.
786 * Pointer to the error structure.
789 * 0 on success, a negative errno value otherwise and rte_errno is set.
792 flow_dv_convert_action_modify_dec_ttl
793 (struct mlx5_flow_dv_modify_hdr_resource *resource,
794 const struct rte_flow_item *items,
795 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
796 bool tunnel_decap, struct rte_flow_error *error)
798 struct rte_flow_item item;
799 struct rte_flow_item_ipv4 ipv4;
800 struct rte_flow_item_ipv4 ipv4_mask;
801 struct rte_flow_item_ipv6 ipv6;
802 struct rte_flow_item_ipv6 ipv6_mask;
803 struct field_modify_info *field;
806 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
808 memset(&ipv4, 0, sizeof(ipv4));
809 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
810 ipv4.hdr.time_to_live = 0xFF;
811 ipv4_mask.hdr.time_to_live = 0xFF;
812 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
814 item.mask = &ipv4_mask;
817 MLX5_ASSERT(attr->ipv6);
818 memset(&ipv6, 0, sizeof(ipv6));
819 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
820 ipv6.hdr.hop_limits = 0xFF;
821 ipv6_mask.hdr.hop_limits = 0xFF;
822 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
824 item.mask = &ipv6_mask;
827 return flow_dv_convert_modify_action(&item, field, NULL, resource,
828 MLX5_MODIFICATION_TYPE_ADD, error);
832 * Convert modify-header increment/decrement TCP Sequence number
833 * to DV specification.
835 * @param[in,out] resource
836 * Pointer to the modify-header resource.
838 * Pointer to action specification.
840 * Pointer to the error structure.
843 * 0 on success, a negative errno value otherwise and rte_errno is set.
846 flow_dv_convert_action_modify_tcp_seq
847 (struct mlx5_flow_dv_modify_hdr_resource *resource,
848 const struct rte_flow_action *action,
849 struct rte_flow_error *error)
851 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
852 uint64_t value = rte_be_to_cpu_32(*conf);
853 struct rte_flow_item item;
854 struct rte_flow_item_tcp tcp;
855 struct rte_flow_item_tcp tcp_mask;
857 memset(&tcp, 0, sizeof(tcp));
858 memset(&tcp_mask, 0, sizeof(tcp_mask));
859 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
861 * The HW has no decrement operation, only increment operation.
862 * To simulate decrement X from Y using increment operation
863 * we need to add UINT32_MAX X times to Y.
864 * Each adding of UINT32_MAX decrements Y by 1.
867 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
868 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
869 item.type = RTE_FLOW_ITEM_TYPE_TCP;
871 item.mask = &tcp_mask;
872 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
873 MLX5_MODIFICATION_TYPE_ADD, error);
877 * Convert modify-header increment/decrement TCP Acknowledgment number
878 * to DV specification.
880 * @param[in,out] resource
881 * Pointer to the modify-header resource.
883 * Pointer to action specification.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_tcp_ack
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_action *action,
894 struct rte_flow_error *error)
896 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
897 uint64_t value = rte_be_to_cpu_32(*conf);
898 struct rte_flow_item item;
899 struct rte_flow_item_tcp tcp;
900 struct rte_flow_item_tcp tcp_mask;
902 memset(&tcp, 0, sizeof(tcp));
903 memset(&tcp_mask, 0, sizeof(tcp_mask));
904 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
906 * The HW has no decrement operation, only increment operation.
907 * To simulate decrement X from Y using increment operation
908 * we need to add UINT32_MAX X times to Y.
909 * Each adding of UINT32_MAX decrements Y by 1.
912 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
913 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
914 item.type = RTE_FLOW_ITEM_TYPE_TCP;
916 item.mask = &tcp_mask;
917 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
918 MLX5_MODIFICATION_TYPE_ADD, error);
921 static enum mlx5_modification_field reg_to_field[] = {
922 [REG_NON] = MLX5_MODI_OUT_NONE,
923 [REG_A] = MLX5_MODI_META_DATA_REG_A,
924 [REG_B] = MLX5_MODI_META_DATA_REG_B,
925 [REG_C_0] = MLX5_MODI_META_REG_C_0,
926 [REG_C_1] = MLX5_MODI_META_REG_C_1,
927 [REG_C_2] = MLX5_MODI_META_REG_C_2,
928 [REG_C_3] = MLX5_MODI_META_REG_C_3,
929 [REG_C_4] = MLX5_MODI_META_REG_C_4,
930 [REG_C_5] = MLX5_MODI_META_REG_C_5,
931 [REG_C_6] = MLX5_MODI_META_REG_C_6,
932 [REG_C_7] = MLX5_MODI_META_REG_C_7,
936 * Convert register set to DV specification.
938 * @param[in,out] resource
939 * Pointer to the modify-header resource.
941 * Pointer to action specification.
943 * Pointer to the error structure.
946 * 0 on success, a negative errno value otherwise and rte_errno is set.
949 flow_dv_convert_action_set_reg
950 (struct mlx5_flow_dv_modify_hdr_resource *resource,
951 const struct rte_flow_action *action,
952 struct rte_flow_error *error)
954 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
955 struct mlx5_modification_cmd *actions = resource->actions;
956 uint32_t i = resource->actions_num;
958 if (i >= MLX5_MAX_MODIFY_NUM)
959 return rte_flow_error_set(error, EINVAL,
960 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
961 "too many items to modify");
962 MLX5_ASSERT(conf->id != REG_NON);
963 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
964 actions[i] = (struct mlx5_modification_cmd) {
965 .action_type = MLX5_MODIFICATION_TYPE_SET,
966 .field = reg_to_field[conf->id],
968 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
969 actions[i].data1 = rte_cpu_to_be_32(conf->data);
971 resource->actions_num = i;
976 * Convert SET_TAG action to DV specification.
979 * Pointer to the rte_eth_dev structure.
980 * @param[in,out] resource
981 * Pointer to the modify-header resource.
983 * Pointer to action specification.
985 * Pointer to the error structure.
988 * 0 on success, a negative errno value otherwise and rte_errno is set.
991 flow_dv_convert_action_set_tag
992 (struct rte_eth_dev *dev,
993 struct mlx5_flow_dv_modify_hdr_resource *resource,
994 const struct rte_flow_action_set_tag *conf,
995 struct rte_flow_error *error)
997 rte_be32_t data = rte_cpu_to_be_32(conf->data);
998 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
999 struct rte_flow_item item = {
1003 struct field_modify_info reg_c_x[] = {
1006 enum mlx5_modification_field reg_type;
1009 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1012 MLX5_ASSERT(ret != REG_NON);
1013 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014 reg_type = reg_to_field[ret];
1015 MLX5_ASSERT(reg_type > 0);
1016 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018 MLX5_MODIFICATION_TYPE_SET, error);
1022 * Convert internal COPY_REG action to DV specification.
1025 * Pointer to the rte_eth_dev structure.
1026 * @param[in,out] res
1027 * Pointer to the modify-header resource.
1029 * Pointer to action specification.
1031 * Pointer to the error structure.
1034 * 0 on success, a negative errno value otherwise and rte_errno is set.
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038 struct mlx5_flow_dv_modify_hdr_resource *res,
1039 const struct rte_flow_action *action,
1040 struct rte_flow_error *error)
1042 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044 struct rte_flow_item item = {
1048 struct field_modify_info reg_src[] = {
1049 {4, 0, reg_to_field[conf->src]},
1052 struct field_modify_info reg_dst = {
1054 .id = reg_to_field[conf->dst],
1056 /* Adjust reg_c[0] usage according to reported mask. */
1057 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058 struct mlx5_priv *priv = dev->data->dev_private;
1059 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1061 MLX5_ASSERT(reg_c0);
1062 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063 if (conf->dst == REG_C_0) {
1064 /* Copy to reg_c[0], within mask only. */
1065 reg_dst.offset = rte_bsf32(reg_c0);
1067 * Mask is ignoring the enianness, because
1068 * there is no conversion in datapath.
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071 /* Copy from destination lower bits to reg_c[0]. */
1072 mask = reg_c0 >> reg_dst.offset;
1074 /* Copy from destination upper bits to reg_c[0]. */
1075 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076 rte_fls_u32(reg_c0));
1079 mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081 /* Copy from reg_c[0] to destination lower bits. */
1084 /* Copy from reg_c[0] to destination upper bits. */
1085 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086 (rte_fls_u32(reg_c0) -
1091 return flow_dv_convert_modify_action(&item,
1092 reg_src, ®_dst, res,
1093 MLX5_MODIFICATION_TYPE_COPY,
1098 * Convert MARK action to DV specification. This routine is used
1099 * in extensive metadata only and requires metadata register to be
1100 * handled. In legacy mode hardware tag resource is engaged.
1103 * Pointer to the rte_eth_dev structure.
1105 * Pointer to MARK action specification.
1106 * @param[in,out] resource
1107 * Pointer to the modify-header resource.
1109 * Pointer to the error structure.
1112 * 0 on success, a negative errno value otherwise and rte_errno is set.
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116 const struct rte_flow_action_mark *conf,
1117 struct mlx5_flow_dv_modify_hdr_resource *resource,
1118 struct rte_flow_error *error)
1120 struct mlx5_priv *priv = dev->data->dev_private;
1121 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122 priv->sh->dv_mark_mask);
1123 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124 struct rte_flow_item item = {
1128 struct field_modify_info reg_c_x[] = {
1134 return rte_flow_error_set(error, EINVAL,
1135 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136 NULL, "zero mark action mask");
1137 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1140 MLX5_ASSERT(reg > 0);
1141 if (reg == REG_C_0) {
1142 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143 uint32_t shl_c0 = rte_bsf32(msk_c0);
1145 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147 mask = rte_cpu_to_be_32(mask << shl_c0);
1149 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151 MLX5_MODIFICATION_TYPE_SET, error);
1155 * Get metadata register index for specified steering domain.
1158 * Pointer to the rte_eth_dev structure.
1160 * Attributes of flow to determine steering domain.
1162 * Pointer to the error structure.
1165 * positive index on success, a negative errno value otherwise
1166 * and rte_errno is set.
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170 const struct rte_flow_attr *attr,
1171 struct rte_flow_error *error)
1174 mlx5_flow_get_reg_id(dev, attr->transfer ?
1178 MLX5_METADATA_RX, 0, error);
1180 return rte_flow_error_set(error,
1181 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182 NULL, "unavailable "
1183 "metadata register");
1188 * Convert SET_META action to DV specification.
1191 * Pointer to the rte_eth_dev structure.
1192 * @param[in,out] resource
1193 * Pointer to the modify-header resource.
1195 * Attributes of flow that includes this item.
1197 * Pointer to action specification.
1199 * Pointer to the error structure.
1202 * 0 on success, a negative errno value otherwise and rte_errno is set.
1205 flow_dv_convert_action_set_meta
1206 (struct rte_eth_dev *dev,
1207 struct mlx5_flow_dv_modify_hdr_resource *resource,
1208 const struct rte_flow_attr *attr,
1209 const struct rte_flow_action_set_meta *conf,
1210 struct rte_flow_error *error)
1212 uint32_t data = conf->data;
1213 uint32_t mask = conf->mask;
1214 struct rte_flow_item item = {
1218 struct field_modify_info reg_c_x[] = {
1221 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225 MLX5_ASSERT(reg != REG_NON);
1227 * In datapath code there is no endianness
1228 * coversions for perfromance reasons, all
1229 * pattern conversions are done in rte_flow.
1231 if (reg == REG_C_0) {
1232 struct mlx5_priv *priv = dev->data->dev_private;
1233 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1236 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238 shl_c0 = rte_bsf32(msk_c0);
1240 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1244 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1246 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247 /* The routine expects parameters in memory as big-endian ones. */
1248 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249 MLX5_MODIFICATION_TYPE_SET, error);
1253 * Convert modify-header set IPv4 DSCP action to DV specification.
1255 * @param[in,out] resource
1256 * Pointer to the modify-header resource.
1258 * Pointer to action specification.
1260 * Pointer to the error structure.
1263 * 0 on success, a negative errno value otherwise and rte_errno is set.
1266 flow_dv_convert_action_modify_ipv4_dscp
1267 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268 const struct rte_flow_action *action,
1269 struct rte_flow_error *error)
1271 const struct rte_flow_action_set_dscp *conf =
1272 (const struct rte_flow_action_set_dscp *)(action->conf);
1273 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274 struct rte_flow_item_ipv4 ipv4;
1275 struct rte_flow_item_ipv4 ipv4_mask;
1277 memset(&ipv4, 0, sizeof(ipv4));
1278 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279 ipv4.hdr.type_of_service = conf->dscp;
1280 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1282 item.mask = &ipv4_mask;
1283 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284 MLX5_MODIFICATION_TYPE_SET, error);
1288 * Convert modify-header set IPv6 DSCP action to DV specification.
1290 * @param[in,out] resource
1291 * Pointer to the modify-header resource.
1293 * Pointer to action specification.
1295 * Pointer to the error structure.
1298 * 0 on success, a negative errno value otherwise and rte_errno is set.
1301 flow_dv_convert_action_modify_ipv6_dscp
1302 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303 const struct rte_flow_action *action,
1304 struct rte_flow_error *error)
1306 const struct rte_flow_action_set_dscp *conf =
1307 (const struct rte_flow_action_set_dscp *)(action->conf);
1308 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309 struct rte_flow_item_ipv6 ipv6;
1310 struct rte_flow_item_ipv6 ipv6_mask;
1312 memset(&ipv6, 0, sizeof(ipv6));
1313 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1315 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316 * rdma-core only accept the DSCP bits byte aligned start from
1317 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318 * bits in IPv6 case as rdma-core requires byte aligned value.
1320 ipv6.hdr.vtc_flow = conf->dscp;
1321 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1323 item.mask = &ipv6_mask;
1324 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325 MLX5_MODIFICATION_TYPE_SET, error);
1329 mlx5_flow_field_id_to_modify_info
1330 (const struct rte_flow_action_modify_data *data,
1331 struct field_modify_info *info,
1332 uint32_t *mask, uint32_t *value, uint32_t width,
1333 struct rte_eth_dev *dev,
1334 const struct rte_flow_attr *attr,
1335 struct rte_flow_error *error)
1338 switch (data->field) {
1339 case RTE_FLOW_FIELD_START:
1340 /* not supported yet */
1343 case RTE_FLOW_FIELD_MAC_DST:
1345 if (data->offset < 32) {
1346 info[idx] = (struct field_modify_info){4, 0,
1347 MLX5_MODI_OUT_DMAC_47_16};
1348 mask[idx] = 0xffffffff;
1350 mask[idx] = mask[idx] << (32 - width);
1359 info[idx] = (struct field_modify_info){2, 4 * idx,
1360 MLX5_MODI_OUT_DMAC_15_0};
1361 mask[idx] = (width) ? 0x0000ffff : 0x0;
1363 mask[idx] = (mask[idx] << (16 - width)) &
1366 if (data->offset < 32)
1367 info[idx++] = (struct field_modify_info){4, 0,
1368 MLX5_MODI_OUT_DMAC_47_16};
1369 info[idx] = (struct field_modify_info){2, 0,
1370 MLX5_MODI_OUT_DMAC_15_0};
1373 case RTE_FLOW_FIELD_MAC_SRC:
1375 if (data->offset < 32) {
1376 info[idx] = (struct field_modify_info){4, 0,
1377 MLX5_MODI_OUT_SMAC_47_16};
1378 mask[idx] = 0xffffffff;
1380 mask[idx] = mask[idx] << (32 - width);
1389 info[idx] = (struct field_modify_info){2, 4 * idx,
1390 MLX5_MODI_OUT_SMAC_15_0};
1391 mask[idx] = (width) ? 0x0000ffff : 0x0;
1393 mask[idx] = (mask[idx] << (16 - width)) &
1396 if (data->offset < 32)
1397 info[idx++] = (struct field_modify_info){4, 0,
1398 MLX5_MODI_OUT_SMAC_47_16};
1399 info[idx] = (struct field_modify_info){2, 0,
1400 MLX5_MODI_OUT_SMAC_15_0};
1403 case RTE_FLOW_FIELD_VLAN_TYPE:
1404 /* not supported yet */
1406 case RTE_FLOW_FIELD_VLAN_ID:
1407 info[idx] = (struct field_modify_info){2, 0,
1408 MLX5_MODI_OUT_FIRST_VID};
1410 mask[idx] = 0x00000fff;
1412 mask[idx] = (mask[idx] << (12 - width)) &
1416 case RTE_FLOW_FIELD_MAC_TYPE:
1417 info[idx] = (struct field_modify_info){2, 0,
1418 MLX5_MODI_OUT_ETHERTYPE};
1420 mask[idx] = 0x0000ffff;
1422 mask[idx] = (mask[idx] << (16 - width)) &
1426 case RTE_FLOW_FIELD_IPV4_DSCP:
1427 info[idx] = (struct field_modify_info){1, 0,
1428 MLX5_MODI_OUT_IP_DSCP};
1430 mask[idx] = 0x0000003f;
1432 mask[idx] = (mask[idx] << (6 - width)) &
1436 case RTE_FLOW_FIELD_IPV4_TTL:
1437 info[idx] = (struct field_modify_info){1, 0,
1438 MLX5_MODI_OUT_IPV4_TTL};
1440 mask[idx] = 0x000000ff;
1442 mask[idx] = (mask[idx] << (8 - width)) &
1446 case RTE_FLOW_FIELD_IPV4_SRC:
1447 info[idx] = (struct field_modify_info){4, 0,
1448 MLX5_MODI_OUT_SIPV4};
1450 mask[idx] = 0xffffffff;
1452 mask[idx] = mask[idx] << (32 - width);
1455 case RTE_FLOW_FIELD_IPV4_DST:
1456 info[idx] = (struct field_modify_info){4, 0,
1457 MLX5_MODI_OUT_DIPV4};
1459 mask[idx] = 0xffffffff;
1461 mask[idx] = mask[idx] << (32 - width);
1464 case RTE_FLOW_FIELD_IPV6_DSCP:
1465 info[idx] = (struct field_modify_info){1, 0,
1466 MLX5_MODI_OUT_IP_DSCP};
1468 mask[idx] = 0x0000003f;
1470 mask[idx] = (mask[idx] << (6 - width)) &
1474 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1475 info[idx] = (struct field_modify_info){1, 0,
1476 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1478 mask[idx] = 0x000000ff;
1480 mask[idx] = (mask[idx] << (8 - width)) &
1484 case RTE_FLOW_FIELD_IPV6_SRC:
1486 if (data->offset < 32) {
1487 info[idx] = (struct field_modify_info){4, 0,
1488 MLX5_MODI_OUT_SIPV6_127_96};
1489 mask[idx] = 0xffffffff;
1491 mask[idx] = mask[idx] << (32 - width);
1500 if (data->offset < 64) {
1501 info[idx] = (struct field_modify_info){4,
1503 MLX5_MODI_OUT_SIPV6_95_64};
1504 mask[idx] = 0xffffffff;
1506 mask[idx] = mask[idx] << (32 - width);
1515 if (data->offset < 96) {
1516 info[idx] = (struct field_modify_info){4,
1518 MLX5_MODI_OUT_SIPV6_63_32};
1519 mask[idx] = 0xffffffff;
1521 mask[idx] = mask[idx] << (32 - width);
1530 info[idx] = (struct field_modify_info){4, 12 * idx,
1531 MLX5_MODI_OUT_SIPV6_31_0};
1532 mask[idx] = 0xffffffff;
1534 mask[idx] = mask[idx] << (32 - width);
1536 if (data->offset < 32)
1537 info[idx++] = (struct field_modify_info){4, 0,
1538 MLX5_MODI_OUT_SIPV6_127_96};
1539 if (data->offset < 64)
1540 info[idx++] = (struct field_modify_info){4, 0,
1541 MLX5_MODI_OUT_SIPV6_95_64};
1542 if (data->offset < 96)
1543 info[idx++] = (struct field_modify_info){4, 0,
1544 MLX5_MODI_OUT_SIPV6_63_32};
1545 if (data->offset < 128)
1546 info[idx++] = (struct field_modify_info){4, 0,
1547 MLX5_MODI_OUT_SIPV6_31_0};
1550 case RTE_FLOW_FIELD_IPV6_DST:
1552 if (data->offset < 32) {
1553 info[idx] = (struct field_modify_info){4, 0,
1554 MLX5_MODI_OUT_DIPV6_127_96};
1555 mask[idx] = 0xffffffff;
1557 mask[idx] = mask[idx] << (32 - width);
1566 if (data->offset < 64) {
1567 info[idx] = (struct field_modify_info){4,
1569 MLX5_MODI_OUT_DIPV6_95_64};
1570 mask[idx] = 0xffffffff;
1572 mask[idx] = mask[idx] << (32 - width);
1581 if (data->offset < 96) {
1582 info[idx] = (struct field_modify_info){4,
1584 MLX5_MODI_OUT_DIPV6_63_32};
1585 mask[idx] = 0xffffffff;
1587 mask[idx] = mask[idx] << (32 - width);
1596 info[idx] = (struct field_modify_info){4, 12 * idx,
1597 MLX5_MODI_OUT_DIPV6_31_0};
1598 mask[idx] = 0xffffffff;
1600 mask[idx] = mask[idx] << (32 - width);
1602 if (data->offset < 32)
1603 info[idx++] = (struct field_modify_info){4, 0,
1604 MLX5_MODI_OUT_DIPV6_127_96};
1605 if (data->offset < 64)
1606 info[idx++] = (struct field_modify_info){4, 0,
1607 MLX5_MODI_OUT_DIPV6_95_64};
1608 if (data->offset < 96)
1609 info[idx++] = (struct field_modify_info){4, 0,
1610 MLX5_MODI_OUT_DIPV6_63_32};
1611 if (data->offset < 128)
1612 info[idx++] = (struct field_modify_info){4, 0,
1613 MLX5_MODI_OUT_DIPV6_31_0};
1616 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1617 info[idx] = (struct field_modify_info){2, 0,
1618 MLX5_MODI_OUT_TCP_SPORT};
1620 mask[idx] = 0x0000ffff;
1622 mask[idx] = (mask[idx] << (16 - width)) &
1626 case RTE_FLOW_FIELD_TCP_PORT_DST:
1627 info[idx] = (struct field_modify_info){2, 0,
1628 MLX5_MODI_OUT_TCP_DPORT};
1630 mask[idx] = 0x0000ffff;
1632 mask[idx] = (mask[idx] << (16 - width)) &
1636 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1637 info[idx] = (struct field_modify_info){4, 0,
1638 MLX5_MODI_OUT_TCP_SEQ_NUM};
1640 mask[idx] = 0xffffffff;
1642 mask[idx] = (mask[idx] << (32 - width));
1645 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1646 info[idx] = (struct field_modify_info){4, 0,
1647 MLX5_MODI_OUT_TCP_ACK_NUM};
1649 mask[idx] = 0xffffffff;
1651 mask[idx] = (mask[idx] << (32 - width));
1654 case RTE_FLOW_FIELD_TCP_FLAGS:
1655 info[idx] = (struct field_modify_info){1, 0,
1656 MLX5_MODI_OUT_TCP_FLAGS};
1658 mask[idx] = 0x0000003f;
1660 mask[idx] = (mask[idx] << (6 - width)) &
1664 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1665 info[idx] = (struct field_modify_info){2, 0,
1666 MLX5_MODI_OUT_UDP_SPORT};
1668 mask[idx] = 0x0000ffff;
1670 mask[idx] = (mask[idx] << (16 - width)) &
1674 case RTE_FLOW_FIELD_UDP_PORT_DST:
1675 info[idx] = (struct field_modify_info){2, 0,
1676 MLX5_MODI_OUT_UDP_DPORT};
1678 mask[idx] = 0x0000ffff;
1680 mask[idx] = (mask[idx] << (16 - width)) &
1684 case RTE_FLOW_FIELD_VXLAN_VNI:
1685 /* not supported yet */
1687 case RTE_FLOW_FIELD_GENEVE_VNI:
1688 /* not supported yet*/
1690 case RTE_FLOW_FIELD_GTP_TEID:
1691 info[idx] = (struct field_modify_info){4, 0,
1692 MLX5_MODI_GTP_TEID};
1694 mask[idx] = 0xffffffff;
1696 mask[idx] = mask[idx] << (32 - width);
1699 case RTE_FLOW_FIELD_TAG:
1701 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1702 data->level, error);
1705 MLX5_ASSERT(reg != REG_NON);
1706 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1707 info[idx] = (struct field_modify_info){4, 0,
1710 mask[idx] = 0xffffffff;
1712 mask[idx] = mask[idx] << (32 - width);
1716 case RTE_FLOW_FIELD_MARK:
1718 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1722 MLX5_ASSERT(reg != REG_NON);
1723 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1724 info[idx] = (struct field_modify_info){4, 0,
1727 mask[idx] = 0xffffffff;
1729 mask[idx] = mask[idx] << (32 - width);
1733 case RTE_FLOW_FIELD_META:
1735 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1738 MLX5_ASSERT(reg != REG_NON);
1739 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1740 info[idx] = (struct field_modify_info){4, 0,
1743 mask[idx] = 0xffffffff;
1745 mask[idx] = mask[idx] << (32 - width);
1749 case RTE_FLOW_FIELD_POINTER:
1750 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1753 (void *)(uintptr_t)data->value, 32);
1754 value[idx] = RTE_BE32(value[idx]);
1759 case RTE_FLOW_FIELD_VALUE:
1760 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1762 value[idx] = RTE_BE32((uint32_t)data->value);
1774 * Convert modify_field action to DV specification.
1777 * Pointer to the rte_eth_dev structure.
1778 * @param[in,out] resource
1779 * Pointer to the modify-header resource.
1781 * Pointer to action specification.
1783 * Attributes of flow that includes this item.
1785 * Pointer to the error structure.
1788 * 0 on success, a negative errno value otherwise and rte_errno is set.
1791 flow_dv_convert_action_modify_field
1792 (struct rte_eth_dev *dev,
1793 struct mlx5_flow_dv_modify_hdr_resource *resource,
1794 const struct rte_flow_action *action,
1795 const struct rte_flow_attr *attr,
1796 struct rte_flow_error *error)
1798 const struct rte_flow_action_modify_field *conf =
1799 (const struct rte_flow_action_modify_field *)(action->conf);
1800 struct rte_flow_item item;
1801 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1803 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1805 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1806 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1809 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1810 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1811 type = MLX5_MODIFICATION_TYPE_SET;
1812 /** For SET fill the destination field (field) first. */
1813 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1814 value, conf->width, dev, attr, error);
1815 /** Then copy immediate value from source as per mask. */
1816 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1817 value, conf->width, dev, attr, error);
1820 type = MLX5_MODIFICATION_TYPE_COPY;
1821 /** For COPY fill the destination field (dcopy) without mask. */
1822 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1823 value, conf->width, dev, attr, error);
1824 /** Then construct the source field (field) with mask. */
1825 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1826 value, conf->width, dev, attr, error);
1829 return flow_dv_convert_modify_action(&item,
1830 field, dcopy, resource, type, error);
1834 * Validate MARK item.
1837 * Pointer to the rte_eth_dev structure.
1839 * Item specification.
1841 * Attributes of flow that includes this item.
1843 * Pointer to error structure.
1846 * 0 on success, a negative errno value otherwise and rte_errno is set.
1849 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1850 const struct rte_flow_item *item,
1851 const struct rte_flow_attr *attr __rte_unused,
1852 struct rte_flow_error *error)
1854 struct mlx5_priv *priv = dev->data->dev_private;
1855 struct mlx5_dev_config *config = &priv->config;
1856 const struct rte_flow_item_mark *spec = item->spec;
1857 const struct rte_flow_item_mark *mask = item->mask;
1858 const struct rte_flow_item_mark nic_mask = {
1859 .id = priv->sh->dv_mark_mask,
1863 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1864 return rte_flow_error_set(error, ENOTSUP,
1865 RTE_FLOW_ERROR_TYPE_ITEM, item,
1866 "extended metadata feature"
1868 if (!mlx5_flow_ext_mreg_supported(dev))
1869 return rte_flow_error_set(error, ENOTSUP,
1870 RTE_FLOW_ERROR_TYPE_ITEM, item,
1871 "extended metadata register"
1872 " isn't supported");
1874 return rte_flow_error_set(error, ENOTSUP,
1875 RTE_FLOW_ERROR_TYPE_ITEM, item,
1876 "extended metadata register"
1877 " isn't available");
1878 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1882 return rte_flow_error_set(error, EINVAL,
1883 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1885 "data cannot be empty");
1886 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1887 return rte_flow_error_set(error, EINVAL,
1888 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1890 "mark id exceeds the limit");
1894 return rte_flow_error_set(error, EINVAL,
1895 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1896 "mask cannot be zero");
1898 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1899 (const uint8_t *)&nic_mask,
1900 sizeof(struct rte_flow_item_mark),
1901 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1908 * Validate META item.
1911 * Pointer to the rte_eth_dev structure.
1913 * Item specification.
1915 * Attributes of flow that includes this item.
1917 * Pointer to error structure.
1920 * 0 on success, a negative errno value otherwise and rte_errno is set.
1923 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1924 const struct rte_flow_item *item,
1925 const struct rte_flow_attr *attr,
1926 struct rte_flow_error *error)
1928 struct mlx5_priv *priv = dev->data->dev_private;
1929 struct mlx5_dev_config *config = &priv->config;
1930 const struct rte_flow_item_meta *spec = item->spec;
1931 const struct rte_flow_item_meta *mask = item->mask;
1932 struct rte_flow_item_meta nic_mask = {
1939 return rte_flow_error_set(error, EINVAL,
1940 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1942 "data cannot be empty");
1943 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1944 if (!mlx5_flow_ext_mreg_supported(dev))
1945 return rte_flow_error_set(error, ENOTSUP,
1946 RTE_FLOW_ERROR_TYPE_ITEM, item,
1947 "extended metadata register"
1948 " isn't supported");
1949 reg = flow_dv_get_metadata_reg(dev, attr, error);
1953 return rte_flow_error_set(error, ENOTSUP,
1954 RTE_FLOW_ERROR_TYPE_ITEM, item,
1955 "unavalable extended metadata register");
1957 return rte_flow_error_set(error, ENOTSUP,
1958 RTE_FLOW_ERROR_TYPE_ITEM, item,
1962 nic_mask.data = priv->sh->dv_meta_mask;
1965 return rte_flow_error_set(error, ENOTSUP,
1966 RTE_FLOW_ERROR_TYPE_ITEM, item,
1967 "extended metadata feature "
1968 "should be enabled when "
1969 "meta item is requested "
1970 "with e-switch mode ");
1972 return rte_flow_error_set(error, ENOTSUP,
1973 RTE_FLOW_ERROR_TYPE_ITEM, item,
1974 "match on metadata for ingress "
1975 "is not supported in legacy "
1979 mask = &rte_flow_item_meta_mask;
1981 return rte_flow_error_set(error, EINVAL,
1982 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1983 "mask cannot be zero");
1985 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1986 (const uint8_t *)&nic_mask,
1987 sizeof(struct rte_flow_item_meta),
1988 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1993 * Validate TAG item.
1996 * Pointer to the rte_eth_dev structure.
1998 * Item specification.
2000 * Attributes of flow that includes this item.
2002 * Pointer to error structure.
2005 * 0 on success, a negative errno value otherwise and rte_errno is set.
2008 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2009 const struct rte_flow_item *item,
2010 const struct rte_flow_attr *attr __rte_unused,
2011 struct rte_flow_error *error)
2013 const struct rte_flow_item_tag *spec = item->spec;
2014 const struct rte_flow_item_tag *mask = item->mask;
2015 const struct rte_flow_item_tag nic_mask = {
2016 .data = RTE_BE32(UINT32_MAX),
2021 if (!mlx5_flow_ext_mreg_supported(dev))
2022 return rte_flow_error_set(error, ENOTSUP,
2023 RTE_FLOW_ERROR_TYPE_ITEM, item,
2024 "extensive metadata register"
2025 " isn't supported");
2027 return rte_flow_error_set(error, EINVAL,
2028 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2030 "data cannot be empty");
2032 mask = &rte_flow_item_tag_mask;
2034 return rte_flow_error_set(error, EINVAL,
2035 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2036 "mask cannot be zero");
2038 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2039 (const uint8_t *)&nic_mask,
2040 sizeof(struct rte_flow_item_tag),
2041 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2044 if (mask->index != 0xff)
2045 return rte_flow_error_set(error, EINVAL,
2046 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2047 "partial mask for tag index"
2048 " is not supported");
2049 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2052 MLX5_ASSERT(ret != REG_NON);
2057 * Validate vport item.
2060 * Pointer to the rte_eth_dev structure.
2062 * Item specification.
2064 * Attributes of flow that includes this item.
2065 * @param[in] item_flags
2066 * Bit-fields that holds the items detected until now.
2068 * Pointer to error structure.
2071 * 0 on success, a negative errno value otherwise and rte_errno is set.
2074 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2075 const struct rte_flow_item *item,
2076 const struct rte_flow_attr *attr,
2077 uint64_t item_flags,
2078 struct rte_flow_error *error)
2080 const struct rte_flow_item_port_id *spec = item->spec;
2081 const struct rte_flow_item_port_id *mask = item->mask;
2082 const struct rte_flow_item_port_id switch_mask = {
2085 struct mlx5_priv *esw_priv;
2086 struct mlx5_priv *dev_priv;
2089 if (!attr->transfer)
2090 return rte_flow_error_set(error, EINVAL,
2091 RTE_FLOW_ERROR_TYPE_ITEM,
2093 "match on port id is valid only"
2094 " when transfer flag is enabled");
2095 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2096 return rte_flow_error_set(error, ENOTSUP,
2097 RTE_FLOW_ERROR_TYPE_ITEM, item,
2098 "multiple source ports are not"
2101 mask = &switch_mask;
2102 if (mask->id != 0xffffffff)
2103 return rte_flow_error_set(error, ENOTSUP,
2104 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2106 "no support for partial mask on"
2108 ret = mlx5_flow_item_acceptable
2109 (item, (const uint8_t *)mask,
2110 (const uint8_t *)&rte_flow_item_port_id_mask,
2111 sizeof(struct rte_flow_item_port_id),
2112 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2117 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2119 return rte_flow_error_set(error, rte_errno,
2120 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2121 "failed to obtain E-Switch info for"
2123 dev_priv = mlx5_dev_to_eswitch_info(dev);
2125 return rte_flow_error_set(error, rte_errno,
2126 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2128 "failed to obtain E-Switch info");
2129 if (esw_priv->domain_id != dev_priv->domain_id)
2130 return rte_flow_error_set(error, EINVAL,
2131 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2132 "cannot match on a port from a"
2133 " different E-Switch");
2138 * Validate VLAN item.
2141 * Item specification.
2142 * @param[in] item_flags
2143 * Bit-fields that holds the items detected until now.
2145 * Ethernet device flow is being created on.
2147 * Pointer to error structure.
2150 * 0 on success, a negative errno value otherwise and rte_errno is set.
2153 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2154 uint64_t item_flags,
2155 struct rte_eth_dev *dev,
2156 struct rte_flow_error *error)
2158 const struct rte_flow_item_vlan *mask = item->mask;
2159 const struct rte_flow_item_vlan nic_mask = {
2160 .tci = RTE_BE16(UINT16_MAX),
2161 .inner_type = RTE_BE16(UINT16_MAX),
2164 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2166 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2167 MLX5_FLOW_LAYER_INNER_L4) :
2168 (MLX5_FLOW_LAYER_OUTER_L3 |
2169 MLX5_FLOW_LAYER_OUTER_L4);
2170 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2171 MLX5_FLOW_LAYER_OUTER_VLAN;
2173 if (item_flags & vlanm)
2174 return rte_flow_error_set(error, EINVAL,
2175 RTE_FLOW_ERROR_TYPE_ITEM, item,
2176 "multiple VLAN layers not supported");
2177 else if ((item_flags & l34m) != 0)
2178 return rte_flow_error_set(error, EINVAL,
2179 RTE_FLOW_ERROR_TYPE_ITEM, item,
2180 "VLAN cannot follow L3/L4 layer");
2182 mask = &rte_flow_item_vlan_mask;
2183 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2184 (const uint8_t *)&nic_mask,
2185 sizeof(struct rte_flow_item_vlan),
2186 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2189 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2190 struct mlx5_priv *priv = dev->data->dev_private;
2192 if (priv->vmwa_context) {
2194 * Non-NULL context means we have a virtual machine
2195 * and SR-IOV enabled, we have to create VLAN interface
2196 * to make hypervisor to setup E-Switch vport
2197 * context correctly. We avoid creating the multiple
2198 * VLAN interfaces, so we cannot support VLAN tag mask.
2200 return rte_flow_error_set(error, EINVAL,
2201 RTE_FLOW_ERROR_TYPE_ITEM,
2203 "VLAN tag mask is not"
2204 " supported in virtual"
2212 * GTP flags are contained in 1 byte of the format:
2213 * -------------------------------------------
2214 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2215 * |-----------------------------------------|
2216 * | value | Version | PT | Res | E | S | PN |
2217 * -------------------------------------------
2219 * Matching is supported only for GTP flags E, S, PN.
2221 #define MLX5_GTP_FLAGS_MASK 0x07
2224 * Validate GTP item.
2227 * Pointer to the rte_eth_dev structure.
2229 * Item specification.
2230 * @param[in] item_flags
2231 * Bit-fields that holds the items detected until now.
2233 * Pointer to error structure.
2236 * 0 on success, a negative errno value otherwise and rte_errno is set.
2239 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2240 const struct rte_flow_item *item,
2241 uint64_t item_flags,
2242 struct rte_flow_error *error)
2244 struct mlx5_priv *priv = dev->data->dev_private;
2245 const struct rte_flow_item_gtp *spec = item->spec;
2246 const struct rte_flow_item_gtp *mask = item->mask;
2247 const struct rte_flow_item_gtp nic_mask = {
2248 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2250 .teid = RTE_BE32(0xffffffff),
2253 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2254 return rte_flow_error_set(error, ENOTSUP,
2255 RTE_FLOW_ERROR_TYPE_ITEM, item,
2256 "GTP support is not enabled");
2257 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2258 return rte_flow_error_set(error, ENOTSUP,
2259 RTE_FLOW_ERROR_TYPE_ITEM, item,
2260 "multiple tunnel layers not"
2262 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2263 return rte_flow_error_set(error, EINVAL,
2264 RTE_FLOW_ERROR_TYPE_ITEM, item,
2265 "no outer UDP layer found");
2267 mask = &rte_flow_item_gtp_mask;
2268 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2269 return rte_flow_error_set(error, ENOTSUP,
2270 RTE_FLOW_ERROR_TYPE_ITEM, item,
2271 "Match is supported for GTP"
2273 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2274 (const uint8_t *)&nic_mask,
2275 sizeof(struct rte_flow_item_gtp),
2276 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2280 * Validate GTP PSC item.
2283 * Item specification.
2284 * @param[in] last_item
2285 * Previous validated item in the pattern items.
2286 * @param[in] gtp_item
2287 * Previous GTP item specification.
2289 * Pointer to flow attributes.
2291 * Pointer to error structure.
2294 * 0 on success, a negative errno value otherwise and rte_errno is set.
2297 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2299 const struct rte_flow_item *gtp_item,
2300 const struct rte_flow_attr *attr,
2301 struct rte_flow_error *error)
2303 const struct rte_flow_item_gtp *gtp_spec;
2304 const struct rte_flow_item_gtp *gtp_mask;
2305 const struct rte_flow_item_gtp_psc *spec;
2306 const struct rte_flow_item_gtp_psc *mask;
2307 const struct rte_flow_item_gtp_psc nic_mask = {
2312 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2313 return rte_flow_error_set
2314 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2315 "GTP PSC item must be preceded with GTP item");
2316 gtp_spec = gtp_item->spec;
2317 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2318 /* GTP spec and E flag is requested to match zero. */
2320 (gtp_mask->v_pt_rsv_flags &
2321 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2322 return rte_flow_error_set
2323 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2324 "GTP E flag must be 1 to match GTP PSC");
2325 /* Check the flow is not created in group zero. */
2326 if (!attr->transfer && !attr->group)
2327 return rte_flow_error_set
2328 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2329 "GTP PSC is not supported for group 0");
2330 /* GTP spec is here and E flag is requested to match zero. */
2334 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2335 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2336 return rte_flow_error_set
2337 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "PDU type should be smaller than 16");
2339 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2340 (const uint8_t *)&nic_mask,
2341 sizeof(struct rte_flow_item_gtp_psc),
2342 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2346 * Validate IPV4 item.
2347 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2348 * add specific validation of fragment_offset field,
2351 * Item specification.
2352 * @param[in] item_flags
2353 * Bit-fields that holds the items detected until now.
2355 * Pointer to error structure.
2358 * 0 on success, a negative errno value otherwise and rte_errno is set.
2361 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2362 uint64_t item_flags,
2364 uint16_t ether_type,
2365 struct rte_flow_error *error)
2368 const struct rte_flow_item_ipv4 *spec = item->spec;
2369 const struct rte_flow_item_ipv4 *last = item->last;
2370 const struct rte_flow_item_ipv4 *mask = item->mask;
2371 rte_be16_t fragment_offset_spec = 0;
2372 rte_be16_t fragment_offset_last = 0;
2373 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2375 .src_addr = RTE_BE32(0xffffffff),
2376 .dst_addr = RTE_BE32(0xffffffff),
2377 .type_of_service = 0xff,
2378 .fragment_offset = RTE_BE16(0xffff),
2379 .next_proto_id = 0xff,
2380 .time_to_live = 0xff,
2384 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2385 ether_type, &nic_ipv4_mask,
2386 MLX5_ITEM_RANGE_ACCEPTED, error);
2390 fragment_offset_spec = spec->hdr.fragment_offset &
2391 mask->hdr.fragment_offset;
2392 if (!fragment_offset_spec)
2395 * spec and mask are valid, enforce using full mask to make sure the
2396 * complete value is used correctly.
2398 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2399 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2400 return rte_flow_error_set(error, EINVAL,
2401 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2402 item, "must use full mask for"
2403 " fragment_offset");
2405 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2406 * indicating this is 1st fragment of fragmented packet.
2407 * This is not yet supported in MLX5, return appropriate error message.
2409 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2410 return rte_flow_error_set(error, ENOTSUP,
2411 RTE_FLOW_ERROR_TYPE_ITEM, item,
2412 "match on first fragment not "
2414 if (fragment_offset_spec && !last)
2415 return rte_flow_error_set(error, ENOTSUP,
2416 RTE_FLOW_ERROR_TYPE_ITEM, item,
2417 "specified value not supported");
2418 /* spec and last are valid, validate the specified range. */
2419 fragment_offset_last = last->hdr.fragment_offset &
2420 mask->hdr.fragment_offset;
2422 * Match on fragment_offset spec 0x2001 and last 0x3fff
2423 * means MF is 1 and frag-offset is > 0.
2424 * This packet is fragment 2nd and onward, excluding last.
2425 * This is not yet supported in MLX5, return appropriate
2428 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2429 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2432 last, "match on following "
2433 "fragments not supported");
2435 * Match on fragment_offset spec 0x0001 and last 0x1fff
2436 * means MF is 0 and frag-offset is > 0.
2437 * This packet is last fragment of fragmented packet.
2438 * This is not yet supported in MLX5, return appropriate
2441 if (fragment_offset_spec == RTE_BE16(1) &&
2442 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2443 return rte_flow_error_set(error, ENOTSUP,
2444 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2445 last, "match on last "
2446 "fragment not supported");
2448 * Match on fragment_offset spec 0x0001 and last 0x3fff
2449 * means MF and/or frag-offset is not 0.
2450 * This is a fragmented packet.
2451 * Other range values are invalid and rejected.
2453 if (!(fragment_offset_spec == RTE_BE16(1) &&
2454 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2455 return rte_flow_error_set(error, ENOTSUP,
2456 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2457 "specified range not supported");
2462 * Validate IPV6 fragment extension item.
2465 * Item specification.
2466 * @param[in] item_flags
2467 * Bit-fields that holds the items detected until now.
2469 * Pointer to error structure.
2472 * 0 on success, a negative errno value otherwise and rte_errno is set.
2475 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2476 uint64_t item_flags,
2477 struct rte_flow_error *error)
2479 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2480 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2481 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2482 rte_be16_t frag_data_spec = 0;
2483 rte_be16_t frag_data_last = 0;
2484 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2485 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2486 MLX5_FLOW_LAYER_OUTER_L4;
2488 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2490 .next_header = 0xff,
2491 .frag_data = RTE_BE16(0xffff),
2495 if (item_flags & l4m)
2496 return rte_flow_error_set(error, EINVAL,
2497 RTE_FLOW_ERROR_TYPE_ITEM, item,
2498 "ipv6 fragment extension item cannot "
2500 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2501 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2502 return rte_flow_error_set(error, EINVAL,
2503 RTE_FLOW_ERROR_TYPE_ITEM, item,
2504 "ipv6 fragment extension item must "
2505 "follow ipv6 item");
2507 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2508 if (!frag_data_spec)
2511 * spec and mask are valid, enforce using full mask to make sure the
2512 * complete value is used correctly.
2514 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2515 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2516 return rte_flow_error_set(error, EINVAL,
2517 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2518 item, "must use full mask for"
2521 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2522 * This is 1st fragment of fragmented packet.
2524 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2525 return rte_flow_error_set(error, ENOTSUP,
2526 RTE_FLOW_ERROR_TYPE_ITEM, item,
2527 "match on first fragment not "
2529 if (frag_data_spec && !last)
2530 return rte_flow_error_set(error, EINVAL,
2531 RTE_FLOW_ERROR_TYPE_ITEM, item,
2532 "specified value not supported");
2533 ret = mlx5_flow_item_acceptable
2534 (item, (const uint8_t *)mask,
2535 (const uint8_t *)&nic_mask,
2536 sizeof(struct rte_flow_item_ipv6_frag_ext),
2537 MLX5_ITEM_RANGE_ACCEPTED, error);
2540 /* spec and last are valid, validate the specified range. */
2541 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2543 * Match on frag_data spec 0x0009 and last 0xfff9
2544 * means M is 1 and frag-offset is > 0.
2545 * This packet is fragment 2nd and onward, excluding last.
2546 * This is not yet supported in MLX5, return appropriate
2549 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2550 RTE_IPV6_EHDR_MF_MASK) &&
2551 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2552 return rte_flow_error_set(error, ENOTSUP,
2553 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2554 last, "match on following "
2555 "fragments not supported");
2557 * Match on frag_data spec 0x0008 and last 0xfff8
2558 * means M is 0 and frag-offset is > 0.
2559 * This packet is last fragment of fragmented packet.
2560 * This is not yet supported in MLX5, return appropriate
2563 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2564 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2565 return rte_flow_error_set(error, ENOTSUP,
2566 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2567 last, "match on last "
2568 "fragment not supported");
2569 /* Other range values are invalid and rejected. */
2570 return rte_flow_error_set(error, EINVAL,
2571 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2572 "specified range not supported");
2576 * Validate the pop VLAN action.
2579 * Pointer to the rte_eth_dev structure.
2580 * @param[in] action_flags
2581 * Holds the actions detected until now.
2583 * Pointer to the pop vlan action.
2584 * @param[in] item_flags
2585 * The items found in this flow rule.
2587 * Pointer to flow attributes.
2589 * Pointer to error structure.
2592 * 0 on success, a negative errno value otherwise and rte_errno is set.
2595 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2596 uint64_t action_flags,
2597 const struct rte_flow_action *action,
2598 uint64_t item_flags,
2599 const struct rte_flow_attr *attr,
2600 struct rte_flow_error *error)
2602 const struct mlx5_priv *priv = dev->data->dev_private;
2606 if (!priv->sh->pop_vlan_action)
2607 return rte_flow_error_set(error, ENOTSUP,
2608 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2610 "pop vlan action is not supported");
2612 return rte_flow_error_set(error, ENOTSUP,
2613 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2615 "pop vlan action not supported for "
2617 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2618 return rte_flow_error_set(error, ENOTSUP,
2619 RTE_FLOW_ERROR_TYPE_ACTION, action,
2620 "no support for multiple VLAN "
2622 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2623 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2624 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2625 return rte_flow_error_set(error, ENOTSUP,
2626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2628 "cannot pop vlan after decap without "
2629 "match on inner vlan in the flow");
2630 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2631 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2632 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2633 return rte_flow_error_set(error, ENOTSUP,
2634 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2636 "cannot pop vlan without a "
2637 "match on (outer) vlan in the flow");
2638 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2639 return rte_flow_error_set(error, EINVAL,
2640 RTE_FLOW_ERROR_TYPE_ACTION, action,
2641 "wrong action order, port_id should "
2642 "be after pop VLAN action");
2643 if (!attr->transfer && priv->representor)
2644 return rte_flow_error_set(error, ENOTSUP,
2645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2646 "pop vlan action for VF representor "
2647 "not supported on NIC table");
2652 * Get VLAN default info from vlan match info.
2655 * the list of item specifications.
2657 * pointer VLAN info to fill to.
2660 * 0 on success, a negative errno value otherwise and rte_errno is set.
2663 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2664 struct rte_vlan_hdr *vlan)
2666 const struct rte_flow_item_vlan nic_mask = {
2667 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2668 MLX5DV_FLOW_VLAN_VID_MASK),
2669 .inner_type = RTE_BE16(0xffff),
2674 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2675 int type = items->type;
2677 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2678 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2681 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2682 const struct rte_flow_item_vlan *vlan_m = items->mask;
2683 const struct rte_flow_item_vlan *vlan_v = items->spec;
2685 /* If VLAN item in pattern doesn't contain data, return here. */
2690 /* Only full match values are accepted */
2691 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2692 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2693 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2695 rte_be_to_cpu_16(vlan_v->tci &
2696 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2698 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2699 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2700 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2702 rte_be_to_cpu_16(vlan_v->tci &
2703 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2705 if (vlan_m->inner_type == nic_mask.inner_type)
2706 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2707 vlan_m->inner_type);
2712 * Validate the push VLAN action.
2715 * Pointer to the rte_eth_dev structure.
2716 * @param[in] action_flags
2717 * Holds the actions detected until now.
2718 * @param[in] item_flags
2719 * The items found in this flow rule.
2721 * Pointer to the action structure.
2723 * Pointer to flow attributes
2725 * Pointer to error structure.
2728 * 0 on success, a negative errno value otherwise and rte_errno is set.
2731 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2732 uint64_t action_flags,
2733 const struct rte_flow_item_vlan *vlan_m,
2734 const struct rte_flow_action *action,
2735 const struct rte_flow_attr *attr,
2736 struct rte_flow_error *error)
2738 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2739 const struct mlx5_priv *priv = dev->data->dev_private;
2741 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2742 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2743 return rte_flow_error_set(error, EINVAL,
2744 RTE_FLOW_ERROR_TYPE_ACTION, action,
2745 "invalid vlan ethertype");
2746 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2747 return rte_flow_error_set(error, EINVAL,
2748 RTE_FLOW_ERROR_TYPE_ACTION, action,
2749 "wrong action order, port_id should "
2750 "be after push VLAN");
2751 if (!attr->transfer && priv->representor)
2752 return rte_flow_error_set(error, ENOTSUP,
2753 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2754 "push vlan action for VF representor "
2755 "not supported on NIC table");
2757 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2758 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2759 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2760 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2761 !(mlx5_flow_find_action
2762 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2763 return rte_flow_error_set(error, EINVAL,
2764 RTE_FLOW_ERROR_TYPE_ACTION, action,
2765 "not full match mask on VLAN PCP and "
2766 "there is no of_set_vlan_pcp action, "
2767 "push VLAN action cannot figure out "
2770 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2771 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2772 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2773 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2774 !(mlx5_flow_find_action
2775 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2776 return rte_flow_error_set(error, EINVAL,
2777 RTE_FLOW_ERROR_TYPE_ACTION, action,
2778 "not full match mask on VLAN VID and "
2779 "there is no of_set_vlan_vid action, "
2780 "push VLAN action cannot figure out "
2787 * Validate the set VLAN PCP.
2789 * @param[in] action_flags
2790 * Holds the actions detected until now.
2791 * @param[in] actions
2792 * Pointer to the list of actions remaining in the flow rule.
2794 * Pointer to error structure.
2797 * 0 on success, a negative errno value otherwise and rte_errno is set.
2800 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2801 const struct rte_flow_action actions[],
2802 struct rte_flow_error *error)
2804 const struct rte_flow_action *action = actions;
2805 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2807 if (conf->vlan_pcp > 7)
2808 return rte_flow_error_set(error, EINVAL,
2809 RTE_FLOW_ERROR_TYPE_ACTION, action,
2810 "VLAN PCP value is too big");
2811 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2812 return rte_flow_error_set(error, ENOTSUP,
2813 RTE_FLOW_ERROR_TYPE_ACTION, action,
2814 "set VLAN PCP action must follow "
2815 "the push VLAN action");
2816 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2817 return rte_flow_error_set(error, ENOTSUP,
2818 RTE_FLOW_ERROR_TYPE_ACTION, action,
2819 "Multiple VLAN PCP modification are "
2821 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2822 return rte_flow_error_set(error, EINVAL,
2823 RTE_FLOW_ERROR_TYPE_ACTION, action,
2824 "wrong action order, port_id should "
2825 "be after set VLAN PCP");
2830 * Validate the set VLAN VID.
2832 * @param[in] item_flags
2833 * Holds the items detected in this rule.
2834 * @param[in] action_flags
2835 * Holds the actions detected until now.
2836 * @param[in] actions
2837 * Pointer to the list of actions remaining in the flow rule.
2839 * Pointer to error structure.
2842 * 0 on success, a negative errno value otherwise and rte_errno is set.
2845 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2846 uint64_t action_flags,
2847 const struct rte_flow_action actions[],
2848 struct rte_flow_error *error)
2850 const struct rte_flow_action *action = actions;
2851 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2853 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2854 return rte_flow_error_set(error, EINVAL,
2855 RTE_FLOW_ERROR_TYPE_ACTION, action,
2856 "VLAN VID value is too big");
2857 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2858 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2859 return rte_flow_error_set(error, ENOTSUP,
2860 RTE_FLOW_ERROR_TYPE_ACTION, action,
2861 "set VLAN VID action must follow push"
2862 " VLAN action or match on VLAN item");
2863 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2864 return rte_flow_error_set(error, ENOTSUP,
2865 RTE_FLOW_ERROR_TYPE_ACTION, action,
2866 "Multiple VLAN VID modifications are "
2868 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2869 return rte_flow_error_set(error, EINVAL,
2870 RTE_FLOW_ERROR_TYPE_ACTION, action,
2871 "wrong action order, port_id should "
2872 "be after set VLAN VID");
2877 * Validate the FLAG action.
2880 * Pointer to the rte_eth_dev structure.
2881 * @param[in] action_flags
2882 * Holds the actions detected until now.
2884 * Pointer to flow attributes
2886 * Pointer to error structure.
2889 * 0 on success, a negative errno value otherwise and rte_errno is set.
2892 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2893 uint64_t action_flags,
2894 const struct rte_flow_attr *attr,
2895 struct rte_flow_error *error)
2897 struct mlx5_priv *priv = dev->data->dev_private;
2898 struct mlx5_dev_config *config = &priv->config;
2901 /* Fall back if no extended metadata register support. */
2902 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2903 return mlx5_flow_validate_action_flag(action_flags, attr,
2905 /* Extensive metadata mode requires registers. */
2906 if (!mlx5_flow_ext_mreg_supported(dev))
2907 return rte_flow_error_set(error, ENOTSUP,
2908 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2909 "no metadata registers "
2910 "to support flag action");
2911 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2912 return rte_flow_error_set(error, ENOTSUP,
2913 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2914 "extended metadata register"
2915 " isn't available");
2916 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2919 MLX5_ASSERT(ret > 0);
2920 if (action_flags & MLX5_FLOW_ACTION_MARK)
2921 return rte_flow_error_set(error, EINVAL,
2922 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2923 "can't mark and flag in same flow");
2924 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2925 return rte_flow_error_set(error, EINVAL,
2926 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2928 " actions in same flow");
2933 * Validate MARK action.
2936 * Pointer to the rte_eth_dev structure.
2938 * Pointer to action.
2939 * @param[in] action_flags
2940 * Holds the actions detected until now.
2942 * Pointer to flow attributes
2944 * Pointer to error structure.
2947 * 0 on success, a negative errno value otherwise and rte_errno is set.
2950 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2951 const struct rte_flow_action *action,
2952 uint64_t action_flags,
2953 const struct rte_flow_attr *attr,
2954 struct rte_flow_error *error)
2956 struct mlx5_priv *priv = dev->data->dev_private;
2957 struct mlx5_dev_config *config = &priv->config;
2958 const struct rte_flow_action_mark *mark = action->conf;
2961 if (is_tunnel_offload_active(dev))
2962 return rte_flow_error_set(error, ENOTSUP,
2963 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2965 "if tunnel offload active");
2966 /* Fall back if no extended metadata register support. */
2967 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2968 return mlx5_flow_validate_action_mark(action, action_flags,
2970 /* Extensive metadata mode requires registers. */
2971 if (!mlx5_flow_ext_mreg_supported(dev))
2972 return rte_flow_error_set(error, ENOTSUP,
2973 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2974 "no metadata registers "
2975 "to support mark action");
2976 if (!priv->sh->dv_mark_mask)
2977 return rte_flow_error_set(error, ENOTSUP,
2978 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2979 "extended metadata register"
2980 " isn't available");
2981 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2984 MLX5_ASSERT(ret > 0);
2986 return rte_flow_error_set(error, EINVAL,
2987 RTE_FLOW_ERROR_TYPE_ACTION, action,
2988 "configuration cannot be null");
2989 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2990 return rte_flow_error_set(error, EINVAL,
2991 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2993 "mark id exceeds the limit");
2994 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2995 return rte_flow_error_set(error, EINVAL,
2996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2997 "can't flag and mark in same flow");
2998 if (action_flags & MLX5_FLOW_ACTION_MARK)
2999 return rte_flow_error_set(error, EINVAL,
3000 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3001 "can't have 2 mark actions in same"
3007 * Validate SET_META action.
3010 * Pointer to the rte_eth_dev structure.
3012 * Pointer to the action structure.
3013 * @param[in] action_flags
3014 * Holds the actions detected until now.
3016 * Pointer to flow attributes
3018 * Pointer to error structure.
3021 * 0 on success, a negative errno value otherwise and rte_errno is set.
3024 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3025 const struct rte_flow_action *action,
3026 uint64_t action_flags __rte_unused,
3027 const struct rte_flow_attr *attr,
3028 struct rte_flow_error *error)
3030 const struct rte_flow_action_set_meta *conf;
3031 uint32_t nic_mask = UINT32_MAX;
3034 if (!mlx5_flow_ext_mreg_supported(dev))
3035 return rte_flow_error_set(error, ENOTSUP,
3036 RTE_FLOW_ERROR_TYPE_ACTION, action,
3037 "extended metadata register"
3038 " isn't supported");
3039 reg = flow_dv_get_metadata_reg(dev, attr, error);
3043 return rte_flow_error_set(error, ENOTSUP,
3044 RTE_FLOW_ERROR_TYPE_ACTION, action,
3045 "unavalable extended metadata register");
3046 if (reg != REG_A && reg != REG_B) {
3047 struct mlx5_priv *priv = dev->data->dev_private;
3049 nic_mask = priv->sh->dv_meta_mask;
3051 if (!(action->conf))
3052 return rte_flow_error_set(error, EINVAL,
3053 RTE_FLOW_ERROR_TYPE_ACTION, action,
3054 "configuration cannot be null");
3055 conf = (const struct rte_flow_action_set_meta *)action->conf;
3057 return rte_flow_error_set(error, EINVAL,
3058 RTE_FLOW_ERROR_TYPE_ACTION, action,
3059 "zero mask doesn't have any effect");
3060 if (conf->mask & ~nic_mask)
3061 return rte_flow_error_set(error, EINVAL,
3062 RTE_FLOW_ERROR_TYPE_ACTION, action,
3063 "meta data must be within reg C0");
3068 * Validate SET_TAG action.
3071 * Pointer to the rte_eth_dev structure.
3073 * Pointer to the action structure.
3074 * @param[in] action_flags
3075 * Holds the actions detected until now.
3077 * Pointer to flow attributes
3079 * Pointer to error structure.
3082 * 0 on success, a negative errno value otherwise and rte_errno is set.
3085 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3086 const struct rte_flow_action *action,
3087 uint64_t action_flags,
3088 const struct rte_flow_attr *attr,
3089 struct rte_flow_error *error)
3091 const struct rte_flow_action_set_tag *conf;
3092 const uint64_t terminal_action_flags =
3093 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3094 MLX5_FLOW_ACTION_RSS;
3097 if (!mlx5_flow_ext_mreg_supported(dev))
3098 return rte_flow_error_set(error, ENOTSUP,
3099 RTE_FLOW_ERROR_TYPE_ACTION, action,
3100 "extensive metadata register"
3101 " isn't supported");
3102 if (!(action->conf))
3103 return rte_flow_error_set(error, EINVAL,
3104 RTE_FLOW_ERROR_TYPE_ACTION, action,
3105 "configuration cannot be null");
3106 conf = (const struct rte_flow_action_set_tag *)action->conf;
3108 return rte_flow_error_set(error, EINVAL,
3109 RTE_FLOW_ERROR_TYPE_ACTION, action,
3110 "zero mask doesn't have any effect");
3111 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3114 if (!attr->transfer && attr->ingress &&
3115 (action_flags & terminal_action_flags))
3116 return rte_flow_error_set(error, EINVAL,
3117 RTE_FLOW_ERROR_TYPE_ACTION, action,
3118 "set_tag has no effect"
3119 " with terminal actions");
3124 * Validate count action.
3127 * Pointer to rte_eth_dev structure.
3129 * Pointer to the action structure.
3130 * @param[in] action_flags
3131 * Holds the actions detected until now.
3133 * Pointer to error structure.
3136 * 0 on success, a negative errno value otherwise and rte_errno is set.
3139 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3140 const struct rte_flow_action *action,
3141 uint64_t action_flags,
3142 struct rte_flow_error *error)
3144 struct mlx5_priv *priv = dev->data->dev_private;
3145 const struct rte_flow_action_count *count;
3147 if (!priv->config.devx)
3149 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3150 return rte_flow_error_set(error, EINVAL,
3151 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3152 "duplicate count actions set");
3153 count = (const struct rte_flow_action_count *)action->conf;
3154 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3155 !priv->sh->flow_hit_aso_en)
3156 return rte_flow_error_set(error, EINVAL,
3157 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3158 "old age and shared count combination is not supported");
3159 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3163 return rte_flow_error_set
3165 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3167 "count action not supported");
3171 * Validate the L2 encap action.
3174 * Pointer to the rte_eth_dev structure.
3175 * @param[in] action_flags
3176 * Holds the actions detected until now.
3178 * Pointer to the action structure.
3180 * Pointer to flow attributes.
3182 * Pointer to error structure.
3185 * 0 on success, a negative errno value otherwise and rte_errno is set.
3188 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3189 uint64_t action_flags,
3190 const struct rte_flow_action *action,
3191 const struct rte_flow_attr *attr,
3192 struct rte_flow_error *error)
3194 const struct mlx5_priv *priv = dev->data->dev_private;
3196 if (!(action->conf))
3197 return rte_flow_error_set(error, EINVAL,
3198 RTE_FLOW_ERROR_TYPE_ACTION, action,
3199 "configuration cannot be null");
3200 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3201 return rte_flow_error_set(error, EINVAL,
3202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3203 "can only have a single encap action "
3205 if (!attr->transfer && priv->representor)
3206 return rte_flow_error_set(error, ENOTSUP,
3207 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3208 "encap action for VF representor "
3209 "not supported on NIC table");
3214 * Validate a decap action.
3217 * Pointer to the rte_eth_dev structure.
3218 * @param[in] action_flags
3219 * Holds the actions detected until now.
3221 * Pointer to the action structure.
3222 * @param[in] item_flags
3223 * Holds the items detected.
3225 * Pointer to flow attributes
3227 * Pointer to error structure.
3230 * 0 on success, a negative errno value otherwise and rte_errno is set.
3233 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3234 uint64_t action_flags,
3235 const struct rte_flow_action *action,
3236 const uint64_t item_flags,
3237 const struct rte_flow_attr *attr,
3238 struct rte_flow_error *error)
3240 const struct mlx5_priv *priv = dev->data->dev_private;
3242 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3243 !priv->config.decap_en)
3244 return rte_flow_error_set(error, ENOTSUP,
3245 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3246 "decap is not enabled");
3247 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3248 return rte_flow_error_set(error, ENOTSUP,
3249 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3251 MLX5_FLOW_ACTION_DECAP ? "can only "
3252 "have a single decap action" : "decap "
3253 "after encap is not supported");
3254 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3255 return rte_flow_error_set(error, EINVAL,
3256 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3257 "can't have decap action after"
3260 return rte_flow_error_set(error, ENOTSUP,
3261 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3263 "decap action not supported for "
3265 if (!attr->transfer && priv->representor)
3266 return rte_flow_error_set(error, ENOTSUP,
3267 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3268 "decap action for VF representor "
3269 "not supported on NIC table");
3270 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3271 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3272 return rte_flow_error_set(error, ENOTSUP,
3273 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3274 "VXLAN item should be present for VXLAN decap");
3278 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3281 * Validate the raw encap and decap actions.
3284 * Pointer to the rte_eth_dev structure.
3286 * Pointer to the decap action.
3288 * Pointer to the encap action.
3290 * Pointer to flow attributes
3291 * @param[in/out] action_flags
3292 * Holds the actions detected until now.
3293 * @param[out] actions_n
3294 * pointer to the number of actions counter.
3296 * Pointer to the action structure.
3297 * @param[in] item_flags
3298 * Holds the items detected.
3300 * Pointer to error structure.
3303 * 0 on success, a negative errno value otherwise and rte_errno is set.
3306 flow_dv_validate_action_raw_encap_decap
3307 (struct rte_eth_dev *dev,
3308 const struct rte_flow_action_raw_decap *decap,
3309 const struct rte_flow_action_raw_encap *encap,
3310 const struct rte_flow_attr *attr, uint64_t *action_flags,
3311 int *actions_n, const struct rte_flow_action *action,
3312 uint64_t item_flags, struct rte_flow_error *error)
3314 const struct mlx5_priv *priv = dev->data->dev_private;
3317 if (encap && (!encap->size || !encap->data))
3318 return rte_flow_error_set(error, EINVAL,
3319 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3320 "raw encap data cannot be empty");
3321 if (decap && encap) {
3322 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3323 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3326 else if (encap->size <=
3327 MLX5_ENCAPSULATION_DECISION_SIZE &&
3329 MLX5_ENCAPSULATION_DECISION_SIZE)
3332 else if (encap->size >
3333 MLX5_ENCAPSULATION_DECISION_SIZE &&
3335 MLX5_ENCAPSULATION_DECISION_SIZE)
3336 /* 2 L2 actions: encap and decap. */
3339 return rte_flow_error_set(error,
3341 RTE_FLOW_ERROR_TYPE_ACTION,
3342 NULL, "unsupported too small "
3343 "raw decap and too small raw "
3344 "encap combination");
3347 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3348 item_flags, attr, error);
3351 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3355 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3356 return rte_flow_error_set(error, ENOTSUP,
3357 RTE_FLOW_ERROR_TYPE_ACTION,
3359 "small raw encap size");
3360 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION,
3364 "more than one encap action");
3365 if (!attr->transfer && priv->representor)
3366 return rte_flow_error_set
3368 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3369 "encap action for VF representor "
3370 "not supported on NIC table");
3371 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3378 * Match encap_decap resource.
3381 * Pointer to the hash list.
3383 * Pointer to exist resource entry object.
3385 * Key of the new entry.
3387 * Pointer to new encap_decap resource.
3390 * 0 on matching, none-zero otherwise.
3393 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3394 struct mlx5_hlist_entry *entry,
3395 uint64_t key __rte_unused, void *cb_ctx)
3397 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3398 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3399 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3401 cache_resource = container_of(entry,
3402 struct mlx5_flow_dv_encap_decap_resource,
3404 if (resource->reformat_type == cache_resource->reformat_type &&
3405 resource->ft_type == cache_resource->ft_type &&
3406 resource->flags == cache_resource->flags &&
3407 resource->size == cache_resource->size &&
3408 !memcmp((const void *)resource->buf,
3409 (const void *)cache_resource->buf,
3416 * Allocate encap_decap resource.
3419 * Pointer to the hash list.
3421 * Pointer to exist resource entry object.
3423 * Pointer to new encap_decap resource.
3426 * 0 on matching, none-zero otherwise.
3428 struct mlx5_hlist_entry *
3429 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3430 uint64_t key __rte_unused,
3433 struct mlx5_dev_ctx_shared *sh = list->ctx;
3434 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3435 struct mlx5dv_dr_domain *domain;
3436 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3437 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3441 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3442 domain = sh->fdb_domain;
3443 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3444 domain = sh->rx_domain;
3446 domain = sh->tx_domain;
3447 /* Register new encap/decap resource. */
3448 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3450 if (!cache_resource) {
3451 rte_flow_error_set(ctx->error, ENOMEM,
3452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3453 "cannot allocate resource memory");
3456 *cache_resource = *resource;
3457 cache_resource->idx = idx;
3458 ret = mlx5_flow_os_create_flow_action_packet_reformat
3459 (sh->ctx, domain, cache_resource,
3460 &cache_resource->action);
3462 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3463 rte_flow_error_set(ctx->error, ENOMEM,
3464 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3465 NULL, "cannot create action");
3469 return &cache_resource->entry;
3473 * Find existing encap/decap resource or create and register a new one.
3475 * @param[in, out] dev
3476 * Pointer to rte_eth_dev structure.
3477 * @param[in, out] resource
3478 * Pointer to encap/decap resource.
3479 * @parm[in, out] dev_flow
3480 * Pointer to the dev_flow.
3482 * pointer to error structure.
3485 * 0 on success otherwise -errno and errno is set.
3488 flow_dv_encap_decap_resource_register
3489 (struct rte_eth_dev *dev,
3490 struct mlx5_flow_dv_encap_decap_resource *resource,
3491 struct mlx5_flow *dev_flow,
3492 struct rte_flow_error *error)
3494 struct mlx5_priv *priv = dev->data->dev_private;
3495 struct mlx5_dev_ctx_shared *sh = priv->sh;
3496 struct mlx5_hlist_entry *entry;
3500 uint32_t refmt_type:8;
3502 * Header reformat actions can be shared between
3503 * non-root tables. One bit to indicate non-root
3507 uint32_t reserve:15;
3510 } encap_decap_key = {
3512 .ft_type = resource->ft_type,
3513 .refmt_type = resource->reformat_type,
3514 .is_root = !!dev_flow->dv.group,
3518 struct mlx5_flow_cb_ctx ctx = {
3524 resource->flags = dev_flow->dv.group ? 0 : 1;
3525 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3526 sizeof(encap_decap_key.v32), 0);
3527 if (resource->reformat_type !=
3528 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3530 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3531 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3534 resource = container_of(entry, typeof(*resource), entry);
3535 dev_flow->dv.encap_decap = resource;
3536 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3541 * Find existing table jump resource or create and register a new one.
3543 * @param[in, out] dev
3544 * Pointer to rte_eth_dev structure.
3545 * @param[in, out] tbl
3546 * Pointer to flow table resource.
3547 * @parm[in, out] dev_flow
3548 * Pointer to the dev_flow.
3550 * pointer to error structure.
3553 * 0 on success otherwise -errno and errno is set.
3556 flow_dv_jump_tbl_resource_register
3557 (struct rte_eth_dev *dev __rte_unused,
3558 struct mlx5_flow_tbl_resource *tbl,
3559 struct mlx5_flow *dev_flow,
3560 struct rte_flow_error *error __rte_unused)
3562 struct mlx5_flow_tbl_data_entry *tbl_data =
3563 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3566 MLX5_ASSERT(tbl_data->jump.action);
3567 dev_flow->handle->rix_jump = tbl_data->idx;
3568 dev_flow->dv.jump = &tbl_data->jump;
3573 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3574 struct mlx5_cache_entry *entry, void *cb_ctx)
3576 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3577 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3578 struct mlx5_flow_dv_port_id_action_resource *res =
3579 container_of(entry, typeof(*res), entry);
3581 return ref->port_id != res->port_id;
3584 struct mlx5_cache_entry *
3585 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3586 struct mlx5_cache_entry *entry __rte_unused,
3589 struct mlx5_dev_ctx_shared *sh = list->ctx;
3590 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3591 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3592 struct mlx5_flow_dv_port_id_action_resource *cache;
3596 /* Register new port id action resource. */
3597 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3599 rte_flow_error_set(ctx->error, ENOMEM,
3600 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3601 "cannot allocate port_id action cache memory");
3605 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3609 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3610 rte_flow_error_set(ctx->error, ENOMEM,
3611 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3612 "cannot create action");
3615 return &cache->entry;
3619 * Find existing table port ID resource or create and register a new one.
3621 * @param[in, out] dev
3622 * Pointer to rte_eth_dev structure.
3623 * @param[in, out] resource
3624 * Pointer to port ID action resource.
3625 * @parm[in, out] dev_flow
3626 * Pointer to the dev_flow.
3628 * pointer to error structure.
3631 * 0 on success otherwise -errno and errno is set.
3634 flow_dv_port_id_action_resource_register
3635 (struct rte_eth_dev *dev,
3636 struct mlx5_flow_dv_port_id_action_resource *resource,
3637 struct mlx5_flow *dev_flow,
3638 struct rte_flow_error *error)
3640 struct mlx5_priv *priv = dev->data->dev_private;
3641 struct mlx5_cache_entry *entry;
3642 struct mlx5_flow_dv_port_id_action_resource *cache;
3643 struct mlx5_flow_cb_ctx ctx = {
3648 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3651 cache = container_of(entry, typeof(*cache), entry);
3652 dev_flow->dv.port_id_action = cache;
3653 dev_flow->handle->rix_port_id_action = cache->idx;
3658 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3659 struct mlx5_cache_entry *entry, void *cb_ctx)
3661 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3662 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3663 struct mlx5_flow_dv_push_vlan_action_resource *res =
3664 container_of(entry, typeof(*res), entry);
3666 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3669 struct mlx5_cache_entry *
3670 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3671 struct mlx5_cache_entry *entry __rte_unused,
3674 struct mlx5_dev_ctx_shared *sh = list->ctx;
3675 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3676 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3677 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3678 struct mlx5dv_dr_domain *domain;
3682 /* Register new port id action resource. */
3683 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3685 rte_flow_error_set(ctx->error, ENOMEM,
3686 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3687 "cannot allocate push_vlan action cache memory");
3691 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3692 domain = sh->fdb_domain;
3693 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3694 domain = sh->rx_domain;
3696 domain = sh->tx_domain;
3697 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3700 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3701 rte_flow_error_set(ctx->error, ENOMEM,
3702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3703 "cannot create push vlan action");
3706 return &cache->entry;
3710 * Find existing push vlan resource or create and register a new one.
3712 * @param [in, out] dev
3713 * Pointer to rte_eth_dev structure.
3714 * @param[in, out] resource
3715 * Pointer to port ID action resource.
3716 * @parm[in, out] dev_flow
3717 * Pointer to the dev_flow.
3719 * pointer to error structure.
3722 * 0 on success otherwise -errno and errno is set.
3725 flow_dv_push_vlan_action_resource_register
3726 (struct rte_eth_dev *dev,
3727 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3728 struct mlx5_flow *dev_flow,
3729 struct rte_flow_error *error)
3731 struct mlx5_priv *priv = dev->data->dev_private;
3732 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3733 struct mlx5_cache_entry *entry;
3734 struct mlx5_flow_cb_ctx ctx = {
3739 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3742 cache = container_of(entry, typeof(*cache), entry);
3744 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3745 dev_flow->dv.push_vlan_res = cache;
3750 * Get the size of specific rte_flow_item_type hdr size
3752 * @param[in] item_type
3753 * Tested rte_flow_item_type.
3756 * sizeof struct item_type, 0 if void or irrelevant.
3759 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3763 switch (item_type) {
3764 case RTE_FLOW_ITEM_TYPE_ETH:
3765 retval = sizeof(struct rte_ether_hdr);
3767 case RTE_FLOW_ITEM_TYPE_VLAN:
3768 retval = sizeof(struct rte_vlan_hdr);
3770 case RTE_FLOW_ITEM_TYPE_IPV4:
3771 retval = sizeof(struct rte_ipv4_hdr);
3773 case RTE_FLOW_ITEM_TYPE_IPV6:
3774 retval = sizeof(struct rte_ipv6_hdr);
3776 case RTE_FLOW_ITEM_TYPE_UDP:
3777 retval = sizeof(struct rte_udp_hdr);
3779 case RTE_FLOW_ITEM_TYPE_TCP:
3780 retval = sizeof(struct rte_tcp_hdr);
3782 case RTE_FLOW_ITEM_TYPE_VXLAN:
3783 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3784 retval = sizeof(struct rte_vxlan_hdr);
3786 case RTE_FLOW_ITEM_TYPE_GRE:
3787 case RTE_FLOW_ITEM_TYPE_NVGRE:
3788 retval = sizeof(struct rte_gre_hdr);
3790 case RTE_FLOW_ITEM_TYPE_MPLS:
3791 retval = sizeof(struct rte_mpls_hdr);
3793 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3801 #define MLX5_ENCAP_IPV4_VERSION 0x40
3802 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3803 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3804 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3805 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3806 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3807 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3810 * Convert the encap action data from list of rte_flow_item to raw buffer
3813 * Pointer to rte_flow_item objects list.
3815 * Pointer to the output buffer.
3817 * Pointer to the output buffer size.
3819 * Pointer to the error structure.
3822 * 0 on success, a negative errno value otherwise and rte_errno is set.
3825 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3826 size_t *size, struct rte_flow_error *error)
3828 struct rte_ether_hdr *eth = NULL;
3829 struct rte_vlan_hdr *vlan = NULL;
3830 struct rte_ipv4_hdr *ipv4 = NULL;
3831 struct rte_ipv6_hdr *ipv6 = NULL;
3832 struct rte_udp_hdr *udp = NULL;
3833 struct rte_vxlan_hdr *vxlan = NULL;
3834 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3835 struct rte_gre_hdr *gre = NULL;
3837 size_t temp_size = 0;
3840 return rte_flow_error_set(error, EINVAL,
3841 RTE_FLOW_ERROR_TYPE_ACTION,
3842 NULL, "invalid empty data");
3843 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3844 len = flow_dv_get_item_hdr_len(items->type);
3845 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3846 return rte_flow_error_set(error, EINVAL,
3847 RTE_FLOW_ERROR_TYPE_ACTION,
3848 (void *)items->type,
3849 "items total size is too big"
3850 " for encap action");
3851 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3852 switch (items->type) {
3853 case RTE_FLOW_ITEM_TYPE_ETH:
3854 eth = (struct rte_ether_hdr *)&buf[temp_size];
3856 case RTE_FLOW_ITEM_TYPE_VLAN:
3857 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3859 return rte_flow_error_set(error, EINVAL,
3860 RTE_FLOW_ERROR_TYPE_ACTION,
3861 (void *)items->type,
3862 "eth header not found");
3863 if (!eth->ether_type)
3864 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3866 case RTE_FLOW_ITEM_TYPE_IPV4:
3867 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3869 return rte_flow_error_set(error, EINVAL,
3870 RTE_FLOW_ERROR_TYPE_ACTION,
3871 (void *)items->type,
3872 "neither eth nor vlan"
3874 if (vlan && !vlan->eth_proto)
3875 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3876 else if (eth && !eth->ether_type)
3877 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3878 if (!ipv4->version_ihl)
3879 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3880 MLX5_ENCAP_IPV4_IHL_MIN;
3881 if (!ipv4->time_to_live)
3882 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3884 case RTE_FLOW_ITEM_TYPE_IPV6:
3885 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3887 return rte_flow_error_set(error, EINVAL,
3888 RTE_FLOW_ERROR_TYPE_ACTION,
3889 (void *)items->type,
3890 "neither eth nor vlan"
3892 if (vlan && !vlan->eth_proto)
3893 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3894 else if (eth && !eth->ether_type)
3895 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3896 if (!ipv6->vtc_flow)
3898 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3899 if (!ipv6->hop_limits)
3900 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3902 case RTE_FLOW_ITEM_TYPE_UDP:
3903 udp = (struct rte_udp_hdr *)&buf[temp_size];
3905 return rte_flow_error_set(error, EINVAL,
3906 RTE_FLOW_ERROR_TYPE_ACTION,
3907 (void *)items->type,
3908 "ip header not found");
3909 if (ipv4 && !ipv4->next_proto_id)
3910 ipv4->next_proto_id = IPPROTO_UDP;
3911 else if (ipv6 && !ipv6->proto)
3912 ipv6->proto = IPPROTO_UDP;
3914 case RTE_FLOW_ITEM_TYPE_VXLAN:
3915 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3917 return rte_flow_error_set(error, EINVAL,
3918 RTE_FLOW_ERROR_TYPE_ACTION,
3919 (void *)items->type,
3920 "udp header not found");
3922 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3923 if (!vxlan->vx_flags)
3925 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3927 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3928 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3930 return rte_flow_error_set(error, EINVAL,
3931 RTE_FLOW_ERROR_TYPE_ACTION,
3932 (void *)items->type,
3933 "udp header not found");
3934 if (!vxlan_gpe->proto)
3935 return rte_flow_error_set(error, EINVAL,
3936 RTE_FLOW_ERROR_TYPE_ACTION,
3937 (void *)items->type,
3938 "next protocol not found");
3941 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3942 if (!vxlan_gpe->vx_flags)
3943 vxlan_gpe->vx_flags =
3944 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3946 case RTE_FLOW_ITEM_TYPE_GRE:
3947 case RTE_FLOW_ITEM_TYPE_NVGRE:
3948 gre = (struct rte_gre_hdr *)&buf[temp_size];
3950 return rte_flow_error_set(error, EINVAL,
3951 RTE_FLOW_ERROR_TYPE_ACTION,
3952 (void *)items->type,
3953 "next protocol not found");
3955 return rte_flow_error_set(error, EINVAL,
3956 RTE_FLOW_ERROR_TYPE_ACTION,
3957 (void *)items->type,
3958 "ip header not found");
3959 if (ipv4 && !ipv4->next_proto_id)
3960 ipv4->next_proto_id = IPPROTO_GRE;
3961 else if (ipv6 && !ipv6->proto)
3962 ipv6->proto = IPPROTO_GRE;
3964 case RTE_FLOW_ITEM_TYPE_VOID:
3967 return rte_flow_error_set(error, EINVAL,
3968 RTE_FLOW_ERROR_TYPE_ACTION,
3969 (void *)items->type,
3970 "unsupported item type");
3980 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3982 struct rte_ether_hdr *eth = NULL;
3983 struct rte_vlan_hdr *vlan = NULL;
3984 struct rte_ipv6_hdr *ipv6 = NULL;
3985 struct rte_udp_hdr *udp = NULL;
3989 eth = (struct rte_ether_hdr *)data;
3990 next_hdr = (char *)(eth + 1);
3991 proto = RTE_BE16(eth->ether_type);
3994 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3995 vlan = (struct rte_vlan_hdr *)next_hdr;
3996 proto = RTE_BE16(vlan->eth_proto);
3997 next_hdr += sizeof(struct rte_vlan_hdr);
4000 /* HW calculates IPv4 csum. no need to proceed */
4001 if (proto == RTE_ETHER_TYPE_IPV4)
4004 /* non IPv4/IPv6 header. not supported */
4005 if (proto != RTE_ETHER_TYPE_IPV6) {
4006 return rte_flow_error_set(error, ENOTSUP,
4007 RTE_FLOW_ERROR_TYPE_ACTION,
4008 NULL, "Cannot offload non IPv4/IPv6");
4011 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4013 /* ignore non UDP */
4014 if (ipv6->proto != IPPROTO_UDP)
4017 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4018 udp->dgram_cksum = 0;
4024 * Convert L2 encap action to DV specification.
4027 * Pointer to rte_eth_dev structure.
4029 * Pointer to action structure.
4030 * @param[in, out] dev_flow
4031 * Pointer to the mlx5_flow.
4032 * @param[in] transfer
4033 * Mark if the flow is E-Switch flow.
4035 * Pointer to the error structure.
4038 * 0 on success, a negative errno value otherwise and rte_errno is set.
4041 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4042 const struct rte_flow_action *action,
4043 struct mlx5_flow *dev_flow,
4045 struct rte_flow_error *error)
4047 const struct rte_flow_item *encap_data;
4048 const struct rte_flow_action_raw_encap *raw_encap_data;
4049 struct mlx5_flow_dv_encap_decap_resource res = {
4051 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4052 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4053 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4056 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4058 (const struct rte_flow_action_raw_encap *)action->conf;
4059 res.size = raw_encap_data->size;
4060 memcpy(res.buf, raw_encap_data->data, res.size);
4062 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4064 ((const struct rte_flow_action_vxlan_encap *)
4065 action->conf)->definition;
4068 ((const struct rte_flow_action_nvgre_encap *)
4069 action->conf)->definition;
4070 if (flow_dv_convert_encap_data(encap_data, res.buf,
4074 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4076 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4077 return rte_flow_error_set(error, EINVAL,
4078 RTE_FLOW_ERROR_TYPE_ACTION,
4079 NULL, "can't create L2 encap action");
4084 * Convert L2 decap action to DV specification.
4087 * Pointer to rte_eth_dev structure.
4088 * @param[in, out] dev_flow
4089 * Pointer to the mlx5_flow.
4090 * @param[in] transfer
4091 * Mark if the flow is E-Switch flow.
4093 * Pointer to the error structure.
4096 * 0 on success, a negative errno value otherwise and rte_errno is set.
4099 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4100 struct mlx5_flow *dev_flow,
4102 struct rte_flow_error *error)
4104 struct mlx5_flow_dv_encap_decap_resource res = {
4107 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4108 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4109 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4112 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4113 return rte_flow_error_set(error, EINVAL,
4114 RTE_FLOW_ERROR_TYPE_ACTION,
4115 NULL, "can't create L2 decap action");
4120 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4123 * Pointer to rte_eth_dev structure.
4125 * Pointer to action structure.
4126 * @param[in, out] dev_flow
4127 * Pointer to the mlx5_flow.
4129 * Pointer to the flow attributes.
4131 * Pointer to the error structure.
4134 * 0 on success, a negative errno value otherwise and rte_errno is set.
4137 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4138 const struct rte_flow_action *action,
4139 struct mlx5_flow *dev_flow,
4140 const struct rte_flow_attr *attr,
4141 struct rte_flow_error *error)
4143 const struct rte_flow_action_raw_encap *encap_data;
4144 struct mlx5_flow_dv_encap_decap_resource res;
4146 memset(&res, 0, sizeof(res));
4147 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4148 res.size = encap_data->size;
4149 memcpy(res.buf, encap_data->data, res.size);
4150 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4151 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4152 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4154 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4156 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4157 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4158 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4159 return rte_flow_error_set(error, EINVAL,
4160 RTE_FLOW_ERROR_TYPE_ACTION,
4161 NULL, "can't create encap action");
4166 * Create action push VLAN.
4169 * Pointer to rte_eth_dev structure.
4171 * Pointer to the flow attributes.
4173 * Pointer to the vlan to push to the Ethernet header.
4174 * @param[in, out] dev_flow
4175 * Pointer to the mlx5_flow.
4177 * Pointer to the error structure.
4180 * 0 on success, a negative errno value otherwise and rte_errno is set.
4183 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4184 const struct rte_flow_attr *attr,
4185 const struct rte_vlan_hdr *vlan,
4186 struct mlx5_flow *dev_flow,
4187 struct rte_flow_error *error)
4189 struct mlx5_flow_dv_push_vlan_action_resource res;
4191 memset(&res, 0, sizeof(res));
4193 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4196 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4198 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4199 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4200 return flow_dv_push_vlan_action_resource_register
4201 (dev, &res, dev_flow, error);
4205 * Validate the modify-header actions.
4207 * @param[in] action_flags
4208 * Holds the actions detected until now.
4210 * Pointer to the modify action.
4212 * Pointer to error structure.
4215 * 0 on success, a negative errno value otherwise and rte_errno is set.
4218 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4219 const struct rte_flow_action *action,
4220 struct rte_flow_error *error)
4222 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4223 return rte_flow_error_set(error, EINVAL,
4224 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4225 NULL, "action configuration not set");
4226 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4227 return rte_flow_error_set(error, EINVAL,
4228 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4229 "can't have encap action before"
4235 * Validate the modify-header MAC address actions.
4237 * @param[in] action_flags
4238 * Holds the actions detected until now.
4240 * Pointer to the modify action.
4241 * @param[in] item_flags
4242 * Holds the items detected.
4244 * Pointer to error structure.
4247 * 0 on success, a negative errno value otherwise and rte_errno is set.
4250 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4251 const struct rte_flow_action *action,
4252 const uint64_t item_flags,
4253 struct rte_flow_error *error)
4257 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4259 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4260 return rte_flow_error_set(error, EINVAL,
4261 RTE_FLOW_ERROR_TYPE_ACTION,
4263 "no L2 item in pattern");
4269 * Validate the modify-header IPv4 address actions.
4271 * @param[in] action_flags
4272 * Holds the actions detected until now.
4274 * Pointer to the modify action.
4275 * @param[in] item_flags
4276 * Holds the items detected.
4278 * Pointer to error structure.
4281 * 0 on success, a negative errno value otherwise and rte_errno is set.
4284 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4285 const struct rte_flow_action *action,
4286 const uint64_t item_flags,
4287 struct rte_flow_error *error)
4292 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4294 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4295 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4296 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4297 if (!(item_flags & layer))
4298 return rte_flow_error_set(error, EINVAL,
4299 RTE_FLOW_ERROR_TYPE_ACTION,
4301 "no ipv4 item in pattern");
4307 * Validate the modify-header IPv6 address actions.
4309 * @param[in] action_flags
4310 * Holds the actions detected until now.
4312 * Pointer to the modify action.
4313 * @param[in] item_flags
4314 * Holds the items detected.
4316 * Pointer to error structure.
4319 * 0 on success, a negative errno value otherwise and rte_errno is set.
4322 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4323 const struct rte_flow_action *action,
4324 const uint64_t item_flags,
4325 struct rte_flow_error *error)
4330 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4332 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4333 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4334 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4335 if (!(item_flags & layer))
4336 return rte_flow_error_set(error, EINVAL,
4337 RTE_FLOW_ERROR_TYPE_ACTION,
4339 "no ipv6 item in pattern");
4345 * Validate the modify-header TP actions.
4347 * @param[in] action_flags
4348 * Holds the actions detected until now.
4350 * Pointer to the modify action.
4351 * @param[in] item_flags
4352 * Holds the items detected.
4354 * Pointer to error structure.
4357 * 0 on success, a negative errno value otherwise and rte_errno is set.
4360 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4361 const struct rte_flow_action *action,
4362 const uint64_t item_flags,
4363 struct rte_flow_error *error)
4368 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4370 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4371 MLX5_FLOW_LAYER_INNER_L4 :
4372 MLX5_FLOW_LAYER_OUTER_L4;
4373 if (!(item_flags & layer))
4374 return rte_flow_error_set(error, EINVAL,
4375 RTE_FLOW_ERROR_TYPE_ACTION,
4376 NULL, "no transport layer "
4383 * Validate the modify-header actions of increment/decrement
4384 * TCP Sequence-number.
4386 * @param[in] action_flags
4387 * Holds the actions detected until now.
4389 * Pointer to the modify action.
4390 * @param[in] item_flags
4391 * Holds the items detected.
4393 * Pointer to error structure.
4396 * 0 on success, a negative errno value otherwise and rte_errno is set.
4399 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4400 const struct rte_flow_action *action,
4401 const uint64_t item_flags,
4402 struct rte_flow_error *error)
4407 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4409 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4410 MLX5_FLOW_LAYER_INNER_L4_TCP :
4411 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4412 if (!(item_flags & layer))
4413 return rte_flow_error_set(error, EINVAL,
4414 RTE_FLOW_ERROR_TYPE_ACTION,
4415 NULL, "no TCP item in"
4417 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4418 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4419 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4420 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4421 return rte_flow_error_set(error, EINVAL,
4422 RTE_FLOW_ERROR_TYPE_ACTION,
4424 "cannot decrease and increase"
4425 " TCP sequence number"
4426 " at the same time");
4432 * Validate the modify-header actions of increment/decrement
4433 * TCP Acknowledgment number.
4435 * @param[in] action_flags
4436 * Holds the actions detected until now.
4438 * Pointer to the modify action.
4439 * @param[in] item_flags
4440 * Holds the items detected.
4442 * Pointer to error structure.
4445 * 0 on success, a negative errno value otherwise and rte_errno is set.
4448 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4449 const struct rte_flow_action *action,
4450 const uint64_t item_flags,
4451 struct rte_flow_error *error)
4456 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4458 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4459 MLX5_FLOW_LAYER_INNER_L4_TCP :
4460 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4461 if (!(item_flags & layer))
4462 return rte_flow_error_set(error, EINVAL,
4463 RTE_FLOW_ERROR_TYPE_ACTION,
4464 NULL, "no TCP item in"
4466 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4467 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4468 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4469 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4470 return rte_flow_error_set(error, EINVAL,
4471 RTE_FLOW_ERROR_TYPE_ACTION,
4473 "cannot decrease and increase"
4474 " TCP acknowledgment number"
4475 " at the same time");
4481 * Validate the modify-header TTL actions.
4483 * @param[in] action_flags
4484 * Holds the actions detected until now.
4486 * Pointer to the modify action.
4487 * @param[in] item_flags
4488 * Holds the items detected.
4490 * Pointer to error structure.
4493 * 0 on success, a negative errno value otherwise and rte_errno is set.
4496 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4497 const struct rte_flow_action *action,
4498 const uint64_t item_flags,
4499 struct rte_flow_error *error)
4504 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4506 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4507 MLX5_FLOW_LAYER_INNER_L3 :
4508 MLX5_FLOW_LAYER_OUTER_L3;
4509 if (!(item_flags & layer))
4510 return rte_flow_error_set(error, EINVAL,
4511 RTE_FLOW_ERROR_TYPE_ACTION,
4513 "no IP protocol in pattern");
4519 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4522 case RTE_FLOW_FIELD_START:
4524 case RTE_FLOW_FIELD_MAC_DST:
4525 case RTE_FLOW_FIELD_MAC_SRC:
4527 case RTE_FLOW_FIELD_VLAN_TYPE:
4529 case RTE_FLOW_FIELD_VLAN_ID:
4531 case RTE_FLOW_FIELD_MAC_TYPE:
4533 case RTE_FLOW_FIELD_IPV4_DSCP:
4535 case RTE_FLOW_FIELD_IPV4_TTL:
4537 case RTE_FLOW_FIELD_IPV4_SRC:
4538 case RTE_FLOW_FIELD_IPV4_DST:
4540 case RTE_FLOW_FIELD_IPV6_DSCP:
4542 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4544 case RTE_FLOW_FIELD_IPV6_SRC:
4545 case RTE_FLOW_FIELD_IPV6_DST:
4547 case RTE_FLOW_FIELD_TCP_PORT_SRC:
4548 case RTE_FLOW_FIELD_TCP_PORT_DST:
4550 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4551 case RTE_FLOW_FIELD_TCP_ACK_NUM:
4553 case RTE_FLOW_FIELD_TCP_FLAGS:
4555 case RTE_FLOW_FIELD_UDP_PORT_SRC:
4556 case RTE_FLOW_FIELD_UDP_PORT_DST:
4558 case RTE_FLOW_FIELD_VXLAN_VNI:
4559 case RTE_FLOW_FIELD_GENEVE_VNI:
4561 case RTE_FLOW_FIELD_GTP_TEID:
4562 case RTE_FLOW_FIELD_TAG:
4564 case RTE_FLOW_FIELD_MARK:
4566 case RTE_FLOW_FIELD_META:
4567 case RTE_FLOW_FIELD_POINTER:
4568 case RTE_FLOW_FIELD_VALUE:
4577 * Validate the generic modify field actions.
4579 * @param[in] action_flags
4580 * Holds the actions detected until now.
4582 * Pointer to the modify action.
4583 * @param[in] item_flags
4584 * Holds the items detected.
4586 * Pointer to error structure.
4589 * Number of header fields to modify (0 or more) on success,
4590 * a negative errno value otherwise and rte_errno is set.
4593 flow_dv_validate_action_modify_field(const uint64_t action_flags,
4594 const struct rte_flow_action *action,
4595 struct rte_flow_error *error)
4598 const struct rte_flow_action_modify_field *action_modify_field =
4600 uint32_t dst_width =
4601 mlx5_flow_item_field_width(action_modify_field->dst.field);
4602 uint32_t src_width =
4603 mlx5_flow_item_field_width(action_modify_field->src.field);
4605 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4609 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4610 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4611 if (action_modify_field->dst.offset >= dst_width ||
4612 (action_modify_field->dst.offset % 32))
4613 return rte_flow_error_set(error, EINVAL,
4614 RTE_FLOW_ERROR_TYPE_ACTION,
4616 "destination offset is too big"
4617 " or not aligned to 4 bytes");
4618 if (action_modify_field->dst.level &&
4619 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "cannot modify inner headers");
4625 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4626 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4627 if (action_modify_field->src.offset >= src_width ||
4628 (action_modify_field->src.offset % 32))
4629 return rte_flow_error_set(error, EINVAL,
4630 RTE_FLOW_ERROR_TYPE_ACTION,
4632 "source offset is too big"
4633 " or not aligned to 4 bytes");
4634 if (action_modify_field->src.level &&
4635 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4636 return rte_flow_error_set(error, EINVAL,
4637 RTE_FLOW_ERROR_TYPE_ACTION,
4639 "cannot copy from inner headers");
4641 if (action_modify_field->width == 0)
4642 return rte_flow_error_set(error, EINVAL,
4643 RTE_FLOW_ERROR_TYPE_ACTION,
4645 "width is required for modify action");
4646 if (action_modify_field->dst.field ==
4647 action_modify_field->src.field)
4648 return rte_flow_error_set(error, EINVAL,
4649 RTE_FLOW_ERROR_TYPE_ACTION,
4651 "source and destination fields"
4652 " cannot be the same");
4653 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4654 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4655 return rte_flow_error_set(error, EINVAL,
4656 RTE_FLOW_ERROR_TYPE_ACTION,
4658 "immediate value or a pointer to it"
4659 " cannot be used as a destination");
4660 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4661 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4662 return rte_flow_error_set(error, EINVAL,
4663 RTE_FLOW_ERROR_TYPE_ACTION,
4665 "modifications of an arbitrary"
4666 " place in a packet is not supported");
4667 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4668 return rte_flow_error_set(error, EINVAL,
4669 RTE_FLOW_ERROR_TYPE_ACTION,
4671 "add and sub operations"
4672 " are not supported");
4673 return (action_modify_field->width / 32) +
4674 !!(action_modify_field->width % 32);
4678 * Validate jump action.
4681 * Pointer to the jump action.
4682 * @param[in] action_flags
4683 * Holds the actions detected until now.
4684 * @param[in] attributes
4685 * Pointer to flow attributes
4686 * @param[in] external
4687 * Action belongs to flow rule created by request external to PMD.
4689 * Pointer to error structure.
4692 * 0 on success, a negative errno value otherwise and rte_errno is set.
4695 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4696 const struct mlx5_flow_tunnel *tunnel,
4697 const struct rte_flow_action *action,
4698 uint64_t action_flags,
4699 const struct rte_flow_attr *attributes,
4700 bool external, struct rte_flow_error *error)
4702 uint32_t target_group, table;
4704 struct flow_grp_info grp_info = {
4705 .external = !!external,
4706 .transfer = !!attributes->transfer,
4710 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4711 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4712 return rte_flow_error_set(error, EINVAL,
4713 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4714 "can't have 2 fate actions in"
4716 if (action_flags & MLX5_FLOW_ACTION_METER)
4717 return rte_flow_error_set(error, ENOTSUP,
4718 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4719 "jump with meter not support");
4721 return rte_flow_error_set(error, EINVAL,
4722 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4723 NULL, "action configuration not set");
4725 ((const struct rte_flow_action_jump *)action->conf)->group;
4726 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4730 if (attributes->group == target_group &&
4731 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4732 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4733 return rte_flow_error_set(error, EINVAL,
4734 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4735 "target group must be other than"
4736 " the current flow group");
4741 * Validate the port_id action.
4744 * Pointer to rte_eth_dev structure.
4745 * @param[in] action_flags
4746 * Bit-fields that holds the actions detected until now.
4748 * Port_id RTE action structure.
4750 * Attributes of flow that includes this action.
4752 * Pointer to error structure.
4755 * 0 on success, a negative errno value otherwise and rte_errno is set.
4758 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4759 uint64_t action_flags,
4760 const struct rte_flow_action *action,
4761 const struct rte_flow_attr *attr,
4762 struct rte_flow_error *error)
4764 const struct rte_flow_action_port_id *port_id;
4765 struct mlx5_priv *act_priv;
4766 struct mlx5_priv *dev_priv;
4769 if (!attr->transfer)
4770 return rte_flow_error_set(error, ENOTSUP,
4771 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4773 "port id action is valid in transfer"
4775 if (!action || !action->conf)
4776 return rte_flow_error_set(error, ENOTSUP,
4777 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4779 "port id action parameters must be"
4781 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4782 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4783 return rte_flow_error_set(error, EINVAL,
4784 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4785 "can have only one fate actions in"
4787 dev_priv = mlx5_dev_to_eswitch_info(dev);
4789 return rte_flow_error_set(error, rte_errno,
4790 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4792 "failed to obtain E-Switch info");
4793 port_id = action->conf;
4794 port = port_id->original ? dev->data->port_id : port_id->id;
4795 act_priv = mlx5_port_to_eswitch_info(port, false);
4797 return rte_flow_error_set
4799 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4800 "failed to obtain E-Switch port id for port");
4801 if (act_priv->domain_id != dev_priv->domain_id)
4802 return rte_flow_error_set
4804 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4805 "port does not belong to"
4806 " E-Switch being configured");
4811 * Get the maximum number of modify header actions.
4814 * Pointer to rte_eth_dev structure.
4816 * Flags bits to check if root level.
4819 * Max number of modify header actions device can support.
4821 static inline unsigned int
4822 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4826 * There's no way to directly query the max capacity from FW.
4827 * The maximal value on root table should be assumed to be supported.
4829 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4830 return MLX5_MAX_MODIFY_NUM;
4832 return MLX5_ROOT_TBL_MODIFY_NUM;
4836 * Validate the meter action.
4839 * Pointer to rte_eth_dev structure.
4840 * @param[in] action_flags
4841 * Bit-fields that holds the actions detected until now.
4843 * Pointer to the meter action.
4845 * Attributes of flow that includes this action.
4847 * Pointer to error structure.
4850 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4853 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4854 uint64_t action_flags,
4855 const struct rte_flow_action *action,
4856 const struct rte_flow_attr *attr,
4857 struct rte_flow_error *error)
4859 struct mlx5_priv *priv = dev->data->dev_private;
4860 const struct rte_flow_action_meter *am = action->conf;
4861 struct mlx5_flow_meter *fm;
4864 return rte_flow_error_set(error, EINVAL,
4865 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4866 "meter action conf is NULL");
4868 if (action_flags & MLX5_FLOW_ACTION_METER)
4869 return rte_flow_error_set(error, ENOTSUP,
4870 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4871 "meter chaining not support");
4872 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4873 return rte_flow_error_set(error, ENOTSUP,
4874 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4875 "meter with jump not support");
4877 return rte_flow_error_set(error, ENOTSUP,
4878 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4880 "meter action not supported");
4881 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4883 return rte_flow_error_set(error, EINVAL,
4884 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4886 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4887 (!fm->ingress && !attr->ingress && attr->egress) ||
4888 (!fm->egress && !attr->egress && attr->ingress))))
4889 return rte_flow_error_set(error, EINVAL,
4890 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4891 "Flow attributes are either invalid "
4892 "or have a conflict with current "
4893 "meter attributes");
4898 * Validate the age action.
4900 * @param[in] action_flags
4901 * Holds the actions detected until now.
4903 * Pointer to the age action.
4905 * Pointer to the Ethernet device structure.
4907 * Pointer to error structure.
4910 * 0 on success, a negative errno value otherwise and rte_errno is set.
4913 flow_dv_validate_action_age(uint64_t action_flags,
4914 const struct rte_flow_action *action,
4915 struct rte_eth_dev *dev,
4916 struct rte_flow_error *error)
4918 struct mlx5_priv *priv = dev->data->dev_private;
4919 const struct rte_flow_action_age *age = action->conf;
4921 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4922 !priv->sh->aso_age_mng))
4923 return rte_flow_error_set(error, ENOTSUP,
4924 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4926 "age action not supported");
4927 if (!(action->conf))
4928 return rte_flow_error_set(error, EINVAL,
4929 RTE_FLOW_ERROR_TYPE_ACTION, action,
4930 "configuration cannot be null");
4931 if (!(age->timeout))
4932 return rte_flow_error_set(error, EINVAL,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "invalid timeout value 0");
4935 if (action_flags & MLX5_FLOW_ACTION_AGE)
4936 return rte_flow_error_set(error, EINVAL,
4937 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4938 "duplicate age actions set");
4943 * Validate the modify-header IPv4 DSCP actions.
4945 * @param[in] action_flags
4946 * Holds the actions detected until now.
4948 * Pointer to the modify action.
4949 * @param[in] item_flags
4950 * Holds the items detected.
4952 * Pointer to error structure.
4955 * 0 on success, a negative errno value otherwise and rte_errno is set.
4958 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4959 const struct rte_flow_action *action,
4960 const uint64_t item_flags,
4961 struct rte_flow_error *error)
4965 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4967 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4968 return rte_flow_error_set(error, EINVAL,
4969 RTE_FLOW_ERROR_TYPE_ACTION,
4971 "no ipv4 item in pattern");
4977 * Validate the modify-header IPv6 DSCP actions.
4979 * @param[in] action_flags
4980 * Holds the actions detected until now.
4982 * Pointer to the modify action.
4983 * @param[in] item_flags
4984 * Holds the items detected.
4986 * Pointer to error structure.
4989 * 0 on success, a negative errno value otherwise and rte_errno is set.
4992 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4993 const struct rte_flow_action *action,
4994 const uint64_t item_flags,
4995 struct rte_flow_error *error)
4999 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5001 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5002 return rte_flow_error_set(error, EINVAL,
5003 RTE_FLOW_ERROR_TYPE_ACTION,
5005 "no ipv6 item in pattern");
5011 * Match modify-header resource.
5014 * Pointer to the hash list.
5016 * Pointer to exist resource entry object.
5018 * Key of the new entry.
5020 * Pointer to new modify-header resource.
5023 * 0 on matching, non-zero otherwise.
5026 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5027 struct mlx5_hlist_entry *entry,
5028 uint64_t key __rte_unused, void *cb_ctx)
5030 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5031 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5032 struct mlx5_flow_dv_modify_hdr_resource *resource =
5033 container_of(entry, typeof(*resource), entry);
5034 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5036 key_len += ref->actions_num * sizeof(ref->actions[0]);
5037 return ref->actions_num != resource->actions_num ||
5038 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5041 struct mlx5_hlist_entry *
5042 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5045 struct mlx5_dev_ctx_shared *sh = list->ctx;
5046 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5047 struct mlx5dv_dr_domain *ns;
5048 struct mlx5_flow_dv_modify_hdr_resource *entry;
5049 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5051 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5052 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5054 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5057 rte_flow_error_set(ctx->error, ENOMEM,
5058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5059 "cannot allocate resource memory");
5062 rte_memcpy(&entry->ft_type,
5063 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5064 key_len + data_len);
5065 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5066 ns = sh->fdb_domain;
5067 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5071 ret = mlx5_flow_os_create_flow_action_modify_header
5072 (sh->ctx, ns, entry,
5073 data_len, &entry->action);
5076 rte_flow_error_set(ctx->error, ENOMEM,
5077 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5078 NULL, "cannot create modification action");
5081 return &entry->entry;
5085 * Validate the sample action.
5087 * @param[in, out] action_flags
5088 * Holds the actions detected until now.
5090 * Pointer to the sample action.
5092 * Pointer to the Ethernet device structure.
5094 * Attributes of flow that includes this action.
5095 * @param[in] item_flags
5096 * Holds the items detected.
5098 * Pointer to the RSS action.
5099 * @param[out] sample_rss
5100 * Pointer to the RSS action in sample action list.
5102 * Pointer to the COUNT action in sample action list.
5103 * @param[out] fdb_mirror_limit
5104 * Pointer to the FDB mirror limitation flag.
5106 * Pointer to error structure.
5109 * 0 on success, a negative errno value otherwise and rte_errno is set.
5112 flow_dv_validate_action_sample(uint64_t *action_flags,
5113 const struct rte_flow_action *action,
5114 struct rte_eth_dev *dev,
5115 const struct rte_flow_attr *attr,
5116 uint64_t item_flags,
5117 const struct rte_flow_action_rss *rss,
5118 const struct rte_flow_action_rss **sample_rss,
5119 const struct rte_flow_action_count **count,
5120 int *fdb_mirror_limit,
5121 struct rte_flow_error *error)
5123 struct mlx5_priv *priv = dev->data->dev_private;
5124 struct mlx5_dev_config *dev_conf = &priv->config;
5125 const struct rte_flow_action_sample *sample = action->conf;
5126 const struct rte_flow_action *act;
5127 uint64_t sub_action_flags = 0;
5128 uint16_t queue_index = 0xFFFF;
5133 return rte_flow_error_set(error, EINVAL,
5134 RTE_FLOW_ERROR_TYPE_ACTION, action,
5135 "configuration cannot be NULL");
5136 if (sample->ratio == 0)
5137 return rte_flow_error_set(error, EINVAL,
5138 RTE_FLOW_ERROR_TYPE_ACTION, action,
5139 "ratio value starts from 1");
5140 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5141 return rte_flow_error_set(error, ENOTSUP,
5142 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5144 "sample action not supported");
5145 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5146 return rte_flow_error_set(error, EINVAL,
5147 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5148 "Multiple sample actions not "
5150 if (*action_flags & MLX5_FLOW_ACTION_METER)
5151 return rte_flow_error_set(error, EINVAL,
5152 RTE_FLOW_ERROR_TYPE_ACTION, action,
5153 "wrong action order, meter should "
5154 "be after sample action");
5155 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5156 return rte_flow_error_set(error, EINVAL,
5157 RTE_FLOW_ERROR_TYPE_ACTION, action,
5158 "wrong action order, jump should "
5159 "be after sample action");
5160 act = sample->actions;
5161 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5162 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5163 return rte_flow_error_set(error, ENOTSUP,
5164 RTE_FLOW_ERROR_TYPE_ACTION,
5165 act, "too many actions");
5166 switch (act->type) {
5167 case RTE_FLOW_ACTION_TYPE_QUEUE:
5168 ret = mlx5_flow_validate_action_queue(act,
5174 queue_index = ((const struct rte_flow_action_queue *)
5175 (act->conf))->index;
5176 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5179 case RTE_FLOW_ACTION_TYPE_RSS:
5180 *sample_rss = act->conf;
5181 ret = mlx5_flow_validate_action_rss(act,
5188 if (rss && *sample_rss &&
5189 ((*sample_rss)->level != rss->level ||
5190 (*sample_rss)->types != rss->types))
5191 return rte_flow_error_set(error, ENOTSUP,
5192 RTE_FLOW_ERROR_TYPE_ACTION,
5194 "Can't use the different RSS types "
5195 "or level in the same flow");
5196 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5197 queue_index = (*sample_rss)->queue[0];
5198 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5201 case RTE_FLOW_ACTION_TYPE_MARK:
5202 ret = flow_dv_validate_action_mark(dev, act,
5207 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5208 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5209 MLX5_FLOW_ACTION_MARK_EXT;
5211 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5214 case RTE_FLOW_ACTION_TYPE_COUNT:
5215 ret = flow_dv_validate_action_count
5217 *action_flags | sub_action_flags,
5222 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5223 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5226 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5227 ret = flow_dv_validate_action_port_id(dev,
5234 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5237 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5238 ret = flow_dv_validate_action_raw_encap_decap
5239 (dev, NULL, act->conf, attr, &sub_action_flags,
5240 &actions_n, action, item_flags, error);
5246 return rte_flow_error_set(error, ENOTSUP,
5247 RTE_FLOW_ERROR_TYPE_ACTION,
5249 "Doesn't support optional "
5253 if (attr->ingress && !attr->transfer) {
5254 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5255 MLX5_FLOW_ACTION_RSS)))
5256 return rte_flow_error_set(error, EINVAL,
5257 RTE_FLOW_ERROR_TYPE_ACTION,
5259 "Ingress must has a dest "
5260 "QUEUE for Sample");
5261 } else if (attr->egress && !attr->transfer) {
5262 return rte_flow_error_set(error, ENOTSUP,
5263 RTE_FLOW_ERROR_TYPE_ACTION,
5265 "Sample Only support Ingress "
5267 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5268 MLX5_ASSERT(attr->transfer);
5269 if (sample->ratio > 1)
5270 return rte_flow_error_set(error, ENOTSUP,
5271 RTE_FLOW_ERROR_TYPE_ACTION,
5273 "E-Switch doesn't support "
5274 "any optional action "
5276 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5277 return rte_flow_error_set(error, ENOTSUP,
5278 RTE_FLOW_ERROR_TYPE_ACTION,
5280 "unsupported action QUEUE");
5281 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5282 return rte_flow_error_set(error, ENOTSUP,
5283 RTE_FLOW_ERROR_TYPE_ACTION,
5285 "unsupported action QUEUE");
5286 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5287 return rte_flow_error_set(error, EINVAL,
5288 RTE_FLOW_ERROR_TYPE_ACTION,
5290 "E-Switch must has a dest "
5291 "port for mirroring");
5292 if (!priv->config.hca_attr.reg_c_preserve &&
5293 priv->representor_id != -1)
5294 *fdb_mirror_limit = 1;
5296 /* Continue validation for Xcap actions.*/
5297 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5298 (queue_index == 0xFFFF ||
5299 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5300 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5301 MLX5_FLOW_XCAP_ACTIONS)
5302 return rte_flow_error_set(error, ENOTSUP,
5303 RTE_FLOW_ERROR_TYPE_ACTION,
5304 NULL, "encap and decap "
5305 "combination aren't "
5307 if (!attr->transfer && attr->ingress && (sub_action_flags &
5308 MLX5_FLOW_ACTION_ENCAP))
5309 return rte_flow_error_set(error, ENOTSUP,
5310 RTE_FLOW_ERROR_TYPE_ACTION,
5311 NULL, "encap is not supported"
5312 " for ingress traffic");
5318 * Find existing modify-header resource or create and register a new one.
5320 * @param dev[in, out]
5321 * Pointer to rte_eth_dev structure.
5322 * @param[in, out] resource
5323 * Pointer to modify-header resource.
5324 * @parm[in, out] dev_flow
5325 * Pointer to the dev_flow.
5327 * pointer to error structure.
5330 * 0 on success otherwise -errno and errno is set.
5333 flow_dv_modify_hdr_resource_register
5334 (struct rte_eth_dev *dev,
5335 struct mlx5_flow_dv_modify_hdr_resource *resource,
5336 struct mlx5_flow *dev_flow,
5337 struct rte_flow_error *error)
5339 struct mlx5_priv *priv = dev->data->dev_private;
5340 struct mlx5_dev_ctx_shared *sh = priv->sh;
5341 uint32_t key_len = sizeof(*resource) -
5342 offsetof(typeof(*resource), ft_type) +
5343 resource->actions_num * sizeof(resource->actions[0]);
5344 struct mlx5_hlist_entry *entry;
5345 struct mlx5_flow_cb_ctx ctx = {
5351 resource->flags = dev_flow->dv.group ? 0 :
5352 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5353 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5355 return rte_flow_error_set(error, EOVERFLOW,
5356 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5357 "too many modify header items");
5358 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5359 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5362 resource = container_of(entry, typeof(*resource), entry);
5363 dev_flow->handle->dvh.modify_hdr = resource;
5368 * Get DV flow counter by index.
5371 * Pointer to the Ethernet device structure.
5373 * mlx5 flow counter index in the container.
5375 * mlx5 flow counter pool in the container,
5378 * Pointer to the counter, NULL otherwise.
5380 static struct mlx5_flow_counter *
5381 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5383 struct mlx5_flow_counter_pool **ppool)
5385 struct mlx5_priv *priv = dev->data->dev_private;
5386 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5387 struct mlx5_flow_counter_pool *pool;
5389 /* Decrease to original index and clear shared bit. */
5390 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5391 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5392 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5396 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5400 * Check the devx counter belongs to the pool.
5403 * Pointer to the counter pool.
5405 * The counter devx ID.
5408 * True if counter belongs to the pool, false otherwise.
5411 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5413 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5414 MLX5_COUNTERS_PER_POOL;
5416 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5422 * Get a pool by devx counter ID.
5425 * Pointer to the counter management.
5427 * The counter devx ID.
5430 * The counter pool pointer if exists, NULL otherwise,
5432 static struct mlx5_flow_counter_pool *
5433 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5436 struct mlx5_flow_counter_pool *pool = NULL;
5438 rte_spinlock_lock(&cmng->pool_update_sl);
5439 /* Check last used pool. */
5440 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5441 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5442 pool = cmng->pools[cmng->last_pool_idx];
5445 /* ID out of range means no suitable pool in the container. */
5446 if (id > cmng->max_id || id < cmng->min_id)
5449 * Find the pool from the end of the container, since mostly counter
5450 * ID is sequence increasing, and the last pool should be the needed
5455 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5457 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5463 rte_spinlock_unlock(&cmng->pool_update_sl);
5468 * Resize a counter container.
5471 * Pointer to the Ethernet device structure.
5474 * 0 on success, otherwise negative errno value and rte_errno is set.
5477 flow_dv_container_resize(struct rte_eth_dev *dev)
5479 struct mlx5_priv *priv = dev->data->dev_private;
5480 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5481 void *old_pools = cmng->pools;
5482 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5483 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5484 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5491 memcpy(pools, old_pools, cmng->n *
5492 sizeof(struct mlx5_flow_counter_pool *));
5494 cmng->pools = pools;
5496 mlx5_free(old_pools);
5501 * Query a devx flow counter.
5504 * Pointer to the Ethernet device structure.
5506 * Index to the flow counter.
5508 * The statistics value of packets.
5510 * The statistics value of bytes.
5513 * 0 on success, otherwise a negative errno value and rte_errno is set.
5516 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5519 struct mlx5_priv *priv = dev->data->dev_private;
5520 struct mlx5_flow_counter_pool *pool = NULL;
5521 struct mlx5_flow_counter *cnt;
5524 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5526 if (priv->sh->cmng.counter_fallback)
5527 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5528 0, pkts, bytes, 0, NULL, NULL, 0);
5529 rte_spinlock_lock(&pool->sl);
5534 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5535 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5536 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5538 rte_spinlock_unlock(&pool->sl);
5543 * Create and initialize a new counter pool.
5546 * Pointer to the Ethernet device structure.
5548 * The devX counter handle.
5550 * Whether the pool is for counter that was allocated for aging.
5551 * @param[in/out] cont_cur
5552 * Pointer to the container pointer, it will be update in pool resize.
5555 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5557 static struct mlx5_flow_counter_pool *
5558 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5561 struct mlx5_priv *priv = dev->data->dev_private;
5562 struct mlx5_flow_counter_pool *pool;
5563 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5564 bool fallback = priv->sh->cmng.counter_fallback;
5565 uint32_t size = sizeof(*pool);
5567 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5568 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5569 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5575 pool->is_aged = !!age;
5576 pool->query_gen = 0;
5577 pool->min_dcs = dcs;
5578 rte_spinlock_init(&pool->sl);
5579 rte_spinlock_init(&pool->csl);
5580 TAILQ_INIT(&pool->counters[0]);
5581 TAILQ_INIT(&pool->counters[1]);
5582 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5583 rte_spinlock_lock(&cmng->pool_update_sl);
5584 pool->index = cmng->n_valid;
5585 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5587 rte_spinlock_unlock(&cmng->pool_update_sl);
5590 cmng->pools[pool->index] = pool;
5592 if (unlikely(fallback)) {
5593 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5595 if (base < cmng->min_id)
5596 cmng->min_id = base;
5597 if (base > cmng->max_id)
5598 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5599 cmng->last_pool_idx = pool->index;
5601 rte_spinlock_unlock(&cmng->pool_update_sl);
5606 * Prepare a new counter and/or a new counter pool.
5609 * Pointer to the Ethernet device structure.
5610 * @param[out] cnt_free
5611 * Where to put the pointer of a new counter.
5613 * Whether the pool is for counter that was allocated for aging.
5616 * The counter pool pointer and @p cnt_free is set on success,
5617 * NULL otherwise and rte_errno is set.
5619 static struct mlx5_flow_counter_pool *
5620 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5621 struct mlx5_flow_counter **cnt_free,
5624 struct mlx5_priv *priv = dev->data->dev_private;
5625 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5626 struct mlx5_flow_counter_pool *pool;
5627 struct mlx5_counters tmp_tq;
5628 struct mlx5_devx_obj *dcs = NULL;
5629 struct mlx5_flow_counter *cnt;
5630 enum mlx5_counter_type cnt_type =
5631 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5632 bool fallback = priv->sh->cmng.counter_fallback;
5636 /* bulk_bitmap must be 0 for single counter allocation. */
5637 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5640 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5642 pool = flow_dv_pool_create(dev, dcs, age);
5644 mlx5_devx_cmd_destroy(dcs);
5648 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5649 cnt = MLX5_POOL_GET_CNT(pool, i);
5651 cnt->dcs_when_free = dcs;
5655 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5657 rte_errno = ENODATA;
5660 pool = flow_dv_pool_create(dev, dcs, age);
5662 mlx5_devx_cmd_destroy(dcs);
5665 TAILQ_INIT(&tmp_tq);
5666 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5667 cnt = MLX5_POOL_GET_CNT(pool, i);
5669 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5671 rte_spinlock_lock(&cmng->csl[cnt_type]);
5672 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5673 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5674 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5675 (*cnt_free)->pool = pool;
5680 * Allocate a flow counter.
5683 * Pointer to the Ethernet device structure.
5685 * Whether the counter was allocated for aging.
5688 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5691 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5693 struct mlx5_priv *priv = dev->data->dev_private;
5694 struct mlx5_flow_counter_pool *pool = NULL;
5695 struct mlx5_flow_counter *cnt_free = NULL;
5696 bool fallback = priv->sh->cmng.counter_fallback;
5697 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5698 enum mlx5_counter_type cnt_type =
5699 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5702 if (!priv->config.devx) {
5703 rte_errno = ENOTSUP;
5706 /* Get free counters from container. */
5707 rte_spinlock_lock(&cmng->csl[cnt_type]);
5708 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5710 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5711 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5712 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5714 pool = cnt_free->pool;
5716 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5717 /* Create a DV counter action only in the first time usage. */
5718 if (!cnt_free->action) {
5720 struct mlx5_devx_obj *dcs;
5724 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5725 dcs = pool->min_dcs;
5728 dcs = cnt_free->dcs_when_free;
5730 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5737 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5738 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5739 /* Update the counter reset values. */
5740 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5743 if (!fallback && !priv->sh->cmng.query_thread_on)
5744 /* Start the asynchronous batch query by the host thread. */
5745 mlx5_set_query_alarm(priv->sh);
5749 cnt_free->pool = pool;
5751 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5752 rte_spinlock_lock(&cmng->csl[cnt_type]);
5753 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5754 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5760 * Allocate a shared flow counter.
5763 * Pointer to the shared counter configuration.
5765 * Pointer to save the allocated counter index.
5768 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5772 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5774 struct mlx5_shared_counter_conf *conf = ctx;
5775 struct rte_eth_dev *dev = conf->dev;
5776 struct mlx5_flow_counter *cnt;
5778 data->dword = flow_dv_counter_alloc(dev, 0);
5779 data->dword |= MLX5_CNT_SHARED_OFFSET;
5780 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5781 cnt->shared_info.id = conf->id;
5786 * Get a shared flow counter.
5789 * Pointer to the Ethernet device structure.
5791 * Counter identifier.
5794 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5797 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5799 struct mlx5_priv *priv = dev->data->dev_private;
5800 struct mlx5_shared_counter_conf conf = {
5804 union mlx5_l3t_data data = {
5808 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5809 flow_dv_counter_alloc_shared_cb, &conf);
5814 * Get age param from counter index.
5817 * Pointer to the Ethernet device structure.
5818 * @param[in] counter
5819 * Index to the counter handler.
5822 * The aging parameter specified for the counter index.
5824 static struct mlx5_age_param*
5825 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5828 struct mlx5_flow_counter *cnt;
5829 struct mlx5_flow_counter_pool *pool = NULL;
5831 flow_dv_counter_get_by_idx(dev, counter, &pool);
5832 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5833 cnt = MLX5_POOL_GET_CNT(pool, counter);
5834 return MLX5_CNT_TO_AGE(cnt);
5838 * Remove a flow counter from aged counter list.
5841 * Pointer to the Ethernet device structure.
5842 * @param[in] counter
5843 * Index to the counter handler.
5845 * Pointer to the counter handler.
5848 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5849 uint32_t counter, struct mlx5_flow_counter *cnt)
5851 struct mlx5_age_info *age_info;
5852 struct mlx5_age_param *age_param;
5853 struct mlx5_priv *priv = dev->data->dev_private;
5854 uint16_t expected = AGE_CANDIDATE;
5856 age_info = GET_PORT_AGE_INFO(priv);
5857 age_param = flow_dv_counter_idx_get_age(dev, counter);
5858 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5859 AGE_FREE, false, __ATOMIC_RELAXED,
5860 __ATOMIC_RELAXED)) {
5862 * We need the lock even it is age timeout,
5863 * since counter may still in process.
5865 rte_spinlock_lock(&age_info->aged_sl);
5866 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5867 rte_spinlock_unlock(&age_info->aged_sl);
5868 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5873 * Release a flow counter.
5876 * Pointer to the Ethernet device structure.
5877 * @param[in] counter
5878 * Index to the counter handler.
5881 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5883 struct mlx5_priv *priv = dev->data->dev_private;
5884 struct mlx5_flow_counter_pool *pool = NULL;
5885 struct mlx5_flow_counter *cnt;
5886 enum mlx5_counter_type cnt_type;
5890 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5892 if (IS_SHARED_CNT(counter) &&
5893 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5896 flow_dv_counter_remove_from_age(dev, counter, cnt);
5899 * Put the counter back to list to be updated in none fallback mode.
5900 * Currently, we are using two list alternately, while one is in query,
5901 * add the freed counter to the other list based on the pool query_gen
5902 * value. After query finishes, add counter the list to the global
5903 * container counter list. The list changes while query starts. In
5904 * this case, lock will not be needed as query callback and release
5905 * function both operate with the different list.
5908 if (!priv->sh->cmng.counter_fallback) {
5909 rte_spinlock_lock(&pool->csl);
5910 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5911 rte_spinlock_unlock(&pool->csl);
5913 cnt->dcs_when_free = cnt->dcs_when_active;
5914 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5915 MLX5_COUNTER_TYPE_ORIGIN;
5916 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5917 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5919 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5924 * Verify the @p attributes will be correctly understood by the NIC and store
5925 * them in the @p flow if everything is correct.
5928 * Pointer to dev struct.
5929 * @param[in] attributes
5930 * Pointer to flow attributes
5931 * @param[in] external
5932 * This flow rule is created by request external to PMD.
5934 * Pointer to error structure.
5937 * - 0 on success and non root table.
5938 * - 1 on success and root table.
5939 * - a negative errno value otherwise and rte_errno is set.
5942 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5943 const struct mlx5_flow_tunnel *tunnel,
5944 const struct rte_flow_attr *attributes,
5945 const struct flow_grp_info *grp_info,
5946 struct rte_flow_error *error)
5948 struct mlx5_priv *priv = dev->data->dev_private;
5949 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5952 #ifndef HAVE_MLX5DV_DR
5953 RTE_SET_USED(tunnel);
5954 RTE_SET_USED(grp_info);
5955 if (attributes->group)
5956 return rte_flow_error_set(error, ENOTSUP,
5957 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5959 "groups are not supported");
5963 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5968 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5970 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5971 attributes->priority > lowest_priority)
5972 return rte_flow_error_set(error, ENOTSUP,
5973 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5975 "priority out of range");
5976 if (attributes->transfer) {
5977 if (!priv->config.dv_esw_en)
5978 return rte_flow_error_set
5980 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5981 "E-Switch dr is not supported");
5982 if (!(priv->representor || priv->master))
5983 return rte_flow_error_set
5984 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5985 NULL, "E-Switch configuration can only be"
5986 " done by a master or a representor device");
5987 if (attributes->egress)
5988 return rte_flow_error_set
5990 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5991 "egress is not supported");
5993 if (!(attributes->egress ^ attributes->ingress))
5994 return rte_flow_error_set(error, ENOTSUP,
5995 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5996 "must specify exactly one of "
5997 "ingress or egress");
6002 * Internal validation function. For validating both actions and items.
6005 * Pointer to the rte_eth_dev structure.
6007 * Pointer to the flow attributes.
6009 * Pointer to the list of items.
6010 * @param[in] actions
6011 * Pointer to the list of actions.
6012 * @param[in] external
6013 * This flow rule is created by request external to PMD.
6014 * @param[in] hairpin
6015 * Number of hairpin TX actions, 0 means classic flow.
6017 * Pointer to the error structure.
6020 * 0 on success, a negative errno value otherwise and rte_errno is set.
6023 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6024 const struct rte_flow_item items[],
6025 const struct rte_flow_action actions[],
6026 bool external, int hairpin, struct rte_flow_error *error)
6029 uint64_t action_flags = 0;
6030 uint64_t item_flags = 0;
6031 uint64_t last_item = 0;
6032 uint8_t next_protocol = 0xff;
6033 uint16_t ether_type = 0;
6035 uint8_t item_ipv6_proto = 0;
6036 int fdb_mirror_limit = 0;
6037 int modify_after_mirror = 0;
6038 const struct rte_flow_item *geneve_item = NULL;
6039 const struct rte_flow_item *gre_item = NULL;
6040 const struct rte_flow_item *gtp_item = NULL;
6041 const struct rte_flow_action_raw_decap *decap;
6042 const struct rte_flow_action_raw_encap *encap;
6043 const struct rte_flow_action_rss *rss = NULL;
6044 const struct rte_flow_action_rss *sample_rss = NULL;
6045 const struct rte_flow_action_count *count = NULL;
6046 const struct rte_flow_action_count *sample_count = NULL;
6047 const struct rte_flow_item_tcp nic_tcp_mask = {
6050 .src_port = RTE_BE16(UINT16_MAX),
6051 .dst_port = RTE_BE16(UINT16_MAX),
6054 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6057 "\xff\xff\xff\xff\xff\xff\xff\xff"
6058 "\xff\xff\xff\xff\xff\xff\xff\xff",
6060 "\xff\xff\xff\xff\xff\xff\xff\xff"
6061 "\xff\xff\xff\xff\xff\xff\xff\xff",
6062 .vtc_flow = RTE_BE32(0xffffffff),
6068 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6072 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6076 .dummy[0] = 0xffffffff,
6079 struct mlx5_priv *priv = dev->data->dev_private;
6080 struct mlx5_dev_config *dev_conf = &priv->config;
6081 uint16_t queue_index = 0xFFFF;
6082 const struct rte_flow_item_vlan *vlan_m = NULL;
6083 uint32_t rw_act_num = 0;
6085 const struct mlx5_flow_tunnel *tunnel;
6086 struct flow_grp_info grp_info = {
6087 .external = !!external,
6088 .transfer = !!attr->transfer,
6089 .fdb_def_rule = !!priv->fdb_def_rule,
6091 const struct rte_eth_hairpin_conf *conf;
6095 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6096 tunnel = flow_items_to_tunnel(items);
6097 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6098 MLX5_FLOW_ACTION_DECAP;
6099 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6100 tunnel = flow_actions_to_tunnel(actions);
6101 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6105 if (tunnel && priv->representor)
6106 return rte_flow_error_set(error, ENOTSUP,
6107 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6108 "decap not supported "
6109 "for VF representor");
6110 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6111 (dev, tunnel, attr, items, actions);
6112 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6115 is_root = (uint64_t)ret;
6116 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6117 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6118 int type = items->type;
6120 if (!mlx5_flow_os_item_supported(type))
6121 return rte_flow_error_set(error, ENOTSUP,
6122 RTE_FLOW_ERROR_TYPE_ITEM,
6123 NULL, "item not supported");
6125 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6126 if (items[0].type != (typeof(items[0].type))
6127 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6128 return rte_flow_error_set
6130 RTE_FLOW_ERROR_TYPE_ITEM,
6131 NULL, "MLX5 private items "
6132 "must be the first");
6134 case RTE_FLOW_ITEM_TYPE_VOID:
6136 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6137 ret = flow_dv_validate_item_port_id
6138 (dev, items, attr, item_flags, error);
6141 last_item = MLX5_FLOW_ITEM_PORT_ID;
6143 case RTE_FLOW_ITEM_TYPE_ETH:
6144 ret = mlx5_flow_validate_item_eth(items, item_flags,
6148 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6149 MLX5_FLOW_LAYER_OUTER_L2;
6150 if (items->mask != NULL && items->spec != NULL) {
6152 ((const struct rte_flow_item_eth *)
6155 ((const struct rte_flow_item_eth *)
6157 ether_type = rte_be_to_cpu_16(ether_type);
6162 case RTE_FLOW_ITEM_TYPE_VLAN:
6163 ret = flow_dv_validate_item_vlan(items, item_flags,
6167 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6168 MLX5_FLOW_LAYER_OUTER_VLAN;
6169 if (items->mask != NULL && items->spec != NULL) {
6171 ((const struct rte_flow_item_vlan *)
6172 items->spec)->inner_type;
6174 ((const struct rte_flow_item_vlan *)
6175 items->mask)->inner_type;
6176 ether_type = rte_be_to_cpu_16(ether_type);
6180 /* Store outer VLAN mask for of_push_vlan action. */
6182 vlan_m = items->mask;
6184 case RTE_FLOW_ITEM_TYPE_IPV4:
6185 mlx5_flow_tunnel_ip_check(items, next_protocol,
6186 &item_flags, &tunnel);
6187 ret = flow_dv_validate_item_ipv4(items, item_flags,
6188 last_item, ether_type,
6192 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6193 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6194 if (items->mask != NULL &&
6195 ((const struct rte_flow_item_ipv4 *)
6196 items->mask)->hdr.next_proto_id) {
6198 ((const struct rte_flow_item_ipv4 *)
6199 (items->spec))->hdr.next_proto_id;
6201 ((const struct rte_flow_item_ipv4 *)
6202 (items->mask))->hdr.next_proto_id;
6204 /* Reset for inner layer. */
6205 next_protocol = 0xff;
6208 case RTE_FLOW_ITEM_TYPE_IPV6:
6209 mlx5_flow_tunnel_ip_check(items, next_protocol,
6210 &item_flags, &tunnel);
6211 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6218 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6219 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6220 if (items->mask != NULL &&
6221 ((const struct rte_flow_item_ipv6 *)
6222 items->mask)->hdr.proto) {
6224 ((const struct rte_flow_item_ipv6 *)
6225 items->spec)->hdr.proto;
6227 ((const struct rte_flow_item_ipv6 *)
6228 items->spec)->hdr.proto;
6230 ((const struct rte_flow_item_ipv6 *)
6231 items->mask)->hdr.proto;
6233 /* Reset for inner layer. */
6234 next_protocol = 0xff;
6237 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6238 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6243 last_item = tunnel ?
6244 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6245 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6246 if (items->mask != NULL &&
6247 ((const struct rte_flow_item_ipv6_frag_ext *)
6248 items->mask)->hdr.next_header) {
6250 ((const struct rte_flow_item_ipv6_frag_ext *)
6251 items->spec)->hdr.next_header;
6253 ((const struct rte_flow_item_ipv6_frag_ext *)
6254 items->mask)->hdr.next_header;
6256 /* Reset for inner layer. */
6257 next_protocol = 0xff;
6260 case RTE_FLOW_ITEM_TYPE_TCP:
6261 ret = mlx5_flow_validate_item_tcp
6268 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6269 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6271 case RTE_FLOW_ITEM_TYPE_UDP:
6272 ret = mlx5_flow_validate_item_udp(items, item_flags,
6277 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6278 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6280 case RTE_FLOW_ITEM_TYPE_GRE:
6281 ret = mlx5_flow_validate_item_gre(items, item_flags,
6282 next_protocol, error);
6286 last_item = MLX5_FLOW_LAYER_GRE;
6288 case RTE_FLOW_ITEM_TYPE_NVGRE:
6289 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6294 last_item = MLX5_FLOW_LAYER_NVGRE;
6296 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6297 ret = mlx5_flow_validate_item_gre_key
6298 (items, item_flags, gre_item, error);
6301 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6303 case RTE_FLOW_ITEM_TYPE_VXLAN:
6304 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6308 last_item = MLX5_FLOW_LAYER_VXLAN;
6310 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6311 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6316 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6318 case RTE_FLOW_ITEM_TYPE_GENEVE:
6319 ret = mlx5_flow_validate_item_geneve(items,
6324 geneve_item = items;
6325 last_item = MLX5_FLOW_LAYER_GENEVE;
6327 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6328 ret = mlx5_flow_validate_item_geneve_opt(items,
6335 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6337 case RTE_FLOW_ITEM_TYPE_MPLS:
6338 ret = mlx5_flow_validate_item_mpls(dev, items,
6343 last_item = MLX5_FLOW_LAYER_MPLS;
6346 case RTE_FLOW_ITEM_TYPE_MARK:
6347 ret = flow_dv_validate_item_mark(dev, items, attr,
6351 last_item = MLX5_FLOW_ITEM_MARK;
6353 case RTE_FLOW_ITEM_TYPE_META:
6354 ret = flow_dv_validate_item_meta(dev, items, attr,
6358 last_item = MLX5_FLOW_ITEM_METADATA;
6360 case RTE_FLOW_ITEM_TYPE_ICMP:
6361 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6366 last_item = MLX5_FLOW_LAYER_ICMP;
6368 case RTE_FLOW_ITEM_TYPE_ICMP6:
6369 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6374 item_ipv6_proto = IPPROTO_ICMPV6;
6375 last_item = MLX5_FLOW_LAYER_ICMP6;
6377 case RTE_FLOW_ITEM_TYPE_TAG:
6378 ret = flow_dv_validate_item_tag(dev, items,
6382 last_item = MLX5_FLOW_ITEM_TAG;
6384 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6385 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6387 case RTE_FLOW_ITEM_TYPE_GTP:
6388 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6393 last_item = MLX5_FLOW_LAYER_GTP;
6395 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6396 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6401 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6403 case RTE_FLOW_ITEM_TYPE_ECPRI:
6404 /* Capacity will be checked in the translate stage. */
6405 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6412 last_item = MLX5_FLOW_LAYER_ECPRI;
6415 return rte_flow_error_set(error, ENOTSUP,
6416 RTE_FLOW_ERROR_TYPE_ITEM,
6417 NULL, "item not supported");
6419 item_flags |= last_item;
6421 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6422 int type = actions->type;
6424 if (!mlx5_flow_os_action_supported(type))
6425 return rte_flow_error_set(error, ENOTSUP,
6426 RTE_FLOW_ERROR_TYPE_ACTION,
6428 "action not supported");
6429 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6430 return rte_flow_error_set(error, ENOTSUP,
6431 RTE_FLOW_ERROR_TYPE_ACTION,
6432 actions, "too many actions");
6434 case RTE_FLOW_ACTION_TYPE_VOID:
6436 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6437 ret = flow_dv_validate_action_port_id(dev,
6444 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6447 case RTE_FLOW_ACTION_TYPE_FLAG:
6448 ret = flow_dv_validate_action_flag(dev, action_flags,
6452 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6453 /* Count all modify-header actions as one. */
6454 if (!(action_flags &
6455 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6457 action_flags |= MLX5_FLOW_ACTION_FLAG |
6458 MLX5_FLOW_ACTION_MARK_EXT;
6459 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6460 modify_after_mirror = 1;
6463 action_flags |= MLX5_FLOW_ACTION_FLAG;
6466 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6468 case RTE_FLOW_ACTION_TYPE_MARK:
6469 ret = flow_dv_validate_action_mark(dev, actions,
6474 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6475 /* Count all modify-header actions as one. */
6476 if (!(action_flags &
6477 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6479 action_flags |= MLX5_FLOW_ACTION_MARK |
6480 MLX5_FLOW_ACTION_MARK_EXT;
6481 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6482 modify_after_mirror = 1;
6484 action_flags |= MLX5_FLOW_ACTION_MARK;
6487 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6489 case RTE_FLOW_ACTION_TYPE_SET_META:
6490 ret = flow_dv_validate_action_set_meta(dev, actions,
6495 /* Count all modify-header actions as one action. */
6496 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6498 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6499 modify_after_mirror = 1;
6500 action_flags |= MLX5_FLOW_ACTION_SET_META;
6501 rw_act_num += MLX5_ACT_NUM_SET_META;
6503 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6504 ret = flow_dv_validate_action_set_tag(dev, actions,
6509 /* Count all modify-header actions as one action. */
6510 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6512 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6513 modify_after_mirror = 1;
6514 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6515 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6517 case RTE_FLOW_ACTION_TYPE_DROP:
6518 ret = mlx5_flow_validate_action_drop(action_flags,
6522 action_flags |= MLX5_FLOW_ACTION_DROP;
6525 case RTE_FLOW_ACTION_TYPE_QUEUE:
6526 ret = mlx5_flow_validate_action_queue(actions,
6531 queue_index = ((const struct rte_flow_action_queue *)
6532 (actions->conf))->index;
6533 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6536 case RTE_FLOW_ACTION_TYPE_RSS:
6537 rss = actions->conf;
6538 ret = mlx5_flow_validate_action_rss(actions,
6544 if (rss && sample_rss &&
6545 (sample_rss->level != rss->level ||
6546 sample_rss->types != rss->types))
6547 return rte_flow_error_set(error, ENOTSUP,
6548 RTE_FLOW_ERROR_TYPE_ACTION,
6550 "Can't use the different RSS types "
6551 "or level in the same flow");
6552 if (rss != NULL && rss->queue_num)
6553 queue_index = rss->queue[0];
6554 action_flags |= MLX5_FLOW_ACTION_RSS;
6557 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6559 mlx5_flow_validate_action_default_miss(action_flags,
6563 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6566 case RTE_FLOW_ACTION_TYPE_COUNT:
6567 ret = flow_dv_validate_action_count(dev, actions,
6572 count = actions->conf;
6573 action_flags |= MLX5_FLOW_ACTION_COUNT;
6576 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6577 if (flow_dv_validate_action_pop_vlan(dev,
6583 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6586 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6587 ret = flow_dv_validate_action_push_vlan(dev,
6594 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6597 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6598 ret = flow_dv_validate_action_set_vlan_pcp
6599 (action_flags, actions, error);
6602 /* Count PCP with push_vlan command. */
6603 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6605 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6606 ret = flow_dv_validate_action_set_vlan_vid
6607 (item_flags, action_flags,
6611 /* Count VID with push_vlan command. */
6612 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6613 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6615 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6616 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6617 ret = flow_dv_validate_action_l2_encap(dev,
6623 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6626 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6627 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6628 ret = flow_dv_validate_action_decap(dev, action_flags,
6629 actions, item_flags,
6633 action_flags |= MLX5_FLOW_ACTION_DECAP;
6636 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6637 ret = flow_dv_validate_action_raw_encap_decap
6638 (dev, NULL, actions->conf, attr, &action_flags,
6639 &actions_n, actions, item_flags, error);
6643 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6644 decap = actions->conf;
6645 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6647 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6651 encap = actions->conf;
6653 ret = flow_dv_validate_action_raw_encap_decap
6655 decap ? decap : &empty_decap, encap,
6656 attr, &action_flags, &actions_n,
6657 actions, item_flags, error);
6661 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6662 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6663 ret = flow_dv_validate_action_modify_mac(action_flags,
6669 /* Count all modify-header actions as one action. */
6670 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6672 action_flags |= actions->type ==
6673 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6674 MLX5_FLOW_ACTION_SET_MAC_SRC :
6675 MLX5_FLOW_ACTION_SET_MAC_DST;
6676 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6677 modify_after_mirror = 1;
6679 * Even if the source and destination MAC addresses have
6680 * overlap in the header with 4B alignment, the convert
6681 * function will handle them separately and 4 SW actions
6682 * will be created. And 2 actions will be added each
6683 * time no matter how many bytes of address will be set.
6685 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6687 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6688 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6689 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6695 /* Count all modify-header actions as one action. */
6696 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6698 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6699 modify_after_mirror = 1;
6700 action_flags |= actions->type ==
6701 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6702 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6703 MLX5_FLOW_ACTION_SET_IPV4_DST;
6704 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6706 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6707 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6708 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6714 if (item_ipv6_proto == IPPROTO_ICMPV6)
6715 return rte_flow_error_set(error, ENOTSUP,
6716 RTE_FLOW_ERROR_TYPE_ACTION,
6718 "Can't change header "
6719 "with ICMPv6 proto");
6720 /* Count all modify-header actions as one action. */
6721 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6723 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6724 modify_after_mirror = 1;
6725 action_flags |= actions->type ==
6726 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6727 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6728 MLX5_FLOW_ACTION_SET_IPV6_DST;
6729 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6731 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6732 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6733 ret = flow_dv_validate_action_modify_tp(action_flags,
6739 /* Count all modify-header actions as one action. */
6740 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6742 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6743 modify_after_mirror = 1;
6744 action_flags |= actions->type ==
6745 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6746 MLX5_FLOW_ACTION_SET_TP_SRC :
6747 MLX5_FLOW_ACTION_SET_TP_DST;
6748 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6750 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6751 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6752 ret = flow_dv_validate_action_modify_ttl(action_flags,
6758 /* Count all modify-header actions as one action. */
6759 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6761 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6762 modify_after_mirror = 1;
6763 action_flags |= actions->type ==
6764 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6765 MLX5_FLOW_ACTION_SET_TTL :
6766 MLX5_FLOW_ACTION_DEC_TTL;
6767 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6769 case RTE_FLOW_ACTION_TYPE_JUMP:
6770 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6776 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6778 return rte_flow_error_set(error, EINVAL,
6779 RTE_FLOW_ERROR_TYPE_ACTION,
6781 "sample and jump action combination is not supported");
6783 action_flags |= MLX5_FLOW_ACTION_JUMP;
6785 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6786 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6787 ret = flow_dv_validate_action_modify_tcp_seq
6794 /* Count all modify-header actions as one action. */
6795 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6797 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6798 modify_after_mirror = 1;
6799 action_flags |= actions->type ==
6800 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6801 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6802 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6803 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6805 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6806 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6807 ret = flow_dv_validate_action_modify_tcp_ack
6814 /* Count all modify-header actions as one action. */
6815 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6817 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6818 modify_after_mirror = 1;
6819 action_flags |= actions->type ==
6820 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6821 MLX5_FLOW_ACTION_INC_TCP_ACK :
6822 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6823 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6825 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6827 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6828 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6829 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6831 case RTE_FLOW_ACTION_TYPE_METER:
6832 ret = mlx5_flow_validate_action_meter(dev,
6838 action_flags |= MLX5_FLOW_ACTION_METER;
6840 /* Meter action will add one more TAG action. */
6841 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6843 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6844 if (!attr->transfer && !attr->group)
6845 return rte_flow_error_set(error, ENOTSUP,
6846 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6848 "Shared ASO age action is not supported for group 0");
6849 action_flags |= MLX5_FLOW_ACTION_AGE;
6852 case RTE_FLOW_ACTION_TYPE_AGE:
6853 ret = flow_dv_validate_action_age(action_flags,
6859 * Validate the regular AGE action (using counter)
6860 * mutual exclusion with share counter actions.
6862 if (!priv->sh->flow_hit_aso_en) {
6863 if (count && count->shared)
6864 return rte_flow_error_set
6866 RTE_FLOW_ERROR_TYPE_ACTION,
6868 "old age and shared count combination is not supported");
6870 return rte_flow_error_set
6872 RTE_FLOW_ERROR_TYPE_ACTION,
6874 "old age action and count must be in the same sub flow");
6876 action_flags |= MLX5_FLOW_ACTION_AGE;
6879 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6880 ret = flow_dv_validate_action_modify_ipv4_dscp
6887 /* Count all modify-header actions as one action. */
6888 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6890 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6891 modify_after_mirror = 1;
6892 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6893 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6895 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6896 ret = flow_dv_validate_action_modify_ipv6_dscp
6903 /* Count all modify-header actions as one action. */
6904 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6906 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6907 modify_after_mirror = 1;
6908 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6909 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6911 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6912 ret = flow_dv_validate_action_sample(&action_flags,
6921 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6924 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6925 if (actions[0].type != (typeof(actions[0].type))
6926 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6927 return rte_flow_error_set
6929 RTE_FLOW_ERROR_TYPE_ACTION,
6930 NULL, "MLX5 private action "
6931 "must be the first");
6933 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6935 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6936 if (!attr->transfer && !attr->group)
6937 return rte_flow_error_set(error, ENOTSUP,
6938 RTE_FLOW_ERROR_TYPE_ACTION,
6939 NULL, "modify field action "
6940 "is not supported for group 0");
6941 ret = flow_dv_validate_action_modify_field(action_flags,
6946 /* Count all modify-header actions as one action. */
6947 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6949 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6953 return rte_flow_error_set(error, ENOTSUP,
6954 RTE_FLOW_ERROR_TYPE_ACTION,
6956 "action not supported");
6960 * Validate actions in flow rules
6961 * - Explicit decap action is prohibited by the tunnel offload API.
6962 * - Drop action in tunnel steer rule is prohibited by the API.
6963 * - Application cannot use MARK action because it's value can mask
6964 * tunnel default miss nitification.
6965 * - JUMP in tunnel match rule has no support in current PMD
6967 * - TAG & META are reserved for future uses.
6969 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6970 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6971 MLX5_FLOW_ACTION_MARK |
6972 MLX5_FLOW_ACTION_SET_TAG |
6973 MLX5_FLOW_ACTION_SET_META |
6974 MLX5_FLOW_ACTION_DROP;
6976 if (action_flags & bad_actions_mask)
6977 return rte_flow_error_set
6979 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6980 "Invalid RTE action in tunnel "
6982 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6983 return rte_flow_error_set
6985 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6986 "tunnel set decap rule must terminate "
6989 return rte_flow_error_set
6991 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6992 "tunnel flows for ingress traffic only");
6994 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6995 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6996 MLX5_FLOW_ACTION_MARK |
6997 MLX5_FLOW_ACTION_SET_TAG |
6998 MLX5_FLOW_ACTION_SET_META;
7000 if (action_flags & bad_actions_mask)
7001 return rte_flow_error_set
7003 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7004 "Invalid RTE action in tunnel "
7008 * Validate the drop action mutual exclusion with other actions.
7009 * Drop action is mutually-exclusive with any other action, except for
7011 * Drop action compatibility with tunnel offload was already validated.
7013 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7014 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7015 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7016 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7017 return rte_flow_error_set(error, EINVAL,
7018 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7019 "Drop action is mutually-exclusive "
7020 "with any other action, except for "
7022 /* Eswitch has few restrictions on using items and actions */
7023 if (attr->transfer) {
7024 if (!mlx5_flow_ext_mreg_supported(dev) &&
7025 action_flags & MLX5_FLOW_ACTION_FLAG)
7026 return rte_flow_error_set(error, ENOTSUP,
7027 RTE_FLOW_ERROR_TYPE_ACTION,
7029 "unsupported action FLAG");
7030 if (!mlx5_flow_ext_mreg_supported(dev) &&
7031 action_flags & MLX5_FLOW_ACTION_MARK)
7032 return rte_flow_error_set(error, ENOTSUP,
7033 RTE_FLOW_ERROR_TYPE_ACTION,
7035 "unsupported action MARK");
7036 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7037 return rte_flow_error_set(error, ENOTSUP,
7038 RTE_FLOW_ERROR_TYPE_ACTION,
7040 "unsupported action QUEUE");
7041 if (action_flags & MLX5_FLOW_ACTION_RSS)
7042 return rte_flow_error_set(error, ENOTSUP,
7043 RTE_FLOW_ERROR_TYPE_ACTION,
7045 "unsupported action RSS");
7046 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7047 return rte_flow_error_set(error, EINVAL,
7048 RTE_FLOW_ERROR_TYPE_ACTION,
7050 "no fate action is found");
7052 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7053 return rte_flow_error_set(error, EINVAL,
7054 RTE_FLOW_ERROR_TYPE_ACTION,
7056 "no fate action is found");
7059 * Continue validation for Xcap and VLAN actions.
7060 * If hairpin is working in explicit TX rule mode, there is no actions
7061 * splitting and the validation of hairpin ingress flow should be the
7062 * same as other standard flows.
7064 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7065 MLX5_FLOW_VLAN_ACTIONS)) &&
7066 (queue_index == 0xFFFF ||
7067 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7068 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7069 conf->tx_explicit != 0))) {
7070 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7071 MLX5_FLOW_XCAP_ACTIONS)
7072 return rte_flow_error_set(error, ENOTSUP,
7073 RTE_FLOW_ERROR_TYPE_ACTION,
7074 NULL, "encap and decap "
7075 "combination aren't supported");
7076 if (!attr->transfer && attr->ingress) {
7077 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7078 return rte_flow_error_set
7080 RTE_FLOW_ERROR_TYPE_ACTION,
7081 NULL, "encap is not supported"
7082 " for ingress traffic");
7083 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7084 return rte_flow_error_set
7086 RTE_FLOW_ERROR_TYPE_ACTION,
7087 NULL, "push VLAN action not "
7088 "supported for ingress");
7089 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7090 MLX5_FLOW_VLAN_ACTIONS)
7091 return rte_flow_error_set
7093 RTE_FLOW_ERROR_TYPE_ACTION,
7094 NULL, "no support for "
7095 "multiple VLAN actions");
7099 * Hairpin flow will add one more TAG action in TX implicit mode.
7100 * In TX explicit mode, there will be no hairpin flow ID.
7103 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7104 /* extra metadata enabled: one more TAG action will be add. */
7105 if (dev_conf->dv_flow_en &&
7106 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7107 mlx5_flow_ext_mreg_supported(dev))
7108 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7110 flow_dv_modify_hdr_action_max(dev, is_root)) {
7111 return rte_flow_error_set(error, ENOTSUP,
7112 RTE_FLOW_ERROR_TYPE_ACTION,
7113 NULL, "too many header modify"
7114 " actions to support");
7116 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7117 if (fdb_mirror_limit && modify_after_mirror)
7118 return rte_flow_error_set(error, EINVAL,
7119 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7120 "sample before modify action is not supported");
7125 * Internal preparation function. Allocates the DV flow size,
7126 * this size is constant.
7129 * Pointer to the rte_eth_dev structure.
7131 * Pointer to the flow attributes.
7133 * Pointer to the list of items.
7134 * @param[in] actions
7135 * Pointer to the list of actions.
7137 * Pointer to the error structure.
7140 * Pointer to mlx5_flow object on success,
7141 * otherwise NULL and rte_errno is set.
7143 static struct mlx5_flow *
7144 flow_dv_prepare(struct rte_eth_dev *dev,
7145 const struct rte_flow_attr *attr __rte_unused,
7146 const struct rte_flow_item items[] __rte_unused,
7147 const struct rte_flow_action actions[] __rte_unused,
7148 struct rte_flow_error *error)
7150 uint32_t handle_idx = 0;
7151 struct mlx5_flow *dev_flow;
7152 struct mlx5_flow_handle *dev_handle;
7153 struct mlx5_priv *priv = dev->data->dev_private;
7154 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7157 /* In case of corrupting the memory. */
7158 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7159 rte_flow_error_set(error, ENOSPC,
7160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7161 "not free temporary device flow");
7164 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7167 rte_flow_error_set(error, ENOMEM,
7168 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7169 "not enough memory to create flow handle");
7172 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7173 dev_flow = &wks->flows[wks->flow_idx++];
7174 memset(dev_flow, 0, sizeof(*dev_flow));
7175 dev_flow->handle = dev_handle;
7176 dev_flow->handle_idx = handle_idx;
7178 * In some old rdma-core releases, before continuing, a check of the
7179 * length of matching parameter will be done at first. It needs to use
7180 * the length without misc4 param. If the flow has misc4 support, then
7181 * the length needs to be adjusted accordingly. Each param member is
7182 * aligned with a 64B boundary naturally.
7184 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7185 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7186 dev_flow->ingress = attr->ingress;
7187 dev_flow->dv.transfer = attr->transfer;
7191 #ifdef RTE_LIBRTE_MLX5_DEBUG
7193 * Sanity check for match mask and value. Similar to check_valid_spec() in
7194 * kernel driver. If unmasked bit is present in value, it returns failure.
7197 * pointer to match mask buffer.
7198 * @param match_value
7199 * pointer to match value buffer.
7202 * 0 if valid, -EINVAL otherwise.
7205 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7207 uint8_t *m = match_mask;
7208 uint8_t *v = match_value;
7211 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7214 "match_value differs from match_criteria"
7215 " %p[%u] != %p[%u]",
7216 match_value, i, match_mask, i);
7225 * Add match of ip_version.
7229 * @param[in] headers_v
7230 * Values header pointer.
7231 * @param[in] headers_m
7232 * Masks header pointer.
7233 * @param[in] ip_version
7234 * The IP version to set.
7237 flow_dv_set_match_ip_version(uint32_t group,
7243 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7245 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7247 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7248 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7249 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7253 * Add Ethernet item to matcher and to the value.
7255 * @param[in, out] matcher
7257 * @param[in, out] key
7258 * Flow matcher value.
7260 * Flow pattern to translate.
7262 * Item is inner pattern.
7265 flow_dv_translate_item_eth(void *matcher, void *key,
7266 const struct rte_flow_item *item, int inner,
7269 const struct rte_flow_item_eth *eth_m = item->mask;
7270 const struct rte_flow_item_eth *eth_v = item->spec;
7271 const struct rte_flow_item_eth nic_mask = {
7272 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7273 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7274 .type = RTE_BE16(0xffff),
7287 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7289 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7291 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7293 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7295 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7296 ð_m->dst, sizeof(eth_m->dst));
7297 /* The value must be in the range of the mask. */
7298 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7299 for (i = 0; i < sizeof(eth_m->dst); ++i)
7300 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7301 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7302 ð_m->src, sizeof(eth_m->src));
7303 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7304 /* The value must be in the range of the mask. */
7305 for (i = 0; i < sizeof(eth_m->dst); ++i)
7306 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7308 * HW supports match on one Ethertype, the Ethertype following the last
7309 * VLAN tag of the packet (see PRM).
7310 * Set match on ethertype only if ETH header is not followed by VLAN.
7311 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7312 * ethertype, and use ip_version field instead.
7313 * eCPRI over Ether layer will use type value 0xAEFE.
7315 if (eth_m->type == 0xFFFF) {
7316 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7317 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7318 switch (eth_v->type) {
7319 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7320 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7322 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7323 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7326 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7327 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7329 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7330 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7336 if (eth_m->has_vlan) {
7337 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7338 if (eth_v->has_vlan) {
7340 * Here, when also has_more_vlan field in VLAN item is
7341 * not set, only single-tagged packets will be matched.
7343 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7347 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7348 rte_be_to_cpu_16(eth_m->type));
7349 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7350 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7354 * Add VLAN item to matcher and to the value.
7356 * @param[in, out] dev_flow
7358 * @param[in, out] matcher
7360 * @param[in, out] key
7361 * Flow matcher value.
7363 * Flow pattern to translate.
7365 * Item is inner pattern.
7368 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7369 void *matcher, void *key,
7370 const struct rte_flow_item *item,
7371 int inner, uint32_t group)
7373 const struct rte_flow_item_vlan *vlan_m = item->mask;
7374 const struct rte_flow_item_vlan *vlan_v = item->spec;
7381 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7383 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7385 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7387 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7389 * This is workaround, masks are not supported,
7390 * and pre-validated.
7393 dev_flow->handle->vf_vlan.tag =
7394 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7397 * When VLAN item exists in flow, mark packet as tagged,
7398 * even if TCI is not specified.
7400 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7401 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7402 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7407 vlan_m = &rte_flow_item_vlan_mask;
7408 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7409 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7410 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7411 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7412 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7413 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7414 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7415 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7417 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7418 * ethertype, and use ip_version field instead.
7420 if (vlan_m->inner_type == 0xFFFF) {
7421 switch (vlan_v->inner_type) {
7422 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7423 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7424 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7425 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7427 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7428 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7430 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7431 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7437 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7438 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7439 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7440 /* Only one vlan_tag bit can be set. */
7441 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7444 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7445 rte_be_to_cpu_16(vlan_m->inner_type));
7446 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7447 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7451 * Add IPV4 item to matcher and to the value.
7453 * @param[in, out] matcher
7455 * @param[in, out] key
7456 * Flow matcher value.
7458 * Flow pattern to translate.
7460 * Item is inner pattern.
7462 * The group to insert the rule.
7465 flow_dv_translate_item_ipv4(void *matcher, void *key,
7466 const struct rte_flow_item *item,
7467 int inner, uint32_t group)
7469 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7470 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7471 const struct rte_flow_item_ipv4 nic_mask = {
7473 .src_addr = RTE_BE32(0xffffffff),
7474 .dst_addr = RTE_BE32(0xffffffff),
7475 .type_of_service = 0xff,
7476 .next_proto_id = 0xff,
7477 .time_to_live = 0xff,
7487 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7489 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7491 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7493 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7495 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7500 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7501 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7502 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7503 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7504 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7505 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7506 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7507 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7508 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7509 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7510 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7511 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7512 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7513 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7514 ipv4_m->hdr.type_of_service);
7515 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7516 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7517 ipv4_m->hdr.type_of_service >> 2);
7518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7519 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7520 ipv4_m->hdr.next_proto_id);
7521 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7522 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7523 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7524 ipv4_m->hdr.time_to_live);
7525 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7526 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7528 !!(ipv4_m->hdr.fragment_offset));
7529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7530 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7534 * Add IPV6 item to matcher and to the value.
7536 * @param[in, out] matcher
7538 * @param[in, out] key
7539 * Flow matcher value.
7541 * Flow pattern to translate.
7543 * Item is inner pattern.
7545 * The group to insert the rule.
7548 flow_dv_translate_item_ipv6(void *matcher, void *key,
7549 const struct rte_flow_item *item,
7550 int inner, uint32_t group)
7552 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7553 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7554 const struct rte_flow_item_ipv6 nic_mask = {
7557 "\xff\xff\xff\xff\xff\xff\xff\xff"
7558 "\xff\xff\xff\xff\xff\xff\xff\xff",
7560 "\xff\xff\xff\xff\xff\xff\xff\xff"
7561 "\xff\xff\xff\xff\xff\xff\xff\xff",
7562 .vtc_flow = RTE_BE32(0xffffffff),
7569 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7570 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7579 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7581 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7583 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7585 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7587 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7592 size = sizeof(ipv6_m->hdr.dst_addr);
7593 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7594 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7595 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7596 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7597 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7598 for (i = 0; i < size; ++i)
7599 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7600 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7601 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7602 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7603 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7604 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7605 for (i = 0; i < size; ++i)
7606 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7608 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7609 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7610 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7611 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7612 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7613 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7616 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7618 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7621 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7623 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7627 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7629 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7630 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7632 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7633 ipv6_m->hdr.hop_limits);
7634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7635 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7636 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7637 !!(ipv6_m->has_frag_ext));
7638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7639 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7643 * Add IPV6 fragment extension item to matcher and to the value.
7645 * @param[in, out] matcher
7647 * @param[in, out] key
7648 * Flow matcher value.
7650 * Flow pattern to translate.
7652 * Item is inner pattern.
7655 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7656 const struct rte_flow_item *item,
7659 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7660 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7661 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7663 .next_header = 0xff,
7664 .frag_data = RTE_BE16(0xffff),
7671 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7673 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7675 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7677 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7679 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7680 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7682 if (!ipv6_frag_ext_v)
7684 if (!ipv6_frag_ext_m)
7685 ipv6_frag_ext_m = &nic_mask;
7686 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7687 ipv6_frag_ext_m->hdr.next_header);
7688 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7689 ipv6_frag_ext_v->hdr.next_header &
7690 ipv6_frag_ext_m->hdr.next_header);
7694 * Add TCP item to matcher and to the value.
7696 * @param[in, out] matcher
7698 * @param[in, out] key
7699 * Flow matcher value.
7701 * Flow pattern to translate.
7703 * Item is inner pattern.
7706 flow_dv_translate_item_tcp(void *matcher, void *key,
7707 const struct rte_flow_item *item,
7710 const struct rte_flow_item_tcp *tcp_m = item->mask;
7711 const struct rte_flow_item_tcp *tcp_v = item->spec;
7716 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7718 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7720 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7722 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7724 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7725 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7729 tcp_m = &rte_flow_item_tcp_mask;
7730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7731 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7733 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7734 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7735 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7737 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7738 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7739 tcp_m->hdr.tcp_flags);
7740 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7741 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7745 * Add UDP item to matcher and to the value.
7747 * @param[in, out] matcher
7749 * @param[in, out] key
7750 * Flow matcher value.
7752 * Flow pattern to translate.
7754 * Item is inner pattern.
7757 flow_dv_translate_item_udp(void *matcher, void *key,
7758 const struct rte_flow_item *item,
7761 const struct rte_flow_item_udp *udp_m = item->mask;
7762 const struct rte_flow_item_udp *udp_v = item->spec;
7767 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7769 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7771 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7773 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7775 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7776 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7780 udp_m = &rte_flow_item_udp_mask;
7781 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7782 rte_be_to_cpu_16(udp_m->hdr.src_port));
7783 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7784 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7785 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7786 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7788 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7792 * Add GRE optional Key item to matcher and to the value.
7794 * @param[in, out] matcher
7796 * @param[in, out] key
7797 * Flow matcher value.
7799 * Flow pattern to translate.
7801 * Item is inner pattern.
7804 flow_dv_translate_item_gre_key(void *matcher, void *key,
7805 const struct rte_flow_item *item)
7807 const rte_be32_t *key_m = item->mask;
7808 const rte_be32_t *key_v = item->spec;
7809 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7810 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7811 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7813 /* GRE K bit must be on and should already be validated */
7814 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7815 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7819 key_m = &gre_key_default_mask;
7820 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7821 rte_be_to_cpu_32(*key_m) >> 8);
7822 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7823 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7824 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7825 rte_be_to_cpu_32(*key_m) & 0xFF);
7826 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7827 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7831 * Add GRE item to matcher and to the value.
7833 * @param[in, out] matcher
7835 * @param[in, out] key
7836 * Flow matcher value.
7838 * Flow pattern to translate.
7840 * Item is inner pattern.
7843 flow_dv_translate_item_gre(void *matcher, void *key,
7844 const struct rte_flow_item *item,
7847 const struct rte_flow_item_gre *gre_m = item->mask;
7848 const struct rte_flow_item_gre *gre_v = item->spec;
7851 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7852 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7859 uint16_t s_present:1;
7860 uint16_t k_present:1;
7861 uint16_t rsvd_bit1:1;
7862 uint16_t c_present:1;
7866 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7869 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7871 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7873 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7875 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7877 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7878 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7882 gre_m = &rte_flow_item_gre_mask;
7883 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7884 rte_be_to_cpu_16(gre_m->protocol));
7885 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7886 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7887 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7888 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7889 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7890 gre_crks_rsvd0_ver_m.c_present);
7891 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7892 gre_crks_rsvd0_ver_v.c_present &
7893 gre_crks_rsvd0_ver_m.c_present);
7894 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7895 gre_crks_rsvd0_ver_m.k_present);
7896 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7897 gre_crks_rsvd0_ver_v.k_present &
7898 gre_crks_rsvd0_ver_m.k_present);
7899 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7900 gre_crks_rsvd0_ver_m.s_present);
7901 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7902 gre_crks_rsvd0_ver_v.s_present &
7903 gre_crks_rsvd0_ver_m.s_present);
7907 * Add NVGRE item to matcher and to the value.
7909 * @param[in, out] matcher
7911 * @param[in, out] key
7912 * Flow matcher value.
7914 * Flow pattern to translate.
7916 * Item is inner pattern.
7919 flow_dv_translate_item_nvgre(void *matcher, void *key,
7920 const struct rte_flow_item *item,
7923 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7924 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7925 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7926 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7927 const char *tni_flow_id_m;
7928 const char *tni_flow_id_v;
7934 /* For NVGRE, GRE header fields must be set with defined values. */
7935 const struct rte_flow_item_gre gre_spec = {
7936 .c_rsvd0_ver = RTE_BE16(0x2000),
7937 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7939 const struct rte_flow_item_gre gre_mask = {
7940 .c_rsvd0_ver = RTE_BE16(0xB000),
7941 .protocol = RTE_BE16(UINT16_MAX),
7943 const struct rte_flow_item gre_item = {
7948 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7952 nvgre_m = &rte_flow_item_nvgre_mask;
7953 tni_flow_id_m = (const char *)nvgre_m->tni;
7954 tni_flow_id_v = (const char *)nvgre_v->tni;
7955 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7956 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7957 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7958 memcpy(gre_key_m, tni_flow_id_m, size);
7959 for (i = 0; i < size; ++i)
7960 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7964 * Add VXLAN item to matcher and to the value.
7966 * @param[in, out] matcher
7968 * @param[in, out] key
7969 * Flow matcher value.
7971 * Flow pattern to translate.
7973 * Item is inner pattern.
7976 flow_dv_translate_item_vxlan(void *matcher, void *key,
7977 const struct rte_flow_item *item,
7980 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7981 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7984 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7985 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7993 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7995 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7997 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7999 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8001 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8002 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8003 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8004 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8005 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8010 vxlan_m = &rte_flow_item_vxlan_mask;
8011 size = sizeof(vxlan_m->vni);
8012 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8013 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8014 memcpy(vni_m, vxlan_m->vni, size);
8015 for (i = 0; i < size; ++i)
8016 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8020 * Add VXLAN-GPE item to matcher and to the value.
8022 * @param[in, out] matcher
8024 * @param[in, out] key
8025 * Flow matcher value.
8027 * Flow pattern to translate.
8029 * Item is inner pattern.
8033 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8034 const struct rte_flow_item *item, int inner)
8036 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8037 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8041 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8043 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8049 uint8_t flags_m = 0xff;
8050 uint8_t flags_v = 0xc;
8053 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8055 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8059 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8061 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8062 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8063 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8064 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8065 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8070 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8071 size = sizeof(vxlan_m->vni);
8072 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8073 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8074 memcpy(vni_m, vxlan_m->vni, size);
8075 for (i = 0; i < size; ++i)
8076 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8077 if (vxlan_m->flags) {
8078 flags_m = vxlan_m->flags;
8079 flags_v = vxlan_v->flags;
8081 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8082 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8083 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8085 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8090 * Add Geneve item to matcher and to the value.
8092 * @param[in, out] matcher
8094 * @param[in, out] key
8095 * Flow matcher value.
8097 * Flow pattern to translate.
8099 * Item is inner pattern.
8103 flow_dv_translate_item_geneve(void *matcher, void *key,
8104 const struct rte_flow_item *item, int inner)
8106 const struct rte_flow_item_geneve *geneve_m = item->mask;
8107 const struct rte_flow_item_geneve *geneve_v = item->spec;
8110 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8111 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8120 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8122 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8124 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8126 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8128 dport = MLX5_UDP_PORT_GENEVE;
8129 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8130 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8131 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8136 geneve_m = &rte_flow_item_geneve_mask;
8137 size = sizeof(geneve_m->vni);
8138 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8139 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8140 memcpy(vni_m, geneve_m->vni, size);
8141 for (i = 0; i < size; ++i)
8142 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8143 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8144 rte_be_to_cpu_16(geneve_m->protocol));
8145 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8146 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8147 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8148 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8149 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8150 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8151 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8152 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8153 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8154 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8155 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8156 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8157 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8161 * Create Geneve TLV option resource.
8163 * @param dev[in, out]
8164 * Pointer to rte_eth_dev structure.
8165 * @param[in, out] tag_be24
8166 * Tag value in big endian then R-shift 8.
8167 * @parm[in, out] dev_flow
8168 * Pointer to the dev_flow.
8170 * pointer to error structure.
8173 * 0 on success otherwise -errno and errno is set.
8177 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8178 const struct rte_flow_item *item,
8179 struct rte_flow_error *error)
8181 struct mlx5_priv *priv = dev->data->dev_private;
8182 struct mlx5_dev_ctx_shared *sh = priv->sh;
8183 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8184 sh->geneve_tlv_option_resource;
8185 struct mlx5_devx_obj *obj;
8186 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8191 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8192 if (geneve_opt_resource != NULL) {
8193 if (geneve_opt_resource->option_class ==
8194 geneve_opt_v->option_class &&
8195 geneve_opt_resource->option_type ==
8196 geneve_opt_v->option_type &&
8197 geneve_opt_resource->length ==
8198 geneve_opt_v->option_len) {
8199 /* We already have GENVE TLV option obj allocated. */
8200 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8203 ret = rte_flow_error_set(error, ENOMEM,
8204 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8205 "Only one GENEVE TLV option supported");
8209 /* Create a GENEVE TLV object and resource. */
8210 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8211 geneve_opt_v->option_class,
8212 geneve_opt_v->option_type,
8213 geneve_opt_v->option_len);
8215 ret = rte_flow_error_set(error, ENODATA,
8216 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8217 "Failed to create GENEVE TLV Devx object");
8220 sh->geneve_tlv_option_resource =
8221 mlx5_malloc(MLX5_MEM_ZERO,
8222 sizeof(*geneve_opt_resource),
8224 if (!sh->geneve_tlv_option_resource) {
8225 claim_zero(mlx5_devx_cmd_destroy(obj));
8226 ret = rte_flow_error_set(error, ENOMEM,
8227 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8228 "GENEVE TLV object memory allocation failed");
8231 geneve_opt_resource = sh->geneve_tlv_option_resource;
8232 geneve_opt_resource->obj = obj;
8233 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8234 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8235 geneve_opt_resource->length = geneve_opt_v->option_len;
8236 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8240 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8245 * Add Geneve TLV option item to matcher.
8247 * @param[in, out] dev
8248 * Pointer to rte_eth_dev structure.
8249 * @param[in, out] matcher
8251 * @param[in, out] key
8252 * Flow matcher value.
8254 * Flow pattern to translate.
8256 * Pointer to error structure.
8259 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8260 void *key, const struct rte_flow_item *item,
8261 struct rte_flow_error *error)
8263 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8264 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8265 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8266 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8267 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8269 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8270 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8276 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8277 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8280 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8284 * Set the option length in GENEVE header if not requested.
8285 * The GENEVE TLV option length is expressed by the option length field
8286 * in the GENEVE header.
8287 * If the option length was not requested but the GENEVE TLV option item
8288 * is present we set the option length field implicitly.
8290 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8291 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8292 MLX5_GENEVE_OPTLEN_MASK);
8293 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8294 geneve_opt_v->option_len + 1);
8297 if (geneve_opt_v->data) {
8298 memcpy(&opt_data_key, geneve_opt_v->data,
8299 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8300 sizeof(opt_data_key)));
8301 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8302 sizeof(opt_data_key));
8303 memcpy(&opt_data_mask, geneve_opt_m->data,
8304 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8305 sizeof(opt_data_mask)));
8306 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8307 sizeof(opt_data_mask));
8308 MLX5_SET(fte_match_set_misc3, misc3_m,
8309 geneve_tlv_option_0_data,
8310 rte_be_to_cpu_32(opt_data_mask));
8311 MLX5_SET(fte_match_set_misc3, misc3_v,
8312 geneve_tlv_option_0_data,
8313 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8319 * Add MPLS item to matcher and to the value.
8321 * @param[in, out] matcher
8323 * @param[in, out] key
8324 * Flow matcher value.
8326 * Flow pattern to translate.
8327 * @param[in] prev_layer
8328 * The protocol layer indicated in previous item.
8330 * Item is inner pattern.
8333 flow_dv_translate_item_mpls(void *matcher, void *key,
8334 const struct rte_flow_item *item,
8335 uint64_t prev_layer,
8338 const uint32_t *in_mpls_m = item->mask;
8339 const uint32_t *in_mpls_v = item->spec;
8340 uint32_t *out_mpls_m = 0;
8341 uint32_t *out_mpls_v = 0;
8342 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8343 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8344 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8346 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8347 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8348 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8350 switch (prev_layer) {
8351 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8352 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8353 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8354 MLX5_UDP_PORT_MPLS);
8356 case MLX5_FLOW_LAYER_GRE:
8357 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8358 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8359 RTE_ETHER_TYPE_MPLS);
8362 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8363 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8370 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8371 switch (prev_layer) {
8372 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8374 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8375 outer_first_mpls_over_udp);
8377 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8378 outer_first_mpls_over_udp);
8380 case MLX5_FLOW_LAYER_GRE:
8382 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8383 outer_first_mpls_over_gre);
8385 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8386 outer_first_mpls_over_gre);
8389 /* Inner MPLS not over GRE is not supported. */
8392 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8396 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8402 if (out_mpls_m && out_mpls_v) {
8403 *out_mpls_m = *in_mpls_m;
8404 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8409 * Add metadata register item to matcher
8411 * @param[in, out] matcher
8413 * @param[in, out] key
8414 * Flow matcher value.
8415 * @param[in] reg_type
8416 * Type of device metadata register
8423 flow_dv_match_meta_reg(void *matcher, void *key,
8424 enum modify_reg reg_type,
8425 uint32_t data, uint32_t mask)
8428 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8430 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8436 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8437 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8440 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8441 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8445 * The metadata register C0 field might be divided into
8446 * source vport index and META item value, we should set
8447 * this field according to specified mask, not as whole one.
8449 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8451 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8452 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8455 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8458 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8459 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8462 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8463 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8466 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8467 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8470 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8471 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8474 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8475 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8478 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8479 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8482 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8483 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8492 * Add MARK item to matcher
8495 * The device to configure through.
8496 * @param[in, out] matcher
8498 * @param[in, out] key
8499 * Flow matcher value.
8501 * Flow pattern to translate.
8504 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8505 void *matcher, void *key,
8506 const struct rte_flow_item *item)
8508 struct mlx5_priv *priv = dev->data->dev_private;
8509 const struct rte_flow_item_mark *mark;
8513 mark = item->mask ? (const void *)item->mask :
8514 &rte_flow_item_mark_mask;
8515 mask = mark->id & priv->sh->dv_mark_mask;
8516 mark = (const void *)item->spec;
8518 value = mark->id & priv->sh->dv_mark_mask & mask;
8520 enum modify_reg reg;
8522 /* Get the metadata register index for the mark. */
8523 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8524 MLX5_ASSERT(reg > 0);
8525 if (reg == REG_C_0) {
8526 struct mlx5_priv *priv = dev->data->dev_private;
8527 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8528 uint32_t shl_c0 = rte_bsf32(msk_c0);
8534 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8539 * Add META item to matcher
8542 * The devich to configure through.
8543 * @param[in, out] matcher
8545 * @param[in, out] key
8546 * Flow matcher value.
8548 * Attributes of flow that includes this item.
8550 * Flow pattern to translate.
8553 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8554 void *matcher, void *key,
8555 const struct rte_flow_attr *attr,
8556 const struct rte_flow_item *item)
8558 const struct rte_flow_item_meta *meta_m;
8559 const struct rte_flow_item_meta *meta_v;
8561 meta_m = (const void *)item->mask;
8563 meta_m = &rte_flow_item_meta_mask;
8564 meta_v = (const void *)item->spec;
8567 uint32_t value = meta_v->data;
8568 uint32_t mask = meta_m->data;
8570 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8573 MLX5_ASSERT(reg != REG_NON);
8575 * In datapath code there is no endianness
8576 * coversions for perfromance reasons, all
8577 * pattern conversions are done in rte_flow.
8579 value = rte_cpu_to_be_32(value);
8580 mask = rte_cpu_to_be_32(mask);
8581 if (reg == REG_C_0) {
8582 struct mlx5_priv *priv = dev->data->dev_private;
8583 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8584 uint32_t shl_c0 = rte_bsf32(msk_c0);
8585 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8586 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8593 MLX5_ASSERT(msk_c0);
8594 MLX5_ASSERT(!(~msk_c0 & mask));
8596 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8601 * Add vport metadata Reg C0 item to matcher
8603 * @param[in, out] matcher
8605 * @param[in, out] key
8606 * Flow matcher value.
8608 * Flow pattern to translate.
8611 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8612 uint32_t value, uint32_t mask)
8614 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8618 * Add tag item to matcher
8621 * The devich to configure through.
8622 * @param[in, out] matcher
8624 * @param[in, out] key
8625 * Flow matcher value.
8627 * Flow pattern to translate.
8630 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8631 void *matcher, void *key,
8632 const struct rte_flow_item *item)
8634 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8635 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8636 uint32_t mask, value;
8639 value = tag_v->data;
8640 mask = tag_m ? tag_m->data : UINT32_MAX;
8641 if (tag_v->id == REG_C_0) {
8642 struct mlx5_priv *priv = dev->data->dev_private;
8643 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8644 uint32_t shl_c0 = rte_bsf32(msk_c0);
8650 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8654 * Add TAG item to matcher
8657 * The devich to configure through.
8658 * @param[in, out] matcher
8660 * @param[in, out] key
8661 * Flow matcher value.
8663 * Flow pattern to translate.
8666 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8667 void *matcher, void *key,
8668 const struct rte_flow_item *item)
8670 const struct rte_flow_item_tag *tag_v = item->spec;
8671 const struct rte_flow_item_tag *tag_m = item->mask;
8672 enum modify_reg reg;
8675 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8676 /* Get the metadata register index for the tag. */
8677 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8678 MLX5_ASSERT(reg > 0);
8679 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8683 * Add source vport match to the specified matcher.
8685 * @param[in, out] matcher
8687 * @param[in, out] key
8688 * Flow matcher value.
8690 * Source vport value to match
8695 flow_dv_translate_item_source_vport(void *matcher, void *key,
8696 int16_t port, uint16_t mask)
8698 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8699 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8701 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8702 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8706 * Translate port-id item to eswitch match on port-id.
8709 * The devich to configure through.
8710 * @param[in, out] matcher
8712 * @param[in, out] key
8713 * Flow matcher value.
8715 * Flow pattern to translate.
8720 * 0 on success, a negative errno value otherwise.
8723 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8724 void *key, const struct rte_flow_item *item,
8725 const struct rte_flow_attr *attr)
8727 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8728 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8729 struct mlx5_priv *priv;
8732 mask = pid_m ? pid_m->id : 0xffff;
8733 id = pid_v ? pid_v->id : dev->data->port_id;
8734 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8738 * Translate to vport field or to metadata, depending on mode.
8739 * Kernel can use either misc.source_port or half of C0 metadata
8742 if (priv->vport_meta_mask) {
8744 * Provide the hint for SW steering library
8745 * to insert the flow into ingress domain and
8746 * save the extra vport match.
8748 if (mask == 0xffff && priv->vport_id == 0xffff &&
8749 priv->pf_bond < 0 && attr->transfer)
8750 flow_dv_translate_item_source_vport
8751 (matcher, key, priv->vport_id, mask);
8753 * We should always set the vport metadata register,
8754 * otherwise the SW steering library can drop
8755 * the rule if wire vport metadata value is not zero,
8756 * it depends on kernel configuration.
8758 flow_dv_translate_item_meta_vport(matcher, key,
8759 priv->vport_meta_tag,
8760 priv->vport_meta_mask);
8762 flow_dv_translate_item_source_vport(matcher, key,
8763 priv->vport_id, mask);
8769 * Add ICMP6 item to matcher and to the value.
8771 * @param[in, out] matcher
8773 * @param[in, out] key
8774 * Flow matcher value.
8776 * Flow pattern to translate.
8778 * Item is inner pattern.
8781 flow_dv_translate_item_icmp6(void *matcher, void *key,
8782 const struct rte_flow_item *item,
8785 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8786 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8789 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8791 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8793 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8795 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8797 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8799 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8801 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8802 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8806 icmp6_m = &rte_flow_item_icmp6_mask;
8807 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8808 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8809 icmp6_v->type & icmp6_m->type);
8810 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8811 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8812 icmp6_v->code & icmp6_m->code);
8816 * Add ICMP item to matcher and to the value.
8818 * @param[in, out] matcher
8820 * @param[in, out] key
8821 * Flow matcher value.
8823 * Flow pattern to translate.
8825 * Item is inner pattern.
8828 flow_dv_translate_item_icmp(void *matcher, void *key,
8829 const struct rte_flow_item *item,
8832 const struct rte_flow_item_icmp *icmp_m = item->mask;
8833 const struct rte_flow_item_icmp *icmp_v = item->spec;
8834 uint32_t icmp_header_data_m = 0;
8835 uint32_t icmp_header_data_v = 0;
8838 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8840 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8842 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8844 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8846 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8848 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8850 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8851 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8855 icmp_m = &rte_flow_item_icmp_mask;
8856 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8857 icmp_m->hdr.icmp_type);
8858 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8859 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8860 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8861 icmp_m->hdr.icmp_code);
8862 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8863 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8864 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8865 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8866 if (icmp_header_data_m) {
8867 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8868 icmp_header_data_v |=
8869 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8870 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8871 icmp_header_data_m);
8872 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8873 icmp_header_data_v & icmp_header_data_m);
8878 * Add GTP item to matcher and to the value.
8880 * @param[in, out] matcher
8882 * @param[in, out] key
8883 * Flow matcher value.
8885 * Flow pattern to translate.
8887 * Item is inner pattern.
8890 flow_dv_translate_item_gtp(void *matcher, void *key,
8891 const struct rte_flow_item *item, int inner)
8893 const struct rte_flow_item_gtp *gtp_m = item->mask;
8894 const struct rte_flow_item_gtp *gtp_v = item->spec;
8897 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8899 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8900 uint16_t dport = RTE_GTPU_UDP_PORT;
8903 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8905 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8907 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8909 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8911 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8912 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8913 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8918 gtp_m = &rte_flow_item_gtp_mask;
8919 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8920 gtp_m->v_pt_rsv_flags);
8921 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8922 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8923 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8924 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8925 gtp_v->msg_type & gtp_m->msg_type);
8926 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8927 rte_be_to_cpu_32(gtp_m->teid));
8928 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8929 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8933 * Add GTP PSC item to matcher.
8935 * @param[in, out] matcher
8937 * @param[in, out] key
8938 * Flow matcher value.
8940 * Flow pattern to translate.
8943 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8944 const struct rte_flow_item *item)
8946 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8947 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8948 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8950 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8956 uint8_t next_ext_header_type;
8961 /* Always set E-flag match on one, regardless of GTP item settings. */
8962 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8963 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8964 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8965 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8966 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8967 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8968 /*Set next extension header type. */
8971 dw_2.next_ext_header_type = 0xff;
8972 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8973 rte_cpu_to_be_32(dw_2.w32));
8976 dw_2.next_ext_header_type = 0x85;
8977 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8978 rte_cpu_to_be_32(dw_2.w32));
8990 /*Set extension header PDU type and Qos. */
8992 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8994 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8995 dw_0.qfi = gtp_psc_m->qfi;
8996 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8997 rte_cpu_to_be_32(dw_0.w32));
8999 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9000 gtp_psc_m->pdu_type);
9001 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9002 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9003 rte_cpu_to_be_32(dw_0.w32));
9009 * Add eCPRI item to matcher and to the value.
9012 * The devich to configure through.
9013 * @param[in, out] matcher
9015 * @param[in, out] key
9016 * Flow matcher value.
9018 * Flow pattern to translate.
9019 * @param[in] samples
9020 * Sample IDs to be used in the matching.
9023 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9024 void *key, const struct rte_flow_item *item)
9026 struct mlx5_priv *priv = dev->data->dev_private;
9027 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9028 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9029 struct rte_ecpri_common_hdr common;
9030 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9032 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9040 ecpri_m = &rte_flow_item_ecpri_mask;
9042 * Maximal four DW samples are supported in a single matching now.
9043 * Two are used now for a eCPRI matching:
9044 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9045 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9048 if (!ecpri_m->hdr.common.u32)
9050 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9051 /* Need to take the whole DW as the mask to fill the entry. */
9052 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9053 prog_sample_field_value_0);
9054 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9055 prog_sample_field_value_0);
9056 /* Already big endian (network order) in the header. */
9057 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9058 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9059 /* Sample#0, used for matching type, offset 0. */
9060 MLX5_SET(fte_match_set_misc4, misc4_m,
9061 prog_sample_field_id_0, samples[0]);
9062 /* It makes no sense to set the sample ID in the mask field. */
9063 MLX5_SET(fte_match_set_misc4, misc4_v,
9064 prog_sample_field_id_0, samples[0]);
9066 * Checking if message body part needs to be matched.
9067 * Some wildcard rules only matching type field should be supported.
9069 if (ecpri_m->hdr.dummy[0]) {
9070 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9071 switch (common.type) {
9072 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9073 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9074 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9075 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9076 prog_sample_field_value_1);
9077 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9078 prog_sample_field_value_1);
9079 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9080 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9081 ecpri_m->hdr.dummy[0];
9082 /* Sample#1, to match message body, offset 4. */
9083 MLX5_SET(fte_match_set_misc4, misc4_m,
9084 prog_sample_field_id_1, samples[1]);
9085 MLX5_SET(fte_match_set_misc4, misc4_v,
9086 prog_sample_field_id_1, samples[1]);
9089 /* Others, do not match any sample ID. */
9095 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9097 #define HEADER_IS_ZERO(match_criteria, headers) \
9098 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9099 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9102 * Calculate flow matcher enable bitmap.
9104 * @param match_criteria
9105 * Pointer to flow matcher criteria.
9108 * Bitmap of enabled fields.
9111 flow_dv_matcher_enable(uint32_t *match_criteria)
9113 uint8_t match_criteria_enable;
9115 match_criteria_enable =
9116 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9117 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9118 match_criteria_enable |=
9119 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9120 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9121 match_criteria_enable |=
9122 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9123 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9124 match_criteria_enable |=
9125 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9126 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9127 match_criteria_enable |=
9128 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9129 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9130 match_criteria_enable |=
9131 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9132 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9133 return match_criteria_enable;
9136 struct mlx5_hlist_entry *
9137 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9139 struct mlx5_dev_ctx_shared *sh = list->ctx;
9140 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9141 struct rte_eth_dev *dev = ctx->dev;
9142 struct mlx5_flow_tbl_data_entry *tbl_data;
9143 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9144 struct rte_flow_error *error = ctx->error;
9145 union mlx5_flow_tbl_key key = { .v64 = key64 };
9146 struct mlx5_flow_tbl_resource *tbl;
9151 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9153 rte_flow_error_set(error, ENOMEM,
9154 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9156 "cannot allocate flow table data entry");
9159 tbl_data->idx = idx;
9160 tbl_data->tunnel = tt_prm->tunnel;
9161 tbl_data->group_id = tt_prm->group_id;
9162 tbl_data->external = !!tt_prm->external;
9163 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9164 tbl_data->is_egress = !!key.direction;
9165 tbl_data->is_transfer = !!key.domain;
9166 tbl_data->dummy = !!key.dummy;
9167 tbl_data->table_id = key.table_id;
9168 tbl = &tbl_data->tbl;
9170 return &tbl_data->entry;
9172 domain = sh->fdb_domain;
9173 else if (key.direction)
9174 domain = sh->tx_domain;
9176 domain = sh->rx_domain;
9177 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9179 rte_flow_error_set(error, ENOMEM,
9180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9181 NULL, "cannot create flow table object");
9182 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9186 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9187 (tbl->obj, &tbl_data->jump.action);
9189 rte_flow_error_set(error, ENOMEM,
9190 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9192 "cannot create flow jump action");
9193 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9194 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9198 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9199 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9201 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9202 flow_dv_matcher_create_cb,
9203 flow_dv_matcher_match_cb,
9204 flow_dv_matcher_remove_cb);
9205 return &tbl_data->entry;
9209 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9210 struct mlx5_hlist_entry *entry, uint64_t key64,
9211 void *cb_ctx __rte_unused)
9213 struct mlx5_flow_tbl_data_entry *tbl_data =
9214 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9215 union mlx5_flow_tbl_key key = { .v64 = key64 };
9217 return tbl_data->table_id != key.table_id ||
9218 tbl_data->dummy != key.dummy ||
9219 tbl_data->is_transfer != key.domain ||
9220 tbl_data->is_egress != key.direction;
9226 * @param[in, out] dev
9227 * Pointer to rte_eth_dev structure.
9228 * @param[in] table_id
9231 * Direction of the table.
9232 * @param[in] transfer
9233 * E-Switch or NIC flow.
9235 * Dummy entry for dv API.
9237 * pointer to error structure.
9240 * Returns tables resource based on the index, NULL in case of failed.
9242 struct mlx5_flow_tbl_resource *
9243 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9244 uint32_t table_id, uint8_t egress,
9247 const struct mlx5_flow_tunnel *tunnel,
9248 uint32_t group_id, uint8_t dummy,
9249 struct rte_flow_error *error)
9251 struct mlx5_priv *priv = dev->data->dev_private;
9252 union mlx5_flow_tbl_key table_key = {
9254 .table_id = table_id,
9256 .domain = !!transfer,
9257 .direction = !!egress,
9260 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9262 .group_id = group_id,
9263 .external = external,
9265 struct mlx5_flow_cb_ctx ctx = {
9270 struct mlx5_hlist_entry *entry;
9271 struct mlx5_flow_tbl_data_entry *tbl_data;
9273 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9275 rte_flow_error_set(error, ENOMEM,
9276 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9277 "cannot get table");
9280 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9281 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9282 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9283 return &tbl_data->tbl;
9287 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9288 struct mlx5_hlist_entry *entry)
9290 struct mlx5_dev_ctx_shared *sh = list->ctx;
9291 struct mlx5_flow_tbl_data_entry *tbl_data =
9292 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9294 MLX5_ASSERT(entry && sh);
9295 if (tbl_data->jump.action)
9296 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9297 if (tbl_data->tbl.obj)
9298 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9299 if (tbl_data->tunnel_offload && tbl_data->external) {
9300 struct mlx5_hlist_entry *he;
9301 struct mlx5_hlist *tunnel_grp_hash;
9302 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9303 union tunnel_tbl_key tunnel_key = {
9304 .tunnel_id = tbl_data->tunnel ?
9305 tbl_data->tunnel->tunnel_id : 0,
9306 .group = tbl_data->group_id
9308 uint32_t table_id = tbl_data->table_id;
9310 tunnel_grp_hash = tbl_data->tunnel ?
9311 tbl_data->tunnel->groups :
9313 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9315 mlx5_hlist_unregister(tunnel_grp_hash, he);
9317 "Table_id %u tunnel %u group %u released.",
9320 tbl_data->tunnel->tunnel_id : 0,
9321 tbl_data->group_id);
9323 mlx5_cache_list_destroy(&tbl_data->matchers);
9324 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9328 * Release a flow table.
9331 * Pointer to device shared structure.
9333 * Table resource to be released.
9336 * Returns 0 if table was released, else return 1;
9339 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9340 struct mlx5_flow_tbl_resource *tbl)
9342 struct mlx5_flow_tbl_data_entry *tbl_data =
9343 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9347 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9351 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9352 struct mlx5_cache_entry *entry, void *cb_ctx)
9354 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9355 struct mlx5_flow_dv_matcher *ref = ctx->data;
9356 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9359 return cur->crc != ref->crc ||
9360 cur->priority != ref->priority ||
9361 memcmp((const void *)cur->mask.buf,
9362 (const void *)ref->mask.buf, ref->mask.size);
9365 struct mlx5_cache_entry *
9366 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9367 struct mlx5_cache_entry *entry __rte_unused,
9370 struct mlx5_dev_ctx_shared *sh = list->ctx;
9371 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9372 struct mlx5_flow_dv_matcher *ref = ctx->data;
9373 struct mlx5_flow_dv_matcher *cache;
9374 struct mlx5dv_flow_matcher_attr dv_attr = {
9375 .type = IBV_FLOW_ATTR_NORMAL,
9376 .match_mask = (void *)&ref->mask,
9378 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9382 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9384 rte_flow_error_set(ctx->error, ENOMEM,
9385 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9386 "cannot create matcher");
9390 dv_attr.match_criteria_enable =
9391 flow_dv_matcher_enable(cache->mask.buf);
9392 dv_attr.priority = ref->priority;
9394 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9395 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9396 &cache->matcher_object);
9399 rte_flow_error_set(ctx->error, ENOMEM,
9400 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9401 "cannot create matcher");
9404 return &cache->entry;
9408 * Register the flow matcher.
9410 * @param[in, out] dev
9411 * Pointer to rte_eth_dev structure.
9412 * @param[in, out] matcher
9413 * Pointer to flow matcher.
9414 * @param[in, out] key
9415 * Pointer to flow table key.
9416 * @parm[in, out] dev_flow
9417 * Pointer to the dev_flow.
9419 * pointer to error structure.
9422 * 0 on success otherwise -errno and errno is set.
9425 flow_dv_matcher_register(struct rte_eth_dev *dev,
9426 struct mlx5_flow_dv_matcher *ref,
9427 union mlx5_flow_tbl_key *key,
9428 struct mlx5_flow *dev_flow,
9429 const struct mlx5_flow_tunnel *tunnel,
9431 struct rte_flow_error *error)
9433 struct mlx5_cache_entry *entry;
9434 struct mlx5_flow_dv_matcher *cache;
9435 struct mlx5_flow_tbl_resource *tbl;
9436 struct mlx5_flow_tbl_data_entry *tbl_data;
9437 struct mlx5_flow_cb_ctx ctx = {
9443 * tunnel offload API requires this registration for cases when
9444 * tunnel match rule was inserted before tunnel set rule.
9446 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9447 key->direction, key->domain,
9448 dev_flow->external, tunnel,
9449 group_id, 0, error);
9451 return -rte_errno; /* No need to refill the error info */
9452 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9454 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9456 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9457 return rte_flow_error_set(error, ENOMEM,
9458 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9459 "cannot allocate ref memory");
9461 cache = container_of(entry, typeof(*cache), entry);
9462 dev_flow->handle->dvh.matcher = cache;
9466 struct mlx5_hlist_entry *
9467 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9469 struct mlx5_dev_ctx_shared *sh = list->ctx;
9470 struct rte_flow_error *error = ctx;
9471 struct mlx5_flow_dv_tag_resource *entry;
9475 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9477 rte_flow_error_set(error, ENOMEM,
9478 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9479 "cannot allocate resource memory");
9483 entry->tag_id = key;
9484 ret = mlx5_flow_os_create_flow_action_tag(key,
9487 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9488 rte_flow_error_set(error, ENOMEM,
9489 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9490 NULL, "cannot create action");
9493 return &entry->entry;
9497 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9498 struct mlx5_hlist_entry *entry, uint64_t key,
9499 void *cb_ctx __rte_unused)
9501 struct mlx5_flow_dv_tag_resource *tag =
9502 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9504 return key != tag->tag_id;
9508 * Find existing tag resource or create and register a new one.
9510 * @param dev[in, out]
9511 * Pointer to rte_eth_dev structure.
9512 * @param[in, out] tag_be24
9513 * Tag value in big endian then R-shift 8.
9514 * @parm[in, out] dev_flow
9515 * Pointer to the dev_flow.
9517 * pointer to error structure.
9520 * 0 on success otherwise -errno and errno is set.
9523 flow_dv_tag_resource_register
9524 (struct rte_eth_dev *dev,
9526 struct mlx5_flow *dev_flow,
9527 struct rte_flow_error *error)
9529 struct mlx5_priv *priv = dev->data->dev_private;
9530 struct mlx5_flow_dv_tag_resource *cache_resource;
9531 struct mlx5_hlist_entry *entry;
9533 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9535 cache_resource = container_of
9536 (entry, struct mlx5_flow_dv_tag_resource, entry);
9537 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9538 dev_flow->dv.tag_resource = cache_resource;
9545 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9546 struct mlx5_hlist_entry *entry)
9548 struct mlx5_dev_ctx_shared *sh = list->ctx;
9549 struct mlx5_flow_dv_tag_resource *tag =
9550 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9552 MLX5_ASSERT(tag && sh && tag->action);
9553 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9554 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9555 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9562 * Pointer to Ethernet device.
9567 * 1 while a reference on it exists, 0 when freed.
9570 flow_dv_tag_release(struct rte_eth_dev *dev,
9573 struct mlx5_priv *priv = dev->data->dev_private;
9574 struct mlx5_flow_dv_tag_resource *tag;
9576 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9579 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9580 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9581 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9585 * Translate port ID action to vport.
9588 * Pointer to rte_eth_dev structure.
9590 * Pointer to the port ID action.
9591 * @param[out] dst_port_id
9592 * The target port ID.
9594 * Pointer to the error structure.
9597 * 0 on success, a negative errno value otherwise and rte_errno is set.
9600 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9601 const struct rte_flow_action *action,
9602 uint32_t *dst_port_id,
9603 struct rte_flow_error *error)
9606 struct mlx5_priv *priv;
9607 const struct rte_flow_action_port_id *conf =
9608 (const struct rte_flow_action_port_id *)action->conf;
9610 port = conf->original ? dev->data->port_id : conf->id;
9611 priv = mlx5_port_to_eswitch_info(port, false);
9613 return rte_flow_error_set(error, -rte_errno,
9614 RTE_FLOW_ERROR_TYPE_ACTION,
9616 "No eswitch info was found for port");
9617 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9619 * This parameter is transferred to
9620 * mlx5dv_dr_action_create_dest_ib_port().
9622 *dst_port_id = priv->dev_port;
9625 * Legacy mode, no LAG configurations is supported.
9626 * This parameter is transferred to
9627 * mlx5dv_dr_action_create_dest_vport().
9629 *dst_port_id = priv->vport_id;
9635 * Create a counter with aging configuration.
9638 * Pointer to rte_eth_dev structure.
9640 * Pointer to the counter action configuration.
9642 * Pointer to the aging action configuration.
9645 * Index to flow counter on success, 0 otherwise.
9648 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9649 struct mlx5_flow *dev_flow,
9650 const struct rte_flow_action_count *count,
9651 const struct rte_flow_action_age *age)
9654 struct mlx5_age_param *age_param;
9656 if (count && count->shared)
9657 counter = flow_dv_counter_get_shared(dev, count->id);
9659 counter = flow_dv_counter_alloc(dev, !!age);
9660 if (!counter || age == NULL)
9662 age_param = flow_dv_counter_idx_get_age(dev, counter);
9663 age_param->context = age->context ? age->context :
9664 (void *)(uintptr_t)(dev_flow->flow_idx);
9665 age_param->timeout = age->timeout;
9666 age_param->port_id = dev->data->port_id;
9667 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9668 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9673 * Add Tx queue matcher
9676 * Pointer to the dev struct.
9677 * @param[in, out] matcher
9679 * @param[in, out] key
9680 * Flow matcher value.
9682 * Flow pattern to translate.
9684 * Item is inner pattern.
9687 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9688 void *matcher, void *key,
9689 const struct rte_flow_item *item)
9691 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9692 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9694 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9696 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9697 struct mlx5_txq_ctrl *txq;
9701 queue_m = (const void *)item->mask;
9704 queue_v = (const void *)item->spec;
9707 txq = mlx5_txq_get(dev, queue_v->queue);
9710 queue = txq->obj->sq->id;
9711 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9712 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9713 queue & queue_m->queue);
9714 mlx5_txq_release(dev, queue_v->queue);
9718 * Set the hash fields according to the @p flow information.
9720 * @param[in] dev_flow
9721 * Pointer to the mlx5_flow.
9722 * @param[in] rss_desc
9723 * Pointer to the mlx5_flow_rss_desc.
9726 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9727 struct mlx5_flow_rss_desc *rss_desc)
9729 uint64_t items = dev_flow->handle->layers;
9731 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9733 dev_flow->hash_fields = 0;
9734 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9735 if (rss_desc->level >= 2) {
9736 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9740 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9741 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9742 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9743 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9744 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9745 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9746 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9748 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9750 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9751 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9752 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9753 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9754 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9755 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9756 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9758 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9761 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9762 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9763 if (rss_types & ETH_RSS_UDP) {
9764 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9765 dev_flow->hash_fields |=
9766 IBV_RX_HASH_SRC_PORT_UDP;
9767 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9768 dev_flow->hash_fields |=
9769 IBV_RX_HASH_DST_PORT_UDP;
9771 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9773 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9774 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9775 if (rss_types & ETH_RSS_TCP) {
9776 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9777 dev_flow->hash_fields |=
9778 IBV_RX_HASH_SRC_PORT_TCP;
9779 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9780 dev_flow->hash_fields |=
9781 IBV_RX_HASH_DST_PORT_TCP;
9783 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9789 * Prepare an Rx Hash queue.
9792 * Pointer to Ethernet device.
9793 * @param[in] dev_flow
9794 * Pointer to the mlx5_flow.
9795 * @param[in] rss_desc
9796 * Pointer to the mlx5_flow_rss_desc.
9797 * @param[out] hrxq_idx
9798 * Hash Rx queue index.
9801 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9803 static struct mlx5_hrxq *
9804 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9805 struct mlx5_flow *dev_flow,
9806 struct mlx5_flow_rss_desc *rss_desc,
9809 struct mlx5_priv *priv = dev->data->dev_private;
9810 struct mlx5_flow_handle *dh = dev_flow->handle;
9811 struct mlx5_hrxq *hrxq;
9813 MLX5_ASSERT(rss_desc->queue_num);
9814 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9815 rss_desc->hash_fields = dev_flow->hash_fields;
9816 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9817 rss_desc->shared_rss = 0;
9818 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9821 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9827 * Release sample sub action resource.
9829 * @param[in, out] dev
9830 * Pointer to rte_eth_dev structure.
9831 * @param[in] act_res
9832 * Pointer to sample sub action resource.
9835 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9836 struct mlx5_flow_sub_actions_idx *act_res)
9838 if (act_res->rix_hrxq) {
9839 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9840 act_res->rix_hrxq = 0;
9842 if (act_res->rix_encap_decap) {
9843 flow_dv_encap_decap_resource_release(dev,
9844 act_res->rix_encap_decap);
9845 act_res->rix_encap_decap = 0;
9847 if (act_res->rix_port_id_action) {
9848 flow_dv_port_id_action_resource_release(dev,
9849 act_res->rix_port_id_action);
9850 act_res->rix_port_id_action = 0;
9852 if (act_res->rix_tag) {
9853 flow_dv_tag_release(dev, act_res->rix_tag);
9854 act_res->rix_tag = 0;
9856 if (act_res->rix_jump) {
9857 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9858 act_res->rix_jump = 0;
9863 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9864 struct mlx5_cache_entry *entry, void *cb_ctx)
9866 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9867 struct rte_eth_dev *dev = ctx->dev;
9868 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9869 struct mlx5_flow_dv_sample_resource *cache_resource =
9870 container_of(entry, typeof(*cache_resource), entry);
9872 if (resource->ratio == cache_resource->ratio &&
9873 resource->ft_type == cache_resource->ft_type &&
9874 resource->ft_id == cache_resource->ft_id &&
9875 resource->set_action == cache_resource->set_action &&
9876 !memcmp((void *)&resource->sample_act,
9877 (void *)&cache_resource->sample_act,
9878 sizeof(struct mlx5_flow_sub_actions_list))) {
9880 * Existing sample action should release the prepared
9881 * sub-actions reference counter.
9883 flow_dv_sample_sub_actions_release(dev,
9884 &resource->sample_idx);
9890 struct mlx5_cache_entry *
9891 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9892 struct mlx5_cache_entry *entry __rte_unused,
9895 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9896 struct rte_eth_dev *dev = ctx->dev;
9897 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9898 void **sample_dv_actions = resource->sub_actions;
9899 struct mlx5_flow_dv_sample_resource *cache_resource;
9900 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9901 struct mlx5_priv *priv = dev->data->dev_private;
9902 struct mlx5_dev_ctx_shared *sh = priv->sh;
9903 struct mlx5_flow_tbl_resource *tbl;
9905 const uint32_t next_ft_step = 1;
9906 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9907 uint8_t is_egress = 0;
9908 uint8_t is_transfer = 0;
9909 struct rte_flow_error *error = ctx->error;
9911 /* Register new sample resource. */
9912 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9913 if (!cache_resource) {
9914 rte_flow_error_set(error, ENOMEM,
9915 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9917 "cannot allocate resource memory");
9920 *cache_resource = *resource;
9921 /* Create normal path table level */
9922 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9924 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9926 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9927 is_egress, is_transfer,
9928 true, NULL, 0, 0, error);
9930 rte_flow_error_set(error, ENOMEM,
9931 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9933 "fail to create normal path table "
9937 cache_resource->normal_path_tbl = tbl;
9938 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9939 if (!sh->default_miss_action) {
9940 rte_flow_error_set(error, ENOMEM,
9941 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9943 "default miss action was not "
9947 sample_dv_actions[resource->sample_act.actions_num++] =
9948 sh->default_miss_action;
9950 /* Create a DR sample action */
9951 sampler_attr.sample_ratio = cache_resource->ratio;
9952 sampler_attr.default_next_table = tbl->obj;
9953 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9954 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9955 &sample_dv_actions[0];
9956 sampler_attr.action = cache_resource->set_action;
9957 if (mlx5_os_flow_dr_create_flow_action_sampler
9958 (&sampler_attr, &cache_resource->verbs_action)) {
9959 rte_flow_error_set(error, ENOMEM,
9960 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9961 NULL, "cannot create sample action");
9964 cache_resource->idx = idx;
9965 cache_resource->dev = dev;
9966 return &cache_resource->entry;
9968 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9969 flow_dv_sample_sub_actions_release(dev,
9970 &cache_resource->sample_idx);
9971 if (cache_resource->normal_path_tbl)
9972 flow_dv_tbl_resource_release(MLX5_SH(dev),
9973 cache_resource->normal_path_tbl);
9974 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9980 * Find existing sample resource or create and register a new one.
9982 * @param[in, out] dev
9983 * Pointer to rte_eth_dev structure.
9984 * @param[in] resource
9985 * Pointer to sample resource.
9986 * @parm[in, out] dev_flow
9987 * Pointer to the dev_flow.
9989 * pointer to error structure.
9992 * 0 on success otherwise -errno and errno is set.
9995 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9996 struct mlx5_flow_dv_sample_resource *resource,
9997 struct mlx5_flow *dev_flow,
9998 struct rte_flow_error *error)
10000 struct mlx5_flow_dv_sample_resource *cache_resource;
10001 struct mlx5_cache_entry *entry;
10002 struct mlx5_priv *priv = dev->data->dev_private;
10003 struct mlx5_flow_cb_ctx ctx = {
10009 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10012 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10013 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10014 dev_flow->dv.sample_res = cache_resource;
10019 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10020 struct mlx5_cache_entry *entry, void *cb_ctx)
10022 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10023 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10024 struct rte_eth_dev *dev = ctx->dev;
10025 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10026 container_of(entry, typeof(*cache_resource), entry);
10029 if (resource->num_of_dest == cache_resource->num_of_dest &&
10030 resource->ft_type == cache_resource->ft_type &&
10031 !memcmp((void *)cache_resource->sample_act,
10032 (void *)resource->sample_act,
10033 (resource->num_of_dest *
10034 sizeof(struct mlx5_flow_sub_actions_list)))) {
10036 * Existing sample action should release the prepared
10037 * sub-actions reference counter.
10039 for (idx = 0; idx < resource->num_of_dest; idx++)
10040 flow_dv_sample_sub_actions_release(dev,
10041 &resource->sample_idx[idx]);
10047 struct mlx5_cache_entry *
10048 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10049 struct mlx5_cache_entry *entry __rte_unused,
10052 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10053 struct rte_eth_dev *dev = ctx->dev;
10054 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10055 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10056 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10057 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10058 struct mlx5_priv *priv = dev->data->dev_private;
10059 struct mlx5_dev_ctx_shared *sh = priv->sh;
10060 struct mlx5_flow_sub_actions_list *sample_act;
10061 struct mlx5dv_dr_domain *domain;
10062 uint32_t idx = 0, res_idx = 0;
10063 struct rte_flow_error *error = ctx->error;
10064 uint64_t action_flags;
10067 /* Register new destination array resource. */
10068 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10070 if (!cache_resource) {
10071 rte_flow_error_set(error, ENOMEM,
10072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10074 "cannot allocate resource memory");
10077 *cache_resource = *resource;
10078 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10079 domain = sh->fdb_domain;
10080 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10081 domain = sh->rx_domain;
10083 domain = sh->tx_domain;
10084 for (idx = 0; idx < resource->num_of_dest; idx++) {
10085 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10086 mlx5_malloc(MLX5_MEM_ZERO,
10087 sizeof(struct mlx5dv_dr_action_dest_attr),
10089 if (!dest_attr[idx]) {
10090 rte_flow_error_set(error, ENOMEM,
10091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10093 "cannot allocate resource memory");
10096 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10097 sample_act = &resource->sample_act[idx];
10098 action_flags = sample_act->action_flags;
10099 switch (action_flags) {
10100 case MLX5_FLOW_ACTION_QUEUE:
10101 dest_attr[idx]->dest = sample_act->dr_queue_action;
10103 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10104 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10105 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10106 dest_attr[idx]->dest_reformat->reformat =
10107 sample_act->dr_encap_action;
10108 dest_attr[idx]->dest_reformat->dest =
10109 sample_act->dr_port_id_action;
10111 case MLX5_FLOW_ACTION_PORT_ID:
10112 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10114 case MLX5_FLOW_ACTION_JUMP:
10115 dest_attr[idx]->dest = sample_act->dr_jump_action;
10118 rte_flow_error_set(error, EINVAL,
10119 RTE_FLOW_ERROR_TYPE_ACTION,
10121 "unsupported actions type");
10125 /* create a dest array actioin */
10126 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10128 cache_resource->num_of_dest,
10130 &cache_resource->action);
10132 rte_flow_error_set(error, ENOMEM,
10133 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10135 "cannot create destination array action");
10138 cache_resource->idx = res_idx;
10139 cache_resource->dev = dev;
10140 for (idx = 0; idx < resource->num_of_dest; idx++)
10141 mlx5_free(dest_attr[idx]);
10142 return &cache_resource->entry;
10144 for (idx = 0; idx < resource->num_of_dest; idx++) {
10145 struct mlx5_flow_sub_actions_idx *act_res =
10146 &cache_resource->sample_idx[idx];
10147 if (act_res->rix_hrxq &&
10148 !mlx5_hrxq_release(dev,
10149 act_res->rix_hrxq))
10150 act_res->rix_hrxq = 0;
10151 if (act_res->rix_encap_decap &&
10152 !flow_dv_encap_decap_resource_release(dev,
10153 act_res->rix_encap_decap))
10154 act_res->rix_encap_decap = 0;
10155 if (act_res->rix_port_id_action &&
10156 !flow_dv_port_id_action_resource_release(dev,
10157 act_res->rix_port_id_action))
10158 act_res->rix_port_id_action = 0;
10159 if (act_res->rix_jump &&
10160 !flow_dv_jump_tbl_resource_release(dev,
10161 act_res->rix_jump))
10162 act_res->rix_jump = 0;
10163 if (dest_attr[idx])
10164 mlx5_free(dest_attr[idx]);
10167 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10172 * Find existing destination array resource or create and register a new one.
10174 * @param[in, out] dev
10175 * Pointer to rte_eth_dev structure.
10176 * @param[in] resource
10177 * Pointer to destination array resource.
10178 * @parm[in, out] dev_flow
10179 * Pointer to the dev_flow.
10180 * @param[out] error
10181 * pointer to error structure.
10184 * 0 on success otherwise -errno and errno is set.
10187 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10188 struct mlx5_flow_dv_dest_array_resource *resource,
10189 struct mlx5_flow *dev_flow,
10190 struct rte_flow_error *error)
10192 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10193 struct mlx5_priv *priv = dev->data->dev_private;
10194 struct mlx5_cache_entry *entry;
10195 struct mlx5_flow_cb_ctx ctx = {
10201 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10204 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10205 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10206 dev_flow->dv.dest_array_res = cache_resource;
10211 * Convert Sample action to DV specification.
10214 * Pointer to rte_eth_dev structure.
10215 * @param[in] action
10216 * Pointer to sample action structure.
10217 * @param[in, out] dev_flow
10218 * Pointer to the mlx5_flow.
10220 * Pointer to the flow attributes.
10221 * @param[in, out] num_of_dest
10222 * Pointer to the num of destination.
10223 * @param[in, out] sample_actions
10224 * Pointer to sample actions list.
10225 * @param[in, out] res
10226 * Pointer to sample resource.
10227 * @param[out] error
10228 * Pointer to the error structure.
10231 * 0 on success, a negative errno value otherwise and rte_errno is set.
10234 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10235 const struct rte_flow_action_sample *action,
10236 struct mlx5_flow *dev_flow,
10237 const struct rte_flow_attr *attr,
10238 uint32_t *num_of_dest,
10239 void **sample_actions,
10240 struct mlx5_flow_dv_sample_resource *res,
10241 struct rte_flow_error *error)
10243 struct mlx5_priv *priv = dev->data->dev_private;
10244 const struct rte_flow_action *sub_actions;
10245 struct mlx5_flow_sub_actions_list *sample_act;
10246 struct mlx5_flow_sub_actions_idx *sample_idx;
10247 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10248 struct rte_flow *flow = dev_flow->flow;
10249 struct mlx5_flow_rss_desc *rss_desc;
10250 uint64_t action_flags = 0;
10253 rss_desc = &wks->rss_desc;
10254 sample_act = &res->sample_act;
10255 sample_idx = &res->sample_idx;
10256 res->ratio = action->ratio;
10257 sub_actions = action->actions;
10258 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10259 int type = sub_actions->type;
10260 uint32_t pre_rix = 0;
10263 case RTE_FLOW_ACTION_TYPE_QUEUE:
10265 const struct rte_flow_action_queue *queue;
10266 struct mlx5_hrxq *hrxq;
10269 queue = sub_actions->conf;
10270 rss_desc->queue_num = 1;
10271 rss_desc->queue[0] = queue->index;
10272 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10273 rss_desc, &hrxq_idx);
10275 return rte_flow_error_set
10277 RTE_FLOW_ERROR_TYPE_ACTION,
10279 "cannot create fate queue");
10280 sample_act->dr_queue_action = hrxq->action;
10281 sample_idx->rix_hrxq = hrxq_idx;
10282 sample_actions[sample_act->actions_num++] =
10285 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10286 if (action_flags & MLX5_FLOW_ACTION_MARK)
10287 dev_flow->handle->rix_hrxq = hrxq_idx;
10288 dev_flow->handle->fate_action =
10289 MLX5_FLOW_FATE_QUEUE;
10292 case RTE_FLOW_ACTION_TYPE_RSS:
10294 struct mlx5_hrxq *hrxq;
10296 const struct rte_flow_action_rss *rss;
10297 const uint8_t *rss_key;
10299 rss = sub_actions->conf;
10300 memcpy(rss_desc->queue, rss->queue,
10301 rss->queue_num * sizeof(uint16_t));
10302 rss_desc->queue_num = rss->queue_num;
10303 /* NULL RSS key indicates default RSS key. */
10304 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10305 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10307 * rss->level and rss.types should be set in advance
10308 * when expanding items for RSS.
10310 flow_dv_hashfields_set(dev_flow, rss_desc);
10311 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10312 rss_desc, &hrxq_idx);
10314 return rte_flow_error_set
10316 RTE_FLOW_ERROR_TYPE_ACTION,
10318 "cannot create fate queue");
10319 sample_act->dr_queue_action = hrxq->action;
10320 sample_idx->rix_hrxq = hrxq_idx;
10321 sample_actions[sample_act->actions_num++] =
10324 action_flags |= MLX5_FLOW_ACTION_RSS;
10325 if (action_flags & MLX5_FLOW_ACTION_MARK)
10326 dev_flow->handle->rix_hrxq = hrxq_idx;
10327 dev_flow->handle->fate_action =
10328 MLX5_FLOW_FATE_QUEUE;
10331 case RTE_FLOW_ACTION_TYPE_MARK:
10333 uint32_t tag_be = mlx5_flow_mark_set
10334 (((const struct rte_flow_action_mark *)
10335 (sub_actions->conf))->id);
10337 dev_flow->handle->mark = 1;
10338 pre_rix = dev_flow->handle->dvh.rix_tag;
10339 /* Save the mark resource before sample */
10340 pre_r = dev_flow->dv.tag_resource;
10341 if (flow_dv_tag_resource_register(dev, tag_be,
10344 MLX5_ASSERT(dev_flow->dv.tag_resource);
10345 sample_act->dr_tag_action =
10346 dev_flow->dv.tag_resource->action;
10347 sample_idx->rix_tag =
10348 dev_flow->handle->dvh.rix_tag;
10349 sample_actions[sample_act->actions_num++] =
10350 sample_act->dr_tag_action;
10351 /* Recover the mark resource after sample */
10352 dev_flow->dv.tag_resource = pre_r;
10353 dev_flow->handle->dvh.rix_tag = pre_rix;
10354 action_flags |= MLX5_FLOW_ACTION_MARK;
10357 case RTE_FLOW_ACTION_TYPE_COUNT:
10359 if (!flow->counter) {
10361 flow_dv_translate_create_counter(dev,
10362 dev_flow, sub_actions->conf,
10364 if (!flow->counter)
10365 return rte_flow_error_set
10367 RTE_FLOW_ERROR_TYPE_ACTION,
10369 "cannot create counter"
10372 sample_act->dr_cnt_action =
10373 (flow_dv_counter_get_by_idx(dev,
10374 flow->counter, NULL))->action;
10375 sample_actions[sample_act->actions_num++] =
10376 sample_act->dr_cnt_action;
10377 action_flags |= MLX5_FLOW_ACTION_COUNT;
10380 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10382 struct mlx5_flow_dv_port_id_action_resource
10384 uint32_t port_id = 0;
10386 memset(&port_id_resource, 0, sizeof(port_id_resource));
10387 /* Save the port id resource before sample */
10388 pre_rix = dev_flow->handle->rix_port_id_action;
10389 pre_r = dev_flow->dv.port_id_action;
10390 if (flow_dv_translate_action_port_id(dev, sub_actions,
10393 port_id_resource.port_id = port_id;
10394 if (flow_dv_port_id_action_resource_register
10395 (dev, &port_id_resource, dev_flow, error))
10397 sample_act->dr_port_id_action =
10398 dev_flow->dv.port_id_action->action;
10399 sample_idx->rix_port_id_action =
10400 dev_flow->handle->rix_port_id_action;
10401 sample_actions[sample_act->actions_num++] =
10402 sample_act->dr_port_id_action;
10403 /* Recover the port id resource after sample */
10404 dev_flow->dv.port_id_action = pre_r;
10405 dev_flow->handle->rix_port_id_action = pre_rix;
10407 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10410 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10411 /* Save the encap resource before sample */
10412 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10413 pre_r = dev_flow->dv.encap_decap;
10414 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10419 sample_act->dr_encap_action =
10420 dev_flow->dv.encap_decap->action;
10421 sample_idx->rix_encap_decap =
10422 dev_flow->handle->dvh.rix_encap_decap;
10423 sample_actions[sample_act->actions_num++] =
10424 sample_act->dr_encap_action;
10425 /* Recover the encap resource after sample */
10426 dev_flow->dv.encap_decap = pre_r;
10427 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10428 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10431 return rte_flow_error_set(error, EINVAL,
10432 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10434 "Not support for sampler action");
10437 sample_act->action_flags = action_flags;
10438 res->ft_id = dev_flow->dv.group;
10439 if (attr->transfer) {
10441 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10442 uint64_t set_action;
10443 } action_ctx = { .set_action = 0 };
10445 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10446 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10447 MLX5_MODIFICATION_TYPE_SET);
10448 MLX5_SET(set_action_in, action_ctx.action_in, field,
10449 MLX5_MODI_META_REG_C_0);
10450 MLX5_SET(set_action_in, action_ctx.action_in, data,
10451 priv->vport_meta_tag);
10452 res->set_action = action_ctx.set_action;
10453 } else if (attr->ingress) {
10454 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10456 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10462 * Convert Sample action to DV specification.
10465 * Pointer to rte_eth_dev structure.
10466 * @param[in, out] dev_flow
10467 * Pointer to the mlx5_flow.
10468 * @param[in] num_of_dest
10469 * The num of destination.
10470 * @param[in, out] res
10471 * Pointer to sample resource.
10472 * @param[in, out] mdest_res
10473 * Pointer to destination array resource.
10474 * @param[in] sample_actions
10475 * Pointer to sample path actions list.
10476 * @param[in] action_flags
10477 * Holds the actions detected until now.
10478 * @param[out] error
10479 * Pointer to the error structure.
10482 * 0 on success, a negative errno value otherwise and rte_errno is set.
10485 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10486 struct mlx5_flow *dev_flow,
10487 uint32_t num_of_dest,
10488 struct mlx5_flow_dv_sample_resource *res,
10489 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10490 void **sample_actions,
10491 uint64_t action_flags,
10492 struct rte_flow_error *error)
10494 /* update normal path action resource into last index of array */
10495 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10496 struct mlx5_flow_sub_actions_list *sample_act =
10497 &mdest_res->sample_act[dest_index];
10498 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10499 struct mlx5_flow_rss_desc *rss_desc;
10500 uint32_t normal_idx = 0;
10501 struct mlx5_hrxq *hrxq;
10505 rss_desc = &wks->rss_desc;
10506 if (num_of_dest > 1) {
10507 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10508 /* Handle QP action for mirroring */
10509 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10510 rss_desc, &hrxq_idx);
10512 return rte_flow_error_set
10514 RTE_FLOW_ERROR_TYPE_ACTION,
10516 "cannot create rx queue");
10518 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10519 sample_act->dr_queue_action = hrxq->action;
10520 if (action_flags & MLX5_FLOW_ACTION_MARK)
10521 dev_flow->handle->rix_hrxq = hrxq_idx;
10522 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10524 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10526 mdest_res->sample_idx[dest_index].rix_encap_decap =
10527 dev_flow->handle->dvh.rix_encap_decap;
10528 sample_act->dr_encap_action =
10529 dev_flow->dv.encap_decap->action;
10531 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10533 mdest_res->sample_idx[dest_index].rix_port_id_action =
10534 dev_flow->handle->rix_port_id_action;
10535 sample_act->dr_port_id_action =
10536 dev_flow->dv.port_id_action->action;
10538 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10540 mdest_res->sample_idx[dest_index].rix_jump =
10541 dev_flow->handle->rix_jump;
10542 sample_act->dr_jump_action =
10543 dev_flow->dv.jump->action;
10544 dev_flow->handle->rix_jump = 0;
10546 sample_act->actions_num = normal_idx;
10547 /* update sample action resource into first index of array */
10548 mdest_res->ft_type = res->ft_type;
10549 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10550 sizeof(struct mlx5_flow_sub_actions_idx));
10551 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10552 sizeof(struct mlx5_flow_sub_actions_list));
10553 mdest_res->num_of_dest = num_of_dest;
10554 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10556 return rte_flow_error_set(error, EINVAL,
10557 RTE_FLOW_ERROR_TYPE_ACTION,
10558 NULL, "can't create sample "
10561 res->sub_actions = sample_actions;
10562 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10563 return rte_flow_error_set(error, EINVAL,
10564 RTE_FLOW_ERROR_TYPE_ACTION,
10566 "can't create sample action");
10572 * Remove an ASO age action from age actions list.
10575 * Pointer to the Ethernet device structure.
10577 * Pointer to the aso age action handler.
10580 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10581 struct mlx5_aso_age_action *age)
10583 struct mlx5_age_info *age_info;
10584 struct mlx5_age_param *age_param = &age->age_params;
10585 struct mlx5_priv *priv = dev->data->dev_private;
10586 uint16_t expected = AGE_CANDIDATE;
10588 age_info = GET_PORT_AGE_INFO(priv);
10589 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10590 AGE_FREE, false, __ATOMIC_RELAXED,
10591 __ATOMIC_RELAXED)) {
10593 * We need the lock even it is age timeout,
10594 * since age action may still in process.
10596 rte_spinlock_lock(&age_info->aged_sl);
10597 LIST_REMOVE(age, next);
10598 rte_spinlock_unlock(&age_info->aged_sl);
10599 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10604 * Release an ASO age action.
10607 * Pointer to the Ethernet device structure.
10608 * @param[in] age_idx
10609 * Index of ASO age action to release.
10611 * True if the release operation is during flow destroy operation.
10612 * False if the release operation is during action destroy operation.
10615 * 0 when age action was removed, otherwise the number of references.
10618 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10620 struct mlx5_priv *priv = dev->data->dev_private;
10621 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10622 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10623 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10626 flow_dv_aso_age_remove_from_age(dev, age);
10627 rte_spinlock_lock(&mng->free_sl);
10628 LIST_INSERT_HEAD(&mng->free, age, next);
10629 rte_spinlock_unlock(&mng->free_sl);
10635 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10638 * Pointer to the Ethernet device structure.
10641 * 0 on success, otherwise negative errno value and rte_errno is set.
10644 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10646 struct mlx5_priv *priv = dev->data->dev_private;
10647 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10648 void *old_pools = mng->pools;
10649 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10650 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10651 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10654 rte_errno = ENOMEM;
10658 memcpy(pools, old_pools,
10659 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10660 mlx5_free(old_pools);
10662 /* First ASO flow hit allocation - starting ASO data-path. */
10663 int ret = mlx5_aso_queue_start(priv->sh);
10671 mng->pools = pools;
10676 * Create and initialize a new ASO aging pool.
10679 * Pointer to the Ethernet device structure.
10680 * @param[out] age_free
10681 * Where to put the pointer of a new age action.
10684 * The age actions pool pointer and @p age_free is set on success,
10685 * NULL otherwise and rte_errno is set.
10687 static struct mlx5_aso_age_pool *
10688 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10689 struct mlx5_aso_age_action **age_free)
10691 struct mlx5_priv *priv = dev->data->dev_private;
10692 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10693 struct mlx5_aso_age_pool *pool = NULL;
10694 struct mlx5_devx_obj *obj = NULL;
10697 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10700 rte_errno = ENODATA;
10701 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10704 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10706 claim_zero(mlx5_devx_cmd_destroy(obj));
10707 rte_errno = ENOMEM;
10710 pool->flow_hit_aso_obj = obj;
10711 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10712 rte_spinlock_lock(&mng->resize_sl);
10713 pool->index = mng->next;
10714 /* Resize pools array if there is no room for the new pool in it. */
10715 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10716 claim_zero(mlx5_devx_cmd_destroy(obj));
10718 rte_spinlock_unlock(&mng->resize_sl);
10721 mng->pools[pool->index] = pool;
10723 rte_spinlock_unlock(&mng->resize_sl);
10724 /* Assign the first action in the new pool, the rest go to free list. */
10725 *age_free = &pool->actions[0];
10726 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10727 pool->actions[i].offset = i;
10728 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10734 * Allocate a ASO aging bit.
10737 * Pointer to the Ethernet device structure.
10738 * @param[out] error
10739 * Pointer to the error structure.
10742 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10745 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10747 struct mlx5_priv *priv = dev->data->dev_private;
10748 const struct mlx5_aso_age_pool *pool;
10749 struct mlx5_aso_age_action *age_free = NULL;
10750 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10753 /* Try to get the next free age action bit. */
10754 rte_spinlock_lock(&mng->free_sl);
10755 age_free = LIST_FIRST(&mng->free);
10757 LIST_REMOVE(age_free, next);
10758 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10759 rte_spinlock_unlock(&mng->free_sl);
10760 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10761 NULL, "failed to create ASO age pool");
10762 return 0; /* 0 is an error. */
10764 rte_spinlock_unlock(&mng->free_sl);
10765 pool = container_of
10766 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10767 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10769 if (!age_free->dr_action) {
10770 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10774 rte_flow_error_set(error, rte_errno,
10775 RTE_FLOW_ERROR_TYPE_ACTION,
10776 NULL, "failed to get reg_c "
10777 "for ASO flow hit");
10778 return 0; /* 0 is an error. */
10780 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10781 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10782 (priv->sh->rx_domain,
10783 pool->flow_hit_aso_obj->obj, age_free->offset,
10784 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10785 (reg_c - REG_C_0));
10786 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10787 if (!age_free->dr_action) {
10789 rte_spinlock_lock(&mng->free_sl);
10790 LIST_INSERT_HEAD(&mng->free, age_free, next);
10791 rte_spinlock_unlock(&mng->free_sl);
10792 rte_flow_error_set(error, rte_errno,
10793 RTE_FLOW_ERROR_TYPE_ACTION,
10794 NULL, "failed to create ASO "
10795 "flow hit action");
10796 return 0; /* 0 is an error. */
10799 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10800 return pool->index | ((age_free->offset + 1) << 16);
10804 * Create a age action using ASO mechanism.
10807 * Pointer to rte_eth_dev structure.
10809 * Pointer to the aging action configuration.
10810 * @param[out] error
10811 * Pointer to the error structure.
10814 * Index to flow counter on success, 0 otherwise.
10817 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10818 const struct rte_flow_action_age *age,
10819 struct rte_flow_error *error)
10821 uint32_t age_idx = 0;
10822 struct mlx5_aso_age_action *aso_age;
10824 age_idx = flow_dv_aso_age_alloc(dev, error);
10827 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10828 aso_age->age_params.context = age->context;
10829 aso_age->age_params.timeout = age->timeout;
10830 aso_age->age_params.port_id = dev->data->port_id;
10831 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10833 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10839 * Fill the flow with DV spec, lock free
10840 * (mutex should be acquired by caller).
10843 * Pointer to rte_eth_dev structure.
10844 * @param[in, out] dev_flow
10845 * Pointer to the sub flow.
10847 * Pointer to the flow attributes.
10849 * Pointer to the list of items.
10850 * @param[in] actions
10851 * Pointer to the list of actions.
10852 * @param[out] error
10853 * Pointer to the error structure.
10856 * 0 on success, a negative errno value otherwise and rte_errno is set.
10859 flow_dv_translate(struct rte_eth_dev *dev,
10860 struct mlx5_flow *dev_flow,
10861 const struct rte_flow_attr *attr,
10862 const struct rte_flow_item items[],
10863 const struct rte_flow_action actions[],
10864 struct rte_flow_error *error)
10866 struct mlx5_priv *priv = dev->data->dev_private;
10867 struct mlx5_dev_config *dev_conf = &priv->config;
10868 struct rte_flow *flow = dev_flow->flow;
10869 struct mlx5_flow_handle *handle = dev_flow->handle;
10870 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10871 struct mlx5_flow_rss_desc *rss_desc;
10872 uint64_t item_flags = 0;
10873 uint64_t last_item = 0;
10874 uint64_t action_flags = 0;
10875 struct mlx5_flow_dv_matcher matcher = {
10877 .size = sizeof(matcher.mask.buf) -
10878 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10882 bool actions_end = false;
10884 struct mlx5_flow_dv_modify_hdr_resource res;
10885 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10886 sizeof(struct mlx5_modification_cmd) *
10887 (MLX5_MAX_MODIFY_NUM + 1)];
10889 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10890 const struct rte_flow_action_count *count = NULL;
10891 const struct rte_flow_action_age *age = NULL;
10892 union flow_dv_attr flow_attr = { .attr = 0 };
10894 union mlx5_flow_tbl_key tbl_key;
10895 uint32_t modify_action_position = UINT32_MAX;
10896 void *match_mask = matcher.mask.buf;
10897 void *match_value = dev_flow->dv.value.buf;
10898 uint8_t next_protocol = 0xff;
10899 struct rte_vlan_hdr vlan = { 0 };
10900 struct mlx5_flow_dv_dest_array_resource mdest_res;
10901 struct mlx5_flow_dv_sample_resource sample_res;
10902 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10903 const struct rte_flow_action_sample *sample = NULL;
10904 struct mlx5_flow_sub_actions_list *sample_act;
10905 uint32_t sample_act_pos = UINT32_MAX;
10906 uint32_t num_of_dest = 0;
10907 int tmp_actions_n = 0;
10910 const struct mlx5_flow_tunnel *tunnel;
10911 struct flow_grp_info grp_info = {
10912 .external = !!dev_flow->external,
10913 .transfer = !!attr->transfer,
10914 .fdb_def_rule = !!priv->fdb_def_rule,
10915 .skip_scale = dev_flow->skip_scale &
10916 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10920 return rte_flow_error_set(error, ENOMEM,
10921 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10923 "failed to push flow workspace");
10924 rss_desc = &wks->rss_desc;
10925 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10926 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10927 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10928 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10929 /* update normal path action resource into last index of array */
10930 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10931 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10932 flow_items_to_tunnel(items) :
10933 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10934 flow_actions_to_tunnel(actions) :
10935 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10936 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10937 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10938 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10939 (dev, tunnel, attr, items, actions);
10940 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10944 dev_flow->dv.group = table;
10945 if (attr->transfer)
10946 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10947 /* number of actions must be set to 0 in case of dirty stack. */
10948 mhdr_res->actions_num = 0;
10949 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10951 * do not add decap action if match rule drops packet
10952 * HW rejects rules with decap & drop
10954 * if tunnel match rule was inserted before matching tunnel set
10955 * rule flow table used in the match rule must be registered.
10956 * current implementation handles that in the
10957 * flow_dv_match_register() at the function end.
10959 bool add_decap = true;
10960 const struct rte_flow_action *ptr = actions;
10962 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10963 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10969 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10973 dev_flow->dv.actions[actions_n++] =
10974 dev_flow->dv.encap_decap->action;
10975 action_flags |= MLX5_FLOW_ACTION_DECAP;
10978 for (; !actions_end ; actions++) {
10979 const struct rte_flow_action_queue *queue;
10980 const struct rte_flow_action_rss *rss;
10981 const struct rte_flow_action *action = actions;
10982 const uint8_t *rss_key;
10983 const struct rte_flow_action_meter *mtr;
10984 struct mlx5_flow_tbl_resource *tbl;
10985 struct mlx5_aso_age_action *age_act;
10986 uint32_t port_id = 0;
10987 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10988 int action_type = actions->type;
10989 const struct rte_flow_action *found_action = NULL;
10990 struct mlx5_flow_meter *fm = NULL;
10991 uint32_t jump_group = 0;
10993 if (!mlx5_flow_os_action_supported(action_type))
10994 return rte_flow_error_set(error, ENOTSUP,
10995 RTE_FLOW_ERROR_TYPE_ACTION,
10997 "action not supported");
10998 switch (action_type) {
10999 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11000 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11002 case RTE_FLOW_ACTION_TYPE_VOID:
11004 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11005 if (flow_dv_translate_action_port_id(dev, action,
11008 port_id_resource.port_id = port_id;
11009 MLX5_ASSERT(!handle->rix_port_id_action);
11010 if (flow_dv_port_id_action_resource_register
11011 (dev, &port_id_resource, dev_flow, error))
11013 dev_flow->dv.actions[actions_n++] =
11014 dev_flow->dv.port_id_action->action;
11015 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11016 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11017 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11020 case RTE_FLOW_ACTION_TYPE_FLAG:
11021 action_flags |= MLX5_FLOW_ACTION_FLAG;
11022 dev_flow->handle->mark = 1;
11023 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11024 struct rte_flow_action_mark mark = {
11025 .id = MLX5_FLOW_MARK_DEFAULT,
11028 if (flow_dv_convert_action_mark(dev, &mark,
11032 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11035 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11037 * Only one FLAG or MARK is supported per device flow
11038 * right now. So the pointer to the tag resource must be
11039 * zero before the register process.
11041 MLX5_ASSERT(!handle->dvh.rix_tag);
11042 if (flow_dv_tag_resource_register(dev, tag_be,
11045 MLX5_ASSERT(dev_flow->dv.tag_resource);
11046 dev_flow->dv.actions[actions_n++] =
11047 dev_flow->dv.tag_resource->action;
11049 case RTE_FLOW_ACTION_TYPE_MARK:
11050 action_flags |= MLX5_FLOW_ACTION_MARK;
11051 dev_flow->handle->mark = 1;
11052 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11053 const struct rte_flow_action_mark *mark =
11054 (const struct rte_flow_action_mark *)
11057 if (flow_dv_convert_action_mark(dev, mark,
11061 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11065 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11066 /* Legacy (non-extensive) MARK action. */
11067 tag_be = mlx5_flow_mark_set
11068 (((const struct rte_flow_action_mark *)
11069 (actions->conf))->id);
11070 MLX5_ASSERT(!handle->dvh.rix_tag);
11071 if (flow_dv_tag_resource_register(dev, tag_be,
11074 MLX5_ASSERT(dev_flow->dv.tag_resource);
11075 dev_flow->dv.actions[actions_n++] =
11076 dev_flow->dv.tag_resource->action;
11078 case RTE_FLOW_ACTION_TYPE_SET_META:
11079 if (flow_dv_convert_action_set_meta
11080 (dev, mhdr_res, attr,
11081 (const struct rte_flow_action_set_meta *)
11082 actions->conf, error))
11084 action_flags |= MLX5_FLOW_ACTION_SET_META;
11086 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11087 if (flow_dv_convert_action_set_tag
11089 (const struct rte_flow_action_set_tag *)
11090 actions->conf, error))
11092 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11094 case RTE_FLOW_ACTION_TYPE_DROP:
11095 action_flags |= MLX5_FLOW_ACTION_DROP;
11096 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11098 case RTE_FLOW_ACTION_TYPE_QUEUE:
11099 queue = actions->conf;
11100 rss_desc->queue_num = 1;
11101 rss_desc->queue[0] = queue->index;
11102 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11103 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11104 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11107 case RTE_FLOW_ACTION_TYPE_RSS:
11108 rss = actions->conf;
11109 memcpy(rss_desc->queue, rss->queue,
11110 rss->queue_num * sizeof(uint16_t));
11111 rss_desc->queue_num = rss->queue_num;
11112 /* NULL RSS key indicates default RSS key. */
11113 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11114 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11116 * rss->level and rss.types should be set in advance
11117 * when expanding items for RSS.
11119 action_flags |= MLX5_FLOW_ACTION_RSS;
11120 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11121 MLX5_FLOW_FATE_SHARED_RSS :
11122 MLX5_FLOW_FATE_QUEUE;
11124 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11125 flow->age = (uint32_t)(uintptr_t)(action->conf);
11126 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11127 __atomic_fetch_add(&age_act->refcnt, 1,
11129 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11130 action_flags |= MLX5_FLOW_ACTION_AGE;
11132 case RTE_FLOW_ACTION_TYPE_AGE:
11133 if (priv->sh->flow_hit_aso_en && attr->group) {
11135 * Create one shared age action, to be used
11136 * by all sub-flows.
11140 flow_dv_translate_create_aso_age
11141 (dev, action->conf,
11144 return rte_flow_error_set
11146 RTE_FLOW_ERROR_TYPE_ACTION,
11148 "can't create ASO age action");
11150 dev_flow->dv.actions[actions_n++] =
11151 (flow_aso_age_get_by_idx
11152 (dev, flow->age))->dr_action;
11153 action_flags |= MLX5_FLOW_ACTION_AGE;
11157 case RTE_FLOW_ACTION_TYPE_COUNT:
11158 if (!dev_conf->devx) {
11159 return rte_flow_error_set
11161 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11163 "count action not supported");
11165 /* Save information first, will apply later. */
11166 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11167 count = action->conf;
11169 age = action->conf;
11170 action_flags |= MLX5_FLOW_ACTION_COUNT;
11172 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11173 dev_flow->dv.actions[actions_n++] =
11174 priv->sh->pop_vlan_action;
11175 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11177 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11178 if (!(action_flags &
11179 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11180 flow_dev_get_vlan_info_from_items(items, &vlan);
11181 vlan.eth_proto = rte_be_to_cpu_16
11182 ((((const struct rte_flow_action_of_push_vlan *)
11183 actions->conf)->ethertype));
11184 found_action = mlx5_flow_find_action
11186 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11188 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11189 found_action = mlx5_flow_find_action
11191 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11193 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11194 if (flow_dv_create_action_push_vlan
11195 (dev, attr, &vlan, dev_flow, error))
11197 dev_flow->dv.actions[actions_n++] =
11198 dev_flow->dv.push_vlan_res->action;
11199 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11201 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11202 /* of_vlan_push action handled this action */
11203 MLX5_ASSERT(action_flags &
11204 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11206 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11207 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11209 flow_dev_get_vlan_info_from_items(items, &vlan);
11210 mlx5_update_vlan_vid_pcp(actions, &vlan);
11211 /* If no VLAN push - this is a modify header action */
11212 if (flow_dv_convert_action_modify_vlan_vid
11213 (mhdr_res, actions, error))
11215 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11217 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11218 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11219 if (flow_dv_create_action_l2_encap(dev, actions,
11224 dev_flow->dv.actions[actions_n++] =
11225 dev_flow->dv.encap_decap->action;
11226 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11227 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11228 sample_act->action_flags |=
11229 MLX5_FLOW_ACTION_ENCAP;
11231 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11232 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11233 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11237 dev_flow->dv.actions[actions_n++] =
11238 dev_flow->dv.encap_decap->action;
11239 action_flags |= MLX5_FLOW_ACTION_DECAP;
11241 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11242 /* Handle encap with preceding decap. */
11243 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11244 if (flow_dv_create_action_raw_encap
11245 (dev, actions, dev_flow, attr, error))
11247 dev_flow->dv.actions[actions_n++] =
11248 dev_flow->dv.encap_decap->action;
11250 /* Handle encap without preceding decap. */
11251 if (flow_dv_create_action_l2_encap
11252 (dev, actions, dev_flow, attr->transfer,
11255 dev_flow->dv.actions[actions_n++] =
11256 dev_flow->dv.encap_decap->action;
11258 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11259 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11260 sample_act->action_flags |=
11261 MLX5_FLOW_ACTION_ENCAP;
11263 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11264 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11266 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11267 if (flow_dv_create_action_l2_decap
11268 (dev, dev_flow, attr->transfer, error))
11270 dev_flow->dv.actions[actions_n++] =
11271 dev_flow->dv.encap_decap->action;
11273 /* If decap is followed by encap, handle it at encap. */
11274 action_flags |= MLX5_FLOW_ACTION_DECAP;
11276 case RTE_FLOW_ACTION_TYPE_JUMP:
11277 jump_group = ((const struct rte_flow_action_jump *)
11278 action->conf)->group;
11279 grp_info.std_tbl_fix = 0;
11280 if (dev_flow->skip_scale &
11281 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11282 grp_info.skip_scale = 1;
11284 grp_info.skip_scale = 0;
11285 ret = mlx5_flow_group_to_table(dev, tunnel,
11291 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11293 !!dev_flow->external,
11294 tunnel, jump_group, 0,
11297 return rte_flow_error_set
11299 RTE_FLOW_ERROR_TYPE_ACTION,
11301 "cannot create jump action.");
11302 if (flow_dv_jump_tbl_resource_register
11303 (dev, tbl, dev_flow, error)) {
11304 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11305 return rte_flow_error_set
11307 RTE_FLOW_ERROR_TYPE_ACTION,
11309 "cannot create jump action.");
11311 dev_flow->dv.actions[actions_n++] =
11312 dev_flow->dv.jump->action;
11313 action_flags |= MLX5_FLOW_ACTION_JUMP;
11314 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11315 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11318 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11319 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11320 if (flow_dv_convert_action_modify_mac
11321 (mhdr_res, actions, error))
11323 action_flags |= actions->type ==
11324 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11325 MLX5_FLOW_ACTION_SET_MAC_SRC :
11326 MLX5_FLOW_ACTION_SET_MAC_DST;
11328 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11329 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11330 if (flow_dv_convert_action_modify_ipv4
11331 (mhdr_res, actions, error))
11333 action_flags |= actions->type ==
11334 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11335 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11336 MLX5_FLOW_ACTION_SET_IPV4_DST;
11338 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11339 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11340 if (flow_dv_convert_action_modify_ipv6
11341 (mhdr_res, actions, error))
11343 action_flags |= actions->type ==
11344 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11345 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11346 MLX5_FLOW_ACTION_SET_IPV6_DST;
11348 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11349 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11350 if (flow_dv_convert_action_modify_tp
11351 (mhdr_res, actions, items,
11352 &flow_attr, dev_flow, !!(action_flags &
11353 MLX5_FLOW_ACTION_DECAP), error))
11355 action_flags |= actions->type ==
11356 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11357 MLX5_FLOW_ACTION_SET_TP_SRC :
11358 MLX5_FLOW_ACTION_SET_TP_DST;
11360 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11361 if (flow_dv_convert_action_modify_dec_ttl
11362 (mhdr_res, items, &flow_attr, dev_flow,
11364 MLX5_FLOW_ACTION_DECAP), error))
11366 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11368 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11369 if (flow_dv_convert_action_modify_ttl
11370 (mhdr_res, actions, items, &flow_attr,
11371 dev_flow, !!(action_flags &
11372 MLX5_FLOW_ACTION_DECAP), error))
11374 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11376 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11377 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11378 if (flow_dv_convert_action_modify_tcp_seq
11379 (mhdr_res, actions, error))
11381 action_flags |= actions->type ==
11382 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11383 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11384 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11387 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11388 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11389 if (flow_dv_convert_action_modify_tcp_ack
11390 (mhdr_res, actions, error))
11392 action_flags |= actions->type ==
11393 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11394 MLX5_FLOW_ACTION_INC_TCP_ACK :
11395 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11397 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11398 if (flow_dv_convert_action_set_reg
11399 (mhdr_res, actions, error))
11401 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11403 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11404 if (flow_dv_convert_action_copy_mreg
11405 (dev, mhdr_res, actions, error))
11407 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11409 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11410 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11411 dev_flow->handle->fate_action =
11412 MLX5_FLOW_FATE_DEFAULT_MISS;
11414 case RTE_FLOW_ACTION_TYPE_METER:
11415 mtr = actions->conf;
11416 if (!flow->meter) {
11417 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11420 return rte_flow_error_set(error,
11422 RTE_FLOW_ERROR_TYPE_ACTION,
11425 "or invalid parameters");
11426 flow->meter = fm->idx;
11428 /* Set the meter action. */
11430 fm = mlx5_ipool_get(priv->sh->ipool
11431 [MLX5_IPOOL_MTR], flow->meter);
11433 return rte_flow_error_set(error,
11435 RTE_FLOW_ERROR_TYPE_ACTION,
11438 "or invalid parameters");
11440 dev_flow->dv.actions[actions_n++] =
11441 fm->mfts->meter_action;
11442 action_flags |= MLX5_FLOW_ACTION_METER;
11444 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11445 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11448 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11450 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11451 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11454 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11456 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11457 sample_act_pos = actions_n;
11458 sample = (const struct rte_flow_action_sample *)
11461 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11462 /* put encap action into group if work with port id */
11463 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11464 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11465 sample_act->action_flags |=
11466 MLX5_FLOW_ACTION_ENCAP;
11468 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11469 if (flow_dv_convert_action_modify_field
11470 (dev, mhdr_res, actions, attr, error))
11472 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11474 case RTE_FLOW_ACTION_TYPE_END:
11475 actions_end = true;
11476 if (mhdr_res->actions_num) {
11477 /* create modify action if needed. */
11478 if (flow_dv_modify_hdr_resource_register
11479 (dev, mhdr_res, dev_flow, error))
11481 dev_flow->dv.actions[modify_action_position] =
11482 handle->dvh.modify_hdr->action;
11484 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11486 * Create one count action, to be used
11487 * by all sub-flows.
11489 if (!flow->counter) {
11491 flow_dv_translate_create_counter
11492 (dev, dev_flow, count,
11494 if (!flow->counter)
11495 return rte_flow_error_set
11497 RTE_FLOW_ERROR_TYPE_ACTION,
11498 NULL, "cannot create counter"
11501 dev_flow->dv.actions[actions_n] =
11502 (flow_dv_counter_get_by_idx(dev,
11503 flow->counter, NULL))->action;
11509 if (mhdr_res->actions_num &&
11510 modify_action_position == UINT32_MAX)
11511 modify_action_position = actions_n++;
11513 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11514 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11515 int item_type = items->type;
11517 if (!mlx5_flow_os_item_supported(item_type))
11518 return rte_flow_error_set(error, ENOTSUP,
11519 RTE_FLOW_ERROR_TYPE_ITEM,
11520 NULL, "item not supported");
11521 switch (item_type) {
11522 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11523 flow_dv_translate_item_port_id
11524 (dev, match_mask, match_value, items, attr);
11525 last_item = MLX5_FLOW_ITEM_PORT_ID;
11527 case RTE_FLOW_ITEM_TYPE_ETH:
11528 flow_dv_translate_item_eth(match_mask, match_value,
11530 dev_flow->dv.group);
11531 matcher.priority = action_flags &
11532 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11533 !dev_flow->external ?
11534 MLX5_PRIORITY_MAP_L3 :
11535 MLX5_PRIORITY_MAP_L2;
11536 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11537 MLX5_FLOW_LAYER_OUTER_L2;
11539 case RTE_FLOW_ITEM_TYPE_VLAN:
11540 flow_dv_translate_item_vlan(dev_flow,
11541 match_mask, match_value,
11543 dev_flow->dv.group);
11544 matcher.priority = MLX5_PRIORITY_MAP_L2;
11545 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11546 MLX5_FLOW_LAYER_INNER_VLAN) :
11547 (MLX5_FLOW_LAYER_OUTER_L2 |
11548 MLX5_FLOW_LAYER_OUTER_VLAN);
11550 case RTE_FLOW_ITEM_TYPE_IPV4:
11551 mlx5_flow_tunnel_ip_check(items, next_protocol,
11552 &item_flags, &tunnel);
11553 flow_dv_translate_item_ipv4(match_mask, match_value,
11555 dev_flow->dv.group);
11556 matcher.priority = MLX5_PRIORITY_MAP_L3;
11557 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11558 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11559 if (items->mask != NULL &&
11560 ((const struct rte_flow_item_ipv4 *)
11561 items->mask)->hdr.next_proto_id) {
11563 ((const struct rte_flow_item_ipv4 *)
11564 (items->spec))->hdr.next_proto_id;
11566 ((const struct rte_flow_item_ipv4 *)
11567 (items->mask))->hdr.next_proto_id;
11569 /* Reset for inner layer. */
11570 next_protocol = 0xff;
11573 case RTE_FLOW_ITEM_TYPE_IPV6:
11574 mlx5_flow_tunnel_ip_check(items, next_protocol,
11575 &item_flags, &tunnel);
11576 flow_dv_translate_item_ipv6(match_mask, match_value,
11578 dev_flow->dv.group);
11579 matcher.priority = MLX5_PRIORITY_MAP_L3;
11580 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11581 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11582 if (items->mask != NULL &&
11583 ((const struct rte_flow_item_ipv6 *)
11584 items->mask)->hdr.proto) {
11586 ((const struct rte_flow_item_ipv6 *)
11587 items->spec)->hdr.proto;
11589 ((const struct rte_flow_item_ipv6 *)
11590 items->mask)->hdr.proto;
11592 /* Reset for inner layer. */
11593 next_protocol = 0xff;
11596 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11597 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11600 last_item = tunnel ?
11601 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11602 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11603 if (items->mask != NULL &&
11604 ((const struct rte_flow_item_ipv6_frag_ext *)
11605 items->mask)->hdr.next_header) {
11607 ((const struct rte_flow_item_ipv6_frag_ext *)
11608 items->spec)->hdr.next_header;
11610 ((const struct rte_flow_item_ipv6_frag_ext *)
11611 items->mask)->hdr.next_header;
11613 /* Reset for inner layer. */
11614 next_protocol = 0xff;
11617 case RTE_FLOW_ITEM_TYPE_TCP:
11618 flow_dv_translate_item_tcp(match_mask, match_value,
11620 matcher.priority = MLX5_PRIORITY_MAP_L4;
11621 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11622 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11624 case RTE_FLOW_ITEM_TYPE_UDP:
11625 flow_dv_translate_item_udp(match_mask, match_value,
11627 matcher.priority = MLX5_PRIORITY_MAP_L4;
11628 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11629 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11631 case RTE_FLOW_ITEM_TYPE_GRE:
11632 flow_dv_translate_item_gre(match_mask, match_value,
11634 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11635 last_item = MLX5_FLOW_LAYER_GRE;
11637 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11638 flow_dv_translate_item_gre_key(match_mask,
11639 match_value, items);
11640 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11642 case RTE_FLOW_ITEM_TYPE_NVGRE:
11643 flow_dv_translate_item_nvgre(match_mask, match_value,
11645 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11646 last_item = MLX5_FLOW_LAYER_GRE;
11648 case RTE_FLOW_ITEM_TYPE_VXLAN:
11649 flow_dv_translate_item_vxlan(match_mask, match_value,
11651 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11652 last_item = MLX5_FLOW_LAYER_VXLAN;
11654 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11655 flow_dv_translate_item_vxlan_gpe(match_mask,
11656 match_value, items,
11658 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11659 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11661 case RTE_FLOW_ITEM_TYPE_GENEVE:
11662 flow_dv_translate_item_geneve(match_mask, match_value,
11664 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11665 last_item = MLX5_FLOW_LAYER_GENEVE;
11667 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11668 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11672 return rte_flow_error_set(error, -ret,
11673 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11674 "cannot create GENEVE TLV option");
11675 flow->geneve_tlv_option = 1;
11676 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11678 case RTE_FLOW_ITEM_TYPE_MPLS:
11679 flow_dv_translate_item_mpls(match_mask, match_value,
11680 items, last_item, tunnel);
11681 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11682 last_item = MLX5_FLOW_LAYER_MPLS;
11684 case RTE_FLOW_ITEM_TYPE_MARK:
11685 flow_dv_translate_item_mark(dev, match_mask,
11686 match_value, items);
11687 last_item = MLX5_FLOW_ITEM_MARK;
11689 case RTE_FLOW_ITEM_TYPE_META:
11690 flow_dv_translate_item_meta(dev, match_mask,
11691 match_value, attr, items);
11692 last_item = MLX5_FLOW_ITEM_METADATA;
11694 case RTE_FLOW_ITEM_TYPE_ICMP:
11695 flow_dv_translate_item_icmp(match_mask, match_value,
11697 last_item = MLX5_FLOW_LAYER_ICMP;
11699 case RTE_FLOW_ITEM_TYPE_ICMP6:
11700 flow_dv_translate_item_icmp6(match_mask, match_value,
11702 last_item = MLX5_FLOW_LAYER_ICMP6;
11704 case RTE_FLOW_ITEM_TYPE_TAG:
11705 flow_dv_translate_item_tag(dev, match_mask,
11706 match_value, items);
11707 last_item = MLX5_FLOW_ITEM_TAG;
11709 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11710 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11711 match_value, items);
11712 last_item = MLX5_FLOW_ITEM_TAG;
11714 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11715 flow_dv_translate_item_tx_queue(dev, match_mask,
11718 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11720 case RTE_FLOW_ITEM_TYPE_GTP:
11721 flow_dv_translate_item_gtp(match_mask, match_value,
11723 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11724 last_item = MLX5_FLOW_LAYER_GTP;
11726 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11727 ret = flow_dv_translate_item_gtp_psc(match_mask,
11731 return rte_flow_error_set(error, -ret,
11732 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11733 "cannot create GTP PSC item");
11734 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11736 case RTE_FLOW_ITEM_TYPE_ECPRI:
11737 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11738 /* Create it only the first time to be used. */
11739 ret = mlx5_flex_parser_ecpri_alloc(dev);
11741 return rte_flow_error_set
11743 RTE_FLOW_ERROR_TYPE_ITEM,
11745 "cannot create eCPRI parser");
11747 /* Adjust the length matcher and device flow value. */
11748 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11749 dev_flow->dv.value.size =
11750 MLX5_ST_SZ_BYTES(fte_match_param);
11751 flow_dv_translate_item_ecpri(dev, match_mask,
11752 match_value, items);
11753 /* No other protocol should follow eCPRI layer. */
11754 last_item = MLX5_FLOW_LAYER_ECPRI;
11759 item_flags |= last_item;
11762 * When E-Switch mode is enabled, we have two cases where we need to
11763 * set the source port manually.
11764 * The first one, is in case of Nic steering rule, and the second is
11765 * E-Switch rule where no port_id item was found. In both cases
11766 * the source port is set according the current port in use.
11768 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11769 (priv->representor || priv->master)) {
11770 if (flow_dv_translate_item_port_id(dev, match_mask,
11771 match_value, NULL, attr))
11774 #ifdef RTE_LIBRTE_MLX5_DEBUG
11775 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11776 dev_flow->dv.value.buf));
11779 * Layers may be already initialized from prefix flow if this dev_flow
11780 * is the suffix flow.
11782 handle->layers |= item_flags;
11783 if (action_flags & MLX5_FLOW_ACTION_RSS)
11784 flow_dv_hashfields_set(dev_flow, rss_desc);
11785 /* If has RSS action in the sample action, the Sample/Mirror resource
11786 * should be registered after the hash filed be update.
11788 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11789 ret = flow_dv_translate_action_sample(dev,
11798 ret = flow_dv_create_action_sample(dev,
11807 return rte_flow_error_set
11809 RTE_FLOW_ERROR_TYPE_ACTION,
11811 "cannot create sample action");
11812 if (num_of_dest > 1) {
11813 dev_flow->dv.actions[sample_act_pos] =
11814 dev_flow->dv.dest_array_res->action;
11816 dev_flow->dv.actions[sample_act_pos] =
11817 dev_flow->dv.sample_res->verbs_action;
11821 * For multiple destination (sample action with ratio=1), the encap
11822 * action and port id action will be combined into group action.
11823 * So need remove the original these actions in the flow and only
11824 * use the sample action instead of.
11826 if (num_of_dest > 1 &&
11827 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11829 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11831 for (i = 0; i < actions_n; i++) {
11832 if ((sample_act->dr_encap_action &&
11833 sample_act->dr_encap_action ==
11834 dev_flow->dv.actions[i]) ||
11835 (sample_act->dr_port_id_action &&
11836 sample_act->dr_port_id_action ==
11837 dev_flow->dv.actions[i]) ||
11838 (sample_act->dr_jump_action &&
11839 sample_act->dr_jump_action ==
11840 dev_flow->dv.actions[i]))
11842 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11844 memcpy((void *)dev_flow->dv.actions,
11845 (void *)temp_actions,
11846 tmp_actions_n * sizeof(void *));
11847 actions_n = tmp_actions_n;
11849 dev_flow->dv.actions_n = actions_n;
11850 dev_flow->act_flags = action_flags;
11851 /* Register matcher. */
11852 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11853 matcher.mask.size);
11854 matcher.priority = mlx5_get_matcher_priority(dev, attr,
11856 /* reserved field no needs to be set to 0 here. */
11857 tbl_key.domain = attr->transfer;
11858 tbl_key.direction = attr->egress;
11859 tbl_key.table_id = dev_flow->dv.group;
11860 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11861 tunnel, attr->group, error))
11867 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11870 * @param[in, out] action
11871 * Shred RSS action holding hash RX queue objects.
11872 * @param[in] hash_fields
11873 * Defines combination of packet fields to participate in RX hash.
11874 * @param[in] tunnel
11876 * @param[in] hrxq_idx
11877 * Hash RX queue index to set.
11880 * 0 on success, otherwise negative errno value.
11883 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11884 const uint64_t hash_fields,
11888 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11890 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11891 case MLX5_RSS_HASH_IPV4:
11892 hrxqs[0] = hrxq_idx;
11894 case MLX5_RSS_HASH_IPV4_TCP:
11895 hrxqs[1] = hrxq_idx;
11897 case MLX5_RSS_HASH_IPV4_UDP:
11898 hrxqs[2] = hrxq_idx;
11900 case MLX5_RSS_HASH_IPV6:
11901 hrxqs[3] = hrxq_idx;
11903 case MLX5_RSS_HASH_IPV6_TCP:
11904 hrxqs[4] = hrxq_idx;
11906 case MLX5_RSS_HASH_IPV6_UDP:
11907 hrxqs[5] = hrxq_idx;
11909 case MLX5_RSS_HASH_NONE:
11910 hrxqs[6] = hrxq_idx;
11918 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11922 * Pointer to the Ethernet device structure.
11924 * Shared RSS action ID holding hash RX queue objects.
11925 * @param[in] hash_fields
11926 * Defines combination of packet fields to participate in RX hash.
11927 * @param[in] tunnel
11931 * Valid hash RX queue index, otherwise 0.
11934 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11935 const uint64_t hash_fields,
11938 struct mlx5_priv *priv = dev->data->dev_private;
11939 struct mlx5_shared_action_rss *shared_rss =
11940 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11941 const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11942 shared_rss->hrxq_tunnel;
11944 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11945 case MLX5_RSS_HASH_IPV4:
11947 case MLX5_RSS_HASH_IPV4_TCP:
11949 case MLX5_RSS_HASH_IPV4_UDP:
11951 case MLX5_RSS_HASH_IPV6:
11953 case MLX5_RSS_HASH_IPV6_TCP:
11955 case MLX5_RSS_HASH_IPV6_UDP:
11957 case MLX5_RSS_HASH_NONE:
11965 * Apply the flow to the NIC, lock free,
11966 * (mutex should be acquired by caller).
11969 * Pointer to the Ethernet device structure.
11970 * @param[in, out] flow
11971 * Pointer to flow structure.
11972 * @param[out] error
11973 * Pointer to error structure.
11976 * 0 on success, a negative errno value otherwise and rte_errno is set.
11979 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11980 struct rte_flow_error *error)
11982 struct mlx5_flow_dv_workspace *dv;
11983 struct mlx5_flow_handle *dh;
11984 struct mlx5_flow_handle_dv *dv_h;
11985 struct mlx5_flow *dev_flow;
11986 struct mlx5_priv *priv = dev->data->dev_private;
11987 uint32_t handle_idx;
11991 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11992 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11995 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11996 dev_flow = &wks->flows[idx];
11997 dv = &dev_flow->dv;
11998 dh = dev_flow->handle;
12001 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12002 if (dv->transfer) {
12003 dv->actions[n++] = priv->sh->esw_drop_action;
12005 MLX5_ASSERT(priv->drop_queue.hrxq);
12007 priv->drop_queue.hrxq->action;
12009 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12010 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12011 struct mlx5_hrxq *hrxq;
12014 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12019 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12020 "cannot get hash queue");
12023 dh->rix_hrxq = hrxq_idx;
12024 dv->actions[n++] = hrxq->action;
12025 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12026 struct mlx5_hrxq *hrxq = NULL;
12029 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12030 rss_desc->shared_rss,
12031 dev_flow->hash_fields,
12033 MLX5_FLOW_LAYER_TUNNEL));
12035 hrxq = mlx5_ipool_get
12036 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12041 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12042 "cannot get hash queue");
12045 dh->rix_srss = rss_desc->shared_rss;
12046 dv->actions[n++] = hrxq->action;
12047 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12048 if (!priv->sh->default_miss_action) {
12051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12052 "default miss action not be created.");
12055 dv->actions[n++] = priv->sh->default_miss_action;
12057 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12058 (void *)&dv->value, n,
12059 dv->actions, &dh->drv_flow);
12061 rte_flow_error_set(error, errno,
12062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12064 "hardware refuses to create flow");
12067 if (priv->vmwa_context &&
12068 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12070 * The rule contains the VLAN pattern.
12071 * For VF we are going to create VLAN
12072 * interface to make hypervisor set correct
12073 * e-Switch vport context.
12075 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12080 err = rte_errno; /* Save rte_errno before cleanup. */
12081 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12082 handle_idx, dh, next) {
12083 /* hrxq is union, don't clear it if the flag is not set. */
12084 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12085 mlx5_hrxq_release(dev, dh->rix_hrxq);
12087 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12090 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12091 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12093 rte_errno = err; /* Restore rte_errno. */
12098 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12099 struct mlx5_cache_entry *entry)
12101 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12104 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12109 * Release the flow matcher.
12112 * Pointer to Ethernet device.
12114 * Index to port ID action resource.
12117 * 1 while a reference on it exists, 0 when freed.
12120 flow_dv_matcher_release(struct rte_eth_dev *dev,
12121 struct mlx5_flow_handle *handle)
12123 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12124 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12125 typeof(*tbl), tbl);
12128 MLX5_ASSERT(matcher->matcher_object);
12129 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12130 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12135 * Release encap_decap resource.
12138 * Pointer to the hash list.
12140 * Pointer to exist resource entry object.
12143 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12144 struct mlx5_hlist_entry *entry)
12146 struct mlx5_dev_ctx_shared *sh = list->ctx;
12147 struct mlx5_flow_dv_encap_decap_resource *res =
12148 container_of(entry, typeof(*res), entry);
12150 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12151 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12155 * Release an encap/decap resource.
12158 * Pointer to Ethernet device.
12159 * @param encap_decap_idx
12160 * Index of encap decap resource.
12163 * 1 while a reference on it exists, 0 when freed.
12166 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12167 uint32_t encap_decap_idx)
12169 struct mlx5_priv *priv = dev->data->dev_private;
12170 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12172 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12174 if (!cache_resource)
12176 MLX5_ASSERT(cache_resource->action);
12177 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12178 &cache_resource->entry);
12182 * Release an jump to table action resource.
12185 * Pointer to Ethernet device.
12187 * Index to the jump action resource.
12190 * 1 while a reference on it exists, 0 when freed.
12193 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12196 struct mlx5_priv *priv = dev->data->dev_private;
12197 struct mlx5_flow_tbl_data_entry *tbl_data;
12199 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12203 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12207 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12208 struct mlx5_hlist_entry *entry)
12210 struct mlx5_flow_dv_modify_hdr_resource *res =
12211 container_of(entry, typeof(*res), entry);
12213 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12218 * Release a modify-header resource.
12221 * Pointer to Ethernet device.
12223 * Pointer to mlx5_flow_handle.
12226 * 1 while a reference on it exists, 0 when freed.
12229 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12230 struct mlx5_flow_handle *handle)
12232 struct mlx5_priv *priv = dev->data->dev_private;
12233 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12235 MLX5_ASSERT(entry->action);
12236 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12240 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12241 struct mlx5_cache_entry *entry)
12243 struct mlx5_dev_ctx_shared *sh = list->ctx;
12244 struct mlx5_flow_dv_port_id_action_resource *cache =
12245 container_of(entry, typeof(*cache), entry);
12247 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12248 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12252 * Release port ID action resource.
12255 * Pointer to Ethernet device.
12257 * Pointer to mlx5_flow_handle.
12260 * 1 while a reference on it exists, 0 when freed.
12263 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12266 struct mlx5_priv *priv = dev->data->dev_private;
12267 struct mlx5_flow_dv_port_id_action_resource *cache;
12269 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12272 MLX5_ASSERT(cache->action);
12273 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12278 * Release shared RSS action resource.
12281 * Pointer to Ethernet device.
12283 * Shared RSS action index.
12286 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12288 struct mlx5_priv *priv = dev->data->dev_private;
12289 struct mlx5_shared_action_rss *shared_rss;
12291 shared_rss = mlx5_ipool_get
12292 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12293 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12297 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12298 struct mlx5_cache_entry *entry)
12300 struct mlx5_dev_ctx_shared *sh = list->ctx;
12301 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12302 container_of(entry, typeof(*cache), entry);
12304 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12305 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12309 * Release push vlan action resource.
12312 * Pointer to Ethernet device.
12314 * Pointer to mlx5_flow_handle.
12317 * 1 while a reference on it exists, 0 when freed.
12320 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12321 struct mlx5_flow_handle *handle)
12323 struct mlx5_priv *priv = dev->data->dev_private;
12324 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12325 uint32_t idx = handle->dvh.rix_push_vlan;
12327 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12330 MLX5_ASSERT(cache->action);
12331 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12336 * Release the fate resource.
12339 * Pointer to Ethernet device.
12341 * Pointer to mlx5_flow_handle.
12344 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12345 struct mlx5_flow_handle *handle)
12347 if (!handle->rix_fate)
12349 switch (handle->fate_action) {
12350 case MLX5_FLOW_FATE_QUEUE:
12351 mlx5_hrxq_release(dev, handle->rix_hrxq);
12353 case MLX5_FLOW_FATE_JUMP:
12354 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12356 case MLX5_FLOW_FATE_PORT_ID:
12357 flow_dv_port_id_action_resource_release(dev,
12358 handle->rix_port_id_action);
12361 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12364 handle->rix_fate = 0;
12368 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12369 struct mlx5_cache_entry *entry)
12371 struct mlx5_flow_dv_sample_resource *cache_resource =
12372 container_of(entry, typeof(*cache_resource), entry);
12373 struct rte_eth_dev *dev = cache_resource->dev;
12374 struct mlx5_priv *priv = dev->data->dev_private;
12376 if (cache_resource->verbs_action)
12377 claim_zero(mlx5_flow_os_destroy_flow_action
12378 (cache_resource->verbs_action));
12379 if (cache_resource->normal_path_tbl)
12380 flow_dv_tbl_resource_release(MLX5_SH(dev),
12381 cache_resource->normal_path_tbl);
12382 flow_dv_sample_sub_actions_release(dev,
12383 &cache_resource->sample_idx);
12384 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12385 cache_resource->idx);
12386 DRV_LOG(DEBUG, "sample resource %p: removed",
12387 (void *)cache_resource);
12391 * Release an sample resource.
12394 * Pointer to Ethernet device.
12396 * Pointer to mlx5_flow_handle.
12399 * 1 while a reference on it exists, 0 when freed.
12402 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12403 struct mlx5_flow_handle *handle)
12405 struct mlx5_priv *priv = dev->data->dev_private;
12406 struct mlx5_flow_dv_sample_resource *cache_resource;
12408 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12409 handle->dvh.rix_sample);
12410 if (!cache_resource)
12412 MLX5_ASSERT(cache_resource->verbs_action);
12413 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12414 &cache_resource->entry);
12418 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12419 struct mlx5_cache_entry *entry)
12421 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12422 container_of(entry, typeof(*cache_resource), entry);
12423 struct rte_eth_dev *dev = cache_resource->dev;
12424 struct mlx5_priv *priv = dev->data->dev_private;
12427 MLX5_ASSERT(cache_resource->action);
12428 if (cache_resource->action)
12429 claim_zero(mlx5_flow_os_destroy_flow_action
12430 (cache_resource->action));
12431 for (; i < cache_resource->num_of_dest; i++)
12432 flow_dv_sample_sub_actions_release(dev,
12433 &cache_resource->sample_idx[i]);
12434 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12435 cache_resource->idx);
12436 DRV_LOG(DEBUG, "destination array resource %p: removed",
12437 (void *)cache_resource);
12441 * Release an destination array resource.
12444 * Pointer to Ethernet device.
12446 * Pointer to mlx5_flow_handle.
12449 * 1 while a reference on it exists, 0 when freed.
12452 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12453 struct mlx5_flow_handle *handle)
12455 struct mlx5_priv *priv = dev->data->dev_private;
12456 struct mlx5_flow_dv_dest_array_resource *cache;
12458 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12459 handle->dvh.rix_dest_array);
12462 MLX5_ASSERT(cache->action);
12463 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12468 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12470 struct mlx5_priv *priv = dev->data->dev_private;
12471 struct mlx5_dev_ctx_shared *sh = priv->sh;
12472 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12473 sh->geneve_tlv_option_resource;
12474 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12475 if (geneve_opt_resource) {
12476 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12477 __ATOMIC_RELAXED))) {
12478 claim_zero(mlx5_devx_cmd_destroy
12479 (geneve_opt_resource->obj));
12480 mlx5_free(sh->geneve_tlv_option_resource);
12481 sh->geneve_tlv_option_resource = NULL;
12484 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12488 * Remove the flow from the NIC but keeps it in memory.
12489 * Lock free, (mutex should be acquired by caller).
12492 * Pointer to Ethernet device.
12493 * @param[in, out] flow
12494 * Pointer to flow structure.
12497 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12499 struct mlx5_flow_handle *dh;
12500 uint32_t handle_idx;
12501 struct mlx5_priv *priv = dev->data->dev_private;
12505 handle_idx = flow->dev_handles;
12506 while (handle_idx) {
12507 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12511 if (dh->drv_flow) {
12512 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12513 dh->drv_flow = NULL;
12515 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12516 flow_dv_fate_resource_release(dev, dh);
12517 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12518 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12519 handle_idx = dh->next.next;
12524 * Remove the flow from the NIC and the memory.
12525 * Lock free, (mutex should be acquired by caller).
12528 * Pointer to the Ethernet device structure.
12529 * @param[in, out] flow
12530 * Pointer to flow structure.
12533 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12535 struct mlx5_flow_handle *dev_handle;
12536 struct mlx5_priv *priv = dev->data->dev_private;
12541 flow_dv_remove(dev, flow);
12542 if (flow->counter) {
12543 flow_dv_counter_free(dev, flow->counter);
12547 struct mlx5_flow_meter *fm;
12549 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12552 mlx5_flow_meter_detach(fm);
12556 flow_dv_aso_age_release(dev, flow->age);
12557 if (flow->geneve_tlv_option) {
12558 flow_dv_geneve_tlv_option_resource_release(dev);
12559 flow->geneve_tlv_option = 0;
12561 while (flow->dev_handles) {
12562 uint32_t tmp_idx = flow->dev_handles;
12564 dev_handle = mlx5_ipool_get(priv->sh->ipool
12565 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12568 flow->dev_handles = dev_handle->next.next;
12569 if (dev_handle->dvh.matcher)
12570 flow_dv_matcher_release(dev, dev_handle);
12571 if (dev_handle->dvh.rix_sample)
12572 flow_dv_sample_resource_release(dev, dev_handle);
12573 if (dev_handle->dvh.rix_dest_array)
12574 flow_dv_dest_array_resource_release(dev, dev_handle);
12575 if (dev_handle->dvh.rix_encap_decap)
12576 flow_dv_encap_decap_resource_release(dev,
12577 dev_handle->dvh.rix_encap_decap);
12578 if (dev_handle->dvh.modify_hdr)
12579 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12580 if (dev_handle->dvh.rix_push_vlan)
12581 flow_dv_push_vlan_action_resource_release(dev,
12583 if (dev_handle->dvh.rix_tag)
12584 flow_dv_tag_release(dev,
12585 dev_handle->dvh.rix_tag);
12586 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12587 flow_dv_fate_resource_release(dev, dev_handle);
12589 srss = dev_handle->rix_srss;
12590 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12594 flow_dv_shared_rss_action_release(dev, srss);
12598 * Release array of hash RX queue objects.
12602 * Pointer to the Ethernet device structure.
12603 * @param[in, out] hrxqs
12604 * Array of hash RX queue objects.
12607 * Total number of references to hash RX queue objects in *hrxqs* array
12608 * after this operation.
12611 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12612 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12617 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12618 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12628 * Release all hash RX queue objects representing shared RSS action.
12631 * Pointer to the Ethernet device structure.
12632 * @param[in, out] action
12633 * Shared RSS action to remove hash RX queue objects from.
12636 * Total number of references to hash RX queue objects stored in *action*
12637 * after this operation.
12638 * Expected to be 0 if no external references held.
12641 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12642 struct mlx5_shared_action_rss *shared_rss)
12644 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq) +
12645 __flow_dv_hrxqs_release(dev, &shared_rss->hrxq_tunnel);
12649 * Setup shared RSS action.
12650 * Prepare set of hash RX queue objects sufficient to handle all valid
12651 * hash_fields combinations (see enum ibv_rx_hash_fields).
12654 * Pointer to the Ethernet device structure.
12655 * @param[in] action_idx
12656 * Shared RSS action ipool index.
12657 * @param[in, out] action
12658 * Partially initialized shared RSS action.
12659 * @param[out] error
12660 * Perform verbose error reporting if not NULL. Initialized in case of
12664 * 0 on success, otherwise negative errno value.
12667 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12668 uint32_t action_idx,
12669 struct mlx5_shared_action_rss *shared_rss,
12670 struct rte_flow_error *error)
12672 struct mlx5_flow_rss_desc rss_desc = { 0 };
12676 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12677 return rte_flow_error_set(error, rte_errno,
12678 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12679 "cannot setup indirection table");
12681 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12682 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12683 rss_desc.const_q = shared_rss->origin.queue;
12684 rss_desc.queue_num = shared_rss->origin.queue_num;
12685 /* Set non-zero value to indicate a shared RSS. */
12686 rss_desc.shared_rss = action_idx;
12687 rss_desc.ind_tbl = shared_rss->ind_tbl;
12688 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12690 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12693 for (tunnel = 0; tunnel < 2; tunnel++) {
12694 rss_desc.tunnel = tunnel;
12695 rss_desc.hash_fields = hash_fields;
12696 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12700 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12701 "cannot get hash queue");
12702 goto error_hrxq_new;
12704 err = __flow_dv_action_rss_hrxq_set
12705 (shared_rss, hash_fields, tunnel, hrxq_idx);
12712 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12713 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12714 shared_rss->ind_tbl = NULL;
12720 * Create shared RSS action.
12723 * Pointer to the Ethernet device structure.
12725 * Shared action configuration.
12727 * RSS action specification used to create shared action.
12728 * @param[out] error
12729 * Perform verbose error reporting if not NULL. Initialized in case of
12733 * A valid shared action ID in case of success, 0 otherwise and
12734 * rte_errno is set.
12737 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12738 const struct rte_flow_shared_action_conf *conf,
12739 const struct rte_flow_action_rss *rss,
12740 struct rte_flow_error *error)
12742 struct mlx5_priv *priv = dev->data->dev_private;
12743 struct mlx5_shared_action_rss *shared_rss = NULL;
12744 void *queue = NULL;
12745 struct rte_flow_action_rss *origin;
12746 const uint8_t *rss_key;
12747 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12750 RTE_SET_USED(conf);
12751 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12753 shared_rss = mlx5_ipool_zmalloc
12754 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12755 if (!shared_rss || !queue) {
12756 rte_flow_error_set(error, ENOMEM,
12757 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12758 "cannot allocate resource memory");
12759 goto error_rss_init;
12761 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12762 rte_flow_error_set(error, E2BIG,
12763 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12764 "rss action number out of range");
12765 goto error_rss_init;
12767 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12768 sizeof(*shared_rss->ind_tbl),
12770 if (!shared_rss->ind_tbl) {
12771 rte_flow_error_set(error, ENOMEM,
12772 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12773 "cannot allocate resource memory");
12774 goto error_rss_init;
12776 memcpy(queue, rss->queue, queue_size);
12777 shared_rss->ind_tbl->queues = queue;
12778 shared_rss->ind_tbl->queues_n = rss->queue_num;
12779 origin = &shared_rss->origin;
12780 origin->func = rss->func;
12781 origin->level = rss->level;
12782 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12783 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12784 /* NULL RSS key indicates default RSS key. */
12785 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12786 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12787 origin->key = &shared_rss->key[0];
12788 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12789 origin->queue = queue;
12790 origin->queue_num = rss->queue_num;
12791 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12792 goto error_rss_init;
12793 rte_spinlock_init(&shared_rss->action_rss_sl);
12794 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12795 rte_spinlock_lock(&priv->shared_act_sl);
12796 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12797 &priv->rss_shared_actions, idx, shared_rss, next);
12798 rte_spinlock_unlock(&priv->shared_act_sl);
12802 if (shared_rss->ind_tbl)
12803 mlx5_free(shared_rss->ind_tbl);
12804 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12813 * Destroy the shared RSS action.
12814 * Release related hash RX queue objects.
12817 * Pointer to the Ethernet device structure.
12819 * The shared RSS action object ID to be removed.
12820 * @param[out] error
12821 * Perform verbose error reporting if not NULL. Initialized in case of
12825 * 0 on success, otherwise negative errno value.
12828 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12829 struct rte_flow_error *error)
12831 struct mlx5_priv *priv = dev->data->dev_private;
12832 struct mlx5_shared_action_rss *shared_rss =
12833 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12834 uint32_t old_refcnt = 1;
12836 uint16_t *queue = NULL;
12839 return rte_flow_error_set(error, EINVAL,
12840 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12841 "invalid shared action");
12842 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12844 return rte_flow_error_set(error, EBUSY,
12845 RTE_FLOW_ERROR_TYPE_ACTION,
12847 "shared rss hrxq has references");
12848 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12849 0, 0, __ATOMIC_ACQUIRE,
12851 return rte_flow_error_set(error, EBUSY,
12852 RTE_FLOW_ERROR_TYPE_ACTION,
12854 "shared rss has references");
12855 queue = shared_rss->ind_tbl->queues;
12856 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12858 return rte_flow_error_set(error, EBUSY,
12859 RTE_FLOW_ERROR_TYPE_ACTION,
12861 "shared rss indirection table has"
12864 rte_spinlock_lock(&priv->shared_act_sl);
12865 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12866 &priv->rss_shared_actions, idx, shared_rss, next);
12867 rte_spinlock_unlock(&priv->shared_act_sl);
12868 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12874 * Create shared action, lock free,
12875 * (mutex should be acquired by caller).
12876 * Dispatcher for action type specific call.
12879 * Pointer to the Ethernet device structure.
12881 * Shared action configuration.
12882 * @param[in] action
12883 * Action specification used to create shared action.
12884 * @param[out] error
12885 * Perform verbose error reporting if not NULL. Initialized in case of
12889 * A valid shared action handle in case of success, NULL otherwise and
12890 * rte_errno is set.
12892 static struct rte_flow_shared_action *
12893 flow_dv_action_create(struct rte_eth_dev *dev,
12894 const struct rte_flow_shared_action_conf *conf,
12895 const struct rte_flow_action *action,
12896 struct rte_flow_error *err)
12901 switch (action->type) {
12902 case RTE_FLOW_ACTION_TYPE_RSS:
12903 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12904 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12905 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12907 case RTE_FLOW_ACTION_TYPE_AGE:
12908 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12909 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12910 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12912 struct mlx5_aso_age_action *aso_age =
12913 flow_aso_age_get_by_idx(dev, ret);
12915 if (!aso_age->age_params.context)
12916 aso_age->age_params.context =
12917 (void *)(uintptr_t)idx;
12921 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12922 NULL, "action type not supported");
12925 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12929 * Destroy the shared action.
12930 * Release action related resources on the NIC and the memory.
12931 * Lock free, (mutex should be acquired by caller).
12932 * Dispatcher for action type specific call.
12935 * Pointer to the Ethernet device structure.
12936 * @param[in] action
12937 * The shared action object to be removed.
12938 * @param[out] error
12939 * Perform verbose error reporting if not NULL. Initialized in case of
12943 * 0 on success, otherwise negative errno value.
12946 flow_dv_action_destroy(struct rte_eth_dev *dev,
12947 struct rte_flow_shared_action *action,
12948 struct rte_flow_error *error)
12950 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12951 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12952 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12956 case MLX5_SHARED_ACTION_TYPE_RSS:
12957 return __flow_dv_action_rss_release(dev, idx, error);
12958 case MLX5_SHARED_ACTION_TYPE_AGE:
12959 ret = flow_dv_aso_age_release(dev, idx);
12962 * In this case, the last flow has a reference will
12963 * actually release the age action.
12965 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12966 " released with references %d.", idx, ret);
12969 return rte_flow_error_set(error, ENOTSUP,
12970 RTE_FLOW_ERROR_TYPE_ACTION,
12972 "action type not supported");
12977 * Updates in place shared RSS action configuration.
12980 * Pointer to the Ethernet device structure.
12982 * The shared RSS action object ID to be updated.
12983 * @param[in] action_conf
12984 * RSS action specification used to modify *shared_rss*.
12985 * @param[out] error
12986 * Perform verbose error reporting if not NULL. Initialized in case of
12990 * 0 on success, otherwise negative errno value.
12991 * @note: currently only support update of RSS queues.
12994 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12995 const struct rte_flow_action_rss *action_conf,
12996 struct rte_flow_error *error)
12998 struct mlx5_priv *priv = dev->data->dev_private;
12999 struct mlx5_shared_action_rss *shared_rss =
13000 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13002 void *queue = NULL;
13003 uint16_t *queue_old = NULL;
13004 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13007 return rte_flow_error_set(error, EINVAL,
13008 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13009 "invalid shared action to update");
13010 if (priv->obj_ops.ind_table_modify == NULL)
13011 return rte_flow_error_set(error, ENOTSUP,
13012 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13013 "cannot modify indirection table");
13014 queue = mlx5_malloc(MLX5_MEM_ZERO,
13015 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13018 return rte_flow_error_set(error, ENOMEM,
13019 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13021 "cannot allocate resource memory");
13022 memcpy(queue, action_conf->queue, queue_size);
13023 MLX5_ASSERT(shared_rss->ind_tbl);
13024 rte_spinlock_lock(&shared_rss->action_rss_sl);
13025 queue_old = shared_rss->ind_tbl->queues;
13026 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13027 queue, action_conf->queue_num, true);
13030 ret = rte_flow_error_set(error, rte_errno,
13031 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13032 "cannot update indirection table");
13034 mlx5_free(queue_old);
13035 shared_rss->origin.queue = queue;
13036 shared_rss->origin.queue_num = action_conf->queue_num;
13038 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13043 * Updates in place shared action configuration, lock free,
13044 * (mutex should be acquired by caller).
13047 * Pointer to the Ethernet device structure.
13048 * @param[in] action
13049 * The shared action object to be updated.
13050 * @param[in] action_conf
13051 * Action specification used to modify *action*.
13052 * *action_conf* should be of type correlating with type of the *action*,
13053 * otherwise considered as invalid.
13054 * @param[out] error
13055 * Perform verbose error reporting if not NULL. Initialized in case of
13059 * 0 on success, otherwise negative errno value.
13062 flow_dv_action_update(struct rte_eth_dev *dev,
13063 struct rte_flow_shared_action *action,
13064 const void *action_conf,
13065 struct rte_flow_error *err)
13067 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13068 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13069 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13072 case MLX5_SHARED_ACTION_TYPE_RSS:
13073 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13075 return rte_flow_error_set(err, ENOTSUP,
13076 RTE_FLOW_ERROR_TYPE_ACTION,
13078 "action type update not supported");
13083 flow_dv_action_query(struct rte_eth_dev *dev,
13084 const struct rte_flow_shared_action *action, void *data,
13085 struct rte_flow_error *error)
13087 struct mlx5_age_param *age_param;
13088 struct rte_flow_query_age *resp;
13089 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13090 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13091 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13094 case MLX5_SHARED_ACTION_TYPE_AGE:
13095 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13097 resp->aged = __atomic_load_n(&age_param->state,
13098 __ATOMIC_RELAXED) == AGE_TMOUT ?
13100 resp->sec_since_last_hit_valid = !resp->aged;
13101 if (resp->sec_since_last_hit_valid)
13102 resp->sec_since_last_hit = __atomic_load_n
13103 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13106 return rte_flow_error_set(error, ENOTSUP,
13107 RTE_FLOW_ERROR_TYPE_ACTION,
13109 "action type query not supported");
13114 * Query a dv flow rule for its statistics via devx.
13117 * Pointer to Ethernet device.
13119 * Pointer to the sub flow.
13121 * data retrieved by the query.
13122 * @param[out] error
13123 * Perform verbose error reporting if not NULL.
13126 * 0 on success, a negative errno value otherwise and rte_errno is set.
13129 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13130 void *data, struct rte_flow_error *error)
13132 struct mlx5_priv *priv = dev->data->dev_private;
13133 struct rte_flow_query_count *qc = data;
13135 if (!priv->config.devx)
13136 return rte_flow_error_set(error, ENOTSUP,
13137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13139 "counters are not supported");
13140 if (flow->counter) {
13141 uint64_t pkts, bytes;
13142 struct mlx5_flow_counter *cnt;
13144 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13146 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13150 return rte_flow_error_set(error, -err,
13151 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13152 NULL, "cannot read counters");
13155 qc->hits = pkts - cnt->hits;
13156 qc->bytes = bytes - cnt->bytes;
13159 cnt->bytes = bytes;
13163 return rte_flow_error_set(error, EINVAL,
13164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13166 "counters are not available");
13170 * Query a flow rule AGE action for aging information.
13173 * Pointer to Ethernet device.
13175 * Pointer to the sub flow.
13177 * data retrieved by the query.
13178 * @param[out] error
13179 * Perform verbose error reporting if not NULL.
13182 * 0 on success, a negative errno value otherwise and rte_errno is set.
13185 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13186 void *data, struct rte_flow_error *error)
13188 struct rte_flow_query_age *resp = data;
13189 struct mlx5_age_param *age_param;
13192 struct mlx5_aso_age_action *act =
13193 flow_aso_age_get_by_idx(dev, flow->age);
13195 age_param = &act->age_params;
13196 } else if (flow->counter) {
13197 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13199 if (!age_param || !age_param->timeout)
13200 return rte_flow_error_set
13202 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13203 NULL, "cannot read age data");
13205 return rte_flow_error_set(error, EINVAL,
13206 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13207 NULL, "age data not available");
13209 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13211 resp->sec_since_last_hit_valid = !resp->aged;
13212 if (resp->sec_since_last_hit_valid)
13213 resp->sec_since_last_hit = __atomic_load_n
13214 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13221 * @see rte_flow_query()
13222 * @see rte_flow_ops
13225 flow_dv_query(struct rte_eth_dev *dev,
13226 struct rte_flow *flow __rte_unused,
13227 const struct rte_flow_action *actions __rte_unused,
13228 void *data __rte_unused,
13229 struct rte_flow_error *error __rte_unused)
13233 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13234 switch (actions->type) {
13235 case RTE_FLOW_ACTION_TYPE_VOID:
13237 case RTE_FLOW_ACTION_TYPE_COUNT:
13238 ret = flow_dv_query_count(dev, flow, data, error);
13240 case RTE_FLOW_ACTION_TYPE_AGE:
13241 ret = flow_dv_query_age(dev, flow, data, error);
13244 return rte_flow_error_set(error, ENOTSUP,
13245 RTE_FLOW_ERROR_TYPE_ACTION,
13247 "action not supported");
13254 * Destroy the meter table set.
13255 * Lock free, (mutex should be acquired by caller).
13258 * Pointer to Ethernet device.
13260 * Pointer to the meter table set.
13266 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13267 struct mlx5_meter_domains_infos *tbl)
13269 struct mlx5_priv *priv = dev->data->dev_private;
13270 struct mlx5_meter_domains_infos *mtd =
13271 (struct mlx5_meter_domains_infos *)tbl;
13273 if (!mtd || !priv->config.dv_flow_en)
13275 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13276 claim_zero(mlx5_flow_os_destroy_flow
13277 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13278 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13279 claim_zero(mlx5_flow_os_destroy_flow
13280 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13281 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13282 claim_zero(mlx5_flow_os_destroy_flow
13283 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13284 if (mtd->egress.color_matcher)
13285 claim_zero(mlx5_flow_os_destroy_flow_matcher
13286 (mtd->egress.color_matcher));
13287 if (mtd->egress.any_matcher)
13288 claim_zero(mlx5_flow_os_destroy_flow_matcher
13289 (mtd->egress.any_matcher));
13290 if (mtd->egress.tbl)
13291 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13292 if (mtd->egress.sfx_tbl)
13293 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13294 if (mtd->ingress.color_matcher)
13295 claim_zero(mlx5_flow_os_destroy_flow_matcher
13296 (mtd->ingress.color_matcher));
13297 if (mtd->ingress.any_matcher)
13298 claim_zero(mlx5_flow_os_destroy_flow_matcher
13299 (mtd->ingress.any_matcher));
13300 if (mtd->ingress.tbl)
13301 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13302 if (mtd->ingress.sfx_tbl)
13303 flow_dv_tbl_resource_release(MLX5_SH(dev),
13304 mtd->ingress.sfx_tbl);
13305 if (mtd->transfer.color_matcher)
13306 claim_zero(mlx5_flow_os_destroy_flow_matcher
13307 (mtd->transfer.color_matcher));
13308 if (mtd->transfer.any_matcher)
13309 claim_zero(mlx5_flow_os_destroy_flow_matcher
13310 (mtd->transfer.any_matcher));
13311 if (mtd->transfer.tbl)
13312 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13313 if (mtd->transfer.sfx_tbl)
13314 flow_dv_tbl_resource_release(MLX5_SH(dev),
13315 mtd->transfer.sfx_tbl);
13316 if (mtd->drop_actn)
13317 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13322 /* Number of meter flow actions, count and jump or count and drop. */
13323 #define METER_ACTIONS 2
13326 * Create specify domain meter table and suffix table.
13329 * Pointer to Ethernet device.
13330 * @param[in,out] mtb
13331 * Pointer to DV meter table set.
13332 * @param[in] egress
13334 * @param[in] transfer
13336 * @param[in] color_reg_c_idx
13337 * Reg C index for color match.
13340 * 0 on success, -1 otherwise and rte_errno is set.
13343 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13344 struct mlx5_meter_domains_infos *mtb,
13345 uint8_t egress, uint8_t transfer,
13346 uint32_t color_reg_c_idx)
13348 struct mlx5_priv *priv = dev->data->dev_private;
13349 struct mlx5_dev_ctx_shared *sh = priv->sh;
13350 struct mlx5_flow_dv_match_params mask = {
13351 .size = sizeof(mask.buf),
13353 struct mlx5_flow_dv_match_params value = {
13354 .size = sizeof(value.buf),
13356 struct mlx5dv_flow_matcher_attr dv_attr = {
13357 .type = IBV_FLOW_ATTR_NORMAL,
13359 .match_criteria_enable = 0,
13360 .match_mask = (void *)&mask,
13362 void *actions[METER_ACTIONS];
13363 struct mlx5_meter_domain_info *dtb;
13364 struct rte_flow_error error;
13369 dtb = &mtb->transfer;
13371 dtb = &mtb->egress;
13373 dtb = &mtb->ingress;
13374 /* Create the meter table with METER level. */
13375 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13376 egress, transfer, false, NULL, 0,
13379 DRV_LOG(ERR, "Failed to create meter policer table.");
13382 /* Create the meter suffix table with SUFFIX level. */
13383 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13384 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13385 egress, transfer, false, NULL, 0,
13387 if (!dtb->sfx_tbl) {
13388 DRV_LOG(ERR, "Failed to create meter suffix table.");
13391 /* Create matchers, Any and Color. */
13392 dv_attr.priority = 3;
13393 dv_attr.match_criteria_enable = 0;
13394 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13395 &dtb->any_matcher);
13397 DRV_LOG(ERR, "Failed to create meter"
13398 " policer default matcher.");
13401 dv_attr.priority = 0;
13402 dv_attr.match_criteria_enable =
13403 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13404 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13405 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13406 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13407 &dtb->color_matcher);
13409 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13412 if (mtb->count_actns[RTE_MTR_DROPPED])
13413 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13414 actions[i++] = mtb->drop_actn;
13415 /* Default rule: lowest priority, match any, actions: drop. */
13416 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13418 &dtb->policer_rules[RTE_MTR_DROPPED]);
13420 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13429 * Create the needed meter and suffix tables.
13430 * Lock free, (mutex should be acquired by caller).
13433 * Pointer to Ethernet device.
13435 * Pointer to the flow meter.
13438 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13440 static struct mlx5_meter_domains_infos *
13441 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13442 const struct mlx5_flow_meter *fm)
13444 struct mlx5_priv *priv = dev->data->dev_private;
13445 struct mlx5_meter_domains_infos *mtb;
13449 if (!priv->mtr_en) {
13450 rte_errno = ENOTSUP;
13453 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13455 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13458 /* Create meter count actions */
13459 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13460 struct mlx5_flow_counter *cnt;
13461 if (!fm->policer_stats.cnt[i])
13463 cnt = flow_dv_counter_get_by_idx(dev,
13464 fm->policer_stats.cnt[i], NULL);
13465 mtb->count_actns[i] = cnt->action;
13467 /* Create drop action. */
13468 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13470 DRV_LOG(ERR, "Failed to create drop action.");
13473 /* Egress meter table. */
13474 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13476 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13479 /* Ingress meter table. */
13480 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13482 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13485 /* FDB meter table. */
13486 if (priv->config.dv_esw_en) {
13487 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13488 priv->mtr_color_reg);
13490 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13496 flow_dv_destroy_mtr_tbl(dev, mtb);
13501 * Destroy domain policer rule.
13504 * Pointer to domain table.
13507 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13511 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13512 if (dt->policer_rules[i]) {
13513 claim_zero(mlx5_flow_os_destroy_flow
13514 (dt->policer_rules[i]));
13515 dt->policer_rules[i] = NULL;
13518 if (dt->jump_actn) {
13519 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13520 dt->jump_actn = NULL;
13525 * Destroy policer rules.
13528 * Pointer to Ethernet device.
13530 * Pointer to flow meter structure.
13532 * Pointer to flow attributes.
13538 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13539 const struct mlx5_flow_meter *fm,
13540 const struct rte_flow_attr *attr)
13542 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13547 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13549 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13550 if (attr->transfer)
13551 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13556 * Create specify domain meter policer rule.
13559 * Pointer to flow meter structure.
13561 * Pointer to DV meter table set.
13562 * @param[in] mtr_reg_c
13563 * Color match REG_C.
13566 * 0 on success, -1 otherwise.
13569 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13570 struct mlx5_meter_domain_info *dtb,
13573 struct mlx5_flow_dv_match_params matcher = {
13574 .size = sizeof(matcher.buf),
13576 struct mlx5_flow_dv_match_params value = {
13577 .size = sizeof(value.buf),
13579 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13580 void *actions[METER_ACTIONS];
13584 /* Create jump action. */
13585 if (!dtb->jump_actn)
13586 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13587 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13589 DRV_LOG(ERR, "Failed to create policer jump action.");
13592 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13595 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13596 rte_col_2_mlx5_col(i), UINT8_MAX);
13597 if (mtb->count_actns[i])
13598 actions[j++] = mtb->count_actns[i];
13599 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13600 actions[j++] = mtb->drop_actn;
13602 actions[j++] = dtb->jump_actn;
13603 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13604 (void *)&value, j, actions,
13605 &dtb->policer_rules[i]);
13607 DRV_LOG(ERR, "Failed to create policer rule.");
13618 * Create policer rules.
13621 * Pointer to Ethernet device.
13623 * Pointer to flow meter structure.
13625 * Pointer to flow attributes.
13628 * 0 on success, -1 otherwise.
13631 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13632 struct mlx5_flow_meter *fm,
13633 const struct rte_flow_attr *attr)
13635 struct mlx5_priv *priv = dev->data->dev_private;
13636 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13639 if (attr->egress) {
13640 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13641 priv->mtr_color_reg);
13643 DRV_LOG(ERR, "Failed to create egress policer.");
13647 if (attr->ingress) {
13648 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13649 priv->mtr_color_reg);
13651 DRV_LOG(ERR, "Failed to create ingress policer.");
13655 if (attr->transfer) {
13656 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13657 priv->mtr_color_reg);
13659 DRV_LOG(ERR, "Failed to create transfer policer.");
13665 flow_dv_destroy_policer_rules(dev, fm, attr);
13670 * Validate the batch counter support in root table.
13672 * Create a simple flow with invalid counter and drop action on root table to
13673 * validate if batch counter with offset on root table is supported or not.
13676 * Pointer to rte_eth_dev structure.
13679 * 0 on success, a negative errno value otherwise and rte_errno is set.
13682 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13684 struct mlx5_priv *priv = dev->data->dev_private;
13685 struct mlx5_dev_ctx_shared *sh = priv->sh;
13686 struct mlx5_flow_dv_match_params mask = {
13687 .size = sizeof(mask.buf),
13689 struct mlx5_flow_dv_match_params value = {
13690 .size = sizeof(value.buf),
13692 struct mlx5dv_flow_matcher_attr dv_attr = {
13693 .type = IBV_FLOW_ATTR_NORMAL,
13695 .match_criteria_enable = 0,
13696 .match_mask = (void *)&mask,
13698 void *actions[2] = { 0 };
13699 struct mlx5_flow_tbl_resource *tbl = NULL;
13700 struct mlx5_devx_obj *dcs = NULL;
13701 void *matcher = NULL;
13705 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13708 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13711 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13715 actions[1] = priv->drop_queue.hrxq->action;
13716 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13717 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13721 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13725 * If batch counter with offset is not supported, the driver will not
13726 * validate the invalid offset value, flow create should success.
13727 * In this case, it means batch counter is not supported in root table.
13729 * Otherwise, if flow create is failed, counter offset is supported.
13732 DRV_LOG(INFO, "Batch counter is not supported in root "
13733 "table. Switch to fallback mode.");
13734 rte_errno = ENOTSUP;
13736 claim_zero(mlx5_flow_os_destroy_flow(flow));
13738 /* Check matcher to make sure validate fail at flow create. */
13739 if (!matcher || (matcher && errno != EINVAL))
13740 DRV_LOG(ERR, "Unexpected error in counter offset "
13741 "support detection");
13745 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13747 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13749 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13751 claim_zero(mlx5_devx_cmd_destroy(dcs));
13756 * Query a devx counter.
13759 * Pointer to the Ethernet device structure.
13761 * Index to the flow counter.
13763 * Set to clear the counter statistics.
13765 * The statistics value of packets.
13766 * @param[out] bytes
13767 * The statistics value of bytes.
13770 * 0 on success, otherwise return -1.
13773 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13774 uint64_t *pkts, uint64_t *bytes)
13776 struct mlx5_priv *priv = dev->data->dev_private;
13777 struct mlx5_flow_counter *cnt;
13778 uint64_t inn_pkts, inn_bytes;
13781 if (!priv->config.devx)
13784 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13787 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13788 *pkts = inn_pkts - cnt->hits;
13789 *bytes = inn_bytes - cnt->bytes;
13791 cnt->hits = inn_pkts;
13792 cnt->bytes = inn_bytes;
13798 * Get aged-out flows.
13801 * Pointer to the Ethernet device structure.
13802 * @param[in] context
13803 * The address of an array of pointers to the aged-out flows contexts.
13804 * @param[in] nb_contexts
13805 * The length of context array pointers.
13806 * @param[out] error
13807 * Perform verbose error reporting if not NULL. Initialized in case of
13811 * how many contexts get in success, otherwise negative errno value.
13812 * if nb_contexts is 0, return the amount of all aged contexts.
13813 * if nb_contexts is not 0 , return the amount of aged flows reported
13814 * in the context array.
13815 * @note: only stub for now
13818 flow_get_aged_flows(struct rte_eth_dev *dev,
13820 uint32_t nb_contexts,
13821 struct rte_flow_error *error)
13823 struct mlx5_priv *priv = dev->data->dev_private;
13824 struct mlx5_age_info *age_info;
13825 struct mlx5_age_param *age_param;
13826 struct mlx5_flow_counter *counter;
13827 struct mlx5_aso_age_action *act;
13830 if (nb_contexts && !context)
13831 return rte_flow_error_set(error, EINVAL,
13832 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13833 NULL, "empty context");
13834 age_info = GET_PORT_AGE_INFO(priv);
13835 rte_spinlock_lock(&age_info->aged_sl);
13836 LIST_FOREACH(act, &age_info->aged_aso, next) {
13839 context[nb_flows - 1] =
13840 act->age_params.context;
13841 if (!(--nb_contexts))
13845 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13848 age_param = MLX5_CNT_TO_AGE(counter);
13849 context[nb_flows - 1] = age_param->context;
13850 if (!(--nb_contexts))
13854 rte_spinlock_unlock(&age_info->aged_sl);
13855 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13860 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13863 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13865 return flow_dv_counter_alloc(dev, 0);
13869 * Validate shared action.
13870 * Dispatcher for action type specific validation.
13873 * Pointer to the Ethernet device structure.
13875 * Shared action configuration.
13876 * @param[in] action
13877 * The shared action object to validate.
13878 * @param[out] error
13879 * Perform verbose error reporting if not NULL. Initialized in case of
13883 * 0 on success, otherwise negative errno value.
13886 flow_dv_action_validate(struct rte_eth_dev *dev,
13887 const struct rte_flow_shared_action_conf *conf,
13888 const struct rte_flow_action *action,
13889 struct rte_flow_error *err)
13891 struct mlx5_priv *priv = dev->data->dev_private;
13893 RTE_SET_USED(conf);
13894 switch (action->type) {
13895 case RTE_FLOW_ACTION_TYPE_RSS:
13897 * priv->obj_ops is set according to driver capabilities.
13898 * When DevX capabilities are
13899 * sufficient, it is set to devx_obj_ops.
13900 * Otherwise, it is set to ibv_obj_ops.
13901 * ibv_obj_ops doesn't support ind_table_modify operation.
13902 * In this case the shared RSS action can't be used.
13904 if (priv->obj_ops.ind_table_modify == NULL)
13905 return rte_flow_error_set
13907 RTE_FLOW_ERROR_TYPE_ACTION,
13909 "shared RSS action not supported");
13910 return mlx5_validate_action_rss(dev, action, err);
13911 case RTE_FLOW_ACTION_TYPE_AGE:
13912 if (!priv->sh->aso_age_mng)
13913 return rte_flow_error_set(err, ENOTSUP,
13914 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13916 "shared age action not supported");
13917 return flow_dv_validate_action_age(0, action, dev, err);
13919 return rte_flow_error_set(err, ENOTSUP,
13920 RTE_FLOW_ERROR_TYPE_ACTION,
13922 "action type not supported");
13927 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13929 struct mlx5_priv *priv = dev->data->dev_private;
13932 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13933 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13938 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13939 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13943 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13944 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13951 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13952 .validate = flow_dv_validate,
13953 .prepare = flow_dv_prepare,
13954 .translate = flow_dv_translate,
13955 .apply = flow_dv_apply,
13956 .remove = flow_dv_remove,
13957 .destroy = flow_dv_destroy,
13958 .query = flow_dv_query,
13959 .create_mtr_tbls = flow_dv_create_mtr_tbl,
13960 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13961 .create_policer_rules = flow_dv_create_policer_rules,
13962 .destroy_policer_rules = flow_dv_destroy_policer_rules,
13963 .counter_alloc = flow_dv_counter_allocate,
13964 .counter_free = flow_dv_counter_free,
13965 .counter_query = flow_dv_counter_query,
13966 .get_aged_flows = flow_get_aged_flows,
13967 .action_validate = flow_dv_action_validate,
13968 .action_create = flow_dv_action_create,
13969 .action_destroy = flow_dv_action_destroy,
13970 .action_update = flow_dv_action_update,
13971 .action_query = flow_dv_action_query,
13972 .sync_domain = flow_dv_sync_domain,
13975 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */