1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
101 if (priv->pci_dev == NULL)
103 switch (priv->pci_dev->id.device_id) {
104 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
105 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
106 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
107 return (int16_t)0xfffe;
114 * Initialize flow attributes structure according to flow items' types.
116 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
117 * mode. For tunnel mode, the items to be modified are the outermost ones.
120 * Pointer to item specification.
122 * Pointer to flow attributes structure.
123 * @param[in] dev_flow
124 * Pointer to the sub flow.
125 * @param[in] tunnel_decap
126 * Whether action is after tunnel decapsulation.
129 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
130 struct mlx5_flow *dev_flow, bool tunnel_decap)
132 uint64_t layers = dev_flow->handle->layers;
135 * If layers is already initialized, it means this dev_flow is the
136 * suffix flow, the layers flags is set by the prefix flow. Need to
137 * use the layer flags from prefix flow as the suffix flow may not
138 * have the user defined items as the flow is split.
141 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
143 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
145 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
152 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
153 uint8_t next_protocol = 0xff;
154 switch (item->type) {
155 case RTE_FLOW_ITEM_TYPE_GRE:
156 case RTE_FLOW_ITEM_TYPE_NVGRE:
157 case RTE_FLOW_ITEM_TYPE_VXLAN:
158 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
159 case RTE_FLOW_ITEM_TYPE_GENEVE:
160 case RTE_FLOW_ITEM_TYPE_MPLS:
164 case RTE_FLOW_ITEM_TYPE_IPV4:
167 if (item->mask != NULL &&
168 ((const struct rte_flow_item_ipv4 *)
169 item->mask)->hdr.next_proto_id)
171 ((const struct rte_flow_item_ipv4 *)
172 (item->spec))->hdr.next_proto_id &
173 ((const struct rte_flow_item_ipv4 *)
174 (item->mask))->hdr.next_proto_id;
175 if ((next_protocol == IPPROTO_IPIP ||
176 next_protocol == IPPROTO_IPV6) && tunnel_decap)
179 case RTE_FLOW_ITEM_TYPE_IPV6:
182 if (item->mask != NULL &&
183 ((const struct rte_flow_item_ipv6 *)
184 item->mask)->hdr.proto)
186 ((const struct rte_flow_item_ipv6 *)
187 (item->spec))->hdr.proto &
188 ((const struct rte_flow_item_ipv6 *)
189 (item->mask))->hdr.proto;
190 if ((next_protocol == IPPROTO_IPIP ||
191 next_protocol == IPPROTO_IPV6) && tunnel_decap)
194 case RTE_FLOW_ITEM_TYPE_UDP:
198 case RTE_FLOW_ITEM_TYPE_TCP:
210 * Convert rte_mtr_color to mlx5 color.
219 rte_col_2_mlx5_col(enum rte_color rcol)
222 case RTE_COLOR_GREEN:
223 return MLX5_FLOW_COLOR_GREEN;
224 case RTE_COLOR_YELLOW:
225 return MLX5_FLOW_COLOR_YELLOW;
227 return MLX5_FLOW_COLOR_RED;
231 return MLX5_FLOW_COLOR_UNDEFINED;
234 struct field_modify_info {
235 uint32_t size; /* Size of field in protocol header, in bytes. */
236 uint32_t offset; /* Offset of field in protocol header, in bytes. */
237 enum mlx5_modification_field id;
240 struct field_modify_info modify_eth[] = {
241 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
242 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
243 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
244 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
248 struct field_modify_info modify_vlan_out_first_vid[] = {
249 /* Size in bits !!! */
250 {12, 0, MLX5_MODI_OUT_FIRST_VID},
254 struct field_modify_info modify_ipv4[] = {
255 {1, 1, MLX5_MODI_OUT_IP_DSCP},
256 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
257 {4, 12, MLX5_MODI_OUT_SIPV4},
258 {4, 16, MLX5_MODI_OUT_DIPV4},
262 struct field_modify_info modify_ipv6[] = {
263 {1, 0, MLX5_MODI_OUT_IP_DSCP},
264 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
265 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
266 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
267 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
268 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
269 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
270 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
271 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
272 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
276 struct field_modify_info modify_udp[] = {
277 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
278 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
282 struct field_modify_info modify_tcp[] = {
283 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
284 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
285 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
286 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
291 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
292 uint8_t next_protocol, uint64_t *item_flags,
295 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
296 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
297 if (next_protocol == IPPROTO_IPIP) {
298 *item_flags |= MLX5_FLOW_LAYER_IPIP;
301 if (next_protocol == IPPROTO_IPV6) {
302 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
307 static inline struct mlx5_hlist *
308 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
309 const char *name, uint32_t size, bool direct_key,
310 bool lcores_share, void *ctx,
311 mlx5_list_create_cb cb_create,
312 mlx5_list_match_cb cb_match,
313 mlx5_list_remove_cb cb_remove,
314 mlx5_list_clone_cb cb_clone,
315 mlx5_list_clone_free_cb cb_clone_free)
317 struct mlx5_hlist *hl;
318 struct mlx5_hlist *expected = NULL;
319 char s[MLX5_NAME_SIZE];
321 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
324 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
325 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
326 ctx, cb_create, cb_match, cb_remove, cb_clone,
329 DRV_LOG(ERR, "%s hash creation failed", name);
333 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
336 mlx5_hlist_destroy(hl);
337 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
342 /* Update VLAN's VID/PCP based on input rte_flow_action.
345 * Pointer to struct rte_flow_action.
347 * Pointer to struct rte_vlan_hdr.
350 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
351 struct rte_vlan_hdr *vlan)
354 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
356 ((const struct rte_flow_action_of_set_vlan_pcp *)
357 action->conf)->vlan_pcp;
358 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
359 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
360 vlan->vlan_tci |= vlan_tci;
361 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
362 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
363 vlan->vlan_tci |= rte_be_to_cpu_16
364 (((const struct rte_flow_action_of_set_vlan_vid *)
365 action->conf)->vlan_vid);
370 * Fetch 1, 2, 3 or 4 byte field from the byte array
371 * and return as unsigned integer in host-endian format.
374 * Pointer to data array.
376 * Size of field to extract.
379 * converted field in host endian format.
381 static inline uint32_t
382 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
391 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
394 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
395 ret = (ret << 8) | *(data + sizeof(uint16_t));
398 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
409 * Convert modify-header action to DV specification.
411 * Data length of each action is determined by provided field description
412 * and the item mask. Data bit offset and width of each action is determined
413 * by provided item mask.
416 * Pointer to item specification.
418 * Pointer to field modification information.
419 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
420 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
421 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
423 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
424 * Negative offset value sets the same offset as source offset.
425 * size field is ignored, value is taken from source field.
426 * @param[in,out] resource
427 * Pointer to the modify-header resource.
429 * Type of modification.
431 * Pointer to the error structure.
434 * 0 on success, a negative errno value otherwise and rte_errno is set.
437 flow_dv_convert_modify_action(struct rte_flow_item *item,
438 struct field_modify_info *field,
439 struct field_modify_info *dcopy,
440 struct mlx5_flow_dv_modify_hdr_resource *resource,
441 uint32_t type, struct rte_flow_error *error)
443 uint32_t i = resource->actions_num;
444 struct mlx5_modification_cmd *actions = resource->actions;
445 uint32_t carry_b = 0;
448 * The item and mask are provided in big-endian format.
449 * The fields should be presented as in big-endian format either.
450 * Mask must be always present, it defines the actual field width.
452 MLX5_ASSERT(item->mask);
453 MLX5_ASSERT(field->size);
459 bool next_field = true;
460 bool next_dcopy = true;
462 if (i >= MLX5_MAX_MODIFY_NUM)
463 return rte_flow_error_set(error, EINVAL,
464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
465 "too many items to modify");
466 /* Fetch variable byte size mask from the array. */
467 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
468 field->offset, field->size);
473 /* Deduce actual data width in bits from mask value. */
474 off_b = rte_bsf32(mask) + carry_b;
475 size_b = sizeof(uint32_t) * CHAR_BIT -
476 off_b - __builtin_clz(mask);
478 actions[i] = (struct mlx5_modification_cmd) {
482 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
485 if (type == MLX5_MODIFICATION_TYPE_COPY) {
487 actions[i].dst_field = dcopy->id;
488 actions[i].dst_offset =
489 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
490 /* Convert entire record to big-endian format. */
491 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
493 * Destination field overflow. Copy leftovers of
494 * a source field to the next destination field.
497 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
500 dcopy->size * CHAR_BIT - dcopy->offset;
501 carry_b = actions[i].length;
505 * Not enough bits in a source filed to fill a
506 * destination field. Switch to the next source.
508 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
509 (size_b == field->size * CHAR_BIT - off_b)) {
511 field->size * CHAR_BIT - off_b;
512 dcopy->offset += actions[i].length;
518 MLX5_ASSERT(item->spec);
519 data = flow_dv_fetch_field((const uint8_t *)item->spec +
520 field->offset, field->size);
521 /* Shift out the trailing masked bits from data. */
522 data = (data & mask) >> off_b;
523 actions[i].data1 = rte_cpu_to_be_32(data);
525 /* Convert entire record to expected big-endian format. */
526 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
530 } while (field->size);
531 if (resource->actions_num == i)
532 return rte_flow_error_set(error, EINVAL,
533 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
534 "invalid modification flow item");
535 resource->actions_num = i;
540 * Convert modify-header set IPv4 address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_ipv4
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_ipv4 *conf =
559 (const struct rte_flow_action_set_ipv4 *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
561 struct rte_flow_item_ipv4 ipv4;
562 struct rte_flow_item_ipv4 ipv4_mask;
564 memset(&ipv4, 0, sizeof(ipv4));
565 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
567 ipv4.hdr.src_addr = conf->ipv4_addr;
568 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
570 ipv4.hdr.dst_addr = conf->ipv4_addr;
571 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
574 item.mask = &ipv4_mask;
575 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
576 MLX5_MODIFICATION_TYPE_SET, error);
580 * Convert modify-header set IPv6 address action to DV specification.
582 * @param[in,out] resource
583 * Pointer to the modify-header resource.
585 * Pointer to action specification.
587 * Pointer to the error structure.
590 * 0 on success, a negative errno value otherwise and rte_errno is set.
593 flow_dv_convert_action_modify_ipv6
594 (struct mlx5_flow_dv_modify_hdr_resource *resource,
595 const struct rte_flow_action *action,
596 struct rte_flow_error *error)
598 const struct rte_flow_action_set_ipv6 *conf =
599 (const struct rte_flow_action_set_ipv6 *)(action->conf);
600 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
601 struct rte_flow_item_ipv6 ipv6;
602 struct rte_flow_item_ipv6 ipv6_mask;
604 memset(&ipv6, 0, sizeof(ipv6));
605 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
606 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
607 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
608 sizeof(ipv6.hdr.src_addr));
609 memcpy(&ipv6_mask.hdr.src_addr,
610 &rte_flow_item_ipv6_mask.hdr.src_addr,
611 sizeof(ipv6.hdr.src_addr));
613 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
614 sizeof(ipv6.hdr.dst_addr));
615 memcpy(&ipv6_mask.hdr.dst_addr,
616 &rte_flow_item_ipv6_mask.hdr.dst_addr,
617 sizeof(ipv6.hdr.dst_addr));
620 item.mask = &ipv6_mask;
621 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
622 MLX5_MODIFICATION_TYPE_SET, error);
626 * Convert modify-header set MAC address action to DV specification.
628 * @param[in,out] resource
629 * Pointer to the modify-header resource.
631 * Pointer to action specification.
633 * Pointer to the error structure.
636 * 0 on success, a negative errno value otherwise and rte_errno is set.
639 flow_dv_convert_action_modify_mac
640 (struct mlx5_flow_dv_modify_hdr_resource *resource,
641 const struct rte_flow_action *action,
642 struct rte_flow_error *error)
644 const struct rte_flow_action_set_mac *conf =
645 (const struct rte_flow_action_set_mac *)(action->conf);
646 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
647 struct rte_flow_item_eth eth;
648 struct rte_flow_item_eth eth_mask;
650 memset(ð, 0, sizeof(eth));
651 memset(ð_mask, 0, sizeof(eth_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
653 memcpy(ð.src.addr_bytes, &conf->mac_addr,
654 sizeof(eth.src.addr_bytes));
655 memcpy(ð_mask.src.addr_bytes,
656 &rte_flow_item_eth_mask.src.addr_bytes,
657 sizeof(eth_mask.src.addr_bytes));
659 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
660 sizeof(eth.dst.addr_bytes));
661 memcpy(ð_mask.dst.addr_bytes,
662 &rte_flow_item_eth_mask.dst.addr_bytes,
663 sizeof(eth_mask.dst.addr_bytes));
666 item.mask = ð_mask;
667 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
668 MLX5_MODIFICATION_TYPE_SET, error);
672 * Convert modify-header set VLAN VID action to DV specification.
674 * @param[in,out] resource
675 * Pointer to the modify-header resource.
677 * Pointer to action specification.
679 * Pointer to the error structure.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 flow_dv_convert_action_modify_vlan_vid
686 (struct mlx5_flow_dv_modify_hdr_resource *resource,
687 const struct rte_flow_action *action,
688 struct rte_flow_error *error)
690 const struct rte_flow_action_of_set_vlan_vid *conf =
691 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
692 int i = resource->actions_num;
693 struct mlx5_modification_cmd *actions = resource->actions;
694 struct field_modify_info *field = modify_vlan_out_first_vid;
696 if (i >= MLX5_MAX_MODIFY_NUM)
697 return rte_flow_error_set(error, EINVAL,
698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
699 "too many items to modify");
700 actions[i] = (struct mlx5_modification_cmd) {
701 .action_type = MLX5_MODIFICATION_TYPE_SET,
703 .length = field->size,
704 .offset = field->offset,
706 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
707 actions[i].data1 = conf->vlan_vid;
708 actions[i].data1 = actions[i].data1 << 16;
709 resource->actions_num = ++i;
714 * Convert modify-header set TP action to DV specification.
716 * @param[in,out] resource
717 * Pointer to the modify-header resource.
719 * Pointer to action specification.
721 * Pointer to rte_flow_item objects list.
723 * Pointer to flow attributes structure.
724 * @param[in] dev_flow
725 * Pointer to the sub flow.
726 * @param[in] tunnel_decap
727 * Whether action is after tunnel decapsulation.
729 * Pointer to the error structure.
732 * 0 on success, a negative errno value otherwise and rte_errno is set.
735 flow_dv_convert_action_modify_tp
736 (struct mlx5_flow_dv_modify_hdr_resource *resource,
737 const struct rte_flow_action *action,
738 const struct rte_flow_item *items,
739 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
740 bool tunnel_decap, struct rte_flow_error *error)
742 const struct rte_flow_action_set_tp *conf =
743 (const struct rte_flow_action_set_tp *)(action->conf);
744 struct rte_flow_item item;
745 struct rte_flow_item_udp udp;
746 struct rte_flow_item_udp udp_mask;
747 struct rte_flow_item_tcp tcp;
748 struct rte_flow_item_tcp tcp_mask;
749 struct field_modify_info *field;
752 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
754 memset(&udp, 0, sizeof(udp));
755 memset(&udp_mask, 0, sizeof(udp_mask));
756 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
757 udp.hdr.src_port = conf->port;
758 udp_mask.hdr.src_port =
759 rte_flow_item_udp_mask.hdr.src_port;
761 udp.hdr.dst_port = conf->port;
762 udp_mask.hdr.dst_port =
763 rte_flow_item_udp_mask.hdr.dst_port;
765 item.type = RTE_FLOW_ITEM_TYPE_UDP;
767 item.mask = &udp_mask;
770 MLX5_ASSERT(attr->tcp);
771 memset(&tcp, 0, sizeof(tcp));
772 memset(&tcp_mask, 0, sizeof(tcp_mask));
773 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
774 tcp.hdr.src_port = conf->port;
775 tcp_mask.hdr.src_port =
776 rte_flow_item_tcp_mask.hdr.src_port;
778 tcp.hdr.dst_port = conf->port;
779 tcp_mask.hdr.dst_port =
780 rte_flow_item_tcp_mask.hdr.dst_port;
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header set TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_action *action,
816 const struct rte_flow_item *items,
817 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
818 bool tunnel_decap, struct rte_flow_error *error)
820 const struct rte_flow_action_set_ttl *conf =
821 (const struct rte_flow_action_set_ttl *)(action->conf);
822 struct rte_flow_item item;
823 struct rte_flow_item_ipv4 ipv4;
824 struct rte_flow_item_ipv4 ipv4_mask;
825 struct rte_flow_item_ipv6 ipv6;
826 struct rte_flow_item_ipv6 ipv6_mask;
827 struct field_modify_info *field;
830 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
832 memset(&ipv4, 0, sizeof(ipv4));
833 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
834 ipv4.hdr.time_to_live = conf->ttl_value;
835 ipv4_mask.hdr.time_to_live = 0xFF;
836 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
838 item.mask = &ipv4_mask;
841 MLX5_ASSERT(attr->ipv6);
842 memset(&ipv6, 0, sizeof(ipv6));
843 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
844 ipv6.hdr.hop_limits = conf->ttl_value;
845 ipv6_mask.hdr.hop_limits = 0xFF;
846 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
848 item.mask = &ipv6_mask;
851 return flow_dv_convert_modify_action(&item, field, NULL, resource,
852 MLX5_MODIFICATION_TYPE_SET, error);
856 * Convert modify-header decrement TTL action to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to rte_flow_item objects list.
865 * Pointer to flow attributes structure.
866 * @param[in] dev_flow
867 * Pointer to the sub flow.
868 * @param[in] tunnel_decap
869 * Whether action is after tunnel decapsulation.
871 * Pointer to the error structure.
874 * 0 on success, a negative errno value otherwise and rte_errno is set.
877 flow_dv_convert_action_modify_dec_ttl
878 (struct mlx5_flow_dv_modify_hdr_resource *resource,
879 const struct rte_flow_item *items,
880 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
881 bool tunnel_decap, struct rte_flow_error *error)
883 struct rte_flow_item item;
884 struct rte_flow_item_ipv4 ipv4;
885 struct rte_flow_item_ipv4 ipv4_mask;
886 struct rte_flow_item_ipv6 ipv6;
887 struct rte_flow_item_ipv6 ipv6_mask;
888 struct field_modify_info *field;
891 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
893 memset(&ipv4, 0, sizeof(ipv4));
894 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
895 ipv4.hdr.time_to_live = 0xFF;
896 ipv4_mask.hdr.time_to_live = 0xFF;
897 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
899 item.mask = &ipv4_mask;
902 MLX5_ASSERT(attr->ipv6);
903 memset(&ipv6, 0, sizeof(ipv6));
904 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
905 ipv6.hdr.hop_limits = 0xFF;
906 ipv6_mask.hdr.hop_limits = 0xFF;
907 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
909 item.mask = &ipv6_mask;
912 return flow_dv_convert_modify_action(&item, field, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
917 * Convert modify-header increment/decrement TCP Sequence number
918 * to DV specification.
920 * @param[in,out] resource
921 * Pointer to the modify-header resource.
923 * Pointer to action specification.
925 * Pointer to the error structure.
928 * 0 on success, a negative errno value otherwise and rte_errno is set.
931 flow_dv_convert_action_modify_tcp_seq
932 (struct mlx5_flow_dv_modify_hdr_resource *resource,
933 const struct rte_flow_action *action,
934 struct rte_flow_error *error)
936 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
937 uint64_t value = rte_be_to_cpu_32(*conf);
938 struct rte_flow_item item;
939 struct rte_flow_item_tcp tcp;
940 struct rte_flow_item_tcp tcp_mask;
942 memset(&tcp, 0, sizeof(tcp));
943 memset(&tcp_mask, 0, sizeof(tcp_mask));
944 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
946 * The HW has no decrement operation, only increment operation.
947 * To simulate decrement X from Y using increment operation
948 * we need to add UINT32_MAX X times to Y.
949 * Each adding of UINT32_MAX decrements Y by 1.
952 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
953 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
954 item.type = RTE_FLOW_ITEM_TYPE_TCP;
956 item.mask = &tcp_mask;
957 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
958 MLX5_MODIFICATION_TYPE_ADD, error);
962 * Convert modify-header increment/decrement TCP Acknowledgment number
963 * to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_modify_tcp_ack
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
982 uint64_t value = rte_be_to_cpu_32(*conf);
983 struct rte_flow_item item;
984 struct rte_flow_item_tcp tcp;
985 struct rte_flow_item_tcp tcp_mask;
987 memset(&tcp, 0, sizeof(tcp));
988 memset(&tcp_mask, 0, sizeof(tcp_mask));
989 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
991 * The HW has no decrement operation, only increment operation.
992 * To simulate decrement X from Y using increment operation
993 * we need to add UINT32_MAX X times to Y.
994 * Each adding of UINT32_MAX decrements Y by 1.
997 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
998 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
999 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1001 item.mask = &tcp_mask;
1002 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1003 MLX5_MODIFICATION_TYPE_ADD, error);
1006 static enum mlx5_modification_field reg_to_field[] = {
1007 [REG_NON] = MLX5_MODI_OUT_NONE,
1008 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1009 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1010 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1011 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1012 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1013 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1014 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1015 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1016 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1017 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1021 * Convert register set to DV specification.
1023 * @param[in,out] resource
1024 * Pointer to the modify-header resource.
1026 * Pointer to action specification.
1028 * Pointer to the error structure.
1031 * 0 on success, a negative errno value otherwise and rte_errno is set.
1034 flow_dv_convert_action_set_reg
1035 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1036 const struct rte_flow_action *action,
1037 struct rte_flow_error *error)
1039 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1040 struct mlx5_modification_cmd *actions = resource->actions;
1041 uint32_t i = resource->actions_num;
1043 if (i >= MLX5_MAX_MODIFY_NUM)
1044 return rte_flow_error_set(error, EINVAL,
1045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1046 "too many items to modify");
1047 MLX5_ASSERT(conf->id != REG_NON);
1048 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1049 actions[i] = (struct mlx5_modification_cmd) {
1050 .action_type = MLX5_MODIFICATION_TYPE_SET,
1051 .field = reg_to_field[conf->id],
1052 .offset = conf->offset,
1053 .length = conf->length,
1055 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1056 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1058 resource->actions_num = i;
1063 * Convert SET_TAG action to DV specification.
1066 * Pointer to the rte_eth_dev structure.
1067 * @param[in,out] resource
1068 * Pointer to the modify-header resource.
1070 * Pointer to action specification.
1072 * Pointer to the error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_convert_action_set_tag
1079 (struct rte_eth_dev *dev,
1080 struct mlx5_flow_dv_modify_hdr_resource *resource,
1081 const struct rte_flow_action_set_tag *conf,
1082 struct rte_flow_error *error)
1084 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1085 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1086 struct rte_flow_item item = {
1090 struct field_modify_info reg_c_x[] = {
1093 enum mlx5_modification_field reg_type;
1096 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1099 MLX5_ASSERT(ret != REG_NON);
1100 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1101 reg_type = reg_to_field[ret];
1102 MLX5_ASSERT(reg_type > 0);
1103 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1104 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1105 MLX5_MODIFICATION_TYPE_SET, error);
1109 * Convert internal COPY_REG action to DV specification.
1112 * Pointer to the rte_eth_dev structure.
1113 * @param[in,out] res
1114 * Pointer to the modify-header resource.
1116 * Pointer to action specification.
1118 * Pointer to the error structure.
1121 * 0 on success, a negative errno value otherwise and rte_errno is set.
1124 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1125 struct mlx5_flow_dv_modify_hdr_resource *res,
1126 const struct rte_flow_action *action,
1127 struct rte_flow_error *error)
1129 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1130 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1131 struct rte_flow_item item = {
1135 struct field_modify_info reg_src[] = {
1136 {4, 0, reg_to_field[conf->src]},
1139 struct field_modify_info reg_dst = {
1141 .id = reg_to_field[conf->dst],
1143 /* Adjust reg_c[0] usage according to reported mask. */
1144 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1145 struct mlx5_priv *priv = dev->data->dev_private;
1146 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1148 MLX5_ASSERT(reg_c0);
1149 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1150 if (conf->dst == REG_C_0) {
1151 /* Copy to reg_c[0], within mask only. */
1152 reg_dst.offset = rte_bsf32(reg_c0);
1153 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1156 mask = rte_cpu_to_be_32(reg_c0);
1159 return flow_dv_convert_modify_action(&item,
1160 reg_src, ®_dst, res,
1161 MLX5_MODIFICATION_TYPE_COPY,
1166 * Convert MARK action to DV specification. This routine is used
1167 * in extensive metadata only and requires metadata register to be
1168 * handled. In legacy mode hardware tag resource is engaged.
1171 * Pointer to the rte_eth_dev structure.
1173 * Pointer to MARK action specification.
1174 * @param[in,out] resource
1175 * Pointer to the modify-header resource.
1177 * Pointer to the error structure.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1184 const struct rte_flow_action_mark *conf,
1185 struct mlx5_flow_dv_modify_hdr_resource *resource,
1186 struct rte_flow_error *error)
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1190 priv->sh->dv_mark_mask);
1191 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1192 struct rte_flow_item item = {
1196 struct field_modify_info reg_c_x[] = {
1202 return rte_flow_error_set(error, EINVAL,
1203 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1204 NULL, "zero mark action mask");
1205 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1208 MLX5_ASSERT(reg > 0);
1209 if (reg == REG_C_0) {
1210 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1211 uint32_t shl_c0 = rte_bsf32(msk_c0);
1213 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1214 mask = rte_cpu_to_be_32(mask) & msk_c0;
1215 mask = rte_cpu_to_be_32(mask << shl_c0);
1217 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1218 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1219 MLX5_MODIFICATION_TYPE_SET, error);
1223 * Get metadata register index for specified steering domain.
1226 * Pointer to the rte_eth_dev structure.
1228 * Attributes of flow to determine steering domain.
1230 * Pointer to the error structure.
1233 * positive index on success, a negative errno value otherwise
1234 * and rte_errno is set.
1236 static enum modify_reg
1237 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1238 const struct rte_flow_attr *attr,
1239 struct rte_flow_error *error)
1242 mlx5_flow_get_reg_id(dev, attr->transfer ?
1246 MLX5_METADATA_RX, 0, error);
1248 return rte_flow_error_set(error,
1249 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1250 NULL, "unavailable "
1251 "metadata register");
1256 * Convert SET_META action to DV specification.
1259 * Pointer to the rte_eth_dev structure.
1260 * @param[in,out] resource
1261 * Pointer to the modify-header resource.
1263 * Attributes of flow that includes this item.
1265 * Pointer to action specification.
1267 * Pointer to the error structure.
1270 * 0 on success, a negative errno value otherwise and rte_errno is set.
1273 flow_dv_convert_action_set_meta
1274 (struct rte_eth_dev *dev,
1275 struct mlx5_flow_dv_modify_hdr_resource *resource,
1276 const struct rte_flow_attr *attr,
1277 const struct rte_flow_action_set_meta *conf,
1278 struct rte_flow_error *error)
1280 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1281 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1282 struct rte_flow_item item = {
1286 struct field_modify_info reg_c_x[] = {
1289 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1293 MLX5_ASSERT(reg != REG_NON);
1294 if (reg == REG_C_0) {
1295 struct mlx5_priv *priv = dev->data->dev_private;
1296 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1297 uint32_t shl_c0 = rte_bsf32(msk_c0);
1299 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1300 mask = rte_cpu_to_be_32(mask) & msk_c0;
1301 mask = rte_cpu_to_be_32(mask << shl_c0);
1303 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1304 /* The routine expects parameters in memory as big-endian ones. */
1305 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1306 MLX5_MODIFICATION_TYPE_SET, error);
1310 * Convert modify-header set IPv4 DSCP action to DV specification.
1312 * @param[in,out] resource
1313 * Pointer to the modify-header resource.
1315 * Pointer to action specification.
1317 * Pointer to the error structure.
1320 * 0 on success, a negative errno value otherwise and rte_errno is set.
1323 flow_dv_convert_action_modify_ipv4_dscp
1324 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1325 const struct rte_flow_action *action,
1326 struct rte_flow_error *error)
1328 const struct rte_flow_action_set_dscp *conf =
1329 (const struct rte_flow_action_set_dscp *)(action->conf);
1330 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1331 struct rte_flow_item_ipv4 ipv4;
1332 struct rte_flow_item_ipv4 ipv4_mask;
1334 memset(&ipv4, 0, sizeof(ipv4));
1335 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1336 ipv4.hdr.type_of_service = conf->dscp;
1337 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1339 item.mask = &ipv4_mask;
1340 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1341 MLX5_MODIFICATION_TYPE_SET, error);
1345 * Convert modify-header set IPv6 DSCP action to DV specification.
1347 * @param[in,out] resource
1348 * Pointer to the modify-header resource.
1350 * Pointer to action specification.
1352 * Pointer to the error structure.
1355 * 0 on success, a negative errno value otherwise and rte_errno is set.
1358 flow_dv_convert_action_modify_ipv6_dscp
1359 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1360 const struct rte_flow_action *action,
1361 struct rte_flow_error *error)
1363 const struct rte_flow_action_set_dscp *conf =
1364 (const struct rte_flow_action_set_dscp *)(action->conf);
1365 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1366 struct rte_flow_item_ipv6 ipv6;
1367 struct rte_flow_item_ipv6 ipv6_mask;
1369 memset(&ipv6, 0, sizeof(ipv6));
1370 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1372 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1373 * rdma-core only accept the DSCP bits byte aligned start from
1374 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1375 * bits in IPv6 case as rdma-core requires byte aligned value.
1377 ipv6.hdr.vtc_flow = conf->dscp;
1378 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1380 item.mask = &ipv6_mask;
1381 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1382 MLX5_MODIFICATION_TYPE_SET, error);
1386 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1387 enum rte_flow_field_id field, int inherit,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error)
1391 struct mlx5_priv *priv = dev->data->dev_private;
1394 case RTE_FLOW_FIELD_START:
1396 case RTE_FLOW_FIELD_MAC_DST:
1397 case RTE_FLOW_FIELD_MAC_SRC:
1399 case RTE_FLOW_FIELD_VLAN_TYPE:
1401 case RTE_FLOW_FIELD_VLAN_ID:
1403 case RTE_FLOW_FIELD_MAC_TYPE:
1405 case RTE_FLOW_FIELD_IPV4_DSCP:
1407 case RTE_FLOW_FIELD_IPV4_TTL:
1409 case RTE_FLOW_FIELD_IPV4_SRC:
1410 case RTE_FLOW_FIELD_IPV4_DST:
1412 case RTE_FLOW_FIELD_IPV6_DSCP:
1414 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1416 case RTE_FLOW_FIELD_IPV6_SRC:
1417 case RTE_FLOW_FIELD_IPV6_DST:
1419 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1420 case RTE_FLOW_FIELD_TCP_PORT_DST:
1422 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1423 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1425 case RTE_FLOW_FIELD_TCP_FLAGS:
1427 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1428 case RTE_FLOW_FIELD_UDP_PORT_DST:
1430 case RTE_FLOW_FIELD_VXLAN_VNI:
1431 case RTE_FLOW_FIELD_GENEVE_VNI:
1433 case RTE_FLOW_FIELD_GTP_TEID:
1434 case RTE_FLOW_FIELD_TAG:
1436 case RTE_FLOW_FIELD_MARK:
1437 return __builtin_popcount(priv->sh->dv_mark_mask);
1438 case RTE_FLOW_FIELD_META:
1439 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1440 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1441 case RTE_FLOW_FIELD_POINTER:
1442 case RTE_FLOW_FIELD_VALUE:
1443 return inherit < 0 ? 0 : inherit;
1451 mlx5_flow_field_id_to_modify_info
1452 (const struct rte_flow_action_modify_data *data,
1453 struct field_modify_info *info, uint32_t *mask,
1454 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1455 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1457 struct mlx5_priv *priv = dev->data->dev_private;
1461 switch (data->field) {
1462 case RTE_FLOW_FIELD_START:
1463 /* not supported yet */
1466 case RTE_FLOW_FIELD_MAC_DST:
1467 off = data->offset > 16 ? data->offset - 16 : 0;
1469 if (data->offset < 16) {
1470 info[idx] = (struct field_modify_info){2, 4,
1471 MLX5_MODI_OUT_DMAC_15_0};
1473 mask[1] = rte_cpu_to_be_16(0xffff >>
1477 mask[1] = RTE_BE16(0xffff);
1484 info[idx] = (struct field_modify_info){4, 0,
1485 MLX5_MODI_OUT_DMAC_47_16};
1486 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1487 (32 - width)) << off);
1489 if (data->offset < 16)
1490 info[idx++] = (struct field_modify_info){2, 4,
1491 MLX5_MODI_OUT_DMAC_15_0};
1492 info[idx] = (struct field_modify_info){4, 0,
1493 MLX5_MODI_OUT_DMAC_47_16};
1496 case RTE_FLOW_FIELD_MAC_SRC:
1497 off = data->offset > 16 ? data->offset - 16 : 0;
1499 if (data->offset < 16) {
1500 info[idx] = (struct field_modify_info){2, 4,
1501 MLX5_MODI_OUT_SMAC_15_0};
1503 mask[1] = rte_cpu_to_be_16(0xffff >>
1507 mask[1] = RTE_BE16(0xffff);
1514 info[idx] = (struct field_modify_info){4, 0,
1515 MLX5_MODI_OUT_SMAC_47_16};
1516 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1517 (32 - width)) << off);
1519 if (data->offset < 16)
1520 info[idx++] = (struct field_modify_info){2, 4,
1521 MLX5_MODI_OUT_SMAC_15_0};
1522 info[idx] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SMAC_47_16};
1526 case RTE_FLOW_FIELD_VLAN_TYPE:
1527 /* not supported yet */
1529 case RTE_FLOW_FIELD_VLAN_ID:
1530 info[idx] = (struct field_modify_info){2, 0,
1531 MLX5_MODI_OUT_FIRST_VID};
1533 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1535 case RTE_FLOW_FIELD_MAC_TYPE:
1536 info[idx] = (struct field_modify_info){2, 0,
1537 MLX5_MODI_OUT_ETHERTYPE};
1539 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1541 case RTE_FLOW_FIELD_IPV4_DSCP:
1542 info[idx] = (struct field_modify_info){1, 0,
1543 MLX5_MODI_OUT_IP_DSCP};
1545 mask[idx] = 0x3f >> (6 - width);
1547 case RTE_FLOW_FIELD_IPV4_TTL:
1548 info[idx] = (struct field_modify_info){1, 0,
1549 MLX5_MODI_OUT_IPV4_TTL};
1551 mask[idx] = 0xff >> (8 - width);
1553 case RTE_FLOW_FIELD_IPV4_SRC:
1554 info[idx] = (struct field_modify_info){4, 0,
1555 MLX5_MODI_OUT_SIPV4};
1557 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1560 case RTE_FLOW_FIELD_IPV4_DST:
1561 info[idx] = (struct field_modify_info){4, 0,
1562 MLX5_MODI_OUT_DIPV4};
1564 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1567 case RTE_FLOW_FIELD_IPV6_DSCP:
1568 info[idx] = (struct field_modify_info){1, 0,
1569 MLX5_MODI_OUT_IP_DSCP};
1571 mask[idx] = 0x3f >> (6 - width);
1573 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1574 info[idx] = (struct field_modify_info){1, 0,
1575 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1577 mask[idx] = 0xff >> (8 - width);
1579 case RTE_FLOW_FIELD_IPV6_SRC:
1581 if (data->offset < 32) {
1582 info[idx] = (struct field_modify_info){4, 12,
1583 MLX5_MODI_OUT_SIPV6_31_0};
1586 rte_cpu_to_be_32(0xffffffff >>
1590 mask[3] = RTE_BE32(0xffffffff);
1597 if (data->offset < 64) {
1598 info[idx] = (struct field_modify_info){4, 8,
1599 MLX5_MODI_OUT_SIPV6_63_32};
1602 rte_cpu_to_be_32(0xffffffff >>
1606 mask[2] = RTE_BE32(0xffffffff);
1613 if (data->offset < 96) {
1614 info[idx] = (struct field_modify_info){4, 4,
1615 MLX5_MODI_OUT_SIPV6_95_64};
1618 rte_cpu_to_be_32(0xffffffff >>
1622 mask[1] = RTE_BE32(0xffffffff);
1629 info[idx] = (struct field_modify_info){4, 0,
1630 MLX5_MODI_OUT_SIPV6_127_96};
1631 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1633 if (data->offset < 32)
1634 info[idx++] = (struct field_modify_info){4, 12,
1635 MLX5_MODI_OUT_SIPV6_31_0};
1636 if (data->offset < 64)
1637 info[idx++] = (struct field_modify_info){4, 8,
1638 MLX5_MODI_OUT_SIPV6_63_32};
1639 if (data->offset < 96)
1640 info[idx++] = (struct field_modify_info){4, 4,
1641 MLX5_MODI_OUT_SIPV6_95_64};
1642 if (data->offset < 128)
1643 info[idx++] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1647 case RTE_FLOW_FIELD_IPV6_DST:
1649 if (data->offset < 32) {
1650 info[idx] = (struct field_modify_info){4, 12,
1651 MLX5_MODI_OUT_DIPV6_31_0};
1654 rte_cpu_to_be_32(0xffffffff >>
1658 mask[3] = RTE_BE32(0xffffffff);
1665 if (data->offset < 64) {
1666 info[idx] = (struct field_modify_info){4, 8,
1667 MLX5_MODI_OUT_DIPV6_63_32};
1670 rte_cpu_to_be_32(0xffffffff >>
1674 mask[2] = RTE_BE32(0xffffffff);
1681 if (data->offset < 96) {
1682 info[idx] = (struct field_modify_info){4, 4,
1683 MLX5_MODI_OUT_DIPV6_95_64};
1686 rte_cpu_to_be_32(0xffffffff >>
1690 mask[1] = RTE_BE32(0xffffffff);
1697 info[idx] = (struct field_modify_info){4, 0,
1698 MLX5_MODI_OUT_DIPV6_127_96};
1699 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1701 if (data->offset < 32)
1702 info[idx++] = (struct field_modify_info){4, 12,
1703 MLX5_MODI_OUT_DIPV6_31_0};
1704 if (data->offset < 64)
1705 info[idx++] = (struct field_modify_info){4, 8,
1706 MLX5_MODI_OUT_DIPV6_63_32};
1707 if (data->offset < 96)
1708 info[idx++] = (struct field_modify_info){4, 4,
1709 MLX5_MODI_OUT_DIPV6_95_64};
1710 if (data->offset < 128)
1711 info[idx++] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1715 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1716 info[idx] = (struct field_modify_info){2, 0,
1717 MLX5_MODI_OUT_TCP_SPORT};
1719 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1721 case RTE_FLOW_FIELD_TCP_PORT_DST:
1722 info[idx] = (struct field_modify_info){2, 0,
1723 MLX5_MODI_OUT_TCP_DPORT};
1725 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1727 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1728 info[idx] = (struct field_modify_info){4, 0,
1729 MLX5_MODI_OUT_TCP_SEQ_NUM};
1731 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1734 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1735 info[idx] = (struct field_modify_info){4, 0,
1736 MLX5_MODI_OUT_TCP_ACK_NUM};
1738 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1741 case RTE_FLOW_FIELD_TCP_FLAGS:
1742 info[idx] = (struct field_modify_info){2, 0,
1743 MLX5_MODI_OUT_TCP_FLAGS};
1745 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1747 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1748 info[idx] = (struct field_modify_info){2, 0,
1749 MLX5_MODI_OUT_UDP_SPORT};
1751 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1753 case RTE_FLOW_FIELD_UDP_PORT_DST:
1754 info[idx] = (struct field_modify_info){2, 0,
1755 MLX5_MODI_OUT_UDP_DPORT};
1757 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1759 case RTE_FLOW_FIELD_VXLAN_VNI:
1760 /* not supported yet */
1762 case RTE_FLOW_FIELD_GENEVE_VNI:
1763 /* not supported yet*/
1765 case RTE_FLOW_FIELD_GTP_TEID:
1766 info[idx] = (struct field_modify_info){4, 0,
1767 MLX5_MODI_GTP_TEID};
1769 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1772 case RTE_FLOW_FIELD_TAG:
1774 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1775 data->level, error);
1778 MLX5_ASSERT(reg != REG_NON);
1779 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1780 info[idx] = (struct field_modify_info){4, 0,
1784 rte_cpu_to_be_32(0xffffffff >>
1788 case RTE_FLOW_FIELD_MARK:
1790 uint32_t mark_mask = priv->sh->dv_mark_mask;
1791 uint32_t mark_count = __builtin_popcount(mark_mask);
1792 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1796 MLX5_ASSERT(reg != REG_NON);
1797 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1798 info[idx] = (struct field_modify_info){4, 0,
1801 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1802 (mark_count - width)) & mark_mask);
1805 case RTE_FLOW_FIELD_META:
1807 uint32_t meta_mask = priv->sh->dv_meta_mask;
1808 uint32_t meta_count = __builtin_popcount(meta_mask);
1810 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1811 uint32_t shl_c0 = rte_bsf32(msk_c0);
1812 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1815 MLX5_ASSERT(reg != REG_NON);
1816 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1819 info[idx] = (struct field_modify_info){4, 0,
1822 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1823 (meta_count - width)) & meta_mask);
1826 case RTE_FLOW_FIELD_POINTER:
1827 case RTE_FLOW_FIELD_VALUE:
1835 * Convert modify_field action to DV specification.
1838 * Pointer to the rte_eth_dev structure.
1839 * @param[in,out] resource
1840 * Pointer to the modify-header resource.
1842 * Pointer to action specification.
1844 * Attributes of flow that includes this item.
1846 * Pointer to the error structure.
1849 * 0 on success, a negative errno value otherwise and rte_errno is set.
1852 flow_dv_convert_action_modify_field
1853 (struct rte_eth_dev *dev,
1854 struct mlx5_flow_dv_modify_hdr_resource *resource,
1855 const struct rte_flow_action *action,
1856 const struct rte_flow_attr *attr,
1857 struct rte_flow_error *error)
1859 const struct rte_flow_action_modify_field *conf =
1860 (const struct rte_flow_action_modify_field *)(action->conf);
1861 struct rte_flow_item item = {
1865 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1867 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1869 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1873 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1874 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1875 type = MLX5_MODIFICATION_TYPE_SET;
1876 /** For SET fill the destination field (field) first. */
1877 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1878 conf->width, &shift, dev,
1880 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1881 (void *)(uintptr_t)conf->src.pvalue :
1882 (void *)(uintptr_t)&conf->src.value;
1884 type = MLX5_MODIFICATION_TYPE_COPY;
1885 /** For COPY fill the destination field (dcopy) without mask. */
1886 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1887 conf->width, &shift, dev,
1889 /** Then construct the source field (field) with mask. */
1890 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1891 conf->width, &shift,
1895 return flow_dv_convert_modify_action(&item,
1896 field, dcopy, resource, type, error);
1900 * Validate MARK item.
1903 * Pointer to the rte_eth_dev structure.
1905 * Item specification.
1907 * Attributes of flow that includes this item.
1909 * Pointer to error structure.
1912 * 0 on success, a negative errno value otherwise and rte_errno is set.
1915 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1916 const struct rte_flow_item *item,
1917 const struct rte_flow_attr *attr __rte_unused,
1918 struct rte_flow_error *error)
1920 struct mlx5_priv *priv = dev->data->dev_private;
1921 struct mlx5_dev_config *config = &priv->config;
1922 const struct rte_flow_item_mark *spec = item->spec;
1923 const struct rte_flow_item_mark *mask = item->mask;
1924 const struct rte_flow_item_mark nic_mask = {
1925 .id = priv->sh->dv_mark_mask,
1929 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1930 return rte_flow_error_set(error, ENOTSUP,
1931 RTE_FLOW_ERROR_TYPE_ITEM, item,
1932 "extended metadata feature"
1934 if (!mlx5_flow_ext_mreg_supported(dev))
1935 return rte_flow_error_set(error, ENOTSUP,
1936 RTE_FLOW_ERROR_TYPE_ITEM, item,
1937 "extended metadata register"
1938 " isn't supported");
1940 return rte_flow_error_set(error, ENOTSUP,
1941 RTE_FLOW_ERROR_TYPE_ITEM, item,
1942 "extended metadata register"
1943 " isn't available");
1944 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1948 return rte_flow_error_set(error, EINVAL,
1949 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1951 "data cannot be empty");
1952 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1953 return rte_flow_error_set(error, EINVAL,
1954 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1956 "mark id exceeds the limit");
1960 return rte_flow_error_set(error, EINVAL,
1961 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1962 "mask cannot be zero");
1964 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1965 (const uint8_t *)&nic_mask,
1966 sizeof(struct rte_flow_item_mark),
1967 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1974 * Validate META item.
1977 * Pointer to the rte_eth_dev structure.
1979 * Item specification.
1981 * Attributes of flow that includes this item.
1983 * Pointer to error structure.
1986 * 0 on success, a negative errno value otherwise and rte_errno is set.
1989 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1990 const struct rte_flow_item *item,
1991 const struct rte_flow_attr *attr,
1992 struct rte_flow_error *error)
1994 struct mlx5_priv *priv = dev->data->dev_private;
1995 struct mlx5_dev_config *config = &priv->config;
1996 const struct rte_flow_item_meta *spec = item->spec;
1997 const struct rte_flow_item_meta *mask = item->mask;
1998 struct rte_flow_item_meta nic_mask = {
2005 return rte_flow_error_set(error, EINVAL,
2006 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2008 "data cannot be empty");
2009 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2010 if (!mlx5_flow_ext_mreg_supported(dev))
2011 return rte_flow_error_set(error, ENOTSUP,
2012 RTE_FLOW_ERROR_TYPE_ITEM, item,
2013 "extended metadata register"
2014 " isn't supported");
2015 reg = flow_dv_get_metadata_reg(dev, attr, error);
2019 return rte_flow_error_set(error, ENOTSUP,
2020 RTE_FLOW_ERROR_TYPE_ITEM, item,
2021 "unavalable extended metadata register");
2023 return rte_flow_error_set(error, ENOTSUP,
2024 RTE_FLOW_ERROR_TYPE_ITEM, item,
2028 nic_mask.data = priv->sh->dv_meta_mask;
2031 return rte_flow_error_set(error, ENOTSUP,
2032 RTE_FLOW_ERROR_TYPE_ITEM, item,
2033 "extended metadata feature "
2034 "should be enabled when "
2035 "meta item is requested "
2036 "with e-switch mode ");
2038 return rte_flow_error_set(error, ENOTSUP,
2039 RTE_FLOW_ERROR_TYPE_ITEM, item,
2040 "match on metadata for ingress "
2041 "is not supported in legacy "
2045 mask = &rte_flow_item_meta_mask;
2047 return rte_flow_error_set(error, EINVAL,
2048 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2049 "mask cannot be zero");
2051 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2052 (const uint8_t *)&nic_mask,
2053 sizeof(struct rte_flow_item_meta),
2054 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2059 * Validate TAG item.
2062 * Pointer to the rte_eth_dev structure.
2064 * Item specification.
2066 * Attributes of flow that includes this item.
2068 * Pointer to error structure.
2071 * 0 on success, a negative errno value otherwise and rte_errno is set.
2074 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2075 const struct rte_flow_item *item,
2076 const struct rte_flow_attr *attr __rte_unused,
2077 struct rte_flow_error *error)
2079 const struct rte_flow_item_tag *spec = item->spec;
2080 const struct rte_flow_item_tag *mask = item->mask;
2081 const struct rte_flow_item_tag nic_mask = {
2082 .data = RTE_BE32(UINT32_MAX),
2087 if (!mlx5_flow_ext_mreg_supported(dev))
2088 return rte_flow_error_set(error, ENOTSUP,
2089 RTE_FLOW_ERROR_TYPE_ITEM, item,
2090 "extensive metadata register"
2091 " isn't supported");
2093 return rte_flow_error_set(error, EINVAL,
2094 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2096 "data cannot be empty");
2098 mask = &rte_flow_item_tag_mask;
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2102 "mask cannot be zero");
2104 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2105 (const uint8_t *)&nic_mask,
2106 sizeof(struct rte_flow_item_tag),
2107 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2110 if (mask->index != 0xff)
2111 return rte_flow_error_set(error, EINVAL,
2112 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2113 "partial mask for tag index"
2114 " is not supported");
2115 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2118 MLX5_ASSERT(ret != REG_NON);
2123 * Validate vport item.
2126 * Pointer to the rte_eth_dev structure.
2128 * Item specification.
2130 * Attributes of flow that includes this item.
2131 * @param[in] item_flags
2132 * Bit-fields that holds the items detected until now.
2134 * Pointer to error structure.
2137 * 0 on success, a negative errno value otherwise and rte_errno is set.
2140 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2141 const struct rte_flow_item *item,
2142 const struct rte_flow_attr *attr,
2143 uint64_t item_flags,
2144 struct rte_flow_error *error)
2146 const struct rte_flow_item_port_id *spec = item->spec;
2147 const struct rte_flow_item_port_id *mask = item->mask;
2148 const struct rte_flow_item_port_id switch_mask = {
2151 struct mlx5_priv *esw_priv;
2152 struct mlx5_priv *dev_priv;
2155 if (!attr->transfer)
2156 return rte_flow_error_set(error, EINVAL,
2157 RTE_FLOW_ERROR_TYPE_ITEM,
2159 "match on port id is valid only"
2160 " when transfer flag is enabled");
2161 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2162 return rte_flow_error_set(error, ENOTSUP,
2163 RTE_FLOW_ERROR_TYPE_ITEM, item,
2164 "multiple source ports are not"
2167 mask = &switch_mask;
2168 if (mask->id != 0xffffffff)
2169 return rte_flow_error_set(error, ENOTSUP,
2170 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2172 "no support for partial mask on"
2174 ret = mlx5_flow_item_acceptable
2175 (item, (const uint8_t *)mask,
2176 (const uint8_t *)&rte_flow_item_port_id_mask,
2177 sizeof(struct rte_flow_item_port_id),
2178 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2183 if (spec->id == MLX5_PORT_ESW_MGR)
2185 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2187 return rte_flow_error_set(error, rte_errno,
2188 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2189 "failed to obtain E-Switch info for"
2191 dev_priv = mlx5_dev_to_eswitch_info(dev);
2193 return rte_flow_error_set(error, rte_errno,
2194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2196 "failed to obtain E-Switch info");
2197 if (esw_priv->domain_id != dev_priv->domain_id)
2198 return rte_flow_error_set(error, EINVAL,
2199 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2200 "cannot match on a port from a"
2201 " different E-Switch");
2206 * Validate VLAN item.
2209 * Item specification.
2210 * @param[in] item_flags
2211 * Bit-fields that holds the items detected until now.
2213 * Ethernet device flow is being created on.
2215 * Pointer to error structure.
2218 * 0 on success, a negative errno value otherwise and rte_errno is set.
2221 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2222 uint64_t item_flags,
2223 struct rte_eth_dev *dev,
2224 struct rte_flow_error *error)
2226 const struct rte_flow_item_vlan *mask = item->mask;
2227 const struct rte_flow_item_vlan nic_mask = {
2228 .tci = RTE_BE16(UINT16_MAX),
2229 .inner_type = RTE_BE16(UINT16_MAX),
2232 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2234 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2235 MLX5_FLOW_LAYER_INNER_L4) :
2236 (MLX5_FLOW_LAYER_OUTER_L3 |
2237 MLX5_FLOW_LAYER_OUTER_L4);
2238 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2239 MLX5_FLOW_LAYER_OUTER_VLAN;
2241 if (item_flags & vlanm)
2242 return rte_flow_error_set(error, EINVAL,
2243 RTE_FLOW_ERROR_TYPE_ITEM, item,
2244 "multiple VLAN layers not supported");
2245 else if ((item_flags & l34m) != 0)
2246 return rte_flow_error_set(error, EINVAL,
2247 RTE_FLOW_ERROR_TYPE_ITEM, item,
2248 "VLAN cannot follow L3/L4 layer");
2250 mask = &rte_flow_item_vlan_mask;
2251 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2252 (const uint8_t *)&nic_mask,
2253 sizeof(struct rte_flow_item_vlan),
2254 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2257 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2258 struct mlx5_priv *priv = dev->data->dev_private;
2260 if (priv->vmwa_context) {
2262 * Non-NULL context means we have a virtual machine
2263 * and SR-IOV enabled, we have to create VLAN interface
2264 * to make hypervisor to setup E-Switch vport
2265 * context correctly. We avoid creating the multiple
2266 * VLAN interfaces, so we cannot support VLAN tag mask.
2268 return rte_flow_error_set(error, EINVAL,
2269 RTE_FLOW_ERROR_TYPE_ITEM,
2271 "VLAN tag mask is not"
2272 " supported in virtual"
2280 * GTP flags are contained in 1 byte of the format:
2281 * -------------------------------------------
2282 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2283 * |-----------------------------------------|
2284 * | value | Version | PT | Res | E | S | PN |
2285 * -------------------------------------------
2287 * Matching is supported only for GTP flags E, S, PN.
2289 #define MLX5_GTP_FLAGS_MASK 0x07
2292 * Validate GTP item.
2295 * Pointer to the rte_eth_dev structure.
2297 * Item specification.
2298 * @param[in] item_flags
2299 * Bit-fields that holds the items detected until now.
2301 * Pointer to error structure.
2304 * 0 on success, a negative errno value otherwise and rte_errno is set.
2307 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2308 const struct rte_flow_item *item,
2309 uint64_t item_flags,
2310 struct rte_flow_error *error)
2312 struct mlx5_priv *priv = dev->data->dev_private;
2313 const struct rte_flow_item_gtp *spec = item->spec;
2314 const struct rte_flow_item_gtp *mask = item->mask;
2315 const struct rte_flow_item_gtp nic_mask = {
2316 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2318 .teid = RTE_BE32(0xffffffff),
2321 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2322 return rte_flow_error_set(error, ENOTSUP,
2323 RTE_FLOW_ERROR_TYPE_ITEM, item,
2324 "GTP support is not enabled");
2325 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2326 return rte_flow_error_set(error, ENOTSUP,
2327 RTE_FLOW_ERROR_TYPE_ITEM, item,
2328 "multiple tunnel layers not"
2330 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2331 return rte_flow_error_set(error, EINVAL,
2332 RTE_FLOW_ERROR_TYPE_ITEM, item,
2333 "no outer UDP layer found");
2335 mask = &rte_flow_item_gtp_mask;
2336 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2337 return rte_flow_error_set(error, ENOTSUP,
2338 RTE_FLOW_ERROR_TYPE_ITEM, item,
2339 "Match is supported for GTP"
2341 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2342 (const uint8_t *)&nic_mask,
2343 sizeof(struct rte_flow_item_gtp),
2344 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2348 * Validate GTP PSC item.
2351 * Item specification.
2352 * @param[in] last_item
2353 * Previous validated item in the pattern items.
2354 * @param[in] gtp_item
2355 * Previous GTP item specification.
2357 * Pointer to flow attributes.
2359 * Pointer to error structure.
2362 * 0 on success, a negative errno value otherwise and rte_errno is set.
2365 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2367 const struct rte_flow_item *gtp_item,
2368 const struct rte_flow_attr *attr,
2369 struct rte_flow_error *error)
2371 const struct rte_flow_item_gtp *gtp_spec;
2372 const struct rte_flow_item_gtp *gtp_mask;
2373 const struct rte_flow_item_gtp_psc *mask;
2374 const struct rte_flow_item_gtp_psc nic_mask = {
2379 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2380 return rte_flow_error_set
2381 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2382 "GTP PSC item must be preceded with GTP item");
2383 gtp_spec = gtp_item->spec;
2384 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2385 /* GTP spec and E flag is requested to match zero. */
2387 (gtp_mask->v_pt_rsv_flags &
2388 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2389 return rte_flow_error_set
2390 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2391 "GTP E flag must be 1 to match GTP PSC");
2392 /* Check the flow is not created in group zero. */
2393 if (!attr->transfer && !attr->group)
2394 return rte_flow_error_set
2395 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396 "GTP PSC is not supported for group 0");
2397 /* GTP spec is here and E flag is requested to match zero. */
2400 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2401 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2402 (const uint8_t *)&nic_mask,
2403 sizeof(struct rte_flow_item_gtp_psc),
2404 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2408 * Validate IPV4 item.
2409 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2410 * add specific validation of fragment_offset field,
2413 * Item specification.
2414 * @param[in] item_flags
2415 * Bit-fields that holds the items detected until now.
2417 * Pointer to error structure.
2420 * 0 on success, a negative errno value otherwise and rte_errno is set.
2423 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2424 const struct rte_flow_item *item,
2425 uint64_t item_flags, uint64_t last_item,
2426 uint16_t ether_type, struct rte_flow_error *error)
2429 struct mlx5_priv *priv = dev->data->dev_private;
2430 const struct rte_flow_item_ipv4 *spec = item->spec;
2431 const struct rte_flow_item_ipv4 *last = item->last;
2432 const struct rte_flow_item_ipv4 *mask = item->mask;
2433 rte_be16_t fragment_offset_spec = 0;
2434 rte_be16_t fragment_offset_last = 0;
2435 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2437 .src_addr = RTE_BE32(0xffffffff),
2438 .dst_addr = RTE_BE32(0xffffffff),
2439 .type_of_service = 0xff,
2440 .fragment_offset = RTE_BE16(0xffff),
2441 .next_proto_id = 0xff,
2442 .time_to_live = 0xff,
2446 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2447 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2448 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2449 priv->config.hca_attr.inner_ipv4_ihl;
2451 return rte_flow_error_set(error, ENOTSUP,
2452 RTE_FLOW_ERROR_TYPE_ITEM,
2454 "IPV4 ihl offload not supported");
2455 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2457 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2458 ether_type, &nic_ipv4_mask,
2459 MLX5_ITEM_RANGE_ACCEPTED, error);
2463 fragment_offset_spec = spec->hdr.fragment_offset &
2464 mask->hdr.fragment_offset;
2465 if (!fragment_offset_spec)
2468 * spec and mask are valid, enforce using full mask to make sure the
2469 * complete value is used correctly.
2471 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2472 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2473 return rte_flow_error_set(error, EINVAL,
2474 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2475 item, "must use full mask for"
2476 " fragment_offset");
2478 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2479 * indicating this is 1st fragment of fragmented packet.
2480 * This is not yet supported in MLX5, return appropriate error message.
2482 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2483 return rte_flow_error_set(error, ENOTSUP,
2484 RTE_FLOW_ERROR_TYPE_ITEM, item,
2485 "match on first fragment not "
2487 if (fragment_offset_spec && !last)
2488 return rte_flow_error_set(error, ENOTSUP,
2489 RTE_FLOW_ERROR_TYPE_ITEM, item,
2490 "specified value not supported");
2491 /* spec and last are valid, validate the specified range. */
2492 fragment_offset_last = last->hdr.fragment_offset &
2493 mask->hdr.fragment_offset;
2495 * Match on fragment_offset spec 0x2001 and last 0x3fff
2496 * means MF is 1 and frag-offset is > 0.
2497 * This packet is fragment 2nd and onward, excluding last.
2498 * This is not yet supported in MLX5, return appropriate
2501 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2502 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2503 return rte_flow_error_set(error, ENOTSUP,
2504 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2505 last, "match on following "
2506 "fragments not supported");
2508 * Match on fragment_offset spec 0x0001 and last 0x1fff
2509 * means MF is 0 and frag-offset is > 0.
2510 * This packet is last fragment of fragmented packet.
2511 * This is not yet supported in MLX5, return appropriate
2514 if (fragment_offset_spec == RTE_BE16(1) &&
2515 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2516 return rte_flow_error_set(error, ENOTSUP,
2517 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2518 last, "match on last "
2519 "fragment not supported");
2521 * Match on fragment_offset spec 0x0001 and last 0x3fff
2522 * means MF and/or frag-offset is not 0.
2523 * This is a fragmented packet.
2524 * Other range values are invalid and rejected.
2526 if (!(fragment_offset_spec == RTE_BE16(1) &&
2527 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2528 return rte_flow_error_set(error, ENOTSUP,
2529 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2530 "specified range not supported");
2535 * Validate IPV6 fragment extension item.
2538 * Item specification.
2539 * @param[in] item_flags
2540 * Bit-fields that holds the items detected until now.
2542 * Pointer to error structure.
2545 * 0 on success, a negative errno value otherwise and rte_errno is set.
2548 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2549 uint64_t item_flags,
2550 struct rte_flow_error *error)
2552 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2553 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2554 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2555 rte_be16_t frag_data_spec = 0;
2556 rte_be16_t frag_data_last = 0;
2557 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2558 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2559 MLX5_FLOW_LAYER_OUTER_L4;
2561 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2563 .next_header = 0xff,
2564 .frag_data = RTE_BE16(0xffff),
2568 if (item_flags & l4m)
2569 return rte_flow_error_set(error, EINVAL,
2570 RTE_FLOW_ERROR_TYPE_ITEM, item,
2571 "ipv6 fragment extension item cannot "
2573 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2574 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2575 return rte_flow_error_set(error, EINVAL,
2576 RTE_FLOW_ERROR_TYPE_ITEM, item,
2577 "ipv6 fragment extension item must "
2578 "follow ipv6 item");
2580 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2581 if (!frag_data_spec)
2584 * spec and mask are valid, enforce using full mask to make sure the
2585 * complete value is used correctly.
2587 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2588 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2591 item, "must use full mask for"
2594 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2595 * This is 1st fragment of fragmented packet.
2597 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2598 return rte_flow_error_set(error, ENOTSUP,
2599 RTE_FLOW_ERROR_TYPE_ITEM, item,
2600 "match on first fragment not "
2602 if (frag_data_spec && !last)
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM, item,
2605 "specified value not supported");
2606 ret = mlx5_flow_item_acceptable
2607 (item, (const uint8_t *)mask,
2608 (const uint8_t *)&nic_mask,
2609 sizeof(struct rte_flow_item_ipv6_frag_ext),
2610 MLX5_ITEM_RANGE_ACCEPTED, error);
2613 /* spec and last are valid, validate the specified range. */
2614 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2616 * Match on frag_data spec 0x0009 and last 0xfff9
2617 * means M is 1 and frag-offset is > 0.
2618 * This packet is fragment 2nd and onward, excluding last.
2619 * This is not yet supported in MLX5, return appropriate
2622 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2623 RTE_IPV6_EHDR_MF_MASK) &&
2624 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2625 return rte_flow_error_set(error, ENOTSUP,
2626 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2627 last, "match on following "
2628 "fragments not supported");
2630 * Match on frag_data spec 0x0008 and last 0xfff8
2631 * means M is 0 and frag-offset is > 0.
2632 * This packet is last fragment of fragmented packet.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2637 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2638 return rte_flow_error_set(error, ENOTSUP,
2639 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2640 last, "match on last "
2641 "fragment not supported");
2642 /* Other range values are invalid and rejected. */
2643 return rte_flow_error_set(error, EINVAL,
2644 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2645 "specified range not supported");
2649 * Validate ASO CT item.
2652 * Pointer to the rte_eth_dev structure.
2654 * Item specification.
2655 * @param[in] item_flags
2656 * Pointer to bit-fields that holds the items detected until now.
2658 * Pointer to error structure.
2661 * 0 on success, a negative errno value otherwise and rte_errno is set.
2664 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2665 const struct rte_flow_item *item,
2666 uint64_t *item_flags,
2667 struct rte_flow_error *error)
2669 const struct rte_flow_item_conntrack *spec = item->spec;
2670 const struct rte_flow_item_conntrack *mask = item->mask;
2674 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2675 return rte_flow_error_set(error, EINVAL,
2676 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2677 "Only one CT is supported");
2679 mask = &rte_flow_item_conntrack_mask;
2680 flags = spec->flags & mask->flags;
2681 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2682 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2683 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2684 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2685 return rte_flow_error_set(error, EINVAL,
2686 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2687 "Conflict status bits");
2688 /* State change also needs to be considered. */
2689 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2694 * Validate the pop VLAN action.
2697 * Pointer to the rte_eth_dev structure.
2698 * @param[in] action_flags
2699 * Holds the actions detected until now.
2701 * Pointer to the pop vlan action.
2702 * @param[in] item_flags
2703 * The items found in this flow rule.
2705 * Pointer to flow attributes.
2707 * Pointer to error structure.
2710 * 0 on success, a negative errno value otherwise and rte_errno is set.
2713 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2714 uint64_t action_flags,
2715 const struct rte_flow_action *action,
2716 uint64_t item_flags,
2717 const struct rte_flow_attr *attr,
2718 struct rte_flow_error *error)
2720 const struct mlx5_priv *priv = dev->data->dev_private;
2721 struct mlx5_dev_ctx_shared *sh = priv->sh;
2722 bool direction_error = false;
2724 if (!priv->sh->pop_vlan_action)
2725 return rte_flow_error_set(error, ENOTSUP,
2726 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2728 "pop vlan action is not supported");
2729 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2730 if (attr->transfer) {
2731 bool fdb_tx = priv->representor_id != UINT16_MAX;
2732 bool is_cx5 = sh->steering_format_version ==
2733 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2735 if (fdb_tx && is_cx5)
2736 direction_error = true;
2737 } else if (attr->egress) {
2738 direction_error = true;
2740 if (direction_error)
2741 return rte_flow_error_set(error, ENOTSUP,
2742 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2744 "pop vlan action not supported for egress");
2745 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2746 return rte_flow_error_set(error, ENOTSUP,
2747 RTE_FLOW_ERROR_TYPE_ACTION, action,
2748 "no support for multiple VLAN "
2750 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2751 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2752 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2753 return rte_flow_error_set(error, ENOTSUP,
2754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2756 "cannot pop vlan after decap without "
2757 "match on inner vlan in the flow");
2758 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2759 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2760 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2761 return rte_flow_error_set(error, ENOTSUP,
2762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2764 "cannot pop vlan without a "
2765 "match on (outer) vlan in the flow");
2766 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2767 return rte_flow_error_set(error, EINVAL,
2768 RTE_FLOW_ERROR_TYPE_ACTION, action,
2769 "wrong action order, port_id should "
2770 "be after pop VLAN action");
2771 if (!attr->transfer && priv->representor)
2772 return rte_flow_error_set(error, ENOTSUP,
2773 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2774 "pop vlan action for VF representor "
2775 "not supported on NIC table");
2780 * Get VLAN default info from vlan match info.
2783 * the list of item specifications.
2785 * pointer VLAN info to fill to.
2788 * 0 on success, a negative errno value otherwise and rte_errno is set.
2791 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2792 struct rte_vlan_hdr *vlan)
2794 const struct rte_flow_item_vlan nic_mask = {
2795 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2796 MLX5DV_FLOW_VLAN_VID_MASK),
2797 .inner_type = RTE_BE16(0xffff),
2802 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2803 int type = items->type;
2805 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2806 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2809 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2810 const struct rte_flow_item_vlan *vlan_m = items->mask;
2811 const struct rte_flow_item_vlan *vlan_v = items->spec;
2813 /* If VLAN item in pattern doesn't contain data, return here. */
2818 /* Only full match values are accepted */
2819 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2820 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2821 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2823 rte_be_to_cpu_16(vlan_v->tci &
2824 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2826 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2827 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2828 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2830 rte_be_to_cpu_16(vlan_v->tci &
2831 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2833 if (vlan_m->inner_type == nic_mask.inner_type)
2834 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2835 vlan_m->inner_type);
2840 * Validate the push VLAN action.
2843 * Pointer to the rte_eth_dev structure.
2844 * @param[in] action_flags
2845 * Holds the actions detected until now.
2846 * @param[in] item_flags
2847 * The items found in this flow rule.
2849 * Pointer to the action structure.
2851 * Pointer to flow attributes
2853 * Pointer to error structure.
2856 * 0 on success, a negative errno value otherwise and rte_errno is set.
2859 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2860 uint64_t action_flags,
2861 const struct rte_flow_item_vlan *vlan_m,
2862 const struct rte_flow_action *action,
2863 const struct rte_flow_attr *attr,
2864 struct rte_flow_error *error)
2866 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2867 const struct mlx5_priv *priv = dev->data->dev_private;
2868 struct mlx5_dev_ctx_shared *sh = priv->sh;
2869 bool direction_error = false;
2871 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2872 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2873 return rte_flow_error_set(error, EINVAL,
2874 RTE_FLOW_ERROR_TYPE_ACTION, action,
2875 "invalid vlan ethertype");
2876 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2877 return rte_flow_error_set(error, EINVAL,
2878 RTE_FLOW_ERROR_TYPE_ACTION, action,
2879 "wrong action order, port_id should "
2880 "be after push VLAN");
2881 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2882 if (attr->transfer) {
2883 bool fdb_tx = priv->representor_id != UINT16_MAX;
2884 bool is_cx5 = sh->steering_format_version ==
2885 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2887 if (!fdb_tx && is_cx5)
2888 direction_error = true;
2889 } else if (attr->ingress) {
2890 direction_error = true;
2892 if (direction_error)
2893 return rte_flow_error_set(error, ENOTSUP,
2894 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2896 "push vlan action not supported for ingress");
2897 if (!attr->transfer && priv->representor)
2898 return rte_flow_error_set(error, ENOTSUP,
2899 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2900 "push vlan action for VF representor "
2901 "not supported on NIC table");
2903 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2904 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2905 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2906 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2907 !(mlx5_flow_find_action
2908 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2909 return rte_flow_error_set(error, EINVAL,
2910 RTE_FLOW_ERROR_TYPE_ACTION, action,
2911 "not full match mask on VLAN PCP and "
2912 "there is no of_set_vlan_pcp action, "
2913 "push VLAN action cannot figure out "
2916 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2918 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2919 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2920 !(mlx5_flow_find_action
2921 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2922 return rte_flow_error_set(error, EINVAL,
2923 RTE_FLOW_ERROR_TYPE_ACTION, action,
2924 "not full match mask on VLAN VID and "
2925 "there is no of_set_vlan_vid action, "
2926 "push VLAN action cannot figure out "
2933 * Validate the set VLAN PCP.
2935 * @param[in] action_flags
2936 * Holds the actions detected until now.
2937 * @param[in] actions
2938 * Pointer to the list of actions remaining in the flow rule.
2940 * Pointer to error structure.
2943 * 0 on success, a negative errno value otherwise and rte_errno is set.
2946 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2947 const struct rte_flow_action actions[],
2948 struct rte_flow_error *error)
2950 const struct rte_flow_action *action = actions;
2951 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2953 if (conf->vlan_pcp > 7)
2954 return rte_flow_error_set(error, EINVAL,
2955 RTE_FLOW_ERROR_TYPE_ACTION, action,
2956 "VLAN PCP value is too big");
2957 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2958 return rte_flow_error_set(error, ENOTSUP,
2959 RTE_FLOW_ERROR_TYPE_ACTION, action,
2960 "set VLAN PCP action must follow "
2961 "the push VLAN action");
2962 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2963 return rte_flow_error_set(error, ENOTSUP,
2964 RTE_FLOW_ERROR_TYPE_ACTION, action,
2965 "Multiple VLAN PCP modification are "
2967 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "wrong action order, port_id should "
2971 "be after set VLAN PCP");
2976 * Validate the set VLAN VID.
2978 * @param[in] item_flags
2979 * Holds the items detected in this rule.
2980 * @param[in] action_flags
2981 * Holds the actions detected until now.
2982 * @param[in] actions
2983 * Pointer to the list of actions remaining in the flow rule.
2985 * Pointer to error structure.
2988 * 0 on success, a negative errno value otherwise and rte_errno is set.
2991 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2992 uint64_t action_flags,
2993 const struct rte_flow_action actions[],
2994 struct rte_flow_error *error)
2996 const struct rte_flow_action *action = actions;
2997 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2999 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3000 return rte_flow_error_set(error, EINVAL,
3001 RTE_FLOW_ERROR_TYPE_ACTION, action,
3002 "VLAN VID value is too big");
3003 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3004 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3005 return rte_flow_error_set(error, ENOTSUP,
3006 RTE_FLOW_ERROR_TYPE_ACTION, action,
3007 "set VLAN VID action must follow push"
3008 " VLAN action or match on VLAN item");
3009 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3010 return rte_flow_error_set(error, ENOTSUP,
3011 RTE_FLOW_ERROR_TYPE_ACTION, action,
3012 "Multiple VLAN VID modifications are "
3014 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3015 return rte_flow_error_set(error, EINVAL,
3016 RTE_FLOW_ERROR_TYPE_ACTION, action,
3017 "wrong action order, port_id should "
3018 "be after set VLAN VID");
3023 * Validate the FLAG action.
3026 * Pointer to the rte_eth_dev structure.
3027 * @param[in] action_flags
3028 * Holds the actions detected until now.
3030 * Pointer to flow attributes
3032 * Pointer to error structure.
3035 * 0 on success, a negative errno value otherwise and rte_errno is set.
3038 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3039 uint64_t action_flags,
3040 const struct rte_flow_attr *attr,
3041 struct rte_flow_error *error)
3043 struct mlx5_priv *priv = dev->data->dev_private;
3044 struct mlx5_dev_config *config = &priv->config;
3047 /* Fall back if no extended metadata register support. */
3048 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3049 return mlx5_flow_validate_action_flag(action_flags, attr,
3051 /* Extensive metadata mode requires registers. */
3052 if (!mlx5_flow_ext_mreg_supported(dev))
3053 return rte_flow_error_set(error, ENOTSUP,
3054 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3055 "no metadata registers "
3056 "to support flag action");
3057 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3058 return rte_flow_error_set(error, ENOTSUP,
3059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3060 "extended metadata register"
3061 " isn't available");
3062 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3065 MLX5_ASSERT(ret > 0);
3066 if (action_flags & MLX5_FLOW_ACTION_MARK)
3067 return rte_flow_error_set(error, EINVAL,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "can't mark and flag in same flow");
3070 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3071 return rte_flow_error_set(error, EINVAL,
3072 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 " actions in same flow");
3079 * Validate MARK action.
3082 * Pointer to the rte_eth_dev structure.
3084 * Pointer to action.
3085 * @param[in] action_flags
3086 * Holds the actions detected until now.
3088 * Pointer to flow attributes
3090 * Pointer to error structure.
3093 * 0 on success, a negative errno value otherwise and rte_errno is set.
3096 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3097 const struct rte_flow_action *action,
3098 uint64_t action_flags,
3099 const struct rte_flow_attr *attr,
3100 struct rte_flow_error *error)
3102 struct mlx5_priv *priv = dev->data->dev_private;
3103 struct mlx5_dev_config *config = &priv->config;
3104 const struct rte_flow_action_mark *mark = action->conf;
3107 if (is_tunnel_offload_active(dev))
3108 return rte_flow_error_set(error, ENOTSUP,
3109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3111 "if tunnel offload active");
3112 /* Fall back if no extended metadata register support. */
3113 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3114 return mlx5_flow_validate_action_mark(action, action_flags,
3116 /* Extensive metadata mode requires registers. */
3117 if (!mlx5_flow_ext_mreg_supported(dev))
3118 return rte_flow_error_set(error, ENOTSUP,
3119 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3120 "no metadata registers "
3121 "to support mark action");
3122 if (!priv->sh->dv_mark_mask)
3123 return rte_flow_error_set(error, ENOTSUP,
3124 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "extended metadata register"
3126 " isn't available");
3127 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3130 MLX5_ASSERT(ret > 0);
3132 return rte_flow_error_set(error, EINVAL,
3133 RTE_FLOW_ERROR_TYPE_ACTION, action,
3134 "configuration cannot be null");
3135 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3136 return rte_flow_error_set(error, EINVAL,
3137 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3139 "mark id exceeds the limit");
3140 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3141 return rte_flow_error_set(error, EINVAL,
3142 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3143 "can't flag and mark in same flow");
3144 if (action_flags & MLX5_FLOW_ACTION_MARK)
3145 return rte_flow_error_set(error, EINVAL,
3146 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3147 "can't have 2 mark actions in same"
3153 * Validate SET_META action.
3156 * Pointer to the rte_eth_dev structure.
3158 * Pointer to the action structure.
3159 * @param[in] action_flags
3160 * Holds the actions detected until now.
3162 * Pointer to flow attributes
3164 * Pointer to error structure.
3167 * 0 on success, a negative errno value otherwise and rte_errno is set.
3170 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3171 const struct rte_flow_action *action,
3172 uint64_t action_flags __rte_unused,
3173 const struct rte_flow_attr *attr,
3174 struct rte_flow_error *error)
3176 struct mlx5_priv *priv = dev->data->dev_private;
3177 struct mlx5_dev_config *config = &priv->config;
3178 const struct rte_flow_action_set_meta *conf;
3179 uint32_t nic_mask = UINT32_MAX;
3182 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3183 !mlx5_flow_ext_mreg_supported(dev))
3184 return rte_flow_error_set(error, ENOTSUP,
3185 RTE_FLOW_ERROR_TYPE_ACTION, action,
3186 "extended metadata register"
3187 " isn't supported");
3188 reg = flow_dv_get_metadata_reg(dev, attr, error);
3192 return rte_flow_error_set(error, ENOTSUP,
3193 RTE_FLOW_ERROR_TYPE_ACTION, action,
3194 "unavalable extended metadata register");
3195 if (reg != REG_A && reg != REG_B) {
3196 struct mlx5_priv *priv = dev->data->dev_private;
3198 nic_mask = priv->sh->dv_meta_mask;
3200 if (!(action->conf))
3201 return rte_flow_error_set(error, EINVAL,
3202 RTE_FLOW_ERROR_TYPE_ACTION, action,
3203 "configuration cannot be null");
3204 conf = (const struct rte_flow_action_set_meta *)action->conf;
3206 return rte_flow_error_set(error, EINVAL,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "zero mask doesn't have any effect");
3209 if (conf->mask & ~nic_mask)
3210 return rte_flow_error_set(error, EINVAL,
3211 RTE_FLOW_ERROR_TYPE_ACTION, action,
3212 "meta data must be within reg C0");
3217 * Validate SET_TAG action.
3220 * Pointer to the rte_eth_dev structure.
3222 * Pointer to the action structure.
3223 * @param[in] action_flags
3224 * Holds the actions detected until now.
3226 * Pointer to flow attributes
3228 * Pointer to error structure.
3231 * 0 on success, a negative errno value otherwise and rte_errno is set.
3234 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3235 const struct rte_flow_action *action,
3236 uint64_t action_flags,
3237 const struct rte_flow_attr *attr,
3238 struct rte_flow_error *error)
3240 const struct rte_flow_action_set_tag *conf;
3241 const uint64_t terminal_action_flags =
3242 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3243 MLX5_FLOW_ACTION_RSS;
3246 if (!mlx5_flow_ext_mreg_supported(dev))
3247 return rte_flow_error_set(error, ENOTSUP,
3248 RTE_FLOW_ERROR_TYPE_ACTION, action,
3249 "extensive metadata register"
3250 " isn't supported");
3251 if (!(action->conf))
3252 return rte_flow_error_set(error, EINVAL,
3253 RTE_FLOW_ERROR_TYPE_ACTION, action,
3254 "configuration cannot be null");
3255 conf = (const struct rte_flow_action_set_tag *)action->conf;
3257 return rte_flow_error_set(error, EINVAL,
3258 RTE_FLOW_ERROR_TYPE_ACTION, action,
3259 "zero mask doesn't have any effect");
3260 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3263 if (!attr->transfer && attr->ingress &&
3264 (action_flags & terminal_action_flags))
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION, action,
3267 "set_tag has no effect"
3268 " with terminal actions");
3273 * Validate count action.
3276 * Pointer to rte_eth_dev structure.
3278 * Indicator if action is shared.
3279 * @param[in] action_flags
3280 * Holds the actions detected until now.
3282 * Pointer to error structure.
3285 * 0 on success, a negative errno value otherwise and rte_errno is set.
3288 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3289 uint64_t action_flags,
3290 struct rte_flow_error *error)
3292 struct mlx5_priv *priv = dev->data->dev_private;
3294 if (!priv->sh->devx)
3296 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3297 return rte_flow_error_set(error, EINVAL,
3298 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3299 "duplicate count actions set");
3300 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3301 !priv->sh->flow_hit_aso_en)
3302 return rte_flow_error_set(error, EINVAL,
3303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3304 "old age and shared count combination is not supported");
3305 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3309 return rte_flow_error_set
3311 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3313 "count action not supported");
3317 * Validate the L2 encap action.
3320 * Pointer to the rte_eth_dev structure.
3321 * @param[in] action_flags
3322 * Holds the actions detected until now.
3324 * Pointer to the action structure.
3326 * Pointer to flow attributes.
3328 * Pointer to error structure.
3331 * 0 on success, a negative errno value otherwise and rte_errno is set.
3334 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3335 uint64_t action_flags,
3336 const struct rte_flow_action *action,
3337 const struct rte_flow_attr *attr,
3338 struct rte_flow_error *error)
3340 const struct mlx5_priv *priv = dev->data->dev_private;
3342 if (!(action->conf))
3343 return rte_flow_error_set(error, EINVAL,
3344 RTE_FLOW_ERROR_TYPE_ACTION, action,
3345 "configuration cannot be null");
3346 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349 "can only have a single encap action "
3351 if (!attr->transfer && priv->representor)
3352 return rte_flow_error_set(error, ENOTSUP,
3353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3354 "encap action for VF representor "
3355 "not supported on NIC table");
3360 * Validate a decap action.
3363 * Pointer to the rte_eth_dev structure.
3364 * @param[in] action_flags
3365 * Holds the actions detected until now.
3367 * Pointer to the action structure.
3368 * @param[in] item_flags
3369 * Holds the items detected.
3371 * Pointer to flow attributes
3373 * Pointer to error structure.
3376 * 0 on success, a negative errno value otherwise and rte_errno is set.
3379 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3380 uint64_t action_flags,
3381 const struct rte_flow_action *action,
3382 const uint64_t item_flags,
3383 const struct rte_flow_attr *attr,
3384 struct rte_flow_error *error)
3386 const struct mlx5_priv *priv = dev->data->dev_private;
3388 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3389 !priv->config.decap_en)
3390 return rte_flow_error_set(error, ENOTSUP,
3391 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3392 "decap is not enabled");
3393 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3394 return rte_flow_error_set(error, ENOTSUP,
3395 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3397 MLX5_FLOW_ACTION_DECAP ? "can only "
3398 "have a single decap action" : "decap "
3399 "after encap is not supported");
3400 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3401 return rte_flow_error_set(error, EINVAL,
3402 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3403 "can't have decap action after"
3406 return rte_flow_error_set(error, ENOTSUP,
3407 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3409 "decap action not supported for "
3411 if (!attr->transfer && priv->representor)
3412 return rte_flow_error_set(error, ENOTSUP,
3413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3414 "decap action for VF representor "
3415 "not supported on NIC table");
3416 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3417 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3418 return rte_flow_error_set(error, ENOTSUP,
3419 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3420 "VXLAN item should be present for VXLAN decap");
3424 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3427 * Validate the raw encap and decap actions.
3430 * Pointer to the rte_eth_dev structure.
3432 * Pointer to the decap action.
3434 * Pointer to the encap action.
3436 * Pointer to flow attributes
3437 * @param[in/out] action_flags
3438 * Holds the actions detected until now.
3439 * @param[out] actions_n
3440 * pointer to the number of actions counter.
3442 * Pointer to the action structure.
3443 * @param[in] item_flags
3444 * Holds the items detected.
3446 * Pointer to error structure.
3449 * 0 on success, a negative errno value otherwise and rte_errno is set.
3452 flow_dv_validate_action_raw_encap_decap
3453 (struct rte_eth_dev *dev,
3454 const struct rte_flow_action_raw_decap *decap,
3455 const struct rte_flow_action_raw_encap *encap,
3456 const struct rte_flow_attr *attr, uint64_t *action_flags,
3457 int *actions_n, const struct rte_flow_action *action,
3458 uint64_t item_flags, struct rte_flow_error *error)
3460 const struct mlx5_priv *priv = dev->data->dev_private;
3463 if (encap && (!encap->size || !encap->data))
3464 return rte_flow_error_set(error, EINVAL,
3465 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3466 "raw encap data cannot be empty");
3467 if (decap && encap) {
3468 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3469 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3472 else if (encap->size <=
3473 MLX5_ENCAPSULATION_DECISION_SIZE &&
3475 MLX5_ENCAPSULATION_DECISION_SIZE)
3478 else if (encap->size >
3479 MLX5_ENCAPSULATION_DECISION_SIZE &&
3481 MLX5_ENCAPSULATION_DECISION_SIZE)
3482 /* 2 L2 actions: encap and decap. */
3485 return rte_flow_error_set(error,
3487 RTE_FLOW_ERROR_TYPE_ACTION,
3488 NULL, "unsupported too small "
3489 "raw decap and too small raw "
3490 "encap combination");
3493 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3494 item_flags, attr, error);
3497 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3501 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3502 return rte_flow_error_set(error, ENOTSUP,
3503 RTE_FLOW_ERROR_TYPE_ACTION,
3505 "small raw encap size");
3506 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3507 return rte_flow_error_set(error, EINVAL,
3508 RTE_FLOW_ERROR_TYPE_ACTION,
3510 "more than one encap action");
3511 if (!attr->transfer && priv->representor)
3512 return rte_flow_error_set
3514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3515 "encap action for VF representor "
3516 "not supported on NIC table");
3517 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3524 * Validate the ASO CT action.
3527 * Pointer to the rte_eth_dev structure.
3528 * @param[in] action_flags
3529 * Holds the actions detected until now.
3530 * @param[in] item_flags
3531 * The items found in this flow rule.
3533 * Pointer to flow attributes.
3535 * Pointer to error structure.
3538 * 0 on success, a negative errno value otherwise and rte_errno is set.
3541 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3542 uint64_t action_flags,
3543 uint64_t item_flags,
3544 const struct rte_flow_attr *attr,
3545 struct rte_flow_error *error)
3549 if (attr->group == 0 && !attr->transfer)
3550 return rte_flow_error_set(error, ENOTSUP,
3551 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3553 "Only support non-root table");
3554 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3555 return rte_flow_error_set(error, ENOTSUP,
3556 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557 "CT cannot follow a fate action");
3558 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3559 (action_flags & MLX5_FLOW_ACTION_AGE))
3560 return rte_flow_error_set(error, EINVAL,
3561 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3562 "Only one ASO action is supported");
3563 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3564 return rte_flow_error_set(error, EINVAL,
3565 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3566 "Encap cannot exist before CT");
3567 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3568 return rte_flow_error_set(error, EINVAL,
3569 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3570 "Not a outer TCP packet");
3575 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3576 struct mlx5_list_entry *entry, void *cb_ctx)
3578 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3579 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3580 struct mlx5_flow_dv_encap_decap_resource *resource;
3582 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3584 if (resource->reformat_type == ctx_resource->reformat_type &&
3585 resource->ft_type == ctx_resource->ft_type &&
3586 resource->flags == ctx_resource->flags &&
3587 resource->size == ctx_resource->size &&
3588 !memcmp((const void *)resource->buf,
3589 (const void *)ctx_resource->buf,
3595 struct mlx5_list_entry *
3596 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3598 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3599 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3600 struct mlx5dv_dr_domain *domain;
3601 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3602 struct mlx5_flow_dv_encap_decap_resource *resource;
3606 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3607 domain = sh->fdb_domain;
3608 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3609 domain = sh->rx_domain;
3611 domain = sh->tx_domain;
3612 /* Register new encap/decap resource. */
3613 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3615 rte_flow_error_set(ctx->error, ENOMEM,
3616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3617 "cannot allocate resource memory");
3620 *resource = *ctx_resource;
3621 resource->idx = idx;
3622 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3626 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3627 rte_flow_error_set(ctx->error, ENOMEM,
3628 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3629 NULL, "cannot create action");
3633 return &resource->entry;
3636 struct mlx5_list_entry *
3637 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3640 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3641 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3645 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3647 if (!cache_resource) {
3648 rte_flow_error_set(ctx->error, ENOMEM,
3649 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3650 "cannot allocate resource memory");
3653 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3654 cache_resource->idx = idx;
3655 return &cache_resource->entry;
3659 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3661 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3662 struct mlx5_flow_dv_encap_decap_resource *res =
3663 container_of(entry, typeof(*res), entry);
3665 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3669 * Find existing encap/decap resource or create and register a new one.
3671 * @param[in, out] dev
3672 * Pointer to rte_eth_dev structure.
3673 * @param[in, out] resource
3674 * Pointer to encap/decap resource.
3675 * @parm[in, out] dev_flow
3676 * Pointer to the dev_flow.
3678 * pointer to error structure.
3681 * 0 on success otherwise -errno and errno is set.
3684 flow_dv_encap_decap_resource_register
3685 (struct rte_eth_dev *dev,
3686 struct mlx5_flow_dv_encap_decap_resource *resource,
3687 struct mlx5_flow *dev_flow,
3688 struct rte_flow_error *error)
3690 struct mlx5_priv *priv = dev->data->dev_private;
3691 struct mlx5_dev_ctx_shared *sh = priv->sh;
3692 struct mlx5_list_entry *entry;
3696 uint32_t refmt_type:8;
3698 * Header reformat actions can be shared between
3699 * non-root tables. One bit to indicate non-root
3703 uint32_t reserve:15;
3706 } encap_decap_key = {
3708 .ft_type = resource->ft_type,
3709 .refmt_type = resource->reformat_type,
3710 .is_root = !!dev_flow->dv.group,
3714 struct mlx5_flow_cb_ctx ctx = {
3718 struct mlx5_hlist *encaps_decaps;
3721 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3723 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3725 flow_dv_encap_decap_create_cb,
3726 flow_dv_encap_decap_match_cb,
3727 flow_dv_encap_decap_remove_cb,
3728 flow_dv_encap_decap_clone_cb,
3729 flow_dv_encap_decap_clone_free_cb);
3730 if (unlikely(!encaps_decaps))
3732 resource->flags = dev_flow->dv.group ? 0 : 1;
3733 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3734 sizeof(encap_decap_key.v32), 0);
3735 if (resource->reformat_type !=
3736 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3738 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3739 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3742 resource = container_of(entry, typeof(*resource), entry);
3743 dev_flow->dv.encap_decap = resource;
3744 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3749 * Find existing table jump resource or create and register a new one.
3751 * @param[in, out] dev
3752 * Pointer to rte_eth_dev structure.
3753 * @param[in, out] tbl
3754 * Pointer to flow table resource.
3755 * @parm[in, out] dev_flow
3756 * Pointer to the dev_flow.
3758 * pointer to error structure.
3761 * 0 on success otherwise -errno and errno is set.
3764 flow_dv_jump_tbl_resource_register
3765 (struct rte_eth_dev *dev __rte_unused,
3766 struct mlx5_flow_tbl_resource *tbl,
3767 struct mlx5_flow *dev_flow,
3768 struct rte_flow_error *error __rte_unused)
3770 struct mlx5_flow_tbl_data_entry *tbl_data =
3771 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3774 MLX5_ASSERT(tbl_data->jump.action);
3775 dev_flow->handle->rix_jump = tbl_data->idx;
3776 dev_flow->dv.jump = &tbl_data->jump;
3781 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3782 struct mlx5_list_entry *entry, void *cb_ctx)
3784 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3785 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3786 struct mlx5_flow_dv_port_id_action_resource *res =
3787 container_of(entry, typeof(*res), entry);
3789 return ref->port_id != res->port_id;
3792 struct mlx5_list_entry *
3793 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3795 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3796 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3797 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3798 struct mlx5_flow_dv_port_id_action_resource *resource;
3802 /* Register new port id action resource. */
3803 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3805 rte_flow_error_set(ctx->error, ENOMEM,
3806 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3807 "cannot allocate port_id action memory");
3811 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3815 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3816 rte_flow_error_set(ctx->error, ENOMEM,
3817 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3818 "cannot create action");
3821 resource->idx = idx;
3822 return &resource->entry;
3825 struct mlx5_list_entry *
3826 flow_dv_port_id_clone_cb(void *tool_ctx,
3827 struct mlx5_list_entry *entry __rte_unused,
3830 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3831 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3832 struct mlx5_flow_dv_port_id_action_resource *resource;
3835 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3837 rte_flow_error_set(ctx->error, ENOMEM,
3838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3839 "cannot allocate port_id action memory");
3842 memcpy(resource, entry, sizeof(*resource));
3843 resource->idx = idx;
3844 return &resource->entry;
3848 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3850 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3851 struct mlx5_flow_dv_port_id_action_resource *resource =
3852 container_of(entry, typeof(*resource), entry);
3854 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3858 * Find existing table port ID resource or create and register a new one.
3860 * @param[in, out] dev
3861 * Pointer to rte_eth_dev structure.
3862 * @param[in, out] ref
3863 * Pointer to port ID action resource reference.
3864 * @parm[in, out] dev_flow
3865 * Pointer to the dev_flow.
3867 * pointer to error structure.
3870 * 0 on success otherwise -errno and errno is set.
3873 flow_dv_port_id_action_resource_register
3874 (struct rte_eth_dev *dev,
3875 struct mlx5_flow_dv_port_id_action_resource *ref,
3876 struct mlx5_flow *dev_flow,
3877 struct rte_flow_error *error)
3879 struct mlx5_priv *priv = dev->data->dev_private;
3880 struct mlx5_list_entry *entry;
3881 struct mlx5_flow_dv_port_id_action_resource *resource;
3882 struct mlx5_flow_cb_ctx ctx = {
3887 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3890 resource = container_of(entry, typeof(*resource), entry);
3891 dev_flow->dv.port_id_action = resource;
3892 dev_flow->handle->rix_port_id_action = resource->idx;
3897 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3898 struct mlx5_list_entry *entry, void *cb_ctx)
3900 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3901 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3902 struct mlx5_flow_dv_push_vlan_action_resource *res =
3903 container_of(entry, typeof(*res), entry);
3905 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3908 struct mlx5_list_entry *
3909 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3911 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3912 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3913 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3914 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3915 struct mlx5dv_dr_domain *domain;
3919 /* Register new port id action resource. */
3920 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3922 rte_flow_error_set(ctx->error, ENOMEM,
3923 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3924 "cannot allocate push_vlan action memory");
3928 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3929 domain = sh->fdb_domain;
3930 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3931 domain = sh->rx_domain;
3933 domain = sh->tx_domain;
3934 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3937 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3938 rte_flow_error_set(ctx->error, ENOMEM,
3939 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3940 "cannot create push vlan action");
3943 resource->idx = idx;
3944 return &resource->entry;
3947 struct mlx5_list_entry *
3948 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3949 struct mlx5_list_entry *entry __rte_unused,
3952 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3953 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3954 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3957 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3959 rte_flow_error_set(ctx->error, ENOMEM,
3960 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3961 "cannot allocate push_vlan action memory");
3964 memcpy(resource, entry, sizeof(*resource));
3965 resource->idx = idx;
3966 return &resource->entry;
3970 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3972 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3973 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3974 container_of(entry, typeof(*resource), entry);
3976 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3980 * Find existing push vlan resource or create and register a new one.
3982 * @param [in, out] dev
3983 * Pointer to rte_eth_dev structure.
3984 * @param[in, out] ref
3985 * Pointer to port ID action resource reference.
3986 * @parm[in, out] dev_flow
3987 * Pointer to the dev_flow.
3989 * pointer to error structure.
3992 * 0 on success otherwise -errno and errno is set.
3995 flow_dv_push_vlan_action_resource_register
3996 (struct rte_eth_dev *dev,
3997 struct mlx5_flow_dv_push_vlan_action_resource *ref,
3998 struct mlx5_flow *dev_flow,
3999 struct rte_flow_error *error)
4001 struct mlx5_priv *priv = dev->data->dev_private;
4002 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4003 struct mlx5_list_entry *entry;
4004 struct mlx5_flow_cb_ctx ctx = {
4009 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4012 resource = container_of(entry, typeof(*resource), entry);
4014 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4015 dev_flow->dv.push_vlan_res = resource;
4020 * Get the size of specific rte_flow_item_type hdr size
4022 * @param[in] item_type
4023 * Tested rte_flow_item_type.
4026 * sizeof struct item_type, 0 if void or irrelevant.
4029 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4033 switch (item_type) {
4034 case RTE_FLOW_ITEM_TYPE_ETH:
4035 retval = sizeof(struct rte_ether_hdr);
4037 case RTE_FLOW_ITEM_TYPE_VLAN:
4038 retval = sizeof(struct rte_vlan_hdr);
4040 case RTE_FLOW_ITEM_TYPE_IPV4:
4041 retval = sizeof(struct rte_ipv4_hdr);
4043 case RTE_FLOW_ITEM_TYPE_IPV6:
4044 retval = sizeof(struct rte_ipv6_hdr);
4046 case RTE_FLOW_ITEM_TYPE_UDP:
4047 retval = sizeof(struct rte_udp_hdr);
4049 case RTE_FLOW_ITEM_TYPE_TCP:
4050 retval = sizeof(struct rte_tcp_hdr);
4052 case RTE_FLOW_ITEM_TYPE_VXLAN:
4053 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4054 retval = sizeof(struct rte_vxlan_hdr);
4056 case RTE_FLOW_ITEM_TYPE_GRE:
4057 case RTE_FLOW_ITEM_TYPE_NVGRE:
4058 retval = sizeof(struct rte_gre_hdr);
4060 case RTE_FLOW_ITEM_TYPE_MPLS:
4061 retval = sizeof(struct rte_mpls_hdr);
4063 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4071 #define MLX5_ENCAP_IPV4_VERSION 0x40
4072 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4073 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4074 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4075 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4076 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4077 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4080 * Convert the encap action data from list of rte_flow_item to raw buffer
4083 * Pointer to rte_flow_item objects list.
4085 * Pointer to the output buffer.
4087 * Pointer to the output buffer size.
4089 * Pointer to the error structure.
4092 * 0 on success, a negative errno value otherwise and rte_errno is set.
4095 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4096 size_t *size, struct rte_flow_error *error)
4098 struct rte_ether_hdr *eth = NULL;
4099 struct rte_vlan_hdr *vlan = NULL;
4100 struct rte_ipv4_hdr *ipv4 = NULL;
4101 struct rte_ipv6_hdr *ipv6 = NULL;
4102 struct rte_udp_hdr *udp = NULL;
4103 struct rte_vxlan_hdr *vxlan = NULL;
4104 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4105 struct rte_gre_hdr *gre = NULL;
4107 size_t temp_size = 0;
4110 return rte_flow_error_set(error, EINVAL,
4111 RTE_FLOW_ERROR_TYPE_ACTION,
4112 NULL, "invalid empty data");
4113 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4114 len = flow_dv_get_item_hdr_len(items->type);
4115 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4116 return rte_flow_error_set(error, EINVAL,
4117 RTE_FLOW_ERROR_TYPE_ACTION,
4118 (void *)items->type,
4119 "items total size is too big"
4120 " for encap action");
4121 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4122 switch (items->type) {
4123 case RTE_FLOW_ITEM_TYPE_ETH:
4124 eth = (struct rte_ether_hdr *)&buf[temp_size];
4126 case RTE_FLOW_ITEM_TYPE_VLAN:
4127 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4129 return rte_flow_error_set(error, EINVAL,
4130 RTE_FLOW_ERROR_TYPE_ACTION,
4131 (void *)items->type,
4132 "eth header not found");
4133 if (!eth->ether_type)
4134 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4136 case RTE_FLOW_ITEM_TYPE_IPV4:
4137 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4139 return rte_flow_error_set(error, EINVAL,
4140 RTE_FLOW_ERROR_TYPE_ACTION,
4141 (void *)items->type,
4142 "neither eth nor vlan"
4144 if (vlan && !vlan->eth_proto)
4145 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4146 else if (eth && !eth->ether_type)
4147 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4148 if (!ipv4->version_ihl)
4149 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4150 MLX5_ENCAP_IPV4_IHL_MIN;
4151 if (!ipv4->time_to_live)
4152 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4154 case RTE_FLOW_ITEM_TYPE_IPV6:
4155 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4157 return rte_flow_error_set(error, EINVAL,
4158 RTE_FLOW_ERROR_TYPE_ACTION,
4159 (void *)items->type,
4160 "neither eth nor vlan"
4162 if (vlan && !vlan->eth_proto)
4163 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4164 else if (eth && !eth->ether_type)
4165 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4166 if (!ipv6->vtc_flow)
4168 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4169 if (!ipv6->hop_limits)
4170 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4172 case RTE_FLOW_ITEM_TYPE_UDP:
4173 udp = (struct rte_udp_hdr *)&buf[temp_size];
4175 return rte_flow_error_set(error, EINVAL,
4176 RTE_FLOW_ERROR_TYPE_ACTION,
4177 (void *)items->type,
4178 "ip header not found");
4179 if (ipv4 && !ipv4->next_proto_id)
4180 ipv4->next_proto_id = IPPROTO_UDP;
4181 else if (ipv6 && !ipv6->proto)
4182 ipv6->proto = IPPROTO_UDP;
4184 case RTE_FLOW_ITEM_TYPE_VXLAN:
4185 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4187 return rte_flow_error_set(error, EINVAL,
4188 RTE_FLOW_ERROR_TYPE_ACTION,
4189 (void *)items->type,
4190 "udp header not found");
4192 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4193 if (!vxlan->vx_flags)
4195 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4197 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4198 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4200 return rte_flow_error_set(error, EINVAL,
4201 RTE_FLOW_ERROR_TYPE_ACTION,
4202 (void *)items->type,
4203 "udp header not found");
4204 if (!vxlan_gpe->proto)
4205 return rte_flow_error_set(error, EINVAL,
4206 RTE_FLOW_ERROR_TYPE_ACTION,
4207 (void *)items->type,
4208 "next protocol not found");
4211 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4212 if (!vxlan_gpe->vx_flags)
4213 vxlan_gpe->vx_flags =
4214 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4216 case RTE_FLOW_ITEM_TYPE_GRE:
4217 case RTE_FLOW_ITEM_TYPE_NVGRE:
4218 gre = (struct rte_gre_hdr *)&buf[temp_size];
4220 return rte_flow_error_set(error, EINVAL,
4221 RTE_FLOW_ERROR_TYPE_ACTION,
4222 (void *)items->type,
4223 "next protocol not found");
4225 return rte_flow_error_set(error, EINVAL,
4226 RTE_FLOW_ERROR_TYPE_ACTION,
4227 (void *)items->type,
4228 "ip header not found");
4229 if (ipv4 && !ipv4->next_proto_id)
4230 ipv4->next_proto_id = IPPROTO_GRE;
4231 else if (ipv6 && !ipv6->proto)
4232 ipv6->proto = IPPROTO_GRE;
4234 case RTE_FLOW_ITEM_TYPE_VOID:
4237 return rte_flow_error_set(error, EINVAL,
4238 RTE_FLOW_ERROR_TYPE_ACTION,
4239 (void *)items->type,
4240 "unsupported item type");
4250 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4252 struct rte_ether_hdr *eth = NULL;
4253 struct rte_vlan_hdr *vlan = NULL;
4254 struct rte_ipv6_hdr *ipv6 = NULL;
4255 struct rte_udp_hdr *udp = NULL;
4259 eth = (struct rte_ether_hdr *)data;
4260 next_hdr = (char *)(eth + 1);
4261 proto = RTE_BE16(eth->ether_type);
4264 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4265 vlan = (struct rte_vlan_hdr *)next_hdr;
4266 proto = RTE_BE16(vlan->eth_proto);
4267 next_hdr += sizeof(struct rte_vlan_hdr);
4270 /* HW calculates IPv4 csum. no need to proceed */
4271 if (proto == RTE_ETHER_TYPE_IPV4)
4274 /* non IPv4/IPv6 header. not supported */
4275 if (proto != RTE_ETHER_TYPE_IPV6) {
4276 return rte_flow_error_set(error, ENOTSUP,
4277 RTE_FLOW_ERROR_TYPE_ACTION,
4278 NULL, "Cannot offload non IPv4/IPv6");
4281 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4283 /* ignore non UDP */
4284 if (ipv6->proto != IPPROTO_UDP)
4287 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4288 udp->dgram_cksum = 0;
4294 * Convert L2 encap action to DV specification.
4297 * Pointer to rte_eth_dev structure.
4299 * Pointer to action structure.
4300 * @param[in, out] dev_flow
4301 * Pointer to the mlx5_flow.
4302 * @param[in] transfer
4303 * Mark if the flow is E-Switch flow.
4305 * Pointer to the error structure.
4308 * 0 on success, a negative errno value otherwise and rte_errno is set.
4311 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4312 const struct rte_flow_action *action,
4313 struct mlx5_flow *dev_flow,
4315 struct rte_flow_error *error)
4317 const struct rte_flow_item *encap_data;
4318 const struct rte_flow_action_raw_encap *raw_encap_data;
4319 struct mlx5_flow_dv_encap_decap_resource res = {
4321 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4322 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4323 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4326 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4328 (const struct rte_flow_action_raw_encap *)action->conf;
4329 res.size = raw_encap_data->size;
4330 memcpy(res.buf, raw_encap_data->data, res.size);
4332 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4334 ((const struct rte_flow_action_vxlan_encap *)
4335 action->conf)->definition;
4338 ((const struct rte_flow_action_nvgre_encap *)
4339 action->conf)->definition;
4340 if (flow_dv_convert_encap_data(encap_data, res.buf,
4344 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4346 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4347 return rte_flow_error_set(error, EINVAL,
4348 RTE_FLOW_ERROR_TYPE_ACTION,
4349 NULL, "can't create L2 encap action");
4354 * Convert L2 decap action to DV specification.
4357 * Pointer to rte_eth_dev structure.
4358 * @param[in, out] dev_flow
4359 * Pointer to the mlx5_flow.
4360 * @param[in] transfer
4361 * Mark if the flow is E-Switch flow.
4363 * Pointer to the error structure.
4366 * 0 on success, a negative errno value otherwise and rte_errno is set.
4369 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4370 struct mlx5_flow *dev_flow,
4372 struct rte_flow_error *error)
4374 struct mlx5_flow_dv_encap_decap_resource res = {
4377 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4378 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4379 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4382 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4383 return rte_flow_error_set(error, EINVAL,
4384 RTE_FLOW_ERROR_TYPE_ACTION,
4385 NULL, "can't create L2 decap action");
4390 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4393 * Pointer to rte_eth_dev structure.
4395 * Pointer to action structure.
4396 * @param[in, out] dev_flow
4397 * Pointer to the mlx5_flow.
4399 * Pointer to the flow attributes.
4401 * Pointer to the error structure.
4404 * 0 on success, a negative errno value otherwise and rte_errno is set.
4407 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4408 const struct rte_flow_action *action,
4409 struct mlx5_flow *dev_flow,
4410 const struct rte_flow_attr *attr,
4411 struct rte_flow_error *error)
4413 const struct rte_flow_action_raw_encap *encap_data;
4414 struct mlx5_flow_dv_encap_decap_resource res;
4416 memset(&res, 0, sizeof(res));
4417 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4418 res.size = encap_data->size;
4419 memcpy(res.buf, encap_data->data, res.size);
4420 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4421 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4422 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4424 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4426 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4427 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4428 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4429 return rte_flow_error_set(error, EINVAL,
4430 RTE_FLOW_ERROR_TYPE_ACTION,
4431 NULL, "can't create encap action");
4436 * Create action push VLAN.
4439 * Pointer to rte_eth_dev structure.
4441 * Pointer to the flow attributes.
4443 * Pointer to the vlan to push to the Ethernet header.
4444 * @param[in, out] dev_flow
4445 * Pointer to the mlx5_flow.
4447 * Pointer to the error structure.
4450 * 0 on success, a negative errno value otherwise and rte_errno is set.
4453 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4454 const struct rte_flow_attr *attr,
4455 const struct rte_vlan_hdr *vlan,
4456 struct mlx5_flow *dev_flow,
4457 struct rte_flow_error *error)
4459 struct mlx5_flow_dv_push_vlan_action_resource res;
4461 memset(&res, 0, sizeof(res));
4463 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4466 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4468 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4469 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4470 return flow_dv_push_vlan_action_resource_register
4471 (dev, &res, dev_flow, error);
4475 * Validate the modify-header actions.
4477 * @param[in] action_flags
4478 * Holds the actions detected until now.
4480 * Pointer to the modify action.
4482 * Pointer to error structure.
4485 * 0 on success, a negative errno value otherwise and rte_errno is set.
4488 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4489 const struct rte_flow_action *action,
4490 struct rte_flow_error *error)
4492 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4493 return rte_flow_error_set(error, EINVAL,
4494 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4495 NULL, "action configuration not set");
4496 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4497 return rte_flow_error_set(error, EINVAL,
4498 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4499 "can't have encap action before"
4505 * Validate the modify-header MAC address actions.
4507 * @param[in] action_flags
4508 * Holds the actions detected until now.
4510 * Pointer to the modify action.
4511 * @param[in] item_flags
4512 * Holds the items detected.
4514 * Pointer to error structure.
4517 * 0 on success, a negative errno value otherwise and rte_errno is set.
4520 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4521 const struct rte_flow_action *action,
4522 const uint64_t item_flags,
4523 struct rte_flow_error *error)
4527 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4529 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4530 return rte_flow_error_set(error, EINVAL,
4531 RTE_FLOW_ERROR_TYPE_ACTION,
4533 "no L2 item in pattern");
4539 * Validate the modify-header IPv4 address actions.
4541 * @param[in] action_flags
4542 * Holds the actions detected until now.
4544 * Pointer to the modify action.
4545 * @param[in] item_flags
4546 * Holds the items detected.
4548 * Pointer to error structure.
4551 * 0 on success, a negative errno value otherwise and rte_errno is set.
4554 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4555 const struct rte_flow_action *action,
4556 const uint64_t item_flags,
4557 struct rte_flow_error *error)
4562 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4564 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4565 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4566 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4567 if (!(item_flags & layer))
4568 return rte_flow_error_set(error, EINVAL,
4569 RTE_FLOW_ERROR_TYPE_ACTION,
4571 "no ipv4 item in pattern");
4577 * Validate the modify-header IPv6 address actions.
4579 * @param[in] action_flags
4580 * Holds the actions detected until now.
4582 * Pointer to the modify action.
4583 * @param[in] item_flags
4584 * Holds the items detected.
4586 * Pointer to error structure.
4589 * 0 on success, a negative errno value otherwise and rte_errno is set.
4592 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4593 const struct rte_flow_action *action,
4594 const uint64_t item_flags,
4595 struct rte_flow_error *error)
4600 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4602 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4603 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4604 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4605 if (!(item_flags & layer))
4606 return rte_flow_error_set(error, EINVAL,
4607 RTE_FLOW_ERROR_TYPE_ACTION,
4609 "no ipv6 item in pattern");
4615 * Validate the modify-header TP actions.
4617 * @param[in] action_flags
4618 * Holds the actions detected until now.
4620 * Pointer to the modify action.
4621 * @param[in] item_flags
4622 * Holds the items detected.
4624 * Pointer to error structure.
4627 * 0 on success, a negative errno value otherwise and rte_errno is set.
4630 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4631 const struct rte_flow_action *action,
4632 const uint64_t item_flags,
4633 struct rte_flow_error *error)
4638 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4640 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4641 MLX5_FLOW_LAYER_INNER_L4 :
4642 MLX5_FLOW_LAYER_OUTER_L4;
4643 if (!(item_flags & layer))
4644 return rte_flow_error_set(error, EINVAL,
4645 RTE_FLOW_ERROR_TYPE_ACTION,
4646 NULL, "no transport layer "
4653 * Validate the modify-header actions of increment/decrement
4654 * TCP Sequence-number.
4656 * @param[in] action_flags
4657 * Holds the actions detected until now.
4659 * Pointer to the modify action.
4660 * @param[in] item_flags
4661 * Holds the items detected.
4663 * Pointer to error structure.
4666 * 0 on success, a negative errno value otherwise and rte_errno is set.
4669 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4670 const struct rte_flow_action *action,
4671 const uint64_t item_flags,
4672 struct rte_flow_error *error)
4677 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4679 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4680 MLX5_FLOW_LAYER_INNER_L4_TCP :
4681 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4682 if (!(item_flags & layer))
4683 return rte_flow_error_set(error, EINVAL,
4684 RTE_FLOW_ERROR_TYPE_ACTION,
4685 NULL, "no TCP item in"
4687 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4688 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4689 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4690 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4691 return rte_flow_error_set(error, EINVAL,
4692 RTE_FLOW_ERROR_TYPE_ACTION,
4694 "cannot decrease and increase"
4695 " TCP sequence number"
4696 " at the same time");
4702 * Validate the modify-header actions of increment/decrement
4703 * TCP Acknowledgment number.
4705 * @param[in] action_flags
4706 * Holds the actions detected until now.
4708 * Pointer to the modify action.
4709 * @param[in] item_flags
4710 * Holds the items detected.
4712 * Pointer to error structure.
4715 * 0 on success, a negative errno value otherwise and rte_errno is set.
4718 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4719 const struct rte_flow_action *action,
4720 const uint64_t item_flags,
4721 struct rte_flow_error *error)
4726 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4728 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4729 MLX5_FLOW_LAYER_INNER_L4_TCP :
4730 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4731 if (!(item_flags & layer))
4732 return rte_flow_error_set(error, EINVAL,
4733 RTE_FLOW_ERROR_TYPE_ACTION,
4734 NULL, "no TCP item in"
4736 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4737 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4738 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4739 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4740 return rte_flow_error_set(error, EINVAL,
4741 RTE_FLOW_ERROR_TYPE_ACTION,
4743 "cannot decrease and increase"
4744 " TCP acknowledgment number"
4745 " at the same time");
4751 * Validate the modify-header TTL actions.
4753 * @param[in] action_flags
4754 * Holds the actions detected until now.
4756 * Pointer to the modify action.
4757 * @param[in] item_flags
4758 * Holds the items detected.
4760 * Pointer to error structure.
4763 * 0 on success, a negative errno value otherwise and rte_errno is set.
4766 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4767 const struct rte_flow_action *action,
4768 const uint64_t item_flags,
4769 struct rte_flow_error *error)
4774 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4776 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4777 MLX5_FLOW_LAYER_INNER_L3 :
4778 MLX5_FLOW_LAYER_OUTER_L3;
4779 if (!(item_flags & layer))
4780 return rte_flow_error_set(error, EINVAL,
4781 RTE_FLOW_ERROR_TYPE_ACTION,
4783 "no IP protocol in pattern");
4789 * Validate the generic modify field actions.
4791 * Pointer to the rte_eth_dev structure.
4792 * @param[in] action_flags
4793 * Holds the actions detected until now.
4795 * Pointer to the modify action.
4797 * Pointer to the flow attributes.
4799 * Pointer to error structure.
4802 * Number of header fields to modify (0 or more) on success,
4803 * a negative errno value otherwise and rte_errno is set.
4806 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4807 const uint64_t action_flags,
4808 const struct rte_flow_action *action,
4809 const struct rte_flow_attr *attr,
4810 struct rte_flow_error *error)
4813 struct mlx5_priv *priv = dev->data->dev_private;
4814 struct mlx5_dev_config *config = &priv->config;
4815 const struct rte_flow_action_modify_field *action_modify_field =
4817 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4818 action_modify_field->dst.field,
4820 uint32_t src_width = mlx5_flow_item_field_width(dev,
4821 action_modify_field->src.field,
4822 dst_width, attr, error);
4824 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4828 if (action_modify_field->width == 0)
4829 return rte_flow_error_set(error, EINVAL,
4830 RTE_FLOW_ERROR_TYPE_ACTION, action,
4831 "no bits are requested to be modified");
4832 else if (action_modify_field->width > dst_width ||
4833 action_modify_field->width > src_width)
4834 return rte_flow_error_set(error, EINVAL,
4835 RTE_FLOW_ERROR_TYPE_ACTION, action,
4836 "cannot modify more bits than"
4837 " the width of a field");
4838 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4839 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4840 if ((action_modify_field->dst.offset +
4841 action_modify_field->width > dst_width) ||
4842 (action_modify_field->dst.offset % 32))
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "destination offset is too big"
4846 " or not aligned to 4 bytes");
4847 if (action_modify_field->dst.level &&
4848 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4849 return rte_flow_error_set(error, ENOTSUP,
4850 RTE_FLOW_ERROR_TYPE_ACTION, action,
4851 "inner header fields modification"
4852 " is not supported");
4854 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4855 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4856 if (!attr->transfer && !attr->group)
4857 return rte_flow_error_set(error, ENOTSUP,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "modify field action is not"
4860 " supported for group 0");
4861 if ((action_modify_field->src.offset +
4862 action_modify_field->width > src_width) ||
4863 (action_modify_field->src.offset % 32))
4864 return rte_flow_error_set(error, EINVAL,
4865 RTE_FLOW_ERROR_TYPE_ACTION, action,
4866 "source offset is too big"
4867 " or not aligned to 4 bytes");
4868 if (action_modify_field->src.level &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4870 return rte_flow_error_set(error, ENOTSUP,
4871 RTE_FLOW_ERROR_TYPE_ACTION, action,
4872 "inner header fields modification"
4873 " is not supported");
4875 if ((action_modify_field->dst.field ==
4876 action_modify_field->src.field) &&
4877 (action_modify_field->dst.level ==
4878 action_modify_field->src.level))
4879 return rte_flow_error_set(error, EINVAL,
4880 RTE_FLOW_ERROR_TYPE_ACTION, action,
4881 "source and destination fields"
4882 " cannot be the same");
4883 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4884 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4885 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4886 return rte_flow_error_set(error, EINVAL,
4887 RTE_FLOW_ERROR_TYPE_ACTION, action,
4888 "mark, immediate value or a pointer to it"
4889 " cannot be used as a destination");
4890 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4891 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4892 return rte_flow_error_set(error, ENOTSUP,
4893 RTE_FLOW_ERROR_TYPE_ACTION, action,
4894 "modifications of an arbitrary"
4895 " place in a packet is not supported");
4896 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4897 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4898 return rte_flow_error_set(error, ENOTSUP,
4899 RTE_FLOW_ERROR_TYPE_ACTION, action,
4900 "modifications of the 802.1Q Tag"
4901 " Identifier is not supported");
4902 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4903 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4904 return rte_flow_error_set(error, ENOTSUP,
4905 RTE_FLOW_ERROR_TYPE_ACTION, action,
4906 "modifications of the VXLAN Network"
4907 " Identifier is not supported");
4908 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4909 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4910 return rte_flow_error_set(error, ENOTSUP,
4911 RTE_FLOW_ERROR_TYPE_ACTION, action,
4912 "modifications of the GENEVE Network"
4913 " Identifier is not supported");
4914 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4915 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4916 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4917 !mlx5_flow_ext_mreg_supported(dev))
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "cannot modify mark in legacy mode"
4921 " or without extensive registers");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4924 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4925 !mlx5_flow_ext_mreg_supported(dev))
4926 return rte_flow_error_set(error, ENOTSUP,
4927 RTE_FLOW_ERROR_TYPE_ACTION, action,
4928 "cannot modify meta without"
4929 " extensive registers support");
4930 ret = flow_dv_get_metadata_reg(dev, attr, error);
4931 if (ret < 0 || ret == REG_NON)
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify meta without"
4935 " extensive registers available");
4937 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4938 return rte_flow_error_set(error, ENOTSUP,
4939 RTE_FLOW_ERROR_TYPE_ACTION, action,
4940 "add and sub operations"
4941 " are not supported");
4942 return (action_modify_field->width / 32) +
4943 !!(action_modify_field->width % 32);
4947 * Validate jump action.
4950 * Pointer to the jump action.
4951 * @param[in] action_flags
4952 * Holds the actions detected until now.
4953 * @param[in] attributes
4954 * Pointer to flow attributes
4955 * @param[in] external
4956 * Action belongs to flow rule created by request external to PMD.
4958 * Pointer to error structure.
4961 * 0 on success, a negative errno value otherwise and rte_errno is set.
4964 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4965 const struct mlx5_flow_tunnel *tunnel,
4966 const struct rte_flow_action *action,
4967 uint64_t action_flags,
4968 const struct rte_flow_attr *attributes,
4969 bool external, struct rte_flow_error *error)
4971 uint32_t target_group, table;
4973 struct flow_grp_info grp_info = {
4974 .external = !!external,
4975 .transfer = !!attributes->transfer,
4979 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4980 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4981 return rte_flow_error_set(error, EINVAL,
4982 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4983 "can't have 2 fate actions in"
4986 return rte_flow_error_set(error, EINVAL,
4987 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4988 NULL, "action configuration not set");
4990 ((const struct rte_flow_action_jump *)action->conf)->group;
4991 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4995 if (attributes->group == target_group &&
4996 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4997 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4998 return rte_flow_error_set(error, EINVAL,
4999 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5000 "target group must be other than"
5001 " the current flow group");
5006 * Validate action PORT_ID / REPRESENTED_PORT.
5009 * Pointer to rte_eth_dev structure.
5010 * @param[in] action_flags
5011 * Bit-fields that holds the actions detected until now.
5013 * PORT_ID / REPRESENTED_PORT action structure.
5015 * Attributes of flow that includes this action.
5017 * Pointer to error structure.
5020 * 0 on success, a negative errno value otherwise and rte_errno is set.
5023 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5024 uint64_t action_flags,
5025 const struct rte_flow_action *action,
5026 const struct rte_flow_attr *attr,
5027 struct rte_flow_error *error)
5029 const struct rte_flow_action_port_id *port_id;
5030 const struct rte_flow_action_ethdev *ethdev;
5031 struct mlx5_priv *act_priv;
5032 struct mlx5_priv *dev_priv;
5035 if (!attr->transfer)
5036 return rte_flow_error_set(error, ENOTSUP,
5037 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5039 "port action is valid in transfer"
5041 if (!action || !action->conf)
5042 return rte_flow_error_set(error, ENOTSUP,
5043 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5045 "port action parameters must be"
5047 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5048 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5049 return rte_flow_error_set(error, EINVAL,
5050 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5051 "can have only one fate actions in"
5053 dev_priv = mlx5_dev_to_eswitch_info(dev);
5055 return rte_flow_error_set(error, rte_errno,
5056 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5058 "failed to obtain E-Switch info");
5059 switch (action->type) {
5060 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5061 port_id = action->conf;
5062 port = port_id->original ? dev->data->port_id : port_id->id;
5064 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5065 ethdev = action->conf;
5066 port = ethdev->port_id;
5070 return rte_flow_error_set
5072 RTE_FLOW_ERROR_TYPE_ACTION, action,
5073 "unknown E-Switch action");
5075 act_priv = mlx5_port_to_eswitch_info(port, false);
5077 return rte_flow_error_set
5079 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5080 "failed to obtain E-Switch port id for port");
5081 if (act_priv->domain_id != dev_priv->domain_id)
5082 return rte_flow_error_set
5084 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5085 "port does not belong to"
5086 " E-Switch being configured");
5091 * Get the maximum number of modify header actions.
5094 * Pointer to rte_eth_dev structure.
5096 * Whether action is on root table.
5099 * Max number of modify header actions device can support.
5101 static inline unsigned int
5102 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5106 * There's no way to directly query the max capacity from FW.
5107 * The maximal value on root table should be assumed to be supported.
5110 return MLX5_MAX_MODIFY_NUM;
5112 return MLX5_ROOT_TBL_MODIFY_NUM;
5116 * Validate the meter action.
5119 * Pointer to rte_eth_dev structure.
5120 * @param[in] action_flags
5121 * Bit-fields that holds the actions detected until now.
5123 * Pointer to the meter action.
5125 * Attributes of flow that includes this action.
5126 * @param[in] port_id_item
5127 * Pointer to item indicating port id.
5129 * Pointer to error structure.
5132 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5135 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5136 uint64_t action_flags,
5137 const struct rte_flow_action *action,
5138 const struct rte_flow_attr *attr,
5139 const struct rte_flow_item *port_id_item,
5141 struct rte_flow_error *error)
5143 struct mlx5_priv *priv = dev->data->dev_private;
5144 const struct rte_flow_action_meter *am = action->conf;
5145 struct mlx5_flow_meter_info *fm;
5146 struct mlx5_flow_meter_policy *mtr_policy;
5147 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5150 return rte_flow_error_set(error, EINVAL,
5151 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5152 "meter action conf is NULL");
5154 if (action_flags & MLX5_FLOW_ACTION_METER)
5155 return rte_flow_error_set(error, ENOTSUP,
5156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5157 "meter chaining not support");
5158 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5159 return rte_flow_error_set(error, ENOTSUP,
5160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5161 "meter with jump not support");
5163 return rte_flow_error_set(error, ENOTSUP,
5164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5166 "meter action not supported");
5167 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5169 return rte_flow_error_set(error, EINVAL,
5170 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5172 /* aso meter can always be shared by different domains */
5173 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5174 !(fm->transfer == attr->transfer ||
5175 (!fm->ingress && !attr->ingress && attr->egress) ||
5176 (!fm->egress && !attr->egress && attr->ingress)))
5177 return rte_flow_error_set(error, EINVAL,
5178 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5179 "Flow attributes domain are either invalid "
5180 "or have a domain conflict with current "
5181 "meter attributes");
5182 if (fm->def_policy) {
5183 if (!((attr->transfer &&
5184 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5186 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5188 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5189 return rte_flow_error_set(error, EINVAL,
5190 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5191 "Flow attributes domain "
5192 "have a conflict with current "
5193 "meter domain attributes");
5196 mtr_policy = mlx5_flow_meter_policy_find(dev,
5197 fm->policy_id, NULL);
5199 return rte_flow_error_set(error, EINVAL,
5200 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5201 "Invalid policy id for meter ");
5202 if (!((attr->transfer && mtr_policy->transfer) ||
5203 (attr->egress && mtr_policy->egress) ||
5204 (attr->ingress && mtr_policy->ingress)))
5205 return rte_flow_error_set(error, EINVAL,
5206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5207 "Flow attributes domain "
5208 "have a conflict with current "
5209 "meter domain attributes");
5210 if (attr->transfer && mtr_policy->dev) {
5212 * When policy has fate action of port_id,
5213 * the flow should have the same src port as policy.
5215 struct mlx5_priv *policy_port_priv =
5216 mtr_policy->dev->data->dev_private;
5217 int32_t flow_src_port = priv->representor_id;
5220 const struct rte_flow_item_port_id *spec =
5222 struct mlx5_priv *port_priv =
5223 mlx5_port_to_eswitch_info(spec->id,
5226 return rte_flow_error_set(error,
5228 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5230 "Failed to get port info.");
5231 flow_src_port = port_priv->representor_id;
5233 if (flow_src_port != policy_port_priv->representor_id)
5234 return rte_flow_error_set(error,
5236 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5238 "Flow and meter policy "
5239 "have different src port.");
5241 *def_policy = false;
5247 * Validate the age action.
5249 * @param[in] action_flags
5250 * Holds the actions detected until now.
5252 * Pointer to the age action.
5254 * Pointer to the Ethernet device structure.
5256 * Pointer to error structure.
5259 * 0 on success, a negative errno value otherwise and rte_errno is set.
5262 flow_dv_validate_action_age(uint64_t action_flags,
5263 const struct rte_flow_action *action,
5264 struct rte_eth_dev *dev,
5265 struct rte_flow_error *error)
5267 struct mlx5_priv *priv = dev->data->dev_private;
5268 const struct rte_flow_action_age *age = action->conf;
5270 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5271 !priv->sh->aso_age_mng))
5272 return rte_flow_error_set(error, ENOTSUP,
5273 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5275 "age action not supported");
5276 if (!(action->conf))
5277 return rte_flow_error_set(error, EINVAL,
5278 RTE_FLOW_ERROR_TYPE_ACTION, action,
5279 "configuration cannot be null");
5280 if (!(age->timeout))
5281 return rte_flow_error_set(error, EINVAL,
5282 RTE_FLOW_ERROR_TYPE_ACTION, action,
5283 "invalid timeout value 0");
5284 if (action_flags & MLX5_FLOW_ACTION_AGE)
5285 return rte_flow_error_set(error, EINVAL,
5286 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5287 "duplicate age actions set");
5292 * Validate the modify-header IPv4 DSCP actions.
5294 * @param[in] action_flags
5295 * Holds the actions detected until now.
5297 * Pointer to the modify action.
5298 * @param[in] item_flags
5299 * Holds the items detected.
5301 * Pointer to error structure.
5304 * 0 on success, a negative errno value otherwise and rte_errno is set.
5307 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5308 const struct rte_flow_action *action,
5309 const uint64_t item_flags,
5310 struct rte_flow_error *error)
5314 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5316 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5317 return rte_flow_error_set(error, EINVAL,
5318 RTE_FLOW_ERROR_TYPE_ACTION,
5320 "no ipv4 item in pattern");
5326 * Validate the modify-header IPv6 DSCP actions.
5328 * @param[in] action_flags
5329 * Holds the actions detected until now.
5331 * Pointer to the modify action.
5332 * @param[in] item_flags
5333 * Holds the items detected.
5335 * Pointer to error structure.
5338 * 0 on success, a negative errno value otherwise and rte_errno is set.
5341 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5342 const struct rte_flow_action *action,
5343 const uint64_t item_flags,
5344 struct rte_flow_error *error)
5348 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5350 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5351 return rte_flow_error_set(error, EINVAL,
5352 RTE_FLOW_ERROR_TYPE_ACTION,
5354 "no ipv6 item in pattern");
5360 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5361 struct mlx5_list_entry *entry, void *cb_ctx)
5363 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5364 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5365 struct mlx5_flow_dv_modify_hdr_resource *resource =
5366 container_of(entry, typeof(*resource), entry);
5367 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5369 key_len += ref->actions_num * sizeof(ref->actions[0]);
5370 return ref->actions_num != resource->actions_num ||
5371 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5374 static struct mlx5_indexed_pool *
5375 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5377 struct mlx5_indexed_pool *ipool = __atomic_load_n
5378 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5381 struct mlx5_indexed_pool *expected = NULL;
5382 struct mlx5_indexed_pool_config cfg =
5383 (struct mlx5_indexed_pool_config) {
5384 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5386 sizeof(struct mlx5_modification_cmd),
5391 .release_mem_en = !!sh->reclaim_mode,
5392 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5393 .malloc = mlx5_malloc,
5395 .type = "mlx5_modify_action_resource",
5398 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5399 ipool = mlx5_ipool_create(&cfg);
5402 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5403 &expected, ipool, false,
5405 __ATOMIC_SEQ_CST)) {
5406 mlx5_ipool_destroy(ipool);
5407 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5414 struct mlx5_list_entry *
5415 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5417 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5418 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5419 struct mlx5dv_dr_domain *ns;
5420 struct mlx5_flow_dv_modify_hdr_resource *entry;
5421 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5422 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5423 ref->actions_num - 1);
5425 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5426 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5429 if (unlikely(!ipool)) {
5430 rte_flow_error_set(ctx->error, ENOMEM,
5431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5432 NULL, "cannot allocate modify ipool");
5435 entry = mlx5_ipool_zmalloc(ipool, &idx);
5437 rte_flow_error_set(ctx->error, ENOMEM,
5438 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5439 "cannot allocate resource memory");
5442 rte_memcpy(&entry->ft_type,
5443 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5444 key_len + data_len);
5445 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5446 ns = sh->fdb_domain;
5447 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5451 ret = mlx5_flow_os_create_flow_action_modify_header
5452 (sh->cdev->ctx, ns, entry,
5453 data_len, &entry->action);
5455 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5456 rte_flow_error_set(ctx->error, ENOMEM,
5457 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5458 NULL, "cannot create modification action");
5462 return &entry->entry;
5465 struct mlx5_list_entry *
5466 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5469 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5470 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5471 struct mlx5_flow_dv_modify_hdr_resource *entry;
5472 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5473 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5476 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5479 rte_flow_error_set(ctx->error, ENOMEM,
5480 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5481 "cannot allocate resource memory");
5484 memcpy(entry, oentry, sizeof(*entry) + data_len);
5486 return &entry->entry;
5490 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5492 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5493 struct mlx5_flow_dv_modify_hdr_resource *res =
5494 container_of(entry, typeof(*res), entry);
5496 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5500 * Validate the sample action.
5502 * @param[in, out] action_flags
5503 * Holds the actions detected until now.
5505 * Pointer to the sample action.
5507 * Pointer to the Ethernet device structure.
5509 * Attributes of flow that includes this action.
5510 * @param[in] item_flags
5511 * Holds the items detected.
5513 * Pointer to the RSS action.
5514 * @param[out] sample_rss
5515 * Pointer to the RSS action in sample action list.
5517 * Pointer to the COUNT action in sample action list.
5518 * @param[out] fdb_mirror_limit
5519 * Pointer to the FDB mirror limitation flag.
5521 * Pointer to error structure.
5524 * 0 on success, a negative errno value otherwise and rte_errno is set.
5527 flow_dv_validate_action_sample(uint64_t *action_flags,
5528 const struct rte_flow_action *action,
5529 struct rte_eth_dev *dev,
5530 const struct rte_flow_attr *attr,
5531 uint64_t item_flags,
5532 const struct rte_flow_action_rss *rss,
5533 const struct rte_flow_action_rss **sample_rss,
5534 const struct rte_flow_action_count **count,
5535 int *fdb_mirror_limit,
5536 struct rte_flow_error *error)
5538 struct mlx5_priv *priv = dev->data->dev_private;
5539 struct mlx5_dev_config *dev_conf = &priv->config;
5540 const struct rte_flow_action_sample *sample = action->conf;
5541 const struct rte_flow_action *act;
5542 uint64_t sub_action_flags = 0;
5543 uint16_t queue_index = 0xFFFF;
5548 return rte_flow_error_set(error, EINVAL,
5549 RTE_FLOW_ERROR_TYPE_ACTION, action,
5550 "configuration cannot be NULL");
5551 if (sample->ratio == 0)
5552 return rte_flow_error_set(error, EINVAL,
5553 RTE_FLOW_ERROR_TYPE_ACTION, action,
5554 "ratio value starts from 1");
5555 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5556 return rte_flow_error_set(error, ENOTSUP,
5557 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5559 "sample action not supported");
5560 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5561 return rte_flow_error_set(error, EINVAL,
5562 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5563 "Multiple sample actions not "
5565 if (*action_flags & MLX5_FLOW_ACTION_METER)
5566 return rte_flow_error_set(error, EINVAL,
5567 RTE_FLOW_ERROR_TYPE_ACTION, action,
5568 "wrong action order, meter should "
5569 "be after sample action");
5570 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5571 return rte_flow_error_set(error, EINVAL,
5572 RTE_FLOW_ERROR_TYPE_ACTION, action,
5573 "wrong action order, jump should "
5574 "be after sample action");
5575 if (*action_flags & MLX5_FLOW_ACTION_CT)
5576 return rte_flow_error_set(error, EINVAL,
5577 RTE_FLOW_ERROR_TYPE_ACTION, action,
5578 "Sample after CT not supported");
5579 act = sample->actions;
5580 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5581 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5582 return rte_flow_error_set(error, ENOTSUP,
5583 RTE_FLOW_ERROR_TYPE_ACTION,
5584 act, "too many actions");
5585 switch (act->type) {
5586 case RTE_FLOW_ACTION_TYPE_QUEUE:
5587 ret = mlx5_flow_validate_action_queue(act,
5593 queue_index = ((const struct rte_flow_action_queue *)
5594 (act->conf))->index;
5595 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5598 case RTE_FLOW_ACTION_TYPE_RSS:
5599 *sample_rss = act->conf;
5600 ret = mlx5_flow_validate_action_rss(act,
5607 if (rss && *sample_rss &&
5608 ((*sample_rss)->level != rss->level ||
5609 (*sample_rss)->types != rss->types))
5610 return rte_flow_error_set(error, ENOTSUP,
5611 RTE_FLOW_ERROR_TYPE_ACTION,
5613 "Can't use the different RSS types "
5614 "or level in the same flow");
5615 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5616 queue_index = (*sample_rss)->queue[0];
5617 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5620 case RTE_FLOW_ACTION_TYPE_MARK:
5621 ret = flow_dv_validate_action_mark(dev, act,
5626 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5627 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5628 MLX5_FLOW_ACTION_MARK_EXT;
5630 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5633 case RTE_FLOW_ACTION_TYPE_COUNT:
5634 ret = flow_dv_validate_action_count
5635 (dev, false, *action_flags | sub_action_flags,
5640 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5641 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5644 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5645 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5646 ret = flow_dv_validate_action_port_id(dev,
5653 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5656 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5657 ret = flow_dv_validate_action_raw_encap_decap
5658 (dev, NULL, act->conf, attr, &sub_action_flags,
5659 &actions_n, action, item_flags, error);
5664 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5665 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5666 ret = flow_dv_validate_action_l2_encap(dev,
5672 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5676 return rte_flow_error_set(error, ENOTSUP,
5677 RTE_FLOW_ERROR_TYPE_ACTION,
5679 "Doesn't support optional "
5683 if (attr->ingress && !attr->transfer) {
5684 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5685 MLX5_FLOW_ACTION_RSS)))
5686 return rte_flow_error_set(error, EINVAL,
5687 RTE_FLOW_ERROR_TYPE_ACTION,
5689 "Ingress must has a dest "
5690 "QUEUE for Sample");
5691 } else if (attr->egress && !attr->transfer) {
5692 return rte_flow_error_set(error, ENOTSUP,
5693 RTE_FLOW_ERROR_TYPE_ACTION,
5695 "Sample Only support Ingress "
5697 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5698 MLX5_ASSERT(attr->transfer);
5699 if (sample->ratio > 1)
5700 return rte_flow_error_set(error, ENOTSUP,
5701 RTE_FLOW_ERROR_TYPE_ACTION,
5703 "E-Switch doesn't support "
5704 "any optional action "
5706 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5707 return rte_flow_error_set(error, ENOTSUP,
5708 RTE_FLOW_ERROR_TYPE_ACTION,
5710 "unsupported action QUEUE");
5711 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5712 return rte_flow_error_set(error, ENOTSUP,
5713 RTE_FLOW_ERROR_TYPE_ACTION,
5715 "unsupported action QUEUE");
5716 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5717 return rte_flow_error_set(error, EINVAL,
5718 RTE_FLOW_ERROR_TYPE_ACTION,
5720 "E-Switch must has a dest "
5721 "port for mirroring");
5722 if (!priv->config.hca_attr.reg_c_preserve &&
5723 priv->representor_id != UINT16_MAX)
5724 *fdb_mirror_limit = 1;
5726 /* Continue validation for Xcap actions.*/
5727 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5728 (queue_index == 0xFFFF ||
5729 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5730 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5731 MLX5_FLOW_XCAP_ACTIONS)
5732 return rte_flow_error_set(error, ENOTSUP,
5733 RTE_FLOW_ERROR_TYPE_ACTION,
5734 NULL, "encap and decap "
5735 "combination aren't "
5737 if (!attr->transfer && attr->ingress && (sub_action_flags &
5738 MLX5_FLOW_ACTION_ENCAP))
5739 return rte_flow_error_set(error, ENOTSUP,
5740 RTE_FLOW_ERROR_TYPE_ACTION,
5741 NULL, "encap is not supported"
5742 " for ingress traffic");
5748 * Find existing modify-header resource or create and register a new one.
5750 * @param dev[in, out]
5751 * Pointer to rte_eth_dev structure.
5752 * @param[in, out] resource
5753 * Pointer to modify-header resource.
5754 * @parm[in, out] dev_flow
5755 * Pointer to the dev_flow.
5757 * pointer to error structure.
5760 * 0 on success otherwise -errno and errno is set.
5763 flow_dv_modify_hdr_resource_register
5764 (struct rte_eth_dev *dev,
5765 struct mlx5_flow_dv_modify_hdr_resource *resource,
5766 struct mlx5_flow *dev_flow,
5767 struct rte_flow_error *error)
5769 struct mlx5_priv *priv = dev->data->dev_private;
5770 struct mlx5_dev_ctx_shared *sh = priv->sh;
5771 uint32_t key_len = sizeof(*resource) -
5772 offsetof(typeof(*resource), ft_type) +
5773 resource->actions_num * sizeof(resource->actions[0]);
5774 struct mlx5_list_entry *entry;
5775 struct mlx5_flow_cb_ctx ctx = {
5779 struct mlx5_hlist *modify_cmds;
5782 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5784 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5786 flow_dv_modify_create_cb,
5787 flow_dv_modify_match_cb,
5788 flow_dv_modify_remove_cb,
5789 flow_dv_modify_clone_cb,
5790 flow_dv_modify_clone_free_cb);
5791 if (unlikely(!modify_cmds))
5793 resource->root = !dev_flow->dv.group;
5794 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5796 return rte_flow_error_set(error, EOVERFLOW,
5797 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5798 "too many modify header items");
5799 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5800 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5803 resource = container_of(entry, typeof(*resource), entry);
5804 dev_flow->handle->dvh.modify_hdr = resource;
5809 * Get DV flow counter by index.
5812 * Pointer to the Ethernet device structure.
5814 * mlx5 flow counter index in the container.
5816 * mlx5 flow counter pool in the container.
5819 * Pointer to the counter, NULL otherwise.
5821 static struct mlx5_flow_counter *
5822 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5824 struct mlx5_flow_counter_pool **ppool)
5826 struct mlx5_priv *priv = dev->data->dev_private;
5827 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5828 struct mlx5_flow_counter_pool *pool;
5830 /* Decrease to original index and clear shared bit. */
5831 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5832 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5833 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5837 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5841 * Check the devx counter belongs to the pool.
5844 * Pointer to the counter pool.
5846 * The counter devx ID.
5849 * True if counter belongs to the pool, false otherwise.
5852 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5854 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5855 MLX5_COUNTERS_PER_POOL;
5857 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5863 * Get a pool by devx counter ID.
5866 * Pointer to the counter management.
5868 * The counter devx ID.
5871 * The counter pool pointer if exists, NULL otherwise,
5873 static struct mlx5_flow_counter_pool *
5874 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5877 struct mlx5_flow_counter_pool *pool = NULL;
5879 rte_spinlock_lock(&cmng->pool_update_sl);
5880 /* Check last used pool. */
5881 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5882 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5883 pool = cmng->pools[cmng->last_pool_idx];
5886 /* ID out of range means no suitable pool in the container. */
5887 if (id > cmng->max_id || id < cmng->min_id)
5890 * Find the pool from the end of the container, since mostly counter
5891 * ID is sequence increasing, and the last pool should be the needed
5896 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5898 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5904 rte_spinlock_unlock(&cmng->pool_update_sl);
5909 * Resize a counter container.
5912 * Pointer to the Ethernet device structure.
5915 * 0 on success, otherwise negative errno value and rte_errno is set.
5918 flow_dv_container_resize(struct rte_eth_dev *dev)
5920 struct mlx5_priv *priv = dev->data->dev_private;
5921 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5922 void *old_pools = cmng->pools;
5923 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5924 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5925 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5932 memcpy(pools, old_pools, cmng->n *
5933 sizeof(struct mlx5_flow_counter_pool *));
5935 cmng->pools = pools;
5937 mlx5_free(old_pools);
5942 * Query a devx flow counter.
5945 * Pointer to the Ethernet device structure.
5946 * @param[in] counter
5947 * Index to the flow counter.
5949 * The statistics value of packets.
5951 * The statistics value of bytes.
5954 * 0 on success, otherwise a negative errno value and rte_errno is set.
5957 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5960 struct mlx5_priv *priv = dev->data->dev_private;
5961 struct mlx5_flow_counter_pool *pool = NULL;
5962 struct mlx5_flow_counter *cnt;
5965 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5967 if (priv->sh->cmng.counter_fallback)
5968 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5969 0, pkts, bytes, 0, NULL, NULL, 0);
5970 rte_spinlock_lock(&pool->sl);
5975 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5976 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5977 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5979 rte_spinlock_unlock(&pool->sl);
5984 * Create and initialize a new counter pool.
5987 * Pointer to the Ethernet device structure.
5989 * The devX counter handle.
5991 * Whether the pool is for counter that was allocated for aging.
5992 * @param[in/out] cont_cur
5993 * Pointer to the container pointer, it will be update in pool resize.
5996 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5998 static struct mlx5_flow_counter_pool *
5999 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6002 struct mlx5_priv *priv = dev->data->dev_private;
6003 struct mlx5_flow_counter_pool *pool;
6004 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6005 bool fallback = priv->sh->cmng.counter_fallback;
6006 uint32_t size = sizeof(*pool);
6008 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6009 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6010 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6016 pool->is_aged = !!age;
6017 pool->query_gen = 0;
6018 pool->min_dcs = dcs;
6019 rte_spinlock_init(&pool->sl);
6020 rte_spinlock_init(&pool->csl);
6021 TAILQ_INIT(&pool->counters[0]);
6022 TAILQ_INIT(&pool->counters[1]);
6023 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6024 rte_spinlock_lock(&cmng->pool_update_sl);
6025 pool->index = cmng->n_valid;
6026 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6028 rte_spinlock_unlock(&cmng->pool_update_sl);
6031 cmng->pools[pool->index] = pool;
6033 if (unlikely(fallback)) {
6034 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6036 if (base < cmng->min_id)
6037 cmng->min_id = base;
6038 if (base > cmng->max_id)
6039 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6040 cmng->last_pool_idx = pool->index;
6042 rte_spinlock_unlock(&cmng->pool_update_sl);
6047 * Prepare a new counter and/or a new counter pool.
6050 * Pointer to the Ethernet device structure.
6051 * @param[out] cnt_free
6052 * Where to put the pointer of a new counter.
6054 * Whether the pool is for counter that was allocated for aging.
6057 * The counter pool pointer and @p cnt_free is set on success,
6058 * NULL otherwise and rte_errno is set.
6060 static struct mlx5_flow_counter_pool *
6061 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6062 struct mlx5_flow_counter **cnt_free,
6065 struct mlx5_priv *priv = dev->data->dev_private;
6066 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6067 struct mlx5_flow_counter_pool *pool;
6068 struct mlx5_counters tmp_tq;
6069 struct mlx5_devx_obj *dcs = NULL;
6070 struct mlx5_flow_counter *cnt;
6071 enum mlx5_counter_type cnt_type =
6072 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6073 bool fallback = priv->sh->cmng.counter_fallback;
6077 /* bulk_bitmap must be 0 for single counter allocation. */
6078 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6081 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6083 pool = flow_dv_pool_create(dev, dcs, age);
6085 mlx5_devx_cmd_destroy(dcs);
6089 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6090 cnt = MLX5_POOL_GET_CNT(pool, i);
6092 cnt->dcs_when_free = dcs;
6096 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6098 rte_errno = ENODATA;
6101 pool = flow_dv_pool_create(dev, dcs, age);
6103 mlx5_devx_cmd_destroy(dcs);
6106 TAILQ_INIT(&tmp_tq);
6107 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6108 cnt = MLX5_POOL_GET_CNT(pool, i);
6110 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6112 rte_spinlock_lock(&cmng->csl[cnt_type]);
6113 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6114 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6115 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6116 (*cnt_free)->pool = pool;
6121 * Allocate a flow counter.
6124 * Pointer to the Ethernet device structure.
6126 * Whether the counter was allocated for aging.
6129 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6132 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6134 struct mlx5_priv *priv = dev->data->dev_private;
6135 struct mlx5_flow_counter_pool *pool = NULL;
6136 struct mlx5_flow_counter *cnt_free = NULL;
6137 bool fallback = priv->sh->cmng.counter_fallback;
6138 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6139 enum mlx5_counter_type cnt_type =
6140 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6143 if (!priv->sh->devx) {
6144 rte_errno = ENOTSUP;
6147 /* Get free counters from container. */
6148 rte_spinlock_lock(&cmng->csl[cnt_type]);
6149 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6151 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6152 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6153 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6155 pool = cnt_free->pool;
6157 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6158 /* Create a DV counter action only in the first time usage. */
6159 if (!cnt_free->action) {
6161 struct mlx5_devx_obj *dcs;
6165 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6166 dcs = pool->min_dcs;
6169 dcs = cnt_free->dcs_when_free;
6171 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6178 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6179 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6180 /* Update the counter reset values. */
6181 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6184 if (!fallback && !priv->sh->cmng.query_thread_on)
6185 /* Start the asynchronous batch query by the host thread. */
6186 mlx5_set_query_alarm(priv->sh);
6188 * When the count action isn't shared (by ID), shared_info field is
6189 * used for indirect action API's refcnt.
6190 * When the counter action is not shared neither by ID nor by indirect
6191 * action API, shared info must be 1.
6193 cnt_free->shared_info.refcnt = 1;
6197 cnt_free->pool = pool;
6199 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6200 rte_spinlock_lock(&cmng->csl[cnt_type]);
6201 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6202 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6208 * Get age param from counter index.
6211 * Pointer to the Ethernet device structure.
6212 * @param[in] counter
6213 * Index to the counter handler.
6216 * The aging parameter specified for the counter index.
6218 static struct mlx5_age_param*
6219 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6222 struct mlx5_flow_counter *cnt;
6223 struct mlx5_flow_counter_pool *pool = NULL;
6225 flow_dv_counter_get_by_idx(dev, counter, &pool);
6226 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6227 cnt = MLX5_POOL_GET_CNT(pool, counter);
6228 return MLX5_CNT_TO_AGE(cnt);
6232 * Remove a flow counter from aged counter list.
6235 * Pointer to the Ethernet device structure.
6236 * @param[in] counter
6237 * Index to the counter handler.
6239 * Pointer to the counter handler.
6242 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6243 uint32_t counter, struct mlx5_flow_counter *cnt)
6245 struct mlx5_age_info *age_info;
6246 struct mlx5_age_param *age_param;
6247 struct mlx5_priv *priv = dev->data->dev_private;
6248 uint16_t expected = AGE_CANDIDATE;
6250 age_info = GET_PORT_AGE_INFO(priv);
6251 age_param = flow_dv_counter_idx_get_age(dev, counter);
6252 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6253 AGE_FREE, false, __ATOMIC_RELAXED,
6254 __ATOMIC_RELAXED)) {
6256 * We need the lock even it is age timeout,
6257 * since counter may still in process.
6259 rte_spinlock_lock(&age_info->aged_sl);
6260 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6261 rte_spinlock_unlock(&age_info->aged_sl);
6262 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6267 * Release a flow counter.
6270 * Pointer to the Ethernet device structure.
6271 * @param[in] counter
6272 * Index to the counter handler.
6275 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6277 struct mlx5_priv *priv = dev->data->dev_private;
6278 struct mlx5_flow_counter_pool *pool = NULL;
6279 struct mlx5_flow_counter *cnt;
6280 enum mlx5_counter_type cnt_type;
6284 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6286 if (pool->is_aged) {
6287 flow_dv_counter_remove_from_age(dev, counter, cnt);
6290 * If the counter action is shared by indirect action API,
6291 * the atomic function reduces its references counter.
6292 * If after the reduction the action is still referenced, the
6293 * function returns here and does not release it.
6294 * When the counter action is not shared by
6295 * indirect action API, shared info is 1 before the reduction,
6296 * so this condition is failed and function doesn't return here.
6298 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6304 * Put the counter back to list to be updated in none fallback mode.
6305 * Currently, we are using two list alternately, while one is in query,
6306 * add the freed counter to the other list based on the pool query_gen
6307 * value. After query finishes, add counter the list to the global
6308 * container counter list. The list changes while query starts. In
6309 * this case, lock will not be needed as query callback and release
6310 * function both operate with the different list.
6312 if (!priv->sh->cmng.counter_fallback) {
6313 rte_spinlock_lock(&pool->csl);
6314 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6315 rte_spinlock_unlock(&pool->csl);
6317 cnt->dcs_when_free = cnt->dcs_when_active;
6318 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6319 MLX5_COUNTER_TYPE_ORIGIN;
6320 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6321 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6323 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6328 * Resize a meter id container.
6331 * Pointer to the Ethernet device structure.
6334 * 0 on success, otherwise negative errno value and rte_errno is set.
6337 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6339 struct mlx5_priv *priv = dev->data->dev_private;
6340 struct mlx5_aso_mtr_pools_mng *pools_mng =
6341 &priv->sh->mtrmng->pools_mng;
6342 void *old_pools = pools_mng->pools;
6343 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6344 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6345 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6352 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6357 memcpy(pools, old_pools, pools_mng->n *
6358 sizeof(struct mlx5_aso_mtr_pool *));
6359 pools_mng->n = resize;
6360 pools_mng->pools = pools;
6362 mlx5_free(old_pools);
6367 * Prepare a new meter and/or a new meter pool.
6370 * Pointer to the Ethernet device structure.
6371 * @param[out] mtr_free
6372 * Where to put the pointer of a new meter.g.
6375 * The meter pool pointer and @mtr_free is set on success,
6376 * NULL otherwise and rte_errno is set.
6378 static struct mlx5_aso_mtr_pool *
6379 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6381 struct mlx5_priv *priv = dev->data->dev_private;
6382 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6383 struct mlx5_aso_mtr_pool *pool = NULL;
6384 struct mlx5_devx_obj *dcs = NULL;
6386 uint32_t log_obj_size;
6388 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6389 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6390 priv->sh->cdev->pdn,
6393 rte_errno = ENODATA;
6396 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6399 claim_zero(mlx5_devx_cmd_destroy(dcs));
6402 pool->devx_obj = dcs;
6403 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6404 pool->index = pools_mng->n_valid;
6405 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6407 claim_zero(mlx5_devx_cmd_destroy(dcs));
6408 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6411 pools_mng->pools[pool->index] = pool;
6412 pools_mng->n_valid++;
6413 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6414 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6415 pool->mtrs[i].offset = i;
6416 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6418 pool->mtrs[0].offset = 0;
6419 *mtr_free = &pool->mtrs[0];
6424 * Release a flow meter into pool.
6427 * Pointer to the Ethernet device structure.
6428 * @param[in] mtr_idx
6429 * Index to aso flow meter.
6432 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6434 struct mlx5_priv *priv = dev->data->dev_private;
6435 struct mlx5_aso_mtr_pools_mng *pools_mng =
6436 &priv->sh->mtrmng->pools_mng;
6437 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6439 MLX5_ASSERT(aso_mtr);
6440 rte_spinlock_lock(&pools_mng->mtrsl);
6441 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6442 aso_mtr->state = ASO_METER_FREE;
6443 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6444 rte_spinlock_unlock(&pools_mng->mtrsl);
6448 * Allocate a aso flow meter.
6451 * Pointer to the Ethernet device structure.
6454 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6457 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6459 struct mlx5_priv *priv = dev->data->dev_private;
6460 struct mlx5_aso_mtr *mtr_free = NULL;
6461 struct mlx5_aso_mtr_pools_mng *pools_mng =
6462 &priv->sh->mtrmng->pools_mng;
6463 struct mlx5_aso_mtr_pool *pool;
6464 uint32_t mtr_idx = 0;
6466 if (!priv->sh->devx) {
6467 rte_errno = ENOTSUP;
6470 /* Allocate the flow meter memory. */
6471 /* Get free meters from management. */
6472 rte_spinlock_lock(&pools_mng->mtrsl);
6473 mtr_free = LIST_FIRST(&pools_mng->meters);
6475 LIST_REMOVE(mtr_free, next);
6476 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6477 rte_spinlock_unlock(&pools_mng->mtrsl);
6480 mtr_free->state = ASO_METER_WAIT;
6481 rte_spinlock_unlock(&pools_mng->mtrsl);
6482 pool = container_of(mtr_free,
6483 struct mlx5_aso_mtr_pool,
6484 mtrs[mtr_free->offset]);
6485 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6486 if (!mtr_free->fm.meter_action) {
6487 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6488 struct rte_flow_error error;
6491 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6492 mtr_free->fm.meter_action =
6493 mlx5_glue->dv_create_flow_action_aso
6494 (priv->sh->rx_domain,
6495 pool->devx_obj->obj,
6497 (1 << MLX5_FLOW_COLOR_GREEN),
6499 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6500 if (!mtr_free->fm.meter_action) {
6501 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6509 * Verify the @p attributes will be correctly understood by the NIC and store
6510 * them in the @p flow if everything is correct.
6513 * Pointer to dev struct.
6514 * @param[in] attributes
6515 * Pointer to flow attributes
6516 * @param[in] external
6517 * This flow rule is created by request external to PMD.
6519 * Pointer to error structure.
6522 * - 0 on success and non root table.
6523 * - 1 on success and root table.
6524 * - a negative errno value otherwise and rte_errno is set.
6527 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6528 const struct mlx5_flow_tunnel *tunnel,
6529 const struct rte_flow_attr *attributes,
6530 const struct flow_grp_info *grp_info,
6531 struct rte_flow_error *error)
6533 struct mlx5_priv *priv = dev->data->dev_private;
6534 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6537 #ifndef HAVE_MLX5DV_DR
6538 RTE_SET_USED(tunnel);
6539 RTE_SET_USED(grp_info);
6540 if (attributes->group)
6541 return rte_flow_error_set(error, ENOTSUP,
6542 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6544 "groups are not supported");
6548 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6553 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6555 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6556 attributes->priority > lowest_priority)
6557 return rte_flow_error_set(error, ENOTSUP,
6558 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6560 "priority out of range");
6561 if (attributes->transfer) {
6562 if (!priv->config.dv_esw_en)
6563 return rte_flow_error_set
6565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6566 "E-Switch dr is not supported");
6567 if (!(priv->representor || priv->master))
6568 return rte_flow_error_set
6569 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6570 NULL, "E-Switch configuration can only be"
6571 " done by a master or a representor device");
6572 if (attributes->egress)
6573 return rte_flow_error_set
6575 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6576 "egress is not supported");
6578 if (!(attributes->egress ^ attributes->ingress))
6579 return rte_flow_error_set(error, ENOTSUP,
6580 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6581 "must specify exactly one of "
6582 "ingress or egress");
6587 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6588 int64_t pattern_flags, uint64_t l3_flags,
6589 uint64_t l4_flags, uint64_t ip4_flag,
6590 struct rte_flow_error *error)
6592 if (mask->l3_ok && !(pattern_flags & l3_flags))
6593 return rte_flow_error_set(error, EINVAL,
6594 RTE_FLOW_ERROR_TYPE_ITEM,
6595 NULL, "missing L3 protocol");
6597 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6598 return rte_flow_error_set(error, EINVAL,
6599 RTE_FLOW_ERROR_TYPE_ITEM,
6600 NULL, "missing IPv4 protocol");
6602 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6603 return rte_flow_error_set(error, EINVAL,
6604 RTE_FLOW_ERROR_TYPE_ITEM,
6605 NULL, "missing L4 protocol");
6611 flow_dv_validate_item_integrity_post(const struct
6612 rte_flow_item *integrity_items[2],
6613 int64_t pattern_flags,
6614 struct rte_flow_error *error)
6616 const struct rte_flow_item_integrity *mask;
6619 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6620 mask = (typeof(mask))integrity_items[0]->mask;
6621 ret = validate_integrity_bits(mask, pattern_flags,
6622 MLX5_FLOW_LAYER_OUTER_L3,
6623 MLX5_FLOW_LAYER_OUTER_L4,
6624 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6629 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6630 mask = (typeof(mask))integrity_items[1]->mask;
6631 ret = validate_integrity_bits(mask, pattern_flags,
6632 MLX5_FLOW_LAYER_INNER_L3,
6633 MLX5_FLOW_LAYER_INNER_L4,
6634 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6643 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6644 const struct rte_flow_item *integrity_item,
6645 uint64_t pattern_flags, uint64_t *last_item,
6646 const struct rte_flow_item *integrity_items[2],
6647 struct rte_flow_error *error)
6649 struct mlx5_priv *priv = dev->data->dev_private;
6650 const struct rte_flow_item_integrity *mask = (typeof(mask))
6651 integrity_item->mask;
6652 const struct rte_flow_item_integrity *spec = (typeof(spec))
6653 integrity_item->spec;
6655 if (!priv->config.hca_attr.pkt_integrity_match)
6656 return rte_flow_error_set(error, ENOTSUP,
6657 RTE_FLOW_ERROR_TYPE_ITEM,
6659 "packet integrity integrity_item not supported");
6661 return rte_flow_error_set(error, ENOTSUP,
6662 RTE_FLOW_ERROR_TYPE_ITEM,
6664 "no spec for integrity item");
6666 mask = &rte_flow_item_integrity_mask;
6667 if (!mlx5_validate_integrity_item(mask))
6668 return rte_flow_error_set(error, ENOTSUP,
6669 RTE_FLOW_ERROR_TYPE_ITEM,
6671 "unsupported integrity filter");
6672 if (spec->level > 1) {
6673 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6674 return rte_flow_error_set
6676 RTE_FLOW_ERROR_TYPE_ITEM,
6677 NULL, "multiple inner integrity items not supported");
6678 integrity_items[1] = integrity_item;
6679 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6681 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6682 return rte_flow_error_set
6684 RTE_FLOW_ERROR_TYPE_ITEM,
6685 NULL, "multiple outer integrity items not supported");
6686 integrity_items[0] = integrity_item;
6687 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6693 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6694 const struct rte_flow_item *item,
6695 uint64_t item_flags,
6696 uint64_t *last_item,
6698 struct rte_flow_error *error)
6700 const struct rte_flow_item_flex *flow_spec = item->spec;
6701 const struct rte_flow_item_flex *flow_mask = item->mask;
6702 struct mlx5_flex_item *flex;
6705 return rte_flow_error_set(error, EINVAL,
6706 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6707 "flex flow item spec cannot be NULL");
6709 return rte_flow_error_set(error, EINVAL,
6710 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6711 "flex flow item mask cannot be NULL");
6713 return rte_flow_error_set(error, ENOTSUP,
6714 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6715 "flex flow item last not supported");
6716 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6717 return rte_flow_error_set(error, EINVAL,
6718 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6719 "invalid flex flow item handle");
6720 flex = (struct mlx5_flex_item *)flow_spec->handle;
6721 switch (flex->tunnel_mode) {
6722 case FLEX_TUNNEL_MODE_SINGLE:
6724 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6725 rte_flow_error_set(error, EINVAL,
6726 RTE_FLOW_ERROR_TYPE_ITEM,
6727 NULL, "multiple flex items not supported");
6729 case FLEX_TUNNEL_MODE_OUTER:
6731 rte_flow_error_set(error, EINVAL,
6732 RTE_FLOW_ERROR_TYPE_ITEM,
6733 NULL, "inner flex item was not configured");
6734 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6735 rte_flow_error_set(error, ENOTSUP,
6736 RTE_FLOW_ERROR_TYPE_ITEM,
6737 NULL, "multiple flex items not supported");
6739 case FLEX_TUNNEL_MODE_INNER:
6741 rte_flow_error_set(error, EINVAL,
6742 RTE_FLOW_ERROR_TYPE_ITEM,
6743 NULL, "outer flex item was not configured");
6744 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6745 rte_flow_error_set(error, EINVAL,
6746 RTE_FLOW_ERROR_TYPE_ITEM,
6747 NULL, "multiple flex items not supported");
6749 case FLEX_TUNNEL_MODE_MULTI:
6750 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6751 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6752 rte_flow_error_set(error, EINVAL,
6753 RTE_FLOW_ERROR_TYPE_ITEM,
6754 NULL, "multiple flex items not supported");
6757 case FLEX_TUNNEL_MODE_TUNNEL:
6758 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6759 rte_flow_error_set(error, EINVAL,
6760 RTE_FLOW_ERROR_TYPE_ITEM,
6761 NULL, "multiple flex tunnel items not supported");
6764 rte_flow_error_set(error, EINVAL,
6765 RTE_FLOW_ERROR_TYPE_ITEM,
6766 NULL, "invalid flex item configuration");
6768 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6769 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6770 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6775 * Internal validation function. For validating both actions and items.
6778 * Pointer to the rte_eth_dev structure.
6780 * Pointer to the flow attributes.
6782 * Pointer to the list of items.
6783 * @param[in] actions
6784 * Pointer to the list of actions.
6785 * @param[in] external
6786 * This flow rule is created by request external to PMD.
6787 * @param[in] hairpin
6788 * Number of hairpin TX actions, 0 means classic flow.
6790 * Pointer to the error structure.
6793 * 0 on success, a negative errno value otherwise and rte_errno is set.
6796 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6797 const struct rte_flow_item items[],
6798 const struct rte_flow_action actions[],
6799 bool external, int hairpin, struct rte_flow_error *error)
6802 uint64_t action_flags = 0;
6803 uint64_t item_flags = 0;
6804 uint64_t last_item = 0;
6805 uint8_t next_protocol = 0xff;
6806 uint16_t ether_type = 0;
6808 uint8_t item_ipv6_proto = 0;
6809 int fdb_mirror_limit = 0;
6810 int modify_after_mirror = 0;
6811 const struct rte_flow_item *geneve_item = NULL;
6812 const struct rte_flow_item *gre_item = NULL;
6813 const struct rte_flow_item *gtp_item = NULL;
6814 const struct rte_flow_action_raw_decap *decap;
6815 const struct rte_flow_action_raw_encap *encap;
6816 const struct rte_flow_action_rss *rss = NULL;
6817 const struct rte_flow_action_rss *sample_rss = NULL;
6818 const struct rte_flow_action_count *sample_count = NULL;
6819 const struct rte_flow_item_tcp nic_tcp_mask = {
6822 .src_port = RTE_BE16(UINT16_MAX),
6823 .dst_port = RTE_BE16(UINT16_MAX),
6826 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6829 "\xff\xff\xff\xff\xff\xff\xff\xff"
6830 "\xff\xff\xff\xff\xff\xff\xff\xff",
6832 "\xff\xff\xff\xff\xff\xff\xff\xff"
6833 "\xff\xff\xff\xff\xff\xff\xff\xff",
6834 .vtc_flow = RTE_BE32(0xffffffff),
6840 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6844 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6848 .dummy[0] = 0xffffffff,
6851 struct mlx5_priv *priv = dev->data->dev_private;
6852 struct mlx5_dev_config *dev_conf = &priv->config;
6853 uint16_t queue_index = 0xFFFF;
6854 const struct rte_flow_item_vlan *vlan_m = NULL;
6855 uint32_t rw_act_num = 0;
6857 const struct mlx5_flow_tunnel *tunnel;
6858 enum mlx5_tof_rule_type tof_rule_type;
6859 struct flow_grp_info grp_info = {
6860 .external = !!external,
6861 .transfer = !!attr->transfer,
6862 .fdb_def_rule = !!priv->fdb_def_rule,
6863 .std_tbl_fix = true,
6865 const struct rte_eth_hairpin_conf *conf;
6866 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6867 const struct rte_flow_item *port_id_item = NULL;
6868 bool def_policy = false;
6869 uint16_t udp_dport = 0;
6873 tunnel = is_tunnel_offload_active(dev) ?
6874 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6876 if (!priv->config.dv_flow_en)
6877 return rte_flow_error_set
6879 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6880 NULL, "tunnel offload requires DV flow interface");
6881 if (priv->representor)
6882 return rte_flow_error_set
6884 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6885 NULL, "decap not supported for VF representor");
6886 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6887 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6888 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6889 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6890 MLX5_FLOW_ACTION_DECAP;
6891 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6892 (dev, attr, tunnel, tof_rule_type);
6894 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6897 is_root = (uint64_t)ret;
6898 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6899 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6900 int type = items->type;
6902 if (!mlx5_flow_os_item_supported(type))
6903 return rte_flow_error_set(error, ENOTSUP,
6904 RTE_FLOW_ERROR_TYPE_ITEM,
6905 NULL, "item not supported");
6907 case RTE_FLOW_ITEM_TYPE_VOID:
6909 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6910 ret = flow_dv_validate_item_port_id
6911 (dev, items, attr, item_flags, error);
6914 last_item = MLX5_FLOW_ITEM_PORT_ID;
6915 port_id_item = items;
6917 case RTE_FLOW_ITEM_TYPE_ETH:
6918 ret = mlx5_flow_validate_item_eth(items, item_flags,
6922 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6923 MLX5_FLOW_LAYER_OUTER_L2;
6924 if (items->mask != NULL && items->spec != NULL) {
6926 ((const struct rte_flow_item_eth *)
6929 ((const struct rte_flow_item_eth *)
6931 ether_type = rte_be_to_cpu_16(ether_type);
6936 case RTE_FLOW_ITEM_TYPE_VLAN:
6937 ret = flow_dv_validate_item_vlan(items, item_flags,
6941 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6942 MLX5_FLOW_LAYER_OUTER_VLAN;
6943 if (items->mask != NULL && items->spec != NULL) {
6945 ((const struct rte_flow_item_vlan *)
6946 items->spec)->inner_type;
6948 ((const struct rte_flow_item_vlan *)
6949 items->mask)->inner_type;
6950 ether_type = rte_be_to_cpu_16(ether_type);
6954 /* Store outer VLAN mask for of_push_vlan action. */
6956 vlan_m = items->mask;
6958 case RTE_FLOW_ITEM_TYPE_IPV4:
6959 mlx5_flow_tunnel_ip_check(items, next_protocol,
6960 &item_flags, &tunnel);
6961 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6962 last_item, ether_type,
6966 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6967 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6968 if (items->mask != NULL &&
6969 ((const struct rte_flow_item_ipv4 *)
6970 items->mask)->hdr.next_proto_id) {
6972 ((const struct rte_flow_item_ipv4 *)
6973 (items->spec))->hdr.next_proto_id;
6975 ((const struct rte_flow_item_ipv4 *)
6976 (items->mask))->hdr.next_proto_id;
6978 /* Reset for inner layer. */
6979 next_protocol = 0xff;
6982 case RTE_FLOW_ITEM_TYPE_IPV6:
6983 mlx5_flow_tunnel_ip_check(items, next_protocol,
6984 &item_flags, &tunnel);
6985 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6992 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6993 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6994 if (items->mask != NULL &&
6995 ((const struct rte_flow_item_ipv6 *)
6996 items->mask)->hdr.proto) {
6998 ((const struct rte_flow_item_ipv6 *)
6999 items->spec)->hdr.proto;
7001 ((const struct rte_flow_item_ipv6 *)
7002 items->spec)->hdr.proto;
7004 ((const struct rte_flow_item_ipv6 *)
7005 items->mask)->hdr.proto;
7007 /* Reset for inner layer. */
7008 next_protocol = 0xff;
7011 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7012 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7017 last_item = tunnel ?
7018 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7019 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7020 if (items->mask != NULL &&
7021 ((const struct rte_flow_item_ipv6_frag_ext *)
7022 items->mask)->hdr.next_header) {
7024 ((const struct rte_flow_item_ipv6_frag_ext *)
7025 items->spec)->hdr.next_header;
7027 ((const struct rte_flow_item_ipv6_frag_ext *)
7028 items->mask)->hdr.next_header;
7030 /* Reset for inner layer. */
7031 next_protocol = 0xff;
7034 case RTE_FLOW_ITEM_TYPE_TCP:
7035 ret = mlx5_flow_validate_item_tcp
7042 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7043 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7045 case RTE_FLOW_ITEM_TYPE_UDP:
7046 ret = mlx5_flow_validate_item_udp(items, item_flags,
7049 const struct rte_flow_item_udp *spec = items->spec;
7050 const struct rte_flow_item_udp *mask = items->mask;
7052 mask = &rte_flow_item_udp_mask;
7054 udp_dport = rte_be_to_cpu_16
7055 (spec->hdr.dst_port &
7056 mask->hdr.dst_port);
7059 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7060 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7062 case RTE_FLOW_ITEM_TYPE_GRE:
7063 ret = mlx5_flow_validate_item_gre(items, item_flags,
7064 next_protocol, error);
7068 last_item = MLX5_FLOW_LAYER_GRE;
7070 case RTE_FLOW_ITEM_TYPE_NVGRE:
7071 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7076 last_item = MLX5_FLOW_LAYER_NVGRE;
7078 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7079 ret = mlx5_flow_validate_item_gre_key
7080 (items, item_flags, gre_item, error);
7083 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7085 case RTE_FLOW_ITEM_TYPE_VXLAN:
7086 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7091 last_item = MLX5_FLOW_LAYER_VXLAN;
7093 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7094 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7099 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7101 case RTE_FLOW_ITEM_TYPE_GENEVE:
7102 ret = mlx5_flow_validate_item_geneve(items,
7107 geneve_item = items;
7108 last_item = MLX5_FLOW_LAYER_GENEVE;
7110 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7111 ret = mlx5_flow_validate_item_geneve_opt(items,
7118 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7120 case RTE_FLOW_ITEM_TYPE_MPLS:
7121 ret = mlx5_flow_validate_item_mpls(dev, items,
7126 last_item = MLX5_FLOW_LAYER_MPLS;
7129 case RTE_FLOW_ITEM_TYPE_MARK:
7130 ret = flow_dv_validate_item_mark(dev, items, attr,
7134 last_item = MLX5_FLOW_ITEM_MARK;
7136 case RTE_FLOW_ITEM_TYPE_META:
7137 ret = flow_dv_validate_item_meta(dev, items, attr,
7141 last_item = MLX5_FLOW_ITEM_METADATA;
7143 case RTE_FLOW_ITEM_TYPE_ICMP:
7144 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7149 last_item = MLX5_FLOW_LAYER_ICMP;
7151 case RTE_FLOW_ITEM_TYPE_ICMP6:
7152 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7157 item_ipv6_proto = IPPROTO_ICMPV6;
7158 last_item = MLX5_FLOW_LAYER_ICMP6;
7160 case RTE_FLOW_ITEM_TYPE_TAG:
7161 ret = flow_dv_validate_item_tag(dev, items,
7165 last_item = MLX5_FLOW_ITEM_TAG;
7167 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7168 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7170 case RTE_FLOW_ITEM_TYPE_GTP:
7171 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7176 last_item = MLX5_FLOW_LAYER_GTP;
7178 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7179 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7184 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7186 case RTE_FLOW_ITEM_TYPE_ECPRI:
7187 /* Capacity will be checked in the translate stage. */
7188 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7195 last_item = MLX5_FLOW_LAYER_ECPRI;
7197 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7198 ret = flow_dv_validate_item_integrity(dev, items,
7206 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7207 ret = flow_dv_validate_item_aso_ct(dev, items,
7208 &item_flags, error);
7212 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7213 /* tunnel offload item was processed before
7214 * list it here as a supported type
7217 case RTE_FLOW_ITEM_TYPE_FLEX:
7218 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7220 tunnel != 0, error);
7225 return rte_flow_error_set(error, ENOTSUP,
7226 RTE_FLOW_ERROR_TYPE_ITEM,
7227 NULL, "item not supported");
7229 item_flags |= last_item;
7231 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7232 ret = flow_dv_validate_item_integrity_post(integrity_items,
7237 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7238 int type = actions->type;
7239 bool shared_count = false;
7241 if (!mlx5_flow_os_action_supported(type))
7242 return rte_flow_error_set(error, ENOTSUP,
7243 RTE_FLOW_ERROR_TYPE_ACTION,
7245 "action not supported");
7246 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7247 return rte_flow_error_set(error, ENOTSUP,
7248 RTE_FLOW_ERROR_TYPE_ACTION,
7249 actions, "too many actions");
7251 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7252 return rte_flow_error_set(error, ENOTSUP,
7253 RTE_FLOW_ERROR_TYPE_ACTION,
7254 NULL, "meter action with policy "
7255 "must be the last action");
7257 case RTE_FLOW_ACTION_TYPE_VOID:
7259 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7260 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7261 ret = flow_dv_validate_action_port_id(dev,
7268 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7271 case RTE_FLOW_ACTION_TYPE_FLAG:
7272 ret = flow_dv_validate_action_flag(dev, action_flags,
7276 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7277 /* Count all modify-header actions as one. */
7278 if (!(action_flags &
7279 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7281 action_flags |= MLX5_FLOW_ACTION_FLAG |
7282 MLX5_FLOW_ACTION_MARK_EXT;
7283 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7284 modify_after_mirror = 1;
7287 action_flags |= MLX5_FLOW_ACTION_FLAG;
7290 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7292 case RTE_FLOW_ACTION_TYPE_MARK:
7293 ret = flow_dv_validate_action_mark(dev, actions,
7298 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7299 /* Count all modify-header actions as one. */
7300 if (!(action_flags &
7301 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7303 action_flags |= MLX5_FLOW_ACTION_MARK |
7304 MLX5_FLOW_ACTION_MARK_EXT;
7305 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7306 modify_after_mirror = 1;
7308 action_flags |= MLX5_FLOW_ACTION_MARK;
7311 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7313 case RTE_FLOW_ACTION_TYPE_SET_META:
7314 ret = flow_dv_validate_action_set_meta(dev, actions,
7319 /* Count all modify-header actions as one action. */
7320 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7322 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7323 modify_after_mirror = 1;
7324 action_flags |= MLX5_FLOW_ACTION_SET_META;
7325 rw_act_num += MLX5_ACT_NUM_SET_META;
7327 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7328 ret = flow_dv_validate_action_set_tag(dev, actions,
7333 /* Count all modify-header actions as one action. */
7334 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7336 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7337 modify_after_mirror = 1;
7338 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7339 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7341 case RTE_FLOW_ACTION_TYPE_DROP:
7342 ret = mlx5_flow_validate_action_drop(action_flags,
7346 action_flags |= MLX5_FLOW_ACTION_DROP;
7349 case RTE_FLOW_ACTION_TYPE_QUEUE:
7350 ret = mlx5_flow_validate_action_queue(actions,
7355 queue_index = ((const struct rte_flow_action_queue *)
7356 (actions->conf))->index;
7357 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7360 case RTE_FLOW_ACTION_TYPE_RSS:
7361 rss = actions->conf;
7362 ret = mlx5_flow_validate_action_rss(actions,
7368 if (rss && sample_rss &&
7369 (sample_rss->level != rss->level ||
7370 sample_rss->types != rss->types))
7371 return rte_flow_error_set(error, ENOTSUP,
7372 RTE_FLOW_ERROR_TYPE_ACTION,
7374 "Can't use the different RSS types "
7375 "or level in the same flow");
7376 if (rss != NULL && rss->queue_num)
7377 queue_index = rss->queue[0];
7378 action_flags |= MLX5_FLOW_ACTION_RSS;
7381 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7383 mlx5_flow_validate_action_default_miss(action_flags,
7387 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7390 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7391 shared_count = true;
7393 case RTE_FLOW_ACTION_TYPE_COUNT:
7394 ret = flow_dv_validate_action_count(dev, shared_count,
7399 action_flags |= MLX5_FLOW_ACTION_COUNT;
7402 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7403 if (flow_dv_validate_action_pop_vlan(dev,
7409 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7410 modify_after_mirror = 1;
7411 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7414 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7415 ret = flow_dv_validate_action_push_vlan(dev,
7422 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7423 modify_after_mirror = 1;
7424 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7427 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7428 ret = flow_dv_validate_action_set_vlan_pcp
7429 (action_flags, actions, error);
7432 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7433 modify_after_mirror = 1;
7434 /* Count PCP with push_vlan command. */
7435 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7437 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7438 ret = flow_dv_validate_action_set_vlan_vid
7439 (item_flags, action_flags,
7443 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7444 modify_after_mirror = 1;
7445 /* Count VID with push_vlan command. */
7446 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7447 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7449 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7450 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7451 ret = flow_dv_validate_action_l2_encap(dev,
7457 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7460 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7461 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7462 ret = flow_dv_validate_action_decap(dev, action_flags,
7463 actions, item_flags,
7467 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7468 modify_after_mirror = 1;
7469 action_flags |= MLX5_FLOW_ACTION_DECAP;
7472 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7473 ret = flow_dv_validate_action_raw_encap_decap
7474 (dev, NULL, actions->conf, attr, &action_flags,
7475 &actions_n, actions, item_flags, error);
7479 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7480 decap = actions->conf;
7481 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7483 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7487 encap = actions->conf;
7489 ret = flow_dv_validate_action_raw_encap_decap
7491 decap ? decap : &empty_decap, encap,
7492 attr, &action_flags, &actions_n,
7493 actions, item_flags, error);
7496 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7497 (action_flags & MLX5_FLOW_ACTION_DECAP))
7498 modify_after_mirror = 1;
7500 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7501 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7502 ret = flow_dv_validate_action_modify_mac(action_flags,
7508 /* Count all modify-header actions as one action. */
7509 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7511 action_flags |= actions->type ==
7512 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7513 MLX5_FLOW_ACTION_SET_MAC_SRC :
7514 MLX5_FLOW_ACTION_SET_MAC_DST;
7515 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7516 modify_after_mirror = 1;
7518 * Even if the source and destination MAC addresses have
7519 * overlap in the header with 4B alignment, the convert
7520 * function will handle them separately and 4 SW actions
7521 * will be created. And 2 actions will be added each
7522 * time no matter how many bytes of address will be set.
7524 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7526 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7527 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7528 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7534 /* Count all modify-header actions as one action. */
7535 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7537 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7538 modify_after_mirror = 1;
7539 action_flags |= actions->type ==
7540 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7541 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7542 MLX5_FLOW_ACTION_SET_IPV4_DST;
7543 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7545 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7546 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7547 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7553 if (item_ipv6_proto == IPPROTO_ICMPV6)
7554 return rte_flow_error_set(error, ENOTSUP,
7555 RTE_FLOW_ERROR_TYPE_ACTION,
7557 "Can't change header "
7558 "with ICMPv6 proto");
7559 /* Count all modify-header actions as one action. */
7560 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7562 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7563 modify_after_mirror = 1;
7564 action_flags |= actions->type ==
7565 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7566 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7567 MLX5_FLOW_ACTION_SET_IPV6_DST;
7568 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7570 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7571 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7572 ret = flow_dv_validate_action_modify_tp(action_flags,
7578 /* Count all modify-header actions as one action. */
7579 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7581 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7582 modify_after_mirror = 1;
7583 action_flags |= actions->type ==
7584 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7585 MLX5_FLOW_ACTION_SET_TP_SRC :
7586 MLX5_FLOW_ACTION_SET_TP_DST;
7587 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7589 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7590 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7591 ret = flow_dv_validate_action_modify_ttl(action_flags,
7597 /* Count all modify-header actions as one action. */
7598 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7600 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7601 modify_after_mirror = 1;
7602 action_flags |= actions->type ==
7603 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7604 MLX5_FLOW_ACTION_SET_TTL :
7605 MLX5_FLOW_ACTION_DEC_TTL;
7606 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7608 case RTE_FLOW_ACTION_TYPE_JUMP:
7609 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7615 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7617 return rte_flow_error_set(error, EINVAL,
7618 RTE_FLOW_ERROR_TYPE_ACTION,
7620 "sample and jump action combination is not supported");
7622 action_flags |= MLX5_FLOW_ACTION_JUMP;
7624 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7625 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7626 ret = flow_dv_validate_action_modify_tcp_seq
7633 /* Count all modify-header actions as one action. */
7634 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7636 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7637 modify_after_mirror = 1;
7638 action_flags |= actions->type ==
7639 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7640 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7641 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7642 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7644 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7645 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7646 ret = flow_dv_validate_action_modify_tcp_ack
7653 /* Count all modify-header actions as one action. */
7654 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7656 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7657 modify_after_mirror = 1;
7658 action_flags |= actions->type ==
7659 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7660 MLX5_FLOW_ACTION_INC_TCP_ACK :
7661 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7662 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7664 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7666 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7667 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7668 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7670 case RTE_FLOW_ACTION_TYPE_METER:
7671 ret = mlx5_flow_validate_action_meter(dev,
7679 action_flags |= MLX5_FLOW_ACTION_METER;
7682 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7684 /* Meter action will add one more TAG action. */
7685 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7687 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7688 if (!attr->transfer && !attr->group)
7689 return rte_flow_error_set(error, ENOTSUP,
7690 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7692 "Shared ASO age action is not supported for group 0");
7693 if (action_flags & MLX5_FLOW_ACTION_AGE)
7694 return rte_flow_error_set
7696 RTE_FLOW_ERROR_TYPE_ACTION,
7698 "duplicate age actions set");
7699 action_flags |= MLX5_FLOW_ACTION_AGE;
7702 case RTE_FLOW_ACTION_TYPE_AGE:
7703 ret = flow_dv_validate_action_age(action_flags,
7709 * Validate the regular AGE action (using counter)
7710 * mutual exclusion with share counter actions.
7712 if (!priv->sh->flow_hit_aso_en) {
7714 return rte_flow_error_set
7716 RTE_FLOW_ERROR_TYPE_ACTION,
7718 "old age and shared count combination is not supported");
7720 return rte_flow_error_set
7722 RTE_FLOW_ERROR_TYPE_ACTION,
7724 "old age action and count must be in the same sub flow");
7726 action_flags |= MLX5_FLOW_ACTION_AGE;
7729 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7730 ret = flow_dv_validate_action_modify_ipv4_dscp
7737 /* Count all modify-header actions as one action. */
7738 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7740 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7741 modify_after_mirror = 1;
7742 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7743 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7745 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7746 ret = flow_dv_validate_action_modify_ipv6_dscp
7753 /* Count all modify-header actions as one action. */
7754 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7756 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7757 modify_after_mirror = 1;
7758 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7759 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7761 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7762 ret = flow_dv_validate_action_sample(&action_flags,
7771 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7774 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7775 ret = flow_dv_validate_action_modify_field(dev,
7782 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7783 modify_after_mirror = 1;
7784 /* Count all modify-header actions as one action. */
7785 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7787 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7790 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7791 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7796 action_flags |= MLX5_FLOW_ACTION_CT;
7798 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7799 /* tunnel offload action was processed before
7800 * list it here as a supported type
7804 return rte_flow_error_set(error, ENOTSUP,
7805 RTE_FLOW_ERROR_TYPE_ACTION,
7807 "action not supported");
7811 * Validate actions in flow rules
7812 * - Explicit decap action is prohibited by the tunnel offload API.
7813 * - Drop action in tunnel steer rule is prohibited by the API.
7814 * - Application cannot use MARK action because it's value can mask
7815 * tunnel default miss nitification.
7816 * - JUMP in tunnel match rule has no support in current PMD
7818 * - TAG & META are reserved for future uses.
7820 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7821 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7822 MLX5_FLOW_ACTION_MARK |
7823 MLX5_FLOW_ACTION_SET_TAG |
7824 MLX5_FLOW_ACTION_SET_META |
7825 MLX5_FLOW_ACTION_DROP;
7827 if (action_flags & bad_actions_mask)
7828 return rte_flow_error_set
7830 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7831 "Invalid RTE action in tunnel "
7833 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7834 return rte_flow_error_set
7836 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7837 "tunnel set decap rule must terminate "
7840 return rte_flow_error_set
7842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7843 "tunnel flows for ingress traffic only");
7845 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7846 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7847 MLX5_FLOW_ACTION_MARK |
7848 MLX5_FLOW_ACTION_SET_TAG |
7849 MLX5_FLOW_ACTION_SET_META;
7851 if (action_flags & bad_actions_mask)
7852 return rte_flow_error_set
7854 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7855 "Invalid RTE action in tunnel "
7859 * Validate the drop action mutual exclusion with other actions.
7860 * Drop action is mutually-exclusive with any other action, except for
7862 * Drop action compatibility with tunnel offload was already validated.
7864 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7865 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7866 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7867 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7868 return rte_flow_error_set(error, EINVAL,
7869 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7870 "Drop action is mutually-exclusive "
7871 "with any other action, except for "
7873 /* Eswitch has few restrictions on using items and actions */
7874 if (attr->transfer) {
7875 if (!mlx5_flow_ext_mreg_supported(dev) &&
7876 action_flags & MLX5_FLOW_ACTION_FLAG)
7877 return rte_flow_error_set(error, ENOTSUP,
7878 RTE_FLOW_ERROR_TYPE_ACTION,
7880 "unsupported action FLAG");
7881 if (!mlx5_flow_ext_mreg_supported(dev) &&
7882 action_flags & MLX5_FLOW_ACTION_MARK)
7883 return rte_flow_error_set(error, ENOTSUP,
7884 RTE_FLOW_ERROR_TYPE_ACTION,
7886 "unsupported action MARK");
7887 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7888 return rte_flow_error_set(error, ENOTSUP,
7889 RTE_FLOW_ERROR_TYPE_ACTION,
7891 "unsupported action QUEUE");
7892 if (action_flags & MLX5_FLOW_ACTION_RSS)
7893 return rte_flow_error_set(error, ENOTSUP,
7894 RTE_FLOW_ERROR_TYPE_ACTION,
7896 "unsupported action RSS");
7897 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7898 return rte_flow_error_set(error, EINVAL,
7899 RTE_FLOW_ERROR_TYPE_ACTION,
7901 "no fate action is found");
7903 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7904 return rte_flow_error_set(error, EINVAL,
7905 RTE_FLOW_ERROR_TYPE_ACTION,
7907 "no fate action is found");
7910 * Continue validation for Xcap and VLAN actions.
7911 * If hairpin is working in explicit TX rule mode, there is no actions
7912 * splitting and the validation of hairpin ingress flow should be the
7913 * same as other standard flows.
7915 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7916 MLX5_FLOW_VLAN_ACTIONS)) &&
7917 (queue_index == 0xFFFF ||
7918 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7919 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7920 conf->tx_explicit != 0))) {
7921 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7922 MLX5_FLOW_XCAP_ACTIONS)
7923 return rte_flow_error_set(error, ENOTSUP,
7924 RTE_FLOW_ERROR_TYPE_ACTION,
7925 NULL, "encap and decap "
7926 "combination aren't supported");
7927 if (!attr->transfer && attr->ingress) {
7928 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7929 return rte_flow_error_set
7931 RTE_FLOW_ERROR_TYPE_ACTION,
7932 NULL, "encap is not supported"
7933 " for ingress traffic");
7934 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7935 return rte_flow_error_set
7937 RTE_FLOW_ERROR_TYPE_ACTION,
7938 NULL, "push VLAN action not "
7939 "supported for ingress");
7940 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7941 MLX5_FLOW_VLAN_ACTIONS)
7942 return rte_flow_error_set
7944 RTE_FLOW_ERROR_TYPE_ACTION,
7945 NULL, "no support for "
7946 "multiple VLAN actions");
7949 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7950 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7951 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7953 return rte_flow_error_set
7955 RTE_FLOW_ERROR_TYPE_ACTION,
7956 NULL, "fate action not supported for "
7957 "meter with policy");
7959 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7960 return rte_flow_error_set
7962 RTE_FLOW_ERROR_TYPE_ACTION,
7963 NULL, "modify header action in egress "
7964 "cannot be done before meter action");
7965 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7966 return rte_flow_error_set
7968 RTE_FLOW_ERROR_TYPE_ACTION,
7969 NULL, "encap action in egress "
7970 "cannot be done before meter action");
7971 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7972 return rte_flow_error_set
7974 RTE_FLOW_ERROR_TYPE_ACTION,
7975 NULL, "push vlan action in egress "
7976 "cannot be done before meter action");
7980 * Hairpin flow will add one more TAG action in TX implicit mode.
7981 * In TX explicit mode, there will be no hairpin flow ID.
7984 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7985 /* extra metadata enabled: one more TAG action will be add. */
7986 if (dev_conf->dv_flow_en &&
7987 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7988 mlx5_flow_ext_mreg_supported(dev))
7989 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7991 flow_dv_modify_hdr_action_max(dev, is_root)) {
7992 return rte_flow_error_set(error, ENOTSUP,
7993 RTE_FLOW_ERROR_TYPE_ACTION,
7994 NULL, "too many header modify"
7995 " actions to support");
7997 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7998 if (fdb_mirror_limit && modify_after_mirror)
7999 return rte_flow_error_set(error, EINVAL,
8000 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8001 "sample before modify action is not supported");
8006 * Internal preparation function. Allocates the DV flow size,
8007 * this size is constant.
8010 * Pointer to the rte_eth_dev structure.
8012 * Pointer to the flow attributes.
8014 * Pointer to the list of items.
8015 * @param[in] actions
8016 * Pointer to the list of actions.
8018 * Pointer to the error structure.
8021 * Pointer to mlx5_flow object on success,
8022 * otherwise NULL and rte_errno is set.
8024 static struct mlx5_flow *
8025 flow_dv_prepare(struct rte_eth_dev *dev,
8026 const struct rte_flow_attr *attr __rte_unused,
8027 const struct rte_flow_item items[] __rte_unused,
8028 const struct rte_flow_action actions[] __rte_unused,
8029 struct rte_flow_error *error)
8031 uint32_t handle_idx = 0;
8032 struct mlx5_flow *dev_flow;
8033 struct mlx5_flow_handle *dev_handle;
8034 struct mlx5_priv *priv = dev->data->dev_private;
8035 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8038 wks->skip_matcher_reg = 0;
8040 wks->final_policy = NULL;
8041 /* In case of corrupting the memory. */
8042 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8043 rte_flow_error_set(error, ENOSPC,
8044 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8045 "not free temporary device flow");
8048 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8051 rte_flow_error_set(error, ENOMEM,
8052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8053 "not enough memory to create flow handle");
8056 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8057 dev_flow = &wks->flows[wks->flow_idx++];
8058 memset(dev_flow, 0, sizeof(*dev_flow));
8059 dev_flow->handle = dev_handle;
8060 dev_flow->handle_idx = handle_idx;
8061 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8062 dev_flow->ingress = attr->ingress;
8063 dev_flow->dv.transfer = attr->transfer;
8067 #ifdef RTE_LIBRTE_MLX5_DEBUG
8069 * Sanity check for match mask and value. Similar to check_valid_spec() in
8070 * kernel driver. If unmasked bit is present in value, it returns failure.
8073 * pointer to match mask buffer.
8074 * @param match_value
8075 * pointer to match value buffer.
8078 * 0 if valid, -EINVAL otherwise.
8081 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8083 uint8_t *m = match_mask;
8084 uint8_t *v = match_value;
8087 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8090 "match_value differs from match_criteria"
8091 " %p[%u] != %p[%u]",
8092 match_value, i, match_mask, i);
8101 * Add match of ip_version.
8105 * @param[in] headers_v
8106 * Values header pointer.
8107 * @param[in] headers_m
8108 * Masks header pointer.
8109 * @param[in] ip_version
8110 * The IP version to set.
8113 flow_dv_set_match_ip_version(uint32_t group,
8119 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8121 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8123 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8124 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8125 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8129 * Add Ethernet item to matcher and to the value.
8131 * @param[in, out] matcher
8133 * @param[in, out] key
8134 * Flow matcher value.
8136 * Flow pattern to translate.
8138 * Item is inner pattern.
8141 flow_dv_translate_item_eth(void *matcher, void *key,
8142 const struct rte_flow_item *item, int inner,
8145 const struct rte_flow_item_eth *eth_m = item->mask;
8146 const struct rte_flow_item_eth *eth_v = item->spec;
8147 const struct rte_flow_item_eth nic_mask = {
8148 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8149 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8150 .type = RTE_BE16(0xffff),
8163 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8165 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8167 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8169 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8171 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8172 ð_m->dst, sizeof(eth_m->dst));
8173 /* The value must be in the range of the mask. */
8174 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8175 for (i = 0; i < sizeof(eth_m->dst); ++i)
8176 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8177 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8178 ð_m->src, sizeof(eth_m->src));
8179 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8180 /* The value must be in the range of the mask. */
8181 for (i = 0; i < sizeof(eth_m->dst); ++i)
8182 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8184 * HW supports match on one Ethertype, the Ethertype following the last
8185 * VLAN tag of the packet (see PRM).
8186 * Set match on ethertype only if ETH header is not followed by VLAN.
8187 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8188 * ethertype, and use ip_version field instead.
8189 * eCPRI over Ether layer will use type value 0xAEFE.
8191 if (eth_m->type == 0xFFFF) {
8192 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8193 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8194 switch (eth_v->type) {
8195 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8196 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8198 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8199 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8200 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8202 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8203 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8205 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8206 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8212 if (eth_m->has_vlan) {
8213 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8214 if (eth_v->has_vlan) {
8216 * Here, when also has_more_vlan field in VLAN item is
8217 * not set, only single-tagged packets will be matched.
8219 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8223 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8224 rte_be_to_cpu_16(eth_m->type));
8225 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8226 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8230 * Add VLAN item to matcher and to the value.
8232 * @param[in, out] dev_flow
8234 * @param[in, out] matcher
8236 * @param[in, out] key
8237 * Flow matcher value.
8239 * Flow pattern to translate.
8241 * Item is inner pattern.
8244 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8245 void *matcher, void *key,
8246 const struct rte_flow_item *item,
8247 int inner, uint32_t group)
8249 const struct rte_flow_item_vlan *vlan_m = item->mask;
8250 const struct rte_flow_item_vlan *vlan_v = item->spec;
8257 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8259 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8261 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8263 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8265 * This is workaround, masks are not supported,
8266 * and pre-validated.
8269 dev_flow->handle->vf_vlan.tag =
8270 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8273 * When VLAN item exists in flow, mark packet as tagged,
8274 * even if TCI is not specified.
8276 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8277 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8278 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8283 vlan_m = &rte_flow_item_vlan_mask;
8284 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8285 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8286 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8287 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8288 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8289 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8290 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8291 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8293 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8294 * ethertype, and use ip_version field instead.
8296 if (vlan_m->inner_type == 0xFFFF) {
8297 switch (vlan_v->inner_type) {
8298 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8299 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8300 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8301 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8303 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8304 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8306 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8307 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8313 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8314 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8315 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8316 /* Only one vlan_tag bit can be set. */
8317 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8320 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8321 rte_be_to_cpu_16(vlan_m->inner_type));
8322 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8323 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8327 * Add IPV4 item to matcher and to the value.
8329 * @param[in, out] matcher
8331 * @param[in, out] key
8332 * Flow matcher value.
8334 * Flow pattern to translate.
8336 * Item is inner pattern.
8338 * The group to insert the rule.
8341 flow_dv_translate_item_ipv4(void *matcher, void *key,
8342 const struct rte_flow_item *item,
8343 int inner, uint32_t group)
8345 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8346 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8347 const struct rte_flow_item_ipv4 nic_mask = {
8349 .src_addr = RTE_BE32(0xffffffff),
8350 .dst_addr = RTE_BE32(0xffffffff),
8351 .type_of_service = 0xff,
8352 .next_proto_id = 0xff,
8353 .time_to_live = 0xff,
8360 uint8_t tos, ihl_m, ihl_v;
8363 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8365 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8367 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8369 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8371 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8376 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8377 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8378 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8379 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8380 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8381 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8382 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8383 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8384 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8385 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8386 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8387 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8388 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8389 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8390 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8391 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8392 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8393 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8394 ipv4_m->hdr.type_of_service);
8395 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8396 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8397 ipv4_m->hdr.type_of_service >> 2);
8398 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8399 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8400 ipv4_m->hdr.next_proto_id);
8401 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8402 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8403 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8404 ipv4_m->hdr.time_to_live);
8405 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8406 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8407 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8408 !!(ipv4_m->hdr.fragment_offset));
8409 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8410 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8414 * Add IPV6 item to matcher and to the value.
8416 * @param[in, out] matcher
8418 * @param[in, out] key
8419 * Flow matcher value.
8421 * Flow pattern to translate.
8423 * Item is inner pattern.
8425 * The group to insert the rule.
8428 flow_dv_translate_item_ipv6(void *matcher, void *key,
8429 const struct rte_flow_item *item,
8430 int inner, uint32_t group)
8432 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8433 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8434 const struct rte_flow_item_ipv6 nic_mask = {
8437 "\xff\xff\xff\xff\xff\xff\xff\xff"
8438 "\xff\xff\xff\xff\xff\xff\xff\xff",
8440 "\xff\xff\xff\xff\xff\xff\xff\xff"
8441 "\xff\xff\xff\xff\xff\xff\xff\xff",
8442 .vtc_flow = RTE_BE32(0xffffffff),
8449 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8450 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8459 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8461 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8463 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8465 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8467 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8472 size = sizeof(ipv6_m->hdr.dst_addr);
8473 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8474 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8475 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8476 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8477 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8478 for (i = 0; i < size; ++i)
8479 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8480 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8481 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8482 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8483 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8484 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8485 for (i = 0; i < size; ++i)
8486 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8488 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8489 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8490 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8492 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8496 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8498 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8501 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8503 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8507 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8509 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8510 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8512 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8513 ipv6_m->hdr.hop_limits);
8514 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8515 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8516 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8517 !!(ipv6_m->has_frag_ext));
8518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8519 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8523 * Add IPV6 fragment extension item to matcher and to the value.
8525 * @param[in, out] matcher
8527 * @param[in, out] key
8528 * Flow matcher value.
8530 * Flow pattern to translate.
8532 * Item is inner pattern.
8535 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8536 const struct rte_flow_item *item,
8539 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8540 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8541 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8543 .next_header = 0xff,
8544 .frag_data = RTE_BE16(0xffff),
8551 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8553 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8555 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8557 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8559 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8560 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8561 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8562 if (!ipv6_frag_ext_v)
8564 if (!ipv6_frag_ext_m)
8565 ipv6_frag_ext_m = &nic_mask;
8566 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8567 ipv6_frag_ext_m->hdr.next_header);
8568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8569 ipv6_frag_ext_v->hdr.next_header &
8570 ipv6_frag_ext_m->hdr.next_header);
8574 * Add TCP item to matcher and to the value.
8576 * @param[in, out] matcher
8578 * @param[in, out] key
8579 * Flow matcher value.
8581 * Flow pattern to translate.
8583 * Item is inner pattern.
8586 flow_dv_translate_item_tcp(void *matcher, void *key,
8587 const struct rte_flow_item *item,
8590 const struct rte_flow_item_tcp *tcp_m = item->mask;
8591 const struct rte_flow_item_tcp *tcp_v = item->spec;
8596 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8598 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8600 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8602 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8604 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8609 tcp_m = &rte_flow_item_tcp_mask;
8610 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8611 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8612 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8613 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8614 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8615 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8617 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8618 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8619 tcp_m->hdr.tcp_flags);
8620 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8621 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8625 * Add UDP item to matcher and to the value.
8627 * @param[in, out] matcher
8629 * @param[in, out] key
8630 * Flow matcher value.
8632 * Flow pattern to translate.
8634 * Item is inner pattern.
8637 flow_dv_translate_item_udp(void *matcher, void *key,
8638 const struct rte_flow_item *item,
8641 const struct rte_flow_item_udp *udp_m = item->mask;
8642 const struct rte_flow_item_udp *udp_v = item->spec;
8647 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8649 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8651 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8653 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8655 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8660 udp_m = &rte_flow_item_udp_mask;
8661 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8662 rte_be_to_cpu_16(udp_m->hdr.src_port));
8663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8664 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8665 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8666 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8667 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8668 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8672 * Add GRE optional Key item to matcher and to the value.
8674 * @param[in, out] matcher
8676 * @param[in, out] key
8677 * Flow matcher value.
8679 * Flow pattern to translate.
8681 * Item is inner pattern.
8684 flow_dv_translate_item_gre_key(void *matcher, void *key,
8685 const struct rte_flow_item *item)
8687 const rte_be32_t *key_m = item->mask;
8688 const rte_be32_t *key_v = item->spec;
8689 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8690 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8691 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8693 /* GRE K bit must be on and should already be validated */
8694 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8695 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8699 key_m = &gre_key_default_mask;
8700 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8701 rte_be_to_cpu_32(*key_m) >> 8);
8702 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8703 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8704 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8705 rte_be_to_cpu_32(*key_m) & 0xFF);
8706 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8707 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8711 * Add GRE item to matcher and to the value.
8713 * @param[in, out] matcher
8715 * @param[in, out] key
8716 * Flow matcher value.
8718 * Flow pattern to translate.
8720 * Item is inner pattern.
8723 flow_dv_translate_item_gre(void *matcher, void *key,
8724 const struct rte_flow_item *item,
8727 const struct rte_flow_item_gre *gre_m = item->mask;
8728 const struct rte_flow_item_gre *gre_v = item->spec;
8731 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8732 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8739 uint16_t s_present:1;
8740 uint16_t k_present:1;
8741 uint16_t rsvd_bit1:1;
8742 uint16_t c_present:1;
8746 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8749 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8751 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8753 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8755 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8757 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8758 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8762 gre_m = &rte_flow_item_gre_mask;
8763 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8764 rte_be_to_cpu_16(gre_m->protocol));
8765 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8766 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8767 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8768 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8769 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8770 gre_crks_rsvd0_ver_m.c_present);
8771 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8772 gre_crks_rsvd0_ver_v.c_present &
8773 gre_crks_rsvd0_ver_m.c_present);
8774 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8775 gre_crks_rsvd0_ver_m.k_present);
8776 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8777 gre_crks_rsvd0_ver_v.k_present &
8778 gre_crks_rsvd0_ver_m.k_present);
8779 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8780 gre_crks_rsvd0_ver_m.s_present);
8781 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8782 gre_crks_rsvd0_ver_v.s_present &
8783 gre_crks_rsvd0_ver_m.s_present);
8787 * Add NVGRE item to matcher and to the value.
8789 * @param[in, out] matcher
8791 * @param[in, out] key
8792 * Flow matcher value.
8794 * Flow pattern to translate.
8796 * Item is inner pattern.
8799 flow_dv_translate_item_nvgre(void *matcher, void *key,
8800 const struct rte_flow_item *item,
8803 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8804 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8805 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8806 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8807 const char *tni_flow_id_m;
8808 const char *tni_flow_id_v;
8814 /* For NVGRE, GRE header fields must be set with defined values. */
8815 const struct rte_flow_item_gre gre_spec = {
8816 .c_rsvd0_ver = RTE_BE16(0x2000),
8817 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8819 const struct rte_flow_item_gre gre_mask = {
8820 .c_rsvd0_ver = RTE_BE16(0xB000),
8821 .protocol = RTE_BE16(UINT16_MAX),
8823 const struct rte_flow_item gre_item = {
8828 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8832 nvgre_m = &rte_flow_item_nvgre_mask;
8833 tni_flow_id_m = (const char *)nvgre_m->tni;
8834 tni_flow_id_v = (const char *)nvgre_v->tni;
8835 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8836 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8837 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8838 memcpy(gre_key_m, tni_flow_id_m, size);
8839 for (i = 0; i < size; ++i)
8840 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8844 * Add VXLAN item to matcher and to the value.
8847 * Pointer to the Ethernet device structure.
8849 * Flow rule attributes.
8850 * @param[in, out] matcher
8852 * @param[in, out] key
8853 * Flow matcher value.
8855 * Flow pattern to translate.
8857 * Item is inner pattern.
8860 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8861 const struct rte_flow_attr *attr,
8862 void *matcher, void *key,
8863 const struct rte_flow_item *item,
8866 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8867 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8872 uint32_t *tunnel_header_v;
8873 uint32_t *tunnel_header_m;
8875 struct mlx5_priv *priv = dev->data->dev_private;
8876 const struct rte_flow_item_vxlan nic_mask = {
8877 .vni = "\xff\xff\xff",
8882 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8884 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8886 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8888 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8890 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8891 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8892 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8893 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8894 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8896 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8900 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8901 (attr->group && !priv->sh->misc5_cap))
8902 vxlan_m = &rte_flow_item_vxlan_mask;
8904 vxlan_m = &nic_mask;
8906 if ((priv->sh->steering_format_version ==
8907 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8908 dport != MLX5_UDP_PORT_VXLAN) ||
8909 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8910 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8917 misc_m = MLX5_ADDR_OF(fte_match_param,
8918 matcher, misc_parameters);
8919 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8920 size = sizeof(vxlan_m->vni);
8921 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8922 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8923 memcpy(vni_m, vxlan_m->vni, size);
8924 for (i = 0; i < size; ++i)
8925 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8928 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8929 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8930 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8933 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8936 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8937 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8938 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8939 if (*tunnel_header_v)
8940 *tunnel_header_m = vxlan_m->vni[0] |
8941 vxlan_m->vni[1] << 8 |
8942 vxlan_m->vni[2] << 16;
8944 *tunnel_header_m = 0x0;
8945 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8946 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8947 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8951 * Add VXLAN-GPE item to matcher and to the value.
8953 * @param[in, out] matcher
8955 * @param[in, out] key
8956 * Flow matcher value.
8958 * Flow pattern to translate.
8960 * Item is inner pattern.
8964 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8965 const struct rte_flow_item *item, int inner)
8967 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8968 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8972 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8974 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8980 uint8_t flags_m = 0xff;
8981 uint8_t flags_v = 0xc;
8984 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8986 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8988 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8990 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8992 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8993 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8994 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8995 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9001 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9002 size = sizeof(vxlan_m->vni);
9003 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9004 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9005 memcpy(vni_m, vxlan_m->vni, size);
9006 for (i = 0; i < size; ++i)
9007 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9008 if (vxlan_m->flags) {
9009 flags_m = vxlan_m->flags;
9010 flags_v = vxlan_v->flags;
9012 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9013 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9014 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
9016 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
9021 * Add Geneve item to matcher and to the value.
9023 * @param[in, out] matcher
9025 * @param[in, out] key
9026 * Flow matcher value.
9028 * Flow pattern to translate.
9030 * Item is inner pattern.
9034 flow_dv_translate_item_geneve(void *matcher, void *key,
9035 const struct rte_flow_item *item, int inner)
9037 const struct rte_flow_item_geneve *geneve_m = item->mask;
9038 const struct rte_flow_item_geneve *geneve_v = item->spec;
9041 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9042 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9051 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9053 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9055 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9057 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9059 dport = MLX5_UDP_PORT_GENEVE;
9060 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9067 geneve_m = &rte_flow_item_geneve_mask;
9068 size = sizeof(geneve_m->vni);
9069 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9070 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9071 memcpy(vni_m, geneve_m->vni, size);
9072 for (i = 0; i < size; ++i)
9073 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9074 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
9075 rte_be_to_cpu_16(geneve_m->protocol));
9076 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9077 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
9078 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9079 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9080 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9081 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9082 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9083 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9084 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9085 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9086 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9087 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9088 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9092 * Create Geneve TLV option resource.
9094 * @param dev[in, out]
9095 * Pointer to rte_eth_dev structure.
9096 * @param[in, out] tag_be24
9097 * Tag value in big endian then R-shift 8.
9098 * @parm[in, out] dev_flow
9099 * Pointer to the dev_flow.
9101 * pointer to error structure.
9104 * 0 on success otherwise -errno and errno is set.
9108 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9109 const struct rte_flow_item *item,
9110 struct rte_flow_error *error)
9112 struct mlx5_priv *priv = dev->data->dev_private;
9113 struct mlx5_dev_ctx_shared *sh = priv->sh;
9114 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9115 sh->geneve_tlv_option_resource;
9116 struct mlx5_devx_obj *obj;
9117 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9122 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9123 if (geneve_opt_resource != NULL) {
9124 if (geneve_opt_resource->option_class ==
9125 geneve_opt_v->option_class &&
9126 geneve_opt_resource->option_type ==
9127 geneve_opt_v->option_type &&
9128 geneve_opt_resource->length ==
9129 geneve_opt_v->option_len) {
9130 /* We already have GENVE TLV option obj allocated. */
9131 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9134 ret = rte_flow_error_set(error, ENOMEM,
9135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9136 "Only one GENEVE TLV option supported");
9140 /* Create a GENEVE TLV object and resource. */
9141 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9142 geneve_opt_v->option_class,
9143 geneve_opt_v->option_type,
9144 geneve_opt_v->option_len);
9146 ret = rte_flow_error_set(error, ENODATA,
9147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9148 "Failed to create GENEVE TLV Devx object");
9151 sh->geneve_tlv_option_resource =
9152 mlx5_malloc(MLX5_MEM_ZERO,
9153 sizeof(*geneve_opt_resource),
9155 if (!sh->geneve_tlv_option_resource) {
9156 claim_zero(mlx5_devx_cmd_destroy(obj));
9157 ret = rte_flow_error_set(error, ENOMEM,
9158 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9159 "GENEVE TLV object memory allocation failed");
9162 geneve_opt_resource = sh->geneve_tlv_option_resource;
9163 geneve_opt_resource->obj = obj;
9164 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9165 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9166 geneve_opt_resource->length = geneve_opt_v->option_len;
9167 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9171 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9176 * Add Geneve TLV option item to matcher.
9178 * @param[in, out] dev
9179 * Pointer to rte_eth_dev structure.
9180 * @param[in, out] matcher
9182 * @param[in, out] key
9183 * Flow matcher value.
9185 * Flow pattern to translate.
9187 * Pointer to error structure.
9190 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9191 void *key, const struct rte_flow_item *item,
9192 struct rte_flow_error *error)
9194 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9195 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9196 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9197 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9198 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9200 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9201 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9207 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9208 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9211 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9215 * Set the option length in GENEVE header if not requested.
9216 * The GENEVE TLV option length is expressed by the option length field
9217 * in the GENEVE header.
9218 * If the option length was not requested but the GENEVE TLV option item
9219 * is present we set the option length field implicitly.
9221 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9222 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9223 MLX5_GENEVE_OPTLEN_MASK);
9224 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9225 geneve_opt_v->option_len + 1);
9227 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9228 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9230 if (geneve_opt_v->data) {
9231 memcpy(&opt_data_key, geneve_opt_v->data,
9232 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9233 sizeof(opt_data_key)));
9234 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9235 sizeof(opt_data_key));
9236 memcpy(&opt_data_mask, geneve_opt_m->data,
9237 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9238 sizeof(opt_data_mask)));
9239 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9240 sizeof(opt_data_mask));
9241 MLX5_SET(fte_match_set_misc3, misc3_m,
9242 geneve_tlv_option_0_data,
9243 rte_be_to_cpu_32(opt_data_mask));
9244 MLX5_SET(fte_match_set_misc3, misc3_v,
9245 geneve_tlv_option_0_data,
9246 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9252 * Add MPLS item to matcher and to the value.
9254 * @param[in, out] matcher
9256 * @param[in, out] key
9257 * Flow matcher value.
9259 * Flow pattern to translate.
9260 * @param[in] prev_layer
9261 * The protocol layer indicated in previous item.
9263 * Item is inner pattern.
9266 flow_dv_translate_item_mpls(void *matcher, void *key,
9267 const struct rte_flow_item *item,
9268 uint64_t prev_layer,
9271 const uint32_t *in_mpls_m = item->mask;
9272 const uint32_t *in_mpls_v = item->spec;
9273 uint32_t *out_mpls_m = 0;
9274 uint32_t *out_mpls_v = 0;
9275 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9276 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9277 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9279 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9280 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9281 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9283 switch (prev_layer) {
9284 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9286 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9287 MLX5_UDP_PORT_MPLS);
9289 case MLX5_FLOW_LAYER_GRE:
9291 case MLX5_FLOW_LAYER_GRE_KEY:
9292 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9293 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9294 RTE_ETHER_TYPE_MPLS);
9302 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9303 switch (prev_layer) {
9304 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9306 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9307 outer_first_mpls_over_udp);
9309 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9310 outer_first_mpls_over_udp);
9312 case MLX5_FLOW_LAYER_GRE:
9314 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9315 outer_first_mpls_over_gre);
9317 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9318 outer_first_mpls_over_gre);
9321 /* Inner MPLS not over GRE is not supported. */
9324 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9328 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9334 if (out_mpls_m && out_mpls_v) {
9335 *out_mpls_m = *in_mpls_m;
9336 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9341 * Add metadata register item to matcher
9343 * @param[in, out] matcher
9345 * @param[in, out] key
9346 * Flow matcher value.
9347 * @param[in] reg_type
9348 * Type of device metadata register
9355 flow_dv_match_meta_reg(void *matcher, void *key,
9356 enum modify_reg reg_type,
9357 uint32_t data, uint32_t mask)
9360 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9362 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9368 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9369 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9372 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9373 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9377 * The metadata register C0 field might be divided into
9378 * source vport index and META item value, we should set
9379 * this field according to specified mask, not as whole one.
9381 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9383 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9384 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9387 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9390 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9391 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9394 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9395 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9398 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9399 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9402 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9403 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9406 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9407 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9410 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9411 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9414 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9415 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9424 * Add MARK item to matcher
9427 * The device to configure through.
9428 * @param[in, out] matcher
9430 * @param[in, out] key
9431 * Flow matcher value.
9433 * Flow pattern to translate.
9436 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9437 void *matcher, void *key,
9438 const struct rte_flow_item *item)
9440 struct mlx5_priv *priv = dev->data->dev_private;
9441 const struct rte_flow_item_mark *mark;
9445 mark = item->mask ? (const void *)item->mask :
9446 &rte_flow_item_mark_mask;
9447 mask = mark->id & priv->sh->dv_mark_mask;
9448 mark = (const void *)item->spec;
9450 value = mark->id & priv->sh->dv_mark_mask & mask;
9452 enum modify_reg reg;
9454 /* Get the metadata register index for the mark. */
9455 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9456 MLX5_ASSERT(reg > 0);
9457 if (reg == REG_C_0) {
9458 struct mlx5_priv *priv = dev->data->dev_private;
9459 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9460 uint32_t shl_c0 = rte_bsf32(msk_c0);
9466 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9471 * Add META item to matcher
9474 * The devich to configure through.
9475 * @param[in, out] matcher
9477 * @param[in, out] key
9478 * Flow matcher value.
9480 * Attributes of flow that includes this item.
9482 * Flow pattern to translate.
9485 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9486 void *matcher, void *key,
9487 const struct rte_flow_attr *attr,
9488 const struct rte_flow_item *item)
9490 const struct rte_flow_item_meta *meta_m;
9491 const struct rte_flow_item_meta *meta_v;
9493 meta_m = (const void *)item->mask;
9495 meta_m = &rte_flow_item_meta_mask;
9496 meta_v = (const void *)item->spec;
9499 uint32_t value = meta_v->data;
9500 uint32_t mask = meta_m->data;
9502 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9505 MLX5_ASSERT(reg != REG_NON);
9506 if (reg == REG_C_0) {
9507 struct mlx5_priv *priv = dev->data->dev_private;
9508 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9509 uint32_t shl_c0 = rte_bsf32(msk_c0);
9515 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9520 * Add vport metadata Reg C0 item to matcher
9522 * @param[in, out] matcher
9524 * @param[in, out] key
9525 * Flow matcher value.
9527 * Flow pattern to translate.
9530 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9531 uint32_t value, uint32_t mask)
9533 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9537 * Add tag item to matcher
9540 * The devich to configure through.
9541 * @param[in, out] matcher
9543 * @param[in, out] key
9544 * Flow matcher value.
9546 * Flow pattern to translate.
9549 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9550 void *matcher, void *key,
9551 const struct rte_flow_item *item)
9553 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9554 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9555 uint32_t mask, value;
9558 value = tag_v->data;
9559 mask = tag_m ? tag_m->data : UINT32_MAX;
9560 if (tag_v->id == REG_C_0) {
9561 struct mlx5_priv *priv = dev->data->dev_private;
9562 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9563 uint32_t shl_c0 = rte_bsf32(msk_c0);
9569 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9573 * Add TAG item to matcher
9576 * The devich to configure through.
9577 * @param[in, out] matcher
9579 * @param[in, out] key
9580 * Flow matcher value.
9582 * Flow pattern to translate.
9585 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9586 void *matcher, void *key,
9587 const struct rte_flow_item *item)
9589 const struct rte_flow_item_tag *tag_v = item->spec;
9590 const struct rte_flow_item_tag *tag_m = item->mask;
9591 enum modify_reg reg;
9594 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9595 /* Get the metadata register index for the tag. */
9596 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9597 MLX5_ASSERT(reg > 0);
9598 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9602 * Add source vport match to the specified matcher.
9604 * @param[in, out] matcher
9606 * @param[in, out] key
9607 * Flow matcher value.
9609 * Source vport value to match
9614 flow_dv_translate_item_source_vport(void *matcher, void *key,
9615 int16_t port, uint16_t mask)
9617 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9618 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9620 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9621 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9625 * Translate port-id item to eswitch match on port-id.
9628 * The devich to configure through.
9629 * @param[in, out] matcher
9631 * @param[in, out] key
9632 * Flow matcher value.
9634 * Flow pattern to translate.
9639 * 0 on success, a negative errno value otherwise.
9642 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9643 void *key, const struct rte_flow_item *item,
9644 const struct rte_flow_attr *attr)
9646 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9647 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9648 struct mlx5_priv *priv;
9651 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9652 flow_dv_translate_item_source_vport(matcher, key,
9653 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9656 mask = pid_m ? pid_m->id : 0xffff;
9657 id = pid_v ? pid_v->id : dev->data->port_id;
9658 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9662 * Translate to vport field or to metadata, depending on mode.
9663 * Kernel can use either misc.source_port or half of C0 metadata
9666 if (priv->vport_meta_mask) {
9668 * Provide the hint for SW steering library
9669 * to insert the flow into ingress domain and
9670 * save the extra vport match.
9672 if (mask == 0xffff && priv->vport_id == 0xffff &&
9673 priv->pf_bond < 0 && attr->transfer)
9674 flow_dv_translate_item_source_vport
9675 (matcher, key, priv->vport_id, mask);
9677 * We should always set the vport metadata register,
9678 * otherwise the SW steering library can drop
9679 * the rule if wire vport metadata value is not zero,
9680 * it depends on kernel configuration.
9682 flow_dv_translate_item_meta_vport(matcher, key,
9683 priv->vport_meta_tag,
9684 priv->vport_meta_mask);
9686 flow_dv_translate_item_source_vport(matcher, key,
9687 priv->vport_id, mask);
9693 * Add ICMP6 item to matcher and to the value.
9695 * @param[in, out] matcher
9697 * @param[in, out] key
9698 * Flow matcher value.
9700 * Flow pattern to translate.
9702 * Item is inner pattern.
9705 flow_dv_translate_item_icmp6(void *matcher, void *key,
9706 const struct rte_flow_item *item,
9709 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9710 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9713 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9715 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9717 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9719 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9721 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9723 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9725 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9726 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9730 icmp6_m = &rte_flow_item_icmp6_mask;
9731 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9732 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9733 icmp6_v->type & icmp6_m->type);
9734 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9735 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9736 icmp6_v->code & icmp6_m->code);
9740 * Add ICMP item to matcher and to the value.
9742 * @param[in, out] matcher
9744 * @param[in, out] key
9745 * Flow matcher value.
9747 * Flow pattern to translate.
9749 * Item is inner pattern.
9752 flow_dv_translate_item_icmp(void *matcher, void *key,
9753 const struct rte_flow_item *item,
9756 const struct rte_flow_item_icmp *icmp_m = item->mask;
9757 const struct rte_flow_item_icmp *icmp_v = item->spec;
9758 uint32_t icmp_header_data_m = 0;
9759 uint32_t icmp_header_data_v = 0;
9762 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9764 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9766 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9768 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9770 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9772 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9774 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9775 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9779 icmp_m = &rte_flow_item_icmp_mask;
9780 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9781 icmp_m->hdr.icmp_type);
9782 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9783 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9784 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9785 icmp_m->hdr.icmp_code);
9786 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9787 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9788 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9789 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9790 if (icmp_header_data_m) {
9791 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9792 icmp_header_data_v |=
9793 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9794 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9795 icmp_header_data_m);
9796 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9797 icmp_header_data_v & icmp_header_data_m);
9802 * Add GTP item to matcher and to the value.
9804 * @param[in, out] matcher
9806 * @param[in, out] key
9807 * Flow matcher value.
9809 * Flow pattern to translate.
9811 * Item is inner pattern.
9814 flow_dv_translate_item_gtp(void *matcher, void *key,
9815 const struct rte_flow_item *item, int inner)
9817 const struct rte_flow_item_gtp *gtp_m = item->mask;
9818 const struct rte_flow_item_gtp *gtp_v = item->spec;
9821 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9823 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9824 uint16_t dport = RTE_GTPU_UDP_PORT;
9827 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9829 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9831 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9833 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9835 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9836 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9837 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9842 gtp_m = &rte_flow_item_gtp_mask;
9843 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9844 gtp_m->v_pt_rsv_flags);
9845 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9846 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9847 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9848 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9849 gtp_v->msg_type & gtp_m->msg_type);
9850 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9851 rte_be_to_cpu_32(gtp_m->teid));
9852 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9853 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9857 * Add GTP PSC item to matcher.
9859 * @param[in, out] matcher
9861 * @param[in, out] key
9862 * Flow matcher value.
9864 * Flow pattern to translate.
9867 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9868 const struct rte_flow_item *item)
9870 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9871 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9872 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9874 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9880 uint8_t next_ext_header_type;
9885 /* Always set E-flag match on one, regardless of GTP item settings. */
9886 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9887 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9888 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9889 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9890 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9891 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9892 /*Set next extension header type. */
9895 dw_2.next_ext_header_type = 0xff;
9896 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9897 rte_cpu_to_be_32(dw_2.w32));
9900 dw_2.next_ext_header_type = 0x85;
9901 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9902 rte_cpu_to_be_32(dw_2.w32));
9914 /*Set extension header PDU type and Qos. */
9916 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9918 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9919 dw_0.qfi = gtp_psc_m->hdr.qfi;
9920 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9921 rte_cpu_to_be_32(dw_0.w32));
9923 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9924 gtp_psc_m->hdr.type);
9925 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9926 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9927 rte_cpu_to_be_32(dw_0.w32));
9933 * Add eCPRI item to matcher and to the value.
9936 * The devich to configure through.
9937 * @param[in, out] matcher
9939 * @param[in, out] key
9940 * Flow matcher value.
9942 * Flow pattern to translate.
9943 * @param[in] last_item
9947 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9948 void *key, const struct rte_flow_item *item,
9951 struct mlx5_priv *priv = dev->data->dev_private;
9952 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9953 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9954 struct rte_ecpri_common_hdr common;
9955 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9957 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9963 * In case of eCPRI over Ethernet, if EtherType is not specified,
9964 * match on eCPRI EtherType implicitly.
9966 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
9967 void *hdrs_m, *hdrs_v, *l2m, *l2v;
9969 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9970 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9971 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
9972 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
9973 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
9974 *(uint16_t *)l2m = UINT16_MAX;
9975 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
9981 ecpri_m = &rte_flow_item_ecpri_mask;
9983 * Maximal four DW samples are supported in a single matching now.
9984 * Two are used now for a eCPRI matching:
9985 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9986 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9989 if (!ecpri_m->hdr.common.u32)
9991 samples = priv->sh->ecpri_parser.ids;
9992 /* Need to take the whole DW as the mask to fill the entry. */
9993 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9994 prog_sample_field_value_0);
9995 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9996 prog_sample_field_value_0);
9997 /* Already big endian (network order) in the header. */
9998 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9999 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10000 /* Sample#0, used for matching type, offset 0. */
10001 MLX5_SET(fte_match_set_misc4, misc4_m,
10002 prog_sample_field_id_0, samples[0]);
10003 /* It makes no sense to set the sample ID in the mask field. */
10004 MLX5_SET(fte_match_set_misc4, misc4_v,
10005 prog_sample_field_id_0, samples[0]);
10007 * Checking if message body part needs to be matched.
10008 * Some wildcard rules only matching type field should be supported.
10010 if (ecpri_m->hdr.dummy[0]) {
10011 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10012 switch (common.type) {
10013 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10014 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10015 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10016 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10017 prog_sample_field_value_1);
10018 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10019 prog_sample_field_value_1);
10020 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10021 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10022 ecpri_m->hdr.dummy[0];
10023 /* Sample#1, to match message body, offset 4. */
10024 MLX5_SET(fte_match_set_misc4, misc4_m,
10025 prog_sample_field_id_1, samples[1]);
10026 MLX5_SET(fte_match_set_misc4, misc4_v,
10027 prog_sample_field_id_1, samples[1]);
10030 /* Others, do not match any sample ID. */
10037 * Add connection tracking status item to matcher
10040 * The devich to configure through.
10041 * @param[in, out] matcher
10043 * @param[in, out] key
10044 * Flow matcher value.
10046 * Flow pattern to translate.
10049 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10050 void *matcher, void *key,
10051 const struct rte_flow_item *item)
10053 uint32_t reg_value = 0;
10055 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10056 uint32_t reg_mask = 0;
10057 const struct rte_flow_item_conntrack *spec = item->spec;
10058 const struct rte_flow_item_conntrack *mask = item->mask;
10060 struct rte_flow_error error;
10063 mask = &rte_flow_item_conntrack_mask;
10064 if (!spec || !mask->flags)
10066 flags = spec->flags & mask->flags;
10067 /* The conflict should be checked in the validation. */
10068 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10069 reg_value |= MLX5_CT_SYNDROME_VALID;
10070 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10071 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10072 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10073 reg_value |= MLX5_CT_SYNDROME_INVALID;
10074 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10075 reg_value |= MLX5_CT_SYNDROME_TRAP;
10076 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10077 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10078 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10079 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10080 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10082 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10083 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10084 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10085 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10086 /* The REG_C_x value could be saved during startup. */
10087 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10088 if (reg_id == REG_NON)
10090 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10091 reg_value, reg_mask);
10095 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10096 const struct rte_flow_item *item,
10097 struct mlx5_flow *dev_flow, bool is_inner)
10099 const struct rte_flow_item_flex *spec =
10100 (const struct rte_flow_item_flex *)item->spec;
10101 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10103 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10106 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10107 /* Don't count both inner and outer flex items in one rule. */
10108 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10109 MLX5_ASSERT(false);
10110 dev_flow->handle->flex_item |= RTE_BIT32(index);
10112 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10115 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10117 #define HEADER_IS_ZERO(match_criteria, headers) \
10118 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10119 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10122 * Calculate flow matcher enable bitmap.
10124 * @param match_criteria
10125 * Pointer to flow matcher criteria.
10128 * Bitmap of enabled fields.
10131 flow_dv_matcher_enable(uint32_t *match_criteria)
10133 uint8_t match_criteria_enable;
10135 match_criteria_enable =
10136 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10137 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10138 match_criteria_enable |=
10139 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10140 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10141 match_criteria_enable |=
10142 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10143 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10144 match_criteria_enable |=
10145 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10146 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10147 match_criteria_enable |=
10148 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10149 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10150 match_criteria_enable |=
10151 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10152 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10153 match_criteria_enable |=
10154 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10155 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10156 return match_criteria_enable;
10160 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10163 * Check flow matching criteria first, subtract misc5/4 length if flow
10164 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10165 * misc5/4 are not supported, and matcher creation failure is expected
10166 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10167 * misc5 is right after misc4.
10169 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10170 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10171 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10172 if (!(match_criteria & (1 <<
10173 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10174 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10179 static struct mlx5_list_entry *
10180 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10181 struct mlx5_list_entry *entry, void *cb_ctx)
10183 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10184 struct mlx5_flow_dv_matcher *ref = ctx->data;
10185 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10186 typeof(*tbl), tbl);
10187 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10192 rte_flow_error_set(ctx->error, ENOMEM,
10193 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10194 "cannot create matcher");
10197 memcpy(resource, entry, sizeof(*resource));
10198 resource->tbl = &tbl->tbl;
10199 return &resource->entry;
10203 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10204 struct mlx5_list_entry *entry)
10209 struct mlx5_list_entry *
10210 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10212 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10213 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10214 struct rte_eth_dev *dev = ctx->dev;
10215 struct mlx5_flow_tbl_data_entry *tbl_data;
10216 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10217 struct rte_flow_error *error = ctx->error;
10218 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10219 struct mlx5_flow_tbl_resource *tbl;
10224 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10226 rte_flow_error_set(error, ENOMEM,
10227 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10229 "cannot allocate flow table data entry");
10232 tbl_data->idx = idx;
10233 tbl_data->tunnel = tt_prm->tunnel;
10234 tbl_data->group_id = tt_prm->group_id;
10235 tbl_data->external = !!tt_prm->external;
10236 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10237 tbl_data->is_egress = !!key.is_egress;
10238 tbl_data->is_transfer = !!key.is_fdb;
10239 tbl_data->dummy = !!key.dummy;
10240 tbl_data->level = key.level;
10241 tbl_data->id = key.id;
10242 tbl = &tbl_data->tbl;
10244 return &tbl_data->entry;
10246 domain = sh->fdb_domain;
10247 else if (key.is_egress)
10248 domain = sh->tx_domain;
10250 domain = sh->rx_domain;
10251 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10253 rte_flow_error_set(error, ENOMEM,
10254 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10255 NULL, "cannot create flow table object");
10256 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10259 if (key.level != 0) {
10260 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10261 (tbl->obj, &tbl_data->jump.action);
10263 rte_flow_error_set(error, ENOMEM,
10264 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10266 "cannot create flow jump action");
10267 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10268 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10272 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10273 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10274 key.level, key.id);
10275 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10276 flow_dv_matcher_create_cb,
10277 flow_dv_matcher_match_cb,
10278 flow_dv_matcher_remove_cb,
10279 flow_dv_matcher_clone_cb,
10280 flow_dv_matcher_clone_free_cb);
10281 if (!tbl_data->matchers) {
10282 rte_flow_error_set(error, ENOMEM,
10283 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10285 "cannot create tbl matcher list");
10286 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10287 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10288 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10291 return &tbl_data->entry;
10295 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10298 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10299 struct mlx5_flow_tbl_data_entry *tbl_data =
10300 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10301 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10303 return tbl_data->level != key.level ||
10304 tbl_data->id != key.id ||
10305 tbl_data->dummy != key.dummy ||
10306 tbl_data->is_transfer != !!key.is_fdb ||
10307 tbl_data->is_egress != !!key.is_egress;
10310 struct mlx5_list_entry *
10311 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10314 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10315 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10316 struct mlx5_flow_tbl_data_entry *tbl_data;
10317 struct rte_flow_error *error = ctx->error;
10320 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10322 rte_flow_error_set(error, ENOMEM,
10323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10325 "cannot allocate flow table data entry");
10328 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10329 tbl_data->idx = idx;
10330 return &tbl_data->entry;
10334 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10336 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10337 struct mlx5_flow_tbl_data_entry *tbl_data =
10338 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10340 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10344 * Get a flow table.
10346 * @param[in, out] dev
10347 * Pointer to rte_eth_dev structure.
10348 * @param[in] table_level
10349 * Table level to use.
10350 * @param[in] egress
10351 * Direction of the table.
10352 * @param[in] transfer
10353 * E-Switch or NIC flow.
10355 * Dummy entry for dv API.
10356 * @param[in] table_id
10358 * @param[out] error
10359 * pointer to error structure.
10362 * Returns tables resource based on the index, NULL in case of failed.
10364 struct mlx5_flow_tbl_resource *
10365 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10366 uint32_t table_level, uint8_t egress,
10369 const struct mlx5_flow_tunnel *tunnel,
10370 uint32_t group_id, uint8_t dummy,
10372 struct rte_flow_error *error)
10374 struct mlx5_priv *priv = dev->data->dev_private;
10375 union mlx5_flow_tbl_key table_key = {
10377 .level = table_level,
10381 .is_fdb = !!transfer,
10382 .is_egress = !!egress,
10385 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10387 .group_id = group_id,
10388 .external = external,
10390 struct mlx5_flow_cb_ctx ctx = {
10393 .data = &table_key.v64,
10396 struct mlx5_list_entry *entry;
10397 struct mlx5_flow_tbl_data_entry *tbl_data;
10399 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10401 rte_flow_error_set(error, ENOMEM,
10402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10403 "cannot get table");
10406 DRV_LOG(DEBUG, "table_level %u table_id %u "
10407 "tunnel %u group %u registered.",
10408 table_level, table_id,
10409 tunnel ? tunnel->tunnel_id : 0, group_id);
10410 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10411 return &tbl_data->tbl;
10415 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10417 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10418 struct mlx5_flow_tbl_data_entry *tbl_data =
10419 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10421 MLX5_ASSERT(entry && sh);
10422 if (tbl_data->jump.action)
10423 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10424 if (tbl_data->tbl.obj)
10425 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10426 if (tbl_data->tunnel_offload && tbl_data->external) {
10427 struct mlx5_list_entry *he;
10428 struct mlx5_hlist *tunnel_grp_hash;
10429 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10430 union tunnel_tbl_key tunnel_key = {
10431 .tunnel_id = tbl_data->tunnel ?
10432 tbl_data->tunnel->tunnel_id : 0,
10433 .group = tbl_data->group_id
10435 uint32_t table_level = tbl_data->level;
10436 struct mlx5_flow_cb_ctx ctx = {
10437 .data = (void *)&tunnel_key.val,
10440 tunnel_grp_hash = tbl_data->tunnel ?
10441 tbl_data->tunnel->groups :
10443 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10445 mlx5_hlist_unregister(tunnel_grp_hash, he);
10447 "table_level %u id %u tunnel %u group %u released.",
10451 tbl_data->tunnel->tunnel_id : 0,
10452 tbl_data->group_id);
10454 mlx5_list_destroy(tbl_data->matchers);
10455 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10459 * Release a flow table.
10462 * Pointer to device shared structure.
10464 * Table resource to be released.
10467 * Returns 0 if table was released, else return 1;
10470 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10471 struct mlx5_flow_tbl_resource *tbl)
10473 struct mlx5_flow_tbl_data_entry *tbl_data =
10474 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10478 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10482 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10483 struct mlx5_list_entry *entry, void *cb_ctx)
10485 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10486 struct mlx5_flow_dv_matcher *ref = ctx->data;
10487 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10490 return cur->crc != ref->crc ||
10491 cur->priority != ref->priority ||
10492 memcmp((const void *)cur->mask.buf,
10493 (const void *)ref->mask.buf, ref->mask.size);
10496 struct mlx5_list_entry *
10497 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10499 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10500 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10501 struct mlx5_flow_dv_matcher *ref = ctx->data;
10502 struct mlx5_flow_dv_matcher *resource;
10503 struct mlx5dv_flow_matcher_attr dv_attr = {
10504 .type = IBV_FLOW_ATTR_NORMAL,
10505 .match_mask = (void *)&ref->mask,
10507 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10508 typeof(*tbl), tbl);
10511 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10514 rte_flow_error_set(ctx->error, ENOMEM,
10515 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10516 "cannot create matcher");
10520 dv_attr.match_criteria_enable =
10521 flow_dv_matcher_enable(resource->mask.buf);
10522 __flow_dv_adjust_buf_size(&ref->mask.size,
10523 dv_attr.match_criteria_enable);
10524 dv_attr.priority = ref->priority;
10525 if (tbl->is_egress)
10526 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10527 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10529 &resource->matcher_object);
10531 mlx5_free(resource);
10532 rte_flow_error_set(ctx->error, ENOMEM,
10533 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10534 "cannot create matcher");
10537 return &resource->entry;
10541 * Register the flow matcher.
10543 * @param[in, out] dev
10544 * Pointer to rte_eth_dev structure.
10545 * @param[in, out] matcher
10546 * Pointer to flow matcher.
10547 * @param[in, out] key
10548 * Pointer to flow table key.
10549 * @parm[in, out] dev_flow
10550 * Pointer to the dev_flow.
10551 * @param[out] error
10552 * pointer to error structure.
10555 * 0 on success otherwise -errno and errno is set.
10558 flow_dv_matcher_register(struct rte_eth_dev *dev,
10559 struct mlx5_flow_dv_matcher *ref,
10560 union mlx5_flow_tbl_key *key,
10561 struct mlx5_flow *dev_flow,
10562 const struct mlx5_flow_tunnel *tunnel,
10564 struct rte_flow_error *error)
10566 struct mlx5_list_entry *entry;
10567 struct mlx5_flow_dv_matcher *resource;
10568 struct mlx5_flow_tbl_resource *tbl;
10569 struct mlx5_flow_tbl_data_entry *tbl_data;
10570 struct mlx5_flow_cb_ctx ctx = {
10575 * tunnel offload API requires this registration for cases when
10576 * tunnel match rule was inserted before tunnel set rule.
10578 tbl = flow_dv_tbl_resource_get(dev, key->level,
10579 key->is_egress, key->is_fdb,
10580 dev_flow->external, tunnel,
10581 group_id, 0, key->id, error);
10583 return -rte_errno; /* No need to refill the error info */
10584 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10586 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10588 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10589 return rte_flow_error_set(error, ENOMEM,
10590 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10591 "cannot allocate ref memory");
10593 resource = container_of(entry, typeof(*resource), entry);
10594 dev_flow->handle->dvh.matcher = resource;
10598 struct mlx5_list_entry *
10599 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10601 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10602 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10603 struct mlx5_flow_dv_tag_resource *entry;
10607 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10609 rte_flow_error_set(ctx->error, ENOMEM,
10610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10611 "cannot allocate resource memory");
10615 entry->tag_id = *(uint32_t *)(ctx->data);
10616 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10619 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10620 rte_flow_error_set(ctx->error, ENOMEM,
10621 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10622 NULL, "cannot create action");
10625 return &entry->entry;
10629 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10632 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10633 struct mlx5_flow_dv_tag_resource *tag =
10634 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10636 return *(uint32_t *)(ctx->data) != tag->tag_id;
10639 struct mlx5_list_entry *
10640 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10643 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10644 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10645 struct mlx5_flow_dv_tag_resource *entry;
10648 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10650 rte_flow_error_set(ctx->error, ENOMEM,
10651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10652 "cannot allocate tag resource memory");
10655 memcpy(entry, oentry, sizeof(*entry));
10657 return &entry->entry;
10661 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10663 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10664 struct mlx5_flow_dv_tag_resource *tag =
10665 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10667 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10671 * Find existing tag resource or create and register a new one.
10673 * @param dev[in, out]
10674 * Pointer to rte_eth_dev structure.
10675 * @param[in, out] tag_be24
10676 * Tag value in big endian then R-shift 8.
10677 * @parm[in, out] dev_flow
10678 * Pointer to the dev_flow.
10679 * @param[out] error
10680 * pointer to error structure.
10683 * 0 on success otherwise -errno and errno is set.
10686 flow_dv_tag_resource_register
10687 (struct rte_eth_dev *dev,
10689 struct mlx5_flow *dev_flow,
10690 struct rte_flow_error *error)
10692 struct mlx5_priv *priv = dev->data->dev_private;
10693 struct mlx5_flow_dv_tag_resource *resource;
10694 struct mlx5_list_entry *entry;
10695 struct mlx5_flow_cb_ctx ctx = {
10699 struct mlx5_hlist *tag_table;
10701 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10703 MLX5_TAGS_HLIST_ARRAY_SIZE,
10704 false, false, priv->sh,
10705 flow_dv_tag_create_cb,
10706 flow_dv_tag_match_cb,
10707 flow_dv_tag_remove_cb,
10708 flow_dv_tag_clone_cb,
10709 flow_dv_tag_clone_free_cb);
10710 if (unlikely(!tag_table))
10712 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10714 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10716 dev_flow->handle->dvh.rix_tag = resource->idx;
10717 dev_flow->dv.tag_resource = resource;
10724 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10726 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10727 struct mlx5_flow_dv_tag_resource *tag =
10728 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10730 MLX5_ASSERT(tag && sh && tag->action);
10731 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10732 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10733 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10740 * Pointer to Ethernet device.
10745 * 1 while a reference on it exists, 0 when freed.
10748 flow_dv_tag_release(struct rte_eth_dev *dev,
10751 struct mlx5_priv *priv = dev->data->dev_private;
10752 struct mlx5_flow_dv_tag_resource *tag;
10754 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10757 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10758 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10759 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10763 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10766 * Pointer to rte_eth_dev structure.
10767 * @param[in] action
10768 * Pointer to action PORT_ID / REPRESENTED_PORT.
10769 * @param[out] dst_port_id
10770 * The target port ID.
10771 * @param[out] error
10772 * Pointer to the error structure.
10775 * 0 on success, a negative errno value otherwise and rte_errno is set.
10778 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10779 const struct rte_flow_action *action,
10780 uint32_t *dst_port_id,
10781 struct rte_flow_error *error)
10784 struct mlx5_priv *priv;
10786 switch (action->type) {
10787 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10788 const struct rte_flow_action_port_id *conf;
10790 conf = (const struct rte_flow_action_port_id *)action->conf;
10791 port = conf->original ? dev->data->port_id : conf->id;
10794 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10795 const struct rte_flow_action_ethdev *ethdev;
10797 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10798 port = ethdev->port_id;
10802 MLX5_ASSERT(false);
10803 return rte_flow_error_set(error, EINVAL,
10804 RTE_FLOW_ERROR_TYPE_ACTION, action,
10805 "unknown E-Switch action");
10808 priv = mlx5_port_to_eswitch_info(port, false);
10810 return rte_flow_error_set(error, -rte_errno,
10811 RTE_FLOW_ERROR_TYPE_ACTION,
10813 "No eswitch info was found for port");
10814 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10816 * This parameter is transferred to
10817 * mlx5dv_dr_action_create_dest_ib_port().
10819 *dst_port_id = priv->dev_port;
10822 * Legacy mode, no LAG configurations is supported.
10823 * This parameter is transferred to
10824 * mlx5dv_dr_action_create_dest_vport().
10826 *dst_port_id = priv->vport_id;
10832 * Create a counter with aging configuration.
10835 * Pointer to rte_eth_dev structure.
10836 * @param[in] dev_flow
10837 * Pointer to the mlx5_flow.
10838 * @param[out] count
10839 * Pointer to the counter action configuration.
10841 * Pointer to the aging action configuration.
10844 * Index to flow counter on success, 0 otherwise.
10847 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10848 struct mlx5_flow *dev_flow,
10849 const struct rte_flow_action_count *count
10851 const struct rte_flow_action_age *age)
10854 struct mlx5_age_param *age_param;
10856 counter = flow_dv_counter_alloc(dev, !!age);
10857 if (!counter || age == NULL)
10859 age_param = flow_dv_counter_idx_get_age(dev, counter);
10860 age_param->context = age->context ? age->context :
10861 (void *)(uintptr_t)(dev_flow->flow_idx);
10862 age_param->timeout = age->timeout;
10863 age_param->port_id = dev->data->port_id;
10864 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10865 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10870 * Add Tx queue matcher
10873 * Pointer to the dev struct.
10874 * @param[in, out] matcher
10876 * @param[in, out] key
10877 * Flow matcher value.
10879 * Flow pattern to translate.
10881 * Item is inner pattern.
10884 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10885 void *matcher, void *key,
10886 const struct rte_flow_item *item)
10888 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10889 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10891 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10893 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10894 struct mlx5_txq_ctrl *txq;
10895 uint32_t queue, mask;
10897 queue_m = (const void *)item->mask;
10898 queue_v = (const void *)item->spec;
10901 txq = mlx5_txq_get(dev, queue_v->queue);
10904 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10905 queue = txq->obj->sq->id;
10907 queue = txq->obj->sq_obj.sq->id;
10908 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10909 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10910 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10911 mlx5_txq_release(dev, queue_v->queue);
10915 * Set the hash fields according to the @p flow information.
10917 * @param[in] dev_flow
10918 * Pointer to the mlx5_flow.
10919 * @param[in] rss_desc
10920 * Pointer to the mlx5_flow_rss_desc.
10923 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10924 struct mlx5_flow_rss_desc *rss_desc)
10926 uint64_t items = dev_flow->handle->layers;
10928 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10930 dev_flow->hash_fields = 0;
10931 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10932 if (rss_desc->level >= 2)
10935 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10936 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10937 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10938 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10939 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10940 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10941 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10943 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10945 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10946 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10947 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10948 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10949 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10950 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10951 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10953 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10956 if (dev_flow->hash_fields == 0)
10958 * There is no match between the RSS types and the
10959 * L3 protocol (IPv4/IPv6) defined in the flow rule.
10962 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10963 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10964 if (rss_types & RTE_ETH_RSS_UDP) {
10965 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10966 dev_flow->hash_fields |=
10967 IBV_RX_HASH_SRC_PORT_UDP;
10968 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10969 dev_flow->hash_fields |=
10970 IBV_RX_HASH_DST_PORT_UDP;
10972 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10974 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10975 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10976 if (rss_types & RTE_ETH_RSS_TCP) {
10977 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10978 dev_flow->hash_fields |=
10979 IBV_RX_HASH_SRC_PORT_TCP;
10980 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10981 dev_flow->hash_fields |=
10982 IBV_RX_HASH_DST_PORT_TCP;
10984 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10988 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
10992 * Prepare an Rx Hash queue.
10995 * Pointer to Ethernet device.
10996 * @param[in] dev_flow
10997 * Pointer to the mlx5_flow.
10998 * @param[in] rss_desc
10999 * Pointer to the mlx5_flow_rss_desc.
11000 * @param[out] hrxq_idx
11001 * Hash Rx queue index.
11004 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11006 static struct mlx5_hrxq *
11007 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11008 struct mlx5_flow *dev_flow,
11009 struct mlx5_flow_rss_desc *rss_desc,
11010 uint32_t *hrxq_idx)
11012 struct mlx5_priv *priv = dev->data->dev_private;
11013 struct mlx5_flow_handle *dh = dev_flow->handle;
11014 struct mlx5_hrxq *hrxq;
11016 MLX5_ASSERT(rss_desc->queue_num);
11017 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11018 rss_desc->hash_fields = dev_flow->hash_fields;
11019 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11020 rss_desc->shared_rss = 0;
11021 if (rss_desc->hash_fields == 0)
11022 rss_desc->queue_num = 1;
11023 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11026 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11032 * Release sample sub action resource.
11034 * @param[in, out] dev
11035 * Pointer to rte_eth_dev structure.
11036 * @param[in] act_res
11037 * Pointer to sample sub action resource.
11040 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11041 struct mlx5_flow_sub_actions_idx *act_res)
11043 if (act_res->rix_hrxq) {
11044 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11045 act_res->rix_hrxq = 0;
11047 if (act_res->rix_encap_decap) {
11048 flow_dv_encap_decap_resource_release(dev,
11049 act_res->rix_encap_decap);
11050 act_res->rix_encap_decap = 0;
11052 if (act_res->rix_port_id_action) {
11053 flow_dv_port_id_action_resource_release(dev,
11054 act_res->rix_port_id_action);
11055 act_res->rix_port_id_action = 0;
11057 if (act_res->rix_tag) {
11058 flow_dv_tag_release(dev, act_res->rix_tag);
11059 act_res->rix_tag = 0;
11061 if (act_res->rix_jump) {
11062 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11063 act_res->rix_jump = 0;
11068 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11069 struct mlx5_list_entry *entry, void *cb_ctx)
11071 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11072 struct rte_eth_dev *dev = ctx->dev;
11073 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11074 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11078 if (ctx_resource->ratio == resource->ratio &&
11079 ctx_resource->ft_type == resource->ft_type &&
11080 ctx_resource->ft_id == resource->ft_id &&
11081 ctx_resource->set_action == resource->set_action &&
11082 !memcmp((void *)&ctx_resource->sample_act,
11083 (void *)&resource->sample_act,
11084 sizeof(struct mlx5_flow_sub_actions_list))) {
11086 * Existing sample action should release the prepared
11087 * sub-actions reference counter.
11089 flow_dv_sample_sub_actions_release(dev,
11090 &ctx_resource->sample_idx);
11096 struct mlx5_list_entry *
11097 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11099 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11100 struct rte_eth_dev *dev = ctx->dev;
11101 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11102 void **sample_dv_actions = ctx_resource->sub_actions;
11103 struct mlx5_flow_dv_sample_resource *resource;
11104 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11105 struct mlx5_priv *priv = dev->data->dev_private;
11106 struct mlx5_dev_ctx_shared *sh = priv->sh;
11107 struct mlx5_flow_tbl_resource *tbl;
11109 const uint32_t next_ft_step = 1;
11110 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11111 uint8_t is_egress = 0;
11112 uint8_t is_transfer = 0;
11113 struct rte_flow_error *error = ctx->error;
11115 /* Register new sample resource. */
11116 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11118 rte_flow_error_set(error, ENOMEM,
11119 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11121 "cannot allocate resource memory");
11124 *resource = *ctx_resource;
11125 /* Create normal path table level */
11126 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11128 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11130 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11131 is_egress, is_transfer,
11132 true, NULL, 0, 0, 0, error);
11134 rte_flow_error_set(error, ENOMEM,
11135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11137 "fail to create normal path table "
11141 resource->normal_path_tbl = tbl;
11142 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11143 if (!sh->default_miss_action) {
11144 rte_flow_error_set(error, ENOMEM,
11145 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11147 "default miss action was not "
11151 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11152 sh->default_miss_action;
11154 /* Create a DR sample action */
11155 sampler_attr.sample_ratio = resource->ratio;
11156 sampler_attr.default_next_table = tbl->obj;
11157 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11158 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11159 &sample_dv_actions[0];
11160 sampler_attr.action = resource->set_action;
11161 if (mlx5_os_flow_dr_create_flow_action_sampler
11162 (&sampler_attr, &resource->verbs_action)) {
11163 rte_flow_error_set(error, ENOMEM,
11164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11165 NULL, "cannot create sample action");
11168 resource->idx = idx;
11169 resource->dev = dev;
11170 return &resource->entry;
11172 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11173 flow_dv_sample_sub_actions_release(dev,
11174 &resource->sample_idx);
11175 if (resource->normal_path_tbl)
11176 flow_dv_tbl_resource_release(MLX5_SH(dev),
11177 resource->normal_path_tbl);
11178 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11183 struct mlx5_list_entry *
11184 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11185 struct mlx5_list_entry *entry __rte_unused,
11188 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11189 struct rte_eth_dev *dev = ctx->dev;
11190 struct mlx5_flow_dv_sample_resource *resource;
11191 struct mlx5_priv *priv = dev->data->dev_private;
11192 struct mlx5_dev_ctx_shared *sh = priv->sh;
11195 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11197 rte_flow_error_set(ctx->error, ENOMEM,
11198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11200 "cannot allocate resource memory");
11203 memcpy(resource, entry, sizeof(*resource));
11204 resource->idx = idx;
11205 resource->dev = dev;
11206 return &resource->entry;
11210 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11211 struct mlx5_list_entry *entry)
11213 struct mlx5_flow_dv_sample_resource *resource =
11214 container_of(entry, typeof(*resource), entry);
11215 struct rte_eth_dev *dev = resource->dev;
11216 struct mlx5_priv *priv = dev->data->dev_private;
11218 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11222 * Find existing sample resource or create and register a new one.
11224 * @param[in, out] dev
11225 * Pointer to rte_eth_dev structure.
11227 * Pointer to sample resource reference.
11228 * @parm[in, out] dev_flow
11229 * Pointer to the dev_flow.
11230 * @param[out] error
11231 * pointer to error structure.
11234 * 0 on success otherwise -errno and errno is set.
11237 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11238 struct mlx5_flow_dv_sample_resource *ref,
11239 struct mlx5_flow *dev_flow,
11240 struct rte_flow_error *error)
11242 struct mlx5_flow_dv_sample_resource *resource;
11243 struct mlx5_list_entry *entry;
11244 struct mlx5_priv *priv = dev->data->dev_private;
11245 struct mlx5_flow_cb_ctx ctx = {
11251 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11254 resource = container_of(entry, typeof(*resource), entry);
11255 dev_flow->handle->dvh.rix_sample = resource->idx;
11256 dev_flow->dv.sample_res = resource;
11261 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11262 struct mlx5_list_entry *entry, void *cb_ctx)
11264 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11265 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11266 struct rte_eth_dev *dev = ctx->dev;
11267 struct mlx5_flow_dv_dest_array_resource *resource =
11268 container_of(entry, typeof(*resource), entry);
11271 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11272 ctx_resource->ft_type == resource->ft_type &&
11273 !memcmp((void *)resource->sample_act,
11274 (void *)ctx_resource->sample_act,
11275 (ctx_resource->num_of_dest *
11276 sizeof(struct mlx5_flow_sub_actions_list)))) {
11278 * Existing sample action should release the prepared
11279 * sub-actions reference counter.
11281 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11282 flow_dv_sample_sub_actions_release(dev,
11283 &ctx_resource->sample_idx[idx]);
11289 struct mlx5_list_entry *
11290 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11292 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11293 struct rte_eth_dev *dev = ctx->dev;
11294 struct mlx5_flow_dv_dest_array_resource *resource;
11295 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11296 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11297 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11298 struct mlx5_priv *priv = dev->data->dev_private;
11299 struct mlx5_dev_ctx_shared *sh = priv->sh;
11300 struct mlx5_flow_sub_actions_list *sample_act;
11301 struct mlx5dv_dr_domain *domain;
11302 uint32_t idx = 0, res_idx = 0;
11303 struct rte_flow_error *error = ctx->error;
11304 uint64_t action_flags;
11307 /* Register new destination array resource. */
11308 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11311 rte_flow_error_set(error, ENOMEM,
11312 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11314 "cannot allocate resource memory");
11317 *resource = *ctx_resource;
11318 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11319 domain = sh->fdb_domain;
11320 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11321 domain = sh->rx_domain;
11323 domain = sh->tx_domain;
11324 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11325 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11326 mlx5_malloc(MLX5_MEM_ZERO,
11327 sizeof(struct mlx5dv_dr_action_dest_attr),
11329 if (!dest_attr[idx]) {
11330 rte_flow_error_set(error, ENOMEM,
11331 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11333 "cannot allocate resource memory");
11336 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11337 sample_act = &ctx_resource->sample_act[idx];
11338 action_flags = sample_act->action_flags;
11339 switch (action_flags) {
11340 case MLX5_FLOW_ACTION_QUEUE:
11341 dest_attr[idx]->dest = sample_act->dr_queue_action;
11343 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11344 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11345 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11346 dest_attr[idx]->dest_reformat->reformat =
11347 sample_act->dr_encap_action;
11348 dest_attr[idx]->dest_reformat->dest =
11349 sample_act->dr_port_id_action;
11351 case MLX5_FLOW_ACTION_PORT_ID:
11352 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11354 case MLX5_FLOW_ACTION_JUMP:
11355 dest_attr[idx]->dest = sample_act->dr_jump_action;
11358 rte_flow_error_set(error, EINVAL,
11359 RTE_FLOW_ERROR_TYPE_ACTION,
11361 "unsupported actions type");
11365 /* create a dest array actioin */
11366 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11368 resource->num_of_dest,
11370 &resource->action);
11372 rte_flow_error_set(error, ENOMEM,
11373 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11375 "cannot create destination array action");
11378 resource->idx = res_idx;
11379 resource->dev = dev;
11380 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11381 mlx5_free(dest_attr[idx]);
11382 return &resource->entry;
11384 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11385 flow_dv_sample_sub_actions_release(dev,
11386 &resource->sample_idx[idx]);
11387 if (dest_attr[idx])
11388 mlx5_free(dest_attr[idx]);
11390 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11394 struct mlx5_list_entry *
11395 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11396 struct mlx5_list_entry *entry __rte_unused,
11399 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11400 struct rte_eth_dev *dev = ctx->dev;
11401 struct mlx5_flow_dv_dest_array_resource *resource;
11402 struct mlx5_priv *priv = dev->data->dev_private;
11403 struct mlx5_dev_ctx_shared *sh = priv->sh;
11404 uint32_t res_idx = 0;
11405 struct rte_flow_error *error = ctx->error;
11407 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11410 rte_flow_error_set(error, ENOMEM,
11411 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11413 "cannot allocate dest-array memory");
11416 memcpy(resource, entry, sizeof(*resource));
11417 resource->idx = res_idx;
11418 resource->dev = dev;
11419 return &resource->entry;
11423 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11424 struct mlx5_list_entry *entry)
11426 struct mlx5_flow_dv_dest_array_resource *resource =
11427 container_of(entry, typeof(*resource), entry);
11428 struct rte_eth_dev *dev = resource->dev;
11429 struct mlx5_priv *priv = dev->data->dev_private;
11431 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11435 * Find existing destination array resource or create and register a new one.
11437 * @param[in, out] dev
11438 * Pointer to rte_eth_dev structure.
11440 * Pointer to destination array resource reference.
11441 * @parm[in, out] dev_flow
11442 * Pointer to the dev_flow.
11443 * @param[out] error
11444 * pointer to error structure.
11447 * 0 on success otherwise -errno and errno is set.
11450 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11451 struct mlx5_flow_dv_dest_array_resource *ref,
11452 struct mlx5_flow *dev_flow,
11453 struct rte_flow_error *error)
11455 struct mlx5_flow_dv_dest_array_resource *resource;
11456 struct mlx5_priv *priv = dev->data->dev_private;
11457 struct mlx5_list_entry *entry;
11458 struct mlx5_flow_cb_ctx ctx = {
11464 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11467 resource = container_of(entry, typeof(*resource), entry);
11468 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11469 dev_flow->dv.dest_array_res = resource;
11474 * Convert Sample action to DV specification.
11477 * Pointer to rte_eth_dev structure.
11478 * @param[in] action
11479 * Pointer to sample action structure.
11480 * @param[in, out] dev_flow
11481 * Pointer to the mlx5_flow.
11483 * Pointer to the flow attributes.
11484 * @param[in, out] num_of_dest
11485 * Pointer to the num of destination.
11486 * @param[in, out] sample_actions
11487 * Pointer to sample actions list.
11488 * @param[in, out] res
11489 * Pointer to sample resource.
11490 * @param[out] error
11491 * Pointer to the error structure.
11494 * 0 on success, a negative errno value otherwise and rte_errno is set.
11497 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11498 const struct rte_flow_action_sample *action,
11499 struct mlx5_flow *dev_flow,
11500 const struct rte_flow_attr *attr,
11501 uint32_t *num_of_dest,
11502 void **sample_actions,
11503 struct mlx5_flow_dv_sample_resource *res,
11504 struct rte_flow_error *error)
11506 struct mlx5_priv *priv = dev->data->dev_private;
11507 const struct rte_flow_action *sub_actions;
11508 struct mlx5_flow_sub_actions_list *sample_act;
11509 struct mlx5_flow_sub_actions_idx *sample_idx;
11510 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11511 struct rte_flow *flow = dev_flow->flow;
11512 struct mlx5_flow_rss_desc *rss_desc;
11513 uint64_t action_flags = 0;
11516 rss_desc = &wks->rss_desc;
11517 sample_act = &res->sample_act;
11518 sample_idx = &res->sample_idx;
11519 res->ratio = action->ratio;
11520 sub_actions = action->actions;
11521 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11522 int type = sub_actions->type;
11523 uint32_t pre_rix = 0;
11526 case RTE_FLOW_ACTION_TYPE_QUEUE:
11528 const struct rte_flow_action_queue *queue;
11529 struct mlx5_hrxq *hrxq;
11532 queue = sub_actions->conf;
11533 rss_desc->queue_num = 1;
11534 rss_desc->queue[0] = queue->index;
11535 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11536 rss_desc, &hrxq_idx);
11538 return rte_flow_error_set
11540 RTE_FLOW_ERROR_TYPE_ACTION,
11542 "cannot create fate queue");
11543 sample_act->dr_queue_action = hrxq->action;
11544 sample_idx->rix_hrxq = hrxq_idx;
11545 sample_actions[sample_act->actions_num++] =
11548 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11549 if (action_flags & MLX5_FLOW_ACTION_MARK)
11550 dev_flow->handle->rix_hrxq = hrxq_idx;
11551 dev_flow->handle->fate_action =
11552 MLX5_FLOW_FATE_QUEUE;
11555 case RTE_FLOW_ACTION_TYPE_RSS:
11557 struct mlx5_hrxq *hrxq;
11559 const struct rte_flow_action_rss *rss;
11560 const uint8_t *rss_key;
11562 rss = sub_actions->conf;
11563 memcpy(rss_desc->queue, rss->queue,
11564 rss->queue_num * sizeof(uint16_t));
11565 rss_desc->queue_num = rss->queue_num;
11566 /* NULL RSS key indicates default RSS key. */
11567 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11568 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11570 * rss->level and rss.types should be set in advance
11571 * when expanding items for RSS.
11573 flow_dv_hashfields_set(dev_flow, rss_desc);
11574 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11575 rss_desc, &hrxq_idx);
11577 return rte_flow_error_set
11579 RTE_FLOW_ERROR_TYPE_ACTION,
11581 "cannot create fate queue");
11582 sample_act->dr_queue_action = hrxq->action;
11583 sample_idx->rix_hrxq = hrxq_idx;
11584 sample_actions[sample_act->actions_num++] =
11587 action_flags |= MLX5_FLOW_ACTION_RSS;
11588 if (action_flags & MLX5_FLOW_ACTION_MARK)
11589 dev_flow->handle->rix_hrxq = hrxq_idx;
11590 dev_flow->handle->fate_action =
11591 MLX5_FLOW_FATE_QUEUE;
11594 case RTE_FLOW_ACTION_TYPE_MARK:
11596 uint32_t tag_be = mlx5_flow_mark_set
11597 (((const struct rte_flow_action_mark *)
11598 (sub_actions->conf))->id);
11600 dev_flow->handle->mark = 1;
11601 pre_rix = dev_flow->handle->dvh.rix_tag;
11602 /* Save the mark resource before sample */
11603 pre_r = dev_flow->dv.tag_resource;
11604 if (flow_dv_tag_resource_register(dev, tag_be,
11607 MLX5_ASSERT(dev_flow->dv.tag_resource);
11608 sample_act->dr_tag_action =
11609 dev_flow->dv.tag_resource->action;
11610 sample_idx->rix_tag =
11611 dev_flow->handle->dvh.rix_tag;
11612 sample_actions[sample_act->actions_num++] =
11613 sample_act->dr_tag_action;
11614 /* Recover the mark resource after sample */
11615 dev_flow->dv.tag_resource = pre_r;
11616 dev_flow->handle->dvh.rix_tag = pre_rix;
11617 action_flags |= MLX5_FLOW_ACTION_MARK;
11620 case RTE_FLOW_ACTION_TYPE_COUNT:
11622 if (!flow->counter) {
11624 flow_dv_translate_create_counter(dev,
11625 dev_flow, sub_actions->conf,
11627 if (!flow->counter)
11628 return rte_flow_error_set
11630 RTE_FLOW_ERROR_TYPE_ACTION,
11632 "cannot create counter"
11635 sample_act->dr_cnt_action =
11636 (flow_dv_counter_get_by_idx(dev,
11637 flow->counter, NULL))->action;
11638 sample_actions[sample_act->actions_num++] =
11639 sample_act->dr_cnt_action;
11640 action_flags |= MLX5_FLOW_ACTION_COUNT;
11643 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11644 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11646 struct mlx5_flow_dv_port_id_action_resource
11648 uint32_t port_id = 0;
11650 memset(&port_id_resource, 0, sizeof(port_id_resource));
11651 /* Save the port id resource before sample */
11652 pre_rix = dev_flow->handle->rix_port_id_action;
11653 pre_r = dev_flow->dv.port_id_action;
11654 if (flow_dv_translate_action_port_id(dev, sub_actions,
11657 port_id_resource.port_id = port_id;
11658 if (flow_dv_port_id_action_resource_register
11659 (dev, &port_id_resource, dev_flow, error))
11661 sample_act->dr_port_id_action =
11662 dev_flow->dv.port_id_action->action;
11663 sample_idx->rix_port_id_action =
11664 dev_flow->handle->rix_port_id_action;
11665 sample_actions[sample_act->actions_num++] =
11666 sample_act->dr_port_id_action;
11667 /* Recover the port id resource after sample */
11668 dev_flow->dv.port_id_action = pre_r;
11669 dev_flow->handle->rix_port_id_action = pre_rix;
11671 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11674 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11675 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11676 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11677 /* Save the encap resource before sample */
11678 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11679 pre_r = dev_flow->dv.encap_decap;
11680 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11685 sample_act->dr_encap_action =
11686 dev_flow->dv.encap_decap->action;
11687 sample_idx->rix_encap_decap =
11688 dev_flow->handle->dvh.rix_encap_decap;
11689 sample_actions[sample_act->actions_num++] =
11690 sample_act->dr_encap_action;
11691 /* Recover the encap resource after sample */
11692 dev_flow->dv.encap_decap = pre_r;
11693 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11694 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11697 return rte_flow_error_set(error, EINVAL,
11698 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11700 "Not support for sampler action");
11703 sample_act->action_flags = action_flags;
11704 res->ft_id = dev_flow->dv.group;
11705 if (attr->transfer) {
11707 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11708 uint64_t set_action;
11709 } action_ctx = { .set_action = 0 };
11711 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11712 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11713 MLX5_MODIFICATION_TYPE_SET);
11714 MLX5_SET(set_action_in, action_ctx.action_in, field,
11715 MLX5_MODI_META_REG_C_0);
11716 MLX5_SET(set_action_in, action_ctx.action_in, data,
11717 priv->vport_meta_tag);
11718 res->set_action = action_ctx.set_action;
11719 } else if (attr->ingress) {
11720 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11722 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11728 * Convert Sample action to DV specification.
11731 * Pointer to rte_eth_dev structure.
11732 * @param[in, out] dev_flow
11733 * Pointer to the mlx5_flow.
11734 * @param[in] num_of_dest
11735 * The num of destination.
11736 * @param[in, out] res
11737 * Pointer to sample resource.
11738 * @param[in, out] mdest_res
11739 * Pointer to destination array resource.
11740 * @param[in] sample_actions
11741 * Pointer to sample path actions list.
11742 * @param[in] action_flags
11743 * Holds the actions detected until now.
11744 * @param[out] error
11745 * Pointer to the error structure.
11748 * 0 on success, a negative errno value otherwise and rte_errno is set.
11751 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11752 struct mlx5_flow *dev_flow,
11753 uint32_t num_of_dest,
11754 struct mlx5_flow_dv_sample_resource *res,
11755 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11756 void **sample_actions,
11757 uint64_t action_flags,
11758 struct rte_flow_error *error)
11760 /* update normal path action resource into last index of array */
11761 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11762 struct mlx5_flow_sub_actions_list *sample_act =
11763 &mdest_res->sample_act[dest_index];
11764 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11765 struct mlx5_flow_rss_desc *rss_desc;
11766 uint32_t normal_idx = 0;
11767 struct mlx5_hrxq *hrxq;
11771 rss_desc = &wks->rss_desc;
11772 if (num_of_dest > 1) {
11773 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11774 /* Handle QP action for mirroring */
11775 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11776 rss_desc, &hrxq_idx);
11778 return rte_flow_error_set
11780 RTE_FLOW_ERROR_TYPE_ACTION,
11782 "cannot create rx queue");
11784 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11785 sample_act->dr_queue_action = hrxq->action;
11786 if (action_flags & MLX5_FLOW_ACTION_MARK)
11787 dev_flow->handle->rix_hrxq = hrxq_idx;
11788 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11790 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11792 mdest_res->sample_idx[dest_index].rix_encap_decap =
11793 dev_flow->handle->dvh.rix_encap_decap;
11794 sample_act->dr_encap_action =
11795 dev_flow->dv.encap_decap->action;
11796 dev_flow->handle->dvh.rix_encap_decap = 0;
11798 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11800 mdest_res->sample_idx[dest_index].rix_port_id_action =
11801 dev_flow->handle->rix_port_id_action;
11802 sample_act->dr_port_id_action =
11803 dev_flow->dv.port_id_action->action;
11804 dev_flow->handle->rix_port_id_action = 0;
11806 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11808 mdest_res->sample_idx[dest_index].rix_jump =
11809 dev_flow->handle->rix_jump;
11810 sample_act->dr_jump_action =
11811 dev_flow->dv.jump->action;
11812 dev_flow->handle->rix_jump = 0;
11814 sample_act->actions_num = normal_idx;
11815 /* update sample action resource into first index of array */
11816 mdest_res->ft_type = res->ft_type;
11817 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11818 sizeof(struct mlx5_flow_sub_actions_idx));
11819 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11820 sizeof(struct mlx5_flow_sub_actions_list));
11821 mdest_res->num_of_dest = num_of_dest;
11822 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11824 return rte_flow_error_set(error, EINVAL,
11825 RTE_FLOW_ERROR_TYPE_ACTION,
11826 NULL, "can't create sample "
11829 res->sub_actions = sample_actions;
11830 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11831 return rte_flow_error_set(error, EINVAL,
11832 RTE_FLOW_ERROR_TYPE_ACTION,
11834 "can't create sample action");
11840 * Remove an ASO age action from age actions list.
11843 * Pointer to the Ethernet device structure.
11845 * Pointer to the aso age action handler.
11848 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11849 struct mlx5_aso_age_action *age)
11851 struct mlx5_age_info *age_info;
11852 struct mlx5_age_param *age_param = &age->age_params;
11853 struct mlx5_priv *priv = dev->data->dev_private;
11854 uint16_t expected = AGE_CANDIDATE;
11856 age_info = GET_PORT_AGE_INFO(priv);
11857 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11858 AGE_FREE, false, __ATOMIC_RELAXED,
11859 __ATOMIC_RELAXED)) {
11861 * We need the lock even it is age timeout,
11862 * since age action may still in process.
11864 rte_spinlock_lock(&age_info->aged_sl);
11865 LIST_REMOVE(age, next);
11866 rte_spinlock_unlock(&age_info->aged_sl);
11867 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11872 * Release an ASO age action.
11875 * Pointer to the Ethernet device structure.
11876 * @param[in] age_idx
11877 * Index of ASO age action to release.
11879 * True if the release operation is during flow destroy operation.
11880 * False if the release operation is during action destroy operation.
11883 * 0 when age action was removed, otherwise the number of references.
11886 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11888 struct mlx5_priv *priv = dev->data->dev_private;
11889 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11890 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11891 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11894 flow_dv_aso_age_remove_from_age(dev, age);
11895 rte_spinlock_lock(&mng->free_sl);
11896 LIST_INSERT_HEAD(&mng->free, age, next);
11897 rte_spinlock_unlock(&mng->free_sl);
11903 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11906 * Pointer to the Ethernet device structure.
11909 * 0 on success, otherwise negative errno value and rte_errno is set.
11912 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11914 struct mlx5_priv *priv = dev->data->dev_private;
11915 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11916 void *old_pools = mng->pools;
11917 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11918 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11919 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11922 rte_errno = ENOMEM;
11926 memcpy(pools, old_pools,
11927 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11928 mlx5_free(old_pools);
11930 /* First ASO flow hit allocation - starting ASO data-path. */
11931 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11939 mng->pools = pools;
11944 * Create and initialize a new ASO aging pool.
11947 * Pointer to the Ethernet device structure.
11948 * @param[out] age_free
11949 * Where to put the pointer of a new age action.
11952 * The age actions pool pointer and @p age_free is set on success,
11953 * NULL otherwise and rte_errno is set.
11955 static struct mlx5_aso_age_pool *
11956 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11957 struct mlx5_aso_age_action **age_free)
11959 struct mlx5_priv *priv = dev->data->dev_private;
11960 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11961 struct mlx5_aso_age_pool *pool = NULL;
11962 struct mlx5_devx_obj *obj = NULL;
11965 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
11966 priv->sh->cdev->pdn);
11968 rte_errno = ENODATA;
11969 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11972 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11974 claim_zero(mlx5_devx_cmd_destroy(obj));
11975 rte_errno = ENOMEM;
11978 pool->flow_hit_aso_obj = obj;
11979 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
11980 rte_rwlock_write_lock(&mng->resize_rwl);
11981 pool->index = mng->next;
11982 /* Resize pools array if there is no room for the new pool in it. */
11983 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
11984 claim_zero(mlx5_devx_cmd_destroy(obj));
11986 rte_rwlock_write_unlock(&mng->resize_rwl);
11989 mng->pools[pool->index] = pool;
11991 rte_rwlock_write_unlock(&mng->resize_rwl);
11992 /* Assign the first action in the new pool, the rest go to free list. */
11993 *age_free = &pool->actions[0];
11994 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
11995 pool->actions[i].offset = i;
11996 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12002 * Allocate a ASO aging bit.
12005 * Pointer to the Ethernet device structure.
12006 * @param[out] error
12007 * Pointer to the error structure.
12010 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12013 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12015 struct mlx5_priv *priv = dev->data->dev_private;
12016 const struct mlx5_aso_age_pool *pool;
12017 struct mlx5_aso_age_action *age_free = NULL;
12018 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12021 /* Try to get the next free age action bit. */
12022 rte_spinlock_lock(&mng->free_sl);
12023 age_free = LIST_FIRST(&mng->free);
12025 LIST_REMOVE(age_free, next);
12026 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12027 rte_spinlock_unlock(&mng->free_sl);
12028 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12029 NULL, "failed to create ASO age pool");
12030 return 0; /* 0 is an error. */
12032 rte_spinlock_unlock(&mng->free_sl);
12033 pool = container_of
12034 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12035 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12037 if (!age_free->dr_action) {
12038 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12042 rte_flow_error_set(error, rte_errno,
12043 RTE_FLOW_ERROR_TYPE_ACTION,
12044 NULL, "failed to get reg_c "
12045 "for ASO flow hit");
12046 return 0; /* 0 is an error. */
12048 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12049 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12050 (priv->sh->rx_domain,
12051 pool->flow_hit_aso_obj->obj, age_free->offset,
12052 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12053 (reg_c - REG_C_0));
12054 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12055 if (!age_free->dr_action) {
12057 rte_spinlock_lock(&mng->free_sl);
12058 LIST_INSERT_HEAD(&mng->free, age_free, next);
12059 rte_spinlock_unlock(&mng->free_sl);
12060 rte_flow_error_set(error, rte_errno,
12061 RTE_FLOW_ERROR_TYPE_ACTION,
12062 NULL, "failed to create ASO "
12063 "flow hit action");
12064 return 0; /* 0 is an error. */
12067 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12068 return pool->index | ((age_free->offset + 1) << 16);
12072 * Initialize flow ASO age parameters.
12075 * Pointer to rte_eth_dev structure.
12076 * @param[in] age_idx
12077 * Index of ASO age action.
12078 * @param[in] context
12079 * Pointer to flow counter age context.
12080 * @param[in] timeout
12081 * Aging timeout in seconds.
12085 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12090 struct mlx5_aso_age_action *aso_age;
12092 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12093 MLX5_ASSERT(aso_age);
12094 aso_age->age_params.context = context;
12095 aso_age->age_params.timeout = timeout;
12096 aso_age->age_params.port_id = dev->data->port_id;
12097 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12099 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12104 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12105 const struct rte_flow_item_integrity *value,
12106 void *headers_m, void *headers_v)
12109 /* RTE l4_ok filter aggregates hardware l4_ok and
12110 * l4_checksum_ok filters.
12111 * Positive RTE l4_ok match requires hardware match on both L4
12112 * hardware integrity bits.
12113 * For negative match, check hardware l4_checksum_ok bit only,
12114 * because hardware sets that bit to 0 for all packets
12117 if (value->l4_ok) {
12118 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12119 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12121 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12122 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12125 if (mask->l4_csum_ok) {
12126 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12127 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12128 value->l4_csum_ok);
12133 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12134 const struct rte_flow_item_integrity *value,
12135 void *headers_m, void *headers_v, bool is_ipv4)
12138 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12139 * ipv4_csum_ok filters.
12140 * Positive RTE l3_ok match requires hardware match on both L3
12141 * hardware integrity bits.
12142 * For negative match, check hardware l3_csum_ok bit only,
12143 * because hardware sets that bit to 0 for all packets
12147 if (value->l3_ok) {
12148 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12150 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12153 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12154 ipv4_checksum_ok, 1);
12155 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12156 ipv4_checksum_ok, !!value->l3_ok);
12158 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12159 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12163 if (mask->ipv4_csum_ok) {
12164 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12165 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12166 value->ipv4_csum_ok);
12171 set_integrity_bits(void *headers_m, void *headers_v,
12172 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12174 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12175 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12177 /* Integrity bits validation cleared spec pointer */
12178 MLX5_ASSERT(spec != NULL);
12180 mask = &rte_flow_item_integrity_mask;
12181 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12183 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12187 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12189 struct rte_flow_item *integrity_items[2],
12190 uint64_t pattern_flags)
12192 void *headers_m, *headers_v;
12195 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12196 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12198 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12199 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12201 set_integrity_bits(headers_m, headers_v,
12202 integrity_items[1], is_l3_ip4);
12204 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12205 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12207 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12208 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12210 set_integrity_bits(headers_m, headers_v,
12211 integrity_items[0], is_l3_ip4);
12216 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12217 const struct rte_flow_item *integrity_items[2],
12218 uint64_t *last_item)
12220 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12222 /* integrity bits validation cleared spec pointer */
12223 MLX5_ASSERT(spec != NULL);
12224 if (spec->level > 1) {
12225 integrity_items[1] = item;
12226 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12228 integrity_items[0] = item;
12229 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12234 * Prepares DV flow counter with aging configuration.
12235 * Gets it by index when exists, creates a new one when doesn't.
12238 * Pointer to rte_eth_dev structure.
12239 * @param[in] dev_flow
12240 * Pointer to the mlx5_flow.
12241 * @param[in, out] flow
12242 * Pointer to the sub flow.
12244 * Pointer to the counter action configuration.
12246 * Pointer to the aging action configuration.
12247 * @param[out] error
12248 * Pointer to the error structure.
12251 * Pointer to the counter, NULL otherwise.
12253 static struct mlx5_flow_counter *
12254 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12255 struct mlx5_flow *dev_flow,
12256 struct rte_flow *flow,
12257 const struct rte_flow_action_count *count,
12258 const struct rte_flow_action_age *age,
12259 struct rte_flow_error *error)
12261 if (!flow->counter) {
12262 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12264 if (!flow->counter) {
12265 rte_flow_error_set(error, rte_errno,
12266 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12267 "cannot create counter object.");
12271 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12275 * Release an ASO CT action by its own device.
12278 * Pointer to the Ethernet device structure.
12280 * Index of ASO CT action to release.
12283 * 0 when CT action was removed, otherwise the number of references.
12286 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12288 struct mlx5_priv *priv = dev->data->dev_private;
12289 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12291 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12292 enum mlx5_aso_ct_state state =
12293 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12295 /* Cannot release when CT is in the ASO SQ. */
12296 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12298 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12300 if (ct->dr_action_orig) {
12301 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12302 claim_zero(mlx5_glue->destroy_flow_action
12303 (ct->dr_action_orig));
12305 ct->dr_action_orig = NULL;
12307 if (ct->dr_action_rply) {
12308 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12309 claim_zero(mlx5_glue->destroy_flow_action
12310 (ct->dr_action_rply));
12312 ct->dr_action_rply = NULL;
12314 /* Clear the state to free, no need in 1st allocation. */
12315 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12316 rte_spinlock_lock(&mng->ct_sl);
12317 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12318 rte_spinlock_unlock(&mng->ct_sl);
12324 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12325 struct rte_flow_error *error)
12327 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12328 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12329 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12332 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12333 if (dev->data->dev_started != 1)
12334 return rte_flow_error_set(error, EAGAIN,
12335 RTE_FLOW_ERROR_TYPE_ACTION,
12337 "Indirect CT action cannot be destroyed when the port is stopped");
12338 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12340 return rte_flow_error_set(error, EAGAIN,
12341 RTE_FLOW_ERROR_TYPE_ACTION,
12343 "Current state prevents indirect CT action from being destroyed");
12348 * Resize the ASO CT pools array by 64 pools.
12351 * Pointer to the Ethernet device structure.
12354 * 0 on success, otherwise negative errno value and rte_errno is set.
12357 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12359 struct mlx5_priv *priv = dev->data->dev_private;
12360 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12361 void *old_pools = mng->pools;
12362 /* Magic number now, need a macro. */
12363 uint32_t resize = mng->n + 64;
12364 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12365 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12368 rte_errno = ENOMEM;
12371 rte_rwlock_write_lock(&mng->resize_rwl);
12372 /* ASO SQ/QP was already initialized in the startup. */
12374 /* Realloc could be an alternative choice. */
12375 rte_memcpy(pools, old_pools,
12376 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12377 mlx5_free(old_pools);
12380 mng->pools = pools;
12381 rte_rwlock_write_unlock(&mng->resize_rwl);
12386 * Create and initialize a new ASO CT pool.
12389 * Pointer to the Ethernet device structure.
12390 * @param[out] ct_free
12391 * Where to put the pointer of a new CT action.
12394 * The CT actions pool pointer and @p ct_free is set on success,
12395 * NULL otherwise and rte_errno is set.
12397 static struct mlx5_aso_ct_pool *
12398 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12399 struct mlx5_aso_ct_action **ct_free)
12401 struct mlx5_priv *priv = dev->data->dev_private;
12402 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12403 struct mlx5_aso_ct_pool *pool = NULL;
12404 struct mlx5_devx_obj *obj = NULL;
12406 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12408 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12409 priv->sh->cdev->pdn,
12412 rte_errno = ENODATA;
12413 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12416 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12418 rte_errno = ENOMEM;
12419 claim_zero(mlx5_devx_cmd_destroy(obj));
12422 pool->devx_obj = obj;
12423 pool->index = mng->next;
12424 /* Resize pools array if there is no room for the new pool in it. */
12425 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12426 claim_zero(mlx5_devx_cmd_destroy(obj));
12430 mng->pools[pool->index] = pool;
12432 /* Assign the first action in the new pool, the rest go to free list. */
12433 *ct_free = &pool->actions[0];
12434 /* Lock outside, the list operation is safe here. */
12435 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12436 /* refcnt is 0 when allocating the memory. */
12437 pool->actions[i].offset = i;
12438 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12444 * Allocate a ASO CT action from free list.
12447 * Pointer to the Ethernet device structure.
12448 * @param[out] error
12449 * Pointer to the error structure.
12452 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12455 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12457 struct mlx5_priv *priv = dev->data->dev_private;
12458 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12459 struct mlx5_aso_ct_action *ct = NULL;
12460 struct mlx5_aso_ct_pool *pool;
12465 if (!priv->sh->devx) {
12466 rte_errno = ENOTSUP;
12469 /* Get a free CT action, if no, a new pool will be created. */
12470 rte_spinlock_lock(&mng->ct_sl);
12471 ct = LIST_FIRST(&mng->free_cts);
12473 LIST_REMOVE(ct, next);
12474 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12475 rte_spinlock_unlock(&mng->ct_sl);
12476 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12477 NULL, "failed to create ASO CT pool");
12480 rte_spinlock_unlock(&mng->ct_sl);
12481 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12482 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12483 /* 0: inactive, 1: created, 2+: used by flows. */
12484 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12485 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12486 if (!ct->dr_action_orig) {
12487 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12488 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12489 (priv->sh->rx_domain, pool->devx_obj->obj,
12491 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12494 RTE_SET_USED(reg_c);
12496 if (!ct->dr_action_orig) {
12497 flow_dv_aso_ct_dev_release(dev, ct_idx);
12498 rte_flow_error_set(error, rte_errno,
12499 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12500 "failed to create ASO CT action");
12504 if (!ct->dr_action_rply) {
12505 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12506 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12507 (priv->sh->rx_domain, pool->devx_obj->obj,
12509 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12512 if (!ct->dr_action_rply) {
12513 flow_dv_aso_ct_dev_release(dev, ct_idx);
12514 rte_flow_error_set(error, rte_errno,
12515 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12516 "failed to create ASO CT action");
12524 * Create a conntrack object with context and actions by using ASO mechanism.
12527 * Pointer to rte_eth_dev structure.
12529 * Pointer to conntrack information profile.
12530 * @param[out] error
12531 * Pointer to the error structure.
12534 * Index to conntrack object on success, 0 otherwise.
12537 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12538 const struct rte_flow_action_conntrack *pro,
12539 struct rte_flow_error *error)
12541 struct mlx5_priv *priv = dev->data->dev_private;
12542 struct mlx5_dev_ctx_shared *sh = priv->sh;
12543 struct mlx5_aso_ct_action *ct;
12546 if (!sh->ct_aso_en)
12547 return rte_flow_error_set(error, ENOTSUP,
12548 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12549 "Connection is not supported");
12550 idx = flow_dv_aso_ct_alloc(dev, error);
12552 return rte_flow_error_set(error, rte_errno,
12553 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12554 "Failed to allocate CT object");
12555 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12556 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12557 return rte_flow_error_set(error, EBUSY,
12558 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12559 "Failed to update CT");
12560 ct->is_original = !!pro->is_original_dir;
12561 ct->peer = pro->peer_port;
12566 * Fill the flow with DV spec, lock free
12567 * (mutex should be acquired by caller).
12570 * Pointer to rte_eth_dev structure.
12571 * @param[in, out] dev_flow
12572 * Pointer to the sub flow.
12574 * Pointer to the flow attributes.
12576 * Pointer to the list of items.
12577 * @param[in] actions
12578 * Pointer to the list of actions.
12579 * @param[out] error
12580 * Pointer to the error structure.
12583 * 0 on success, a negative errno value otherwise and rte_errno is set.
12586 flow_dv_translate(struct rte_eth_dev *dev,
12587 struct mlx5_flow *dev_flow,
12588 const struct rte_flow_attr *attr,
12589 const struct rte_flow_item items[],
12590 const struct rte_flow_action actions[],
12591 struct rte_flow_error *error)
12593 struct mlx5_priv *priv = dev->data->dev_private;
12594 struct mlx5_dev_config *dev_conf = &priv->config;
12595 struct rte_flow *flow = dev_flow->flow;
12596 struct mlx5_flow_handle *handle = dev_flow->handle;
12597 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12598 struct mlx5_flow_rss_desc *rss_desc;
12599 uint64_t item_flags = 0;
12600 uint64_t last_item = 0;
12601 uint64_t action_flags = 0;
12602 struct mlx5_flow_dv_matcher matcher = {
12604 .size = sizeof(matcher.mask.buf),
12608 bool actions_end = false;
12610 struct mlx5_flow_dv_modify_hdr_resource res;
12611 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12612 sizeof(struct mlx5_modification_cmd) *
12613 (MLX5_MAX_MODIFY_NUM + 1)];
12615 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12616 const struct rte_flow_action_count *count = NULL;
12617 const struct rte_flow_action_age *non_shared_age = NULL;
12618 union flow_dv_attr flow_attr = { .attr = 0 };
12620 union mlx5_flow_tbl_key tbl_key;
12621 uint32_t modify_action_position = UINT32_MAX;
12622 void *match_mask = matcher.mask.buf;
12623 void *match_value = dev_flow->dv.value.buf;
12624 uint8_t next_protocol = 0xff;
12625 struct rte_vlan_hdr vlan = { 0 };
12626 struct mlx5_flow_dv_dest_array_resource mdest_res;
12627 struct mlx5_flow_dv_sample_resource sample_res;
12628 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12629 const struct rte_flow_action_sample *sample = NULL;
12630 struct mlx5_flow_sub_actions_list *sample_act;
12631 uint32_t sample_act_pos = UINT32_MAX;
12632 uint32_t age_act_pos = UINT32_MAX;
12633 uint32_t num_of_dest = 0;
12634 int tmp_actions_n = 0;
12637 const struct mlx5_flow_tunnel *tunnel = NULL;
12638 struct flow_grp_info grp_info = {
12639 .external = !!dev_flow->external,
12640 .transfer = !!attr->transfer,
12641 .fdb_def_rule = !!priv->fdb_def_rule,
12642 .skip_scale = dev_flow->skip_scale &
12643 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12644 .std_tbl_fix = true,
12646 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12649 return rte_flow_error_set(error, ENOMEM,
12650 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12652 "failed to push flow workspace");
12653 rss_desc = &wks->rss_desc;
12654 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12655 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12656 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12657 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12658 /* update normal path action resource into last index of array */
12659 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12660 if (is_tunnel_offload_active(dev)) {
12661 if (dev_flow->tunnel) {
12662 RTE_VERIFY(dev_flow->tof_type ==
12663 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12664 tunnel = dev_flow->tunnel;
12666 tunnel = mlx5_get_tof(items, actions,
12667 &dev_flow->tof_type);
12668 dev_flow->tunnel = tunnel;
12670 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12671 (dev, attr, tunnel, dev_flow->tof_type);
12673 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12674 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12675 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12679 dev_flow->dv.group = table;
12680 if (attr->transfer)
12681 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12682 /* number of actions must be set to 0 in case of dirty stack. */
12683 mhdr_res->actions_num = 0;
12684 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12686 * do not add decap action if match rule drops packet
12687 * HW rejects rules with decap & drop
12689 * if tunnel match rule was inserted before matching tunnel set
12690 * rule flow table used in the match rule must be registered.
12691 * current implementation handles that in the
12692 * flow_dv_match_register() at the function end.
12694 bool add_decap = true;
12695 const struct rte_flow_action *ptr = actions;
12697 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12698 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12704 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12708 dev_flow->dv.actions[actions_n++] =
12709 dev_flow->dv.encap_decap->action;
12710 action_flags |= MLX5_FLOW_ACTION_DECAP;
12713 for (; !actions_end ; actions++) {
12714 const struct rte_flow_action_queue *queue;
12715 const struct rte_flow_action_rss *rss;
12716 const struct rte_flow_action *action = actions;
12717 const uint8_t *rss_key;
12718 struct mlx5_flow_tbl_resource *tbl;
12719 struct mlx5_aso_age_action *age_act;
12720 struct mlx5_flow_counter *cnt_act;
12721 uint32_t port_id = 0;
12722 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12723 int action_type = actions->type;
12724 const struct rte_flow_action *found_action = NULL;
12725 uint32_t jump_group = 0;
12726 uint32_t owner_idx;
12727 struct mlx5_aso_ct_action *ct;
12729 if (!mlx5_flow_os_action_supported(action_type))
12730 return rte_flow_error_set(error, ENOTSUP,
12731 RTE_FLOW_ERROR_TYPE_ACTION,
12733 "action not supported");
12734 switch (action_type) {
12735 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12736 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12738 case RTE_FLOW_ACTION_TYPE_VOID:
12740 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12741 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12742 if (flow_dv_translate_action_port_id(dev, action,
12745 port_id_resource.port_id = port_id;
12746 MLX5_ASSERT(!handle->rix_port_id_action);
12747 if (flow_dv_port_id_action_resource_register
12748 (dev, &port_id_resource, dev_flow, error))
12750 dev_flow->dv.actions[actions_n++] =
12751 dev_flow->dv.port_id_action->action;
12752 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12753 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12754 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12757 case RTE_FLOW_ACTION_TYPE_FLAG:
12758 action_flags |= MLX5_FLOW_ACTION_FLAG;
12759 dev_flow->handle->mark = 1;
12760 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12761 struct rte_flow_action_mark mark = {
12762 .id = MLX5_FLOW_MARK_DEFAULT,
12765 if (flow_dv_convert_action_mark(dev, &mark,
12769 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12772 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12774 * Only one FLAG or MARK is supported per device flow
12775 * right now. So the pointer to the tag resource must be
12776 * zero before the register process.
12778 MLX5_ASSERT(!handle->dvh.rix_tag);
12779 if (flow_dv_tag_resource_register(dev, tag_be,
12782 MLX5_ASSERT(dev_flow->dv.tag_resource);
12783 dev_flow->dv.actions[actions_n++] =
12784 dev_flow->dv.tag_resource->action;
12786 case RTE_FLOW_ACTION_TYPE_MARK:
12787 action_flags |= MLX5_FLOW_ACTION_MARK;
12788 dev_flow->handle->mark = 1;
12789 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12790 const struct rte_flow_action_mark *mark =
12791 (const struct rte_flow_action_mark *)
12794 if (flow_dv_convert_action_mark(dev, mark,
12798 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12802 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12803 /* Legacy (non-extensive) MARK action. */
12804 tag_be = mlx5_flow_mark_set
12805 (((const struct rte_flow_action_mark *)
12806 (actions->conf))->id);
12807 MLX5_ASSERT(!handle->dvh.rix_tag);
12808 if (flow_dv_tag_resource_register(dev, tag_be,
12811 MLX5_ASSERT(dev_flow->dv.tag_resource);
12812 dev_flow->dv.actions[actions_n++] =
12813 dev_flow->dv.tag_resource->action;
12815 case RTE_FLOW_ACTION_TYPE_SET_META:
12816 if (flow_dv_convert_action_set_meta
12817 (dev, mhdr_res, attr,
12818 (const struct rte_flow_action_set_meta *)
12819 actions->conf, error))
12821 action_flags |= MLX5_FLOW_ACTION_SET_META;
12823 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12824 if (flow_dv_convert_action_set_tag
12826 (const struct rte_flow_action_set_tag *)
12827 actions->conf, error))
12829 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12831 case RTE_FLOW_ACTION_TYPE_DROP:
12832 action_flags |= MLX5_FLOW_ACTION_DROP;
12833 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12835 case RTE_FLOW_ACTION_TYPE_QUEUE:
12836 queue = actions->conf;
12837 rss_desc->queue_num = 1;
12838 rss_desc->queue[0] = queue->index;
12839 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12840 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12841 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12844 case RTE_FLOW_ACTION_TYPE_RSS:
12845 rss = actions->conf;
12846 memcpy(rss_desc->queue, rss->queue,
12847 rss->queue_num * sizeof(uint16_t));
12848 rss_desc->queue_num = rss->queue_num;
12849 /* NULL RSS key indicates default RSS key. */
12850 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12851 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12853 * rss->level and rss.types should be set in advance
12854 * when expanding items for RSS.
12856 action_flags |= MLX5_FLOW_ACTION_RSS;
12857 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12858 MLX5_FLOW_FATE_SHARED_RSS :
12859 MLX5_FLOW_FATE_QUEUE;
12861 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12862 owner_idx = (uint32_t)(uintptr_t)action->conf;
12863 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12864 if (flow->age == 0) {
12865 flow->age = owner_idx;
12866 __atomic_fetch_add(&age_act->refcnt, 1,
12869 age_act_pos = actions_n++;
12870 action_flags |= MLX5_FLOW_ACTION_AGE;
12872 case RTE_FLOW_ACTION_TYPE_AGE:
12873 non_shared_age = action->conf;
12874 age_act_pos = actions_n++;
12875 action_flags |= MLX5_FLOW_ACTION_AGE;
12877 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12878 owner_idx = (uint32_t)(uintptr_t)action->conf;
12879 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12881 MLX5_ASSERT(cnt_act != NULL);
12883 * When creating meter drop flow in drop table, the
12884 * counter should not overwrite the rte flow counter.
12886 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12887 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12888 dev_flow->dv.actions[actions_n++] =
12891 if (flow->counter == 0) {
12892 flow->counter = owner_idx;
12894 (&cnt_act->shared_info.refcnt,
12895 1, __ATOMIC_RELAXED);
12897 /* Save information first, will apply later. */
12898 action_flags |= MLX5_FLOW_ACTION_COUNT;
12901 case RTE_FLOW_ACTION_TYPE_COUNT:
12902 if (!priv->sh->devx) {
12903 return rte_flow_error_set
12905 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12907 "count action not supported");
12909 /* Save information first, will apply later. */
12910 count = action->conf;
12911 action_flags |= MLX5_FLOW_ACTION_COUNT;
12913 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12914 dev_flow->dv.actions[actions_n++] =
12915 priv->sh->pop_vlan_action;
12916 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12918 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12919 if (!(action_flags &
12920 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12921 flow_dev_get_vlan_info_from_items(items, &vlan);
12922 vlan.eth_proto = rte_be_to_cpu_16
12923 ((((const struct rte_flow_action_of_push_vlan *)
12924 actions->conf)->ethertype));
12925 found_action = mlx5_flow_find_action
12927 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12929 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12930 found_action = mlx5_flow_find_action
12932 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12934 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12935 if (flow_dv_create_action_push_vlan
12936 (dev, attr, &vlan, dev_flow, error))
12938 dev_flow->dv.actions[actions_n++] =
12939 dev_flow->dv.push_vlan_res->action;
12940 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12942 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12943 /* of_vlan_push action handled this action */
12944 MLX5_ASSERT(action_flags &
12945 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12947 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12948 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12950 flow_dev_get_vlan_info_from_items(items, &vlan);
12951 mlx5_update_vlan_vid_pcp(actions, &vlan);
12952 /* If no VLAN push - this is a modify header action */
12953 if (flow_dv_convert_action_modify_vlan_vid
12954 (mhdr_res, actions, error))
12956 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12958 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12959 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12960 if (flow_dv_create_action_l2_encap(dev, actions,
12965 dev_flow->dv.actions[actions_n++] =
12966 dev_flow->dv.encap_decap->action;
12967 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12968 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12969 sample_act->action_flags |=
12970 MLX5_FLOW_ACTION_ENCAP;
12972 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12973 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12974 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12978 dev_flow->dv.actions[actions_n++] =
12979 dev_flow->dv.encap_decap->action;
12980 action_flags |= MLX5_FLOW_ACTION_DECAP;
12982 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
12983 /* Handle encap with preceding decap. */
12984 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
12985 if (flow_dv_create_action_raw_encap
12986 (dev, actions, dev_flow, attr, error))
12988 dev_flow->dv.actions[actions_n++] =
12989 dev_flow->dv.encap_decap->action;
12991 /* Handle encap without preceding decap. */
12992 if (flow_dv_create_action_l2_encap
12993 (dev, actions, dev_flow, attr->transfer,
12996 dev_flow->dv.actions[actions_n++] =
12997 dev_flow->dv.encap_decap->action;
12999 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13000 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13001 sample_act->action_flags |=
13002 MLX5_FLOW_ACTION_ENCAP;
13004 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13005 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13007 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13008 if (flow_dv_create_action_l2_decap
13009 (dev, dev_flow, attr->transfer, error))
13011 dev_flow->dv.actions[actions_n++] =
13012 dev_flow->dv.encap_decap->action;
13014 /* If decap is followed by encap, handle it at encap. */
13015 action_flags |= MLX5_FLOW_ACTION_DECAP;
13017 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13018 dev_flow->dv.actions[actions_n++] =
13019 (void *)(uintptr_t)action->conf;
13020 action_flags |= MLX5_FLOW_ACTION_JUMP;
13022 case RTE_FLOW_ACTION_TYPE_JUMP:
13023 jump_group = ((const struct rte_flow_action_jump *)
13024 action->conf)->group;
13025 grp_info.std_tbl_fix = 0;
13026 if (dev_flow->skip_scale &
13027 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13028 grp_info.skip_scale = 1;
13030 grp_info.skip_scale = 0;
13031 ret = mlx5_flow_group_to_table(dev, tunnel,
13037 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13039 !!dev_flow->external,
13040 tunnel, jump_group, 0,
13043 return rte_flow_error_set
13045 RTE_FLOW_ERROR_TYPE_ACTION,
13047 "cannot create jump action.");
13048 if (flow_dv_jump_tbl_resource_register
13049 (dev, tbl, dev_flow, error)) {
13050 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13051 return rte_flow_error_set
13053 RTE_FLOW_ERROR_TYPE_ACTION,
13055 "cannot create jump action.");
13057 dev_flow->dv.actions[actions_n++] =
13058 dev_flow->dv.jump->action;
13059 action_flags |= MLX5_FLOW_ACTION_JUMP;
13060 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13061 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13064 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13065 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13066 if (flow_dv_convert_action_modify_mac
13067 (mhdr_res, actions, error))
13069 action_flags |= actions->type ==
13070 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13071 MLX5_FLOW_ACTION_SET_MAC_SRC :
13072 MLX5_FLOW_ACTION_SET_MAC_DST;
13074 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13075 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13076 if (flow_dv_convert_action_modify_ipv4
13077 (mhdr_res, actions, error))
13079 action_flags |= actions->type ==
13080 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13081 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13082 MLX5_FLOW_ACTION_SET_IPV4_DST;
13084 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13085 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13086 if (flow_dv_convert_action_modify_ipv6
13087 (mhdr_res, actions, error))
13089 action_flags |= actions->type ==
13090 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13091 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13092 MLX5_FLOW_ACTION_SET_IPV6_DST;
13094 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13095 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13096 if (flow_dv_convert_action_modify_tp
13097 (mhdr_res, actions, items,
13098 &flow_attr, dev_flow, !!(action_flags &
13099 MLX5_FLOW_ACTION_DECAP), error))
13101 action_flags |= actions->type ==
13102 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13103 MLX5_FLOW_ACTION_SET_TP_SRC :
13104 MLX5_FLOW_ACTION_SET_TP_DST;
13106 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13107 if (flow_dv_convert_action_modify_dec_ttl
13108 (mhdr_res, items, &flow_attr, dev_flow,
13110 MLX5_FLOW_ACTION_DECAP), error))
13112 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13114 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13115 if (flow_dv_convert_action_modify_ttl
13116 (mhdr_res, actions, items, &flow_attr,
13117 dev_flow, !!(action_flags &
13118 MLX5_FLOW_ACTION_DECAP), error))
13120 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13122 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13123 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13124 if (flow_dv_convert_action_modify_tcp_seq
13125 (mhdr_res, actions, error))
13127 action_flags |= actions->type ==
13128 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13129 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13130 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13133 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13134 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13135 if (flow_dv_convert_action_modify_tcp_ack
13136 (mhdr_res, actions, error))
13138 action_flags |= actions->type ==
13139 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13140 MLX5_FLOW_ACTION_INC_TCP_ACK :
13141 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13143 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13144 if (flow_dv_convert_action_set_reg
13145 (mhdr_res, actions, error))
13147 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13149 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13150 if (flow_dv_convert_action_copy_mreg
13151 (dev, mhdr_res, actions, error))
13153 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13155 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13156 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13157 dev_flow->handle->fate_action =
13158 MLX5_FLOW_FATE_DEFAULT_MISS;
13160 case RTE_FLOW_ACTION_TYPE_METER:
13162 return rte_flow_error_set(error, rte_errno,
13163 RTE_FLOW_ERROR_TYPE_ACTION,
13164 NULL, "Failed to get meter in flow.");
13165 /* Set the meter action. */
13166 dev_flow->dv.actions[actions_n++] =
13167 wks->fm->meter_action;
13168 action_flags |= MLX5_FLOW_ACTION_METER;
13170 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13171 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13174 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13176 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13177 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13180 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13182 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13183 sample_act_pos = actions_n;
13184 sample = (const struct rte_flow_action_sample *)
13187 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13188 /* put encap action into group if work with port id */
13189 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13190 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13191 sample_act->action_flags |=
13192 MLX5_FLOW_ACTION_ENCAP;
13194 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13195 if (flow_dv_convert_action_modify_field
13196 (dev, mhdr_res, actions, attr, error))
13198 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13200 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13201 owner_idx = (uint32_t)(uintptr_t)action->conf;
13202 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13204 return rte_flow_error_set(error, EINVAL,
13205 RTE_FLOW_ERROR_TYPE_ACTION,
13207 "Failed to get CT object.");
13208 if (mlx5_aso_ct_available(priv->sh, ct))
13209 return rte_flow_error_set(error, rte_errno,
13210 RTE_FLOW_ERROR_TYPE_ACTION,
13212 "CT is unavailable.");
13213 if (ct->is_original)
13214 dev_flow->dv.actions[actions_n] =
13215 ct->dr_action_orig;
13217 dev_flow->dv.actions[actions_n] =
13218 ct->dr_action_rply;
13219 if (flow->ct == 0) {
13220 flow->indirect_type =
13221 MLX5_INDIRECT_ACTION_TYPE_CT;
13222 flow->ct = owner_idx;
13223 __atomic_fetch_add(&ct->refcnt, 1,
13227 action_flags |= MLX5_FLOW_ACTION_CT;
13229 case RTE_FLOW_ACTION_TYPE_END:
13230 actions_end = true;
13231 if (mhdr_res->actions_num) {
13232 /* create modify action if needed. */
13233 if (flow_dv_modify_hdr_resource_register
13234 (dev, mhdr_res, dev_flow, error))
13236 dev_flow->dv.actions[modify_action_position] =
13237 handle->dvh.modify_hdr->action;
13240 * Handle AGE and COUNT action by single HW counter
13241 * when they are not shared.
13243 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13244 if ((non_shared_age && count) ||
13245 !(priv->sh->flow_hit_aso_en &&
13246 (attr->group || attr->transfer))) {
13247 /* Creates age by counters. */
13248 cnt_act = flow_dv_prepare_counter
13255 dev_flow->dv.actions[age_act_pos] =
13259 if (!flow->age && non_shared_age) {
13260 flow->age = flow_dv_aso_age_alloc
13264 flow_dv_aso_age_params_init
13266 non_shared_age->context ?
13267 non_shared_age->context :
13268 (void *)(uintptr_t)
13269 (dev_flow->flow_idx),
13270 non_shared_age->timeout);
13272 age_act = flow_aso_age_get_by_idx(dev,
13274 dev_flow->dv.actions[age_act_pos] =
13275 age_act->dr_action;
13277 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13279 * Create one count action, to be used
13280 * by all sub-flows.
13282 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13287 dev_flow->dv.actions[actions_n++] =
13293 if (mhdr_res->actions_num &&
13294 modify_action_position == UINT32_MAX)
13295 modify_action_position = actions_n++;
13297 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13298 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13299 int item_type = items->type;
13301 if (!mlx5_flow_os_item_supported(item_type))
13302 return rte_flow_error_set(error, ENOTSUP,
13303 RTE_FLOW_ERROR_TYPE_ITEM,
13304 NULL, "item not supported");
13305 switch (item_type) {
13306 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13307 flow_dv_translate_item_port_id
13308 (dev, match_mask, match_value, items, attr);
13309 last_item = MLX5_FLOW_ITEM_PORT_ID;
13311 case RTE_FLOW_ITEM_TYPE_ETH:
13312 flow_dv_translate_item_eth(match_mask, match_value,
13314 dev_flow->dv.group);
13315 matcher.priority = action_flags &
13316 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13317 !dev_flow->external ?
13318 MLX5_PRIORITY_MAP_L3 :
13319 MLX5_PRIORITY_MAP_L2;
13320 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13321 MLX5_FLOW_LAYER_OUTER_L2;
13323 case RTE_FLOW_ITEM_TYPE_VLAN:
13324 flow_dv_translate_item_vlan(dev_flow,
13325 match_mask, match_value,
13327 dev_flow->dv.group);
13328 matcher.priority = MLX5_PRIORITY_MAP_L2;
13329 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13330 MLX5_FLOW_LAYER_INNER_VLAN) :
13331 (MLX5_FLOW_LAYER_OUTER_L2 |
13332 MLX5_FLOW_LAYER_OUTER_VLAN);
13334 case RTE_FLOW_ITEM_TYPE_IPV4:
13335 mlx5_flow_tunnel_ip_check(items, next_protocol,
13336 &item_flags, &tunnel);
13337 flow_dv_translate_item_ipv4(match_mask, match_value,
13339 dev_flow->dv.group);
13340 matcher.priority = MLX5_PRIORITY_MAP_L3;
13341 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13342 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13343 if (items->mask != NULL &&
13344 ((const struct rte_flow_item_ipv4 *)
13345 items->mask)->hdr.next_proto_id) {
13347 ((const struct rte_flow_item_ipv4 *)
13348 (items->spec))->hdr.next_proto_id;
13350 ((const struct rte_flow_item_ipv4 *)
13351 (items->mask))->hdr.next_proto_id;
13353 /* Reset for inner layer. */
13354 next_protocol = 0xff;
13357 case RTE_FLOW_ITEM_TYPE_IPV6:
13358 mlx5_flow_tunnel_ip_check(items, next_protocol,
13359 &item_flags, &tunnel);
13360 flow_dv_translate_item_ipv6(match_mask, match_value,
13362 dev_flow->dv.group);
13363 matcher.priority = MLX5_PRIORITY_MAP_L3;
13364 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13365 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13366 if (items->mask != NULL &&
13367 ((const struct rte_flow_item_ipv6 *)
13368 items->mask)->hdr.proto) {
13370 ((const struct rte_flow_item_ipv6 *)
13371 items->spec)->hdr.proto;
13373 ((const struct rte_flow_item_ipv6 *)
13374 items->mask)->hdr.proto;
13376 /* Reset for inner layer. */
13377 next_protocol = 0xff;
13380 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13381 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13384 last_item = tunnel ?
13385 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13386 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13387 if (items->mask != NULL &&
13388 ((const struct rte_flow_item_ipv6_frag_ext *)
13389 items->mask)->hdr.next_header) {
13391 ((const struct rte_flow_item_ipv6_frag_ext *)
13392 items->spec)->hdr.next_header;
13394 ((const struct rte_flow_item_ipv6_frag_ext *)
13395 items->mask)->hdr.next_header;
13397 /* Reset for inner layer. */
13398 next_protocol = 0xff;
13401 case RTE_FLOW_ITEM_TYPE_TCP:
13402 flow_dv_translate_item_tcp(match_mask, match_value,
13404 matcher.priority = MLX5_PRIORITY_MAP_L4;
13405 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13406 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13408 case RTE_FLOW_ITEM_TYPE_UDP:
13409 flow_dv_translate_item_udp(match_mask, match_value,
13411 matcher.priority = MLX5_PRIORITY_MAP_L4;
13412 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13413 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13415 case RTE_FLOW_ITEM_TYPE_GRE:
13416 flow_dv_translate_item_gre(match_mask, match_value,
13418 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13419 last_item = MLX5_FLOW_LAYER_GRE;
13421 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13422 flow_dv_translate_item_gre_key(match_mask,
13423 match_value, items);
13424 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13426 case RTE_FLOW_ITEM_TYPE_NVGRE:
13427 flow_dv_translate_item_nvgre(match_mask, match_value,
13429 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13430 last_item = MLX5_FLOW_LAYER_GRE;
13432 case RTE_FLOW_ITEM_TYPE_VXLAN:
13433 flow_dv_translate_item_vxlan(dev, attr,
13434 match_mask, match_value,
13436 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13437 last_item = MLX5_FLOW_LAYER_VXLAN;
13439 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13440 flow_dv_translate_item_vxlan_gpe(match_mask,
13441 match_value, items,
13443 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13444 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13446 case RTE_FLOW_ITEM_TYPE_GENEVE:
13447 flow_dv_translate_item_geneve(match_mask, match_value,
13449 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13450 last_item = MLX5_FLOW_LAYER_GENEVE;
13452 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13453 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13457 return rte_flow_error_set(error, -ret,
13458 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13459 "cannot create GENEVE TLV option");
13460 flow->geneve_tlv_option = 1;
13461 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13463 case RTE_FLOW_ITEM_TYPE_MPLS:
13464 flow_dv_translate_item_mpls(match_mask, match_value,
13465 items, last_item, tunnel);
13466 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13467 last_item = MLX5_FLOW_LAYER_MPLS;
13469 case RTE_FLOW_ITEM_TYPE_MARK:
13470 flow_dv_translate_item_mark(dev, match_mask,
13471 match_value, items);
13472 last_item = MLX5_FLOW_ITEM_MARK;
13474 case RTE_FLOW_ITEM_TYPE_META:
13475 flow_dv_translate_item_meta(dev, match_mask,
13476 match_value, attr, items);
13477 last_item = MLX5_FLOW_ITEM_METADATA;
13479 case RTE_FLOW_ITEM_TYPE_ICMP:
13480 flow_dv_translate_item_icmp(match_mask, match_value,
13482 last_item = MLX5_FLOW_LAYER_ICMP;
13484 case RTE_FLOW_ITEM_TYPE_ICMP6:
13485 flow_dv_translate_item_icmp6(match_mask, match_value,
13487 last_item = MLX5_FLOW_LAYER_ICMP6;
13489 case RTE_FLOW_ITEM_TYPE_TAG:
13490 flow_dv_translate_item_tag(dev, match_mask,
13491 match_value, items);
13492 last_item = MLX5_FLOW_ITEM_TAG;
13494 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13495 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13496 match_value, items);
13497 last_item = MLX5_FLOW_ITEM_TAG;
13499 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13500 flow_dv_translate_item_tx_queue(dev, match_mask,
13503 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13505 case RTE_FLOW_ITEM_TYPE_GTP:
13506 flow_dv_translate_item_gtp(match_mask, match_value,
13508 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13509 last_item = MLX5_FLOW_LAYER_GTP;
13511 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13512 ret = flow_dv_translate_item_gtp_psc(match_mask,
13516 return rte_flow_error_set(error, -ret,
13517 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13518 "cannot create GTP PSC item");
13519 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13521 case RTE_FLOW_ITEM_TYPE_ECPRI:
13522 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13523 /* Create it only the first time to be used. */
13524 ret = mlx5_flex_parser_ecpri_alloc(dev);
13526 return rte_flow_error_set
13528 RTE_FLOW_ERROR_TYPE_ITEM,
13530 "cannot create eCPRI parser");
13532 flow_dv_translate_item_ecpri(dev, match_mask,
13533 match_value, items,
13535 /* No other protocol should follow eCPRI layer. */
13536 last_item = MLX5_FLOW_LAYER_ECPRI;
13538 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13539 flow_dv_translate_item_integrity(items, integrity_items,
13542 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13543 flow_dv_translate_item_aso_ct(dev, match_mask,
13544 match_value, items);
13546 case RTE_FLOW_ITEM_TYPE_FLEX:
13547 flow_dv_translate_item_flex(dev, match_mask,
13548 match_value, items,
13549 dev_flow, tunnel != 0);
13550 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13551 MLX5_FLOW_ITEM_OUTER_FLEX;
13556 item_flags |= last_item;
13559 * When E-Switch mode is enabled, we have two cases where we need to
13560 * set the source port manually.
13561 * The first one, is in case of Nic steering rule, and the second is
13562 * E-Switch rule where no port_id item was found. In both cases
13563 * the source port is set according the current port in use.
13565 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13566 (priv->representor || priv->master)) {
13567 if (flow_dv_translate_item_port_id(dev, match_mask,
13568 match_value, NULL, attr))
13571 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13572 flow_dv_translate_item_integrity_post(match_mask, match_value,
13576 #ifdef RTE_LIBRTE_MLX5_DEBUG
13577 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13578 dev_flow->dv.value.buf));
13581 * Layers may be already initialized from prefix flow if this dev_flow
13582 * is the suffix flow.
13584 handle->layers |= item_flags;
13585 if (action_flags & MLX5_FLOW_ACTION_RSS)
13586 flow_dv_hashfields_set(dev_flow, rss_desc);
13587 /* If has RSS action in the sample action, the Sample/Mirror resource
13588 * should be registered after the hash filed be update.
13590 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13591 ret = flow_dv_translate_action_sample(dev,
13600 ret = flow_dv_create_action_sample(dev,
13609 return rte_flow_error_set
13611 RTE_FLOW_ERROR_TYPE_ACTION,
13613 "cannot create sample action");
13614 if (num_of_dest > 1) {
13615 dev_flow->dv.actions[sample_act_pos] =
13616 dev_flow->dv.dest_array_res->action;
13618 dev_flow->dv.actions[sample_act_pos] =
13619 dev_flow->dv.sample_res->verbs_action;
13623 * For multiple destination (sample action with ratio=1), the encap
13624 * action and port id action will be combined into group action.
13625 * So need remove the original these actions in the flow and only
13626 * use the sample action instead of.
13628 if (num_of_dest > 1 &&
13629 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13631 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13633 for (i = 0; i < actions_n; i++) {
13634 if ((sample_act->dr_encap_action &&
13635 sample_act->dr_encap_action ==
13636 dev_flow->dv.actions[i]) ||
13637 (sample_act->dr_port_id_action &&
13638 sample_act->dr_port_id_action ==
13639 dev_flow->dv.actions[i]) ||
13640 (sample_act->dr_jump_action &&
13641 sample_act->dr_jump_action ==
13642 dev_flow->dv.actions[i]))
13644 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13646 memcpy((void *)dev_flow->dv.actions,
13647 (void *)temp_actions,
13648 tmp_actions_n * sizeof(void *));
13649 actions_n = tmp_actions_n;
13651 dev_flow->dv.actions_n = actions_n;
13652 dev_flow->act_flags = action_flags;
13653 if (wks->skip_matcher_reg)
13655 /* Register matcher. */
13656 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13657 matcher.mask.size);
13658 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13660 dev_flow->external);
13662 * When creating meter drop flow in drop table, using original
13663 * 5-tuple match, the matcher priority should be lower than
13666 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13667 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13668 matcher.priority <= MLX5_REG_BITS)
13669 matcher.priority += MLX5_REG_BITS;
13670 /* reserved field no needs to be set to 0 here. */
13671 tbl_key.is_fdb = attr->transfer;
13672 tbl_key.is_egress = attr->egress;
13673 tbl_key.level = dev_flow->dv.group;
13674 tbl_key.id = dev_flow->dv.table_id;
13675 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13676 tunnel, attr->group, error))
13682 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13685 * @param[in, out] action
13686 * Shred RSS action holding hash RX queue objects.
13687 * @param[in] hash_fields
13688 * Defines combination of packet fields to participate in RX hash.
13689 * @param[in] tunnel
13691 * @param[in] hrxq_idx
13692 * Hash RX queue index to set.
13695 * 0 on success, otherwise negative errno value.
13698 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13699 const uint64_t hash_fields,
13702 uint32_t *hrxqs = action->hrxq;
13704 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13705 case MLX5_RSS_HASH_IPV4:
13706 /* fall-through. */
13707 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13708 /* fall-through. */
13709 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13710 hrxqs[0] = hrxq_idx;
13712 case MLX5_RSS_HASH_IPV4_TCP:
13713 /* fall-through. */
13714 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13715 /* fall-through. */
13716 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13717 hrxqs[1] = hrxq_idx;
13719 case MLX5_RSS_HASH_IPV4_UDP:
13720 /* fall-through. */
13721 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13722 /* fall-through. */
13723 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13724 hrxqs[2] = hrxq_idx;
13726 case MLX5_RSS_HASH_IPV6:
13727 /* fall-through. */
13728 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13729 /* fall-through. */
13730 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13731 hrxqs[3] = hrxq_idx;
13733 case MLX5_RSS_HASH_IPV6_TCP:
13734 /* fall-through. */
13735 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13736 /* fall-through. */
13737 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13738 hrxqs[4] = hrxq_idx;
13740 case MLX5_RSS_HASH_IPV6_UDP:
13741 /* fall-through. */
13742 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13743 /* fall-through. */
13744 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13745 hrxqs[5] = hrxq_idx;
13747 case MLX5_RSS_HASH_NONE:
13748 hrxqs[6] = hrxq_idx;
13756 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13760 * Pointer to the Ethernet device structure.
13762 * Shared RSS action ID holding hash RX queue objects.
13763 * @param[in] hash_fields
13764 * Defines combination of packet fields to participate in RX hash.
13765 * @param[in] tunnel
13769 * Valid hash RX queue index, otherwise 0.
13772 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13773 const uint64_t hash_fields)
13775 struct mlx5_priv *priv = dev->data->dev_private;
13776 struct mlx5_shared_action_rss *shared_rss =
13777 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13778 const uint32_t *hrxqs = shared_rss->hrxq;
13780 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13781 case MLX5_RSS_HASH_IPV4:
13782 /* fall-through. */
13783 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13784 /* fall-through. */
13785 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13787 case MLX5_RSS_HASH_IPV4_TCP:
13788 /* fall-through. */
13789 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13790 /* fall-through. */
13791 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13793 case MLX5_RSS_HASH_IPV4_UDP:
13794 /* fall-through. */
13795 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13796 /* fall-through. */
13797 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13799 case MLX5_RSS_HASH_IPV6:
13800 /* fall-through. */
13801 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13802 /* fall-through. */
13803 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13805 case MLX5_RSS_HASH_IPV6_TCP:
13806 /* fall-through. */
13807 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13808 /* fall-through. */
13809 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13811 case MLX5_RSS_HASH_IPV6_UDP:
13812 /* fall-through. */
13813 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13814 /* fall-through. */
13815 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13817 case MLX5_RSS_HASH_NONE:
13826 * Apply the flow to the NIC, lock free,
13827 * (mutex should be acquired by caller).
13830 * Pointer to the Ethernet device structure.
13831 * @param[in, out] flow
13832 * Pointer to flow structure.
13833 * @param[out] error
13834 * Pointer to error structure.
13837 * 0 on success, a negative errno value otherwise and rte_errno is set.
13840 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13841 struct rte_flow_error *error)
13843 struct mlx5_flow_dv_workspace *dv;
13844 struct mlx5_flow_handle *dh;
13845 struct mlx5_flow_handle_dv *dv_h;
13846 struct mlx5_flow *dev_flow;
13847 struct mlx5_priv *priv = dev->data->dev_private;
13848 uint32_t handle_idx;
13852 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13853 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13857 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13858 dev_flow = &wks->flows[idx];
13859 dv = &dev_flow->dv;
13860 dh = dev_flow->handle;
13863 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13864 if (dv->transfer) {
13865 MLX5_ASSERT(priv->sh->dr_drop_action);
13866 dv->actions[n++] = priv->sh->dr_drop_action;
13868 #ifdef HAVE_MLX5DV_DR
13869 /* DR supports drop action placeholder. */
13870 MLX5_ASSERT(priv->sh->dr_drop_action);
13871 dv->actions[n++] = dv->group ?
13872 priv->sh->dr_drop_action :
13873 priv->root_drop_action;
13875 /* For DV we use the explicit drop queue. */
13876 MLX5_ASSERT(priv->drop_queue.hrxq);
13878 priv->drop_queue.hrxq->action;
13881 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13882 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13883 struct mlx5_hrxq *hrxq;
13886 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13891 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13892 "cannot get hash queue");
13895 dh->rix_hrxq = hrxq_idx;
13896 dv->actions[n++] = hrxq->action;
13897 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13898 struct mlx5_hrxq *hrxq = NULL;
13901 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13902 rss_desc->shared_rss,
13903 dev_flow->hash_fields);
13905 hrxq = mlx5_ipool_get
13906 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13911 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13912 "cannot get hash queue");
13915 dh->rix_srss = rss_desc->shared_rss;
13916 dv->actions[n++] = hrxq->action;
13917 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13918 if (!priv->sh->default_miss_action) {
13921 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13922 "default miss action not be created.");
13925 dv->actions[n++] = priv->sh->default_miss_action;
13927 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13928 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13929 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13930 (void *)&dv->value, n,
13931 dv->actions, &dh->drv_flow);
13935 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13937 (!priv->config.allow_duplicate_pattern &&
13939 "duplicating pattern is not allowed" :
13940 "hardware refuses to create flow");
13943 if (priv->vmwa_context &&
13944 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13946 * The rule contains the VLAN pattern.
13947 * For VF we are going to create VLAN
13948 * interface to make hypervisor set correct
13949 * e-Switch vport context.
13951 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13956 err = rte_errno; /* Save rte_errno before cleanup. */
13957 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13958 handle_idx, dh, next) {
13959 /* hrxq is union, don't clear it if the flag is not set. */
13960 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13961 mlx5_hrxq_release(dev, dh->rix_hrxq);
13963 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13966 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13967 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13969 rte_errno = err; /* Restore rte_errno. */
13974 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
13975 struct mlx5_list_entry *entry)
13977 struct mlx5_flow_dv_matcher *resource = container_of(entry,
13981 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
13982 mlx5_free(resource);
13986 * Release the flow matcher.
13989 * Pointer to Ethernet device.
13991 * Index to port ID action resource.
13994 * 1 while a reference on it exists, 0 when freed.
13997 flow_dv_matcher_release(struct rte_eth_dev *dev,
13998 struct mlx5_flow_handle *handle)
14000 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14001 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14002 typeof(*tbl), tbl);
14005 MLX5_ASSERT(matcher->matcher_object);
14006 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14007 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14012 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14014 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14015 struct mlx5_flow_dv_encap_decap_resource *res =
14016 container_of(entry, typeof(*res), entry);
14018 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14019 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14023 * Release an encap/decap resource.
14026 * Pointer to Ethernet device.
14027 * @param encap_decap_idx
14028 * Index of encap decap resource.
14031 * 1 while a reference on it exists, 0 when freed.
14034 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14035 uint32_t encap_decap_idx)
14037 struct mlx5_priv *priv = dev->data->dev_private;
14038 struct mlx5_flow_dv_encap_decap_resource *resource;
14040 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14044 MLX5_ASSERT(resource->action);
14045 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14049 * Release an jump to table action resource.
14052 * Pointer to Ethernet device.
14054 * Index to the jump action resource.
14057 * 1 while a reference on it exists, 0 when freed.
14060 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14063 struct mlx5_priv *priv = dev->data->dev_private;
14064 struct mlx5_flow_tbl_data_entry *tbl_data;
14066 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14070 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14074 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14076 struct mlx5_flow_dv_modify_hdr_resource *res =
14077 container_of(entry, typeof(*res), entry);
14078 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14080 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14081 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14085 * Release a modify-header resource.
14088 * Pointer to Ethernet device.
14090 * Pointer to mlx5_flow_handle.
14093 * 1 while a reference on it exists, 0 when freed.
14096 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14097 struct mlx5_flow_handle *handle)
14099 struct mlx5_priv *priv = dev->data->dev_private;
14100 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14102 MLX5_ASSERT(entry->action);
14103 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14107 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14109 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14110 struct mlx5_flow_dv_port_id_action_resource *resource =
14111 container_of(entry, typeof(*resource), entry);
14113 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14114 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14118 * Release port ID action resource.
14121 * Pointer to Ethernet device.
14123 * Pointer to mlx5_flow_handle.
14126 * 1 while a reference on it exists, 0 when freed.
14129 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14132 struct mlx5_priv *priv = dev->data->dev_private;
14133 struct mlx5_flow_dv_port_id_action_resource *resource;
14135 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14138 MLX5_ASSERT(resource->action);
14139 return mlx5_list_unregister(priv->sh->port_id_action_list,
14144 * Release shared RSS action resource.
14147 * Pointer to Ethernet device.
14149 * Shared RSS action index.
14152 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14154 struct mlx5_priv *priv = dev->data->dev_private;
14155 struct mlx5_shared_action_rss *shared_rss;
14157 shared_rss = mlx5_ipool_get
14158 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14159 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14163 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14165 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14166 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14167 container_of(entry, typeof(*resource), entry);
14169 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14170 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14174 * Release push vlan action resource.
14177 * Pointer to Ethernet device.
14179 * Pointer to mlx5_flow_handle.
14182 * 1 while a reference on it exists, 0 when freed.
14185 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14186 struct mlx5_flow_handle *handle)
14188 struct mlx5_priv *priv = dev->data->dev_private;
14189 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14190 uint32_t idx = handle->dvh.rix_push_vlan;
14192 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14195 MLX5_ASSERT(resource->action);
14196 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14201 * Release the fate resource.
14204 * Pointer to Ethernet device.
14206 * Pointer to mlx5_flow_handle.
14209 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14210 struct mlx5_flow_handle *handle)
14212 if (!handle->rix_fate)
14214 switch (handle->fate_action) {
14215 case MLX5_FLOW_FATE_QUEUE:
14216 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14217 mlx5_hrxq_release(dev, handle->rix_hrxq);
14219 case MLX5_FLOW_FATE_JUMP:
14220 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14222 case MLX5_FLOW_FATE_PORT_ID:
14223 flow_dv_port_id_action_resource_release(dev,
14224 handle->rix_port_id_action);
14227 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14230 handle->rix_fate = 0;
14234 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14235 struct mlx5_list_entry *entry)
14237 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14240 struct rte_eth_dev *dev = resource->dev;
14241 struct mlx5_priv *priv = dev->data->dev_private;
14243 if (resource->verbs_action)
14244 claim_zero(mlx5_flow_os_destroy_flow_action
14245 (resource->verbs_action));
14246 if (resource->normal_path_tbl)
14247 flow_dv_tbl_resource_release(MLX5_SH(dev),
14248 resource->normal_path_tbl);
14249 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14250 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14251 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14255 * Release an sample resource.
14258 * Pointer to Ethernet device.
14260 * Pointer to mlx5_flow_handle.
14263 * 1 while a reference on it exists, 0 when freed.
14266 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14267 struct mlx5_flow_handle *handle)
14269 struct mlx5_priv *priv = dev->data->dev_private;
14270 struct mlx5_flow_dv_sample_resource *resource;
14272 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14273 handle->dvh.rix_sample);
14276 MLX5_ASSERT(resource->verbs_action);
14277 return mlx5_list_unregister(priv->sh->sample_action_list,
14282 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14283 struct mlx5_list_entry *entry)
14285 struct mlx5_flow_dv_dest_array_resource *resource =
14286 container_of(entry, typeof(*resource), entry);
14287 struct rte_eth_dev *dev = resource->dev;
14288 struct mlx5_priv *priv = dev->data->dev_private;
14291 MLX5_ASSERT(resource->action);
14292 if (resource->action)
14293 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14294 for (; i < resource->num_of_dest; i++)
14295 flow_dv_sample_sub_actions_release(dev,
14296 &resource->sample_idx[i]);
14297 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14298 DRV_LOG(DEBUG, "destination array resource %p: removed",
14303 * Release an destination array resource.
14306 * Pointer to Ethernet device.
14308 * Pointer to mlx5_flow_handle.
14311 * 1 while a reference on it exists, 0 when freed.
14314 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14315 struct mlx5_flow_handle *handle)
14317 struct mlx5_priv *priv = dev->data->dev_private;
14318 struct mlx5_flow_dv_dest_array_resource *resource;
14320 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14321 handle->dvh.rix_dest_array);
14324 MLX5_ASSERT(resource->action);
14325 return mlx5_list_unregister(priv->sh->dest_array_list,
14330 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14332 struct mlx5_priv *priv = dev->data->dev_private;
14333 struct mlx5_dev_ctx_shared *sh = priv->sh;
14334 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14335 sh->geneve_tlv_option_resource;
14336 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14337 if (geneve_opt_resource) {
14338 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14339 __ATOMIC_RELAXED))) {
14340 claim_zero(mlx5_devx_cmd_destroy
14341 (geneve_opt_resource->obj));
14342 mlx5_free(sh->geneve_tlv_option_resource);
14343 sh->geneve_tlv_option_resource = NULL;
14346 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14350 * Remove the flow from the NIC but keeps it in memory.
14351 * Lock free, (mutex should be acquired by caller).
14354 * Pointer to Ethernet device.
14355 * @param[in, out] flow
14356 * Pointer to flow structure.
14359 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14361 struct mlx5_flow_handle *dh;
14362 uint32_t handle_idx;
14363 struct mlx5_priv *priv = dev->data->dev_private;
14367 handle_idx = flow->dev_handles;
14368 while (handle_idx) {
14369 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14373 if (dh->drv_flow) {
14374 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14375 dh->drv_flow = NULL;
14377 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14378 flow_dv_fate_resource_release(dev, dh);
14379 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14380 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14381 handle_idx = dh->next.next;
14386 * Remove the flow from the NIC and the memory.
14387 * Lock free, (mutex should be acquired by caller).
14390 * Pointer to the Ethernet device structure.
14391 * @param[in, out] flow
14392 * Pointer to flow structure.
14395 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14397 struct mlx5_flow_handle *dev_handle;
14398 struct mlx5_priv *priv = dev->data->dev_private;
14399 struct mlx5_flow_meter_info *fm = NULL;
14404 flow_dv_remove(dev, flow);
14405 if (flow->counter) {
14406 flow_dv_counter_free(dev, flow->counter);
14410 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14412 mlx5_flow_meter_detach(priv, fm);
14415 /* Keep the current age handling by default. */
14416 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14417 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14418 else if (flow->age)
14419 flow_dv_aso_age_release(dev, flow->age);
14420 if (flow->geneve_tlv_option) {
14421 flow_dv_geneve_tlv_option_resource_release(dev);
14422 flow->geneve_tlv_option = 0;
14424 while (flow->dev_handles) {
14425 uint32_t tmp_idx = flow->dev_handles;
14427 dev_handle = mlx5_ipool_get(priv->sh->ipool
14428 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14431 flow->dev_handles = dev_handle->next.next;
14432 while (dev_handle->flex_item) {
14433 int index = rte_bsf32(dev_handle->flex_item);
14435 mlx5_flex_release_index(dev, index);
14436 dev_handle->flex_item &= ~RTE_BIT32(index);
14438 if (dev_handle->dvh.matcher)
14439 flow_dv_matcher_release(dev, dev_handle);
14440 if (dev_handle->dvh.rix_sample)
14441 flow_dv_sample_resource_release(dev, dev_handle);
14442 if (dev_handle->dvh.rix_dest_array)
14443 flow_dv_dest_array_resource_release(dev, dev_handle);
14444 if (dev_handle->dvh.rix_encap_decap)
14445 flow_dv_encap_decap_resource_release(dev,
14446 dev_handle->dvh.rix_encap_decap);
14447 if (dev_handle->dvh.modify_hdr)
14448 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14449 if (dev_handle->dvh.rix_push_vlan)
14450 flow_dv_push_vlan_action_resource_release(dev,
14452 if (dev_handle->dvh.rix_tag)
14453 flow_dv_tag_release(dev,
14454 dev_handle->dvh.rix_tag);
14455 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14456 flow_dv_fate_resource_release(dev, dev_handle);
14458 srss = dev_handle->rix_srss;
14459 if (fm && dev_handle->is_meter_flow_id &&
14460 dev_handle->split_flow_id)
14461 mlx5_ipool_free(fm->flow_ipool,
14462 dev_handle->split_flow_id);
14463 else if (dev_handle->split_flow_id &&
14464 !dev_handle->is_meter_flow_id)
14465 mlx5_ipool_free(priv->sh->ipool
14466 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14467 dev_handle->split_flow_id);
14468 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14472 flow_dv_shared_rss_action_release(dev, srss);
14476 * Release array of hash RX queue objects.
14480 * Pointer to the Ethernet device structure.
14481 * @param[in, out] hrxqs
14482 * Array of hash RX queue objects.
14485 * Total number of references to hash RX queue objects in *hrxqs* array
14486 * after this operation.
14489 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14490 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14495 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14496 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14506 * Release all hash RX queue objects representing shared RSS action.
14509 * Pointer to the Ethernet device structure.
14510 * @param[in, out] action
14511 * Shared RSS action to remove hash RX queue objects from.
14514 * Total number of references to hash RX queue objects stored in *action*
14515 * after this operation.
14516 * Expected to be 0 if no external references held.
14519 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14520 struct mlx5_shared_action_rss *shared_rss)
14522 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14526 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14529 * Only one hash value is available for one L3+L4 combination:
14531 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14532 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14533 * same slot in mlx5_rss_hash_fields.
14536 * Pointer to the shared action RSS conf.
14537 * @param[in, out] hash_field
14538 * hash_field variable needed to be adjusted.
14544 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14545 uint64_t *hash_field)
14547 uint64_t rss_types = rss->origin.types;
14549 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14550 case MLX5_RSS_HASH_IPV4:
14551 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14552 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14553 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14554 *hash_field |= IBV_RX_HASH_DST_IPV4;
14555 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14556 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14558 *hash_field |= MLX5_RSS_HASH_IPV4;
14561 case MLX5_RSS_HASH_IPV6:
14562 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14563 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14564 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14565 *hash_field |= IBV_RX_HASH_DST_IPV6;
14566 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14567 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14569 *hash_field |= MLX5_RSS_HASH_IPV6;
14572 case MLX5_RSS_HASH_IPV4_UDP:
14573 /* fall-through. */
14574 case MLX5_RSS_HASH_IPV6_UDP:
14575 if (rss_types & RTE_ETH_RSS_UDP) {
14576 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14577 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14578 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14579 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14580 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14582 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14585 case MLX5_RSS_HASH_IPV4_TCP:
14586 /* fall-through. */
14587 case MLX5_RSS_HASH_IPV6_TCP:
14588 if (rss_types & RTE_ETH_RSS_TCP) {
14589 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14590 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14591 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14592 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14593 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14595 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14604 * Setup shared RSS action.
14605 * Prepare set of hash RX queue objects sufficient to handle all valid
14606 * hash_fields combinations (see enum ibv_rx_hash_fields).
14609 * Pointer to the Ethernet device structure.
14610 * @param[in] action_idx
14611 * Shared RSS action ipool index.
14612 * @param[in, out] action
14613 * Partially initialized shared RSS action.
14614 * @param[out] error
14615 * Perform verbose error reporting if not NULL. Initialized in case of
14619 * 0 on success, otherwise negative errno value.
14622 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14623 uint32_t action_idx,
14624 struct mlx5_shared_action_rss *shared_rss,
14625 struct rte_flow_error *error)
14627 struct mlx5_flow_rss_desc rss_desc = { 0 };
14631 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14632 return rte_flow_error_set(error, rte_errno,
14633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14634 "cannot setup indirection table");
14636 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14637 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14638 rss_desc.const_q = shared_rss->origin.queue;
14639 rss_desc.queue_num = shared_rss->origin.queue_num;
14640 /* Set non-zero value to indicate a shared RSS. */
14641 rss_desc.shared_rss = action_idx;
14642 rss_desc.ind_tbl = shared_rss->ind_tbl;
14643 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14645 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14648 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14649 if (shared_rss->origin.level > 1) {
14650 hash_fields |= IBV_RX_HASH_INNER;
14653 rss_desc.tunnel = tunnel;
14654 rss_desc.hash_fields = hash_fields;
14655 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14659 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14660 "cannot get hash queue");
14661 goto error_hrxq_new;
14663 err = __flow_dv_action_rss_hrxq_set
14664 (shared_rss, hash_fields, hrxq_idx);
14670 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14671 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14672 shared_rss->ind_tbl = NULL;
14678 * Create shared RSS action.
14681 * Pointer to the Ethernet device structure.
14683 * Shared action configuration.
14685 * RSS action specification used to create shared action.
14686 * @param[out] error
14687 * Perform verbose error reporting if not NULL. Initialized in case of
14691 * A valid shared action ID in case of success, 0 otherwise and
14692 * rte_errno is set.
14695 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14696 const struct rte_flow_indir_action_conf *conf,
14697 const struct rte_flow_action_rss *rss,
14698 struct rte_flow_error *error)
14700 struct mlx5_priv *priv = dev->data->dev_private;
14701 struct mlx5_shared_action_rss *shared_rss = NULL;
14702 void *queue = NULL;
14703 struct rte_flow_action_rss *origin;
14704 const uint8_t *rss_key;
14705 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14708 RTE_SET_USED(conf);
14709 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14711 shared_rss = mlx5_ipool_zmalloc
14712 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14713 if (!shared_rss || !queue) {
14714 rte_flow_error_set(error, ENOMEM,
14715 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14716 "cannot allocate resource memory");
14717 goto error_rss_init;
14719 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14720 rte_flow_error_set(error, E2BIG,
14721 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14722 "rss action number out of range");
14723 goto error_rss_init;
14725 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14726 sizeof(*shared_rss->ind_tbl),
14728 if (!shared_rss->ind_tbl) {
14729 rte_flow_error_set(error, ENOMEM,
14730 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14731 "cannot allocate resource memory");
14732 goto error_rss_init;
14734 memcpy(queue, rss->queue, queue_size);
14735 shared_rss->ind_tbl->queues = queue;
14736 shared_rss->ind_tbl->queues_n = rss->queue_num;
14737 origin = &shared_rss->origin;
14738 origin->func = rss->func;
14739 origin->level = rss->level;
14740 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14741 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14742 /* NULL RSS key indicates default RSS key. */
14743 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14744 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14745 origin->key = &shared_rss->key[0];
14746 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14747 origin->queue = queue;
14748 origin->queue_num = rss->queue_num;
14749 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14750 goto error_rss_init;
14751 rte_spinlock_init(&shared_rss->action_rss_sl);
14752 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14753 rte_spinlock_lock(&priv->shared_act_sl);
14754 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14755 &priv->rss_shared_actions, idx, shared_rss, next);
14756 rte_spinlock_unlock(&priv->shared_act_sl);
14760 if (shared_rss->ind_tbl)
14761 mlx5_free(shared_rss->ind_tbl);
14762 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14771 * Destroy the shared RSS action.
14772 * Release related hash RX queue objects.
14775 * Pointer to the Ethernet device structure.
14777 * The shared RSS action object ID to be removed.
14778 * @param[out] error
14779 * Perform verbose error reporting if not NULL. Initialized in case of
14783 * 0 on success, otherwise negative errno value.
14786 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14787 struct rte_flow_error *error)
14789 struct mlx5_priv *priv = dev->data->dev_private;
14790 struct mlx5_shared_action_rss *shared_rss =
14791 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14792 uint32_t old_refcnt = 1;
14794 uint16_t *queue = NULL;
14797 return rte_flow_error_set(error, EINVAL,
14798 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14799 "invalid shared action");
14800 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14801 0, 0, __ATOMIC_ACQUIRE,
14803 return rte_flow_error_set(error, EBUSY,
14804 RTE_FLOW_ERROR_TYPE_ACTION,
14806 "shared rss has references");
14807 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14809 return rte_flow_error_set(error, EBUSY,
14810 RTE_FLOW_ERROR_TYPE_ACTION,
14812 "shared rss hrxq has references");
14813 queue = shared_rss->ind_tbl->queues;
14814 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14816 return rte_flow_error_set(error, EBUSY,
14817 RTE_FLOW_ERROR_TYPE_ACTION,
14819 "shared rss indirection table has"
14822 rte_spinlock_lock(&priv->shared_act_sl);
14823 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14824 &priv->rss_shared_actions, idx, shared_rss, next);
14825 rte_spinlock_unlock(&priv->shared_act_sl);
14826 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14832 * Create indirect action, lock free,
14833 * (mutex should be acquired by caller).
14834 * Dispatcher for action type specific call.
14837 * Pointer to the Ethernet device structure.
14839 * Shared action configuration.
14840 * @param[in] action
14841 * Action specification used to create indirect action.
14842 * @param[out] error
14843 * Perform verbose error reporting if not NULL. Initialized in case of
14847 * A valid shared action handle in case of success, NULL otherwise and
14848 * rte_errno is set.
14850 static struct rte_flow_action_handle *
14851 flow_dv_action_create(struct rte_eth_dev *dev,
14852 const struct rte_flow_indir_action_conf *conf,
14853 const struct rte_flow_action *action,
14854 struct rte_flow_error *err)
14856 struct mlx5_priv *priv = dev->data->dev_private;
14857 uint32_t age_idx = 0;
14861 switch (action->type) {
14862 case RTE_FLOW_ACTION_TYPE_RSS:
14863 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14864 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14865 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14867 case RTE_FLOW_ACTION_TYPE_AGE:
14868 age_idx = flow_dv_aso_age_alloc(dev, err);
14873 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14874 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14875 flow_dv_aso_age_params_init(dev, age_idx,
14876 ((const struct rte_flow_action_age *)
14877 action->conf)->context ?
14878 ((const struct rte_flow_action_age *)
14879 action->conf)->context :
14880 (void *)(uintptr_t)idx,
14881 ((const struct rte_flow_action_age *)
14882 action->conf)->timeout);
14885 case RTE_FLOW_ACTION_TYPE_COUNT:
14886 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14887 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14888 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14890 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14891 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14893 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14896 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14897 NULL, "action type not supported");
14900 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14904 * Destroy the indirect action.
14905 * Release action related resources on the NIC and the memory.
14906 * Lock free, (mutex should be acquired by caller).
14907 * Dispatcher for action type specific call.
14910 * Pointer to the Ethernet device structure.
14911 * @param[in] handle
14912 * The indirect action object handle to be removed.
14913 * @param[out] error
14914 * Perform verbose error reporting if not NULL. Initialized in case of
14918 * 0 on success, otherwise negative errno value.
14921 flow_dv_action_destroy(struct rte_eth_dev *dev,
14922 struct rte_flow_action_handle *handle,
14923 struct rte_flow_error *error)
14925 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14926 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14927 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14928 struct mlx5_flow_counter *cnt;
14929 uint32_t no_flow_refcnt = 1;
14933 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14934 return __flow_dv_action_rss_release(dev, idx, error);
14935 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14936 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14937 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14938 &no_flow_refcnt, 1, false,
14941 return rte_flow_error_set(error, EBUSY,
14942 RTE_FLOW_ERROR_TYPE_ACTION,
14944 "Indirect count action has references");
14945 flow_dv_counter_free(dev, idx);
14947 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14948 ret = flow_dv_aso_age_release(dev, idx);
14951 * In this case, the last flow has a reference will
14952 * actually release the age action.
14954 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14955 " released with references %d.", idx, ret);
14957 case MLX5_INDIRECT_ACTION_TYPE_CT:
14958 ret = flow_dv_aso_ct_release(dev, idx, error);
14962 DRV_LOG(DEBUG, "Connection tracking object %u still "
14963 "has references %d.", idx, ret);
14966 return rte_flow_error_set(error, ENOTSUP,
14967 RTE_FLOW_ERROR_TYPE_ACTION,
14969 "action type not supported");
14974 * Updates in place shared RSS action configuration.
14977 * Pointer to the Ethernet device structure.
14979 * The shared RSS action object ID to be updated.
14980 * @param[in] action_conf
14981 * RSS action specification used to modify *shared_rss*.
14982 * @param[out] error
14983 * Perform verbose error reporting if not NULL. Initialized in case of
14987 * 0 on success, otherwise negative errno value.
14988 * @note: currently only support update of RSS queues.
14991 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
14992 const struct rte_flow_action_rss *action_conf,
14993 struct rte_flow_error *error)
14995 struct mlx5_priv *priv = dev->data->dev_private;
14996 struct mlx5_shared_action_rss *shared_rss =
14997 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14999 void *queue = NULL;
15000 uint16_t *queue_old = NULL;
15001 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15004 return rte_flow_error_set(error, EINVAL,
15005 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15006 "invalid shared action to update");
15007 if (priv->obj_ops.ind_table_modify == NULL)
15008 return rte_flow_error_set(error, ENOTSUP,
15009 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15010 "cannot modify indirection table");
15011 queue = mlx5_malloc(MLX5_MEM_ZERO,
15012 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15015 return rte_flow_error_set(error, ENOMEM,
15016 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15018 "cannot allocate resource memory");
15019 memcpy(queue, action_conf->queue, queue_size);
15020 MLX5_ASSERT(shared_rss->ind_tbl);
15021 rte_spinlock_lock(&shared_rss->action_rss_sl);
15022 queue_old = shared_rss->ind_tbl->queues;
15023 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15024 queue, action_conf->queue_num, true);
15027 ret = rte_flow_error_set(error, rte_errno,
15028 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15029 "cannot update indirection table");
15031 mlx5_free(queue_old);
15032 shared_rss->origin.queue = queue;
15033 shared_rss->origin.queue_num = action_conf->queue_num;
15035 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15040 * Updates in place conntrack context or direction.
15041 * Context update should be synchronized.
15044 * Pointer to the Ethernet device structure.
15046 * The conntrack object ID to be updated.
15047 * @param[in] update
15048 * Pointer to the structure of information to update.
15049 * @param[out] error
15050 * Perform verbose error reporting if not NULL. Initialized in case of
15054 * 0 on success, otherwise negative errno value.
15057 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15058 const struct rte_flow_modify_conntrack *update,
15059 struct rte_flow_error *error)
15061 struct mlx5_priv *priv = dev->data->dev_private;
15062 struct mlx5_aso_ct_action *ct;
15063 const struct rte_flow_action_conntrack *new_prf;
15065 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15068 if (PORT_ID(priv) != owner)
15069 return rte_flow_error_set(error, EACCES,
15070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15072 "CT object owned by another port");
15073 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15074 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15076 return rte_flow_error_set(error, ENOMEM,
15077 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15079 "CT object is inactive");
15080 new_prf = &update->new_ct;
15081 if (update->direction)
15082 ct->is_original = !!new_prf->is_original_dir;
15083 if (update->state) {
15084 /* Only validate the profile when it needs to be updated. */
15085 ret = mlx5_validate_action_ct(dev, new_prf, error);
15088 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15090 return rte_flow_error_set(error, EIO,
15091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15093 "Failed to send CT context update WQE");
15094 /* Block until ready or a failure. */
15095 ret = mlx5_aso_ct_available(priv->sh, ct);
15097 rte_flow_error_set(error, rte_errno,
15098 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15100 "Timeout to get the CT update");
15106 * Updates in place shared action configuration, lock free,
15107 * (mutex should be acquired by caller).
15110 * Pointer to the Ethernet device structure.
15111 * @param[in] handle
15112 * The indirect action object handle to be updated.
15113 * @param[in] update
15114 * Action specification used to modify the action pointed by *handle*.
15115 * *update* could be of same type with the action pointed by the *handle*
15116 * handle argument, or some other structures like a wrapper, depending on
15117 * the indirect action type.
15118 * @param[out] error
15119 * Perform verbose error reporting if not NULL. Initialized in case of
15123 * 0 on success, otherwise negative errno value.
15126 flow_dv_action_update(struct rte_eth_dev *dev,
15127 struct rte_flow_action_handle *handle,
15128 const void *update,
15129 struct rte_flow_error *err)
15131 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15132 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15133 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15134 const void *action_conf;
15137 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15138 action_conf = ((const struct rte_flow_action *)update)->conf;
15139 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15140 case MLX5_INDIRECT_ACTION_TYPE_CT:
15141 return __flow_dv_action_ct_update(dev, idx, update, err);
15143 return rte_flow_error_set(err, ENOTSUP,
15144 RTE_FLOW_ERROR_TYPE_ACTION,
15146 "action type update not supported");
15151 * Destroy the meter sub policy table rules.
15152 * Lock free, (mutex should be acquired by caller).
15155 * Pointer to Ethernet device.
15156 * @param[in] sub_policy
15157 * Pointer to meter sub policy table.
15160 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15161 struct mlx5_flow_meter_sub_policy *sub_policy)
15163 struct mlx5_priv *priv = dev->data->dev_private;
15164 struct mlx5_flow_tbl_data_entry *tbl;
15165 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15166 struct mlx5_flow_meter_info *next_fm;
15167 struct mlx5_sub_policy_color_rule *color_rule;
15171 for (i = 0; i < RTE_COLORS; i++) {
15173 if (i == RTE_COLOR_GREEN && policy &&
15174 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15175 next_fm = mlx5_flow_meter_find(priv,
15176 policy->act_cnt[i].next_mtr_id, NULL);
15177 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15179 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15180 tbl = container_of(color_rule->matcher->tbl,
15181 typeof(*tbl), tbl);
15182 mlx5_list_unregister(tbl->matchers,
15183 &color_rule->matcher->entry);
15184 TAILQ_REMOVE(&sub_policy->color_rules[i],
15185 color_rule, next_port);
15186 mlx5_free(color_rule);
15188 mlx5_flow_meter_detach(priv, next_fm);
15191 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15192 if (sub_policy->rix_hrxq[i]) {
15193 if (policy && !policy->is_hierarchy)
15194 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15195 sub_policy->rix_hrxq[i] = 0;
15197 if (sub_policy->jump_tbl[i]) {
15198 flow_dv_tbl_resource_release(MLX5_SH(dev),
15199 sub_policy->jump_tbl[i]);
15200 sub_policy->jump_tbl[i] = NULL;
15203 if (sub_policy->tbl_rsc) {
15204 flow_dv_tbl_resource_release(MLX5_SH(dev),
15205 sub_policy->tbl_rsc);
15206 sub_policy->tbl_rsc = NULL;
15211 * Destroy policy rules, lock free,
15212 * (mutex should be acquired by caller).
15213 * Dispatcher for action type specific call.
15216 * Pointer to the Ethernet device structure.
15217 * @param[in] mtr_policy
15218 * Meter policy struct.
15221 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15222 struct mlx5_flow_meter_policy *mtr_policy)
15225 struct mlx5_flow_meter_sub_policy *sub_policy;
15226 uint16_t sub_policy_num;
15228 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15229 sub_policy_num = (mtr_policy->sub_policy_num >>
15230 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15231 MLX5_MTR_SUB_POLICY_NUM_MASK;
15232 for (j = 0; j < sub_policy_num; j++) {
15233 sub_policy = mtr_policy->sub_policys[i][j];
15235 __flow_dv_destroy_sub_policy_rules(dev,
15242 * Destroy policy action, lock free,
15243 * (mutex should be acquired by caller).
15244 * Dispatcher for action type specific call.
15247 * Pointer to the Ethernet device structure.
15248 * @param[in] mtr_policy
15249 * Meter policy struct.
15252 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15253 struct mlx5_flow_meter_policy *mtr_policy)
15255 struct rte_flow_action *rss_action;
15256 struct mlx5_flow_handle dev_handle;
15259 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15260 if (mtr_policy->act_cnt[i].rix_mark) {
15261 flow_dv_tag_release(dev,
15262 mtr_policy->act_cnt[i].rix_mark);
15263 mtr_policy->act_cnt[i].rix_mark = 0;
15265 if (mtr_policy->act_cnt[i].modify_hdr) {
15266 dev_handle.dvh.modify_hdr =
15267 mtr_policy->act_cnt[i].modify_hdr;
15268 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15270 switch (mtr_policy->act_cnt[i].fate_action) {
15271 case MLX5_FLOW_FATE_SHARED_RSS:
15272 rss_action = mtr_policy->act_cnt[i].rss;
15273 mlx5_free(rss_action);
15275 case MLX5_FLOW_FATE_PORT_ID:
15276 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15277 flow_dv_port_id_action_resource_release(dev,
15278 mtr_policy->act_cnt[i].rix_port_id_action);
15279 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15282 case MLX5_FLOW_FATE_DROP:
15283 case MLX5_FLOW_FATE_JUMP:
15284 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15285 mtr_policy->act_cnt[i].dr_jump_action[j] =
15289 /*Queue action do nothing*/
15293 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15294 mtr_policy->dr_drop_action[j] = NULL;
15298 * Create policy action per domain, lock free,
15299 * (mutex should be acquired by caller).
15300 * Dispatcher for action type specific call.
15303 * Pointer to the Ethernet device structure.
15304 * @param[in] mtr_policy
15305 * Meter policy struct.
15306 * @param[in] action
15307 * Action specification used to create meter actions.
15308 * @param[out] error
15309 * Perform verbose error reporting if not NULL. Initialized in case of
15313 * 0 on success, otherwise negative errno value.
15316 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15317 struct mlx5_flow_meter_policy *mtr_policy,
15318 const struct rte_flow_action *actions[RTE_COLORS],
15319 enum mlx5_meter_domain domain,
15320 struct rte_mtr_error *error)
15322 struct mlx5_priv *priv = dev->data->dev_private;
15323 struct rte_flow_error flow_err;
15324 const struct rte_flow_action *act;
15325 uint64_t action_flags;
15326 struct mlx5_flow_handle dh;
15327 struct mlx5_flow dev_flow;
15328 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15330 uint8_t egress, transfer;
15331 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15333 struct mlx5_flow_dv_modify_hdr_resource res;
15334 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15335 sizeof(struct mlx5_modification_cmd) *
15336 (MLX5_MAX_MODIFY_NUM + 1)];
15338 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15340 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15341 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15342 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15343 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15344 memset(&port_id_action, 0,
15345 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15346 memset(mhdr_res, 0, sizeof(*mhdr_res));
15347 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15348 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15349 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15350 dev_flow.handle = &dh;
15351 dev_flow.dv.port_id_action = &port_id_action;
15352 dev_flow.external = true;
15353 for (i = 0; i < RTE_COLORS; i++) {
15354 if (i < MLX5_MTR_RTE_COLORS)
15355 act_cnt = &mtr_policy->act_cnt[i];
15356 /* Skip the color policy actions creation. */
15357 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15358 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15361 for (act = actions[i];
15362 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15363 switch (act->type) {
15364 case RTE_FLOW_ACTION_TYPE_MARK:
15366 uint32_t tag_be = mlx5_flow_mark_set
15367 (((const struct rte_flow_action_mark *)
15370 if (i >= MLX5_MTR_RTE_COLORS)
15371 return -rte_mtr_error_set(error,
15373 RTE_MTR_ERROR_TYPE_METER_POLICY,
15375 "cannot create policy "
15376 "mark action for this color");
15377 dev_flow.handle->mark = 1;
15378 if (flow_dv_tag_resource_register(dev, tag_be,
15379 &dev_flow, &flow_err))
15380 return -rte_mtr_error_set(error,
15382 RTE_MTR_ERROR_TYPE_METER_POLICY,
15384 "cannot setup policy mark action");
15385 MLX5_ASSERT(dev_flow.dv.tag_resource);
15386 act_cnt->rix_mark =
15387 dev_flow.handle->dvh.rix_tag;
15388 action_flags |= MLX5_FLOW_ACTION_MARK;
15391 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15392 if (i >= MLX5_MTR_RTE_COLORS)
15393 return -rte_mtr_error_set(error,
15395 RTE_MTR_ERROR_TYPE_METER_POLICY,
15397 "cannot create policy "
15398 "set tag action for this color");
15399 if (flow_dv_convert_action_set_tag
15401 (const struct rte_flow_action_set_tag *)
15402 act->conf, &flow_err))
15403 return -rte_mtr_error_set(error,
15405 RTE_MTR_ERROR_TYPE_METER_POLICY,
15406 NULL, "cannot convert policy "
15408 if (!mhdr_res->actions_num)
15409 return -rte_mtr_error_set(error,
15411 RTE_MTR_ERROR_TYPE_METER_POLICY,
15412 NULL, "cannot find policy "
15414 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15416 case RTE_FLOW_ACTION_TYPE_DROP:
15418 struct mlx5_flow_mtr_mng *mtrmng =
15420 struct mlx5_flow_tbl_data_entry *tbl_data;
15423 * Create the drop table with
15424 * METER DROP level.
15426 if (!mtrmng->drop_tbl[domain]) {
15427 mtrmng->drop_tbl[domain] =
15428 flow_dv_tbl_resource_get(dev,
15429 MLX5_FLOW_TABLE_LEVEL_METER,
15430 egress, transfer, false, NULL, 0,
15431 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15432 if (!mtrmng->drop_tbl[domain])
15433 return -rte_mtr_error_set
15435 RTE_MTR_ERROR_TYPE_METER_POLICY,
15437 "Failed to create meter drop table");
15439 tbl_data = container_of
15440 (mtrmng->drop_tbl[domain],
15441 struct mlx5_flow_tbl_data_entry, tbl);
15442 if (i < MLX5_MTR_RTE_COLORS) {
15443 act_cnt->dr_jump_action[domain] =
15444 tbl_data->jump.action;
15445 act_cnt->fate_action =
15446 MLX5_FLOW_FATE_DROP;
15448 if (i == RTE_COLOR_RED)
15449 mtr_policy->dr_drop_action[domain] =
15450 tbl_data->jump.action;
15451 action_flags |= MLX5_FLOW_ACTION_DROP;
15454 case RTE_FLOW_ACTION_TYPE_QUEUE:
15456 if (i >= MLX5_MTR_RTE_COLORS)
15457 return -rte_mtr_error_set(error,
15459 RTE_MTR_ERROR_TYPE_METER_POLICY,
15460 NULL, "cannot create policy "
15461 "fate queue for this color");
15463 ((const struct rte_flow_action_queue *)
15464 (act->conf))->index;
15465 act_cnt->fate_action =
15466 MLX5_FLOW_FATE_QUEUE;
15467 dev_flow.handle->fate_action =
15468 MLX5_FLOW_FATE_QUEUE;
15469 mtr_policy->is_queue = 1;
15470 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15473 case RTE_FLOW_ACTION_TYPE_RSS:
15477 if (i >= MLX5_MTR_RTE_COLORS)
15478 return -rte_mtr_error_set(error,
15480 RTE_MTR_ERROR_TYPE_METER_POLICY,
15482 "cannot create policy "
15483 "rss action for this color");
15485 * Save RSS conf into policy struct
15486 * for translate stage.
15488 rss_size = (int)rte_flow_conv
15489 (RTE_FLOW_CONV_OP_ACTION,
15490 NULL, 0, act, &flow_err);
15492 return -rte_mtr_error_set(error,
15494 RTE_MTR_ERROR_TYPE_METER_POLICY,
15495 NULL, "Get the wrong "
15496 "rss action struct size");
15497 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15498 rss_size, 0, SOCKET_ID_ANY);
15500 return -rte_mtr_error_set(error,
15502 RTE_MTR_ERROR_TYPE_METER_POLICY,
15504 "Fail to malloc rss action memory");
15505 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15506 act_cnt->rss, rss_size,
15509 return -rte_mtr_error_set(error,
15511 RTE_MTR_ERROR_TYPE_METER_POLICY,
15512 NULL, "Fail to save "
15513 "rss action into policy struct");
15514 act_cnt->fate_action =
15515 MLX5_FLOW_FATE_SHARED_RSS;
15516 action_flags |= MLX5_FLOW_ACTION_RSS;
15519 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15520 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15522 struct mlx5_flow_dv_port_id_action_resource
15524 uint32_t port_id = 0;
15526 if (i >= MLX5_MTR_RTE_COLORS)
15527 return -rte_mtr_error_set(error,
15529 RTE_MTR_ERROR_TYPE_METER_POLICY,
15530 NULL, "cannot create policy "
15531 "port action for this color");
15532 memset(&port_id_resource, 0,
15533 sizeof(port_id_resource));
15534 if (flow_dv_translate_action_port_id(dev, act,
15535 &port_id, &flow_err))
15536 return -rte_mtr_error_set(error,
15538 RTE_MTR_ERROR_TYPE_METER_POLICY,
15539 NULL, "cannot translate "
15540 "policy port action");
15541 port_id_resource.port_id = port_id;
15542 if (flow_dv_port_id_action_resource_register
15543 (dev, &port_id_resource,
15544 &dev_flow, &flow_err))
15545 return -rte_mtr_error_set(error,
15547 RTE_MTR_ERROR_TYPE_METER_POLICY,
15548 NULL, "cannot setup "
15549 "policy port action");
15550 act_cnt->rix_port_id_action =
15551 dev_flow.handle->rix_port_id_action;
15552 act_cnt->fate_action =
15553 MLX5_FLOW_FATE_PORT_ID;
15554 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15557 case RTE_FLOW_ACTION_TYPE_JUMP:
15559 uint32_t jump_group = 0;
15560 uint32_t table = 0;
15561 struct mlx5_flow_tbl_data_entry *tbl_data;
15562 struct flow_grp_info grp_info = {
15563 .external = !!dev_flow.external,
15564 .transfer = !!transfer,
15565 .fdb_def_rule = !!priv->fdb_def_rule,
15567 .skip_scale = dev_flow.skip_scale &
15568 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15570 struct mlx5_flow_meter_sub_policy *sub_policy =
15571 mtr_policy->sub_policys[domain][0];
15573 if (i >= MLX5_MTR_RTE_COLORS)
15574 return -rte_mtr_error_set(error,
15576 RTE_MTR_ERROR_TYPE_METER_POLICY,
15578 "cannot create policy "
15579 "jump action for this color");
15581 ((const struct rte_flow_action_jump *)
15583 if (mlx5_flow_group_to_table(dev, NULL,
15586 &grp_info, &flow_err))
15587 return -rte_mtr_error_set(error,
15589 RTE_MTR_ERROR_TYPE_METER_POLICY,
15590 NULL, "cannot setup "
15591 "policy jump action");
15592 sub_policy->jump_tbl[i] =
15593 flow_dv_tbl_resource_get(dev,
15596 !!dev_flow.external,
15597 NULL, jump_group, 0,
15600 (!sub_policy->jump_tbl[i])
15601 return -rte_mtr_error_set(error,
15603 RTE_MTR_ERROR_TYPE_METER_POLICY,
15604 NULL, "cannot create jump action.");
15605 tbl_data = container_of
15606 (sub_policy->jump_tbl[i],
15607 struct mlx5_flow_tbl_data_entry, tbl);
15608 act_cnt->dr_jump_action[domain] =
15609 tbl_data->jump.action;
15610 act_cnt->fate_action =
15611 MLX5_FLOW_FATE_JUMP;
15612 action_flags |= MLX5_FLOW_ACTION_JUMP;
15616 * No need to check meter hierarchy for Y or R colors
15617 * here since it is done in the validation stage.
15619 case RTE_FLOW_ACTION_TYPE_METER:
15621 const struct rte_flow_action_meter *mtr;
15622 struct mlx5_flow_meter_info *next_fm;
15623 struct mlx5_flow_meter_policy *next_policy;
15624 struct rte_flow_action tag_action;
15625 struct mlx5_rte_flow_action_set_tag set_tag;
15626 uint32_t next_mtr_idx = 0;
15629 next_fm = mlx5_flow_meter_find(priv,
15633 return -rte_mtr_error_set(error, EINVAL,
15634 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15635 "Fail to find next meter.");
15636 if (next_fm->def_policy)
15637 return -rte_mtr_error_set(error, EINVAL,
15638 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15639 "Hierarchy only supports termination meter.");
15640 next_policy = mlx5_flow_meter_policy_find(dev,
15641 next_fm->policy_id, NULL);
15642 MLX5_ASSERT(next_policy);
15643 if (next_fm->drop_cnt) {
15646 mlx5_flow_get_reg_id(dev,
15649 (struct rte_flow_error *)error);
15650 set_tag.offset = (priv->mtr_reg_share ?
15651 MLX5_MTR_COLOR_BITS : 0);
15652 set_tag.length = (priv->mtr_reg_share ?
15653 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15655 set_tag.data = next_mtr_idx;
15657 (enum rte_flow_action_type)
15658 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15659 tag_action.conf = &set_tag;
15660 if (flow_dv_convert_action_set_reg
15661 (mhdr_res, &tag_action,
15662 (struct rte_flow_error *)error))
15665 MLX5_FLOW_ACTION_SET_TAG;
15667 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15668 act_cnt->next_mtr_id = next_fm->meter_id;
15669 act_cnt->next_sub_policy = NULL;
15670 mtr_policy->is_hierarchy = 1;
15671 mtr_policy->dev = next_policy->dev;
15673 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15677 return -rte_mtr_error_set(error, ENOTSUP,
15678 RTE_MTR_ERROR_TYPE_METER_POLICY,
15679 NULL, "action type not supported");
15681 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15682 /* create modify action if needed. */
15683 dev_flow.dv.group = 1;
15684 if (flow_dv_modify_hdr_resource_register
15685 (dev, mhdr_res, &dev_flow, &flow_err))
15686 return -rte_mtr_error_set(error,
15688 RTE_MTR_ERROR_TYPE_METER_POLICY,
15689 NULL, "cannot register policy "
15691 act_cnt->modify_hdr =
15692 dev_flow.handle->dvh.modify_hdr;
15700 * Create policy action per domain, lock free,
15701 * (mutex should be acquired by caller).
15702 * Dispatcher for action type specific call.
15705 * Pointer to the Ethernet device structure.
15706 * @param[in] mtr_policy
15707 * Meter policy struct.
15708 * @param[in] action
15709 * Action specification used to create meter actions.
15710 * @param[out] error
15711 * Perform verbose error reporting if not NULL. Initialized in case of
15715 * 0 on success, otherwise negative errno value.
15718 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15719 struct mlx5_flow_meter_policy *mtr_policy,
15720 const struct rte_flow_action *actions[RTE_COLORS],
15721 struct rte_mtr_error *error)
15724 uint16_t sub_policy_num;
15726 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15727 sub_policy_num = (mtr_policy->sub_policy_num >>
15728 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15729 MLX5_MTR_SUB_POLICY_NUM_MASK;
15730 if (sub_policy_num) {
15731 ret = __flow_dv_create_domain_policy_acts(dev,
15732 mtr_policy, actions,
15733 (enum mlx5_meter_domain)i, error);
15734 /* Cleaning resource is done in the caller level. */
15743 * Query a DV flow rule for its statistics via DevX.
15746 * Pointer to Ethernet device.
15747 * @param[in] cnt_idx
15748 * Index to the flow counter.
15750 * Data retrieved by the query.
15751 * @param[out] error
15752 * Perform verbose error reporting if not NULL.
15755 * 0 on success, a negative errno value otherwise and rte_errno is set.
15758 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15759 struct rte_flow_error *error)
15761 struct mlx5_priv *priv = dev->data->dev_private;
15762 struct rte_flow_query_count *qc = data;
15764 if (!priv->sh->devx)
15765 return rte_flow_error_set(error, ENOTSUP,
15766 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15768 "counters are not supported");
15770 uint64_t pkts, bytes;
15771 struct mlx5_flow_counter *cnt;
15772 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15775 return rte_flow_error_set(error, -err,
15776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15777 NULL, "cannot read counters");
15778 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15781 qc->hits = pkts - cnt->hits;
15782 qc->bytes = bytes - cnt->bytes;
15785 cnt->bytes = bytes;
15789 return rte_flow_error_set(error, EINVAL,
15790 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15792 "counters are not available");
15797 * Query counter's action pointer for a DV flow rule via DevX.
15800 * Pointer to Ethernet device.
15801 * @param[in] cnt_idx
15802 * Index to the flow counter.
15803 * @param[out] action_ptr
15804 * Action pointer for counter.
15805 * @param[out] error
15806 * Perform verbose error reporting if not NULL.
15809 * 0 on success, a negative errno value otherwise and rte_errno is set.
15812 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15813 void **action_ptr, struct rte_flow_error *error)
15815 struct mlx5_priv *priv = dev->data->dev_private;
15817 if (!priv->sh->devx || !action_ptr)
15818 return rte_flow_error_set(error, ENOTSUP,
15819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15821 "counters are not supported");
15824 struct mlx5_flow_counter *cnt = NULL;
15825 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15827 *action_ptr = cnt->action;
15831 return rte_flow_error_set(error, EINVAL,
15832 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15834 "counters are not available");
15838 flow_dv_action_query(struct rte_eth_dev *dev,
15839 const struct rte_flow_action_handle *handle, void *data,
15840 struct rte_flow_error *error)
15842 struct mlx5_age_param *age_param;
15843 struct rte_flow_query_age *resp;
15844 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15845 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15846 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15847 struct mlx5_priv *priv = dev->data->dev_private;
15848 struct mlx5_aso_ct_action *ct;
15853 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15854 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15856 resp->aged = __atomic_load_n(&age_param->state,
15857 __ATOMIC_RELAXED) == AGE_TMOUT ?
15859 resp->sec_since_last_hit_valid = !resp->aged;
15860 if (resp->sec_since_last_hit_valid)
15861 resp->sec_since_last_hit = __atomic_load_n
15862 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15864 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15865 return flow_dv_query_count(dev, idx, data, error);
15866 case MLX5_INDIRECT_ACTION_TYPE_CT:
15867 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15868 if (owner != PORT_ID(priv))
15869 return rte_flow_error_set(error, EACCES,
15870 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15872 "CT object owned by another port");
15873 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15874 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15877 return rte_flow_error_set(error, EFAULT,
15878 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15880 "CT object is inactive");
15881 ((struct rte_flow_action_conntrack *)data)->peer_port =
15883 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15885 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15886 return rte_flow_error_set(error, EIO,
15887 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15889 "Failed to query CT context");
15892 return rte_flow_error_set(error, ENOTSUP,
15893 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15894 "action type query not supported");
15899 * Query a flow rule AGE action for aging information.
15902 * Pointer to Ethernet device.
15904 * Pointer to the sub flow.
15906 * data retrieved by the query.
15907 * @param[out] error
15908 * Perform verbose error reporting if not NULL.
15911 * 0 on success, a negative errno value otherwise and rte_errno is set.
15914 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15915 void *data, struct rte_flow_error *error)
15917 struct rte_flow_query_age *resp = data;
15918 struct mlx5_age_param *age_param;
15921 struct mlx5_aso_age_action *act =
15922 flow_aso_age_get_by_idx(dev, flow->age);
15924 age_param = &act->age_params;
15925 } else if (flow->counter) {
15926 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15928 if (!age_param || !age_param->timeout)
15929 return rte_flow_error_set
15931 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15932 NULL, "cannot read age data");
15934 return rte_flow_error_set(error, EINVAL,
15935 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15936 NULL, "age data not available");
15938 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15940 resp->sec_since_last_hit_valid = !resp->aged;
15941 if (resp->sec_since_last_hit_valid)
15942 resp->sec_since_last_hit = __atomic_load_n
15943 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15950 * @see rte_flow_query()
15951 * @see rte_flow_ops
15954 flow_dv_query(struct rte_eth_dev *dev,
15955 struct rte_flow *flow __rte_unused,
15956 const struct rte_flow_action *actions __rte_unused,
15957 void *data __rte_unused,
15958 struct rte_flow_error *error __rte_unused)
15962 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15963 switch (actions->type) {
15964 case RTE_FLOW_ACTION_TYPE_VOID:
15966 case RTE_FLOW_ACTION_TYPE_COUNT:
15967 ret = flow_dv_query_count(dev, flow->counter, data,
15970 case RTE_FLOW_ACTION_TYPE_AGE:
15971 ret = flow_dv_query_age(dev, flow, data, error);
15974 return rte_flow_error_set(error, ENOTSUP,
15975 RTE_FLOW_ERROR_TYPE_ACTION,
15977 "action not supported");
15984 * Destroy the meter table set.
15985 * Lock free, (mutex should be acquired by caller).
15988 * Pointer to Ethernet device.
15990 * Meter information table.
15993 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
15994 struct mlx5_flow_meter_info *fm)
15996 struct mlx5_priv *priv = dev->data->dev_private;
15999 if (!fm || !priv->config.dv_flow_en)
16001 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16002 if (fm->drop_rule[i]) {
16003 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16004 fm->drop_rule[i] = NULL;
16010 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16012 struct mlx5_priv *priv = dev->data->dev_private;
16013 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16014 struct mlx5_flow_tbl_data_entry *tbl;
16017 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16018 if (mtrmng->def_rule[i]) {
16019 claim_zero(mlx5_flow_os_destroy_flow
16020 (mtrmng->def_rule[i]));
16021 mtrmng->def_rule[i] = NULL;
16023 if (mtrmng->def_matcher[i]) {
16024 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16025 struct mlx5_flow_tbl_data_entry, tbl);
16026 mlx5_list_unregister(tbl->matchers,
16027 &mtrmng->def_matcher[i]->entry);
16028 mtrmng->def_matcher[i] = NULL;
16030 for (j = 0; j < MLX5_REG_BITS; j++) {
16031 if (mtrmng->drop_matcher[i][j]) {
16033 container_of(mtrmng->drop_matcher[i][j]->tbl,
16034 struct mlx5_flow_tbl_data_entry,
16036 mlx5_list_unregister(tbl->matchers,
16037 &mtrmng->drop_matcher[i][j]->entry);
16038 mtrmng->drop_matcher[i][j] = NULL;
16041 if (mtrmng->drop_tbl[i]) {
16042 flow_dv_tbl_resource_release(MLX5_SH(dev),
16043 mtrmng->drop_tbl[i]);
16044 mtrmng->drop_tbl[i] = NULL;
16049 /* Number of meter flow actions, count and jump or count and drop. */
16050 #define METER_ACTIONS 2
16053 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16054 enum mlx5_meter_domain domain)
16056 struct mlx5_priv *priv = dev->data->dev_private;
16057 struct mlx5_flow_meter_def_policy *def_policy =
16058 priv->sh->mtrmng->def_policy[domain];
16060 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16061 mlx5_free(def_policy);
16062 priv->sh->mtrmng->def_policy[domain] = NULL;
16066 * Destroy the default policy table set.
16069 * Pointer to Ethernet device.
16072 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16074 struct mlx5_priv *priv = dev->data->dev_private;
16077 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16078 if (priv->sh->mtrmng->def_policy[i])
16079 __flow_dv_destroy_domain_def_policy(dev,
16080 (enum mlx5_meter_domain)i);
16081 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16085 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16086 uint32_t color_reg_c_idx,
16087 enum rte_color color, void *matcher_object,
16088 int actions_n, void *actions,
16089 bool match_src_port, const struct rte_flow_item *item,
16090 void **rule, const struct rte_flow_attr *attr)
16093 struct mlx5_flow_dv_match_params value = {
16094 .size = sizeof(value.buf),
16096 struct mlx5_flow_dv_match_params matcher = {
16097 .size = sizeof(matcher.buf),
16099 struct mlx5_priv *priv = dev->data->dev_private;
16102 if (match_src_port && (priv->representor || priv->master)) {
16103 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16104 value.buf, item, attr)) {
16105 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16106 " value with port.", color);
16110 flow_dv_match_meta_reg(matcher.buf, value.buf,
16111 (enum modify_reg)color_reg_c_idx,
16112 rte_col_2_mlx5_col(color), UINT32_MAX);
16113 misc_mask = flow_dv_matcher_enable(value.buf);
16114 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16115 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16116 actions_n, actions, rule);
16118 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16125 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16126 uint32_t color_reg_c_idx,
16128 struct mlx5_flow_meter_sub_policy *sub_policy,
16129 const struct rte_flow_attr *attr,
16130 bool match_src_port,
16131 const struct rte_flow_item *item,
16132 struct mlx5_flow_dv_matcher **policy_matcher,
16133 struct rte_flow_error *error)
16135 struct mlx5_list_entry *entry;
16136 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16137 struct mlx5_flow_dv_matcher matcher = {
16139 .size = sizeof(matcher.mask.buf),
16143 struct mlx5_flow_dv_match_params value = {
16144 .size = sizeof(value.buf),
16146 struct mlx5_flow_cb_ctx ctx = {
16150 struct mlx5_flow_tbl_data_entry *tbl_data;
16151 struct mlx5_priv *priv = dev->data->dev_private;
16152 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16154 if (match_src_port && (priv->representor || priv->master)) {
16155 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16156 value.buf, item, attr)) {
16157 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16158 " with port.", priority);
16162 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16163 if (priority < RTE_COLOR_RED)
16164 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16165 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16166 matcher.priority = priority;
16167 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16168 matcher.mask.size);
16169 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16171 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16175 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16180 * Create the policy rules per domain.
16183 * Pointer to Ethernet device.
16184 * @param[in] sub_policy
16185 * Pointer to sub policy table..
16186 * @param[in] egress
16187 * Direction of the table.
16188 * @param[in] transfer
16189 * E-Switch or NIC flow.
16191 * Pointer to policy action list per color.
16194 * 0 on success, -1 otherwise.
16197 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16198 struct mlx5_flow_meter_sub_policy *sub_policy,
16199 uint8_t egress, uint8_t transfer, bool match_src_port,
16200 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16202 struct mlx5_priv *priv = dev->data->dev_private;
16203 struct rte_flow_error flow_err;
16204 uint32_t color_reg_c_idx;
16205 struct rte_flow_attr attr = {
16206 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16209 .egress = !!egress,
16210 .transfer = !!transfer,
16214 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16215 struct mlx5_sub_policy_color_rule *color_rule;
16217 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16221 /* Create policy table with POLICY level. */
16222 if (!sub_policy->tbl_rsc)
16223 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16224 MLX5_FLOW_TABLE_LEVEL_POLICY,
16225 egress, transfer, false, NULL, 0, 0,
16226 sub_policy->idx, &flow_err);
16227 if (!sub_policy->tbl_rsc) {
16229 "Failed to create meter sub policy table.");
16232 /* Prepare matchers. */
16233 color_reg_c_idx = ret;
16234 for (i = 0; i < RTE_COLORS; i++) {
16235 TAILQ_INIT(&sub_policy->color_rules[i]);
16236 if (!acts[i].actions_n)
16238 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16239 sizeof(struct mlx5_sub_policy_color_rule),
16242 DRV_LOG(ERR, "No memory to create color rule.");
16245 tmp_rules[i] = color_rule;
16246 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16247 color_rule, next_port);
16248 color_rule->src_port = priv->representor_id;
16251 /* Create matchers for colors. */
16252 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16253 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16254 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16255 &attr, svport_match, NULL,
16256 &color_rule->matcher, &flow_err)) {
16257 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16260 /* Create flow, matching color. */
16261 if (__flow_dv_create_policy_flow(dev,
16262 color_reg_c_idx, (enum rte_color)i,
16263 color_rule->matcher->matcher_object,
16264 acts[i].actions_n, acts[i].dv_actions,
16265 svport_match, NULL, &color_rule->rule,
16267 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16273 /* All the policy rules will be cleared. */
16275 color_rule = tmp_rules[i];
16277 if (color_rule->rule)
16278 mlx5_flow_os_destroy_flow(color_rule->rule);
16279 if (color_rule->matcher) {
16280 struct mlx5_flow_tbl_data_entry *tbl =
16281 container_of(color_rule->matcher->tbl,
16282 typeof(*tbl), tbl);
16283 mlx5_list_unregister(tbl->matchers,
16284 &color_rule->matcher->entry);
16286 TAILQ_REMOVE(&sub_policy->color_rules[i],
16287 color_rule, next_port);
16288 mlx5_free(color_rule);
16295 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16296 struct mlx5_flow_meter_policy *mtr_policy,
16297 struct mlx5_flow_meter_sub_policy *sub_policy,
16300 struct mlx5_priv *priv = dev->data->dev_private;
16301 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16302 struct mlx5_flow_dv_tag_resource *tag;
16303 struct mlx5_flow_dv_port_id_action_resource *port_action;
16304 struct mlx5_hrxq *hrxq;
16305 struct mlx5_flow_meter_info *next_fm = NULL;
16306 struct mlx5_flow_meter_policy *next_policy;
16307 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16308 struct mlx5_flow_tbl_data_entry *tbl_data;
16309 struct rte_flow_error error;
16310 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16311 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16312 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16313 bool match_src_port = false;
16316 /* If RSS or Queue, no previous actions / rules is created. */
16317 for (i = 0; i < RTE_COLORS; i++) {
16318 acts[i].actions_n = 0;
16319 if (i == RTE_COLOR_RED) {
16320 /* Only support drop on red. */
16321 acts[i].dv_actions[0] =
16322 mtr_policy->dr_drop_action[domain];
16323 acts[i].actions_n = 1;
16326 if (i == RTE_COLOR_GREEN &&
16327 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16328 struct rte_flow_attr attr = {
16329 .transfer = transfer
16332 next_fm = mlx5_flow_meter_find(priv,
16333 mtr_policy->act_cnt[i].next_mtr_id,
16337 "Failed to get next hierarchy meter.");
16340 if (mlx5_flow_meter_attach(priv, next_fm,
16342 DRV_LOG(ERR, "%s", error.message);
16346 /* Meter action must be the first for TX. */
16348 acts[i].dv_actions[acts[i].actions_n] =
16349 next_fm->meter_action;
16350 acts[i].actions_n++;
16353 if (mtr_policy->act_cnt[i].rix_mark) {
16354 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16355 mtr_policy->act_cnt[i].rix_mark);
16357 DRV_LOG(ERR, "Failed to find "
16358 "mark action for policy.");
16361 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16362 acts[i].actions_n++;
16364 if (mtr_policy->act_cnt[i].modify_hdr) {
16365 acts[i].dv_actions[acts[i].actions_n] =
16366 mtr_policy->act_cnt[i].modify_hdr->action;
16367 acts[i].actions_n++;
16369 if (mtr_policy->act_cnt[i].fate_action) {
16370 switch (mtr_policy->act_cnt[i].fate_action) {
16371 case MLX5_FLOW_FATE_PORT_ID:
16372 port_action = mlx5_ipool_get
16373 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16374 mtr_policy->act_cnt[i].rix_port_id_action);
16375 if (!port_action) {
16376 DRV_LOG(ERR, "Failed to find "
16377 "port action for policy.");
16380 acts[i].dv_actions[acts[i].actions_n] =
16381 port_action->action;
16382 acts[i].actions_n++;
16383 mtr_policy->dev = dev;
16384 match_src_port = true;
16386 case MLX5_FLOW_FATE_DROP:
16387 case MLX5_FLOW_FATE_JUMP:
16388 acts[i].dv_actions[acts[i].actions_n] =
16389 mtr_policy->act_cnt[i].dr_jump_action[domain];
16390 acts[i].actions_n++;
16392 case MLX5_FLOW_FATE_SHARED_RSS:
16393 case MLX5_FLOW_FATE_QUEUE:
16394 hrxq = mlx5_ipool_get
16395 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16396 sub_policy->rix_hrxq[i]);
16398 DRV_LOG(ERR, "Failed to find "
16399 "queue action for policy.");
16402 acts[i].dv_actions[acts[i].actions_n] =
16404 acts[i].actions_n++;
16406 case MLX5_FLOW_FATE_MTR:
16409 "No next hierarchy meter.");
16413 acts[i].dv_actions[acts[i].actions_n] =
16414 next_fm->meter_action;
16415 acts[i].actions_n++;
16417 if (mtr_policy->act_cnt[i].next_sub_policy) {
16419 mtr_policy->act_cnt[i].next_sub_policy;
16422 mlx5_flow_meter_policy_find(dev,
16423 next_fm->policy_id, NULL);
16424 MLX5_ASSERT(next_policy);
16426 next_policy->sub_policys[domain][0];
16429 container_of(next_sub_policy->tbl_rsc,
16430 struct mlx5_flow_tbl_data_entry, tbl);
16431 acts[i].dv_actions[acts[i].actions_n++] =
16432 tbl_data->jump.action;
16433 if (mtr_policy->act_cnt[i].modify_hdr)
16434 match_src_port = !!transfer;
16437 /*Queue action do nothing*/
16442 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16443 egress, transfer, match_src_port, acts)) {
16445 "Failed to create policy rules per domain.");
16451 mlx5_flow_meter_detach(priv, next_fm);
16456 * Create the policy rules.
16459 * Pointer to Ethernet device.
16460 * @param[in,out] mtr_policy
16461 * Pointer to meter policy table.
16464 * 0 on success, -1 otherwise.
16467 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16468 struct mlx5_flow_meter_policy *mtr_policy)
16471 uint16_t sub_policy_num;
16473 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16474 sub_policy_num = (mtr_policy->sub_policy_num >>
16475 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16476 MLX5_MTR_SUB_POLICY_NUM_MASK;
16477 if (!sub_policy_num)
16479 /* Prepare actions list and create policy rules. */
16480 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16481 mtr_policy->sub_policys[i][0], i)) {
16482 DRV_LOG(ERR, "Failed to create policy action "
16483 "list per domain.");
16491 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16493 struct mlx5_priv *priv = dev->data->dev_private;
16494 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16495 struct mlx5_flow_meter_def_policy *def_policy;
16496 struct mlx5_flow_tbl_resource *jump_tbl;
16497 struct mlx5_flow_tbl_data_entry *tbl_data;
16498 uint8_t egress, transfer;
16499 struct rte_flow_error error;
16500 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16503 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16504 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16505 def_policy = mtrmng->def_policy[domain];
16507 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16508 sizeof(struct mlx5_flow_meter_def_policy),
16509 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16511 DRV_LOG(ERR, "Failed to alloc default policy table.");
16512 goto def_policy_error;
16514 mtrmng->def_policy[domain] = def_policy;
16515 /* Create the meter suffix table with SUFFIX level. */
16516 jump_tbl = flow_dv_tbl_resource_get(dev,
16517 MLX5_FLOW_TABLE_LEVEL_METER,
16518 egress, transfer, false, NULL, 0,
16519 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16522 "Failed to create meter suffix table.");
16523 goto def_policy_error;
16525 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16526 tbl_data = container_of(jump_tbl,
16527 struct mlx5_flow_tbl_data_entry, tbl);
16528 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16529 tbl_data->jump.action;
16530 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16531 acts[RTE_COLOR_GREEN].actions_n = 1;
16533 * YELLOW has the same default policy as GREEN does.
16534 * G & Y share the same table and action. The 2nd time of table
16535 * resource getting is just to update the reference count for
16536 * the releasing stage.
16538 jump_tbl = flow_dv_tbl_resource_get(dev,
16539 MLX5_FLOW_TABLE_LEVEL_METER,
16540 egress, transfer, false, NULL, 0,
16541 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16544 "Failed to get meter suffix table.");
16545 goto def_policy_error;
16547 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16548 tbl_data = container_of(jump_tbl,
16549 struct mlx5_flow_tbl_data_entry, tbl);
16550 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16551 tbl_data->jump.action;
16552 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16553 acts[RTE_COLOR_YELLOW].actions_n = 1;
16554 /* Create jump action to the drop table. */
16555 if (!mtrmng->drop_tbl[domain]) {
16556 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16557 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16558 egress, transfer, false, NULL, 0,
16559 0, MLX5_MTR_TABLE_ID_DROP, &error);
16560 if (!mtrmng->drop_tbl[domain]) {
16561 DRV_LOG(ERR, "Failed to create meter "
16562 "drop table for default policy.");
16563 goto def_policy_error;
16566 /* all RED: unique Drop table for jump action. */
16567 tbl_data = container_of(mtrmng->drop_tbl[domain],
16568 struct mlx5_flow_tbl_data_entry, tbl);
16569 def_policy->dr_jump_action[RTE_COLOR_RED] =
16570 tbl_data->jump.action;
16571 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16572 acts[RTE_COLOR_RED].actions_n = 1;
16573 /* Create default policy rules. */
16574 ret = __flow_dv_create_domain_policy_rules(dev,
16575 &def_policy->sub_policy,
16576 egress, transfer, false, acts);
16578 DRV_LOG(ERR, "Failed to create default policy rules.");
16579 goto def_policy_error;
16584 __flow_dv_destroy_domain_def_policy(dev,
16585 (enum mlx5_meter_domain)domain);
16590 * Create the default policy table set.
16593 * Pointer to Ethernet device.
16595 * 0 on success, -1 otherwise.
16598 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16600 struct mlx5_priv *priv = dev->data->dev_private;
16603 /* Non-termination policy table. */
16604 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16605 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16607 if (__flow_dv_create_domain_def_policy(dev, i)) {
16608 DRV_LOG(ERR, "Failed to create default policy");
16609 /* Rollback the created default policies for others. */
16610 flow_dv_destroy_def_policy(dev);
16618 * Create the needed meter tables.
16619 * Lock free, (mutex should be acquired by caller).
16622 * Pointer to Ethernet device.
16624 * Meter information table.
16625 * @param[in] mtr_idx
16627 * @param[in] domain_bitmap
16630 * 0 on success, -1 otherwise.
16633 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16634 struct mlx5_flow_meter_info *fm,
16636 uint8_t domain_bitmap)
16638 struct mlx5_priv *priv = dev->data->dev_private;
16639 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16640 struct rte_flow_error error;
16641 struct mlx5_flow_tbl_data_entry *tbl_data;
16642 uint8_t egress, transfer;
16643 void *actions[METER_ACTIONS];
16644 int domain, ret, i;
16645 struct mlx5_flow_counter *cnt;
16646 struct mlx5_flow_dv_match_params value = {
16647 .size = sizeof(value.buf),
16649 struct mlx5_flow_dv_match_params matcher_para = {
16650 .size = sizeof(matcher_para.buf),
16652 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16654 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16655 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16656 struct mlx5_list_entry *entry;
16657 struct mlx5_flow_dv_matcher matcher = {
16659 .size = sizeof(matcher.mask.buf),
16662 struct mlx5_flow_dv_matcher *drop_matcher;
16663 struct mlx5_flow_cb_ctx ctx = {
16669 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16670 rte_errno = ENOTSUP;
16673 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16674 if (!(domain_bitmap & (1 << domain)) ||
16675 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16677 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16678 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16679 /* Create the drop table with METER DROP level. */
16680 if (!mtrmng->drop_tbl[domain]) {
16681 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16682 MLX5_FLOW_TABLE_LEVEL_METER,
16683 egress, transfer, false, NULL, 0,
16684 0, MLX5_MTR_TABLE_ID_DROP, &error);
16685 if (!mtrmng->drop_tbl[domain]) {
16686 DRV_LOG(ERR, "Failed to create meter drop table.");
16690 /* Create default matcher in drop table. */
16691 matcher.tbl = mtrmng->drop_tbl[domain],
16692 tbl_data = container_of(mtrmng->drop_tbl[domain],
16693 struct mlx5_flow_tbl_data_entry, tbl);
16694 if (!mtrmng->def_matcher[domain]) {
16695 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16696 (enum modify_reg)mtr_id_reg_c,
16698 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16699 matcher.crc = rte_raw_cksum
16700 ((const void *)matcher.mask.buf,
16701 matcher.mask.size);
16702 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16704 DRV_LOG(ERR, "Failed to register meter "
16705 "drop default matcher.");
16708 mtrmng->def_matcher[domain] = container_of(entry,
16709 struct mlx5_flow_dv_matcher, entry);
16711 /* Create default rule in drop table. */
16712 if (!mtrmng->def_rule[domain]) {
16714 actions[i++] = priv->sh->dr_drop_action;
16715 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16716 (enum modify_reg)mtr_id_reg_c, 0, 0);
16717 misc_mask = flow_dv_matcher_enable(value.buf);
16718 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16719 ret = mlx5_flow_os_create_flow
16720 (mtrmng->def_matcher[domain]->matcher_object,
16721 (void *)&value, i, actions,
16722 &mtrmng->def_rule[domain]);
16724 DRV_LOG(ERR, "Failed to create meter "
16725 "default drop rule for drop table.");
16731 MLX5_ASSERT(mtrmng->max_mtr_bits);
16732 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16733 /* Create matchers for Drop. */
16734 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16735 (enum modify_reg)mtr_id_reg_c, 0,
16736 (mtr_id_mask << mtr_id_offset));
16737 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16738 matcher.crc = rte_raw_cksum
16739 ((const void *)matcher.mask.buf,
16740 matcher.mask.size);
16741 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16744 "Failed to register meter drop matcher.");
16747 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16748 container_of(entry, struct mlx5_flow_dv_matcher,
16752 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16753 /* Create drop rule, matching meter_id only. */
16754 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16755 (enum modify_reg)mtr_id_reg_c,
16756 (mtr_idx << mtr_id_offset), UINT32_MAX);
16758 cnt = flow_dv_counter_get_by_idx(dev,
16759 fm->drop_cnt, NULL);
16760 actions[i++] = cnt->action;
16761 actions[i++] = priv->sh->dr_drop_action;
16762 misc_mask = flow_dv_matcher_enable(value.buf);
16763 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16764 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16765 (void *)&value, i, actions,
16766 &fm->drop_rule[domain]);
16768 DRV_LOG(ERR, "Failed to create meter "
16769 "drop rule for drop table.");
16775 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16776 if (fm->drop_rule[i]) {
16777 claim_zero(mlx5_flow_os_destroy_flow
16778 (fm->drop_rule[i]));
16779 fm->drop_rule[i] = NULL;
16785 static struct mlx5_flow_meter_sub_policy *
16786 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16787 struct mlx5_flow_meter_policy *mtr_policy,
16788 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16789 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16792 struct mlx5_priv *priv = dev->data->dev_private;
16793 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16794 uint32_t sub_policy_idx = 0;
16795 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16797 struct mlx5_hrxq *hrxq;
16798 struct mlx5_flow_handle dh;
16799 struct mlx5_meter_policy_action_container *act_cnt;
16800 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16801 uint16_t sub_policy_num;
16803 rte_spinlock_lock(&mtr_policy->sl);
16804 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16807 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16808 if (!hrxq_idx[i]) {
16809 rte_spinlock_unlock(&mtr_policy->sl);
16813 sub_policy_num = (mtr_policy->sub_policy_num >>
16814 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16815 MLX5_MTR_SUB_POLICY_NUM_MASK;
16816 for (j = 0; j < sub_policy_num; j++) {
16817 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16820 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16823 if (i >= MLX5_MTR_RTE_COLORS) {
16825 * Found the sub policy table with
16826 * the same queue per color.
16828 rte_spinlock_unlock(&mtr_policy->sl);
16829 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16830 mlx5_hrxq_release(dev, hrxq_idx[i]);
16832 return mtr_policy->sub_policys[domain][j];
16835 /* Create sub policy. */
16836 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16837 /* Reuse the first pre-allocated sub_policy. */
16838 sub_policy = mtr_policy->sub_policys[domain][0];
16839 sub_policy_idx = sub_policy->idx;
16841 sub_policy = mlx5_ipool_zmalloc
16842 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16845 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16846 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16847 mlx5_hrxq_release(dev, hrxq_idx[i]);
16848 goto rss_sub_policy_error;
16850 sub_policy->idx = sub_policy_idx;
16851 sub_policy->main_policy = mtr_policy;
16853 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16856 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16857 if (mtr_policy->is_hierarchy) {
16858 act_cnt = &mtr_policy->act_cnt[i];
16859 act_cnt->next_sub_policy = next_sub_policy;
16860 mlx5_hrxq_release(dev, hrxq_idx[i]);
16863 * Overwrite the last action from
16864 * RSS action to Queue action.
16866 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16869 DRV_LOG(ERR, "Failed to get policy hrxq");
16870 goto rss_sub_policy_error;
16872 act_cnt = &mtr_policy->act_cnt[i];
16873 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16874 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16875 if (act_cnt->rix_mark)
16877 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16878 dh.rix_hrxq = hrxq_idx[i];
16879 flow_drv_rxq_flags_set(dev, &dh);
16883 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16884 sub_policy, domain)) {
16885 DRV_LOG(ERR, "Failed to create policy "
16886 "rules for ingress domain.");
16887 goto rss_sub_policy_error;
16889 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16890 i = (mtr_policy->sub_policy_num >>
16891 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16892 MLX5_MTR_SUB_POLICY_NUM_MASK;
16893 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16894 DRV_LOG(ERR, "No free sub-policy slot.");
16895 goto rss_sub_policy_error;
16897 mtr_policy->sub_policys[domain][i] = sub_policy;
16899 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16900 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16901 mtr_policy->sub_policy_num |=
16902 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16903 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16905 rte_spinlock_unlock(&mtr_policy->sl);
16908 rss_sub_policy_error:
16910 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16911 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16912 i = (mtr_policy->sub_policy_num >>
16913 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16914 MLX5_MTR_SUB_POLICY_NUM_MASK;
16915 mtr_policy->sub_policys[domain][i] = NULL;
16916 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16920 rte_spinlock_unlock(&mtr_policy->sl);
16925 * Find the policy table for prefix table with RSS.
16928 * Pointer to Ethernet device.
16929 * @param[in] mtr_policy
16930 * Pointer to meter policy table.
16931 * @param[in] rss_desc
16932 * Pointer to rss_desc
16934 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16936 static struct mlx5_flow_meter_sub_policy *
16937 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16938 struct mlx5_flow_meter_policy *mtr_policy,
16939 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16941 struct mlx5_priv *priv = dev->data->dev_private;
16942 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16943 struct mlx5_flow_meter_info *next_fm;
16944 struct mlx5_flow_meter_policy *next_policy;
16945 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16946 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16947 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16948 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16949 bool reuse_sub_policy;
16954 /* Iterate hierarchy to get all policies in this hierarchy. */
16955 policies[i++] = mtr_policy;
16956 if (!mtr_policy->is_hierarchy)
16958 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16959 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16962 next_fm = mlx5_flow_meter_find(priv,
16963 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16965 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
16969 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
16971 MLX5_ASSERT(next_policy);
16972 mtr_policy = next_policy;
16976 * From last policy to the first one in hierarchy,
16977 * create / get the sub policy for each of them.
16979 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
16983 &reuse_sub_policy);
16985 DRV_LOG(ERR, "Failed to get the sub policy.");
16988 if (!reuse_sub_policy)
16989 sub_policies[j++] = sub_policy;
16990 next_sub_policy = sub_policy;
16995 uint16_t sub_policy_num;
16997 sub_policy = sub_policies[--j];
16998 mtr_policy = sub_policy->main_policy;
16999 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17000 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17001 sub_policy_num = (mtr_policy->sub_policy_num >>
17002 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17003 MLX5_MTR_SUB_POLICY_NUM_MASK;
17004 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17007 mtr_policy->sub_policy_num &=
17008 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17009 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17010 mtr_policy->sub_policy_num |=
17011 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17012 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17013 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17021 * Create the sub policy tag rule for all meters in hierarchy.
17024 * Pointer to Ethernet device.
17026 * Meter information table.
17027 * @param[in] src_port
17028 * The src port this extra rule should use.
17030 * The src port match item.
17031 * @param[out] error
17032 * Perform verbose error reporting if not NULL.
17034 * 0 on success, a negative errno value otherwise and rte_errno is set.
17037 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17038 struct mlx5_flow_meter_info *fm,
17040 const struct rte_flow_item *item,
17041 struct rte_flow_error *error)
17043 struct mlx5_priv *priv = dev->data->dev_private;
17044 struct mlx5_flow_meter_policy *mtr_policy;
17045 struct mlx5_flow_meter_sub_policy *sub_policy;
17046 struct mlx5_flow_meter_info *next_fm = NULL;
17047 struct mlx5_flow_meter_policy *next_policy;
17048 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17049 struct mlx5_flow_tbl_data_entry *tbl_data;
17050 struct mlx5_sub_policy_color_rule *color_rule;
17051 struct mlx5_meter_policy_acts acts;
17052 uint32_t color_reg_c_idx;
17053 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17054 struct rte_flow_attr attr = {
17055 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17062 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17065 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17066 MLX5_ASSERT(mtr_policy);
17067 if (!mtr_policy->is_hierarchy)
17069 next_fm = mlx5_flow_meter_find(priv,
17070 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17072 return rte_flow_error_set(error, EINVAL,
17073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17074 "Failed to find next meter in hierarchy.");
17076 if (!next_fm->drop_cnt)
17078 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17079 sub_policy = mtr_policy->sub_policys[domain][0];
17080 for (i = 0; i < RTE_COLORS; i++) {
17081 bool rule_exist = false;
17082 struct mlx5_meter_policy_action_container *act_cnt;
17084 if (i >= RTE_COLOR_YELLOW)
17086 TAILQ_FOREACH(color_rule,
17087 &sub_policy->color_rules[i], next_port)
17088 if (color_rule->src_port == src_port) {
17094 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17095 sizeof(struct mlx5_sub_policy_color_rule),
17098 return rte_flow_error_set(error, ENOMEM,
17099 RTE_FLOW_ERROR_TYPE_ACTION,
17100 NULL, "No memory to create tag color rule.");
17101 color_rule->src_port = src_port;
17103 next_policy = mlx5_flow_meter_policy_find(dev,
17104 next_fm->policy_id, NULL);
17105 MLX5_ASSERT(next_policy);
17106 next_sub_policy = next_policy->sub_policys[domain][0];
17107 tbl_data = container_of(next_sub_policy->tbl_rsc,
17108 struct mlx5_flow_tbl_data_entry, tbl);
17109 act_cnt = &mtr_policy->act_cnt[i];
17111 acts.dv_actions[0] = next_fm->meter_action;
17112 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17114 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17115 acts.dv_actions[1] = next_fm->meter_action;
17117 acts.dv_actions[2] = tbl_data->jump.action;
17118 acts.actions_n = 3;
17119 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17123 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17124 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17126 &color_rule->matcher, error)) {
17127 rte_flow_error_set(error, errno,
17128 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17129 "Failed to create hierarchy meter matcher.");
17132 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17134 color_rule->matcher->matcher_object,
17135 acts.actions_n, acts.dv_actions,
17137 &color_rule->rule, &attr)) {
17138 rte_flow_error_set(error, errno,
17139 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17140 "Failed to create hierarchy meter rule.");
17143 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17144 color_rule, next_port);
17148 * Recursive call to iterate all meters in hierarchy and
17149 * create needed rules.
17151 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17152 src_port, item, error);
17155 if (color_rule->rule)
17156 mlx5_flow_os_destroy_flow(color_rule->rule);
17157 if (color_rule->matcher) {
17158 struct mlx5_flow_tbl_data_entry *tbl =
17159 container_of(color_rule->matcher->tbl,
17160 typeof(*tbl), tbl);
17161 mlx5_list_unregister(tbl->matchers,
17162 &color_rule->matcher->entry);
17164 mlx5_free(color_rule);
17167 mlx5_flow_meter_detach(priv, next_fm);
17172 * Destroy the sub policy table with RX queue.
17175 * Pointer to Ethernet device.
17176 * @param[in] mtr_policy
17177 * Pointer to meter policy table.
17180 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17181 struct mlx5_flow_meter_policy *mtr_policy)
17183 struct mlx5_priv *priv = dev->data->dev_private;
17184 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17185 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17187 uint16_t sub_policy_num, new_policy_num;
17189 rte_spinlock_lock(&mtr_policy->sl);
17190 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17191 switch (mtr_policy->act_cnt[i].fate_action) {
17192 case MLX5_FLOW_FATE_SHARED_RSS:
17193 sub_policy_num = (mtr_policy->sub_policy_num >>
17194 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17195 MLX5_MTR_SUB_POLICY_NUM_MASK;
17196 new_policy_num = sub_policy_num;
17197 for (j = 0; j < sub_policy_num; j++) {
17199 mtr_policy->sub_policys[domain][j];
17201 __flow_dv_destroy_sub_policy_rules(dev,
17204 mtr_policy->sub_policys[domain][0]) {
17205 mtr_policy->sub_policys[domain][j] =
17208 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17214 if (new_policy_num != sub_policy_num) {
17215 mtr_policy->sub_policy_num &=
17216 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17217 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17218 mtr_policy->sub_policy_num |=
17220 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17221 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17224 case MLX5_FLOW_FATE_QUEUE:
17225 sub_policy = mtr_policy->sub_policys[domain][0];
17226 __flow_dv_destroy_sub_policy_rules(dev,
17230 /*Other actions without queue and do nothing*/
17234 rte_spinlock_unlock(&mtr_policy->sl);
17237 * Check whether the DR drop action is supported on the root table or not.
17239 * Create a simple flow with DR drop action on root table to validate
17240 * if DR drop action on root table is supported or not.
17243 * Pointer to rte_eth_dev structure.
17246 * 0 on success, a negative errno value otherwise and rte_errno is set.
17249 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17251 struct mlx5_priv *priv = dev->data->dev_private;
17252 struct mlx5_dev_ctx_shared *sh = priv->sh;
17253 struct mlx5_flow_dv_match_params mask = {
17254 .size = sizeof(mask.buf),
17256 struct mlx5_flow_dv_match_params value = {
17257 .size = sizeof(value.buf),
17259 struct mlx5dv_flow_matcher_attr dv_attr = {
17260 .type = IBV_FLOW_ATTR_NORMAL,
17262 .match_criteria_enable = 0,
17263 .match_mask = (void *)&mask,
17265 struct mlx5_flow_tbl_resource *tbl = NULL;
17266 void *matcher = NULL;
17270 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17274 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17275 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17276 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17277 tbl->obj, &matcher);
17280 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17281 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17282 &sh->dr_drop_action, &flow);
17285 * If DR drop action is not supported on root table, flow create will
17286 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17290 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17291 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17293 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17296 claim_zero(mlx5_flow_os_destroy_flow(flow));
17299 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17301 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17306 * Validate the batch counter support in root table.
17308 * Create a simple flow with invalid counter and drop action on root table to
17309 * validate if batch counter with offset on root table is supported or not.
17312 * Pointer to rte_eth_dev structure.
17315 * 0 on success, a negative errno value otherwise and rte_errno is set.
17318 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17320 struct mlx5_priv *priv = dev->data->dev_private;
17321 struct mlx5_dev_ctx_shared *sh = priv->sh;
17322 struct mlx5_flow_dv_match_params mask = {
17323 .size = sizeof(mask.buf),
17325 struct mlx5_flow_dv_match_params value = {
17326 .size = sizeof(value.buf),
17328 struct mlx5dv_flow_matcher_attr dv_attr = {
17329 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17331 .match_criteria_enable = 0,
17332 .match_mask = (void *)&mask,
17334 void *actions[2] = { 0 };
17335 struct mlx5_flow_tbl_resource *tbl = NULL;
17336 struct mlx5_devx_obj *dcs = NULL;
17337 void *matcher = NULL;
17341 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17345 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17348 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17352 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17353 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17354 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17355 tbl->obj, &matcher);
17358 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17359 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17363 * If batch counter with offset is not supported, the driver will not
17364 * validate the invalid offset value, flow create should success.
17365 * In this case, it means batch counter is not supported in root table.
17367 * Otherwise, if flow create is failed, counter offset is supported.
17370 DRV_LOG(INFO, "Batch counter is not supported in root "
17371 "table. Switch to fallback mode.");
17372 rte_errno = ENOTSUP;
17374 claim_zero(mlx5_flow_os_destroy_flow(flow));
17376 /* Check matcher to make sure validate fail at flow create. */
17377 if (!matcher || (matcher && errno != EINVAL))
17378 DRV_LOG(ERR, "Unexpected error in counter offset "
17379 "support detection");
17383 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17385 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17387 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17389 claim_zero(mlx5_devx_cmd_destroy(dcs));
17394 * Query a devx counter.
17397 * Pointer to the Ethernet device structure.
17399 * Index to the flow counter.
17401 * Set to clear the counter statistics.
17403 * The statistics value of packets.
17404 * @param[out] bytes
17405 * The statistics value of bytes.
17408 * 0 on success, otherwise return -1.
17411 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17412 uint64_t *pkts, uint64_t *bytes)
17414 struct mlx5_priv *priv = dev->data->dev_private;
17415 struct mlx5_flow_counter *cnt;
17416 uint64_t inn_pkts, inn_bytes;
17419 if (!priv->sh->devx)
17422 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17425 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17426 *pkts = inn_pkts - cnt->hits;
17427 *bytes = inn_bytes - cnt->bytes;
17429 cnt->hits = inn_pkts;
17430 cnt->bytes = inn_bytes;
17436 * Get aged-out flows.
17439 * Pointer to the Ethernet device structure.
17440 * @param[in] context
17441 * The address of an array of pointers to the aged-out flows contexts.
17442 * @param[in] nb_contexts
17443 * The length of context array pointers.
17444 * @param[out] error
17445 * Perform verbose error reporting if not NULL. Initialized in case of
17449 * how many contexts get in success, otherwise negative errno value.
17450 * if nb_contexts is 0, return the amount of all aged contexts.
17451 * if nb_contexts is not 0 , return the amount of aged flows reported
17452 * in the context array.
17453 * @note: only stub for now
17456 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17458 uint32_t nb_contexts,
17459 struct rte_flow_error *error)
17461 struct mlx5_priv *priv = dev->data->dev_private;
17462 struct mlx5_age_info *age_info;
17463 struct mlx5_age_param *age_param;
17464 struct mlx5_flow_counter *counter;
17465 struct mlx5_aso_age_action *act;
17468 if (nb_contexts && !context)
17469 return rte_flow_error_set(error, EINVAL,
17470 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17471 NULL, "empty context");
17472 age_info = GET_PORT_AGE_INFO(priv);
17473 rte_spinlock_lock(&age_info->aged_sl);
17474 LIST_FOREACH(act, &age_info->aged_aso, next) {
17477 context[nb_flows - 1] =
17478 act->age_params.context;
17479 if (!(--nb_contexts))
17483 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17486 age_param = MLX5_CNT_TO_AGE(counter);
17487 context[nb_flows - 1] = age_param->context;
17488 if (!(--nb_contexts))
17492 rte_spinlock_unlock(&age_info->aged_sl);
17493 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17498 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17501 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17503 return flow_dv_counter_alloc(dev, 0);
17507 * Validate indirect action.
17508 * Dispatcher for action type specific validation.
17511 * Pointer to the Ethernet device structure.
17513 * Indirect action configuration.
17514 * @param[in] action
17515 * The indirect action object to validate.
17516 * @param[out] error
17517 * Perform verbose error reporting if not NULL. Initialized in case of
17521 * 0 on success, otherwise negative errno value.
17524 flow_dv_action_validate(struct rte_eth_dev *dev,
17525 const struct rte_flow_indir_action_conf *conf,
17526 const struct rte_flow_action *action,
17527 struct rte_flow_error *err)
17529 struct mlx5_priv *priv = dev->data->dev_private;
17531 RTE_SET_USED(conf);
17532 switch (action->type) {
17533 case RTE_FLOW_ACTION_TYPE_RSS:
17535 * priv->obj_ops is set according to driver capabilities.
17536 * When DevX capabilities are
17537 * sufficient, it is set to devx_obj_ops.
17538 * Otherwise, it is set to ibv_obj_ops.
17539 * ibv_obj_ops doesn't support ind_table_modify operation.
17540 * In this case the indirect RSS action can't be used.
17542 if (priv->obj_ops.ind_table_modify == NULL)
17543 return rte_flow_error_set
17545 RTE_FLOW_ERROR_TYPE_ACTION,
17547 "Indirect RSS action not supported");
17548 return mlx5_validate_action_rss(dev, action, err);
17549 case RTE_FLOW_ACTION_TYPE_AGE:
17550 if (!priv->sh->aso_age_mng)
17551 return rte_flow_error_set(err, ENOTSUP,
17552 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17554 "Indirect age action not supported");
17555 return flow_dv_validate_action_age(0, action, dev, err);
17556 case RTE_FLOW_ACTION_TYPE_COUNT:
17557 return flow_dv_validate_action_count(dev, true, 0, err);
17558 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17559 if (!priv->sh->ct_aso_en)
17560 return rte_flow_error_set(err, ENOTSUP,
17561 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17562 "ASO CT is not supported");
17563 return mlx5_validate_action_ct(dev, action->conf, err);
17565 return rte_flow_error_set(err, ENOTSUP,
17566 RTE_FLOW_ERROR_TYPE_ACTION,
17568 "action type not supported");
17573 * Check if the RSS configurations for colors of a meter policy match
17574 * each other, except the queues.
17577 * Pointer to the first RSS flow action.
17579 * Pointer to the second RSS flow action.
17582 * 0 on match, 1 on conflict.
17585 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17586 const struct rte_flow_action_rss *r2)
17588 if (r1 == NULL || r2 == NULL)
17590 if (!(r1->level <= 1 && r2->level <= 1) &&
17591 !(r1->level > 1 && r2->level > 1))
17593 if (r1->types != r2->types &&
17594 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17595 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17597 if (r1->key || r2->key) {
17598 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17599 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17601 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17608 * Validate the meter hierarchy chain for meter policy.
17611 * Pointer to the Ethernet device structure.
17612 * @param[in] meter_id
17614 * @param[in] action_flags
17615 * Holds the actions detected until now.
17616 * @param[out] is_rss
17618 * @param[out] hierarchy_domain
17619 * The domain bitmap for hierarchy policy.
17620 * @param[out] error
17621 * Perform verbose error reporting if not NULL. Initialized in case of
17625 * 0 on success, otherwise negative errno value with error set.
17628 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17630 uint64_t action_flags,
17632 uint8_t *hierarchy_domain,
17633 struct rte_mtr_error *error)
17635 struct mlx5_priv *priv = dev->data->dev_private;
17636 struct mlx5_flow_meter_info *fm;
17637 struct mlx5_flow_meter_policy *policy;
17640 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17641 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17642 return -rte_mtr_error_set(error, EINVAL,
17643 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17645 "Multiple fate actions not supported.");
17646 *hierarchy_domain = 0;
17648 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17650 return -rte_mtr_error_set(error, EINVAL,
17651 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17652 "Meter not found in meter hierarchy.");
17653 if (fm->def_policy)
17654 return -rte_mtr_error_set(error, EINVAL,
17655 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17656 "Non termination meter not supported in hierarchy.");
17657 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17658 MLX5_ASSERT(policy);
17660 * Only inherit the supported domains of the first meter in
17662 * One meter supports at least one domain.
17664 if (!*hierarchy_domain) {
17665 if (policy->transfer)
17666 *hierarchy_domain |=
17667 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17668 if (policy->ingress)
17669 *hierarchy_domain |=
17670 MLX5_MTR_DOMAIN_INGRESS_BIT;
17671 if (policy->egress)
17672 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17674 if (!policy->is_hierarchy) {
17675 *is_rss = policy->is_rss;
17678 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17679 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17680 return -rte_mtr_error_set(error, EINVAL,
17681 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17682 "Exceed max hierarchy meter number.");
17688 * Validate meter policy actions.
17689 * Dispatcher for action type specific validation.
17692 * Pointer to the Ethernet device structure.
17693 * @param[in] action
17694 * The meter policy action object to validate.
17696 * Attributes of flow to determine steering domain.
17697 * @param[out] error
17698 * Perform verbose error reporting if not NULL. Initialized in case of
17702 * 0 on success, otherwise negative errno value.
17705 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17706 const struct rte_flow_action *actions[RTE_COLORS],
17707 struct rte_flow_attr *attr,
17709 uint8_t *domain_bitmap,
17710 uint8_t *policy_mode,
17711 struct rte_mtr_error *error)
17713 struct mlx5_priv *priv = dev->data->dev_private;
17714 struct mlx5_dev_config *dev_conf = &priv->config;
17715 const struct rte_flow_action *act;
17716 uint64_t action_flags[RTE_COLORS] = {0};
17719 struct rte_flow_error flow_err;
17720 uint8_t domain_color[RTE_COLORS] = {0};
17721 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17722 uint8_t hierarchy_domain = 0;
17723 const struct rte_flow_action_meter *mtr;
17724 bool def_green = false;
17725 bool def_yellow = false;
17726 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17728 if (!priv->config.dv_esw_en)
17729 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17730 *domain_bitmap = def_domain;
17731 /* Red color could only support DROP action. */
17732 if (!actions[RTE_COLOR_RED] ||
17733 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17734 return -rte_mtr_error_set(error, ENOTSUP,
17735 RTE_MTR_ERROR_TYPE_METER_POLICY,
17736 NULL, "Red color only supports drop action.");
17738 * Check default policy actions:
17739 * Green / Yellow: no action, Red: drop action
17740 * Either G or Y will trigger default policy actions to be created.
17742 if (!actions[RTE_COLOR_GREEN] ||
17743 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17745 if (!actions[RTE_COLOR_YELLOW] ||
17746 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17748 if (def_green && def_yellow) {
17749 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17751 } else if (!def_green && def_yellow) {
17752 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17753 } else if (def_green && !def_yellow) {
17754 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17756 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17758 /* Set to empty string in case of NULL pointer access by user. */
17759 flow_err.message = "";
17760 for (i = 0; i < RTE_COLORS; i++) {
17762 for (action_flags[i] = 0, actions_n = 0;
17763 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17765 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17766 return -rte_mtr_error_set(error, ENOTSUP,
17767 RTE_MTR_ERROR_TYPE_METER_POLICY,
17768 NULL, "too many actions");
17769 switch (act->type) {
17770 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17771 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17772 if (!priv->config.dv_esw_en)
17773 return -rte_mtr_error_set(error,
17775 RTE_MTR_ERROR_TYPE_METER_POLICY,
17776 NULL, "PORT action validate check"
17777 " fail for ESW disable");
17778 ret = flow_dv_validate_action_port_id(dev,
17780 act, attr, &flow_err);
17782 return -rte_mtr_error_set(error,
17784 RTE_MTR_ERROR_TYPE_METER_POLICY,
17785 NULL, flow_err.message ?
17787 "PORT action validate check fail");
17789 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17791 case RTE_FLOW_ACTION_TYPE_MARK:
17792 ret = flow_dv_validate_action_mark(dev, act,
17796 return -rte_mtr_error_set(error,
17798 RTE_MTR_ERROR_TYPE_METER_POLICY,
17799 NULL, flow_err.message ?
17801 "Mark action validate check fail");
17802 if (dev_conf->dv_xmeta_en !=
17803 MLX5_XMETA_MODE_LEGACY)
17804 return -rte_mtr_error_set(error,
17806 RTE_MTR_ERROR_TYPE_METER_POLICY,
17807 NULL, "Extend MARK action is "
17808 "not supported. Please try use "
17809 "default policy for meter.");
17810 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17813 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17814 ret = flow_dv_validate_action_set_tag(dev,
17815 act, action_flags[i],
17818 return -rte_mtr_error_set(error,
17820 RTE_MTR_ERROR_TYPE_METER_POLICY,
17821 NULL, flow_err.message ?
17823 "Set tag action validate check fail");
17824 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17827 case RTE_FLOW_ACTION_TYPE_DROP:
17828 ret = mlx5_flow_validate_action_drop
17829 (action_flags[i], attr, &flow_err);
17831 return -rte_mtr_error_set(error,
17833 RTE_MTR_ERROR_TYPE_METER_POLICY,
17834 NULL, flow_err.message ?
17836 "Drop action validate check fail");
17837 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17840 case RTE_FLOW_ACTION_TYPE_QUEUE:
17842 * Check whether extensive
17843 * metadata feature is engaged.
17845 if (dev_conf->dv_flow_en &&
17846 (dev_conf->dv_xmeta_en !=
17847 MLX5_XMETA_MODE_LEGACY) &&
17848 mlx5_flow_ext_mreg_supported(dev))
17849 return -rte_mtr_error_set(error,
17851 RTE_MTR_ERROR_TYPE_METER_POLICY,
17852 NULL, "Queue action with meta "
17853 "is not supported. Please try use "
17854 "default policy for meter.");
17855 ret = mlx5_flow_validate_action_queue(act,
17856 action_flags[i], dev,
17859 return -rte_mtr_error_set(error,
17861 RTE_MTR_ERROR_TYPE_METER_POLICY,
17862 NULL, flow_err.message ?
17864 "Queue action validate check fail");
17865 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17868 case RTE_FLOW_ACTION_TYPE_RSS:
17869 if (dev_conf->dv_flow_en &&
17870 (dev_conf->dv_xmeta_en !=
17871 MLX5_XMETA_MODE_LEGACY) &&
17872 mlx5_flow_ext_mreg_supported(dev))
17873 return -rte_mtr_error_set(error,
17875 RTE_MTR_ERROR_TYPE_METER_POLICY,
17876 NULL, "RSS action with meta "
17877 "is not supported. Please try use "
17878 "default policy for meter.");
17879 ret = mlx5_validate_action_rss(dev, act,
17882 return -rte_mtr_error_set(error,
17884 RTE_MTR_ERROR_TYPE_METER_POLICY,
17885 NULL, flow_err.message ?
17887 "RSS action validate check fail");
17888 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17890 /* Either G or Y will set the RSS. */
17891 rss_color[i] = act->conf;
17893 case RTE_FLOW_ACTION_TYPE_JUMP:
17894 ret = flow_dv_validate_action_jump(dev,
17895 NULL, act, action_flags[i],
17896 attr, true, &flow_err);
17898 return -rte_mtr_error_set(error,
17900 RTE_MTR_ERROR_TYPE_METER_POLICY,
17901 NULL, flow_err.message ?
17903 "Jump action validate check fail");
17905 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17908 * Only the last meter in the hierarchy will support
17909 * the YELLOW color steering. Then in the meter policy
17910 * actions list, there should be no other meter inside.
17912 case RTE_FLOW_ACTION_TYPE_METER:
17913 if (i != RTE_COLOR_GREEN)
17914 return -rte_mtr_error_set(error,
17916 RTE_MTR_ERROR_TYPE_METER_POLICY,
17918 "Meter hierarchy only supports GREEN color.");
17919 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17920 return -rte_mtr_error_set(error,
17922 RTE_MTR_ERROR_TYPE_METER_POLICY,
17924 "No yellow policy should be provided in meter hierarchy.");
17926 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17936 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17939 return -rte_mtr_error_set(error, ENOTSUP,
17940 RTE_MTR_ERROR_TYPE_METER_POLICY,
17942 "Doesn't support optional action");
17945 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
17946 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17947 } else if ((action_flags[i] &
17948 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17949 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
17951 * Only support MLX5_XMETA_MODE_LEGACY
17952 * so MARK action is only in ingress domain.
17954 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17956 domain_color[i] = def_domain;
17957 if (action_flags[i] &&
17958 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17960 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17962 if (action_flags[i] &
17963 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
17964 domain_color[i] &= hierarchy_domain;
17966 * Non-termination actions only support NIC Tx domain.
17967 * The adjustion should be skipped when there is no
17968 * action or only END is provided. The default domains
17969 * bit-mask is set to find the MIN intersection.
17970 * The action flags checking should also be skipped.
17972 if ((def_green && i == RTE_COLOR_GREEN) ||
17973 (def_yellow && i == RTE_COLOR_YELLOW))
17976 * Validate the drop action mutual exclusion
17977 * with other actions. Drop action is mutually-exclusive
17978 * with any other action, except for Count action.
17980 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
17981 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
17982 return -rte_mtr_error_set(error, ENOTSUP,
17983 RTE_MTR_ERROR_TYPE_METER_POLICY,
17984 NULL, "Drop action is mutually-exclusive "
17985 "with any other action");
17987 /* Eswitch has few restrictions on using items and actions */
17988 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
17989 if (!mlx5_flow_ext_mreg_supported(dev) &&
17990 action_flags[i] & MLX5_FLOW_ACTION_MARK)
17991 return -rte_mtr_error_set(error, ENOTSUP,
17992 RTE_MTR_ERROR_TYPE_METER_POLICY,
17993 NULL, "unsupported action MARK");
17994 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
17995 return -rte_mtr_error_set(error, ENOTSUP,
17996 RTE_MTR_ERROR_TYPE_METER_POLICY,
17997 NULL, "unsupported action QUEUE");
17998 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
17999 return -rte_mtr_error_set(error, ENOTSUP,
18000 RTE_MTR_ERROR_TYPE_METER_POLICY,
18001 NULL, "unsupported action RSS");
18002 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18003 return -rte_mtr_error_set(error, ENOTSUP,
18004 RTE_MTR_ERROR_TYPE_METER_POLICY,
18005 NULL, "no fate action is found");
18007 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18008 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18009 if ((domain_color[i] &
18010 MLX5_MTR_DOMAIN_EGRESS_BIT))
18012 MLX5_MTR_DOMAIN_EGRESS_BIT;
18014 return -rte_mtr_error_set(error,
18016 RTE_MTR_ERROR_TYPE_METER_POLICY,
18018 "no fate action is found");
18022 /* If both colors have RSS, the attributes should be the same. */
18023 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18024 rss_color[RTE_COLOR_YELLOW]))
18025 return -rte_mtr_error_set(error, EINVAL,
18026 RTE_MTR_ERROR_TYPE_METER_POLICY,
18027 NULL, "policy RSS attr conflict");
18028 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18030 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18031 if (!def_green && !def_yellow &&
18032 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18033 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18034 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18035 return -rte_mtr_error_set(error, EINVAL,
18036 RTE_MTR_ERROR_TYPE_METER_POLICY,
18037 NULL, "policy domains conflict");
18039 * At least one color policy is listed in the actions, the domains
18040 * to be supported should be the intersection.
18042 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18043 domain_color[RTE_COLOR_YELLOW];
18048 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18050 struct mlx5_priv *priv = dev->data->dev_private;
18053 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18054 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18059 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18060 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18064 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18065 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18073 * Discover the number of available flow priorities
18074 * by trying to create a flow with the highest priority value
18075 * for each possible number.
18080 * List of possible number of available priorities.
18081 * @param[in] vprio_n
18082 * Size of @p vprio array.
18084 * On success, number of available flow priorities.
18085 * On failure, a negative errno-style code and rte_errno is set.
18088 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18089 const uint16_t *vprio, int vprio_n)
18091 struct mlx5_priv *priv = dev->data->dev_private;
18092 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18093 struct rte_flow_item_eth eth;
18094 struct rte_flow_item item = {
18095 .type = RTE_FLOW_ITEM_TYPE_ETH,
18099 struct mlx5_flow_dv_matcher matcher = {
18101 .size = sizeof(matcher.mask.buf),
18104 union mlx5_flow_tbl_key tbl_key;
18105 struct mlx5_flow flow;
18107 struct rte_flow_error error;
18109 int i, err, ret = -ENOTSUP;
18112 * Prepare a flow with a catch-all pattern and a drop action.
18113 * Use drop queue, because shared drop action may be unavailable.
18115 action = priv->drop_queue.hrxq->action;
18116 if (action == NULL) {
18117 DRV_LOG(ERR, "Priority discovery requires a drop action");
18118 rte_errno = ENOTSUP;
18121 memset(&flow, 0, sizeof(flow));
18122 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18123 if (flow.handle == NULL) {
18124 DRV_LOG(ERR, "Cannot create flow handle");
18125 rte_errno = ENOMEM;
18128 flow.ingress = true;
18129 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18130 flow.dv.actions[0] = action;
18131 flow.dv.actions_n = 1;
18132 memset(ð, 0, sizeof(eth));
18133 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18134 &item, /* inner */ false, /* group */ 0);
18135 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18136 for (i = 0; i < vprio_n; i++) {
18137 /* Configure the next proposed maximum priority. */
18138 matcher.priority = vprio[i] - 1;
18139 memset(&tbl_key, 0, sizeof(tbl_key));
18140 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18145 /* This action is pure SW and must always succeed. */
18146 DRV_LOG(ERR, "Cannot register matcher");
18150 /* Try to apply the flow to HW. */
18151 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18152 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18153 err = mlx5_flow_os_create_flow
18154 (flow.handle->dvh.matcher->matcher_object,
18155 (void *)&flow.dv.value, flow.dv.actions_n,
18156 flow.dv.actions, &flow.handle->drv_flow);
18158 claim_zero(mlx5_flow_os_destroy_flow
18159 (flow.handle->drv_flow));
18160 flow.handle->drv_flow = NULL;
18162 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18167 mlx5_ipool_free(pool, flow.handle_idx);
18168 /* Set rte_errno if no expected priority value matched. */
18174 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18175 .validate = flow_dv_validate,
18176 .prepare = flow_dv_prepare,
18177 .translate = flow_dv_translate,
18178 .apply = flow_dv_apply,
18179 .remove = flow_dv_remove,
18180 .destroy = flow_dv_destroy,
18181 .query = flow_dv_query,
18182 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18183 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18184 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18185 .create_meter = flow_dv_mtr_alloc,
18186 .free_meter = flow_dv_aso_mtr_release_to_pool,
18187 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18188 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18189 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18190 .create_policy_rules = flow_dv_create_policy_rules,
18191 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18192 .create_def_policy = flow_dv_create_def_policy,
18193 .destroy_def_policy = flow_dv_destroy_def_policy,
18194 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18195 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18196 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18197 .counter_alloc = flow_dv_counter_allocate,
18198 .counter_free = flow_dv_counter_free,
18199 .counter_query = flow_dv_counter_query,
18200 .get_aged_flows = flow_dv_get_aged_flows,
18201 .action_validate = flow_dv_action_validate,
18202 .action_create = flow_dv_action_create,
18203 .action_destroy = flow_dv_action_destroy,
18204 .action_update = flow_dv_action_update,
18205 .action_query = flow_dv_action_query,
18206 .sync_domain = flow_dv_sync_domain,
18207 .discover_priorities = flow_dv_discover_priorities,
18208 .item_create = flow_dv_item_create,
18209 .item_release = flow_dv_item_release,
18212 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */