1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 static inline uint16_t
97 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
99 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
100 return RTE_ETHER_TYPE_TEB;
101 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 return RTE_ETHER_TYPE_IPV4;
103 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 return RTE_ETHER_TYPE_IPV6;
105 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
106 return RTE_ETHER_TYPE_MPLS;
111 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
113 struct mlx5_priv *priv = dev->data->dev_private;
115 if (priv->pci_dev == NULL)
117 switch (priv->pci_dev->id.device_id) {
118 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
119 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
120 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
121 return (int16_t)0xfffe;
128 * Initialize flow attributes structure according to flow items' types.
130 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
131 * mode. For tunnel mode, the items to be modified are the outermost ones.
134 * Pointer to item specification.
136 * Pointer to flow attributes structure.
137 * @param[in] dev_flow
138 * Pointer to the sub flow.
139 * @param[in] tunnel_decap
140 * Whether action is after tunnel decapsulation.
143 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
144 struct mlx5_flow *dev_flow, bool tunnel_decap)
146 uint64_t layers = dev_flow->handle->layers;
149 * If layers is already initialized, it means this dev_flow is the
150 * suffix flow, the layers flags is set by the prefix flow. Need to
151 * use the layer flags from prefix flow as the suffix flow may not
152 * have the user defined items as the flow is split.
155 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
157 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
159 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
161 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
166 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
167 uint8_t next_protocol = 0xff;
168 switch (item->type) {
169 case RTE_FLOW_ITEM_TYPE_GRE:
170 case RTE_FLOW_ITEM_TYPE_NVGRE:
171 case RTE_FLOW_ITEM_TYPE_VXLAN:
172 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
173 case RTE_FLOW_ITEM_TYPE_GENEVE:
174 case RTE_FLOW_ITEM_TYPE_MPLS:
178 case RTE_FLOW_ITEM_TYPE_IPV4:
181 if (item->mask != NULL &&
182 ((const struct rte_flow_item_ipv4 *)
183 item->mask)->hdr.next_proto_id)
185 ((const struct rte_flow_item_ipv4 *)
186 (item->spec))->hdr.next_proto_id &
187 ((const struct rte_flow_item_ipv4 *)
188 (item->mask))->hdr.next_proto_id;
189 if ((next_protocol == IPPROTO_IPIP ||
190 next_protocol == IPPROTO_IPV6) && tunnel_decap)
193 case RTE_FLOW_ITEM_TYPE_IPV6:
196 if (item->mask != NULL &&
197 ((const struct rte_flow_item_ipv6 *)
198 item->mask)->hdr.proto)
200 ((const struct rte_flow_item_ipv6 *)
201 (item->spec))->hdr.proto &
202 ((const struct rte_flow_item_ipv6 *)
203 (item->mask))->hdr.proto;
204 if ((next_protocol == IPPROTO_IPIP ||
205 next_protocol == IPPROTO_IPV6) && tunnel_decap)
208 case RTE_FLOW_ITEM_TYPE_UDP:
212 case RTE_FLOW_ITEM_TYPE_TCP:
224 * Convert rte_mtr_color to mlx5 color.
233 rte_col_2_mlx5_col(enum rte_color rcol)
236 case RTE_COLOR_GREEN:
237 return MLX5_FLOW_COLOR_GREEN;
238 case RTE_COLOR_YELLOW:
239 return MLX5_FLOW_COLOR_YELLOW;
241 return MLX5_FLOW_COLOR_RED;
245 return MLX5_FLOW_COLOR_UNDEFINED;
248 struct field_modify_info {
249 uint32_t size; /* Size of field in protocol header, in bytes. */
250 uint32_t offset; /* Offset of field in protocol header, in bytes. */
251 enum mlx5_modification_field id;
254 struct field_modify_info modify_eth[] = {
255 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
256 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
257 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
258 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
262 struct field_modify_info modify_vlan_out_first_vid[] = {
263 /* Size in bits !!! */
264 {12, 0, MLX5_MODI_OUT_FIRST_VID},
268 struct field_modify_info modify_ipv4[] = {
269 {1, 1, MLX5_MODI_OUT_IP_DSCP},
270 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
271 {4, 12, MLX5_MODI_OUT_SIPV4},
272 {4, 16, MLX5_MODI_OUT_DIPV4},
276 struct field_modify_info modify_ipv6[] = {
277 {1, 0, MLX5_MODI_OUT_IP_DSCP},
278 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
279 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
280 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
281 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
282 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
283 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
284 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
285 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
286 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
290 struct field_modify_info modify_udp[] = {
291 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
292 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
296 struct field_modify_info modify_tcp[] = {
297 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
298 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
299 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
300 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
305 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
306 uint8_t next_protocol, uint64_t *item_flags,
309 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
310 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
311 if (next_protocol == IPPROTO_IPIP) {
312 *item_flags |= MLX5_FLOW_LAYER_IPIP;
315 if (next_protocol == IPPROTO_IPV6) {
316 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
321 static inline struct mlx5_hlist *
322 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
323 const char *name, uint32_t size, bool direct_key,
324 bool lcores_share, void *ctx,
325 mlx5_list_create_cb cb_create,
326 mlx5_list_match_cb cb_match,
327 mlx5_list_remove_cb cb_remove,
328 mlx5_list_clone_cb cb_clone,
329 mlx5_list_clone_free_cb cb_clone_free)
331 struct mlx5_hlist *hl;
332 struct mlx5_hlist *expected = NULL;
333 char s[MLX5_NAME_SIZE];
335 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
338 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
339 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
340 ctx, cb_create, cb_match, cb_remove, cb_clone,
343 DRV_LOG(ERR, "%s hash creation failed", name);
347 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
350 mlx5_hlist_destroy(hl);
351 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
356 /* Update VLAN's VID/PCP based on input rte_flow_action.
359 * Pointer to struct rte_flow_action.
361 * Pointer to struct rte_vlan_hdr.
364 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
365 struct rte_vlan_hdr *vlan)
368 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
370 ((const struct rte_flow_action_of_set_vlan_pcp *)
371 action->conf)->vlan_pcp;
372 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
373 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
374 vlan->vlan_tci |= vlan_tci;
375 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
376 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
377 vlan->vlan_tci |= rte_be_to_cpu_16
378 (((const struct rte_flow_action_of_set_vlan_vid *)
379 action->conf)->vlan_vid);
384 * Fetch 1, 2, 3 or 4 byte field from the byte array
385 * and return as unsigned integer in host-endian format.
388 * Pointer to data array.
390 * Size of field to extract.
393 * converted field in host endian format.
395 static inline uint32_t
396 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
405 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
408 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
409 ret = (ret << 8) | *(data + sizeof(uint16_t));
412 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
423 * Convert modify-header action to DV specification.
425 * Data length of each action is determined by provided field description
426 * and the item mask. Data bit offset and width of each action is determined
427 * by provided item mask.
430 * Pointer to item specification.
432 * Pointer to field modification information.
433 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
434 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
435 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
437 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
438 * Negative offset value sets the same offset as source offset.
439 * size field is ignored, value is taken from source field.
440 * @param[in,out] resource
441 * Pointer to the modify-header resource.
443 * Type of modification.
445 * Pointer to the error structure.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 flow_dv_convert_modify_action(struct rte_flow_item *item,
452 struct field_modify_info *field,
453 struct field_modify_info *dcopy,
454 struct mlx5_flow_dv_modify_hdr_resource *resource,
455 uint32_t type, struct rte_flow_error *error)
457 uint32_t i = resource->actions_num;
458 struct mlx5_modification_cmd *actions = resource->actions;
459 uint32_t carry_b = 0;
462 * The item and mask are provided in big-endian format.
463 * The fields should be presented as in big-endian format either.
464 * Mask must be always present, it defines the actual field width.
466 MLX5_ASSERT(item->mask);
467 MLX5_ASSERT(field->size);
473 bool next_field = true;
474 bool next_dcopy = true;
476 if (i >= MLX5_MAX_MODIFY_NUM)
477 return rte_flow_error_set(error, EINVAL,
478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
479 "too many items to modify");
480 /* Fetch variable byte size mask from the array. */
481 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
482 field->offset, field->size);
487 /* Deduce actual data width in bits from mask value. */
488 off_b = rte_bsf32(mask) + carry_b;
489 size_b = sizeof(uint32_t) * CHAR_BIT -
490 off_b - __builtin_clz(mask);
492 actions[i] = (struct mlx5_modification_cmd) {
496 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
499 if (type == MLX5_MODIFICATION_TYPE_COPY) {
501 actions[i].dst_field = dcopy->id;
502 actions[i].dst_offset =
503 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
504 /* Convert entire record to big-endian format. */
505 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
507 * Destination field overflow. Copy leftovers of
508 * a source field to the next destination field.
511 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
514 dcopy->size * CHAR_BIT - dcopy->offset;
515 carry_b = actions[i].length;
519 * Not enough bits in a source filed to fill a
520 * destination field. Switch to the next source.
522 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
523 (size_b == field->size * CHAR_BIT - off_b)) {
525 field->size * CHAR_BIT - off_b;
526 dcopy->offset += actions[i].length;
532 MLX5_ASSERT(item->spec);
533 data = flow_dv_fetch_field((const uint8_t *)item->spec +
534 field->offset, field->size);
535 /* Shift out the trailing masked bits from data. */
536 data = (data & mask) >> off_b;
537 actions[i].data1 = rte_cpu_to_be_32(data);
539 /* Convert entire record to expected big-endian format. */
540 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
544 } while (field->size);
545 if (resource->actions_num == i)
546 return rte_flow_error_set(error, EINVAL,
547 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
548 "invalid modification flow item");
549 resource->actions_num = i;
554 * Convert modify-header set IPv4 address action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to the error structure.
564 * 0 on success, a negative errno value otherwise and rte_errno is set.
567 flow_dv_convert_action_modify_ipv4
568 (struct mlx5_flow_dv_modify_hdr_resource *resource,
569 const struct rte_flow_action *action,
570 struct rte_flow_error *error)
572 const struct rte_flow_action_set_ipv4 *conf =
573 (const struct rte_flow_action_set_ipv4 *)(action->conf);
574 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
575 struct rte_flow_item_ipv4 ipv4;
576 struct rte_flow_item_ipv4 ipv4_mask;
578 memset(&ipv4, 0, sizeof(ipv4));
579 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
580 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
581 ipv4.hdr.src_addr = conf->ipv4_addr;
582 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
584 ipv4.hdr.dst_addr = conf->ipv4_addr;
585 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
588 item.mask = &ipv4_mask;
589 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
590 MLX5_MODIFICATION_TYPE_SET, error);
594 * Convert modify-header set IPv6 address action to DV specification.
596 * @param[in,out] resource
597 * Pointer to the modify-header resource.
599 * Pointer to action specification.
601 * Pointer to the error structure.
604 * 0 on success, a negative errno value otherwise and rte_errno is set.
607 flow_dv_convert_action_modify_ipv6
608 (struct mlx5_flow_dv_modify_hdr_resource *resource,
609 const struct rte_flow_action *action,
610 struct rte_flow_error *error)
612 const struct rte_flow_action_set_ipv6 *conf =
613 (const struct rte_flow_action_set_ipv6 *)(action->conf);
614 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
615 struct rte_flow_item_ipv6 ipv6;
616 struct rte_flow_item_ipv6 ipv6_mask;
618 memset(&ipv6, 0, sizeof(ipv6));
619 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
620 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
621 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
622 sizeof(ipv6.hdr.src_addr));
623 memcpy(&ipv6_mask.hdr.src_addr,
624 &rte_flow_item_ipv6_mask.hdr.src_addr,
625 sizeof(ipv6.hdr.src_addr));
627 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
628 sizeof(ipv6.hdr.dst_addr));
629 memcpy(&ipv6_mask.hdr.dst_addr,
630 &rte_flow_item_ipv6_mask.hdr.dst_addr,
631 sizeof(ipv6.hdr.dst_addr));
634 item.mask = &ipv6_mask;
635 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
636 MLX5_MODIFICATION_TYPE_SET, error);
640 * Convert modify-header set MAC address action to DV specification.
642 * @param[in,out] resource
643 * Pointer to the modify-header resource.
645 * Pointer to action specification.
647 * Pointer to the error structure.
650 * 0 on success, a negative errno value otherwise and rte_errno is set.
653 flow_dv_convert_action_modify_mac
654 (struct mlx5_flow_dv_modify_hdr_resource *resource,
655 const struct rte_flow_action *action,
656 struct rte_flow_error *error)
658 const struct rte_flow_action_set_mac *conf =
659 (const struct rte_flow_action_set_mac *)(action->conf);
660 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
661 struct rte_flow_item_eth eth;
662 struct rte_flow_item_eth eth_mask;
664 memset(ð, 0, sizeof(eth));
665 memset(ð_mask, 0, sizeof(eth_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
667 memcpy(ð.src.addr_bytes, &conf->mac_addr,
668 sizeof(eth.src.addr_bytes));
669 memcpy(ð_mask.src.addr_bytes,
670 &rte_flow_item_eth_mask.src.addr_bytes,
671 sizeof(eth_mask.src.addr_bytes));
673 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
674 sizeof(eth.dst.addr_bytes));
675 memcpy(ð_mask.dst.addr_bytes,
676 &rte_flow_item_eth_mask.dst.addr_bytes,
677 sizeof(eth_mask.dst.addr_bytes));
680 item.mask = ð_mask;
681 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
682 MLX5_MODIFICATION_TYPE_SET, error);
686 * Convert modify-header set VLAN VID action to DV specification.
688 * @param[in,out] resource
689 * Pointer to the modify-header resource.
691 * Pointer to action specification.
693 * Pointer to the error structure.
696 * 0 on success, a negative errno value otherwise and rte_errno is set.
699 flow_dv_convert_action_modify_vlan_vid
700 (struct mlx5_flow_dv_modify_hdr_resource *resource,
701 const struct rte_flow_action *action,
702 struct rte_flow_error *error)
704 const struct rte_flow_action_of_set_vlan_vid *conf =
705 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
706 int i = resource->actions_num;
707 struct mlx5_modification_cmd *actions = resource->actions;
708 struct field_modify_info *field = modify_vlan_out_first_vid;
710 if (i >= MLX5_MAX_MODIFY_NUM)
711 return rte_flow_error_set(error, EINVAL,
712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
713 "too many items to modify");
714 actions[i] = (struct mlx5_modification_cmd) {
715 .action_type = MLX5_MODIFICATION_TYPE_SET,
717 .length = field->size,
718 .offset = field->offset,
720 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
721 actions[i].data1 = conf->vlan_vid;
722 actions[i].data1 = actions[i].data1 << 16;
723 resource->actions_num = ++i;
728 * Convert modify-header set TP action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_tp
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_tp *conf =
757 (const struct rte_flow_action_set_tp *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_udp udp;
760 struct rte_flow_item_udp udp_mask;
761 struct rte_flow_item_tcp tcp;
762 struct rte_flow_item_tcp tcp_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&udp, 0, sizeof(udp));
769 memset(&udp_mask, 0, sizeof(udp_mask));
770 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
771 udp.hdr.src_port = conf->port;
772 udp_mask.hdr.src_port =
773 rte_flow_item_udp_mask.hdr.src_port;
775 udp.hdr.dst_port = conf->port;
776 udp_mask.hdr.dst_port =
777 rte_flow_item_udp_mask.hdr.dst_port;
779 item.type = RTE_FLOW_ITEM_TYPE_UDP;
781 item.mask = &udp_mask;
784 MLX5_ASSERT(attr->tcp);
785 memset(&tcp, 0, sizeof(tcp));
786 memset(&tcp_mask, 0, sizeof(tcp_mask));
787 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
788 tcp.hdr.src_port = conf->port;
789 tcp_mask.hdr.src_port =
790 rte_flow_item_tcp_mask.hdr.src_port;
792 tcp.hdr.dst_port = conf->port;
793 tcp_mask.hdr.dst_port =
794 rte_flow_item_tcp_mask.hdr.dst_port;
796 item.type = RTE_FLOW_ITEM_TYPE_TCP;
798 item.mask = &tcp_mask;
801 return flow_dv_convert_modify_action(&item, field, NULL, resource,
802 MLX5_MODIFICATION_TYPE_SET, error);
806 * Convert modify-header set TTL action to DV specification.
808 * @param[in,out] resource
809 * Pointer to the modify-header resource.
811 * Pointer to action specification.
813 * Pointer to rte_flow_item objects list.
815 * Pointer to flow attributes structure.
816 * @param[in] dev_flow
817 * Pointer to the sub flow.
818 * @param[in] tunnel_decap
819 * Whether action is after tunnel decapsulation.
821 * Pointer to the error structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 flow_dv_convert_action_modify_ttl
828 (struct mlx5_flow_dv_modify_hdr_resource *resource,
829 const struct rte_flow_action *action,
830 const struct rte_flow_item *items,
831 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
832 bool tunnel_decap, struct rte_flow_error *error)
834 const struct rte_flow_action_set_ttl *conf =
835 (const struct rte_flow_action_set_ttl *)(action->conf);
836 struct rte_flow_item item;
837 struct rte_flow_item_ipv4 ipv4;
838 struct rte_flow_item_ipv4 ipv4_mask;
839 struct rte_flow_item_ipv6 ipv6;
840 struct rte_flow_item_ipv6 ipv6_mask;
841 struct field_modify_info *field;
844 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
846 memset(&ipv4, 0, sizeof(ipv4));
847 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
848 ipv4.hdr.time_to_live = conf->ttl_value;
849 ipv4_mask.hdr.time_to_live = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
852 item.mask = &ipv4_mask;
855 MLX5_ASSERT(attr->ipv6);
856 memset(&ipv6, 0, sizeof(ipv6));
857 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
858 ipv6.hdr.hop_limits = conf->ttl_value;
859 ipv6_mask.hdr.hop_limits = 0xFF;
860 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
862 item.mask = &ipv6_mask;
865 return flow_dv_convert_modify_action(&item, field, NULL, resource,
866 MLX5_MODIFICATION_TYPE_SET, error);
870 * Convert modify-header decrement TTL action to DV specification.
872 * @param[in,out] resource
873 * Pointer to the modify-header resource.
875 * Pointer to action specification.
877 * Pointer to rte_flow_item objects list.
879 * Pointer to flow attributes structure.
880 * @param[in] dev_flow
881 * Pointer to the sub flow.
882 * @param[in] tunnel_decap
883 * Whether action is after tunnel decapsulation.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_dec_ttl
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_item *items,
894 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
895 bool tunnel_decap, struct rte_flow_error *error)
897 struct rte_flow_item item;
898 struct rte_flow_item_ipv4 ipv4;
899 struct rte_flow_item_ipv4 ipv4_mask;
900 struct rte_flow_item_ipv6 ipv6;
901 struct rte_flow_item_ipv6 ipv6_mask;
902 struct field_modify_info *field;
905 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
907 memset(&ipv4, 0, sizeof(ipv4));
908 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
909 ipv4.hdr.time_to_live = 0xFF;
910 ipv4_mask.hdr.time_to_live = 0xFF;
911 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
913 item.mask = &ipv4_mask;
916 MLX5_ASSERT(attr->ipv6);
917 memset(&ipv6, 0, sizeof(ipv6));
918 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
919 ipv6.hdr.hop_limits = 0xFF;
920 ipv6_mask.hdr.hop_limits = 0xFF;
921 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
923 item.mask = &ipv6_mask;
926 return flow_dv_convert_modify_action(&item, field, NULL, resource,
927 MLX5_MODIFICATION_TYPE_ADD, error);
931 * Convert modify-header increment/decrement TCP Sequence number
932 * to DV specification.
934 * @param[in,out] resource
935 * Pointer to the modify-header resource.
937 * Pointer to action specification.
939 * Pointer to the error structure.
942 * 0 on success, a negative errno value otherwise and rte_errno is set.
945 flow_dv_convert_action_modify_tcp_seq
946 (struct mlx5_flow_dv_modify_hdr_resource *resource,
947 const struct rte_flow_action *action,
948 struct rte_flow_error *error)
950 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
951 uint64_t value = rte_be_to_cpu_32(*conf);
952 struct rte_flow_item item;
953 struct rte_flow_item_tcp tcp;
954 struct rte_flow_item_tcp tcp_mask;
956 memset(&tcp, 0, sizeof(tcp));
957 memset(&tcp_mask, 0, sizeof(tcp_mask));
958 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
960 * The HW has no decrement operation, only increment operation.
961 * To simulate decrement X from Y using increment operation
962 * we need to add UINT32_MAX X times to Y.
963 * Each adding of UINT32_MAX decrements Y by 1.
966 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
967 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
968 item.type = RTE_FLOW_ITEM_TYPE_TCP;
970 item.mask = &tcp_mask;
971 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
972 MLX5_MODIFICATION_TYPE_ADD, error);
976 * Convert modify-header increment/decrement TCP Acknowledgment number
977 * to DV specification.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_modify_tcp_ack
991 (struct mlx5_flow_dv_modify_hdr_resource *resource,
992 const struct rte_flow_action *action,
993 struct rte_flow_error *error)
995 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
996 uint64_t value = rte_be_to_cpu_32(*conf);
997 struct rte_flow_item item;
998 struct rte_flow_item_tcp tcp;
999 struct rte_flow_item_tcp tcp_mask;
1001 memset(&tcp, 0, sizeof(tcp));
1002 memset(&tcp_mask, 0, sizeof(tcp_mask));
1003 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
1005 * The HW has no decrement operation, only increment operation.
1006 * To simulate decrement X from Y using increment operation
1007 * we need to add UINT32_MAX X times to Y.
1008 * Each adding of UINT32_MAX decrements Y by 1.
1010 value *= UINT32_MAX;
1011 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1012 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1013 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1015 item.mask = &tcp_mask;
1016 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_ADD, error);
1020 static enum mlx5_modification_field reg_to_field[] = {
1021 [REG_NON] = MLX5_MODI_OUT_NONE,
1022 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1023 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1024 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1025 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1026 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1027 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1028 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1029 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1030 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1031 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1035 * Convert register set to DV specification.
1037 * @param[in,out] resource
1038 * Pointer to the modify-header resource.
1040 * Pointer to action specification.
1042 * Pointer to the error structure.
1045 * 0 on success, a negative errno value otherwise and rte_errno is set.
1048 flow_dv_convert_action_set_reg
1049 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1050 const struct rte_flow_action *action,
1051 struct rte_flow_error *error)
1053 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1054 struct mlx5_modification_cmd *actions = resource->actions;
1055 uint32_t i = resource->actions_num;
1057 if (i >= MLX5_MAX_MODIFY_NUM)
1058 return rte_flow_error_set(error, EINVAL,
1059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1060 "too many items to modify");
1061 MLX5_ASSERT(conf->id != REG_NON);
1062 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1063 actions[i] = (struct mlx5_modification_cmd) {
1064 .action_type = MLX5_MODIFICATION_TYPE_SET,
1065 .field = reg_to_field[conf->id],
1066 .offset = conf->offset,
1067 .length = conf->length,
1069 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1070 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1072 resource->actions_num = i;
1077 * Convert SET_TAG action to DV specification.
1080 * Pointer to the rte_eth_dev structure.
1081 * @param[in,out] resource
1082 * Pointer to the modify-header resource.
1084 * Pointer to action specification.
1086 * Pointer to the error structure.
1089 * 0 on success, a negative errno value otherwise and rte_errno is set.
1092 flow_dv_convert_action_set_tag
1093 (struct rte_eth_dev *dev,
1094 struct mlx5_flow_dv_modify_hdr_resource *resource,
1095 const struct rte_flow_action_set_tag *conf,
1096 struct rte_flow_error *error)
1098 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1099 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1100 struct rte_flow_item item = {
1104 struct field_modify_info reg_c_x[] = {
1107 enum mlx5_modification_field reg_type;
1110 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1113 MLX5_ASSERT(ret != REG_NON);
1114 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1115 reg_type = reg_to_field[ret];
1116 MLX5_ASSERT(reg_type > 0);
1117 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1118 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1119 MLX5_MODIFICATION_TYPE_SET, error);
1123 * Convert internal COPY_REG action to DV specification.
1126 * Pointer to the rte_eth_dev structure.
1127 * @param[in,out] res
1128 * Pointer to the modify-header resource.
1130 * Pointer to action specification.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1139 struct mlx5_flow_dv_modify_hdr_resource *res,
1140 const struct rte_flow_action *action,
1141 struct rte_flow_error *error)
1143 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1144 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_src[] = {
1150 {4, 0, reg_to_field[conf->src]},
1153 struct field_modify_info reg_dst = {
1155 .id = reg_to_field[conf->dst],
1157 /* Adjust reg_c[0] usage according to reported mask. */
1158 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1159 struct mlx5_priv *priv = dev->data->dev_private;
1160 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1162 MLX5_ASSERT(reg_c0);
1163 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1164 if (conf->dst == REG_C_0) {
1165 /* Copy to reg_c[0], within mask only. */
1166 reg_dst.offset = rte_bsf32(reg_c0);
1167 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1170 mask = rte_cpu_to_be_32(reg_c0);
1173 return flow_dv_convert_modify_action(&item,
1174 reg_src, ®_dst, res,
1175 MLX5_MODIFICATION_TYPE_COPY,
1180 * Convert MARK action to DV specification. This routine is used
1181 * in extensive metadata only and requires metadata register to be
1182 * handled. In legacy mode hardware tag resource is engaged.
1185 * Pointer to the rte_eth_dev structure.
1187 * Pointer to MARK action specification.
1188 * @param[in,out] resource
1189 * Pointer to the modify-header resource.
1191 * Pointer to the error structure.
1194 * 0 on success, a negative errno value otherwise and rte_errno is set.
1197 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1198 const struct rte_flow_action_mark *conf,
1199 struct mlx5_flow_dv_modify_hdr_resource *resource,
1200 struct rte_flow_error *error)
1202 struct mlx5_priv *priv = dev->data->dev_private;
1203 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1204 priv->sh->dv_mark_mask);
1205 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1206 struct rte_flow_item item = {
1210 struct field_modify_info reg_c_x[] = {
1216 return rte_flow_error_set(error, EINVAL,
1217 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1218 NULL, "zero mark action mask");
1219 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1222 MLX5_ASSERT(reg > 0);
1223 if (reg == REG_C_0) {
1224 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1225 uint32_t shl_c0 = rte_bsf32(msk_c0);
1227 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1228 mask = rte_cpu_to_be_32(mask) & msk_c0;
1229 mask = rte_cpu_to_be_32(mask << shl_c0);
1231 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1232 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1233 MLX5_MODIFICATION_TYPE_SET, error);
1237 * Get metadata register index for specified steering domain.
1240 * Pointer to the rte_eth_dev structure.
1242 * Attributes of flow to determine steering domain.
1244 * Pointer to the error structure.
1247 * positive index on success, a negative errno value otherwise
1248 * and rte_errno is set.
1250 static enum modify_reg
1251 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1252 const struct rte_flow_attr *attr,
1253 struct rte_flow_error *error)
1256 mlx5_flow_get_reg_id(dev, attr->transfer ?
1260 MLX5_METADATA_RX, 0, error);
1262 return rte_flow_error_set(error,
1263 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1264 NULL, "unavailable "
1265 "metadata register");
1270 * Convert SET_META action to DV specification.
1273 * Pointer to the rte_eth_dev structure.
1274 * @param[in,out] resource
1275 * Pointer to the modify-header resource.
1277 * Attributes of flow that includes this item.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_set_meta
1288 (struct rte_eth_dev *dev,
1289 struct mlx5_flow_dv_modify_hdr_resource *resource,
1290 const struct rte_flow_attr *attr,
1291 const struct rte_flow_action_set_meta *conf,
1292 struct rte_flow_error *error)
1294 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1295 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1296 struct rte_flow_item item = {
1300 struct field_modify_info reg_c_x[] = {
1303 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1307 MLX5_ASSERT(reg != REG_NON);
1308 if (reg == REG_C_0) {
1309 struct mlx5_priv *priv = dev->data->dev_private;
1310 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1311 uint32_t shl_c0 = rte_bsf32(msk_c0);
1313 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1314 mask = rte_cpu_to_be_32(mask) & msk_c0;
1315 mask = rte_cpu_to_be_32(mask << shl_c0);
1317 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1318 /* The routine expects parameters in memory as big-endian ones. */
1319 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Convert modify-header set IPv4 DSCP action to DV specification.
1326 * @param[in,out] resource
1327 * Pointer to the modify-header resource.
1329 * Pointer to action specification.
1331 * Pointer to the error structure.
1334 * 0 on success, a negative errno value otherwise and rte_errno is set.
1337 flow_dv_convert_action_modify_ipv4_dscp
1338 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1339 const struct rte_flow_action *action,
1340 struct rte_flow_error *error)
1342 const struct rte_flow_action_set_dscp *conf =
1343 (const struct rte_flow_action_set_dscp *)(action->conf);
1344 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1345 struct rte_flow_item_ipv4 ipv4;
1346 struct rte_flow_item_ipv4 ipv4_mask;
1348 memset(&ipv4, 0, sizeof(ipv4));
1349 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1350 ipv4.hdr.type_of_service = conf->dscp;
1351 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1353 item.mask = &ipv4_mask;
1354 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1355 MLX5_MODIFICATION_TYPE_SET, error);
1359 * Convert modify-header set IPv6 DSCP action to DV specification.
1361 * @param[in,out] resource
1362 * Pointer to the modify-header resource.
1364 * Pointer to action specification.
1366 * Pointer to the error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_convert_action_modify_ipv6_dscp
1373 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1374 const struct rte_flow_action *action,
1375 struct rte_flow_error *error)
1377 const struct rte_flow_action_set_dscp *conf =
1378 (const struct rte_flow_action_set_dscp *)(action->conf);
1379 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1380 struct rte_flow_item_ipv6 ipv6;
1381 struct rte_flow_item_ipv6 ipv6_mask;
1383 memset(&ipv6, 0, sizeof(ipv6));
1384 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1386 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1387 * rdma-core only accept the DSCP bits byte aligned start from
1388 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1389 * bits in IPv6 case as rdma-core requires byte aligned value.
1391 ipv6.hdr.vtc_flow = conf->dscp;
1392 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1394 item.mask = &ipv6_mask;
1395 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1396 MLX5_MODIFICATION_TYPE_SET, error);
1400 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1401 enum rte_flow_field_id field, int inherit,
1402 const struct rte_flow_attr *attr,
1403 struct rte_flow_error *error)
1405 struct mlx5_priv *priv = dev->data->dev_private;
1408 case RTE_FLOW_FIELD_START:
1410 case RTE_FLOW_FIELD_MAC_DST:
1411 case RTE_FLOW_FIELD_MAC_SRC:
1413 case RTE_FLOW_FIELD_VLAN_TYPE:
1415 case RTE_FLOW_FIELD_VLAN_ID:
1417 case RTE_FLOW_FIELD_MAC_TYPE:
1419 case RTE_FLOW_FIELD_IPV4_DSCP:
1421 case RTE_FLOW_FIELD_IPV4_TTL:
1423 case RTE_FLOW_FIELD_IPV4_SRC:
1424 case RTE_FLOW_FIELD_IPV4_DST:
1426 case RTE_FLOW_FIELD_IPV6_DSCP:
1428 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1430 case RTE_FLOW_FIELD_IPV6_SRC:
1431 case RTE_FLOW_FIELD_IPV6_DST:
1433 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1434 case RTE_FLOW_FIELD_TCP_PORT_DST:
1436 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1437 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1439 case RTE_FLOW_FIELD_TCP_FLAGS:
1441 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1442 case RTE_FLOW_FIELD_UDP_PORT_DST:
1444 case RTE_FLOW_FIELD_VXLAN_VNI:
1445 case RTE_FLOW_FIELD_GENEVE_VNI:
1447 case RTE_FLOW_FIELD_GTP_TEID:
1448 case RTE_FLOW_FIELD_TAG:
1450 case RTE_FLOW_FIELD_MARK:
1451 return __builtin_popcount(priv->sh->dv_mark_mask);
1452 case RTE_FLOW_FIELD_META:
1453 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1454 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1455 case RTE_FLOW_FIELD_POINTER:
1456 case RTE_FLOW_FIELD_VALUE:
1457 return inherit < 0 ? 0 : inherit;
1465 mlx5_flow_field_id_to_modify_info
1466 (const struct rte_flow_action_modify_data *data,
1467 struct field_modify_info *info, uint32_t *mask,
1468 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1469 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1471 struct mlx5_priv *priv = dev->data->dev_private;
1475 switch (data->field) {
1476 case RTE_FLOW_FIELD_START:
1477 /* not supported yet */
1480 case RTE_FLOW_FIELD_MAC_DST:
1481 off = data->offset > 16 ? data->offset - 16 : 0;
1483 if (data->offset < 16) {
1484 info[idx] = (struct field_modify_info){2, 4,
1485 MLX5_MODI_OUT_DMAC_15_0};
1487 mask[1] = rte_cpu_to_be_16(0xffff >>
1491 mask[1] = RTE_BE16(0xffff);
1498 info[idx] = (struct field_modify_info){4, 0,
1499 MLX5_MODI_OUT_DMAC_47_16};
1500 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1501 (32 - width)) << off);
1503 if (data->offset < 16)
1504 info[idx++] = (struct field_modify_info){2, 4,
1505 MLX5_MODI_OUT_DMAC_15_0};
1506 info[idx] = (struct field_modify_info){4, 0,
1507 MLX5_MODI_OUT_DMAC_47_16};
1510 case RTE_FLOW_FIELD_MAC_SRC:
1511 off = data->offset > 16 ? data->offset - 16 : 0;
1513 if (data->offset < 16) {
1514 info[idx] = (struct field_modify_info){2, 4,
1515 MLX5_MODI_OUT_SMAC_15_0};
1517 mask[1] = rte_cpu_to_be_16(0xffff >>
1521 mask[1] = RTE_BE16(0xffff);
1528 info[idx] = (struct field_modify_info){4, 0,
1529 MLX5_MODI_OUT_SMAC_47_16};
1530 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1531 (32 - width)) << off);
1533 if (data->offset < 16)
1534 info[idx++] = (struct field_modify_info){2, 4,
1535 MLX5_MODI_OUT_SMAC_15_0};
1536 info[idx] = (struct field_modify_info){4, 0,
1537 MLX5_MODI_OUT_SMAC_47_16};
1540 case RTE_FLOW_FIELD_VLAN_TYPE:
1541 /* not supported yet */
1543 case RTE_FLOW_FIELD_VLAN_ID:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_FIRST_VID};
1547 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1549 case RTE_FLOW_FIELD_MAC_TYPE:
1550 info[idx] = (struct field_modify_info){2, 0,
1551 MLX5_MODI_OUT_ETHERTYPE};
1553 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1555 case RTE_FLOW_FIELD_IPV4_DSCP:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IP_DSCP};
1559 mask[idx] = 0x3f >> (6 - width);
1561 case RTE_FLOW_FIELD_IPV4_TTL:
1562 info[idx] = (struct field_modify_info){1, 0,
1563 MLX5_MODI_OUT_IPV4_TTL};
1565 mask[idx] = 0xff >> (8 - width);
1567 case RTE_FLOW_FIELD_IPV4_SRC:
1568 info[idx] = (struct field_modify_info){4, 0,
1569 MLX5_MODI_OUT_SIPV4};
1571 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574 case RTE_FLOW_FIELD_IPV4_DST:
1575 info[idx] = (struct field_modify_info){4, 0,
1576 MLX5_MODI_OUT_DIPV4};
1578 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1581 case RTE_FLOW_FIELD_IPV6_DSCP:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IP_DSCP};
1585 mask[idx] = 0x3f >> (6 - width);
1587 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1588 info[idx] = (struct field_modify_info){1, 0,
1589 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1591 mask[idx] = 0xff >> (8 - width);
1593 case RTE_FLOW_FIELD_IPV6_SRC:
1595 if (data->offset < 32) {
1596 info[idx] = (struct field_modify_info){4, 12,
1597 MLX5_MODI_OUT_SIPV6_31_0};
1600 rte_cpu_to_be_32(0xffffffff >>
1604 mask[3] = RTE_BE32(0xffffffff);
1611 if (data->offset < 64) {
1612 info[idx] = (struct field_modify_info){4, 8,
1613 MLX5_MODI_OUT_SIPV6_63_32};
1616 rte_cpu_to_be_32(0xffffffff >>
1620 mask[2] = RTE_BE32(0xffffffff);
1627 if (data->offset < 96) {
1628 info[idx] = (struct field_modify_info){4, 4,
1629 MLX5_MODI_OUT_SIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[1] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1645 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1647 if (data->offset < 32)
1648 info[idx++] = (struct field_modify_info){4, 12,
1649 MLX5_MODI_OUT_SIPV6_31_0};
1650 if (data->offset < 64)
1651 info[idx++] = (struct field_modify_info){4, 8,
1652 MLX5_MODI_OUT_SIPV6_63_32};
1653 if (data->offset < 96)
1654 info[idx++] = (struct field_modify_info){4, 4,
1655 MLX5_MODI_OUT_SIPV6_95_64};
1656 if (data->offset < 128)
1657 info[idx++] = (struct field_modify_info){4, 0,
1658 MLX5_MODI_OUT_SIPV6_127_96};
1661 case RTE_FLOW_FIELD_IPV6_DST:
1663 if (data->offset < 32) {
1664 info[idx] = (struct field_modify_info){4, 12,
1665 MLX5_MODI_OUT_DIPV6_31_0};
1668 rte_cpu_to_be_32(0xffffffff >>
1672 mask[3] = RTE_BE32(0xffffffff);
1679 if (data->offset < 64) {
1680 info[idx] = (struct field_modify_info){4, 8,
1681 MLX5_MODI_OUT_DIPV6_63_32};
1684 rte_cpu_to_be_32(0xffffffff >>
1688 mask[2] = RTE_BE32(0xffffffff);
1695 if (data->offset < 96) {
1696 info[idx] = (struct field_modify_info){4, 4,
1697 MLX5_MODI_OUT_DIPV6_95_64};
1700 rte_cpu_to_be_32(0xffffffff >>
1704 mask[1] = RTE_BE32(0xffffffff);
1711 info[idx] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1713 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1715 if (data->offset < 32)
1716 info[idx++] = (struct field_modify_info){4, 12,
1717 MLX5_MODI_OUT_DIPV6_31_0};
1718 if (data->offset < 64)
1719 info[idx++] = (struct field_modify_info){4, 8,
1720 MLX5_MODI_OUT_DIPV6_63_32};
1721 if (data->offset < 96)
1722 info[idx++] = (struct field_modify_info){4, 4,
1723 MLX5_MODI_OUT_DIPV6_95_64};
1724 if (data->offset < 128)
1725 info[idx++] = (struct field_modify_info){4, 0,
1726 MLX5_MODI_OUT_DIPV6_127_96};
1729 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_SPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_PORT_DST:
1736 info[idx] = (struct field_modify_info){2, 0,
1737 MLX5_MODI_OUT_TCP_DPORT};
1739 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1741 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1742 info[idx] = (struct field_modify_info){4, 0,
1743 MLX5_MODI_OUT_TCP_SEQ_NUM};
1745 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1748 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1749 info[idx] = (struct field_modify_info){4, 0,
1750 MLX5_MODI_OUT_TCP_ACK_NUM};
1752 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1755 case RTE_FLOW_FIELD_TCP_FLAGS:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_TCP_FLAGS};
1759 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_SPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_UDP_PORT_DST:
1768 info[idx] = (struct field_modify_info){2, 0,
1769 MLX5_MODI_OUT_UDP_DPORT};
1771 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1773 case RTE_FLOW_FIELD_VXLAN_VNI:
1774 /* not supported yet */
1776 case RTE_FLOW_FIELD_GENEVE_VNI:
1777 /* not supported yet*/
1779 case RTE_FLOW_FIELD_GTP_TEID:
1780 info[idx] = (struct field_modify_info){4, 0,
1781 MLX5_MODI_GTP_TEID};
1783 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1786 case RTE_FLOW_FIELD_TAG:
1788 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1789 data->level, error);
1792 MLX5_ASSERT(reg != REG_NON);
1793 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1794 info[idx] = (struct field_modify_info){4, 0,
1798 rte_cpu_to_be_32(0xffffffff >>
1802 case RTE_FLOW_FIELD_MARK:
1804 uint32_t mark_mask = priv->sh->dv_mark_mask;
1805 uint32_t mark_count = __builtin_popcount(mark_mask);
1806 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1810 MLX5_ASSERT(reg != REG_NON);
1811 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1812 info[idx] = (struct field_modify_info){4, 0,
1815 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1816 (mark_count - width)) & mark_mask);
1819 case RTE_FLOW_FIELD_META:
1821 uint32_t meta_mask = priv->sh->dv_meta_mask;
1822 uint32_t meta_count = __builtin_popcount(meta_mask);
1824 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1825 uint32_t shl_c0 = rte_bsf32(msk_c0);
1826 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1829 MLX5_ASSERT(reg != REG_NON);
1830 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1833 info[idx] = (struct field_modify_info){4, 0,
1836 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1837 (meta_count - width)) & meta_mask);
1840 case RTE_FLOW_FIELD_POINTER:
1841 case RTE_FLOW_FIELD_VALUE:
1849 * Convert modify_field action to DV specification.
1852 * Pointer to the rte_eth_dev structure.
1853 * @param[in,out] resource
1854 * Pointer to the modify-header resource.
1856 * Pointer to action specification.
1858 * Attributes of flow that includes this item.
1860 * Pointer to the error structure.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 flow_dv_convert_action_modify_field
1867 (struct rte_eth_dev *dev,
1868 struct mlx5_flow_dv_modify_hdr_resource *resource,
1869 const struct rte_flow_action *action,
1870 const struct rte_flow_attr *attr,
1871 struct rte_flow_error *error)
1873 const struct rte_flow_action_modify_field *conf =
1874 (const struct rte_flow_action_modify_field *)(action->conf);
1875 struct rte_flow_item item = {
1879 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1881 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1883 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1887 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1888 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1889 type = MLX5_MODIFICATION_TYPE_SET;
1890 /** For SET fill the destination field (field) first. */
1891 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1892 conf->width, &shift, dev,
1894 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1895 (void *)(uintptr_t)conf->src.pvalue :
1896 (void *)(uintptr_t)&conf->src.value;
1898 type = MLX5_MODIFICATION_TYPE_COPY;
1899 /** For COPY fill the destination field (dcopy) without mask. */
1900 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1901 conf->width, &shift, dev,
1903 /** Then construct the source field (field) with mask. */
1904 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1905 conf->width, &shift,
1909 return flow_dv_convert_modify_action(&item,
1910 field, dcopy, resource, type, error);
1914 * Validate MARK item.
1917 * Pointer to the rte_eth_dev structure.
1919 * Item specification.
1921 * Attributes of flow that includes this item.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1930 const struct rte_flow_item *item,
1931 const struct rte_flow_attr *attr __rte_unused,
1932 struct rte_flow_error *error)
1934 struct mlx5_priv *priv = dev->data->dev_private;
1935 struct mlx5_dev_config *config = &priv->config;
1936 const struct rte_flow_item_mark *spec = item->spec;
1937 const struct rte_flow_item_mark *mask = item->mask;
1938 const struct rte_flow_item_mark nic_mask = {
1939 .id = priv->sh->dv_mark_mask,
1943 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1944 return rte_flow_error_set(error, ENOTSUP,
1945 RTE_FLOW_ERROR_TYPE_ITEM, item,
1946 "extended metadata feature"
1948 if (!mlx5_flow_ext_mreg_supported(dev))
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ITEM, item,
1951 "extended metadata register"
1952 " isn't supported");
1954 return rte_flow_error_set(error, ENOTSUP,
1955 RTE_FLOW_ERROR_TYPE_ITEM, item,
1956 "extended metadata register"
1957 " isn't available");
1958 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965 "data cannot be empty");
1966 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1970 "mark id exceeds the limit");
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1976 "mask cannot be zero");
1978 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1979 (const uint8_t *)&nic_mask,
1980 sizeof(struct rte_flow_item_mark),
1981 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1988 * Validate META item.
1991 * Pointer to the rte_eth_dev structure.
1993 * Item specification.
1995 * Attributes of flow that includes this item.
1997 * Pointer to error structure.
2000 * 0 on success, a negative errno value otherwise and rte_errno is set.
2003 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2004 const struct rte_flow_item *item,
2005 const struct rte_flow_attr *attr,
2006 struct rte_flow_error *error)
2008 struct mlx5_priv *priv = dev->data->dev_private;
2009 struct mlx5_dev_config *config = &priv->config;
2010 const struct rte_flow_item_meta *spec = item->spec;
2011 const struct rte_flow_item_meta *mask = item->mask;
2012 struct rte_flow_item_meta nic_mask = {
2019 return rte_flow_error_set(error, EINVAL,
2020 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2022 "data cannot be empty");
2023 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2024 if (!mlx5_flow_ext_mreg_supported(dev))
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 "extended metadata register"
2028 " isn't supported");
2029 reg = flow_dv_get_metadata_reg(dev, attr, error);
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "unavalable extended metadata register");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 nic_mask.data = priv->sh->dv_meta_mask;
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "extended metadata feature "
2048 "should be enabled when "
2049 "meta item is requested "
2050 "with e-switch mode ");
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM, item,
2054 "match on metadata for ingress "
2055 "is not supported in legacy "
2059 mask = &rte_flow_item_meta_mask;
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2063 "mask cannot be zero");
2065 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2066 (const uint8_t *)&nic_mask,
2067 sizeof(struct rte_flow_item_meta),
2068 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2073 * Validate TAG item.
2076 * Pointer to the rte_eth_dev structure.
2078 * Item specification.
2080 * Attributes of flow that includes this item.
2082 * Pointer to error structure.
2085 * 0 on success, a negative errno value otherwise and rte_errno is set.
2088 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2089 const struct rte_flow_item *item,
2090 const struct rte_flow_attr *attr __rte_unused,
2091 struct rte_flow_error *error)
2093 const struct rte_flow_item_tag *spec = item->spec;
2094 const struct rte_flow_item_tag *mask = item->mask;
2095 const struct rte_flow_item_tag nic_mask = {
2096 .data = RTE_BE32(UINT32_MAX),
2101 if (!mlx5_flow_ext_mreg_supported(dev))
2102 return rte_flow_error_set(error, ENOTSUP,
2103 RTE_FLOW_ERROR_TYPE_ITEM, item,
2104 "extensive metadata register"
2105 " isn't supported");
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2110 "data cannot be empty");
2112 mask = &rte_flow_item_tag_mask;
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2116 "mask cannot be zero");
2118 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2119 (const uint8_t *)&nic_mask,
2120 sizeof(struct rte_flow_item_tag),
2121 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2124 if (mask->index != 0xff)
2125 return rte_flow_error_set(error, EINVAL,
2126 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2127 "partial mask for tag index"
2128 " is not supported");
2129 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2132 MLX5_ASSERT(ret != REG_NON);
2137 * Validate vport item.
2140 * Pointer to the rte_eth_dev structure.
2142 * Item specification.
2144 * Attributes of flow that includes this item.
2145 * @param[in] item_flags
2146 * Bit-fields that holds the items detected until now.
2148 * Pointer to error structure.
2151 * 0 on success, a negative errno value otherwise and rte_errno is set.
2154 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2155 const struct rte_flow_item *item,
2156 const struct rte_flow_attr *attr,
2157 uint64_t item_flags,
2158 struct rte_flow_error *error)
2160 const struct rte_flow_item_port_id *spec = item->spec;
2161 const struct rte_flow_item_port_id *mask = item->mask;
2162 const struct rte_flow_item_port_id switch_mask = {
2165 struct mlx5_priv *esw_priv;
2166 struct mlx5_priv *dev_priv;
2169 if (!attr->transfer)
2170 return rte_flow_error_set(error, EINVAL,
2171 RTE_FLOW_ERROR_TYPE_ITEM,
2173 "match on port id is valid only"
2174 " when transfer flag is enabled");
2175 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM, item,
2178 "multiple source ports are not"
2181 mask = &switch_mask;
2182 if (mask->id != 0xffffffff)
2183 return rte_flow_error_set(error, ENOTSUP,
2184 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2186 "no support for partial mask on"
2188 ret = mlx5_flow_item_acceptable
2189 (item, (const uint8_t *)mask,
2190 (const uint8_t *)&rte_flow_item_port_id_mask,
2191 sizeof(struct rte_flow_item_port_id),
2192 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2197 if (spec->id == MLX5_PORT_ESW_MGR)
2199 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2201 return rte_flow_error_set(error, rte_errno,
2202 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2203 "failed to obtain E-Switch info for"
2205 dev_priv = mlx5_dev_to_eswitch_info(dev);
2207 return rte_flow_error_set(error, rte_errno,
2208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2210 "failed to obtain E-Switch info");
2211 if (esw_priv->domain_id != dev_priv->domain_id)
2212 return rte_flow_error_set(error, EINVAL,
2213 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2214 "cannot match on a port from a"
2215 " different E-Switch");
2220 * Validate VLAN item.
2223 * Item specification.
2224 * @param[in] item_flags
2225 * Bit-fields that holds the items detected until now.
2227 * Ethernet device flow is being created on.
2229 * Pointer to error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2236 uint64_t item_flags,
2237 struct rte_eth_dev *dev,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_item_vlan *mask = item->mask;
2241 const struct rte_flow_item_vlan nic_mask = {
2242 .tci = RTE_BE16(UINT16_MAX),
2243 .inner_type = RTE_BE16(UINT16_MAX),
2246 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2248 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2249 MLX5_FLOW_LAYER_INNER_L4) :
2250 (MLX5_FLOW_LAYER_OUTER_L3 |
2251 MLX5_FLOW_LAYER_OUTER_L4);
2252 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2253 MLX5_FLOW_LAYER_OUTER_VLAN;
2255 if (item_flags & vlanm)
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ITEM, item,
2258 "multiple VLAN layers not supported");
2259 else if ((item_flags & l34m) != 0)
2260 return rte_flow_error_set(error, EINVAL,
2261 RTE_FLOW_ERROR_TYPE_ITEM, item,
2262 "VLAN cannot follow L3/L4 layer");
2264 mask = &rte_flow_item_vlan_mask;
2265 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2266 (const uint8_t *)&nic_mask,
2267 sizeof(struct rte_flow_item_vlan),
2268 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2271 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2272 struct mlx5_priv *priv = dev->data->dev_private;
2274 if (priv->vmwa_context) {
2276 * Non-NULL context means we have a virtual machine
2277 * and SR-IOV enabled, we have to create VLAN interface
2278 * to make hypervisor to setup E-Switch vport
2279 * context correctly. We avoid creating the multiple
2280 * VLAN interfaces, so we cannot support VLAN tag mask.
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ITEM,
2285 "VLAN tag mask is not"
2286 " supported in virtual"
2294 * GTP flags are contained in 1 byte of the format:
2295 * -------------------------------------------
2296 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2297 * |-----------------------------------------|
2298 * | value | Version | PT | Res | E | S | PN |
2299 * -------------------------------------------
2301 * Matching is supported only for GTP flags E, S, PN.
2303 #define MLX5_GTP_FLAGS_MASK 0x07
2306 * Validate GTP item.
2309 * Pointer to the rte_eth_dev structure.
2311 * Item specification.
2312 * @param[in] item_flags
2313 * Bit-fields that holds the items detected until now.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2322 const struct rte_flow_item *item,
2323 uint64_t item_flags,
2324 struct rte_flow_error *error)
2326 struct mlx5_priv *priv = dev->data->dev_private;
2327 const struct rte_flow_item_gtp *spec = item->spec;
2328 const struct rte_flow_item_gtp *mask = item->mask;
2329 const struct rte_flow_item_gtp nic_mask = {
2330 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2332 .teid = RTE_BE32(0xffffffff),
2335 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "GTP support is not enabled");
2339 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2340 return rte_flow_error_set(error, ENOTSUP,
2341 RTE_FLOW_ERROR_TYPE_ITEM, item,
2342 "multiple tunnel layers not"
2344 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2345 return rte_flow_error_set(error, EINVAL,
2346 RTE_FLOW_ERROR_TYPE_ITEM, item,
2347 "no outer UDP layer found");
2349 mask = &rte_flow_item_gtp_mask;
2350 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ITEM, item,
2353 "Match is supported for GTP"
2355 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2356 (const uint8_t *)&nic_mask,
2357 sizeof(struct rte_flow_item_gtp),
2358 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2362 * Validate GTP PSC item.
2365 * Item specification.
2366 * @param[in] last_item
2367 * Previous validated item in the pattern items.
2368 * @param[in] gtp_item
2369 * Previous GTP item specification.
2371 * Pointer to flow attributes.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2381 const struct rte_flow_item *gtp_item,
2382 const struct rte_flow_attr *attr,
2383 struct rte_flow_error *error)
2385 const struct rte_flow_item_gtp *gtp_spec;
2386 const struct rte_flow_item_gtp *gtp_mask;
2387 const struct rte_flow_item_gtp_psc *mask;
2388 const struct rte_flow_item_gtp_psc nic_mask = {
2393 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2394 return rte_flow_error_set
2395 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2396 "GTP PSC item must be preceded with GTP item");
2397 gtp_spec = gtp_item->spec;
2398 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2399 /* GTP spec and E flag is requested to match zero. */
2401 (gtp_mask->v_pt_rsv_flags &
2402 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2403 return rte_flow_error_set
2404 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2405 "GTP E flag must be 1 to match GTP PSC");
2406 /* Check the flow is not created in group zero. */
2407 if (!attr->transfer && !attr->group)
2408 return rte_flow_error_set
2409 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2410 "GTP PSC is not supported for group 0");
2411 /* GTP spec is here and E flag is requested to match zero. */
2414 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2415 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2416 (const uint8_t *)&nic_mask,
2417 sizeof(struct rte_flow_item_gtp_psc),
2418 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2422 * Validate IPV4 item.
2423 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2424 * add specific validation of fragment_offset field,
2427 * Item specification.
2428 * @param[in] item_flags
2429 * Bit-fields that holds the items detected until now.
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2438 const struct rte_flow_item *item,
2439 uint64_t item_flags, uint64_t last_item,
2440 uint16_t ether_type, struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 const struct rte_flow_item_ipv4 *spec = item->spec;
2445 const struct rte_flow_item_ipv4 *last = item->last;
2446 const struct rte_flow_item_ipv4 *mask = item->mask;
2447 rte_be16_t fragment_offset_spec = 0;
2448 rte_be16_t fragment_offset_last = 0;
2449 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2451 .src_addr = RTE_BE32(0xffffffff),
2452 .dst_addr = RTE_BE32(0xffffffff),
2453 .type_of_service = 0xff,
2454 .fragment_offset = RTE_BE16(0xffff),
2455 .next_proto_id = 0xff,
2456 .time_to_live = 0xff,
2460 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2461 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2462 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2463 priv->config.hca_attr.inner_ipv4_ihl;
2465 return rte_flow_error_set(error, ENOTSUP,
2466 RTE_FLOW_ERROR_TYPE_ITEM,
2468 "IPV4 ihl offload not supported");
2469 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2471 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2472 ether_type, &nic_ipv4_mask,
2473 MLX5_ITEM_RANGE_ACCEPTED, error);
2477 fragment_offset_spec = spec->hdr.fragment_offset &
2478 mask->hdr.fragment_offset;
2479 if (!fragment_offset_spec)
2482 * spec and mask are valid, enforce using full mask to make sure the
2483 * complete value is used correctly.
2485 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2486 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2487 return rte_flow_error_set(error, EINVAL,
2488 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2489 item, "must use full mask for"
2490 " fragment_offset");
2492 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2493 * indicating this is 1st fragment of fragmented packet.
2494 * This is not yet supported in MLX5, return appropriate error message.
2496 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2497 return rte_flow_error_set(error, ENOTSUP,
2498 RTE_FLOW_ERROR_TYPE_ITEM, item,
2499 "match on first fragment not "
2501 if (fragment_offset_spec && !last)
2502 return rte_flow_error_set(error, ENOTSUP,
2503 RTE_FLOW_ERROR_TYPE_ITEM, item,
2504 "specified value not supported");
2505 /* spec and last are valid, validate the specified range. */
2506 fragment_offset_last = last->hdr.fragment_offset &
2507 mask->hdr.fragment_offset;
2509 * Match on fragment_offset spec 0x2001 and last 0x3fff
2510 * means MF is 1 and frag-offset is > 0.
2511 * This packet is fragment 2nd and onward, excluding last.
2512 * This is not yet supported in MLX5, return appropriate
2515 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2516 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519 last, "match on following "
2520 "fragments not supported");
2522 * Match on fragment_offset spec 0x0001 and last 0x1fff
2523 * means MF is 0 and frag-offset is > 0.
2524 * This packet is last fragment of fragmented packet.
2525 * This is not yet supported in MLX5, return appropriate
2528 if (fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532 last, "match on last "
2533 "fragment not supported");
2535 * Match on fragment_offset spec 0x0001 and last 0x3fff
2536 * means MF and/or frag-offset is not 0.
2537 * This is a fragmented packet.
2538 * Other range values are invalid and rejected.
2540 if (!(fragment_offset_spec == RTE_BE16(1) &&
2541 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2542 return rte_flow_error_set(error, ENOTSUP,
2543 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2544 "specified range not supported");
2549 * Validate IPV6 fragment extension item.
2552 * Item specification.
2553 * @param[in] item_flags
2554 * Bit-fields that holds the items detected until now.
2556 * Pointer to error structure.
2559 * 0 on success, a negative errno value otherwise and rte_errno is set.
2562 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2563 uint64_t item_flags,
2564 struct rte_flow_error *error)
2566 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2567 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2568 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2569 rte_be16_t frag_data_spec = 0;
2570 rte_be16_t frag_data_last = 0;
2571 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2572 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2573 MLX5_FLOW_LAYER_OUTER_L4;
2575 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2577 .next_header = 0xff,
2578 .frag_data = RTE_BE16(0xffff),
2582 if (item_flags & l4m)
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item cannot "
2587 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2588 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM, item,
2591 "ipv6 fragment extension item must "
2592 "follow ipv6 item");
2594 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2595 if (!frag_data_spec)
2598 * spec and mask are valid, enforce using full mask to make sure the
2599 * complete value is used correctly.
2601 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2602 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2605 item, "must use full mask for"
2608 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2609 * This is 1st fragment of fragmented packet.
2611 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2612 return rte_flow_error_set(error, ENOTSUP,
2613 RTE_FLOW_ERROR_TYPE_ITEM, item,
2614 "match on first fragment not "
2616 if (frag_data_spec && !last)
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ITEM, item,
2619 "specified value not supported");
2620 ret = mlx5_flow_item_acceptable
2621 (item, (const uint8_t *)mask,
2622 (const uint8_t *)&nic_mask,
2623 sizeof(struct rte_flow_item_ipv6_frag_ext),
2624 MLX5_ITEM_RANGE_ACCEPTED, error);
2627 /* spec and last are valid, validate the specified range. */
2628 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2630 * Match on frag_data spec 0x0009 and last 0xfff9
2631 * means M is 1 and frag-offset is > 0.
2632 * This packet is fragment 2nd and onward, excluding last.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2637 RTE_IPV6_EHDR_MF_MASK) &&
2638 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2639 return rte_flow_error_set(error, ENOTSUP,
2640 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2641 last, "match on following "
2642 "fragments not supported");
2644 * Match on frag_data spec 0x0008 and last 0xfff8
2645 * means M is 0 and frag-offset is > 0.
2646 * This packet is last fragment of fragmented packet.
2647 * This is not yet supported in MLX5, return appropriate
2650 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2651 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2652 return rte_flow_error_set(error, ENOTSUP,
2653 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2654 last, "match on last "
2655 "fragment not supported");
2656 /* Other range values are invalid and rejected. */
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2659 "specified range not supported");
2663 * Validate ASO CT item.
2666 * Pointer to the rte_eth_dev structure.
2668 * Item specification.
2669 * @param[in] item_flags
2670 * Pointer to bit-fields that holds the items detected until now.
2672 * Pointer to error structure.
2675 * 0 on success, a negative errno value otherwise and rte_errno is set.
2678 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2679 const struct rte_flow_item *item,
2680 uint64_t *item_flags,
2681 struct rte_flow_error *error)
2683 const struct rte_flow_item_conntrack *spec = item->spec;
2684 const struct rte_flow_item_conntrack *mask = item->mask;
2688 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2691 "Only one CT is supported");
2693 mask = &rte_flow_item_conntrack_mask;
2694 flags = spec->flags & mask->flags;
2695 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2696 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2697 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2698 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2701 "Conflict status bits");
2702 /* State change also needs to be considered. */
2703 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2708 * Validate the pop VLAN action.
2711 * Pointer to the rte_eth_dev structure.
2712 * @param[in] action_flags
2713 * Holds the actions detected until now.
2715 * Pointer to the pop vlan action.
2716 * @param[in] item_flags
2717 * The items found in this flow rule.
2719 * Pointer to flow attributes.
2721 * Pointer to error structure.
2724 * 0 on success, a negative errno value otherwise and rte_errno is set.
2727 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2728 uint64_t action_flags,
2729 const struct rte_flow_action *action,
2730 uint64_t item_flags,
2731 const struct rte_flow_attr *attr,
2732 struct rte_flow_error *error)
2734 const struct mlx5_priv *priv = dev->data->dev_private;
2735 struct mlx5_dev_ctx_shared *sh = priv->sh;
2736 bool direction_error = false;
2738 if (!priv->sh->pop_vlan_action)
2739 return rte_flow_error_set(error, ENOTSUP,
2740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2742 "pop vlan action is not supported");
2743 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2744 if (attr->transfer) {
2745 bool fdb_tx = priv->representor_id != UINT16_MAX;
2746 bool is_cx5 = sh->steering_format_version ==
2747 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2749 if (fdb_tx && is_cx5)
2750 direction_error = true;
2751 } else if (attr->egress) {
2752 direction_error = true;
2754 if (direction_error)
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2758 "pop vlan action not supported for egress");
2759 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2760 return rte_flow_error_set(error, ENOTSUP,
2761 RTE_FLOW_ERROR_TYPE_ACTION, action,
2762 "no support for multiple VLAN "
2764 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2765 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2766 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2767 return rte_flow_error_set(error, ENOTSUP,
2768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2770 "cannot pop vlan after decap without "
2771 "match on inner vlan in the flow");
2772 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2773 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2774 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2775 return rte_flow_error_set(error, ENOTSUP,
2776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2778 "cannot pop vlan without a "
2779 "match on (outer) vlan in the flow");
2780 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION, action,
2783 "wrong action order, port_id should "
2784 "be after pop VLAN action");
2785 if (!attr->transfer && priv->representor)
2786 return rte_flow_error_set(error, ENOTSUP,
2787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2788 "pop vlan action for VF representor "
2789 "not supported on NIC table");
2794 * Get VLAN default info from vlan match info.
2797 * the list of item specifications.
2799 * pointer VLAN info to fill to.
2802 * 0 on success, a negative errno value otherwise and rte_errno is set.
2805 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2806 struct rte_vlan_hdr *vlan)
2808 const struct rte_flow_item_vlan nic_mask = {
2809 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2810 MLX5DV_FLOW_VLAN_VID_MASK),
2811 .inner_type = RTE_BE16(0xffff),
2816 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2817 int type = items->type;
2819 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2820 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2823 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2824 const struct rte_flow_item_vlan *vlan_m = items->mask;
2825 const struct rte_flow_item_vlan *vlan_v = items->spec;
2827 /* If VLAN item in pattern doesn't contain data, return here. */
2832 /* Only full match values are accepted */
2833 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2834 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2835 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2837 rte_be_to_cpu_16(vlan_v->tci &
2838 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2840 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2841 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2842 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2844 rte_be_to_cpu_16(vlan_v->tci &
2845 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2847 if (vlan_m->inner_type == nic_mask.inner_type)
2848 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2849 vlan_m->inner_type);
2854 * Validate the push VLAN action.
2857 * Pointer to the rte_eth_dev structure.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] item_flags
2861 * The items found in this flow rule.
2863 * Pointer to the action structure.
2865 * Pointer to flow attributes
2867 * Pointer to error structure.
2870 * 0 on success, a negative errno value otherwise and rte_errno is set.
2873 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2874 uint64_t action_flags,
2875 const struct rte_flow_item_vlan *vlan_m,
2876 const struct rte_flow_action *action,
2877 const struct rte_flow_attr *attr,
2878 struct rte_flow_error *error)
2880 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2881 const struct mlx5_priv *priv = dev->data->dev_private;
2882 struct mlx5_dev_ctx_shared *sh = priv->sh;
2883 bool direction_error = false;
2885 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2886 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, action,
2889 "invalid vlan ethertype");
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after push VLAN");
2895 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2896 if (attr->transfer) {
2897 bool fdb_tx = priv->representor_id != UINT16_MAX;
2898 bool is_cx5 = sh->steering_format_version ==
2899 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2901 if (!fdb_tx && is_cx5)
2902 direction_error = true;
2903 } else if (attr->ingress) {
2904 direction_error = true;
2906 if (direction_error)
2907 return rte_flow_error_set(error, ENOTSUP,
2908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2910 "push vlan action not supported for ingress");
2911 if (!attr->transfer && priv->representor)
2912 return rte_flow_error_set(error, ENOTSUP,
2913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914 "push vlan action for VF representor "
2915 "not supported on NIC table");
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2919 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2920 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2921 !(mlx5_flow_find_action
2922 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2923 return rte_flow_error_set(error, EINVAL,
2924 RTE_FLOW_ERROR_TYPE_ACTION, action,
2925 "not full match mask on VLAN PCP and "
2926 "there is no of_set_vlan_pcp action, "
2927 "push VLAN action cannot figure out "
2930 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2931 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2932 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2933 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2934 !(mlx5_flow_find_action
2935 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2936 return rte_flow_error_set(error, EINVAL,
2937 RTE_FLOW_ERROR_TYPE_ACTION, action,
2938 "not full match mask on VLAN VID and "
2939 "there is no of_set_vlan_vid action, "
2940 "push VLAN action cannot figure out "
2947 * Validate the set VLAN PCP.
2949 * @param[in] action_flags
2950 * Holds the actions detected until now.
2951 * @param[in] actions
2952 * Pointer to the list of actions remaining in the flow rule.
2954 * Pointer to error structure.
2957 * 0 on success, a negative errno value otherwise and rte_errno is set.
2960 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2961 const struct rte_flow_action actions[],
2962 struct rte_flow_error *error)
2964 const struct rte_flow_action *action = actions;
2965 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2967 if (conf->vlan_pcp > 7)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "VLAN PCP value is too big");
2971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2972 return rte_flow_error_set(error, ENOTSUP,
2973 RTE_FLOW_ERROR_TYPE_ACTION, action,
2974 "set VLAN PCP action must follow "
2975 "the push VLAN action");
2976 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2977 return rte_flow_error_set(error, ENOTSUP,
2978 RTE_FLOW_ERROR_TYPE_ACTION, action,
2979 "Multiple VLAN PCP modification are "
2981 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2982 return rte_flow_error_set(error, EINVAL,
2983 RTE_FLOW_ERROR_TYPE_ACTION, action,
2984 "wrong action order, port_id should "
2985 "be after set VLAN PCP");
2990 * Validate the set VLAN VID.
2992 * @param[in] item_flags
2993 * Holds the items detected in this rule.
2994 * @param[in] action_flags
2995 * Holds the actions detected until now.
2996 * @param[in] actions
2997 * Pointer to the list of actions remaining in the flow rule.
2999 * Pointer to error structure.
3002 * 0 on success, a negative errno value otherwise and rte_errno is set.
3005 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3006 uint64_t action_flags,
3007 const struct rte_flow_action actions[],
3008 struct rte_flow_error *error)
3010 const struct rte_flow_action *action = actions;
3011 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3013 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION, action,
3016 "VLAN VID value is too big");
3017 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3018 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3019 return rte_flow_error_set(error, ENOTSUP,
3020 RTE_FLOW_ERROR_TYPE_ACTION, action,
3021 "set VLAN VID action must follow push"
3022 " VLAN action or match on VLAN item");
3023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3024 return rte_flow_error_set(error, ENOTSUP,
3025 RTE_FLOW_ERROR_TYPE_ACTION, action,
3026 "Multiple VLAN VID modifications are "
3028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3029 return rte_flow_error_set(error, EINVAL,
3030 RTE_FLOW_ERROR_TYPE_ACTION, action,
3031 "wrong action order, port_id should "
3032 "be after set VLAN VID");
3037 * Validate the FLAG action.
3040 * Pointer to the rte_eth_dev structure.
3041 * @param[in] action_flags
3042 * Holds the actions detected until now.
3044 * Pointer to flow attributes
3046 * Pointer to error structure.
3049 * 0 on success, a negative errno value otherwise and rte_errno is set.
3052 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3053 uint64_t action_flags,
3054 const struct rte_flow_attr *attr,
3055 struct rte_flow_error *error)
3057 struct mlx5_priv *priv = dev->data->dev_private;
3058 struct mlx5_dev_config *config = &priv->config;
3061 /* Fall back if no extended metadata register support. */
3062 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3063 return mlx5_flow_validate_action_flag(action_flags, attr,
3065 /* Extensive metadata mode requires registers. */
3066 if (!mlx5_flow_ext_mreg_supported(dev))
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "no metadata registers "
3070 "to support flag action");
3071 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3072 return rte_flow_error_set(error, ENOTSUP,
3073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 "extended metadata register"
3075 " isn't available");
3076 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3079 MLX5_ASSERT(ret > 0);
3080 if (action_flags & MLX5_FLOW_ACTION_MARK)
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3083 "can't mark and flag in same flow");
3084 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3088 " actions in same flow");
3093 * Validate MARK action.
3096 * Pointer to the rte_eth_dev structure.
3098 * Pointer to action.
3099 * @param[in] action_flags
3100 * Holds the actions detected until now.
3102 * Pointer to flow attributes
3104 * Pointer to error structure.
3107 * 0 on success, a negative errno value otherwise and rte_errno is set.
3110 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3111 const struct rte_flow_action *action,
3112 uint64_t action_flags,
3113 const struct rte_flow_attr *attr,
3114 struct rte_flow_error *error)
3116 struct mlx5_priv *priv = dev->data->dev_private;
3117 struct mlx5_dev_config *config = &priv->config;
3118 const struct rte_flow_action_mark *mark = action->conf;
3121 if (is_tunnel_offload_active(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "if tunnel offload active");
3126 /* Fall back if no extended metadata register support. */
3127 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3128 return mlx5_flow_validate_action_mark(action, action_flags,
3130 /* Extensive metadata mode requires registers. */
3131 if (!mlx5_flow_ext_mreg_supported(dev))
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3134 "no metadata registers "
3135 "to support mark action");
3136 if (!priv->sh->dv_mark_mask)
3137 return rte_flow_error_set(error, ENOTSUP,
3138 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3139 "extended metadata register"
3140 " isn't available");
3141 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3144 MLX5_ASSERT(ret > 0);
3146 return rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION, action,
3148 "configuration cannot be null");
3149 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3150 return rte_flow_error_set(error, EINVAL,
3151 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3153 "mark id exceeds the limit");
3154 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "can't flag and mark in same flow");
3158 if (action_flags & MLX5_FLOW_ACTION_MARK)
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3161 "can't have 2 mark actions in same"
3167 * Validate SET_META action.
3170 * Pointer to the rte_eth_dev structure.
3172 * Pointer to the action structure.
3173 * @param[in] action_flags
3174 * Holds the actions detected until now.
3176 * Pointer to flow attributes
3178 * Pointer to error structure.
3181 * 0 on success, a negative errno value otherwise and rte_errno is set.
3184 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3185 const struct rte_flow_action *action,
3186 uint64_t action_flags __rte_unused,
3187 const struct rte_flow_attr *attr,
3188 struct rte_flow_error *error)
3190 struct mlx5_priv *priv = dev->data->dev_private;
3191 struct mlx5_dev_config *config = &priv->config;
3192 const struct rte_flow_action_set_meta *conf;
3193 uint32_t nic_mask = UINT32_MAX;
3196 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3197 !mlx5_flow_ext_mreg_supported(dev))
3198 return rte_flow_error_set(error, ENOTSUP,
3199 RTE_FLOW_ERROR_TYPE_ACTION, action,
3200 "extended metadata register"
3201 " isn't supported");
3202 reg = flow_dv_get_metadata_reg(dev, attr, error);
3206 return rte_flow_error_set(error, ENOTSUP,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "unavalable extended metadata register");
3209 if (reg != REG_A && reg != REG_B) {
3210 struct mlx5_priv *priv = dev->data->dev_private;
3212 nic_mask = priv->sh->dv_meta_mask;
3214 if (!(action->conf))
3215 return rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ACTION, action,
3217 "configuration cannot be null");
3218 conf = (const struct rte_flow_action_set_meta *)action->conf;
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION, action,
3222 "zero mask doesn't have any effect");
3223 if (conf->mask & ~nic_mask)
3224 return rte_flow_error_set(error, EINVAL,
3225 RTE_FLOW_ERROR_TYPE_ACTION, action,
3226 "meta data must be within reg C0");
3231 * Validate SET_TAG action.
3234 * Pointer to the rte_eth_dev structure.
3236 * Pointer to the action structure.
3237 * @param[in] action_flags
3238 * Holds the actions detected until now.
3240 * Pointer to flow attributes
3242 * Pointer to error structure.
3245 * 0 on success, a negative errno value otherwise and rte_errno is set.
3248 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3249 const struct rte_flow_action *action,
3250 uint64_t action_flags,
3251 const struct rte_flow_attr *attr,
3252 struct rte_flow_error *error)
3254 const struct rte_flow_action_set_tag *conf;
3255 const uint64_t terminal_action_flags =
3256 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3257 MLX5_FLOW_ACTION_RSS;
3260 if (!mlx5_flow_ext_mreg_supported(dev))
3261 return rte_flow_error_set(error, ENOTSUP,
3262 RTE_FLOW_ERROR_TYPE_ACTION, action,
3263 "extensive metadata register"
3264 " isn't supported");
3265 if (!(action->conf))
3266 return rte_flow_error_set(error, EINVAL,
3267 RTE_FLOW_ERROR_TYPE_ACTION, action,
3268 "configuration cannot be null");
3269 conf = (const struct rte_flow_action_set_tag *)action->conf;
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION, action,
3273 "zero mask doesn't have any effect");
3274 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3277 if (!attr->transfer && attr->ingress &&
3278 (action_flags & terminal_action_flags))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, action,
3281 "set_tag has no effect"
3282 " with terminal actions");
3287 * Validate count action.
3290 * Pointer to rte_eth_dev structure.
3292 * Indicator if action is shared.
3293 * @param[in] action_flags
3294 * Holds the actions detected until now.
3296 * Pointer to error structure.
3299 * 0 on success, a negative errno value otherwise and rte_errno is set.
3302 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3303 uint64_t action_flags,
3304 struct rte_flow_error *error)
3306 struct mlx5_priv *priv = dev->data->dev_private;
3308 if (!priv->sh->devx)
3310 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3313 "duplicate count actions set");
3314 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3315 !priv->sh->flow_hit_aso_en)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3318 "old age and shared count combination is not supported");
3319 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3323 return rte_flow_error_set
3325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3327 "count action not supported");
3331 * Validate the L2 encap action.
3334 * Pointer to the rte_eth_dev structure.
3335 * @param[in] action_flags
3336 * Holds the actions detected until now.
3338 * Pointer to the action structure.
3340 * Pointer to flow attributes.
3342 * Pointer to error structure.
3345 * 0 on success, a negative errno value otherwise and rte_errno is set.
3348 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3349 uint64_t action_flags,
3350 const struct rte_flow_action *action,
3351 const struct rte_flow_attr *attr,
3352 struct rte_flow_error *error)
3354 const struct mlx5_priv *priv = dev->data->dev_private;
3356 if (!(action->conf))
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION, action,
3359 "configuration cannot be null");
3360 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3363 "can only have a single encap action "
3365 if (!attr->transfer && priv->representor)
3366 return rte_flow_error_set(error, ENOTSUP,
3367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368 "encap action for VF representor "
3369 "not supported on NIC table");
3374 * Validate a decap action.
3377 * Pointer to the rte_eth_dev structure.
3378 * @param[in] action_flags
3379 * Holds the actions detected until now.
3381 * Pointer to the action structure.
3382 * @param[in] item_flags
3383 * Holds the items detected.
3385 * Pointer to flow attributes
3387 * Pointer to error structure.
3390 * 0 on success, a negative errno value otherwise and rte_errno is set.
3393 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3394 uint64_t action_flags,
3395 const struct rte_flow_action *action,
3396 const uint64_t item_flags,
3397 const struct rte_flow_attr *attr,
3398 struct rte_flow_error *error)
3400 const struct mlx5_priv *priv = dev->data->dev_private;
3402 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3403 !priv->config.decap_en)
3404 return rte_flow_error_set(error, ENOTSUP,
3405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3406 "decap is not enabled");
3407 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3411 MLX5_FLOW_ACTION_DECAP ? "can only "
3412 "have a single decap action" : "decap "
3413 "after encap is not supported");
3414 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3415 return rte_flow_error_set(error, EINVAL,
3416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3417 "can't have decap action after"
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3423 "decap action not supported for "
3425 if (!attr->transfer && priv->representor)
3426 return rte_flow_error_set(error, ENOTSUP,
3427 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3428 "decap action for VF representor "
3429 "not supported on NIC table");
3430 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3431 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3432 return rte_flow_error_set(error, ENOTSUP,
3433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3434 "VXLAN item should be present for VXLAN decap");
3438 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3441 * Validate the raw encap and decap actions.
3444 * Pointer to the rte_eth_dev structure.
3446 * Pointer to the decap action.
3448 * Pointer to the encap action.
3450 * Pointer to flow attributes
3451 * @param[in/out] action_flags
3452 * Holds the actions detected until now.
3453 * @param[out] actions_n
3454 * pointer to the number of actions counter.
3456 * Pointer to the action structure.
3457 * @param[in] item_flags
3458 * Holds the items detected.
3460 * Pointer to error structure.
3463 * 0 on success, a negative errno value otherwise and rte_errno is set.
3466 flow_dv_validate_action_raw_encap_decap
3467 (struct rte_eth_dev *dev,
3468 const struct rte_flow_action_raw_decap *decap,
3469 const struct rte_flow_action_raw_encap *encap,
3470 const struct rte_flow_attr *attr, uint64_t *action_flags,
3471 int *actions_n, const struct rte_flow_action *action,
3472 uint64_t item_flags, struct rte_flow_error *error)
3474 const struct mlx5_priv *priv = dev->data->dev_private;
3477 if (encap && (!encap->size || !encap->data))
3478 return rte_flow_error_set(error, EINVAL,
3479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3480 "raw encap data cannot be empty");
3481 if (decap && encap) {
3482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3486 else if (encap->size <=
3487 MLX5_ENCAPSULATION_DECISION_SIZE &&
3489 MLX5_ENCAPSULATION_DECISION_SIZE)
3492 else if (encap->size >
3493 MLX5_ENCAPSULATION_DECISION_SIZE &&
3495 MLX5_ENCAPSULATION_DECISION_SIZE)
3496 /* 2 L2 actions: encap and decap. */
3499 return rte_flow_error_set(error,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "unsupported too small "
3503 "raw decap and too small raw "
3504 "encap combination");
3507 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3508 item_flags, attr, error);
3511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3516 return rte_flow_error_set(error, ENOTSUP,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3519 "small raw encap size");
3520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3521 return rte_flow_error_set(error, EINVAL,
3522 RTE_FLOW_ERROR_TYPE_ACTION,
3524 "more than one encap action");
3525 if (!attr->transfer && priv->representor)
3526 return rte_flow_error_set
3528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3529 "encap action for VF representor "
3530 "not supported on NIC table");
3531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3538 * Validate the ASO CT action.
3541 * Pointer to the rte_eth_dev structure.
3542 * @param[in] action_flags
3543 * Holds the actions detected until now.
3544 * @param[in] item_flags
3545 * The items found in this flow rule.
3547 * Pointer to flow attributes.
3549 * Pointer to error structure.
3552 * 0 on success, a negative errno value otherwise and rte_errno is set.
3555 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3556 uint64_t action_flags,
3557 uint64_t item_flags,
3558 const struct rte_flow_attr *attr,
3559 struct rte_flow_error *error)
3563 if (attr->group == 0 && !attr->transfer)
3564 return rte_flow_error_set(error, ENOTSUP,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3567 "Only support non-root table");
3568 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3569 return rte_flow_error_set(error, ENOTSUP,
3570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3571 "CT cannot follow a fate action");
3572 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3573 (action_flags & MLX5_FLOW_ACTION_AGE))
3574 return rte_flow_error_set(error, EINVAL,
3575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3576 "Only one ASO action is supported");
3577 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3578 return rte_flow_error_set(error, EINVAL,
3579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3580 "Encap cannot exist before CT");
3581 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3584 "Not a outer TCP packet");
3589 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3590 struct mlx5_list_entry *entry, void *cb_ctx)
3592 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3593 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3594 struct mlx5_flow_dv_encap_decap_resource *resource;
3596 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3598 if (resource->reformat_type == ctx_resource->reformat_type &&
3599 resource->ft_type == ctx_resource->ft_type &&
3600 resource->flags == ctx_resource->flags &&
3601 resource->size == ctx_resource->size &&
3602 !memcmp((const void *)resource->buf,
3603 (const void *)ctx_resource->buf,
3609 struct mlx5_list_entry *
3610 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3612 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3613 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3614 struct mlx5dv_dr_domain *domain;
3615 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3616 struct mlx5_flow_dv_encap_decap_resource *resource;
3620 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621 domain = sh->fdb_domain;
3622 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3623 domain = sh->rx_domain;
3625 domain = sh->tx_domain;
3626 /* Register new encap/decap resource. */
3627 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3629 rte_flow_error_set(ctx->error, ENOMEM,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3631 "cannot allocate resource memory");
3634 *resource = *ctx_resource;
3635 resource->idx = idx;
3636 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3640 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3641 rte_flow_error_set(ctx->error, ENOMEM,
3642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3643 NULL, "cannot create action");
3647 return &resource->entry;
3650 struct mlx5_list_entry *
3651 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3654 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3655 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3656 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3659 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3661 if (!cache_resource) {
3662 rte_flow_error_set(ctx->error, ENOMEM,
3663 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3664 "cannot allocate resource memory");
3667 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3668 cache_resource->idx = idx;
3669 return &cache_resource->entry;
3673 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3675 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3676 struct mlx5_flow_dv_encap_decap_resource *res =
3677 container_of(entry, typeof(*res), entry);
3679 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3683 * Find existing encap/decap resource or create and register a new one.
3685 * @param[in, out] dev
3686 * Pointer to rte_eth_dev structure.
3687 * @param[in, out] resource
3688 * Pointer to encap/decap resource.
3689 * @parm[in, out] dev_flow
3690 * Pointer to the dev_flow.
3692 * pointer to error structure.
3695 * 0 on success otherwise -errno and errno is set.
3698 flow_dv_encap_decap_resource_register
3699 (struct rte_eth_dev *dev,
3700 struct mlx5_flow_dv_encap_decap_resource *resource,
3701 struct mlx5_flow *dev_flow,
3702 struct rte_flow_error *error)
3704 struct mlx5_priv *priv = dev->data->dev_private;
3705 struct mlx5_dev_ctx_shared *sh = priv->sh;
3706 struct mlx5_list_entry *entry;
3710 uint32_t refmt_type:8;
3712 * Header reformat actions can be shared between
3713 * non-root tables. One bit to indicate non-root
3717 uint32_t reserve:15;
3720 } encap_decap_key = {
3722 .ft_type = resource->ft_type,
3723 .refmt_type = resource->reformat_type,
3724 .is_root = !!dev_flow->dv.group,
3728 struct mlx5_flow_cb_ctx ctx = {
3732 struct mlx5_hlist *encaps_decaps;
3735 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3737 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3739 flow_dv_encap_decap_create_cb,
3740 flow_dv_encap_decap_match_cb,
3741 flow_dv_encap_decap_remove_cb,
3742 flow_dv_encap_decap_clone_cb,
3743 flow_dv_encap_decap_clone_free_cb);
3744 if (unlikely(!encaps_decaps))
3746 resource->flags = dev_flow->dv.group ? 0 : 1;
3747 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3748 sizeof(encap_decap_key.v32), 0);
3749 if (resource->reformat_type !=
3750 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3752 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3753 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3756 resource = container_of(entry, typeof(*resource), entry);
3757 dev_flow->dv.encap_decap = resource;
3758 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3763 * Find existing table jump resource or create and register a new one.
3765 * @param[in, out] dev
3766 * Pointer to rte_eth_dev structure.
3767 * @param[in, out] tbl
3768 * Pointer to flow table resource.
3769 * @parm[in, out] dev_flow
3770 * Pointer to the dev_flow.
3772 * pointer to error structure.
3775 * 0 on success otherwise -errno and errno is set.
3778 flow_dv_jump_tbl_resource_register
3779 (struct rte_eth_dev *dev __rte_unused,
3780 struct mlx5_flow_tbl_resource *tbl,
3781 struct mlx5_flow *dev_flow,
3782 struct rte_flow_error *error __rte_unused)
3784 struct mlx5_flow_tbl_data_entry *tbl_data =
3785 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3788 MLX5_ASSERT(tbl_data->jump.action);
3789 dev_flow->handle->rix_jump = tbl_data->idx;
3790 dev_flow->dv.jump = &tbl_data->jump;
3795 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3796 struct mlx5_list_entry *entry, void *cb_ctx)
3798 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3799 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3800 struct mlx5_flow_dv_port_id_action_resource *res =
3801 container_of(entry, typeof(*res), entry);
3803 return ref->port_id != res->port_id;
3806 struct mlx5_list_entry *
3807 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3809 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3810 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3811 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3812 struct mlx5_flow_dv_port_id_action_resource *resource;
3816 /* Register new port id action resource. */
3817 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3819 rte_flow_error_set(ctx->error, ENOMEM,
3820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3821 "cannot allocate port_id action memory");
3825 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3829 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3830 rte_flow_error_set(ctx->error, ENOMEM,
3831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3832 "cannot create action");
3835 resource->idx = idx;
3836 return &resource->entry;
3839 struct mlx5_list_entry *
3840 flow_dv_port_id_clone_cb(void *tool_ctx,
3841 struct mlx5_list_entry *entry __rte_unused,
3844 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3845 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3846 struct mlx5_flow_dv_port_id_action_resource *resource;
3849 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3851 rte_flow_error_set(ctx->error, ENOMEM,
3852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3853 "cannot allocate port_id action memory");
3856 memcpy(resource, entry, sizeof(*resource));
3857 resource->idx = idx;
3858 return &resource->entry;
3862 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3864 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3865 struct mlx5_flow_dv_port_id_action_resource *resource =
3866 container_of(entry, typeof(*resource), entry);
3868 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3872 * Find existing table port ID resource or create and register a new one.
3874 * @param[in, out] dev
3875 * Pointer to rte_eth_dev structure.
3876 * @param[in, out] ref
3877 * Pointer to port ID action resource reference.
3878 * @parm[in, out] dev_flow
3879 * Pointer to the dev_flow.
3881 * pointer to error structure.
3884 * 0 on success otherwise -errno and errno is set.
3887 flow_dv_port_id_action_resource_register
3888 (struct rte_eth_dev *dev,
3889 struct mlx5_flow_dv_port_id_action_resource *ref,
3890 struct mlx5_flow *dev_flow,
3891 struct rte_flow_error *error)
3893 struct mlx5_priv *priv = dev->data->dev_private;
3894 struct mlx5_list_entry *entry;
3895 struct mlx5_flow_dv_port_id_action_resource *resource;
3896 struct mlx5_flow_cb_ctx ctx = {
3901 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3904 resource = container_of(entry, typeof(*resource), entry);
3905 dev_flow->dv.port_id_action = resource;
3906 dev_flow->handle->rix_port_id_action = resource->idx;
3911 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3912 struct mlx5_list_entry *entry, void *cb_ctx)
3914 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3915 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3916 struct mlx5_flow_dv_push_vlan_action_resource *res =
3917 container_of(entry, typeof(*res), entry);
3919 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3922 struct mlx5_list_entry *
3923 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3925 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3926 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3927 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3928 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3929 struct mlx5dv_dr_domain *domain;
3933 /* Register new port id action resource. */
3934 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3936 rte_flow_error_set(ctx->error, ENOMEM,
3937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3938 "cannot allocate push_vlan action memory");
3942 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3943 domain = sh->fdb_domain;
3944 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3945 domain = sh->rx_domain;
3947 domain = sh->tx_domain;
3948 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3951 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3952 rte_flow_error_set(ctx->error, ENOMEM,
3953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3954 "cannot create push vlan action");
3957 resource->idx = idx;
3958 return &resource->entry;
3961 struct mlx5_list_entry *
3962 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3963 struct mlx5_list_entry *entry __rte_unused,
3966 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3967 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3968 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3971 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3973 rte_flow_error_set(ctx->error, ENOMEM,
3974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3975 "cannot allocate push_vlan action memory");
3978 memcpy(resource, entry, sizeof(*resource));
3979 resource->idx = idx;
3980 return &resource->entry;
3984 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3986 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3987 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3988 container_of(entry, typeof(*resource), entry);
3990 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3994 * Find existing push vlan resource or create and register a new one.
3996 * @param [in, out] dev
3997 * Pointer to rte_eth_dev structure.
3998 * @param[in, out] ref
3999 * Pointer to port ID action resource reference.
4000 * @parm[in, out] dev_flow
4001 * Pointer to the dev_flow.
4003 * pointer to error structure.
4006 * 0 on success otherwise -errno and errno is set.
4009 flow_dv_push_vlan_action_resource_register
4010 (struct rte_eth_dev *dev,
4011 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4012 struct mlx5_flow *dev_flow,
4013 struct rte_flow_error *error)
4015 struct mlx5_priv *priv = dev->data->dev_private;
4016 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4017 struct mlx5_list_entry *entry;
4018 struct mlx5_flow_cb_ctx ctx = {
4023 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4026 resource = container_of(entry, typeof(*resource), entry);
4028 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4029 dev_flow->dv.push_vlan_res = resource;
4034 * Get the size of specific rte_flow_item_type hdr size
4036 * @param[in] item_type
4037 * Tested rte_flow_item_type.
4040 * sizeof struct item_type, 0 if void or irrelevant.
4043 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4047 switch (item_type) {
4048 case RTE_FLOW_ITEM_TYPE_ETH:
4049 retval = sizeof(struct rte_ether_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VLAN:
4052 retval = sizeof(struct rte_vlan_hdr);
4054 case RTE_FLOW_ITEM_TYPE_IPV4:
4055 retval = sizeof(struct rte_ipv4_hdr);
4057 case RTE_FLOW_ITEM_TYPE_IPV6:
4058 retval = sizeof(struct rte_ipv6_hdr);
4060 case RTE_FLOW_ITEM_TYPE_UDP:
4061 retval = sizeof(struct rte_udp_hdr);
4063 case RTE_FLOW_ITEM_TYPE_TCP:
4064 retval = sizeof(struct rte_tcp_hdr);
4066 case RTE_FLOW_ITEM_TYPE_VXLAN:
4067 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4068 retval = sizeof(struct rte_vxlan_hdr);
4070 case RTE_FLOW_ITEM_TYPE_GRE:
4071 case RTE_FLOW_ITEM_TYPE_NVGRE:
4072 retval = sizeof(struct rte_gre_hdr);
4074 case RTE_FLOW_ITEM_TYPE_MPLS:
4075 retval = sizeof(struct rte_mpls_hdr);
4077 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4085 #define MLX5_ENCAP_IPV4_VERSION 0x40
4086 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4087 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4088 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4089 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4090 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4091 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4094 * Convert the encap action data from list of rte_flow_item to raw buffer
4097 * Pointer to rte_flow_item objects list.
4099 * Pointer to the output buffer.
4101 * Pointer to the output buffer size.
4103 * Pointer to the error structure.
4106 * 0 on success, a negative errno value otherwise and rte_errno is set.
4109 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4110 size_t *size, struct rte_flow_error *error)
4112 struct rte_ether_hdr *eth = NULL;
4113 struct rte_vlan_hdr *vlan = NULL;
4114 struct rte_ipv4_hdr *ipv4 = NULL;
4115 struct rte_ipv6_hdr *ipv6 = NULL;
4116 struct rte_udp_hdr *udp = NULL;
4117 struct rte_vxlan_hdr *vxlan = NULL;
4118 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4119 struct rte_gre_hdr *gre = NULL;
4121 size_t temp_size = 0;
4124 return rte_flow_error_set(error, EINVAL,
4125 RTE_FLOW_ERROR_TYPE_ACTION,
4126 NULL, "invalid empty data");
4127 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4128 len = flow_dv_get_item_hdr_len(items->type);
4129 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4130 return rte_flow_error_set(error, EINVAL,
4131 RTE_FLOW_ERROR_TYPE_ACTION,
4132 (void *)items->type,
4133 "items total size is too big"
4134 " for encap action");
4135 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4136 switch (items->type) {
4137 case RTE_FLOW_ITEM_TYPE_ETH:
4138 eth = (struct rte_ether_hdr *)&buf[temp_size];
4140 case RTE_FLOW_ITEM_TYPE_VLAN:
4141 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4143 return rte_flow_error_set(error, EINVAL,
4144 RTE_FLOW_ERROR_TYPE_ACTION,
4145 (void *)items->type,
4146 "eth header not found");
4147 if (!eth->ether_type)
4148 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4150 case RTE_FLOW_ITEM_TYPE_IPV4:
4151 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4153 return rte_flow_error_set(error, EINVAL,
4154 RTE_FLOW_ERROR_TYPE_ACTION,
4155 (void *)items->type,
4156 "neither eth nor vlan"
4158 if (vlan && !vlan->eth_proto)
4159 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4160 else if (eth && !eth->ether_type)
4161 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4162 if (!ipv4->version_ihl)
4163 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4164 MLX5_ENCAP_IPV4_IHL_MIN;
4165 if (!ipv4->time_to_live)
4166 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4168 case RTE_FLOW_ITEM_TYPE_IPV6:
4169 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4171 return rte_flow_error_set(error, EINVAL,
4172 RTE_FLOW_ERROR_TYPE_ACTION,
4173 (void *)items->type,
4174 "neither eth nor vlan"
4176 if (vlan && !vlan->eth_proto)
4177 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4178 else if (eth && !eth->ether_type)
4179 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4180 if (!ipv6->vtc_flow)
4182 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4183 if (!ipv6->hop_limits)
4184 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4186 case RTE_FLOW_ITEM_TYPE_UDP:
4187 udp = (struct rte_udp_hdr *)&buf[temp_size];
4189 return rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ACTION,
4191 (void *)items->type,
4192 "ip header not found");
4193 if (ipv4 && !ipv4->next_proto_id)
4194 ipv4->next_proto_id = IPPROTO_UDP;
4195 else if (ipv6 && !ipv6->proto)
4196 ipv6->proto = IPPROTO_UDP;
4198 case RTE_FLOW_ITEM_TYPE_VXLAN:
4199 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4201 return rte_flow_error_set(error, EINVAL,
4202 RTE_FLOW_ERROR_TYPE_ACTION,
4203 (void *)items->type,
4204 "udp header not found");
4206 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4207 if (!vxlan->vx_flags)
4209 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4211 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4212 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4214 return rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ACTION,
4216 (void *)items->type,
4217 "udp header not found");
4218 if (!vxlan_gpe->proto)
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4225 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4226 if (!vxlan_gpe->vx_flags)
4227 vxlan_gpe->vx_flags =
4228 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4230 case RTE_FLOW_ITEM_TYPE_GRE:
4231 case RTE_FLOW_ITEM_TYPE_NVGRE:
4232 gre = (struct rte_gre_hdr *)&buf[temp_size];
4234 return rte_flow_error_set(error, EINVAL,
4235 RTE_FLOW_ERROR_TYPE_ACTION,
4236 (void *)items->type,
4237 "next protocol not found");
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION,
4241 (void *)items->type,
4242 "ip header not found");
4243 if (ipv4 && !ipv4->next_proto_id)
4244 ipv4->next_proto_id = IPPROTO_GRE;
4245 else if (ipv6 && !ipv6->proto)
4246 ipv6->proto = IPPROTO_GRE;
4248 case RTE_FLOW_ITEM_TYPE_VOID:
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "unsupported item type");
4264 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4266 struct rte_ether_hdr *eth = NULL;
4267 struct rte_vlan_hdr *vlan = NULL;
4268 struct rte_ipv6_hdr *ipv6 = NULL;
4269 struct rte_udp_hdr *udp = NULL;
4273 eth = (struct rte_ether_hdr *)data;
4274 next_hdr = (char *)(eth + 1);
4275 proto = RTE_BE16(eth->ether_type);
4278 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4279 vlan = (struct rte_vlan_hdr *)next_hdr;
4280 proto = RTE_BE16(vlan->eth_proto);
4281 next_hdr += sizeof(struct rte_vlan_hdr);
4284 /* HW calculates IPv4 csum. no need to proceed */
4285 if (proto == RTE_ETHER_TYPE_IPV4)
4288 /* non IPv4/IPv6 header. not supported */
4289 if (proto != RTE_ETHER_TYPE_IPV6) {
4290 return rte_flow_error_set(error, ENOTSUP,
4291 RTE_FLOW_ERROR_TYPE_ACTION,
4292 NULL, "Cannot offload non IPv4/IPv6");
4295 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4297 /* ignore non UDP */
4298 if (ipv6->proto != IPPROTO_UDP)
4301 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4302 udp->dgram_cksum = 0;
4308 * Convert L2 encap action to DV specification.
4311 * Pointer to rte_eth_dev structure.
4313 * Pointer to action structure.
4314 * @param[in, out] dev_flow
4315 * Pointer to the mlx5_flow.
4316 * @param[in] transfer
4317 * Mark if the flow is E-Switch flow.
4319 * Pointer to the error structure.
4322 * 0 on success, a negative errno value otherwise and rte_errno is set.
4325 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4326 const struct rte_flow_action *action,
4327 struct mlx5_flow *dev_flow,
4329 struct rte_flow_error *error)
4331 const struct rte_flow_item *encap_data;
4332 const struct rte_flow_action_raw_encap *raw_encap_data;
4333 struct mlx5_flow_dv_encap_decap_resource res = {
4335 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4336 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4337 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4340 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4342 (const struct rte_flow_action_raw_encap *)action->conf;
4343 res.size = raw_encap_data->size;
4344 memcpy(res.buf, raw_encap_data->data, res.size);
4346 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4348 ((const struct rte_flow_action_vxlan_encap *)
4349 action->conf)->definition;
4352 ((const struct rte_flow_action_nvgre_encap *)
4353 action->conf)->definition;
4354 if (flow_dv_convert_encap_data(encap_data, res.buf,
4358 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4360 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4361 return rte_flow_error_set(error, EINVAL,
4362 RTE_FLOW_ERROR_TYPE_ACTION,
4363 NULL, "can't create L2 encap action");
4368 * Convert L2 decap action to DV specification.
4371 * Pointer to rte_eth_dev structure.
4372 * @param[in, out] dev_flow
4373 * Pointer to the mlx5_flow.
4374 * @param[in] transfer
4375 * Mark if the flow is E-Switch flow.
4377 * Pointer to the error structure.
4380 * 0 on success, a negative errno value otherwise and rte_errno is set.
4383 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4384 struct mlx5_flow *dev_flow,
4386 struct rte_flow_error *error)
4388 struct mlx5_flow_dv_encap_decap_resource res = {
4391 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4392 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4393 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4396 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4397 return rte_flow_error_set(error, EINVAL,
4398 RTE_FLOW_ERROR_TYPE_ACTION,
4399 NULL, "can't create L2 decap action");
4404 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4407 * Pointer to rte_eth_dev structure.
4409 * Pointer to action structure.
4410 * @param[in, out] dev_flow
4411 * Pointer to the mlx5_flow.
4413 * Pointer to the flow attributes.
4415 * Pointer to the error structure.
4418 * 0 on success, a negative errno value otherwise and rte_errno is set.
4421 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4422 const struct rte_flow_action *action,
4423 struct mlx5_flow *dev_flow,
4424 const struct rte_flow_attr *attr,
4425 struct rte_flow_error *error)
4427 const struct rte_flow_action_raw_encap *encap_data;
4428 struct mlx5_flow_dv_encap_decap_resource res;
4430 memset(&res, 0, sizeof(res));
4431 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4432 res.size = encap_data->size;
4433 memcpy(res.buf, encap_data->data, res.size);
4434 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4435 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4436 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4438 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4440 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4441 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4442 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4443 return rte_flow_error_set(error, EINVAL,
4444 RTE_FLOW_ERROR_TYPE_ACTION,
4445 NULL, "can't create encap action");
4450 * Create action push VLAN.
4453 * Pointer to rte_eth_dev structure.
4455 * Pointer to the flow attributes.
4457 * Pointer to the vlan to push to the Ethernet header.
4458 * @param[in, out] dev_flow
4459 * Pointer to the mlx5_flow.
4461 * Pointer to the error structure.
4464 * 0 on success, a negative errno value otherwise and rte_errno is set.
4467 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4468 const struct rte_flow_attr *attr,
4469 const struct rte_vlan_hdr *vlan,
4470 struct mlx5_flow *dev_flow,
4471 struct rte_flow_error *error)
4473 struct mlx5_flow_dv_push_vlan_action_resource res;
4475 memset(&res, 0, sizeof(res));
4477 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4480 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4482 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4483 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4484 return flow_dv_push_vlan_action_resource_register
4485 (dev, &res, dev_flow, error);
4489 * Validate the modify-header actions.
4491 * @param[in] action_flags
4492 * Holds the actions detected until now.
4494 * Pointer to the modify action.
4496 * Pointer to error structure.
4499 * 0 on success, a negative errno value otherwise and rte_errno is set.
4502 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4503 const struct rte_flow_action *action,
4504 struct rte_flow_error *error)
4506 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4507 return rte_flow_error_set(error, EINVAL,
4508 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4509 NULL, "action configuration not set");
4510 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4511 return rte_flow_error_set(error, EINVAL,
4512 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4513 "can't have encap action before"
4519 * Validate the modify-header MAC address actions.
4521 * @param[in] action_flags
4522 * Holds the actions detected until now.
4524 * Pointer to the modify action.
4525 * @param[in] item_flags
4526 * Holds the items detected.
4528 * Pointer to error structure.
4531 * 0 on success, a negative errno value otherwise and rte_errno is set.
4534 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4535 const struct rte_flow_action *action,
4536 const uint64_t item_flags,
4537 struct rte_flow_error *error)
4541 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4543 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4544 return rte_flow_error_set(error, EINVAL,
4545 RTE_FLOW_ERROR_TYPE_ACTION,
4547 "no L2 item in pattern");
4553 * Validate the modify-header IPv4 address actions.
4555 * @param[in] action_flags
4556 * Holds the actions detected until now.
4558 * Pointer to the modify action.
4559 * @param[in] item_flags
4560 * Holds the items detected.
4562 * Pointer to error structure.
4565 * 0 on success, a negative errno value otherwise and rte_errno is set.
4568 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4569 const struct rte_flow_action *action,
4570 const uint64_t item_flags,
4571 struct rte_flow_error *error)
4576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4579 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4580 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4581 if (!(item_flags & layer))
4582 return rte_flow_error_set(error, EINVAL,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "no ipv4 item in pattern");
4591 * Validate the modify-header IPv6 address actions.
4593 * @param[in] action_flags
4594 * Holds the actions detected until now.
4596 * Pointer to the modify action.
4597 * @param[in] item_flags
4598 * Holds the items detected.
4600 * Pointer to error structure.
4603 * 0 on success, a negative errno value otherwise and rte_errno is set.
4606 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4607 const struct rte_flow_action *action,
4608 const uint64_t item_flags,
4609 struct rte_flow_error *error)
4614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4616 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4617 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4618 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4619 if (!(item_flags & layer))
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "no ipv6 item in pattern");
4629 * Validate the modify-header TP actions.
4631 * @param[in] action_flags
4632 * Holds the actions detected until now.
4634 * Pointer to the modify action.
4635 * @param[in] item_flags
4636 * Holds the items detected.
4638 * Pointer to error structure.
4641 * 0 on success, a negative errno value otherwise and rte_errno is set.
4644 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4645 const struct rte_flow_action *action,
4646 const uint64_t item_flags,
4647 struct rte_flow_error *error)
4652 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4654 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4655 MLX5_FLOW_LAYER_INNER_L4 :
4656 MLX5_FLOW_LAYER_OUTER_L4;
4657 if (!(item_flags & layer))
4658 return rte_flow_error_set(error, EINVAL,
4659 RTE_FLOW_ERROR_TYPE_ACTION,
4660 NULL, "no transport layer "
4667 * Validate the modify-header actions of increment/decrement
4668 * TCP Sequence-number.
4670 * @param[in] action_flags
4671 * Holds the actions detected until now.
4673 * Pointer to the modify action.
4674 * @param[in] item_flags
4675 * Holds the items detected.
4677 * Pointer to error structure.
4680 * 0 on success, a negative errno value otherwise and rte_errno is set.
4683 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4684 const struct rte_flow_action *action,
4685 const uint64_t item_flags,
4686 struct rte_flow_error *error)
4691 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4693 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4694 MLX5_FLOW_LAYER_INNER_L4_TCP :
4695 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4696 if (!(item_flags & layer))
4697 return rte_flow_error_set(error, EINVAL,
4698 RTE_FLOW_ERROR_TYPE_ACTION,
4699 NULL, "no TCP item in"
4701 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4702 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4703 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4704 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4705 return rte_flow_error_set(error, EINVAL,
4706 RTE_FLOW_ERROR_TYPE_ACTION,
4708 "cannot decrease and increase"
4709 " TCP sequence number"
4710 " at the same time");
4716 * Validate the modify-header actions of increment/decrement
4717 * TCP Acknowledgment number.
4719 * @param[in] action_flags
4720 * Holds the actions detected until now.
4722 * Pointer to the modify action.
4723 * @param[in] item_flags
4724 * Holds the items detected.
4726 * Pointer to error structure.
4729 * 0 on success, a negative errno value otherwise and rte_errno is set.
4732 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4733 const struct rte_flow_action *action,
4734 const uint64_t item_flags,
4735 struct rte_flow_error *error)
4740 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4742 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4743 MLX5_FLOW_LAYER_INNER_L4_TCP :
4744 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4745 if (!(item_flags & layer))
4746 return rte_flow_error_set(error, EINVAL,
4747 RTE_FLOW_ERROR_TYPE_ACTION,
4748 NULL, "no TCP item in"
4750 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4751 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4752 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4753 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4754 return rte_flow_error_set(error, EINVAL,
4755 RTE_FLOW_ERROR_TYPE_ACTION,
4757 "cannot decrease and increase"
4758 " TCP acknowledgment number"
4759 " at the same time");
4765 * Validate the modify-header TTL actions.
4767 * @param[in] action_flags
4768 * Holds the actions detected until now.
4770 * Pointer to the modify action.
4771 * @param[in] item_flags
4772 * Holds the items detected.
4774 * Pointer to error structure.
4777 * 0 on success, a negative errno value otherwise and rte_errno is set.
4780 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4781 const struct rte_flow_action *action,
4782 const uint64_t item_flags,
4783 struct rte_flow_error *error)
4788 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4790 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4791 MLX5_FLOW_LAYER_INNER_L3 :
4792 MLX5_FLOW_LAYER_OUTER_L3;
4793 if (!(item_flags & layer))
4794 return rte_flow_error_set(error, EINVAL,
4795 RTE_FLOW_ERROR_TYPE_ACTION,
4797 "no IP protocol in pattern");
4803 * Validate the generic modify field actions.
4805 * Pointer to the rte_eth_dev structure.
4806 * @param[in] action_flags
4807 * Holds the actions detected until now.
4809 * Pointer to the modify action.
4811 * Pointer to the flow attributes.
4813 * Pointer to error structure.
4816 * Number of header fields to modify (0 or more) on success,
4817 * a negative errno value otherwise and rte_errno is set.
4820 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4821 const uint64_t action_flags,
4822 const struct rte_flow_action *action,
4823 const struct rte_flow_attr *attr,
4824 struct rte_flow_error *error)
4827 struct mlx5_priv *priv = dev->data->dev_private;
4828 struct mlx5_dev_config *config = &priv->config;
4829 const struct rte_flow_action_modify_field *action_modify_field =
4831 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4832 action_modify_field->dst.field,
4834 uint32_t src_width = mlx5_flow_item_field_width(dev,
4835 action_modify_field->src.field,
4836 dst_width, attr, error);
4838 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4842 if (action_modify_field->width == 0)
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "no bits are requested to be modified");
4846 else if (action_modify_field->width > dst_width ||
4847 action_modify_field->width > src_width)
4848 return rte_flow_error_set(error, EINVAL,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "cannot modify more bits than"
4851 " the width of a field");
4852 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4853 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4854 if ((action_modify_field->dst.offset +
4855 action_modify_field->width > dst_width) ||
4856 (action_modify_field->dst.offset % 32))
4857 return rte_flow_error_set(error, EINVAL,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "destination offset is too big"
4860 " or not aligned to 4 bytes");
4861 if (action_modify_field->dst.level &&
4862 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4863 return rte_flow_error_set(error, ENOTSUP,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "inner header fields modification"
4866 " is not supported");
4868 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4870 if (!attr->transfer && !attr->group)
4871 return rte_flow_error_set(error, ENOTSUP,
4872 RTE_FLOW_ERROR_TYPE_ACTION, action,
4873 "modify field action is not"
4874 " supported for group 0");
4875 if ((action_modify_field->src.offset +
4876 action_modify_field->width > src_width) ||
4877 (action_modify_field->src.offset % 32))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source offset is too big"
4881 " or not aligned to 4 bytes");
4882 if (action_modify_field->src.level &&
4883 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4884 return rte_flow_error_set(error, ENOTSUP,
4885 RTE_FLOW_ERROR_TYPE_ACTION, action,
4886 "inner header fields modification"
4887 " is not supported");
4889 if ((action_modify_field->dst.field ==
4890 action_modify_field->src.field) &&
4891 (action_modify_field->dst.level ==
4892 action_modify_field->src.level))
4893 return rte_flow_error_set(error, EINVAL,
4894 RTE_FLOW_ERROR_TYPE_ACTION, action,
4895 "source and destination fields"
4896 " cannot be the same");
4897 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4898 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4899 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4900 return rte_flow_error_set(error, EINVAL,
4901 RTE_FLOW_ERROR_TYPE_ACTION, action,
4902 "mark, immediate value or a pointer to it"
4903 " cannot be used as a destination");
4904 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4905 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4906 return rte_flow_error_set(error, ENOTSUP,
4907 RTE_FLOW_ERROR_TYPE_ACTION, action,
4908 "modifications of an arbitrary"
4909 " place in a packet is not supported");
4910 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4911 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION, action,
4914 "modifications of the 802.1Q Tag"
4915 " Identifier is not supported");
4916 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4917 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "modifications of the VXLAN Network"
4921 " Identifier is not supported");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4924 return rte_flow_error_set(error, ENOTSUP,
4925 RTE_FLOW_ERROR_TYPE_ACTION, action,
4926 "modifications of the GENEVE Network"
4927 " Identifier is not supported");
4928 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4929 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4930 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4931 !mlx5_flow_ext_mreg_supported(dev))
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify mark in legacy mode"
4935 " or without extensive registers");
4936 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4937 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4938 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4939 !mlx5_flow_ext_mreg_supported(dev))
4940 return rte_flow_error_set(error, ENOTSUP,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "cannot modify meta without"
4943 " extensive registers support");
4944 ret = flow_dv_get_metadata_reg(dev, attr, error);
4945 if (ret < 0 || ret == REG_NON)
4946 return rte_flow_error_set(error, ENOTSUP,
4947 RTE_FLOW_ERROR_TYPE_ACTION, action,
4948 "cannot modify meta without"
4949 " extensive registers available");
4951 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4952 return rte_flow_error_set(error, ENOTSUP,
4953 RTE_FLOW_ERROR_TYPE_ACTION, action,
4954 "add and sub operations"
4955 " are not supported");
4956 return (action_modify_field->width / 32) +
4957 !!(action_modify_field->width % 32);
4961 * Validate jump action.
4964 * Pointer to the jump action.
4965 * @param[in] action_flags
4966 * Holds the actions detected until now.
4967 * @param[in] attributes
4968 * Pointer to flow attributes
4969 * @param[in] external
4970 * Action belongs to flow rule created by request external to PMD.
4972 * Pointer to error structure.
4975 * 0 on success, a negative errno value otherwise and rte_errno is set.
4978 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4979 const struct mlx5_flow_tunnel *tunnel,
4980 const struct rte_flow_action *action,
4981 uint64_t action_flags,
4982 const struct rte_flow_attr *attributes,
4983 bool external, struct rte_flow_error *error)
4985 uint32_t target_group, table;
4987 struct flow_grp_info grp_info = {
4988 .external = !!external,
4989 .transfer = !!attributes->transfer,
4993 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4994 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4995 return rte_flow_error_set(error, EINVAL,
4996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4997 "can't have 2 fate actions in"
5000 return rte_flow_error_set(error, EINVAL,
5001 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5002 NULL, "action configuration not set");
5004 ((const struct rte_flow_action_jump *)action->conf)->group;
5005 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5009 if (attributes->group == target_group &&
5010 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5011 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "target group must be other than"
5015 " the current flow group");
5020 * Validate action PORT_ID / REPRESENTED_PORT.
5023 * Pointer to rte_eth_dev structure.
5024 * @param[in] action_flags
5025 * Bit-fields that holds the actions detected until now.
5027 * PORT_ID / REPRESENTED_PORT action structure.
5029 * Attributes of flow that includes this action.
5031 * Pointer to error structure.
5034 * 0 on success, a negative errno value otherwise and rte_errno is set.
5037 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5038 uint64_t action_flags,
5039 const struct rte_flow_action *action,
5040 const struct rte_flow_attr *attr,
5041 struct rte_flow_error *error)
5043 const struct rte_flow_action_port_id *port_id;
5044 const struct rte_flow_action_ethdev *ethdev;
5045 struct mlx5_priv *act_priv;
5046 struct mlx5_priv *dev_priv;
5049 if (!attr->transfer)
5050 return rte_flow_error_set(error, ENOTSUP,
5051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5053 "port action is valid in transfer"
5055 if (!action || !action->conf)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5059 "port action parameters must be"
5061 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5062 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5063 return rte_flow_error_set(error, EINVAL,
5064 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5065 "can have only one fate actions in"
5067 dev_priv = mlx5_dev_to_eswitch_info(dev);
5069 return rte_flow_error_set(error, rte_errno,
5070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5072 "failed to obtain E-Switch info");
5073 switch (action->type) {
5074 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5075 port_id = action->conf;
5076 port = port_id->original ? dev->data->port_id : port_id->id;
5078 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5079 ethdev = action->conf;
5080 port = ethdev->port_id;
5084 return rte_flow_error_set
5086 RTE_FLOW_ERROR_TYPE_ACTION, action,
5087 "unknown E-Switch action");
5089 act_priv = mlx5_port_to_eswitch_info(port, false);
5091 return rte_flow_error_set
5093 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5094 "failed to obtain E-Switch port id for port");
5095 if (act_priv->domain_id != dev_priv->domain_id)
5096 return rte_flow_error_set
5098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5099 "port does not belong to"
5100 " E-Switch being configured");
5105 * Get the maximum number of modify header actions.
5108 * Pointer to rte_eth_dev structure.
5110 * Whether action is on root table.
5113 * Max number of modify header actions device can support.
5115 static inline unsigned int
5116 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5120 * There's no way to directly query the max capacity from FW.
5121 * The maximal value on root table should be assumed to be supported.
5124 return MLX5_MAX_MODIFY_NUM;
5126 return MLX5_ROOT_TBL_MODIFY_NUM;
5130 * Validate the meter action.
5133 * Pointer to rte_eth_dev structure.
5134 * @param[in] action_flags
5135 * Bit-fields that holds the actions detected until now.
5137 * Pointer to the meter action.
5139 * Attributes of flow that includes this action.
5140 * @param[in] port_id_item
5141 * Pointer to item indicating port id.
5143 * Pointer to error structure.
5146 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5149 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5150 uint64_t action_flags,
5151 const struct rte_flow_action *action,
5152 const struct rte_flow_attr *attr,
5153 const struct rte_flow_item *port_id_item,
5155 struct rte_flow_error *error)
5157 struct mlx5_priv *priv = dev->data->dev_private;
5158 const struct rte_flow_action_meter *am = action->conf;
5159 struct mlx5_flow_meter_info *fm;
5160 struct mlx5_flow_meter_policy *mtr_policy;
5161 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5164 return rte_flow_error_set(error, EINVAL,
5165 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5166 "meter action conf is NULL");
5168 if (action_flags & MLX5_FLOW_ACTION_METER)
5169 return rte_flow_error_set(error, ENOTSUP,
5170 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5171 "meter chaining not support");
5172 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5173 return rte_flow_error_set(error, ENOTSUP,
5174 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5175 "meter with jump not support");
5177 return rte_flow_error_set(error, ENOTSUP,
5178 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5180 "meter action not supported");
5181 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5183 return rte_flow_error_set(error, EINVAL,
5184 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5186 /* aso meter can always be shared by different domains */
5187 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5188 !(fm->transfer == attr->transfer ||
5189 (!fm->ingress && !attr->ingress && attr->egress) ||
5190 (!fm->egress && !attr->egress && attr->ingress)))
5191 return rte_flow_error_set(error, EINVAL,
5192 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5193 "Flow attributes domain are either invalid "
5194 "or have a domain conflict with current "
5195 "meter attributes");
5196 if (fm->def_policy) {
5197 if (!((attr->transfer &&
5198 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5200 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5202 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5203 return rte_flow_error_set(error, EINVAL,
5204 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5205 "Flow attributes domain "
5206 "have a conflict with current "
5207 "meter domain attributes");
5210 mtr_policy = mlx5_flow_meter_policy_find(dev,
5211 fm->policy_id, NULL);
5213 return rte_flow_error_set(error, EINVAL,
5214 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5215 "Invalid policy id for meter ");
5216 if (!((attr->transfer && mtr_policy->transfer) ||
5217 (attr->egress && mtr_policy->egress) ||
5218 (attr->ingress && mtr_policy->ingress)))
5219 return rte_flow_error_set(error, EINVAL,
5220 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5221 "Flow attributes domain "
5222 "have a conflict with current "
5223 "meter domain attributes");
5224 if (attr->transfer && mtr_policy->dev) {
5226 * When policy has fate action of port_id,
5227 * the flow should have the same src port as policy.
5229 struct mlx5_priv *policy_port_priv =
5230 mtr_policy->dev->data->dev_private;
5231 int32_t flow_src_port = priv->representor_id;
5234 const struct rte_flow_item_port_id *spec =
5236 struct mlx5_priv *port_priv =
5237 mlx5_port_to_eswitch_info(spec->id,
5240 return rte_flow_error_set(error,
5242 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5244 "Failed to get port info.");
5245 flow_src_port = port_priv->representor_id;
5247 if (flow_src_port != policy_port_priv->representor_id)
5248 return rte_flow_error_set(error,
5250 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5252 "Flow and meter policy "
5253 "have different src port.");
5255 *def_policy = false;
5261 * Validate the age action.
5263 * @param[in] action_flags
5264 * Holds the actions detected until now.
5266 * Pointer to the age action.
5268 * Pointer to the Ethernet device structure.
5270 * Pointer to error structure.
5273 * 0 on success, a negative errno value otherwise and rte_errno is set.
5276 flow_dv_validate_action_age(uint64_t action_flags,
5277 const struct rte_flow_action *action,
5278 struct rte_eth_dev *dev,
5279 struct rte_flow_error *error)
5281 struct mlx5_priv *priv = dev->data->dev_private;
5282 const struct rte_flow_action_age *age = action->conf;
5284 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5285 !priv->sh->aso_age_mng))
5286 return rte_flow_error_set(error, ENOTSUP,
5287 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5289 "age action not supported");
5290 if (!(action->conf))
5291 return rte_flow_error_set(error, EINVAL,
5292 RTE_FLOW_ERROR_TYPE_ACTION, action,
5293 "configuration cannot be null");
5294 if (!(age->timeout))
5295 return rte_flow_error_set(error, EINVAL,
5296 RTE_FLOW_ERROR_TYPE_ACTION, action,
5297 "invalid timeout value 0");
5298 if (action_flags & MLX5_FLOW_ACTION_AGE)
5299 return rte_flow_error_set(error, EINVAL,
5300 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5301 "duplicate age actions set");
5306 * Validate the modify-header IPv4 DSCP actions.
5308 * @param[in] action_flags
5309 * Holds the actions detected until now.
5311 * Pointer to the modify action.
5312 * @param[in] item_flags
5313 * Holds the items detected.
5315 * Pointer to error structure.
5318 * 0 on success, a negative errno value otherwise and rte_errno is set.
5321 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5322 const struct rte_flow_action *action,
5323 const uint64_t item_flags,
5324 struct rte_flow_error *error)
5328 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5330 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5331 return rte_flow_error_set(error, EINVAL,
5332 RTE_FLOW_ERROR_TYPE_ACTION,
5334 "no ipv4 item in pattern");
5340 * Validate the modify-header IPv6 DSCP actions.
5342 * @param[in] action_flags
5343 * Holds the actions detected until now.
5345 * Pointer to the modify action.
5346 * @param[in] item_flags
5347 * Holds the items detected.
5349 * Pointer to error structure.
5352 * 0 on success, a negative errno value otherwise and rte_errno is set.
5355 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5356 const struct rte_flow_action *action,
5357 const uint64_t item_flags,
5358 struct rte_flow_error *error)
5362 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5364 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5365 return rte_flow_error_set(error, EINVAL,
5366 RTE_FLOW_ERROR_TYPE_ACTION,
5368 "no ipv6 item in pattern");
5374 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5375 struct mlx5_list_entry *entry, void *cb_ctx)
5377 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5378 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5379 struct mlx5_flow_dv_modify_hdr_resource *resource =
5380 container_of(entry, typeof(*resource), entry);
5381 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5383 key_len += ref->actions_num * sizeof(ref->actions[0]);
5384 return ref->actions_num != resource->actions_num ||
5385 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5388 static struct mlx5_indexed_pool *
5389 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5391 struct mlx5_indexed_pool *ipool = __atomic_load_n
5392 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5395 struct mlx5_indexed_pool *expected = NULL;
5396 struct mlx5_indexed_pool_config cfg =
5397 (struct mlx5_indexed_pool_config) {
5398 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5400 sizeof(struct mlx5_modification_cmd),
5405 .release_mem_en = !!sh->reclaim_mode,
5406 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5407 .malloc = mlx5_malloc,
5409 .type = "mlx5_modify_action_resource",
5412 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5413 ipool = mlx5_ipool_create(&cfg);
5416 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5417 &expected, ipool, false,
5419 __ATOMIC_SEQ_CST)) {
5420 mlx5_ipool_destroy(ipool);
5421 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5428 struct mlx5_list_entry *
5429 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5431 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5432 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5433 struct mlx5dv_dr_domain *ns;
5434 struct mlx5_flow_dv_modify_hdr_resource *entry;
5435 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5436 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5437 ref->actions_num - 1);
5439 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5440 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5443 if (unlikely(!ipool)) {
5444 rte_flow_error_set(ctx->error, ENOMEM,
5445 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5446 NULL, "cannot allocate modify ipool");
5449 entry = mlx5_ipool_zmalloc(ipool, &idx);
5451 rte_flow_error_set(ctx->error, ENOMEM,
5452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5453 "cannot allocate resource memory");
5456 rte_memcpy(&entry->ft_type,
5457 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5458 key_len + data_len);
5459 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5460 ns = sh->fdb_domain;
5461 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5465 ret = mlx5_flow_os_create_flow_action_modify_header
5466 (sh->cdev->ctx, ns, entry,
5467 data_len, &entry->action);
5469 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5470 rte_flow_error_set(ctx->error, ENOMEM,
5471 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5472 NULL, "cannot create modification action");
5476 return &entry->entry;
5479 struct mlx5_list_entry *
5480 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5483 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5484 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5485 struct mlx5_flow_dv_modify_hdr_resource *entry;
5486 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5487 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5490 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5493 rte_flow_error_set(ctx->error, ENOMEM,
5494 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5495 "cannot allocate resource memory");
5498 memcpy(entry, oentry, sizeof(*entry) + data_len);
5500 return &entry->entry;
5504 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5506 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5507 struct mlx5_flow_dv_modify_hdr_resource *res =
5508 container_of(entry, typeof(*res), entry);
5510 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5514 * Validate the sample action.
5516 * @param[in, out] action_flags
5517 * Holds the actions detected until now.
5519 * Pointer to the sample action.
5521 * Pointer to the Ethernet device structure.
5523 * Attributes of flow that includes this action.
5524 * @param[in] item_flags
5525 * Holds the items detected.
5527 * Pointer to the RSS action.
5528 * @param[out] sample_rss
5529 * Pointer to the RSS action in sample action list.
5531 * Pointer to the COUNT action in sample action list.
5532 * @param[out] fdb_mirror_limit
5533 * Pointer to the FDB mirror limitation flag.
5535 * Pointer to error structure.
5538 * 0 on success, a negative errno value otherwise and rte_errno is set.
5541 flow_dv_validate_action_sample(uint64_t *action_flags,
5542 const struct rte_flow_action *action,
5543 struct rte_eth_dev *dev,
5544 const struct rte_flow_attr *attr,
5545 uint64_t item_flags,
5546 const struct rte_flow_action_rss *rss,
5547 const struct rte_flow_action_rss **sample_rss,
5548 const struct rte_flow_action_count **count,
5549 int *fdb_mirror_limit,
5550 struct rte_flow_error *error)
5552 struct mlx5_priv *priv = dev->data->dev_private;
5553 struct mlx5_dev_config *dev_conf = &priv->config;
5554 const struct rte_flow_action_sample *sample = action->conf;
5555 const struct rte_flow_action *act;
5556 uint64_t sub_action_flags = 0;
5557 uint16_t queue_index = 0xFFFF;
5562 return rte_flow_error_set(error, EINVAL,
5563 RTE_FLOW_ERROR_TYPE_ACTION, action,
5564 "configuration cannot be NULL");
5565 if (sample->ratio == 0)
5566 return rte_flow_error_set(error, EINVAL,
5567 RTE_FLOW_ERROR_TYPE_ACTION, action,
5568 "ratio value starts from 1");
5569 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5570 return rte_flow_error_set(error, ENOTSUP,
5571 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5573 "sample action not supported");
5574 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5575 return rte_flow_error_set(error, EINVAL,
5576 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5577 "Multiple sample actions not "
5579 if (*action_flags & MLX5_FLOW_ACTION_METER)
5580 return rte_flow_error_set(error, EINVAL,
5581 RTE_FLOW_ERROR_TYPE_ACTION, action,
5582 "wrong action order, meter should "
5583 "be after sample action");
5584 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5585 return rte_flow_error_set(error, EINVAL,
5586 RTE_FLOW_ERROR_TYPE_ACTION, action,
5587 "wrong action order, jump should "
5588 "be after sample action");
5589 if (*action_flags & MLX5_FLOW_ACTION_CT)
5590 return rte_flow_error_set(error, EINVAL,
5591 RTE_FLOW_ERROR_TYPE_ACTION, action,
5592 "Sample after CT not supported");
5593 act = sample->actions;
5594 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5595 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5596 return rte_flow_error_set(error, ENOTSUP,
5597 RTE_FLOW_ERROR_TYPE_ACTION,
5598 act, "too many actions");
5599 switch (act->type) {
5600 case RTE_FLOW_ACTION_TYPE_QUEUE:
5601 ret = mlx5_flow_validate_action_queue(act,
5607 queue_index = ((const struct rte_flow_action_queue *)
5608 (act->conf))->index;
5609 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5612 case RTE_FLOW_ACTION_TYPE_RSS:
5613 *sample_rss = act->conf;
5614 ret = mlx5_flow_validate_action_rss(act,
5621 if (rss && *sample_rss &&
5622 ((*sample_rss)->level != rss->level ||
5623 (*sample_rss)->types != rss->types))
5624 return rte_flow_error_set(error, ENOTSUP,
5625 RTE_FLOW_ERROR_TYPE_ACTION,
5627 "Can't use the different RSS types "
5628 "or level in the same flow");
5629 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5630 queue_index = (*sample_rss)->queue[0];
5631 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5634 case RTE_FLOW_ACTION_TYPE_MARK:
5635 ret = flow_dv_validate_action_mark(dev, act,
5640 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5641 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5642 MLX5_FLOW_ACTION_MARK_EXT;
5644 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5647 case RTE_FLOW_ACTION_TYPE_COUNT:
5648 ret = flow_dv_validate_action_count
5649 (dev, false, *action_flags | sub_action_flags,
5654 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5655 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5658 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5659 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5660 ret = flow_dv_validate_action_port_id(dev,
5667 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5670 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5671 ret = flow_dv_validate_action_raw_encap_decap
5672 (dev, NULL, act->conf, attr, &sub_action_flags,
5673 &actions_n, action, item_flags, error);
5678 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5679 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5680 ret = flow_dv_validate_action_l2_encap(dev,
5686 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5690 return rte_flow_error_set(error, ENOTSUP,
5691 RTE_FLOW_ERROR_TYPE_ACTION,
5693 "Doesn't support optional "
5697 if (attr->ingress && !attr->transfer) {
5698 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5699 MLX5_FLOW_ACTION_RSS)))
5700 return rte_flow_error_set(error, EINVAL,
5701 RTE_FLOW_ERROR_TYPE_ACTION,
5703 "Ingress must has a dest "
5704 "QUEUE for Sample");
5705 } else if (attr->egress && !attr->transfer) {
5706 return rte_flow_error_set(error, ENOTSUP,
5707 RTE_FLOW_ERROR_TYPE_ACTION,
5709 "Sample Only support Ingress "
5711 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5712 MLX5_ASSERT(attr->transfer);
5713 if (sample->ratio > 1)
5714 return rte_flow_error_set(error, ENOTSUP,
5715 RTE_FLOW_ERROR_TYPE_ACTION,
5717 "E-Switch doesn't support "
5718 "any optional action "
5720 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5721 return rte_flow_error_set(error, ENOTSUP,
5722 RTE_FLOW_ERROR_TYPE_ACTION,
5724 "unsupported action QUEUE");
5725 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5726 return rte_flow_error_set(error, ENOTSUP,
5727 RTE_FLOW_ERROR_TYPE_ACTION,
5729 "unsupported action QUEUE");
5730 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5731 return rte_flow_error_set(error, EINVAL,
5732 RTE_FLOW_ERROR_TYPE_ACTION,
5734 "E-Switch must has a dest "
5735 "port for mirroring");
5736 if (!priv->config.hca_attr.reg_c_preserve &&
5737 priv->representor_id != UINT16_MAX)
5738 *fdb_mirror_limit = 1;
5740 /* Continue validation for Xcap actions.*/
5741 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5742 (queue_index == 0xFFFF ||
5743 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5744 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5745 MLX5_FLOW_XCAP_ACTIONS)
5746 return rte_flow_error_set(error, ENOTSUP,
5747 RTE_FLOW_ERROR_TYPE_ACTION,
5748 NULL, "encap and decap "
5749 "combination aren't "
5751 if (!attr->transfer && attr->ingress && (sub_action_flags &
5752 MLX5_FLOW_ACTION_ENCAP))
5753 return rte_flow_error_set(error, ENOTSUP,
5754 RTE_FLOW_ERROR_TYPE_ACTION,
5755 NULL, "encap is not supported"
5756 " for ingress traffic");
5762 * Find existing modify-header resource or create and register a new one.
5764 * @param dev[in, out]
5765 * Pointer to rte_eth_dev structure.
5766 * @param[in, out] resource
5767 * Pointer to modify-header resource.
5768 * @parm[in, out] dev_flow
5769 * Pointer to the dev_flow.
5771 * pointer to error structure.
5774 * 0 on success otherwise -errno and errno is set.
5777 flow_dv_modify_hdr_resource_register
5778 (struct rte_eth_dev *dev,
5779 struct mlx5_flow_dv_modify_hdr_resource *resource,
5780 struct mlx5_flow *dev_flow,
5781 struct rte_flow_error *error)
5783 struct mlx5_priv *priv = dev->data->dev_private;
5784 struct mlx5_dev_ctx_shared *sh = priv->sh;
5785 uint32_t key_len = sizeof(*resource) -
5786 offsetof(typeof(*resource), ft_type) +
5787 resource->actions_num * sizeof(resource->actions[0]);
5788 struct mlx5_list_entry *entry;
5789 struct mlx5_flow_cb_ctx ctx = {
5793 struct mlx5_hlist *modify_cmds;
5796 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5798 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5800 flow_dv_modify_create_cb,
5801 flow_dv_modify_match_cb,
5802 flow_dv_modify_remove_cb,
5803 flow_dv_modify_clone_cb,
5804 flow_dv_modify_clone_free_cb);
5805 if (unlikely(!modify_cmds))
5807 resource->root = !dev_flow->dv.group;
5808 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5810 return rte_flow_error_set(error, EOVERFLOW,
5811 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5812 "too many modify header items");
5813 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5814 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5817 resource = container_of(entry, typeof(*resource), entry);
5818 dev_flow->handle->dvh.modify_hdr = resource;
5823 * Get DV flow counter by index.
5826 * Pointer to the Ethernet device structure.
5828 * mlx5 flow counter index in the container.
5830 * mlx5 flow counter pool in the container.
5833 * Pointer to the counter, NULL otherwise.
5835 static struct mlx5_flow_counter *
5836 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5838 struct mlx5_flow_counter_pool **ppool)
5840 struct mlx5_priv *priv = dev->data->dev_private;
5841 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5842 struct mlx5_flow_counter_pool *pool;
5844 /* Decrease to original index and clear shared bit. */
5845 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5846 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5847 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5851 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5855 * Check the devx counter belongs to the pool.
5858 * Pointer to the counter pool.
5860 * The counter devx ID.
5863 * True if counter belongs to the pool, false otherwise.
5866 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5868 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5869 MLX5_COUNTERS_PER_POOL;
5871 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5877 * Get a pool by devx counter ID.
5880 * Pointer to the counter management.
5882 * The counter devx ID.
5885 * The counter pool pointer if exists, NULL otherwise,
5887 static struct mlx5_flow_counter_pool *
5888 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5891 struct mlx5_flow_counter_pool *pool = NULL;
5893 rte_spinlock_lock(&cmng->pool_update_sl);
5894 /* Check last used pool. */
5895 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5896 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5897 pool = cmng->pools[cmng->last_pool_idx];
5900 /* ID out of range means no suitable pool in the container. */
5901 if (id > cmng->max_id || id < cmng->min_id)
5904 * Find the pool from the end of the container, since mostly counter
5905 * ID is sequence increasing, and the last pool should be the needed
5910 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5912 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5918 rte_spinlock_unlock(&cmng->pool_update_sl);
5923 * Resize a counter container.
5926 * Pointer to the Ethernet device structure.
5929 * 0 on success, otherwise negative errno value and rte_errno is set.
5932 flow_dv_container_resize(struct rte_eth_dev *dev)
5934 struct mlx5_priv *priv = dev->data->dev_private;
5935 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5936 void *old_pools = cmng->pools;
5937 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5938 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5939 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5946 memcpy(pools, old_pools, cmng->n *
5947 sizeof(struct mlx5_flow_counter_pool *));
5949 cmng->pools = pools;
5951 mlx5_free(old_pools);
5956 * Query a devx flow counter.
5959 * Pointer to the Ethernet device structure.
5960 * @param[in] counter
5961 * Index to the flow counter.
5963 * The statistics value of packets.
5965 * The statistics value of bytes.
5968 * 0 on success, otherwise a negative errno value and rte_errno is set.
5971 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5974 struct mlx5_priv *priv = dev->data->dev_private;
5975 struct mlx5_flow_counter_pool *pool = NULL;
5976 struct mlx5_flow_counter *cnt;
5979 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5981 if (priv->sh->cmng.counter_fallback)
5982 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5983 0, pkts, bytes, 0, NULL, NULL, 0);
5984 rte_spinlock_lock(&pool->sl);
5989 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5990 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5991 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5993 rte_spinlock_unlock(&pool->sl);
5998 * Create and initialize a new counter pool.
6001 * Pointer to the Ethernet device structure.
6003 * The devX counter handle.
6005 * Whether the pool is for counter that was allocated for aging.
6006 * @param[in/out] cont_cur
6007 * Pointer to the container pointer, it will be update in pool resize.
6010 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6012 static struct mlx5_flow_counter_pool *
6013 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6016 struct mlx5_priv *priv = dev->data->dev_private;
6017 struct mlx5_flow_counter_pool *pool;
6018 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6019 bool fallback = priv->sh->cmng.counter_fallback;
6020 uint32_t size = sizeof(*pool);
6022 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6023 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6024 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6030 pool->is_aged = !!age;
6031 pool->query_gen = 0;
6032 pool->min_dcs = dcs;
6033 rte_spinlock_init(&pool->sl);
6034 rte_spinlock_init(&pool->csl);
6035 TAILQ_INIT(&pool->counters[0]);
6036 TAILQ_INIT(&pool->counters[1]);
6037 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6038 rte_spinlock_lock(&cmng->pool_update_sl);
6039 pool->index = cmng->n_valid;
6040 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6042 rte_spinlock_unlock(&cmng->pool_update_sl);
6045 cmng->pools[pool->index] = pool;
6047 if (unlikely(fallback)) {
6048 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6050 if (base < cmng->min_id)
6051 cmng->min_id = base;
6052 if (base > cmng->max_id)
6053 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6054 cmng->last_pool_idx = pool->index;
6056 rte_spinlock_unlock(&cmng->pool_update_sl);
6061 * Prepare a new counter and/or a new counter pool.
6064 * Pointer to the Ethernet device structure.
6065 * @param[out] cnt_free
6066 * Where to put the pointer of a new counter.
6068 * Whether the pool is for counter that was allocated for aging.
6071 * The counter pool pointer and @p cnt_free is set on success,
6072 * NULL otherwise and rte_errno is set.
6074 static struct mlx5_flow_counter_pool *
6075 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6076 struct mlx5_flow_counter **cnt_free,
6079 struct mlx5_priv *priv = dev->data->dev_private;
6080 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6081 struct mlx5_flow_counter_pool *pool;
6082 struct mlx5_counters tmp_tq;
6083 struct mlx5_devx_obj *dcs = NULL;
6084 struct mlx5_flow_counter *cnt;
6085 enum mlx5_counter_type cnt_type =
6086 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6087 bool fallback = priv->sh->cmng.counter_fallback;
6091 /* bulk_bitmap must be 0 for single counter allocation. */
6092 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6095 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6097 pool = flow_dv_pool_create(dev, dcs, age);
6099 mlx5_devx_cmd_destroy(dcs);
6103 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6104 cnt = MLX5_POOL_GET_CNT(pool, i);
6106 cnt->dcs_when_free = dcs;
6110 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6112 rte_errno = ENODATA;
6115 pool = flow_dv_pool_create(dev, dcs, age);
6117 mlx5_devx_cmd_destroy(dcs);
6120 TAILQ_INIT(&tmp_tq);
6121 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6122 cnt = MLX5_POOL_GET_CNT(pool, i);
6124 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6126 rte_spinlock_lock(&cmng->csl[cnt_type]);
6127 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6128 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6129 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6130 (*cnt_free)->pool = pool;
6135 * Allocate a flow counter.
6138 * Pointer to the Ethernet device structure.
6140 * Whether the counter was allocated for aging.
6143 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6146 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6148 struct mlx5_priv *priv = dev->data->dev_private;
6149 struct mlx5_flow_counter_pool *pool = NULL;
6150 struct mlx5_flow_counter *cnt_free = NULL;
6151 bool fallback = priv->sh->cmng.counter_fallback;
6152 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6153 enum mlx5_counter_type cnt_type =
6154 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6157 if (!priv->sh->devx) {
6158 rte_errno = ENOTSUP;
6161 /* Get free counters from container. */
6162 rte_spinlock_lock(&cmng->csl[cnt_type]);
6163 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6165 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6166 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6167 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6169 pool = cnt_free->pool;
6171 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6172 /* Create a DV counter action only in the first time usage. */
6173 if (!cnt_free->action) {
6175 struct mlx5_devx_obj *dcs;
6179 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6180 dcs = pool->min_dcs;
6183 dcs = cnt_free->dcs_when_free;
6185 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6192 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6193 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6194 /* Update the counter reset values. */
6195 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6198 if (!fallback && !priv->sh->cmng.query_thread_on)
6199 /* Start the asynchronous batch query by the host thread. */
6200 mlx5_set_query_alarm(priv->sh);
6202 * When the count action isn't shared (by ID), shared_info field is
6203 * used for indirect action API's refcnt.
6204 * When the counter action is not shared neither by ID nor by indirect
6205 * action API, shared info must be 1.
6207 cnt_free->shared_info.refcnt = 1;
6211 cnt_free->pool = pool;
6213 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6214 rte_spinlock_lock(&cmng->csl[cnt_type]);
6215 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6216 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6222 * Get age param from counter index.
6225 * Pointer to the Ethernet device structure.
6226 * @param[in] counter
6227 * Index to the counter handler.
6230 * The aging parameter specified for the counter index.
6232 static struct mlx5_age_param*
6233 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6236 struct mlx5_flow_counter *cnt;
6237 struct mlx5_flow_counter_pool *pool = NULL;
6239 flow_dv_counter_get_by_idx(dev, counter, &pool);
6240 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6241 cnt = MLX5_POOL_GET_CNT(pool, counter);
6242 return MLX5_CNT_TO_AGE(cnt);
6246 * Remove a flow counter from aged counter list.
6249 * Pointer to the Ethernet device structure.
6250 * @param[in] counter
6251 * Index to the counter handler.
6253 * Pointer to the counter handler.
6256 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6257 uint32_t counter, struct mlx5_flow_counter *cnt)
6259 struct mlx5_age_info *age_info;
6260 struct mlx5_age_param *age_param;
6261 struct mlx5_priv *priv = dev->data->dev_private;
6262 uint16_t expected = AGE_CANDIDATE;
6264 age_info = GET_PORT_AGE_INFO(priv);
6265 age_param = flow_dv_counter_idx_get_age(dev, counter);
6266 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6267 AGE_FREE, false, __ATOMIC_RELAXED,
6268 __ATOMIC_RELAXED)) {
6270 * We need the lock even it is age timeout,
6271 * since counter may still in process.
6273 rte_spinlock_lock(&age_info->aged_sl);
6274 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6275 rte_spinlock_unlock(&age_info->aged_sl);
6276 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6281 * Release a flow counter.
6284 * Pointer to the Ethernet device structure.
6285 * @param[in] counter
6286 * Index to the counter handler.
6289 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6291 struct mlx5_priv *priv = dev->data->dev_private;
6292 struct mlx5_flow_counter_pool *pool = NULL;
6293 struct mlx5_flow_counter *cnt;
6294 enum mlx5_counter_type cnt_type;
6298 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6300 if (pool->is_aged) {
6301 flow_dv_counter_remove_from_age(dev, counter, cnt);
6304 * If the counter action is shared by indirect action API,
6305 * the atomic function reduces its references counter.
6306 * If after the reduction the action is still referenced, the
6307 * function returns here and does not release it.
6308 * When the counter action is not shared by
6309 * indirect action API, shared info is 1 before the reduction,
6310 * so this condition is failed and function doesn't return here.
6312 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6318 * Put the counter back to list to be updated in none fallback mode.
6319 * Currently, we are using two list alternately, while one is in query,
6320 * add the freed counter to the other list based on the pool query_gen
6321 * value. After query finishes, add counter the list to the global
6322 * container counter list. The list changes while query starts. In
6323 * this case, lock will not be needed as query callback and release
6324 * function both operate with the different list.
6326 if (!priv->sh->cmng.counter_fallback) {
6327 rte_spinlock_lock(&pool->csl);
6328 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6329 rte_spinlock_unlock(&pool->csl);
6331 cnt->dcs_when_free = cnt->dcs_when_active;
6332 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6333 MLX5_COUNTER_TYPE_ORIGIN;
6334 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6335 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6337 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6342 * Resize a meter id container.
6345 * Pointer to the Ethernet device structure.
6348 * 0 on success, otherwise negative errno value and rte_errno is set.
6351 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6353 struct mlx5_priv *priv = dev->data->dev_private;
6354 struct mlx5_aso_mtr_pools_mng *pools_mng =
6355 &priv->sh->mtrmng->pools_mng;
6356 void *old_pools = pools_mng->pools;
6357 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6358 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6359 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6366 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6371 memcpy(pools, old_pools, pools_mng->n *
6372 sizeof(struct mlx5_aso_mtr_pool *));
6373 pools_mng->n = resize;
6374 pools_mng->pools = pools;
6376 mlx5_free(old_pools);
6381 * Prepare a new meter and/or a new meter pool.
6384 * Pointer to the Ethernet device structure.
6385 * @param[out] mtr_free
6386 * Where to put the pointer of a new meter.g.
6389 * The meter pool pointer and @mtr_free is set on success,
6390 * NULL otherwise and rte_errno is set.
6392 static struct mlx5_aso_mtr_pool *
6393 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6395 struct mlx5_priv *priv = dev->data->dev_private;
6396 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6397 struct mlx5_aso_mtr_pool *pool = NULL;
6398 struct mlx5_devx_obj *dcs = NULL;
6400 uint32_t log_obj_size;
6402 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6403 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6404 priv->sh->cdev->pdn,
6407 rte_errno = ENODATA;
6410 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6413 claim_zero(mlx5_devx_cmd_destroy(dcs));
6416 pool->devx_obj = dcs;
6417 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6418 pool->index = pools_mng->n_valid;
6419 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6421 claim_zero(mlx5_devx_cmd_destroy(dcs));
6422 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6425 pools_mng->pools[pool->index] = pool;
6426 pools_mng->n_valid++;
6427 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6428 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6429 pool->mtrs[i].offset = i;
6430 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6432 pool->mtrs[0].offset = 0;
6433 *mtr_free = &pool->mtrs[0];
6438 * Release a flow meter into pool.
6441 * Pointer to the Ethernet device structure.
6442 * @param[in] mtr_idx
6443 * Index to aso flow meter.
6446 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6448 struct mlx5_priv *priv = dev->data->dev_private;
6449 struct mlx5_aso_mtr_pools_mng *pools_mng =
6450 &priv->sh->mtrmng->pools_mng;
6451 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6453 MLX5_ASSERT(aso_mtr);
6454 rte_spinlock_lock(&pools_mng->mtrsl);
6455 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6456 aso_mtr->state = ASO_METER_FREE;
6457 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6458 rte_spinlock_unlock(&pools_mng->mtrsl);
6462 * Allocate a aso flow meter.
6465 * Pointer to the Ethernet device structure.
6468 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6471 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6473 struct mlx5_priv *priv = dev->data->dev_private;
6474 struct mlx5_aso_mtr *mtr_free = NULL;
6475 struct mlx5_aso_mtr_pools_mng *pools_mng =
6476 &priv->sh->mtrmng->pools_mng;
6477 struct mlx5_aso_mtr_pool *pool;
6478 uint32_t mtr_idx = 0;
6480 if (!priv->sh->devx) {
6481 rte_errno = ENOTSUP;
6484 /* Allocate the flow meter memory. */
6485 /* Get free meters from management. */
6486 rte_spinlock_lock(&pools_mng->mtrsl);
6487 mtr_free = LIST_FIRST(&pools_mng->meters);
6489 LIST_REMOVE(mtr_free, next);
6490 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6491 rte_spinlock_unlock(&pools_mng->mtrsl);
6494 mtr_free->state = ASO_METER_WAIT;
6495 rte_spinlock_unlock(&pools_mng->mtrsl);
6496 pool = container_of(mtr_free,
6497 struct mlx5_aso_mtr_pool,
6498 mtrs[mtr_free->offset]);
6499 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6500 if (!mtr_free->fm.meter_action) {
6501 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6502 struct rte_flow_error error;
6505 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6506 mtr_free->fm.meter_action =
6507 mlx5_glue->dv_create_flow_action_aso
6508 (priv->sh->rx_domain,
6509 pool->devx_obj->obj,
6511 (1 << MLX5_FLOW_COLOR_GREEN),
6513 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6514 if (!mtr_free->fm.meter_action) {
6515 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6523 * Verify the @p attributes will be correctly understood by the NIC and store
6524 * them in the @p flow if everything is correct.
6527 * Pointer to dev struct.
6528 * @param[in] attributes
6529 * Pointer to flow attributes
6530 * @param[in] external
6531 * This flow rule is created by request external to PMD.
6533 * Pointer to error structure.
6536 * - 0 on success and non root table.
6537 * - 1 on success and root table.
6538 * - a negative errno value otherwise and rte_errno is set.
6541 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6542 const struct mlx5_flow_tunnel *tunnel,
6543 const struct rte_flow_attr *attributes,
6544 const struct flow_grp_info *grp_info,
6545 struct rte_flow_error *error)
6547 struct mlx5_priv *priv = dev->data->dev_private;
6548 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6551 #ifndef HAVE_MLX5DV_DR
6552 RTE_SET_USED(tunnel);
6553 RTE_SET_USED(grp_info);
6554 if (attributes->group)
6555 return rte_flow_error_set(error, ENOTSUP,
6556 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6558 "groups are not supported");
6562 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6567 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6569 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6570 attributes->priority > lowest_priority)
6571 return rte_flow_error_set(error, ENOTSUP,
6572 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6574 "priority out of range");
6575 if (attributes->transfer) {
6576 if (!priv->config.dv_esw_en)
6577 return rte_flow_error_set
6579 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6580 "E-Switch dr is not supported");
6581 if (!(priv->representor || priv->master))
6582 return rte_flow_error_set
6583 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6584 NULL, "E-Switch configuration can only be"
6585 " done by a master or a representor device");
6586 if (attributes->egress)
6587 return rte_flow_error_set
6589 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6590 "egress is not supported");
6592 if (!(attributes->egress ^ attributes->ingress))
6593 return rte_flow_error_set(error, ENOTSUP,
6594 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6595 "must specify exactly one of "
6596 "ingress or egress");
6601 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6602 int64_t pattern_flags, uint64_t l3_flags,
6603 uint64_t l4_flags, uint64_t ip4_flag,
6604 struct rte_flow_error *error)
6606 if (mask->l3_ok && !(pattern_flags & l3_flags))
6607 return rte_flow_error_set(error, EINVAL,
6608 RTE_FLOW_ERROR_TYPE_ITEM,
6609 NULL, "missing L3 protocol");
6611 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6612 return rte_flow_error_set(error, EINVAL,
6613 RTE_FLOW_ERROR_TYPE_ITEM,
6614 NULL, "missing IPv4 protocol");
6616 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6617 return rte_flow_error_set(error, EINVAL,
6618 RTE_FLOW_ERROR_TYPE_ITEM,
6619 NULL, "missing L4 protocol");
6625 flow_dv_validate_item_integrity_post(const struct
6626 rte_flow_item *integrity_items[2],
6627 int64_t pattern_flags,
6628 struct rte_flow_error *error)
6630 const struct rte_flow_item_integrity *mask;
6633 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6634 mask = (typeof(mask))integrity_items[0]->mask;
6635 ret = validate_integrity_bits(mask, pattern_flags,
6636 MLX5_FLOW_LAYER_OUTER_L3,
6637 MLX5_FLOW_LAYER_OUTER_L4,
6638 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6643 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6644 mask = (typeof(mask))integrity_items[1]->mask;
6645 ret = validate_integrity_bits(mask, pattern_flags,
6646 MLX5_FLOW_LAYER_INNER_L3,
6647 MLX5_FLOW_LAYER_INNER_L4,
6648 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6657 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6658 const struct rte_flow_item *integrity_item,
6659 uint64_t pattern_flags, uint64_t *last_item,
6660 const struct rte_flow_item *integrity_items[2],
6661 struct rte_flow_error *error)
6663 struct mlx5_priv *priv = dev->data->dev_private;
6664 const struct rte_flow_item_integrity *mask = (typeof(mask))
6665 integrity_item->mask;
6666 const struct rte_flow_item_integrity *spec = (typeof(spec))
6667 integrity_item->spec;
6669 if (!priv->config.hca_attr.pkt_integrity_match)
6670 return rte_flow_error_set(error, ENOTSUP,
6671 RTE_FLOW_ERROR_TYPE_ITEM,
6673 "packet integrity integrity_item not supported");
6675 return rte_flow_error_set(error, ENOTSUP,
6676 RTE_FLOW_ERROR_TYPE_ITEM,
6678 "no spec for integrity item");
6680 mask = &rte_flow_item_integrity_mask;
6681 if (!mlx5_validate_integrity_item(mask))
6682 return rte_flow_error_set(error, ENOTSUP,
6683 RTE_FLOW_ERROR_TYPE_ITEM,
6685 "unsupported integrity filter");
6686 if (spec->level > 1) {
6687 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6688 return rte_flow_error_set
6690 RTE_FLOW_ERROR_TYPE_ITEM,
6691 NULL, "multiple inner integrity items not supported");
6692 integrity_items[1] = integrity_item;
6693 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6695 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6696 return rte_flow_error_set
6698 RTE_FLOW_ERROR_TYPE_ITEM,
6699 NULL, "multiple outer integrity items not supported");
6700 integrity_items[0] = integrity_item;
6701 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6707 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6708 const struct rte_flow_item *item,
6709 uint64_t item_flags,
6710 uint64_t *last_item,
6712 struct rte_flow_error *error)
6714 const struct rte_flow_item_flex *flow_spec = item->spec;
6715 const struct rte_flow_item_flex *flow_mask = item->mask;
6716 struct mlx5_flex_item *flex;
6719 return rte_flow_error_set(error, EINVAL,
6720 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6721 "flex flow item spec cannot be NULL");
6723 return rte_flow_error_set(error, EINVAL,
6724 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6725 "flex flow item mask cannot be NULL");
6727 return rte_flow_error_set(error, ENOTSUP,
6728 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6729 "flex flow item last not supported");
6730 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6731 return rte_flow_error_set(error, EINVAL,
6732 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6733 "invalid flex flow item handle");
6734 flex = (struct mlx5_flex_item *)flow_spec->handle;
6735 switch (flex->tunnel_mode) {
6736 case FLEX_TUNNEL_MODE_SINGLE:
6738 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6739 rte_flow_error_set(error, EINVAL,
6740 RTE_FLOW_ERROR_TYPE_ITEM,
6741 NULL, "multiple flex items not supported");
6743 case FLEX_TUNNEL_MODE_OUTER:
6745 rte_flow_error_set(error, EINVAL,
6746 RTE_FLOW_ERROR_TYPE_ITEM,
6747 NULL, "inner flex item was not configured");
6748 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6749 rte_flow_error_set(error, ENOTSUP,
6750 RTE_FLOW_ERROR_TYPE_ITEM,
6751 NULL, "multiple flex items not supported");
6753 case FLEX_TUNNEL_MODE_INNER:
6755 rte_flow_error_set(error, EINVAL,
6756 RTE_FLOW_ERROR_TYPE_ITEM,
6757 NULL, "outer flex item was not configured");
6758 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6759 rte_flow_error_set(error, EINVAL,
6760 RTE_FLOW_ERROR_TYPE_ITEM,
6761 NULL, "multiple flex items not supported");
6763 case FLEX_TUNNEL_MODE_MULTI:
6764 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6765 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6766 rte_flow_error_set(error, EINVAL,
6767 RTE_FLOW_ERROR_TYPE_ITEM,
6768 NULL, "multiple flex items not supported");
6771 case FLEX_TUNNEL_MODE_TUNNEL:
6772 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6773 rte_flow_error_set(error, EINVAL,
6774 RTE_FLOW_ERROR_TYPE_ITEM,
6775 NULL, "multiple flex tunnel items not supported");
6778 rte_flow_error_set(error, EINVAL,
6779 RTE_FLOW_ERROR_TYPE_ITEM,
6780 NULL, "invalid flex item configuration");
6782 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6783 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6784 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6789 * Internal validation function. For validating both actions and items.
6792 * Pointer to the rte_eth_dev structure.
6794 * Pointer to the flow attributes.
6796 * Pointer to the list of items.
6797 * @param[in] actions
6798 * Pointer to the list of actions.
6799 * @param[in] external
6800 * This flow rule is created by request external to PMD.
6801 * @param[in] hairpin
6802 * Number of hairpin TX actions, 0 means classic flow.
6804 * Pointer to the error structure.
6807 * 0 on success, a negative errno value otherwise and rte_errno is set.
6810 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6811 const struct rte_flow_item items[],
6812 const struct rte_flow_action actions[],
6813 bool external, int hairpin, struct rte_flow_error *error)
6816 uint64_t action_flags = 0;
6817 uint64_t item_flags = 0;
6818 uint64_t last_item = 0;
6819 uint8_t next_protocol = 0xff;
6820 uint16_t ether_type = 0;
6822 uint8_t item_ipv6_proto = 0;
6823 int fdb_mirror_limit = 0;
6824 int modify_after_mirror = 0;
6825 const struct rte_flow_item *geneve_item = NULL;
6826 const struct rte_flow_item *gre_item = NULL;
6827 const struct rte_flow_item *gtp_item = NULL;
6828 const struct rte_flow_action_raw_decap *decap;
6829 const struct rte_flow_action_raw_encap *encap;
6830 const struct rte_flow_action_rss *rss = NULL;
6831 const struct rte_flow_action_rss *sample_rss = NULL;
6832 const struct rte_flow_action_count *sample_count = NULL;
6833 const struct rte_flow_item_tcp nic_tcp_mask = {
6836 .src_port = RTE_BE16(UINT16_MAX),
6837 .dst_port = RTE_BE16(UINT16_MAX),
6840 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6843 "\xff\xff\xff\xff\xff\xff\xff\xff"
6844 "\xff\xff\xff\xff\xff\xff\xff\xff",
6846 "\xff\xff\xff\xff\xff\xff\xff\xff"
6847 "\xff\xff\xff\xff\xff\xff\xff\xff",
6848 .vtc_flow = RTE_BE32(0xffffffff),
6854 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6858 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6862 .dummy[0] = 0xffffffff,
6865 struct mlx5_priv *priv = dev->data->dev_private;
6866 struct mlx5_dev_config *dev_conf = &priv->config;
6867 uint16_t queue_index = 0xFFFF;
6868 const struct rte_flow_item_vlan *vlan_m = NULL;
6869 uint32_t rw_act_num = 0;
6871 const struct mlx5_flow_tunnel *tunnel;
6872 enum mlx5_tof_rule_type tof_rule_type;
6873 struct flow_grp_info grp_info = {
6874 .external = !!external,
6875 .transfer = !!attr->transfer,
6876 .fdb_def_rule = !!priv->fdb_def_rule,
6877 .std_tbl_fix = true,
6879 const struct rte_eth_hairpin_conf *conf;
6880 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6881 const struct rte_flow_item *port_id_item = NULL;
6882 bool def_policy = false;
6883 uint16_t udp_dport = 0;
6887 tunnel = is_tunnel_offload_active(dev) ?
6888 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6890 if (!priv->config.dv_flow_en)
6891 return rte_flow_error_set
6893 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6894 NULL, "tunnel offload requires DV flow interface");
6895 if (priv->representor)
6896 return rte_flow_error_set
6898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6899 NULL, "decap not supported for VF representor");
6900 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6901 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6902 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6903 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6904 MLX5_FLOW_ACTION_DECAP;
6905 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6906 (dev, attr, tunnel, tof_rule_type);
6908 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6911 is_root = (uint64_t)ret;
6912 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6913 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6914 int type = items->type;
6916 if (!mlx5_flow_os_item_supported(type))
6917 return rte_flow_error_set(error, ENOTSUP,
6918 RTE_FLOW_ERROR_TYPE_ITEM,
6919 NULL, "item not supported");
6921 case RTE_FLOW_ITEM_TYPE_VOID:
6923 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6924 ret = flow_dv_validate_item_port_id
6925 (dev, items, attr, item_flags, error);
6928 last_item = MLX5_FLOW_ITEM_PORT_ID;
6929 port_id_item = items;
6931 case RTE_FLOW_ITEM_TYPE_ETH:
6932 ret = mlx5_flow_validate_item_eth(items, item_flags,
6936 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6937 MLX5_FLOW_LAYER_OUTER_L2;
6938 if (items->mask != NULL && items->spec != NULL) {
6940 ((const struct rte_flow_item_eth *)
6943 ((const struct rte_flow_item_eth *)
6945 ether_type = rte_be_to_cpu_16(ether_type);
6950 case RTE_FLOW_ITEM_TYPE_VLAN:
6951 ret = flow_dv_validate_item_vlan(items, item_flags,
6955 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6956 MLX5_FLOW_LAYER_OUTER_VLAN;
6957 if (items->mask != NULL && items->spec != NULL) {
6959 ((const struct rte_flow_item_vlan *)
6960 items->spec)->inner_type;
6962 ((const struct rte_flow_item_vlan *)
6963 items->mask)->inner_type;
6964 ether_type = rte_be_to_cpu_16(ether_type);
6968 /* Store outer VLAN mask for of_push_vlan action. */
6970 vlan_m = items->mask;
6972 case RTE_FLOW_ITEM_TYPE_IPV4:
6973 mlx5_flow_tunnel_ip_check(items, next_protocol,
6974 &item_flags, &tunnel);
6975 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6976 last_item, ether_type,
6980 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6981 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6982 if (items->mask != NULL &&
6983 ((const struct rte_flow_item_ipv4 *)
6984 items->mask)->hdr.next_proto_id) {
6986 ((const struct rte_flow_item_ipv4 *)
6987 (items->spec))->hdr.next_proto_id;
6989 ((const struct rte_flow_item_ipv4 *)
6990 (items->mask))->hdr.next_proto_id;
6992 /* Reset for inner layer. */
6993 next_protocol = 0xff;
6996 case RTE_FLOW_ITEM_TYPE_IPV6:
6997 mlx5_flow_tunnel_ip_check(items, next_protocol,
6998 &item_flags, &tunnel);
6999 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7006 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7007 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7008 if (items->mask != NULL &&
7009 ((const struct rte_flow_item_ipv6 *)
7010 items->mask)->hdr.proto) {
7012 ((const struct rte_flow_item_ipv6 *)
7013 items->spec)->hdr.proto;
7015 ((const struct rte_flow_item_ipv6 *)
7016 items->spec)->hdr.proto;
7018 ((const struct rte_flow_item_ipv6 *)
7019 items->mask)->hdr.proto;
7021 /* Reset for inner layer. */
7022 next_protocol = 0xff;
7025 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7026 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7031 last_item = tunnel ?
7032 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7033 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7034 if (items->mask != NULL &&
7035 ((const struct rte_flow_item_ipv6_frag_ext *)
7036 items->mask)->hdr.next_header) {
7038 ((const struct rte_flow_item_ipv6_frag_ext *)
7039 items->spec)->hdr.next_header;
7041 ((const struct rte_flow_item_ipv6_frag_ext *)
7042 items->mask)->hdr.next_header;
7044 /* Reset for inner layer. */
7045 next_protocol = 0xff;
7048 case RTE_FLOW_ITEM_TYPE_TCP:
7049 ret = mlx5_flow_validate_item_tcp
7056 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7057 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7059 case RTE_FLOW_ITEM_TYPE_UDP:
7060 ret = mlx5_flow_validate_item_udp(items, item_flags,
7063 const struct rte_flow_item_udp *spec = items->spec;
7064 const struct rte_flow_item_udp *mask = items->mask;
7066 mask = &rte_flow_item_udp_mask;
7068 udp_dport = rte_be_to_cpu_16
7069 (spec->hdr.dst_port &
7070 mask->hdr.dst_port);
7073 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7074 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7076 case RTE_FLOW_ITEM_TYPE_GRE:
7077 ret = mlx5_flow_validate_item_gre(items, item_flags,
7078 next_protocol, error);
7082 last_item = MLX5_FLOW_LAYER_GRE;
7084 case RTE_FLOW_ITEM_TYPE_NVGRE:
7085 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7090 last_item = MLX5_FLOW_LAYER_NVGRE;
7092 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7093 ret = mlx5_flow_validate_item_gre_key
7094 (items, item_flags, gre_item, error);
7097 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7099 case RTE_FLOW_ITEM_TYPE_VXLAN:
7100 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7105 last_item = MLX5_FLOW_LAYER_VXLAN;
7107 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7108 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7113 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7115 case RTE_FLOW_ITEM_TYPE_GENEVE:
7116 ret = mlx5_flow_validate_item_geneve(items,
7121 geneve_item = items;
7122 last_item = MLX5_FLOW_LAYER_GENEVE;
7124 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7125 ret = mlx5_flow_validate_item_geneve_opt(items,
7132 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7134 case RTE_FLOW_ITEM_TYPE_MPLS:
7135 ret = mlx5_flow_validate_item_mpls(dev, items,
7140 last_item = MLX5_FLOW_LAYER_MPLS;
7143 case RTE_FLOW_ITEM_TYPE_MARK:
7144 ret = flow_dv_validate_item_mark(dev, items, attr,
7148 last_item = MLX5_FLOW_ITEM_MARK;
7150 case RTE_FLOW_ITEM_TYPE_META:
7151 ret = flow_dv_validate_item_meta(dev, items, attr,
7155 last_item = MLX5_FLOW_ITEM_METADATA;
7157 case RTE_FLOW_ITEM_TYPE_ICMP:
7158 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7163 last_item = MLX5_FLOW_LAYER_ICMP;
7165 case RTE_FLOW_ITEM_TYPE_ICMP6:
7166 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7171 item_ipv6_proto = IPPROTO_ICMPV6;
7172 last_item = MLX5_FLOW_LAYER_ICMP6;
7174 case RTE_FLOW_ITEM_TYPE_TAG:
7175 ret = flow_dv_validate_item_tag(dev, items,
7179 last_item = MLX5_FLOW_ITEM_TAG;
7181 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7182 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7184 case RTE_FLOW_ITEM_TYPE_GTP:
7185 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7190 last_item = MLX5_FLOW_LAYER_GTP;
7192 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7193 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7198 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7200 case RTE_FLOW_ITEM_TYPE_ECPRI:
7201 /* Capacity will be checked in the translate stage. */
7202 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7209 last_item = MLX5_FLOW_LAYER_ECPRI;
7211 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7212 ret = flow_dv_validate_item_integrity(dev, items,
7220 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7221 ret = flow_dv_validate_item_aso_ct(dev, items,
7222 &item_flags, error);
7226 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7227 /* tunnel offload item was processed before
7228 * list it here as a supported type
7231 case RTE_FLOW_ITEM_TYPE_FLEX:
7232 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7234 tunnel != 0, error);
7239 return rte_flow_error_set(error, ENOTSUP,
7240 RTE_FLOW_ERROR_TYPE_ITEM,
7241 NULL, "item not supported");
7243 item_flags |= last_item;
7245 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7246 ret = flow_dv_validate_item_integrity_post(integrity_items,
7251 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7252 int type = actions->type;
7253 bool shared_count = false;
7255 if (!mlx5_flow_os_action_supported(type))
7256 return rte_flow_error_set(error, ENOTSUP,
7257 RTE_FLOW_ERROR_TYPE_ACTION,
7259 "action not supported");
7260 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7261 return rte_flow_error_set(error, ENOTSUP,
7262 RTE_FLOW_ERROR_TYPE_ACTION,
7263 actions, "too many actions");
7265 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7266 return rte_flow_error_set(error, ENOTSUP,
7267 RTE_FLOW_ERROR_TYPE_ACTION,
7268 NULL, "meter action with policy "
7269 "must be the last action");
7271 case RTE_FLOW_ACTION_TYPE_VOID:
7273 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7274 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7275 ret = flow_dv_validate_action_port_id(dev,
7282 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7285 case RTE_FLOW_ACTION_TYPE_FLAG:
7286 ret = flow_dv_validate_action_flag(dev, action_flags,
7290 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7291 /* Count all modify-header actions as one. */
7292 if (!(action_flags &
7293 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7295 action_flags |= MLX5_FLOW_ACTION_FLAG |
7296 MLX5_FLOW_ACTION_MARK_EXT;
7297 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7298 modify_after_mirror = 1;
7301 action_flags |= MLX5_FLOW_ACTION_FLAG;
7304 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7306 case RTE_FLOW_ACTION_TYPE_MARK:
7307 ret = flow_dv_validate_action_mark(dev, actions,
7312 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7313 /* Count all modify-header actions as one. */
7314 if (!(action_flags &
7315 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7317 action_flags |= MLX5_FLOW_ACTION_MARK |
7318 MLX5_FLOW_ACTION_MARK_EXT;
7319 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7320 modify_after_mirror = 1;
7322 action_flags |= MLX5_FLOW_ACTION_MARK;
7325 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7327 case RTE_FLOW_ACTION_TYPE_SET_META:
7328 ret = flow_dv_validate_action_set_meta(dev, actions,
7333 /* Count all modify-header actions as one action. */
7334 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7336 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7337 modify_after_mirror = 1;
7338 action_flags |= MLX5_FLOW_ACTION_SET_META;
7339 rw_act_num += MLX5_ACT_NUM_SET_META;
7341 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7342 ret = flow_dv_validate_action_set_tag(dev, actions,
7347 /* Count all modify-header actions as one action. */
7348 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7350 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7351 modify_after_mirror = 1;
7352 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7353 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7355 case RTE_FLOW_ACTION_TYPE_DROP:
7356 ret = mlx5_flow_validate_action_drop(action_flags,
7360 action_flags |= MLX5_FLOW_ACTION_DROP;
7363 case RTE_FLOW_ACTION_TYPE_QUEUE:
7364 ret = mlx5_flow_validate_action_queue(actions,
7369 queue_index = ((const struct rte_flow_action_queue *)
7370 (actions->conf))->index;
7371 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7374 case RTE_FLOW_ACTION_TYPE_RSS:
7375 rss = actions->conf;
7376 ret = mlx5_flow_validate_action_rss(actions,
7382 if (rss && sample_rss &&
7383 (sample_rss->level != rss->level ||
7384 sample_rss->types != rss->types))
7385 return rte_flow_error_set(error, ENOTSUP,
7386 RTE_FLOW_ERROR_TYPE_ACTION,
7388 "Can't use the different RSS types "
7389 "or level in the same flow");
7390 if (rss != NULL && rss->queue_num)
7391 queue_index = rss->queue[0];
7392 action_flags |= MLX5_FLOW_ACTION_RSS;
7395 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7397 mlx5_flow_validate_action_default_miss(action_flags,
7401 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7404 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7405 shared_count = true;
7407 case RTE_FLOW_ACTION_TYPE_COUNT:
7408 ret = flow_dv_validate_action_count(dev, shared_count,
7413 action_flags |= MLX5_FLOW_ACTION_COUNT;
7416 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7417 if (flow_dv_validate_action_pop_vlan(dev,
7423 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7424 modify_after_mirror = 1;
7425 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7428 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7429 ret = flow_dv_validate_action_push_vlan(dev,
7436 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7437 modify_after_mirror = 1;
7438 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7441 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7442 ret = flow_dv_validate_action_set_vlan_pcp
7443 (action_flags, actions, error);
7446 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7447 modify_after_mirror = 1;
7448 /* Count PCP with push_vlan command. */
7449 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7451 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7452 ret = flow_dv_validate_action_set_vlan_vid
7453 (item_flags, action_flags,
7457 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7458 modify_after_mirror = 1;
7459 /* Count VID with push_vlan command. */
7460 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7461 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7463 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7464 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7465 ret = flow_dv_validate_action_l2_encap(dev,
7471 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7474 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7475 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7476 ret = flow_dv_validate_action_decap(dev, action_flags,
7477 actions, item_flags,
7481 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7482 modify_after_mirror = 1;
7483 action_flags |= MLX5_FLOW_ACTION_DECAP;
7486 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7487 ret = flow_dv_validate_action_raw_encap_decap
7488 (dev, NULL, actions->conf, attr, &action_flags,
7489 &actions_n, actions, item_flags, error);
7493 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7494 decap = actions->conf;
7495 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7497 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7501 encap = actions->conf;
7503 ret = flow_dv_validate_action_raw_encap_decap
7505 decap ? decap : &empty_decap, encap,
7506 attr, &action_flags, &actions_n,
7507 actions, item_flags, error);
7510 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7511 (action_flags & MLX5_FLOW_ACTION_DECAP))
7512 modify_after_mirror = 1;
7514 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7515 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7516 ret = flow_dv_validate_action_modify_mac(action_flags,
7522 /* Count all modify-header actions as one action. */
7523 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7525 action_flags |= actions->type ==
7526 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7527 MLX5_FLOW_ACTION_SET_MAC_SRC :
7528 MLX5_FLOW_ACTION_SET_MAC_DST;
7529 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7530 modify_after_mirror = 1;
7532 * Even if the source and destination MAC addresses have
7533 * overlap in the header with 4B alignment, the convert
7534 * function will handle them separately and 4 SW actions
7535 * will be created. And 2 actions will be added each
7536 * time no matter how many bytes of address will be set.
7538 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7540 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7541 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7542 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7548 /* Count all modify-header actions as one action. */
7549 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7551 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7552 modify_after_mirror = 1;
7553 action_flags |= actions->type ==
7554 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7555 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7556 MLX5_FLOW_ACTION_SET_IPV4_DST;
7557 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7559 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7560 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7561 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7567 if (item_ipv6_proto == IPPROTO_ICMPV6)
7568 return rte_flow_error_set(error, ENOTSUP,
7569 RTE_FLOW_ERROR_TYPE_ACTION,
7571 "Can't change header "
7572 "with ICMPv6 proto");
7573 /* Count all modify-header actions as one action. */
7574 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7576 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7577 modify_after_mirror = 1;
7578 action_flags |= actions->type ==
7579 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7580 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7581 MLX5_FLOW_ACTION_SET_IPV6_DST;
7582 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7584 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7585 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7586 ret = flow_dv_validate_action_modify_tp(action_flags,
7592 /* Count all modify-header actions as one action. */
7593 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7595 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7596 modify_after_mirror = 1;
7597 action_flags |= actions->type ==
7598 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7599 MLX5_FLOW_ACTION_SET_TP_SRC :
7600 MLX5_FLOW_ACTION_SET_TP_DST;
7601 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7603 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7604 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7605 ret = flow_dv_validate_action_modify_ttl(action_flags,
7611 /* Count all modify-header actions as one action. */
7612 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7614 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7615 modify_after_mirror = 1;
7616 action_flags |= actions->type ==
7617 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7618 MLX5_FLOW_ACTION_SET_TTL :
7619 MLX5_FLOW_ACTION_DEC_TTL;
7620 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7622 case RTE_FLOW_ACTION_TYPE_JUMP:
7623 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7629 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7631 return rte_flow_error_set(error, EINVAL,
7632 RTE_FLOW_ERROR_TYPE_ACTION,
7634 "sample and jump action combination is not supported");
7636 action_flags |= MLX5_FLOW_ACTION_JUMP;
7638 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7639 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7640 ret = flow_dv_validate_action_modify_tcp_seq
7647 /* Count all modify-header actions as one action. */
7648 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7650 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7651 modify_after_mirror = 1;
7652 action_flags |= actions->type ==
7653 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7654 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7655 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7656 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7658 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7659 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7660 ret = flow_dv_validate_action_modify_tcp_ack
7667 /* Count all modify-header actions as one action. */
7668 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7670 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7671 modify_after_mirror = 1;
7672 action_flags |= actions->type ==
7673 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7674 MLX5_FLOW_ACTION_INC_TCP_ACK :
7675 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7676 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7678 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7680 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7681 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7682 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7684 case RTE_FLOW_ACTION_TYPE_METER:
7685 ret = mlx5_flow_validate_action_meter(dev,
7693 action_flags |= MLX5_FLOW_ACTION_METER;
7696 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7698 /* Meter action will add one more TAG action. */
7699 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7701 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7702 if (!attr->transfer && !attr->group)
7703 return rte_flow_error_set(error, ENOTSUP,
7704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7706 "Shared ASO age action is not supported for group 0");
7707 if (action_flags & MLX5_FLOW_ACTION_AGE)
7708 return rte_flow_error_set
7710 RTE_FLOW_ERROR_TYPE_ACTION,
7712 "duplicate age actions set");
7713 action_flags |= MLX5_FLOW_ACTION_AGE;
7716 case RTE_FLOW_ACTION_TYPE_AGE:
7717 ret = flow_dv_validate_action_age(action_flags,
7723 * Validate the regular AGE action (using counter)
7724 * mutual exclusion with share counter actions.
7726 if (!priv->sh->flow_hit_aso_en) {
7728 return rte_flow_error_set
7730 RTE_FLOW_ERROR_TYPE_ACTION,
7732 "old age and shared count combination is not supported");
7734 return rte_flow_error_set
7736 RTE_FLOW_ERROR_TYPE_ACTION,
7738 "old age action and count must be in the same sub flow");
7740 action_flags |= MLX5_FLOW_ACTION_AGE;
7743 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7744 ret = flow_dv_validate_action_modify_ipv4_dscp
7751 /* Count all modify-header actions as one action. */
7752 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7754 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7755 modify_after_mirror = 1;
7756 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7757 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7759 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7760 ret = flow_dv_validate_action_modify_ipv6_dscp
7767 /* Count all modify-header actions as one action. */
7768 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7770 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7771 modify_after_mirror = 1;
7772 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7773 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7775 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7776 ret = flow_dv_validate_action_sample(&action_flags,
7785 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7788 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7789 ret = flow_dv_validate_action_modify_field(dev,
7796 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7797 modify_after_mirror = 1;
7798 /* Count all modify-header actions as one action. */
7799 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7801 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7804 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7805 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7810 action_flags |= MLX5_FLOW_ACTION_CT;
7812 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7813 /* tunnel offload action was processed before
7814 * list it here as a supported type
7818 return rte_flow_error_set(error, ENOTSUP,
7819 RTE_FLOW_ERROR_TYPE_ACTION,
7821 "action not supported");
7825 * Validate actions in flow rules
7826 * - Explicit decap action is prohibited by the tunnel offload API.
7827 * - Drop action in tunnel steer rule is prohibited by the API.
7828 * - Application cannot use MARK action because it's value can mask
7829 * tunnel default miss nitification.
7830 * - JUMP in tunnel match rule has no support in current PMD
7832 * - TAG & META are reserved for future uses.
7834 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7835 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7836 MLX5_FLOW_ACTION_MARK |
7837 MLX5_FLOW_ACTION_SET_TAG |
7838 MLX5_FLOW_ACTION_SET_META |
7839 MLX5_FLOW_ACTION_DROP;
7841 if (action_flags & bad_actions_mask)
7842 return rte_flow_error_set
7844 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7845 "Invalid RTE action in tunnel "
7847 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7848 return rte_flow_error_set
7850 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7851 "tunnel set decap rule must terminate "
7854 return rte_flow_error_set
7856 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7857 "tunnel flows for ingress traffic only");
7859 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7860 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7861 MLX5_FLOW_ACTION_MARK |
7862 MLX5_FLOW_ACTION_SET_TAG |
7863 MLX5_FLOW_ACTION_SET_META;
7865 if (action_flags & bad_actions_mask)
7866 return rte_flow_error_set
7868 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7869 "Invalid RTE action in tunnel "
7873 * Validate the drop action mutual exclusion with other actions.
7874 * Drop action is mutually-exclusive with any other action, except for
7876 * Drop action compatibility with tunnel offload was already validated.
7878 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7879 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7880 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7881 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7882 return rte_flow_error_set(error, EINVAL,
7883 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7884 "Drop action is mutually-exclusive "
7885 "with any other action, except for "
7887 /* Eswitch has few restrictions on using items and actions */
7888 if (attr->transfer) {
7889 if (!mlx5_flow_ext_mreg_supported(dev) &&
7890 action_flags & MLX5_FLOW_ACTION_FLAG)
7891 return rte_flow_error_set(error, ENOTSUP,
7892 RTE_FLOW_ERROR_TYPE_ACTION,
7894 "unsupported action FLAG");
7895 if (!mlx5_flow_ext_mreg_supported(dev) &&
7896 action_flags & MLX5_FLOW_ACTION_MARK)
7897 return rte_flow_error_set(error, ENOTSUP,
7898 RTE_FLOW_ERROR_TYPE_ACTION,
7900 "unsupported action MARK");
7901 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7902 return rte_flow_error_set(error, ENOTSUP,
7903 RTE_FLOW_ERROR_TYPE_ACTION,
7905 "unsupported action QUEUE");
7906 if (action_flags & MLX5_FLOW_ACTION_RSS)
7907 return rte_flow_error_set(error, ENOTSUP,
7908 RTE_FLOW_ERROR_TYPE_ACTION,
7910 "unsupported action RSS");
7911 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7912 return rte_flow_error_set(error, EINVAL,
7913 RTE_FLOW_ERROR_TYPE_ACTION,
7915 "no fate action is found");
7917 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7918 return rte_flow_error_set(error, EINVAL,
7919 RTE_FLOW_ERROR_TYPE_ACTION,
7921 "no fate action is found");
7924 * Continue validation for Xcap and VLAN actions.
7925 * If hairpin is working in explicit TX rule mode, there is no actions
7926 * splitting and the validation of hairpin ingress flow should be the
7927 * same as other standard flows.
7929 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7930 MLX5_FLOW_VLAN_ACTIONS)) &&
7931 (queue_index == 0xFFFF ||
7932 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7933 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7934 conf->tx_explicit != 0))) {
7935 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7936 MLX5_FLOW_XCAP_ACTIONS)
7937 return rte_flow_error_set(error, ENOTSUP,
7938 RTE_FLOW_ERROR_TYPE_ACTION,
7939 NULL, "encap and decap "
7940 "combination aren't supported");
7941 if (!attr->transfer && attr->ingress) {
7942 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7943 return rte_flow_error_set
7945 RTE_FLOW_ERROR_TYPE_ACTION,
7946 NULL, "encap is not supported"
7947 " for ingress traffic");
7948 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7949 return rte_flow_error_set
7951 RTE_FLOW_ERROR_TYPE_ACTION,
7952 NULL, "push VLAN action not "
7953 "supported for ingress");
7954 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7955 MLX5_FLOW_VLAN_ACTIONS)
7956 return rte_flow_error_set
7958 RTE_FLOW_ERROR_TYPE_ACTION,
7959 NULL, "no support for "
7960 "multiple VLAN actions");
7963 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7964 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7965 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7967 return rte_flow_error_set
7969 RTE_FLOW_ERROR_TYPE_ACTION,
7970 NULL, "fate action not supported for "
7971 "meter with policy");
7973 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7974 return rte_flow_error_set
7976 RTE_FLOW_ERROR_TYPE_ACTION,
7977 NULL, "modify header action in egress "
7978 "cannot be done before meter action");
7979 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7980 return rte_flow_error_set
7982 RTE_FLOW_ERROR_TYPE_ACTION,
7983 NULL, "encap action in egress "
7984 "cannot be done before meter action");
7985 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7986 return rte_flow_error_set
7988 RTE_FLOW_ERROR_TYPE_ACTION,
7989 NULL, "push vlan action in egress "
7990 "cannot be done before meter action");
7994 * Hairpin flow will add one more TAG action in TX implicit mode.
7995 * In TX explicit mode, there will be no hairpin flow ID.
7998 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7999 /* extra metadata enabled: one more TAG action will be add. */
8000 if (dev_conf->dv_flow_en &&
8001 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8002 mlx5_flow_ext_mreg_supported(dev))
8003 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8005 flow_dv_modify_hdr_action_max(dev, is_root)) {
8006 return rte_flow_error_set(error, ENOTSUP,
8007 RTE_FLOW_ERROR_TYPE_ACTION,
8008 NULL, "too many header modify"
8009 " actions to support");
8011 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8012 if (fdb_mirror_limit && modify_after_mirror)
8013 return rte_flow_error_set(error, EINVAL,
8014 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8015 "sample before modify action is not supported");
8020 * Internal preparation function. Allocates the DV flow size,
8021 * this size is constant.
8024 * Pointer to the rte_eth_dev structure.
8026 * Pointer to the flow attributes.
8028 * Pointer to the list of items.
8029 * @param[in] actions
8030 * Pointer to the list of actions.
8032 * Pointer to the error structure.
8035 * Pointer to mlx5_flow object on success,
8036 * otherwise NULL and rte_errno is set.
8038 static struct mlx5_flow *
8039 flow_dv_prepare(struct rte_eth_dev *dev,
8040 const struct rte_flow_attr *attr __rte_unused,
8041 const struct rte_flow_item items[] __rte_unused,
8042 const struct rte_flow_action actions[] __rte_unused,
8043 struct rte_flow_error *error)
8045 uint32_t handle_idx = 0;
8046 struct mlx5_flow *dev_flow;
8047 struct mlx5_flow_handle *dev_handle;
8048 struct mlx5_priv *priv = dev->data->dev_private;
8049 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8052 wks->skip_matcher_reg = 0;
8054 wks->final_policy = NULL;
8055 /* In case of corrupting the memory. */
8056 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8057 rte_flow_error_set(error, ENOSPC,
8058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8059 "not free temporary device flow");
8062 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8065 rte_flow_error_set(error, ENOMEM,
8066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8067 "not enough memory to create flow handle");
8070 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8071 dev_flow = &wks->flows[wks->flow_idx++];
8072 memset(dev_flow, 0, sizeof(*dev_flow));
8073 dev_flow->handle = dev_handle;
8074 dev_flow->handle_idx = handle_idx;
8075 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8076 dev_flow->ingress = attr->ingress;
8077 dev_flow->dv.transfer = attr->transfer;
8081 #ifdef RTE_LIBRTE_MLX5_DEBUG
8083 * Sanity check for match mask and value. Similar to check_valid_spec() in
8084 * kernel driver. If unmasked bit is present in value, it returns failure.
8087 * pointer to match mask buffer.
8088 * @param match_value
8089 * pointer to match value buffer.
8092 * 0 if valid, -EINVAL otherwise.
8095 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8097 uint8_t *m = match_mask;
8098 uint8_t *v = match_value;
8101 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8104 "match_value differs from match_criteria"
8105 " %p[%u] != %p[%u]",
8106 match_value, i, match_mask, i);
8115 * Add match of ip_version.
8119 * @param[in] headers_v
8120 * Values header pointer.
8121 * @param[in] headers_m
8122 * Masks header pointer.
8123 * @param[in] ip_version
8124 * The IP version to set.
8127 flow_dv_set_match_ip_version(uint32_t group,
8133 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8135 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8137 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8138 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8139 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8143 * Add Ethernet item to matcher and to the value.
8145 * @param[in, out] matcher
8147 * @param[in, out] key
8148 * Flow matcher value.
8150 * Flow pattern to translate.
8152 * Item is inner pattern.
8155 flow_dv_translate_item_eth(void *matcher, void *key,
8156 const struct rte_flow_item *item, int inner,
8159 const struct rte_flow_item_eth *eth_m = item->mask;
8160 const struct rte_flow_item_eth *eth_v = item->spec;
8161 const struct rte_flow_item_eth nic_mask = {
8162 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8163 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8164 .type = RTE_BE16(0xffff),
8177 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8179 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8181 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8183 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8185 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8186 ð_m->dst, sizeof(eth_m->dst));
8187 /* The value must be in the range of the mask. */
8188 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8189 for (i = 0; i < sizeof(eth_m->dst); ++i)
8190 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8191 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8192 ð_m->src, sizeof(eth_m->src));
8193 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8194 /* The value must be in the range of the mask. */
8195 for (i = 0; i < sizeof(eth_m->dst); ++i)
8196 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8198 * HW supports match on one Ethertype, the Ethertype following the last
8199 * VLAN tag of the packet (see PRM).
8200 * Set match on ethertype only if ETH header is not followed by VLAN.
8201 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8202 * ethertype, and use ip_version field instead.
8203 * eCPRI over Ether layer will use type value 0xAEFE.
8205 if (eth_m->type == 0xFFFF) {
8206 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8207 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8208 switch (eth_v->type) {
8209 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8210 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8212 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8213 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8214 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8216 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8217 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8219 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8220 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8226 if (eth_m->has_vlan) {
8227 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8228 if (eth_v->has_vlan) {
8230 * Here, when also has_more_vlan field in VLAN item is
8231 * not set, only single-tagged packets will be matched.
8233 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8237 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8238 rte_be_to_cpu_16(eth_m->type));
8239 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8240 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8244 * Add VLAN item to matcher and to the value.
8246 * @param[in, out] dev_flow
8248 * @param[in, out] matcher
8250 * @param[in, out] key
8251 * Flow matcher value.
8253 * Flow pattern to translate.
8255 * Item is inner pattern.
8258 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8259 void *matcher, void *key,
8260 const struct rte_flow_item *item,
8261 int inner, uint32_t group)
8263 const struct rte_flow_item_vlan *vlan_m = item->mask;
8264 const struct rte_flow_item_vlan *vlan_v = item->spec;
8271 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8273 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8275 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8277 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8279 * This is workaround, masks are not supported,
8280 * and pre-validated.
8283 dev_flow->handle->vf_vlan.tag =
8284 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8287 * When VLAN item exists in flow, mark packet as tagged,
8288 * even if TCI is not specified.
8290 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8291 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8292 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8297 vlan_m = &rte_flow_item_vlan_mask;
8298 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8299 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8300 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8301 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8302 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8303 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8304 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8305 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8307 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8308 * ethertype, and use ip_version field instead.
8310 if (vlan_m->inner_type == 0xFFFF) {
8311 switch (vlan_v->inner_type) {
8312 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8313 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8314 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8315 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8317 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8318 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8320 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8321 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8327 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8328 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8329 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8330 /* Only one vlan_tag bit can be set. */
8331 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8334 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8335 rte_be_to_cpu_16(vlan_m->inner_type));
8336 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8337 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8341 * Add IPV4 item to matcher and to the value.
8343 * @param[in, out] matcher
8345 * @param[in, out] key
8346 * Flow matcher value.
8348 * Flow pattern to translate.
8350 * Item is inner pattern.
8352 * The group to insert the rule.
8355 flow_dv_translate_item_ipv4(void *matcher, void *key,
8356 const struct rte_flow_item *item,
8357 int inner, uint32_t group)
8359 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8360 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8361 const struct rte_flow_item_ipv4 nic_mask = {
8363 .src_addr = RTE_BE32(0xffffffff),
8364 .dst_addr = RTE_BE32(0xffffffff),
8365 .type_of_service = 0xff,
8366 .next_proto_id = 0xff,
8367 .time_to_live = 0xff,
8374 uint8_t tos, ihl_m, ihl_v;
8377 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8379 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8381 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8383 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8385 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8390 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8391 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8392 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8393 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8394 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8395 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8396 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8397 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8398 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8399 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8400 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8401 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8402 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8403 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8404 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8405 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8406 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8407 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8408 ipv4_m->hdr.type_of_service);
8409 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8410 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8411 ipv4_m->hdr.type_of_service >> 2);
8412 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8413 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8414 ipv4_m->hdr.next_proto_id);
8415 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8416 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8417 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8418 ipv4_m->hdr.time_to_live);
8419 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8420 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8421 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8422 !!(ipv4_m->hdr.fragment_offset));
8423 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8424 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8428 * Add IPV6 item to matcher and to the value.
8430 * @param[in, out] matcher
8432 * @param[in, out] key
8433 * Flow matcher value.
8435 * Flow pattern to translate.
8437 * Item is inner pattern.
8439 * The group to insert the rule.
8442 flow_dv_translate_item_ipv6(void *matcher, void *key,
8443 const struct rte_flow_item *item,
8444 int inner, uint32_t group)
8446 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8447 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8448 const struct rte_flow_item_ipv6 nic_mask = {
8451 "\xff\xff\xff\xff\xff\xff\xff\xff"
8452 "\xff\xff\xff\xff\xff\xff\xff\xff",
8454 "\xff\xff\xff\xff\xff\xff\xff\xff"
8455 "\xff\xff\xff\xff\xff\xff\xff\xff",
8456 .vtc_flow = RTE_BE32(0xffffffff),
8463 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8464 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8473 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8475 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8477 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8479 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8481 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8486 size = sizeof(ipv6_m->hdr.dst_addr);
8487 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8488 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8489 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8490 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8491 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8492 for (i = 0; i < size; ++i)
8493 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8494 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8495 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8496 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8497 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8498 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8499 for (i = 0; i < size; ++i)
8500 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8502 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8503 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8504 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8505 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8506 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8510 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8512 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8515 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8517 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8521 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8523 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8524 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8526 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8527 ipv6_m->hdr.hop_limits);
8528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8529 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8531 !!(ipv6_m->has_frag_ext));
8532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8533 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8537 * Add IPV6 fragment extension item to matcher and to the value.
8539 * @param[in, out] matcher
8541 * @param[in, out] key
8542 * Flow matcher value.
8544 * Flow pattern to translate.
8546 * Item is inner pattern.
8549 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8550 const struct rte_flow_item *item,
8553 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8554 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8555 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8557 .next_header = 0xff,
8558 .frag_data = RTE_BE16(0xffff),
8565 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8567 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8569 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8571 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8573 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8574 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8576 if (!ipv6_frag_ext_v)
8578 if (!ipv6_frag_ext_m)
8579 ipv6_frag_ext_m = &nic_mask;
8580 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8581 ipv6_frag_ext_m->hdr.next_header);
8582 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8583 ipv6_frag_ext_v->hdr.next_header &
8584 ipv6_frag_ext_m->hdr.next_header);
8588 * Add TCP item to matcher and to the value.
8590 * @param[in, out] matcher
8592 * @param[in, out] key
8593 * Flow matcher value.
8595 * Flow pattern to translate.
8597 * Item is inner pattern.
8600 flow_dv_translate_item_tcp(void *matcher, void *key,
8601 const struct rte_flow_item *item,
8604 const struct rte_flow_item_tcp *tcp_m = item->mask;
8605 const struct rte_flow_item_tcp *tcp_v = item->spec;
8610 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8612 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8614 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8616 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8618 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8619 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8623 tcp_m = &rte_flow_item_tcp_mask;
8624 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8625 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8626 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8627 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8628 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8629 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8630 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8631 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8632 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8633 tcp_m->hdr.tcp_flags);
8634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8635 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8639 * Add UDP item to matcher and to the value.
8641 * @param[in, out] matcher
8643 * @param[in, out] key
8644 * Flow matcher value.
8646 * Flow pattern to translate.
8648 * Item is inner pattern.
8651 flow_dv_translate_item_udp(void *matcher, void *key,
8652 const struct rte_flow_item *item,
8655 const struct rte_flow_item_udp *udp_m = item->mask;
8656 const struct rte_flow_item_udp *udp_v = item->spec;
8661 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8663 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8665 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8667 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8674 udp_m = &rte_flow_item_udp_mask;
8675 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8676 rte_be_to_cpu_16(udp_m->hdr.src_port));
8677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8678 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8680 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8682 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8686 * Add GRE optional Key item to matcher and to the value.
8688 * @param[in, out] matcher
8690 * @param[in, out] key
8691 * Flow matcher value.
8693 * Flow pattern to translate.
8695 * Item is inner pattern.
8698 flow_dv_translate_item_gre_key(void *matcher, void *key,
8699 const struct rte_flow_item *item)
8701 const rte_be32_t *key_m = item->mask;
8702 const rte_be32_t *key_v = item->spec;
8703 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8704 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8705 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8707 /* GRE K bit must be on and should already be validated */
8708 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8709 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8713 key_m = &gre_key_default_mask;
8714 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8715 rte_be_to_cpu_32(*key_m) >> 8);
8716 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8717 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8718 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8719 rte_be_to_cpu_32(*key_m) & 0xFF);
8720 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8721 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8725 * Add GRE item to matcher and to the value.
8727 * @param[in, out] matcher
8729 * @param[in, out] key
8730 * Flow matcher value.
8732 * Flow pattern to translate.
8733 * @param[in] pattern_flags
8734 * Accumulated pattern flags.
8737 flow_dv_translate_item_gre(void *matcher, void *key,
8738 const struct rte_flow_item *item,
8739 uint64_t pattern_flags)
8741 static const struct rte_flow_item_gre empty_gre = {0,};
8742 const struct rte_flow_item_gre *gre_m = item->mask;
8743 const struct rte_flow_item_gre *gre_v = item->spec;
8744 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8745 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8746 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8747 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8754 uint16_t s_present:1;
8755 uint16_t k_present:1;
8756 uint16_t rsvd_bit1:1;
8757 uint16_t c_present:1;
8761 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8762 uint16_t protocol_m, protocol_v;
8764 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8765 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8771 gre_m = &rte_flow_item_gre_mask;
8773 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8774 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8775 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8776 gre_crks_rsvd0_ver_m.c_present);
8777 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8778 gre_crks_rsvd0_ver_v.c_present &
8779 gre_crks_rsvd0_ver_m.c_present);
8780 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8781 gre_crks_rsvd0_ver_m.k_present);
8782 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8783 gre_crks_rsvd0_ver_v.k_present &
8784 gre_crks_rsvd0_ver_m.k_present);
8785 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8786 gre_crks_rsvd0_ver_m.s_present);
8787 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8788 gre_crks_rsvd0_ver_v.s_present &
8789 gre_crks_rsvd0_ver_m.s_present);
8790 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8791 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8793 /* Force next protocol to prevent matchers duplication */
8794 protocol_m = 0xFFFF;
8795 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8797 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8798 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8799 protocol_m & protocol_v);
8803 * Add NVGRE item to matcher and to the value.
8805 * @param[in, out] matcher
8807 * @param[in, out] key
8808 * Flow matcher value.
8810 * Flow pattern to translate.
8811 * @param[in] pattern_flags
8812 * Accumulated pattern flags.
8815 flow_dv_translate_item_nvgre(void *matcher, void *key,
8816 const struct rte_flow_item *item,
8817 unsigned long pattern_flags)
8819 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8820 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8821 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8822 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8823 const char *tni_flow_id_m;
8824 const char *tni_flow_id_v;
8830 /* For NVGRE, GRE header fields must be set with defined values. */
8831 const struct rte_flow_item_gre gre_spec = {
8832 .c_rsvd0_ver = RTE_BE16(0x2000),
8833 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8835 const struct rte_flow_item_gre gre_mask = {
8836 .c_rsvd0_ver = RTE_BE16(0xB000),
8837 .protocol = RTE_BE16(UINT16_MAX),
8839 const struct rte_flow_item gre_item = {
8844 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
8848 nvgre_m = &rte_flow_item_nvgre_mask;
8849 tni_flow_id_m = (const char *)nvgre_m->tni;
8850 tni_flow_id_v = (const char *)nvgre_v->tni;
8851 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8852 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8853 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8854 memcpy(gre_key_m, tni_flow_id_m, size);
8855 for (i = 0; i < size; ++i)
8856 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8860 * Add VXLAN item to matcher and to the value.
8863 * Pointer to the Ethernet device structure.
8865 * Flow rule attributes.
8866 * @param[in, out] matcher
8868 * @param[in, out] key
8869 * Flow matcher value.
8871 * Flow pattern to translate.
8873 * Item is inner pattern.
8876 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8877 const struct rte_flow_attr *attr,
8878 void *matcher, void *key,
8879 const struct rte_flow_item *item,
8882 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8883 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8888 uint32_t *tunnel_header_v;
8889 uint32_t *tunnel_header_m;
8891 struct mlx5_priv *priv = dev->data->dev_private;
8892 const struct rte_flow_item_vxlan nic_mask = {
8893 .vni = "\xff\xff\xff",
8898 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8900 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8902 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8904 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8906 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8907 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8908 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8909 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8910 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8912 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8916 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8917 (attr->group && !priv->sh->misc5_cap))
8918 vxlan_m = &rte_flow_item_vxlan_mask;
8920 vxlan_m = &nic_mask;
8922 if ((priv->sh->steering_format_version ==
8923 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8924 dport != MLX5_UDP_PORT_VXLAN) ||
8925 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8926 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8933 misc_m = MLX5_ADDR_OF(fte_match_param,
8934 matcher, misc_parameters);
8935 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8936 size = sizeof(vxlan_m->vni);
8937 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8938 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8939 memcpy(vni_m, vxlan_m->vni, size);
8940 for (i = 0; i < size; ++i)
8941 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8944 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8945 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8946 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8949 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8952 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8953 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8954 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8955 if (*tunnel_header_v)
8956 *tunnel_header_m = vxlan_m->vni[0] |
8957 vxlan_m->vni[1] << 8 |
8958 vxlan_m->vni[2] << 16;
8960 *tunnel_header_m = 0x0;
8961 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8962 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8963 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8967 * Add VXLAN-GPE item to matcher and to the value.
8969 * @param[in, out] matcher
8971 * @param[in, out] key
8972 * Flow matcher value.
8974 * Flow pattern to translate.
8976 * Item is inner pattern.
8980 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8981 const struct rte_flow_item *item,
8982 const uint64_t pattern_flags)
8984 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
8985 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8986 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8987 /* The item was validated to be on the outer side */
8988 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8989 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8991 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8993 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8995 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8997 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8998 int i, size = sizeof(vxlan_m->vni);
8999 uint8_t flags_m = 0xff;
9000 uint8_t flags_v = 0xc;
9001 uint8_t m_protocol, v_protocol;
9003 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9004 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9005 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9006 MLX5_UDP_PORT_VXLAN_GPE);
9009 vxlan_v = &dummy_vxlan_gpe_hdr;
9010 vxlan_m = &dummy_vxlan_gpe_hdr;
9013 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9015 memcpy(vni_m, vxlan_m->vni, size);
9016 for (i = 0; i < size; ++i)
9017 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9018 if (vxlan_m->flags) {
9019 flags_m = vxlan_m->flags;
9020 flags_v = vxlan_v->flags;
9022 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9023 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9024 m_protocol = vxlan_m->protocol;
9025 v_protocol = vxlan_v->protocol;
9028 /* Force next protocol to ensure next headers parsing. */
9029 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9030 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9031 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9032 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9033 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9034 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9036 MLX5_SET(fte_match_set_misc3, misc_m,
9037 outer_vxlan_gpe_next_protocol, m_protocol);
9038 MLX5_SET(fte_match_set_misc3, misc_v,
9039 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9043 * Add Geneve item to matcher and to the value.
9045 * @param[in, out] matcher
9047 * @param[in, out] key
9048 * Flow matcher value.
9050 * Flow pattern to translate.
9052 * Item is inner pattern.
9056 flow_dv_translate_item_geneve(void *matcher, void *key,
9057 const struct rte_flow_item *item,
9058 uint64_t pattern_flags)
9060 static const struct rte_flow_item_geneve empty_geneve = {0,};
9061 const struct rte_flow_item_geneve *geneve_m = item->mask;
9062 const struct rte_flow_item_geneve *geneve_v = item->spec;
9063 /* GENEVE flow item validation allows single tunnel item */
9064 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9065 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9066 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9067 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9070 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9071 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9072 size_t size = sizeof(geneve_m->vni), i;
9073 uint16_t protocol_m, protocol_v;
9075 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9076 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9077 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9078 MLX5_UDP_PORT_GENEVE);
9081 geneve_v = &empty_geneve;
9082 geneve_m = &empty_geneve;
9085 geneve_m = &rte_flow_item_geneve_mask;
9087 memcpy(vni_m, geneve_m->vni, size);
9088 for (i = 0; i < size; ++i)
9089 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9090 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9091 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9092 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9093 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9094 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9095 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9096 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9097 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9098 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9099 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9100 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9101 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9102 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9104 /* Force next protocol to prevent matchers duplication */
9105 protocol_m = 0xFFFF;
9106 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9108 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9109 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9110 protocol_m & protocol_v);
9114 * Create Geneve TLV option resource.
9116 * @param dev[in, out]
9117 * Pointer to rte_eth_dev structure.
9118 * @param[in, out] tag_be24
9119 * Tag value in big endian then R-shift 8.
9120 * @parm[in, out] dev_flow
9121 * Pointer to the dev_flow.
9123 * pointer to error structure.
9126 * 0 on success otherwise -errno and errno is set.
9130 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9131 const struct rte_flow_item *item,
9132 struct rte_flow_error *error)
9134 struct mlx5_priv *priv = dev->data->dev_private;
9135 struct mlx5_dev_ctx_shared *sh = priv->sh;
9136 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9137 sh->geneve_tlv_option_resource;
9138 struct mlx5_devx_obj *obj;
9139 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9144 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9145 if (geneve_opt_resource != NULL) {
9146 if (geneve_opt_resource->option_class ==
9147 geneve_opt_v->option_class &&
9148 geneve_opt_resource->option_type ==
9149 geneve_opt_v->option_type &&
9150 geneve_opt_resource->length ==
9151 geneve_opt_v->option_len) {
9152 /* We already have GENVE TLV option obj allocated. */
9153 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9156 ret = rte_flow_error_set(error, ENOMEM,
9157 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9158 "Only one GENEVE TLV option supported");
9162 /* Create a GENEVE TLV object and resource. */
9163 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9164 geneve_opt_v->option_class,
9165 geneve_opt_v->option_type,
9166 geneve_opt_v->option_len);
9168 ret = rte_flow_error_set(error, ENODATA,
9169 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9170 "Failed to create GENEVE TLV Devx object");
9173 sh->geneve_tlv_option_resource =
9174 mlx5_malloc(MLX5_MEM_ZERO,
9175 sizeof(*geneve_opt_resource),
9177 if (!sh->geneve_tlv_option_resource) {
9178 claim_zero(mlx5_devx_cmd_destroy(obj));
9179 ret = rte_flow_error_set(error, ENOMEM,
9180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9181 "GENEVE TLV object memory allocation failed");
9184 geneve_opt_resource = sh->geneve_tlv_option_resource;
9185 geneve_opt_resource->obj = obj;
9186 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9187 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9188 geneve_opt_resource->length = geneve_opt_v->option_len;
9189 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9193 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9198 * Add Geneve TLV option item to matcher.
9200 * @param[in, out] dev
9201 * Pointer to rte_eth_dev structure.
9202 * @param[in, out] matcher
9204 * @param[in, out] key
9205 * Flow matcher value.
9207 * Flow pattern to translate.
9209 * Pointer to error structure.
9212 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9213 void *key, const struct rte_flow_item *item,
9214 struct rte_flow_error *error)
9216 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9217 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9218 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9219 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9220 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9222 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9223 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9229 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9230 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9233 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9237 * Set the option length in GENEVE header if not requested.
9238 * The GENEVE TLV option length is expressed by the option length field
9239 * in the GENEVE header.
9240 * If the option length was not requested but the GENEVE TLV option item
9241 * is present we set the option length field implicitly.
9243 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9244 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9245 MLX5_GENEVE_OPTLEN_MASK);
9246 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9247 geneve_opt_v->option_len + 1);
9249 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9250 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9252 if (geneve_opt_v->data) {
9253 memcpy(&opt_data_key, geneve_opt_v->data,
9254 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9255 sizeof(opt_data_key)));
9256 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9257 sizeof(opt_data_key));
9258 memcpy(&opt_data_mask, geneve_opt_m->data,
9259 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9260 sizeof(opt_data_mask)));
9261 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9262 sizeof(opt_data_mask));
9263 MLX5_SET(fte_match_set_misc3, misc3_m,
9264 geneve_tlv_option_0_data,
9265 rte_be_to_cpu_32(opt_data_mask));
9266 MLX5_SET(fte_match_set_misc3, misc3_v,
9267 geneve_tlv_option_0_data,
9268 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9274 * Add MPLS item to matcher and to the value.
9276 * @param[in, out] matcher
9278 * @param[in, out] key
9279 * Flow matcher value.
9281 * Flow pattern to translate.
9282 * @param[in] prev_layer
9283 * The protocol layer indicated in previous item.
9285 * Item is inner pattern.
9288 flow_dv_translate_item_mpls(void *matcher, void *key,
9289 const struct rte_flow_item *item,
9290 uint64_t prev_layer,
9293 const uint32_t *in_mpls_m = item->mask;
9294 const uint32_t *in_mpls_v = item->spec;
9295 uint32_t *out_mpls_m = 0;
9296 uint32_t *out_mpls_v = 0;
9297 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9298 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9299 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9301 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9302 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9303 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9305 switch (prev_layer) {
9306 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9307 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9308 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9309 MLX5_UDP_PORT_MPLS);
9311 case MLX5_FLOW_LAYER_GRE:
9313 case MLX5_FLOW_LAYER_GRE_KEY:
9314 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9315 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9316 RTE_ETHER_TYPE_MPLS);
9324 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9325 switch (prev_layer) {
9326 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9328 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9329 outer_first_mpls_over_udp);
9331 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9332 outer_first_mpls_over_udp);
9334 case MLX5_FLOW_LAYER_GRE:
9336 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9337 outer_first_mpls_over_gre);
9339 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9340 outer_first_mpls_over_gre);
9343 /* Inner MPLS not over GRE is not supported. */
9346 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9350 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9356 if (out_mpls_m && out_mpls_v) {
9357 *out_mpls_m = *in_mpls_m;
9358 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9363 * Add metadata register item to matcher
9365 * @param[in, out] matcher
9367 * @param[in, out] key
9368 * Flow matcher value.
9369 * @param[in] reg_type
9370 * Type of device metadata register
9377 flow_dv_match_meta_reg(void *matcher, void *key,
9378 enum modify_reg reg_type,
9379 uint32_t data, uint32_t mask)
9382 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9384 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9390 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9391 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9394 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9395 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9399 * The metadata register C0 field might be divided into
9400 * source vport index and META item value, we should set
9401 * this field according to specified mask, not as whole one.
9403 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9405 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9406 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9409 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9412 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9413 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9416 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9417 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9420 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9421 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9424 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9425 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9428 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9429 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9432 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9433 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9436 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9437 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9446 * Add MARK item to matcher
9449 * The device to configure through.
9450 * @param[in, out] matcher
9452 * @param[in, out] key
9453 * Flow matcher value.
9455 * Flow pattern to translate.
9458 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9459 void *matcher, void *key,
9460 const struct rte_flow_item *item)
9462 struct mlx5_priv *priv = dev->data->dev_private;
9463 const struct rte_flow_item_mark *mark;
9467 mark = item->mask ? (const void *)item->mask :
9468 &rte_flow_item_mark_mask;
9469 mask = mark->id & priv->sh->dv_mark_mask;
9470 mark = (const void *)item->spec;
9472 value = mark->id & priv->sh->dv_mark_mask & mask;
9474 enum modify_reg reg;
9476 /* Get the metadata register index for the mark. */
9477 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9478 MLX5_ASSERT(reg > 0);
9479 if (reg == REG_C_0) {
9480 struct mlx5_priv *priv = dev->data->dev_private;
9481 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9482 uint32_t shl_c0 = rte_bsf32(msk_c0);
9488 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9493 * Add META item to matcher
9496 * The devich to configure through.
9497 * @param[in, out] matcher
9499 * @param[in, out] key
9500 * Flow matcher value.
9502 * Attributes of flow that includes this item.
9504 * Flow pattern to translate.
9507 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9508 void *matcher, void *key,
9509 const struct rte_flow_attr *attr,
9510 const struct rte_flow_item *item)
9512 const struct rte_flow_item_meta *meta_m;
9513 const struct rte_flow_item_meta *meta_v;
9515 meta_m = (const void *)item->mask;
9517 meta_m = &rte_flow_item_meta_mask;
9518 meta_v = (const void *)item->spec;
9521 uint32_t value = meta_v->data;
9522 uint32_t mask = meta_m->data;
9524 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9527 MLX5_ASSERT(reg != REG_NON);
9528 if (reg == REG_C_0) {
9529 struct mlx5_priv *priv = dev->data->dev_private;
9530 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9531 uint32_t shl_c0 = rte_bsf32(msk_c0);
9537 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9542 * Add vport metadata Reg C0 item to matcher
9544 * @param[in, out] matcher
9546 * @param[in, out] key
9547 * Flow matcher value.
9549 * Flow pattern to translate.
9552 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9553 uint32_t value, uint32_t mask)
9555 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9559 * Add tag item to matcher
9562 * The devich to configure through.
9563 * @param[in, out] matcher
9565 * @param[in, out] key
9566 * Flow matcher value.
9568 * Flow pattern to translate.
9571 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9572 void *matcher, void *key,
9573 const struct rte_flow_item *item)
9575 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9576 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9577 uint32_t mask, value;
9580 value = tag_v->data;
9581 mask = tag_m ? tag_m->data : UINT32_MAX;
9582 if (tag_v->id == REG_C_0) {
9583 struct mlx5_priv *priv = dev->data->dev_private;
9584 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9585 uint32_t shl_c0 = rte_bsf32(msk_c0);
9591 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9595 * Add TAG item to matcher
9598 * The devich to configure through.
9599 * @param[in, out] matcher
9601 * @param[in, out] key
9602 * Flow matcher value.
9604 * Flow pattern to translate.
9607 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9608 void *matcher, void *key,
9609 const struct rte_flow_item *item)
9611 const struct rte_flow_item_tag *tag_v = item->spec;
9612 const struct rte_flow_item_tag *tag_m = item->mask;
9613 enum modify_reg reg;
9616 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9617 /* Get the metadata register index for the tag. */
9618 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9619 MLX5_ASSERT(reg > 0);
9620 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9624 * Add source vport match to the specified matcher.
9626 * @param[in, out] matcher
9628 * @param[in, out] key
9629 * Flow matcher value.
9631 * Source vport value to match
9636 flow_dv_translate_item_source_vport(void *matcher, void *key,
9637 int16_t port, uint16_t mask)
9639 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9640 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9642 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9643 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9647 * Translate port-id item to eswitch match on port-id.
9650 * The devich to configure through.
9651 * @param[in, out] matcher
9653 * @param[in, out] key
9654 * Flow matcher value.
9656 * Flow pattern to translate.
9661 * 0 on success, a negative errno value otherwise.
9664 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9665 void *key, const struct rte_flow_item *item,
9666 const struct rte_flow_attr *attr)
9668 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9669 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9670 struct mlx5_priv *priv;
9673 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9674 flow_dv_translate_item_source_vport(matcher, key,
9675 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9678 mask = pid_m ? pid_m->id : 0xffff;
9679 id = pid_v ? pid_v->id : dev->data->port_id;
9680 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9684 * Translate to vport field or to metadata, depending on mode.
9685 * Kernel can use either misc.source_port or half of C0 metadata
9688 if (priv->vport_meta_mask) {
9690 * Provide the hint for SW steering library
9691 * to insert the flow into ingress domain and
9692 * save the extra vport match.
9694 if (mask == 0xffff && priv->vport_id == 0xffff &&
9695 priv->pf_bond < 0 && attr->transfer)
9696 flow_dv_translate_item_source_vport
9697 (matcher, key, priv->vport_id, mask);
9699 * We should always set the vport metadata register,
9700 * otherwise the SW steering library can drop
9701 * the rule if wire vport metadata value is not zero,
9702 * it depends on kernel configuration.
9704 flow_dv_translate_item_meta_vport(matcher, key,
9705 priv->vport_meta_tag,
9706 priv->vport_meta_mask);
9708 flow_dv_translate_item_source_vport(matcher, key,
9709 priv->vport_id, mask);
9715 * Add ICMP6 item to matcher and to the value.
9717 * @param[in, out] matcher
9719 * @param[in, out] key
9720 * Flow matcher value.
9722 * Flow pattern to translate.
9724 * Item is inner pattern.
9727 flow_dv_translate_item_icmp6(void *matcher, void *key,
9728 const struct rte_flow_item *item,
9731 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9732 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9735 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9737 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9739 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9741 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9743 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9745 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9747 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9748 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9752 icmp6_m = &rte_flow_item_icmp6_mask;
9753 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9754 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9755 icmp6_v->type & icmp6_m->type);
9756 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9757 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9758 icmp6_v->code & icmp6_m->code);
9762 * Add ICMP item to matcher and to the value.
9764 * @param[in, out] matcher
9766 * @param[in, out] key
9767 * Flow matcher value.
9769 * Flow pattern to translate.
9771 * Item is inner pattern.
9774 flow_dv_translate_item_icmp(void *matcher, void *key,
9775 const struct rte_flow_item *item,
9778 const struct rte_flow_item_icmp *icmp_m = item->mask;
9779 const struct rte_flow_item_icmp *icmp_v = item->spec;
9780 uint32_t icmp_header_data_m = 0;
9781 uint32_t icmp_header_data_v = 0;
9784 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9786 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9788 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9790 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9792 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9794 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9796 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9797 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9801 icmp_m = &rte_flow_item_icmp_mask;
9802 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9803 icmp_m->hdr.icmp_type);
9804 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9805 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9806 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9807 icmp_m->hdr.icmp_code);
9808 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9809 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9810 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9811 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9812 if (icmp_header_data_m) {
9813 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9814 icmp_header_data_v |=
9815 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9816 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9817 icmp_header_data_m);
9818 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9819 icmp_header_data_v & icmp_header_data_m);
9824 * Add GTP item to matcher and to the value.
9826 * @param[in, out] matcher
9828 * @param[in, out] key
9829 * Flow matcher value.
9831 * Flow pattern to translate.
9833 * Item is inner pattern.
9836 flow_dv_translate_item_gtp(void *matcher, void *key,
9837 const struct rte_flow_item *item, int inner)
9839 const struct rte_flow_item_gtp *gtp_m = item->mask;
9840 const struct rte_flow_item_gtp *gtp_v = item->spec;
9843 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9845 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9846 uint16_t dport = RTE_GTPU_UDP_PORT;
9849 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9851 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9853 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9855 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9857 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9858 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9859 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9864 gtp_m = &rte_flow_item_gtp_mask;
9865 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9866 gtp_m->v_pt_rsv_flags);
9867 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9868 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9869 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9870 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9871 gtp_v->msg_type & gtp_m->msg_type);
9872 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9873 rte_be_to_cpu_32(gtp_m->teid));
9874 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9875 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9879 * Add GTP PSC item to matcher.
9881 * @param[in, out] matcher
9883 * @param[in, out] key
9884 * Flow matcher value.
9886 * Flow pattern to translate.
9889 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9890 const struct rte_flow_item *item)
9892 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9893 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9894 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9896 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9902 uint8_t next_ext_header_type;
9907 /* Always set E-flag match on one, regardless of GTP item settings. */
9908 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9909 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9910 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9911 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9912 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9913 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9914 /*Set next extension header type. */
9917 dw_2.next_ext_header_type = 0xff;
9918 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9919 rte_cpu_to_be_32(dw_2.w32));
9922 dw_2.next_ext_header_type = 0x85;
9923 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9924 rte_cpu_to_be_32(dw_2.w32));
9936 /*Set extension header PDU type and Qos. */
9938 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9940 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9941 dw_0.qfi = gtp_psc_m->hdr.qfi;
9942 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9943 rte_cpu_to_be_32(dw_0.w32));
9945 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9946 gtp_psc_m->hdr.type);
9947 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9948 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9949 rte_cpu_to_be_32(dw_0.w32));
9955 * Add eCPRI item to matcher and to the value.
9958 * The devich to configure through.
9959 * @param[in, out] matcher
9961 * @param[in, out] key
9962 * Flow matcher value.
9964 * Flow pattern to translate.
9965 * @param[in] last_item
9969 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9970 void *key, const struct rte_flow_item *item,
9973 struct mlx5_priv *priv = dev->data->dev_private;
9974 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9975 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9976 struct rte_ecpri_common_hdr common;
9977 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9979 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9985 * In case of eCPRI over Ethernet, if EtherType is not specified,
9986 * match on eCPRI EtherType implicitly.
9988 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
9989 void *hdrs_m, *hdrs_v, *l2m, *l2v;
9991 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9992 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9993 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
9994 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
9995 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
9996 *(uint16_t *)l2m = UINT16_MAX;
9997 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10003 ecpri_m = &rte_flow_item_ecpri_mask;
10005 * Maximal four DW samples are supported in a single matching now.
10006 * Two are used now for a eCPRI matching:
10007 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10008 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10011 if (!ecpri_m->hdr.common.u32)
10013 samples = priv->sh->ecpri_parser.ids;
10014 /* Need to take the whole DW as the mask to fill the entry. */
10015 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10016 prog_sample_field_value_0);
10017 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10018 prog_sample_field_value_0);
10019 /* Already big endian (network order) in the header. */
10020 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10021 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10022 /* Sample#0, used for matching type, offset 0. */
10023 MLX5_SET(fte_match_set_misc4, misc4_m,
10024 prog_sample_field_id_0, samples[0]);
10025 /* It makes no sense to set the sample ID in the mask field. */
10026 MLX5_SET(fte_match_set_misc4, misc4_v,
10027 prog_sample_field_id_0, samples[0]);
10029 * Checking if message body part needs to be matched.
10030 * Some wildcard rules only matching type field should be supported.
10032 if (ecpri_m->hdr.dummy[0]) {
10033 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10034 switch (common.type) {
10035 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10036 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10037 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10038 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10039 prog_sample_field_value_1);
10040 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10041 prog_sample_field_value_1);
10042 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10043 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10044 ecpri_m->hdr.dummy[0];
10045 /* Sample#1, to match message body, offset 4. */
10046 MLX5_SET(fte_match_set_misc4, misc4_m,
10047 prog_sample_field_id_1, samples[1]);
10048 MLX5_SET(fte_match_set_misc4, misc4_v,
10049 prog_sample_field_id_1, samples[1]);
10052 /* Others, do not match any sample ID. */
10059 * Add connection tracking status item to matcher
10062 * The devich to configure through.
10063 * @param[in, out] matcher
10065 * @param[in, out] key
10066 * Flow matcher value.
10068 * Flow pattern to translate.
10071 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10072 void *matcher, void *key,
10073 const struct rte_flow_item *item)
10075 uint32_t reg_value = 0;
10077 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10078 uint32_t reg_mask = 0;
10079 const struct rte_flow_item_conntrack *spec = item->spec;
10080 const struct rte_flow_item_conntrack *mask = item->mask;
10082 struct rte_flow_error error;
10085 mask = &rte_flow_item_conntrack_mask;
10086 if (!spec || !mask->flags)
10088 flags = spec->flags & mask->flags;
10089 /* The conflict should be checked in the validation. */
10090 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10091 reg_value |= MLX5_CT_SYNDROME_VALID;
10092 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10093 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10094 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10095 reg_value |= MLX5_CT_SYNDROME_INVALID;
10096 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10097 reg_value |= MLX5_CT_SYNDROME_TRAP;
10098 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10099 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10100 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10101 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10102 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10104 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10105 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10106 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10107 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10108 /* The REG_C_x value could be saved during startup. */
10109 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10110 if (reg_id == REG_NON)
10112 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10113 reg_value, reg_mask);
10117 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10118 const struct rte_flow_item *item,
10119 struct mlx5_flow *dev_flow, bool is_inner)
10121 const struct rte_flow_item_flex *spec =
10122 (const struct rte_flow_item_flex *)item->spec;
10123 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10125 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10128 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10129 /* Don't count both inner and outer flex items in one rule. */
10130 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10131 MLX5_ASSERT(false);
10132 dev_flow->handle->flex_item |= RTE_BIT32(index);
10134 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10137 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10139 #define HEADER_IS_ZERO(match_criteria, headers) \
10140 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10141 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10144 * Calculate flow matcher enable bitmap.
10146 * @param match_criteria
10147 * Pointer to flow matcher criteria.
10150 * Bitmap of enabled fields.
10153 flow_dv_matcher_enable(uint32_t *match_criteria)
10155 uint8_t match_criteria_enable;
10157 match_criteria_enable =
10158 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10159 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10160 match_criteria_enable |=
10161 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10162 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10163 match_criteria_enable |=
10164 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10165 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10166 match_criteria_enable |=
10167 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10168 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10169 match_criteria_enable |=
10170 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10171 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10172 match_criteria_enable |=
10173 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10174 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10175 match_criteria_enable |=
10176 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10177 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10178 return match_criteria_enable;
10182 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10185 * Check flow matching criteria first, subtract misc5/4 length if flow
10186 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10187 * misc5/4 are not supported, and matcher creation failure is expected
10188 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10189 * misc5 is right after misc4.
10191 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10192 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10193 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10194 if (!(match_criteria & (1 <<
10195 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10196 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10201 static struct mlx5_list_entry *
10202 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10203 struct mlx5_list_entry *entry, void *cb_ctx)
10205 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10206 struct mlx5_flow_dv_matcher *ref = ctx->data;
10207 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10208 typeof(*tbl), tbl);
10209 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10214 rte_flow_error_set(ctx->error, ENOMEM,
10215 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10216 "cannot create matcher");
10219 memcpy(resource, entry, sizeof(*resource));
10220 resource->tbl = &tbl->tbl;
10221 return &resource->entry;
10225 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10226 struct mlx5_list_entry *entry)
10231 struct mlx5_list_entry *
10232 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10234 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10235 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10236 struct rte_eth_dev *dev = ctx->dev;
10237 struct mlx5_flow_tbl_data_entry *tbl_data;
10238 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10239 struct rte_flow_error *error = ctx->error;
10240 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10241 struct mlx5_flow_tbl_resource *tbl;
10246 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10248 rte_flow_error_set(error, ENOMEM,
10249 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10251 "cannot allocate flow table data entry");
10254 tbl_data->idx = idx;
10255 tbl_data->tunnel = tt_prm->tunnel;
10256 tbl_data->group_id = tt_prm->group_id;
10257 tbl_data->external = !!tt_prm->external;
10258 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10259 tbl_data->is_egress = !!key.is_egress;
10260 tbl_data->is_transfer = !!key.is_fdb;
10261 tbl_data->dummy = !!key.dummy;
10262 tbl_data->level = key.level;
10263 tbl_data->id = key.id;
10264 tbl = &tbl_data->tbl;
10266 return &tbl_data->entry;
10268 domain = sh->fdb_domain;
10269 else if (key.is_egress)
10270 domain = sh->tx_domain;
10272 domain = sh->rx_domain;
10273 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10275 rte_flow_error_set(error, ENOMEM,
10276 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10277 NULL, "cannot create flow table object");
10278 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10281 if (key.level != 0) {
10282 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10283 (tbl->obj, &tbl_data->jump.action);
10285 rte_flow_error_set(error, ENOMEM,
10286 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10288 "cannot create flow jump action");
10289 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10290 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10294 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10295 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10296 key.level, key.id);
10297 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10298 flow_dv_matcher_create_cb,
10299 flow_dv_matcher_match_cb,
10300 flow_dv_matcher_remove_cb,
10301 flow_dv_matcher_clone_cb,
10302 flow_dv_matcher_clone_free_cb);
10303 if (!tbl_data->matchers) {
10304 rte_flow_error_set(error, ENOMEM,
10305 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10307 "cannot create tbl matcher list");
10308 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10309 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10310 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10313 return &tbl_data->entry;
10317 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10320 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10321 struct mlx5_flow_tbl_data_entry *tbl_data =
10322 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10323 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10325 return tbl_data->level != key.level ||
10326 tbl_data->id != key.id ||
10327 tbl_data->dummy != key.dummy ||
10328 tbl_data->is_transfer != !!key.is_fdb ||
10329 tbl_data->is_egress != !!key.is_egress;
10332 struct mlx5_list_entry *
10333 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10336 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10337 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10338 struct mlx5_flow_tbl_data_entry *tbl_data;
10339 struct rte_flow_error *error = ctx->error;
10342 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10344 rte_flow_error_set(error, ENOMEM,
10345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10347 "cannot allocate flow table data entry");
10350 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10351 tbl_data->idx = idx;
10352 return &tbl_data->entry;
10356 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10358 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10359 struct mlx5_flow_tbl_data_entry *tbl_data =
10360 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10362 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10366 * Get a flow table.
10368 * @param[in, out] dev
10369 * Pointer to rte_eth_dev structure.
10370 * @param[in] table_level
10371 * Table level to use.
10372 * @param[in] egress
10373 * Direction of the table.
10374 * @param[in] transfer
10375 * E-Switch or NIC flow.
10377 * Dummy entry for dv API.
10378 * @param[in] table_id
10380 * @param[out] error
10381 * pointer to error structure.
10384 * Returns tables resource based on the index, NULL in case of failed.
10386 struct mlx5_flow_tbl_resource *
10387 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10388 uint32_t table_level, uint8_t egress,
10391 const struct mlx5_flow_tunnel *tunnel,
10392 uint32_t group_id, uint8_t dummy,
10394 struct rte_flow_error *error)
10396 struct mlx5_priv *priv = dev->data->dev_private;
10397 union mlx5_flow_tbl_key table_key = {
10399 .level = table_level,
10403 .is_fdb = !!transfer,
10404 .is_egress = !!egress,
10407 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10409 .group_id = group_id,
10410 .external = external,
10412 struct mlx5_flow_cb_ctx ctx = {
10415 .data = &table_key.v64,
10418 struct mlx5_list_entry *entry;
10419 struct mlx5_flow_tbl_data_entry *tbl_data;
10421 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10423 rte_flow_error_set(error, ENOMEM,
10424 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10425 "cannot get table");
10428 DRV_LOG(DEBUG, "table_level %u table_id %u "
10429 "tunnel %u group %u registered.",
10430 table_level, table_id,
10431 tunnel ? tunnel->tunnel_id : 0, group_id);
10432 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10433 return &tbl_data->tbl;
10437 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10439 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10440 struct mlx5_flow_tbl_data_entry *tbl_data =
10441 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10443 MLX5_ASSERT(entry && sh);
10444 if (tbl_data->jump.action)
10445 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10446 if (tbl_data->tbl.obj)
10447 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10448 if (tbl_data->tunnel_offload && tbl_data->external) {
10449 struct mlx5_list_entry *he;
10450 struct mlx5_hlist *tunnel_grp_hash;
10451 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10452 union tunnel_tbl_key tunnel_key = {
10453 .tunnel_id = tbl_data->tunnel ?
10454 tbl_data->tunnel->tunnel_id : 0,
10455 .group = tbl_data->group_id
10457 uint32_t table_level = tbl_data->level;
10458 struct mlx5_flow_cb_ctx ctx = {
10459 .data = (void *)&tunnel_key.val,
10462 tunnel_grp_hash = tbl_data->tunnel ?
10463 tbl_data->tunnel->groups :
10465 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10467 mlx5_hlist_unregister(tunnel_grp_hash, he);
10469 "table_level %u id %u tunnel %u group %u released.",
10473 tbl_data->tunnel->tunnel_id : 0,
10474 tbl_data->group_id);
10476 mlx5_list_destroy(tbl_data->matchers);
10477 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10481 * Release a flow table.
10484 * Pointer to device shared structure.
10486 * Table resource to be released.
10489 * Returns 0 if table was released, else return 1;
10492 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10493 struct mlx5_flow_tbl_resource *tbl)
10495 struct mlx5_flow_tbl_data_entry *tbl_data =
10496 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10500 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10504 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10505 struct mlx5_list_entry *entry, void *cb_ctx)
10507 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10508 struct mlx5_flow_dv_matcher *ref = ctx->data;
10509 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10512 return cur->crc != ref->crc ||
10513 cur->priority != ref->priority ||
10514 memcmp((const void *)cur->mask.buf,
10515 (const void *)ref->mask.buf, ref->mask.size);
10518 struct mlx5_list_entry *
10519 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10521 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10522 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10523 struct mlx5_flow_dv_matcher *ref = ctx->data;
10524 struct mlx5_flow_dv_matcher *resource;
10525 struct mlx5dv_flow_matcher_attr dv_attr = {
10526 .type = IBV_FLOW_ATTR_NORMAL,
10527 .match_mask = (void *)&ref->mask,
10529 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10530 typeof(*tbl), tbl);
10533 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10536 rte_flow_error_set(ctx->error, ENOMEM,
10537 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10538 "cannot create matcher");
10542 dv_attr.match_criteria_enable =
10543 flow_dv_matcher_enable(resource->mask.buf);
10544 __flow_dv_adjust_buf_size(&ref->mask.size,
10545 dv_attr.match_criteria_enable);
10546 dv_attr.priority = ref->priority;
10547 if (tbl->is_egress)
10548 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10549 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10551 &resource->matcher_object);
10553 mlx5_free(resource);
10554 rte_flow_error_set(ctx->error, ENOMEM,
10555 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10556 "cannot create matcher");
10559 return &resource->entry;
10563 * Register the flow matcher.
10565 * @param[in, out] dev
10566 * Pointer to rte_eth_dev structure.
10567 * @param[in, out] matcher
10568 * Pointer to flow matcher.
10569 * @param[in, out] key
10570 * Pointer to flow table key.
10571 * @parm[in, out] dev_flow
10572 * Pointer to the dev_flow.
10573 * @param[out] error
10574 * pointer to error structure.
10577 * 0 on success otherwise -errno and errno is set.
10580 flow_dv_matcher_register(struct rte_eth_dev *dev,
10581 struct mlx5_flow_dv_matcher *ref,
10582 union mlx5_flow_tbl_key *key,
10583 struct mlx5_flow *dev_flow,
10584 const struct mlx5_flow_tunnel *tunnel,
10586 struct rte_flow_error *error)
10588 struct mlx5_list_entry *entry;
10589 struct mlx5_flow_dv_matcher *resource;
10590 struct mlx5_flow_tbl_resource *tbl;
10591 struct mlx5_flow_tbl_data_entry *tbl_data;
10592 struct mlx5_flow_cb_ctx ctx = {
10597 * tunnel offload API requires this registration for cases when
10598 * tunnel match rule was inserted before tunnel set rule.
10600 tbl = flow_dv_tbl_resource_get(dev, key->level,
10601 key->is_egress, key->is_fdb,
10602 dev_flow->external, tunnel,
10603 group_id, 0, key->id, error);
10605 return -rte_errno; /* No need to refill the error info */
10606 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10608 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10610 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10611 return rte_flow_error_set(error, ENOMEM,
10612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10613 "cannot allocate ref memory");
10615 resource = container_of(entry, typeof(*resource), entry);
10616 dev_flow->handle->dvh.matcher = resource;
10620 struct mlx5_list_entry *
10621 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10623 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10624 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10625 struct mlx5_flow_dv_tag_resource *entry;
10629 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10631 rte_flow_error_set(ctx->error, ENOMEM,
10632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10633 "cannot allocate resource memory");
10637 entry->tag_id = *(uint32_t *)(ctx->data);
10638 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10641 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10642 rte_flow_error_set(ctx->error, ENOMEM,
10643 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10644 NULL, "cannot create action");
10647 return &entry->entry;
10651 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10654 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10655 struct mlx5_flow_dv_tag_resource *tag =
10656 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10658 return *(uint32_t *)(ctx->data) != tag->tag_id;
10661 struct mlx5_list_entry *
10662 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10665 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10666 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10667 struct mlx5_flow_dv_tag_resource *entry;
10670 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10672 rte_flow_error_set(ctx->error, ENOMEM,
10673 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10674 "cannot allocate tag resource memory");
10677 memcpy(entry, oentry, sizeof(*entry));
10679 return &entry->entry;
10683 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10685 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10686 struct mlx5_flow_dv_tag_resource *tag =
10687 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10689 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10693 * Find existing tag resource or create and register a new one.
10695 * @param dev[in, out]
10696 * Pointer to rte_eth_dev structure.
10697 * @param[in, out] tag_be24
10698 * Tag value in big endian then R-shift 8.
10699 * @parm[in, out] dev_flow
10700 * Pointer to the dev_flow.
10701 * @param[out] error
10702 * pointer to error structure.
10705 * 0 on success otherwise -errno and errno is set.
10708 flow_dv_tag_resource_register
10709 (struct rte_eth_dev *dev,
10711 struct mlx5_flow *dev_flow,
10712 struct rte_flow_error *error)
10714 struct mlx5_priv *priv = dev->data->dev_private;
10715 struct mlx5_flow_dv_tag_resource *resource;
10716 struct mlx5_list_entry *entry;
10717 struct mlx5_flow_cb_ctx ctx = {
10721 struct mlx5_hlist *tag_table;
10723 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10725 MLX5_TAGS_HLIST_ARRAY_SIZE,
10726 false, false, priv->sh,
10727 flow_dv_tag_create_cb,
10728 flow_dv_tag_match_cb,
10729 flow_dv_tag_remove_cb,
10730 flow_dv_tag_clone_cb,
10731 flow_dv_tag_clone_free_cb);
10732 if (unlikely(!tag_table))
10734 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10736 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10738 dev_flow->handle->dvh.rix_tag = resource->idx;
10739 dev_flow->dv.tag_resource = resource;
10746 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10748 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10749 struct mlx5_flow_dv_tag_resource *tag =
10750 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10752 MLX5_ASSERT(tag && sh && tag->action);
10753 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10754 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10755 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10762 * Pointer to Ethernet device.
10767 * 1 while a reference on it exists, 0 when freed.
10770 flow_dv_tag_release(struct rte_eth_dev *dev,
10773 struct mlx5_priv *priv = dev->data->dev_private;
10774 struct mlx5_flow_dv_tag_resource *tag;
10776 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10779 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10780 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10781 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10785 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10788 * Pointer to rte_eth_dev structure.
10789 * @param[in] action
10790 * Pointer to action PORT_ID / REPRESENTED_PORT.
10791 * @param[out] dst_port_id
10792 * The target port ID.
10793 * @param[out] error
10794 * Pointer to the error structure.
10797 * 0 on success, a negative errno value otherwise and rte_errno is set.
10800 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10801 const struct rte_flow_action *action,
10802 uint32_t *dst_port_id,
10803 struct rte_flow_error *error)
10806 struct mlx5_priv *priv;
10808 switch (action->type) {
10809 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10810 const struct rte_flow_action_port_id *conf;
10812 conf = (const struct rte_flow_action_port_id *)action->conf;
10813 port = conf->original ? dev->data->port_id : conf->id;
10816 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10817 const struct rte_flow_action_ethdev *ethdev;
10819 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10820 port = ethdev->port_id;
10824 MLX5_ASSERT(false);
10825 return rte_flow_error_set(error, EINVAL,
10826 RTE_FLOW_ERROR_TYPE_ACTION, action,
10827 "unknown E-Switch action");
10830 priv = mlx5_port_to_eswitch_info(port, false);
10832 return rte_flow_error_set(error, -rte_errno,
10833 RTE_FLOW_ERROR_TYPE_ACTION,
10835 "No eswitch info was found for port");
10836 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10838 * This parameter is transferred to
10839 * mlx5dv_dr_action_create_dest_ib_port().
10841 *dst_port_id = priv->dev_port;
10844 * Legacy mode, no LAG configurations is supported.
10845 * This parameter is transferred to
10846 * mlx5dv_dr_action_create_dest_vport().
10848 *dst_port_id = priv->vport_id;
10854 * Create a counter with aging configuration.
10857 * Pointer to rte_eth_dev structure.
10858 * @param[in] dev_flow
10859 * Pointer to the mlx5_flow.
10860 * @param[out] count
10861 * Pointer to the counter action configuration.
10863 * Pointer to the aging action configuration.
10866 * Index to flow counter on success, 0 otherwise.
10869 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10870 struct mlx5_flow *dev_flow,
10871 const struct rte_flow_action_count *count
10873 const struct rte_flow_action_age *age)
10876 struct mlx5_age_param *age_param;
10878 counter = flow_dv_counter_alloc(dev, !!age);
10879 if (!counter || age == NULL)
10881 age_param = flow_dv_counter_idx_get_age(dev, counter);
10882 age_param->context = age->context ? age->context :
10883 (void *)(uintptr_t)(dev_flow->flow_idx);
10884 age_param->timeout = age->timeout;
10885 age_param->port_id = dev->data->port_id;
10886 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10887 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10892 * Add Tx queue matcher
10895 * Pointer to the dev struct.
10896 * @param[in, out] matcher
10898 * @param[in, out] key
10899 * Flow matcher value.
10901 * Flow pattern to translate.
10903 * Item is inner pattern.
10906 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10907 void *matcher, void *key,
10908 const struct rte_flow_item *item)
10910 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10911 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10913 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10915 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10916 struct mlx5_txq_ctrl *txq;
10917 uint32_t queue, mask;
10919 queue_m = (const void *)item->mask;
10920 queue_v = (const void *)item->spec;
10923 txq = mlx5_txq_get(dev, queue_v->queue);
10926 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10927 queue = txq->obj->sq->id;
10929 queue = txq->obj->sq_obj.sq->id;
10930 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10931 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10932 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10933 mlx5_txq_release(dev, queue_v->queue);
10937 * Set the hash fields according to the @p flow information.
10939 * @param[in] dev_flow
10940 * Pointer to the mlx5_flow.
10941 * @param[in] rss_desc
10942 * Pointer to the mlx5_flow_rss_desc.
10945 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10946 struct mlx5_flow_rss_desc *rss_desc)
10948 uint64_t items = dev_flow->handle->layers;
10950 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10952 dev_flow->hash_fields = 0;
10953 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10954 if (rss_desc->level >= 2)
10957 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10958 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10959 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10960 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10961 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10962 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10963 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10965 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10967 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10968 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10969 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10970 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10971 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10972 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10973 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10975 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10978 if (dev_flow->hash_fields == 0)
10980 * There is no match between the RSS types and the
10981 * L3 protocol (IPv4/IPv6) defined in the flow rule.
10984 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10985 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10986 if (rss_types & RTE_ETH_RSS_UDP) {
10987 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10988 dev_flow->hash_fields |=
10989 IBV_RX_HASH_SRC_PORT_UDP;
10990 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10991 dev_flow->hash_fields |=
10992 IBV_RX_HASH_DST_PORT_UDP;
10994 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10996 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10997 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10998 if (rss_types & RTE_ETH_RSS_TCP) {
10999 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11000 dev_flow->hash_fields |=
11001 IBV_RX_HASH_SRC_PORT_TCP;
11002 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11003 dev_flow->hash_fields |=
11004 IBV_RX_HASH_DST_PORT_TCP;
11006 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11010 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11014 * Prepare an Rx Hash queue.
11017 * Pointer to Ethernet device.
11018 * @param[in] dev_flow
11019 * Pointer to the mlx5_flow.
11020 * @param[in] rss_desc
11021 * Pointer to the mlx5_flow_rss_desc.
11022 * @param[out] hrxq_idx
11023 * Hash Rx queue index.
11026 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11028 static struct mlx5_hrxq *
11029 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11030 struct mlx5_flow *dev_flow,
11031 struct mlx5_flow_rss_desc *rss_desc,
11032 uint32_t *hrxq_idx)
11034 struct mlx5_priv *priv = dev->data->dev_private;
11035 struct mlx5_flow_handle *dh = dev_flow->handle;
11036 struct mlx5_hrxq *hrxq;
11038 MLX5_ASSERT(rss_desc->queue_num);
11039 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11040 rss_desc->hash_fields = dev_flow->hash_fields;
11041 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11042 rss_desc->shared_rss = 0;
11043 if (rss_desc->hash_fields == 0)
11044 rss_desc->queue_num = 1;
11045 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11048 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11054 * Release sample sub action resource.
11056 * @param[in, out] dev
11057 * Pointer to rte_eth_dev structure.
11058 * @param[in] act_res
11059 * Pointer to sample sub action resource.
11062 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11063 struct mlx5_flow_sub_actions_idx *act_res)
11065 if (act_res->rix_hrxq) {
11066 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11067 act_res->rix_hrxq = 0;
11069 if (act_res->rix_encap_decap) {
11070 flow_dv_encap_decap_resource_release(dev,
11071 act_res->rix_encap_decap);
11072 act_res->rix_encap_decap = 0;
11074 if (act_res->rix_port_id_action) {
11075 flow_dv_port_id_action_resource_release(dev,
11076 act_res->rix_port_id_action);
11077 act_res->rix_port_id_action = 0;
11079 if (act_res->rix_tag) {
11080 flow_dv_tag_release(dev, act_res->rix_tag);
11081 act_res->rix_tag = 0;
11083 if (act_res->rix_jump) {
11084 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11085 act_res->rix_jump = 0;
11090 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11091 struct mlx5_list_entry *entry, void *cb_ctx)
11093 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11094 struct rte_eth_dev *dev = ctx->dev;
11095 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11096 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11100 if (ctx_resource->ratio == resource->ratio &&
11101 ctx_resource->ft_type == resource->ft_type &&
11102 ctx_resource->ft_id == resource->ft_id &&
11103 ctx_resource->set_action == resource->set_action &&
11104 !memcmp((void *)&ctx_resource->sample_act,
11105 (void *)&resource->sample_act,
11106 sizeof(struct mlx5_flow_sub_actions_list))) {
11108 * Existing sample action should release the prepared
11109 * sub-actions reference counter.
11111 flow_dv_sample_sub_actions_release(dev,
11112 &ctx_resource->sample_idx);
11118 struct mlx5_list_entry *
11119 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11121 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11122 struct rte_eth_dev *dev = ctx->dev;
11123 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11124 void **sample_dv_actions = ctx_resource->sub_actions;
11125 struct mlx5_flow_dv_sample_resource *resource;
11126 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11127 struct mlx5_priv *priv = dev->data->dev_private;
11128 struct mlx5_dev_ctx_shared *sh = priv->sh;
11129 struct mlx5_flow_tbl_resource *tbl;
11131 const uint32_t next_ft_step = 1;
11132 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11133 uint8_t is_egress = 0;
11134 uint8_t is_transfer = 0;
11135 struct rte_flow_error *error = ctx->error;
11137 /* Register new sample resource. */
11138 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11140 rte_flow_error_set(error, ENOMEM,
11141 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11143 "cannot allocate resource memory");
11146 *resource = *ctx_resource;
11147 /* Create normal path table level */
11148 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11150 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11152 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11153 is_egress, is_transfer,
11154 true, NULL, 0, 0, 0, error);
11156 rte_flow_error_set(error, ENOMEM,
11157 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11159 "fail to create normal path table "
11163 resource->normal_path_tbl = tbl;
11164 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11165 if (!sh->default_miss_action) {
11166 rte_flow_error_set(error, ENOMEM,
11167 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11169 "default miss action was not "
11173 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11174 sh->default_miss_action;
11176 /* Create a DR sample action */
11177 sampler_attr.sample_ratio = resource->ratio;
11178 sampler_attr.default_next_table = tbl->obj;
11179 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11180 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11181 &sample_dv_actions[0];
11182 sampler_attr.action = resource->set_action;
11183 if (mlx5_os_flow_dr_create_flow_action_sampler
11184 (&sampler_attr, &resource->verbs_action)) {
11185 rte_flow_error_set(error, ENOMEM,
11186 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11187 NULL, "cannot create sample action");
11190 resource->idx = idx;
11191 resource->dev = dev;
11192 return &resource->entry;
11194 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11195 flow_dv_sample_sub_actions_release(dev,
11196 &resource->sample_idx);
11197 if (resource->normal_path_tbl)
11198 flow_dv_tbl_resource_release(MLX5_SH(dev),
11199 resource->normal_path_tbl);
11200 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11205 struct mlx5_list_entry *
11206 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11207 struct mlx5_list_entry *entry __rte_unused,
11210 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11211 struct rte_eth_dev *dev = ctx->dev;
11212 struct mlx5_flow_dv_sample_resource *resource;
11213 struct mlx5_priv *priv = dev->data->dev_private;
11214 struct mlx5_dev_ctx_shared *sh = priv->sh;
11217 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11219 rte_flow_error_set(ctx->error, ENOMEM,
11220 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11222 "cannot allocate resource memory");
11225 memcpy(resource, entry, sizeof(*resource));
11226 resource->idx = idx;
11227 resource->dev = dev;
11228 return &resource->entry;
11232 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11233 struct mlx5_list_entry *entry)
11235 struct mlx5_flow_dv_sample_resource *resource =
11236 container_of(entry, typeof(*resource), entry);
11237 struct rte_eth_dev *dev = resource->dev;
11238 struct mlx5_priv *priv = dev->data->dev_private;
11240 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11244 * Find existing sample resource or create and register a new one.
11246 * @param[in, out] dev
11247 * Pointer to rte_eth_dev structure.
11249 * Pointer to sample resource reference.
11250 * @parm[in, out] dev_flow
11251 * Pointer to the dev_flow.
11252 * @param[out] error
11253 * pointer to error structure.
11256 * 0 on success otherwise -errno and errno is set.
11259 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11260 struct mlx5_flow_dv_sample_resource *ref,
11261 struct mlx5_flow *dev_flow,
11262 struct rte_flow_error *error)
11264 struct mlx5_flow_dv_sample_resource *resource;
11265 struct mlx5_list_entry *entry;
11266 struct mlx5_priv *priv = dev->data->dev_private;
11267 struct mlx5_flow_cb_ctx ctx = {
11273 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11276 resource = container_of(entry, typeof(*resource), entry);
11277 dev_flow->handle->dvh.rix_sample = resource->idx;
11278 dev_flow->dv.sample_res = resource;
11283 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11284 struct mlx5_list_entry *entry, void *cb_ctx)
11286 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11287 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11288 struct rte_eth_dev *dev = ctx->dev;
11289 struct mlx5_flow_dv_dest_array_resource *resource =
11290 container_of(entry, typeof(*resource), entry);
11293 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11294 ctx_resource->ft_type == resource->ft_type &&
11295 !memcmp((void *)resource->sample_act,
11296 (void *)ctx_resource->sample_act,
11297 (ctx_resource->num_of_dest *
11298 sizeof(struct mlx5_flow_sub_actions_list)))) {
11300 * Existing sample action should release the prepared
11301 * sub-actions reference counter.
11303 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11304 flow_dv_sample_sub_actions_release(dev,
11305 &ctx_resource->sample_idx[idx]);
11311 struct mlx5_list_entry *
11312 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11314 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11315 struct rte_eth_dev *dev = ctx->dev;
11316 struct mlx5_flow_dv_dest_array_resource *resource;
11317 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11318 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11319 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11320 struct mlx5_priv *priv = dev->data->dev_private;
11321 struct mlx5_dev_ctx_shared *sh = priv->sh;
11322 struct mlx5_flow_sub_actions_list *sample_act;
11323 struct mlx5dv_dr_domain *domain;
11324 uint32_t idx = 0, res_idx = 0;
11325 struct rte_flow_error *error = ctx->error;
11326 uint64_t action_flags;
11329 /* Register new destination array resource. */
11330 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11333 rte_flow_error_set(error, ENOMEM,
11334 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11336 "cannot allocate resource memory");
11339 *resource = *ctx_resource;
11340 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11341 domain = sh->fdb_domain;
11342 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11343 domain = sh->rx_domain;
11345 domain = sh->tx_domain;
11346 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11347 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11348 mlx5_malloc(MLX5_MEM_ZERO,
11349 sizeof(struct mlx5dv_dr_action_dest_attr),
11351 if (!dest_attr[idx]) {
11352 rte_flow_error_set(error, ENOMEM,
11353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11355 "cannot allocate resource memory");
11358 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11359 sample_act = &ctx_resource->sample_act[idx];
11360 action_flags = sample_act->action_flags;
11361 switch (action_flags) {
11362 case MLX5_FLOW_ACTION_QUEUE:
11363 dest_attr[idx]->dest = sample_act->dr_queue_action;
11365 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11366 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11367 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11368 dest_attr[idx]->dest_reformat->reformat =
11369 sample_act->dr_encap_action;
11370 dest_attr[idx]->dest_reformat->dest =
11371 sample_act->dr_port_id_action;
11373 case MLX5_FLOW_ACTION_PORT_ID:
11374 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11376 case MLX5_FLOW_ACTION_JUMP:
11377 dest_attr[idx]->dest = sample_act->dr_jump_action;
11380 rte_flow_error_set(error, EINVAL,
11381 RTE_FLOW_ERROR_TYPE_ACTION,
11383 "unsupported actions type");
11387 /* create a dest array actioin */
11388 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11390 resource->num_of_dest,
11392 &resource->action);
11394 rte_flow_error_set(error, ENOMEM,
11395 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11397 "cannot create destination array action");
11400 resource->idx = res_idx;
11401 resource->dev = dev;
11402 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11403 mlx5_free(dest_attr[idx]);
11404 return &resource->entry;
11406 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11407 flow_dv_sample_sub_actions_release(dev,
11408 &resource->sample_idx[idx]);
11409 if (dest_attr[idx])
11410 mlx5_free(dest_attr[idx]);
11412 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11416 struct mlx5_list_entry *
11417 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11418 struct mlx5_list_entry *entry __rte_unused,
11421 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11422 struct rte_eth_dev *dev = ctx->dev;
11423 struct mlx5_flow_dv_dest_array_resource *resource;
11424 struct mlx5_priv *priv = dev->data->dev_private;
11425 struct mlx5_dev_ctx_shared *sh = priv->sh;
11426 uint32_t res_idx = 0;
11427 struct rte_flow_error *error = ctx->error;
11429 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11432 rte_flow_error_set(error, ENOMEM,
11433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11435 "cannot allocate dest-array memory");
11438 memcpy(resource, entry, sizeof(*resource));
11439 resource->idx = res_idx;
11440 resource->dev = dev;
11441 return &resource->entry;
11445 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11446 struct mlx5_list_entry *entry)
11448 struct mlx5_flow_dv_dest_array_resource *resource =
11449 container_of(entry, typeof(*resource), entry);
11450 struct rte_eth_dev *dev = resource->dev;
11451 struct mlx5_priv *priv = dev->data->dev_private;
11453 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11457 * Find existing destination array resource or create and register a new one.
11459 * @param[in, out] dev
11460 * Pointer to rte_eth_dev structure.
11462 * Pointer to destination array resource reference.
11463 * @parm[in, out] dev_flow
11464 * Pointer to the dev_flow.
11465 * @param[out] error
11466 * pointer to error structure.
11469 * 0 on success otherwise -errno and errno is set.
11472 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11473 struct mlx5_flow_dv_dest_array_resource *ref,
11474 struct mlx5_flow *dev_flow,
11475 struct rte_flow_error *error)
11477 struct mlx5_flow_dv_dest_array_resource *resource;
11478 struct mlx5_priv *priv = dev->data->dev_private;
11479 struct mlx5_list_entry *entry;
11480 struct mlx5_flow_cb_ctx ctx = {
11486 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11489 resource = container_of(entry, typeof(*resource), entry);
11490 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11491 dev_flow->dv.dest_array_res = resource;
11496 * Convert Sample action to DV specification.
11499 * Pointer to rte_eth_dev structure.
11500 * @param[in] action
11501 * Pointer to sample action structure.
11502 * @param[in, out] dev_flow
11503 * Pointer to the mlx5_flow.
11505 * Pointer to the flow attributes.
11506 * @param[in, out] num_of_dest
11507 * Pointer to the num of destination.
11508 * @param[in, out] sample_actions
11509 * Pointer to sample actions list.
11510 * @param[in, out] res
11511 * Pointer to sample resource.
11512 * @param[out] error
11513 * Pointer to the error structure.
11516 * 0 on success, a negative errno value otherwise and rte_errno is set.
11519 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11520 const struct rte_flow_action_sample *action,
11521 struct mlx5_flow *dev_flow,
11522 const struct rte_flow_attr *attr,
11523 uint32_t *num_of_dest,
11524 void **sample_actions,
11525 struct mlx5_flow_dv_sample_resource *res,
11526 struct rte_flow_error *error)
11528 struct mlx5_priv *priv = dev->data->dev_private;
11529 const struct rte_flow_action *sub_actions;
11530 struct mlx5_flow_sub_actions_list *sample_act;
11531 struct mlx5_flow_sub_actions_idx *sample_idx;
11532 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11533 struct rte_flow *flow = dev_flow->flow;
11534 struct mlx5_flow_rss_desc *rss_desc;
11535 uint64_t action_flags = 0;
11538 rss_desc = &wks->rss_desc;
11539 sample_act = &res->sample_act;
11540 sample_idx = &res->sample_idx;
11541 res->ratio = action->ratio;
11542 sub_actions = action->actions;
11543 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11544 int type = sub_actions->type;
11545 uint32_t pre_rix = 0;
11548 case RTE_FLOW_ACTION_TYPE_QUEUE:
11550 const struct rte_flow_action_queue *queue;
11551 struct mlx5_hrxq *hrxq;
11554 queue = sub_actions->conf;
11555 rss_desc->queue_num = 1;
11556 rss_desc->queue[0] = queue->index;
11557 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11558 rss_desc, &hrxq_idx);
11560 return rte_flow_error_set
11562 RTE_FLOW_ERROR_TYPE_ACTION,
11564 "cannot create fate queue");
11565 sample_act->dr_queue_action = hrxq->action;
11566 sample_idx->rix_hrxq = hrxq_idx;
11567 sample_actions[sample_act->actions_num++] =
11570 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11571 if (action_flags & MLX5_FLOW_ACTION_MARK)
11572 dev_flow->handle->rix_hrxq = hrxq_idx;
11573 dev_flow->handle->fate_action =
11574 MLX5_FLOW_FATE_QUEUE;
11577 case RTE_FLOW_ACTION_TYPE_RSS:
11579 struct mlx5_hrxq *hrxq;
11581 const struct rte_flow_action_rss *rss;
11582 const uint8_t *rss_key;
11584 rss = sub_actions->conf;
11585 memcpy(rss_desc->queue, rss->queue,
11586 rss->queue_num * sizeof(uint16_t));
11587 rss_desc->queue_num = rss->queue_num;
11588 /* NULL RSS key indicates default RSS key. */
11589 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11590 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11592 * rss->level and rss.types should be set in advance
11593 * when expanding items for RSS.
11595 flow_dv_hashfields_set(dev_flow, rss_desc);
11596 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11597 rss_desc, &hrxq_idx);
11599 return rte_flow_error_set
11601 RTE_FLOW_ERROR_TYPE_ACTION,
11603 "cannot create fate queue");
11604 sample_act->dr_queue_action = hrxq->action;
11605 sample_idx->rix_hrxq = hrxq_idx;
11606 sample_actions[sample_act->actions_num++] =
11609 action_flags |= MLX5_FLOW_ACTION_RSS;
11610 if (action_flags & MLX5_FLOW_ACTION_MARK)
11611 dev_flow->handle->rix_hrxq = hrxq_idx;
11612 dev_flow->handle->fate_action =
11613 MLX5_FLOW_FATE_QUEUE;
11616 case RTE_FLOW_ACTION_TYPE_MARK:
11618 uint32_t tag_be = mlx5_flow_mark_set
11619 (((const struct rte_flow_action_mark *)
11620 (sub_actions->conf))->id);
11622 dev_flow->handle->mark = 1;
11623 pre_rix = dev_flow->handle->dvh.rix_tag;
11624 /* Save the mark resource before sample */
11625 pre_r = dev_flow->dv.tag_resource;
11626 if (flow_dv_tag_resource_register(dev, tag_be,
11629 MLX5_ASSERT(dev_flow->dv.tag_resource);
11630 sample_act->dr_tag_action =
11631 dev_flow->dv.tag_resource->action;
11632 sample_idx->rix_tag =
11633 dev_flow->handle->dvh.rix_tag;
11634 sample_actions[sample_act->actions_num++] =
11635 sample_act->dr_tag_action;
11636 /* Recover the mark resource after sample */
11637 dev_flow->dv.tag_resource = pre_r;
11638 dev_flow->handle->dvh.rix_tag = pre_rix;
11639 action_flags |= MLX5_FLOW_ACTION_MARK;
11642 case RTE_FLOW_ACTION_TYPE_COUNT:
11644 if (!flow->counter) {
11646 flow_dv_translate_create_counter(dev,
11647 dev_flow, sub_actions->conf,
11649 if (!flow->counter)
11650 return rte_flow_error_set
11652 RTE_FLOW_ERROR_TYPE_ACTION,
11654 "cannot create counter"
11657 sample_act->dr_cnt_action =
11658 (flow_dv_counter_get_by_idx(dev,
11659 flow->counter, NULL))->action;
11660 sample_actions[sample_act->actions_num++] =
11661 sample_act->dr_cnt_action;
11662 action_flags |= MLX5_FLOW_ACTION_COUNT;
11665 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11666 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11668 struct mlx5_flow_dv_port_id_action_resource
11670 uint32_t port_id = 0;
11672 memset(&port_id_resource, 0, sizeof(port_id_resource));
11673 /* Save the port id resource before sample */
11674 pre_rix = dev_flow->handle->rix_port_id_action;
11675 pre_r = dev_flow->dv.port_id_action;
11676 if (flow_dv_translate_action_port_id(dev, sub_actions,
11679 port_id_resource.port_id = port_id;
11680 if (flow_dv_port_id_action_resource_register
11681 (dev, &port_id_resource, dev_flow, error))
11683 sample_act->dr_port_id_action =
11684 dev_flow->dv.port_id_action->action;
11685 sample_idx->rix_port_id_action =
11686 dev_flow->handle->rix_port_id_action;
11687 sample_actions[sample_act->actions_num++] =
11688 sample_act->dr_port_id_action;
11689 /* Recover the port id resource after sample */
11690 dev_flow->dv.port_id_action = pre_r;
11691 dev_flow->handle->rix_port_id_action = pre_rix;
11693 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11696 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11697 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11698 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11699 /* Save the encap resource before sample */
11700 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11701 pre_r = dev_flow->dv.encap_decap;
11702 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11707 sample_act->dr_encap_action =
11708 dev_flow->dv.encap_decap->action;
11709 sample_idx->rix_encap_decap =
11710 dev_flow->handle->dvh.rix_encap_decap;
11711 sample_actions[sample_act->actions_num++] =
11712 sample_act->dr_encap_action;
11713 /* Recover the encap resource after sample */
11714 dev_flow->dv.encap_decap = pre_r;
11715 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11716 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11719 return rte_flow_error_set(error, EINVAL,
11720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11722 "Not support for sampler action");
11725 sample_act->action_flags = action_flags;
11726 res->ft_id = dev_flow->dv.group;
11727 if (attr->transfer) {
11729 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11730 uint64_t set_action;
11731 } action_ctx = { .set_action = 0 };
11733 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11734 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11735 MLX5_MODIFICATION_TYPE_SET);
11736 MLX5_SET(set_action_in, action_ctx.action_in, field,
11737 MLX5_MODI_META_REG_C_0);
11738 MLX5_SET(set_action_in, action_ctx.action_in, data,
11739 priv->vport_meta_tag);
11740 res->set_action = action_ctx.set_action;
11741 } else if (attr->ingress) {
11742 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11744 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11750 * Convert Sample action to DV specification.
11753 * Pointer to rte_eth_dev structure.
11754 * @param[in, out] dev_flow
11755 * Pointer to the mlx5_flow.
11756 * @param[in] num_of_dest
11757 * The num of destination.
11758 * @param[in, out] res
11759 * Pointer to sample resource.
11760 * @param[in, out] mdest_res
11761 * Pointer to destination array resource.
11762 * @param[in] sample_actions
11763 * Pointer to sample path actions list.
11764 * @param[in] action_flags
11765 * Holds the actions detected until now.
11766 * @param[out] error
11767 * Pointer to the error structure.
11770 * 0 on success, a negative errno value otherwise and rte_errno is set.
11773 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11774 struct mlx5_flow *dev_flow,
11775 uint32_t num_of_dest,
11776 struct mlx5_flow_dv_sample_resource *res,
11777 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11778 void **sample_actions,
11779 uint64_t action_flags,
11780 struct rte_flow_error *error)
11782 /* update normal path action resource into last index of array */
11783 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11784 struct mlx5_flow_sub_actions_list *sample_act =
11785 &mdest_res->sample_act[dest_index];
11786 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11787 struct mlx5_flow_rss_desc *rss_desc;
11788 uint32_t normal_idx = 0;
11789 struct mlx5_hrxq *hrxq;
11793 rss_desc = &wks->rss_desc;
11794 if (num_of_dest > 1) {
11795 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11796 /* Handle QP action for mirroring */
11797 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11798 rss_desc, &hrxq_idx);
11800 return rte_flow_error_set
11802 RTE_FLOW_ERROR_TYPE_ACTION,
11804 "cannot create rx queue");
11806 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11807 sample_act->dr_queue_action = hrxq->action;
11808 if (action_flags & MLX5_FLOW_ACTION_MARK)
11809 dev_flow->handle->rix_hrxq = hrxq_idx;
11810 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11812 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11814 mdest_res->sample_idx[dest_index].rix_encap_decap =
11815 dev_flow->handle->dvh.rix_encap_decap;
11816 sample_act->dr_encap_action =
11817 dev_flow->dv.encap_decap->action;
11818 dev_flow->handle->dvh.rix_encap_decap = 0;
11820 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11822 mdest_res->sample_idx[dest_index].rix_port_id_action =
11823 dev_flow->handle->rix_port_id_action;
11824 sample_act->dr_port_id_action =
11825 dev_flow->dv.port_id_action->action;
11826 dev_flow->handle->rix_port_id_action = 0;
11828 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11830 mdest_res->sample_idx[dest_index].rix_jump =
11831 dev_flow->handle->rix_jump;
11832 sample_act->dr_jump_action =
11833 dev_flow->dv.jump->action;
11834 dev_flow->handle->rix_jump = 0;
11836 sample_act->actions_num = normal_idx;
11837 /* update sample action resource into first index of array */
11838 mdest_res->ft_type = res->ft_type;
11839 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11840 sizeof(struct mlx5_flow_sub_actions_idx));
11841 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11842 sizeof(struct mlx5_flow_sub_actions_list));
11843 mdest_res->num_of_dest = num_of_dest;
11844 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11846 return rte_flow_error_set(error, EINVAL,
11847 RTE_FLOW_ERROR_TYPE_ACTION,
11848 NULL, "can't create sample "
11851 res->sub_actions = sample_actions;
11852 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11853 return rte_flow_error_set(error, EINVAL,
11854 RTE_FLOW_ERROR_TYPE_ACTION,
11856 "can't create sample action");
11862 * Remove an ASO age action from age actions list.
11865 * Pointer to the Ethernet device structure.
11867 * Pointer to the aso age action handler.
11870 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11871 struct mlx5_aso_age_action *age)
11873 struct mlx5_age_info *age_info;
11874 struct mlx5_age_param *age_param = &age->age_params;
11875 struct mlx5_priv *priv = dev->data->dev_private;
11876 uint16_t expected = AGE_CANDIDATE;
11878 age_info = GET_PORT_AGE_INFO(priv);
11879 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11880 AGE_FREE, false, __ATOMIC_RELAXED,
11881 __ATOMIC_RELAXED)) {
11883 * We need the lock even it is age timeout,
11884 * since age action may still in process.
11886 rte_spinlock_lock(&age_info->aged_sl);
11887 LIST_REMOVE(age, next);
11888 rte_spinlock_unlock(&age_info->aged_sl);
11889 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11894 * Release an ASO age action.
11897 * Pointer to the Ethernet device structure.
11898 * @param[in] age_idx
11899 * Index of ASO age action to release.
11901 * True if the release operation is during flow destroy operation.
11902 * False if the release operation is during action destroy operation.
11905 * 0 when age action was removed, otherwise the number of references.
11908 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11910 struct mlx5_priv *priv = dev->data->dev_private;
11911 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11912 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11913 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11916 flow_dv_aso_age_remove_from_age(dev, age);
11917 rte_spinlock_lock(&mng->free_sl);
11918 LIST_INSERT_HEAD(&mng->free, age, next);
11919 rte_spinlock_unlock(&mng->free_sl);
11925 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11928 * Pointer to the Ethernet device structure.
11931 * 0 on success, otherwise negative errno value and rte_errno is set.
11934 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11936 struct mlx5_priv *priv = dev->data->dev_private;
11937 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11938 void *old_pools = mng->pools;
11939 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11940 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11941 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11944 rte_errno = ENOMEM;
11948 memcpy(pools, old_pools,
11949 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11950 mlx5_free(old_pools);
11952 /* First ASO flow hit allocation - starting ASO data-path. */
11953 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11961 mng->pools = pools;
11966 * Create and initialize a new ASO aging pool.
11969 * Pointer to the Ethernet device structure.
11970 * @param[out] age_free
11971 * Where to put the pointer of a new age action.
11974 * The age actions pool pointer and @p age_free is set on success,
11975 * NULL otherwise and rte_errno is set.
11977 static struct mlx5_aso_age_pool *
11978 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11979 struct mlx5_aso_age_action **age_free)
11981 struct mlx5_priv *priv = dev->data->dev_private;
11982 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11983 struct mlx5_aso_age_pool *pool = NULL;
11984 struct mlx5_devx_obj *obj = NULL;
11987 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
11988 priv->sh->cdev->pdn);
11990 rte_errno = ENODATA;
11991 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11994 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11996 claim_zero(mlx5_devx_cmd_destroy(obj));
11997 rte_errno = ENOMEM;
12000 pool->flow_hit_aso_obj = obj;
12001 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12002 rte_rwlock_write_lock(&mng->resize_rwl);
12003 pool->index = mng->next;
12004 /* Resize pools array if there is no room for the new pool in it. */
12005 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12006 claim_zero(mlx5_devx_cmd_destroy(obj));
12008 rte_rwlock_write_unlock(&mng->resize_rwl);
12011 mng->pools[pool->index] = pool;
12013 rte_rwlock_write_unlock(&mng->resize_rwl);
12014 /* Assign the first action in the new pool, the rest go to free list. */
12015 *age_free = &pool->actions[0];
12016 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12017 pool->actions[i].offset = i;
12018 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12024 * Allocate a ASO aging bit.
12027 * Pointer to the Ethernet device structure.
12028 * @param[out] error
12029 * Pointer to the error structure.
12032 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12035 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12037 struct mlx5_priv *priv = dev->data->dev_private;
12038 const struct mlx5_aso_age_pool *pool;
12039 struct mlx5_aso_age_action *age_free = NULL;
12040 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12043 /* Try to get the next free age action bit. */
12044 rte_spinlock_lock(&mng->free_sl);
12045 age_free = LIST_FIRST(&mng->free);
12047 LIST_REMOVE(age_free, next);
12048 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12049 rte_spinlock_unlock(&mng->free_sl);
12050 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12051 NULL, "failed to create ASO age pool");
12052 return 0; /* 0 is an error. */
12054 rte_spinlock_unlock(&mng->free_sl);
12055 pool = container_of
12056 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12057 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12059 if (!age_free->dr_action) {
12060 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12064 rte_flow_error_set(error, rte_errno,
12065 RTE_FLOW_ERROR_TYPE_ACTION,
12066 NULL, "failed to get reg_c "
12067 "for ASO flow hit");
12068 return 0; /* 0 is an error. */
12070 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12071 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12072 (priv->sh->rx_domain,
12073 pool->flow_hit_aso_obj->obj, age_free->offset,
12074 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12075 (reg_c - REG_C_0));
12076 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12077 if (!age_free->dr_action) {
12079 rte_spinlock_lock(&mng->free_sl);
12080 LIST_INSERT_HEAD(&mng->free, age_free, next);
12081 rte_spinlock_unlock(&mng->free_sl);
12082 rte_flow_error_set(error, rte_errno,
12083 RTE_FLOW_ERROR_TYPE_ACTION,
12084 NULL, "failed to create ASO "
12085 "flow hit action");
12086 return 0; /* 0 is an error. */
12089 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12090 return pool->index | ((age_free->offset + 1) << 16);
12094 * Initialize flow ASO age parameters.
12097 * Pointer to rte_eth_dev structure.
12098 * @param[in] age_idx
12099 * Index of ASO age action.
12100 * @param[in] context
12101 * Pointer to flow counter age context.
12102 * @param[in] timeout
12103 * Aging timeout in seconds.
12107 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12112 struct mlx5_aso_age_action *aso_age;
12114 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12115 MLX5_ASSERT(aso_age);
12116 aso_age->age_params.context = context;
12117 aso_age->age_params.timeout = timeout;
12118 aso_age->age_params.port_id = dev->data->port_id;
12119 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12121 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12126 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12127 const struct rte_flow_item_integrity *value,
12128 void *headers_m, void *headers_v)
12131 /* RTE l4_ok filter aggregates hardware l4_ok and
12132 * l4_checksum_ok filters.
12133 * Positive RTE l4_ok match requires hardware match on both L4
12134 * hardware integrity bits.
12135 * For negative match, check hardware l4_checksum_ok bit only,
12136 * because hardware sets that bit to 0 for all packets
12139 if (value->l4_ok) {
12140 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12141 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12143 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12144 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12147 if (mask->l4_csum_ok) {
12148 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12149 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12150 value->l4_csum_ok);
12155 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12156 const struct rte_flow_item_integrity *value,
12157 void *headers_m, void *headers_v, bool is_ipv4)
12160 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12161 * ipv4_csum_ok filters.
12162 * Positive RTE l3_ok match requires hardware match on both L3
12163 * hardware integrity bits.
12164 * For negative match, check hardware l3_csum_ok bit only,
12165 * because hardware sets that bit to 0 for all packets
12169 if (value->l3_ok) {
12170 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12172 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12175 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12176 ipv4_checksum_ok, 1);
12177 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12178 ipv4_checksum_ok, !!value->l3_ok);
12180 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12185 if (mask->ipv4_csum_ok) {
12186 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12187 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12188 value->ipv4_csum_ok);
12193 set_integrity_bits(void *headers_m, void *headers_v,
12194 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12196 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12197 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12199 /* Integrity bits validation cleared spec pointer */
12200 MLX5_ASSERT(spec != NULL);
12202 mask = &rte_flow_item_integrity_mask;
12203 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12205 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12209 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12211 struct rte_flow_item *integrity_items[2],
12212 uint64_t pattern_flags)
12214 void *headers_m, *headers_v;
12217 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12218 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12220 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12221 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12223 set_integrity_bits(headers_m, headers_v,
12224 integrity_items[1], is_l3_ip4);
12226 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12227 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12229 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12230 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12232 set_integrity_bits(headers_m, headers_v,
12233 integrity_items[0], is_l3_ip4);
12238 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12239 const struct rte_flow_item *integrity_items[2],
12240 uint64_t *last_item)
12242 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12244 /* integrity bits validation cleared spec pointer */
12245 MLX5_ASSERT(spec != NULL);
12246 if (spec->level > 1) {
12247 integrity_items[1] = item;
12248 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12250 integrity_items[0] = item;
12251 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12256 * Prepares DV flow counter with aging configuration.
12257 * Gets it by index when exists, creates a new one when doesn't.
12260 * Pointer to rte_eth_dev structure.
12261 * @param[in] dev_flow
12262 * Pointer to the mlx5_flow.
12263 * @param[in, out] flow
12264 * Pointer to the sub flow.
12266 * Pointer to the counter action configuration.
12268 * Pointer to the aging action configuration.
12269 * @param[out] error
12270 * Pointer to the error structure.
12273 * Pointer to the counter, NULL otherwise.
12275 static struct mlx5_flow_counter *
12276 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12277 struct mlx5_flow *dev_flow,
12278 struct rte_flow *flow,
12279 const struct rte_flow_action_count *count,
12280 const struct rte_flow_action_age *age,
12281 struct rte_flow_error *error)
12283 if (!flow->counter) {
12284 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12286 if (!flow->counter) {
12287 rte_flow_error_set(error, rte_errno,
12288 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12289 "cannot create counter object.");
12293 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12297 * Release an ASO CT action by its own device.
12300 * Pointer to the Ethernet device structure.
12302 * Index of ASO CT action to release.
12305 * 0 when CT action was removed, otherwise the number of references.
12308 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12310 struct mlx5_priv *priv = dev->data->dev_private;
12311 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12313 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12314 enum mlx5_aso_ct_state state =
12315 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12317 /* Cannot release when CT is in the ASO SQ. */
12318 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12320 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12322 if (ct->dr_action_orig) {
12323 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12324 claim_zero(mlx5_glue->destroy_flow_action
12325 (ct->dr_action_orig));
12327 ct->dr_action_orig = NULL;
12329 if (ct->dr_action_rply) {
12330 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12331 claim_zero(mlx5_glue->destroy_flow_action
12332 (ct->dr_action_rply));
12334 ct->dr_action_rply = NULL;
12336 /* Clear the state to free, no need in 1st allocation. */
12337 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12338 rte_spinlock_lock(&mng->ct_sl);
12339 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12340 rte_spinlock_unlock(&mng->ct_sl);
12346 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12347 struct rte_flow_error *error)
12349 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12350 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12351 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12354 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12355 if (dev->data->dev_started != 1)
12356 return rte_flow_error_set(error, EAGAIN,
12357 RTE_FLOW_ERROR_TYPE_ACTION,
12359 "Indirect CT action cannot be destroyed when the port is stopped");
12360 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12362 return rte_flow_error_set(error, EAGAIN,
12363 RTE_FLOW_ERROR_TYPE_ACTION,
12365 "Current state prevents indirect CT action from being destroyed");
12370 * Resize the ASO CT pools array by 64 pools.
12373 * Pointer to the Ethernet device structure.
12376 * 0 on success, otherwise negative errno value and rte_errno is set.
12379 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12381 struct mlx5_priv *priv = dev->data->dev_private;
12382 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12383 void *old_pools = mng->pools;
12384 /* Magic number now, need a macro. */
12385 uint32_t resize = mng->n + 64;
12386 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12387 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12390 rte_errno = ENOMEM;
12393 rte_rwlock_write_lock(&mng->resize_rwl);
12394 /* ASO SQ/QP was already initialized in the startup. */
12396 /* Realloc could be an alternative choice. */
12397 rte_memcpy(pools, old_pools,
12398 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12399 mlx5_free(old_pools);
12402 mng->pools = pools;
12403 rte_rwlock_write_unlock(&mng->resize_rwl);
12408 * Create and initialize a new ASO CT pool.
12411 * Pointer to the Ethernet device structure.
12412 * @param[out] ct_free
12413 * Where to put the pointer of a new CT action.
12416 * The CT actions pool pointer and @p ct_free is set on success,
12417 * NULL otherwise and rte_errno is set.
12419 static struct mlx5_aso_ct_pool *
12420 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12421 struct mlx5_aso_ct_action **ct_free)
12423 struct mlx5_priv *priv = dev->data->dev_private;
12424 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12425 struct mlx5_aso_ct_pool *pool = NULL;
12426 struct mlx5_devx_obj *obj = NULL;
12428 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12430 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12431 priv->sh->cdev->pdn,
12434 rte_errno = ENODATA;
12435 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12438 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12440 rte_errno = ENOMEM;
12441 claim_zero(mlx5_devx_cmd_destroy(obj));
12444 pool->devx_obj = obj;
12445 pool->index = mng->next;
12446 /* Resize pools array if there is no room for the new pool in it. */
12447 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12448 claim_zero(mlx5_devx_cmd_destroy(obj));
12452 mng->pools[pool->index] = pool;
12454 /* Assign the first action in the new pool, the rest go to free list. */
12455 *ct_free = &pool->actions[0];
12456 /* Lock outside, the list operation is safe here. */
12457 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12458 /* refcnt is 0 when allocating the memory. */
12459 pool->actions[i].offset = i;
12460 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12466 * Allocate a ASO CT action from free list.
12469 * Pointer to the Ethernet device structure.
12470 * @param[out] error
12471 * Pointer to the error structure.
12474 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12477 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12479 struct mlx5_priv *priv = dev->data->dev_private;
12480 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12481 struct mlx5_aso_ct_action *ct = NULL;
12482 struct mlx5_aso_ct_pool *pool;
12487 if (!priv->sh->devx) {
12488 rte_errno = ENOTSUP;
12491 /* Get a free CT action, if no, a new pool will be created. */
12492 rte_spinlock_lock(&mng->ct_sl);
12493 ct = LIST_FIRST(&mng->free_cts);
12495 LIST_REMOVE(ct, next);
12496 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12497 rte_spinlock_unlock(&mng->ct_sl);
12498 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12499 NULL, "failed to create ASO CT pool");
12502 rte_spinlock_unlock(&mng->ct_sl);
12503 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12504 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12505 /* 0: inactive, 1: created, 2+: used by flows. */
12506 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12507 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12508 if (!ct->dr_action_orig) {
12509 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12510 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12511 (priv->sh->rx_domain, pool->devx_obj->obj,
12513 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12516 RTE_SET_USED(reg_c);
12518 if (!ct->dr_action_orig) {
12519 flow_dv_aso_ct_dev_release(dev, ct_idx);
12520 rte_flow_error_set(error, rte_errno,
12521 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12522 "failed to create ASO CT action");
12526 if (!ct->dr_action_rply) {
12527 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12528 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12529 (priv->sh->rx_domain, pool->devx_obj->obj,
12531 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12534 if (!ct->dr_action_rply) {
12535 flow_dv_aso_ct_dev_release(dev, ct_idx);
12536 rte_flow_error_set(error, rte_errno,
12537 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12538 "failed to create ASO CT action");
12546 * Create a conntrack object with context and actions by using ASO mechanism.
12549 * Pointer to rte_eth_dev structure.
12551 * Pointer to conntrack information profile.
12552 * @param[out] error
12553 * Pointer to the error structure.
12556 * Index to conntrack object on success, 0 otherwise.
12559 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12560 const struct rte_flow_action_conntrack *pro,
12561 struct rte_flow_error *error)
12563 struct mlx5_priv *priv = dev->data->dev_private;
12564 struct mlx5_dev_ctx_shared *sh = priv->sh;
12565 struct mlx5_aso_ct_action *ct;
12568 if (!sh->ct_aso_en)
12569 return rte_flow_error_set(error, ENOTSUP,
12570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12571 "Connection is not supported");
12572 idx = flow_dv_aso_ct_alloc(dev, error);
12574 return rte_flow_error_set(error, rte_errno,
12575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12576 "Failed to allocate CT object");
12577 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12578 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12579 return rte_flow_error_set(error, EBUSY,
12580 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12581 "Failed to update CT");
12582 ct->is_original = !!pro->is_original_dir;
12583 ct->peer = pro->peer_port;
12588 * Fill the flow with DV spec, lock free
12589 * (mutex should be acquired by caller).
12592 * Pointer to rte_eth_dev structure.
12593 * @param[in, out] dev_flow
12594 * Pointer to the sub flow.
12596 * Pointer to the flow attributes.
12598 * Pointer to the list of items.
12599 * @param[in] actions
12600 * Pointer to the list of actions.
12601 * @param[out] error
12602 * Pointer to the error structure.
12605 * 0 on success, a negative errno value otherwise and rte_errno is set.
12608 flow_dv_translate(struct rte_eth_dev *dev,
12609 struct mlx5_flow *dev_flow,
12610 const struct rte_flow_attr *attr,
12611 const struct rte_flow_item items[],
12612 const struct rte_flow_action actions[],
12613 struct rte_flow_error *error)
12615 struct mlx5_priv *priv = dev->data->dev_private;
12616 struct mlx5_dev_config *dev_conf = &priv->config;
12617 struct rte_flow *flow = dev_flow->flow;
12618 struct mlx5_flow_handle *handle = dev_flow->handle;
12619 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12620 struct mlx5_flow_rss_desc *rss_desc;
12621 uint64_t item_flags = 0;
12622 uint64_t last_item = 0;
12623 uint64_t action_flags = 0;
12624 struct mlx5_flow_dv_matcher matcher = {
12626 .size = sizeof(matcher.mask.buf),
12630 bool actions_end = false;
12632 struct mlx5_flow_dv_modify_hdr_resource res;
12633 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12634 sizeof(struct mlx5_modification_cmd) *
12635 (MLX5_MAX_MODIFY_NUM + 1)];
12637 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12638 const struct rte_flow_action_count *count = NULL;
12639 const struct rte_flow_action_age *non_shared_age = NULL;
12640 union flow_dv_attr flow_attr = { .attr = 0 };
12642 union mlx5_flow_tbl_key tbl_key;
12643 uint32_t modify_action_position = UINT32_MAX;
12644 void *match_mask = matcher.mask.buf;
12645 void *match_value = dev_flow->dv.value.buf;
12646 uint8_t next_protocol = 0xff;
12647 struct rte_vlan_hdr vlan = { 0 };
12648 struct mlx5_flow_dv_dest_array_resource mdest_res;
12649 struct mlx5_flow_dv_sample_resource sample_res;
12650 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12651 const struct rte_flow_action_sample *sample = NULL;
12652 struct mlx5_flow_sub_actions_list *sample_act;
12653 uint32_t sample_act_pos = UINT32_MAX;
12654 uint32_t age_act_pos = UINT32_MAX;
12655 uint32_t num_of_dest = 0;
12656 int tmp_actions_n = 0;
12659 const struct mlx5_flow_tunnel *tunnel = NULL;
12660 struct flow_grp_info grp_info = {
12661 .external = !!dev_flow->external,
12662 .transfer = !!attr->transfer,
12663 .fdb_def_rule = !!priv->fdb_def_rule,
12664 .skip_scale = dev_flow->skip_scale &
12665 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12666 .std_tbl_fix = true,
12668 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12669 const struct rte_flow_item *tunnel_item = NULL;
12672 return rte_flow_error_set(error, ENOMEM,
12673 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12675 "failed to push flow workspace");
12676 rss_desc = &wks->rss_desc;
12677 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12678 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12679 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12680 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12681 /* update normal path action resource into last index of array */
12682 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12683 if (is_tunnel_offload_active(dev)) {
12684 if (dev_flow->tunnel) {
12685 RTE_VERIFY(dev_flow->tof_type ==
12686 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12687 tunnel = dev_flow->tunnel;
12689 tunnel = mlx5_get_tof(items, actions,
12690 &dev_flow->tof_type);
12691 dev_flow->tunnel = tunnel;
12693 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12694 (dev, attr, tunnel, dev_flow->tof_type);
12696 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12697 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12698 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12702 dev_flow->dv.group = table;
12703 if (attr->transfer)
12704 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12705 /* number of actions must be set to 0 in case of dirty stack. */
12706 mhdr_res->actions_num = 0;
12707 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12709 * do not add decap action if match rule drops packet
12710 * HW rejects rules with decap & drop
12712 * if tunnel match rule was inserted before matching tunnel set
12713 * rule flow table used in the match rule must be registered.
12714 * current implementation handles that in the
12715 * flow_dv_match_register() at the function end.
12717 bool add_decap = true;
12718 const struct rte_flow_action *ptr = actions;
12720 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12721 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12727 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12731 dev_flow->dv.actions[actions_n++] =
12732 dev_flow->dv.encap_decap->action;
12733 action_flags |= MLX5_FLOW_ACTION_DECAP;
12736 for (; !actions_end ; actions++) {
12737 const struct rte_flow_action_queue *queue;
12738 const struct rte_flow_action_rss *rss;
12739 const struct rte_flow_action *action = actions;
12740 const uint8_t *rss_key;
12741 struct mlx5_flow_tbl_resource *tbl;
12742 struct mlx5_aso_age_action *age_act;
12743 struct mlx5_flow_counter *cnt_act;
12744 uint32_t port_id = 0;
12745 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12746 int action_type = actions->type;
12747 const struct rte_flow_action *found_action = NULL;
12748 uint32_t jump_group = 0;
12749 uint32_t owner_idx;
12750 struct mlx5_aso_ct_action *ct;
12752 if (!mlx5_flow_os_action_supported(action_type))
12753 return rte_flow_error_set(error, ENOTSUP,
12754 RTE_FLOW_ERROR_TYPE_ACTION,
12756 "action not supported");
12757 switch (action_type) {
12758 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12759 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12761 case RTE_FLOW_ACTION_TYPE_VOID:
12763 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12764 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12765 if (flow_dv_translate_action_port_id(dev, action,
12768 port_id_resource.port_id = port_id;
12769 MLX5_ASSERT(!handle->rix_port_id_action);
12770 if (flow_dv_port_id_action_resource_register
12771 (dev, &port_id_resource, dev_flow, error))
12773 dev_flow->dv.actions[actions_n++] =
12774 dev_flow->dv.port_id_action->action;
12775 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12776 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12777 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12780 case RTE_FLOW_ACTION_TYPE_FLAG:
12781 action_flags |= MLX5_FLOW_ACTION_FLAG;
12782 dev_flow->handle->mark = 1;
12783 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12784 struct rte_flow_action_mark mark = {
12785 .id = MLX5_FLOW_MARK_DEFAULT,
12788 if (flow_dv_convert_action_mark(dev, &mark,
12792 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12795 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12797 * Only one FLAG or MARK is supported per device flow
12798 * right now. So the pointer to the tag resource must be
12799 * zero before the register process.
12801 MLX5_ASSERT(!handle->dvh.rix_tag);
12802 if (flow_dv_tag_resource_register(dev, tag_be,
12805 MLX5_ASSERT(dev_flow->dv.tag_resource);
12806 dev_flow->dv.actions[actions_n++] =
12807 dev_flow->dv.tag_resource->action;
12809 case RTE_FLOW_ACTION_TYPE_MARK:
12810 action_flags |= MLX5_FLOW_ACTION_MARK;
12811 dev_flow->handle->mark = 1;
12812 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12813 const struct rte_flow_action_mark *mark =
12814 (const struct rte_flow_action_mark *)
12817 if (flow_dv_convert_action_mark(dev, mark,
12821 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12825 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12826 /* Legacy (non-extensive) MARK action. */
12827 tag_be = mlx5_flow_mark_set
12828 (((const struct rte_flow_action_mark *)
12829 (actions->conf))->id);
12830 MLX5_ASSERT(!handle->dvh.rix_tag);
12831 if (flow_dv_tag_resource_register(dev, tag_be,
12834 MLX5_ASSERT(dev_flow->dv.tag_resource);
12835 dev_flow->dv.actions[actions_n++] =
12836 dev_flow->dv.tag_resource->action;
12838 case RTE_FLOW_ACTION_TYPE_SET_META:
12839 if (flow_dv_convert_action_set_meta
12840 (dev, mhdr_res, attr,
12841 (const struct rte_flow_action_set_meta *)
12842 actions->conf, error))
12844 action_flags |= MLX5_FLOW_ACTION_SET_META;
12846 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12847 if (flow_dv_convert_action_set_tag
12849 (const struct rte_flow_action_set_tag *)
12850 actions->conf, error))
12852 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12854 case RTE_FLOW_ACTION_TYPE_DROP:
12855 action_flags |= MLX5_FLOW_ACTION_DROP;
12856 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12858 case RTE_FLOW_ACTION_TYPE_QUEUE:
12859 queue = actions->conf;
12860 rss_desc->queue_num = 1;
12861 rss_desc->queue[0] = queue->index;
12862 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12863 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12864 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12867 case RTE_FLOW_ACTION_TYPE_RSS:
12868 rss = actions->conf;
12869 memcpy(rss_desc->queue, rss->queue,
12870 rss->queue_num * sizeof(uint16_t));
12871 rss_desc->queue_num = rss->queue_num;
12872 /* NULL RSS key indicates default RSS key. */
12873 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12874 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12876 * rss->level and rss.types should be set in advance
12877 * when expanding items for RSS.
12879 action_flags |= MLX5_FLOW_ACTION_RSS;
12880 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12881 MLX5_FLOW_FATE_SHARED_RSS :
12882 MLX5_FLOW_FATE_QUEUE;
12884 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12885 owner_idx = (uint32_t)(uintptr_t)action->conf;
12886 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12887 if (flow->age == 0) {
12888 flow->age = owner_idx;
12889 __atomic_fetch_add(&age_act->refcnt, 1,
12892 age_act_pos = actions_n++;
12893 action_flags |= MLX5_FLOW_ACTION_AGE;
12895 case RTE_FLOW_ACTION_TYPE_AGE:
12896 non_shared_age = action->conf;
12897 age_act_pos = actions_n++;
12898 action_flags |= MLX5_FLOW_ACTION_AGE;
12900 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12901 owner_idx = (uint32_t)(uintptr_t)action->conf;
12902 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12904 MLX5_ASSERT(cnt_act != NULL);
12906 * When creating meter drop flow in drop table, the
12907 * counter should not overwrite the rte flow counter.
12909 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12910 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12911 dev_flow->dv.actions[actions_n++] =
12914 if (flow->counter == 0) {
12915 flow->counter = owner_idx;
12917 (&cnt_act->shared_info.refcnt,
12918 1, __ATOMIC_RELAXED);
12920 /* Save information first, will apply later. */
12921 action_flags |= MLX5_FLOW_ACTION_COUNT;
12924 case RTE_FLOW_ACTION_TYPE_COUNT:
12925 if (!priv->sh->devx) {
12926 return rte_flow_error_set
12928 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12930 "count action not supported");
12932 /* Save information first, will apply later. */
12933 count = action->conf;
12934 action_flags |= MLX5_FLOW_ACTION_COUNT;
12936 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12937 dev_flow->dv.actions[actions_n++] =
12938 priv->sh->pop_vlan_action;
12939 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12941 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12942 if (!(action_flags &
12943 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12944 flow_dev_get_vlan_info_from_items(items, &vlan);
12945 vlan.eth_proto = rte_be_to_cpu_16
12946 ((((const struct rte_flow_action_of_push_vlan *)
12947 actions->conf)->ethertype));
12948 found_action = mlx5_flow_find_action
12950 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12952 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12953 found_action = mlx5_flow_find_action
12955 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12957 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12958 if (flow_dv_create_action_push_vlan
12959 (dev, attr, &vlan, dev_flow, error))
12961 dev_flow->dv.actions[actions_n++] =
12962 dev_flow->dv.push_vlan_res->action;
12963 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12965 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12966 /* of_vlan_push action handled this action */
12967 MLX5_ASSERT(action_flags &
12968 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12970 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12971 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12973 flow_dev_get_vlan_info_from_items(items, &vlan);
12974 mlx5_update_vlan_vid_pcp(actions, &vlan);
12975 /* If no VLAN push - this is a modify header action */
12976 if (flow_dv_convert_action_modify_vlan_vid
12977 (mhdr_res, actions, error))
12979 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12981 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12982 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12983 if (flow_dv_create_action_l2_encap(dev, actions,
12988 dev_flow->dv.actions[actions_n++] =
12989 dev_flow->dv.encap_decap->action;
12990 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12991 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12992 sample_act->action_flags |=
12993 MLX5_FLOW_ACTION_ENCAP;
12995 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12996 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12997 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13001 dev_flow->dv.actions[actions_n++] =
13002 dev_flow->dv.encap_decap->action;
13003 action_flags |= MLX5_FLOW_ACTION_DECAP;
13005 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13006 /* Handle encap with preceding decap. */
13007 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13008 if (flow_dv_create_action_raw_encap
13009 (dev, actions, dev_flow, attr, error))
13011 dev_flow->dv.actions[actions_n++] =
13012 dev_flow->dv.encap_decap->action;
13014 /* Handle encap without preceding decap. */
13015 if (flow_dv_create_action_l2_encap
13016 (dev, actions, dev_flow, attr->transfer,
13019 dev_flow->dv.actions[actions_n++] =
13020 dev_flow->dv.encap_decap->action;
13022 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13023 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13024 sample_act->action_flags |=
13025 MLX5_FLOW_ACTION_ENCAP;
13027 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13028 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13030 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13031 if (flow_dv_create_action_l2_decap
13032 (dev, dev_flow, attr->transfer, error))
13034 dev_flow->dv.actions[actions_n++] =
13035 dev_flow->dv.encap_decap->action;
13037 /* If decap is followed by encap, handle it at encap. */
13038 action_flags |= MLX5_FLOW_ACTION_DECAP;
13040 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13041 dev_flow->dv.actions[actions_n++] =
13042 (void *)(uintptr_t)action->conf;
13043 action_flags |= MLX5_FLOW_ACTION_JUMP;
13045 case RTE_FLOW_ACTION_TYPE_JUMP:
13046 jump_group = ((const struct rte_flow_action_jump *)
13047 action->conf)->group;
13048 grp_info.std_tbl_fix = 0;
13049 if (dev_flow->skip_scale &
13050 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13051 grp_info.skip_scale = 1;
13053 grp_info.skip_scale = 0;
13054 ret = mlx5_flow_group_to_table(dev, tunnel,
13060 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13062 !!dev_flow->external,
13063 tunnel, jump_group, 0,
13066 return rte_flow_error_set
13068 RTE_FLOW_ERROR_TYPE_ACTION,
13070 "cannot create jump action.");
13071 if (flow_dv_jump_tbl_resource_register
13072 (dev, tbl, dev_flow, error)) {
13073 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13074 return rte_flow_error_set
13076 RTE_FLOW_ERROR_TYPE_ACTION,
13078 "cannot create jump action.");
13080 dev_flow->dv.actions[actions_n++] =
13081 dev_flow->dv.jump->action;
13082 action_flags |= MLX5_FLOW_ACTION_JUMP;
13083 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13084 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13087 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13088 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13089 if (flow_dv_convert_action_modify_mac
13090 (mhdr_res, actions, error))
13092 action_flags |= actions->type ==
13093 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13094 MLX5_FLOW_ACTION_SET_MAC_SRC :
13095 MLX5_FLOW_ACTION_SET_MAC_DST;
13097 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13098 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13099 if (flow_dv_convert_action_modify_ipv4
13100 (mhdr_res, actions, error))
13102 action_flags |= actions->type ==
13103 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13104 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13105 MLX5_FLOW_ACTION_SET_IPV4_DST;
13107 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13108 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13109 if (flow_dv_convert_action_modify_ipv6
13110 (mhdr_res, actions, error))
13112 action_flags |= actions->type ==
13113 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13114 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13115 MLX5_FLOW_ACTION_SET_IPV6_DST;
13117 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13118 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13119 if (flow_dv_convert_action_modify_tp
13120 (mhdr_res, actions, items,
13121 &flow_attr, dev_flow, !!(action_flags &
13122 MLX5_FLOW_ACTION_DECAP), error))
13124 action_flags |= actions->type ==
13125 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13126 MLX5_FLOW_ACTION_SET_TP_SRC :
13127 MLX5_FLOW_ACTION_SET_TP_DST;
13129 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13130 if (flow_dv_convert_action_modify_dec_ttl
13131 (mhdr_res, items, &flow_attr, dev_flow,
13133 MLX5_FLOW_ACTION_DECAP), error))
13135 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13137 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13138 if (flow_dv_convert_action_modify_ttl
13139 (mhdr_res, actions, items, &flow_attr,
13140 dev_flow, !!(action_flags &
13141 MLX5_FLOW_ACTION_DECAP), error))
13143 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13145 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13146 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13147 if (flow_dv_convert_action_modify_tcp_seq
13148 (mhdr_res, actions, error))
13150 action_flags |= actions->type ==
13151 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13152 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13153 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13156 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13157 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13158 if (flow_dv_convert_action_modify_tcp_ack
13159 (mhdr_res, actions, error))
13161 action_flags |= actions->type ==
13162 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13163 MLX5_FLOW_ACTION_INC_TCP_ACK :
13164 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13166 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13167 if (flow_dv_convert_action_set_reg
13168 (mhdr_res, actions, error))
13170 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13172 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13173 if (flow_dv_convert_action_copy_mreg
13174 (dev, mhdr_res, actions, error))
13176 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13178 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13179 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13180 dev_flow->handle->fate_action =
13181 MLX5_FLOW_FATE_DEFAULT_MISS;
13183 case RTE_FLOW_ACTION_TYPE_METER:
13185 return rte_flow_error_set(error, rte_errno,
13186 RTE_FLOW_ERROR_TYPE_ACTION,
13187 NULL, "Failed to get meter in flow.");
13188 /* Set the meter action. */
13189 dev_flow->dv.actions[actions_n++] =
13190 wks->fm->meter_action;
13191 action_flags |= MLX5_FLOW_ACTION_METER;
13193 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13194 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13197 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13199 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13200 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13203 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13205 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13206 sample_act_pos = actions_n;
13207 sample = (const struct rte_flow_action_sample *)
13210 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13211 /* put encap action into group if work with port id */
13212 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13213 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13214 sample_act->action_flags |=
13215 MLX5_FLOW_ACTION_ENCAP;
13217 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13218 if (flow_dv_convert_action_modify_field
13219 (dev, mhdr_res, actions, attr, error))
13221 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13223 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13224 owner_idx = (uint32_t)(uintptr_t)action->conf;
13225 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13227 return rte_flow_error_set(error, EINVAL,
13228 RTE_FLOW_ERROR_TYPE_ACTION,
13230 "Failed to get CT object.");
13231 if (mlx5_aso_ct_available(priv->sh, ct))
13232 return rte_flow_error_set(error, rte_errno,
13233 RTE_FLOW_ERROR_TYPE_ACTION,
13235 "CT is unavailable.");
13236 if (ct->is_original)
13237 dev_flow->dv.actions[actions_n] =
13238 ct->dr_action_orig;
13240 dev_flow->dv.actions[actions_n] =
13241 ct->dr_action_rply;
13242 if (flow->ct == 0) {
13243 flow->indirect_type =
13244 MLX5_INDIRECT_ACTION_TYPE_CT;
13245 flow->ct = owner_idx;
13246 __atomic_fetch_add(&ct->refcnt, 1,
13250 action_flags |= MLX5_FLOW_ACTION_CT;
13252 case RTE_FLOW_ACTION_TYPE_END:
13253 actions_end = true;
13254 if (mhdr_res->actions_num) {
13255 /* create modify action if needed. */
13256 if (flow_dv_modify_hdr_resource_register
13257 (dev, mhdr_res, dev_flow, error))
13259 dev_flow->dv.actions[modify_action_position] =
13260 handle->dvh.modify_hdr->action;
13263 * Handle AGE and COUNT action by single HW counter
13264 * when they are not shared.
13266 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13267 if ((non_shared_age && count) ||
13268 !(priv->sh->flow_hit_aso_en &&
13269 (attr->group || attr->transfer))) {
13270 /* Creates age by counters. */
13271 cnt_act = flow_dv_prepare_counter
13278 dev_flow->dv.actions[age_act_pos] =
13282 if (!flow->age && non_shared_age) {
13283 flow->age = flow_dv_aso_age_alloc
13287 flow_dv_aso_age_params_init
13289 non_shared_age->context ?
13290 non_shared_age->context :
13291 (void *)(uintptr_t)
13292 (dev_flow->flow_idx),
13293 non_shared_age->timeout);
13295 age_act = flow_aso_age_get_by_idx(dev,
13297 dev_flow->dv.actions[age_act_pos] =
13298 age_act->dr_action;
13300 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13302 * Create one count action, to be used
13303 * by all sub-flows.
13305 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13310 dev_flow->dv.actions[actions_n++] =
13316 if (mhdr_res->actions_num &&
13317 modify_action_position == UINT32_MAX)
13318 modify_action_position = actions_n++;
13320 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13321 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13322 int item_type = items->type;
13324 if (!mlx5_flow_os_item_supported(item_type))
13325 return rte_flow_error_set(error, ENOTSUP,
13326 RTE_FLOW_ERROR_TYPE_ITEM,
13327 NULL, "item not supported");
13328 switch (item_type) {
13329 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13330 flow_dv_translate_item_port_id
13331 (dev, match_mask, match_value, items, attr);
13332 last_item = MLX5_FLOW_ITEM_PORT_ID;
13334 case RTE_FLOW_ITEM_TYPE_ETH:
13335 flow_dv_translate_item_eth(match_mask, match_value,
13337 dev_flow->dv.group);
13338 matcher.priority = action_flags &
13339 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13340 !dev_flow->external ?
13341 MLX5_PRIORITY_MAP_L3 :
13342 MLX5_PRIORITY_MAP_L2;
13343 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13344 MLX5_FLOW_LAYER_OUTER_L2;
13346 case RTE_FLOW_ITEM_TYPE_VLAN:
13347 flow_dv_translate_item_vlan(dev_flow,
13348 match_mask, match_value,
13350 dev_flow->dv.group);
13351 matcher.priority = MLX5_PRIORITY_MAP_L2;
13352 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13353 MLX5_FLOW_LAYER_INNER_VLAN) :
13354 (MLX5_FLOW_LAYER_OUTER_L2 |
13355 MLX5_FLOW_LAYER_OUTER_VLAN);
13357 case RTE_FLOW_ITEM_TYPE_IPV4:
13358 mlx5_flow_tunnel_ip_check(items, next_protocol,
13359 &item_flags, &tunnel);
13360 flow_dv_translate_item_ipv4(match_mask, match_value,
13362 dev_flow->dv.group);
13363 matcher.priority = MLX5_PRIORITY_MAP_L3;
13364 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13365 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13366 if (items->mask != NULL &&
13367 ((const struct rte_flow_item_ipv4 *)
13368 items->mask)->hdr.next_proto_id) {
13370 ((const struct rte_flow_item_ipv4 *)
13371 (items->spec))->hdr.next_proto_id;
13373 ((const struct rte_flow_item_ipv4 *)
13374 (items->mask))->hdr.next_proto_id;
13376 /* Reset for inner layer. */
13377 next_protocol = 0xff;
13380 case RTE_FLOW_ITEM_TYPE_IPV6:
13381 mlx5_flow_tunnel_ip_check(items, next_protocol,
13382 &item_flags, &tunnel);
13383 flow_dv_translate_item_ipv6(match_mask, match_value,
13385 dev_flow->dv.group);
13386 matcher.priority = MLX5_PRIORITY_MAP_L3;
13387 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13388 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13389 if (items->mask != NULL &&
13390 ((const struct rte_flow_item_ipv6 *)
13391 items->mask)->hdr.proto) {
13393 ((const struct rte_flow_item_ipv6 *)
13394 items->spec)->hdr.proto;
13396 ((const struct rte_flow_item_ipv6 *)
13397 items->mask)->hdr.proto;
13399 /* Reset for inner layer. */
13400 next_protocol = 0xff;
13403 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13404 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13407 last_item = tunnel ?
13408 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13409 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13410 if (items->mask != NULL &&
13411 ((const struct rte_flow_item_ipv6_frag_ext *)
13412 items->mask)->hdr.next_header) {
13414 ((const struct rte_flow_item_ipv6_frag_ext *)
13415 items->spec)->hdr.next_header;
13417 ((const struct rte_flow_item_ipv6_frag_ext *)
13418 items->mask)->hdr.next_header;
13420 /* Reset for inner layer. */
13421 next_protocol = 0xff;
13424 case RTE_FLOW_ITEM_TYPE_TCP:
13425 flow_dv_translate_item_tcp(match_mask, match_value,
13427 matcher.priority = MLX5_PRIORITY_MAP_L4;
13428 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13429 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13431 case RTE_FLOW_ITEM_TYPE_UDP:
13432 flow_dv_translate_item_udp(match_mask, match_value,
13434 matcher.priority = MLX5_PRIORITY_MAP_L4;
13435 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13436 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13438 case RTE_FLOW_ITEM_TYPE_GRE:
13439 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13440 last_item = MLX5_FLOW_LAYER_GRE;
13441 tunnel_item = items;
13443 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13444 flow_dv_translate_item_gre_key(match_mask,
13445 match_value, items);
13446 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13448 case RTE_FLOW_ITEM_TYPE_NVGRE:
13449 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13450 last_item = MLX5_FLOW_LAYER_GRE;
13451 tunnel_item = items;
13453 case RTE_FLOW_ITEM_TYPE_VXLAN:
13454 flow_dv_translate_item_vxlan(dev, attr,
13455 match_mask, match_value,
13457 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13458 last_item = MLX5_FLOW_LAYER_VXLAN;
13460 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13461 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13462 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13463 tunnel_item = items;
13465 case RTE_FLOW_ITEM_TYPE_GENEVE:
13466 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13467 last_item = MLX5_FLOW_LAYER_GENEVE;
13468 tunnel_item = items;
13470 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13471 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13475 return rte_flow_error_set(error, -ret,
13476 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13477 "cannot create GENEVE TLV option");
13478 flow->geneve_tlv_option = 1;
13479 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13481 case RTE_FLOW_ITEM_TYPE_MPLS:
13482 flow_dv_translate_item_mpls(match_mask, match_value,
13483 items, last_item, tunnel);
13484 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13485 last_item = MLX5_FLOW_LAYER_MPLS;
13487 case RTE_FLOW_ITEM_TYPE_MARK:
13488 flow_dv_translate_item_mark(dev, match_mask,
13489 match_value, items);
13490 last_item = MLX5_FLOW_ITEM_MARK;
13492 case RTE_FLOW_ITEM_TYPE_META:
13493 flow_dv_translate_item_meta(dev, match_mask,
13494 match_value, attr, items);
13495 last_item = MLX5_FLOW_ITEM_METADATA;
13497 case RTE_FLOW_ITEM_TYPE_ICMP:
13498 flow_dv_translate_item_icmp(match_mask, match_value,
13500 last_item = MLX5_FLOW_LAYER_ICMP;
13502 case RTE_FLOW_ITEM_TYPE_ICMP6:
13503 flow_dv_translate_item_icmp6(match_mask, match_value,
13505 last_item = MLX5_FLOW_LAYER_ICMP6;
13507 case RTE_FLOW_ITEM_TYPE_TAG:
13508 flow_dv_translate_item_tag(dev, match_mask,
13509 match_value, items);
13510 last_item = MLX5_FLOW_ITEM_TAG;
13512 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13513 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13514 match_value, items);
13515 last_item = MLX5_FLOW_ITEM_TAG;
13517 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13518 flow_dv_translate_item_tx_queue(dev, match_mask,
13521 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13523 case RTE_FLOW_ITEM_TYPE_GTP:
13524 flow_dv_translate_item_gtp(match_mask, match_value,
13526 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13527 last_item = MLX5_FLOW_LAYER_GTP;
13529 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13530 ret = flow_dv_translate_item_gtp_psc(match_mask,
13534 return rte_flow_error_set(error, -ret,
13535 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13536 "cannot create GTP PSC item");
13537 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13539 case RTE_FLOW_ITEM_TYPE_ECPRI:
13540 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13541 /* Create it only the first time to be used. */
13542 ret = mlx5_flex_parser_ecpri_alloc(dev);
13544 return rte_flow_error_set
13546 RTE_FLOW_ERROR_TYPE_ITEM,
13548 "cannot create eCPRI parser");
13550 flow_dv_translate_item_ecpri(dev, match_mask,
13551 match_value, items,
13553 /* No other protocol should follow eCPRI layer. */
13554 last_item = MLX5_FLOW_LAYER_ECPRI;
13556 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13557 flow_dv_translate_item_integrity(items, integrity_items,
13560 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13561 flow_dv_translate_item_aso_ct(dev, match_mask,
13562 match_value, items);
13564 case RTE_FLOW_ITEM_TYPE_FLEX:
13565 flow_dv_translate_item_flex(dev, match_mask,
13566 match_value, items,
13567 dev_flow, tunnel != 0);
13568 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13569 MLX5_FLOW_ITEM_OUTER_FLEX;
13574 item_flags |= last_item;
13577 * When E-Switch mode is enabled, we have two cases where we need to
13578 * set the source port manually.
13579 * The first one, is in case of Nic steering rule, and the second is
13580 * E-Switch rule where no port_id item was found. In both cases
13581 * the source port is set according the current port in use.
13583 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13584 (priv->representor || priv->master)) {
13585 if (flow_dv_translate_item_port_id(dev, match_mask,
13586 match_value, NULL, attr))
13589 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13590 flow_dv_translate_item_integrity_post(match_mask, match_value,
13594 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13595 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13596 tunnel_item, item_flags);
13597 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13598 flow_dv_translate_item_geneve(match_mask, match_value,
13599 tunnel_item, item_flags);
13600 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13601 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13602 flow_dv_translate_item_gre(match_mask, match_value,
13603 tunnel_item, item_flags);
13604 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13605 flow_dv_translate_item_nvgre(match_mask, match_value,
13606 tunnel_item, item_flags);
13608 MLX5_ASSERT(false);
13610 #ifdef RTE_LIBRTE_MLX5_DEBUG
13611 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13612 dev_flow->dv.value.buf));
13615 * Layers may be already initialized from prefix flow if this dev_flow
13616 * is the suffix flow.
13618 handle->layers |= item_flags;
13619 if (action_flags & MLX5_FLOW_ACTION_RSS)
13620 flow_dv_hashfields_set(dev_flow, rss_desc);
13621 /* If has RSS action in the sample action, the Sample/Mirror resource
13622 * should be registered after the hash filed be update.
13624 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13625 ret = flow_dv_translate_action_sample(dev,
13634 ret = flow_dv_create_action_sample(dev,
13643 return rte_flow_error_set
13645 RTE_FLOW_ERROR_TYPE_ACTION,
13647 "cannot create sample action");
13648 if (num_of_dest > 1) {
13649 dev_flow->dv.actions[sample_act_pos] =
13650 dev_flow->dv.dest_array_res->action;
13652 dev_flow->dv.actions[sample_act_pos] =
13653 dev_flow->dv.sample_res->verbs_action;
13657 * For multiple destination (sample action with ratio=1), the encap
13658 * action and port id action will be combined into group action.
13659 * So need remove the original these actions in the flow and only
13660 * use the sample action instead of.
13662 if (num_of_dest > 1 &&
13663 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13665 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13667 for (i = 0; i < actions_n; i++) {
13668 if ((sample_act->dr_encap_action &&
13669 sample_act->dr_encap_action ==
13670 dev_flow->dv.actions[i]) ||
13671 (sample_act->dr_port_id_action &&
13672 sample_act->dr_port_id_action ==
13673 dev_flow->dv.actions[i]) ||
13674 (sample_act->dr_jump_action &&
13675 sample_act->dr_jump_action ==
13676 dev_flow->dv.actions[i]))
13678 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13680 memcpy((void *)dev_flow->dv.actions,
13681 (void *)temp_actions,
13682 tmp_actions_n * sizeof(void *));
13683 actions_n = tmp_actions_n;
13685 dev_flow->dv.actions_n = actions_n;
13686 dev_flow->act_flags = action_flags;
13687 if (wks->skip_matcher_reg)
13689 /* Register matcher. */
13690 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13691 matcher.mask.size);
13692 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13694 dev_flow->external);
13696 * When creating meter drop flow in drop table, using original
13697 * 5-tuple match, the matcher priority should be lower than
13700 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13701 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13702 matcher.priority <= MLX5_REG_BITS)
13703 matcher.priority += MLX5_REG_BITS;
13704 /* reserved field no needs to be set to 0 here. */
13705 tbl_key.is_fdb = attr->transfer;
13706 tbl_key.is_egress = attr->egress;
13707 tbl_key.level = dev_flow->dv.group;
13708 tbl_key.id = dev_flow->dv.table_id;
13709 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13710 tunnel, attr->group, error))
13716 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13719 * @param[in, out] action
13720 * Shred RSS action holding hash RX queue objects.
13721 * @param[in] hash_fields
13722 * Defines combination of packet fields to participate in RX hash.
13723 * @param[in] tunnel
13725 * @param[in] hrxq_idx
13726 * Hash RX queue index to set.
13729 * 0 on success, otherwise negative errno value.
13732 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13733 const uint64_t hash_fields,
13736 uint32_t *hrxqs = action->hrxq;
13738 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13739 case MLX5_RSS_HASH_IPV4:
13740 /* fall-through. */
13741 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13742 /* fall-through. */
13743 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13744 hrxqs[0] = hrxq_idx;
13746 case MLX5_RSS_HASH_IPV4_TCP:
13747 /* fall-through. */
13748 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13749 /* fall-through. */
13750 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13751 hrxqs[1] = hrxq_idx;
13753 case MLX5_RSS_HASH_IPV4_UDP:
13754 /* fall-through. */
13755 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13756 /* fall-through. */
13757 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13758 hrxqs[2] = hrxq_idx;
13760 case MLX5_RSS_HASH_IPV6:
13761 /* fall-through. */
13762 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13763 /* fall-through. */
13764 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13765 hrxqs[3] = hrxq_idx;
13767 case MLX5_RSS_HASH_IPV6_TCP:
13768 /* fall-through. */
13769 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13770 /* fall-through. */
13771 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13772 hrxqs[4] = hrxq_idx;
13774 case MLX5_RSS_HASH_IPV6_UDP:
13775 /* fall-through. */
13776 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13777 /* fall-through. */
13778 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13779 hrxqs[5] = hrxq_idx;
13781 case MLX5_RSS_HASH_NONE:
13782 hrxqs[6] = hrxq_idx;
13790 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13794 * Pointer to the Ethernet device structure.
13796 * Shared RSS action ID holding hash RX queue objects.
13797 * @param[in] hash_fields
13798 * Defines combination of packet fields to participate in RX hash.
13799 * @param[in] tunnel
13803 * Valid hash RX queue index, otherwise 0.
13806 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13807 const uint64_t hash_fields)
13809 struct mlx5_priv *priv = dev->data->dev_private;
13810 struct mlx5_shared_action_rss *shared_rss =
13811 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13812 const uint32_t *hrxqs = shared_rss->hrxq;
13814 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13815 case MLX5_RSS_HASH_IPV4:
13816 /* fall-through. */
13817 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13818 /* fall-through. */
13819 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13821 case MLX5_RSS_HASH_IPV4_TCP:
13822 /* fall-through. */
13823 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13824 /* fall-through. */
13825 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13827 case MLX5_RSS_HASH_IPV4_UDP:
13828 /* fall-through. */
13829 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13830 /* fall-through. */
13831 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13833 case MLX5_RSS_HASH_IPV6:
13834 /* fall-through. */
13835 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13836 /* fall-through. */
13837 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13839 case MLX5_RSS_HASH_IPV6_TCP:
13840 /* fall-through. */
13841 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13842 /* fall-through. */
13843 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13845 case MLX5_RSS_HASH_IPV6_UDP:
13846 /* fall-through. */
13847 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13848 /* fall-through. */
13849 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13851 case MLX5_RSS_HASH_NONE:
13860 * Apply the flow to the NIC, lock free,
13861 * (mutex should be acquired by caller).
13864 * Pointer to the Ethernet device structure.
13865 * @param[in, out] flow
13866 * Pointer to flow structure.
13867 * @param[out] error
13868 * Pointer to error structure.
13871 * 0 on success, a negative errno value otherwise and rte_errno is set.
13874 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13875 struct rte_flow_error *error)
13877 struct mlx5_flow_dv_workspace *dv;
13878 struct mlx5_flow_handle *dh;
13879 struct mlx5_flow_handle_dv *dv_h;
13880 struct mlx5_flow *dev_flow;
13881 struct mlx5_priv *priv = dev->data->dev_private;
13882 uint32_t handle_idx;
13886 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13887 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13891 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13892 dev_flow = &wks->flows[idx];
13893 dv = &dev_flow->dv;
13894 dh = dev_flow->handle;
13897 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13898 if (dv->transfer) {
13899 MLX5_ASSERT(priv->sh->dr_drop_action);
13900 dv->actions[n++] = priv->sh->dr_drop_action;
13902 #ifdef HAVE_MLX5DV_DR
13903 /* DR supports drop action placeholder. */
13904 MLX5_ASSERT(priv->sh->dr_drop_action);
13905 dv->actions[n++] = dv->group ?
13906 priv->sh->dr_drop_action :
13907 priv->root_drop_action;
13909 /* For DV we use the explicit drop queue. */
13910 MLX5_ASSERT(priv->drop_queue.hrxq);
13912 priv->drop_queue.hrxq->action;
13915 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13916 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13917 struct mlx5_hrxq *hrxq;
13920 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13925 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13926 "cannot get hash queue");
13929 dh->rix_hrxq = hrxq_idx;
13930 dv->actions[n++] = hrxq->action;
13931 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13932 struct mlx5_hrxq *hrxq = NULL;
13935 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13936 rss_desc->shared_rss,
13937 dev_flow->hash_fields);
13939 hrxq = mlx5_ipool_get
13940 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13945 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13946 "cannot get hash queue");
13949 dh->rix_srss = rss_desc->shared_rss;
13950 dv->actions[n++] = hrxq->action;
13951 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13952 if (!priv->sh->default_miss_action) {
13955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13956 "default miss action not be created.");
13959 dv->actions[n++] = priv->sh->default_miss_action;
13961 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13962 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13963 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13964 (void *)&dv->value, n,
13965 dv->actions, &dh->drv_flow);
13969 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13971 (!priv->config.allow_duplicate_pattern &&
13973 "duplicating pattern is not allowed" :
13974 "hardware refuses to create flow");
13977 if (priv->vmwa_context &&
13978 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13980 * The rule contains the VLAN pattern.
13981 * For VF we are going to create VLAN
13982 * interface to make hypervisor set correct
13983 * e-Switch vport context.
13985 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13990 err = rte_errno; /* Save rte_errno before cleanup. */
13991 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13992 handle_idx, dh, next) {
13993 /* hrxq is union, don't clear it if the flag is not set. */
13994 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13995 mlx5_hrxq_release(dev, dh->rix_hrxq);
13997 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14000 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14001 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14003 rte_errno = err; /* Restore rte_errno. */
14008 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14009 struct mlx5_list_entry *entry)
14011 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14015 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14016 mlx5_free(resource);
14020 * Release the flow matcher.
14023 * Pointer to Ethernet device.
14025 * Index to port ID action resource.
14028 * 1 while a reference on it exists, 0 when freed.
14031 flow_dv_matcher_release(struct rte_eth_dev *dev,
14032 struct mlx5_flow_handle *handle)
14034 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14035 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14036 typeof(*tbl), tbl);
14039 MLX5_ASSERT(matcher->matcher_object);
14040 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14041 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14046 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14048 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14049 struct mlx5_flow_dv_encap_decap_resource *res =
14050 container_of(entry, typeof(*res), entry);
14052 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14053 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14057 * Release an encap/decap resource.
14060 * Pointer to Ethernet device.
14061 * @param encap_decap_idx
14062 * Index of encap decap resource.
14065 * 1 while a reference on it exists, 0 when freed.
14068 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14069 uint32_t encap_decap_idx)
14071 struct mlx5_priv *priv = dev->data->dev_private;
14072 struct mlx5_flow_dv_encap_decap_resource *resource;
14074 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14078 MLX5_ASSERT(resource->action);
14079 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14083 * Release an jump to table action resource.
14086 * Pointer to Ethernet device.
14088 * Index to the jump action resource.
14091 * 1 while a reference on it exists, 0 when freed.
14094 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14097 struct mlx5_priv *priv = dev->data->dev_private;
14098 struct mlx5_flow_tbl_data_entry *tbl_data;
14100 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14104 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14108 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14110 struct mlx5_flow_dv_modify_hdr_resource *res =
14111 container_of(entry, typeof(*res), entry);
14112 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14114 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14115 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14119 * Release a modify-header resource.
14122 * Pointer to Ethernet device.
14124 * Pointer to mlx5_flow_handle.
14127 * 1 while a reference on it exists, 0 when freed.
14130 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14131 struct mlx5_flow_handle *handle)
14133 struct mlx5_priv *priv = dev->data->dev_private;
14134 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14136 MLX5_ASSERT(entry->action);
14137 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14141 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14143 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14144 struct mlx5_flow_dv_port_id_action_resource *resource =
14145 container_of(entry, typeof(*resource), entry);
14147 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14148 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14152 * Release port ID action resource.
14155 * Pointer to Ethernet device.
14157 * Pointer to mlx5_flow_handle.
14160 * 1 while a reference on it exists, 0 when freed.
14163 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14166 struct mlx5_priv *priv = dev->data->dev_private;
14167 struct mlx5_flow_dv_port_id_action_resource *resource;
14169 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14172 MLX5_ASSERT(resource->action);
14173 return mlx5_list_unregister(priv->sh->port_id_action_list,
14178 * Release shared RSS action resource.
14181 * Pointer to Ethernet device.
14183 * Shared RSS action index.
14186 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14188 struct mlx5_priv *priv = dev->data->dev_private;
14189 struct mlx5_shared_action_rss *shared_rss;
14191 shared_rss = mlx5_ipool_get
14192 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14193 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14197 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14199 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14200 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14201 container_of(entry, typeof(*resource), entry);
14203 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14204 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14208 * Release push vlan action resource.
14211 * Pointer to Ethernet device.
14213 * Pointer to mlx5_flow_handle.
14216 * 1 while a reference on it exists, 0 when freed.
14219 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14220 struct mlx5_flow_handle *handle)
14222 struct mlx5_priv *priv = dev->data->dev_private;
14223 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14224 uint32_t idx = handle->dvh.rix_push_vlan;
14226 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14229 MLX5_ASSERT(resource->action);
14230 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14235 * Release the fate resource.
14238 * Pointer to Ethernet device.
14240 * Pointer to mlx5_flow_handle.
14243 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14244 struct mlx5_flow_handle *handle)
14246 if (!handle->rix_fate)
14248 switch (handle->fate_action) {
14249 case MLX5_FLOW_FATE_QUEUE:
14250 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14251 mlx5_hrxq_release(dev, handle->rix_hrxq);
14253 case MLX5_FLOW_FATE_JUMP:
14254 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14256 case MLX5_FLOW_FATE_PORT_ID:
14257 flow_dv_port_id_action_resource_release(dev,
14258 handle->rix_port_id_action);
14261 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14264 handle->rix_fate = 0;
14268 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14269 struct mlx5_list_entry *entry)
14271 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14274 struct rte_eth_dev *dev = resource->dev;
14275 struct mlx5_priv *priv = dev->data->dev_private;
14277 if (resource->verbs_action)
14278 claim_zero(mlx5_flow_os_destroy_flow_action
14279 (resource->verbs_action));
14280 if (resource->normal_path_tbl)
14281 flow_dv_tbl_resource_release(MLX5_SH(dev),
14282 resource->normal_path_tbl);
14283 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14284 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14285 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14289 * Release an sample resource.
14292 * Pointer to Ethernet device.
14294 * Pointer to mlx5_flow_handle.
14297 * 1 while a reference on it exists, 0 when freed.
14300 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14301 struct mlx5_flow_handle *handle)
14303 struct mlx5_priv *priv = dev->data->dev_private;
14304 struct mlx5_flow_dv_sample_resource *resource;
14306 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14307 handle->dvh.rix_sample);
14310 MLX5_ASSERT(resource->verbs_action);
14311 return mlx5_list_unregister(priv->sh->sample_action_list,
14316 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14317 struct mlx5_list_entry *entry)
14319 struct mlx5_flow_dv_dest_array_resource *resource =
14320 container_of(entry, typeof(*resource), entry);
14321 struct rte_eth_dev *dev = resource->dev;
14322 struct mlx5_priv *priv = dev->data->dev_private;
14325 MLX5_ASSERT(resource->action);
14326 if (resource->action)
14327 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14328 for (; i < resource->num_of_dest; i++)
14329 flow_dv_sample_sub_actions_release(dev,
14330 &resource->sample_idx[i]);
14331 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14332 DRV_LOG(DEBUG, "destination array resource %p: removed",
14337 * Release an destination array resource.
14340 * Pointer to Ethernet device.
14342 * Pointer to mlx5_flow_handle.
14345 * 1 while a reference on it exists, 0 when freed.
14348 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14349 struct mlx5_flow_handle *handle)
14351 struct mlx5_priv *priv = dev->data->dev_private;
14352 struct mlx5_flow_dv_dest_array_resource *resource;
14354 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14355 handle->dvh.rix_dest_array);
14358 MLX5_ASSERT(resource->action);
14359 return mlx5_list_unregister(priv->sh->dest_array_list,
14364 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14366 struct mlx5_priv *priv = dev->data->dev_private;
14367 struct mlx5_dev_ctx_shared *sh = priv->sh;
14368 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14369 sh->geneve_tlv_option_resource;
14370 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14371 if (geneve_opt_resource) {
14372 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14373 __ATOMIC_RELAXED))) {
14374 claim_zero(mlx5_devx_cmd_destroy
14375 (geneve_opt_resource->obj));
14376 mlx5_free(sh->geneve_tlv_option_resource);
14377 sh->geneve_tlv_option_resource = NULL;
14380 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14384 * Remove the flow from the NIC but keeps it in memory.
14385 * Lock free, (mutex should be acquired by caller).
14388 * Pointer to Ethernet device.
14389 * @param[in, out] flow
14390 * Pointer to flow structure.
14393 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14395 struct mlx5_flow_handle *dh;
14396 uint32_t handle_idx;
14397 struct mlx5_priv *priv = dev->data->dev_private;
14401 handle_idx = flow->dev_handles;
14402 while (handle_idx) {
14403 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14407 if (dh->drv_flow) {
14408 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14409 dh->drv_flow = NULL;
14411 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14412 flow_dv_fate_resource_release(dev, dh);
14413 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14414 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14415 handle_idx = dh->next.next;
14420 * Remove the flow from the NIC and the memory.
14421 * Lock free, (mutex should be acquired by caller).
14424 * Pointer to the Ethernet device structure.
14425 * @param[in, out] flow
14426 * Pointer to flow structure.
14429 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14431 struct mlx5_flow_handle *dev_handle;
14432 struct mlx5_priv *priv = dev->data->dev_private;
14433 struct mlx5_flow_meter_info *fm = NULL;
14438 flow_dv_remove(dev, flow);
14439 if (flow->counter) {
14440 flow_dv_counter_free(dev, flow->counter);
14444 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14446 mlx5_flow_meter_detach(priv, fm);
14449 /* Keep the current age handling by default. */
14450 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14451 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14452 else if (flow->age)
14453 flow_dv_aso_age_release(dev, flow->age);
14454 if (flow->geneve_tlv_option) {
14455 flow_dv_geneve_tlv_option_resource_release(dev);
14456 flow->geneve_tlv_option = 0;
14458 while (flow->dev_handles) {
14459 uint32_t tmp_idx = flow->dev_handles;
14461 dev_handle = mlx5_ipool_get(priv->sh->ipool
14462 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14465 flow->dev_handles = dev_handle->next.next;
14466 while (dev_handle->flex_item) {
14467 int index = rte_bsf32(dev_handle->flex_item);
14469 mlx5_flex_release_index(dev, index);
14470 dev_handle->flex_item &= ~RTE_BIT32(index);
14472 if (dev_handle->dvh.matcher)
14473 flow_dv_matcher_release(dev, dev_handle);
14474 if (dev_handle->dvh.rix_sample)
14475 flow_dv_sample_resource_release(dev, dev_handle);
14476 if (dev_handle->dvh.rix_dest_array)
14477 flow_dv_dest_array_resource_release(dev, dev_handle);
14478 if (dev_handle->dvh.rix_encap_decap)
14479 flow_dv_encap_decap_resource_release(dev,
14480 dev_handle->dvh.rix_encap_decap);
14481 if (dev_handle->dvh.modify_hdr)
14482 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14483 if (dev_handle->dvh.rix_push_vlan)
14484 flow_dv_push_vlan_action_resource_release(dev,
14486 if (dev_handle->dvh.rix_tag)
14487 flow_dv_tag_release(dev,
14488 dev_handle->dvh.rix_tag);
14489 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14490 flow_dv_fate_resource_release(dev, dev_handle);
14492 srss = dev_handle->rix_srss;
14493 if (fm && dev_handle->is_meter_flow_id &&
14494 dev_handle->split_flow_id)
14495 mlx5_ipool_free(fm->flow_ipool,
14496 dev_handle->split_flow_id);
14497 else if (dev_handle->split_flow_id &&
14498 !dev_handle->is_meter_flow_id)
14499 mlx5_ipool_free(priv->sh->ipool
14500 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14501 dev_handle->split_flow_id);
14502 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14506 flow_dv_shared_rss_action_release(dev, srss);
14510 * Release array of hash RX queue objects.
14514 * Pointer to the Ethernet device structure.
14515 * @param[in, out] hrxqs
14516 * Array of hash RX queue objects.
14519 * Total number of references to hash RX queue objects in *hrxqs* array
14520 * after this operation.
14523 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14524 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14529 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14530 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14540 * Release all hash RX queue objects representing shared RSS action.
14543 * Pointer to the Ethernet device structure.
14544 * @param[in, out] action
14545 * Shared RSS action to remove hash RX queue objects from.
14548 * Total number of references to hash RX queue objects stored in *action*
14549 * after this operation.
14550 * Expected to be 0 if no external references held.
14553 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14554 struct mlx5_shared_action_rss *shared_rss)
14556 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14560 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14563 * Only one hash value is available for one L3+L4 combination:
14565 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14566 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14567 * same slot in mlx5_rss_hash_fields.
14570 * Pointer to the shared action RSS conf.
14571 * @param[in, out] hash_field
14572 * hash_field variable needed to be adjusted.
14578 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14579 uint64_t *hash_field)
14581 uint64_t rss_types = rss->origin.types;
14583 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14584 case MLX5_RSS_HASH_IPV4:
14585 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14586 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14587 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14588 *hash_field |= IBV_RX_HASH_DST_IPV4;
14589 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14590 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14592 *hash_field |= MLX5_RSS_HASH_IPV4;
14595 case MLX5_RSS_HASH_IPV6:
14596 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14597 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14598 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14599 *hash_field |= IBV_RX_HASH_DST_IPV6;
14600 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14601 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14603 *hash_field |= MLX5_RSS_HASH_IPV6;
14606 case MLX5_RSS_HASH_IPV4_UDP:
14607 /* fall-through. */
14608 case MLX5_RSS_HASH_IPV6_UDP:
14609 if (rss_types & RTE_ETH_RSS_UDP) {
14610 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14611 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14612 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14613 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14614 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14616 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14619 case MLX5_RSS_HASH_IPV4_TCP:
14620 /* fall-through. */
14621 case MLX5_RSS_HASH_IPV6_TCP:
14622 if (rss_types & RTE_ETH_RSS_TCP) {
14623 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14624 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14625 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14626 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14627 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14629 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14638 * Setup shared RSS action.
14639 * Prepare set of hash RX queue objects sufficient to handle all valid
14640 * hash_fields combinations (see enum ibv_rx_hash_fields).
14643 * Pointer to the Ethernet device structure.
14644 * @param[in] action_idx
14645 * Shared RSS action ipool index.
14646 * @param[in, out] action
14647 * Partially initialized shared RSS action.
14648 * @param[out] error
14649 * Perform verbose error reporting if not NULL. Initialized in case of
14653 * 0 on success, otherwise negative errno value.
14656 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14657 uint32_t action_idx,
14658 struct mlx5_shared_action_rss *shared_rss,
14659 struct rte_flow_error *error)
14661 struct mlx5_flow_rss_desc rss_desc = { 0 };
14665 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14666 return rte_flow_error_set(error, rte_errno,
14667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14668 "cannot setup indirection table");
14670 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14671 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14672 rss_desc.const_q = shared_rss->origin.queue;
14673 rss_desc.queue_num = shared_rss->origin.queue_num;
14674 /* Set non-zero value to indicate a shared RSS. */
14675 rss_desc.shared_rss = action_idx;
14676 rss_desc.ind_tbl = shared_rss->ind_tbl;
14677 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14679 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14682 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14683 if (shared_rss->origin.level > 1) {
14684 hash_fields |= IBV_RX_HASH_INNER;
14687 rss_desc.tunnel = tunnel;
14688 rss_desc.hash_fields = hash_fields;
14689 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14693 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14694 "cannot get hash queue");
14695 goto error_hrxq_new;
14697 err = __flow_dv_action_rss_hrxq_set
14698 (shared_rss, hash_fields, hrxq_idx);
14704 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14705 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14706 shared_rss->ind_tbl = NULL;
14712 * Create shared RSS action.
14715 * Pointer to the Ethernet device structure.
14717 * Shared action configuration.
14719 * RSS action specification used to create shared action.
14720 * @param[out] error
14721 * Perform verbose error reporting if not NULL. Initialized in case of
14725 * A valid shared action ID in case of success, 0 otherwise and
14726 * rte_errno is set.
14729 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14730 const struct rte_flow_indir_action_conf *conf,
14731 const struct rte_flow_action_rss *rss,
14732 struct rte_flow_error *error)
14734 struct mlx5_priv *priv = dev->data->dev_private;
14735 struct mlx5_shared_action_rss *shared_rss = NULL;
14736 void *queue = NULL;
14737 struct rte_flow_action_rss *origin;
14738 const uint8_t *rss_key;
14739 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14742 RTE_SET_USED(conf);
14743 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14745 shared_rss = mlx5_ipool_zmalloc
14746 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14747 if (!shared_rss || !queue) {
14748 rte_flow_error_set(error, ENOMEM,
14749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14750 "cannot allocate resource memory");
14751 goto error_rss_init;
14753 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14754 rte_flow_error_set(error, E2BIG,
14755 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14756 "rss action number out of range");
14757 goto error_rss_init;
14759 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14760 sizeof(*shared_rss->ind_tbl),
14762 if (!shared_rss->ind_tbl) {
14763 rte_flow_error_set(error, ENOMEM,
14764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14765 "cannot allocate resource memory");
14766 goto error_rss_init;
14768 memcpy(queue, rss->queue, queue_size);
14769 shared_rss->ind_tbl->queues = queue;
14770 shared_rss->ind_tbl->queues_n = rss->queue_num;
14771 origin = &shared_rss->origin;
14772 origin->func = rss->func;
14773 origin->level = rss->level;
14774 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14775 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14776 /* NULL RSS key indicates default RSS key. */
14777 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14778 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14779 origin->key = &shared_rss->key[0];
14780 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14781 origin->queue = queue;
14782 origin->queue_num = rss->queue_num;
14783 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14784 goto error_rss_init;
14785 rte_spinlock_init(&shared_rss->action_rss_sl);
14786 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14787 rte_spinlock_lock(&priv->shared_act_sl);
14788 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14789 &priv->rss_shared_actions, idx, shared_rss, next);
14790 rte_spinlock_unlock(&priv->shared_act_sl);
14794 if (shared_rss->ind_tbl)
14795 mlx5_free(shared_rss->ind_tbl);
14796 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14805 * Destroy the shared RSS action.
14806 * Release related hash RX queue objects.
14809 * Pointer to the Ethernet device structure.
14811 * The shared RSS action object ID to be removed.
14812 * @param[out] error
14813 * Perform verbose error reporting if not NULL. Initialized in case of
14817 * 0 on success, otherwise negative errno value.
14820 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14821 struct rte_flow_error *error)
14823 struct mlx5_priv *priv = dev->data->dev_private;
14824 struct mlx5_shared_action_rss *shared_rss =
14825 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14826 uint32_t old_refcnt = 1;
14828 uint16_t *queue = NULL;
14831 return rte_flow_error_set(error, EINVAL,
14832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14833 "invalid shared action");
14834 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14835 0, 0, __ATOMIC_ACQUIRE,
14837 return rte_flow_error_set(error, EBUSY,
14838 RTE_FLOW_ERROR_TYPE_ACTION,
14840 "shared rss has references");
14841 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14843 return rte_flow_error_set(error, EBUSY,
14844 RTE_FLOW_ERROR_TYPE_ACTION,
14846 "shared rss hrxq has references");
14847 queue = shared_rss->ind_tbl->queues;
14848 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14850 return rte_flow_error_set(error, EBUSY,
14851 RTE_FLOW_ERROR_TYPE_ACTION,
14853 "shared rss indirection table has"
14856 rte_spinlock_lock(&priv->shared_act_sl);
14857 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14858 &priv->rss_shared_actions, idx, shared_rss, next);
14859 rte_spinlock_unlock(&priv->shared_act_sl);
14860 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14866 * Create indirect action, lock free,
14867 * (mutex should be acquired by caller).
14868 * Dispatcher for action type specific call.
14871 * Pointer to the Ethernet device structure.
14873 * Shared action configuration.
14874 * @param[in] action
14875 * Action specification used to create indirect action.
14876 * @param[out] error
14877 * Perform verbose error reporting if not NULL. Initialized in case of
14881 * A valid shared action handle in case of success, NULL otherwise and
14882 * rte_errno is set.
14884 static struct rte_flow_action_handle *
14885 flow_dv_action_create(struct rte_eth_dev *dev,
14886 const struct rte_flow_indir_action_conf *conf,
14887 const struct rte_flow_action *action,
14888 struct rte_flow_error *err)
14890 struct mlx5_priv *priv = dev->data->dev_private;
14891 uint32_t age_idx = 0;
14895 switch (action->type) {
14896 case RTE_FLOW_ACTION_TYPE_RSS:
14897 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14898 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14899 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14901 case RTE_FLOW_ACTION_TYPE_AGE:
14902 age_idx = flow_dv_aso_age_alloc(dev, err);
14907 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14908 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14909 flow_dv_aso_age_params_init(dev, age_idx,
14910 ((const struct rte_flow_action_age *)
14911 action->conf)->context ?
14912 ((const struct rte_flow_action_age *)
14913 action->conf)->context :
14914 (void *)(uintptr_t)idx,
14915 ((const struct rte_flow_action_age *)
14916 action->conf)->timeout);
14919 case RTE_FLOW_ACTION_TYPE_COUNT:
14920 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14921 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14922 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14924 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14925 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14927 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14930 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14931 NULL, "action type not supported");
14934 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14938 * Destroy the indirect action.
14939 * Release action related resources on the NIC and the memory.
14940 * Lock free, (mutex should be acquired by caller).
14941 * Dispatcher for action type specific call.
14944 * Pointer to the Ethernet device structure.
14945 * @param[in] handle
14946 * The indirect action object handle to be removed.
14947 * @param[out] error
14948 * Perform verbose error reporting if not NULL. Initialized in case of
14952 * 0 on success, otherwise negative errno value.
14955 flow_dv_action_destroy(struct rte_eth_dev *dev,
14956 struct rte_flow_action_handle *handle,
14957 struct rte_flow_error *error)
14959 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14960 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14961 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14962 struct mlx5_flow_counter *cnt;
14963 uint32_t no_flow_refcnt = 1;
14967 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14968 return __flow_dv_action_rss_release(dev, idx, error);
14969 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14970 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14971 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14972 &no_flow_refcnt, 1, false,
14975 return rte_flow_error_set(error, EBUSY,
14976 RTE_FLOW_ERROR_TYPE_ACTION,
14978 "Indirect count action has references");
14979 flow_dv_counter_free(dev, idx);
14981 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14982 ret = flow_dv_aso_age_release(dev, idx);
14985 * In this case, the last flow has a reference will
14986 * actually release the age action.
14988 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14989 " released with references %d.", idx, ret);
14991 case MLX5_INDIRECT_ACTION_TYPE_CT:
14992 ret = flow_dv_aso_ct_release(dev, idx, error);
14996 DRV_LOG(DEBUG, "Connection tracking object %u still "
14997 "has references %d.", idx, ret);
15000 return rte_flow_error_set(error, ENOTSUP,
15001 RTE_FLOW_ERROR_TYPE_ACTION,
15003 "action type not supported");
15008 * Updates in place shared RSS action configuration.
15011 * Pointer to the Ethernet device structure.
15013 * The shared RSS action object ID to be updated.
15014 * @param[in] action_conf
15015 * RSS action specification used to modify *shared_rss*.
15016 * @param[out] error
15017 * Perform verbose error reporting if not NULL. Initialized in case of
15021 * 0 on success, otherwise negative errno value.
15022 * @note: currently only support update of RSS queues.
15025 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15026 const struct rte_flow_action_rss *action_conf,
15027 struct rte_flow_error *error)
15029 struct mlx5_priv *priv = dev->data->dev_private;
15030 struct mlx5_shared_action_rss *shared_rss =
15031 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15033 void *queue = NULL;
15034 uint16_t *queue_old = NULL;
15035 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15038 return rte_flow_error_set(error, EINVAL,
15039 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15040 "invalid shared action to update");
15041 if (priv->obj_ops.ind_table_modify == NULL)
15042 return rte_flow_error_set(error, ENOTSUP,
15043 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15044 "cannot modify indirection table");
15045 queue = mlx5_malloc(MLX5_MEM_ZERO,
15046 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15049 return rte_flow_error_set(error, ENOMEM,
15050 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15052 "cannot allocate resource memory");
15053 memcpy(queue, action_conf->queue, queue_size);
15054 MLX5_ASSERT(shared_rss->ind_tbl);
15055 rte_spinlock_lock(&shared_rss->action_rss_sl);
15056 queue_old = shared_rss->ind_tbl->queues;
15057 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15058 queue, action_conf->queue_num, true);
15061 ret = rte_flow_error_set(error, rte_errno,
15062 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15063 "cannot update indirection table");
15065 mlx5_free(queue_old);
15066 shared_rss->origin.queue = queue;
15067 shared_rss->origin.queue_num = action_conf->queue_num;
15069 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15074 * Updates in place conntrack context or direction.
15075 * Context update should be synchronized.
15078 * Pointer to the Ethernet device structure.
15080 * The conntrack object ID to be updated.
15081 * @param[in] update
15082 * Pointer to the structure of information to update.
15083 * @param[out] error
15084 * Perform verbose error reporting if not NULL. Initialized in case of
15088 * 0 on success, otherwise negative errno value.
15091 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15092 const struct rte_flow_modify_conntrack *update,
15093 struct rte_flow_error *error)
15095 struct mlx5_priv *priv = dev->data->dev_private;
15096 struct mlx5_aso_ct_action *ct;
15097 const struct rte_flow_action_conntrack *new_prf;
15099 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15102 if (PORT_ID(priv) != owner)
15103 return rte_flow_error_set(error, EACCES,
15104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15106 "CT object owned by another port");
15107 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15108 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15110 return rte_flow_error_set(error, ENOMEM,
15111 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15113 "CT object is inactive");
15114 new_prf = &update->new_ct;
15115 if (update->direction)
15116 ct->is_original = !!new_prf->is_original_dir;
15117 if (update->state) {
15118 /* Only validate the profile when it needs to be updated. */
15119 ret = mlx5_validate_action_ct(dev, new_prf, error);
15122 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15124 return rte_flow_error_set(error, EIO,
15125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15127 "Failed to send CT context update WQE");
15128 /* Block until ready or a failure. */
15129 ret = mlx5_aso_ct_available(priv->sh, ct);
15131 rte_flow_error_set(error, rte_errno,
15132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15134 "Timeout to get the CT update");
15140 * Updates in place shared action configuration, lock free,
15141 * (mutex should be acquired by caller).
15144 * Pointer to the Ethernet device structure.
15145 * @param[in] handle
15146 * The indirect action object handle to be updated.
15147 * @param[in] update
15148 * Action specification used to modify the action pointed by *handle*.
15149 * *update* could be of same type with the action pointed by the *handle*
15150 * handle argument, or some other structures like a wrapper, depending on
15151 * the indirect action type.
15152 * @param[out] error
15153 * Perform verbose error reporting if not NULL. Initialized in case of
15157 * 0 on success, otherwise negative errno value.
15160 flow_dv_action_update(struct rte_eth_dev *dev,
15161 struct rte_flow_action_handle *handle,
15162 const void *update,
15163 struct rte_flow_error *err)
15165 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15166 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15167 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15168 const void *action_conf;
15171 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15172 action_conf = ((const struct rte_flow_action *)update)->conf;
15173 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15174 case MLX5_INDIRECT_ACTION_TYPE_CT:
15175 return __flow_dv_action_ct_update(dev, idx, update, err);
15177 return rte_flow_error_set(err, ENOTSUP,
15178 RTE_FLOW_ERROR_TYPE_ACTION,
15180 "action type update not supported");
15185 * Destroy the meter sub policy table rules.
15186 * Lock free, (mutex should be acquired by caller).
15189 * Pointer to Ethernet device.
15190 * @param[in] sub_policy
15191 * Pointer to meter sub policy table.
15194 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15195 struct mlx5_flow_meter_sub_policy *sub_policy)
15197 struct mlx5_priv *priv = dev->data->dev_private;
15198 struct mlx5_flow_tbl_data_entry *tbl;
15199 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15200 struct mlx5_flow_meter_info *next_fm;
15201 struct mlx5_sub_policy_color_rule *color_rule;
15205 for (i = 0; i < RTE_COLORS; i++) {
15207 if (i == RTE_COLOR_GREEN && policy &&
15208 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15209 next_fm = mlx5_flow_meter_find(priv,
15210 policy->act_cnt[i].next_mtr_id, NULL);
15211 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15213 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15214 tbl = container_of(color_rule->matcher->tbl,
15215 typeof(*tbl), tbl);
15216 mlx5_list_unregister(tbl->matchers,
15217 &color_rule->matcher->entry);
15218 TAILQ_REMOVE(&sub_policy->color_rules[i],
15219 color_rule, next_port);
15220 mlx5_free(color_rule);
15222 mlx5_flow_meter_detach(priv, next_fm);
15225 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15226 if (sub_policy->rix_hrxq[i]) {
15227 if (policy && !policy->is_hierarchy)
15228 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15229 sub_policy->rix_hrxq[i] = 0;
15231 if (sub_policy->jump_tbl[i]) {
15232 flow_dv_tbl_resource_release(MLX5_SH(dev),
15233 sub_policy->jump_tbl[i]);
15234 sub_policy->jump_tbl[i] = NULL;
15237 if (sub_policy->tbl_rsc) {
15238 flow_dv_tbl_resource_release(MLX5_SH(dev),
15239 sub_policy->tbl_rsc);
15240 sub_policy->tbl_rsc = NULL;
15245 * Destroy policy rules, lock free,
15246 * (mutex should be acquired by caller).
15247 * Dispatcher for action type specific call.
15250 * Pointer to the Ethernet device structure.
15251 * @param[in] mtr_policy
15252 * Meter policy struct.
15255 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15256 struct mlx5_flow_meter_policy *mtr_policy)
15259 struct mlx5_flow_meter_sub_policy *sub_policy;
15260 uint16_t sub_policy_num;
15262 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15263 sub_policy_num = (mtr_policy->sub_policy_num >>
15264 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15265 MLX5_MTR_SUB_POLICY_NUM_MASK;
15266 for (j = 0; j < sub_policy_num; j++) {
15267 sub_policy = mtr_policy->sub_policys[i][j];
15269 __flow_dv_destroy_sub_policy_rules(dev,
15276 * Destroy policy action, lock free,
15277 * (mutex should be acquired by caller).
15278 * Dispatcher for action type specific call.
15281 * Pointer to the Ethernet device structure.
15282 * @param[in] mtr_policy
15283 * Meter policy struct.
15286 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15287 struct mlx5_flow_meter_policy *mtr_policy)
15289 struct rte_flow_action *rss_action;
15290 struct mlx5_flow_handle dev_handle;
15293 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15294 if (mtr_policy->act_cnt[i].rix_mark) {
15295 flow_dv_tag_release(dev,
15296 mtr_policy->act_cnt[i].rix_mark);
15297 mtr_policy->act_cnt[i].rix_mark = 0;
15299 if (mtr_policy->act_cnt[i].modify_hdr) {
15300 dev_handle.dvh.modify_hdr =
15301 mtr_policy->act_cnt[i].modify_hdr;
15302 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15304 switch (mtr_policy->act_cnt[i].fate_action) {
15305 case MLX5_FLOW_FATE_SHARED_RSS:
15306 rss_action = mtr_policy->act_cnt[i].rss;
15307 mlx5_free(rss_action);
15309 case MLX5_FLOW_FATE_PORT_ID:
15310 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15311 flow_dv_port_id_action_resource_release(dev,
15312 mtr_policy->act_cnt[i].rix_port_id_action);
15313 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15316 case MLX5_FLOW_FATE_DROP:
15317 case MLX5_FLOW_FATE_JUMP:
15318 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15319 mtr_policy->act_cnt[i].dr_jump_action[j] =
15323 /*Queue action do nothing*/
15327 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15328 mtr_policy->dr_drop_action[j] = NULL;
15332 * Create policy action per domain, lock free,
15333 * (mutex should be acquired by caller).
15334 * Dispatcher for action type specific call.
15337 * Pointer to the Ethernet device structure.
15338 * @param[in] mtr_policy
15339 * Meter policy struct.
15340 * @param[in] action
15341 * Action specification used to create meter actions.
15342 * @param[out] error
15343 * Perform verbose error reporting if not NULL. Initialized in case of
15347 * 0 on success, otherwise negative errno value.
15350 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15351 struct mlx5_flow_meter_policy *mtr_policy,
15352 const struct rte_flow_action *actions[RTE_COLORS],
15353 enum mlx5_meter_domain domain,
15354 struct rte_mtr_error *error)
15356 struct mlx5_priv *priv = dev->data->dev_private;
15357 struct rte_flow_error flow_err;
15358 const struct rte_flow_action *act;
15359 uint64_t action_flags;
15360 struct mlx5_flow_handle dh;
15361 struct mlx5_flow dev_flow;
15362 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15364 uint8_t egress, transfer;
15365 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15367 struct mlx5_flow_dv_modify_hdr_resource res;
15368 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15369 sizeof(struct mlx5_modification_cmd) *
15370 (MLX5_MAX_MODIFY_NUM + 1)];
15372 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15374 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15375 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15376 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15377 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15378 memset(&port_id_action, 0,
15379 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15380 memset(mhdr_res, 0, sizeof(*mhdr_res));
15381 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15382 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15383 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15384 dev_flow.handle = &dh;
15385 dev_flow.dv.port_id_action = &port_id_action;
15386 dev_flow.external = true;
15387 for (i = 0; i < RTE_COLORS; i++) {
15388 if (i < MLX5_MTR_RTE_COLORS)
15389 act_cnt = &mtr_policy->act_cnt[i];
15390 /* Skip the color policy actions creation. */
15391 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15392 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15395 for (act = actions[i];
15396 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15397 switch (act->type) {
15398 case RTE_FLOW_ACTION_TYPE_MARK:
15400 uint32_t tag_be = mlx5_flow_mark_set
15401 (((const struct rte_flow_action_mark *)
15404 if (i >= MLX5_MTR_RTE_COLORS)
15405 return -rte_mtr_error_set(error,
15407 RTE_MTR_ERROR_TYPE_METER_POLICY,
15409 "cannot create policy "
15410 "mark action for this color");
15411 dev_flow.handle->mark = 1;
15412 if (flow_dv_tag_resource_register(dev, tag_be,
15413 &dev_flow, &flow_err))
15414 return -rte_mtr_error_set(error,
15416 RTE_MTR_ERROR_TYPE_METER_POLICY,
15418 "cannot setup policy mark action");
15419 MLX5_ASSERT(dev_flow.dv.tag_resource);
15420 act_cnt->rix_mark =
15421 dev_flow.handle->dvh.rix_tag;
15422 action_flags |= MLX5_FLOW_ACTION_MARK;
15425 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15426 if (i >= MLX5_MTR_RTE_COLORS)
15427 return -rte_mtr_error_set(error,
15429 RTE_MTR_ERROR_TYPE_METER_POLICY,
15431 "cannot create policy "
15432 "set tag action for this color");
15433 if (flow_dv_convert_action_set_tag
15435 (const struct rte_flow_action_set_tag *)
15436 act->conf, &flow_err))
15437 return -rte_mtr_error_set(error,
15439 RTE_MTR_ERROR_TYPE_METER_POLICY,
15440 NULL, "cannot convert policy "
15442 if (!mhdr_res->actions_num)
15443 return -rte_mtr_error_set(error,
15445 RTE_MTR_ERROR_TYPE_METER_POLICY,
15446 NULL, "cannot find policy "
15448 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15450 case RTE_FLOW_ACTION_TYPE_DROP:
15452 struct mlx5_flow_mtr_mng *mtrmng =
15454 struct mlx5_flow_tbl_data_entry *tbl_data;
15457 * Create the drop table with
15458 * METER DROP level.
15460 if (!mtrmng->drop_tbl[domain]) {
15461 mtrmng->drop_tbl[domain] =
15462 flow_dv_tbl_resource_get(dev,
15463 MLX5_FLOW_TABLE_LEVEL_METER,
15464 egress, transfer, false, NULL, 0,
15465 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15466 if (!mtrmng->drop_tbl[domain])
15467 return -rte_mtr_error_set
15469 RTE_MTR_ERROR_TYPE_METER_POLICY,
15471 "Failed to create meter drop table");
15473 tbl_data = container_of
15474 (mtrmng->drop_tbl[domain],
15475 struct mlx5_flow_tbl_data_entry, tbl);
15476 if (i < MLX5_MTR_RTE_COLORS) {
15477 act_cnt->dr_jump_action[domain] =
15478 tbl_data->jump.action;
15479 act_cnt->fate_action =
15480 MLX5_FLOW_FATE_DROP;
15482 if (i == RTE_COLOR_RED)
15483 mtr_policy->dr_drop_action[domain] =
15484 tbl_data->jump.action;
15485 action_flags |= MLX5_FLOW_ACTION_DROP;
15488 case RTE_FLOW_ACTION_TYPE_QUEUE:
15490 if (i >= MLX5_MTR_RTE_COLORS)
15491 return -rte_mtr_error_set(error,
15493 RTE_MTR_ERROR_TYPE_METER_POLICY,
15494 NULL, "cannot create policy "
15495 "fate queue for this color");
15497 ((const struct rte_flow_action_queue *)
15498 (act->conf))->index;
15499 act_cnt->fate_action =
15500 MLX5_FLOW_FATE_QUEUE;
15501 dev_flow.handle->fate_action =
15502 MLX5_FLOW_FATE_QUEUE;
15503 mtr_policy->is_queue = 1;
15504 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15507 case RTE_FLOW_ACTION_TYPE_RSS:
15511 if (i >= MLX5_MTR_RTE_COLORS)
15512 return -rte_mtr_error_set(error,
15514 RTE_MTR_ERROR_TYPE_METER_POLICY,
15516 "cannot create policy "
15517 "rss action for this color");
15519 * Save RSS conf into policy struct
15520 * for translate stage.
15522 rss_size = (int)rte_flow_conv
15523 (RTE_FLOW_CONV_OP_ACTION,
15524 NULL, 0, act, &flow_err);
15526 return -rte_mtr_error_set(error,
15528 RTE_MTR_ERROR_TYPE_METER_POLICY,
15529 NULL, "Get the wrong "
15530 "rss action struct size");
15531 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15532 rss_size, 0, SOCKET_ID_ANY);
15534 return -rte_mtr_error_set(error,
15536 RTE_MTR_ERROR_TYPE_METER_POLICY,
15538 "Fail to malloc rss action memory");
15539 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15540 act_cnt->rss, rss_size,
15543 return -rte_mtr_error_set(error,
15545 RTE_MTR_ERROR_TYPE_METER_POLICY,
15546 NULL, "Fail to save "
15547 "rss action into policy struct");
15548 act_cnt->fate_action =
15549 MLX5_FLOW_FATE_SHARED_RSS;
15550 action_flags |= MLX5_FLOW_ACTION_RSS;
15553 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15554 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15556 struct mlx5_flow_dv_port_id_action_resource
15558 uint32_t port_id = 0;
15560 if (i >= MLX5_MTR_RTE_COLORS)
15561 return -rte_mtr_error_set(error,
15563 RTE_MTR_ERROR_TYPE_METER_POLICY,
15564 NULL, "cannot create policy "
15565 "port action for this color");
15566 memset(&port_id_resource, 0,
15567 sizeof(port_id_resource));
15568 if (flow_dv_translate_action_port_id(dev, act,
15569 &port_id, &flow_err))
15570 return -rte_mtr_error_set(error,
15572 RTE_MTR_ERROR_TYPE_METER_POLICY,
15573 NULL, "cannot translate "
15574 "policy port action");
15575 port_id_resource.port_id = port_id;
15576 if (flow_dv_port_id_action_resource_register
15577 (dev, &port_id_resource,
15578 &dev_flow, &flow_err))
15579 return -rte_mtr_error_set(error,
15581 RTE_MTR_ERROR_TYPE_METER_POLICY,
15582 NULL, "cannot setup "
15583 "policy port action");
15584 act_cnt->rix_port_id_action =
15585 dev_flow.handle->rix_port_id_action;
15586 act_cnt->fate_action =
15587 MLX5_FLOW_FATE_PORT_ID;
15588 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15591 case RTE_FLOW_ACTION_TYPE_JUMP:
15593 uint32_t jump_group = 0;
15594 uint32_t table = 0;
15595 struct mlx5_flow_tbl_data_entry *tbl_data;
15596 struct flow_grp_info grp_info = {
15597 .external = !!dev_flow.external,
15598 .transfer = !!transfer,
15599 .fdb_def_rule = !!priv->fdb_def_rule,
15601 .skip_scale = dev_flow.skip_scale &
15602 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15604 struct mlx5_flow_meter_sub_policy *sub_policy =
15605 mtr_policy->sub_policys[domain][0];
15607 if (i >= MLX5_MTR_RTE_COLORS)
15608 return -rte_mtr_error_set(error,
15610 RTE_MTR_ERROR_TYPE_METER_POLICY,
15612 "cannot create policy "
15613 "jump action for this color");
15615 ((const struct rte_flow_action_jump *)
15617 if (mlx5_flow_group_to_table(dev, NULL,
15620 &grp_info, &flow_err))
15621 return -rte_mtr_error_set(error,
15623 RTE_MTR_ERROR_TYPE_METER_POLICY,
15624 NULL, "cannot setup "
15625 "policy jump action");
15626 sub_policy->jump_tbl[i] =
15627 flow_dv_tbl_resource_get(dev,
15630 !!dev_flow.external,
15631 NULL, jump_group, 0,
15634 (!sub_policy->jump_tbl[i])
15635 return -rte_mtr_error_set(error,
15637 RTE_MTR_ERROR_TYPE_METER_POLICY,
15638 NULL, "cannot create jump action.");
15639 tbl_data = container_of
15640 (sub_policy->jump_tbl[i],
15641 struct mlx5_flow_tbl_data_entry, tbl);
15642 act_cnt->dr_jump_action[domain] =
15643 tbl_data->jump.action;
15644 act_cnt->fate_action =
15645 MLX5_FLOW_FATE_JUMP;
15646 action_flags |= MLX5_FLOW_ACTION_JUMP;
15650 * No need to check meter hierarchy for Y or R colors
15651 * here since it is done in the validation stage.
15653 case RTE_FLOW_ACTION_TYPE_METER:
15655 const struct rte_flow_action_meter *mtr;
15656 struct mlx5_flow_meter_info *next_fm;
15657 struct mlx5_flow_meter_policy *next_policy;
15658 struct rte_flow_action tag_action;
15659 struct mlx5_rte_flow_action_set_tag set_tag;
15660 uint32_t next_mtr_idx = 0;
15663 next_fm = mlx5_flow_meter_find(priv,
15667 return -rte_mtr_error_set(error, EINVAL,
15668 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15669 "Fail to find next meter.");
15670 if (next_fm->def_policy)
15671 return -rte_mtr_error_set(error, EINVAL,
15672 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15673 "Hierarchy only supports termination meter.");
15674 next_policy = mlx5_flow_meter_policy_find(dev,
15675 next_fm->policy_id, NULL);
15676 MLX5_ASSERT(next_policy);
15677 if (next_fm->drop_cnt) {
15680 mlx5_flow_get_reg_id(dev,
15683 (struct rte_flow_error *)error);
15684 set_tag.offset = (priv->mtr_reg_share ?
15685 MLX5_MTR_COLOR_BITS : 0);
15686 set_tag.length = (priv->mtr_reg_share ?
15687 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15689 set_tag.data = next_mtr_idx;
15691 (enum rte_flow_action_type)
15692 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15693 tag_action.conf = &set_tag;
15694 if (flow_dv_convert_action_set_reg
15695 (mhdr_res, &tag_action,
15696 (struct rte_flow_error *)error))
15699 MLX5_FLOW_ACTION_SET_TAG;
15701 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15702 act_cnt->next_mtr_id = next_fm->meter_id;
15703 act_cnt->next_sub_policy = NULL;
15704 mtr_policy->is_hierarchy = 1;
15705 mtr_policy->dev = next_policy->dev;
15707 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15711 return -rte_mtr_error_set(error, ENOTSUP,
15712 RTE_MTR_ERROR_TYPE_METER_POLICY,
15713 NULL, "action type not supported");
15715 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15716 /* create modify action if needed. */
15717 dev_flow.dv.group = 1;
15718 if (flow_dv_modify_hdr_resource_register
15719 (dev, mhdr_res, &dev_flow, &flow_err))
15720 return -rte_mtr_error_set(error,
15722 RTE_MTR_ERROR_TYPE_METER_POLICY,
15723 NULL, "cannot register policy "
15725 act_cnt->modify_hdr =
15726 dev_flow.handle->dvh.modify_hdr;
15734 * Create policy action per domain, lock free,
15735 * (mutex should be acquired by caller).
15736 * Dispatcher for action type specific call.
15739 * Pointer to the Ethernet device structure.
15740 * @param[in] mtr_policy
15741 * Meter policy struct.
15742 * @param[in] action
15743 * Action specification used to create meter actions.
15744 * @param[out] error
15745 * Perform verbose error reporting if not NULL. Initialized in case of
15749 * 0 on success, otherwise negative errno value.
15752 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15753 struct mlx5_flow_meter_policy *mtr_policy,
15754 const struct rte_flow_action *actions[RTE_COLORS],
15755 struct rte_mtr_error *error)
15758 uint16_t sub_policy_num;
15760 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15761 sub_policy_num = (mtr_policy->sub_policy_num >>
15762 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15763 MLX5_MTR_SUB_POLICY_NUM_MASK;
15764 if (sub_policy_num) {
15765 ret = __flow_dv_create_domain_policy_acts(dev,
15766 mtr_policy, actions,
15767 (enum mlx5_meter_domain)i, error);
15768 /* Cleaning resource is done in the caller level. */
15777 * Query a DV flow rule for its statistics via DevX.
15780 * Pointer to Ethernet device.
15781 * @param[in] cnt_idx
15782 * Index to the flow counter.
15784 * Data retrieved by the query.
15785 * @param[out] error
15786 * Perform verbose error reporting if not NULL.
15789 * 0 on success, a negative errno value otherwise and rte_errno is set.
15792 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15793 struct rte_flow_error *error)
15795 struct mlx5_priv *priv = dev->data->dev_private;
15796 struct rte_flow_query_count *qc = data;
15798 if (!priv->sh->devx)
15799 return rte_flow_error_set(error, ENOTSUP,
15800 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15802 "counters are not supported");
15804 uint64_t pkts, bytes;
15805 struct mlx5_flow_counter *cnt;
15806 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15809 return rte_flow_error_set(error, -err,
15810 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15811 NULL, "cannot read counters");
15812 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15815 qc->hits = pkts - cnt->hits;
15816 qc->bytes = bytes - cnt->bytes;
15819 cnt->bytes = bytes;
15823 return rte_flow_error_set(error, EINVAL,
15824 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15826 "counters are not available");
15831 * Query counter's action pointer for a DV flow rule via DevX.
15834 * Pointer to Ethernet device.
15835 * @param[in] cnt_idx
15836 * Index to the flow counter.
15837 * @param[out] action_ptr
15838 * Action pointer for counter.
15839 * @param[out] error
15840 * Perform verbose error reporting if not NULL.
15843 * 0 on success, a negative errno value otherwise and rte_errno is set.
15846 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15847 void **action_ptr, struct rte_flow_error *error)
15849 struct mlx5_priv *priv = dev->data->dev_private;
15851 if (!priv->sh->devx || !action_ptr)
15852 return rte_flow_error_set(error, ENOTSUP,
15853 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15855 "counters are not supported");
15858 struct mlx5_flow_counter *cnt = NULL;
15859 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15861 *action_ptr = cnt->action;
15865 return rte_flow_error_set(error, EINVAL,
15866 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15868 "counters are not available");
15872 flow_dv_action_query(struct rte_eth_dev *dev,
15873 const struct rte_flow_action_handle *handle, void *data,
15874 struct rte_flow_error *error)
15876 struct mlx5_age_param *age_param;
15877 struct rte_flow_query_age *resp;
15878 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15879 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15880 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15881 struct mlx5_priv *priv = dev->data->dev_private;
15882 struct mlx5_aso_ct_action *ct;
15887 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15888 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15890 resp->aged = __atomic_load_n(&age_param->state,
15891 __ATOMIC_RELAXED) == AGE_TMOUT ?
15893 resp->sec_since_last_hit_valid = !resp->aged;
15894 if (resp->sec_since_last_hit_valid)
15895 resp->sec_since_last_hit = __atomic_load_n
15896 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15898 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15899 return flow_dv_query_count(dev, idx, data, error);
15900 case MLX5_INDIRECT_ACTION_TYPE_CT:
15901 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15902 if (owner != PORT_ID(priv))
15903 return rte_flow_error_set(error, EACCES,
15904 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15906 "CT object owned by another port");
15907 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15908 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15911 return rte_flow_error_set(error, EFAULT,
15912 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15914 "CT object is inactive");
15915 ((struct rte_flow_action_conntrack *)data)->peer_port =
15917 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15919 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15920 return rte_flow_error_set(error, EIO,
15921 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15923 "Failed to query CT context");
15926 return rte_flow_error_set(error, ENOTSUP,
15927 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15928 "action type query not supported");
15933 * Query a flow rule AGE action for aging information.
15936 * Pointer to Ethernet device.
15938 * Pointer to the sub flow.
15940 * data retrieved by the query.
15941 * @param[out] error
15942 * Perform verbose error reporting if not NULL.
15945 * 0 on success, a negative errno value otherwise and rte_errno is set.
15948 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15949 void *data, struct rte_flow_error *error)
15951 struct rte_flow_query_age *resp = data;
15952 struct mlx5_age_param *age_param;
15955 struct mlx5_aso_age_action *act =
15956 flow_aso_age_get_by_idx(dev, flow->age);
15958 age_param = &act->age_params;
15959 } else if (flow->counter) {
15960 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15962 if (!age_param || !age_param->timeout)
15963 return rte_flow_error_set
15965 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15966 NULL, "cannot read age data");
15968 return rte_flow_error_set(error, EINVAL,
15969 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15970 NULL, "age data not available");
15972 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15974 resp->sec_since_last_hit_valid = !resp->aged;
15975 if (resp->sec_since_last_hit_valid)
15976 resp->sec_since_last_hit = __atomic_load_n
15977 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15984 * @see rte_flow_query()
15985 * @see rte_flow_ops
15988 flow_dv_query(struct rte_eth_dev *dev,
15989 struct rte_flow *flow __rte_unused,
15990 const struct rte_flow_action *actions __rte_unused,
15991 void *data __rte_unused,
15992 struct rte_flow_error *error __rte_unused)
15996 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15997 switch (actions->type) {
15998 case RTE_FLOW_ACTION_TYPE_VOID:
16000 case RTE_FLOW_ACTION_TYPE_COUNT:
16001 ret = flow_dv_query_count(dev, flow->counter, data,
16004 case RTE_FLOW_ACTION_TYPE_AGE:
16005 ret = flow_dv_query_age(dev, flow, data, error);
16008 return rte_flow_error_set(error, ENOTSUP,
16009 RTE_FLOW_ERROR_TYPE_ACTION,
16011 "action not supported");
16018 * Destroy the meter table set.
16019 * Lock free, (mutex should be acquired by caller).
16022 * Pointer to Ethernet device.
16024 * Meter information table.
16027 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16028 struct mlx5_flow_meter_info *fm)
16030 struct mlx5_priv *priv = dev->data->dev_private;
16033 if (!fm || !priv->config.dv_flow_en)
16035 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16036 if (fm->drop_rule[i]) {
16037 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16038 fm->drop_rule[i] = NULL;
16044 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16046 struct mlx5_priv *priv = dev->data->dev_private;
16047 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16048 struct mlx5_flow_tbl_data_entry *tbl;
16051 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16052 if (mtrmng->def_rule[i]) {
16053 claim_zero(mlx5_flow_os_destroy_flow
16054 (mtrmng->def_rule[i]));
16055 mtrmng->def_rule[i] = NULL;
16057 if (mtrmng->def_matcher[i]) {
16058 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16059 struct mlx5_flow_tbl_data_entry, tbl);
16060 mlx5_list_unregister(tbl->matchers,
16061 &mtrmng->def_matcher[i]->entry);
16062 mtrmng->def_matcher[i] = NULL;
16064 for (j = 0; j < MLX5_REG_BITS; j++) {
16065 if (mtrmng->drop_matcher[i][j]) {
16067 container_of(mtrmng->drop_matcher[i][j]->tbl,
16068 struct mlx5_flow_tbl_data_entry,
16070 mlx5_list_unregister(tbl->matchers,
16071 &mtrmng->drop_matcher[i][j]->entry);
16072 mtrmng->drop_matcher[i][j] = NULL;
16075 if (mtrmng->drop_tbl[i]) {
16076 flow_dv_tbl_resource_release(MLX5_SH(dev),
16077 mtrmng->drop_tbl[i]);
16078 mtrmng->drop_tbl[i] = NULL;
16083 /* Number of meter flow actions, count and jump or count and drop. */
16084 #define METER_ACTIONS 2
16087 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16088 enum mlx5_meter_domain domain)
16090 struct mlx5_priv *priv = dev->data->dev_private;
16091 struct mlx5_flow_meter_def_policy *def_policy =
16092 priv->sh->mtrmng->def_policy[domain];
16094 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16095 mlx5_free(def_policy);
16096 priv->sh->mtrmng->def_policy[domain] = NULL;
16100 * Destroy the default policy table set.
16103 * Pointer to Ethernet device.
16106 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16108 struct mlx5_priv *priv = dev->data->dev_private;
16111 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16112 if (priv->sh->mtrmng->def_policy[i])
16113 __flow_dv_destroy_domain_def_policy(dev,
16114 (enum mlx5_meter_domain)i);
16115 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16119 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16120 uint32_t color_reg_c_idx,
16121 enum rte_color color, void *matcher_object,
16122 int actions_n, void *actions,
16123 bool match_src_port, const struct rte_flow_item *item,
16124 void **rule, const struct rte_flow_attr *attr)
16127 struct mlx5_flow_dv_match_params value = {
16128 .size = sizeof(value.buf),
16130 struct mlx5_flow_dv_match_params matcher = {
16131 .size = sizeof(matcher.buf),
16133 struct mlx5_priv *priv = dev->data->dev_private;
16136 if (match_src_port && (priv->representor || priv->master)) {
16137 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16138 value.buf, item, attr)) {
16139 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16140 " value with port.", color);
16144 flow_dv_match_meta_reg(matcher.buf, value.buf,
16145 (enum modify_reg)color_reg_c_idx,
16146 rte_col_2_mlx5_col(color), UINT32_MAX);
16147 misc_mask = flow_dv_matcher_enable(value.buf);
16148 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16149 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16150 actions_n, actions, rule);
16152 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16159 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16160 uint32_t color_reg_c_idx,
16162 struct mlx5_flow_meter_sub_policy *sub_policy,
16163 const struct rte_flow_attr *attr,
16164 bool match_src_port,
16165 const struct rte_flow_item *item,
16166 struct mlx5_flow_dv_matcher **policy_matcher,
16167 struct rte_flow_error *error)
16169 struct mlx5_list_entry *entry;
16170 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16171 struct mlx5_flow_dv_matcher matcher = {
16173 .size = sizeof(matcher.mask.buf),
16177 struct mlx5_flow_dv_match_params value = {
16178 .size = sizeof(value.buf),
16180 struct mlx5_flow_cb_ctx ctx = {
16184 struct mlx5_flow_tbl_data_entry *tbl_data;
16185 struct mlx5_priv *priv = dev->data->dev_private;
16186 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16188 if (match_src_port && (priv->representor || priv->master)) {
16189 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16190 value.buf, item, attr)) {
16191 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16192 " with port.", priority);
16196 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16197 if (priority < RTE_COLOR_RED)
16198 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16199 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16200 matcher.priority = priority;
16201 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16202 matcher.mask.size);
16203 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16205 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16209 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16214 * Create the policy rules per domain.
16217 * Pointer to Ethernet device.
16218 * @param[in] sub_policy
16219 * Pointer to sub policy table..
16220 * @param[in] egress
16221 * Direction of the table.
16222 * @param[in] transfer
16223 * E-Switch or NIC flow.
16225 * Pointer to policy action list per color.
16228 * 0 on success, -1 otherwise.
16231 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16232 struct mlx5_flow_meter_sub_policy *sub_policy,
16233 uint8_t egress, uint8_t transfer, bool match_src_port,
16234 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16236 struct mlx5_priv *priv = dev->data->dev_private;
16237 struct rte_flow_error flow_err;
16238 uint32_t color_reg_c_idx;
16239 struct rte_flow_attr attr = {
16240 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16243 .egress = !!egress,
16244 .transfer = !!transfer,
16248 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16249 struct mlx5_sub_policy_color_rule *color_rule;
16251 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16255 /* Create policy table with POLICY level. */
16256 if (!sub_policy->tbl_rsc)
16257 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16258 MLX5_FLOW_TABLE_LEVEL_POLICY,
16259 egress, transfer, false, NULL, 0, 0,
16260 sub_policy->idx, &flow_err);
16261 if (!sub_policy->tbl_rsc) {
16263 "Failed to create meter sub policy table.");
16266 /* Prepare matchers. */
16267 color_reg_c_idx = ret;
16268 for (i = 0; i < RTE_COLORS; i++) {
16269 TAILQ_INIT(&sub_policy->color_rules[i]);
16270 if (!acts[i].actions_n)
16272 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16273 sizeof(struct mlx5_sub_policy_color_rule),
16276 DRV_LOG(ERR, "No memory to create color rule.");
16279 tmp_rules[i] = color_rule;
16280 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16281 color_rule, next_port);
16282 color_rule->src_port = priv->representor_id;
16285 /* Create matchers for colors. */
16286 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16287 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16288 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16289 &attr, svport_match, NULL,
16290 &color_rule->matcher, &flow_err)) {
16291 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16294 /* Create flow, matching color. */
16295 if (__flow_dv_create_policy_flow(dev,
16296 color_reg_c_idx, (enum rte_color)i,
16297 color_rule->matcher->matcher_object,
16298 acts[i].actions_n, acts[i].dv_actions,
16299 svport_match, NULL, &color_rule->rule,
16301 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16307 /* All the policy rules will be cleared. */
16309 color_rule = tmp_rules[i];
16311 if (color_rule->rule)
16312 mlx5_flow_os_destroy_flow(color_rule->rule);
16313 if (color_rule->matcher) {
16314 struct mlx5_flow_tbl_data_entry *tbl =
16315 container_of(color_rule->matcher->tbl,
16316 typeof(*tbl), tbl);
16317 mlx5_list_unregister(tbl->matchers,
16318 &color_rule->matcher->entry);
16320 TAILQ_REMOVE(&sub_policy->color_rules[i],
16321 color_rule, next_port);
16322 mlx5_free(color_rule);
16329 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16330 struct mlx5_flow_meter_policy *mtr_policy,
16331 struct mlx5_flow_meter_sub_policy *sub_policy,
16334 struct mlx5_priv *priv = dev->data->dev_private;
16335 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16336 struct mlx5_flow_dv_tag_resource *tag;
16337 struct mlx5_flow_dv_port_id_action_resource *port_action;
16338 struct mlx5_hrxq *hrxq;
16339 struct mlx5_flow_meter_info *next_fm = NULL;
16340 struct mlx5_flow_meter_policy *next_policy;
16341 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16342 struct mlx5_flow_tbl_data_entry *tbl_data;
16343 struct rte_flow_error error;
16344 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16345 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16346 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16347 bool match_src_port = false;
16350 /* If RSS or Queue, no previous actions / rules is created. */
16351 for (i = 0; i < RTE_COLORS; i++) {
16352 acts[i].actions_n = 0;
16353 if (i == RTE_COLOR_RED) {
16354 /* Only support drop on red. */
16355 acts[i].dv_actions[0] =
16356 mtr_policy->dr_drop_action[domain];
16357 acts[i].actions_n = 1;
16360 if (i == RTE_COLOR_GREEN &&
16361 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16362 struct rte_flow_attr attr = {
16363 .transfer = transfer
16366 next_fm = mlx5_flow_meter_find(priv,
16367 mtr_policy->act_cnt[i].next_mtr_id,
16371 "Failed to get next hierarchy meter.");
16374 if (mlx5_flow_meter_attach(priv, next_fm,
16376 DRV_LOG(ERR, "%s", error.message);
16380 /* Meter action must be the first for TX. */
16382 acts[i].dv_actions[acts[i].actions_n] =
16383 next_fm->meter_action;
16384 acts[i].actions_n++;
16387 if (mtr_policy->act_cnt[i].rix_mark) {
16388 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16389 mtr_policy->act_cnt[i].rix_mark);
16391 DRV_LOG(ERR, "Failed to find "
16392 "mark action for policy.");
16395 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16396 acts[i].actions_n++;
16398 if (mtr_policy->act_cnt[i].modify_hdr) {
16399 acts[i].dv_actions[acts[i].actions_n] =
16400 mtr_policy->act_cnt[i].modify_hdr->action;
16401 acts[i].actions_n++;
16403 if (mtr_policy->act_cnt[i].fate_action) {
16404 switch (mtr_policy->act_cnt[i].fate_action) {
16405 case MLX5_FLOW_FATE_PORT_ID:
16406 port_action = mlx5_ipool_get
16407 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16408 mtr_policy->act_cnt[i].rix_port_id_action);
16409 if (!port_action) {
16410 DRV_LOG(ERR, "Failed to find "
16411 "port action for policy.");
16414 acts[i].dv_actions[acts[i].actions_n] =
16415 port_action->action;
16416 acts[i].actions_n++;
16417 mtr_policy->dev = dev;
16418 match_src_port = true;
16420 case MLX5_FLOW_FATE_DROP:
16421 case MLX5_FLOW_FATE_JUMP:
16422 acts[i].dv_actions[acts[i].actions_n] =
16423 mtr_policy->act_cnt[i].dr_jump_action[domain];
16424 acts[i].actions_n++;
16426 case MLX5_FLOW_FATE_SHARED_RSS:
16427 case MLX5_FLOW_FATE_QUEUE:
16428 hrxq = mlx5_ipool_get
16429 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16430 sub_policy->rix_hrxq[i]);
16432 DRV_LOG(ERR, "Failed to find "
16433 "queue action for policy.");
16436 acts[i].dv_actions[acts[i].actions_n] =
16438 acts[i].actions_n++;
16440 case MLX5_FLOW_FATE_MTR:
16443 "No next hierarchy meter.");
16447 acts[i].dv_actions[acts[i].actions_n] =
16448 next_fm->meter_action;
16449 acts[i].actions_n++;
16451 if (mtr_policy->act_cnt[i].next_sub_policy) {
16453 mtr_policy->act_cnt[i].next_sub_policy;
16456 mlx5_flow_meter_policy_find(dev,
16457 next_fm->policy_id, NULL);
16458 MLX5_ASSERT(next_policy);
16460 next_policy->sub_policys[domain][0];
16463 container_of(next_sub_policy->tbl_rsc,
16464 struct mlx5_flow_tbl_data_entry, tbl);
16465 acts[i].dv_actions[acts[i].actions_n++] =
16466 tbl_data->jump.action;
16467 if (mtr_policy->act_cnt[i].modify_hdr)
16468 match_src_port = !!transfer;
16471 /*Queue action do nothing*/
16476 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16477 egress, transfer, match_src_port, acts)) {
16479 "Failed to create policy rules per domain.");
16485 mlx5_flow_meter_detach(priv, next_fm);
16490 * Create the policy rules.
16493 * Pointer to Ethernet device.
16494 * @param[in,out] mtr_policy
16495 * Pointer to meter policy table.
16498 * 0 on success, -1 otherwise.
16501 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16502 struct mlx5_flow_meter_policy *mtr_policy)
16505 uint16_t sub_policy_num;
16507 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16508 sub_policy_num = (mtr_policy->sub_policy_num >>
16509 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16510 MLX5_MTR_SUB_POLICY_NUM_MASK;
16511 if (!sub_policy_num)
16513 /* Prepare actions list and create policy rules. */
16514 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16515 mtr_policy->sub_policys[i][0], i)) {
16516 DRV_LOG(ERR, "Failed to create policy action "
16517 "list per domain.");
16525 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16527 struct mlx5_priv *priv = dev->data->dev_private;
16528 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16529 struct mlx5_flow_meter_def_policy *def_policy;
16530 struct mlx5_flow_tbl_resource *jump_tbl;
16531 struct mlx5_flow_tbl_data_entry *tbl_data;
16532 uint8_t egress, transfer;
16533 struct rte_flow_error error;
16534 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16537 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16538 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16539 def_policy = mtrmng->def_policy[domain];
16541 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16542 sizeof(struct mlx5_flow_meter_def_policy),
16543 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16545 DRV_LOG(ERR, "Failed to alloc default policy table.");
16546 goto def_policy_error;
16548 mtrmng->def_policy[domain] = def_policy;
16549 /* Create the meter suffix table with SUFFIX level. */
16550 jump_tbl = flow_dv_tbl_resource_get(dev,
16551 MLX5_FLOW_TABLE_LEVEL_METER,
16552 egress, transfer, false, NULL, 0,
16553 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16556 "Failed to create meter suffix table.");
16557 goto def_policy_error;
16559 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16560 tbl_data = container_of(jump_tbl,
16561 struct mlx5_flow_tbl_data_entry, tbl);
16562 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16563 tbl_data->jump.action;
16564 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16565 acts[RTE_COLOR_GREEN].actions_n = 1;
16567 * YELLOW has the same default policy as GREEN does.
16568 * G & Y share the same table and action. The 2nd time of table
16569 * resource getting is just to update the reference count for
16570 * the releasing stage.
16572 jump_tbl = flow_dv_tbl_resource_get(dev,
16573 MLX5_FLOW_TABLE_LEVEL_METER,
16574 egress, transfer, false, NULL, 0,
16575 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16578 "Failed to get meter suffix table.");
16579 goto def_policy_error;
16581 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16582 tbl_data = container_of(jump_tbl,
16583 struct mlx5_flow_tbl_data_entry, tbl);
16584 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16585 tbl_data->jump.action;
16586 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16587 acts[RTE_COLOR_YELLOW].actions_n = 1;
16588 /* Create jump action to the drop table. */
16589 if (!mtrmng->drop_tbl[domain]) {
16590 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16591 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16592 egress, transfer, false, NULL, 0,
16593 0, MLX5_MTR_TABLE_ID_DROP, &error);
16594 if (!mtrmng->drop_tbl[domain]) {
16595 DRV_LOG(ERR, "Failed to create meter "
16596 "drop table for default policy.");
16597 goto def_policy_error;
16600 /* all RED: unique Drop table for jump action. */
16601 tbl_data = container_of(mtrmng->drop_tbl[domain],
16602 struct mlx5_flow_tbl_data_entry, tbl);
16603 def_policy->dr_jump_action[RTE_COLOR_RED] =
16604 tbl_data->jump.action;
16605 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16606 acts[RTE_COLOR_RED].actions_n = 1;
16607 /* Create default policy rules. */
16608 ret = __flow_dv_create_domain_policy_rules(dev,
16609 &def_policy->sub_policy,
16610 egress, transfer, false, acts);
16612 DRV_LOG(ERR, "Failed to create default policy rules.");
16613 goto def_policy_error;
16618 __flow_dv_destroy_domain_def_policy(dev,
16619 (enum mlx5_meter_domain)domain);
16624 * Create the default policy table set.
16627 * Pointer to Ethernet device.
16629 * 0 on success, -1 otherwise.
16632 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16634 struct mlx5_priv *priv = dev->data->dev_private;
16637 /* Non-termination policy table. */
16638 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16639 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16641 if (__flow_dv_create_domain_def_policy(dev, i)) {
16642 DRV_LOG(ERR, "Failed to create default policy");
16643 /* Rollback the created default policies for others. */
16644 flow_dv_destroy_def_policy(dev);
16652 * Create the needed meter tables.
16653 * Lock free, (mutex should be acquired by caller).
16656 * Pointer to Ethernet device.
16658 * Meter information table.
16659 * @param[in] mtr_idx
16661 * @param[in] domain_bitmap
16664 * 0 on success, -1 otherwise.
16667 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16668 struct mlx5_flow_meter_info *fm,
16670 uint8_t domain_bitmap)
16672 struct mlx5_priv *priv = dev->data->dev_private;
16673 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16674 struct rte_flow_error error;
16675 struct mlx5_flow_tbl_data_entry *tbl_data;
16676 uint8_t egress, transfer;
16677 void *actions[METER_ACTIONS];
16678 int domain, ret, i;
16679 struct mlx5_flow_counter *cnt;
16680 struct mlx5_flow_dv_match_params value = {
16681 .size = sizeof(value.buf),
16683 struct mlx5_flow_dv_match_params matcher_para = {
16684 .size = sizeof(matcher_para.buf),
16686 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16688 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16689 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16690 struct mlx5_list_entry *entry;
16691 struct mlx5_flow_dv_matcher matcher = {
16693 .size = sizeof(matcher.mask.buf),
16696 struct mlx5_flow_dv_matcher *drop_matcher;
16697 struct mlx5_flow_cb_ctx ctx = {
16703 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16704 rte_errno = ENOTSUP;
16707 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16708 if (!(domain_bitmap & (1 << domain)) ||
16709 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16711 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16712 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16713 /* Create the drop table with METER DROP level. */
16714 if (!mtrmng->drop_tbl[domain]) {
16715 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16716 MLX5_FLOW_TABLE_LEVEL_METER,
16717 egress, transfer, false, NULL, 0,
16718 0, MLX5_MTR_TABLE_ID_DROP, &error);
16719 if (!mtrmng->drop_tbl[domain]) {
16720 DRV_LOG(ERR, "Failed to create meter drop table.");
16724 /* Create default matcher in drop table. */
16725 matcher.tbl = mtrmng->drop_tbl[domain],
16726 tbl_data = container_of(mtrmng->drop_tbl[domain],
16727 struct mlx5_flow_tbl_data_entry, tbl);
16728 if (!mtrmng->def_matcher[domain]) {
16729 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16730 (enum modify_reg)mtr_id_reg_c,
16732 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16733 matcher.crc = rte_raw_cksum
16734 ((const void *)matcher.mask.buf,
16735 matcher.mask.size);
16736 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16738 DRV_LOG(ERR, "Failed to register meter "
16739 "drop default matcher.");
16742 mtrmng->def_matcher[domain] = container_of(entry,
16743 struct mlx5_flow_dv_matcher, entry);
16745 /* Create default rule in drop table. */
16746 if (!mtrmng->def_rule[domain]) {
16748 actions[i++] = priv->sh->dr_drop_action;
16749 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16750 (enum modify_reg)mtr_id_reg_c, 0, 0);
16751 misc_mask = flow_dv_matcher_enable(value.buf);
16752 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16753 ret = mlx5_flow_os_create_flow
16754 (mtrmng->def_matcher[domain]->matcher_object,
16755 (void *)&value, i, actions,
16756 &mtrmng->def_rule[domain]);
16758 DRV_LOG(ERR, "Failed to create meter "
16759 "default drop rule for drop table.");
16765 MLX5_ASSERT(mtrmng->max_mtr_bits);
16766 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16767 /* Create matchers for Drop. */
16768 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16769 (enum modify_reg)mtr_id_reg_c, 0,
16770 (mtr_id_mask << mtr_id_offset));
16771 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16772 matcher.crc = rte_raw_cksum
16773 ((const void *)matcher.mask.buf,
16774 matcher.mask.size);
16775 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16778 "Failed to register meter drop matcher.");
16781 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16782 container_of(entry, struct mlx5_flow_dv_matcher,
16786 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16787 /* Create drop rule, matching meter_id only. */
16788 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16789 (enum modify_reg)mtr_id_reg_c,
16790 (mtr_idx << mtr_id_offset), UINT32_MAX);
16792 cnt = flow_dv_counter_get_by_idx(dev,
16793 fm->drop_cnt, NULL);
16794 actions[i++] = cnt->action;
16795 actions[i++] = priv->sh->dr_drop_action;
16796 misc_mask = flow_dv_matcher_enable(value.buf);
16797 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16798 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16799 (void *)&value, i, actions,
16800 &fm->drop_rule[domain]);
16802 DRV_LOG(ERR, "Failed to create meter "
16803 "drop rule for drop table.");
16809 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16810 if (fm->drop_rule[i]) {
16811 claim_zero(mlx5_flow_os_destroy_flow
16812 (fm->drop_rule[i]));
16813 fm->drop_rule[i] = NULL;
16819 static struct mlx5_flow_meter_sub_policy *
16820 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16821 struct mlx5_flow_meter_policy *mtr_policy,
16822 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16823 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16826 struct mlx5_priv *priv = dev->data->dev_private;
16827 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16828 uint32_t sub_policy_idx = 0;
16829 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16831 struct mlx5_hrxq *hrxq;
16832 struct mlx5_flow_handle dh;
16833 struct mlx5_meter_policy_action_container *act_cnt;
16834 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16835 uint16_t sub_policy_num;
16837 rte_spinlock_lock(&mtr_policy->sl);
16838 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16841 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16842 if (!hrxq_idx[i]) {
16843 rte_spinlock_unlock(&mtr_policy->sl);
16847 sub_policy_num = (mtr_policy->sub_policy_num >>
16848 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16849 MLX5_MTR_SUB_POLICY_NUM_MASK;
16850 for (j = 0; j < sub_policy_num; j++) {
16851 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16854 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16857 if (i >= MLX5_MTR_RTE_COLORS) {
16859 * Found the sub policy table with
16860 * the same queue per color.
16862 rte_spinlock_unlock(&mtr_policy->sl);
16863 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16864 mlx5_hrxq_release(dev, hrxq_idx[i]);
16866 return mtr_policy->sub_policys[domain][j];
16869 /* Create sub policy. */
16870 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16871 /* Reuse the first pre-allocated sub_policy. */
16872 sub_policy = mtr_policy->sub_policys[domain][0];
16873 sub_policy_idx = sub_policy->idx;
16875 sub_policy = mlx5_ipool_zmalloc
16876 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16879 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16880 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16881 mlx5_hrxq_release(dev, hrxq_idx[i]);
16882 goto rss_sub_policy_error;
16884 sub_policy->idx = sub_policy_idx;
16885 sub_policy->main_policy = mtr_policy;
16887 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16890 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16891 if (mtr_policy->is_hierarchy) {
16892 act_cnt = &mtr_policy->act_cnt[i];
16893 act_cnt->next_sub_policy = next_sub_policy;
16894 mlx5_hrxq_release(dev, hrxq_idx[i]);
16897 * Overwrite the last action from
16898 * RSS action to Queue action.
16900 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16903 DRV_LOG(ERR, "Failed to get policy hrxq");
16904 goto rss_sub_policy_error;
16906 act_cnt = &mtr_policy->act_cnt[i];
16907 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16908 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16909 if (act_cnt->rix_mark)
16911 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16912 dh.rix_hrxq = hrxq_idx[i];
16913 flow_drv_rxq_flags_set(dev, &dh);
16917 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16918 sub_policy, domain)) {
16919 DRV_LOG(ERR, "Failed to create policy "
16920 "rules for ingress domain.");
16921 goto rss_sub_policy_error;
16923 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16924 i = (mtr_policy->sub_policy_num >>
16925 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16926 MLX5_MTR_SUB_POLICY_NUM_MASK;
16927 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16928 DRV_LOG(ERR, "No free sub-policy slot.");
16929 goto rss_sub_policy_error;
16931 mtr_policy->sub_policys[domain][i] = sub_policy;
16933 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16934 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16935 mtr_policy->sub_policy_num |=
16936 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16937 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16939 rte_spinlock_unlock(&mtr_policy->sl);
16942 rss_sub_policy_error:
16944 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16945 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16946 i = (mtr_policy->sub_policy_num >>
16947 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16948 MLX5_MTR_SUB_POLICY_NUM_MASK;
16949 mtr_policy->sub_policys[domain][i] = NULL;
16950 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16954 rte_spinlock_unlock(&mtr_policy->sl);
16959 * Find the policy table for prefix table with RSS.
16962 * Pointer to Ethernet device.
16963 * @param[in] mtr_policy
16964 * Pointer to meter policy table.
16965 * @param[in] rss_desc
16966 * Pointer to rss_desc
16968 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16970 static struct mlx5_flow_meter_sub_policy *
16971 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16972 struct mlx5_flow_meter_policy *mtr_policy,
16973 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16975 struct mlx5_priv *priv = dev->data->dev_private;
16976 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16977 struct mlx5_flow_meter_info *next_fm;
16978 struct mlx5_flow_meter_policy *next_policy;
16979 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16980 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16981 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16982 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16983 bool reuse_sub_policy;
16988 /* Iterate hierarchy to get all policies in this hierarchy. */
16989 policies[i++] = mtr_policy;
16990 if (!mtr_policy->is_hierarchy)
16992 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16993 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16996 next_fm = mlx5_flow_meter_find(priv,
16997 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16999 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17003 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17005 MLX5_ASSERT(next_policy);
17006 mtr_policy = next_policy;
17010 * From last policy to the first one in hierarchy,
17011 * create / get the sub policy for each of them.
17013 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17017 &reuse_sub_policy);
17019 DRV_LOG(ERR, "Failed to get the sub policy.");
17022 if (!reuse_sub_policy)
17023 sub_policies[j++] = sub_policy;
17024 next_sub_policy = sub_policy;
17029 uint16_t sub_policy_num;
17031 sub_policy = sub_policies[--j];
17032 mtr_policy = sub_policy->main_policy;
17033 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17034 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17035 sub_policy_num = (mtr_policy->sub_policy_num >>
17036 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17037 MLX5_MTR_SUB_POLICY_NUM_MASK;
17038 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17041 mtr_policy->sub_policy_num &=
17042 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17043 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17044 mtr_policy->sub_policy_num |=
17045 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17046 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17047 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17055 * Create the sub policy tag rule for all meters in hierarchy.
17058 * Pointer to Ethernet device.
17060 * Meter information table.
17061 * @param[in] src_port
17062 * The src port this extra rule should use.
17064 * The src port match item.
17065 * @param[out] error
17066 * Perform verbose error reporting if not NULL.
17068 * 0 on success, a negative errno value otherwise and rte_errno is set.
17071 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17072 struct mlx5_flow_meter_info *fm,
17074 const struct rte_flow_item *item,
17075 struct rte_flow_error *error)
17077 struct mlx5_priv *priv = dev->data->dev_private;
17078 struct mlx5_flow_meter_policy *mtr_policy;
17079 struct mlx5_flow_meter_sub_policy *sub_policy;
17080 struct mlx5_flow_meter_info *next_fm = NULL;
17081 struct mlx5_flow_meter_policy *next_policy;
17082 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17083 struct mlx5_flow_tbl_data_entry *tbl_data;
17084 struct mlx5_sub_policy_color_rule *color_rule;
17085 struct mlx5_meter_policy_acts acts;
17086 uint32_t color_reg_c_idx;
17087 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17088 struct rte_flow_attr attr = {
17089 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17096 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17099 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17100 MLX5_ASSERT(mtr_policy);
17101 if (!mtr_policy->is_hierarchy)
17103 next_fm = mlx5_flow_meter_find(priv,
17104 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17106 return rte_flow_error_set(error, EINVAL,
17107 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17108 "Failed to find next meter in hierarchy.");
17110 if (!next_fm->drop_cnt)
17112 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17113 sub_policy = mtr_policy->sub_policys[domain][0];
17114 for (i = 0; i < RTE_COLORS; i++) {
17115 bool rule_exist = false;
17116 struct mlx5_meter_policy_action_container *act_cnt;
17118 if (i >= RTE_COLOR_YELLOW)
17120 TAILQ_FOREACH(color_rule,
17121 &sub_policy->color_rules[i], next_port)
17122 if (color_rule->src_port == src_port) {
17128 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17129 sizeof(struct mlx5_sub_policy_color_rule),
17132 return rte_flow_error_set(error, ENOMEM,
17133 RTE_FLOW_ERROR_TYPE_ACTION,
17134 NULL, "No memory to create tag color rule.");
17135 color_rule->src_port = src_port;
17137 next_policy = mlx5_flow_meter_policy_find(dev,
17138 next_fm->policy_id, NULL);
17139 MLX5_ASSERT(next_policy);
17140 next_sub_policy = next_policy->sub_policys[domain][0];
17141 tbl_data = container_of(next_sub_policy->tbl_rsc,
17142 struct mlx5_flow_tbl_data_entry, tbl);
17143 act_cnt = &mtr_policy->act_cnt[i];
17145 acts.dv_actions[0] = next_fm->meter_action;
17146 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17148 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17149 acts.dv_actions[1] = next_fm->meter_action;
17151 acts.dv_actions[2] = tbl_data->jump.action;
17152 acts.actions_n = 3;
17153 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17157 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17158 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17160 &color_rule->matcher, error)) {
17161 rte_flow_error_set(error, errno,
17162 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17163 "Failed to create hierarchy meter matcher.");
17166 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17168 color_rule->matcher->matcher_object,
17169 acts.actions_n, acts.dv_actions,
17171 &color_rule->rule, &attr)) {
17172 rte_flow_error_set(error, errno,
17173 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17174 "Failed to create hierarchy meter rule.");
17177 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17178 color_rule, next_port);
17182 * Recursive call to iterate all meters in hierarchy and
17183 * create needed rules.
17185 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17186 src_port, item, error);
17189 if (color_rule->rule)
17190 mlx5_flow_os_destroy_flow(color_rule->rule);
17191 if (color_rule->matcher) {
17192 struct mlx5_flow_tbl_data_entry *tbl =
17193 container_of(color_rule->matcher->tbl,
17194 typeof(*tbl), tbl);
17195 mlx5_list_unregister(tbl->matchers,
17196 &color_rule->matcher->entry);
17198 mlx5_free(color_rule);
17201 mlx5_flow_meter_detach(priv, next_fm);
17206 * Destroy the sub policy table with RX queue.
17209 * Pointer to Ethernet device.
17210 * @param[in] mtr_policy
17211 * Pointer to meter policy table.
17214 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17215 struct mlx5_flow_meter_policy *mtr_policy)
17217 struct mlx5_priv *priv = dev->data->dev_private;
17218 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17219 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17221 uint16_t sub_policy_num, new_policy_num;
17223 rte_spinlock_lock(&mtr_policy->sl);
17224 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17225 switch (mtr_policy->act_cnt[i].fate_action) {
17226 case MLX5_FLOW_FATE_SHARED_RSS:
17227 sub_policy_num = (mtr_policy->sub_policy_num >>
17228 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17229 MLX5_MTR_SUB_POLICY_NUM_MASK;
17230 new_policy_num = sub_policy_num;
17231 for (j = 0; j < sub_policy_num; j++) {
17233 mtr_policy->sub_policys[domain][j];
17235 __flow_dv_destroy_sub_policy_rules(dev,
17238 mtr_policy->sub_policys[domain][0]) {
17239 mtr_policy->sub_policys[domain][j] =
17242 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17248 if (new_policy_num != sub_policy_num) {
17249 mtr_policy->sub_policy_num &=
17250 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17251 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17252 mtr_policy->sub_policy_num |=
17254 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17255 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17258 case MLX5_FLOW_FATE_QUEUE:
17259 sub_policy = mtr_policy->sub_policys[domain][0];
17260 __flow_dv_destroy_sub_policy_rules(dev,
17264 /*Other actions without queue and do nothing*/
17268 rte_spinlock_unlock(&mtr_policy->sl);
17271 * Check whether the DR drop action is supported on the root table or not.
17273 * Create a simple flow with DR drop action on root table to validate
17274 * if DR drop action on root table is supported or not.
17277 * Pointer to rte_eth_dev structure.
17280 * 0 on success, a negative errno value otherwise and rte_errno is set.
17283 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17285 struct mlx5_priv *priv = dev->data->dev_private;
17286 struct mlx5_dev_ctx_shared *sh = priv->sh;
17287 struct mlx5_flow_dv_match_params mask = {
17288 .size = sizeof(mask.buf),
17290 struct mlx5_flow_dv_match_params value = {
17291 .size = sizeof(value.buf),
17293 struct mlx5dv_flow_matcher_attr dv_attr = {
17294 .type = IBV_FLOW_ATTR_NORMAL,
17296 .match_criteria_enable = 0,
17297 .match_mask = (void *)&mask,
17299 struct mlx5_flow_tbl_resource *tbl = NULL;
17300 void *matcher = NULL;
17304 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17308 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17309 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17310 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17311 tbl->obj, &matcher);
17314 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17315 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17316 &sh->dr_drop_action, &flow);
17319 * If DR drop action is not supported on root table, flow create will
17320 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17324 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17325 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17327 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17330 claim_zero(mlx5_flow_os_destroy_flow(flow));
17333 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17335 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17340 * Validate the batch counter support in root table.
17342 * Create a simple flow with invalid counter and drop action on root table to
17343 * validate if batch counter with offset on root table is supported or not.
17346 * Pointer to rte_eth_dev structure.
17349 * 0 on success, a negative errno value otherwise and rte_errno is set.
17352 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17354 struct mlx5_priv *priv = dev->data->dev_private;
17355 struct mlx5_dev_ctx_shared *sh = priv->sh;
17356 struct mlx5_flow_dv_match_params mask = {
17357 .size = sizeof(mask.buf),
17359 struct mlx5_flow_dv_match_params value = {
17360 .size = sizeof(value.buf),
17362 struct mlx5dv_flow_matcher_attr dv_attr = {
17363 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17365 .match_criteria_enable = 0,
17366 .match_mask = (void *)&mask,
17368 void *actions[2] = { 0 };
17369 struct mlx5_flow_tbl_resource *tbl = NULL;
17370 struct mlx5_devx_obj *dcs = NULL;
17371 void *matcher = NULL;
17375 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17379 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17382 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17386 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17387 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17388 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17389 tbl->obj, &matcher);
17392 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17393 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17397 * If batch counter with offset is not supported, the driver will not
17398 * validate the invalid offset value, flow create should success.
17399 * In this case, it means batch counter is not supported in root table.
17401 * Otherwise, if flow create is failed, counter offset is supported.
17404 DRV_LOG(INFO, "Batch counter is not supported in root "
17405 "table. Switch to fallback mode.");
17406 rte_errno = ENOTSUP;
17408 claim_zero(mlx5_flow_os_destroy_flow(flow));
17410 /* Check matcher to make sure validate fail at flow create. */
17411 if (!matcher || (matcher && errno != EINVAL))
17412 DRV_LOG(ERR, "Unexpected error in counter offset "
17413 "support detection");
17417 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17419 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17421 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17423 claim_zero(mlx5_devx_cmd_destroy(dcs));
17428 * Query a devx counter.
17431 * Pointer to the Ethernet device structure.
17433 * Index to the flow counter.
17435 * Set to clear the counter statistics.
17437 * The statistics value of packets.
17438 * @param[out] bytes
17439 * The statistics value of bytes.
17442 * 0 on success, otherwise return -1.
17445 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17446 uint64_t *pkts, uint64_t *bytes)
17448 struct mlx5_priv *priv = dev->data->dev_private;
17449 struct mlx5_flow_counter *cnt;
17450 uint64_t inn_pkts, inn_bytes;
17453 if (!priv->sh->devx)
17456 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17459 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17460 *pkts = inn_pkts - cnt->hits;
17461 *bytes = inn_bytes - cnt->bytes;
17463 cnt->hits = inn_pkts;
17464 cnt->bytes = inn_bytes;
17470 * Get aged-out flows.
17473 * Pointer to the Ethernet device structure.
17474 * @param[in] context
17475 * The address of an array of pointers to the aged-out flows contexts.
17476 * @param[in] nb_contexts
17477 * The length of context array pointers.
17478 * @param[out] error
17479 * Perform verbose error reporting if not NULL. Initialized in case of
17483 * how many contexts get in success, otherwise negative errno value.
17484 * if nb_contexts is 0, return the amount of all aged contexts.
17485 * if nb_contexts is not 0 , return the amount of aged flows reported
17486 * in the context array.
17487 * @note: only stub for now
17490 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17492 uint32_t nb_contexts,
17493 struct rte_flow_error *error)
17495 struct mlx5_priv *priv = dev->data->dev_private;
17496 struct mlx5_age_info *age_info;
17497 struct mlx5_age_param *age_param;
17498 struct mlx5_flow_counter *counter;
17499 struct mlx5_aso_age_action *act;
17502 if (nb_contexts && !context)
17503 return rte_flow_error_set(error, EINVAL,
17504 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17505 NULL, "empty context");
17506 age_info = GET_PORT_AGE_INFO(priv);
17507 rte_spinlock_lock(&age_info->aged_sl);
17508 LIST_FOREACH(act, &age_info->aged_aso, next) {
17511 context[nb_flows - 1] =
17512 act->age_params.context;
17513 if (!(--nb_contexts))
17517 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17520 age_param = MLX5_CNT_TO_AGE(counter);
17521 context[nb_flows - 1] = age_param->context;
17522 if (!(--nb_contexts))
17526 rte_spinlock_unlock(&age_info->aged_sl);
17527 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17532 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17535 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17537 return flow_dv_counter_alloc(dev, 0);
17541 * Validate indirect action.
17542 * Dispatcher for action type specific validation.
17545 * Pointer to the Ethernet device structure.
17547 * Indirect action configuration.
17548 * @param[in] action
17549 * The indirect action object to validate.
17550 * @param[out] error
17551 * Perform verbose error reporting if not NULL. Initialized in case of
17555 * 0 on success, otherwise negative errno value.
17558 flow_dv_action_validate(struct rte_eth_dev *dev,
17559 const struct rte_flow_indir_action_conf *conf,
17560 const struct rte_flow_action *action,
17561 struct rte_flow_error *err)
17563 struct mlx5_priv *priv = dev->data->dev_private;
17565 RTE_SET_USED(conf);
17566 switch (action->type) {
17567 case RTE_FLOW_ACTION_TYPE_RSS:
17569 * priv->obj_ops is set according to driver capabilities.
17570 * When DevX capabilities are
17571 * sufficient, it is set to devx_obj_ops.
17572 * Otherwise, it is set to ibv_obj_ops.
17573 * ibv_obj_ops doesn't support ind_table_modify operation.
17574 * In this case the indirect RSS action can't be used.
17576 if (priv->obj_ops.ind_table_modify == NULL)
17577 return rte_flow_error_set
17579 RTE_FLOW_ERROR_TYPE_ACTION,
17581 "Indirect RSS action not supported");
17582 return mlx5_validate_action_rss(dev, action, err);
17583 case RTE_FLOW_ACTION_TYPE_AGE:
17584 if (!priv->sh->aso_age_mng)
17585 return rte_flow_error_set(err, ENOTSUP,
17586 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17588 "Indirect age action not supported");
17589 return flow_dv_validate_action_age(0, action, dev, err);
17590 case RTE_FLOW_ACTION_TYPE_COUNT:
17591 return flow_dv_validate_action_count(dev, true, 0, err);
17592 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17593 if (!priv->sh->ct_aso_en)
17594 return rte_flow_error_set(err, ENOTSUP,
17595 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17596 "ASO CT is not supported");
17597 return mlx5_validate_action_ct(dev, action->conf, err);
17599 return rte_flow_error_set(err, ENOTSUP,
17600 RTE_FLOW_ERROR_TYPE_ACTION,
17602 "action type not supported");
17607 * Check if the RSS configurations for colors of a meter policy match
17608 * each other, except the queues.
17611 * Pointer to the first RSS flow action.
17613 * Pointer to the second RSS flow action.
17616 * 0 on match, 1 on conflict.
17619 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17620 const struct rte_flow_action_rss *r2)
17622 if (r1 == NULL || r2 == NULL)
17624 if (!(r1->level <= 1 && r2->level <= 1) &&
17625 !(r1->level > 1 && r2->level > 1))
17627 if (r1->types != r2->types &&
17628 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17629 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17631 if (r1->key || r2->key) {
17632 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17633 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17635 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17642 * Validate the meter hierarchy chain for meter policy.
17645 * Pointer to the Ethernet device structure.
17646 * @param[in] meter_id
17648 * @param[in] action_flags
17649 * Holds the actions detected until now.
17650 * @param[out] is_rss
17652 * @param[out] hierarchy_domain
17653 * The domain bitmap for hierarchy policy.
17654 * @param[out] error
17655 * Perform verbose error reporting if not NULL. Initialized in case of
17659 * 0 on success, otherwise negative errno value with error set.
17662 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17664 uint64_t action_flags,
17666 uint8_t *hierarchy_domain,
17667 struct rte_mtr_error *error)
17669 struct mlx5_priv *priv = dev->data->dev_private;
17670 struct mlx5_flow_meter_info *fm;
17671 struct mlx5_flow_meter_policy *policy;
17674 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17675 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17676 return -rte_mtr_error_set(error, EINVAL,
17677 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17679 "Multiple fate actions not supported.");
17680 *hierarchy_domain = 0;
17682 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17684 return -rte_mtr_error_set(error, EINVAL,
17685 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17686 "Meter not found in meter hierarchy.");
17687 if (fm->def_policy)
17688 return -rte_mtr_error_set(error, EINVAL,
17689 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17690 "Non termination meter not supported in hierarchy.");
17691 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17692 MLX5_ASSERT(policy);
17694 * Only inherit the supported domains of the first meter in
17696 * One meter supports at least one domain.
17698 if (!*hierarchy_domain) {
17699 if (policy->transfer)
17700 *hierarchy_domain |=
17701 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17702 if (policy->ingress)
17703 *hierarchy_domain |=
17704 MLX5_MTR_DOMAIN_INGRESS_BIT;
17705 if (policy->egress)
17706 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17708 if (!policy->is_hierarchy) {
17709 *is_rss = policy->is_rss;
17712 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17713 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17714 return -rte_mtr_error_set(error, EINVAL,
17715 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17716 "Exceed max hierarchy meter number.");
17722 * Validate meter policy actions.
17723 * Dispatcher for action type specific validation.
17726 * Pointer to the Ethernet device structure.
17727 * @param[in] action
17728 * The meter policy action object to validate.
17730 * Attributes of flow to determine steering domain.
17731 * @param[out] error
17732 * Perform verbose error reporting if not NULL. Initialized in case of
17736 * 0 on success, otherwise negative errno value.
17739 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17740 const struct rte_flow_action *actions[RTE_COLORS],
17741 struct rte_flow_attr *attr,
17743 uint8_t *domain_bitmap,
17744 uint8_t *policy_mode,
17745 struct rte_mtr_error *error)
17747 struct mlx5_priv *priv = dev->data->dev_private;
17748 struct mlx5_dev_config *dev_conf = &priv->config;
17749 const struct rte_flow_action *act;
17750 uint64_t action_flags[RTE_COLORS] = {0};
17753 struct rte_flow_error flow_err;
17754 uint8_t domain_color[RTE_COLORS] = {0};
17755 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17756 uint8_t hierarchy_domain = 0;
17757 const struct rte_flow_action_meter *mtr;
17758 bool def_green = false;
17759 bool def_yellow = false;
17760 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17762 if (!priv->config.dv_esw_en)
17763 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17764 *domain_bitmap = def_domain;
17765 /* Red color could only support DROP action. */
17766 if (!actions[RTE_COLOR_RED] ||
17767 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17768 return -rte_mtr_error_set(error, ENOTSUP,
17769 RTE_MTR_ERROR_TYPE_METER_POLICY,
17770 NULL, "Red color only supports drop action.");
17772 * Check default policy actions:
17773 * Green / Yellow: no action, Red: drop action
17774 * Either G or Y will trigger default policy actions to be created.
17776 if (!actions[RTE_COLOR_GREEN] ||
17777 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17779 if (!actions[RTE_COLOR_YELLOW] ||
17780 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17782 if (def_green && def_yellow) {
17783 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17785 } else if (!def_green && def_yellow) {
17786 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17787 } else if (def_green && !def_yellow) {
17788 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17790 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17792 /* Set to empty string in case of NULL pointer access by user. */
17793 flow_err.message = "";
17794 for (i = 0; i < RTE_COLORS; i++) {
17796 for (action_flags[i] = 0, actions_n = 0;
17797 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17799 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17800 return -rte_mtr_error_set(error, ENOTSUP,
17801 RTE_MTR_ERROR_TYPE_METER_POLICY,
17802 NULL, "too many actions");
17803 switch (act->type) {
17804 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17805 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17806 if (!priv->config.dv_esw_en)
17807 return -rte_mtr_error_set(error,
17809 RTE_MTR_ERROR_TYPE_METER_POLICY,
17810 NULL, "PORT action validate check"
17811 " fail for ESW disable");
17812 ret = flow_dv_validate_action_port_id(dev,
17814 act, attr, &flow_err);
17816 return -rte_mtr_error_set(error,
17818 RTE_MTR_ERROR_TYPE_METER_POLICY,
17819 NULL, flow_err.message ?
17821 "PORT action validate check fail");
17823 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17825 case RTE_FLOW_ACTION_TYPE_MARK:
17826 ret = flow_dv_validate_action_mark(dev, act,
17830 return -rte_mtr_error_set(error,
17832 RTE_MTR_ERROR_TYPE_METER_POLICY,
17833 NULL, flow_err.message ?
17835 "Mark action validate check fail");
17836 if (dev_conf->dv_xmeta_en !=
17837 MLX5_XMETA_MODE_LEGACY)
17838 return -rte_mtr_error_set(error,
17840 RTE_MTR_ERROR_TYPE_METER_POLICY,
17841 NULL, "Extend MARK action is "
17842 "not supported. Please try use "
17843 "default policy for meter.");
17844 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17847 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17848 ret = flow_dv_validate_action_set_tag(dev,
17849 act, action_flags[i],
17852 return -rte_mtr_error_set(error,
17854 RTE_MTR_ERROR_TYPE_METER_POLICY,
17855 NULL, flow_err.message ?
17857 "Set tag action validate check fail");
17858 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17861 case RTE_FLOW_ACTION_TYPE_DROP:
17862 ret = mlx5_flow_validate_action_drop
17863 (action_flags[i], attr, &flow_err);
17865 return -rte_mtr_error_set(error,
17867 RTE_MTR_ERROR_TYPE_METER_POLICY,
17868 NULL, flow_err.message ?
17870 "Drop action validate check fail");
17871 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17874 case RTE_FLOW_ACTION_TYPE_QUEUE:
17876 * Check whether extensive
17877 * metadata feature is engaged.
17879 if (dev_conf->dv_flow_en &&
17880 (dev_conf->dv_xmeta_en !=
17881 MLX5_XMETA_MODE_LEGACY) &&
17882 mlx5_flow_ext_mreg_supported(dev))
17883 return -rte_mtr_error_set(error,
17885 RTE_MTR_ERROR_TYPE_METER_POLICY,
17886 NULL, "Queue action with meta "
17887 "is not supported. Please try use "
17888 "default policy for meter.");
17889 ret = mlx5_flow_validate_action_queue(act,
17890 action_flags[i], dev,
17893 return -rte_mtr_error_set(error,
17895 RTE_MTR_ERROR_TYPE_METER_POLICY,
17896 NULL, flow_err.message ?
17898 "Queue action validate check fail");
17899 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17902 case RTE_FLOW_ACTION_TYPE_RSS:
17903 if (dev_conf->dv_flow_en &&
17904 (dev_conf->dv_xmeta_en !=
17905 MLX5_XMETA_MODE_LEGACY) &&
17906 mlx5_flow_ext_mreg_supported(dev))
17907 return -rte_mtr_error_set(error,
17909 RTE_MTR_ERROR_TYPE_METER_POLICY,
17910 NULL, "RSS action with meta "
17911 "is not supported. Please try use "
17912 "default policy for meter.");
17913 ret = mlx5_validate_action_rss(dev, act,
17916 return -rte_mtr_error_set(error,
17918 RTE_MTR_ERROR_TYPE_METER_POLICY,
17919 NULL, flow_err.message ?
17921 "RSS action validate check fail");
17922 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17924 /* Either G or Y will set the RSS. */
17925 rss_color[i] = act->conf;
17927 case RTE_FLOW_ACTION_TYPE_JUMP:
17928 ret = flow_dv_validate_action_jump(dev,
17929 NULL, act, action_flags[i],
17930 attr, true, &flow_err);
17932 return -rte_mtr_error_set(error,
17934 RTE_MTR_ERROR_TYPE_METER_POLICY,
17935 NULL, flow_err.message ?
17937 "Jump action validate check fail");
17939 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17942 * Only the last meter in the hierarchy will support
17943 * the YELLOW color steering. Then in the meter policy
17944 * actions list, there should be no other meter inside.
17946 case RTE_FLOW_ACTION_TYPE_METER:
17947 if (i != RTE_COLOR_GREEN)
17948 return -rte_mtr_error_set(error,
17950 RTE_MTR_ERROR_TYPE_METER_POLICY,
17952 "Meter hierarchy only supports GREEN color.");
17953 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17954 return -rte_mtr_error_set(error,
17956 RTE_MTR_ERROR_TYPE_METER_POLICY,
17958 "No yellow policy should be provided in meter hierarchy.");
17960 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17970 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17973 return -rte_mtr_error_set(error, ENOTSUP,
17974 RTE_MTR_ERROR_TYPE_METER_POLICY,
17976 "Doesn't support optional action");
17979 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
17980 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17981 } else if ((action_flags[i] &
17982 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17983 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
17985 * Only support MLX5_XMETA_MODE_LEGACY
17986 * so MARK action is only in ingress domain.
17988 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17990 domain_color[i] = def_domain;
17991 if (action_flags[i] &&
17992 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17994 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17996 if (action_flags[i] &
17997 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
17998 domain_color[i] &= hierarchy_domain;
18000 * Non-termination actions only support NIC Tx domain.
18001 * The adjustion should be skipped when there is no
18002 * action or only END is provided. The default domains
18003 * bit-mask is set to find the MIN intersection.
18004 * The action flags checking should also be skipped.
18006 if ((def_green && i == RTE_COLOR_GREEN) ||
18007 (def_yellow && i == RTE_COLOR_YELLOW))
18010 * Validate the drop action mutual exclusion
18011 * with other actions. Drop action is mutually-exclusive
18012 * with any other action, except for Count action.
18014 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18015 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18016 return -rte_mtr_error_set(error, ENOTSUP,
18017 RTE_MTR_ERROR_TYPE_METER_POLICY,
18018 NULL, "Drop action is mutually-exclusive "
18019 "with any other action");
18021 /* Eswitch has few restrictions on using items and actions */
18022 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18023 if (!mlx5_flow_ext_mreg_supported(dev) &&
18024 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18025 return -rte_mtr_error_set(error, ENOTSUP,
18026 RTE_MTR_ERROR_TYPE_METER_POLICY,
18027 NULL, "unsupported action MARK");
18028 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18029 return -rte_mtr_error_set(error, ENOTSUP,
18030 RTE_MTR_ERROR_TYPE_METER_POLICY,
18031 NULL, "unsupported action QUEUE");
18032 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18033 return -rte_mtr_error_set(error, ENOTSUP,
18034 RTE_MTR_ERROR_TYPE_METER_POLICY,
18035 NULL, "unsupported action RSS");
18036 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18037 return -rte_mtr_error_set(error, ENOTSUP,
18038 RTE_MTR_ERROR_TYPE_METER_POLICY,
18039 NULL, "no fate action is found");
18041 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18042 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18043 if ((domain_color[i] &
18044 MLX5_MTR_DOMAIN_EGRESS_BIT))
18046 MLX5_MTR_DOMAIN_EGRESS_BIT;
18048 return -rte_mtr_error_set(error,
18050 RTE_MTR_ERROR_TYPE_METER_POLICY,
18052 "no fate action is found");
18056 /* If both colors have RSS, the attributes should be the same. */
18057 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18058 rss_color[RTE_COLOR_YELLOW]))
18059 return -rte_mtr_error_set(error, EINVAL,
18060 RTE_MTR_ERROR_TYPE_METER_POLICY,
18061 NULL, "policy RSS attr conflict");
18062 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18064 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18065 if (!def_green && !def_yellow &&
18066 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18067 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18068 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18069 return -rte_mtr_error_set(error, EINVAL,
18070 RTE_MTR_ERROR_TYPE_METER_POLICY,
18071 NULL, "policy domains conflict");
18073 * At least one color policy is listed in the actions, the domains
18074 * to be supported should be the intersection.
18076 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18077 domain_color[RTE_COLOR_YELLOW];
18082 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18084 struct mlx5_priv *priv = dev->data->dev_private;
18087 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18088 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18093 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18094 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18098 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18099 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18107 * Discover the number of available flow priorities
18108 * by trying to create a flow with the highest priority value
18109 * for each possible number.
18114 * List of possible number of available priorities.
18115 * @param[in] vprio_n
18116 * Size of @p vprio array.
18118 * On success, number of available flow priorities.
18119 * On failure, a negative errno-style code and rte_errno is set.
18122 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18123 const uint16_t *vprio, int vprio_n)
18125 struct mlx5_priv *priv = dev->data->dev_private;
18126 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18127 struct rte_flow_item_eth eth;
18128 struct rte_flow_item item = {
18129 .type = RTE_FLOW_ITEM_TYPE_ETH,
18133 struct mlx5_flow_dv_matcher matcher = {
18135 .size = sizeof(matcher.mask.buf),
18138 union mlx5_flow_tbl_key tbl_key;
18139 struct mlx5_flow flow;
18141 struct rte_flow_error error;
18143 int i, err, ret = -ENOTSUP;
18146 * Prepare a flow with a catch-all pattern and a drop action.
18147 * Use drop queue, because shared drop action may be unavailable.
18149 action = priv->drop_queue.hrxq->action;
18150 if (action == NULL) {
18151 DRV_LOG(ERR, "Priority discovery requires a drop action");
18152 rte_errno = ENOTSUP;
18155 memset(&flow, 0, sizeof(flow));
18156 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18157 if (flow.handle == NULL) {
18158 DRV_LOG(ERR, "Cannot create flow handle");
18159 rte_errno = ENOMEM;
18162 flow.ingress = true;
18163 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18164 flow.dv.actions[0] = action;
18165 flow.dv.actions_n = 1;
18166 memset(ð, 0, sizeof(eth));
18167 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18168 &item, /* inner */ false, /* group */ 0);
18169 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18170 for (i = 0; i < vprio_n; i++) {
18171 /* Configure the next proposed maximum priority. */
18172 matcher.priority = vprio[i] - 1;
18173 memset(&tbl_key, 0, sizeof(tbl_key));
18174 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18179 /* This action is pure SW and must always succeed. */
18180 DRV_LOG(ERR, "Cannot register matcher");
18184 /* Try to apply the flow to HW. */
18185 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18186 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18187 err = mlx5_flow_os_create_flow
18188 (flow.handle->dvh.matcher->matcher_object,
18189 (void *)&flow.dv.value, flow.dv.actions_n,
18190 flow.dv.actions, &flow.handle->drv_flow);
18192 claim_zero(mlx5_flow_os_destroy_flow
18193 (flow.handle->drv_flow));
18194 flow.handle->drv_flow = NULL;
18196 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18201 mlx5_ipool_free(pool, flow.handle_idx);
18202 /* Set rte_errno if no expected priority value matched. */
18208 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18209 .validate = flow_dv_validate,
18210 .prepare = flow_dv_prepare,
18211 .translate = flow_dv_translate,
18212 .apply = flow_dv_apply,
18213 .remove = flow_dv_remove,
18214 .destroy = flow_dv_destroy,
18215 .query = flow_dv_query,
18216 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18217 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18218 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18219 .create_meter = flow_dv_mtr_alloc,
18220 .free_meter = flow_dv_aso_mtr_release_to_pool,
18221 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18222 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18223 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18224 .create_policy_rules = flow_dv_create_policy_rules,
18225 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18226 .create_def_policy = flow_dv_create_def_policy,
18227 .destroy_def_policy = flow_dv_destroy_def_policy,
18228 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18229 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18230 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18231 .counter_alloc = flow_dv_counter_allocate,
18232 .counter_free = flow_dv_counter_free,
18233 .counter_query = flow_dv_counter_query,
18234 .get_aged_flows = flow_dv_get_aged_flows,
18235 .action_validate = flow_dv_action_validate,
18236 .action_create = flow_dv_action_create,
18237 .action_destroy = flow_dv_action_destroy,
18238 .action_update = flow_dv_action_update,
18239 .action_query = flow_dv_action_query,
18240 .sync_domain = flow_dv_sync_domain,
18241 .discover_priorities = flow_dv_discover_priorities,
18242 .item_create = flow_dv_item_create,
18243 .item_release = flow_dv_item_release,
18246 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */