1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 * Initialize flow attributes structure according to flow items' types.
90 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
91 * mode. For tunnel mode, the items to be modified are the outermost ones.
94 * Pointer to item specification.
96 * Pointer to flow attributes structure.
98 * Pointer to the sub flow.
99 * @param[in] tunnel_decap
100 * Whether action is after tunnel decapsulation.
103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
104 struct mlx5_flow *dev_flow, bool tunnel_decap)
106 uint64_t layers = dev_flow->handle->layers;
109 * If layers is already initialized, it means this dev_flow is the
110 * suffix flow, the layers flags is set by the prefix flow. Need to
111 * use the layer flags from prefix flow as the suffix flow may not
112 * have the user defined items as the flow is split.
115 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
117 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
119 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
126 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
127 uint8_t next_protocol = 0xff;
128 switch (item->type) {
129 case RTE_FLOW_ITEM_TYPE_GRE:
130 case RTE_FLOW_ITEM_TYPE_NVGRE:
131 case RTE_FLOW_ITEM_TYPE_VXLAN:
132 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
133 case RTE_FLOW_ITEM_TYPE_GENEVE:
134 case RTE_FLOW_ITEM_TYPE_MPLS:
138 case RTE_FLOW_ITEM_TYPE_IPV4:
141 if (item->mask != NULL &&
142 ((const struct rte_flow_item_ipv4 *)
143 item->mask)->hdr.next_proto_id)
145 ((const struct rte_flow_item_ipv4 *)
146 (item->spec))->hdr.next_proto_id &
147 ((const struct rte_flow_item_ipv4 *)
148 (item->mask))->hdr.next_proto_id;
149 if ((next_protocol == IPPROTO_IPIP ||
150 next_protocol == IPPROTO_IPV6) && tunnel_decap)
153 case RTE_FLOW_ITEM_TYPE_IPV6:
156 if (item->mask != NULL &&
157 ((const struct rte_flow_item_ipv6 *)
158 item->mask)->hdr.proto)
160 ((const struct rte_flow_item_ipv6 *)
161 (item->spec))->hdr.proto &
162 ((const struct rte_flow_item_ipv6 *)
163 (item->mask))->hdr.proto;
164 if ((next_protocol == IPPROTO_IPIP ||
165 next_protocol == IPPROTO_IPV6) && tunnel_decap)
168 case RTE_FLOW_ITEM_TYPE_UDP:
172 case RTE_FLOW_ITEM_TYPE_TCP:
184 * Convert rte_mtr_color to mlx5 color.
193 rte_col_2_mlx5_col(enum rte_color rcol)
196 case RTE_COLOR_GREEN:
197 return MLX5_FLOW_COLOR_GREEN;
198 case RTE_COLOR_YELLOW:
199 return MLX5_FLOW_COLOR_YELLOW;
201 return MLX5_FLOW_COLOR_RED;
205 return MLX5_FLOW_COLOR_UNDEFINED;
208 struct field_modify_info {
209 uint32_t size; /* Size of field in protocol header, in bytes. */
210 uint32_t offset; /* Offset of field in protocol header, in bytes. */
211 enum mlx5_modification_field id;
214 struct field_modify_info modify_eth[] = {
215 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
216 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
217 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
218 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
222 struct field_modify_info modify_vlan_out_first_vid[] = {
223 /* Size in bits !!! */
224 {12, 0, MLX5_MODI_OUT_FIRST_VID},
228 struct field_modify_info modify_ipv4[] = {
229 {1, 1, MLX5_MODI_OUT_IP_DSCP},
230 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
231 {4, 12, MLX5_MODI_OUT_SIPV4},
232 {4, 16, MLX5_MODI_OUT_DIPV4},
236 struct field_modify_info modify_ipv6[] = {
237 {1, 0, MLX5_MODI_OUT_IP_DSCP},
238 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
239 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
240 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
241 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
242 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
243 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
244 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
245 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
246 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
250 struct field_modify_info modify_udp[] = {
251 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
252 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
256 struct field_modify_info modify_tcp[] = {
257 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
258 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
259 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
260 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
266 uint8_t next_protocol, uint64_t *item_flags,
269 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
270 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
271 if (next_protocol == IPPROTO_IPIP) {
272 *item_flags |= MLX5_FLOW_LAYER_IPIP;
275 if (next_protocol == IPPROTO_IPV6) {
276 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
281 /* Update VLAN's VID/PCP based on input rte_flow_action.
284 * Pointer to struct rte_flow_action.
286 * Pointer to struct rte_vlan_hdr.
289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
290 struct rte_vlan_hdr *vlan)
293 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
295 ((const struct rte_flow_action_of_set_vlan_pcp *)
296 action->conf)->vlan_pcp;
297 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
298 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
299 vlan->vlan_tci |= vlan_tci;
300 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
301 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
302 vlan->vlan_tci |= rte_be_to_cpu_16
303 (((const struct rte_flow_action_of_set_vlan_vid *)
304 action->conf)->vlan_vid);
309 * Fetch 1, 2, 3 or 4 byte field from the byte array
310 * and return as unsigned integer in host-endian format.
313 * Pointer to data array.
315 * Size of field to extract.
318 * converted field in host endian format.
320 static inline uint32_t
321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
330 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
333 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
334 ret = (ret << 8) | *(data + sizeof(uint16_t));
337 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
348 * Convert modify-header action to DV specification.
350 * Data length of each action is determined by provided field description
351 * and the item mask. Data bit offset and width of each action is determined
352 * by provided item mask.
355 * Pointer to item specification.
357 * Pointer to field modification information.
358 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
359 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
360 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
362 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
363 * Negative offset value sets the same offset as source offset.
364 * size field is ignored, value is taken from source field.
365 * @param[in,out] resource
366 * Pointer to the modify-header resource.
368 * Type of modification.
370 * Pointer to the error structure.
373 * 0 on success, a negative errno value otherwise and rte_errno is set.
376 flow_dv_convert_modify_action(struct rte_flow_item *item,
377 struct field_modify_info *field,
378 struct field_modify_info *dcopy,
379 struct mlx5_flow_dv_modify_hdr_resource *resource,
380 uint32_t type, struct rte_flow_error *error)
382 uint32_t i = resource->actions_num;
383 struct mlx5_modification_cmd *actions = resource->actions;
386 * The item and mask are provided in big-endian format.
387 * The fields should be presented as in big-endian format either.
388 * Mask must be always present, it defines the actual field width.
390 MLX5_ASSERT(item->mask);
391 MLX5_ASSERT(field->size);
398 if (i >= MLX5_MAX_MODIFY_NUM)
399 return rte_flow_error_set(error, EINVAL,
400 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
401 "too many items to modify");
402 /* Fetch variable byte size mask from the array. */
403 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
404 field->offset, field->size);
409 /* Deduce actual data width in bits from mask value. */
410 off_b = rte_bsf32(mask);
411 size_b = sizeof(uint32_t) * CHAR_BIT -
412 off_b - __builtin_clz(mask);
414 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
415 actions[i] = (struct mlx5_modification_cmd) {
421 /* Convert entire record to expected big-endian format. */
422 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
423 if (type == MLX5_MODIFICATION_TYPE_COPY) {
425 actions[i].dst_field = dcopy->id;
426 actions[i].dst_offset =
427 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
428 /* Convert entire record to big-endian format. */
429 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
431 MLX5_ASSERT(item->spec);
432 data = flow_dv_fetch_field((const uint8_t *)item->spec +
433 field->offset, field->size);
434 /* Shift out the trailing masked bits from data. */
435 data = (data & mask) >> off_b;
436 actions[i].data1 = rte_cpu_to_be_32(data);
440 } while (field->size);
441 if (resource->actions_num == i)
442 return rte_flow_error_set(error, EINVAL,
443 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
444 "invalid modification flow item");
445 resource->actions_num = i;
450 * Convert modify-header set IPv4 address action to DV specification.
452 * @param[in,out] resource
453 * Pointer to the modify-header resource.
455 * Pointer to action specification.
457 * Pointer to the error structure.
460 * 0 on success, a negative errno value otherwise and rte_errno is set.
463 flow_dv_convert_action_modify_ipv4
464 (struct mlx5_flow_dv_modify_hdr_resource *resource,
465 const struct rte_flow_action *action,
466 struct rte_flow_error *error)
468 const struct rte_flow_action_set_ipv4 *conf =
469 (const struct rte_flow_action_set_ipv4 *)(action->conf);
470 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
471 struct rte_flow_item_ipv4 ipv4;
472 struct rte_flow_item_ipv4 ipv4_mask;
474 memset(&ipv4, 0, sizeof(ipv4));
475 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
476 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
477 ipv4.hdr.src_addr = conf->ipv4_addr;
478 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
480 ipv4.hdr.dst_addr = conf->ipv4_addr;
481 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
484 item.mask = &ipv4_mask;
485 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
486 MLX5_MODIFICATION_TYPE_SET, error);
490 * Convert modify-header set IPv6 address action to DV specification.
492 * @param[in,out] resource
493 * Pointer to the modify-header resource.
495 * Pointer to action specification.
497 * Pointer to the error structure.
500 * 0 on success, a negative errno value otherwise and rte_errno is set.
503 flow_dv_convert_action_modify_ipv6
504 (struct mlx5_flow_dv_modify_hdr_resource *resource,
505 const struct rte_flow_action *action,
506 struct rte_flow_error *error)
508 const struct rte_flow_action_set_ipv6 *conf =
509 (const struct rte_flow_action_set_ipv6 *)(action->conf);
510 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
511 struct rte_flow_item_ipv6 ipv6;
512 struct rte_flow_item_ipv6 ipv6_mask;
514 memset(&ipv6, 0, sizeof(ipv6));
515 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
516 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
517 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
518 sizeof(ipv6.hdr.src_addr));
519 memcpy(&ipv6_mask.hdr.src_addr,
520 &rte_flow_item_ipv6_mask.hdr.src_addr,
521 sizeof(ipv6.hdr.src_addr));
523 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
524 sizeof(ipv6.hdr.dst_addr));
525 memcpy(&ipv6_mask.hdr.dst_addr,
526 &rte_flow_item_ipv6_mask.hdr.dst_addr,
527 sizeof(ipv6.hdr.dst_addr));
530 item.mask = &ipv6_mask;
531 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
532 MLX5_MODIFICATION_TYPE_SET, error);
536 * Convert modify-header set MAC address action to DV specification.
538 * @param[in,out] resource
539 * Pointer to the modify-header resource.
541 * Pointer to action specification.
543 * Pointer to the error structure.
546 * 0 on success, a negative errno value otherwise and rte_errno is set.
549 flow_dv_convert_action_modify_mac
550 (struct mlx5_flow_dv_modify_hdr_resource *resource,
551 const struct rte_flow_action *action,
552 struct rte_flow_error *error)
554 const struct rte_flow_action_set_mac *conf =
555 (const struct rte_flow_action_set_mac *)(action->conf);
556 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
557 struct rte_flow_item_eth eth;
558 struct rte_flow_item_eth eth_mask;
560 memset(ð, 0, sizeof(eth));
561 memset(ð_mask, 0, sizeof(eth_mask));
562 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
563 memcpy(ð.src.addr_bytes, &conf->mac_addr,
564 sizeof(eth.src.addr_bytes));
565 memcpy(ð_mask.src.addr_bytes,
566 &rte_flow_item_eth_mask.src.addr_bytes,
567 sizeof(eth_mask.src.addr_bytes));
569 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
570 sizeof(eth.dst.addr_bytes));
571 memcpy(ð_mask.dst.addr_bytes,
572 &rte_flow_item_eth_mask.dst.addr_bytes,
573 sizeof(eth_mask.dst.addr_bytes));
576 item.mask = ð_mask;
577 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
578 MLX5_MODIFICATION_TYPE_SET, error);
582 * Convert modify-header set VLAN VID action to DV specification.
584 * @param[in,out] resource
585 * Pointer to the modify-header resource.
587 * Pointer to action specification.
589 * Pointer to the error structure.
592 * 0 on success, a negative errno value otherwise and rte_errno is set.
595 flow_dv_convert_action_modify_vlan_vid
596 (struct mlx5_flow_dv_modify_hdr_resource *resource,
597 const struct rte_flow_action *action,
598 struct rte_flow_error *error)
600 const struct rte_flow_action_of_set_vlan_vid *conf =
601 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
602 int i = resource->actions_num;
603 struct mlx5_modification_cmd *actions = resource->actions;
604 struct field_modify_info *field = modify_vlan_out_first_vid;
606 if (i >= MLX5_MAX_MODIFY_NUM)
607 return rte_flow_error_set(error, EINVAL,
608 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
609 "too many items to modify");
610 actions[i] = (struct mlx5_modification_cmd) {
611 .action_type = MLX5_MODIFICATION_TYPE_SET,
613 .length = field->size,
614 .offset = field->offset,
616 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
617 actions[i].data1 = conf->vlan_vid;
618 actions[i].data1 = actions[i].data1 << 16;
619 resource->actions_num = ++i;
624 * Convert modify-header set TP action to DV specification.
626 * @param[in,out] resource
627 * Pointer to the modify-header resource.
629 * Pointer to action specification.
631 * Pointer to rte_flow_item objects list.
633 * Pointer to flow attributes structure.
634 * @param[in] dev_flow
635 * Pointer to the sub flow.
636 * @param[in] tunnel_decap
637 * Whether action is after tunnel decapsulation.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_tp
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
650 bool tunnel_decap, struct rte_flow_error *error)
652 const struct rte_flow_action_set_tp *conf =
653 (const struct rte_flow_action_set_tp *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_udp udp;
656 struct rte_flow_item_udp udp_mask;
657 struct rte_flow_item_tcp tcp;
658 struct rte_flow_item_tcp tcp_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
664 memset(&udp, 0, sizeof(udp));
665 memset(&udp_mask, 0, sizeof(udp_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
667 udp.hdr.src_port = conf->port;
668 udp_mask.hdr.src_port =
669 rte_flow_item_udp_mask.hdr.src_port;
671 udp.hdr.dst_port = conf->port;
672 udp_mask.hdr.dst_port =
673 rte_flow_item_udp_mask.hdr.dst_port;
675 item.type = RTE_FLOW_ITEM_TYPE_UDP;
677 item.mask = &udp_mask;
680 MLX5_ASSERT(attr->tcp);
681 memset(&tcp, 0, sizeof(tcp));
682 memset(&tcp_mask, 0, sizeof(tcp_mask));
683 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
684 tcp.hdr.src_port = conf->port;
685 tcp_mask.hdr.src_port =
686 rte_flow_item_tcp_mask.hdr.src_port;
688 tcp.hdr.dst_port = conf->port;
689 tcp_mask.hdr.dst_port =
690 rte_flow_item_tcp_mask.hdr.dst_port;
692 item.type = RTE_FLOW_ITEM_TYPE_TCP;
694 item.mask = &tcp_mask;
697 return flow_dv_convert_modify_action(&item, field, NULL, resource,
698 MLX5_MODIFICATION_TYPE_SET, error);
702 * Convert modify-header set TTL action to DV specification.
704 * @param[in,out] resource
705 * Pointer to the modify-header resource.
707 * Pointer to action specification.
709 * Pointer to rte_flow_item objects list.
711 * Pointer to flow attributes structure.
712 * @param[in] dev_flow
713 * Pointer to the sub flow.
714 * @param[in] tunnel_decap
715 * Whether action is after tunnel decapsulation.
717 * Pointer to the error structure.
720 * 0 on success, a negative errno value otherwise and rte_errno is set.
723 flow_dv_convert_action_modify_ttl
724 (struct mlx5_flow_dv_modify_hdr_resource *resource,
725 const struct rte_flow_action *action,
726 const struct rte_flow_item *items,
727 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
728 bool tunnel_decap, struct rte_flow_error *error)
730 const struct rte_flow_action_set_ttl *conf =
731 (const struct rte_flow_action_set_ttl *)(action->conf);
732 struct rte_flow_item item;
733 struct rte_flow_item_ipv4 ipv4;
734 struct rte_flow_item_ipv4 ipv4_mask;
735 struct rte_flow_item_ipv6 ipv6;
736 struct rte_flow_item_ipv6 ipv6_mask;
737 struct field_modify_info *field;
740 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
742 memset(&ipv4, 0, sizeof(ipv4));
743 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
744 ipv4.hdr.time_to_live = conf->ttl_value;
745 ipv4_mask.hdr.time_to_live = 0xFF;
746 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
748 item.mask = &ipv4_mask;
751 MLX5_ASSERT(attr->ipv6);
752 memset(&ipv6, 0, sizeof(ipv6));
753 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
754 ipv6.hdr.hop_limits = conf->ttl_value;
755 ipv6_mask.hdr.hop_limits = 0xFF;
756 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
758 item.mask = &ipv6_mask;
761 return flow_dv_convert_modify_action(&item, field, NULL, resource,
762 MLX5_MODIFICATION_TYPE_SET, error);
766 * Convert modify-header decrement TTL action to DV specification.
768 * @param[in,out] resource
769 * Pointer to the modify-header resource.
771 * Pointer to action specification.
773 * Pointer to rte_flow_item objects list.
775 * Pointer to flow attributes structure.
776 * @param[in] dev_flow
777 * Pointer to the sub flow.
778 * @param[in] tunnel_decap
779 * Whether action is after tunnel decapsulation.
781 * Pointer to the error structure.
784 * 0 on success, a negative errno value otherwise and rte_errno is set.
787 flow_dv_convert_action_modify_dec_ttl
788 (struct mlx5_flow_dv_modify_hdr_resource *resource,
789 const struct rte_flow_item *items,
790 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
791 bool tunnel_decap, struct rte_flow_error *error)
793 struct rte_flow_item item;
794 struct rte_flow_item_ipv4 ipv4;
795 struct rte_flow_item_ipv4 ipv4_mask;
796 struct rte_flow_item_ipv6 ipv6;
797 struct rte_flow_item_ipv6 ipv6_mask;
798 struct field_modify_info *field;
801 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
803 memset(&ipv4, 0, sizeof(ipv4));
804 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
805 ipv4.hdr.time_to_live = 0xFF;
806 ipv4_mask.hdr.time_to_live = 0xFF;
807 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
809 item.mask = &ipv4_mask;
812 MLX5_ASSERT(attr->ipv6);
813 memset(&ipv6, 0, sizeof(ipv6));
814 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
815 ipv6.hdr.hop_limits = 0xFF;
816 ipv6_mask.hdr.hop_limits = 0xFF;
817 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
819 item.mask = &ipv6_mask;
822 return flow_dv_convert_modify_action(&item, field, NULL, resource,
823 MLX5_MODIFICATION_TYPE_ADD, error);
827 * Convert modify-header increment/decrement TCP Sequence number
828 * to DV specification.
830 * @param[in,out] resource
831 * Pointer to the modify-header resource.
833 * Pointer to action specification.
835 * Pointer to the error structure.
838 * 0 on success, a negative errno value otherwise and rte_errno is set.
841 flow_dv_convert_action_modify_tcp_seq
842 (struct mlx5_flow_dv_modify_hdr_resource *resource,
843 const struct rte_flow_action *action,
844 struct rte_flow_error *error)
846 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
847 uint64_t value = rte_be_to_cpu_32(*conf);
848 struct rte_flow_item item;
849 struct rte_flow_item_tcp tcp;
850 struct rte_flow_item_tcp tcp_mask;
852 memset(&tcp, 0, sizeof(tcp));
853 memset(&tcp_mask, 0, sizeof(tcp_mask));
854 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
856 * The HW has no decrement operation, only increment operation.
857 * To simulate decrement X from Y using increment operation
858 * we need to add UINT32_MAX X times to Y.
859 * Each adding of UINT32_MAX decrements Y by 1.
862 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
863 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
864 item.type = RTE_FLOW_ITEM_TYPE_TCP;
866 item.mask = &tcp_mask;
867 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
868 MLX5_MODIFICATION_TYPE_ADD, error);
872 * Convert modify-header increment/decrement TCP Acknowledgment number
873 * to DV specification.
875 * @param[in,out] resource
876 * Pointer to the modify-header resource.
878 * Pointer to action specification.
880 * Pointer to the error structure.
883 * 0 on success, a negative errno value otherwise and rte_errno is set.
886 flow_dv_convert_action_modify_tcp_ack
887 (struct mlx5_flow_dv_modify_hdr_resource *resource,
888 const struct rte_flow_action *action,
889 struct rte_flow_error *error)
891 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
892 uint64_t value = rte_be_to_cpu_32(*conf);
893 struct rte_flow_item item;
894 struct rte_flow_item_tcp tcp;
895 struct rte_flow_item_tcp tcp_mask;
897 memset(&tcp, 0, sizeof(tcp));
898 memset(&tcp_mask, 0, sizeof(tcp_mask));
899 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
901 * The HW has no decrement operation, only increment operation.
902 * To simulate decrement X from Y using increment operation
903 * we need to add UINT32_MAX X times to Y.
904 * Each adding of UINT32_MAX decrements Y by 1.
907 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
908 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
909 item.type = RTE_FLOW_ITEM_TYPE_TCP;
911 item.mask = &tcp_mask;
912 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
916 static enum mlx5_modification_field reg_to_field[] = {
917 [REG_NON] = MLX5_MODI_OUT_NONE,
918 [REG_A] = MLX5_MODI_META_DATA_REG_A,
919 [REG_B] = MLX5_MODI_META_DATA_REG_B,
920 [REG_C_0] = MLX5_MODI_META_REG_C_0,
921 [REG_C_1] = MLX5_MODI_META_REG_C_1,
922 [REG_C_2] = MLX5_MODI_META_REG_C_2,
923 [REG_C_3] = MLX5_MODI_META_REG_C_3,
924 [REG_C_4] = MLX5_MODI_META_REG_C_4,
925 [REG_C_5] = MLX5_MODI_META_REG_C_5,
926 [REG_C_6] = MLX5_MODI_META_REG_C_6,
927 [REG_C_7] = MLX5_MODI_META_REG_C_7,
931 * Convert register set to DV specification.
933 * @param[in,out] resource
934 * Pointer to the modify-header resource.
936 * Pointer to action specification.
938 * Pointer to the error structure.
941 * 0 on success, a negative errno value otherwise and rte_errno is set.
944 flow_dv_convert_action_set_reg
945 (struct mlx5_flow_dv_modify_hdr_resource *resource,
946 const struct rte_flow_action *action,
947 struct rte_flow_error *error)
949 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
950 struct mlx5_modification_cmd *actions = resource->actions;
951 uint32_t i = resource->actions_num;
953 if (i >= MLX5_MAX_MODIFY_NUM)
954 return rte_flow_error_set(error, EINVAL,
955 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
956 "too many items to modify");
957 MLX5_ASSERT(conf->id != REG_NON);
958 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
959 actions[i] = (struct mlx5_modification_cmd) {
960 .action_type = MLX5_MODIFICATION_TYPE_SET,
961 .field = reg_to_field[conf->id],
963 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
964 actions[i].data1 = rte_cpu_to_be_32(conf->data);
966 resource->actions_num = i;
971 * Convert SET_TAG action to DV specification.
974 * Pointer to the rte_eth_dev structure.
975 * @param[in,out] resource
976 * Pointer to the modify-header resource.
978 * Pointer to action specification.
980 * Pointer to the error structure.
983 * 0 on success, a negative errno value otherwise and rte_errno is set.
986 flow_dv_convert_action_set_tag
987 (struct rte_eth_dev *dev,
988 struct mlx5_flow_dv_modify_hdr_resource *resource,
989 const struct rte_flow_action_set_tag *conf,
990 struct rte_flow_error *error)
992 rte_be32_t data = rte_cpu_to_be_32(conf->data);
993 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
994 struct rte_flow_item item = {
998 struct field_modify_info reg_c_x[] = {
1001 enum mlx5_modification_field reg_type;
1004 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1007 MLX5_ASSERT(ret != REG_NON);
1008 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009 reg_type = reg_to_field[ret];
1010 MLX5_ASSERT(reg_type > 0);
1011 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013 MLX5_MODIFICATION_TYPE_SET, error);
1017 * Convert internal COPY_REG action to DV specification.
1020 * Pointer to the rte_eth_dev structure.
1021 * @param[in,out] res
1022 * Pointer to the modify-header resource.
1024 * Pointer to action specification.
1026 * Pointer to the error structure.
1029 * 0 on success, a negative errno value otherwise and rte_errno is set.
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033 struct mlx5_flow_dv_modify_hdr_resource *res,
1034 const struct rte_flow_action *action,
1035 struct rte_flow_error *error)
1037 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039 struct rte_flow_item item = {
1043 struct field_modify_info reg_src[] = {
1044 {4, 0, reg_to_field[conf->src]},
1047 struct field_modify_info reg_dst = {
1049 .id = reg_to_field[conf->dst],
1051 /* Adjust reg_c[0] usage according to reported mask. */
1052 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053 struct mlx5_priv *priv = dev->data->dev_private;
1054 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1056 MLX5_ASSERT(reg_c0);
1057 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058 if (conf->dst == REG_C_0) {
1059 /* Copy to reg_c[0], within mask only. */
1060 reg_dst.offset = rte_bsf32(reg_c0);
1062 * Mask is ignoring the enianness, because
1063 * there is no conversion in datapath.
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066 /* Copy from destination lower bits to reg_c[0]. */
1067 mask = reg_c0 >> reg_dst.offset;
1069 /* Copy from destination upper bits to reg_c[0]. */
1070 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071 rte_fls_u32(reg_c0));
1074 mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076 /* Copy from reg_c[0] to destination lower bits. */
1079 /* Copy from reg_c[0] to destination upper bits. */
1080 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081 (rte_fls_u32(reg_c0) -
1086 return flow_dv_convert_modify_action(&item,
1087 reg_src, ®_dst, res,
1088 MLX5_MODIFICATION_TYPE_COPY,
1093 * Convert MARK action to DV specification. This routine is used
1094 * in extensive metadata only and requires metadata register to be
1095 * handled. In legacy mode hardware tag resource is engaged.
1098 * Pointer to the rte_eth_dev structure.
1100 * Pointer to MARK action specification.
1101 * @param[in,out] resource
1102 * Pointer to the modify-header resource.
1104 * Pointer to the error structure.
1107 * 0 on success, a negative errno value otherwise and rte_errno is set.
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111 const struct rte_flow_action_mark *conf,
1112 struct mlx5_flow_dv_modify_hdr_resource *resource,
1113 struct rte_flow_error *error)
1115 struct mlx5_priv *priv = dev->data->dev_private;
1116 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117 priv->sh->dv_mark_mask);
1118 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119 struct rte_flow_item item = {
1123 struct field_modify_info reg_c_x[] = {
1129 return rte_flow_error_set(error, EINVAL,
1130 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131 NULL, "zero mark action mask");
1132 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1135 MLX5_ASSERT(reg > 0);
1136 if (reg == REG_C_0) {
1137 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138 uint32_t shl_c0 = rte_bsf32(msk_c0);
1140 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142 mask = rte_cpu_to_be_32(mask << shl_c0);
1144 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146 MLX5_MODIFICATION_TYPE_SET, error);
1150 * Get metadata register index for specified steering domain.
1153 * Pointer to the rte_eth_dev structure.
1155 * Attributes of flow to determine steering domain.
1157 * Pointer to the error structure.
1160 * positive index on success, a negative errno value otherwise
1161 * and rte_errno is set.
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165 const struct rte_flow_attr *attr,
1166 struct rte_flow_error *error)
1169 mlx5_flow_get_reg_id(dev, attr->transfer ?
1173 MLX5_METADATA_RX, 0, error);
1175 return rte_flow_error_set(error,
1176 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177 NULL, "unavailable "
1178 "metadata register");
1183 * Convert SET_META action to DV specification.
1186 * Pointer to the rte_eth_dev structure.
1187 * @param[in,out] resource
1188 * Pointer to the modify-header resource.
1190 * Attributes of flow that includes this item.
1192 * Pointer to action specification.
1194 * Pointer to the error structure.
1197 * 0 on success, a negative errno value otherwise and rte_errno is set.
1200 flow_dv_convert_action_set_meta
1201 (struct rte_eth_dev *dev,
1202 struct mlx5_flow_dv_modify_hdr_resource *resource,
1203 const struct rte_flow_attr *attr,
1204 const struct rte_flow_action_set_meta *conf,
1205 struct rte_flow_error *error)
1207 uint32_t data = conf->data;
1208 uint32_t mask = conf->mask;
1209 struct rte_flow_item item = {
1213 struct field_modify_info reg_c_x[] = {
1216 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1220 MLX5_ASSERT(reg != REG_NON);
1222 * In datapath code there is no endianness
1223 * coversions for perfromance reasons, all
1224 * pattern conversions are done in rte_flow.
1226 if (reg == REG_C_0) {
1227 struct mlx5_priv *priv = dev->data->dev_private;
1228 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1231 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233 shl_c0 = rte_bsf32(msk_c0);
1235 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1239 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1241 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242 /* The routine expects parameters in memory as big-endian ones. */
1243 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244 MLX5_MODIFICATION_TYPE_SET, error);
1248 * Convert modify-header set IPv4 DSCP action to DV specification.
1250 * @param[in,out] resource
1251 * Pointer to the modify-header resource.
1253 * Pointer to action specification.
1255 * Pointer to the error structure.
1258 * 0 on success, a negative errno value otherwise and rte_errno is set.
1261 flow_dv_convert_action_modify_ipv4_dscp
1262 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263 const struct rte_flow_action *action,
1264 struct rte_flow_error *error)
1266 const struct rte_flow_action_set_dscp *conf =
1267 (const struct rte_flow_action_set_dscp *)(action->conf);
1268 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269 struct rte_flow_item_ipv4 ipv4;
1270 struct rte_flow_item_ipv4 ipv4_mask;
1272 memset(&ipv4, 0, sizeof(ipv4));
1273 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274 ipv4.hdr.type_of_service = conf->dscp;
1275 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1277 item.mask = &ipv4_mask;
1278 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279 MLX5_MODIFICATION_TYPE_SET, error);
1283 * Convert modify-header set IPv6 DSCP action to DV specification.
1285 * @param[in,out] resource
1286 * Pointer to the modify-header resource.
1288 * Pointer to action specification.
1290 * Pointer to the error structure.
1293 * 0 on success, a negative errno value otherwise and rte_errno is set.
1296 flow_dv_convert_action_modify_ipv6_dscp
1297 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298 const struct rte_flow_action *action,
1299 struct rte_flow_error *error)
1301 const struct rte_flow_action_set_dscp *conf =
1302 (const struct rte_flow_action_set_dscp *)(action->conf);
1303 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304 struct rte_flow_item_ipv6 ipv6;
1305 struct rte_flow_item_ipv6 ipv6_mask;
1307 memset(&ipv6, 0, sizeof(ipv6));
1308 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1310 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311 * rdma-core only accept the DSCP bits byte aligned start from
1312 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313 * bits in IPv6 case as rdma-core requires byte aligned value.
1315 ipv6.hdr.vtc_flow = conf->dscp;
1316 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1318 item.mask = &ipv6_mask;
1319 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Validate MARK item.
1327 * Pointer to the rte_eth_dev structure.
1329 * Item specification.
1331 * Attributes of flow that includes this item.
1333 * Pointer to error structure.
1336 * 0 on success, a negative errno value otherwise and rte_errno is set.
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340 const struct rte_flow_item *item,
1341 const struct rte_flow_attr *attr __rte_unused,
1342 struct rte_flow_error *error)
1344 struct mlx5_priv *priv = dev->data->dev_private;
1345 struct mlx5_dev_config *config = &priv->config;
1346 const struct rte_flow_item_mark *spec = item->spec;
1347 const struct rte_flow_item_mark *mask = item->mask;
1348 const struct rte_flow_item_mark nic_mask = {
1349 .id = priv->sh->dv_mark_mask,
1353 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354 return rte_flow_error_set(error, ENOTSUP,
1355 RTE_FLOW_ERROR_TYPE_ITEM, item,
1356 "extended metadata feature"
1358 if (!mlx5_flow_ext_mreg_supported(dev))
1359 return rte_flow_error_set(error, ENOTSUP,
1360 RTE_FLOW_ERROR_TYPE_ITEM, item,
1361 "extended metadata register"
1362 " isn't supported");
1364 return rte_flow_error_set(error, ENOTSUP,
1365 RTE_FLOW_ERROR_TYPE_ITEM, item,
1366 "extended metadata register"
1367 " isn't available");
1368 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1372 return rte_flow_error_set(error, EINVAL,
1373 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1375 "data cannot be empty");
1376 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377 return rte_flow_error_set(error, EINVAL,
1378 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1380 "mark id exceeds the limit");
1384 return rte_flow_error_set(error, EINVAL,
1385 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386 "mask cannot be zero");
1388 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389 (const uint8_t *)&nic_mask,
1390 sizeof(struct rte_flow_item_mark),
1391 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1398 * Validate META item.
1401 * Pointer to the rte_eth_dev structure.
1403 * Item specification.
1405 * Attributes of flow that includes this item.
1407 * Pointer to error structure.
1410 * 0 on success, a negative errno value otherwise and rte_errno is set.
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414 const struct rte_flow_item *item,
1415 const struct rte_flow_attr *attr,
1416 struct rte_flow_error *error)
1418 struct mlx5_priv *priv = dev->data->dev_private;
1419 struct mlx5_dev_config *config = &priv->config;
1420 const struct rte_flow_item_meta *spec = item->spec;
1421 const struct rte_flow_item_meta *mask = item->mask;
1422 struct rte_flow_item_meta nic_mask = {
1429 return rte_flow_error_set(error, EINVAL,
1430 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1432 "data cannot be empty");
1433 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434 if (!mlx5_flow_ext_mreg_supported(dev))
1435 return rte_flow_error_set(error, ENOTSUP,
1436 RTE_FLOW_ERROR_TYPE_ITEM, item,
1437 "extended metadata register"
1438 " isn't supported");
1439 reg = flow_dv_get_metadata_reg(dev, attr, error);
1443 return rte_flow_error_set(error, ENOTSUP,
1444 RTE_FLOW_ERROR_TYPE_ITEM, item,
1445 "unavalable extended metadata register");
1447 return rte_flow_error_set(error, ENOTSUP,
1448 RTE_FLOW_ERROR_TYPE_ITEM, item,
1452 nic_mask.data = priv->sh->dv_meta_mask;
1453 } else if (attr->transfer) {
1454 return rte_flow_error_set(error, ENOTSUP,
1455 RTE_FLOW_ERROR_TYPE_ITEM, item,
1456 "extended metadata feature "
1457 "should be enabled when "
1458 "meta item is requested "
1459 "with e-switch mode ");
1462 mask = &rte_flow_item_meta_mask;
1464 return rte_flow_error_set(error, EINVAL,
1465 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466 "mask cannot be zero");
1468 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469 (const uint8_t *)&nic_mask,
1470 sizeof(struct rte_flow_item_meta),
1471 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1476 * Validate TAG item.
1479 * Pointer to the rte_eth_dev structure.
1481 * Item specification.
1483 * Attributes of flow that includes this item.
1485 * Pointer to error structure.
1488 * 0 on success, a negative errno value otherwise and rte_errno is set.
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492 const struct rte_flow_item *item,
1493 const struct rte_flow_attr *attr __rte_unused,
1494 struct rte_flow_error *error)
1496 const struct rte_flow_item_tag *spec = item->spec;
1497 const struct rte_flow_item_tag *mask = item->mask;
1498 const struct rte_flow_item_tag nic_mask = {
1499 .data = RTE_BE32(UINT32_MAX),
1504 if (!mlx5_flow_ext_mreg_supported(dev))
1505 return rte_flow_error_set(error, ENOTSUP,
1506 RTE_FLOW_ERROR_TYPE_ITEM, item,
1507 "extensive metadata register"
1508 " isn't supported");
1510 return rte_flow_error_set(error, EINVAL,
1511 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1513 "data cannot be empty");
1515 mask = &rte_flow_item_tag_mask;
1517 return rte_flow_error_set(error, EINVAL,
1518 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519 "mask cannot be zero");
1521 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522 (const uint8_t *)&nic_mask,
1523 sizeof(struct rte_flow_item_tag),
1524 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1527 if (mask->index != 0xff)
1528 return rte_flow_error_set(error, EINVAL,
1529 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530 "partial mask for tag index"
1531 " is not supported");
1532 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1535 MLX5_ASSERT(ret != REG_NON);
1540 * Validate vport item.
1543 * Pointer to the rte_eth_dev structure.
1545 * Item specification.
1547 * Attributes of flow that includes this item.
1548 * @param[in] item_flags
1549 * Bit-fields that holds the items detected until now.
1551 * Pointer to error structure.
1554 * 0 on success, a negative errno value otherwise and rte_errno is set.
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558 const struct rte_flow_item *item,
1559 const struct rte_flow_attr *attr,
1560 uint64_t item_flags,
1561 struct rte_flow_error *error)
1563 const struct rte_flow_item_port_id *spec = item->spec;
1564 const struct rte_flow_item_port_id *mask = item->mask;
1565 const struct rte_flow_item_port_id switch_mask = {
1568 struct mlx5_priv *esw_priv;
1569 struct mlx5_priv *dev_priv;
1572 if (!attr->transfer)
1573 return rte_flow_error_set(error, EINVAL,
1574 RTE_FLOW_ERROR_TYPE_ITEM,
1576 "match on port id is valid only"
1577 " when transfer flag is enabled");
1578 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579 return rte_flow_error_set(error, ENOTSUP,
1580 RTE_FLOW_ERROR_TYPE_ITEM, item,
1581 "multiple source ports are not"
1584 mask = &switch_mask;
1585 if (mask->id != 0xffffffff)
1586 return rte_flow_error_set(error, ENOTSUP,
1587 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1589 "no support for partial mask on"
1591 ret = mlx5_flow_item_acceptable
1592 (item, (const uint8_t *)mask,
1593 (const uint8_t *)&rte_flow_item_port_id_mask,
1594 sizeof(struct rte_flow_item_port_id),
1595 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1600 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1602 return rte_flow_error_set(error, rte_errno,
1603 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604 "failed to obtain E-Switch info for"
1606 dev_priv = mlx5_dev_to_eswitch_info(dev);
1608 return rte_flow_error_set(error, rte_errno,
1609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1611 "failed to obtain E-Switch info");
1612 if (esw_priv->domain_id != dev_priv->domain_id)
1613 return rte_flow_error_set(error, EINVAL,
1614 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615 "cannot match on a port from a"
1616 " different E-Switch");
1621 * Validate VLAN item.
1624 * Item specification.
1625 * @param[in] item_flags
1626 * Bit-fields that holds the items detected until now.
1628 * Ethernet device flow is being created on.
1630 * Pointer to error structure.
1633 * 0 on success, a negative errno value otherwise and rte_errno is set.
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637 uint64_t item_flags,
1638 struct rte_eth_dev *dev,
1639 struct rte_flow_error *error)
1641 const struct rte_flow_item_vlan *mask = item->mask;
1642 const struct rte_flow_item_vlan nic_mask = {
1643 .tci = RTE_BE16(UINT16_MAX),
1644 .inner_type = RTE_BE16(UINT16_MAX),
1647 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1649 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650 MLX5_FLOW_LAYER_INNER_L4) :
1651 (MLX5_FLOW_LAYER_OUTER_L3 |
1652 MLX5_FLOW_LAYER_OUTER_L4);
1653 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654 MLX5_FLOW_LAYER_OUTER_VLAN;
1656 if (item_flags & vlanm)
1657 return rte_flow_error_set(error, EINVAL,
1658 RTE_FLOW_ERROR_TYPE_ITEM, item,
1659 "multiple VLAN layers not supported");
1660 else if ((item_flags & l34m) != 0)
1661 return rte_flow_error_set(error, EINVAL,
1662 RTE_FLOW_ERROR_TYPE_ITEM, item,
1663 "VLAN cannot follow L3/L4 layer");
1665 mask = &rte_flow_item_vlan_mask;
1666 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667 (const uint8_t *)&nic_mask,
1668 sizeof(struct rte_flow_item_vlan),
1669 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1672 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673 struct mlx5_priv *priv = dev->data->dev_private;
1675 if (priv->vmwa_context) {
1677 * Non-NULL context means we have a virtual machine
1678 * and SR-IOV enabled, we have to create VLAN interface
1679 * to make hypervisor to setup E-Switch vport
1680 * context correctly. We avoid creating the multiple
1681 * VLAN interfaces, so we cannot support VLAN tag mask.
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ITEM,
1686 "VLAN tag mask is not"
1687 " supported in virtual"
1695 * GTP flags are contained in 1 byte of the format:
1696 * -------------------------------------------
1697 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1698 * |-----------------------------------------|
1699 * | value | Version | PT | Res | E | S | PN |
1700 * -------------------------------------------
1702 * Matching is supported only for GTP flags E, S, PN.
1704 #define MLX5_GTP_FLAGS_MASK 0x07
1707 * Validate GTP item.
1710 * Pointer to the rte_eth_dev structure.
1712 * Item specification.
1713 * @param[in] item_flags
1714 * Bit-fields that holds the items detected until now.
1716 * Pointer to error structure.
1719 * 0 on success, a negative errno value otherwise and rte_errno is set.
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723 const struct rte_flow_item *item,
1724 uint64_t item_flags,
1725 struct rte_flow_error *error)
1727 struct mlx5_priv *priv = dev->data->dev_private;
1728 const struct rte_flow_item_gtp *spec = item->spec;
1729 const struct rte_flow_item_gtp *mask = item->mask;
1730 const struct rte_flow_item_gtp nic_mask = {
1731 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1733 .teid = RTE_BE32(0xffffffff),
1736 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737 return rte_flow_error_set(error, ENOTSUP,
1738 RTE_FLOW_ERROR_TYPE_ITEM, item,
1739 "GTP support is not enabled");
1740 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741 return rte_flow_error_set(error, ENOTSUP,
1742 RTE_FLOW_ERROR_TYPE_ITEM, item,
1743 "multiple tunnel layers not"
1745 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746 return rte_flow_error_set(error, EINVAL,
1747 RTE_FLOW_ERROR_TYPE_ITEM, item,
1748 "no outer UDP layer found");
1750 mask = &rte_flow_item_gtp_mask;
1751 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752 return rte_flow_error_set(error, ENOTSUP,
1753 RTE_FLOW_ERROR_TYPE_ITEM, item,
1754 "Match is supported for GTP"
1756 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757 (const uint8_t *)&nic_mask,
1758 sizeof(struct rte_flow_item_gtp),
1759 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1763 * Validate IPV4 item.
1764 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1765 * add specific validation of fragment_offset field,
1768 * Item specification.
1769 * @param[in] item_flags
1770 * Bit-fields that holds the items detected until now.
1772 * Pointer to error structure.
1775 * 0 on success, a negative errno value otherwise and rte_errno is set.
1778 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1779 uint64_t item_flags,
1781 uint16_t ether_type,
1782 struct rte_flow_error *error)
1785 const struct rte_flow_item_ipv4 *spec = item->spec;
1786 const struct rte_flow_item_ipv4 *last = item->last;
1787 const struct rte_flow_item_ipv4 *mask = item->mask;
1788 rte_be16_t fragment_offset_spec = 0;
1789 rte_be16_t fragment_offset_last = 0;
1790 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1792 .src_addr = RTE_BE32(0xffffffff),
1793 .dst_addr = RTE_BE32(0xffffffff),
1794 .type_of_service = 0xff,
1795 .fragment_offset = RTE_BE16(0xffff),
1796 .next_proto_id = 0xff,
1797 .time_to_live = 0xff,
1801 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1802 ether_type, &nic_ipv4_mask,
1803 MLX5_ITEM_RANGE_ACCEPTED, error);
1807 fragment_offset_spec = spec->hdr.fragment_offset &
1808 mask->hdr.fragment_offset;
1809 if (!fragment_offset_spec)
1812 * spec and mask are valid, enforce using full mask to make sure the
1813 * complete value is used correctly.
1815 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1816 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1817 return rte_flow_error_set(error, EINVAL,
1818 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1819 item, "must use full mask for"
1820 " fragment_offset");
1822 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1823 * indicating this is 1st fragment of fragmented packet.
1824 * This is not yet supported in MLX5, return appropriate error message.
1826 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1827 return rte_flow_error_set(error, ENOTSUP,
1828 RTE_FLOW_ERROR_TYPE_ITEM, item,
1829 "match on first fragment not "
1831 if (fragment_offset_spec && !last)
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_ITEM, item,
1834 "specified value not supported");
1835 /* spec and last are valid, validate the specified range. */
1836 fragment_offset_last = last->hdr.fragment_offset &
1837 mask->hdr.fragment_offset;
1839 * Match on fragment_offset spec 0x2001 and last 0x3fff
1840 * means MF is 1 and frag-offset is > 0.
1841 * This packet is fragment 2nd and onward, excluding last.
1842 * This is not yet supported in MLX5, return appropriate
1845 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1846 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1849 last, "match on following "
1850 "fragments not supported");
1852 * Match on fragment_offset spec 0x0001 and last 0x1fff
1853 * means MF is 0 and frag-offset is > 0.
1854 * This packet is last fragment of fragmented packet.
1855 * This is not yet supported in MLX5, return appropriate
1858 if (fragment_offset_spec == RTE_BE16(1) &&
1859 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1860 return rte_flow_error_set(error, ENOTSUP,
1861 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1862 last, "match on last "
1863 "fragment not supported");
1865 * Match on fragment_offset spec 0x0001 and last 0x3fff
1866 * means MF and/or frag-offset is not 0.
1867 * This is a fragmented packet.
1868 * Other range values are invalid and rejected.
1870 if (!(fragment_offset_spec == RTE_BE16(1) &&
1871 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1872 return rte_flow_error_set(error, ENOTSUP,
1873 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1874 "specified range not supported");
1879 * Validate IPV6 fragment extension item.
1882 * Item specification.
1883 * @param[in] item_flags
1884 * Bit-fields that holds the items detected until now.
1886 * Pointer to error structure.
1889 * 0 on success, a negative errno value otherwise and rte_errno is set.
1892 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1893 uint64_t item_flags,
1894 struct rte_flow_error *error)
1896 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1897 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1898 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1899 rte_be16_t frag_data_spec = 0;
1900 rte_be16_t frag_data_last = 0;
1901 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1902 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1903 MLX5_FLOW_LAYER_OUTER_L4;
1905 struct rte_flow_item_ipv6_frag_ext nic_mask = {
1907 .next_header = 0xff,
1908 .frag_data = RTE_BE16(0xffff),
1912 if (item_flags & l4m)
1913 return rte_flow_error_set(error, EINVAL,
1914 RTE_FLOW_ERROR_TYPE_ITEM, item,
1915 "ipv6 fragment extension item cannot "
1917 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1918 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1919 return rte_flow_error_set(error, EINVAL,
1920 RTE_FLOW_ERROR_TYPE_ITEM, item,
1921 "ipv6 fragment extension item must "
1922 "follow ipv6 item");
1924 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1925 if (!frag_data_spec)
1928 * spec and mask are valid, enforce using full mask to make sure the
1929 * complete value is used correctly.
1931 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1932 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1933 return rte_flow_error_set(error, EINVAL,
1934 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1935 item, "must use full mask for"
1938 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1939 * This is 1st fragment of fragmented packet.
1941 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM, item,
1944 "match on first fragment not "
1946 if (frag_data_spec && !last)
1947 return rte_flow_error_set(error, EINVAL,
1948 RTE_FLOW_ERROR_TYPE_ITEM, item,
1949 "specified value not supported");
1950 ret = mlx5_flow_item_acceptable
1951 (item, (const uint8_t *)mask,
1952 (const uint8_t *)&nic_mask,
1953 sizeof(struct rte_flow_item_ipv6_frag_ext),
1954 MLX5_ITEM_RANGE_ACCEPTED, error);
1957 /* spec and last are valid, validate the specified range. */
1958 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1960 * Match on frag_data spec 0x0009 and last 0xfff9
1961 * means M is 1 and frag-offset is > 0.
1962 * This packet is fragment 2nd and onward, excluding last.
1963 * This is not yet supported in MLX5, return appropriate
1966 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1967 RTE_IPV6_EHDR_MF_MASK) &&
1968 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1969 return rte_flow_error_set(error, ENOTSUP,
1970 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1971 last, "match on following "
1972 "fragments not supported");
1974 * Match on frag_data spec 0x0008 and last 0xfff8
1975 * means M is 0 and frag-offset is > 0.
1976 * This packet is last fragment of fragmented packet.
1977 * This is not yet supported in MLX5, return appropriate
1980 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
1981 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
1982 return rte_flow_error_set(error, ENOTSUP,
1983 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1984 last, "match on last "
1985 "fragment not supported");
1986 /* Other range values are invalid and rejected. */
1987 return rte_flow_error_set(error, EINVAL,
1988 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1989 "specified range not supported");
1993 * Validate the pop VLAN action.
1996 * Pointer to the rte_eth_dev structure.
1997 * @param[in] action_flags
1998 * Holds the actions detected until now.
2000 * Pointer to the pop vlan action.
2001 * @param[in] item_flags
2002 * The items found in this flow rule.
2004 * Pointer to flow attributes.
2006 * Pointer to error structure.
2009 * 0 on success, a negative errno value otherwise and rte_errno is set.
2012 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2013 uint64_t action_flags,
2014 const struct rte_flow_action *action,
2015 uint64_t item_flags,
2016 const struct rte_flow_attr *attr,
2017 struct rte_flow_error *error)
2019 const struct mlx5_priv *priv = dev->data->dev_private;
2023 if (!priv->sh->pop_vlan_action)
2024 return rte_flow_error_set(error, ENOTSUP,
2025 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2027 "pop vlan action is not supported");
2029 return rte_flow_error_set(error, ENOTSUP,
2030 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2032 "pop vlan action not supported for "
2034 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2035 return rte_flow_error_set(error, ENOTSUP,
2036 RTE_FLOW_ERROR_TYPE_ACTION, action,
2037 "no support for multiple VLAN "
2039 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2040 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2041 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2042 return rte_flow_error_set(error, ENOTSUP,
2043 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2045 "cannot pop vlan after decap without "
2046 "match on inner vlan in the flow");
2047 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2048 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2049 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2050 return rte_flow_error_set(error, ENOTSUP,
2051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2053 "cannot pop vlan without a "
2054 "match on (outer) vlan in the flow");
2055 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2056 return rte_flow_error_set(error, EINVAL,
2057 RTE_FLOW_ERROR_TYPE_ACTION, action,
2058 "wrong action order, port_id should "
2059 "be after pop VLAN action");
2060 if (!attr->transfer && priv->representor)
2061 return rte_flow_error_set(error, ENOTSUP,
2062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2063 "pop vlan action for VF representor "
2064 "not supported on NIC table");
2069 * Get VLAN default info from vlan match info.
2072 * the list of item specifications.
2074 * pointer VLAN info to fill to.
2077 * 0 on success, a negative errno value otherwise and rte_errno is set.
2080 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2081 struct rte_vlan_hdr *vlan)
2083 const struct rte_flow_item_vlan nic_mask = {
2084 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2085 MLX5DV_FLOW_VLAN_VID_MASK),
2086 .inner_type = RTE_BE16(0xffff),
2091 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2092 int type = items->type;
2094 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2095 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2098 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2099 const struct rte_flow_item_vlan *vlan_m = items->mask;
2100 const struct rte_flow_item_vlan *vlan_v = items->spec;
2102 /* If VLAN item in pattern doesn't contain data, return here. */
2107 /* Only full match values are accepted */
2108 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2109 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2110 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2112 rte_be_to_cpu_16(vlan_v->tci &
2113 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2115 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2116 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2117 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2119 rte_be_to_cpu_16(vlan_v->tci &
2120 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2122 if (vlan_m->inner_type == nic_mask.inner_type)
2123 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2124 vlan_m->inner_type);
2129 * Validate the push VLAN action.
2132 * Pointer to the rte_eth_dev structure.
2133 * @param[in] action_flags
2134 * Holds the actions detected until now.
2135 * @param[in] item_flags
2136 * The items found in this flow rule.
2138 * Pointer to the action structure.
2140 * Pointer to flow attributes
2142 * Pointer to error structure.
2145 * 0 on success, a negative errno value otherwise and rte_errno is set.
2148 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2149 uint64_t action_flags,
2150 const struct rte_flow_item_vlan *vlan_m,
2151 const struct rte_flow_action *action,
2152 const struct rte_flow_attr *attr,
2153 struct rte_flow_error *error)
2155 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2156 const struct mlx5_priv *priv = dev->data->dev_private;
2158 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2159 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2160 return rte_flow_error_set(error, EINVAL,
2161 RTE_FLOW_ERROR_TYPE_ACTION, action,
2162 "invalid vlan ethertype");
2163 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2164 return rte_flow_error_set(error, EINVAL,
2165 RTE_FLOW_ERROR_TYPE_ACTION, action,
2166 "wrong action order, port_id should "
2167 "be after push VLAN");
2168 if (!attr->transfer && priv->representor)
2169 return rte_flow_error_set(error, ENOTSUP,
2170 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2171 "push vlan action for VF representor "
2172 "not supported on NIC table");
2174 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2175 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2176 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2177 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2178 !(mlx5_flow_find_action
2179 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2180 return rte_flow_error_set(error, EINVAL,
2181 RTE_FLOW_ERROR_TYPE_ACTION, action,
2182 "not full match mask on VLAN PCP and "
2183 "there is no of_set_vlan_pcp action, "
2184 "push VLAN action cannot figure out "
2187 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2188 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2189 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2190 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2191 !(mlx5_flow_find_action
2192 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2193 return rte_flow_error_set(error, EINVAL,
2194 RTE_FLOW_ERROR_TYPE_ACTION, action,
2195 "not full match mask on VLAN VID and "
2196 "there is no of_set_vlan_vid action, "
2197 "push VLAN action cannot figure out "
2204 * Validate the set VLAN PCP.
2206 * @param[in] action_flags
2207 * Holds the actions detected until now.
2208 * @param[in] actions
2209 * Pointer to the list of actions remaining in the flow rule.
2211 * Pointer to error structure.
2214 * 0 on success, a negative errno value otherwise and rte_errno is set.
2217 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2218 const struct rte_flow_action actions[],
2219 struct rte_flow_error *error)
2221 const struct rte_flow_action *action = actions;
2222 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2224 if (conf->vlan_pcp > 7)
2225 return rte_flow_error_set(error, EINVAL,
2226 RTE_FLOW_ERROR_TYPE_ACTION, action,
2227 "VLAN PCP value is too big");
2228 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2229 return rte_flow_error_set(error, ENOTSUP,
2230 RTE_FLOW_ERROR_TYPE_ACTION, action,
2231 "set VLAN PCP action must follow "
2232 "the push VLAN action");
2233 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2234 return rte_flow_error_set(error, ENOTSUP,
2235 RTE_FLOW_ERROR_TYPE_ACTION, action,
2236 "Multiple VLAN PCP modification are "
2238 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2239 return rte_flow_error_set(error, EINVAL,
2240 RTE_FLOW_ERROR_TYPE_ACTION, action,
2241 "wrong action order, port_id should "
2242 "be after set VLAN PCP");
2247 * Validate the set VLAN VID.
2249 * @param[in] item_flags
2250 * Holds the items detected in this rule.
2251 * @param[in] action_flags
2252 * Holds the actions detected until now.
2253 * @param[in] actions
2254 * Pointer to the list of actions remaining in the flow rule.
2256 * Pointer to error structure.
2259 * 0 on success, a negative errno value otherwise and rte_errno is set.
2262 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2263 uint64_t action_flags,
2264 const struct rte_flow_action actions[],
2265 struct rte_flow_error *error)
2267 const struct rte_flow_action *action = actions;
2268 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2270 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2271 return rte_flow_error_set(error, EINVAL,
2272 RTE_FLOW_ERROR_TYPE_ACTION, action,
2273 "VLAN VID value is too big");
2274 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2275 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2276 return rte_flow_error_set(error, ENOTSUP,
2277 RTE_FLOW_ERROR_TYPE_ACTION, action,
2278 "set VLAN VID action must follow push"
2279 " VLAN action or match on VLAN item");
2280 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2281 return rte_flow_error_set(error, ENOTSUP,
2282 RTE_FLOW_ERROR_TYPE_ACTION, action,
2283 "Multiple VLAN VID modifications are "
2285 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2286 return rte_flow_error_set(error, EINVAL,
2287 RTE_FLOW_ERROR_TYPE_ACTION, action,
2288 "wrong action order, port_id should "
2289 "be after set VLAN VID");
2294 * Validate the FLAG action.
2297 * Pointer to the rte_eth_dev structure.
2298 * @param[in] action_flags
2299 * Holds the actions detected until now.
2301 * Pointer to flow attributes
2303 * Pointer to error structure.
2306 * 0 on success, a negative errno value otherwise and rte_errno is set.
2309 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2310 uint64_t action_flags,
2311 const struct rte_flow_attr *attr,
2312 struct rte_flow_error *error)
2314 struct mlx5_priv *priv = dev->data->dev_private;
2315 struct mlx5_dev_config *config = &priv->config;
2318 /* Fall back if no extended metadata register support. */
2319 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2320 return mlx5_flow_validate_action_flag(action_flags, attr,
2322 /* Extensive metadata mode requires registers. */
2323 if (!mlx5_flow_ext_mreg_supported(dev))
2324 return rte_flow_error_set(error, ENOTSUP,
2325 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2326 "no metadata registers "
2327 "to support flag action");
2328 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2329 return rte_flow_error_set(error, ENOTSUP,
2330 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2331 "extended metadata register"
2332 " isn't available");
2333 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2336 MLX5_ASSERT(ret > 0);
2337 if (action_flags & MLX5_FLOW_ACTION_MARK)
2338 return rte_flow_error_set(error, EINVAL,
2339 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2340 "can't mark and flag in same flow");
2341 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2342 return rte_flow_error_set(error, EINVAL,
2343 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2345 " actions in same flow");
2350 * Validate MARK action.
2353 * Pointer to the rte_eth_dev structure.
2355 * Pointer to action.
2356 * @param[in] action_flags
2357 * Holds the actions detected until now.
2359 * Pointer to flow attributes
2361 * Pointer to error structure.
2364 * 0 on success, a negative errno value otherwise and rte_errno is set.
2367 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2368 const struct rte_flow_action *action,
2369 uint64_t action_flags,
2370 const struct rte_flow_attr *attr,
2371 struct rte_flow_error *error)
2373 struct mlx5_priv *priv = dev->data->dev_private;
2374 struct mlx5_dev_config *config = &priv->config;
2375 const struct rte_flow_action_mark *mark = action->conf;
2378 /* Fall back if no extended metadata register support. */
2379 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2380 return mlx5_flow_validate_action_mark(action, action_flags,
2382 /* Extensive metadata mode requires registers. */
2383 if (!mlx5_flow_ext_mreg_supported(dev))
2384 return rte_flow_error_set(error, ENOTSUP,
2385 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2386 "no metadata registers "
2387 "to support mark action");
2388 if (!priv->sh->dv_mark_mask)
2389 return rte_flow_error_set(error, ENOTSUP,
2390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391 "extended metadata register"
2392 " isn't available");
2393 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2396 MLX5_ASSERT(ret > 0);
2398 return rte_flow_error_set(error, EINVAL,
2399 RTE_FLOW_ERROR_TYPE_ACTION, action,
2400 "configuration cannot be null");
2401 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2402 return rte_flow_error_set(error, EINVAL,
2403 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2405 "mark id exceeds the limit");
2406 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2407 return rte_flow_error_set(error, EINVAL,
2408 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2409 "can't flag and mark in same flow");
2410 if (action_flags & MLX5_FLOW_ACTION_MARK)
2411 return rte_flow_error_set(error, EINVAL,
2412 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2413 "can't have 2 mark actions in same"
2419 * Validate SET_META action.
2422 * Pointer to the rte_eth_dev structure.
2424 * Pointer to the action structure.
2425 * @param[in] action_flags
2426 * Holds the actions detected until now.
2428 * Pointer to flow attributes
2430 * Pointer to error structure.
2433 * 0 on success, a negative errno value otherwise and rte_errno is set.
2436 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2437 const struct rte_flow_action *action,
2438 uint64_t action_flags __rte_unused,
2439 const struct rte_flow_attr *attr,
2440 struct rte_flow_error *error)
2442 const struct rte_flow_action_set_meta *conf;
2443 uint32_t nic_mask = UINT32_MAX;
2446 if (!mlx5_flow_ext_mreg_supported(dev))
2447 return rte_flow_error_set(error, ENOTSUP,
2448 RTE_FLOW_ERROR_TYPE_ACTION, action,
2449 "extended metadata register"
2450 " isn't supported");
2451 reg = flow_dv_get_metadata_reg(dev, attr, error);
2455 return rte_flow_error_set(error, ENOTSUP,
2456 RTE_FLOW_ERROR_TYPE_ACTION, action,
2457 "unavalable extended metadata register");
2458 if (reg != REG_A && reg != REG_B) {
2459 struct mlx5_priv *priv = dev->data->dev_private;
2461 nic_mask = priv->sh->dv_meta_mask;
2463 if (!(action->conf))
2464 return rte_flow_error_set(error, EINVAL,
2465 RTE_FLOW_ERROR_TYPE_ACTION, action,
2466 "configuration cannot be null");
2467 conf = (const struct rte_flow_action_set_meta *)action->conf;
2469 return rte_flow_error_set(error, EINVAL,
2470 RTE_FLOW_ERROR_TYPE_ACTION, action,
2471 "zero mask doesn't have any effect");
2472 if (conf->mask & ~nic_mask)
2473 return rte_flow_error_set(error, EINVAL,
2474 RTE_FLOW_ERROR_TYPE_ACTION, action,
2475 "meta data must be within reg C0");
2480 * Validate SET_TAG action.
2483 * Pointer to the rte_eth_dev structure.
2485 * Pointer to the action structure.
2486 * @param[in] action_flags
2487 * Holds the actions detected until now.
2489 * Pointer to flow attributes
2491 * Pointer to error structure.
2494 * 0 on success, a negative errno value otherwise and rte_errno is set.
2497 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2498 const struct rte_flow_action *action,
2499 uint64_t action_flags,
2500 const struct rte_flow_attr *attr,
2501 struct rte_flow_error *error)
2503 const struct rte_flow_action_set_tag *conf;
2504 const uint64_t terminal_action_flags =
2505 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2506 MLX5_FLOW_ACTION_RSS;
2509 if (!mlx5_flow_ext_mreg_supported(dev))
2510 return rte_flow_error_set(error, ENOTSUP,
2511 RTE_FLOW_ERROR_TYPE_ACTION, action,
2512 "extensive metadata register"
2513 " isn't supported");
2514 if (!(action->conf))
2515 return rte_flow_error_set(error, EINVAL,
2516 RTE_FLOW_ERROR_TYPE_ACTION, action,
2517 "configuration cannot be null");
2518 conf = (const struct rte_flow_action_set_tag *)action->conf;
2520 return rte_flow_error_set(error, EINVAL,
2521 RTE_FLOW_ERROR_TYPE_ACTION, action,
2522 "zero mask doesn't have any effect");
2523 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2526 if (!attr->transfer && attr->ingress &&
2527 (action_flags & terminal_action_flags))
2528 return rte_flow_error_set(error, EINVAL,
2529 RTE_FLOW_ERROR_TYPE_ACTION, action,
2530 "set_tag has no effect"
2531 " with terminal actions");
2536 * Validate count action.
2539 * Pointer to rte_eth_dev structure.
2541 * Pointer to error structure.
2544 * 0 on success, a negative errno value otherwise and rte_errno is set.
2547 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2548 struct rte_flow_error *error)
2550 struct mlx5_priv *priv = dev->data->dev_private;
2552 if (!priv->config.devx)
2554 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2558 return rte_flow_error_set
2560 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2562 "count action not supported");
2566 * Validate the L2 encap action.
2569 * Pointer to the rte_eth_dev structure.
2570 * @param[in] action_flags
2571 * Holds the actions detected until now.
2573 * Pointer to the action structure.
2575 * Pointer to flow attributes.
2577 * Pointer to error structure.
2580 * 0 on success, a negative errno value otherwise and rte_errno is set.
2583 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2584 uint64_t action_flags,
2585 const struct rte_flow_action *action,
2586 const struct rte_flow_attr *attr,
2587 struct rte_flow_error *error)
2589 const struct mlx5_priv *priv = dev->data->dev_private;
2591 if (!(action->conf))
2592 return rte_flow_error_set(error, EINVAL,
2593 RTE_FLOW_ERROR_TYPE_ACTION, action,
2594 "configuration cannot be null");
2595 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2596 return rte_flow_error_set(error, EINVAL,
2597 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2598 "can only have a single encap action "
2600 if (!attr->transfer && priv->representor)
2601 return rte_flow_error_set(error, ENOTSUP,
2602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2603 "encap action for VF representor "
2604 "not supported on NIC table");
2609 * Validate a decap action.
2612 * Pointer to the rte_eth_dev structure.
2613 * @param[in] action_flags
2614 * Holds the actions detected until now.
2616 * Pointer to the action structure.
2617 * @param[in] item_flags
2618 * Holds the items detected.
2620 * Pointer to flow attributes
2622 * Pointer to error structure.
2625 * 0 on success, a negative errno value otherwise and rte_errno is set.
2628 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2629 uint64_t action_flags,
2630 const struct rte_flow_action *action,
2631 const uint64_t item_flags,
2632 const struct rte_flow_attr *attr,
2633 struct rte_flow_error *error)
2635 const struct mlx5_priv *priv = dev->data->dev_private;
2637 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2638 !priv->config.decap_en)
2639 return rte_flow_error_set(error, ENOTSUP,
2640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2641 "decap is not enabled");
2642 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2643 return rte_flow_error_set(error, ENOTSUP,
2644 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2646 MLX5_FLOW_ACTION_DECAP ? "can only "
2647 "have a single decap action" : "decap "
2648 "after encap is not supported");
2649 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2650 return rte_flow_error_set(error, EINVAL,
2651 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2652 "can't have decap action after"
2655 return rte_flow_error_set(error, ENOTSUP,
2656 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2658 "decap action not supported for "
2660 if (!attr->transfer && priv->representor)
2661 return rte_flow_error_set(error, ENOTSUP,
2662 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2663 "decap action for VF representor "
2664 "not supported on NIC table");
2665 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2666 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2667 return rte_flow_error_set(error, ENOTSUP,
2668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2669 "VXLAN item should be present for VXLAN decap");
2673 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2676 * Validate the raw encap and decap actions.
2679 * Pointer to the rte_eth_dev structure.
2681 * Pointer to the decap action.
2683 * Pointer to the encap action.
2685 * Pointer to flow attributes
2686 * @param[in/out] action_flags
2687 * Holds the actions detected until now.
2688 * @param[out] actions_n
2689 * pointer to the number of actions counter.
2691 * Pointer to the action structure.
2692 * @param[in] item_flags
2693 * Holds the items detected.
2695 * Pointer to error structure.
2698 * 0 on success, a negative errno value otherwise and rte_errno is set.
2701 flow_dv_validate_action_raw_encap_decap
2702 (struct rte_eth_dev *dev,
2703 const struct rte_flow_action_raw_decap *decap,
2704 const struct rte_flow_action_raw_encap *encap,
2705 const struct rte_flow_attr *attr, uint64_t *action_flags,
2706 int *actions_n, const struct rte_flow_action *action,
2707 uint64_t item_flags, struct rte_flow_error *error)
2709 const struct mlx5_priv *priv = dev->data->dev_private;
2712 if (encap && (!encap->size || !encap->data))
2713 return rte_flow_error_set(error, EINVAL,
2714 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2715 "raw encap data cannot be empty");
2716 if (decap && encap) {
2717 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2718 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2721 else if (encap->size <=
2722 MLX5_ENCAPSULATION_DECISION_SIZE &&
2724 MLX5_ENCAPSULATION_DECISION_SIZE)
2727 else if (encap->size >
2728 MLX5_ENCAPSULATION_DECISION_SIZE &&
2730 MLX5_ENCAPSULATION_DECISION_SIZE)
2731 /* 2 L2 actions: encap and decap. */
2734 return rte_flow_error_set(error,
2736 RTE_FLOW_ERROR_TYPE_ACTION,
2737 NULL, "unsupported too small "
2738 "raw decap and too small raw "
2739 "encap combination");
2742 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2743 item_flags, attr, error);
2746 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2750 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2751 return rte_flow_error_set(error, ENOTSUP,
2752 RTE_FLOW_ERROR_TYPE_ACTION,
2754 "small raw encap size");
2755 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2756 return rte_flow_error_set(error, EINVAL,
2757 RTE_FLOW_ERROR_TYPE_ACTION,
2759 "more than one encap action");
2760 if (!attr->transfer && priv->representor)
2761 return rte_flow_error_set
2763 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2764 "encap action for VF representor "
2765 "not supported on NIC table");
2766 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2773 * Match encap_decap resource.
2776 * Pointer to the hash list.
2778 * Pointer to exist resource entry object.
2780 * Key of the new entry.
2782 * Pointer to new encap_decap resource.
2785 * 0 on matching, none-zero otherwise.
2788 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2789 struct mlx5_hlist_entry *entry,
2790 uint64_t key __rte_unused, void *cb_ctx)
2792 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2793 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2794 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2796 cache_resource = container_of(entry,
2797 struct mlx5_flow_dv_encap_decap_resource,
2799 if (resource->reformat_type == cache_resource->reformat_type &&
2800 resource->ft_type == cache_resource->ft_type &&
2801 resource->flags == cache_resource->flags &&
2802 resource->size == cache_resource->size &&
2803 !memcmp((const void *)resource->buf,
2804 (const void *)cache_resource->buf,
2811 * Allocate encap_decap resource.
2814 * Pointer to the hash list.
2816 * Pointer to exist resource entry object.
2818 * Pointer to new encap_decap resource.
2821 * 0 on matching, none-zero otherwise.
2823 struct mlx5_hlist_entry *
2824 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2825 uint64_t key __rte_unused,
2828 struct mlx5_dev_ctx_shared *sh = list->ctx;
2829 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2830 struct mlx5dv_dr_domain *domain;
2831 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2832 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2836 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2837 domain = sh->fdb_domain;
2838 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2839 domain = sh->rx_domain;
2841 domain = sh->tx_domain;
2842 /* Register new encap/decap resource. */
2843 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2845 if (!cache_resource) {
2846 rte_flow_error_set(ctx->error, ENOMEM,
2847 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2848 "cannot allocate resource memory");
2851 *cache_resource = *resource;
2852 cache_resource->idx = idx;
2853 ret = mlx5_flow_os_create_flow_action_packet_reformat
2854 (sh->ctx, domain, cache_resource,
2855 &cache_resource->action);
2857 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2858 rte_flow_error_set(ctx->error, ENOMEM,
2859 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2860 NULL, "cannot create action");
2864 return &cache_resource->entry;
2868 * Find existing encap/decap resource or create and register a new one.
2870 * @param[in, out] dev
2871 * Pointer to rte_eth_dev structure.
2872 * @param[in, out] resource
2873 * Pointer to encap/decap resource.
2874 * @parm[in, out] dev_flow
2875 * Pointer to the dev_flow.
2877 * pointer to error structure.
2880 * 0 on success otherwise -errno and errno is set.
2883 flow_dv_encap_decap_resource_register
2884 (struct rte_eth_dev *dev,
2885 struct mlx5_flow_dv_encap_decap_resource *resource,
2886 struct mlx5_flow *dev_flow,
2887 struct rte_flow_error *error)
2889 struct mlx5_priv *priv = dev->data->dev_private;
2890 struct mlx5_dev_ctx_shared *sh = priv->sh;
2891 struct mlx5_hlist_entry *entry;
2895 uint32_t refmt_type:8;
2897 * Header reformat actions can be shared between
2898 * non-root tables. One bit to indicate non-root
2902 uint32_t reserve:15;
2905 } encap_decap_key = {
2907 .ft_type = resource->ft_type,
2908 .refmt_type = resource->reformat_type,
2909 .is_root = !!dev_flow->dv.group,
2913 struct mlx5_flow_cb_ctx ctx = {
2919 resource->flags = dev_flow->dv.group ? 0 : 1;
2920 key64 = __rte_raw_cksum(&encap_decap_key.v32,
2921 sizeof(encap_decap_key.v32), 0);
2922 if (resource->reformat_type !=
2923 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2925 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2926 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2929 resource = container_of(entry, typeof(*resource), entry);
2930 dev_flow->dv.encap_decap = resource;
2931 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2936 * Find existing table jump resource or create and register a new one.
2938 * @param[in, out] dev
2939 * Pointer to rte_eth_dev structure.
2940 * @param[in, out] tbl
2941 * Pointer to flow table resource.
2942 * @parm[in, out] dev_flow
2943 * Pointer to the dev_flow.
2945 * pointer to error structure.
2948 * 0 on success otherwise -errno and errno is set.
2951 flow_dv_jump_tbl_resource_register
2952 (struct rte_eth_dev *dev __rte_unused,
2953 struct mlx5_flow_tbl_resource *tbl,
2954 struct mlx5_flow *dev_flow,
2955 struct rte_flow_error *error __rte_unused)
2957 struct mlx5_flow_tbl_data_entry *tbl_data =
2958 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2961 MLX5_ASSERT(tbl_data->jump.action);
2962 dev_flow->handle->rix_jump = tbl_data->idx;
2963 dev_flow->dv.jump = &tbl_data->jump;
2968 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
2969 struct mlx5_cache_entry *entry, void *cb_ctx)
2971 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2972 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2973 struct mlx5_flow_dv_port_id_action_resource *res =
2974 container_of(entry, typeof(*res), entry);
2976 return ref->port_id != res->port_id;
2979 struct mlx5_cache_entry *
2980 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
2981 struct mlx5_cache_entry *entry __rte_unused,
2984 struct mlx5_dev_ctx_shared *sh = list->ctx;
2985 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2986 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2987 struct mlx5_flow_dv_port_id_action_resource *cache;
2991 /* Register new port id action resource. */
2992 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
2994 rte_flow_error_set(ctx->error, ENOMEM,
2995 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2996 "cannot allocate port_id action cache memory");
3000 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3004 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3005 rte_flow_error_set(ctx->error, ENOMEM,
3006 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3007 "cannot create action");
3010 return &cache->entry;
3014 * Find existing table port ID resource or create and register a new one.
3016 * @param[in, out] dev
3017 * Pointer to rte_eth_dev structure.
3018 * @param[in, out] resource
3019 * Pointer to port ID action resource.
3020 * @parm[in, out] dev_flow
3021 * Pointer to the dev_flow.
3023 * pointer to error structure.
3026 * 0 on success otherwise -errno and errno is set.
3029 flow_dv_port_id_action_resource_register
3030 (struct rte_eth_dev *dev,
3031 struct mlx5_flow_dv_port_id_action_resource *resource,
3032 struct mlx5_flow *dev_flow,
3033 struct rte_flow_error *error)
3035 struct mlx5_priv *priv = dev->data->dev_private;
3036 struct mlx5_cache_entry *entry;
3037 struct mlx5_flow_dv_port_id_action_resource *cache;
3038 struct mlx5_flow_cb_ctx ctx = {
3043 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3046 cache = container_of(entry, typeof(*cache), entry);
3047 dev_flow->dv.port_id_action = cache;
3048 dev_flow->handle->rix_port_id_action = cache->idx;
3053 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3054 struct mlx5_cache_entry *entry, void *cb_ctx)
3056 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3057 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3058 struct mlx5_flow_dv_push_vlan_action_resource *res =
3059 container_of(entry, typeof(*res), entry);
3061 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3064 struct mlx5_cache_entry *
3065 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3066 struct mlx5_cache_entry *entry __rte_unused,
3069 struct mlx5_dev_ctx_shared *sh = list->ctx;
3070 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3071 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3072 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3073 struct mlx5dv_dr_domain *domain;
3077 /* Register new port id action resource. */
3078 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3080 rte_flow_error_set(ctx->error, ENOMEM,
3081 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3082 "cannot allocate push_vlan action cache memory");
3086 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3087 domain = sh->fdb_domain;
3088 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3089 domain = sh->rx_domain;
3091 domain = sh->tx_domain;
3092 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3095 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3096 rte_flow_error_set(ctx->error, ENOMEM,
3097 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3098 "cannot create push vlan action");
3101 return &cache->entry;
3105 * Find existing push vlan resource or create and register a new one.
3107 * @param [in, out] dev
3108 * Pointer to rte_eth_dev structure.
3109 * @param[in, out] resource
3110 * Pointer to port ID action resource.
3111 * @parm[in, out] dev_flow
3112 * Pointer to the dev_flow.
3114 * pointer to error structure.
3117 * 0 on success otherwise -errno and errno is set.
3120 flow_dv_push_vlan_action_resource_register
3121 (struct rte_eth_dev *dev,
3122 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3123 struct mlx5_flow *dev_flow,
3124 struct rte_flow_error *error)
3126 struct mlx5_priv *priv = dev->data->dev_private;
3127 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3128 struct mlx5_cache_entry *entry;
3129 struct mlx5_flow_cb_ctx ctx = {
3134 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3137 cache = container_of(entry, typeof(*cache), entry);
3139 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3140 dev_flow->dv.push_vlan_res = cache;
3145 * Get the size of specific rte_flow_item_type hdr size
3147 * @param[in] item_type
3148 * Tested rte_flow_item_type.
3151 * sizeof struct item_type, 0 if void or irrelevant.
3154 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3158 switch (item_type) {
3159 case RTE_FLOW_ITEM_TYPE_ETH:
3160 retval = sizeof(struct rte_ether_hdr);
3162 case RTE_FLOW_ITEM_TYPE_VLAN:
3163 retval = sizeof(struct rte_vlan_hdr);
3165 case RTE_FLOW_ITEM_TYPE_IPV4:
3166 retval = sizeof(struct rte_ipv4_hdr);
3168 case RTE_FLOW_ITEM_TYPE_IPV6:
3169 retval = sizeof(struct rte_ipv6_hdr);
3171 case RTE_FLOW_ITEM_TYPE_UDP:
3172 retval = sizeof(struct rte_udp_hdr);
3174 case RTE_FLOW_ITEM_TYPE_TCP:
3175 retval = sizeof(struct rte_tcp_hdr);
3177 case RTE_FLOW_ITEM_TYPE_VXLAN:
3178 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3179 retval = sizeof(struct rte_vxlan_hdr);
3181 case RTE_FLOW_ITEM_TYPE_GRE:
3182 case RTE_FLOW_ITEM_TYPE_NVGRE:
3183 retval = sizeof(struct rte_gre_hdr);
3185 case RTE_FLOW_ITEM_TYPE_MPLS:
3186 retval = sizeof(struct rte_mpls_hdr);
3188 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3196 #define MLX5_ENCAP_IPV4_VERSION 0x40
3197 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3198 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3199 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3200 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3201 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3202 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3205 * Convert the encap action data from list of rte_flow_item to raw buffer
3208 * Pointer to rte_flow_item objects list.
3210 * Pointer to the output buffer.
3212 * Pointer to the output buffer size.
3214 * Pointer to the error structure.
3217 * 0 on success, a negative errno value otherwise and rte_errno is set.
3220 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3221 size_t *size, struct rte_flow_error *error)
3223 struct rte_ether_hdr *eth = NULL;
3224 struct rte_vlan_hdr *vlan = NULL;
3225 struct rte_ipv4_hdr *ipv4 = NULL;
3226 struct rte_ipv6_hdr *ipv6 = NULL;
3227 struct rte_udp_hdr *udp = NULL;
3228 struct rte_vxlan_hdr *vxlan = NULL;
3229 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3230 struct rte_gre_hdr *gre = NULL;
3232 size_t temp_size = 0;
3235 return rte_flow_error_set(error, EINVAL,
3236 RTE_FLOW_ERROR_TYPE_ACTION,
3237 NULL, "invalid empty data");
3238 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3239 len = flow_dv_get_item_hdr_len(items->type);
3240 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3241 return rte_flow_error_set(error, EINVAL,
3242 RTE_FLOW_ERROR_TYPE_ACTION,
3243 (void *)items->type,
3244 "items total size is too big"
3245 " for encap action");
3246 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3247 switch (items->type) {
3248 case RTE_FLOW_ITEM_TYPE_ETH:
3249 eth = (struct rte_ether_hdr *)&buf[temp_size];
3251 case RTE_FLOW_ITEM_TYPE_VLAN:
3252 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3254 return rte_flow_error_set(error, EINVAL,
3255 RTE_FLOW_ERROR_TYPE_ACTION,
3256 (void *)items->type,
3257 "eth header not found");
3258 if (!eth->ether_type)
3259 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3261 case RTE_FLOW_ITEM_TYPE_IPV4:
3262 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3264 return rte_flow_error_set(error, EINVAL,
3265 RTE_FLOW_ERROR_TYPE_ACTION,
3266 (void *)items->type,
3267 "neither eth nor vlan"
3269 if (vlan && !vlan->eth_proto)
3270 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3271 else if (eth && !eth->ether_type)
3272 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3273 if (!ipv4->version_ihl)
3274 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3275 MLX5_ENCAP_IPV4_IHL_MIN;
3276 if (!ipv4->time_to_live)
3277 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3279 case RTE_FLOW_ITEM_TYPE_IPV6:
3280 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3282 return rte_flow_error_set(error, EINVAL,
3283 RTE_FLOW_ERROR_TYPE_ACTION,
3284 (void *)items->type,
3285 "neither eth nor vlan"
3287 if (vlan && !vlan->eth_proto)
3288 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3289 else if (eth && !eth->ether_type)
3290 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3291 if (!ipv6->vtc_flow)
3293 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3294 if (!ipv6->hop_limits)
3295 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3297 case RTE_FLOW_ITEM_TYPE_UDP:
3298 udp = (struct rte_udp_hdr *)&buf[temp_size];
3300 return rte_flow_error_set(error, EINVAL,
3301 RTE_FLOW_ERROR_TYPE_ACTION,
3302 (void *)items->type,
3303 "ip header not found");
3304 if (ipv4 && !ipv4->next_proto_id)
3305 ipv4->next_proto_id = IPPROTO_UDP;
3306 else if (ipv6 && !ipv6->proto)
3307 ipv6->proto = IPPROTO_UDP;
3309 case RTE_FLOW_ITEM_TYPE_VXLAN:
3310 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3312 return rte_flow_error_set(error, EINVAL,
3313 RTE_FLOW_ERROR_TYPE_ACTION,
3314 (void *)items->type,
3315 "udp header not found");
3317 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3318 if (!vxlan->vx_flags)
3320 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3322 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3323 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3325 return rte_flow_error_set(error, EINVAL,
3326 RTE_FLOW_ERROR_TYPE_ACTION,
3327 (void *)items->type,
3328 "udp header not found");
3329 if (!vxlan_gpe->proto)
3330 return rte_flow_error_set(error, EINVAL,
3331 RTE_FLOW_ERROR_TYPE_ACTION,
3332 (void *)items->type,
3333 "next protocol not found");
3336 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3337 if (!vxlan_gpe->vx_flags)
3338 vxlan_gpe->vx_flags =
3339 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3341 case RTE_FLOW_ITEM_TYPE_GRE:
3342 case RTE_FLOW_ITEM_TYPE_NVGRE:
3343 gre = (struct rte_gre_hdr *)&buf[temp_size];
3345 return rte_flow_error_set(error, EINVAL,
3346 RTE_FLOW_ERROR_TYPE_ACTION,
3347 (void *)items->type,
3348 "next protocol not found");
3350 return rte_flow_error_set(error, EINVAL,
3351 RTE_FLOW_ERROR_TYPE_ACTION,
3352 (void *)items->type,
3353 "ip header not found");
3354 if (ipv4 && !ipv4->next_proto_id)
3355 ipv4->next_proto_id = IPPROTO_GRE;
3356 else if (ipv6 && !ipv6->proto)
3357 ipv6->proto = IPPROTO_GRE;
3359 case RTE_FLOW_ITEM_TYPE_VOID:
3362 return rte_flow_error_set(error, EINVAL,
3363 RTE_FLOW_ERROR_TYPE_ACTION,
3364 (void *)items->type,
3365 "unsupported item type");
3375 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3377 struct rte_ether_hdr *eth = NULL;
3378 struct rte_vlan_hdr *vlan = NULL;
3379 struct rte_ipv6_hdr *ipv6 = NULL;
3380 struct rte_udp_hdr *udp = NULL;
3384 eth = (struct rte_ether_hdr *)data;
3385 next_hdr = (char *)(eth + 1);
3386 proto = RTE_BE16(eth->ether_type);
3389 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3390 vlan = (struct rte_vlan_hdr *)next_hdr;
3391 proto = RTE_BE16(vlan->eth_proto);
3392 next_hdr += sizeof(struct rte_vlan_hdr);
3395 /* HW calculates IPv4 csum. no need to proceed */
3396 if (proto == RTE_ETHER_TYPE_IPV4)
3399 /* non IPv4/IPv6 header. not supported */
3400 if (proto != RTE_ETHER_TYPE_IPV6) {
3401 return rte_flow_error_set(error, ENOTSUP,
3402 RTE_FLOW_ERROR_TYPE_ACTION,
3403 NULL, "Cannot offload non IPv4/IPv6");
3406 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3408 /* ignore non UDP */
3409 if (ipv6->proto != IPPROTO_UDP)
3412 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3413 udp->dgram_cksum = 0;
3419 * Convert L2 encap action to DV specification.
3422 * Pointer to rte_eth_dev structure.
3424 * Pointer to action structure.
3425 * @param[in, out] dev_flow
3426 * Pointer to the mlx5_flow.
3427 * @param[in] transfer
3428 * Mark if the flow is E-Switch flow.
3430 * Pointer to the error structure.
3433 * 0 on success, a negative errno value otherwise and rte_errno is set.
3436 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3437 const struct rte_flow_action *action,
3438 struct mlx5_flow *dev_flow,
3440 struct rte_flow_error *error)
3442 const struct rte_flow_item *encap_data;
3443 const struct rte_flow_action_raw_encap *raw_encap_data;
3444 struct mlx5_flow_dv_encap_decap_resource res = {
3446 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3447 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3448 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3451 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3453 (const struct rte_flow_action_raw_encap *)action->conf;
3454 res.size = raw_encap_data->size;
3455 memcpy(res.buf, raw_encap_data->data, res.size);
3457 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3459 ((const struct rte_flow_action_vxlan_encap *)
3460 action->conf)->definition;
3463 ((const struct rte_flow_action_nvgre_encap *)
3464 action->conf)->definition;
3465 if (flow_dv_convert_encap_data(encap_data, res.buf,
3469 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3471 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3472 return rte_flow_error_set(error, EINVAL,
3473 RTE_FLOW_ERROR_TYPE_ACTION,
3474 NULL, "can't create L2 encap action");
3479 * Convert L2 decap action to DV specification.
3482 * Pointer to rte_eth_dev structure.
3483 * @param[in, out] dev_flow
3484 * Pointer to the mlx5_flow.
3485 * @param[in] transfer
3486 * Mark if the flow is E-Switch flow.
3488 * Pointer to the error structure.
3491 * 0 on success, a negative errno value otherwise and rte_errno is set.
3494 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3495 struct mlx5_flow *dev_flow,
3497 struct rte_flow_error *error)
3499 struct mlx5_flow_dv_encap_decap_resource res = {
3502 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3503 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3504 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3507 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3508 return rte_flow_error_set(error, EINVAL,
3509 RTE_FLOW_ERROR_TYPE_ACTION,
3510 NULL, "can't create L2 decap action");
3515 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3518 * Pointer to rte_eth_dev structure.
3520 * Pointer to action structure.
3521 * @param[in, out] dev_flow
3522 * Pointer to the mlx5_flow.
3524 * Pointer to the flow attributes.
3526 * Pointer to the error structure.
3529 * 0 on success, a negative errno value otherwise and rte_errno is set.
3532 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3533 const struct rte_flow_action *action,
3534 struct mlx5_flow *dev_flow,
3535 const struct rte_flow_attr *attr,
3536 struct rte_flow_error *error)
3538 const struct rte_flow_action_raw_encap *encap_data;
3539 struct mlx5_flow_dv_encap_decap_resource res;
3541 memset(&res, 0, sizeof(res));
3542 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3543 res.size = encap_data->size;
3544 memcpy(res.buf, encap_data->data, res.size);
3545 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3546 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3547 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3549 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3551 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3552 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3553 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3554 return rte_flow_error_set(error, EINVAL,
3555 RTE_FLOW_ERROR_TYPE_ACTION,
3556 NULL, "can't create encap action");
3561 * Create action push VLAN.
3564 * Pointer to rte_eth_dev structure.
3566 * Pointer to the flow attributes.
3568 * Pointer to the vlan to push to the Ethernet header.
3569 * @param[in, out] dev_flow
3570 * Pointer to the mlx5_flow.
3572 * Pointer to the error structure.
3575 * 0 on success, a negative errno value otherwise and rte_errno is set.
3578 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3579 const struct rte_flow_attr *attr,
3580 const struct rte_vlan_hdr *vlan,
3581 struct mlx5_flow *dev_flow,
3582 struct rte_flow_error *error)
3584 struct mlx5_flow_dv_push_vlan_action_resource res;
3586 memset(&res, 0, sizeof(res));
3588 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3591 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3593 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3594 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3595 return flow_dv_push_vlan_action_resource_register
3596 (dev, &res, dev_flow, error);
3599 static int fdb_mirror;
3602 * Validate the modify-header actions.
3604 * @param[in] action_flags
3605 * Holds the actions detected until now.
3607 * Pointer to the modify action.
3609 * Pointer to error structure.
3612 * 0 on success, a negative errno value otherwise and rte_errno is set.
3615 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3616 const struct rte_flow_action *action,
3617 struct rte_flow_error *error)
3619 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3620 return rte_flow_error_set(error, EINVAL,
3621 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3622 NULL, "action configuration not set");
3623 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3624 return rte_flow_error_set(error, EINVAL,
3625 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3626 "can't have encap action before"
3628 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3629 return rte_flow_error_set(error, EINVAL,
3630 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3631 "can't support sample action before"
3632 " modify action for E-Switch"
3638 * Validate the modify-header MAC address actions.
3640 * @param[in] action_flags
3641 * Holds the actions detected until now.
3643 * Pointer to the modify action.
3644 * @param[in] item_flags
3645 * Holds the items detected.
3647 * Pointer to error structure.
3650 * 0 on success, a negative errno value otherwise and rte_errno is set.
3653 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3654 const struct rte_flow_action *action,
3655 const uint64_t item_flags,
3656 struct rte_flow_error *error)
3660 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3662 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3663 return rte_flow_error_set(error, EINVAL,
3664 RTE_FLOW_ERROR_TYPE_ACTION,
3666 "no L2 item in pattern");
3672 * Validate the modify-header IPv4 address actions.
3674 * @param[in] action_flags
3675 * Holds the actions detected until now.
3677 * Pointer to the modify action.
3678 * @param[in] item_flags
3679 * Holds the items detected.
3681 * Pointer to error structure.
3684 * 0 on success, a negative errno value otherwise and rte_errno is set.
3687 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3688 const struct rte_flow_action *action,
3689 const uint64_t item_flags,
3690 struct rte_flow_error *error)
3695 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3697 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3698 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3699 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3700 if (!(item_flags & layer))
3701 return rte_flow_error_set(error, EINVAL,
3702 RTE_FLOW_ERROR_TYPE_ACTION,
3704 "no ipv4 item in pattern");
3710 * Validate the modify-header IPv6 address actions.
3712 * @param[in] action_flags
3713 * Holds the actions detected until now.
3715 * Pointer to the modify action.
3716 * @param[in] item_flags
3717 * Holds the items detected.
3719 * Pointer to error structure.
3722 * 0 on success, a negative errno value otherwise and rte_errno is set.
3725 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3726 const struct rte_flow_action *action,
3727 const uint64_t item_flags,
3728 struct rte_flow_error *error)
3733 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3735 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3736 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3737 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3738 if (!(item_flags & layer))
3739 return rte_flow_error_set(error, EINVAL,
3740 RTE_FLOW_ERROR_TYPE_ACTION,
3742 "no ipv6 item in pattern");
3748 * Validate the modify-header TP actions.
3750 * @param[in] action_flags
3751 * Holds the actions detected until now.
3753 * Pointer to the modify action.
3754 * @param[in] item_flags
3755 * Holds the items detected.
3757 * Pointer to error structure.
3760 * 0 on success, a negative errno value otherwise and rte_errno is set.
3763 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3764 const struct rte_flow_action *action,
3765 const uint64_t item_flags,
3766 struct rte_flow_error *error)
3771 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3773 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3774 MLX5_FLOW_LAYER_INNER_L4 :
3775 MLX5_FLOW_LAYER_OUTER_L4;
3776 if (!(item_flags & layer))
3777 return rte_flow_error_set(error, EINVAL,
3778 RTE_FLOW_ERROR_TYPE_ACTION,
3779 NULL, "no transport layer "
3786 * Validate the modify-header actions of increment/decrement
3787 * TCP Sequence-number.
3789 * @param[in] action_flags
3790 * Holds the actions detected until now.
3792 * Pointer to the modify action.
3793 * @param[in] item_flags
3794 * Holds the items detected.
3796 * Pointer to error structure.
3799 * 0 on success, a negative errno value otherwise and rte_errno is set.
3802 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3803 const struct rte_flow_action *action,
3804 const uint64_t item_flags,
3805 struct rte_flow_error *error)
3810 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3812 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3813 MLX5_FLOW_LAYER_INNER_L4_TCP :
3814 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3815 if (!(item_flags & layer))
3816 return rte_flow_error_set(error, EINVAL,
3817 RTE_FLOW_ERROR_TYPE_ACTION,
3818 NULL, "no TCP item in"
3820 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3821 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3822 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3823 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3824 return rte_flow_error_set(error, EINVAL,
3825 RTE_FLOW_ERROR_TYPE_ACTION,
3827 "cannot decrease and increase"
3828 " TCP sequence number"
3829 " at the same time");
3835 * Validate the modify-header actions of increment/decrement
3836 * TCP Acknowledgment number.
3838 * @param[in] action_flags
3839 * Holds the actions detected until now.
3841 * Pointer to the modify action.
3842 * @param[in] item_flags
3843 * Holds the items detected.
3845 * Pointer to error structure.
3848 * 0 on success, a negative errno value otherwise and rte_errno is set.
3851 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3852 const struct rte_flow_action *action,
3853 const uint64_t item_flags,
3854 struct rte_flow_error *error)
3859 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3861 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3862 MLX5_FLOW_LAYER_INNER_L4_TCP :
3863 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3864 if (!(item_flags & layer))
3865 return rte_flow_error_set(error, EINVAL,
3866 RTE_FLOW_ERROR_TYPE_ACTION,
3867 NULL, "no TCP item in"
3869 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3870 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3871 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3872 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3873 return rte_flow_error_set(error, EINVAL,
3874 RTE_FLOW_ERROR_TYPE_ACTION,
3876 "cannot decrease and increase"
3877 " TCP acknowledgment number"
3878 " at the same time");
3884 * Validate the modify-header TTL actions.
3886 * @param[in] action_flags
3887 * Holds the actions detected until now.
3889 * Pointer to the modify action.
3890 * @param[in] item_flags
3891 * Holds the items detected.
3893 * Pointer to error structure.
3896 * 0 on success, a negative errno value otherwise and rte_errno is set.
3899 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3900 const struct rte_flow_action *action,
3901 const uint64_t item_flags,
3902 struct rte_flow_error *error)
3907 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3909 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3910 MLX5_FLOW_LAYER_INNER_L3 :
3911 MLX5_FLOW_LAYER_OUTER_L3;
3912 if (!(item_flags & layer))
3913 return rte_flow_error_set(error, EINVAL,
3914 RTE_FLOW_ERROR_TYPE_ACTION,
3916 "no IP protocol in pattern");
3922 * Validate jump action.
3925 * Pointer to the jump action.
3926 * @param[in] action_flags
3927 * Holds the actions detected until now.
3928 * @param[in] attributes
3929 * Pointer to flow attributes
3930 * @param[in] external
3931 * Action belongs to flow rule created by request external to PMD.
3933 * Pointer to error structure.
3936 * 0 on success, a negative errno value otherwise and rte_errno is set.
3939 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3940 const struct mlx5_flow_tunnel *tunnel,
3941 const struct rte_flow_action *action,
3942 uint64_t action_flags,
3943 const struct rte_flow_attr *attributes,
3944 bool external, struct rte_flow_error *error)
3946 uint32_t target_group, table;
3948 struct flow_grp_info grp_info = {
3949 .external = !!external,
3950 .transfer = !!attributes->transfer,
3954 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3955 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3956 return rte_flow_error_set(error, EINVAL,
3957 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3958 "can't have 2 fate actions in"
3960 if (action_flags & MLX5_FLOW_ACTION_METER)
3961 return rte_flow_error_set(error, ENOTSUP,
3962 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3963 "jump with meter not support");
3964 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3965 return rte_flow_error_set(error, EINVAL,
3966 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3967 "E-Switch mirroring can't support"
3968 " Sample action and jump action in"
3971 return rte_flow_error_set(error, EINVAL,
3972 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3973 NULL, "action configuration not set");
3975 ((const struct rte_flow_action_jump *)action->conf)->group;
3976 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3980 if (attributes->group == target_group &&
3981 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3982 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3983 return rte_flow_error_set(error, EINVAL,
3984 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3985 "target group must be other than"
3986 " the current flow group");
3991 * Validate the port_id action.
3994 * Pointer to rte_eth_dev structure.
3995 * @param[in] action_flags
3996 * Bit-fields that holds the actions detected until now.
3998 * Port_id RTE action structure.
4000 * Attributes of flow that includes this action.
4002 * Pointer to error structure.
4005 * 0 on success, a negative errno value otherwise and rte_errno is set.
4008 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4009 uint64_t action_flags,
4010 const struct rte_flow_action *action,
4011 const struct rte_flow_attr *attr,
4012 struct rte_flow_error *error)
4014 const struct rte_flow_action_port_id *port_id;
4015 struct mlx5_priv *act_priv;
4016 struct mlx5_priv *dev_priv;
4019 if (!attr->transfer)
4020 return rte_flow_error_set(error, ENOTSUP,
4021 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4023 "port id action is valid in transfer"
4025 if (!action || !action->conf)
4026 return rte_flow_error_set(error, ENOTSUP,
4027 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4029 "port id action parameters must be"
4031 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4032 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4033 return rte_flow_error_set(error, EINVAL,
4034 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4035 "can have only one fate actions in"
4037 dev_priv = mlx5_dev_to_eswitch_info(dev);
4039 return rte_flow_error_set(error, rte_errno,
4040 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4042 "failed to obtain E-Switch info");
4043 port_id = action->conf;
4044 port = port_id->original ? dev->data->port_id : port_id->id;
4045 act_priv = mlx5_port_to_eswitch_info(port, false);
4047 return rte_flow_error_set
4049 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4050 "failed to obtain E-Switch port id for port");
4051 if (act_priv->domain_id != dev_priv->domain_id)
4052 return rte_flow_error_set
4054 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4055 "port does not belong to"
4056 " E-Switch being configured");
4061 * Get the maximum number of modify header actions.
4064 * Pointer to rte_eth_dev structure.
4066 * Flags bits to check if root level.
4069 * Max number of modify header actions device can support.
4071 static inline unsigned int
4072 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4076 * There's no way to directly query the max capacity from FW.
4077 * The maximal value on root table should be assumed to be supported.
4079 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4080 return MLX5_MAX_MODIFY_NUM;
4082 return MLX5_ROOT_TBL_MODIFY_NUM;
4086 * Validate the meter action.
4089 * Pointer to rte_eth_dev structure.
4090 * @param[in] action_flags
4091 * Bit-fields that holds the actions detected until now.
4093 * Pointer to the meter action.
4095 * Attributes of flow that includes this action.
4097 * Pointer to error structure.
4100 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4103 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4104 uint64_t action_flags,
4105 const struct rte_flow_action *action,
4106 const struct rte_flow_attr *attr,
4107 struct rte_flow_error *error)
4109 struct mlx5_priv *priv = dev->data->dev_private;
4110 const struct rte_flow_action_meter *am = action->conf;
4111 struct mlx5_flow_meter *fm;
4114 return rte_flow_error_set(error, EINVAL,
4115 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4116 "meter action conf is NULL");
4118 if (action_flags & MLX5_FLOW_ACTION_METER)
4119 return rte_flow_error_set(error, ENOTSUP,
4120 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4121 "meter chaining not support");
4122 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4123 return rte_flow_error_set(error, ENOTSUP,
4124 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4125 "meter with jump not support");
4127 return rte_flow_error_set(error, ENOTSUP,
4128 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4130 "meter action not supported");
4131 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4133 return rte_flow_error_set(error, EINVAL,
4134 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4136 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4137 (!fm->ingress && !attr->ingress && attr->egress) ||
4138 (!fm->egress && !attr->egress && attr->ingress))))
4139 return rte_flow_error_set(error, EINVAL,
4140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4141 "Flow attributes are either invalid "
4142 "or have a conflict with current "
4143 "meter attributes");
4148 * Validate the age action.
4150 * @param[in] action_flags
4151 * Holds the actions detected until now.
4153 * Pointer to the age action.
4155 * Pointer to the Ethernet device structure.
4157 * Pointer to error structure.
4160 * 0 on success, a negative errno value otherwise and rte_errno is set.
4163 flow_dv_validate_action_age(uint64_t action_flags,
4164 const struct rte_flow_action *action,
4165 struct rte_eth_dev *dev,
4166 struct rte_flow_error *error)
4168 struct mlx5_priv *priv = dev->data->dev_private;
4169 const struct rte_flow_action_age *age = action->conf;
4171 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4172 !priv->sh->aso_age_mng))
4173 return rte_flow_error_set(error, ENOTSUP,
4174 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4176 "age action not supported");
4177 if (!(action->conf))
4178 return rte_flow_error_set(error, EINVAL,
4179 RTE_FLOW_ERROR_TYPE_ACTION, action,
4180 "configuration cannot be null");
4181 if (!(age->timeout))
4182 return rte_flow_error_set(error, EINVAL,
4183 RTE_FLOW_ERROR_TYPE_ACTION, action,
4184 "invalid timeout value 0");
4185 if (action_flags & MLX5_FLOW_ACTION_AGE)
4186 return rte_flow_error_set(error, EINVAL,
4187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4188 "duplicate age actions set");
4193 * Validate the modify-header IPv4 DSCP actions.
4195 * @param[in] action_flags
4196 * Holds the actions detected until now.
4198 * Pointer to the modify action.
4199 * @param[in] item_flags
4200 * Holds the items detected.
4202 * Pointer to error structure.
4205 * 0 on success, a negative errno value otherwise and rte_errno is set.
4208 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4209 const struct rte_flow_action *action,
4210 const uint64_t item_flags,
4211 struct rte_flow_error *error)
4215 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4217 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4218 return rte_flow_error_set(error, EINVAL,
4219 RTE_FLOW_ERROR_TYPE_ACTION,
4221 "no ipv4 item in pattern");
4227 * Validate the modify-header IPv6 DSCP actions.
4229 * @param[in] action_flags
4230 * Holds the actions detected until now.
4232 * Pointer to the modify action.
4233 * @param[in] item_flags
4234 * Holds the items detected.
4236 * Pointer to error structure.
4239 * 0 on success, a negative errno value otherwise and rte_errno is set.
4242 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4243 const struct rte_flow_action *action,
4244 const uint64_t item_flags,
4245 struct rte_flow_error *error)
4249 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4251 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4252 return rte_flow_error_set(error, EINVAL,
4253 RTE_FLOW_ERROR_TYPE_ACTION,
4255 "no ipv6 item in pattern");
4261 * Match modify-header resource.
4264 * Pointer to the hash list.
4266 * Pointer to exist resource entry object.
4268 * Key of the new entry.
4270 * Pointer to new modify-header resource.
4273 * 0 on matching, non-zero otherwise.
4276 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4277 struct mlx5_hlist_entry *entry,
4278 uint64_t key __rte_unused, void *cb_ctx)
4280 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4281 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4282 struct mlx5_flow_dv_modify_hdr_resource *resource =
4283 container_of(entry, typeof(*resource), entry);
4284 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4286 key_len += ref->actions_num * sizeof(ref->actions[0]);
4287 return ref->actions_num != resource->actions_num ||
4288 memcmp(&ref->ft_type, &resource->ft_type, key_len);
4291 struct mlx5_hlist_entry *
4292 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4295 struct mlx5_dev_ctx_shared *sh = list->ctx;
4296 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4297 struct mlx5dv_dr_domain *ns;
4298 struct mlx5_flow_dv_modify_hdr_resource *entry;
4299 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4301 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4302 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4304 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4307 rte_flow_error_set(ctx->error, ENOMEM,
4308 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4309 "cannot allocate resource memory");
4312 rte_memcpy(&entry->ft_type,
4313 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4314 key_len + data_len);
4315 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4316 ns = sh->fdb_domain;
4317 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4321 ret = mlx5_flow_os_create_flow_action_modify_header
4322 (sh->ctx, ns, entry,
4323 data_len, &entry->action);
4326 rte_flow_error_set(ctx->error, ENOMEM,
4327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4328 NULL, "cannot create modification action");
4331 return &entry->entry;
4335 * Validate the sample action.
4337 * @param[in] action_flags
4338 * Holds the actions detected until now.
4340 * Pointer to the sample action.
4342 * Pointer to the Ethernet device structure.
4344 * Attributes of flow that includes this action.
4345 * @param[in] item_flags
4346 * Holds the items detected.
4348 * Pointer to error structure.
4351 * 0 on success, a negative errno value otherwise and rte_errno is set.
4354 flow_dv_validate_action_sample(uint64_t action_flags,
4355 const struct rte_flow_action *action,
4356 struct rte_eth_dev *dev,
4357 const struct rte_flow_attr *attr,
4358 const uint64_t item_flags,
4359 struct rte_flow_error *error)
4361 struct mlx5_priv *priv = dev->data->dev_private;
4362 struct mlx5_dev_config *dev_conf = &priv->config;
4363 const struct rte_flow_action_sample *sample = action->conf;
4364 const struct rte_flow_action *act;
4365 uint64_t sub_action_flags = 0;
4366 uint16_t queue_index = 0xFFFF;
4372 return rte_flow_error_set(error, EINVAL,
4373 RTE_FLOW_ERROR_TYPE_ACTION, action,
4374 "configuration cannot be NULL");
4375 if (sample->ratio == 0)
4376 return rte_flow_error_set(error, EINVAL,
4377 RTE_FLOW_ERROR_TYPE_ACTION, action,
4378 "ratio value starts from 1");
4379 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4380 return rte_flow_error_set(error, ENOTSUP,
4381 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4383 "sample action not supported");
4384 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4385 return rte_flow_error_set(error, EINVAL,
4386 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4387 "Multiple sample actions not "
4389 if (action_flags & MLX5_FLOW_ACTION_METER)
4390 return rte_flow_error_set(error, EINVAL,
4391 RTE_FLOW_ERROR_TYPE_ACTION, action,
4392 "wrong action order, meter should "
4393 "be after sample action");
4394 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4395 return rte_flow_error_set(error, EINVAL,
4396 RTE_FLOW_ERROR_TYPE_ACTION, action,
4397 "wrong action order, jump should "
4398 "be after sample action");
4399 act = sample->actions;
4400 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4401 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4402 return rte_flow_error_set(error, ENOTSUP,
4403 RTE_FLOW_ERROR_TYPE_ACTION,
4404 act, "too many actions");
4405 switch (act->type) {
4406 case RTE_FLOW_ACTION_TYPE_QUEUE:
4407 ret = mlx5_flow_validate_action_queue(act,
4413 queue_index = ((const struct rte_flow_action_queue *)
4414 (act->conf))->index;
4415 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4418 case RTE_FLOW_ACTION_TYPE_MARK:
4419 ret = flow_dv_validate_action_mark(dev, act,
4424 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4425 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4426 MLX5_FLOW_ACTION_MARK_EXT;
4428 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4431 case RTE_FLOW_ACTION_TYPE_COUNT:
4432 ret = flow_dv_validate_action_count(dev, error);
4435 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4438 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4439 ret = flow_dv_validate_action_port_id(dev,
4446 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4449 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4450 ret = flow_dv_validate_action_raw_encap_decap
4451 (dev, NULL, act->conf, attr, &sub_action_flags,
4452 &actions_n, action, item_flags, error);
4458 return rte_flow_error_set(error, ENOTSUP,
4459 RTE_FLOW_ERROR_TYPE_ACTION,
4461 "Doesn't support optional "
4465 if (attr->ingress && !attr->transfer) {
4466 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4467 return rte_flow_error_set(error, EINVAL,
4468 RTE_FLOW_ERROR_TYPE_ACTION,
4470 "Ingress must has a dest "
4471 "QUEUE for Sample");
4472 } else if (attr->egress && !attr->transfer) {
4473 return rte_flow_error_set(error, ENOTSUP,
4474 RTE_FLOW_ERROR_TYPE_ACTION,
4476 "Sample Only support Ingress "
4478 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4479 MLX5_ASSERT(attr->transfer);
4480 if (sample->ratio > 1)
4481 return rte_flow_error_set(error, ENOTSUP,
4482 RTE_FLOW_ERROR_TYPE_ACTION,
4484 "E-Switch doesn't support "
4485 "any optional action "
4488 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4489 return rte_flow_error_set(error, ENOTSUP,
4490 RTE_FLOW_ERROR_TYPE_ACTION,
4492 "unsupported action QUEUE");
4493 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4494 return rte_flow_error_set(error, EINVAL,
4495 RTE_FLOW_ERROR_TYPE_ACTION,
4497 "E-Switch must has a dest "
4498 "port for mirroring");
4500 /* Continue validation for Xcap actions.*/
4501 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4502 (queue_index == 0xFFFF ||
4503 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4504 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4505 MLX5_FLOW_XCAP_ACTIONS)
4506 return rte_flow_error_set(error, ENOTSUP,
4507 RTE_FLOW_ERROR_TYPE_ACTION,
4508 NULL, "encap and decap "
4509 "combination aren't "
4511 if (!attr->transfer && attr->ingress && (sub_action_flags &
4512 MLX5_FLOW_ACTION_ENCAP))
4513 return rte_flow_error_set(error, ENOTSUP,
4514 RTE_FLOW_ERROR_TYPE_ACTION,
4515 NULL, "encap is not supported"
4516 " for ingress traffic");
4522 * Find existing modify-header resource or create and register a new one.
4524 * @param dev[in, out]
4525 * Pointer to rte_eth_dev structure.
4526 * @param[in, out] resource
4527 * Pointer to modify-header resource.
4528 * @parm[in, out] dev_flow
4529 * Pointer to the dev_flow.
4531 * pointer to error structure.
4534 * 0 on success otherwise -errno and errno is set.
4537 flow_dv_modify_hdr_resource_register
4538 (struct rte_eth_dev *dev,
4539 struct mlx5_flow_dv_modify_hdr_resource *resource,
4540 struct mlx5_flow *dev_flow,
4541 struct rte_flow_error *error)
4543 struct mlx5_priv *priv = dev->data->dev_private;
4544 struct mlx5_dev_ctx_shared *sh = priv->sh;
4545 uint32_t key_len = sizeof(*resource) -
4546 offsetof(typeof(*resource), ft_type) +
4547 resource->actions_num * sizeof(resource->actions[0]);
4548 struct mlx5_hlist_entry *entry;
4549 struct mlx5_flow_cb_ctx ctx = {
4555 resource->flags = dev_flow->dv.group ? 0 :
4556 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4557 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4559 return rte_flow_error_set(error, EOVERFLOW,
4560 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4561 "too many modify header items");
4562 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4563 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4566 resource = container_of(entry, typeof(*resource), entry);
4567 dev_flow->handle->dvh.modify_hdr = resource;
4572 * Get DV flow counter by index.
4575 * Pointer to the Ethernet device structure.
4577 * mlx5 flow counter index in the container.
4579 * mlx5 flow counter pool in the container,
4582 * Pointer to the counter, NULL otherwise.
4584 static struct mlx5_flow_counter *
4585 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4587 struct mlx5_flow_counter_pool **ppool)
4589 struct mlx5_priv *priv = dev->data->dev_private;
4590 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4591 struct mlx5_flow_counter_pool *pool;
4593 /* Decrease to original index and clear shared bit. */
4594 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4595 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4596 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4600 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4604 * Check the devx counter belongs to the pool.
4607 * Pointer to the counter pool.
4609 * The counter devx ID.
4612 * True if counter belongs to the pool, false otherwise.
4615 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4617 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4618 MLX5_COUNTERS_PER_POOL;
4620 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4626 * Get a pool by devx counter ID.
4629 * Pointer to the counter management.
4631 * The counter devx ID.
4634 * The counter pool pointer if exists, NULL otherwise,
4636 static struct mlx5_flow_counter_pool *
4637 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4640 struct mlx5_flow_counter_pool *pool = NULL;
4642 rte_spinlock_lock(&cmng->pool_update_sl);
4643 /* Check last used pool. */
4644 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4645 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4646 pool = cmng->pools[cmng->last_pool_idx];
4649 /* ID out of range means no suitable pool in the container. */
4650 if (id > cmng->max_id || id < cmng->min_id)
4653 * Find the pool from the end of the container, since mostly counter
4654 * ID is sequence increasing, and the last pool should be the needed
4659 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4661 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4667 rte_spinlock_unlock(&cmng->pool_update_sl);
4672 * Resize a counter container.
4675 * Pointer to the Ethernet device structure.
4678 * 0 on success, otherwise negative errno value and rte_errno is set.
4681 flow_dv_container_resize(struct rte_eth_dev *dev)
4683 struct mlx5_priv *priv = dev->data->dev_private;
4684 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4685 void *old_pools = cmng->pools;
4686 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4687 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4688 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4695 memcpy(pools, old_pools, cmng->n *
4696 sizeof(struct mlx5_flow_counter_pool *));
4698 cmng->pools = pools;
4700 mlx5_free(old_pools);
4705 * Query a devx flow counter.
4708 * Pointer to the Ethernet device structure.
4710 * Index to the flow counter.
4712 * The statistics value of packets.
4714 * The statistics value of bytes.
4717 * 0 on success, otherwise a negative errno value and rte_errno is set.
4720 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4723 struct mlx5_priv *priv = dev->data->dev_private;
4724 struct mlx5_flow_counter_pool *pool = NULL;
4725 struct mlx5_flow_counter *cnt;
4728 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4730 if (priv->sh->cmng.counter_fallback)
4731 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4732 0, pkts, bytes, 0, NULL, NULL, 0);
4733 rte_spinlock_lock(&pool->sl);
4738 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4739 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4740 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4742 rte_spinlock_unlock(&pool->sl);
4747 * Create and initialize a new counter pool.
4750 * Pointer to the Ethernet device structure.
4752 * The devX counter handle.
4754 * Whether the pool is for counter that was allocated for aging.
4755 * @param[in/out] cont_cur
4756 * Pointer to the container pointer, it will be update in pool resize.
4759 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4761 static struct mlx5_flow_counter_pool *
4762 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4765 struct mlx5_priv *priv = dev->data->dev_private;
4766 struct mlx5_flow_counter_pool *pool;
4767 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4768 bool fallback = priv->sh->cmng.counter_fallback;
4769 uint32_t size = sizeof(*pool);
4771 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4772 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4773 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4779 pool->is_aged = !!age;
4780 pool->query_gen = 0;
4781 pool->min_dcs = dcs;
4782 rte_spinlock_init(&pool->sl);
4783 rte_spinlock_init(&pool->csl);
4784 TAILQ_INIT(&pool->counters[0]);
4785 TAILQ_INIT(&pool->counters[1]);
4786 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4787 rte_spinlock_lock(&cmng->pool_update_sl);
4788 pool->index = cmng->n_valid;
4789 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4791 rte_spinlock_unlock(&cmng->pool_update_sl);
4794 cmng->pools[pool->index] = pool;
4796 if (unlikely(fallback)) {
4797 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4799 if (base < cmng->min_id)
4800 cmng->min_id = base;
4801 if (base > cmng->max_id)
4802 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4803 cmng->last_pool_idx = pool->index;
4805 rte_spinlock_unlock(&cmng->pool_update_sl);
4810 * Prepare a new counter and/or a new counter pool.
4813 * Pointer to the Ethernet device structure.
4814 * @param[out] cnt_free
4815 * Where to put the pointer of a new counter.
4817 * Whether the pool is for counter that was allocated for aging.
4820 * The counter pool pointer and @p cnt_free is set on success,
4821 * NULL otherwise and rte_errno is set.
4823 static struct mlx5_flow_counter_pool *
4824 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4825 struct mlx5_flow_counter **cnt_free,
4828 struct mlx5_priv *priv = dev->data->dev_private;
4829 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4830 struct mlx5_flow_counter_pool *pool;
4831 struct mlx5_counters tmp_tq;
4832 struct mlx5_devx_obj *dcs = NULL;
4833 struct mlx5_flow_counter *cnt;
4834 enum mlx5_counter_type cnt_type =
4835 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4836 bool fallback = priv->sh->cmng.counter_fallback;
4840 /* bulk_bitmap must be 0 for single counter allocation. */
4841 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4844 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4846 pool = flow_dv_pool_create(dev, dcs, age);
4848 mlx5_devx_cmd_destroy(dcs);
4852 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4853 cnt = MLX5_POOL_GET_CNT(pool, i);
4855 cnt->dcs_when_free = dcs;
4859 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4861 rte_errno = ENODATA;
4864 pool = flow_dv_pool_create(dev, dcs, age);
4866 mlx5_devx_cmd_destroy(dcs);
4869 TAILQ_INIT(&tmp_tq);
4870 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4871 cnt = MLX5_POOL_GET_CNT(pool, i);
4873 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4875 rte_spinlock_lock(&cmng->csl[cnt_type]);
4876 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4877 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4878 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4879 (*cnt_free)->pool = pool;
4884 * Allocate a flow counter.
4887 * Pointer to the Ethernet device structure.
4889 * Whether the counter was allocated for aging.
4892 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4895 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4897 struct mlx5_priv *priv = dev->data->dev_private;
4898 struct mlx5_flow_counter_pool *pool = NULL;
4899 struct mlx5_flow_counter *cnt_free = NULL;
4900 bool fallback = priv->sh->cmng.counter_fallback;
4901 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4902 enum mlx5_counter_type cnt_type =
4903 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4906 if (!priv->config.devx) {
4907 rte_errno = ENOTSUP;
4910 /* Get free counters from container. */
4911 rte_spinlock_lock(&cmng->csl[cnt_type]);
4912 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4914 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4915 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4916 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4918 pool = cnt_free->pool;
4920 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4921 /* Create a DV counter action only in the first time usage. */
4922 if (!cnt_free->action) {
4924 struct mlx5_devx_obj *dcs;
4928 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4929 dcs = pool->min_dcs;
4932 dcs = cnt_free->dcs_when_free;
4934 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4941 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4942 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4943 /* Update the counter reset values. */
4944 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4947 if (!fallback && !priv->sh->cmng.query_thread_on)
4948 /* Start the asynchronous batch query by the host thread. */
4949 mlx5_set_query_alarm(priv->sh);
4953 cnt_free->pool = pool;
4955 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4956 rte_spinlock_lock(&cmng->csl[cnt_type]);
4957 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4958 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4964 * Allocate a shared flow counter.
4967 * Pointer to the shared counter configuration.
4969 * Pointer to save the allocated counter index.
4972 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4976 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4978 struct mlx5_shared_counter_conf *conf = ctx;
4979 struct rte_eth_dev *dev = conf->dev;
4980 struct mlx5_flow_counter *cnt;
4982 data->dword = flow_dv_counter_alloc(dev, 0);
4983 data->dword |= MLX5_CNT_SHARED_OFFSET;
4984 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4985 cnt->shared_info.id = conf->id;
4990 * Get a shared flow counter.
4993 * Pointer to the Ethernet device structure.
4995 * Counter identifier.
4998 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5001 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5003 struct mlx5_priv *priv = dev->data->dev_private;
5004 struct mlx5_shared_counter_conf conf = {
5008 union mlx5_l3t_data data = {
5012 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5013 flow_dv_counter_alloc_shared_cb, &conf);
5018 * Get age param from counter index.
5021 * Pointer to the Ethernet device structure.
5022 * @param[in] counter
5023 * Index to the counter handler.
5026 * The aging parameter specified for the counter index.
5028 static struct mlx5_age_param*
5029 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5032 struct mlx5_flow_counter *cnt;
5033 struct mlx5_flow_counter_pool *pool = NULL;
5035 flow_dv_counter_get_by_idx(dev, counter, &pool);
5036 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5037 cnt = MLX5_POOL_GET_CNT(pool, counter);
5038 return MLX5_CNT_TO_AGE(cnt);
5042 * Remove a flow counter from aged counter list.
5045 * Pointer to the Ethernet device structure.
5046 * @param[in] counter
5047 * Index to the counter handler.
5049 * Pointer to the counter handler.
5052 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5053 uint32_t counter, struct mlx5_flow_counter *cnt)
5055 struct mlx5_age_info *age_info;
5056 struct mlx5_age_param *age_param;
5057 struct mlx5_priv *priv = dev->data->dev_private;
5058 uint16_t expected = AGE_CANDIDATE;
5060 age_info = GET_PORT_AGE_INFO(priv);
5061 age_param = flow_dv_counter_idx_get_age(dev, counter);
5062 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5063 AGE_FREE, false, __ATOMIC_RELAXED,
5064 __ATOMIC_RELAXED)) {
5066 * We need the lock even it is age timeout,
5067 * since counter may still in process.
5069 rte_spinlock_lock(&age_info->aged_sl);
5070 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5071 rte_spinlock_unlock(&age_info->aged_sl);
5072 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5077 * Release a flow counter.
5080 * Pointer to the Ethernet device structure.
5081 * @param[in] counter
5082 * Index to the counter handler.
5085 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5087 struct mlx5_priv *priv = dev->data->dev_private;
5088 struct mlx5_flow_counter_pool *pool = NULL;
5089 struct mlx5_flow_counter *cnt;
5090 enum mlx5_counter_type cnt_type;
5094 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5096 if (IS_SHARED_CNT(counter) &&
5097 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5100 flow_dv_counter_remove_from_age(dev, counter, cnt);
5103 * Put the counter back to list to be updated in none fallback mode.
5104 * Currently, we are using two list alternately, while one is in query,
5105 * add the freed counter to the other list based on the pool query_gen
5106 * value. After query finishes, add counter the list to the global
5107 * container counter list. The list changes while query starts. In
5108 * this case, lock will not be needed as query callback and release
5109 * function both operate with the different list.
5112 if (!priv->sh->cmng.counter_fallback) {
5113 rte_spinlock_lock(&pool->csl);
5114 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5115 rte_spinlock_unlock(&pool->csl);
5117 cnt->dcs_when_free = cnt->dcs_when_active;
5118 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5119 MLX5_COUNTER_TYPE_ORIGIN;
5120 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5121 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5123 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5128 * Verify the @p attributes will be correctly understood by the NIC and store
5129 * them in the @p flow if everything is correct.
5132 * Pointer to dev struct.
5133 * @param[in] attributes
5134 * Pointer to flow attributes
5135 * @param[in] external
5136 * This flow rule is created by request external to PMD.
5138 * Pointer to error structure.
5141 * - 0 on success and non root table.
5142 * - 1 on success and root table.
5143 * - a negative errno value otherwise and rte_errno is set.
5146 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5147 const struct mlx5_flow_tunnel *tunnel,
5148 const struct rte_flow_attr *attributes,
5149 const struct flow_grp_info *grp_info,
5150 struct rte_flow_error *error)
5152 struct mlx5_priv *priv = dev->data->dev_private;
5153 uint32_t priority_max = priv->config.flow_prio - 1;
5156 #ifndef HAVE_MLX5DV_DR
5157 RTE_SET_USED(tunnel);
5158 RTE_SET_USED(grp_info);
5159 if (attributes->group)
5160 return rte_flow_error_set(error, ENOTSUP,
5161 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5163 "groups are not supported");
5167 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5172 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5174 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5175 attributes->priority >= priority_max)
5176 return rte_flow_error_set(error, ENOTSUP,
5177 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5179 "priority out of range");
5180 if (attributes->transfer) {
5181 if (!priv->config.dv_esw_en)
5182 return rte_flow_error_set
5184 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5185 "E-Switch dr is not supported");
5186 if (!(priv->representor || priv->master))
5187 return rte_flow_error_set
5188 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5189 NULL, "E-Switch configuration can only be"
5190 " done by a master or a representor device");
5191 if (attributes->egress)
5192 return rte_flow_error_set
5194 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5195 "egress is not supported");
5197 if (!(attributes->egress ^ attributes->ingress))
5198 return rte_flow_error_set(error, ENOTSUP,
5199 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5200 "must specify exactly one of "
5201 "ingress or egress");
5206 * Internal validation function. For validating both actions and items.
5209 * Pointer to the rte_eth_dev structure.
5211 * Pointer to the flow attributes.
5213 * Pointer to the list of items.
5214 * @param[in] actions
5215 * Pointer to the list of actions.
5216 * @param[in] external
5217 * This flow rule is created by request external to PMD.
5218 * @param[in] hairpin
5219 * Number of hairpin TX actions, 0 means classic flow.
5221 * Pointer to the error structure.
5224 * 0 on success, a negative errno value otherwise and rte_errno is set.
5227 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5228 const struct rte_flow_item items[],
5229 const struct rte_flow_action actions[],
5230 bool external, int hairpin, struct rte_flow_error *error)
5233 uint64_t action_flags = 0;
5234 uint64_t item_flags = 0;
5235 uint64_t last_item = 0;
5236 uint8_t next_protocol = 0xff;
5237 uint16_t ether_type = 0;
5239 uint8_t item_ipv6_proto = 0;
5240 const struct rte_flow_item *gre_item = NULL;
5241 const struct rte_flow_action_raw_decap *decap;
5242 const struct rte_flow_action_raw_encap *encap;
5243 const struct rte_flow_action_rss *rss;
5244 const struct rte_flow_item_tcp nic_tcp_mask = {
5247 .src_port = RTE_BE16(UINT16_MAX),
5248 .dst_port = RTE_BE16(UINT16_MAX),
5251 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5254 "\xff\xff\xff\xff\xff\xff\xff\xff"
5255 "\xff\xff\xff\xff\xff\xff\xff\xff",
5257 "\xff\xff\xff\xff\xff\xff\xff\xff"
5258 "\xff\xff\xff\xff\xff\xff\xff\xff",
5259 .vtc_flow = RTE_BE32(0xffffffff),
5265 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5269 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5273 .dummy[0] = 0xffffffff,
5276 struct mlx5_priv *priv = dev->data->dev_private;
5277 struct mlx5_dev_config *dev_conf = &priv->config;
5278 uint16_t queue_index = 0xFFFF;
5279 const struct rte_flow_item_vlan *vlan_m = NULL;
5280 int16_t rw_act_num = 0;
5282 const struct mlx5_flow_tunnel *tunnel;
5283 struct flow_grp_info grp_info = {
5284 .external = !!external,
5285 .transfer = !!attr->transfer,
5286 .fdb_def_rule = !!priv->fdb_def_rule,
5288 const struct rte_eth_hairpin_conf *conf;
5292 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5293 tunnel = flow_items_to_tunnel(items);
5294 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5295 MLX5_FLOW_ACTION_DECAP;
5296 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5297 tunnel = flow_actions_to_tunnel(actions);
5298 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5302 if (tunnel && priv->representor)
5303 return rte_flow_error_set(error, ENOTSUP,
5304 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5305 "decap not supported "
5306 "for VF representor");
5307 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5308 (dev, tunnel, attr, items, actions);
5309 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5312 is_root = (uint64_t)ret;
5313 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5314 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5315 int type = items->type;
5317 if (!mlx5_flow_os_item_supported(type))
5318 return rte_flow_error_set(error, ENOTSUP,
5319 RTE_FLOW_ERROR_TYPE_ITEM,
5320 NULL, "item not supported");
5322 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5323 if (items[0].type != (typeof(items[0].type))
5324 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5325 return rte_flow_error_set
5327 RTE_FLOW_ERROR_TYPE_ITEM,
5328 NULL, "MLX5 private items "
5329 "must be the first");
5331 case RTE_FLOW_ITEM_TYPE_VOID:
5333 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5334 ret = flow_dv_validate_item_port_id
5335 (dev, items, attr, item_flags, error);
5338 last_item = MLX5_FLOW_ITEM_PORT_ID;
5340 case RTE_FLOW_ITEM_TYPE_ETH:
5341 ret = mlx5_flow_validate_item_eth(items, item_flags,
5345 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5346 MLX5_FLOW_LAYER_OUTER_L2;
5347 if (items->mask != NULL && items->spec != NULL) {
5349 ((const struct rte_flow_item_eth *)
5352 ((const struct rte_flow_item_eth *)
5354 ether_type = rte_be_to_cpu_16(ether_type);
5359 case RTE_FLOW_ITEM_TYPE_VLAN:
5360 ret = flow_dv_validate_item_vlan(items, item_flags,
5364 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5365 MLX5_FLOW_LAYER_OUTER_VLAN;
5366 if (items->mask != NULL && items->spec != NULL) {
5368 ((const struct rte_flow_item_vlan *)
5369 items->spec)->inner_type;
5371 ((const struct rte_flow_item_vlan *)
5372 items->mask)->inner_type;
5373 ether_type = rte_be_to_cpu_16(ether_type);
5377 /* Store outer VLAN mask for of_push_vlan action. */
5379 vlan_m = items->mask;
5381 case RTE_FLOW_ITEM_TYPE_IPV4:
5382 mlx5_flow_tunnel_ip_check(items, next_protocol,
5383 &item_flags, &tunnel);
5384 ret = flow_dv_validate_item_ipv4(items, item_flags,
5385 last_item, ether_type,
5389 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5390 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5391 if (items->mask != NULL &&
5392 ((const struct rte_flow_item_ipv4 *)
5393 items->mask)->hdr.next_proto_id) {
5395 ((const struct rte_flow_item_ipv4 *)
5396 (items->spec))->hdr.next_proto_id;
5398 ((const struct rte_flow_item_ipv4 *)
5399 (items->mask))->hdr.next_proto_id;
5401 /* Reset for inner layer. */
5402 next_protocol = 0xff;
5405 case RTE_FLOW_ITEM_TYPE_IPV6:
5406 mlx5_flow_tunnel_ip_check(items, next_protocol,
5407 &item_flags, &tunnel);
5408 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5415 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5416 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5417 if (items->mask != NULL &&
5418 ((const struct rte_flow_item_ipv6 *)
5419 items->mask)->hdr.proto) {
5421 ((const struct rte_flow_item_ipv6 *)
5422 items->spec)->hdr.proto;
5424 ((const struct rte_flow_item_ipv6 *)
5425 items->spec)->hdr.proto;
5427 ((const struct rte_flow_item_ipv6 *)
5428 items->mask)->hdr.proto;
5430 /* Reset for inner layer. */
5431 next_protocol = 0xff;
5434 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5435 ret = flow_dv_validate_item_ipv6_frag_ext(items,
5440 last_item = tunnel ?
5441 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5442 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5443 if (items->mask != NULL &&
5444 ((const struct rte_flow_item_ipv6_frag_ext *)
5445 items->mask)->hdr.next_header) {
5447 ((const struct rte_flow_item_ipv6_frag_ext *)
5448 items->spec)->hdr.next_header;
5450 ((const struct rte_flow_item_ipv6_frag_ext *)
5451 items->mask)->hdr.next_header;
5453 /* Reset for inner layer. */
5454 next_protocol = 0xff;
5457 case RTE_FLOW_ITEM_TYPE_TCP:
5458 ret = mlx5_flow_validate_item_tcp
5465 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5466 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5468 case RTE_FLOW_ITEM_TYPE_UDP:
5469 ret = mlx5_flow_validate_item_udp(items, item_flags,
5474 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5475 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5477 case RTE_FLOW_ITEM_TYPE_GRE:
5478 ret = mlx5_flow_validate_item_gre(items, item_flags,
5479 next_protocol, error);
5483 last_item = MLX5_FLOW_LAYER_GRE;
5485 case RTE_FLOW_ITEM_TYPE_NVGRE:
5486 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5491 last_item = MLX5_FLOW_LAYER_NVGRE;
5493 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5494 ret = mlx5_flow_validate_item_gre_key
5495 (items, item_flags, gre_item, error);
5498 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5500 case RTE_FLOW_ITEM_TYPE_VXLAN:
5501 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5505 last_item = MLX5_FLOW_LAYER_VXLAN;
5507 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5508 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5513 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5515 case RTE_FLOW_ITEM_TYPE_GENEVE:
5516 ret = mlx5_flow_validate_item_geneve(items,
5521 last_item = MLX5_FLOW_LAYER_GENEVE;
5523 case RTE_FLOW_ITEM_TYPE_MPLS:
5524 ret = mlx5_flow_validate_item_mpls(dev, items,
5529 last_item = MLX5_FLOW_LAYER_MPLS;
5532 case RTE_FLOW_ITEM_TYPE_MARK:
5533 ret = flow_dv_validate_item_mark(dev, items, attr,
5537 last_item = MLX5_FLOW_ITEM_MARK;
5539 case RTE_FLOW_ITEM_TYPE_META:
5540 ret = flow_dv_validate_item_meta(dev, items, attr,
5544 last_item = MLX5_FLOW_ITEM_METADATA;
5546 case RTE_FLOW_ITEM_TYPE_ICMP:
5547 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5552 last_item = MLX5_FLOW_LAYER_ICMP;
5554 case RTE_FLOW_ITEM_TYPE_ICMP6:
5555 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5560 item_ipv6_proto = IPPROTO_ICMPV6;
5561 last_item = MLX5_FLOW_LAYER_ICMP6;
5563 case RTE_FLOW_ITEM_TYPE_TAG:
5564 ret = flow_dv_validate_item_tag(dev, items,
5568 last_item = MLX5_FLOW_ITEM_TAG;
5570 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5571 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5573 case RTE_FLOW_ITEM_TYPE_GTP:
5574 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5578 last_item = MLX5_FLOW_LAYER_GTP;
5580 case RTE_FLOW_ITEM_TYPE_ECPRI:
5581 /* Capacity will be checked in the translate stage. */
5582 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5589 last_item = MLX5_FLOW_LAYER_ECPRI;
5592 return rte_flow_error_set(error, ENOTSUP,
5593 RTE_FLOW_ERROR_TYPE_ITEM,
5594 NULL, "item not supported");
5596 item_flags |= last_item;
5598 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5599 int type = actions->type;
5601 if (!mlx5_flow_os_action_supported(type))
5602 return rte_flow_error_set(error, ENOTSUP,
5603 RTE_FLOW_ERROR_TYPE_ACTION,
5605 "action not supported");
5606 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5607 return rte_flow_error_set(error, ENOTSUP,
5608 RTE_FLOW_ERROR_TYPE_ACTION,
5609 actions, "too many actions");
5611 case RTE_FLOW_ACTION_TYPE_VOID:
5613 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5614 ret = flow_dv_validate_action_port_id(dev,
5621 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5624 case RTE_FLOW_ACTION_TYPE_FLAG:
5625 ret = flow_dv_validate_action_flag(dev, action_flags,
5629 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5630 /* Count all modify-header actions as one. */
5631 if (!(action_flags &
5632 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5634 action_flags |= MLX5_FLOW_ACTION_FLAG |
5635 MLX5_FLOW_ACTION_MARK_EXT;
5637 action_flags |= MLX5_FLOW_ACTION_FLAG;
5640 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5642 case RTE_FLOW_ACTION_TYPE_MARK:
5643 ret = flow_dv_validate_action_mark(dev, actions,
5648 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5649 /* Count all modify-header actions as one. */
5650 if (!(action_flags &
5651 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5653 action_flags |= MLX5_FLOW_ACTION_MARK |
5654 MLX5_FLOW_ACTION_MARK_EXT;
5656 action_flags |= MLX5_FLOW_ACTION_MARK;
5659 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5661 case RTE_FLOW_ACTION_TYPE_SET_META:
5662 ret = flow_dv_validate_action_set_meta(dev, actions,
5667 /* Count all modify-header actions as one action. */
5668 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5670 action_flags |= MLX5_FLOW_ACTION_SET_META;
5671 rw_act_num += MLX5_ACT_NUM_SET_META;
5673 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5674 ret = flow_dv_validate_action_set_tag(dev, actions,
5679 /* Count all modify-header actions as one action. */
5680 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5682 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5683 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5685 case RTE_FLOW_ACTION_TYPE_DROP:
5686 ret = mlx5_flow_validate_action_drop(action_flags,
5690 action_flags |= MLX5_FLOW_ACTION_DROP;
5693 case RTE_FLOW_ACTION_TYPE_QUEUE:
5694 ret = mlx5_flow_validate_action_queue(actions,
5699 queue_index = ((const struct rte_flow_action_queue *)
5700 (actions->conf))->index;
5701 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5704 case RTE_FLOW_ACTION_TYPE_RSS:
5705 rss = actions->conf;
5706 ret = mlx5_flow_validate_action_rss(actions,
5712 if (rss != NULL && rss->queue_num)
5713 queue_index = rss->queue[0];
5714 action_flags |= MLX5_FLOW_ACTION_RSS;
5717 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5719 mlx5_flow_validate_action_default_miss(action_flags,
5723 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5726 case RTE_FLOW_ACTION_TYPE_COUNT:
5727 ret = flow_dv_validate_action_count(dev, error);
5730 action_flags |= MLX5_FLOW_ACTION_COUNT;
5733 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5734 if (flow_dv_validate_action_pop_vlan(dev,
5740 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5743 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5744 ret = flow_dv_validate_action_push_vlan(dev,
5751 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5754 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5755 ret = flow_dv_validate_action_set_vlan_pcp
5756 (action_flags, actions, error);
5759 /* Count PCP with push_vlan command. */
5760 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5762 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5763 ret = flow_dv_validate_action_set_vlan_vid
5764 (item_flags, action_flags,
5768 /* Count VID with push_vlan command. */
5769 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5770 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5772 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5773 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5774 ret = flow_dv_validate_action_l2_encap(dev,
5780 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5783 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5784 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5785 ret = flow_dv_validate_action_decap(dev, action_flags,
5786 actions, item_flags,
5790 action_flags |= MLX5_FLOW_ACTION_DECAP;
5793 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5794 ret = flow_dv_validate_action_raw_encap_decap
5795 (dev, NULL, actions->conf, attr, &action_flags,
5796 &actions_n, actions, item_flags, error);
5800 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5801 decap = actions->conf;
5802 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5804 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5808 encap = actions->conf;
5810 ret = flow_dv_validate_action_raw_encap_decap
5812 decap ? decap : &empty_decap, encap,
5813 attr, &action_flags, &actions_n,
5814 actions, item_flags, error);
5818 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5819 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5820 ret = flow_dv_validate_action_modify_mac(action_flags,
5826 /* Count all modify-header actions as one action. */
5827 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5829 action_flags |= actions->type ==
5830 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5831 MLX5_FLOW_ACTION_SET_MAC_SRC :
5832 MLX5_FLOW_ACTION_SET_MAC_DST;
5834 * Even if the source and destination MAC addresses have
5835 * overlap in the header with 4B alignment, the convert
5836 * function will handle them separately and 4 SW actions
5837 * will be created. And 2 actions will be added each
5838 * time no matter how many bytes of address will be set.
5840 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5842 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5843 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5844 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5850 /* Count all modify-header actions as one action. */
5851 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5853 action_flags |= actions->type ==
5854 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5855 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5856 MLX5_FLOW_ACTION_SET_IPV4_DST;
5857 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5859 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5860 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5861 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5867 if (item_ipv6_proto == IPPROTO_ICMPV6)
5868 return rte_flow_error_set(error, ENOTSUP,
5869 RTE_FLOW_ERROR_TYPE_ACTION,
5871 "Can't change header "
5872 "with ICMPv6 proto");
5873 /* Count all modify-header actions as one action. */
5874 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5876 action_flags |= actions->type ==
5877 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5878 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5879 MLX5_FLOW_ACTION_SET_IPV6_DST;
5880 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5882 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5883 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5884 ret = flow_dv_validate_action_modify_tp(action_flags,
5890 /* Count all modify-header actions as one action. */
5891 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5893 action_flags |= actions->type ==
5894 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5895 MLX5_FLOW_ACTION_SET_TP_SRC :
5896 MLX5_FLOW_ACTION_SET_TP_DST;
5897 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5899 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5900 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5901 ret = flow_dv_validate_action_modify_ttl(action_flags,
5907 /* Count all modify-header actions as one action. */
5908 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5910 action_flags |= actions->type ==
5911 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5912 MLX5_FLOW_ACTION_SET_TTL :
5913 MLX5_FLOW_ACTION_DEC_TTL;
5914 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5916 case RTE_FLOW_ACTION_TYPE_JUMP:
5917 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5924 action_flags |= MLX5_FLOW_ACTION_JUMP;
5926 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5927 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5928 ret = flow_dv_validate_action_modify_tcp_seq
5935 /* Count all modify-header actions as one action. */
5936 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5938 action_flags |= actions->type ==
5939 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5940 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5941 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5942 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5944 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5945 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5946 ret = flow_dv_validate_action_modify_tcp_ack
5953 /* Count all modify-header actions as one action. */
5954 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5956 action_flags |= actions->type ==
5957 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5958 MLX5_FLOW_ACTION_INC_TCP_ACK :
5959 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5960 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5962 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5964 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5965 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5966 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5968 case RTE_FLOW_ACTION_TYPE_METER:
5969 ret = mlx5_flow_validate_action_meter(dev,
5975 action_flags |= MLX5_FLOW_ACTION_METER;
5977 /* Meter action will add one more TAG action. */
5978 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5980 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
5981 if (!attr->transfer && !attr->group)
5982 return rte_flow_error_set(error, ENOTSUP,
5983 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5985 "Shared ASO age action is not supported for group 0");
5986 action_flags |= MLX5_FLOW_ACTION_AGE;
5989 case RTE_FLOW_ACTION_TYPE_AGE:
5990 ret = flow_dv_validate_action_age(action_flags,
5995 action_flags |= MLX5_FLOW_ACTION_AGE;
5998 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5999 ret = flow_dv_validate_action_modify_ipv4_dscp
6006 /* Count all modify-header actions as one action. */
6007 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6009 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6010 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6012 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6013 ret = flow_dv_validate_action_modify_ipv6_dscp
6020 /* Count all modify-header actions as one action. */
6021 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6023 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6024 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6026 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6027 ret = flow_dv_validate_action_sample(action_flags,
6033 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6036 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6037 if (actions[0].type != (typeof(actions[0].type))
6038 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6039 return rte_flow_error_set
6041 RTE_FLOW_ERROR_TYPE_ACTION,
6042 NULL, "MLX5 private action "
6043 "must be the first");
6045 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6048 return rte_flow_error_set(error, ENOTSUP,
6049 RTE_FLOW_ERROR_TYPE_ACTION,
6051 "action not supported");
6055 * Validate actions in flow rules
6056 * - Explicit decap action is prohibited by the tunnel offload API.
6057 * - Drop action in tunnel steer rule is prohibited by the API.
6058 * - Application cannot use MARK action because it's value can mask
6059 * tunnel default miss nitification.
6060 * - JUMP in tunnel match rule has no support in current PMD
6062 * - TAG & META are reserved for future uses.
6064 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6065 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6066 MLX5_FLOW_ACTION_MARK |
6067 MLX5_FLOW_ACTION_SET_TAG |
6068 MLX5_FLOW_ACTION_SET_META |
6069 MLX5_FLOW_ACTION_DROP;
6071 if (action_flags & bad_actions_mask)
6072 return rte_flow_error_set
6074 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6075 "Invalid RTE action in tunnel "
6077 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6078 return rte_flow_error_set
6080 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6081 "tunnel set decap rule must terminate "
6084 return rte_flow_error_set
6086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6087 "tunnel flows for ingress traffic only");
6089 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6090 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6091 MLX5_FLOW_ACTION_MARK |
6092 MLX5_FLOW_ACTION_SET_TAG |
6093 MLX5_FLOW_ACTION_SET_META;
6095 if (action_flags & bad_actions_mask)
6096 return rte_flow_error_set
6098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6099 "Invalid RTE action in tunnel "
6103 * Validate the drop action mutual exclusion with other actions.
6104 * Drop action is mutually-exclusive with any other action, except for
6107 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6108 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6109 return rte_flow_error_set(error, EINVAL,
6110 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6111 "Drop action is mutually-exclusive "
6112 "with any other action, except for "
6114 /* Eswitch has few restrictions on using items and actions */
6115 if (attr->transfer) {
6116 if (!mlx5_flow_ext_mreg_supported(dev) &&
6117 action_flags & MLX5_FLOW_ACTION_FLAG)
6118 return rte_flow_error_set(error, ENOTSUP,
6119 RTE_FLOW_ERROR_TYPE_ACTION,
6121 "unsupported action FLAG");
6122 if (!mlx5_flow_ext_mreg_supported(dev) &&
6123 action_flags & MLX5_FLOW_ACTION_MARK)
6124 return rte_flow_error_set(error, ENOTSUP,
6125 RTE_FLOW_ERROR_TYPE_ACTION,
6127 "unsupported action MARK");
6128 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6129 return rte_flow_error_set(error, ENOTSUP,
6130 RTE_FLOW_ERROR_TYPE_ACTION,
6132 "unsupported action QUEUE");
6133 if (action_flags & MLX5_FLOW_ACTION_RSS)
6134 return rte_flow_error_set(error, ENOTSUP,
6135 RTE_FLOW_ERROR_TYPE_ACTION,
6137 "unsupported action RSS");
6138 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6139 return rte_flow_error_set(error, EINVAL,
6140 RTE_FLOW_ERROR_TYPE_ACTION,
6142 "no fate action is found");
6144 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6145 return rte_flow_error_set(error, EINVAL,
6146 RTE_FLOW_ERROR_TYPE_ACTION,
6148 "no fate action is found");
6151 * Continue validation for Xcap and VLAN actions.
6152 * If hairpin is working in explicit TX rule mode, there is no actions
6153 * splitting and the validation of hairpin ingress flow should be the
6154 * same as other standard flows.
6156 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6157 MLX5_FLOW_VLAN_ACTIONS)) &&
6158 (queue_index == 0xFFFF ||
6159 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6160 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6161 conf->tx_explicit != 0))) {
6162 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6163 MLX5_FLOW_XCAP_ACTIONS)
6164 return rte_flow_error_set(error, ENOTSUP,
6165 RTE_FLOW_ERROR_TYPE_ACTION,
6166 NULL, "encap and decap "
6167 "combination aren't supported");
6168 if (!attr->transfer && attr->ingress) {
6169 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6170 return rte_flow_error_set
6172 RTE_FLOW_ERROR_TYPE_ACTION,
6173 NULL, "encap is not supported"
6174 " for ingress traffic");
6175 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6176 return rte_flow_error_set
6178 RTE_FLOW_ERROR_TYPE_ACTION,
6179 NULL, "push VLAN action not "
6180 "supported for ingress");
6181 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6182 MLX5_FLOW_VLAN_ACTIONS)
6183 return rte_flow_error_set
6185 RTE_FLOW_ERROR_TYPE_ACTION,
6186 NULL, "no support for "
6187 "multiple VLAN actions");
6191 * Hairpin flow will add one more TAG action in TX implicit mode.
6192 * In TX explicit mode, there will be no hairpin flow ID.
6195 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6196 /* extra metadata enabled: one more TAG action will be add. */
6197 if (dev_conf->dv_flow_en &&
6198 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6199 mlx5_flow_ext_mreg_supported(dev))
6200 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6201 if ((uint32_t)rw_act_num >
6202 flow_dv_modify_hdr_action_max(dev, is_root)) {
6203 return rte_flow_error_set(error, ENOTSUP,
6204 RTE_FLOW_ERROR_TYPE_ACTION,
6205 NULL, "too many header modify"
6206 " actions to support");
6212 * Internal preparation function. Allocates the DV flow size,
6213 * this size is constant.
6216 * Pointer to the rte_eth_dev structure.
6218 * Pointer to the flow attributes.
6220 * Pointer to the list of items.
6221 * @param[in] actions
6222 * Pointer to the list of actions.
6224 * Pointer to the error structure.
6227 * Pointer to mlx5_flow object on success,
6228 * otherwise NULL and rte_errno is set.
6230 static struct mlx5_flow *
6231 flow_dv_prepare(struct rte_eth_dev *dev,
6232 const struct rte_flow_attr *attr __rte_unused,
6233 const struct rte_flow_item items[] __rte_unused,
6234 const struct rte_flow_action actions[] __rte_unused,
6235 struct rte_flow_error *error)
6237 uint32_t handle_idx = 0;
6238 struct mlx5_flow *dev_flow;
6239 struct mlx5_flow_handle *dev_handle;
6240 struct mlx5_priv *priv = dev->data->dev_private;
6241 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6244 /* In case of corrupting the memory. */
6245 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6246 rte_flow_error_set(error, ENOSPC,
6247 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6248 "not free temporary device flow");
6251 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6254 rte_flow_error_set(error, ENOMEM,
6255 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6256 "not enough memory to create flow handle");
6259 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6260 dev_flow = &wks->flows[wks->flow_idx++];
6261 memset(dev_flow, 0, sizeof(*dev_flow));
6262 dev_flow->handle = dev_handle;
6263 dev_flow->handle_idx = handle_idx;
6265 * In some old rdma-core releases, before continuing, a check of the
6266 * length of matching parameter will be done at first. It needs to use
6267 * the length without misc4 param. If the flow has misc4 support, then
6268 * the length needs to be adjusted accordingly. Each param member is
6269 * aligned with a 64B boundary naturally.
6271 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6272 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6273 dev_flow->ingress = attr->ingress;
6274 dev_flow->dv.transfer = attr->transfer;
6278 #ifdef RTE_LIBRTE_MLX5_DEBUG
6280 * Sanity check for match mask and value. Similar to check_valid_spec() in
6281 * kernel driver. If unmasked bit is present in value, it returns failure.
6284 * pointer to match mask buffer.
6285 * @param match_value
6286 * pointer to match value buffer.
6289 * 0 if valid, -EINVAL otherwise.
6292 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6294 uint8_t *m = match_mask;
6295 uint8_t *v = match_value;
6298 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6301 "match_value differs from match_criteria"
6302 " %p[%u] != %p[%u]",
6303 match_value, i, match_mask, i);
6312 * Add match of ip_version.
6316 * @param[in] headers_v
6317 * Values header pointer.
6318 * @param[in] headers_m
6319 * Masks header pointer.
6320 * @param[in] ip_version
6321 * The IP version to set.
6324 flow_dv_set_match_ip_version(uint32_t group,
6330 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6332 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6334 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6335 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6336 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6340 * Add Ethernet item to matcher and to the value.
6342 * @param[in, out] matcher
6344 * @param[in, out] key
6345 * Flow matcher value.
6347 * Flow pattern to translate.
6349 * Item is inner pattern.
6352 flow_dv_translate_item_eth(void *matcher, void *key,
6353 const struct rte_flow_item *item, int inner,
6356 const struct rte_flow_item_eth *eth_m = item->mask;
6357 const struct rte_flow_item_eth *eth_v = item->spec;
6358 const struct rte_flow_item_eth nic_mask = {
6359 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6360 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6361 .type = RTE_BE16(0xffff),
6374 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6376 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6378 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6380 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6382 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6383 ð_m->dst, sizeof(eth_m->dst));
6384 /* The value must be in the range of the mask. */
6385 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6386 for (i = 0; i < sizeof(eth_m->dst); ++i)
6387 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6388 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6389 ð_m->src, sizeof(eth_m->src));
6390 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6391 /* The value must be in the range of the mask. */
6392 for (i = 0; i < sizeof(eth_m->dst); ++i)
6393 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6395 * HW supports match on one Ethertype, the Ethertype following the last
6396 * VLAN tag of the packet (see PRM).
6397 * Set match on ethertype only if ETH header is not followed by VLAN.
6398 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6399 * ethertype, and use ip_version field instead.
6400 * eCPRI over Ether layer will use type value 0xAEFE.
6402 if (eth_m->type == 0xFFFF) {
6403 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6404 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6405 switch (eth_v->type) {
6406 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6407 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6409 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6410 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6411 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6413 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6414 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6416 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6417 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6423 if (eth_m->has_vlan) {
6424 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6425 if (eth_v->has_vlan) {
6427 * Here, when also has_more_vlan field in VLAN item is
6428 * not set, only single-tagged packets will be matched.
6430 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6434 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6435 rte_be_to_cpu_16(eth_m->type));
6436 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6437 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6441 * Add VLAN item to matcher and to the value.
6443 * @param[in, out] dev_flow
6445 * @param[in, out] matcher
6447 * @param[in, out] key
6448 * Flow matcher value.
6450 * Flow pattern to translate.
6452 * Item is inner pattern.
6455 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6456 void *matcher, void *key,
6457 const struct rte_flow_item *item,
6458 int inner, uint32_t group)
6460 const struct rte_flow_item_vlan *vlan_m = item->mask;
6461 const struct rte_flow_item_vlan *vlan_v = item->spec;
6468 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6470 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6472 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6474 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6476 * This is workaround, masks are not supported,
6477 * and pre-validated.
6480 dev_flow->handle->vf_vlan.tag =
6481 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6484 * When VLAN item exists in flow, mark packet as tagged,
6485 * even if TCI is not specified.
6487 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6488 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6489 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6494 vlan_m = &rte_flow_item_vlan_mask;
6495 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6496 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6497 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6498 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6499 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6500 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6501 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6502 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6504 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6505 * ethertype, and use ip_version field instead.
6507 if (vlan_m->inner_type == 0xFFFF) {
6508 switch (vlan_v->inner_type) {
6509 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6510 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6511 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6512 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6514 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6515 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6517 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6518 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6524 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6525 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6526 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6527 /* Only one vlan_tag bit can be set. */
6528 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6531 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6532 rte_be_to_cpu_16(vlan_m->inner_type));
6533 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6534 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6538 * Add IPV4 item to matcher and to the value.
6540 * @param[in, out] matcher
6542 * @param[in, out] key
6543 * Flow matcher value.
6545 * Flow pattern to translate.
6547 * Item is inner pattern.
6549 * The group to insert the rule.
6552 flow_dv_translate_item_ipv4(void *matcher, void *key,
6553 const struct rte_flow_item *item,
6554 int inner, uint32_t group)
6556 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6557 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6558 const struct rte_flow_item_ipv4 nic_mask = {
6560 .src_addr = RTE_BE32(0xffffffff),
6561 .dst_addr = RTE_BE32(0xffffffff),
6562 .type_of_service = 0xff,
6563 .next_proto_id = 0xff,
6564 .time_to_live = 0xff,
6574 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6576 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6578 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6580 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6582 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6587 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6588 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6589 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6590 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6591 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6592 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6593 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6594 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6595 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6596 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6597 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6598 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6599 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6600 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6601 ipv4_m->hdr.type_of_service);
6602 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6603 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6604 ipv4_m->hdr.type_of_service >> 2);
6605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6606 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6607 ipv4_m->hdr.next_proto_id);
6608 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6609 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6610 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6611 ipv4_m->hdr.time_to_live);
6612 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6613 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6614 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6615 !!(ipv4_m->hdr.fragment_offset));
6616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6617 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6621 * Add IPV6 item to matcher and to the value.
6623 * @param[in, out] matcher
6625 * @param[in, out] key
6626 * Flow matcher value.
6628 * Flow pattern to translate.
6630 * Item is inner pattern.
6632 * The group to insert the rule.
6635 flow_dv_translate_item_ipv6(void *matcher, void *key,
6636 const struct rte_flow_item *item,
6637 int inner, uint32_t group)
6639 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6640 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6641 const struct rte_flow_item_ipv6 nic_mask = {
6644 "\xff\xff\xff\xff\xff\xff\xff\xff"
6645 "\xff\xff\xff\xff\xff\xff\xff\xff",
6647 "\xff\xff\xff\xff\xff\xff\xff\xff"
6648 "\xff\xff\xff\xff\xff\xff\xff\xff",
6649 .vtc_flow = RTE_BE32(0xffffffff),
6656 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6657 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6666 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6668 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6670 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6672 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6674 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6679 size = sizeof(ipv6_m->hdr.dst_addr);
6680 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6681 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6682 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6683 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6684 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6685 for (i = 0; i < size; ++i)
6686 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6687 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6688 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6689 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6690 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6691 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6692 for (i = 0; i < size; ++i)
6693 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6695 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6696 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6697 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6698 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6699 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6700 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6703 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6705 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6708 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6710 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6714 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6716 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6717 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6719 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6720 ipv6_m->hdr.hop_limits);
6721 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6722 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6723 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6724 !!(ipv6_m->has_frag_ext));
6725 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6726 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6730 * Add IPV6 fragment extension item to matcher and to the value.
6732 * @param[in, out] matcher
6734 * @param[in, out] key
6735 * Flow matcher value.
6737 * Flow pattern to translate.
6739 * Item is inner pattern.
6742 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6743 const struct rte_flow_item *item,
6746 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6747 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6748 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6750 .next_header = 0xff,
6751 .frag_data = RTE_BE16(0xffff),
6758 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6760 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6762 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6764 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6766 /* IPv6 fragment extension item exists, so packet is IP fragment. */
6767 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6768 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6769 if (!ipv6_frag_ext_v)
6771 if (!ipv6_frag_ext_m)
6772 ipv6_frag_ext_m = &nic_mask;
6773 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6774 ipv6_frag_ext_m->hdr.next_header);
6775 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6776 ipv6_frag_ext_v->hdr.next_header &
6777 ipv6_frag_ext_m->hdr.next_header);
6781 * Add TCP item to matcher and to the value.
6783 * @param[in, out] matcher
6785 * @param[in, out] key
6786 * Flow matcher value.
6788 * Flow pattern to translate.
6790 * Item is inner pattern.
6793 flow_dv_translate_item_tcp(void *matcher, void *key,
6794 const struct rte_flow_item *item,
6797 const struct rte_flow_item_tcp *tcp_m = item->mask;
6798 const struct rte_flow_item_tcp *tcp_v = item->spec;
6803 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6805 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6807 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6809 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6811 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6812 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6816 tcp_m = &rte_flow_item_tcp_mask;
6817 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6818 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6819 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6820 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6821 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6822 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6823 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6824 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6825 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6826 tcp_m->hdr.tcp_flags);
6827 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6828 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6832 * Add UDP item to matcher and to the value.
6834 * @param[in, out] matcher
6836 * @param[in, out] key
6837 * Flow matcher value.
6839 * Flow pattern to translate.
6841 * Item is inner pattern.
6844 flow_dv_translate_item_udp(void *matcher, void *key,
6845 const struct rte_flow_item *item,
6848 const struct rte_flow_item_udp *udp_m = item->mask;
6849 const struct rte_flow_item_udp *udp_v = item->spec;
6854 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6856 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6858 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6860 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6862 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6863 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6867 udp_m = &rte_flow_item_udp_mask;
6868 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6869 rte_be_to_cpu_16(udp_m->hdr.src_port));
6870 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6871 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6872 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6873 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6874 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6875 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6879 * Add GRE optional Key item to matcher and to the value.
6881 * @param[in, out] matcher
6883 * @param[in, out] key
6884 * Flow matcher value.
6886 * Flow pattern to translate.
6888 * Item is inner pattern.
6891 flow_dv_translate_item_gre_key(void *matcher, void *key,
6892 const struct rte_flow_item *item)
6894 const rte_be32_t *key_m = item->mask;
6895 const rte_be32_t *key_v = item->spec;
6896 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6897 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6898 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6900 /* GRE K bit must be on and should already be validated */
6901 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6902 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6906 key_m = &gre_key_default_mask;
6907 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6908 rte_be_to_cpu_32(*key_m) >> 8);
6909 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6910 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6911 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6912 rte_be_to_cpu_32(*key_m) & 0xFF);
6913 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6914 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6918 * Add GRE item to matcher and to the value.
6920 * @param[in, out] matcher
6922 * @param[in, out] key
6923 * Flow matcher value.
6925 * Flow pattern to translate.
6927 * Item is inner pattern.
6930 flow_dv_translate_item_gre(void *matcher, void *key,
6931 const struct rte_flow_item *item,
6934 const struct rte_flow_item_gre *gre_m = item->mask;
6935 const struct rte_flow_item_gre *gre_v = item->spec;
6938 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6939 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6946 uint16_t s_present:1;
6947 uint16_t k_present:1;
6948 uint16_t rsvd_bit1:1;
6949 uint16_t c_present:1;
6953 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6956 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6958 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6960 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6962 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6964 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6965 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6969 gre_m = &rte_flow_item_gre_mask;
6970 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6971 rte_be_to_cpu_16(gre_m->protocol));
6972 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6973 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6974 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6975 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6976 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6977 gre_crks_rsvd0_ver_m.c_present);
6978 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6979 gre_crks_rsvd0_ver_v.c_present &
6980 gre_crks_rsvd0_ver_m.c_present);
6981 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6982 gre_crks_rsvd0_ver_m.k_present);
6983 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6984 gre_crks_rsvd0_ver_v.k_present &
6985 gre_crks_rsvd0_ver_m.k_present);
6986 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6987 gre_crks_rsvd0_ver_m.s_present);
6988 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6989 gre_crks_rsvd0_ver_v.s_present &
6990 gre_crks_rsvd0_ver_m.s_present);
6994 * Add NVGRE item to matcher and to the value.
6996 * @param[in, out] matcher
6998 * @param[in, out] key
6999 * Flow matcher value.
7001 * Flow pattern to translate.
7003 * Item is inner pattern.
7006 flow_dv_translate_item_nvgre(void *matcher, void *key,
7007 const struct rte_flow_item *item,
7010 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7011 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7012 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7013 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7014 const char *tni_flow_id_m;
7015 const char *tni_flow_id_v;
7021 /* For NVGRE, GRE header fields must be set with defined values. */
7022 const struct rte_flow_item_gre gre_spec = {
7023 .c_rsvd0_ver = RTE_BE16(0x2000),
7024 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7026 const struct rte_flow_item_gre gre_mask = {
7027 .c_rsvd0_ver = RTE_BE16(0xB000),
7028 .protocol = RTE_BE16(UINT16_MAX),
7030 const struct rte_flow_item gre_item = {
7035 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7039 nvgre_m = &rte_flow_item_nvgre_mask;
7040 tni_flow_id_m = (const char *)nvgre_m->tni;
7041 tni_flow_id_v = (const char *)nvgre_v->tni;
7042 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7043 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7044 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7045 memcpy(gre_key_m, tni_flow_id_m, size);
7046 for (i = 0; i < size; ++i)
7047 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7051 * Add VXLAN item to matcher and to the value.
7053 * @param[in, out] matcher
7055 * @param[in, out] key
7056 * Flow matcher value.
7058 * Flow pattern to translate.
7060 * Item is inner pattern.
7063 flow_dv_translate_item_vxlan(void *matcher, void *key,
7064 const struct rte_flow_item *item,
7067 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7068 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7071 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7072 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7080 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7082 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7084 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7086 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7088 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7089 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7090 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7091 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7092 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7097 vxlan_m = &rte_flow_item_vxlan_mask;
7098 size = sizeof(vxlan_m->vni);
7099 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7100 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7101 memcpy(vni_m, vxlan_m->vni, size);
7102 for (i = 0; i < size; ++i)
7103 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7107 * Add VXLAN-GPE item to matcher and to the value.
7109 * @param[in, out] matcher
7111 * @param[in, out] key
7112 * Flow matcher value.
7114 * Flow pattern to translate.
7116 * Item is inner pattern.
7120 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7121 const struct rte_flow_item *item, int inner)
7123 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7124 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7128 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7130 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7136 uint8_t flags_m = 0xff;
7137 uint8_t flags_v = 0xc;
7140 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7142 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7144 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7146 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7148 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7149 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7150 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7151 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7152 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7157 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7158 size = sizeof(vxlan_m->vni);
7159 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7160 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7161 memcpy(vni_m, vxlan_m->vni, size);
7162 for (i = 0; i < size; ++i)
7163 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7164 if (vxlan_m->flags) {
7165 flags_m = vxlan_m->flags;
7166 flags_v = vxlan_v->flags;
7168 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7169 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7170 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7172 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7177 * Add Geneve item to matcher and to the value.
7179 * @param[in, out] matcher
7181 * @param[in, out] key
7182 * Flow matcher value.
7184 * Flow pattern to translate.
7186 * Item is inner pattern.
7190 flow_dv_translate_item_geneve(void *matcher, void *key,
7191 const struct rte_flow_item *item, int inner)
7193 const struct rte_flow_item_geneve *geneve_m = item->mask;
7194 const struct rte_flow_item_geneve *geneve_v = item->spec;
7197 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7198 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7207 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7209 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7211 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7213 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7215 dport = MLX5_UDP_PORT_GENEVE;
7216 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7217 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7218 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7223 geneve_m = &rte_flow_item_geneve_mask;
7224 size = sizeof(geneve_m->vni);
7225 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7226 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7227 memcpy(vni_m, geneve_m->vni, size);
7228 for (i = 0; i < size; ++i)
7229 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7230 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7231 rte_be_to_cpu_16(geneve_m->protocol));
7232 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7233 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7234 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7235 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7236 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7237 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7238 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7239 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7240 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7241 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7242 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7243 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7244 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7248 * Add MPLS item to matcher and to the value.
7250 * @param[in, out] matcher
7252 * @param[in, out] key
7253 * Flow matcher value.
7255 * Flow pattern to translate.
7256 * @param[in] prev_layer
7257 * The protocol layer indicated in previous item.
7259 * Item is inner pattern.
7262 flow_dv_translate_item_mpls(void *matcher, void *key,
7263 const struct rte_flow_item *item,
7264 uint64_t prev_layer,
7267 const uint32_t *in_mpls_m = item->mask;
7268 const uint32_t *in_mpls_v = item->spec;
7269 uint32_t *out_mpls_m = 0;
7270 uint32_t *out_mpls_v = 0;
7271 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7272 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7273 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7275 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7276 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7277 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7279 switch (prev_layer) {
7280 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7281 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7283 MLX5_UDP_PORT_MPLS);
7285 case MLX5_FLOW_LAYER_GRE:
7286 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7287 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7288 RTE_ETHER_TYPE_MPLS);
7291 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7292 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7299 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7300 switch (prev_layer) {
7301 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7303 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7304 outer_first_mpls_over_udp);
7306 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7307 outer_first_mpls_over_udp);
7309 case MLX5_FLOW_LAYER_GRE:
7311 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7312 outer_first_mpls_over_gre);
7314 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7315 outer_first_mpls_over_gre);
7318 /* Inner MPLS not over GRE is not supported. */
7321 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7325 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7331 if (out_mpls_m && out_mpls_v) {
7332 *out_mpls_m = *in_mpls_m;
7333 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7338 * Add metadata register item to matcher
7340 * @param[in, out] matcher
7342 * @param[in, out] key
7343 * Flow matcher value.
7344 * @param[in] reg_type
7345 * Type of device metadata register
7352 flow_dv_match_meta_reg(void *matcher, void *key,
7353 enum modify_reg reg_type,
7354 uint32_t data, uint32_t mask)
7357 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7359 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7365 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7366 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7369 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7370 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7374 * The metadata register C0 field might be divided into
7375 * source vport index and META item value, we should set
7376 * this field according to specified mask, not as whole one.
7378 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7380 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7381 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7384 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7387 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7388 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7391 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7392 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7395 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7396 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7399 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7400 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7403 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7404 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7407 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7408 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7411 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7412 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7421 * Add MARK item to matcher
7424 * The device to configure through.
7425 * @param[in, out] matcher
7427 * @param[in, out] key
7428 * Flow matcher value.
7430 * Flow pattern to translate.
7433 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7434 void *matcher, void *key,
7435 const struct rte_flow_item *item)
7437 struct mlx5_priv *priv = dev->data->dev_private;
7438 const struct rte_flow_item_mark *mark;
7442 mark = item->mask ? (const void *)item->mask :
7443 &rte_flow_item_mark_mask;
7444 mask = mark->id & priv->sh->dv_mark_mask;
7445 mark = (const void *)item->spec;
7447 value = mark->id & priv->sh->dv_mark_mask & mask;
7449 enum modify_reg reg;
7451 /* Get the metadata register index for the mark. */
7452 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7453 MLX5_ASSERT(reg > 0);
7454 if (reg == REG_C_0) {
7455 struct mlx5_priv *priv = dev->data->dev_private;
7456 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7457 uint32_t shl_c0 = rte_bsf32(msk_c0);
7463 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7468 * Add META item to matcher
7471 * The devich to configure through.
7472 * @param[in, out] matcher
7474 * @param[in, out] key
7475 * Flow matcher value.
7477 * Attributes of flow that includes this item.
7479 * Flow pattern to translate.
7482 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7483 void *matcher, void *key,
7484 const struct rte_flow_attr *attr,
7485 const struct rte_flow_item *item)
7487 const struct rte_flow_item_meta *meta_m;
7488 const struct rte_flow_item_meta *meta_v;
7490 meta_m = (const void *)item->mask;
7492 meta_m = &rte_flow_item_meta_mask;
7493 meta_v = (const void *)item->spec;
7496 uint32_t value = meta_v->data;
7497 uint32_t mask = meta_m->data;
7499 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7502 MLX5_ASSERT(reg != REG_NON);
7504 * In datapath code there is no endianness
7505 * coversions for perfromance reasons, all
7506 * pattern conversions are done in rte_flow.
7508 value = rte_cpu_to_be_32(value);
7509 mask = rte_cpu_to_be_32(mask);
7510 if (reg == REG_C_0) {
7511 struct mlx5_priv *priv = dev->data->dev_private;
7512 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7513 uint32_t shl_c0 = rte_bsf32(msk_c0);
7514 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7515 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7522 MLX5_ASSERT(msk_c0);
7523 MLX5_ASSERT(!(~msk_c0 & mask));
7525 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7530 * Add vport metadata Reg C0 item to matcher
7532 * @param[in, out] matcher
7534 * @param[in, out] key
7535 * Flow matcher value.
7537 * Flow pattern to translate.
7540 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7541 uint32_t value, uint32_t mask)
7543 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7547 * Add tag item to matcher
7550 * The devich to configure through.
7551 * @param[in, out] matcher
7553 * @param[in, out] key
7554 * Flow matcher value.
7556 * Flow pattern to translate.
7559 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7560 void *matcher, void *key,
7561 const struct rte_flow_item *item)
7563 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7564 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7565 uint32_t mask, value;
7568 value = tag_v->data;
7569 mask = tag_m ? tag_m->data : UINT32_MAX;
7570 if (tag_v->id == REG_C_0) {
7571 struct mlx5_priv *priv = dev->data->dev_private;
7572 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7573 uint32_t shl_c0 = rte_bsf32(msk_c0);
7579 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7583 * Add TAG item to matcher
7586 * The devich to configure through.
7587 * @param[in, out] matcher
7589 * @param[in, out] key
7590 * Flow matcher value.
7592 * Flow pattern to translate.
7595 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7596 void *matcher, void *key,
7597 const struct rte_flow_item *item)
7599 const struct rte_flow_item_tag *tag_v = item->spec;
7600 const struct rte_flow_item_tag *tag_m = item->mask;
7601 enum modify_reg reg;
7604 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7605 /* Get the metadata register index for the tag. */
7606 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7607 MLX5_ASSERT(reg > 0);
7608 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7612 * Add source vport match to the specified matcher.
7614 * @param[in, out] matcher
7616 * @param[in, out] key
7617 * Flow matcher value.
7619 * Source vport value to match
7624 flow_dv_translate_item_source_vport(void *matcher, void *key,
7625 int16_t port, uint16_t mask)
7627 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7628 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7630 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7631 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7635 * Translate port-id item to eswitch match on port-id.
7638 * The devich to configure through.
7639 * @param[in, out] matcher
7641 * @param[in, out] key
7642 * Flow matcher value.
7644 * Flow pattern to translate.
7649 * 0 on success, a negative errno value otherwise.
7652 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7653 void *key, const struct rte_flow_item *item,
7654 const struct rte_flow_attr *attr)
7656 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7657 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7658 struct mlx5_priv *priv;
7661 mask = pid_m ? pid_m->id : 0xffff;
7662 id = pid_v ? pid_v->id : dev->data->port_id;
7663 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7667 * Translate to vport field or to metadata, depending on mode.
7668 * Kernel can use either misc.source_port or half of C0 metadata
7671 if (priv->vport_meta_mask) {
7673 * Provide the hint for SW steering library
7674 * to insert the flow into ingress domain and
7675 * save the extra vport match.
7677 if (mask == 0xffff && priv->vport_id == 0xffff &&
7678 priv->pf_bond < 0 && attr->transfer)
7679 flow_dv_translate_item_source_vport
7680 (matcher, key, priv->vport_id, mask);
7682 flow_dv_translate_item_meta_vport
7684 priv->vport_meta_tag,
7685 priv->vport_meta_mask);
7687 flow_dv_translate_item_source_vport(matcher, key,
7688 priv->vport_id, mask);
7694 * Add ICMP6 item to matcher and to the value.
7696 * @param[in, out] matcher
7698 * @param[in, out] key
7699 * Flow matcher value.
7701 * Flow pattern to translate.
7703 * Item is inner pattern.
7706 flow_dv_translate_item_icmp6(void *matcher, void *key,
7707 const struct rte_flow_item *item,
7710 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7711 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7714 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7716 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7718 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7720 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7722 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7724 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7727 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7731 icmp6_m = &rte_flow_item_icmp6_mask;
7732 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7733 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7734 icmp6_v->type & icmp6_m->type);
7735 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7736 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7737 icmp6_v->code & icmp6_m->code);
7741 * Add ICMP item to matcher and to the value.
7743 * @param[in, out] matcher
7745 * @param[in, out] key
7746 * Flow matcher value.
7748 * Flow pattern to translate.
7750 * Item is inner pattern.
7753 flow_dv_translate_item_icmp(void *matcher, void *key,
7754 const struct rte_flow_item *item,
7757 const struct rte_flow_item_icmp *icmp_m = item->mask;
7758 const struct rte_flow_item_icmp *icmp_v = item->spec;
7759 uint32_t icmp_header_data_m = 0;
7760 uint32_t icmp_header_data_v = 0;
7763 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7765 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7767 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7769 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7771 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7773 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7775 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7776 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7780 icmp_m = &rte_flow_item_icmp_mask;
7781 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7782 icmp_m->hdr.icmp_type);
7783 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7784 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7785 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7786 icmp_m->hdr.icmp_code);
7787 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7788 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7789 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7790 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7791 if (icmp_header_data_m) {
7792 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7793 icmp_header_data_v |=
7794 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7795 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7796 icmp_header_data_m);
7797 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7798 icmp_header_data_v & icmp_header_data_m);
7803 * Add GTP item to matcher and to the value.
7805 * @param[in, out] matcher
7807 * @param[in, out] key
7808 * Flow matcher value.
7810 * Flow pattern to translate.
7812 * Item is inner pattern.
7815 flow_dv_translate_item_gtp(void *matcher, void *key,
7816 const struct rte_flow_item *item, int inner)
7818 const struct rte_flow_item_gtp *gtp_m = item->mask;
7819 const struct rte_flow_item_gtp *gtp_v = item->spec;
7822 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7824 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7825 uint16_t dport = RTE_GTPU_UDP_PORT;
7828 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7830 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7832 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7834 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7836 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7837 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7838 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7843 gtp_m = &rte_flow_item_gtp_mask;
7844 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7845 gtp_m->v_pt_rsv_flags);
7846 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7847 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7848 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7849 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7850 gtp_v->msg_type & gtp_m->msg_type);
7851 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7852 rte_be_to_cpu_32(gtp_m->teid));
7853 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7854 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7858 * Add eCPRI item to matcher and to the value.
7861 * The devich to configure through.
7862 * @param[in, out] matcher
7864 * @param[in, out] key
7865 * Flow matcher value.
7867 * Flow pattern to translate.
7868 * @param[in] samples
7869 * Sample IDs to be used in the matching.
7872 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7873 void *key, const struct rte_flow_item *item)
7875 struct mlx5_priv *priv = dev->data->dev_private;
7876 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7877 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7878 struct rte_ecpri_common_hdr common;
7879 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7881 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7889 ecpri_m = &rte_flow_item_ecpri_mask;
7891 * Maximal four DW samples are supported in a single matching now.
7892 * Two are used now for a eCPRI matching:
7893 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7894 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7897 if (!ecpri_m->hdr.common.u32)
7899 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7900 /* Need to take the whole DW as the mask to fill the entry. */
7901 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7902 prog_sample_field_value_0);
7903 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7904 prog_sample_field_value_0);
7905 /* Already big endian (network order) in the header. */
7906 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7907 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
7908 /* Sample#0, used for matching type, offset 0. */
7909 MLX5_SET(fte_match_set_misc4, misc4_m,
7910 prog_sample_field_id_0, samples[0]);
7911 /* It makes no sense to set the sample ID in the mask field. */
7912 MLX5_SET(fte_match_set_misc4, misc4_v,
7913 prog_sample_field_id_0, samples[0]);
7915 * Checking if message body part needs to be matched.
7916 * Some wildcard rules only matching type field should be supported.
7918 if (ecpri_m->hdr.dummy[0]) {
7919 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
7920 switch (common.type) {
7921 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7922 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7923 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7924 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7925 prog_sample_field_value_1);
7926 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7927 prog_sample_field_value_1);
7928 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7929 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
7930 ecpri_m->hdr.dummy[0];
7931 /* Sample#1, to match message body, offset 4. */
7932 MLX5_SET(fte_match_set_misc4, misc4_m,
7933 prog_sample_field_id_1, samples[1]);
7934 MLX5_SET(fte_match_set_misc4, misc4_v,
7935 prog_sample_field_id_1, samples[1]);
7938 /* Others, do not match any sample ID. */
7944 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7946 #define HEADER_IS_ZERO(match_criteria, headers) \
7947 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7948 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7951 * Calculate flow matcher enable bitmap.
7953 * @param match_criteria
7954 * Pointer to flow matcher criteria.
7957 * Bitmap of enabled fields.
7960 flow_dv_matcher_enable(uint32_t *match_criteria)
7962 uint8_t match_criteria_enable;
7964 match_criteria_enable =
7965 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7966 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7967 match_criteria_enable |=
7968 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7969 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7970 match_criteria_enable |=
7971 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7972 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7973 match_criteria_enable |=
7974 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7975 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7976 match_criteria_enable |=
7977 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7978 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7979 match_criteria_enable |=
7980 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7981 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7982 return match_criteria_enable;
7985 struct mlx5_hlist_entry *
7986 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
7988 struct mlx5_dev_ctx_shared *sh = list->ctx;
7989 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
7990 struct rte_eth_dev *dev = ctx->dev;
7991 struct mlx5_flow_tbl_data_entry *tbl_data;
7992 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
7993 struct rte_flow_error *error = ctx->error;
7994 union mlx5_flow_tbl_key key = { .v64 = key64 };
7995 struct mlx5_flow_tbl_resource *tbl;
8000 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8002 rte_flow_error_set(error, ENOMEM,
8003 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8005 "cannot allocate flow table data entry");
8008 tbl_data->idx = idx;
8009 tbl_data->tunnel = tt_prm->tunnel;
8010 tbl_data->group_id = tt_prm->group_id;
8011 tbl_data->external = !!tt_prm->external;
8012 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8013 tbl_data->is_egress = !!key.direction;
8014 tbl_data->is_transfer = !!key.domain;
8015 tbl_data->dummy = !!key.dummy;
8016 tbl_data->table_id = key.table_id;
8017 tbl = &tbl_data->tbl;
8019 return &tbl_data->entry;
8021 domain = sh->fdb_domain;
8022 else if (key.direction)
8023 domain = sh->tx_domain;
8025 domain = sh->rx_domain;
8026 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8028 rte_flow_error_set(error, ENOMEM,
8029 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8030 NULL, "cannot create flow table object");
8031 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8035 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8036 (tbl->obj, &tbl_data->jump.action);
8038 rte_flow_error_set(error, ENOMEM,
8039 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8041 "cannot create flow jump action");
8042 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8043 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8047 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8048 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8050 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8051 flow_dv_matcher_create_cb,
8052 flow_dv_matcher_match_cb,
8053 flow_dv_matcher_remove_cb);
8054 return &tbl_data->entry;
8058 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8059 struct mlx5_hlist_entry *entry, uint64_t key64,
8060 void *cb_ctx __rte_unused)
8062 struct mlx5_flow_tbl_data_entry *tbl_data =
8063 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8064 union mlx5_flow_tbl_key key = { .v64 = key64 };
8066 return tbl_data->table_id != key.table_id ||
8067 tbl_data->dummy != key.dummy ||
8068 tbl_data->is_transfer != key.domain ||
8069 tbl_data->is_egress != key.direction;
8075 * @param[in, out] dev
8076 * Pointer to rte_eth_dev structure.
8077 * @param[in] table_id
8080 * Direction of the table.
8081 * @param[in] transfer
8082 * E-Switch or NIC flow.
8084 * Dummy entry for dv API.
8086 * pointer to error structure.
8089 * Returns tables resource based on the index, NULL in case of failed.
8091 struct mlx5_flow_tbl_resource *
8092 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8093 uint32_t table_id, uint8_t egress,
8096 const struct mlx5_flow_tunnel *tunnel,
8097 uint32_t group_id, uint8_t dummy,
8098 struct rte_flow_error *error)
8100 struct mlx5_priv *priv = dev->data->dev_private;
8101 union mlx5_flow_tbl_key table_key = {
8103 .table_id = table_id,
8105 .domain = !!transfer,
8106 .direction = !!egress,
8109 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8111 .group_id = group_id,
8112 .external = external,
8114 struct mlx5_flow_cb_ctx ctx = {
8119 struct mlx5_hlist_entry *entry;
8120 struct mlx5_flow_tbl_data_entry *tbl_data;
8122 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8124 rte_flow_error_set(error, ENOMEM,
8125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8126 "cannot get table");
8129 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8130 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8131 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8132 return &tbl_data->tbl;
8136 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8137 struct mlx5_hlist_entry *entry)
8139 struct mlx5_dev_ctx_shared *sh = list->ctx;
8140 struct mlx5_flow_tbl_data_entry *tbl_data =
8141 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8143 MLX5_ASSERT(entry && sh);
8144 if (tbl_data->jump.action)
8145 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8146 if (tbl_data->tbl.obj)
8147 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8148 if (tbl_data->tunnel_offload && tbl_data->external) {
8149 struct mlx5_hlist_entry *he;
8150 struct mlx5_hlist *tunnel_grp_hash;
8151 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8152 union tunnel_tbl_key tunnel_key = {
8153 .tunnel_id = tbl_data->tunnel ?
8154 tbl_data->tunnel->tunnel_id : 0,
8155 .group = tbl_data->group_id
8157 uint32_t table_id = tbl_data->table_id;
8159 tunnel_grp_hash = tbl_data->tunnel ?
8160 tbl_data->tunnel->groups :
8162 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8164 mlx5_hlist_unregister(tunnel_grp_hash, he);
8166 "Table_id %u tunnel %u group %u released.",
8169 tbl_data->tunnel->tunnel_id : 0,
8170 tbl_data->group_id);
8172 mlx5_cache_list_destroy(&tbl_data->matchers);
8173 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8177 * Release a flow table.
8180 * Pointer to device shared structure.
8182 * Table resource to be released.
8185 * Returns 0 if table was released, else return 1;
8188 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8189 struct mlx5_flow_tbl_resource *tbl)
8191 struct mlx5_flow_tbl_data_entry *tbl_data =
8192 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8196 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8200 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8201 struct mlx5_cache_entry *entry, void *cb_ctx)
8203 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8204 struct mlx5_flow_dv_matcher *ref = ctx->data;
8205 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8208 return cur->crc != ref->crc ||
8209 cur->priority != ref->priority ||
8210 memcmp((const void *)cur->mask.buf,
8211 (const void *)ref->mask.buf, ref->mask.size);
8214 struct mlx5_cache_entry *
8215 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8216 struct mlx5_cache_entry *entry __rte_unused,
8219 struct mlx5_dev_ctx_shared *sh = list->ctx;
8220 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8221 struct mlx5_flow_dv_matcher *ref = ctx->data;
8222 struct mlx5_flow_dv_matcher *cache;
8223 struct mlx5dv_flow_matcher_attr dv_attr = {
8224 .type = IBV_FLOW_ATTR_NORMAL,
8225 .match_mask = (void *)&ref->mask,
8227 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8231 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8233 rte_flow_error_set(ctx->error, ENOMEM,
8234 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8235 "cannot create matcher");
8239 dv_attr.match_criteria_enable =
8240 flow_dv_matcher_enable(cache->mask.buf);
8241 dv_attr.priority = ref->priority;
8243 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8244 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8245 &cache->matcher_object);
8248 rte_flow_error_set(ctx->error, ENOMEM,
8249 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8250 "cannot create matcher");
8253 return &cache->entry;
8257 * Register the flow matcher.
8259 * @param[in, out] dev
8260 * Pointer to rte_eth_dev structure.
8261 * @param[in, out] matcher
8262 * Pointer to flow matcher.
8263 * @param[in, out] key
8264 * Pointer to flow table key.
8265 * @parm[in, out] dev_flow
8266 * Pointer to the dev_flow.
8268 * pointer to error structure.
8271 * 0 on success otherwise -errno and errno is set.
8274 flow_dv_matcher_register(struct rte_eth_dev *dev,
8275 struct mlx5_flow_dv_matcher *ref,
8276 union mlx5_flow_tbl_key *key,
8277 struct mlx5_flow *dev_flow,
8278 const struct mlx5_flow_tunnel *tunnel,
8280 struct rte_flow_error *error)
8282 struct mlx5_cache_entry *entry;
8283 struct mlx5_flow_dv_matcher *cache;
8284 struct mlx5_flow_tbl_resource *tbl;
8285 struct mlx5_flow_tbl_data_entry *tbl_data;
8286 struct mlx5_flow_cb_ctx ctx = {
8292 * tunnel offload API requires this registration for cases when
8293 * tunnel match rule was inserted before tunnel set rule.
8295 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8296 key->direction, key->domain,
8297 dev_flow->external, tunnel,
8298 group_id, 0, error);
8300 return -rte_errno; /* No need to refill the error info */
8301 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8303 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8305 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8306 return rte_flow_error_set(error, ENOMEM,
8307 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8308 "cannot allocate ref memory");
8310 cache = container_of(entry, typeof(*cache), entry);
8311 dev_flow->handle->dvh.matcher = cache;
8315 struct mlx5_hlist_entry *
8316 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8318 struct mlx5_dev_ctx_shared *sh = list->ctx;
8319 struct rte_flow_error *error = ctx;
8320 struct mlx5_flow_dv_tag_resource *entry;
8324 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8326 rte_flow_error_set(error, ENOMEM,
8327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8328 "cannot allocate resource memory");
8332 entry->tag_id = key;
8333 ret = mlx5_flow_os_create_flow_action_tag(key,
8336 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8337 rte_flow_error_set(error, ENOMEM,
8338 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8339 NULL, "cannot create action");
8342 return &entry->entry;
8346 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8347 struct mlx5_hlist_entry *entry, uint64_t key,
8348 void *cb_ctx __rte_unused)
8350 struct mlx5_flow_dv_tag_resource *tag =
8351 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8353 return key != tag->tag_id;
8357 * Find existing tag resource or create and register a new one.
8359 * @param dev[in, out]
8360 * Pointer to rte_eth_dev structure.
8361 * @param[in, out] tag_be24
8362 * Tag value in big endian then R-shift 8.
8363 * @parm[in, out] dev_flow
8364 * Pointer to the dev_flow.
8366 * pointer to error structure.
8369 * 0 on success otherwise -errno and errno is set.
8372 flow_dv_tag_resource_register
8373 (struct rte_eth_dev *dev,
8375 struct mlx5_flow *dev_flow,
8376 struct rte_flow_error *error)
8378 struct mlx5_priv *priv = dev->data->dev_private;
8379 struct mlx5_flow_dv_tag_resource *cache_resource;
8380 struct mlx5_hlist_entry *entry;
8382 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8384 cache_resource = container_of
8385 (entry, struct mlx5_flow_dv_tag_resource, entry);
8386 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8387 dev_flow->dv.tag_resource = cache_resource;
8394 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8395 struct mlx5_hlist_entry *entry)
8397 struct mlx5_dev_ctx_shared *sh = list->ctx;
8398 struct mlx5_flow_dv_tag_resource *tag =
8399 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8401 MLX5_ASSERT(tag && sh && tag->action);
8402 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8403 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8404 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8411 * Pointer to Ethernet device.
8416 * 1 while a reference on it exists, 0 when freed.
8419 flow_dv_tag_release(struct rte_eth_dev *dev,
8422 struct mlx5_priv *priv = dev->data->dev_private;
8423 struct mlx5_flow_dv_tag_resource *tag;
8425 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8428 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8429 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8430 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8434 * Translate port ID action to vport.
8437 * Pointer to rte_eth_dev structure.
8439 * Pointer to the port ID action.
8440 * @param[out] dst_port_id
8441 * The target port ID.
8443 * Pointer to the error structure.
8446 * 0 on success, a negative errno value otherwise and rte_errno is set.
8449 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8450 const struct rte_flow_action *action,
8451 uint32_t *dst_port_id,
8452 struct rte_flow_error *error)
8455 struct mlx5_priv *priv;
8456 const struct rte_flow_action_port_id *conf =
8457 (const struct rte_flow_action_port_id *)action->conf;
8459 port = conf->original ? dev->data->port_id : conf->id;
8460 priv = mlx5_port_to_eswitch_info(port, false);
8462 return rte_flow_error_set(error, -rte_errno,
8463 RTE_FLOW_ERROR_TYPE_ACTION,
8465 "No eswitch info was found for port");
8466 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8468 * This parameter is transferred to
8469 * mlx5dv_dr_action_create_dest_ib_port().
8471 *dst_port_id = priv->dev_port;
8474 * Legacy mode, no LAG configurations is supported.
8475 * This parameter is transferred to
8476 * mlx5dv_dr_action_create_dest_vport().
8478 *dst_port_id = priv->vport_id;
8484 * Create a counter with aging configuration.
8487 * Pointer to rte_eth_dev structure.
8489 * Pointer to the counter action configuration.
8491 * Pointer to the aging action configuration.
8494 * Index to flow counter on success, 0 otherwise.
8497 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8498 struct mlx5_flow *dev_flow,
8499 const struct rte_flow_action_count *count,
8500 const struct rte_flow_action_age *age)
8503 struct mlx5_age_param *age_param;
8505 if (count && count->shared)
8506 counter = flow_dv_counter_get_shared(dev, count->id);
8508 counter = flow_dv_counter_alloc(dev, !!age);
8509 if (!counter || age == NULL)
8511 age_param = flow_dv_counter_idx_get_age(dev, counter);
8512 age_param->context = age->context ? age->context :
8513 (void *)(uintptr_t)(dev_flow->flow_idx);
8514 age_param->timeout = age->timeout;
8515 age_param->port_id = dev->data->port_id;
8516 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8517 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8522 * Add Tx queue matcher
8525 * Pointer to the dev struct.
8526 * @param[in, out] matcher
8528 * @param[in, out] key
8529 * Flow matcher value.
8531 * Flow pattern to translate.
8533 * Item is inner pattern.
8536 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8537 void *matcher, void *key,
8538 const struct rte_flow_item *item)
8540 const struct mlx5_rte_flow_item_tx_queue *queue_m;
8541 const struct mlx5_rte_flow_item_tx_queue *queue_v;
8543 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8545 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8546 struct mlx5_txq_ctrl *txq;
8550 queue_m = (const void *)item->mask;
8553 queue_v = (const void *)item->spec;
8556 txq = mlx5_txq_get(dev, queue_v->queue);
8559 queue = txq->obj->sq->id;
8560 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8561 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8562 queue & queue_m->queue);
8563 mlx5_txq_release(dev, queue_v->queue);
8567 * Set the hash fields according to the @p flow information.
8569 * @param[in] dev_flow
8570 * Pointer to the mlx5_flow.
8571 * @param[in] rss_desc
8572 * Pointer to the mlx5_flow_rss_desc.
8575 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8576 struct mlx5_flow_rss_desc *rss_desc)
8578 uint64_t items = dev_flow->handle->layers;
8580 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8582 dev_flow->hash_fields = 0;
8583 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8584 if (rss_desc->level >= 2) {
8585 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8589 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8590 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8591 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8592 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8593 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8594 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8595 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8597 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8599 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8600 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8601 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8602 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8603 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8604 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8605 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8607 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8610 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8611 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8612 if (rss_types & ETH_RSS_UDP) {
8613 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8614 dev_flow->hash_fields |=
8615 IBV_RX_HASH_SRC_PORT_UDP;
8616 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8617 dev_flow->hash_fields |=
8618 IBV_RX_HASH_DST_PORT_UDP;
8620 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8622 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8623 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8624 if (rss_types & ETH_RSS_TCP) {
8625 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8626 dev_flow->hash_fields |=
8627 IBV_RX_HASH_SRC_PORT_TCP;
8628 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8629 dev_flow->hash_fields |=
8630 IBV_RX_HASH_DST_PORT_TCP;
8632 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8638 * Prepare an Rx Hash queue.
8641 * Pointer to Ethernet device.
8642 * @param[in] dev_flow
8643 * Pointer to the mlx5_flow.
8644 * @param[in] rss_desc
8645 * Pointer to the mlx5_flow_rss_desc.
8646 * @param[out] hrxq_idx
8647 * Hash Rx queue index.
8650 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8652 static struct mlx5_hrxq *
8653 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8654 struct mlx5_flow *dev_flow,
8655 struct mlx5_flow_rss_desc *rss_desc,
8658 struct mlx5_priv *priv = dev->data->dev_private;
8659 struct mlx5_flow_handle *dh = dev_flow->handle;
8660 struct mlx5_hrxq *hrxq;
8662 MLX5_ASSERT(rss_desc->queue_num);
8663 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8664 rss_desc->hash_fields = dev_flow->hash_fields;
8665 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8666 rss_desc->shared_rss = 0;
8667 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8670 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8676 * Release sample sub action resource.
8678 * @param[in, out] dev
8679 * Pointer to rte_eth_dev structure.
8680 * @param[in] act_res
8681 * Pointer to sample sub action resource.
8684 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8685 struct mlx5_flow_sub_actions_idx *act_res)
8687 if (act_res->rix_hrxq) {
8688 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8689 act_res->rix_hrxq = 0;
8691 if (act_res->rix_encap_decap) {
8692 flow_dv_encap_decap_resource_release(dev,
8693 act_res->rix_encap_decap);
8694 act_res->rix_encap_decap = 0;
8696 if (act_res->rix_port_id_action) {
8697 flow_dv_port_id_action_resource_release(dev,
8698 act_res->rix_port_id_action);
8699 act_res->rix_port_id_action = 0;
8701 if (act_res->rix_tag) {
8702 flow_dv_tag_release(dev, act_res->rix_tag);
8703 act_res->rix_tag = 0;
8706 flow_dv_counter_free(dev, act_res->cnt);
8712 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8713 struct mlx5_cache_entry *entry, void *cb_ctx)
8715 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8716 struct rte_eth_dev *dev = ctx->dev;
8717 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8718 struct mlx5_flow_dv_sample_resource *cache_resource =
8719 container_of(entry, typeof(*cache_resource), entry);
8721 if (resource->ratio == cache_resource->ratio &&
8722 resource->ft_type == cache_resource->ft_type &&
8723 resource->ft_id == cache_resource->ft_id &&
8724 resource->set_action == cache_resource->set_action &&
8725 !memcmp((void *)&resource->sample_act,
8726 (void *)&cache_resource->sample_act,
8727 sizeof(struct mlx5_flow_sub_actions_list))) {
8729 * Existing sample action should release the prepared
8730 * sub-actions reference counter.
8732 flow_dv_sample_sub_actions_release(dev,
8733 &resource->sample_idx);
8739 struct mlx5_cache_entry *
8740 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8741 struct mlx5_cache_entry *entry __rte_unused,
8744 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8745 struct rte_eth_dev *dev = ctx->dev;
8746 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8747 void **sample_dv_actions = resource->sub_actions;
8748 struct mlx5_flow_dv_sample_resource *cache_resource;
8749 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8750 struct mlx5_priv *priv = dev->data->dev_private;
8751 struct mlx5_dev_ctx_shared *sh = priv->sh;
8752 struct mlx5_flow_tbl_resource *tbl;
8754 const uint32_t next_ft_step = 1;
8755 uint32_t next_ft_id = resource->ft_id + next_ft_step;
8756 uint8_t is_egress = 0;
8757 uint8_t is_transfer = 0;
8758 struct rte_flow_error *error = ctx->error;
8760 /* Register new sample resource. */
8761 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
8762 if (!cache_resource) {
8763 rte_flow_error_set(error, ENOMEM,
8764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8766 "cannot allocate resource memory");
8769 *cache_resource = *resource;
8770 /* Create normal path table level */
8771 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8773 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
8775 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8776 is_egress, is_transfer,
8777 true, NULL, 0, 0, error);
8779 rte_flow_error_set(error, ENOMEM,
8780 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8782 "fail to create normal path table "
8788 cache_resource->normal_path_tbl = tbl;
8789 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8790 ret = mlx5_flow_os_create_flow_action_default_miss
8791 (&cache_resource->default_miss);
8793 rte_flow_error_set(error, ENOMEM,
8794 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8796 "cannot create default miss "
8800 sample_dv_actions[resource->sample_act.actions_num++] =
8801 cache_resource->default_miss;
8803 /* Create a DR sample action */
8804 sampler_attr.sample_ratio = cache_resource->ratio;
8805 sampler_attr.default_next_table = tbl->obj;
8806 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8807 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8808 &sample_dv_actions[0];
8809 sampler_attr.action = cache_resource->set_action;
8810 cache_resource->verbs_action =
8811 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8812 if (!cache_resource->verbs_action) {
8813 rte_flow_error_set(error, ENOMEM,
8814 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8815 NULL, "cannot create sample action");
8818 cache_resource->idx = idx;
8819 cache_resource->dev = dev;
8820 return &cache_resource->entry;
8822 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
8823 cache_resource->default_miss)
8824 claim_zero(mlx5_glue->destroy_flow_action
8825 (cache_resource->default_miss));
8827 flow_dv_sample_sub_actions_release(dev,
8828 &cache_resource->sample_idx);
8829 if (cache_resource->normal_path_tbl)
8830 flow_dv_tbl_resource_release(MLX5_SH(dev),
8831 cache_resource->normal_path_tbl);
8832 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
8838 * Find existing sample resource or create and register a new one.
8840 * @param[in, out] dev
8841 * Pointer to rte_eth_dev structure.
8842 * @param[in] resource
8843 * Pointer to sample resource.
8844 * @parm[in, out] dev_flow
8845 * Pointer to the dev_flow.
8847 * pointer to error structure.
8850 * 0 on success otherwise -errno and errno is set.
8853 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8854 struct mlx5_flow_dv_sample_resource *resource,
8855 struct mlx5_flow *dev_flow,
8856 struct rte_flow_error *error)
8858 struct mlx5_flow_dv_sample_resource *cache_resource;
8859 struct mlx5_cache_entry *entry;
8860 struct mlx5_priv *priv = dev->data->dev_private;
8861 struct mlx5_flow_cb_ctx ctx = {
8867 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
8870 cache_resource = container_of(entry, typeof(*cache_resource), entry);
8871 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
8872 dev_flow->dv.sample_res = cache_resource;
8877 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
8878 struct mlx5_cache_entry *entry, void *cb_ctx)
8880 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8881 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8882 struct rte_eth_dev *dev = ctx->dev;
8883 struct mlx5_flow_dv_dest_array_resource *cache_resource =
8884 container_of(entry, typeof(*cache_resource), entry);
8887 if (resource->num_of_dest == cache_resource->num_of_dest &&
8888 resource->ft_type == cache_resource->ft_type &&
8889 !memcmp((void *)cache_resource->sample_act,
8890 (void *)resource->sample_act,
8891 (resource->num_of_dest *
8892 sizeof(struct mlx5_flow_sub_actions_list)))) {
8894 * Existing sample action should release the prepared
8895 * sub-actions reference counter.
8897 for (idx = 0; idx < resource->num_of_dest; idx++)
8898 flow_dv_sample_sub_actions_release(dev,
8899 &resource->sample_idx[idx]);
8905 struct mlx5_cache_entry *
8906 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
8907 struct mlx5_cache_entry *entry __rte_unused,
8910 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8911 struct rte_eth_dev *dev = ctx->dev;
8912 struct mlx5_flow_dv_dest_array_resource *cache_resource;
8913 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8914 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8915 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8916 struct mlx5_priv *priv = dev->data->dev_private;
8917 struct mlx5_dev_ctx_shared *sh = priv->sh;
8918 struct mlx5_flow_sub_actions_list *sample_act;
8919 struct mlx5dv_dr_domain *domain;
8920 uint32_t idx = 0, res_idx = 0;
8921 struct rte_flow_error *error = ctx->error;
8923 /* Register new destination array resource. */
8924 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8926 if (!cache_resource) {
8927 rte_flow_error_set(error, ENOMEM,
8928 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8930 "cannot allocate resource memory");
8933 *cache_resource = *resource;
8934 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8935 domain = sh->fdb_domain;
8936 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
8937 domain = sh->rx_domain;
8939 domain = sh->tx_domain;
8940 for (idx = 0; idx < resource->num_of_dest; idx++) {
8941 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8942 mlx5_malloc(MLX5_MEM_ZERO,
8943 sizeof(struct mlx5dv_dr_action_dest_attr),
8945 if (!dest_attr[idx]) {
8946 rte_flow_error_set(error, ENOMEM,
8947 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8949 "cannot allocate resource memory");
8952 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8953 sample_act = &resource->sample_act[idx];
8954 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8955 dest_attr[idx]->dest = sample_act->dr_queue_action;
8956 } else if (sample_act->action_flags ==
8957 (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8958 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8959 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8960 dest_attr[idx]->dest_reformat->reformat =
8961 sample_act->dr_encap_action;
8962 dest_attr[idx]->dest_reformat->dest =
8963 sample_act->dr_port_id_action;
8964 } else if (sample_act->action_flags ==
8965 MLX5_FLOW_ACTION_PORT_ID) {
8966 dest_attr[idx]->dest = sample_act->dr_port_id_action;
8969 /* create a dest array actioin */
8970 cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8972 cache_resource->num_of_dest,
8974 if (!cache_resource->action) {
8975 rte_flow_error_set(error, ENOMEM,
8976 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8978 "cannot create destination array action");
8981 cache_resource->idx = res_idx;
8982 cache_resource->dev = dev;
8983 for (idx = 0; idx < resource->num_of_dest; idx++)
8984 mlx5_free(dest_attr[idx]);
8985 return &cache_resource->entry;
8987 for (idx = 0; idx < resource->num_of_dest; idx++) {
8988 struct mlx5_flow_sub_actions_idx *act_res =
8989 &cache_resource->sample_idx[idx];
8990 if (act_res->rix_hrxq &&
8991 !mlx5_hrxq_release(dev,
8993 act_res->rix_hrxq = 0;
8994 if (act_res->rix_encap_decap &&
8995 !flow_dv_encap_decap_resource_release(dev,
8996 act_res->rix_encap_decap))
8997 act_res->rix_encap_decap = 0;
8998 if (act_res->rix_port_id_action &&
8999 !flow_dv_port_id_action_resource_release(dev,
9000 act_res->rix_port_id_action))
9001 act_res->rix_port_id_action = 0;
9003 mlx5_free(dest_attr[idx]);
9006 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9011 * Find existing destination array resource or create and register a new one.
9013 * @param[in, out] dev
9014 * Pointer to rte_eth_dev structure.
9015 * @param[in] resource
9016 * Pointer to destination array resource.
9017 * @parm[in, out] dev_flow
9018 * Pointer to the dev_flow.
9020 * pointer to error structure.
9023 * 0 on success otherwise -errno and errno is set.
9026 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9027 struct mlx5_flow_dv_dest_array_resource *resource,
9028 struct mlx5_flow *dev_flow,
9029 struct rte_flow_error *error)
9031 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9032 struct mlx5_priv *priv = dev->data->dev_private;
9033 struct mlx5_cache_entry *entry;
9034 struct mlx5_flow_cb_ctx ctx = {
9040 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9043 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9044 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9045 dev_flow->dv.dest_array_res = cache_resource;
9050 * Convert Sample action to DV specification.
9053 * Pointer to rte_eth_dev structure.
9055 * Pointer to action structure.
9056 * @param[in, out] dev_flow
9057 * Pointer to the mlx5_flow.
9059 * Pointer to the flow attributes.
9060 * @param[in, out] num_of_dest
9061 * Pointer to the num of destination.
9062 * @param[in, out] sample_actions
9063 * Pointer to sample actions list.
9064 * @param[in, out] res
9065 * Pointer to sample resource.
9067 * Pointer to the error structure.
9070 * 0 on success, a negative errno value otherwise and rte_errno is set.
9073 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9074 const struct rte_flow_action *action,
9075 struct mlx5_flow *dev_flow,
9076 const struct rte_flow_attr *attr,
9077 uint32_t *num_of_dest,
9078 void **sample_actions,
9079 struct mlx5_flow_dv_sample_resource *res,
9080 struct rte_flow_error *error)
9082 struct mlx5_priv *priv = dev->data->dev_private;
9083 const struct rte_flow_action_sample *sample_action;
9084 const struct rte_flow_action *sub_actions;
9085 const struct rte_flow_action_queue *queue;
9086 struct mlx5_flow_sub_actions_list *sample_act;
9087 struct mlx5_flow_sub_actions_idx *sample_idx;
9088 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9089 struct mlx5_flow_rss_desc *rss_desc;
9090 uint64_t action_flags = 0;
9093 rss_desc = &wks->rss_desc;
9094 sample_act = &res->sample_act;
9095 sample_idx = &res->sample_idx;
9096 sample_action = (const struct rte_flow_action_sample *)action->conf;
9097 res->ratio = sample_action->ratio;
9098 sub_actions = sample_action->actions;
9099 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9100 int type = sub_actions->type;
9101 uint32_t pre_rix = 0;
9104 case RTE_FLOW_ACTION_TYPE_QUEUE:
9106 struct mlx5_hrxq *hrxq;
9109 queue = sub_actions->conf;
9110 rss_desc->queue_num = 1;
9111 rss_desc->queue[0] = queue->index;
9112 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9113 rss_desc, &hrxq_idx);
9115 return rte_flow_error_set
9117 RTE_FLOW_ERROR_TYPE_ACTION,
9119 "cannot create fate queue");
9120 sample_act->dr_queue_action = hrxq->action;
9121 sample_idx->rix_hrxq = hrxq_idx;
9122 sample_actions[sample_act->actions_num++] =
9125 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9126 if (action_flags & MLX5_FLOW_ACTION_MARK)
9127 dev_flow->handle->rix_hrxq = hrxq_idx;
9128 dev_flow->handle->fate_action =
9129 MLX5_FLOW_FATE_QUEUE;
9132 case RTE_FLOW_ACTION_TYPE_MARK:
9134 uint32_t tag_be = mlx5_flow_mark_set
9135 (((const struct rte_flow_action_mark *)
9136 (sub_actions->conf))->id);
9138 dev_flow->handle->mark = 1;
9139 pre_rix = dev_flow->handle->dvh.rix_tag;
9140 /* Save the mark resource before sample */
9141 pre_r = dev_flow->dv.tag_resource;
9142 if (flow_dv_tag_resource_register(dev, tag_be,
9145 MLX5_ASSERT(dev_flow->dv.tag_resource);
9146 sample_act->dr_tag_action =
9147 dev_flow->dv.tag_resource->action;
9148 sample_idx->rix_tag =
9149 dev_flow->handle->dvh.rix_tag;
9150 sample_actions[sample_act->actions_num++] =
9151 sample_act->dr_tag_action;
9152 /* Recover the mark resource after sample */
9153 dev_flow->dv.tag_resource = pre_r;
9154 dev_flow->handle->dvh.rix_tag = pre_rix;
9155 action_flags |= MLX5_FLOW_ACTION_MARK;
9158 case RTE_FLOW_ACTION_TYPE_COUNT:
9162 counter = flow_dv_translate_create_counter(dev,
9163 dev_flow, sub_actions->conf, 0);
9165 return rte_flow_error_set
9167 RTE_FLOW_ERROR_TYPE_ACTION,
9169 "cannot create counter"
9171 sample_idx->cnt = counter;
9172 sample_act->dr_cnt_action =
9173 (flow_dv_counter_get_by_idx(dev,
9174 counter, NULL))->action;
9175 sample_actions[sample_act->actions_num++] =
9176 sample_act->dr_cnt_action;
9177 action_flags |= MLX5_FLOW_ACTION_COUNT;
9180 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9182 struct mlx5_flow_dv_port_id_action_resource
9184 uint32_t port_id = 0;
9186 memset(&port_id_resource, 0, sizeof(port_id_resource));
9187 /* Save the port id resource before sample */
9188 pre_rix = dev_flow->handle->rix_port_id_action;
9189 pre_r = dev_flow->dv.port_id_action;
9190 if (flow_dv_translate_action_port_id(dev, sub_actions,
9193 port_id_resource.port_id = port_id;
9194 if (flow_dv_port_id_action_resource_register
9195 (dev, &port_id_resource, dev_flow, error))
9197 sample_act->dr_port_id_action =
9198 dev_flow->dv.port_id_action->action;
9199 sample_idx->rix_port_id_action =
9200 dev_flow->handle->rix_port_id_action;
9201 sample_actions[sample_act->actions_num++] =
9202 sample_act->dr_port_id_action;
9203 /* Recover the port id resource after sample */
9204 dev_flow->dv.port_id_action = pre_r;
9205 dev_flow->handle->rix_port_id_action = pre_rix;
9207 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9210 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9211 /* Save the encap resource before sample */
9212 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9213 pre_r = dev_flow->dv.encap_decap;
9214 if (flow_dv_create_action_l2_encap(dev, sub_actions,
9219 sample_act->dr_encap_action =
9220 dev_flow->dv.encap_decap->action;
9221 sample_idx->rix_encap_decap =
9222 dev_flow->handle->dvh.rix_encap_decap;
9223 sample_actions[sample_act->actions_num++] =
9224 sample_act->dr_encap_action;
9225 /* Recover the encap resource after sample */
9226 dev_flow->dv.encap_decap = pre_r;
9227 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9228 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9231 return rte_flow_error_set(error, EINVAL,
9232 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9234 "Not support for sampler action");
9237 sample_act->action_flags = action_flags;
9238 res->ft_id = dev_flow->dv.group;
9239 if (attr->transfer) {
9241 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9242 uint64_t set_action;
9243 } action_ctx = { .set_action = 0 };
9245 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9246 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9247 MLX5_MODIFICATION_TYPE_SET);
9248 MLX5_SET(set_action_in, action_ctx.action_in, field,
9249 MLX5_MODI_META_REG_C_0);
9250 MLX5_SET(set_action_in, action_ctx.action_in, data,
9251 priv->vport_meta_tag);
9252 res->set_action = action_ctx.set_action;
9253 } else if (attr->ingress) {
9254 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9256 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9262 * Convert Sample action to DV specification.
9265 * Pointer to rte_eth_dev structure.
9266 * @param[in, out] dev_flow
9267 * Pointer to the mlx5_flow.
9268 * @param[in] num_of_dest
9269 * The num of destination.
9270 * @param[in, out] res
9271 * Pointer to sample resource.
9272 * @param[in, out] mdest_res
9273 * Pointer to destination array resource.
9274 * @param[in] sample_actions
9275 * Pointer to sample path actions list.
9276 * @param[in] action_flags
9277 * Holds the actions detected until now.
9279 * Pointer to the error structure.
9282 * 0 on success, a negative errno value otherwise and rte_errno is set.
9285 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9286 struct mlx5_flow *dev_flow,
9287 uint32_t num_of_dest,
9288 struct mlx5_flow_dv_sample_resource *res,
9289 struct mlx5_flow_dv_dest_array_resource *mdest_res,
9290 void **sample_actions,
9291 uint64_t action_flags,
9292 struct rte_flow_error *error)
9294 /* update normal path action resource into last index of array */
9295 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9296 struct mlx5_flow_sub_actions_list *sample_act =
9297 &mdest_res->sample_act[dest_index];
9298 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9299 struct mlx5_flow_rss_desc *rss_desc;
9300 uint32_t normal_idx = 0;
9301 struct mlx5_hrxq *hrxq;
9305 rss_desc = &wks->rss_desc;
9306 if (num_of_dest > 1) {
9307 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9308 /* Handle QP action for mirroring */
9309 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9310 rss_desc, &hrxq_idx);
9312 return rte_flow_error_set
9314 RTE_FLOW_ERROR_TYPE_ACTION,
9316 "cannot create rx queue");
9318 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9319 sample_act->dr_queue_action = hrxq->action;
9320 if (action_flags & MLX5_FLOW_ACTION_MARK)
9321 dev_flow->handle->rix_hrxq = hrxq_idx;
9322 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9324 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9326 mdest_res->sample_idx[dest_index].rix_encap_decap =
9327 dev_flow->handle->dvh.rix_encap_decap;
9328 sample_act->dr_encap_action =
9329 dev_flow->dv.encap_decap->action;
9331 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9333 mdest_res->sample_idx[dest_index].rix_port_id_action =
9334 dev_flow->handle->rix_port_id_action;
9335 sample_act->dr_port_id_action =
9336 dev_flow->dv.port_id_action->action;
9338 sample_act->actions_num = normal_idx;
9339 /* update sample action resource into first index of array */
9340 mdest_res->ft_type = res->ft_type;
9341 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9342 sizeof(struct mlx5_flow_sub_actions_idx));
9343 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9344 sizeof(struct mlx5_flow_sub_actions_list));
9345 mdest_res->num_of_dest = num_of_dest;
9346 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9348 return rte_flow_error_set(error, EINVAL,
9349 RTE_FLOW_ERROR_TYPE_ACTION,
9350 NULL, "can't create sample "
9353 res->sub_actions = sample_actions;
9354 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9355 return rte_flow_error_set(error, EINVAL,
9356 RTE_FLOW_ERROR_TYPE_ACTION,
9358 "can't create sample action");
9364 * Remove an ASO age action from age actions list.
9367 * Pointer to the Ethernet device structure.
9369 * Pointer to the aso age action handler.
9372 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9373 struct mlx5_aso_age_action *age)
9375 struct mlx5_age_info *age_info;
9376 struct mlx5_age_param *age_param = &age->age_params;
9377 struct mlx5_priv *priv = dev->data->dev_private;
9378 uint16_t expected = AGE_CANDIDATE;
9380 age_info = GET_PORT_AGE_INFO(priv);
9381 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9382 AGE_FREE, false, __ATOMIC_RELAXED,
9383 __ATOMIC_RELAXED)) {
9385 * We need the lock even it is age timeout,
9386 * since age action may still in process.
9388 rte_spinlock_lock(&age_info->aged_sl);
9389 LIST_REMOVE(age, next);
9390 rte_spinlock_unlock(&age_info->aged_sl);
9391 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9396 * Release an ASO age action.
9399 * Pointer to the Ethernet device structure.
9400 * @param[in] age_idx
9401 * Index of ASO age action to release.
9403 * True if the release operation is during flow destroy operation.
9404 * False if the release operation is during action destroy operation.
9407 * 0 when age action was removed, otherwise the number of references.
9410 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9412 struct mlx5_priv *priv = dev->data->dev_private;
9413 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9414 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9415 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9418 flow_dv_aso_age_remove_from_age(dev, age);
9419 rte_spinlock_lock(&mng->free_sl);
9420 LIST_INSERT_HEAD(&mng->free, age, next);
9421 rte_spinlock_unlock(&mng->free_sl);
9427 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9430 * Pointer to the Ethernet device structure.
9433 * 0 on success, otherwise negative errno value and rte_errno is set.
9436 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9438 struct mlx5_priv *priv = dev->data->dev_private;
9439 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9440 void *old_pools = mng->pools;
9441 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9442 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9443 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9450 memcpy(pools, old_pools,
9451 mng->n * sizeof(struct mlx5_flow_counter_pool *));
9452 mlx5_free(old_pools);
9454 /* First ASO flow hit allocation - starting ASO data-path. */
9455 int ret = mlx5_aso_queue_start(priv->sh);
9468 * Create and initialize a new ASO aging pool.
9471 * Pointer to the Ethernet device structure.
9472 * @param[out] age_free
9473 * Where to put the pointer of a new age action.
9476 * The age actions pool pointer and @p age_free is set on success,
9477 * NULL otherwise and rte_errno is set.
9479 static struct mlx5_aso_age_pool *
9480 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9481 struct mlx5_aso_age_action **age_free)
9483 struct mlx5_priv *priv = dev->data->dev_private;
9484 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9485 struct mlx5_aso_age_pool *pool = NULL;
9486 struct mlx5_devx_obj *obj = NULL;
9489 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9492 rte_errno = ENODATA;
9493 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9496 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9498 claim_zero(mlx5_devx_cmd_destroy(obj));
9502 pool->flow_hit_aso_obj = obj;
9503 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9504 rte_spinlock_lock(&mng->resize_sl);
9505 pool->index = mng->next;
9506 /* Resize pools array if there is no room for the new pool in it. */
9507 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9508 claim_zero(mlx5_devx_cmd_destroy(obj));
9510 rte_spinlock_unlock(&mng->resize_sl);
9513 mng->pools[pool->index] = pool;
9515 rte_spinlock_unlock(&mng->resize_sl);
9516 /* Assign the first action in the new pool, the rest go to free list. */
9517 *age_free = &pool->actions[0];
9518 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9519 pool->actions[i].offset = i;
9520 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9526 * Allocate a ASO aging bit.
9529 * Pointer to the Ethernet device structure.
9531 * Pointer to the error structure.
9534 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
9537 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9539 struct mlx5_priv *priv = dev->data->dev_private;
9540 const struct mlx5_aso_age_pool *pool;
9541 struct mlx5_aso_age_action *age_free = NULL;
9542 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9545 /* Try to get the next free age action bit. */
9546 rte_spinlock_lock(&mng->free_sl);
9547 age_free = LIST_FIRST(&mng->free);
9549 LIST_REMOVE(age_free, next);
9550 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9551 rte_spinlock_unlock(&mng->free_sl);
9552 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9553 NULL, "failed to create ASO age pool");
9554 return 0; /* 0 is an error. */
9556 rte_spinlock_unlock(&mng->free_sl);
9558 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9559 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9561 if (!age_free->dr_action) {
9562 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9566 rte_flow_error_set(error, rte_errno,
9567 RTE_FLOW_ERROR_TYPE_ACTION,
9568 NULL, "failed to get reg_c "
9569 "for ASO flow hit");
9570 return 0; /* 0 is an error. */
9572 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9573 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9574 (priv->sh->rx_domain,
9575 pool->flow_hit_aso_obj->obj, age_free->offset,
9576 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9578 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9579 if (!age_free->dr_action) {
9581 rte_spinlock_lock(&mng->free_sl);
9582 LIST_INSERT_HEAD(&mng->free, age_free, next);
9583 rte_spinlock_unlock(&mng->free_sl);
9584 rte_flow_error_set(error, rte_errno,
9585 RTE_FLOW_ERROR_TYPE_ACTION,
9586 NULL, "failed to create ASO "
9588 return 0; /* 0 is an error. */
9591 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9592 return pool->index | ((age_free->offset + 1) << 16);
9596 * Create a age action using ASO mechanism.
9599 * Pointer to rte_eth_dev structure.
9601 * Pointer to the aging action configuration.
9603 * Pointer to the error structure.
9606 * Index to flow counter on success, 0 otherwise.
9609 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9610 const struct rte_flow_action_age *age,
9611 struct rte_flow_error *error)
9613 uint32_t age_idx = 0;
9614 struct mlx5_aso_age_action *aso_age;
9616 age_idx = flow_dv_aso_age_alloc(dev, error);
9619 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9620 aso_age->age_params.context = age->context;
9621 aso_age->age_params.timeout = age->timeout;
9622 aso_age->age_params.port_id = dev->data->port_id;
9623 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9625 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9631 * Fill the flow with DV spec, lock free
9632 * (mutex should be acquired by caller).
9635 * Pointer to rte_eth_dev structure.
9636 * @param[in, out] dev_flow
9637 * Pointer to the sub flow.
9639 * Pointer to the flow attributes.
9641 * Pointer to the list of items.
9642 * @param[in] actions
9643 * Pointer to the list of actions.
9645 * Pointer to the error structure.
9648 * 0 on success, a negative errno value otherwise and rte_errno is set.
9651 flow_dv_translate(struct rte_eth_dev *dev,
9652 struct mlx5_flow *dev_flow,
9653 const struct rte_flow_attr *attr,
9654 const struct rte_flow_item items[],
9655 const struct rte_flow_action actions[],
9656 struct rte_flow_error *error)
9658 struct mlx5_priv *priv = dev->data->dev_private;
9659 struct mlx5_dev_config *dev_conf = &priv->config;
9660 struct rte_flow *flow = dev_flow->flow;
9661 struct mlx5_flow_handle *handle = dev_flow->handle;
9662 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9663 struct mlx5_flow_rss_desc *rss_desc;
9664 uint64_t item_flags = 0;
9665 uint64_t last_item = 0;
9666 uint64_t action_flags = 0;
9667 uint64_t priority = attr->priority;
9668 struct mlx5_flow_dv_matcher matcher = {
9670 .size = sizeof(matcher.mask.buf) -
9671 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9675 bool actions_end = false;
9677 struct mlx5_flow_dv_modify_hdr_resource res;
9678 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9679 sizeof(struct mlx5_modification_cmd) *
9680 (MLX5_MAX_MODIFY_NUM + 1)];
9682 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9683 const struct rte_flow_action_count *count = NULL;
9684 const struct rte_flow_action_age *age = NULL;
9685 union flow_dv_attr flow_attr = { .attr = 0 };
9687 union mlx5_flow_tbl_key tbl_key;
9688 uint32_t modify_action_position = UINT32_MAX;
9689 void *match_mask = matcher.mask.buf;
9690 void *match_value = dev_flow->dv.value.buf;
9691 uint8_t next_protocol = 0xff;
9692 struct rte_vlan_hdr vlan = { 0 };
9693 struct mlx5_flow_dv_dest_array_resource mdest_res;
9694 struct mlx5_flow_dv_sample_resource sample_res;
9695 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9696 struct mlx5_flow_sub_actions_list *sample_act;
9697 uint32_t sample_act_pos = UINT32_MAX;
9698 uint32_t num_of_dest = 0;
9699 int tmp_actions_n = 0;
9702 const struct mlx5_flow_tunnel *tunnel;
9703 struct flow_grp_info grp_info = {
9704 .external = !!dev_flow->external,
9705 .transfer = !!attr->transfer,
9706 .fdb_def_rule = !!priv->fdb_def_rule,
9707 .skip_scale = !!dev_flow->skip_scale,
9711 return rte_flow_error_set(error, ENOMEM,
9712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9714 "failed to push flow workspace");
9715 rss_desc = &wks->rss_desc;
9716 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9717 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9718 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9719 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9720 /* update normal path action resource into last index of array */
9721 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9722 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9723 flow_items_to_tunnel(items) :
9724 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9725 flow_actions_to_tunnel(actions) :
9726 dev_flow->tunnel ? dev_flow->tunnel : NULL;
9727 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9728 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9729 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9730 (dev, tunnel, attr, items, actions);
9731 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9735 dev_flow->dv.group = table;
9737 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9738 if (priority == MLX5_FLOW_PRIO_RSVD)
9739 priority = dev_conf->flow_prio - 1;
9740 /* number of actions must be set to 0 in case of dirty stack. */
9741 mhdr_res->actions_num = 0;
9742 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9744 * do not add decap action if match rule drops packet
9745 * HW rejects rules with decap & drop
9747 * if tunnel match rule was inserted before matching tunnel set
9748 * rule flow table used in the match rule must be registered.
9749 * current implementation handles that in the
9750 * flow_dv_match_register() at the function end.
9752 bool add_decap = true;
9753 const struct rte_flow_action *ptr = actions;
9755 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9756 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9762 if (flow_dv_create_action_l2_decap(dev, dev_flow,
9766 dev_flow->dv.actions[actions_n++] =
9767 dev_flow->dv.encap_decap->action;
9768 action_flags |= MLX5_FLOW_ACTION_DECAP;
9771 for (; !actions_end ; actions++) {
9772 const struct rte_flow_action_queue *queue;
9773 const struct rte_flow_action_rss *rss;
9774 const struct rte_flow_action *action = actions;
9775 const uint8_t *rss_key;
9776 const struct rte_flow_action_meter *mtr;
9777 struct mlx5_flow_tbl_resource *tbl;
9778 struct mlx5_aso_age_action *age_act;
9779 uint32_t port_id = 0;
9780 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9781 int action_type = actions->type;
9782 const struct rte_flow_action *found_action = NULL;
9783 struct mlx5_flow_meter *fm = NULL;
9784 uint32_t jump_group = 0;
9786 if (!mlx5_flow_os_action_supported(action_type))
9787 return rte_flow_error_set(error, ENOTSUP,
9788 RTE_FLOW_ERROR_TYPE_ACTION,
9790 "action not supported");
9791 switch (action_type) {
9792 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9793 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9795 case RTE_FLOW_ACTION_TYPE_VOID:
9797 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9798 if (flow_dv_translate_action_port_id(dev, action,
9801 port_id_resource.port_id = port_id;
9802 MLX5_ASSERT(!handle->rix_port_id_action);
9803 if (flow_dv_port_id_action_resource_register
9804 (dev, &port_id_resource, dev_flow, error))
9806 dev_flow->dv.actions[actions_n++] =
9807 dev_flow->dv.port_id_action->action;
9808 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9809 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9810 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9813 case RTE_FLOW_ACTION_TYPE_FLAG:
9814 action_flags |= MLX5_FLOW_ACTION_FLAG;
9815 dev_flow->handle->mark = 1;
9816 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9817 struct rte_flow_action_mark mark = {
9818 .id = MLX5_FLOW_MARK_DEFAULT,
9821 if (flow_dv_convert_action_mark(dev, &mark,
9825 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9828 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9830 * Only one FLAG or MARK is supported per device flow
9831 * right now. So the pointer to the tag resource must be
9832 * zero before the register process.
9834 MLX5_ASSERT(!handle->dvh.rix_tag);
9835 if (flow_dv_tag_resource_register(dev, tag_be,
9838 MLX5_ASSERT(dev_flow->dv.tag_resource);
9839 dev_flow->dv.actions[actions_n++] =
9840 dev_flow->dv.tag_resource->action;
9842 case RTE_FLOW_ACTION_TYPE_MARK:
9843 action_flags |= MLX5_FLOW_ACTION_MARK;
9844 dev_flow->handle->mark = 1;
9845 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9846 const struct rte_flow_action_mark *mark =
9847 (const struct rte_flow_action_mark *)
9850 if (flow_dv_convert_action_mark(dev, mark,
9854 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9858 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9859 /* Legacy (non-extensive) MARK action. */
9860 tag_be = mlx5_flow_mark_set
9861 (((const struct rte_flow_action_mark *)
9862 (actions->conf))->id);
9863 MLX5_ASSERT(!handle->dvh.rix_tag);
9864 if (flow_dv_tag_resource_register(dev, tag_be,
9867 MLX5_ASSERT(dev_flow->dv.tag_resource);
9868 dev_flow->dv.actions[actions_n++] =
9869 dev_flow->dv.tag_resource->action;
9871 case RTE_FLOW_ACTION_TYPE_SET_META:
9872 if (flow_dv_convert_action_set_meta
9873 (dev, mhdr_res, attr,
9874 (const struct rte_flow_action_set_meta *)
9875 actions->conf, error))
9877 action_flags |= MLX5_FLOW_ACTION_SET_META;
9879 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9880 if (flow_dv_convert_action_set_tag
9882 (const struct rte_flow_action_set_tag *)
9883 actions->conf, error))
9885 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9887 case RTE_FLOW_ACTION_TYPE_DROP:
9888 action_flags |= MLX5_FLOW_ACTION_DROP;
9889 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9891 case RTE_FLOW_ACTION_TYPE_QUEUE:
9892 queue = actions->conf;
9893 rss_desc->queue_num = 1;
9894 rss_desc->queue[0] = queue->index;
9895 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9896 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9897 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9900 case RTE_FLOW_ACTION_TYPE_RSS:
9901 rss = actions->conf;
9902 memcpy(rss_desc->queue, rss->queue,
9903 rss->queue_num * sizeof(uint16_t));
9904 rss_desc->queue_num = rss->queue_num;
9905 /* NULL RSS key indicates default RSS key. */
9906 rss_key = !rss->key ? rss_hash_default_key : rss->key;
9907 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9909 * rss->level and rss.types should be set in advance
9910 * when expanding items for RSS.
9912 action_flags |= MLX5_FLOW_ACTION_RSS;
9913 dev_flow->handle->fate_action = rss_desc->shared_rss ?
9914 MLX5_FLOW_FATE_SHARED_RSS :
9915 MLX5_FLOW_FATE_QUEUE;
9917 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
9918 flow->age = (uint32_t)(uintptr_t)(action->conf);
9919 age_act = flow_aso_age_get_by_idx(dev, flow->age);
9920 __atomic_fetch_add(&age_act->refcnt, 1,
9922 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
9923 action_flags |= MLX5_FLOW_ACTION_AGE;
9925 case RTE_FLOW_ACTION_TYPE_AGE:
9926 if (priv->sh->flow_hit_aso_en && attr->group) {
9927 flow->age = flow_dv_translate_create_aso_age
9928 (dev, action->conf, error);
9930 return rte_flow_error_set
9932 RTE_FLOW_ERROR_TYPE_ACTION,
9934 "can't create ASO age action");
9935 dev_flow->dv.actions[actions_n++] =
9936 (flow_aso_age_get_by_idx
9937 (dev, flow->age))->dr_action;
9938 action_flags |= MLX5_FLOW_ACTION_AGE;
9942 case RTE_FLOW_ACTION_TYPE_COUNT:
9943 if (!dev_conf->devx) {
9944 return rte_flow_error_set
9946 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9948 "count action not supported");
9950 /* Save information first, will apply later. */
9951 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9952 count = action->conf;
9955 action_flags |= MLX5_FLOW_ACTION_COUNT;
9957 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9958 dev_flow->dv.actions[actions_n++] =
9959 priv->sh->pop_vlan_action;
9960 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9962 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9963 if (!(action_flags &
9964 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9965 flow_dev_get_vlan_info_from_items(items, &vlan);
9966 vlan.eth_proto = rte_be_to_cpu_16
9967 ((((const struct rte_flow_action_of_push_vlan *)
9968 actions->conf)->ethertype));
9969 found_action = mlx5_flow_find_action
9971 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9973 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9974 found_action = mlx5_flow_find_action
9976 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9978 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9979 if (flow_dv_create_action_push_vlan
9980 (dev, attr, &vlan, dev_flow, error))
9982 dev_flow->dv.actions[actions_n++] =
9983 dev_flow->dv.push_vlan_res->action;
9984 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9986 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9987 /* of_vlan_push action handled this action */
9988 MLX5_ASSERT(action_flags &
9989 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9991 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9992 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9994 flow_dev_get_vlan_info_from_items(items, &vlan);
9995 mlx5_update_vlan_vid_pcp(actions, &vlan);
9996 /* If no VLAN push - this is a modify header action */
9997 if (flow_dv_convert_action_modify_vlan_vid
9998 (mhdr_res, actions, error))
10000 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10002 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10003 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10004 if (flow_dv_create_action_l2_encap(dev, actions,
10009 dev_flow->dv.actions[actions_n++] =
10010 dev_flow->dv.encap_decap->action;
10011 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10012 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10013 sample_act->action_flags |=
10014 MLX5_FLOW_ACTION_ENCAP;
10016 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10017 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10018 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10022 dev_flow->dv.actions[actions_n++] =
10023 dev_flow->dv.encap_decap->action;
10024 action_flags |= MLX5_FLOW_ACTION_DECAP;
10026 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10027 /* Handle encap with preceding decap. */
10028 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10029 if (flow_dv_create_action_raw_encap
10030 (dev, actions, dev_flow, attr, error))
10032 dev_flow->dv.actions[actions_n++] =
10033 dev_flow->dv.encap_decap->action;
10035 /* Handle encap without preceding decap. */
10036 if (flow_dv_create_action_l2_encap
10037 (dev, actions, dev_flow, attr->transfer,
10040 dev_flow->dv.actions[actions_n++] =
10041 dev_flow->dv.encap_decap->action;
10043 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10044 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10045 sample_act->action_flags |=
10046 MLX5_FLOW_ACTION_ENCAP;
10048 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10049 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10051 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10052 if (flow_dv_create_action_l2_decap
10053 (dev, dev_flow, attr->transfer, error))
10055 dev_flow->dv.actions[actions_n++] =
10056 dev_flow->dv.encap_decap->action;
10058 /* If decap is followed by encap, handle it at encap. */
10059 action_flags |= MLX5_FLOW_ACTION_DECAP;
10061 case RTE_FLOW_ACTION_TYPE_JUMP:
10062 jump_group = ((const struct rte_flow_action_jump *)
10063 action->conf)->group;
10064 grp_info.std_tbl_fix = 0;
10065 grp_info.skip_scale = 0;
10066 ret = mlx5_flow_group_to_table(dev, tunnel,
10072 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10074 !!dev_flow->external,
10075 tunnel, jump_group, 0,
10078 return rte_flow_error_set
10080 RTE_FLOW_ERROR_TYPE_ACTION,
10082 "cannot create jump action.");
10083 if (flow_dv_jump_tbl_resource_register
10084 (dev, tbl, dev_flow, error)) {
10085 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10086 return rte_flow_error_set
10088 RTE_FLOW_ERROR_TYPE_ACTION,
10090 "cannot create jump action.");
10092 dev_flow->dv.actions[actions_n++] =
10093 dev_flow->dv.jump->action;
10094 action_flags |= MLX5_FLOW_ACTION_JUMP;
10095 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10097 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10098 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10099 if (flow_dv_convert_action_modify_mac
10100 (mhdr_res, actions, error))
10102 action_flags |= actions->type ==
10103 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10104 MLX5_FLOW_ACTION_SET_MAC_SRC :
10105 MLX5_FLOW_ACTION_SET_MAC_DST;
10107 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10108 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10109 if (flow_dv_convert_action_modify_ipv4
10110 (mhdr_res, actions, error))
10112 action_flags |= actions->type ==
10113 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10114 MLX5_FLOW_ACTION_SET_IPV4_SRC :
10115 MLX5_FLOW_ACTION_SET_IPV4_DST;
10117 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10118 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10119 if (flow_dv_convert_action_modify_ipv6
10120 (mhdr_res, actions, error))
10122 action_flags |= actions->type ==
10123 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10124 MLX5_FLOW_ACTION_SET_IPV6_SRC :
10125 MLX5_FLOW_ACTION_SET_IPV6_DST;
10127 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10128 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10129 if (flow_dv_convert_action_modify_tp
10130 (mhdr_res, actions, items,
10131 &flow_attr, dev_flow, !!(action_flags &
10132 MLX5_FLOW_ACTION_DECAP), error))
10134 action_flags |= actions->type ==
10135 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10136 MLX5_FLOW_ACTION_SET_TP_SRC :
10137 MLX5_FLOW_ACTION_SET_TP_DST;
10139 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10140 if (flow_dv_convert_action_modify_dec_ttl
10141 (mhdr_res, items, &flow_attr, dev_flow,
10143 MLX5_FLOW_ACTION_DECAP), error))
10145 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10147 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10148 if (flow_dv_convert_action_modify_ttl
10149 (mhdr_res, actions, items, &flow_attr,
10150 dev_flow, !!(action_flags &
10151 MLX5_FLOW_ACTION_DECAP), error))
10153 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10155 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10156 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10157 if (flow_dv_convert_action_modify_tcp_seq
10158 (mhdr_res, actions, error))
10160 action_flags |= actions->type ==
10161 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10162 MLX5_FLOW_ACTION_INC_TCP_SEQ :
10163 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10166 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10167 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10168 if (flow_dv_convert_action_modify_tcp_ack
10169 (mhdr_res, actions, error))
10171 action_flags |= actions->type ==
10172 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10173 MLX5_FLOW_ACTION_INC_TCP_ACK :
10174 MLX5_FLOW_ACTION_DEC_TCP_ACK;
10176 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10177 if (flow_dv_convert_action_set_reg
10178 (mhdr_res, actions, error))
10180 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10182 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10183 if (flow_dv_convert_action_copy_mreg
10184 (dev, mhdr_res, actions, error))
10186 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10188 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10189 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10190 dev_flow->handle->fate_action =
10191 MLX5_FLOW_FATE_DEFAULT_MISS;
10193 case RTE_FLOW_ACTION_TYPE_METER:
10194 mtr = actions->conf;
10195 if (!flow->meter) {
10196 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10199 return rte_flow_error_set(error,
10201 RTE_FLOW_ERROR_TYPE_ACTION,
10204 "or invalid parameters");
10205 flow->meter = fm->idx;
10207 /* Set the meter action. */
10209 fm = mlx5_ipool_get(priv->sh->ipool
10210 [MLX5_IPOOL_MTR], flow->meter);
10212 return rte_flow_error_set(error,
10214 RTE_FLOW_ERROR_TYPE_ACTION,
10217 "or invalid parameters");
10219 dev_flow->dv.actions[actions_n++] =
10220 fm->mfts->meter_action;
10221 action_flags |= MLX5_FLOW_ACTION_METER;
10223 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10224 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10227 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10229 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10230 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10233 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10235 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10236 sample_act_pos = actions_n;
10237 ret = flow_dv_translate_action_sample(dev,
10247 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10248 /* put encap action into group if work with port id */
10249 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10250 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10251 sample_act->action_flags |=
10252 MLX5_FLOW_ACTION_ENCAP;
10254 case RTE_FLOW_ACTION_TYPE_END:
10255 actions_end = true;
10256 if (mhdr_res->actions_num) {
10257 /* create modify action if needed. */
10258 if (flow_dv_modify_hdr_resource_register
10259 (dev, mhdr_res, dev_flow, error))
10261 dev_flow->dv.actions[modify_action_position] =
10262 handle->dvh.modify_hdr->action;
10264 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10266 flow_dv_translate_create_counter(dev,
10267 dev_flow, count, age);
10269 if (!flow->counter)
10270 return rte_flow_error_set
10272 RTE_FLOW_ERROR_TYPE_ACTION,
10274 "cannot create counter"
10276 dev_flow->dv.actions[actions_n] =
10277 (flow_dv_counter_get_by_idx(dev,
10278 flow->counter, NULL))->action;
10281 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10282 ret = flow_dv_create_action_sample(dev,
10291 return rte_flow_error_set
10293 RTE_FLOW_ERROR_TYPE_ACTION,
10295 "cannot create sample action");
10296 if (num_of_dest > 1) {
10297 dev_flow->dv.actions[sample_act_pos] =
10298 dev_flow->dv.dest_array_res->action;
10300 dev_flow->dv.actions[sample_act_pos] =
10301 dev_flow->dv.sample_res->verbs_action;
10308 if (mhdr_res->actions_num &&
10309 modify_action_position == UINT32_MAX)
10310 modify_action_position = actions_n++;
10313 * For multiple destination (sample action with ratio=1), the encap
10314 * action and port id action will be combined into group action.
10315 * So need remove the original these actions in the flow and only
10316 * use the sample action instead of.
10318 if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10320 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10322 for (i = 0; i < actions_n; i++) {
10323 if ((sample_act->dr_encap_action &&
10324 sample_act->dr_encap_action ==
10325 dev_flow->dv.actions[i]) ||
10326 (sample_act->dr_port_id_action &&
10327 sample_act->dr_port_id_action ==
10328 dev_flow->dv.actions[i]))
10330 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10332 memcpy((void *)dev_flow->dv.actions,
10333 (void *)temp_actions,
10334 tmp_actions_n * sizeof(void *));
10335 actions_n = tmp_actions_n;
10337 dev_flow->dv.actions_n = actions_n;
10338 dev_flow->act_flags = action_flags;
10339 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10340 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10341 int item_type = items->type;
10343 if (!mlx5_flow_os_item_supported(item_type))
10344 return rte_flow_error_set(error, ENOTSUP,
10345 RTE_FLOW_ERROR_TYPE_ITEM,
10346 NULL, "item not supported");
10347 switch (item_type) {
10348 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10349 flow_dv_translate_item_port_id
10350 (dev, match_mask, match_value, items, attr);
10351 last_item = MLX5_FLOW_ITEM_PORT_ID;
10353 case RTE_FLOW_ITEM_TYPE_ETH:
10354 flow_dv_translate_item_eth(match_mask, match_value,
10356 dev_flow->dv.group);
10357 matcher.priority = action_flags &
10358 MLX5_FLOW_ACTION_DEFAULT_MISS &&
10359 !dev_flow->external ?
10360 MLX5_PRIORITY_MAP_L3 :
10361 MLX5_PRIORITY_MAP_L2;
10362 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10363 MLX5_FLOW_LAYER_OUTER_L2;
10365 case RTE_FLOW_ITEM_TYPE_VLAN:
10366 flow_dv_translate_item_vlan(dev_flow,
10367 match_mask, match_value,
10369 dev_flow->dv.group);
10370 matcher.priority = MLX5_PRIORITY_MAP_L2;
10371 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10372 MLX5_FLOW_LAYER_INNER_VLAN) :
10373 (MLX5_FLOW_LAYER_OUTER_L2 |
10374 MLX5_FLOW_LAYER_OUTER_VLAN);
10376 case RTE_FLOW_ITEM_TYPE_IPV4:
10377 mlx5_flow_tunnel_ip_check(items, next_protocol,
10378 &item_flags, &tunnel);
10379 flow_dv_translate_item_ipv4(match_mask, match_value,
10381 dev_flow->dv.group);
10382 matcher.priority = MLX5_PRIORITY_MAP_L3;
10383 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10384 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10385 if (items->mask != NULL &&
10386 ((const struct rte_flow_item_ipv4 *)
10387 items->mask)->hdr.next_proto_id) {
10389 ((const struct rte_flow_item_ipv4 *)
10390 (items->spec))->hdr.next_proto_id;
10392 ((const struct rte_flow_item_ipv4 *)
10393 (items->mask))->hdr.next_proto_id;
10395 /* Reset for inner layer. */
10396 next_protocol = 0xff;
10399 case RTE_FLOW_ITEM_TYPE_IPV6:
10400 mlx5_flow_tunnel_ip_check(items, next_protocol,
10401 &item_flags, &tunnel);
10402 flow_dv_translate_item_ipv6(match_mask, match_value,
10404 dev_flow->dv.group);
10405 matcher.priority = MLX5_PRIORITY_MAP_L3;
10406 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10407 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10408 if (items->mask != NULL &&
10409 ((const struct rte_flow_item_ipv6 *)
10410 items->mask)->hdr.proto) {
10412 ((const struct rte_flow_item_ipv6 *)
10413 items->spec)->hdr.proto;
10415 ((const struct rte_flow_item_ipv6 *)
10416 items->mask)->hdr.proto;
10418 /* Reset for inner layer. */
10419 next_protocol = 0xff;
10422 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10423 flow_dv_translate_item_ipv6_frag_ext(match_mask,
10426 last_item = tunnel ?
10427 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10428 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10429 if (items->mask != NULL &&
10430 ((const struct rte_flow_item_ipv6_frag_ext *)
10431 items->mask)->hdr.next_header) {
10433 ((const struct rte_flow_item_ipv6_frag_ext *)
10434 items->spec)->hdr.next_header;
10436 ((const struct rte_flow_item_ipv6_frag_ext *)
10437 items->mask)->hdr.next_header;
10439 /* Reset for inner layer. */
10440 next_protocol = 0xff;
10443 case RTE_FLOW_ITEM_TYPE_TCP:
10444 flow_dv_translate_item_tcp(match_mask, match_value,
10446 matcher.priority = MLX5_PRIORITY_MAP_L4;
10447 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10448 MLX5_FLOW_LAYER_OUTER_L4_TCP;
10450 case RTE_FLOW_ITEM_TYPE_UDP:
10451 flow_dv_translate_item_udp(match_mask, match_value,
10453 matcher.priority = MLX5_PRIORITY_MAP_L4;
10454 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10455 MLX5_FLOW_LAYER_OUTER_L4_UDP;
10457 case RTE_FLOW_ITEM_TYPE_GRE:
10458 flow_dv_translate_item_gre(match_mask, match_value,
10460 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10461 last_item = MLX5_FLOW_LAYER_GRE;
10463 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10464 flow_dv_translate_item_gre_key(match_mask,
10465 match_value, items);
10466 last_item = MLX5_FLOW_LAYER_GRE_KEY;
10468 case RTE_FLOW_ITEM_TYPE_NVGRE:
10469 flow_dv_translate_item_nvgre(match_mask, match_value,
10471 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10472 last_item = MLX5_FLOW_LAYER_GRE;
10474 case RTE_FLOW_ITEM_TYPE_VXLAN:
10475 flow_dv_translate_item_vxlan(match_mask, match_value,
10477 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10478 last_item = MLX5_FLOW_LAYER_VXLAN;
10480 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10481 flow_dv_translate_item_vxlan_gpe(match_mask,
10482 match_value, items,
10484 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10485 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10487 case RTE_FLOW_ITEM_TYPE_GENEVE:
10488 flow_dv_translate_item_geneve(match_mask, match_value,
10490 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10491 last_item = MLX5_FLOW_LAYER_GENEVE;
10493 case RTE_FLOW_ITEM_TYPE_MPLS:
10494 flow_dv_translate_item_mpls(match_mask, match_value,
10495 items, last_item, tunnel);
10496 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10497 last_item = MLX5_FLOW_LAYER_MPLS;
10499 case RTE_FLOW_ITEM_TYPE_MARK:
10500 flow_dv_translate_item_mark(dev, match_mask,
10501 match_value, items);
10502 last_item = MLX5_FLOW_ITEM_MARK;
10504 case RTE_FLOW_ITEM_TYPE_META:
10505 flow_dv_translate_item_meta(dev, match_mask,
10506 match_value, attr, items);
10507 last_item = MLX5_FLOW_ITEM_METADATA;
10509 case RTE_FLOW_ITEM_TYPE_ICMP:
10510 flow_dv_translate_item_icmp(match_mask, match_value,
10512 last_item = MLX5_FLOW_LAYER_ICMP;
10514 case RTE_FLOW_ITEM_TYPE_ICMP6:
10515 flow_dv_translate_item_icmp6(match_mask, match_value,
10517 last_item = MLX5_FLOW_LAYER_ICMP6;
10519 case RTE_FLOW_ITEM_TYPE_TAG:
10520 flow_dv_translate_item_tag(dev, match_mask,
10521 match_value, items);
10522 last_item = MLX5_FLOW_ITEM_TAG;
10524 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10525 flow_dv_translate_mlx5_item_tag(dev, match_mask,
10526 match_value, items);
10527 last_item = MLX5_FLOW_ITEM_TAG;
10529 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10530 flow_dv_translate_item_tx_queue(dev, match_mask,
10533 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10535 case RTE_FLOW_ITEM_TYPE_GTP:
10536 flow_dv_translate_item_gtp(match_mask, match_value,
10538 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10539 last_item = MLX5_FLOW_LAYER_GTP;
10541 case RTE_FLOW_ITEM_TYPE_ECPRI:
10542 if (!mlx5_flex_parser_ecpri_exist(dev)) {
10543 /* Create it only the first time to be used. */
10544 ret = mlx5_flex_parser_ecpri_alloc(dev);
10546 return rte_flow_error_set
10548 RTE_FLOW_ERROR_TYPE_ITEM,
10550 "cannot create eCPRI parser");
10552 /* Adjust the length matcher and device flow value. */
10553 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10554 dev_flow->dv.value.size =
10555 MLX5_ST_SZ_BYTES(fte_match_param);
10556 flow_dv_translate_item_ecpri(dev, match_mask,
10557 match_value, items);
10558 /* No other protocol should follow eCPRI layer. */
10559 last_item = MLX5_FLOW_LAYER_ECPRI;
10564 item_flags |= last_item;
10567 * When E-Switch mode is enabled, we have two cases where we need to
10568 * set the source port manually.
10569 * The first one, is in case of Nic steering rule, and the second is
10570 * E-Switch rule where no port_id item was found. In both cases
10571 * the source port is set according the current port in use.
10573 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10574 (priv->representor || priv->master)) {
10575 if (flow_dv_translate_item_port_id(dev, match_mask,
10576 match_value, NULL, attr))
10579 #ifdef RTE_LIBRTE_MLX5_DEBUG
10580 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10581 dev_flow->dv.value.buf));
10584 * Layers may be already initialized from prefix flow if this dev_flow
10585 * is the suffix flow.
10587 handle->layers |= item_flags;
10588 if (action_flags & MLX5_FLOW_ACTION_RSS)
10589 flow_dv_hashfields_set(dev_flow, rss_desc);
10590 /* Register matcher. */
10591 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10592 matcher.mask.size);
10593 matcher.priority = mlx5_os_flow_adjust_priority(dev,
10596 /* reserved field no needs to be set to 0 here. */
10597 tbl_key.domain = attr->transfer;
10598 tbl_key.direction = attr->egress;
10599 tbl_key.table_id = dev_flow->dv.group;
10600 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10601 tunnel, attr->group, error))
10607 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10610 * @param[in, out] action
10611 * Shred RSS action holding hash RX queue objects.
10612 * @param[in] hash_fields
10613 * Defines combination of packet fields to participate in RX hash.
10614 * @param[in] tunnel
10616 * @param[in] hrxq_idx
10617 * Hash RX queue index to set.
10620 * 0 on success, otherwise negative errno value.
10623 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10624 const uint64_t hash_fields,
10628 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10630 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10631 case MLX5_RSS_HASH_IPV4:
10632 hrxqs[0] = hrxq_idx;
10634 case MLX5_RSS_HASH_IPV4_TCP:
10635 hrxqs[1] = hrxq_idx;
10637 case MLX5_RSS_HASH_IPV4_UDP:
10638 hrxqs[2] = hrxq_idx;
10640 case MLX5_RSS_HASH_IPV6:
10641 hrxqs[3] = hrxq_idx;
10643 case MLX5_RSS_HASH_IPV6_TCP:
10644 hrxqs[4] = hrxq_idx;
10646 case MLX5_RSS_HASH_IPV6_UDP:
10647 hrxqs[5] = hrxq_idx;
10649 case MLX5_RSS_HASH_NONE:
10650 hrxqs[6] = hrxq_idx;
10658 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10662 * Pointer to the Ethernet device structure.
10664 * Shared RSS action ID holding hash RX queue objects.
10665 * @param[in] hash_fields
10666 * Defines combination of packet fields to participate in RX hash.
10667 * @param[in] tunnel
10671 * Valid hash RX queue index, otherwise 0.
10674 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10675 const uint64_t hash_fields,
10678 struct mlx5_priv *priv = dev->data->dev_private;
10679 struct mlx5_shared_action_rss *shared_rss =
10680 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10681 const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10682 shared_rss->hrxq_tunnel;
10684 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10685 case MLX5_RSS_HASH_IPV4:
10687 case MLX5_RSS_HASH_IPV4_TCP:
10689 case MLX5_RSS_HASH_IPV4_UDP:
10691 case MLX5_RSS_HASH_IPV6:
10693 case MLX5_RSS_HASH_IPV6_TCP:
10695 case MLX5_RSS_HASH_IPV6_UDP:
10697 case MLX5_RSS_HASH_NONE:
10705 * Apply the flow to the NIC, lock free,
10706 * (mutex should be acquired by caller).
10709 * Pointer to the Ethernet device structure.
10710 * @param[in, out] flow
10711 * Pointer to flow structure.
10712 * @param[out] error
10713 * Pointer to error structure.
10716 * 0 on success, a negative errno value otherwise and rte_errno is set.
10719 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10720 struct rte_flow_error *error)
10722 struct mlx5_flow_dv_workspace *dv;
10723 struct mlx5_flow_handle *dh;
10724 struct mlx5_flow_handle_dv *dv_h;
10725 struct mlx5_flow *dev_flow;
10726 struct mlx5_priv *priv = dev->data->dev_private;
10727 uint32_t handle_idx;
10731 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10732 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10735 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10736 dev_flow = &wks->flows[idx];
10737 dv = &dev_flow->dv;
10738 dh = dev_flow->handle;
10741 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10742 if (dv->transfer) {
10743 dv->actions[n++] = priv->sh->esw_drop_action;
10745 MLX5_ASSERT(priv->drop_queue.hrxq);
10747 priv->drop_queue.hrxq->action;
10749 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10750 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
10751 struct mlx5_hrxq *hrxq;
10754 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
10759 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10760 "cannot get hash queue");
10763 dh->rix_hrxq = hrxq_idx;
10764 dv->actions[n++] = hrxq->action;
10765 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
10766 struct mlx5_hrxq *hrxq = NULL;
10769 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
10770 rss_desc->shared_rss,
10771 dev_flow->hash_fields,
10773 MLX5_FLOW_LAYER_TUNNEL));
10775 hrxq = mlx5_ipool_get
10776 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
10781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10782 "cannot get hash queue");
10785 dh->rix_srss = rss_desc->shared_rss;
10786 dv->actions[n++] = hrxq->action;
10787 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10788 if (!priv->sh->default_miss_action) {
10791 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10792 "default miss action not be created.");
10795 dv->actions[n++] = priv->sh->default_miss_action;
10797 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10798 (void *)&dv->value, n,
10799 dv->actions, &dh->drv_flow);
10801 rte_flow_error_set(error, errno,
10802 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10804 "hardware refuses to create flow");
10807 if (priv->vmwa_context &&
10808 dh->vf_vlan.tag && !dh->vf_vlan.created) {
10810 * The rule contains the VLAN pattern.
10811 * For VF we are going to create VLAN
10812 * interface to make hypervisor set correct
10813 * e-Switch vport context.
10815 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10820 err = rte_errno; /* Save rte_errno before cleanup. */
10821 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10822 handle_idx, dh, next) {
10823 /* hrxq is union, don't clear it if the flag is not set. */
10824 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10825 mlx5_hrxq_release(dev, dh->rix_hrxq);
10827 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
10830 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10831 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10833 rte_errno = err; /* Restore rte_errno. */
10838 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
10839 struct mlx5_cache_entry *entry)
10841 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
10844 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
10849 * Release the flow matcher.
10852 * Pointer to Ethernet device.
10854 * Pointer to mlx5_flow_handle.
10857 * 1 while a reference on it exists, 0 when freed.
10860 flow_dv_matcher_release(struct rte_eth_dev *dev,
10861 struct mlx5_flow_handle *handle)
10863 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10864 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
10865 typeof(*tbl), tbl);
10868 MLX5_ASSERT(matcher->matcher_object);
10869 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
10870 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
10875 * Release encap_decap resource.
10878 * Pointer to the hash list.
10880 * Pointer to exist resource entry object.
10883 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
10884 struct mlx5_hlist_entry *entry)
10886 struct mlx5_dev_ctx_shared *sh = list->ctx;
10887 struct mlx5_flow_dv_encap_decap_resource *res =
10888 container_of(entry, typeof(*res), entry);
10890 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10891 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
10895 * Release an encap/decap resource.
10898 * Pointer to Ethernet device.
10899 * @param encap_decap_idx
10900 * Index of encap decap resource.
10903 * 1 while a reference on it exists, 0 when freed.
10906 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10907 uint32_t encap_decap_idx)
10909 struct mlx5_priv *priv = dev->data->dev_private;
10910 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10912 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10914 if (!cache_resource)
10916 MLX5_ASSERT(cache_resource->action);
10917 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
10918 &cache_resource->entry);
10922 * Release an jump to table action resource.
10925 * Pointer to Ethernet device.
10927 * Pointer to mlx5_flow_handle.
10930 * 1 while a reference on it exists, 0 when freed.
10933 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10934 struct mlx5_flow_handle *handle)
10936 struct mlx5_priv *priv = dev->data->dev_private;
10937 struct mlx5_flow_tbl_data_entry *tbl_data;
10939 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10943 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
10947 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
10948 struct mlx5_hlist_entry *entry)
10950 struct mlx5_flow_dv_modify_hdr_resource *res =
10951 container_of(entry, typeof(*res), entry);
10953 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10958 * Release a modify-header resource.
10961 * Pointer to Ethernet device.
10963 * Pointer to mlx5_flow_handle.
10966 * 1 while a reference on it exists, 0 when freed.
10969 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10970 struct mlx5_flow_handle *handle)
10972 struct mlx5_priv *priv = dev->data->dev_private;
10973 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
10975 MLX5_ASSERT(entry->action);
10976 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
10980 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
10981 struct mlx5_cache_entry *entry)
10983 struct mlx5_dev_ctx_shared *sh = list->ctx;
10984 struct mlx5_flow_dv_port_id_action_resource *cache =
10985 container_of(entry, typeof(*cache), entry);
10987 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
10988 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
10992 * Release port ID action resource.
10995 * Pointer to Ethernet device.
10997 * Pointer to mlx5_flow_handle.
11000 * 1 while a reference on it exists, 0 when freed.
11003 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11006 struct mlx5_priv *priv = dev->data->dev_private;
11007 struct mlx5_flow_dv_port_id_action_resource *cache;
11009 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11012 MLX5_ASSERT(cache->action);
11013 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11018 * Release shared RSS action resource.
11021 * Pointer to Ethernet device.
11023 * Shared RSS action index.
11026 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11028 struct mlx5_priv *priv = dev->data->dev_private;
11029 struct mlx5_shared_action_rss *shared_rss;
11031 shared_rss = mlx5_ipool_get
11032 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11033 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11037 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11038 struct mlx5_cache_entry *entry)
11040 struct mlx5_dev_ctx_shared *sh = list->ctx;
11041 struct mlx5_flow_dv_push_vlan_action_resource *cache =
11042 container_of(entry, typeof(*cache), entry);
11044 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11045 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11049 * Release push vlan action resource.
11052 * Pointer to Ethernet device.
11054 * Pointer to mlx5_flow_handle.
11057 * 1 while a reference on it exists, 0 when freed.
11060 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11061 struct mlx5_flow_handle *handle)
11063 struct mlx5_priv *priv = dev->data->dev_private;
11064 struct mlx5_flow_dv_push_vlan_action_resource *cache;
11065 uint32_t idx = handle->dvh.rix_push_vlan;
11067 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11070 MLX5_ASSERT(cache->action);
11071 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11076 * Release the fate resource.
11079 * Pointer to Ethernet device.
11081 * Pointer to mlx5_flow_handle.
11084 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11085 struct mlx5_flow_handle *handle)
11087 if (!handle->rix_fate)
11089 switch (handle->fate_action) {
11090 case MLX5_FLOW_FATE_QUEUE:
11091 mlx5_hrxq_release(dev, handle->rix_hrxq);
11093 case MLX5_FLOW_FATE_JUMP:
11094 flow_dv_jump_tbl_resource_release(dev, handle);
11096 case MLX5_FLOW_FATE_PORT_ID:
11097 flow_dv_port_id_action_resource_release(dev,
11098 handle->rix_port_id_action);
11101 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11104 handle->rix_fate = 0;
11108 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11109 struct mlx5_cache_entry *entry)
11111 struct mlx5_flow_dv_sample_resource *cache_resource =
11112 container_of(entry, typeof(*cache_resource), entry);
11113 struct rte_eth_dev *dev = cache_resource->dev;
11114 struct mlx5_priv *priv = dev->data->dev_private;
11116 if (cache_resource->verbs_action)
11117 claim_zero(mlx5_flow_os_destroy_flow_action
11118 (cache_resource->verbs_action));
11119 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11120 if (cache_resource->default_miss)
11121 claim_zero(mlx5_flow_os_destroy_flow_action
11122 (cache_resource->default_miss));
11124 if (cache_resource->normal_path_tbl)
11125 flow_dv_tbl_resource_release(MLX5_SH(dev),
11126 cache_resource->normal_path_tbl);
11127 flow_dv_sample_sub_actions_release(dev,
11128 &cache_resource->sample_idx);
11129 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11130 cache_resource->idx);
11131 DRV_LOG(DEBUG, "sample resource %p: removed",
11132 (void *)cache_resource);
11136 * Release an sample resource.
11139 * Pointer to Ethernet device.
11141 * Pointer to mlx5_flow_handle.
11144 * 1 while a reference on it exists, 0 when freed.
11147 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11148 struct mlx5_flow_handle *handle)
11150 struct mlx5_priv *priv = dev->data->dev_private;
11151 struct mlx5_flow_dv_sample_resource *cache_resource;
11153 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11154 handle->dvh.rix_sample);
11155 if (!cache_resource)
11157 MLX5_ASSERT(cache_resource->verbs_action);
11158 return mlx5_cache_unregister(&priv->sh->sample_action_list,
11159 &cache_resource->entry);
11163 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11164 struct mlx5_cache_entry *entry)
11166 struct mlx5_flow_dv_dest_array_resource *cache_resource =
11167 container_of(entry, typeof(*cache_resource), entry);
11168 struct rte_eth_dev *dev = cache_resource->dev;
11169 struct mlx5_priv *priv = dev->data->dev_private;
11172 MLX5_ASSERT(cache_resource->action);
11173 if (cache_resource->action)
11174 claim_zero(mlx5_flow_os_destroy_flow_action
11175 (cache_resource->action));
11176 for (; i < cache_resource->num_of_dest; i++)
11177 flow_dv_sample_sub_actions_release(dev,
11178 &cache_resource->sample_idx[i]);
11179 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11180 cache_resource->idx);
11181 DRV_LOG(DEBUG, "destination array resource %p: removed",
11182 (void *)cache_resource);
11186 * Release an destination array resource.
11189 * Pointer to Ethernet device.
11191 * Pointer to mlx5_flow_handle.
11194 * 1 while a reference on it exists, 0 when freed.
11197 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11198 struct mlx5_flow_handle *handle)
11200 struct mlx5_priv *priv = dev->data->dev_private;
11201 struct mlx5_flow_dv_dest_array_resource *cache;
11203 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11204 handle->dvh.rix_dest_array);
11207 MLX5_ASSERT(cache->action);
11208 return mlx5_cache_unregister(&priv->sh->dest_array_list,
11213 * Remove the flow from the NIC but keeps it in memory.
11214 * Lock free, (mutex should be acquired by caller).
11217 * Pointer to Ethernet device.
11218 * @param[in, out] flow
11219 * Pointer to flow structure.
11222 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11224 struct mlx5_flow_handle *dh;
11225 uint32_t handle_idx;
11226 struct mlx5_priv *priv = dev->data->dev_private;
11230 handle_idx = flow->dev_handles;
11231 while (handle_idx) {
11232 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11236 if (dh->drv_flow) {
11237 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11238 dh->drv_flow = NULL;
11240 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11241 flow_dv_fate_resource_release(dev, dh);
11242 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11243 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11244 handle_idx = dh->next.next;
11249 * Remove the flow from the NIC and the memory.
11250 * Lock free, (mutex should be acquired by caller).
11253 * Pointer to the Ethernet device structure.
11254 * @param[in, out] flow
11255 * Pointer to flow structure.
11258 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11260 struct mlx5_flow_handle *dev_handle;
11261 struct mlx5_priv *priv = dev->data->dev_private;
11266 flow_dv_remove(dev, flow);
11267 if (flow->counter) {
11268 flow_dv_counter_free(dev, flow->counter);
11272 struct mlx5_flow_meter *fm;
11274 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11277 mlx5_flow_meter_detach(fm);
11281 flow_dv_aso_age_release(dev, flow->age);
11282 while (flow->dev_handles) {
11283 uint32_t tmp_idx = flow->dev_handles;
11285 dev_handle = mlx5_ipool_get(priv->sh->ipool
11286 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11289 flow->dev_handles = dev_handle->next.next;
11290 if (dev_handle->dvh.matcher)
11291 flow_dv_matcher_release(dev, dev_handle);
11292 if (dev_handle->dvh.rix_sample)
11293 flow_dv_sample_resource_release(dev, dev_handle);
11294 if (dev_handle->dvh.rix_dest_array)
11295 flow_dv_dest_array_resource_release(dev, dev_handle);
11296 if (dev_handle->dvh.rix_encap_decap)
11297 flow_dv_encap_decap_resource_release(dev,
11298 dev_handle->dvh.rix_encap_decap);
11299 if (dev_handle->dvh.modify_hdr)
11300 flow_dv_modify_hdr_resource_release(dev, dev_handle);
11301 if (dev_handle->dvh.rix_push_vlan)
11302 flow_dv_push_vlan_action_resource_release(dev,
11304 if (dev_handle->dvh.rix_tag)
11305 flow_dv_tag_release(dev,
11306 dev_handle->dvh.rix_tag);
11307 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11308 flow_dv_fate_resource_release(dev, dev_handle);
11310 srss = dev_handle->rix_srss;
11311 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11315 flow_dv_shared_rss_action_release(dev, srss);
11319 * Release array of hash RX queue objects.
11323 * Pointer to the Ethernet device structure.
11324 * @param[in, out] hrxqs
11325 * Array of hash RX queue objects.
11328 * Total number of references to hash RX queue objects in *hrxqs* array
11329 * after this operation.
11332 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11333 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11338 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11339 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11349 * Release all hash RX queue objects representing shared RSS action.
11352 * Pointer to the Ethernet device structure.
11353 * @param[in, out] action
11354 * Shared RSS action to remove hash RX queue objects from.
11357 * Total number of references to hash RX queue objects stored in *action*
11358 * after this operation.
11359 * Expected to be 0 if no external references held.
11362 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11363 struct mlx5_shared_action_rss *action)
11365 return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11366 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11370 * Setup shared RSS action.
11371 * Prepare set of hash RX queue objects sufficient to handle all valid
11372 * hash_fields combinations (see enum ibv_rx_hash_fields).
11375 * Pointer to the Ethernet device structure.
11376 * @param[in] action_idx
11377 * Shared RSS action ipool index.
11378 * @param[in, out] action
11379 * Partially initialized shared RSS action.
11380 * @param[out] error
11381 * Perform verbose error reporting if not NULL. Initialized in case of
11385 * 0 on success, otherwise negative errno value.
11388 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11389 uint32_t action_idx,
11390 struct mlx5_shared_action_rss *action,
11391 struct rte_flow_error *error)
11393 struct mlx5_flow_rss_desc rss_desc = { 0 };
11397 if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11398 return rte_flow_error_set(error, rte_errno,
11399 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11400 "cannot setup indirection table");
11402 memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11403 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11404 rss_desc.const_q = action->origin.queue;
11405 rss_desc.queue_num = action->origin.queue_num;
11406 /* Set non-zero value to indicate a shared RSS. */
11407 rss_desc.shared_rss = action_idx;
11408 rss_desc.ind_tbl = action->ind_tbl;
11409 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11411 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11414 for (tunnel = 0; tunnel < 2; tunnel++) {
11415 rss_desc.tunnel = tunnel;
11416 rss_desc.hash_fields = hash_fields;
11417 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11421 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11422 "cannot get hash queue");
11423 goto error_hrxq_new;
11425 err = __flow_dv_action_rss_hrxq_set
11426 (action, hash_fields, tunnel, hrxq_idx);
11433 __flow_dv_action_rss_hrxqs_release(dev, action);
11434 if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11435 action->ind_tbl = NULL;
11441 * Create shared RSS action.
11444 * Pointer to the Ethernet device structure.
11446 * Shared action configuration.
11448 * RSS action specification used to create shared action.
11449 * @param[out] error
11450 * Perform verbose error reporting if not NULL. Initialized in case of
11454 * A valid shared action ID in case of success, 0 otherwise and
11455 * rte_errno is set.
11458 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11459 const struct rte_flow_shared_action_conf *conf,
11460 const struct rte_flow_action_rss *rss,
11461 struct rte_flow_error *error)
11463 struct mlx5_priv *priv = dev->data->dev_private;
11464 struct mlx5_shared_action_rss *shared_action = NULL;
11465 void *queue = NULL;
11466 struct rte_flow_action_rss *origin;
11467 const uint8_t *rss_key;
11468 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11471 RTE_SET_USED(conf);
11472 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11474 shared_action = mlx5_ipool_zmalloc
11475 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11476 if (!shared_action || !queue) {
11477 rte_flow_error_set(error, ENOMEM,
11478 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11479 "cannot allocate resource memory");
11480 goto error_rss_init;
11482 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11483 rte_flow_error_set(error, E2BIG,
11484 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11485 "rss action number out of range");
11486 goto error_rss_init;
11488 shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11489 sizeof(*shared_action->ind_tbl),
11491 if (!shared_action->ind_tbl) {
11492 rte_flow_error_set(error, ENOMEM,
11493 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11494 "cannot allocate resource memory");
11495 goto error_rss_init;
11497 memcpy(queue, rss->queue, queue_size);
11498 shared_action->ind_tbl->queues = queue;
11499 shared_action->ind_tbl->queues_n = rss->queue_num;
11500 origin = &shared_action->origin;
11501 origin->func = rss->func;
11502 origin->level = rss->level;
11503 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11504 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11505 /* NULL RSS key indicates default RSS key. */
11506 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11507 memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11508 origin->key = &shared_action->key[0];
11509 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11510 origin->queue = queue;
11511 origin->queue_num = rss->queue_num;
11512 if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11513 goto error_rss_init;
11514 rte_spinlock_init(&shared_action->action_rss_sl);
11515 __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11516 rte_spinlock_lock(&priv->shared_act_sl);
11517 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11518 &priv->rss_shared_actions, idx, shared_action, next);
11519 rte_spinlock_unlock(&priv->shared_act_sl);
11522 if (shared_action) {
11523 if (shared_action->ind_tbl)
11524 mlx5_free(shared_action->ind_tbl);
11525 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11534 * Destroy the shared RSS action.
11535 * Release related hash RX queue objects.
11538 * Pointer to the Ethernet device structure.
11540 * The shared RSS action object ID to be removed.
11541 * @param[out] error
11542 * Perform verbose error reporting if not NULL. Initialized in case of
11546 * 0 on success, otherwise negative errno value.
11549 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11550 struct rte_flow_error *error)
11552 struct mlx5_priv *priv = dev->data->dev_private;
11553 struct mlx5_shared_action_rss *shared_rss =
11554 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11555 uint32_t old_refcnt = 1;
11557 uint16_t *queue = NULL;
11560 return rte_flow_error_set(error, EINVAL,
11561 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11562 "invalid shared action");
11563 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11565 return rte_flow_error_set(error, EBUSY,
11566 RTE_FLOW_ERROR_TYPE_ACTION,
11568 "shared rss hrxq has references");
11569 queue = shared_rss->ind_tbl->queues;
11570 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11572 return rte_flow_error_set(error, EBUSY,
11573 RTE_FLOW_ERROR_TYPE_ACTION,
11575 "shared rss indirection table has"
11577 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11578 0, 0, __ATOMIC_ACQUIRE,
11580 return rte_flow_error_set(error, EBUSY,
11581 RTE_FLOW_ERROR_TYPE_ACTION,
11583 "shared rss has references");
11585 rte_spinlock_lock(&priv->shared_act_sl);
11586 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11587 &priv->rss_shared_actions, idx, shared_rss, next);
11588 rte_spinlock_unlock(&priv->shared_act_sl);
11589 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11595 * Create shared action, lock free,
11596 * (mutex should be acquired by caller).
11597 * Dispatcher for action type specific call.
11600 * Pointer to the Ethernet device structure.
11602 * Shared action configuration.
11603 * @param[in] action
11604 * Action specification used to create shared action.
11605 * @param[out] error
11606 * Perform verbose error reporting if not NULL. Initialized in case of
11610 * A valid shared action handle in case of success, NULL otherwise and
11611 * rte_errno is set.
11613 static struct rte_flow_shared_action *
11614 flow_dv_action_create(struct rte_eth_dev *dev,
11615 const struct rte_flow_shared_action_conf *conf,
11616 const struct rte_flow_action *action,
11617 struct rte_flow_error *err)
11622 switch (action->type) {
11623 case RTE_FLOW_ACTION_TYPE_RSS:
11624 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11625 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11626 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11628 case RTE_FLOW_ACTION_TYPE_AGE:
11629 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11630 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11631 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11633 struct mlx5_aso_age_action *aso_age =
11634 flow_aso_age_get_by_idx(dev, ret);
11636 if (!aso_age->age_params.context)
11637 aso_age->age_params.context =
11638 (void *)(uintptr_t)idx;
11642 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11643 NULL, "action type not supported");
11646 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11650 * Destroy the shared action.
11651 * Release action related resources on the NIC and the memory.
11652 * Lock free, (mutex should be acquired by caller).
11653 * Dispatcher for action type specific call.
11656 * Pointer to the Ethernet device structure.
11657 * @param[in] action
11658 * The shared action object to be removed.
11659 * @param[out] error
11660 * Perform verbose error reporting if not NULL. Initialized in case of
11664 * 0 on success, otherwise negative errno value.
11667 flow_dv_action_destroy(struct rte_eth_dev *dev,
11668 struct rte_flow_shared_action *action,
11669 struct rte_flow_error *error)
11671 uint32_t act_idx = (uint32_t)(uintptr_t)action;
11672 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11673 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11677 case MLX5_SHARED_ACTION_TYPE_RSS:
11678 return __flow_dv_action_rss_release(dev, idx, error);
11679 case MLX5_SHARED_ACTION_TYPE_AGE:
11680 ret = flow_dv_aso_age_release(dev, idx);
11683 * In this case, the last flow has a reference will
11684 * actually release the age action.
11686 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11687 " released with references %d.", idx, ret);
11690 return rte_flow_error_set(error, ENOTSUP,
11691 RTE_FLOW_ERROR_TYPE_ACTION,
11693 "action type not supported");
11698 * Updates in place shared RSS action configuration.
11701 * Pointer to the Ethernet device structure.
11703 * The shared RSS action object ID to be updated.
11704 * @param[in] action_conf
11705 * RSS action specification used to modify *shared_rss*.
11706 * @param[out] error
11707 * Perform verbose error reporting if not NULL. Initialized in case of
11711 * 0 on success, otherwise negative errno value.
11712 * @note: currently only support update of RSS queues.
11715 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11716 const struct rte_flow_action_rss *action_conf,
11717 struct rte_flow_error *error)
11719 struct mlx5_priv *priv = dev->data->dev_private;
11720 struct mlx5_shared_action_rss *shared_rss =
11721 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11723 void *queue = NULL;
11724 uint16_t *queue_old = NULL;
11725 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11728 return rte_flow_error_set(error, EINVAL,
11729 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11730 "invalid shared action to update");
11731 queue = mlx5_malloc(MLX5_MEM_ZERO,
11732 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11735 return rte_flow_error_set(error, ENOMEM,
11736 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11738 "cannot allocate resource memory");
11739 memcpy(queue, action_conf->queue, queue_size);
11740 MLX5_ASSERT(shared_rss->ind_tbl);
11741 rte_spinlock_lock(&shared_rss->action_rss_sl);
11742 queue_old = shared_rss->ind_tbl->queues;
11743 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
11744 queue, action_conf->queue_num, true);
11747 ret = rte_flow_error_set(error, rte_errno,
11748 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11749 "cannot update indirection table");
11751 mlx5_free(queue_old);
11752 shared_rss->origin.queue = queue;
11753 shared_rss->origin.queue_num = action_conf->queue_num;
11755 rte_spinlock_unlock(&shared_rss->action_rss_sl);
11760 * Updates in place shared action configuration, lock free,
11761 * (mutex should be acquired by caller).
11764 * Pointer to the Ethernet device structure.
11765 * @param[in] action
11766 * The shared action object to be updated.
11767 * @param[in] action_conf
11768 * Action specification used to modify *action*.
11769 * *action_conf* should be of type correlating with type of the *action*,
11770 * otherwise considered as invalid.
11771 * @param[out] error
11772 * Perform verbose error reporting if not NULL. Initialized in case of
11776 * 0 on success, otherwise negative errno value.
11779 flow_dv_action_update(struct rte_eth_dev *dev,
11780 struct rte_flow_shared_action *action,
11781 const void *action_conf,
11782 struct rte_flow_error *err)
11784 uint32_t act_idx = (uint32_t)(uintptr_t)action;
11785 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11786 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11789 case MLX5_SHARED_ACTION_TYPE_RSS:
11790 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
11792 return rte_flow_error_set(err, ENOTSUP,
11793 RTE_FLOW_ERROR_TYPE_ACTION,
11795 "action type update not supported");
11800 flow_dv_action_query(struct rte_eth_dev *dev,
11801 const struct rte_flow_shared_action *action, void *data,
11802 struct rte_flow_error *error)
11804 struct mlx5_age_param *age_param;
11805 struct rte_flow_query_age *resp;
11806 uint32_t act_idx = (uint32_t)(uintptr_t)action;
11807 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11808 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11811 case MLX5_SHARED_ACTION_TYPE_AGE:
11812 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
11814 resp->aged = __atomic_load_n(&age_param->state,
11815 __ATOMIC_RELAXED) == AGE_TMOUT ?
11817 resp->sec_since_last_hit_valid = !resp->aged;
11818 if (resp->sec_since_last_hit_valid)
11819 resp->sec_since_last_hit = __atomic_load_n
11820 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11823 return rte_flow_error_set(error, ENOTSUP,
11824 RTE_FLOW_ERROR_TYPE_ACTION,
11826 "action type query not supported");
11831 * Query a dv flow rule for its statistics via devx.
11834 * Pointer to Ethernet device.
11836 * Pointer to the sub flow.
11838 * data retrieved by the query.
11839 * @param[out] error
11840 * Perform verbose error reporting if not NULL.
11843 * 0 on success, a negative errno value otherwise and rte_errno is set.
11846 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11847 void *data, struct rte_flow_error *error)
11849 struct mlx5_priv *priv = dev->data->dev_private;
11850 struct rte_flow_query_count *qc = data;
11852 if (!priv->config.devx)
11853 return rte_flow_error_set(error, ENOTSUP,
11854 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11856 "counters are not supported");
11857 if (flow->counter) {
11858 uint64_t pkts, bytes;
11859 struct mlx5_flow_counter *cnt;
11861 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11863 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11867 return rte_flow_error_set(error, -err,
11868 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11869 NULL, "cannot read counters");
11872 qc->hits = pkts - cnt->hits;
11873 qc->bytes = bytes - cnt->bytes;
11876 cnt->bytes = bytes;
11880 return rte_flow_error_set(error, EINVAL,
11881 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11883 "counters are not available");
11887 * Query a flow rule AGE action for aging information.
11890 * Pointer to Ethernet device.
11892 * Pointer to the sub flow.
11894 * data retrieved by the query.
11895 * @param[out] error
11896 * Perform verbose error reporting if not NULL.
11899 * 0 on success, a negative errno value otherwise and rte_errno is set.
11902 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11903 void *data, struct rte_flow_error *error)
11905 struct rte_flow_query_age *resp = data;
11906 struct mlx5_age_param *age_param;
11909 struct mlx5_aso_age_action *act =
11910 flow_aso_age_get_by_idx(dev, flow->age);
11912 age_param = &act->age_params;
11913 } else if (flow->counter) {
11914 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
11916 if (!age_param || !age_param->timeout)
11917 return rte_flow_error_set
11919 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11920 NULL, "cannot read age data");
11922 return rte_flow_error_set(error, EINVAL,
11923 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11924 NULL, "age data not available");
11926 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
11928 resp->sec_since_last_hit_valid = !resp->aged;
11929 if (resp->sec_since_last_hit_valid)
11930 resp->sec_since_last_hit = __atomic_load_n
11931 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11938 * @see rte_flow_query()
11939 * @see rte_flow_ops
11942 flow_dv_query(struct rte_eth_dev *dev,
11943 struct rte_flow *flow __rte_unused,
11944 const struct rte_flow_action *actions __rte_unused,
11945 void *data __rte_unused,
11946 struct rte_flow_error *error __rte_unused)
11950 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11951 switch (actions->type) {
11952 case RTE_FLOW_ACTION_TYPE_VOID:
11954 case RTE_FLOW_ACTION_TYPE_COUNT:
11955 ret = flow_dv_query_count(dev, flow, data, error);
11957 case RTE_FLOW_ACTION_TYPE_AGE:
11958 ret = flow_dv_query_age(dev, flow, data, error);
11961 return rte_flow_error_set(error, ENOTSUP,
11962 RTE_FLOW_ERROR_TYPE_ACTION,
11964 "action not supported");
11971 * Destroy the meter table set.
11972 * Lock free, (mutex should be acquired by caller).
11975 * Pointer to Ethernet device.
11977 * Pointer to the meter table set.
11983 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11984 struct mlx5_meter_domains_infos *tbl)
11986 struct mlx5_priv *priv = dev->data->dev_private;
11987 struct mlx5_meter_domains_infos *mtd =
11988 (struct mlx5_meter_domains_infos *)tbl;
11990 if (!mtd || !priv->config.dv_flow_en)
11992 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11993 claim_zero(mlx5_flow_os_destroy_flow
11994 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11995 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11996 claim_zero(mlx5_flow_os_destroy_flow
11997 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11998 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11999 claim_zero(mlx5_flow_os_destroy_flow
12000 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12001 if (mtd->egress.color_matcher)
12002 claim_zero(mlx5_flow_os_destroy_flow_matcher
12003 (mtd->egress.color_matcher));
12004 if (mtd->egress.any_matcher)
12005 claim_zero(mlx5_flow_os_destroy_flow_matcher
12006 (mtd->egress.any_matcher));
12007 if (mtd->egress.tbl)
12008 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12009 if (mtd->egress.sfx_tbl)
12010 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12011 if (mtd->ingress.color_matcher)
12012 claim_zero(mlx5_flow_os_destroy_flow_matcher
12013 (mtd->ingress.color_matcher));
12014 if (mtd->ingress.any_matcher)
12015 claim_zero(mlx5_flow_os_destroy_flow_matcher
12016 (mtd->ingress.any_matcher));
12017 if (mtd->ingress.tbl)
12018 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12019 if (mtd->ingress.sfx_tbl)
12020 flow_dv_tbl_resource_release(MLX5_SH(dev),
12021 mtd->ingress.sfx_tbl);
12022 if (mtd->transfer.color_matcher)
12023 claim_zero(mlx5_flow_os_destroy_flow_matcher
12024 (mtd->transfer.color_matcher));
12025 if (mtd->transfer.any_matcher)
12026 claim_zero(mlx5_flow_os_destroy_flow_matcher
12027 (mtd->transfer.any_matcher));
12028 if (mtd->transfer.tbl)
12029 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12030 if (mtd->transfer.sfx_tbl)
12031 flow_dv_tbl_resource_release(MLX5_SH(dev),
12032 mtd->transfer.sfx_tbl);
12033 if (mtd->drop_actn)
12034 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12039 /* Number of meter flow actions, count and jump or count and drop. */
12040 #define METER_ACTIONS 2
12043 * Create specify domain meter table and suffix table.
12046 * Pointer to Ethernet device.
12047 * @param[in,out] mtb
12048 * Pointer to DV meter table set.
12049 * @param[in] egress
12051 * @param[in] transfer
12053 * @param[in] color_reg_c_idx
12054 * Reg C index for color match.
12057 * 0 on success, -1 otherwise and rte_errno is set.
12060 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12061 struct mlx5_meter_domains_infos *mtb,
12062 uint8_t egress, uint8_t transfer,
12063 uint32_t color_reg_c_idx)
12065 struct mlx5_priv *priv = dev->data->dev_private;
12066 struct mlx5_dev_ctx_shared *sh = priv->sh;
12067 struct mlx5_flow_dv_match_params mask = {
12068 .size = sizeof(mask.buf),
12070 struct mlx5_flow_dv_match_params value = {
12071 .size = sizeof(value.buf),
12073 struct mlx5dv_flow_matcher_attr dv_attr = {
12074 .type = IBV_FLOW_ATTR_NORMAL,
12076 .match_criteria_enable = 0,
12077 .match_mask = (void *)&mask,
12079 void *actions[METER_ACTIONS];
12080 struct mlx5_meter_domain_info *dtb;
12081 struct rte_flow_error error;
12086 dtb = &mtb->transfer;
12088 dtb = &mtb->egress;
12090 dtb = &mtb->ingress;
12091 /* Create the meter table with METER level. */
12092 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12093 egress, transfer, false, NULL, 0,
12096 DRV_LOG(ERR, "Failed to create meter policer table.");
12099 /* Create the meter suffix table with SUFFIX level. */
12100 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12101 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12102 egress, transfer, false, NULL, 0,
12104 if (!dtb->sfx_tbl) {
12105 DRV_LOG(ERR, "Failed to create meter suffix table.");
12108 /* Create matchers, Any and Color. */
12109 dv_attr.priority = 3;
12110 dv_attr.match_criteria_enable = 0;
12111 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12112 &dtb->any_matcher);
12114 DRV_LOG(ERR, "Failed to create meter"
12115 " policer default matcher.");
12118 dv_attr.priority = 0;
12119 dv_attr.match_criteria_enable =
12120 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12121 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12122 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12123 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12124 &dtb->color_matcher);
12126 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12129 if (mtb->count_actns[RTE_MTR_DROPPED])
12130 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12131 actions[i++] = mtb->drop_actn;
12132 /* Default rule: lowest priority, match any, actions: drop. */
12133 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12135 &dtb->policer_rules[RTE_MTR_DROPPED]);
12137 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12146 * Create the needed meter and suffix tables.
12147 * Lock free, (mutex should be acquired by caller).
12150 * Pointer to Ethernet device.
12152 * Pointer to the flow meter.
12155 * Pointer to table set on success, NULL otherwise and rte_errno is set.
12157 static struct mlx5_meter_domains_infos *
12158 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12159 const struct mlx5_flow_meter *fm)
12161 struct mlx5_priv *priv = dev->data->dev_private;
12162 struct mlx5_meter_domains_infos *mtb;
12166 if (!priv->mtr_en) {
12167 rte_errno = ENOTSUP;
12170 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12172 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12175 /* Create meter count actions */
12176 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12177 struct mlx5_flow_counter *cnt;
12178 if (!fm->policer_stats.cnt[i])
12180 cnt = flow_dv_counter_get_by_idx(dev,
12181 fm->policer_stats.cnt[i], NULL);
12182 mtb->count_actns[i] = cnt->action;
12184 /* Create drop action. */
12185 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12187 DRV_LOG(ERR, "Failed to create drop action.");
12190 /* Egress meter table. */
12191 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12193 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12196 /* Ingress meter table. */
12197 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12199 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12202 /* FDB meter table. */
12203 if (priv->config.dv_esw_en) {
12204 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12205 priv->mtr_color_reg);
12207 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12213 flow_dv_destroy_mtr_tbl(dev, mtb);
12218 * Destroy domain policer rule.
12221 * Pointer to domain table.
12224 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12228 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12229 if (dt->policer_rules[i]) {
12230 claim_zero(mlx5_flow_os_destroy_flow
12231 (dt->policer_rules[i]));
12232 dt->policer_rules[i] = NULL;
12235 if (dt->jump_actn) {
12236 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12237 dt->jump_actn = NULL;
12242 * Destroy policer rules.
12245 * Pointer to Ethernet device.
12247 * Pointer to flow meter structure.
12249 * Pointer to flow attributes.
12255 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12256 const struct mlx5_flow_meter *fm,
12257 const struct rte_flow_attr *attr)
12259 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12264 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12266 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12267 if (attr->transfer)
12268 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12273 * Create specify domain meter policer rule.
12276 * Pointer to flow meter structure.
12278 * Pointer to DV meter table set.
12279 * @param[in] mtr_reg_c
12280 * Color match REG_C.
12283 * 0 on success, -1 otherwise.
12286 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12287 struct mlx5_meter_domain_info *dtb,
12290 struct mlx5_flow_dv_match_params matcher = {
12291 .size = sizeof(matcher.buf),
12293 struct mlx5_flow_dv_match_params value = {
12294 .size = sizeof(value.buf),
12296 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12297 void *actions[METER_ACTIONS];
12301 /* Create jump action. */
12302 if (!dtb->jump_actn)
12303 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12304 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12306 DRV_LOG(ERR, "Failed to create policer jump action.");
12309 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12312 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12313 rte_col_2_mlx5_col(i), UINT8_MAX);
12314 if (mtb->count_actns[i])
12315 actions[j++] = mtb->count_actns[i];
12316 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12317 actions[j++] = mtb->drop_actn;
12319 actions[j++] = dtb->jump_actn;
12320 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12321 (void *)&value, j, actions,
12322 &dtb->policer_rules[i]);
12324 DRV_LOG(ERR, "Failed to create policer rule.");
12335 * Create policer rules.
12338 * Pointer to Ethernet device.
12340 * Pointer to flow meter structure.
12342 * Pointer to flow attributes.
12345 * 0 on success, -1 otherwise.
12348 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12349 struct mlx5_flow_meter *fm,
12350 const struct rte_flow_attr *attr)
12352 struct mlx5_priv *priv = dev->data->dev_private;
12353 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12356 if (attr->egress) {
12357 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12358 priv->mtr_color_reg);
12360 DRV_LOG(ERR, "Failed to create egress policer.");
12364 if (attr->ingress) {
12365 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12366 priv->mtr_color_reg);
12368 DRV_LOG(ERR, "Failed to create ingress policer.");
12372 if (attr->transfer) {
12373 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12374 priv->mtr_color_reg);
12376 DRV_LOG(ERR, "Failed to create transfer policer.");
12382 flow_dv_destroy_policer_rules(dev, fm, attr);
12387 * Validate the batch counter support in root table.
12389 * Create a simple flow with invalid counter and drop action on root table to
12390 * validate if batch counter with offset on root table is supported or not.
12393 * Pointer to rte_eth_dev structure.
12396 * 0 on success, a negative errno value otherwise and rte_errno is set.
12399 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12401 struct mlx5_priv *priv = dev->data->dev_private;
12402 struct mlx5_dev_ctx_shared *sh = priv->sh;
12403 struct mlx5_flow_dv_match_params mask = {
12404 .size = sizeof(mask.buf),
12406 struct mlx5_flow_dv_match_params value = {
12407 .size = sizeof(value.buf),
12409 struct mlx5dv_flow_matcher_attr dv_attr = {
12410 .type = IBV_FLOW_ATTR_NORMAL,
12412 .match_criteria_enable = 0,
12413 .match_mask = (void *)&mask,
12415 void *actions[2] = { 0 };
12416 struct mlx5_flow_tbl_resource *tbl = NULL;
12417 struct mlx5_devx_obj *dcs = NULL;
12418 void *matcher = NULL;
12422 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12425 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12428 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12432 actions[1] = priv->drop_queue.hrxq->action;
12433 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12434 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12438 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12442 * If batch counter with offset is not supported, the driver will not
12443 * validate the invalid offset value, flow create should success.
12444 * In this case, it means batch counter is not supported in root table.
12446 * Otherwise, if flow create is failed, counter offset is supported.
12449 DRV_LOG(INFO, "Batch counter is not supported in root "
12450 "table. Switch to fallback mode.");
12451 rte_errno = ENOTSUP;
12453 claim_zero(mlx5_flow_os_destroy_flow(flow));
12455 /* Check matcher to make sure validate fail at flow create. */
12456 if (!matcher || (matcher && errno != EINVAL))
12457 DRV_LOG(ERR, "Unexpected error in counter offset "
12458 "support detection");
12462 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12464 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12466 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12468 claim_zero(mlx5_devx_cmd_destroy(dcs));
12473 * Query a devx counter.
12476 * Pointer to the Ethernet device structure.
12478 * Index to the flow counter.
12480 * Set to clear the counter statistics.
12482 * The statistics value of packets.
12483 * @param[out] bytes
12484 * The statistics value of bytes.
12487 * 0 on success, otherwise return -1.
12490 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12491 uint64_t *pkts, uint64_t *bytes)
12493 struct mlx5_priv *priv = dev->data->dev_private;
12494 struct mlx5_flow_counter *cnt;
12495 uint64_t inn_pkts, inn_bytes;
12498 if (!priv->config.devx)
12501 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12504 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12505 *pkts = inn_pkts - cnt->hits;
12506 *bytes = inn_bytes - cnt->bytes;
12508 cnt->hits = inn_pkts;
12509 cnt->bytes = inn_bytes;
12515 * Get aged-out flows.
12518 * Pointer to the Ethernet device structure.
12519 * @param[in] context
12520 * The address of an array of pointers to the aged-out flows contexts.
12521 * @param[in] nb_contexts
12522 * The length of context array pointers.
12523 * @param[out] error
12524 * Perform verbose error reporting if not NULL. Initialized in case of
12528 * how many contexts get in success, otherwise negative errno value.
12529 * if nb_contexts is 0, return the amount of all aged contexts.
12530 * if nb_contexts is not 0 , return the amount of aged flows reported
12531 * in the context array.
12532 * @note: only stub for now
12535 flow_get_aged_flows(struct rte_eth_dev *dev,
12537 uint32_t nb_contexts,
12538 struct rte_flow_error *error)
12540 struct mlx5_priv *priv = dev->data->dev_private;
12541 struct mlx5_age_info *age_info;
12542 struct mlx5_age_param *age_param;
12543 struct mlx5_flow_counter *counter;
12544 struct mlx5_aso_age_action *act;
12547 if (nb_contexts && !context)
12548 return rte_flow_error_set(error, EINVAL,
12549 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12550 NULL, "empty context");
12551 age_info = GET_PORT_AGE_INFO(priv);
12552 rte_spinlock_lock(&age_info->aged_sl);
12553 LIST_FOREACH(act, &age_info->aged_aso, next) {
12556 context[nb_flows - 1] =
12557 act->age_params.context;
12558 if (!(--nb_contexts))
12562 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12565 age_param = MLX5_CNT_TO_AGE(counter);
12566 context[nb_flows - 1] = age_param->context;
12567 if (!(--nb_contexts))
12571 rte_spinlock_unlock(&age_info->aged_sl);
12572 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12577 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12580 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12582 return flow_dv_counter_alloc(dev, 0);
12586 * Validate shared action.
12587 * Dispatcher for action type specific validation.
12590 * Pointer to the Ethernet device structure.
12592 * Shared action configuration.
12593 * @param[in] action
12594 * The shared action object to validate.
12595 * @param[out] error
12596 * Perform verbose error reporting if not NULL. Initialized in case of
12600 * 0 on success, otherwise negative errno value.
12603 flow_dv_action_validate(struct rte_eth_dev *dev,
12604 const struct rte_flow_shared_action_conf *conf,
12605 const struct rte_flow_action *action,
12606 struct rte_flow_error *err)
12608 struct mlx5_priv *priv = dev->data->dev_private;
12610 RTE_SET_USED(conf);
12611 switch (action->type) {
12612 case RTE_FLOW_ACTION_TYPE_RSS:
12613 return mlx5_validate_action_rss(dev, action, err);
12614 case RTE_FLOW_ACTION_TYPE_AGE:
12615 if (!priv->sh->aso_age_mng)
12616 return rte_flow_error_set(err, ENOTSUP,
12617 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12619 "shared age action not supported");
12620 return flow_dv_validate_action_age(0, action, dev, err);
12622 return rte_flow_error_set(err, ENOTSUP,
12623 RTE_FLOW_ERROR_TYPE_ACTION,
12625 "action type not supported");
12630 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12632 struct mlx5_priv *priv = dev->data->dev_private;
12635 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12636 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
12641 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12642 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
12646 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12647 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
12654 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12655 .validate = flow_dv_validate,
12656 .prepare = flow_dv_prepare,
12657 .translate = flow_dv_translate,
12658 .apply = flow_dv_apply,
12659 .remove = flow_dv_remove,
12660 .destroy = flow_dv_destroy,
12661 .query = flow_dv_query,
12662 .create_mtr_tbls = flow_dv_create_mtr_tbl,
12663 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12664 .create_policer_rules = flow_dv_create_policer_rules,
12665 .destroy_policer_rules = flow_dv_destroy_policer_rules,
12666 .counter_alloc = flow_dv_counter_allocate,
12667 .counter_free = flow_dv_counter_free,
12668 .counter_query = flow_dv_counter_query,
12669 .get_aged_flows = flow_get_aged_flows,
12670 .action_validate = flow_dv_action_validate,
12671 .action_create = flow_dv_action_create,
12672 .action_destroy = flow_dv_action_destroy,
12673 .action_update = flow_dv_action_update,
12674 .action_query = flow_dv_action_query,
12675 .sync_domain = flow_dv_sync_domain,
12678 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */