drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static int
  77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  78                              struct mlx5_flow_tbl_resource *tbl);
  79
  80 /**
  81  * Initialize flow attributes structure according to flow items' types.
  82  *
  83  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  84  * mode. For tunnel mode, the items to be modified are the outermost ones.
  85  *
  86  * @param[in] item
  87  *   Pointer to item specification.
  88  * @param[out] attr
  89  *   Pointer to flow attributes structure.
  90  * @param[in] dev_flow
  91  *   Pointer to the sub flow.
  92  * @param[in] tunnel_decap
  93  *   Whether action is after tunnel decapsulation.
  94  */
  95 static void
  96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  97                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  98 {
  99         uint64_t layers = dev_flow->handle->layers;
 100
 101         /*
 102          * If layers is already initialized, it means this dev_flow is the
 103          * suffix flow, the layers flags is set by the prefix flow. Need to
 104          * use the layer flags from prefix flow as the suffix flow may not
 105          * have the user defined items as the flow is split.
 106          */
 107         if (layers) {
 108                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 109                         attr->ipv4 = 1;
 110                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 111                         attr->ipv6 = 1;
 112                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 113                         attr->tcp = 1;
 114                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 115                         attr->udp = 1;
 116                 attr->valid = 1;
 117                 return;
 118         }
 119         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 120                 uint8_t next_protocol = 0xff;
 121                 switch (item->type) {
 122                 case RTE_FLOW_ITEM_TYPE_GRE:
 123                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 126                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 127                 case RTE_FLOW_ITEM_TYPE_MPLS:
 128                         if (tunnel_decap)
 129                                 attr->attr = 0;
 130                         break;
 131                 case RTE_FLOW_ITEM_TYPE_IPV4:
 132                         if (!attr->ipv6)
 133                                 attr->ipv4 = 1;
 134                         if (item->mask != NULL &&
 135                             ((const struct rte_flow_item_ipv4 *)
 136                             item->mask)->hdr.next_proto_id)
 137                                 next_protocol =
 138                                     ((const struct rte_flow_item_ipv4 *)
 139                                       (item->spec))->hdr.next_proto_id &
 140                                     ((const struct rte_flow_item_ipv4 *)
 141                                       (item->mask))->hdr.next_proto_id;
 142                         if ((next_protocol == IPPROTO_IPIP ||
 143                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 144                                 attr->attr = 0;
 145                         break;
 146                 case RTE_FLOW_ITEM_TYPE_IPV6:
 147                         if (!attr->ipv4)
 148                                 attr->ipv6 = 1;
 149                         if (item->mask != NULL &&
 150                             ((const struct rte_flow_item_ipv6 *)
 151                             item->mask)->hdr.proto)
 152                                 next_protocol =
 153                                     ((const struct rte_flow_item_ipv6 *)
 154                                       (item->spec))->hdr.proto &
 155                                     ((const struct rte_flow_item_ipv6 *)
 156                                       (item->mask))->hdr.proto;
 157                         if ((next_protocol == IPPROTO_IPIP ||
 158                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 159                                 attr->attr = 0;
 160                         break;
 161                 case RTE_FLOW_ITEM_TYPE_UDP:
 162                         if (!attr->tcp)
 163                                 attr->udp = 1;
 164                         break;
 165                 case RTE_FLOW_ITEM_TYPE_TCP:
 166                         if (!attr->udp)
 167                                 attr->tcp = 1;
 168                         break;
 169                 default:
 170                         break;
 171                 }
 172         }
 173         attr->valid = 1;
 174 }
 175
 176 /**
 177  * Convert rte_mtr_color to mlx5 color.
 178  *
 179  * @param[in] rcol
 180  *   rte_mtr_color.
 181  *
 182  * @return
 183  *   mlx5 color.
 184  */
 185 static int
 186 rte_col_2_mlx5_col(enum rte_color rcol)
 187 {
 188         switch (rcol) {
 189         case RTE_COLOR_GREEN:
 190                 return MLX5_FLOW_COLOR_GREEN;
 191         case RTE_COLOR_YELLOW:
 192                 return MLX5_FLOW_COLOR_YELLOW;
 193         case RTE_COLOR_RED:
 194                 return MLX5_FLOW_COLOR_RED;
 195         default:
 196                 break;
 197         }
 198         return MLX5_FLOW_COLOR_UNDEFINED;
 199 }
 200
 201 struct field_modify_info {
 202         uint32_t size; /* Size of field in protocol header, in bytes. */
 203         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 204         enum mlx5_modification_field id;
 205 };
 206
 207 struct field_modify_info modify_eth[] = {
 208         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 209         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 210         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 211         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 212         {0, 0, 0},
 213 };
 214
 215 struct field_modify_info modify_vlan_out_first_vid[] = {
 216         /* Size in bits !!! */
 217         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 218         {0, 0, 0},
 219 };
 220
 221 struct field_modify_info modify_ipv4[] = {
 222         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 223         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 224         {4, 12, MLX5_MODI_OUT_SIPV4},
 225         {4, 16, MLX5_MODI_OUT_DIPV4},
 226         {0, 0, 0},
 227 };
 228
 229 struct field_modify_info modify_ipv6[] = {
 230         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 231         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 232         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 233         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 234         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 235         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 236         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 237         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 238         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 239         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 240         {0, 0, 0},
 241 };
 242
 243 struct field_modify_info modify_udp[] = {
 244         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 245         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 246         {0, 0, 0},
 247 };
 248
 249 struct field_modify_info modify_tcp[] = {
 250         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 251         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 252         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 253         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 254         {0, 0, 0},
 255 };
 256
 257 static void
 258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 259                           uint8_t next_protocol, uint64_t *item_flags,
 260                           int *tunnel)
 261 {
 262         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 263                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 264         if (next_protocol == IPPROTO_IPIP) {
 265                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 266                 *tunnel = 1;
 267         }
 268         if (next_protocol == IPPROTO_IPV6) {
 269                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 270                 *tunnel = 1;
 271         }
 272 }
 273
 274 /**
 275  * Acquire the synchronizing object to protect multithreaded access
 276  * to shared dv context. Lock occurs only if context is actually
 277  * shared, i.e. we have multiport IB device and representors are
 278  * created.
 279  *
 280  * @param[in] dev
 281  *   Pointer to the rte_eth_dev structure.
 282  */
 283 static void
 284 flow_dv_shared_lock(struct rte_eth_dev *dev)
 285 {
 286         struct mlx5_priv *priv = dev->data->dev_private;
 287         struct mlx5_ibv_shared *sh = priv->sh;
 288
 289         if (sh->dv_refcnt > 1) {
 290                 int ret;
 291
 292                 ret = pthread_mutex_lock(&sh->dv_mutex);
 293                 MLX5_ASSERT(!ret);
 294                 (void)ret;
 295         }
 296 }
 297
 298 static void
 299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 300 {
 301         struct mlx5_priv *priv = dev->data->dev_private;
 302         struct mlx5_ibv_shared *sh = priv->sh;
 303
 304         if (sh->dv_refcnt > 1) {
 305                 int ret;
 306
 307                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 308                 MLX5_ASSERT(!ret);
 309                 (void)ret;
 310         }
 311 }
 312
 313 /* Update VLAN's VID/PCP based on input rte_flow_action.
 314  *
 315  * @param[in] action
 316  *   Pointer to struct rte_flow_action.
 317  * @param[out] vlan
 318  *   Pointer to struct rte_vlan_hdr.
 319  */
 320 static void
 321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 322                          struct rte_vlan_hdr *vlan)
 323 {
 324         uint16_t vlan_tci;
 325         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 326                 vlan_tci =
 327                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 328                                                action->conf)->vlan_pcp;
 329                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 330                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 331                 vlan->vlan_tci |= vlan_tci;
 332         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 334                 vlan->vlan_tci |= rte_be_to_cpu_16
 335                     (((const struct rte_flow_action_of_set_vlan_vid *)
 336                                              action->conf)->vlan_vid);
 337         }
 338 }
 339
 340 /**
 341  * Fetch 1, 2, 3 or 4 byte field from the byte array
 342  * and return as unsigned integer in host-endian format.
 343  *
 344  * @param[in] data
 345  *   Pointer to data array.
 346  * @param[in] size
 347  *   Size of field to extract.
 348  *
 349  * @return
 350  *   converted field in host endian format.
 351  */
 352 static inline uint32_t
 353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 354 {
 355         uint32_t ret;
 356
 357         switch (size) {
 358         case 1:
 359                 ret = *data;
 360                 break;
 361         case 2:
 362                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 363                 break;
 364         case 3:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 367                 break;
 368         case 4:
 369                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 370                 break;
 371         default:
 372                 MLX5_ASSERT(false);
 373                 ret = 0;
 374                 break;
 375         }
 376         return ret;
 377 }
 378
 379 /**
 380  * Convert modify-header action to DV specification.
 381  *
 382  * Data length of each action is determined by provided field description
 383  * and the item mask. Data bit offset and width of each action is determined
 384  * by provided item mask.
 385  *
 386  * @param[in] item
 387  *   Pointer to item specification.
 388  * @param[in] field
 389  *   Pointer to field modification information.
 390  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 393  * @param[in] dcopy
 394  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 395  *   Negative offset value sets the same offset as source offset.
 396  *   size field is ignored, value is taken from source field.
 397  * @param[in,out] resource
 398  *   Pointer to the modify-header resource.
 399  * @param[in] type
 400  *   Type of modification.
 401  * @param[out] error
 402  *   Pointer to the error structure.
 403  *
 404  * @return
 405  *   0 on success, a negative errno value otherwise and rte_errno is set.
 406  */
 407 static int
 408 flow_dv_convert_modify_action(struct rte_flow_item *item,
 409                               struct field_modify_info *field,
 410                               struct field_modify_info *dcopy,
 411                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 412                               uint32_t type, struct rte_flow_error *error)
 413 {
 414         uint32_t i = resource->actions_num;
 415         struct mlx5_modification_cmd *actions = resource->actions;
 416
 417         /*
 418          * The item and mask are provided in big-endian format.
 419          * The fields should be presented as in big-endian format either.
 420          * Mask must be always present, it defines the actual field width.
 421          */
 422         MLX5_ASSERT(item->mask);
 423         MLX5_ASSERT(field->size);
 424         do {
 425                 unsigned int size_b;
 426                 unsigned int off_b;
 427                 uint32_t mask;
 428                 uint32_t data;
 429
 430                 if (i >= MLX5_MAX_MODIFY_NUM)
 431                         return rte_flow_error_set(error, EINVAL,
 432                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 433                                  "too many items to modify");
 434                 /* Fetch variable byte size mask from the array. */
 435                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 436                                            field->offset, field->size);
 437                 MLX5_ASSERT(mask);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate GTP item.
1644  *
1645  * @param[in] dev
1646  *   Pointer to the rte_eth_dev structure.
1647  * @param[in] item
1648  *   Item specification.
1649  * @param[in] item_flags
1650  *   Bit-fields that holds the items detected until now.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1659                           const struct rte_flow_item *item,
1660                           uint64_t item_flags,
1661                           struct rte_flow_error *error)
1662 {
1663         struct mlx5_priv *priv = dev->data->dev_private;
1664         const struct rte_flow_item_gtp *mask = item->mask;
1665         const struct rte_flow_item_gtp nic_mask = {
1666                 .msg_type = 0xff,
1667                 .teid = RTE_BE32(0xffffffff),
1668         };
1669
1670         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1671                 return rte_flow_error_set(error, ENOTSUP,
1672                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1673                                           "GTP support is not enabled");
1674         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1675                 return rte_flow_error_set(error, ENOTSUP,
1676                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1677                                           "multiple tunnel layers not"
1678                                           " supported");
1679         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1680                 return rte_flow_error_set(error, EINVAL,
1681                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1682                                           "no outer UDP layer found");
1683         if (!mask)
1684                 mask = &rte_flow_item_gtp_mask;
1685         return mlx5_flow_item_acceptable
1686                 (item, (const uint8_t *)mask,
1687                  (const uint8_t *)&nic_mask,
1688                  sizeof(struct rte_flow_item_gtp),
1689                  error);
1690 }
1691
1692 /**
1693  * Validate the pop VLAN action.
1694  *
1695  * @param[in] dev
1696  *   Pointer to the rte_eth_dev structure.
1697  * @param[in] action_flags
1698  *   Holds the actions detected until now.
1699  * @param[in] action
1700  *   Pointer to the pop vlan action.
1701  * @param[in] item_flags
1702  *   The items found in this flow rule.
1703  * @param[in] attr
1704  *   Pointer to flow attributes.
1705  * @param[out] error
1706  *   Pointer to error structure.
1707  *
1708  * @return
1709  *   0 on success, a negative errno value otherwise and rte_errno is set.
1710  */
1711 static int
1712 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1713                                  uint64_t action_flags,
1714                                  const struct rte_flow_action *action,
1715                                  uint64_t item_flags,
1716                                  const struct rte_flow_attr *attr,
1717                                  struct rte_flow_error *error)
1718 {
1719         const struct mlx5_priv *priv = dev->data->dev_private;
1720
1721         (void)action;
1722         (void)attr;
1723         if (!priv->sh->pop_vlan_action)
1724                 return rte_flow_error_set(error, ENOTSUP,
1725                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726                                           NULL,
1727                                           "pop vlan action is not supported");
1728         if (attr->egress)
1729                 return rte_flow_error_set(error, ENOTSUP,
1730                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731                                           NULL,
1732                                           "pop vlan action not supported for "
1733                                           "egress");
1734         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1735                 return rte_flow_error_set(error, ENOTSUP,
1736                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1737                                           "no support for multiple VLAN "
1738                                           "actions");
1739         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1740                 return rte_flow_error_set(error, ENOTSUP,
1741                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742                                           NULL,
1743                                           "cannot pop vlan without a "
1744                                           "match on (outer) vlan in the flow");
1745         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1748                                           "wrong action order, port_id should "
1749                                           "be after pop VLAN action");
1750         if (!attr->transfer && priv->representor)
1751                 return rte_flow_error_set(error, ENOTSUP,
1752                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1753                                           "pop vlan action for VF representor "
1754                                           "not supported on NIC table");
1755         return 0;
1756 }
1757
1758 /**
1759  * Get VLAN default info from vlan match info.
1760  *
1761  * @param[in] items
1762  *   the list of item specifications.
1763  * @param[out] vlan
1764  *   pointer VLAN info to fill to.
1765  *
1766  * @return
1767  *   0 on success, a negative errno value otherwise and rte_errno is set.
1768  */
1769 static void
1770 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1771                                   struct rte_vlan_hdr *vlan)
1772 {
1773         const struct rte_flow_item_vlan nic_mask = {
1774                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1775                                 MLX5DV_FLOW_VLAN_VID_MASK),
1776                 .inner_type = RTE_BE16(0xffff),
1777         };
1778
1779         if (items == NULL)
1780                 return;
1781         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1782                 int type = items->type;
1783
1784                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1785                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1786                         break;
1787         }
1788         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1789                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1790                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1791
1792                 if (!vlan_m)
1793                         vlan_m = &nic_mask;
1794                 /* Only full match values are accepted */
1795                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1796                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1797                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798                         vlan->vlan_tci |=
1799                                 rte_be_to_cpu_16(vlan_v->tci &
1800                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801                 }
1802                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1803                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1804                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805                         vlan->vlan_tci |=
1806                                 rte_be_to_cpu_16(vlan_v->tci &
1807                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808                 }
1809                 if (vlan_m->inner_type == nic_mask.inner_type)
1810                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1811                                                            vlan_m->inner_type);
1812         }
1813 }
1814
1815 /**
1816  * Validate the push VLAN action.
1817  *
1818  * @param[in] dev
1819  *   Pointer to the rte_eth_dev structure.
1820  * @param[in] action_flags
1821  *   Holds the actions detected until now.
1822  * @param[in] item_flags
1823  *   The items found in this flow rule.
1824  * @param[in] action
1825  *   Pointer to the action structure.
1826  * @param[in] attr
1827  *   Pointer to flow attributes
1828  * @param[out] error
1829  *   Pointer to error structure.
1830  *
1831  * @return
1832  *   0 on success, a negative errno value otherwise and rte_errno is set.
1833  */
1834 static int
1835 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1836                                   uint64_t action_flags,
1837                                   const struct rte_flow_item_vlan *vlan_m,
1838                                   const struct rte_flow_action *action,
1839                                   const struct rte_flow_attr *attr,
1840                                   struct rte_flow_error *error)
1841 {
1842         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1843         const struct mlx5_priv *priv = dev->data->dev_private;
1844
1845         if (!attr->transfer && attr->ingress)
1846                 return rte_flow_error_set(error, ENOTSUP,
1847                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848                                           NULL,
1849                                           "push VLAN action not supported for "
1850                                           "ingress");
1851         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1852             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1853                 return rte_flow_error_set(error, EINVAL,
1854                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1855                                           "invalid vlan ethertype");
1856         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1857                 return rte_flow_error_set(error, ENOTSUP,
1858                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1859                                           "no support for multiple VLAN "
1860                                           "actions");
1861         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1862                 return rte_flow_error_set(error, EINVAL,
1863                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1864                                           "wrong action order, port_id should "
1865                                           "be after push VLAN");
1866         if (!attr->transfer && priv->representor)
1867                 return rte_flow_error_set(error, ENOTSUP,
1868                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1869                                           "push vlan action for VF representor "
1870                                           "not supported on NIC table");
1871         if (vlan_m &&
1872             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1873             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1874                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1875             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1876             !(mlx5_flow_find_action
1877                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1878                 return rte_flow_error_set(error, EINVAL,
1879                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1880                                           "not full match mask on VLAN PCP and "
1881                                           "there is no of_set_vlan_pcp action, "
1882                                           "push VLAN action cannot figure out "
1883                                           "PCP value");
1884         if (vlan_m &&
1885             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1886             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1887                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1888             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1889             !(mlx5_flow_find_action
1890                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1891                 return rte_flow_error_set(error, EINVAL,
1892                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1893                                           "not full match mask on VLAN VID and "
1894                                           "there is no of_set_vlan_vid action, "
1895                                           "push VLAN action cannot figure out "
1896                                           "VID value");
1897         (void)attr;
1898         return 0;
1899 }
1900
1901 /**
1902  * Validate the set VLAN PCP.
1903  *
1904  * @param[in] action_flags
1905  *   Holds the actions detected until now.
1906  * @param[in] actions
1907  *   Pointer to the list of actions remaining in the flow rule.
1908  * @param[out] error
1909  *   Pointer to error structure.
1910  *
1911  * @return
1912  *   0 on success, a negative errno value otherwise and rte_errno is set.
1913  */
1914 static int
1915 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1916                                      const struct rte_flow_action actions[],
1917                                      struct rte_flow_error *error)
1918 {
1919         const struct rte_flow_action *action = actions;
1920         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1921
1922         if (conf->vlan_pcp > 7)
1923                 return rte_flow_error_set(error, EINVAL,
1924                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1925                                           "VLAN PCP value is too big");
1926         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1927                 return rte_flow_error_set(error, ENOTSUP,
1928                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1929                                           "set VLAN PCP action must follow "
1930                                           "the push VLAN action");
1931         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1932                 return rte_flow_error_set(error, ENOTSUP,
1933                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1934                                           "Multiple VLAN PCP modification are "
1935                                           "not supported");
1936         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1937                 return rte_flow_error_set(error, EINVAL,
1938                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1939                                           "wrong action order, port_id should "
1940                                           "be after set VLAN PCP");
1941         return 0;
1942 }
1943
1944 /**
1945  * Validate the set VLAN VID.
1946  *
1947  * @param[in] item_flags
1948  *   Holds the items detected in this rule.
1949  * @param[in] action_flags
1950  *   Holds the actions detected until now.
1951  * @param[in] actions
1952  *   Pointer to the list of actions remaining in the flow rule.
1953  * @param[out] error
1954  *   Pointer to error structure.
1955  *
1956  * @return
1957  *   0 on success, a negative errno value otherwise and rte_errno is set.
1958  */
1959 static int
1960 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1961                                      uint64_t action_flags,
1962                                      const struct rte_flow_action actions[],
1963                                      struct rte_flow_error *error)
1964 {
1965         const struct rte_flow_action *action = actions;
1966         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1967
1968         if (conf->vlan_vid > RTE_BE16(0xFFE))
1969                 return rte_flow_error_set(error, EINVAL,
1970                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1971                                           "VLAN VID value is too big");
1972         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1973             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1974                 return rte_flow_error_set(error, ENOTSUP,
1975                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1976                                           "set VLAN VID action must follow push"
1977                                           " VLAN action or match on VLAN item");
1978         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1979                 return rte_flow_error_set(error, ENOTSUP,
1980                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1981                                           "Multiple VLAN VID modifications are "
1982                                           "not supported");
1983         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1984                 return rte_flow_error_set(error, EINVAL,
1985                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1986                                           "wrong action order, port_id should "
1987                                           "be after set VLAN VID");
1988         return 0;
1989 }
1990
1991 /*
1992  * Validate the FLAG action.
1993  *
1994  * @param[in] dev
1995  *   Pointer to the rte_eth_dev structure.
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] attr
1999  *   Pointer to flow attributes
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2008                              uint64_t action_flags,
2009                              const struct rte_flow_attr *attr,
2010                              struct rte_flow_error *error)
2011 {
2012         struct mlx5_priv *priv = dev->data->dev_private;
2013         struct mlx5_dev_config *config = &priv->config;
2014         int ret;
2015
2016         /* Fall back if no extended metadata register support. */
2017         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2018                 return mlx5_flow_validate_action_flag(action_flags, attr,
2019                                                       error);
2020         /* Extensive metadata mode requires registers. */
2021         if (!mlx5_flow_ext_mreg_supported(dev))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2024                                           "no metadata registers "
2025                                           "to support flag action");
2026         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2029                                           "extended metadata register"
2030                                           " isn't available");
2031         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2032         if (ret < 0)
2033                 return ret;
2034         MLX5_ASSERT(ret > 0);
2035         if (action_flags & MLX5_FLOW_ACTION_MARK)
2036                 return rte_flow_error_set(error, EINVAL,
2037                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2038                                           "can't mark and flag in same flow");
2039         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2040                 return rte_flow_error_set(error, EINVAL,
2041                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042                                           "can't have 2 flag"
2043                                           " actions in same flow");
2044         return 0;
2045 }
2046
2047 /**
2048  * Validate MARK action.
2049  *
2050  * @param[in] dev
2051  *   Pointer to the rte_eth_dev structure.
2052  * @param[in] action
2053  *   Pointer to action.
2054  * @param[in] action_flags
2055  *   Holds the actions detected until now.
2056  * @param[in] attr
2057  *   Pointer to flow attributes
2058  * @param[out] error
2059  *   Pointer to error structure.
2060  *
2061  * @return
2062  *   0 on success, a negative errno value otherwise and rte_errno is set.
2063  */
2064 static int
2065 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2066                              const struct rte_flow_action *action,
2067                              uint64_t action_flags,
2068                              const struct rte_flow_attr *attr,
2069                              struct rte_flow_error *error)
2070 {
2071         struct mlx5_priv *priv = dev->data->dev_private;
2072         struct mlx5_dev_config *config = &priv->config;
2073         const struct rte_flow_action_mark *mark = action->conf;
2074         int ret;
2075
2076         /* Fall back if no extended metadata register support. */
2077         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2078                 return mlx5_flow_validate_action_mark(action, action_flags,
2079                                                       attr, error);
2080         /* Extensive metadata mode requires registers. */
2081         if (!mlx5_flow_ext_mreg_supported(dev))
2082                 return rte_flow_error_set(error, ENOTSUP,
2083                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2084                                           "no metadata registers "
2085                                           "to support mark action");
2086         if (!priv->sh->dv_mark_mask)
2087                 return rte_flow_error_set(error, ENOTSUP,
2088                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2089                                           "extended metadata register"
2090                                           " isn't available");
2091         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2092         if (ret < 0)
2093                 return ret;
2094         MLX5_ASSERT(ret > 0);
2095         if (!mark)
2096                 return rte_flow_error_set(error, EINVAL,
2097                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2098                                           "configuration cannot be null");
2099         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2100                 return rte_flow_error_set(error, EINVAL,
2101                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2102                                           &mark->id,
2103                                           "mark id exceeds the limit");
2104         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2105                 return rte_flow_error_set(error, EINVAL,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2107                                           "can't flag and mark in same flow");
2108         if (action_flags & MLX5_FLOW_ACTION_MARK)
2109                 return rte_flow_error_set(error, EINVAL,
2110                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2111                                           "can't have 2 mark actions in same"
2112                                           " flow");
2113         return 0;
2114 }
2115
2116 /**
2117  * Validate SET_META action.
2118  *
2119  * @param[in] dev
2120  *   Pointer to the rte_eth_dev structure.
2121  * @param[in] action
2122  *   Pointer to the action structure.
2123  * @param[in] action_flags
2124  *   Holds the actions detected until now.
2125  * @param[in] attr
2126  *   Pointer to flow attributes
2127  * @param[out] error
2128  *   Pointer to error structure.
2129  *
2130  * @return
2131  *   0 on success, a negative errno value otherwise and rte_errno is set.
2132  */
2133 static int
2134 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2135                                  const struct rte_flow_action *action,
2136                                  uint64_t action_flags __rte_unused,
2137                                  const struct rte_flow_attr *attr,
2138                                  struct rte_flow_error *error)
2139 {
2140         const struct rte_flow_action_set_meta *conf;
2141         uint32_t nic_mask = UINT32_MAX;
2142         int reg;
2143
2144         if (!mlx5_flow_ext_mreg_supported(dev))
2145                 return rte_flow_error_set(error, ENOTSUP,
2146                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2147                                           "extended metadata register"
2148                                           " isn't supported");
2149         reg = flow_dv_get_metadata_reg(dev, attr, error);
2150         if (reg < 0)
2151                 return reg;
2152         if (reg != REG_A && reg != REG_B) {
2153                 struct mlx5_priv *priv = dev->data->dev_private;
2154
2155                 nic_mask = priv->sh->dv_meta_mask;
2156         }
2157         if (!(action->conf))
2158                 return rte_flow_error_set(error, EINVAL,
2159                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2160                                           "configuration cannot be null");
2161         conf = (const struct rte_flow_action_set_meta *)action->conf;
2162         if (!conf->mask)
2163                 return rte_flow_error_set(error, EINVAL,
2164                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2165                                           "zero mask doesn't have any effect");
2166         if (conf->mask & ~nic_mask)
2167                 return rte_flow_error_set(error, EINVAL,
2168                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2169                                           "meta data must be within reg C0");
2170         return 0;
2171 }
2172
2173 /**
2174  * Validate SET_TAG action.
2175  *
2176  * @param[in] dev
2177  *   Pointer to the rte_eth_dev structure.
2178  * @param[in] action
2179  *   Pointer to the action structure.
2180  * @param[in] action_flags
2181  *   Holds the actions detected until now.
2182  * @param[in] attr
2183  *   Pointer to flow attributes
2184  * @param[out] error
2185  *   Pointer to error structure.
2186  *
2187  * @return
2188  *   0 on success, a negative errno value otherwise and rte_errno is set.
2189  */
2190 static int
2191 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2192                                 const struct rte_flow_action *action,
2193                                 uint64_t action_flags,
2194                                 const struct rte_flow_attr *attr,
2195                                 struct rte_flow_error *error)
2196 {
2197         const struct rte_flow_action_set_tag *conf;
2198         const uint64_t terminal_action_flags =
2199                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2200                 MLX5_FLOW_ACTION_RSS;
2201         int ret;
2202
2203         if (!mlx5_flow_ext_mreg_supported(dev))
2204                 return rte_flow_error_set(error, ENOTSUP,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2206                                           "extensive metadata register"
2207                                           " isn't supported");
2208         if (!(action->conf))
2209                 return rte_flow_error_set(error, EINVAL,
2210                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2211                                           "configuration cannot be null");
2212         conf = (const struct rte_flow_action_set_tag *)action->conf;
2213         if (!conf->mask)
2214                 return rte_flow_error_set(error, EINVAL,
2215                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2216                                           "zero mask doesn't have any effect");
2217         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2218         if (ret < 0)
2219                 return ret;
2220         if (!attr->transfer && attr->ingress &&
2221             (action_flags & terminal_action_flags))
2222                 return rte_flow_error_set(error, EINVAL,
2223                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2224                                           "set_tag has no effect"
2225                                           " with terminal actions");
2226         return 0;
2227 }
2228
2229 /**
2230  * Validate count action.
2231  *
2232  * @param[in] dev
2233  *   Pointer to rte_eth_dev structure.
2234  * @param[out] error
2235  *   Pointer to error structure.
2236  *
2237  * @return
2238  *   0 on success, a negative errno value otherwise and rte_errno is set.
2239  */
2240 static int
2241 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2242                               struct rte_flow_error *error)
2243 {
2244         struct mlx5_priv *priv = dev->data->dev_private;
2245
2246         if (!priv->config.devx)
2247                 goto notsup_err;
2248 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2249         return 0;
2250 #endif
2251 notsup_err:
2252         return rte_flow_error_set
2253                       (error, ENOTSUP,
2254                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2255                        NULL,
2256                        "count action not supported");
2257 }
2258
2259 /**
2260  * Validate the L2 encap action.
2261  *
2262  * @param[in] dev
2263  *   Pointer to the rte_eth_dev structure.
2264  * @param[in] action_flags
2265  *   Holds the actions detected until now.
2266  * @param[in] action
2267  *   Pointer to the action structure.
2268  * @param[in] attr
2269  *   Pointer to flow attributes.
2270  * @param[out] error
2271  *   Pointer to error structure.
2272  *
2273  * @return
2274  *   0 on success, a negative errno value otherwise and rte_errno is set.
2275  */
2276 static int
2277 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2278                                  uint64_t action_flags,
2279                                  const struct rte_flow_action *action,
2280                                  const struct rte_flow_attr *attr,
2281                                  struct rte_flow_error *error)
2282 {
2283         const struct mlx5_priv *priv = dev->data->dev_private;
2284
2285         if (!(action->conf))
2286                 return rte_flow_error_set(error, EINVAL,
2287                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2288                                           "configuration cannot be null");
2289         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2290                 return rte_flow_error_set(error, EINVAL,
2291                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2292                                           "can only have a single encap action "
2293                                           "in a flow");
2294         if (!attr->transfer && priv->representor)
2295                 return rte_flow_error_set(error, ENOTSUP,
2296                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2297                                           "encap action for VF representor "
2298                                           "not supported on NIC table");
2299         return 0;
2300 }
2301
2302 /**
2303  * Validate a decap action.
2304  *
2305  * @param[in] dev
2306  *   Pointer to the rte_eth_dev structure.
2307  * @param[in] action_flags
2308  *   Holds the actions detected until now.
2309  * @param[in] attr
2310  *   Pointer to flow attributes
2311  * @param[out] error
2312  *   Pointer to error structure.
2313  *
2314  * @return
2315  *   0 on success, a negative errno value otherwise and rte_errno is set.
2316  */
2317 static int
2318 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2319                               uint64_t action_flags,
2320                               const struct rte_flow_attr *attr,
2321                               struct rte_flow_error *error)
2322 {
2323         const struct mlx5_priv *priv = dev->data->dev_private;
2324
2325         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2326                 return rte_flow_error_set(error, ENOTSUP,
2327                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2328                                           action_flags &
2329                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2330                                           "have a single decap action" : "decap "
2331                                           "after encap is not supported");
2332         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2333                 return rte_flow_error_set(error, EINVAL,
2334                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2335                                           "can't have decap action after"
2336                                           " modify action");
2337         if (attr->egress)
2338                 return rte_flow_error_set(error, ENOTSUP,
2339                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2340                                           NULL,
2341                                           "decap action not supported for "
2342                                           "egress");
2343         if (!attr->transfer && priv->representor)
2344                 return rte_flow_error_set(error, ENOTSUP,
2345                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2346                                           "decap action for VF representor "
2347                                           "not supported on NIC table");
2348         return 0;
2349 }
2350
2351 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2352
2353 /**
2354  * Validate the raw encap and decap actions.
2355  *
2356  * @param[in] dev
2357  *   Pointer to the rte_eth_dev structure.
2358  * @param[in] decap
2359  *   Pointer to the decap action.
2360  * @param[in] encap
2361  *   Pointer to the encap action.
2362  * @param[in] attr
2363  *   Pointer to flow attributes
2364  * @param[in/out] action_flags
2365  *   Holds the actions detected until now.
2366  * @param[out] actions_n
2367  *   pointer to the number of actions counter.
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_raw_encap_decap
2376         (struct rte_eth_dev *dev,
2377          const struct rte_flow_action_raw_decap *decap,
2378          const struct rte_flow_action_raw_encap *encap,
2379          const struct rte_flow_attr *attr, uint64_t *action_flags,
2380          int *actions_n, struct rte_flow_error *error)
2381 {
2382         const struct mlx5_priv *priv = dev->data->dev_private;
2383         int ret;
2384
2385         if (encap && (!encap->size || !encap->data))
2386                 return rte_flow_error_set(error, EINVAL,
2387                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2388                                           "raw encap data cannot be empty");
2389         if (decap && encap) {
2390                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2391                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2392                         /* L3 encap. */
2393                         decap = NULL;
2394                 else if (encap->size <=
2395                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2396                            decap->size >
2397                            MLX5_ENCAPSULATION_DECISION_SIZE)
2398                         /* L3 decap. */
2399                         encap = NULL;
2400                 else if (encap->size >
2401                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2402                            decap->size >
2403                            MLX5_ENCAPSULATION_DECISION_SIZE)
2404                         /* 2 L2 actions: encap and decap. */
2405                         ;
2406                 else
2407                         return rte_flow_error_set(error,
2408                                 ENOTSUP,
2409                                 RTE_FLOW_ERROR_TYPE_ACTION,
2410                                 NULL, "unsupported too small "
2411                                 "raw decap and too small raw "
2412                                 "encap combination");
2413         }
2414         if (decap) {
2415                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2416                                                     error);
2417                 if (ret < 0)
2418                         return ret;
2419                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2420                 ++(*actions_n);
2421         }
2422         if (encap) {
2423                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2424                         return rte_flow_error_set(error, ENOTSUP,
2425                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2426                                                   NULL,
2427                                                   "small raw encap size");
2428                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2429                         return rte_flow_error_set(error, EINVAL,
2430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2431                                                   NULL,
2432                                                   "more than one encap action");
2433                 if (!attr->transfer && priv->representor)
2434                         return rte_flow_error_set
2435                                         (error, ENOTSUP,
2436                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2437                                          "encap action for VF representor "
2438                                          "not supported on NIC table");
2439                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2440                 ++(*actions_n);
2441         }
2442         return 0;
2443 }
2444
2445 /**
2446  * Find existing encap/decap resource or create and register a new one.
2447  *
2448  * @param[in, out] dev
2449  *   Pointer to rte_eth_dev structure.
2450  * @param[in, out] resource
2451  *   Pointer to encap/decap resource.
2452  * @parm[in, out] dev_flow
2453  *   Pointer to the dev_flow.
2454  * @param[out] error
2455  *   pointer to error structure.
2456  *
2457  * @return
2458  *   0 on success otherwise -errno and errno is set.
2459  */
2460 static int
2461 flow_dv_encap_decap_resource_register
2462                         (struct rte_eth_dev *dev,
2463                          struct mlx5_flow_dv_encap_decap_resource *resource,
2464                          struct mlx5_flow *dev_flow,
2465                          struct rte_flow_error *error)
2466 {
2467         struct mlx5_priv *priv = dev->data->dev_private;
2468         struct mlx5_ibv_shared *sh = priv->sh;
2469         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2470         struct mlx5dv_dr_domain *domain;
2471         uint32_t idx = 0;
2472
2473         resource->flags = dev_flow->dv.group ? 0 : 1;
2474         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2475                 domain = sh->fdb_domain;
2476         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2477                 domain = sh->rx_domain;
2478         else
2479                 domain = sh->tx_domain;
2480         /* Lookup a matching resource from cache. */
2481         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2482                       cache_resource, next) {
2483                 if (resource->reformat_type == cache_resource->reformat_type &&
2484                     resource->ft_type == cache_resource->ft_type &&
2485                     resource->flags == cache_resource->flags &&
2486                     resource->size == cache_resource->size &&
2487                     !memcmp((const void *)resource->buf,
2488                             (const void *)cache_resource->buf,
2489                             resource->size)) {
2490                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2491                                 (void *)cache_resource,
2492                                 rte_atomic32_read(&cache_resource->refcnt));
2493                         rte_atomic32_inc(&cache_resource->refcnt);
2494                         dev_flow->handle->dvh.rix_encap_decap = idx;
2495                         dev_flow->dv.encap_decap = cache_resource;
2496                         return 0;
2497                 }
2498         }
2499         /* Register new encap/decap resource. */
2500         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2501                                        &dev_flow->handle->dvh.rix_encap_decap);
2502         if (!cache_resource)
2503                 return rte_flow_error_set(error, ENOMEM,
2504                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2505                                           "cannot allocate resource memory");
2506         *cache_resource = *resource;
2507         cache_resource->verbs_action =
2508                 mlx5_glue->dv_create_flow_action_packet_reformat
2509                         (sh->ctx, cache_resource->reformat_type,
2510                          cache_resource->ft_type, domain, cache_resource->flags,
2511                          cache_resource->size,
2512                          (cache_resource->size ? cache_resource->buf : NULL));
2513         if (!cache_resource->verbs_action) {
2514                 rte_free(cache_resource);
2515                 return rte_flow_error_set(error, ENOMEM,
2516                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2517                                           NULL, "cannot create action");
2518         }
2519         rte_atomic32_init(&cache_resource->refcnt);
2520         rte_atomic32_inc(&cache_resource->refcnt);
2521         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2522                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2523                      next);
2524         dev_flow->dv.encap_decap = cache_resource;
2525         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2526                 (void *)cache_resource,
2527                 rte_atomic32_read(&cache_resource->refcnt));
2528         return 0;
2529 }
2530
2531 /**
2532  * Find existing table jump resource or create and register a new one.
2533  *
2534  * @param[in, out] dev
2535  *   Pointer to rte_eth_dev structure.
2536  * @param[in, out] tbl
2537  *   Pointer to flow table resource.
2538  * @parm[in, out] dev_flow
2539  *   Pointer to the dev_flow.
2540  * @param[out] error
2541  *   pointer to error structure.
2542  *
2543  * @return
2544  *   0 on success otherwise -errno and errno is set.
2545  */
2546 static int
2547 flow_dv_jump_tbl_resource_register
2548                         (struct rte_eth_dev *dev __rte_unused,
2549                          struct mlx5_flow_tbl_resource *tbl,
2550                          struct mlx5_flow *dev_flow,
2551                          struct rte_flow_error *error)
2552 {
2553         struct mlx5_flow_tbl_data_entry *tbl_data =
2554                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2555         int cnt;
2556
2557         MLX5_ASSERT(tbl);
2558         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2559         if (!cnt) {
2560                 tbl_data->jump.action =
2561                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2562                         (tbl->obj);
2563                 if (!tbl_data->jump.action)
2564                         return rte_flow_error_set(error, ENOMEM,
2565                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2566                                         NULL, "cannot create jump action");
2567                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2568                         (void *)&tbl_data->jump, cnt);
2569         } else {
2570                 /* old jump should not make the table ref++. */
2571                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2572                 MLX5_ASSERT(tbl_data->jump.action);
2573                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2574                         (void *)&tbl_data->jump, cnt);
2575         }
2576         rte_atomic32_inc(&tbl_data->jump.refcnt);
2577         dev_flow->handle->rix_jump = tbl_data->idx;
2578         dev_flow->dv.jump = &tbl_data->jump;
2579         return 0;
2580 }
2581
2582 /**
2583  * Find existing table port ID resource or create and register a new one.
2584  *
2585  * @param[in, out] dev
2586  *   Pointer to rte_eth_dev structure.
2587  * @param[in, out] resource
2588  *   Pointer to port ID action resource.
2589  * @parm[in, out] dev_flow
2590  *   Pointer to the dev_flow.
2591  * @param[out] error
2592  *   pointer to error structure.
2593  *
2594  * @return
2595  *   0 on success otherwise -errno and errno is set.
2596  */
2597 static int
2598 flow_dv_port_id_action_resource_register
2599                         (struct rte_eth_dev *dev,
2600                          struct mlx5_flow_dv_port_id_action_resource *resource,
2601                          struct mlx5_flow *dev_flow,
2602                          struct rte_flow_error *error)
2603 {
2604         struct mlx5_priv *priv = dev->data->dev_private;
2605         struct mlx5_ibv_shared *sh = priv->sh;
2606         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2607         uint32_t idx = 0;
2608
2609         /* Lookup a matching resource from cache. */
2610         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2611                       idx, cache_resource, next) {
2612                 if (resource->port_id == cache_resource->port_id) {
2613                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2614                                 "refcnt %d++",
2615                                 (void *)cache_resource,
2616                                 rte_atomic32_read(&cache_resource->refcnt));
2617                         rte_atomic32_inc(&cache_resource->refcnt);
2618                         dev_flow->handle->rix_port_id_action = idx;
2619                         dev_flow->dv.port_id_action = cache_resource;
2620                         return 0;
2621                 }
2622         }
2623         /* Register new port id action resource. */
2624         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2625                                        &dev_flow->handle->rix_port_id_action);
2626         if (!cache_resource)
2627                 return rte_flow_error_set(error, ENOMEM,
2628                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2629                                           "cannot allocate resource memory");
2630         *cache_resource = *resource;
2631         /*
2632          * Depending on rdma_core version the glue routine calls
2633          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2634          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2635          */
2636         cache_resource->action =
2637                 mlx5_glue->dr_create_flow_action_dest_port
2638                         (priv->sh->fdb_domain, resource->port_id);
2639         if (!cache_resource->action) {
2640                 rte_free(cache_resource);
2641                 return rte_flow_error_set(error, ENOMEM,
2642                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2643                                           NULL, "cannot create action");
2644         }
2645         rte_atomic32_init(&cache_resource->refcnt);
2646         rte_atomic32_inc(&cache_resource->refcnt);
2647         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2648                      dev_flow->handle->rix_port_id_action, cache_resource,
2649                      next);
2650         dev_flow->dv.port_id_action = cache_resource;
2651         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2652                 (void *)cache_resource,
2653                 rte_atomic32_read(&cache_resource->refcnt));
2654         return 0;
2655 }
2656
2657 /**
2658  * Find existing push vlan resource or create and register a new one.
2659  *
2660  * @param [in, out] dev
2661  *   Pointer to rte_eth_dev structure.
2662  * @param[in, out] resource
2663  *   Pointer to port ID action resource.
2664  * @parm[in, out] dev_flow
2665  *   Pointer to the dev_flow.
2666  * @param[out] error
2667  *   pointer to error structure.
2668  *
2669  * @return
2670  *   0 on success otherwise -errno and errno is set.
2671  */
2672 static int
2673 flow_dv_push_vlan_action_resource_register
2674                        (struct rte_eth_dev *dev,
2675                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2676                         struct mlx5_flow *dev_flow,
2677                         struct rte_flow_error *error)
2678 {
2679         struct mlx5_priv *priv = dev->data->dev_private;
2680         struct mlx5_ibv_shared *sh = priv->sh;
2681         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2682         struct mlx5dv_dr_domain *domain;
2683         uint32_t idx = 0;
2684
2685         /* Lookup a matching resource from cache. */
2686         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2687                       sh->push_vlan_action_list, idx, cache_resource, next) {
2688                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2689                     resource->ft_type == cache_resource->ft_type) {
2690                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2691                                 "refcnt %d++",
2692                                 (void *)cache_resource,
2693                                 rte_atomic32_read(&cache_resource->refcnt));
2694                         rte_atomic32_inc(&cache_resource->refcnt);
2695                         dev_flow->handle->dvh.rix_push_vlan = idx;
2696                         dev_flow->dv.push_vlan_res = cache_resource;
2697                         return 0;
2698                 }
2699         }
2700         /* Register new push_vlan action resource. */
2701         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2702                                        &dev_flow->handle->dvh.rix_push_vlan);
2703         if (!cache_resource)
2704                 return rte_flow_error_set(error, ENOMEM,
2705                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2706                                           "cannot allocate resource memory");
2707         *cache_resource = *resource;
2708         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2709                 domain = sh->fdb_domain;
2710         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2711                 domain = sh->rx_domain;
2712         else
2713                 domain = sh->tx_domain;
2714         cache_resource->action =
2715                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2716                                                            resource->vlan_tag);
2717         if (!cache_resource->action) {
2718                 rte_free(cache_resource);
2719                 return rte_flow_error_set(error, ENOMEM,
2720                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2721                                           NULL, "cannot create action");
2722         }
2723         rte_atomic32_init(&cache_resource->refcnt);
2724         rte_atomic32_inc(&cache_resource->refcnt);
2725         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2726                      &sh->push_vlan_action_list,
2727                      dev_flow->handle->dvh.rix_push_vlan,
2728                      cache_resource, next);
2729         dev_flow->dv.push_vlan_res = cache_resource;
2730         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2731                 (void *)cache_resource,
2732                 rte_atomic32_read(&cache_resource->refcnt));
2733         return 0;
2734 }
2735 /**
2736  * Get the size of specific rte_flow_item_type
2737  *
2738  * @param[in] item_type
2739  *   Tested rte_flow_item_type.
2740  *
2741  * @return
2742  *   sizeof struct item_type, 0 if void or irrelevant.
2743  */
2744 static size_t
2745 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2746 {
2747         size_t retval;
2748
2749         switch (item_type) {
2750         case RTE_FLOW_ITEM_TYPE_ETH:
2751                 retval = sizeof(struct rte_flow_item_eth);
2752                 break;
2753         case RTE_FLOW_ITEM_TYPE_VLAN:
2754                 retval = sizeof(struct rte_flow_item_vlan);
2755                 break;
2756         case RTE_FLOW_ITEM_TYPE_IPV4:
2757                 retval = sizeof(struct rte_flow_item_ipv4);
2758                 break;
2759         case RTE_FLOW_ITEM_TYPE_IPV6:
2760                 retval = sizeof(struct rte_flow_item_ipv6);
2761                 break;
2762         case RTE_FLOW_ITEM_TYPE_UDP:
2763                 retval = sizeof(struct rte_flow_item_udp);
2764                 break;
2765         case RTE_FLOW_ITEM_TYPE_TCP:
2766                 retval = sizeof(struct rte_flow_item_tcp);
2767                 break;
2768         case RTE_FLOW_ITEM_TYPE_VXLAN:
2769                 retval = sizeof(struct rte_flow_item_vxlan);
2770                 break;
2771         case RTE_FLOW_ITEM_TYPE_GRE:
2772                 retval = sizeof(struct rte_flow_item_gre);
2773                 break;
2774         case RTE_FLOW_ITEM_TYPE_NVGRE:
2775                 retval = sizeof(struct rte_flow_item_nvgre);
2776                 break;
2777         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2778                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2779                 break;
2780         case RTE_FLOW_ITEM_TYPE_MPLS:
2781                 retval = sizeof(struct rte_flow_item_mpls);
2782                 break;
2783         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2784         default:
2785                 retval = 0;
2786                 break;
2787         }
2788         return retval;
2789 }
2790
2791 #define MLX5_ENCAP_IPV4_VERSION         0x40
2792 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2793 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2794 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2795 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2796 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2797 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2798
2799 /**
2800  * Convert the encap action data from list of rte_flow_item to raw buffer
2801  *
2802  * @param[in] items
2803  *   Pointer to rte_flow_item objects list.
2804  * @param[out] buf
2805  *   Pointer to the output buffer.
2806  * @param[out] size
2807  *   Pointer to the output buffer size.
2808  * @param[out] error
2809  *   Pointer to the error structure.
2810  *
2811  * @return
2812  *   0 on success, a negative errno value otherwise and rte_errno is set.
2813  */
2814 static int
2815 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2816                            size_t *size, struct rte_flow_error *error)
2817 {
2818         struct rte_ether_hdr *eth = NULL;
2819         struct rte_vlan_hdr *vlan = NULL;
2820         struct rte_ipv4_hdr *ipv4 = NULL;
2821         struct rte_ipv6_hdr *ipv6 = NULL;
2822         struct rte_udp_hdr *udp = NULL;
2823         struct rte_vxlan_hdr *vxlan = NULL;
2824         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2825         struct rte_gre_hdr *gre = NULL;
2826         size_t len;
2827         size_t temp_size = 0;
2828
2829         if (!items)
2830                 return rte_flow_error_set(error, EINVAL,
2831                                           RTE_FLOW_ERROR_TYPE_ACTION,
2832                                           NULL, "invalid empty data");
2833         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2834                 len = flow_dv_get_item_len(items->type);
2835                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2836                         return rte_flow_error_set(error, EINVAL,
2837                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2838                                                   (void *)items->type,
2839                                                   "items total size is too big"
2840                                                   " for encap action");
2841                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2842                 switch (items->type) {
2843                 case RTE_FLOW_ITEM_TYPE_ETH:
2844                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2845                         break;
2846                 case RTE_FLOW_ITEM_TYPE_VLAN:
2847                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2848                         if (!eth)
2849                                 return rte_flow_error_set(error, EINVAL,
2850                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2851                                                 (void *)items->type,
2852                                                 "eth header not found");
2853                         if (!eth->ether_type)
2854                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2855                         break;
2856                 case RTE_FLOW_ITEM_TYPE_IPV4:
2857                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2858                         if (!vlan && !eth)
2859                                 return rte_flow_error_set(error, EINVAL,
2860                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2861                                                 (void *)items->type,
2862                                                 "neither eth nor vlan"
2863                                                 " header found");
2864                         if (vlan && !vlan->eth_proto)
2865                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2866                         else if (eth && !eth->ether_type)
2867                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2868                         if (!ipv4->version_ihl)
2869                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2870                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2871                         if (!ipv4->time_to_live)
2872                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2873                         break;
2874                 case RTE_FLOW_ITEM_TYPE_IPV6:
2875                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2876                         if (!vlan && !eth)
2877                                 return rte_flow_error_set(error, EINVAL,
2878                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2879                                                 (void *)items->type,
2880                                                 "neither eth nor vlan"
2881                                                 " header found");
2882                         if (vlan && !vlan->eth_proto)
2883                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2884                         else if (eth && !eth->ether_type)
2885                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2886                         if (!ipv6->vtc_flow)
2887                                 ipv6->vtc_flow =
2888                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2889                         if (!ipv6->hop_limits)
2890                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2891                         break;
2892                 case RTE_FLOW_ITEM_TYPE_UDP:
2893                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2894                         if (!ipv4 && !ipv6)
2895                                 return rte_flow_error_set(error, EINVAL,
2896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2897                                                 (void *)items->type,
2898                                                 "ip header not found");
2899                         if (ipv4 && !ipv4->next_proto_id)
2900                                 ipv4->next_proto_id = IPPROTO_UDP;
2901                         else if (ipv6 && !ipv6->proto)
2902                                 ipv6->proto = IPPROTO_UDP;
2903                         break;
2904                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2905                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2906                         if (!udp)
2907                                 return rte_flow_error_set(error, EINVAL,
2908                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2909                                                 (void *)items->type,
2910                                                 "udp header not found");
2911                         if (!udp->dst_port)
2912                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2913                         if (!vxlan->vx_flags)
2914                                 vxlan->vx_flags =
2915                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2916                         break;
2917                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2918                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2919                         if (!udp)
2920                                 return rte_flow_error_set(error, EINVAL,
2921                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2922                                                 (void *)items->type,
2923                                                 "udp header not found");
2924                         if (!vxlan_gpe->proto)
2925                                 return rte_flow_error_set(error, EINVAL,
2926                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2927                                                 (void *)items->type,
2928                                                 "next protocol not found");
2929                         if (!udp->dst_port)
2930                                 udp->dst_port =
2931                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2932                         if (!vxlan_gpe->vx_flags)
2933                                 vxlan_gpe->vx_flags =
2934                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2935                         break;
2936                 case RTE_FLOW_ITEM_TYPE_GRE:
2937                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2938                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2939                         if (!gre->proto)
2940                                 return rte_flow_error_set(error, EINVAL,
2941                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2942                                                 (void *)items->type,
2943                                                 "next protocol not found");
2944                         if (!ipv4 && !ipv6)
2945                                 return rte_flow_error_set(error, EINVAL,
2946                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2947                                                 (void *)items->type,
2948                                                 "ip header not found");
2949                         if (ipv4 && !ipv4->next_proto_id)
2950                                 ipv4->next_proto_id = IPPROTO_GRE;
2951                         else if (ipv6 && !ipv6->proto)
2952                                 ipv6->proto = IPPROTO_GRE;
2953                         break;
2954                 case RTE_FLOW_ITEM_TYPE_VOID:
2955                         break;
2956                 default:
2957                         return rte_flow_error_set(error, EINVAL,
2958                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2959                                                   (void *)items->type,
2960                                                   "unsupported item type");
2961                         break;
2962                 }
2963                 temp_size += len;
2964         }
2965         *size = temp_size;
2966         return 0;
2967 }
2968
2969 static int
2970 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2971 {
2972         struct rte_ether_hdr *eth = NULL;
2973         struct rte_vlan_hdr *vlan = NULL;
2974         struct rte_ipv6_hdr *ipv6 = NULL;
2975         struct rte_udp_hdr *udp = NULL;
2976         char *next_hdr;
2977         uint16_t proto;
2978
2979         eth = (struct rte_ether_hdr *)data;
2980         next_hdr = (char *)(eth + 1);
2981         proto = RTE_BE16(eth->ether_type);
2982
2983         /* VLAN skipping */
2984         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2985                 vlan = (struct rte_vlan_hdr *)next_hdr;
2986                 proto = RTE_BE16(vlan->eth_proto);
2987                 next_hdr += sizeof(struct rte_vlan_hdr);
2988         }
2989
2990         /* HW calculates IPv4 csum. no need to proceed */
2991         if (proto == RTE_ETHER_TYPE_IPV4)
2992                 return 0;
2993
2994         /* non IPv4/IPv6 header. not supported */
2995         if (proto != RTE_ETHER_TYPE_IPV6) {
2996                 return rte_flow_error_set(error, ENOTSUP,
2997                                           RTE_FLOW_ERROR_TYPE_ACTION,
2998                                           NULL, "Cannot offload non IPv4/IPv6");
2999         }
3000
3001         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3002
3003         /* ignore non UDP */
3004         if (ipv6->proto != IPPROTO_UDP)
3005                 return 0;
3006
3007         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3008         udp->dgram_cksum = 0;
3009
3010         return 0;
3011 }
3012
3013 /**
3014  * Convert L2 encap action to DV specification.
3015  *
3016  * @param[in] dev
3017  *   Pointer to rte_eth_dev structure.
3018  * @param[in] action
3019  *   Pointer to action structure.
3020  * @param[in, out] dev_flow
3021  *   Pointer to the mlx5_flow.
3022  * @param[in] transfer
3023  *   Mark if the flow is E-Switch flow.
3024  * @param[out] error
3025  *   Pointer to the error structure.
3026  *
3027  * @return
3028  *   0 on success, a negative errno value otherwise and rte_errno is set.
3029  */
3030 static int
3031 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3032                                const struct rte_flow_action *action,
3033                                struct mlx5_flow *dev_flow,
3034                                uint8_t transfer,
3035                                struct rte_flow_error *error)
3036 {
3037         const struct rte_flow_item *encap_data;
3038         const struct rte_flow_action_raw_encap *raw_encap_data;
3039         struct mlx5_flow_dv_encap_decap_resource res = {
3040                 .reformat_type =
3041                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3042                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3043                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3044         };
3045
3046         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3047                 raw_encap_data =
3048                         (const struct rte_flow_action_raw_encap *)action->conf;
3049                 res.size = raw_encap_data->size;
3050                 memcpy(res.buf, raw_encap_data->data, res.size);
3051         } else {
3052                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3053                         encap_data =
3054                                 ((const struct rte_flow_action_vxlan_encap *)
3055                                                 action->conf)->definition;
3056                 else
3057                         encap_data =
3058                                 ((const struct rte_flow_action_nvgre_encap *)
3059                                                 action->conf)->definition;
3060                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3061                                                &res.size, error))
3062                         return -rte_errno;
3063         }
3064         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3065                 return -rte_errno;
3066         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3067                 return rte_flow_error_set(error, EINVAL,
3068                                           RTE_FLOW_ERROR_TYPE_ACTION,
3069                                           NULL, "can't create L2 encap action");
3070         return 0;
3071 }
3072
3073 /**
3074  * Convert L2 decap action to DV specification.
3075  *
3076  * @param[in] dev
3077  *   Pointer to rte_eth_dev structure.
3078  * @param[in, out] dev_flow
3079  *   Pointer to the mlx5_flow.
3080  * @param[in] transfer
3081  *   Mark if the flow is E-Switch flow.
3082  * @param[out] error
3083  *   Pointer to the error structure.
3084  *
3085  * @return
3086  *   0 on success, a negative errno value otherwise and rte_errno is set.
3087  */
3088 static int
3089 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3090                                struct mlx5_flow *dev_flow,
3091                                uint8_t transfer,
3092                                struct rte_flow_error *error)
3093 {
3094         struct mlx5_flow_dv_encap_decap_resource res = {
3095                 .size = 0,
3096                 .reformat_type =
3097                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3098                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3099                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3100         };
3101
3102         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3103                 return rte_flow_error_set(error, EINVAL,
3104                                           RTE_FLOW_ERROR_TYPE_ACTION,
3105                                           NULL, "can't create L2 decap action");
3106         return 0;
3107 }
3108
3109 /**
3110  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3111  *
3112  * @param[in] dev
3113  *   Pointer to rte_eth_dev structure.
3114  * @param[in] action
3115  *   Pointer to action structure.
3116  * @param[in, out] dev_flow
3117  *   Pointer to the mlx5_flow.
3118  * @param[in] attr
3119  *   Pointer to the flow attributes.
3120  * @param[out] error
3121  *   Pointer to the error structure.
3122  *
3123  * @return
3124  *   0 on success, a negative errno value otherwise and rte_errno is set.
3125  */
3126 static int
3127 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3128                                 const struct rte_flow_action *action,
3129                                 struct mlx5_flow *dev_flow,
3130                                 const struct rte_flow_attr *attr,
3131                                 struct rte_flow_error *error)
3132 {
3133         const struct rte_flow_action_raw_encap *encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res;
3135
3136         memset(&res, 0, sizeof(res));
3137         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3138         res.size = encap_data->size;
3139         memcpy(res.buf, encap_data->data, res.size);
3140         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3141                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3142                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3143         if (attr->transfer)
3144                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3145         else
3146                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3147                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3148         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3149                 return rte_flow_error_set(error, EINVAL,
3150                                           RTE_FLOW_ERROR_TYPE_ACTION,
3151                                           NULL, "can't create encap action");
3152         return 0;
3153 }
3154
3155 /**
3156  * Create action push VLAN.
3157  *
3158  * @param[in] dev
3159  *   Pointer to rte_eth_dev structure.
3160  * @param[in] attr
3161  *   Pointer to the flow attributes.
3162  * @param[in] vlan
3163  *   Pointer to the vlan to push to the Ethernet header.
3164  * @param[in, out] dev_flow
3165  *   Pointer to the mlx5_flow.
3166  * @param[out] error
3167  *   Pointer to the error structure.
3168  *
3169  * @return
3170  *   0 on success, a negative errno value otherwise and rte_errno is set.
3171  */
3172 static int
3173 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3174                                 const struct rte_flow_attr *attr,
3175                                 const struct rte_vlan_hdr *vlan,
3176                                 struct mlx5_flow *dev_flow,
3177                                 struct rte_flow_error *error)
3178 {
3179         struct mlx5_flow_dv_push_vlan_action_resource res;
3180
3181         memset(&res, 0, sizeof(res));
3182         res.vlan_tag =
3183                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3184                                  vlan->vlan_tci);
3185         if (attr->transfer)
3186                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3187         else
3188                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3189                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3190         return flow_dv_push_vlan_action_resource_register
3191                                             (dev, &res, dev_flow, error);
3192 }
3193
3194 /**
3195  * Validate the modify-header actions.
3196  *
3197  * @param[in] action_flags
3198  *   Holds the actions detected until now.
3199  * @param[in] action
3200  *   Pointer to the modify action.
3201  * @param[out] error
3202  *   Pointer to error structure.
3203  *
3204  * @return
3205  *   0 on success, a negative errno value otherwise and rte_errno is set.
3206  */
3207 static int
3208 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3209                                    const struct rte_flow_action *action,
3210                                    struct rte_flow_error *error)
3211 {
3212         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3213                 return rte_flow_error_set(error, EINVAL,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3215                                           NULL, "action configuration not set");
3216         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3217                 return rte_flow_error_set(error, EINVAL,
3218                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3219                                           "can't have encap action before"
3220                                           " modify action");
3221         return 0;
3222 }
3223
3224 /**
3225  * Validate the modify-header MAC address actions.
3226  *
3227  * @param[in] action_flags
3228  *   Holds the actions detected until now.
3229  * @param[in] action
3230  *   Pointer to the modify action.
3231  * @param[in] item_flags
3232  *   Holds the items detected.
3233  * @param[out] error
3234  *   Pointer to error structure.
3235  *
3236  * @return
3237  *   0 on success, a negative errno value otherwise and rte_errno is set.
3238  */
3239 static int
3240 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3241                                    const struct rte_flow_action *action,
3242                                    const uint64_t item_flags,
3243                                    struct rte_flow_error *error)
3244 {
3245         int ret = 0;
3246
3247         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3248         if (!ret) {
3249                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3250                         return rte_flow_error_set(error, EINVAL,
3251                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3252                                                   NULL,
3253                                                   "no L2 item in pattern");
3254         }
3255         return ret;
3256 }
3257
3258 /**
3259  * Validate the modify-header IPv4 address actions.
3260  *
3261  * @param[in] action_flags
3262  *   Holds the actions detected until now.
3263  * @param[in] action
3264  *   Pointer to the modify action.
3265  * @param[in] item_flags
3266  *   Holds the items detected.
3267  * @param[out] error
3268  *   Pointer to error structure.
3269  *
3270  * @return
3271  *   0 on success, a negative errno value otherwise and rte_errno is set.
3272  */
3273 static int
3274 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3275                                     const struct rte_flow_action *action,
3276                                     const uint64_t item_flags,
3277                                     struct rte_flow_error *error)
3278 {
3279         int ret = 0;
3280         uint64_t layer;
3281
3282         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3283         if (!ret) {
3284                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3285                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3286                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3287                 if (!(item_flags & layer))
3288                         return rte_flow_error_set(error, EINVAL,
3289                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3290                                                   NULL,
3291                                                   "no ipv4 item in pattern");
3292         }
3293         return ret;
3294 }
3295
3296 /**
3297  * Validate the modify-header IPv6 address actions.
3298  *
3299  * @param[in] action_flags
3300  *   Holds the actions detected until now.
3301  * @param[in] action
3302  *   Pointer to the modify action.
3303  * @param[in] item_flags
3304  *   Holds the items detected.
3305  * @param[out] error
3306  *   Pointer to error structure.
3307  *
3308  * @return
3309  *   0 on success, a negative errno value otherwise and rte_errno is set.
3310  */
3311 static int
3312 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3313                                     const struct rte_flow_action *action,
3314                                     const uint64_t item_flags,
3315                                     struct rte_flow_error *error)
3316 {
3317         int ret = 0;
3318         uint64_t layer;
3319
3320         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3321         if (!ret) {
3322                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3323                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3324                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3325                 if (!(item_flags & layer))
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "no ipv6 item in pattern");
3330         }
3331         return ret;
3332 }
3333
3334 /**
3335  * Validate the modify-header TP actions.
3336  *
3337  * @param[in] action_flags
3338  *   Holds the actions detected until now.
3339  * @param[in] action
3340  *   Pointer to the modify action.
3341  * @param[in] item_flags
3342  *   Holds the items detected.
3343  * @param[out] error
3344  *   Pointer to error structure.
3345  *
3346  * @return
3347  *   0 on success, a negative errno value otherwise and rte_errno is set.
3348  */
3349 static int
3350 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3351                                   const struct rte_flow_action *action,
3352                                   const uint64_t item_flags,
3353                                   struct rte_flow_error *error)
3354 {
3355         int ret = 0;
3356         uint64_t layer;
3357
3358         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3359         if (!ret) {
3360                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3361                                  MLX5_FLOW_LAYER_INNER_L4 :
3362                                  MLX5_FLOW_LAYER_OUTER_L4;
3363                 if (!(item_flags & layer))
3364                         return rte_flow_error_set(error, EINVAL,
3365                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3366                                                   NULL, "no transport layer "
3367                                                   "in pattern");
3368         }
3369         return ret;
3370 }
3371
3372 /**
3373  * Validate the modify-header actions of increment/decrement
3374  * TCP Sequence-number.
3375  *
3376  * @param[in] action_flags
3377  *   Holds the actions detected until now.
3378  * @param[in] action
3379  *   Pointer to the modify action.
3380  * @param[in] item_flags
3381  *   Holds the items detected.
3382  * @param[out] error
3383  *   Pointer to error structure.
3384  *
3385  * @return
3386  *   0 on success, a negative errno value otherwise and rte_errno is set.
3387  */
3388 static int
3389 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3390                                        const struct rte_flow_action *action,
3391                                        const uint64_t item_flags,
3392                                        struct rte_flow_error *error)
3393 {
3394         int ret = 0;
3395         uint64_t layer;
3396
3397         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3398         if (!ret) {
3399                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3400                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3401                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3402                 if (!(item_flags & layer))
3403                         return rte_flow_error_set(error, EINVAL,
3404                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3405                                                   NULL, "no TCP item in"
3406                                                   " pattern");
3407                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3408                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3409                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3410                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3411                         return rte_flow_error_set(error, EINVAL,
3412                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3413                                                   NULL,
3414                                                   "cannot decrease and increase"
3415                                                   " TCP sequence number"
3416                                                   " at the same time");
3417         }
3418         return ret;
3419 }
3420
3421 /**
3422  * Validate the modify-header actions of increment/decrement
3423  * TCP Acknowledgment number.
3424  *
3425  * @param[in] action_flags
3426  *   Holds the actions detected until now.
3427  * @param[in] action
3428  *   Pointer to the modify action.
3429  * @param[in] item_flags
3430  *   Holds the items detected.
3431  * @param[out] error
3432  *   Pointer to error structure.
3433  *
3434  * @return
3435  *   0 on success, a negative errno value otherwise and rte_errno is set.
3436  */
3437 static int
3438 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3439                                        const struct rte_flow_action *action,
3440                                        const uint64_t item_flags,
3441                                        struct rte_flow_error *error)
3442 {
3443         int ret = 0;
3444         uint64_t layer;
3445
3446         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3447         if (!ret) {
3448                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3449                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3450                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3451                 if (!(item_flags & layer))
3452                         return rte_flow_error_set(error, EINVAL,
3453                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3454                                                   NULL, "no TCP item in"
3455                                                   " pattern");
3456                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3457                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3458                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3459                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3460                         return rte_flow_error_set(error, EINVAL,
3461                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3462                                                   NULL,
3463                                                   "cannot decrease and increase"
3464                                                   " TCP acknowledgment number"
3465                                                   " at the same time");
3466         }
3467         return ret;
3468 }
3469
3470 /**
3471  * Validate the modify-header TTL actions.
3472  *
3473  * @param[in] action_flags
3474  *   Holds the actions detected until now.
3475  * @param[in] action
3476  *   Pointer to the modify action.
3477  * @param[in] item_flags
3478  *   Holds the items detected.
3479  * @param[out] error
3480  *   Pointer to error structure.
3481  *
3482  * @return
3483  *   0 on success, a negative errno value otherwise and rte_errno is set.
3484  */
3485 static int
3486 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3487                                    const struct rte_flow_action *action,
3488                                    const uint64_t item_flags,
3489                                    struct rte_flow_error *error)
3490 {
3491         int ret = 0;
3492         uint64_t layer;
3493
3494         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3495         if (!ret) {
3496                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3497                                  MLX5_FLOW_LAYER_INNER_L3 :
3498                                  MLX5_FLOW_LAYER_OUTER_L3;
3499                 if (!(item_flags & layer))
3500                         return rte_flow_error_set(error, EINVAL,
3501                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3502                                                   NULL,
3503                                                   "no IP protocol in pattern");
3504         }
3505         return ret;
3506 }
3507
3508 /**
3509  * Validate jump action.
3510  *
3511  * @param[in] action
3512  *   Pointer to the jump action.
3513  * @param[in] action_flags
3514  *   Holds the actions detected until now.
3515  * @param[in] attributes
3516  *   Pointer to flow attributes
3517  * @param[in] external
3518  *   Action belongs to flow rule created by request external to PMD.
3519  * @param[out] error
3520  *   Pointer to error structure.
3521  *
3522  * @return
3523  *   0 on success, a negative errno value otherwise and rte_errno is set.
3524  */
3525 static int
3526 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3527                              uint64_t action_flags,
3528                              const struct rte_flow_attr *attributes,
3529                              bool external, struct rte_flow_error *error)
3530 {
3531         uint32_t target_group, table;
3532         int ret = 0;
3533
3534         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3535                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3536                 return rte_flow_error_set(error, EINVAL,
3537                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3538                                           "can't have 2 fate actions in"
3539                                           " same flow");
3540         if (action_flags & MLX5_FLOW_ACTION_METER)
3541                 return rte_flow_error_set(error, ENOTSUP,
3542                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3543                                           "jump with meter not support");
3544         if (!action->conf)
3545                 return rte_flow_error_set(error, EINVAL,
3546                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3547                                           NULL, "action configuration not set");
3548         target_group =
3549                 ((const struct rte_flow_action_jump *)action->conf)->group;
3550         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3551                                        true, &table, error);
3552         if (ret)
3553                 return ret;
3554         if (attributes->group == target_group)
3555                 return rte_flow_error_set(error, EINVAL,
3556                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557                                           "target group must be other than"
3558                                           " the current flow group");
3559         return 0;
3560 }
3561
3562 /*
3563  * Validate the port_id action.
3564  *
3565  * @param[in] dev
3566  *   Pointer to rte_eth_dev structure.
3567  * @param[in] action_flags
3568  *   Bit-fields that holds the actions detected until now.
3569  * @param[in] action
3570  *   Port_id RTE action structure.
3571  * @param[in] attr
3572  *   Attributes of flow that includes this action.
3573  * @param[out] error
3574  *   Pointer to error structure.
3575  *
3576  * @return
3577  *   0 on success, a negative errno value otherwise and rte_errno is set.
3578  */
3579 static int
3580 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3581                                 uint64_t action_flags,
3582                                 const struct rte_flow_action *action,
3583                                 const struct rte_flow_attr *attr,
3584                                 struct rte_flow_error *error)
3585 {
3586         const struct rte_flow_action_port_id *port_id;
3587         struct mlx5_priv *act_priv;
3588         struct mlx5_priv *dev_priv;
3589         uint16_t port;
3590
3591         if (!attr->transfer)
3592                 return rte_flow_error_set(error, ENOTSUP,
3593                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3594                                           NULL,
3595                                           "port id action is valid in transfer"
3596                                           " mode only");
3597         if (!action || !action->conf)
3598                 return rte_flow_error_set(error, ENOTSUP,
3599                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3600                                           NULL,
3601                                           "port id action parameters must be"
3602                                           " specified");
3603         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3604                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3605                 return rte_flow_error_set(error, EINVAL,
3606                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3607                                           "can have only one fate actions in"
3608                                           " a flow");
3609         dev_priv = mlx5_dev_to_eswitch_info(dev);
3610         if (!dev_priv)
3611                 return rte_flow_error_set(error, rte_errno,
3612                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3613                                           NULL,
3614                                           "failed to obtain E-Switch info");
3615         port_id = action->conf;
3616         port = port_id->original ? dev->data->port_id : port_id->id;
3617         act_priv = mlx5_port_to_eswitch_info(port, false);
3618         if (!act_priv)
3619                 return rte_flow_error_set
3620                                 (error, rte_errno,
3621                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3622                                  "failed to obtain E-Switch port id for port");
3623         if (act_priv->domain_id != dev_priv->domain_id)
3624                 return rte_flow_error_set
3625                                 (error, EINVAL,
3626                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3627                                  "port does not belong to"
3628                                  " E-Switch being configured");
3629         return 0;
3630 }
3631
3632 /**
3633  * Get the maximum number of modify header actions.
3634  *
3635  * @param dev
3636  *   Pointer to rte_eth_dev structure.
3637  * @param flags
3638  *   Flags bits to check if root level.
3639  *
3640  * @return
3641  *   Max number of modify header actions device can support.
3642  */
3643 static unsigned int
3644 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3645 {
3646         /*
3647          * There's no way to directly query the max cap. Although it has to be
3648          * acquried by iterative trial, it is a safe assumption that more
3649          * actions are supported by FW if extensive metadata register is
3650          * supported. (Only in the root table)
3651          */
3652         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3653                 return MLX5_MAX_MODIFY_NUM;
3654         else
3655                 return mlx5_flow_ext_mreg_supported(dev) ?
3656                                         MLX5_ROOT_TBL_MODIFY_NUM :
3657                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3658 }
3659
3660 /**
3661  * Validate the meter action.
3662  *
3663  * @param[in] dev
3664  *   Pointer to rte_eth_dev structure.
3665  * @param[in] action_flags
3666  *   Bit-fields that holds the actions detected until now.
3667  * @param[in] action
3668  *   Pointer to the meter action.
3669  * @param[in] attr
3670  *   Attributes of flow that includes this action.
3671  * @param[out] error
3672  *   Pointer to error structure.
3673  *
3674  * @return
3675  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3676  */
3677 static int
3678 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3679                                 uint64_t action_flags,
3680                                 const struct rte_flow_action *action,
3681                                 const struct rte_flow_attr *attr,
3682                                 struct rte_flow_error *error)
3683 {
3684         struct mlx5_priv *priv = dev->data->dev_private;
3685         const struct rte_flow_action_meter *am = action->conf;
3686         struct mlx5_flow_meter *fm;
3687
3688         if (!am)
3689                 return rte_flow_error_set(error, EINVAL,
3690                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3691                                           "meter action conf is NULL");
3692
3693         if (action_flags & MLX5_FLOW_ACTION_METER)
3694                 return rte_flow_error_set(error, ENOTSUP,
3695                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3696                                           "meter chaining not support");
3697         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3698                 return rte_flow_error_set(error, ENOTSUP,
3699                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3700                                           "meter with jump not support");
3701         if (!priv->mtr_en)
3702                 return rte_flow_error_set(error, ENOTSUP,
3703                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3704                                           NULL,
3705                                           "meter action not supported");
3706         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3707         if (!fm)
3708                 return rte_flow_error_set(error, EINVAL,
3709                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3710                                           "Meter not found");
3711         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3712               (!fm->ingress && !attr->ingress && attr->egress) ||
3713               (!fm->egress && !attr->egress && attr->ingress))))
3714                 return rte_flow_error_set(error, EINVAL,
3715                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3716                                           "Flow attributes are either invalid "
3717                                           "or have a conflict with current "
3718                                           "meter attributes");
3719         return 0;
3720 }
3721
3722 /**
3723  * Validate the modify-header IPv4 DSCP actions.
3724  *
3725  * @param[in] action_flags
3726  *   Holds the actions detected until now.
3727  * @param[in] action
3728  *   Pointer to the modify action.
3729  * @param[in] item_flags
3730  *   Holds the items detected.
3731  * @param[out] error
3732  *   Pointer to error structure.
3733  *
3734  * @return
3735  *   0 on success, a negative errno value otherwise and rte_errno is set.
3736  */
3737 static int
3738 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3739                                          const struct rte_flow_action *action,
3740                                          const uint64_t item_flags,
3741                                          struct rte_flow_error *error)
3742 {
3743         int ret = 0;
3744
3745         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3746         if (!ret) {
3747                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3748                         return rte_flow_error_set(error, EINVAL,
3749                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3750                                                   NULL,
3751                                                   "no ipv4 item in pattern");
3752         }
3753         return ret;
3754 }
3755
3756 /**
3757  * Validate the modify-header IPv6 DSCP actions.
3758  *
3759  * @param[in] action_flags
3760  *   Holds the actions detected until now.
3761  * @param[in] action
3762  *   Pointer to the modify action.
3763  * @param[in] item_flags
3764  *   Holds the items detected.
3765  * @param[out] error
3766  *   Pointer to error structure.
3767  *
3768  * @return
3769  *   0 on success, a negative errno value otherwise and rte_errno is set.
3770  */
3771 static int
3772 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3773                                          const struct rte_flow_action *action,
3774                                          const uint64_t item_flags,
3775                                          struct rte_flow_error *error)
3776 {
3777         int ret = 0;
3778
3779         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3780         if (!ret) {
3781                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3782                         return rte_flow_error_set(error, EINVAL,
3783                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3784                                                   NULL,
3785                                                   "no ipv6 item in pattern");
3786         }
3787         return ret;
3788 }
3789
3790 /**
3791  * Find existing modify-header resource or create and register a new one.
3792  *
3793  * @param dev[in, out]
3794  *   Pointer to rte_eth_dev structure.
3795  * @param[in, out] resource
3796  *   Pointer to modify-header resource.
3797  * @parm[in, out] dev_flow
3798  *   Pointer to the dev_flow.
3799  * @param[out] error
3800  *   pointer to error structure.
3801  *
3802  * @return
3803  *   0 on success otherwise -errno and errno is set.
3804  */
3805 static int
3806 flow_dv_modify_hdr_resource_register
3807                         (struct rte_eth_dev *dev,
3808                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3809                          struct mlx5_flow *dev_flow,
3810                          struct rte_flow_error *error)
3811 {
3812         struct mlx5_priv *priv = dev->data->dev_private;
3813         struct mlx5_ibv_shared *sh = priv->sh;
3814         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3815         struct mlx5dv_dr_domain *ns;
3816         uint32_t actions_len;
3817
3818         resource->flags = dev_flow->dv.group ? 0 :
3819                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3820         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3821                                     resource->flags))
3822                 return rte_flow_error_set(error, EOVERFLOW,
3823                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3824                                           "too many modify header items");
3825         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3826                 ns = sh->fdb_domain;
3827         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3828                 ns = sh->tx_domain;
3829         else
3830                 ns = sh->rx_domain;
3831         /* Lookup a matching resource from cache. */
3832         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3833         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3834                 if (resource->ft_type == cache_resource->ft_type &&
3835                     resource->actions_num == cache_resource->actions_num &&
3836                     resource->flags == cache_resource->flags &&
3837                     !memcmp((const void *)resource->actions,
3838                             (const void *)cache_resource->actions,
3839                             actions_len)) {
3840                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3841                                 (void *)cache_resource,
3842                                 rte_atomic32_read(&cache_resource->refcnt));
3843                         rte_atomic32_inc(&cache_resource->refcnt);
3844                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3845                         return 0;
3846                 }
3847         }
3848         /* Register new modify-header resource. */
3849         cache_resource = rte_calloc(__func__, 1,
3850                                     sizeof(*cache_resource) + actions_len, 0);
3851         if (!cache_resource)
3852                 return rte_flow_error_set(error, ENOMEM,
3853                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3854                                           "cannot allocate resource memory");
3855         *cache_resource = *resource;
3856         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3857         cache_resource->verbs_action =
3858                 mlx5_glue->dv_create_flow_action_modify_header
3859                                         (sh->ctx, cache_resource->ft_type, ns,
3860                                          cache_resource->flags, actions_len,
3861                                          (uint64_t *)cache_resource->actions);
3862         if (!cache_resource->verbs_action) {
3863                 rte_free(cache_resource);
3864                 return rte_flow_error_set(error, ENOMEM,
3865                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3866                                           NULL, "cannot create action");
3867         }
3868         rte_atomic32_init(&cache_resource->refcnt);
3869         rte_atomic32_inc(&cache_resource->refcnt);
3870         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3871         dev_flow->handle->dvh.modify_hdr = cache_resource;
3872         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3873                 (void *)cache_resource,
3874                 rte_atomic32_read(&cache_resource->refcnt));
3875         return 0;
3876 }
3877
3878 /**
3879  * Get DV flow counter by index.
3880  *
3881  * @param[in] dev
3882  *   Pointer to the Ethernet device structure.
3883  * @param[in] idx
3884  *   mlx5 flow counter index in the container.
3885  * @param[out] ppool
3886  *   mlx5 flow counter pool in the container,
3887  *
3888  * @return
3889  *   Pointer to the counter, NULL otherwise.
3890  */
3891 static struct mlx5_flow_counter *
3892 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3893                            uint32_t idx,
3894                            struct mlx5_flow_counter_pool **ppool)
3895 {
3896         struct mlx5_priv *priv = dev->data->dev_private;
3897         struct mlx5_pools_container *cont;
3898         struct mlx5_flow_counter_pool *pool;
3899         uint32_t batch = 0;
3900
3901         idx--;
3902         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3903                 idx -= MLX5_CNT_BATCH_OFFSET;
3904                 batch = 1;
3905         }
3906         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3907         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3908         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3909         MLX5_ASSERT(pool);
3910         if (ppool)
3911                 *ppool = pool;
3912         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3913 }
3914
3915 /**
3916  * Get a pool by devx counter ID.
3917  *
3918  * @param[in] cont
3919  *   Pointer to the counter container.
3920  * @param[in] id
3921  *   The counter devx ID.
3922  *
3923  * @return
3924  *   The counter pool pointer if exists, NULL otherwise,
3925  */
3926 static struct mlx5_flow_counter_pool *
3927 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3928 {
3929         uint32_t i;
3930         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3931
3932         for (i = 0; i < n_valid; i++) {
3933                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3934                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3935                            MLX5_COUNTERS_PER_POOL;
3936
3937                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3938                         /*
3939                          * Move the pool to the head, as counter allocate
3940                          * always gets the first pool in the container.
3941                          */
3942                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3943                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3944                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3945                         }
3946                         return pool;
3947                 }
3948         }
3949         return NULL;
3950 }
3951
3952 /**
3953  * Allocate a new memory for the counter values wrapped by all the needed
3954  * management.
3955  *
3956  * @param[in] dev
3957  *   Pointer to the Ethernet device structure.
3958  * @param[in] raws_n
3959  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3960  *
3961  * @return
3962  *   The new memory management pointer on success, otherwise NULL and rte_errno
3963  *   is set.
3964  */
3965 static struct mlx5_counter_stats_mem_mng *
3966 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3967 {
3968         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3969                                         (dev->data->dev_private))->sh;
3970         struct mlx5_devx_mkey_attr mkey_attr;
3971         struct mlx5_counter_stats_mem_mng *mem_mng;
3972         volatile struct flow_counter_stats *raw_data;
3973         int size = (sizeof(struct flow_counter_stats) *
3974                         MLX5_COUNTERS_PER_POOL +
3975                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3976                         sizeof(struct mlx5_counter_stats_mem_mng);
3977         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3978         int i;
3979
3980         if (!mem) {
3981                 rte_errno = ENOMEM;
3982                 return NULL;
3983         }
3984         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3985         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3986         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3987                                                  IBV_ACCESS_LOCAL_WRITE);
3988         if (!mem_mng->umem) {
3989                 rte_errno = errno;
3990                 rte_free(mem);
3991                 return NULL;
3992         }
3993         mkey_attr.addr = (uintptr_t)mem;
3994         mkey_attr.size = size;
3995         mkey_attr.umem_id = mem_mng->umem->umem_id;
3996         mkey_attr.pd = sh->pdn;
3997         mkey_attr.log_entity_size = 0;
3998         mkey_attr.pg_access = 0;
3999         mkey_attr.klm_array = NULL;
4000         mkey_attr.klm_num = 0;
4001         mkey_attr.relaxed_ordering = 1;
4002         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4003         if (!mem_mng->dm) {
4004                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4005                 rte_errno = errno;
4006                 rte_free(mem);
4007                 return NULL;
4008         }
4009         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4010         raw_data = (volatile struct flow_counter_stats *)mem;
4011         for (i = 0; i < raws_n; ++i) {
4012                 mem_mng->raws[i].mem_mng = mem_mng;
4013                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4014         }
4015         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4016         return mem_mng;
4017 }
4018
4019 /**
4020  * Resize a counter container.
4021  *
4022  * @param[in] dev
4023  *   Pointer to the Ethernet device structure.
4024  * @param[in] batch
4025  *   Whether the pool is for counter that was allocated by batch command.
4026  *
4027  * @return
4028  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4029  */
4030 static struct mlx5_pools_container *
4031 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4032 {
4033         struct mlx5_priv *priv = dev->data->dev_private;
4034         struct mlx5_pools_container *cont =
4035                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4036         struct mlx5_pools_container *new_cont =
4037                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4038         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4039         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4040         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4041         int i;
4042
4043         /* Fallback mode has no background thread. Skip the check. */
4044         if (!priv->counter_fallback &&
4045             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4046                 /* The last resize still hasn't detected by the host thread. */
4047                 rte_errno = EAGAIN;
4048                 return NULL;
4049         }
4050         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4051         if (!new_cont->pools) {
4052                 rte_errno = ENOMEM;
4053                 return NULL;
4054         }
4055         if (cont->n)
4056                 memcpy(new_cont->pools, cont->pools, cont->n *
4057                        sizeof(struct mlx5_flow_counter_pool *));
4058         /*
4059          * Fallback mode query the counter directly, no background query
4060          * resources are needed.
4061          */
4062         if (!priv->counter_fallback) {
4063                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4064                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4065                 if (!mem_mng) {
4066                         rte_free(new_cont->pools);
4067                         return NULL;
4068                 }
4069                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4070                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4071                                          mem_mng->raws +
4072                                          MLX5_CNT_CONTAINER_RESIZE +
4073                                          i, next);
4074         } else {
4075                 /*
4076                  * Release the old container pools directly as no background
4077                  * thread helps that.
4078                  */
4079                 rte_free(cont->pools);
4080         }
4081         new_cont->n = resize;
4082         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4083         TAILQ_INIT(&new_cont->pool_list);
4084         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4085         new_cont->init_mem_mng = mem_mng;
4086         rte_cio_wmb();
4087          /* Flip the master container. */
4088         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4089         return new_cont;
4090 }
4091
4092 /**
4093  * Query a devx flow counter.
4094  *
4095  * @param[in] dev
4096  *   Pointer to the Ethernet device structure.
4097  * @param[in] cnt
4098  *   Index to the flow counter.
4099  * @param[out] pkts
4100  *   The statistics value of packets.
4101  * @param[out] bytes
4102  *   The statistics value of bytes.
4103  *
4104  * @return
4105  *   0 on success, otherwise a negative errno value and rte_errno is set.
4106  */
4107 static inline int
4108 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4109                      uint64_t *bytes)
4110 {
4111         struct mlx5_priv *priv = dev->data->dev_private;
4112         struct mlx5_flow_counter_pool *pool = NULL;
4113         struct mlx5_flow_counter *cnt;
4114         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4115         int offset;
4116
4117         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4118         MLX5_ASSERT(pool);
4119         if (counter < MLX5_CNT_BATCH_OFFSET) {
4120                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4121                 if (priv->counter_fallback)
4122                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4123                                         0, pkts, bytes, 0, NULL, NULL, 0);
4124         }
4125
4126         rte_spinlock_lock(&pool->sl);
4127         /*
4128          * The single counters allocation may allocate smaller ID than the
4129          * current allocated in parallel to the host reading.
4130          * In this case the new counter values must be reported as 0.
4131          */
4132         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4133                 *pkts = 0;
4134                 *bytes = 0;
4135         } else {
4136                 offset = cnt - &pool->counters_raw[0];
4137                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4138                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4139         }
4140         rte_spinlock_unlock(&pool->sl);
4141         return 0;
4142 }
4143
4144 /**
4145  * Create and initialize a new counter pool.
4146  *
4147  * @param[in] dev
4148  *   Pointer to the Ethernet device structure.
4149  * @param[out] dcs
4150  *   The devX counter handle.
4151  * @param[in] batch
4152  *   Whether the pool is for counter that was allocated by batch command.
4153  * @param[in/out] cont_cur
4154  *   Pointer to the container pointer, it will be update in pool resize.
4155  *
4156  * @return
4157  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4158  */
4159 static struct mlx5_pools_container *
4160 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4161                     uint32_t batch)
4162 {
4163         struct mlx5_priv *priv = dev->data->dev_private;
4164         struct mlx5_flow_counter_pool *pool;
4165         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4166                                                                0);
4167         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4168         uint32_t size;
4169
4170         if (cont->n == n_valid) {
4171                 cont = flow_dv_container_resize(dev, batch);
4172                 if (!cont)
4173                         return NULL;
4174         }
4175         size = sizeof(*pool);
4176         if (!batch)
4177                 size += MLX5_COUNTERS_PER_POOL *
4178                         sizeof(struct mlx5_flow_counter_ext);
4179         pool = rte_calloc(__func__, 1, size, 0);
4180         if (!pool) {
4181                 rte_errno = ENOMEM;
4182                 return NULL;
4183         }
4184         pool->min_dcs = dcs;
4185         if (!priv->counter_fallback)
4186                 pool->raw = cont->init_mem_mng->raws + n_valid %
4187                                                      MLX5_CNT_CONTAINER_RESIZE;
4188         pool->raw_hw = NULL;
4189         rte_spinlock_init(&pool->sl);
4190         /*
4191          * The generation of the new allocated counters in this pool is 0, 2 in
4192          * the pool generation makes all the counters valid for allocation.
4193          * The start and end query generation protect the counters be released
4194          * between the query and update gap period will not be reallocated
4195          * without the last query finished and stats updated to the memory.
4196          */
4197         rte_atomic64_set(&pool->start_query_gen, 0x2);
4198         /*
4199          * There's no background query thread for fallback mode, set the
4200          * end_query_gen to the maximum value since no need to wait for
4201          * statistics update.
4202          */
4203         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4204                          INT64_MAX : 0x2);
4205         TAILQ_INIT(&pool->counters);
4206         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4207         pool->index = n_valid;
4208         cont->pools[n_valid] = pool;
4209         /* Pool initialization must be updated before host thread access. */
4210         rte_cio_wmb();
4211         rte_atomic16_add(&cont->n_valid, 1);
4212         return cont;
4213 }
4214
4215 /**
4216  * Prepare a new counter and/or a new counter pool.
4217  *
4218  * @param[in] dev
4219  *   Pointer to the Ethernet device structure.
4220  * @param[out] cnt_free
4221  *   Where to put the pointer of a new counter.
4222  * @param[in] batch
4223  *   Whether the pool is for counter that was allocated by batch command.
4224  *
4225  * @return
4226  *   The counter container pointer and @p cnt_free is set on success,
4227  *   NULL otherwise and rte_errno is set.
4228  */
4229 static struct mlx5_pools_container *
4230 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4231                              struct mlx5_flow_counter **cnt_free,
4232                              uint32_t batch)
4233 {
4234         struct mlx5_priv *priv = dev->data->dev_private;
4235         struct mlx5_pools_container *cont;
4236         struct mlx5_flow_counter_pool *pool;
4237         struct mlx5_devx_obj *dcs = NULL;
4238         struct mlx5_flow_counter *cnt;
4239         uint32_t i;
4240
4241         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4242         if (!batch) {
4243                 /* bulk_bitmap must be 0 for single counter allocation. */
4244                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4245                 if (!dcs)
4246                         return NULL;
4247                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4248                 if (!pool) {
4249                         cont = flow_dv_pool_create(dev, dcs, batch);
4250                         if (!cont) {
4251                                 mlx5_devx_cmd_destroy(dcs);
4252                                 return NULL;
4253                         }
4254                         pool = TAILQ_FIRST(&cont->pool_list);
4255                 } else if (dcs->id < pool->min_dcs->id) {
4256                         rte_atomic64_set(&pool->a64_dcs,
4257                                          (int64_t)(uintptr_t)dcs);
4258                 }
4259                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4260                 cnt = &pool->counters_raw[i];
4261                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4262                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4263                 *cnt_free = cnt;
4264                 return cont;
4265         }
4266         /* bulk_bitmap is in 128 counters units. */
4267         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4268                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4269         if (!dcs) {
4270                 rte_errno = ENODATA;
4271                 return NULL;
4272         }
4273         cont = flow_dv_pool_create(dev, dcs, batch);
4274         if (!cont) {
4275                 mlx5_devx_cmd_destroy(dcs);
4276                 return NULL;
4277         }
4278         pool = TAILQ_FIRST(&cont->pool_list);
4279         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4280                 cnt = &pool->counters_raw[i];
4281                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4282         }
4283         *cnt_free = &pool->counters_raw[0];
4284         return cont;
4285 }
4286
4287 /**
4288  * Search for existed shared counter.
4289  *
4290  * @param[in] cont
4291  *   Pointer to the relevant counter pool container.
4292  * @param[in] id
4293  *   The shared counter ID to search.
4294  * @param[out] ppool
4295  *   mlx5 flow counter pool in the container,
4296  *
4297  * @return
4298  *   NULL if not existed, otherwise pointer to the shared extend counter.
4299  */
4300 static struct mlx5_flow_counter_ext *
4301 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4302                               struct mlx5_flow_counter_pool **ppool)
4303 {
4304         static struct mlx5_flow_counter_ext *cnt;
4305         struct mlx5_flow_counter_pool *pool;
4306         uint32_t i;
4307         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4308
4309         for (i = 0; i < n_valid; i++) {
4310                 pool = cont->pools[i];
4311                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4312                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4313                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4314                                 if (ppool)
4315                                         *ppool = cont->pools[i];
4316                                 return cnt;
4317                         }
4318                 }
4319         }
4320         return NULL;
4321 }
4322
4323 /**
4324  * Allocate a flow counter.
4325  *
4326  * @param[in] dev
4327  *   Pointer to the Ethernet device structure.
4328  * @param[in] shared
4329  *   Indicate if this counter is shared with other flows.
4330  * @param[in] id
4331  *   Counter identifier.
4332  * @param[in] group
4333  *   Counter flow group.
4334  *
4335  * @return
4336  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4337  */
4338 static uint32_t
4339 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4340                       uint16_t group)
4341 {
4342         struct mlx5_priv *priv = dev->data->dev_private;
4343         struct mlx5_flow_counter_pool *pool = NULL;
4344         struct mlx5_flow_counter *cnt_free = NULL;
4345         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4346         /*
4347          * Currently group 0 flow counter cannot be assigned to a flow if it is
4348          * not the first one in the batch counter allocation, so it is better
4349          * to allocate counters one by one for these flows in a separate
4350          * container.
4351          * A counter can be shared between different groups so need to take
4352          * shared counters from the single container.
4353          */
4354         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4355         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4356                                                                0);
4357         uint32_t cnt_idx;
4358
4359         if (!priv->config.devx) {
4360                 rte_errno = ENOTSUP;
4361                 return 0;
4362         }
4363         if (shared) {
4364                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4365                 if (cnt_ext) {
4366                         if (cnt_ext->ref_cnt + 1 == 0) {
4367                                 rte_errno = E2BIG;
4368                                 return 0;
4369                         }
4370                         cnt_ext->ref_cnt++;
4371                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4372                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4373                                   + 1;
4374                         return cnt_idx;
4375                 }
4376         }
4377         /* Pools which has a free counters are in the start. */
4378         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4379                 /*
4380                  * The free counter reset values must be updated between the
4381                  * counter release to the counter allocation, so, at least one
4382                  * query must be done in this time. ensure it by saving the
4383                  * query generation in the release time.
4384                  * The free list is sorted according to the generation - so if
4385                  * the first one is not updated, all the others are not
4386                  * updated too.
4387                  */
4388                 cnt_free = TAILQ_FIRST(&pool->counters);
4389                 if (cnt_free && cnt_free->query_gen <
4390                     rte_atomic64_read(&pool->end_query_gen))
4391                         break;
4392                 cnt_free = NULL;
4393         }
4394         if (!cnt_free) {
4395                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4396                 if (!cont)
4397                         return 0;
4398                 pool = TAILQ_FIRST(&cont->pool_list);
4399         }
4400         if (!batch)
4401                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4402         /* Create a DV counter action only in the first time usage. */
4403         if (!cnt_free->action) {
4404                 uint16_t offset;
4405                 struct mlx5_devx_obj *dcs;
4406
4407                 if (batch) {
4408                         offset = cnt_free - &pool->counters_raw[0];
4409                         dcs = pool->min_dcs;
4410                 } else {
4411                         offset = 0;
4412                         dcs = cnt_ext->dcs;
4413                 }
4414                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4415                                         (dcs->obj, offset);
4416                 if (!cnt_free->action) {
4417                         rte_errno = errno;
4418                         return 0;
4419                 }
4420         }
4421         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4422                                     (cnt_free - pool->counters_raw));
4423         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4424         /* Update the counter reset values. */
4425         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4426                                  &cnt_free->bytes))
4427                 return 0;
4428         if (cnt_ext) {
4429                 cnt_ext->shared = shared;
4430                 cnt_ext->ref_cnt = 1;
4431                 cnt_ext->id = id;
4432         }
4433         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4434                 /* Start the asynchronous batch query by the host thread. */
4435                 mlx5_set_query_alarm(priv->sh);
4436         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4437         if (TAILQ_EMPTY(&pool->counters)) {
4438                 /* Move the pool to the end of the container pool list. */
4439                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4440                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4441         }
4442         return cnt_idx;
4443 }
4444
4445 /**
4446  * Release a flow counter.
4447  *
4448  * @param[in] dev
4449  *   Pointer to the Ethernet device structure.
4450  * @param[in] counter
4451  *   Index to the counter handler.
4452  */
4453 static void
4454 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4455 {
4456         struct mlx5_flow_counter_pool *pool = NULL;
4457         struct mlx5_flow_counter *cnt;
4458         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4459
4460         if (!counter)
4461                 return;
4462         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4463         MLX5_ASSERT(pool);
4464         if (counter < MLX5_CNT_BATCH_OFFSET) {
4465                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4466                 if (cnt_ext && --cnt_ext->ref_cnt)
4467                         return;
4468         }
4469         /* Put the counter in the end - the last updated one. */
4470         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4471         /*
4472          * Counters released between query trigger and handler need
4473          * to wait the next round of query. Since the packets arrive
4474          * in the gap period will not be taken into account to the
4475          * old counter.
4476          */
4477         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4478 }
4479
4480 /**
4481  * Verify the @p attributes will be correctly understood by the NIC and store
4482  * them in the @p flow if everything is correct.
4483  *
4484  * @param[in] dev
4485  *   Pointer to dev struct.
4486  * @param[in] attributes
4487  *   Pointer to flow attributes
4488  * @param[in] external
4489  *   This flow rule is created by request external to PMD.
4490  * @param[out] error
4491  *   Pointer to error structure.
4492  *
4493  * @return
4494  *   - 0 on success and non root table.
4495  *   - 1 on success and root table.
4496  *   - a negative errno value otherwise and rte_errno is set.
4497  */
4498 static int
4499 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4500                             const struct rte_flow_attr *attributes,
4501                             bool external __rte_unused,
4502                             struct rte_flow_error *error)
4503 {
4504         struct mlx5_priv *priv = dev->data->dev_private;
4505         uint32_t priority_max = priv->config.flow_prio - 1;
4506         int ret = 0;
4507
4508 #ifndef HAVE_MLX5DV_DR
4509         if (attributes->group)
4510                 return rte_flow_error_set(error, ENOTSUP,
4511                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4512                                           NULL,
4513                                           "groups are not supported");
4514 #else
4515         uint32_t table = 0;
4516
4517         ret = mlx5_flow_group_to_table(attributes, external,
4518                                        attributes->group, !!priv->fdb_def_rule,
4519                                        &table, error);
4520         if (ret)
4521                 return ret;
4522         if (!table)
4523                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4524 #endif
4525         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4526             attributes->priority >= priority_max)
4527                 return rte_flow_error_set(error, ENOTSUP,
4528                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4529                                           NULL,
4530                                           "priority out of range");
4531         if (attributes->transfer) {
4532                 if (!priv->config.dv_esw_en)
4533                         return rte_flow_error_set
4534                                 (error, ENOTSUP,
4535                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4536                                  "E-Switch dr is not supported");
4537                 if (!(priv->representor || priv->master))
4538                         return rte_flow_error_set
4539                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4540                                  NULL, "E-Switch configuration can only be"
4541                                  " done by a master or a representor device");
4542                 if (attributes->egress)
4543                         return rte_flow_error_set
4544                                 (error, ENOTSUP,
4545                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4546                                  "egress is not supported");
4547         }
4548         if (!(attributes->egress ^ attributes->ingress))
4549                 return rte_flow_error_set(error, ENOTSUP,
4550                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4551                                           "must specify exactly one of "
4552                                           "ingress or egress");
4553         return ret;
4554 }
4555
4556 /**
4557  * Internal validation function. For validating both actions and items.
4558  *
4559  * @param[in] dev
4560  *   Pointer to the rte_eth_dev structure.
4561  * @param[in] attr
4562  *   Pointer to the flow attributes.
4563  * @param[in] items
4564  *   Pointer to the list of items.
4565  * @param[in] actions
4566  *   Pointer to the list of actions.
4567  * @param[in] external
4568  *   This flow rule is created by request external to PMD.
4569  * @param[in] hairpin
4570  *   Number of hairpin TX actions, 0 means classic flow.
4571  * @param[out] error
4572  *   Pointer to the error structure.
4573  *
4574  * @return
4575  *   0 on success, a negative errno value otherwise and rte_errno is set.
4576  */
4577 static int
4578 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4579                  const struct rte_flow_item items[],
4580                  const struct rte_flow_action actions[],
4581                  bool external, int hairpin, struct rte_flow_error *error)
4582 {
4583         int ret;
4584         uint64_t action_flags = 0;
4585         uint64_t item_flags = 0;
4586         uint64_t last_item = 0;
4587         uint8_t next_protocol = 0xff;
4588         uint16_t ether_type = 0;
4589         int actions_n = 0;
4590         uint8_t item_ipv6_proto = 0;
4591         const struct rte_flow_item *gre_item = NULL;
4592         const struct rte_flow_action_raw_decap *decap;
4593         const struct rte_flow_action_raw_encap *encap;
4594         const struct rte_flow_action_rss *rss;
4595         const struct rte_flow_item_tcp nic_tcp_mask = {
4596                 .hdr = {
4597                         .tcp_flags = 0xFF,
4598                         .src_port = RTE_BE16(UINT16_MAX),
4599                         .dst_port = RTE_BE16(UINT16_MAX),
4600                 }
4601         };
4602         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4603                 .hdr = {
4604                         .src_addr = RTE_BE32(0xffffffff),
4605                         .dst_addr = RTE_BE32(0xffffffff),
4606                         .type_of_service = 0xff,
4607                         .next_proto_id = 0xff,
4608                         .time_to_live = 0xff,
4609                 },
4610         };
4611         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4612                 .hdr = {
4613                         .src_addr =
4614                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4615                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4616                         .dst_addr =
4617                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4618                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4619                         .vtc_flow = RTE_BE32(0xffffffff),
4620                         .proto = 0xff,
4621                         .hop_limits = 0xff,
4622                 },
4623         };
4624         struct mlx5_priv *priv = dev->data->dev_private;
4625         struct mlx5_dev_config *dev_conf = &priv->config;
4626         uint16_t queue_index = 0xFFFF;
4627         const struct rte_flow_item_vlan *vlan_m = NULL;
4628         int16_t rw_act_num = 0;
4629         uint64_t is_root;
4630
4631         if (items == NULL)
4632                 return -1;
4633         ret = flow_dv_validate_attributes(dev, attr, external, error);
4634         if (ret < 0)
4635                 return ret;
4636         is_root = (uint64_t)ret;
4637         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4638                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4639                 int type = items->type;
4640
4641                 switch (type) {
4642                 case RTE_FLOW_ITEM_TYPE_VOID:
4643                         break;
4644                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4645                         ret = flow_dv_validate_item_port_id
4646                                         (dev, items, attr, item_flags, error);
4647                         if (ret < 0)
4648                                 return ret;
4649                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4650                         break;
4651                 case RTE_FLOW_ITEM_TYPE_ETH:
4652                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4653                                                           error);
4654                         if (ret < 0)
4655                                 return ret;
4656                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4657                                              MLX5_FLOW_LAYER_OUTER_L2;
4658                         if (items->mask != NULL && items->spec != NULL) {
4659                                 ether_type =
4660                                         ((const struct rte_flow_item_eth *)
4661                                          items->spec)->type;
4662                                 ether_type &=
4663                                         ((const struct rte_flow_item_eth *)
4664                                          items->mask)->type;
4665                                 ether_type = rte_be_to_cpu_16(ether_type);
4666                         } else {
4667                                 ether_type = 0;
4668                         }
4669                         break;
4670                 case RTE_FLOW_ITEM_TYPE_VLAN:
4671                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4672                                                            dev, error);
4673                         if (ret < 0)
4674                                 return ret;
4675                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4676                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4677                         if (items->mask != NULL && items->spec != NULL) {
4678                                 ether_type =
4679                                         ((const struct rte_flow_item_vlan *)
4680                                          items->spec)->inner_type;
4681                                 ether_type &=
4682                                         ((const struct rte_flow_item_vlan *)
4683                                          items->mask)->inner_type;
4684                                 ether_type = rte_be_to_cpu_16(ether_type);
4685                         } else {
4686                                 ether_type = 0;
4687                         }
4688                         /* Store outer VLAN mask for of_push_vlan action. */
4689                         if (!tunnel)
4690                                 vlan_m = items->mask;
4691                         break;
4692                 case RTE_FLOW_ITEM_TYPE_IPV4:
4693                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4694                                                   &item_flags, &tunnel);
4695                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4696                                                            last_item,
4697                                                            ether_type,
4698                                                            &nic_ipv4_mask,
4699                                                            error);
4700                         if (ret < 0)
4701                                 return ret;
4702                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4703                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4704                         if (items->mask != NULL &&
4705                             ((const struct rte_flow_item_ipv4 *)
4706                              items->mask)->hdr.next_proto_id) {
4707                                 next_protocol =
4708                                         ((const struct rte_flow_item_ipv4 *)
4709                                          (items->spec))->hdr.next_proto_id;
4710                                 next_protocol &=
4711                                         ((const struct rte_flow_item_ipv4 *)
4712                                          (items->mask))->hdr.next_proto_id;
4713                         } else {
4714                                 /* Reset for inner layer. */
4715                                 next_protocol = 0xff;
4716                         }
4717                         break;
4718                 case RTE_FLOW_ITEM_TYPE_IPV6:
4719                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4720                                                   &item_flags, &tunnel);
4721                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4722                                                            last_item,
4723                                                            ether_type,
4724                                                            &nic_ipv6_mask,
4725                                                            error);
4726                         if (ret < 0)
4727                                 return ret;
4728                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4729                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4730                         if (items->mask != NULL &&
4731                             ((const struct rte_flow_item_ipv6 *)
4732                              items->mask)->hdr.proto) {
4733                                 item_ipv6_proto =
4734                                         ((const struct rte_flow_item_ipv6 *)
4735                                          items->spec)->hdr.proto;
4736                                 next_protocol =
4737                                         ((const struct rte_flow_item_ipv6 *)
4738                                          items->spec)->hdr.proto;
4739                                 next_protocol &=
4740                                         ((const struct rte_flow_item_ipv6 *)
4741                                          items->mask)->hdr.proto;
4742                         } else {
4743                                 /* Reset for inner layer. */
4744                                 next_protocol = 0xff;
4745                         }
4746                         break;
4747                 case RTE_FLOW_ITEM_TYPE_TCP:
4748                         ret = mlx5_flow_validate_item_tcp
4749                                                 (items, item_flags,
4750                                                  next_protocol,
4751                                                  &nic_tcp_mask,
4752                                                  error);
4753                         if (ret < 0)
4754                                 return ret;
4755                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4756                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4757                         break;
4758                 case RTE_FLOW_ITEM_TYPE_UDP:
4759                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4760                                                           next_protocol,
4761                                                           error);
4762                         if (ret < 0)
4763                                 return ret;
4764                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4765                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4766                         break;
4767                 case RTE_FLOW_ITEM_TYPE_GRE:
4768                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4769                                                           next_protocol, error);
4770                         if (ret < 0)
4771                                 return ret;
4772                         gre_item = items;
4773                         last_item = MLX5_FLOW_LAYER_GRE;
4774                         break;
4775                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4776                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4777                                                             next_protocol,
4778                                                             error);
4779                         if (ret < 0)
4780                                 return ret;
4781                         last_item = MLX5_FLOW_LAYER_NVGRE;
4782                         break;
4783                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4784                         ret = mlx5_flow_validate_item_gre_key
4785                                 (items, item_flags, gre_item, error);
4786                         if (ret < 0)
4787                                 return ret;
4788                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4789                         break;
4790                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4791                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4792                                                             error);
4793                         if (ret < 0)
4794                                 return ret;
4795                         last_item = MLX5_FLOW_LAYER_VXLAN;
4796                         break;
4797                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4798                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4799                                                                 item_flags, dev,
4800                                                                 error);
4801                         if (ret < 0)
4802                                 return ret;
4803                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4804                         break;
4805                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4806                         ret = mlx5_flow_validate_item_geneve(items,
4807                                                              item_flags, dev,
4808                                                              error);
4809                         if (ret < 0)
4810                                 return ret;
4811                         last_item = MLX5_FLOW_LAYER_GENEVE;
4812                         break;
4813                 case RTE_FLOW_ITEM_TYPE_MPLS:
4814                         ret = mlx5_flow_validate_item_mpls(dev, items,
4815                                                            item_flags,
4816                                                            last_item, error);
4817                         if (ret < 0)
4818                                 return ret;
4819                         last_item = MLX5_FLOW_LAYER_MPLS;
4820                         break;
4821
4822                 case RTE_FLOW_ITEM_TYPE_MARK:
4823                         ret = flow_dv_validate_item_mark(dev, items, attr,
4824                                                          error);
4825                         if (ret < 0)
4826                                 return ret;
4827                         last_item = MLX5_FLOW_ITEM_MARK;
4828                         break;
4829                 case RTE_FLOW_ITEM_TYPE_META:
4830                         ret = flow_dv_validate_item_meta(dev, items, attr,
4831                                                          error);
4832                         if (ret < 0)
4833                                 return ret;
4834                         last_item = MLX5_FLOW_ITEM_METADATA;
4835                         break;
4836                 case RTE_FLOW_ITEM_TYPE_ICMP:
4837                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4838                                                            next_protocol,
4839                                                            error);
4840                         if (ret < 0)
4841                                 return ret;
4842                         last_item = MLX5_FLOW_LAYER_ICMP;
4843                         break;
4844                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4845                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4846                                                             next_protocol,
4847                                                             error);
4848                         if (ret < 0)
4849                                 return ret;
4850                         item_ipv6_proto = IPPROTO_ICMPV6;
4851                         last_item = MLX5_FLOW_LAYER_ICMP6;
4852                         break;
4853                 case RTE_FLOW_ITEM_TYPE_TAG:
4854                         ret = flow_dv_validate_item_tag(dev, items,
4855                                                         attr, error);
4856                         if (ret < 0)
4857                                 return ret;
4858                         last_item = MLX5_FLOW_ITEM_TAG;
4859                         break;
4860                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4861                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4862                         break;
4863                 case RTE_FLOW_ITEM_TYPE_GTP:
4864                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4865                                                         error);
4866                         if (ret < 0)
4867                                 return ret;
4868                         last_item = MLX5_FLOW_LAYER_GTP;
4869                         break;
4870                 default:
4871                         return rte_flow_error_set(error, ENOTSUP,
4872                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4873                                                   NULL, "item not supported");
4874                 }
4875                 item_flags |= last_item;
4876         }
4877         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4878                 int type = actions->type;
4879                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4880                         return rte_flow_error_set(error, ENOTSUP,
4881                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4882                                                   actions, "too many actions");
4883                 switch (type) {
4884                 case RTE_FLOW_ACTION_TYPE_VOID:
4885                         break;
4886                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4887                         ret = flow_dv_validate_action_port_id(dev,
4888                                                               action_flags,
4889                                                               actions,
4890                                                               attr,
4891                                                               error);
4892                         if (ret)
4893                                 return ret;
4894                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4895                         ++actions_n;
4896                         break;
4897                 case RTE_FLOW_ACTION_TYPE_FLAG:
4898                         ret = flow_dv_validate_action_flag(dev, action_flags,
4899                                                            attr, error);
4900                         if (ret < 0)
4901                                 return ret;
4902                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4903                                 /* Count all modify-header actions as one. */
4904                                 if (!(action_flags &
4905                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4906                                         ++actions_n;
4907                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4908                                                 MLX5_FLOW_ACTION_MARK_EXT;
4909                         } else {
4910                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4911                                 ++actions_n;
4912                         }
4913                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
4914                         break;
4915                 case RTE_FLOW_ACTION_TYPE_MARK:
4916                         ret = flow_dv_validate_action_mark(dev, actions,
4917                                                            action_flags,
4918                                                            attr, error);
4919                         if (ret < 0)
4920                                 return ret;
4921                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4922                                 /* Count all modify-header actions as one. */
4923                                 if (!(action_flags &
4924                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4925                                         ++actions_n;
4926                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4927                                                 MLX5_FLOW_ACTION_MARK_EXT;
4928                         } else {
4929                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4930                                 ++actions_n;
4931                         }
4932                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
4933                         break;
4934                 case RTE_FLOW_ACTION_TYPE_SET_META:
4935                         ret = flow_dv_validate_action_set_meta(dev, actions,
4936                                                                action_flags,
4937                                                                attr, error);
4938                         if (ret < 0)
4939                                 return ret;
4940                         /* Count all modify-header actions as one action. */
4941                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4942                                 ++actions_n;
4943                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4944                         rw_act_num += MLX5_ACT_NUM_SET_META;
4945                         break;
4946                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4947                         ret = flow_dv_validate_action_set_tag(dev, actions,
4948                                                               action_flags,
4949                                                               attr, error);
4950                         if (ret < 0)
4951                                 return ret;
4952                         /* Count all modify-header actions as one action. */
4953                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4954                                 ++actions_n;
4955                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4956                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
4957                         break;
4958                 case RTE_FLOW_ACTION_TYPE_DROP:
4959                         ret = mlx5_flow_validate_action_drop(action_flags,
4960                                                              attr, error);
4961                         if (ret < 0)
4962                                 return ret;
4963                         action_flags |= MLX5_FLOW_ACTION_DROP;
4964                         ++actions_n;
4965                         break;
4966                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4967                         ret = mlx5_flow_validate_action_queue(actions,
4968                                                               action_flags, dev,
4969                                                               attr, error);
4970                         if (ret < 0)
4971                                 return ret;
4972                         queue_index = ((const struct rte_flow_action_queue *)
4973                                                         (actions->conf))->index;
4974                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4975                         ++actions_n;
4976                         break;
4977                 case RTE_FLOW_ACTION_TYPE_RSS:
4978                         rss = actions->conf;
4979                         ret = mlx5_flow_validate_action_rss(actions,
4980                                                             action_flags, dev,
4981                                                             attr, item_flags,
4982                                                             error);
4983                         if (ret < 0)
4984                                 return ret;
4985                         if (rss != NULL && rss->queue_num)
4986                                 queue_index = rss->queue[0];
4987                         action_flags |= MLX5_FLOW_ACTION_RSS;
4988                         ++actions_n;
4989                         break;
4990                 case RTE_FLOW_ACTION_TYPE_COUNT:
4991                         ret = flow_dv_validate_action_count(dev, error);
4992                         if (ret < 0)
4993                                 return ret;
4994                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4995                         ++actions_n;
4996                         break;
4997                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4998                         if (flow_dv_validate_action_pop_vlan(dev,
4999                                                              action_flags,
5000                                                              actions,
5001                                                              item_flags, attr,
5002                                                              error))
5003                                 return -rte_errno;
5004                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5005                         ++actions_n;
5006                         break;
5007                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5008                         ret = flow_dv_validate_action_push_vlan(dev,
5009                                                                 action_flags,
5010                                                                 vlan_m,
5011                                                                 actions, attr,
5012                                                                 error);
5013                         if (ret < 0)
5014                                 return ret;
5015                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5016                         ++actions_n;
5017                         break;
5018                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5019                         ret = flow_dv_validate_action_set_vlan_pcp
5020                                                 (action_flags, actions, error);
5021                         if (ret < 0)
5022                                 return ret;
5023                         /* Count PCP with push_vlan command. */
5024                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5025                         break;
5026                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5027                         ret = flow_dv_validate_action_set_vlan_vid
5028                                                 (item_flags, action_flags,
5029                                                  actions, error);
5030                         if (ret < 0)
5031                                 return ret;
5032                         /* Count VID with push_vlan command. */
5033                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5034                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5035                         break;
5036                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5037                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5038                         ret = flow_dv_validate_action_l2_encap(dev,
5039                                                                action_flags,
5040                                                                actions, attr,
5041                                                                error);
5042                         if (ret < 0)
5043                                 return ret;
5044                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5045                         ++actions_n;
5046                         break;
5047                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5048                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5049                         ret = flow_dv_validate_action_decap(dev, action_flags,
5050                                                             attr, error);
5051                         if (ret < 0)
5052                                 return ret;
5053                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5054                         ++actions_n;
5055                         break;
5056                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5057                         ret = flow_dv_validate_action_raw_encap_decap
5058                                 (dev, NULL, actions->conf, attr, &action_flags,
5059                                  &actions_n, error);
5060                         if (ret < 0)
5061                                 return ret;
5062                         break;
5063                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5064                         decap = actions->conf;
5065                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5066                                 ;
5067                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5068                                 encap = NULL;
5069                                 actions--;
5070                         } else {
5071                                 encap = actions->conf;
5072                         }
5073                         ret = flow_dv_validate_action_raw_encap_decap
5074                                            (dev,
5075                                             decap ? decap : &empty_decap, encap,
5076                                             attr, &action_flags, &actions_n,
5077                                             error);
5078                         if (ret < 0)
5079                                 return ret;
5080                         break;
5081                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5082                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5083                         ret = flow_dv_validate_action_modify_mac(action_flags,
5084                                                                  actions,
5085                                                                  item_flags,
5086                                                                  error);
5087                         if (ret < 0)
5088                                 return ret;
5089                         /* Count all modify-header actions as one action. */
5090                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5091                                 ++actions_n;
5092                         action_flags |= actions->type ==
5093                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5094                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5095                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5096                         /*
5097                          * Even if the source and destination MAC addresses have
5098                          * overlap in the header with 4B alignment, the convert
5099                          * function will handle them separately and 4 SW actions
5100                          * will be created. And 2 actions will be added each
5101                          * time no matter how many bytes of address will be set.
5102                          */
5103                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5104                         break;
5105                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5106                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5107                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5108                                                                   actions,
5109                                                                   item_flags,
5110                                                                   error);
5111                         if (ret < 0)
5112                                 return ret;
5113                         /* Count all modify-header actions as one action. */
5114                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5115                                 ++actions_n;
5116                         action_flags |= actions->type ==
5117                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5118                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5119                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5120                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5121                         break;
5122                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5123                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5124                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5125                                                                   actions,
5126                                                                   item_flags,
5127                                                                   error);
5128                         if (ret < 0)
5129                                 return ret;
5130                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5131                                 return rte_flow_error_set(error, ENOTSUP,
5132                                         RTE_FLOW_ERROR_TYPE_ACTION,
5133                                         actions,
5134                                         "Can't change header "
5135                                         "with ICMPv6 proto");
5136                         /* Count all modify-header actions as one action. */
5137                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5138                                 ++actions_n;
5139                         action_flags |= actions->type ==
5140                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5141                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5142                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5143                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5144                         break;
5145                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5146                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5147                         ret = flow_dv_validate_action_modify_tp(action_flags,
5148                                                                 actions,
5149                                                                 item_flags,
5150                                                                 error);
5151                         if (ret < 0)
5152                                 return ret;
5153                         /* Count all modify-header actions as one action. */
5154                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5155                                 ++actions_n;
5156                         action_flags |= actions->type ==
5157                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5158                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5159                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5160                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5161                         break;
5162                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5163                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5164                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5165                                                                  actions,
5166                                                                  item_flags,
5167                                                                  error);
5168                         if (ret < 0)
5169                                 return ret;
5170                         /* Count all modify-header actions as one action. */
5171                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5172                                 ++actions_n;
5173                         action_flags |= actions->type ==
5174                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5175                                                 MLX5_FLOW_ACTION_SET_TTL :
5176                                                 MLX5_FLOW_ACTION_DEC_TTL;
5177                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5178                         break;
5179                 case RTE_FLOW_ACTION_TYPE_JUMP:
5180                         ret = flow_dv_validate_action_jump(actions,
5181                                                            action_flags,
5182                                                            attr, external,
5183                                                            error);
5184                         if (ret)
5185                                 return ret;
5186                         ++actions_n;
5187                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5188                         break;
5189                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5190                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5191                         ret = flow_dv_validate_action_modify_tcp_seq
5192                                                                 (action_flags,
5193                                                                  actions,
5194                                                                  item_flags,
5195                                                                  error);
5196                         if (ret < 0)
5197                                 return ret;
5198                         /* Count all modify-header actions as one action. */
5199                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5200                                 ++actions_n;
5201                         action_flags |= actions->type ==
5202                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5203                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5204                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5205                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5206                         break;
5207                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5208                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5209                         ret = flow_dv_validate_action_modify_tcp_ack
5210                                                                 (action_flags,
5211                                                                  actions,
5212                                                                  item_flags,
5213                                                                  error);
5214                         if (ret < 0)
5215                                 return ret;
5216                         /* Count all modify-header actions as one action. */
5217                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5218                                 ++actions_n;
5219                         action_flags |= actions->type ==
5220                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5221                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5222                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5223                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5224                         break;
5225                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5226                         break;
5227                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5228                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5229                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5230                         break;
5231                 case RTE_FLOW_ACTION_TYPE_METER:
5232                         ret = mlx5_flow_validate_action_meter(dev,
5233                                                               action_flags,
5234                                                               actions, attr,
5235                                                               error);
5236                         if (ret < 0)
5237                                 return ret;
5238                         action_flags |= MLX5_FLOW_ACTION_METER;
5239                         ++actions_n;
5240                         /* Meter action will add one more TAG action. */
5241                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5242                         break;
5243                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5244                         ret = flow_dv_validate_action_modify_ipv4_dscp
5245                                                          (action_flags,
5246                                                           actions,
5247                                                           item_flags,
5248                                                           error);
5249                         if (ret < 0)
5250                                 return ret;
5251                         /* Count all modify-header actions as one action. */
5252                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5253                                 ++actions_n;
5254                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5255                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5256                         break;
5257                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5258                         ret = flow_dv_validate_action_modify_ipv6_dscp
5259                                                                 (action_flags,
5260                                                                  actions,
5261                                                                  item_flags,
5262                                                                  error);
5263                         if (ret < 0)
5264                                 return ret;
5265                         /* Count all modify-header actions as one action. */
5266                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5267                                 ++actions_n;
5268                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5269                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5270                         break;
5271                 default:
5272                         return rte_flow_error_set(error, ENOTSUP,
5273                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5274                                                   actions,
5275                                                   "action not supported");
5276                 }
5277         }
5278         /*
5279          * Validate the drop action mutual exclusion with other actions.
5280          * Drop action is mutually-exclusive with any other action, except for
5281          * Count action.
5282          */
5283         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5284             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5285                 return rte_flow_error_set(error, EINVAL,
5286                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5287                                           "Drop action is mutually-exclusive "
5288                                           "with any other action, except for "
5289                                           "Count action");
5290         /* Eswitch has few restrictions on using items and actions */
5291         if (attr->transfer) {
5292                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5293                     action_flags & MLX5_FLOW_ACTION_FLAG)
5294                         return rte_flow_error_set(error, ENOTSUP,
5295                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5296                                                   NULL,
5297                                                   "unsupported action FLAG");
5298                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5299                     action_flags & MLX5_FLOW_ACTION_MARK)
5300                         return rte_flow_error_set(error, ENOTSUP,
5301                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5302                                                   NULL,
5303                                                   "unsupported action MARK");
5304                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5305                         return rte_flow_error_set(error, ENOTSUP,
5306                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5307                                                   NULL,
5308                                                   "unsupported action QUEUE");
5309                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5310                         return rte_flow_error_set(error, ENOTSUP,
5311                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5312                                                   NULL,
5313                                                   "unsupported action RSS");
5314                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5315                         return rte_flow_error_set(error, EINVAL,
5316                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5317                                                   actions,
5318                                                   "no fate action is found");
5319         } else {
5320                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5321                         return rte_flow_error_set(error, EINVAL,
5322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5323                                                   actions,
5324                                                   "no fate action is found");
5325         }
5326         /* Continue validation for Xcap actions.*/
5327         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5328             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5329                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5330                     MLX5_FLOW_XCAP_ACTIONS)
5331                         return rte_flow_error_set(error, ENOTSUP,
5332                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5333                                                   NULL, "encap and decap "
5334                                                   "combination aren't supported");
5335                 if (!attr->transfer && attr->ingress && (action_flags &
5336                                                         MLX5_FLOW_ACTION_ENCAP))
5337                         return rte_flow_error_set(error, ENOTSUP,
5338                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5339                                                   NULL, "encap is not supported"
5340                                                   " for ingress traffic");
5341         }
5342         /* Hairpin flow will add one more TAG action. */
5343         if (hairpin > 0)
5344                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5345         /* extra metadata enabled: one more TAG action will be add. */
5346         if (dev_conf->dv_flow_en &&
5347             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5348             mlx5_flow_ext_mreg_supported(dev))
5349                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5350         if ((uint32_t)rw_act_num >=
5351                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5352                 return rte_flow_error_set(error, ENOTSUP,
5353                                           RTE_FLOW_ERROR_TYPE_ACTION,
5354                                           NULL, "too many header modify"
5355                                           " actions to support");
5356         }
5357         return 0;
5358 }
5359
5360 /**
5361  * Internal preparation function. Allocates the DV flow size,
5362  * this size is constant.
5363  *
5364  * @param[in] dev
5365  *   Pointer to the rte_eth_dev structure.
5366  * @param[in] attr
5367  *   Pointer to the flow attributes.
5368  * @param[in] items
5369  *   Pointer to the list of items.
5370  * @param[in] actions
5371  *   Pointer to the list of actions.
5372  * @param[out] error
5373  *   Pointer to the error structure.
5374  *
5375  * @return
5376  *   Pointer to mlx5_flow object on success,
5377  *   otherwise NULL and rte_errno is set.
5378  */
5379 static struct mlx5_flow *
5380 flow_dv_prepare(struct rte_eth_dev *dev,
5381                 const struct rte_flow_attr *attr __rte_unused,
5382                 const struct rte_flow_item items[] __rte_unused,
5383                 const struct rte_flow_action actions[] __rte_unused,
5384                 struct rte_flow_error *error)
5385 {
5386         uint32_t handle_idx = 0;
5387         struct mlx5_flow *dev_flow;
5388         struct mlx5_flow_handle *dev_handle;
5389         struct mlx5_priv *priv = dev->data->dev_private;
5390
5391         /* In case of corrupting the memory. */
5392         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5393                 rte_flow_error_set(error, ENOSPC,
5394                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5395                                    "not free temporary device flow");
5396                 return NULL;
5397         }
5398         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5399                                    &handle_idx);
5400         if (!dev_handle) {
5401                 rte_flow_error_set(error, ENOMEM,
5402                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5403                                    "not enough memory to create flow handle");
5404                 return NULL;
5405         }
5406         /* No multi-thread supporting. */
5407         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5408         dev_flow->handle = dev_handle;
5409         dev_flow->handle_idx = handle_idx;
5410         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5411         /*
5412          * The matching value needs to be cleared to 0 before using. In the
5413          * past, it will be automatically cleared when using rte_*alloc
5414          * API. The time consumption will be almost the same as before.
5415          */
5416         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5417         dev_flow->ingress = attr->ingress;
5418         dev_flow->dv.transfer = attr->transfer;
5419         return dev_flow;
5420 }
5421
5422 #ifdef RTE_LIBRTE_MLX5_DEBUG
5423 /**
5424  * Sanity check for match mask and value. Similar to check_valid_spec() in
5425  * kernel driver. If unmasked bit is present in value, it returns failure.
5426  *
5427  * @param match_mask
5428  *   pointer to match mask buffer.
5429  * @param match_value
5430  *   pointer to match value buffer.
5431  *
5432  * @return
5433  *   0 if valid, -EINVAL otherwise.
5434  */
5435 static int
5436 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5437 {
5438         uint8_t *m = match_mask;
5439         uint8_t *v = match_value;
5440         unsigned int i;
5441
5442         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5443                 if (v[i] & ~m[i]) {
5444                         DRV_LOG(ERR,
5445                                 "match_value differs from match_criteria"
5446                                 " %p[%u] != %p[%u]",
5447                                 match_value, i, match_mask, i);
5448                         return -EINVAL;
5449                 }
5450         }
5451         return 0;
5452 }
5453 #endif
5454
5455 /**
5456  * Add Ethernet item to matcher and to the value.
5457  *
5458  * @param[in, out] matcher
5459  *   Flow matcher.
5460  * @param[in, out] key
5461  *   Flow matcher value.
5462  * @param[in] item
5463  *   Flow pattern to translate.
5464  * @param[in] inner
5465  *   Item is inner pattern.
5466  */
5467 static void
5468 flow_dv_translate_item_eth(void *matcher, void *key,
5469                            const struct rte_flow_item *item, int inner)
5470 {
5471         const struct rte_flow_item_eth *eth_m = item->mask;
5472         const struct rte_flow_item_eth *eth_v = item->spec;
5473         const struct rte_flow_item_eth nic_mask = {
5474                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5475                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5476                 .type = RTE_BE16(0xffff),
5477         };
5478         void *headers_m;
5479         void *headers_v;
5480         char *l24_v;
5481         unsigned int i;
5482
5483         if (!eth_v)
5484                 return;
5485         if (!eth_m)
5486                 eth_m = &nic_mask;
5487         if (inner) {
5488                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5489                                          inner_headers);
5490                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5491         } else {
5492                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5493                                          outer_headers);
5494                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5495         }
5496         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5497                &eth_m->dst, sizeof(eth_m->dst));
5498         /* The value must be in the range of the mask. */
5499         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5500         for (i = 0; i < sizeof(eth_m->dst); ++i)
5501                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5502         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5503                &eth_m->src, sizeof(eth_m->src));
5504         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5505         /* The value must be in the range of the mask. */
5506         for (i = 0; i < sizeof(eth_m->dst); ++i)
5507                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5508         if (eth_v->type) {
5509                 /* When ethertype is present set mask for tagged VLAN. */
5510                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5511                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5512                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5513                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5514                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5515                                  1);
5516                         /* Return here to avoid setting match on ethertype. */
5517                         return;
5518                 }
5519         }
5520         /*
5521          * HW supports match on one Ethertype, the Ethertype following the last
5522          * VLAN tag of the packet (see PRM).
5523          * Set match on ethertype only if ETH header is not followed by VLAN.
5524          */
5525         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5526                  rte_be_to_cpu_16(eth_m->type));
5527         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5528         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5529 }
5530
5531 /**
5532  * Add VLAN item to matcher and to the value.
5533  *
5534  * @param[in, out] dev_flow
5535  *   Flow descriptor.
5536  * @param[in, out] matcher
5537  *   Flow matcher.
5538  * @param[in, out] key
5539  *   Flow matcher value.
5540  * @param[in] item
5541  *   Flow pattern to translate.
5542  * @param[in] inner
5543  *   Item is inner pattern.
5544  */
5545 static void
5546 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5547                             void *matcher, void *key,
5548                             const struct rte_flow_item *item,
5549                             int inner)
5550 {
5551         const struct rte_flow_item_vlan *vlan_m = item->mask;
5552         const struct rte_flow_item_vlan *vlan_v = item->spec;
5553         void *headers_m;
5554         void *headers_v;
5555         uint16_t tci_m;
5556         uint16_t tci_v;
5557
5558         if (!vlan_v)
5559                 return;
5560         if (!vlan_m)
5561                 vlan_m = &rte_flow_item_vlan_mask;
5562         if (inner) {
5563                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5564                                          inner_headers);
5565                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5566         } else {
5567                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5568                                          outer_headers);
5569                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5570                 /*
5571                  * This is workaround, masks are not supported,
5572                  * and pre-validated.
5573                  */
5574                 dev_flow->handle->vf_vlan.tag =
5575                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5576         }
5577         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5578         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5579         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5580         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5581         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5582         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5583         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5584         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5585         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5586         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5587         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5588                  rte_be_to_cpu_16(vlan_m->inner_type));
5589         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5590                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5591 }
5592
5593 /**
5594  * Add IPV4 item to matcher and to the value.
5595  *
5596  * @param[in, out] matcher
5597  *   Flow matcher.
5598  * @param[in, out] key
5599  *   Flow matcher value.
5600  * @param[in] item
5601  *   Flow pattern to translate.
5602  * @param[in] item_flags
5603  *   Bit-fields that holds the items detected until now.
5604  * @param[in] inner
5605  *   Item is inner pattern.
5606  * @param[in] group
5607  *   The group to insert the rule.
5608  */
5609 static void
5610 flow_dv_translate_item_ipv4(void *matcher, void *key,
5611                             const struct rte_flow_item *item,
5612                             const uint64_t item_flags,
5613                             int inner, uint32_t group)
5614 {
5615         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5616         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5617         const struct rte_flow_item_ipv4 nic_mask = {
5618                 .hdr = {
5619                         .src_addr = RTE_BE32(0xffffffff),
5620                         .dst_addr = RTE_BE32(0xffffffff),
5621                         .type_of_service = 0xff,
5622                         .next_proto_id = 0xff,
5623                         .time_to_live = 0xff,
5624                 },
5625         };
5626         void *headers_m;
5627         void *headers_v;
5628         char *l24_m;
5629         char *l24_v;
5630         uint8_t tos;
5631
5632         if (inner) {
5633                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5634                                          inner_headers);
5635                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5636         } else {
5637                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5638                                          outer_headers);
5639                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5640         }
5641         if (group == 0)
5642                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5643         else
5644                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5645         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5646         /*
5647          * On outer header (which must contains L2), or inner header with L2,
5648          * set cvlan_tag mask bit to mark this packet as untagged.
5649          * This should be done even if item->spec is empty.
5650          */
5651         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5652                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5653         if (!ipv4_v)
5654                 return;
5655         if (!ipv4_m)
5656                 ipv4_m = &nic_mask;
5657         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5658                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5659         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5660                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5661         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5662         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5663         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5664                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5665         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5666                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5667         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5668         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5669         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5670         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5671                  ipv4_m->hdr.type_of_service);
5672         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5673         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5674                  ipv4_m->hdr.type_of_service >> 2);
5675         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5676         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5677                  ipv4_m->hdr.next_proto_id);
5678         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5679                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5680         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5681                  ipv4_m->hdr.time_to_live);
5682         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5683                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5684 }
5685
5686 /**
5687  * Add IPV6 item to matcher and to the value.
5688  *
5689  * @param[in, out] matcher
5690  *   Flow matcher.
5691  * @param[in, out] key
5692  *   Flow matcher value.
5693  * @param[in] item
5694  *   Flow pattern to translate.
5695  * @param[in] item_flags
5696  *   Bit-fields that holds the items detected until now.
5697  * @param[in] inner
5698  *   Item is inner pattern.
5699  * @param[in] group
5700  *   The group to insert the rule.
5701  */
5702 static void
5703 flow_dv_translate_item_ipv6(void *matcher, void *key,
5704                             const struct rte_flow_item *item,
5705                             const uint64_t item_flags,
5706                             int inner, uint32_t group)
5707 {
5708         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5709         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5710         const struct rte_flow_item_ipv6 nic_mask = {
5711                 .hdr = {
5712                         .src_addr =
5713                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5714                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5715                         .dst_addr =
5716                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5717                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5718                         .vtc_flow = RTE_BE32(0xffffffff),
5719                         .proto = 0xff,
5720                         .hop_limits = 0xff,
5721                 },
5722         };
5723         void *headers_m;
5724         void *headers_v;
5725         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5726         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5727         char *l24_m;
5728         char *l24_v;
5729         uint32_t vtc_m;
5730         uint32_t vtc_v;
5731         int i;
5732         int size;
5733
5734         if (inner) {
5735                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5736                                          inner_headers);
5737                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5738         } else {
5739                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5740                                          outer_headers);
5741                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5742         }
5743         if (group == 0)
5744                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5745         else
5746                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5747         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5748         /*
5749          * On outer header (which must contains L2), or inner header with L2,
5750          * set cvlan_tag mask bit to mark this packet as untagged.
5751          * This should be done even if item->spec is empty.
5752          */
5753         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5754                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5755         if (!ipv6_v)
5756                 return;
5757         if (!ipv6_m)
5758                 ipv6_m = &nic_mask;
5759         size = sizeof(ipv6_m->hdr.dst_addr);
5760         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5761                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5762         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5763                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5764         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5765         for (i = 0; i < size; ++i)
5766                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5767         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5768                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5769         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5770                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5771         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5772         for (i = 0; i < size; ++i)
5773                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5774         /* TOS. */
5775         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5776         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5777         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5778         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5779         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5780         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5781         /* Label. */
5782         if (inner) {
5783                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5784                          vtc_m);
5785                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5786                          vtc_v);
5787         } else {
5788                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5789                          vtc_m);
5790                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5791                          vtc_v);
5792         }
5793         /* Protocol. */
5794         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5795                  ipv6_m->hdr.proto);
5796         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5797                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5798         /* Hop limit. */
5799         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5800                  ipv6_m->hdr.hop_limits);
5801         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5802                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5803 }
5804
5805 /**
5806  * Add TCP item to matcher and to the value.
5807  *
5808  * @param[in, out] matcher
5809  *   Flow matcher.
5810  * @param[in, out] key
5811  *   Flow matcher value.
5812  * @param[in] item
5813  *   Flow pattern to translate.
5814  * @param[in] inner
5815  *   Item is inner pattern.
5816  */
5817 static void
5818 flow_dv_translate_item_tcp(void *matcher, void *key,
5819                            const struct rte_flow_item *item,
5820                            int inner)
5821 {
5822         const struct rte_flow_item_tcp *tcp_m = item->mask;
5823         const struct rte_flow_item_tcp *tcp_v = item->spec;
5824         void *headers_m;
5825         void *headers_v;
5826
5827         if (inner) {
5828                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5829                                          inner_headers);
5830                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5831         } else {
5832                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5833                                          outer_headers);
5834                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5835         }
5836         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5837         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5838         if (!tcp_v)
5839                 return;
5840         if (!tcp_m)
5841                 tcp_m = &rte_flow_item_tcp_mask;
5842         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5843                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5845                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5846         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5847                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5848         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5849                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5850         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5851                  tcp_m->hdr.tcp_flags);
5852         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5853                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5854 }
5855
5856 /**
5857  * Add UDP item to matcher and to the value.
5858  *
5859  * @param[in, out] matcher
5860  *   Flow matcher.
5861  * @param[in, out] key
5862  *   Flow matcher value.
5863  * @param[in] item
5864  *   Flow pattern to translate.
5865  * @param[in] inner
5866  *   Item is inner pattern.
5867  */
5868 static void
5869 flow_dv_translate_item_udp(void *matcher, void *key,
5870                            const struct rte_flow_item *item,
5871                            int inner)
5872 {
5873         const struct rte_flow_item_udp *udp_m = item->mask;
5874         const struct rte_flow_item_udp *udp_v = item->spec;
5875         void *headers_m;
5876         void *headers_v;
5877
5878         if (inner) {
5879                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5880                                          inner_headers);
5881                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5882         } else {
5883                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5884                                          outer_headers);
5885                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5886         }
5887         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5888         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5889         if (!udp_v)
5890                 return;
5891         if (!udp_m)
5892                 udp_m = &rte_flow_item_udp_mask;
5893         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5894                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5895         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5896                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5897         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5898                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5899         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5900                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5901 }
5902
5903 /**
5904  * Add GRE optional Key item to matcher and to the value.
5905  *
5906  * @param[in, out] matcher
5907  *   Flow matcher.
5908  * @param[in, out] key
5909  *   Flow matcher value.
5910  * @param[in] item
5911  *   Flow pattern to translate.
5912  * @param[in] inner
5913  *   Item is inner pattern.
5914  */
5915 static void
5916 flow_dv_translate_item_gre_key(void *matcher, void *key,
5917                                    const struct rte_flow_item *item)
5918 {
5919         const rte_be32_t *key_m = item->mask;
5920         const rte_be32_t *key_v = item->spec;
5921         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5922         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5923         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5924
5925         /* GRE K bit must be on and should already be validated */
5926         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5927         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5928         if (!key_v)
5929                 return;
5930         if (!key_m)
5931                 key_m = &gre_key_default_mask;
5932         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5933                  rte_be_to_cpu_32(*key_m) >> 8);
5934         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5935                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5936         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5937                  rte_be_to_cpu_32(*key_m) & 0xFF);
5938         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5939                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5940 }
5941
5942 /**
5943  * Add GRE item to matcher and to the value.
5944  *
5945  * @param[in, out] matcher
5946  *   Flow matcher.
5947  * @param[in, out] key
5948  *   Flow matcher value.
5949  * @param[in] item
5950  *   Flow pattern to translate.
5951  * @param[in] inner
5952  *   Item is inner pattern.
5953  */
5954 static void
5955 flow_dv_translate_item_gre(void *matcher, void *key,
5956                            const struct rte_flow_item *item,
5957                            int inner)
5958 {
5959         const struct rte_flow_item_gre *gre_m = item->mask;
5960         const struct rte_flow_item_gre *gre_v = item->spec;
5961         void *headers_m;
5962         void *headers_v;
5963         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5964         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5965         struct {
5966                 union {
5967                         __extension__
5968                         struct {
5969                                 uint16_t version:3;
5970                                 uint16_t rsvd0:9;
5971                                 uint16_t s_present:1;
5972                                 uint16_t k_present:1;
5973                                 uint16_t rsvd_bit1:1;
5974                                 uint16_t c_present:1;
5975                         };
5976                         uint16_t value;
5977                 };
5978         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5979
5980         if (inner) {
5981                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5982                                          inner_headers);
5983                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5984         } else {
5985                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5986                                          outer_headers);
5987                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5988         }
5989         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5990         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5991         if (!gre_v)
5992                 return;
5993         if (!gre_m)
5994                 gre_m = &rte_flow_item_gre_mask;
5995         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5996                  rte_be_to_cpu_16(gre_m->protocol));
5997         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5998                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5999         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6000         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6001         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6002                  gre_crks_rsvd0_ver_m.c_present);
6003         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6004                  gre_crks_rsvd0_ver_v.c_present &
6005                  gre_crks_rsvd0_ver_m.c_present);
6006         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6007                  gre_crks_rsvd0_ver_m.k_present);
6008         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6009                  gre_crks_rsvd0_ver_v.k_present &
6010                  gre_crks_rsvd0_ver_m.k_present);
6011         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6012                  gre_crks_rsvd0_ver_m.s_present);
6013         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6014                  gre_crks_rsvd0_ver_v.s_present &
6015                  gre_crks_rsvd0_ver_m.s_present);
6016 }
6017
6018 /**
6019  * Add NVGRE item to matcher and to the value.
6020  *
6021  * @param[in, out] matcher
6022  *   Flow matcher.
6023  * @param[in, out] key
6024  *   Flow matcher value.
6025  * @param[in] item
6026  *   Flow pattern to translate.
6027  * @param[in] inner
6028  *   Item is inner pattern.
6029  */
6030 static void
6031 flow_dv_translate_item_nvgre(void *matcher, void *key,
6032                              const struct rte_flow_item *item,
6033                              int inner)
6034 {
6035         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6036         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6037         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6038         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6039         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6040         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6041         char *gre_key_m;
6042         char *gre_key_v;
6043         int size;
6044         int i;
6045
6046         /* For NVGRE, GRE header fields must be set with defined values. */
6047         const struct rte_flow_item_gre gre_spec = {
6048                 .c_rsvd0_ver = RTE_BE16(0x2000),
6049                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6050         };
6051         const struct rte_flow_item_gre gre_mask = {
6052                 .c_rsvd0_ver = RTE_BE16(0xB000),
6053                 .protocol = RTE_BE16(UINT16_MAX),
6054         };
6055         const struct rte_flow_item gre_item = {
6056                 .spec = &gre_spec,
6057                 .mask = &gre_mask,
6058                 .last = NULL,
6059         };
6060         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6061         if (!nvgre_v)
6062                 return;
6063         if (!nvgre_m)
6064                 nvgre_m = &rte_flow_item_nvgre_mask;
6065         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6066         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6067         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6068         memcpy(gre_key_m, tni_flow_id_m, size);
6069         for (i = 0; i < size; ++i)
6070                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6071 }
6072
6073 /**
6074  * Add VXLAN item to matcher and to the value.
6075  *
6076  * @param[in, out] matcher
6077  *   Flow matcher.
6078  * @param[in, out] key
6079  *   Flow matcher value.
6080  * @param[in] item
6081  *   Flow pattern to translate.
6082  * @param[in] inner
6083  *   Item is inner pattern.
6084  */
6085 static void
6086 flow_dv_translate_item_vxlan(void *matcher, void *key,
6087                              const struct rte_flow_item *item,
6088                              int inner)
6089 {
6090         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6091         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6092         void *headers_m;
6093         void *headers_v;
6094         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6095         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6096         char *vni_m;
6097         char *vni_v;
6098         uint16_t dport;
6099         int size;
6100         int i;
6101
6102         if (inner) {
6103                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6104                                          inner_headers);
6105                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6106         } else {
6107                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6108                                          outer_headers);
6109                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6110         }
6111         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6112                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6113         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6114                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6115                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6116         }
6117         if (!vxlan_v)
6118                 return;
6119         if (!vxlan_m)
6120                 vxlan_m = &rte_flow_item_vxlan_mask;
6121         size = sizeof(vxlan_m->vni);
6122         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6123         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6124         memcpy(vni_m, vxlan_m->vni, size);
6125         for (i = 0; i < size; ++i)
6126                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6127 }
6128
6129 /**
6130  * Add VXLAN-GPE item to matcher and to the value.
6131  *
6132  * @param[in, out] matcher
6133  *   Flow matcher.
6134  * @param[in, out] key
6135  *   Flow matcher value.
6136  * @param[in] item
6137  *   Flow pattern to translate.
6138  * @param[in] inner
6139  *   Item is inner pattern.
6140  */
6141
6142 static void
6143 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6144                                  const struct rte_flow_item *item, int inner)
6145 {
6146         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6147         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6148         void *headers_m;
6149         void *headers_v;
6150         void *misc_m =
6151                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6152         void *misc_v =
6153                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6154         char *vni_m;
6155         char *vni_v;
6156         uint16_t dport;
6157         int size;
6158         int i;
6159         uint8_t flags_m = 0xff;
6160         uint8_t flags_v = 0xc;
6161
6162         if (inner) {
6163                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6164                                          inner_headers);
6165                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6166         } else {
6167                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6168                                          outer_headers);
6169                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6170         }
6171         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6172                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6173         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6174                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6175                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6176         }
6177         if (!vxlan_v)
6178                 return;
6179         if (!vxlan_m)
6180                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6181         size = sizeof(vxlan_m->vni);
6182         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6183         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6184         memcpy(vni_m, vxlan_m->vni, size);
6185         for (i = 0; i < size; ++i)
6186                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6187         if (vxlan_m->flags) {
6188                 flags_m = vxlan_m->flags;
6189                 flags_v = vxlan_v->flags;
6190         }
6191         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6192         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6193         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6194                  vxlan_m->protocol);
6195         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6196                  vxlan_v->protocol);
6197 }
6198
6199 /**
6200  * Add Geneve item to matcher and to the value.
6201  *
6202  * @param[in, out] matcher
6203  *   Flow matcher.
6204  * @param[in, out] key
6205  *   Flow matcher value.
6206  * @param[in] item
6207  *   Flow pattern to translate.
6208  * @param[in] inner
6209  *   Item is inner pattern.
6210  */
6211
6212 static void
6213 flow_dv_translate_item_geneve(void *matcher, void *key,
6214                               const struct rte_flow_item *item, int inner)
6215 {
6216         const struct rte_flow_item_geneve *geneve_m = item->mask;
6217         const struct rte_flow_item_geneve *geneve_v = item->spec;
6218         void *headers_m;
6219         void *headers_v;
6220         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6221         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6222         uint16_t dport;
6223         uint16_t gbhdr_m;
6224         uint16_t gbhdr_v;
6225         char *vni_m;
6226         char *vni_v;
6227         size_t size, i;
6228
6229         if (inner) {
6230                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6231                                          inner_headers);
6232                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6233         } else {
6234                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6235                                          outer_headers);
6236                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6237         }
6238         dport = MLX5_UDP_PORT_GENEVE;
6239         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6240                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6241                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6242         }
6243         if (!geneve_v)
6244                 return;
6245         if (!geneve_m)
6246                 geneve_m = &rte_flow_item_geneve_mask;
6247         size = sizeof(geneve_m->vni);
6248         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6249         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6250         memcpy(vni_m, geneve_m->vni, size);
6251         for (i = 0; i < size; ++i)
6252                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6253         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6254                  rte_be_to_cpu_16(geneve_m->protocol));
6255         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6256                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6257         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6258         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6259         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6260                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6261         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6262                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6263         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6264                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6265         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6266                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6267                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6268 }
6269
6270 /**
6271  * Add MPLS item to matcher and to the value.
6272  *
6273  * @param[in, out] matcher
6274  *   Flow matcher.
6275  * @param[in, out] key
6276  *   Flow matcher value.
6277  * @param[in] item
6278  *   Flow pattern to translate.
6279  * @param[in] prev_layer
6280  *   The protocol layer indicated in previous item.
6281  * @param[in] inner
6282  *   Item is inner pattern.
6283  */
6284 static void
6285 flow_dv_translate_item_mpls(void *matcher, void *key,
6286                             const struct rte_flow_item *item,
6287                             uint64_t prev_layer,
6288                             int inner)
6289 {
6290         const uint32_t *in_mpls_m = item->mask;
6291         const uint32_t *in_mpls_v = item->spec;
6292         uint32_t *out_mpls_m = 0;
6293         uint32_t *out_mpls_v = 0;
6294         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6295         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6296         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6297                                      misc_parameters_2);
6298         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6299         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6300         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6301
6302         switch (prev_layer) {
6303         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6304                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6305                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6306                          MLX5_UDP_PORT_MPLS);
6307                 break;
6308         case MLX5_FLOW_LAYER_GRE:
6309                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6310                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6311                          RTE_ETHER_TYPE_MPLS);
6312                 break;
6313         default:
6314                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6315                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6316                          IPPROTO_MPLS);
6317                 break;
6318         }
6319         if (!in_mpls_v)
6320                 return;
6321         if (!in_mpls_m)
6322                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6323         switch (prev_layer) {
6324         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6325                 out_mpls_m =
6326                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6327                                                  outer_first_mpls_over_udp);
6328                 out_mpls_v =
6329                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6330                                                  outer_first_mpls_over_udp);
6331                 break;
6332         case MLX5_FLOW_LAYER_GRE:
6333                 out_mpls_m =
6334                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6335                                                  outer_first_mpls_over_gre);
6336                 out_mpls_v =
6337                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6338                                                  outer_first_mpls_over_gre);
6339                 break;
6340         default:
6341                 /* Inner MPLS not over GRE is not supported. */
6342                 if (!inner) {
6343                         out_mpls_m =
6344                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6345                                                          misc2_m,
6346                                                          outer_first_mpls);
6347                         out_mpls_v =
6348                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6349                                                          misc2_v,
6350                                                          outer_first_mpls);
6351                 }
6352                 break;
6353         }
6354         if (out_mpls_m && out_mpls_v) {
6355                 *out_mpls_m = *in_mpls_m;
6356                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6357         }
6358 }
6359
6360 /**
6361  * Add metadata register item to matcher
6362  *
6363  * @param[in, out] matcher
6364  *   Flow matcher.
6365  * @param[in, out] key
6366  *   Flow matcher value.
6367  * @param[in] reg_type
6368  *   Type of device metadata register
6369  * @param[in] value
6370  *   Register value
6371  * @param[in] mask
6372  *   Register mask
6373  */
6374 static void
6375 flow_dv_match_meta_reg(void *matcher, void *key,
6376                        enum modify_reg reg_type,
6377                        uint32_t data, uint32_t mask)
6378 {
6379         void *misc2_m =
6380                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6381         void *misc2_v =
6382                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6383         uint32_t temp;
6384
6385         data &= mask;
6386         switch (reg_type) {
6387         case REG_A:
6388                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6389                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6390                 break;
6391         case REG_B:
6392                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6393                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6394                 break;
6395         case REG_C_0:
6396                 /*
6397                  * The metadata register C0 field might be divided into
6398                  * source vport index and META item value, we should set
6399                  * this field according to specified mask, not as whole one.
6400                  */
6401                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6402                 temp |= mask;
6403                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6404                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6405                 temp &= ~mask;
6406                 temp |= data;
6407                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6408                 break;
6409         case REG_C_1:
6410                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6411                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6412                 break;
6413         case REG_C_2:
6414                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6415                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6416                 break;
6417         case REG_C_3:
6418                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6419                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6420                 break;
6421         case REG_C_4:
6422                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6423                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6424                 break;
6425         case REG_C_5:
6426                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6427                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6428                 break;
6429         case REG_C_6:
6430                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6431                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6432                 break;
6433         case REG_C_7:
6434                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6435                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6436                 break;
6437         default:
6438                 MLX5_ASSERT(false);
6439                 break;
6440         }
6441 }
6442
6443 /**
6444  * Add MARK item to matcher
6445  *
6446  * @param[in] dev
6447  *   The device to configure through.
6448  * @param[in, out] matcher
6449  *   Flow matcher.
6450  * @param[in, out] key
6451  *   Flow matcher value.
6452  * @param[in] item
6453  *   Flow pattern to translate.
6454  */
6455 static void
6456 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6457                             void *matcher, void *key,
6458                             const struct rte_flow_item *item)
6459 {
6460         struct mlx5_priv *priv = dev->data->dev_private;
6461         const struct rte_flow_item_mark *mark;
6462         uint32_t value;
6463         uint32_t mask;
6464
6465         mark = item->mask ? (const void *)item->mask :
6466                             &rte_flow_item_mark_mask;
6467         mask = mark->id & priv->sh->dv_mark_mask;
6468         mark = (const void *)item->spec;
6469         MLX5_ASSERT(mark);
6470         value = mark->id & priv->sh->dv_mark_mask & mask;
6471         if (mask) {
6472                 enum modify_reg reg;
6473
6474                 /* Get the metadata register index for the mark. */
6475                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6476                 MLX5_ASSERT(reg > 0);
6477                 if (reg == REG_C_0) {
6478                         struct mlx5_priv *priv = dev->data->dev_private;
6479                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6480                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6481
6482                         mask &= msk_c0;
6483                         mask <<= shl_c0;
6484                         value <<= shl_c0;
6485                 }
6486                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6487         }
6488 }
6489
6490 /**
6491  * Add META item to matcher
6492  *
6493  * @param[in] dev
6494  *   The devich to configure through.
6495  * @param[in, out] matcher
6496  *   Flow matcher.
6497  * @param[in, out] key
6498  *   Flow matcher value.
6499  * @param[in] attr
6500  *   Attributes of flow that includes this item.
6501  * @param[in] item
6502  *   Flow pattern to translate.
6503  */
6504 static void
6505 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6506                             void *matcher, void *key,
6507                             const struct rte_flow_attr *attr,
6508                             const struct rte_flow_item *item)
6509 {
6510         const struct rte_flow_item_meta *meta_m;
6511         const struct rte_flow_item_meta *meta_v;
6512
6513         meta_m = (const void *)item->mask;
6514         if (!meta_m)
6515                 meta_m = &rte_flow_item_meta_mask;
6516         meta_v = (const void *)item->spec;
6517         if (meta_v) {
6518                 int reg;
6519                 uint32_t value = meta_v->data;
6520                 uint32_t mask = meta_m->data;
6521
6522                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6523                 if (reg < 0)
6524                         return;
6525                 /*
6526                  * In datapath code there is no endianness
6527                  * coversions for perfromance reasons, all
6528                  * pattern conversions are done in rte_flow.
6529                  */
6530                 value = rte_cpu_to_be_32(value);
6531                 mask = rte_cpu_to_be_32(mask);
6532                 if (reg == REG_C_0) {
6533                         struct mlx5_priv *priv = dev->data->dev_private;
6534                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6535                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6536 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6537                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6538
6539                         value >>= shr_c0;
6540                         mask >>= shr_c0;
6541 #endif
6542                         value <<= shl_c0;
6543                         mask <<= shl_c0;
6544                         MLX5_ASSERT(msk_c0);
6545                         MLX5_ASSERT(!(~msk_c0 & mask));
6546                 }
6547                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6548         }
6549 }
6550
6551 /**
6552  * Add vport metadata Reg C0 item to matcher
6553  *
6554  * @param[in, out] matcher
6555  *   Flow matcher.
6556  * @param[in, out] key
6557  *   Flow matcher value.
6558  * @param[in] reg
6559  *   Flow pattern to translate.
6560  */
6561 static void
6562 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6563                                   uint32_t value, uint32_t mask)
6564 {
6565         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6566 }
6567
6568 /**
6569  * Add tag item to matcher
6570  *
6571  * @param[in] dev
6572  *   The devich to configure through.
6573  * @param[in, out] matcher
6574  *   Flow matcher.
6575  * @param[in, out] key
6576  *   Flow matcher value.
6577  * @param[in] item
6578  *   Flow pattern to translate.
6579  */
6580 static void
6581 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6582                                 void *matcher, void *key,
6583                                 const struct rte_flow_item *item)
6584 {
6585         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6586         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6587         uint32_t mask, value;
6588
6589         MLX5_ASSERT(tag_v);
6590         value = tag_v->data;
6591         mask = tag_m ? tag_m->data : UINT32_MAX;
6592         if (tag_v->id == REG_C_0) {
6593                 struct mlx5_priv *priv = dev->data->dev_private;
6594                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6595                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6596
6597                 mask &= msk_c0;
6598                 mask <<= shl_c0;
6599                 value <<= shl_c0;
6600         }
6601         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6602 }
6603
6604 /**
6605  * Add TAG item to matcher
6606  *
6607  * @param[in] dev
6608  *   The devich to configure through.
6609  * @param[in, out] matcher
6610  *   Flow matcher.
6611  * @param[in, out] key
6612  *   Flow matcher value.
6613  * @param[in] item
6614  *   Flow pattern to translate.
6615  */
6616 static void
6617 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6618                            void *matcher, void *key,
6619                            const struct rte_flow_item *item)
6620 {
6621         const struct rte_flow_item_tag *tag_v = item->spec;
6622         const struct rte_flow_item_tag *tag_m = item->mask;
6623         enum modify_reg reg;
6624
6625         MLX5_ASSERT(tag_v);
6626         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6627         /* Get the metadata register index for the tag. */
6628         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6629         MLX5_ASSERT(reg > 0);
6630         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6631 }
6632
6633 /**
6634  * Add source vport match to the specified matcher.
6635  *
6636  * @param[in, out] matcher
6637  *   Flow matcher.
6638  * @param[in, out] key
6639  *   Flow matcher value.
6640  * @param[in] port
6641  *   Source vport value to match
6642  * @param[in] mask
6643  *   Mask
6644  */
6645 static void
6646 flow_dv_translate_item_source_vport(void *matcher, void *key,
6647                                     int16_t port, uint16_t mask)
6648 {
6649         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6650         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6651
6652         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6653         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6654 }
6655
6656 /**
6657  * Translate port-id item to eswitch match on  port-id.
6658  *
6659  * @param[in] dev
6660  *   The devich to configure through.
6661  * @param[in, out] matcher
6662  *   Flow matcher.
6663  * @param[in, out] key
6664  *   Flow matcher value.
6665  * @param[in] item
6666  *   Flow pattern to translate.
6667  *
6668  * @return
6669  *   0 on success, a negative errno value otherwise.
6670  */
6671 static int
6672 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6673                                void *key, const struct rte_flow_item *item)
6674 {
6675         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6676         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6677         struct mlx5_priv *priv;
6678         uint16_t mask, id;
6679
6680         mask = pid_m ? pid_m->id : 0xffff;
6681         id = pid_v ? pid_v->id : dev->data->port_id;
6682         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6683         if (!priv)
6684                 return -rte_errno;
6685         /* Translate to vport field or to metadata, depending on mode. */
6686         if (priv->vport_meta_mask)
6687                 flow_dv_translate_item_meta_vport(matcher, key,
6688                                                   priv->vport_meta_tag,
6689                                                   priv->vport_meta_mask);
6690         else
6691                 flow_dv_translate_item_source_vport(matcher, key,
6692                                                     priv->vport_id, mask);
6693         return 0;
6694 }
6695
6696 /**
6697  * Add ICMP6 item to matcher and to the value.
6698  *
6699  * @param[in, out] matcher
6700  *   Flow matcher.
6701  * @param[in, out] key
6702  *   Flow matcher value.
6703  * @param[in] item
6704  *   Flow pattern to translate.
6705  * @param[in] inner
6706  *   Item is inner pattern.
6707  */
6708 static void
6709 flow_dv_translate_item_icmp6(void *matcher, void *key,
6710                               const struct rte_flow_item *item,
6711                               int inner)
6712 {
6713         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6714         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6715         void *headers_m;
6716         void *headers_v;
6717         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6718                                      misc_parameters_3);
6719         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6720         if (inner) {
6721                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6722                                          inner_headers);
6723                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6724         } else {
6725                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6726                                          outer_headers);
6727                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6728         }
6729         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6731         if (!icmp6_v)
6732                 return;
6733         if (!icmp6_m)
6734                 icmp6_m = &rte_flow_item_icmp6_mask;
6735         /*
6736          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6737          * If only the protocol is specified, no need to match the frag.
6738          */
6739         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6740         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6741         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6742         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6743                  icmp6_v->type & icmp6_m->type);
6744         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6745         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6746                  icmp6_v->code & icmp6_m->code);
6747 }
6748
6749 /**
6750  * Add ICMP item to matcher and to the value.
6751  *
6752  * @param[in, out] matcher
6753  *   Flow matcher.
6754  * @param[in, out] key
6755  *   Flow matcher value.
6756  * @param[in] item
6757  *   Flow pattern to translate.
6758  * @param[in] inner
6759  *   Item is inner pattern.
6760  */
6761 static void
6762 flow_dv_translate_item_icmp(void *matcher, void *key,
6763                             const struct rte_flow_item *item,
6764                             int inner)
6765 {
6766         const struct rte_flow_item_icmp *icmp_m = item->mask;
6767         const struct rte_flow_item_icmp *icmp_v = item->spec;
6768         void *headers_m;
6769         void *headers_v;
6770         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6771                                      misc_parameters_3);
6772         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6773         if (inner) {
6774                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6775                                          inner_headers);
6776                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6777         } else {
6778                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6779                                          outer_headers);
6780                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6781         }
6782         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6783         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6784         if (!icmp_v)
6785                 return;
6786         if (!icmp_m)
6787                 icmp_m = &rte_flow_item_icmp_mask;
6788         /*
6789          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6790          * If only the protocol is specified, no need to match the frag.
6791          */
6792         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6793         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6794         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6795                  icmp_m->hdr.icmp_type);
6796         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6797                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6798         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6799                  icmp_m->hdr.icmp_code);
6800         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6801                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6802 }
6803
6804 /**
6805  * Add GTP item to matcher and to the value.
6806  *
6807  * @param[in, out] matcher
6808  *   Flow matcher.
6809  * @param[in, out] key
6810  *   Flow matcher value.
6811  * @param[in] item
6812  *   Flow pattern to translate.
6813  * @param[in] inner
6814  *   Item is inner pattern.
6815  */
6816 static void
6817 flow_dv_translate_item_gtp(void *matcher, void *key,
6818                            const struct rte_flow_item *item, int inner)
6819 {
6820         const struct rte_flow_item_gtp *gtp_m = item->mask;
6821         const struct rte_flow_item_gtp *gtp_v = item->spec;
6822         void *headers_m;
6823         void *headers_v;
6824         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6825                                      misc_parameters_3);
6826         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6827         uint16_t dport = RTE_GTPU_UDP_PORT;
6828
6829         if (inner) {
6830                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6831                                          inner_headers);
6832                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6833         } else {
6834                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6835                                          outer_headers);
6836                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6837         }
6838         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6839                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6840                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6841         }
6842         if (!gtp_v)
6843                 return;
6844         if (!gtp_m)
6845                 gtp_m = &rte_flow_item_gtp_mask;
6846         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6847         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6848                  gtp_v->msg_type & gtp_m->msg_type);
6849         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6850                  rte_be_to_cpu_32(gtp_m->teid));
6851         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6852                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6853 }
6854
6855 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6856
6857 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6858         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6859                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6860
6861 /**
6862  * Calculate flow matcher enable bitmap.
6863  *
6864  * @param match_criteria
6865  *   Pointer to flow matcher criteria.
6866  *
6867  * @return
6868  *   Bitmap of enabled fields.
6869  */
6870 static uint8_t
6871 flow_dv_matcher_enable(uint32_t *match_criteria)
6872 {
6873         uint8_t match_criteria_enable;
6874
6875         match_criteria_enable =
6876                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6877                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6878         match_criteria_enable |=
6879                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6880                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6881         match_criteria_enable |=
6882                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6883                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6884         match_criteria_enable |=
6885                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6886                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6887         match_criteria_enable |=
6888                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6889                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6890         return match_criteria_enable;
6891 }
6892
6893
6894 /**
6895  * Get a flow table.
6896  *
6897  * @param[in, out] dev
6898  *   Pointer to rte_eth_dev structure.
6899  * @param[in] table_id
6900  *   Table id to use.
6901  * @param[in] egress
6902  *   Direction of the table.
6903  * @param[in] transfer
6904  *   E-Switch or NIC flow.
6905  * @param[out] error
6906  *   pointer to error structure.
6907  *
6908  * @return
6909  *   Returns tables resource based on the index, NULL in case of failed.
6910  */
6911 static struct mlx5_flow_tbl_resource *
6912 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6913                          uint32_t table_id, uint8_t egress,
6914                          uint8_t transfer,
6915                          struct rte_flow_error *error)
6916 {
6917         struct mlx5_priv *priv = dev->data->dev_private;
6918         struct mlx5_ibv_shared *sh = priv->sh;
6919         struct mlx5_flow_tbl_resource *tbl;
6920         union mlx5_flow_tbl_key table_key = {
6921                 {
6922                         .table_id = table_id,
6923                         .reserved = 0,
6924                         .domain = !!transfer,
6925                         .direction = !!egress,
6926                 }
6927         };
6928         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6929                                                          table_key.v64);
6930         struct mlx5_flow_tbl_data_entry *tbl_data;
6931         uint32_t idx = 0;
6932         int ret;
6933         void *domain;
6934
6935         if (pos) {
6936                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6937                                         entry);
6938                 tbl = &tbl_data->tbl;
6939                 rte_atomic32_inc(&tbl->refcnt);
6940                 return tbl;
6941         }
6942         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
6943         if (!tbl_data) {
6944                 rte_flow_error_set(error, ENOMEM,
6945                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6946                                    NULL,
6947                                    "cannot allocate flow table data entry");
6948                 return NULL;
6949         }
6950         tbl_data->idx = idx;
6951         tbl = &tbl_data->tbl;
6952         pos = &tbl_data->entry;
6953         if (transfer)
6954                 domain = sh->fdb_domain;
6955         else if (egress)
6956                 domain = sh->tx_domain;
6957         else
6958                 domain = sh->rx_domain;
6959         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6960         if (!tbl->obj) {
6961                 rte_flow_error_set(error, ENOMEM,
6962                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6963                                    NULL, "cannot create flow table object");
6964                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6965                 return NULL;
6966         }
6967         /*
6968          * No multi-threads now, but still better to initialize the reference
6969          * count before insert it into the hash list.
6970          */
6971         rte_atomic32_init(&tbl->refcnt);
6972         /* Jump action reference count is initialized here. */
6973         rte_atomic32_init(&tbl_data->jump.refcnt);
6974         pos->key = table_key.v64;
6975         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6976         if (ret < 0) {
6977                 rte_flow_error_set(error, -ret,
6978                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6979                                    "cannot insert flow table data entry");
6980                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6981                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6982         }
6983         rte_atomic32_inc(&tbl->refcnt);
6984         return tbl;
6985 }
6986
6987 /**
6988  * Release a flow table.
6989  *
6990  * @param[in] dev
6991  *   Pointer to rte_eth_dev structure.
6992  * @param[in] tbl
6993  *   Table resource to be released.
6994  *
6995  * @return
6996  *   Returns 0 if table was released, else return 1;
6997  */
6998 static int
6999 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7000                              struct mlx5_flow_tbl_resource *tbl)
7001 {
7002         struct mlx5_priv *priv = dev->data->dev_private;
7003         struct mlx5_ibv_shared *sh = priv->sh;
7004         struct mlx5_flow_tbl_data_entry *tbl_data =
7005                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7006
7007         if (!tbl)
7008                 return 0;
7009         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7010                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7011
7012                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7013                 tbl->obj = NULL;
7014                 /* remove the entry from the hash list and free memory. */
7015                 mlx5_hlist_remove(sh->flow_tbls, pos);
7016                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7017                                 tbl_data->idx);
7018                 return 0;
7019         }
7020         return 1;
7021 }
7022
7023 /**
7024  * Register the flow matcher.
7025  *
7026  * @param[in, out] dev
7027  *   Pointer to rte_eth_dev structure.
7028  * @param[in, out] matcher
7029  *   Pointer to flow matcher.
7030  * @param[in, out] key
7031  *   Pointer to flow table key.
7032  * @parm[in, out] dev_flow
7033  *   Pointer to the dev_flow.
7034  * @param[out] error
7035  *   pointer to error structure.
7036  *
7037  * @return
7038  *   0 on success otherwise -errno and errno is set.
7039  */
7040 static int
7041 flow_dv_matcher_register(struct rte_eth_dev *dev,
7042                          struct mlx5_flow_dv_matcher *matcher,
7043                          union mlx5_flow_tbl_key *key,
7044                          struct mlx5_flow *dev_flow,
7045                          struct rte_flow_error *error)
7046 {
7047         struct mlx5_priv *priv = dev->data->dev_private;
7048         struct mlx5_ibv_shared *sh = priv->sh;
7049         struct mlx5_flow_dv_matcher *cache_matcher;
7050         struct mlx5dv_flow_matcher_attr dv_attr = {
7051                 .type = IBV_FLOW_ATTR_NORMAL,
7052                 .match_mask = (void *)&matcher->mask,
7053         };
7054         struct mlx5_flow_tbl_resource *tbl;
7055         struct mlx5_flow_tbl_data_entry *tbl_data;
7056
7057         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7058                                        key->domain, error);
7059         if (!tbl)
7060                 return -rte_errno;      /* No need to refill the error info */
7061         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7062         /* Lookup from cache. */
7063         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7064                 if (matcher->crc == cache_matcher->crc &&
7065                     matcher->priority == cache_matcher->priority &&
7066                     !memcmp((const void *)matcher->mask.buf,
7067                             (const void *)cache_matcher->mask.buf,
7068                             cache_matcher->mask.size)) {
7069                         DRV_LOG(DEBUG,
7070                                 "%s group %u priority %hd use %s "
7071                                 "matcher %p: refcnt %d++",
7072                                 key->domain ? "FDB" : "NIC", key->table_id,
7073                                 cache_matcher->priority,
7074                                 key->direction ? "tx" : "rx",
7075                                 (void *)cache_matcher,
7076                                 rte_atomic32_read(&cache_matcher->refcnt));
7077                         rte_atomic32_inc(&cache_matcher->refcnt);
7078                         dev_flow->handle->dvh.matcher = cache_matcher;
7079                         /* old matcher should not make the table ref++. */
7080                         flow_dv_tbl_resource_release(dev, tbl);
7081                         return 0;
7082                 }
7083         }
7084         /* Register new matcher. */
7085         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7086         if (!cache_matcher) {
7087                 flow_dv_tbl_resource_release(dev, tbl);
7088                 return rte_flow_error_set(error, ENOMEM,
7089                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7090                                           "cannot allocate matcher memory");
7091         }
7092         *cache_matcher = *matcher;
7093         dv_attr.match_criteria_enable =
7094                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7095         dv_attr.priority = matcher->priority;
7096         if (key->direction)
7097                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7098         cache_matcher->matcher_object =
7099                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7100         if (!cache_matcher->matcher_object) {
7101                 rte_free(cache_matcher);
7102 #ifdef HAVE_MLX5DV_DR
7103                 flow_dv_tbl_resource_release(dev, tbl);
7104 #endif
7105                 return rte_flow_error_set(error, ENOMEM,
7106                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7107                                           NULL, "cannot create matcher");
7108         }
7109         /* Save the table information */
7110         cache_matcher->tbl = tbl;
7111         rte_atomic32_init(&cache_matcher->refcnt);
7112         /* only matcher ref++, table ref++ already done above in get API. */
7113         rte_atomic32_inc(&cache_matcher->refcnt);
7114         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7115         dev_flow->handle->dvh.matcher = cache_matcher;
7116         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7117                 key->domain ? "FDB" : "NIC", key->table_id,
7118                 cache_matcher->priority,
7119                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7120                 rte_atomic32_read(&cache_matcher->refcnt));
7121         return 0;
7122 }
7123
7124 /**
7125  * Find existing tag resource or create and register a new one.
7126  *
7127  * @param dev[in, out]
7128  *   Pointer to rte_eth_dev structure.
7129  * @param[in, out] tag_be24
7130  *   Tag value in big endian then R-shift 8.
7131  * @parm[in, out] dev_flow
7132  *   Pointer to the dev_flow.
7133  * @param[out] error
7134  *   pointer to error structure.
7135  *
7136  * @return
7137  *   0 on success otherwise -errno and errno is set.
7138  */
7139 static int
7140 flow_dv_tag_resource_register
7141                         (struct rte_eth_dev *dev,
7142                          uint32_t tag_be24,
7143                          struct mlx5_flow *dev_flow,
7144                          struct rte_flow_error *error)
7145 {
7146         struct mlx5_priv *priv = dev->data->dev_private;
7147         struct mlx5_ibv_shared *sh = priv->sh;
7148         struct mlx5_flow_dv_tag_resource *cache_resource;
7149         struct mlx5_hlist_entry *entry;
7150
7151         /* Lookup a matching resource from cache. */
7152         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7153         if (entry) {
7154                 cache_resource = container_of
7155                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7156                 rte_atomic32_inc(&cache_resource->refcnt);
7157                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7158                 dev_flow->dv.tag_resource = cache_resource;
7159                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7160                         (void *)cache_resource,
7161                         rte_atomic32_read(&cache_resource->refcnt));
7162                 return 0;
7163         }
7164         /* Register new resource. */
7165         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7166                                        &dev_flow->handle->dvh.rix_tag);
7167         if (!cache_resource)
7168                 return rte_flow_error_set(error, ENOMEM,
7169                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7170                                           "cannot allocate resource memory");
7171         cache_resource->entry.key = (uint64_t)tag_be24;
7172         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7173         if (!cache_resource->action) {
7174                 rte_free(cache_resource);
7175                 return rte_flow_error_set(error, ENOMEM,
7176                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7177                                           NULL, "cannot create action");
7178         }
7179         rte_atomic32_init(&cache_resource->refcnt);
7180         rte_atomic32_inc(&cache_resource->refcnt);
7181         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7182                 mlx5_glue->destroy_flow_action(cache_resource->action);
7183                 rte_free(cache_resource);
7184                 return rte_flow_error_set(error, EEXIST,
7185                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7186                                           NULL, "cannot insert tag");
7187         }
7188         dev_flow->dv.tag_resource = cache_resource;
7189         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7190                 (void *)cache_resource,
7191                 rte_atomic32_read(&cache_resource->refcnt));
7192         return 0;
7193 }
7194
7195 /**
7196  * Release the tag.
7197  *
7198  * @param dev
7199  *   Pointer to Ethernet device.
7200  * @param tag_idx
7201  *   Tag index.
7202  *
7203  * @return
7204  *   1 while a reference on it exists, 0 when freed.
7205  */
7206 static int
7207 flow_dv_tag_release(struct rte_eth_dev *dev,
7208                     uint32_t tag_idx)
7209 {
7210         struct mlx5_priv *priv = dev->data->dev_private;
7211         struct mlx5_ibv_shared *sh = priv->sh;
7212         struct mlx5_flow_dv_tag_resource *tag;
7213
7214         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7215         if (!tag)
7216                 return 0;
7217         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7218                 dev->data->port_id, (void *)tag,
7219                 rte_atomic32_read(&tag->refcnt));
7220         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7221                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7222                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7223                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7224                         dev->data->port_id, (void *)tag);
7225                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7226                 return 0;
7227         }
7228         return 1;
7229 }
7230
7231 /**
7232  * Translate port ID action to vport.
7233  *
7234  * @param[in] dev
7235  *   Pointer to rte_eth_dev structure.
7236  * @param[in] action
7237  *   Pointer to the port ID action.
7238  * @param[out] dst_port_id
7239  *   The target port ID.
7240  * @param[out] error
7241  *   Pointer to the error structure.
7242  *
7243  * @return
7244  *   0 on success, a negative errno value otherwise and rte_errno is set.
7245  */
7246 static int
7247 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7248                                  const struct rte_flow_action *action,
7249                                  uint32_t *dst_port_id,
7250                                  struct rte_flow_error *error)
7251 {
7252         uint32_t port;
7253         struct mlx5_priv *priv;
7254         const struct rte_flow_action_port_id *conf =
7255                         (const struct rte_flow_action_port_id *)action->conf;
7256
7257         port = conf->original ? dev->data->port_id : conf->id;
7258         priv = mlx5_port_to_eswitch_info(port, false);
7259         if (!priv)
7260                 return rte_flow_error_set(error, -rte_errno,
7261                                           RTE_FLOW_ERROR_TYPE_ACTION,
7262                                           NULL,
7263                                           "No eswitch info was found for port");
7264 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7265         /*
7266          * This parameter is transferred to
7267          * mlx5dv_dr_action_create_dest_ib_port().
7268          */
7269         *dst_port_id = priv->ibv_port;
7270 #else
7271         /*
7272          * Legacy mode, no LAG configurations is supported.
7273          * This parameter is transferred to
7274          * mlx5dv_dr_action_create_dest_vport().
7275          */
7276         *dst_port_id = priv->vport_id;
7277 #endif
7278         return 0;
7279 }
7280
7281 /**
7282  * Add Tx queue matcher
7283  *
7284  * @param[in] dev
7285  *   Pointer to the dev struct.
7286  * @param[in, out] matcher
7287  *   Flow matcher.
7288  * @param[in, out] key
7289  *   Flow matcher value.
7290  * @param[in] item
7291  *   Flow pattern to translate.
7292  * @param[in] inner
7293  *   Item is inner pattern.
7294  */
7295 static void
7296 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7297                                 void *matcher, void *key,
7298                                 const struct rte_flow_item *item)
7299 {
7300         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7301         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7302         void *misc_m =
7303                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7304         void *misc_v =
7305                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7306         struct mlx5_txq_ctrl *txq;
7307         uint32_t queue;
7308
7309
7310         queue_m = (const void *)item->mask;
7311         if (!queue_m)
7312                 return;
7313         queue_v = (const void *)item->spec;
7314         if (!queue_v)
7315                 return;
7316         txq = mlx5_txq_get(dev, queue_v->queue);
7317         if (!txq)
7318                 return;
7319         queue = txq->obj->sq->id;
7320         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7321         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7322                  queue & queue_m->queue);
7323         mlx5_txq_release(dev, queue_v->queue);
7324 }
7325
7326 /**
7327  * Set the hash fields according to the @p flow information.
7328  *
7329  * @param[in] dev_flow
7330  *   Pointer to the mlx5_flow.
7331  * @param[in] rss_desc
7332  *   Pointer to the mlx5_flow_rss_desc.
7333  */
7334 static void
7335 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7336                        struct mlx5_flow_rss_desc *rss_desc)
7337 {
7338         uint64_t items = dev_flow->handle->layers;
7339         int rss_inner = 0;
7340         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7341
7342         dev_flow->hash_fields = 0;
7343 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7344         if (rss_desc->level >= 2) {
7345                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7346                 rss_inner = 1;
7347         }
7348 #endif
7349         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7350             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7351                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7352                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7353                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7354                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7355                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7356                         else
7357                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7358                 }
7359         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7360                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7361                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7362                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7363                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7364                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7365                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7366                         else
7367                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7368                 }
7369         }
7370         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7371             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7372                 if (rss_types & ETH_RSS_UDP) {
7373                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7374                                 dev_flow->hash_fields |=
7375                                                 IBV_RX_HASH_SRC_PORT_UDP;
7376                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7377                                 dev_flow->hash_fields |=
7378                                                 IBV_RX_HASH_DST_PORT_UDP;
7379                         else
7380                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7381                 }
7382         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7383                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7384                 if (rss_types & ETH_RSS_TCP) {
7385                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7386                                 dev_flow->hash_fields |=
7387                                                 IBV_RX_HASH_SRC_PORT_TCP;
7388                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7389                                 dev_flow->hash_fields |=
7390                                                 IBV_RX_HASH_DST_PORT_TCP;
7391                         else
7392                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7393                 }
7394         }
7395 }
7396
7397 /**
7398  * Fill the flow with DV spec, lock free
7399  * (mutex should be acquired by caller).
7400  *
7401  * @param[in] dev
7402  *   Pointer to rte_eth_dev structure.
7403  * @param[in, out] dev_flow
7404  *   Pointer to the sub flow.
7405  * @param[in] attr
7406  *   Pointer to the flow attributes.
7407  * @param[in] items
7408  *   Pointer to the list of items.
7409  * @param[in] actions
7410  *   Pointer to the list of actions.
7411  * @param[out] error
7412  *   Pointer to the error structure.
7413  *
7414  * @return
7415  *   0 on success, a negative errno value otherwise and rte_errno is set.
7416  */
7417 static int
7418 __flow_dv_translate(struct rte_eth_dev *dev,
7419                     struct mlx5_flow *dev_flow,
7420                     const struct rte_flow_attr *attr,
7421                     const struct rte_flow_item items[],
7422                     const struct rte_flow_action actions[],
7423                     struct rte_flow_error *error)
7424 {
7425         struct mlx5_priv *priv = dev->data->dev_private;
7426         struct mlx5_dev_config *dev_conf = &priv->config;
7427         struct rte_flow *flow = dev_flow->flow;
7428         struct mlx5_flow_handle *handle = dev_flow->handle;
7429         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7430                                               priv->rss_desc)
7431                                               [!!priv->flow_nested_idx];
7432         uint64_t item_flags = 0;
7433         uint64_t last_item = 0;
7434         uint64_t action_flags = 0;
7435         uint64_t priority = attr->priority;
7436         struct mlx5_flow_dv_matcher matcher = {
7437                 .mask = {
7438                         .size = sizeof(matcher.mask.buf),
7439                 },
7440         };
7441         int actions_n = 0;
7442         bool actions_end = false;
7443         union {
7444                 struct mlx5_flow_dv_modify_hdr_resource res;
7445                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7446                             sizeof(struct mlx5_modification_cmd) *
7447                             (MLX5_MAX_MODIFY_NUM + 1)];
7448         } mhdr_dummy;
7449         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7450         union flow_dv_attr flow_attr = { .attr = 0 };
7451         uint32_t tag_be;
7452         union mlx5_flow_tbl_key tbl_key;
7453         uint32_t modify_action_position = UINT32_MAX;
7454         void *match_mask = matcher.mask.buf;
7455         void *match_value = dev_flow->dv.value.buf;
7456         uint8_t next_protocol = 0xff;
7457         struct rte_vlan_hdr vlan = { 0 };
7458         uint32_t table;
7459         int ret = 0;
7460
7461         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7462                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7463         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7464                                        !!priv->fdb_def_rule, &table, error);
7465         if (ret)
7466                 return ret;
7467         dev_flow->dv.group = table;
7468         if (attr->transfer)
7469                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7470         if (priority == MLX5_FLOW_PRIO_RSVD)
7471                 priority = dev_conf->flow_prio - 1;
7472         /* number of actions must be set to 0 in case of dirty stack. */
7473         mhdr_res->actions_num = 0;
7474         for (; !actions_end ; actions++) {
7475                 const struct rte_flow_action_queue *queue;
7476                 const struct rte_flow_action_rss *rss;
7477                 const struct rte_flow_action *action = actions;
7478                 const struct rte_flow_action_count *count = action->conf;
7479                 const uint8_t *rss_key;
7480                 const struct rte_flow_action_jump *jump_data;
7481                 const struct rte_flow_action_meter *mtr;
7482                 struct mlx5_flow_tbl_resource *tbl;
7483                 uint32_t port_id = 0;
7484                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7485                 int action_type = actions->type;
7486                 const struct rte_flow_action *found_action = NULL;
7487                 struct mlx5_flow_meter *fm = NULL;
7488
7489                 switch (action_type) {
7490                 case RTE_FLOW_ACTION_TYPE_VOID:
7491                         break;
7492                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7493                         if (flow_dv_translate_action_port_id(dev, action,
7494                                                              &port_id, error))
7495                                 return -rte_errno;
7496                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7497                         port_id_resource.port_id = port_id;
7498                         if (flow_dv_port_id_action_resource_register
7499                             (dev, &port_id_resource, dev_flow, error))
7500                                 return -rte_errno;
7501                         MLX5_ASSERT(!handle->rix_port_id_action);
7502                         dev_flow->dv.actions[actions_n++] =
7503                                         dev_flow->dv.port_id_action->action;
7504                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7505                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7506                         break;
7507                 case RTE_FLOW_ACTION_TYPE_FLAG:
7508                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7509                         dev_flow->handle->mark = 1;
7510                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7511                                 struct rte_flow_action_mark mark = {
7512                                         .id = MLX5_FLOW_MARK_DEFAULT,
7513                                 };
7514
7515                                 if (flow_dv_convert_action_mark(dev, &mark,
7516                                                                 mhdr_res,
7517                                                                 error))
7518                                         return -rte_errno;
7519                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7520                                 break;
7521                         }
7522                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7523                         /*
7524                          * Only one FLAG or MARK is supported per device flow
7525                          * right now. So the pointer to the tag resource must be
7526                          * zero before the register process.
7527                          */
7528                         MLX5_ASSERT(!handle->dvh.rix_tag);
7529                         if (flow_dv_tag_resource_register(dev, tag_be,
7530                                                           dev_flow, error))
7531                                 return -rte_errno;
7532                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7533                         dev_flow->dv.actions[actions_n++] =
7534                                         dev_flow->dv.tag_resource->action;
7535                         break;
7536                 case RTE_FLOW_ACTION_TYPE_MARK:
7537                         action_flags |= MLX5_FLOW_ACTION_MARK;
7538                         dev_flow->handle->mark = 1;
7539                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7540                                 const struct rte_flow_action_mark *mark =
7541                                         (const struct rte_flow_action_mark *)
7542                                                 actions->conf;
7543
7544                                 if (flow_dv_convert_action_mark(dev, mark,
7545                                                                 mhdr_res,
7546                                                                 error))
7547                                         return -rte_errno;
7548                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7549                                 break;
7550                         }
7551                         /* Fall-through */
7552                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7553                         /* Legacy (non-extensive) MARK action. */
7554                         tag_be = mlx5_flow_mark_set
7555                               (((const struct rte_flow_action_mark *)
7556                                (actions->conf))->id);
7557                         MLX5_ASSERT(!handle->dvh.rix_tag);
7558                         if (flow_dv_tag_resource_register(dev, tag_be,
7559                                                           dev_flow, error))
7560                                 return -rte_errno;
7561                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7562                         dev_flow->dv.actions[actions_n++] =
7563                                         dev_flow->dv.tag_resource->action;
7564                         break;
7565                 case RTE_FLOW_ACTION_TYPE_SET_META:
7566                         if (flow_dv_convert_action_set_meta
7567                                 (dev, mhdr_res, attr,
7568                                  (const struct rte_flow_action_set_meta *)
7569                                   actions->conf, error))
7570                                 return -rte_errno;
7571                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7572                         break;
7573                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7574                         if (flow_dv_convert_action_set_tag
7575                                 (dev, mhdr_res,
7576                                  (const struct rte_flow_action_set_tag *)
7577                                   actions->conf, error))
7578                                 return -rte_errno;
7579                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7580                         break;
7581                 case RTE_FLOW_ACTION_TYPE_DROP:
7582                         action_flags |= MLX5_FLOW_ACTION_DROP;
7583                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7584                         break;
7585                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7586                         queue = actions->conf;
7587                         rss_desc->queue_num = 1;
7588                         rss_desc->queue[0] = queue->index;
7589                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7590                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7591                         break;
7592                 case RTE_FLOW_ACTION_TYPE_RSS:
7593                         rss = actions->conf;
7594                         memcpy(rss_desc->queue, rss->queue,
7595                                rss->queue_num * sizeof(uint16_t));
7596                         rss_desc->queue_num = rss->queue_num;
7597                         /* NULL RSS key indicates default RSS key. */
7598                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7599                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7600                         /*
7601                          * rss->level and rss.types should be set in advance
7602                          * when expanding items for RSS.
7603                          */
7604                         action_flags |= MLX5_FLOW_ACTION_RSS;
7605                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7606                         break;
7607                 case RTE_FLOW_ACTION_TYPE_COUNT:
7608                         if (!dev_conf->devx) {
7609                                 rte_errno = ENOTSUP;
7610                                 goto cnt_err;
7611                         }
7612                         flow->counter = flow_dv_counter_alloc(dev,
7613                                                         count->shared,
7614                                                         count->id,
7615                                                         dev_flow->dv.group);
7616                         if (!flow->counter)
7617                                 goto cnt_err;
7618                         dev_flow->dv.actions[actions_n++] =
7619                                   (flow_dv_counter_get_by_idx(dev,
7620                                   flow->counter, NULL))->action;
7621                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7622                         break;
7623 cnt_err:
7624                         if (rte_errno == ENOTSUP)
7625                                 return rte_flow_error_set
7626                                               (error, ENOTSUP,
7627                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7628                                                NULL,
7629                                                "count action not supported");
7630                         else
7631                                 return rte_flow_error_set
7632                                                 (error, rte_errno,
7633                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7634                                                  action,
7635                                                  "cannot create counter"
7636                                                   " object.");
7637                         break;
7638                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7639                         dev_flow->dv.actions[actions_n++] =
7640                                                 priv->sh->pop_vlan_action;
7641                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7642                         break;
7643                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7644                         if (!(action_flags &
7645                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7646                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7647                         vlan.eth_proto = rte_be_to_cpu_16
7648                              ((((const struct rte_flow_action_of_push_vlan *)
7649                                                    actions->conf)->ethertype));
7650                         found_action = mlx5_flow_find_action
7651                                         (actions + 1,
7652                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7653                         if (found_action)
7654                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7655                         found_action = mlx5_flow_find_action
7656                                         (actions + 1,
7657                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7658                         if (found_action)
7659                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7660                         if (flow_dv_create_action_push_vlan
7661                                             (dev, attr, &vlan, dev_flow, error))
7662                                 return -rte_errno;
7663                         dev_flow->dv.actions[actions_n++] =
7664                                         dev_flow->dv.push_vlan_res->action;
7665                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7666                         break;
7667                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7668                         /* of_vlan_push action handled this action */
7669                         MLX5_ASSERT(action_flags &
7670                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7671                         break;
7672                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7673                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7674                                 break;
7675                         flow_dev_get_vlan_info_from_items(items, &vlan);
7676                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7677                         /* If no VLAN push - this is a modify header action */
7678                         if (flow_dv_convert_action_modify_vlan_vid
7679                                                 (mhdr_res, actions, error))
7680                                 return -rte_errno;
7681                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7682                         break;
7683                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7684                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7685                         if (flow_dv_create_action_l2_encap(dev, actions,
7686                                                            dev_flow,
7687                                                            attr->transfer,
7688                                                            error))
7689                                 return -rte_errno;
7690                         dev_flow->dv.actions[actions_n++] =
7691                                         dev_flow->dv.encap_decap->verbs_action;
7692                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7693                         break;
7694                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7695                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7696                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7697                                                            attr->transfer,
7698                                                            error))
7699                                 return -rte_errno;
7700                         dev_flow->dv.actions[actions_n++] =
7701                                         dev_flow->dv.encap_decap->verbs_action;
7702                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7703                         break;
7704                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7705                         /* Handle encap with preceding decap. */
7706                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7707                                 if (flow_dv_create_action_raw_encap
7708                                         (dev, actions, dev_flow, attr, error))
7709                                         return -rte_errno;
7710                                 dev_flow->dv.actions[actions_n++] =
7711                                         dev_flow->dv.encap_decap->verbs_action;
7712                         } else {
7713                                 /* Handle encap without preceding decap. */
7714                                 if (flow_dv_create_action_l2_encap
7715                                     (dev, actions, dev_flow, attr->transfer,
7716                                      error))
7717                                         return -rte_errno;
7718                                 dev_flow->dv.actions[actions_n++] =
7719                                         dev_flow->dv.encap_decap->verbs_action;
7720                         }
7721                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7722                         break;
7723                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7724                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7725                                 ;
7726                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7727                                 if (flow_dv_create_action_l2_decap
7728                                     (dev, dev_flow, attr->transfer, error))
7729                                         return -rte_errno;
7730                                 dev_flow->dv.actions[actions_n++] =
7731                                         dev_flow->dv.encap_decap->verbs_action;
7732                         }
7733                         /* If decap is followed by encap, handle it at encap. */
7734                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7735                         break;
7736                 case RTE_FLOW_ACTION_TYPE_JUMP:
7737                         jump_data = action->conf;
7738                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7739                                                        jump_data->group,
7740                                                        !!priv->fdb_def_rule,
7741                                                        &table, error);
7742                         if (ret)
7743                                 return ret;
7744                         tbl = flow_dv_tbl_resource_get(dev, table,
7745                                                        attr->egress,
7746                                                        attr->transfer, error);
7747                         if (!tbl)
7748                                 return rte_flow_error_set
7749                                                 (error, errno,
7750                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7751                                                  NULL,
7752                                                  "cannot create jump action.");
7753                         if (flow_dv_jump_tbl_resource_register
7754                             (dev, tbl, dev_flow, error)) {
7755                                 flow_dv_tbl_resource_release(dev, tbl);
7756                                 return rte_flow_error_set
7757                                                 (error, errno,
7758                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7759                                                  NULL,
7760                                                  "cannot create jump action.");
7761                         }
7762                         dev_flow->dv.actions[actions_n++] =
7763                                         dev_flow->dv.jump->action;
7764                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7765                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
7766                         break;
7767                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7768                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7769                         if (flow_dv_convert_action_modify_mac
7770                                         (mhdr_res, actions, error))
7771                                 return -rte_errno;
7772                         action_flags |= actions->type ==
7773                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7774                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7775                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7776                         break;
7777                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7778                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7779                         if (flow_dv_convert_action_modify_ipv4
7780                                         (mhdr_res, actions, error))
7781                                 return -rte_errno;
7782                         action_flags |= actions->type ==
7783                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7784                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7785                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7786                         break;
7787                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7788                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7789                         if (flow_dv_convert_action_modify_ipv6
7790                                         (mhdr_res, actions, error))
7791                                 return -rte_errno;
7792                         action_flags |= actions->type ==
7793                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7794                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7795                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7796                         break;
7797                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7798                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7799                         if (flow_dv_convert_action_modify_tp
7800                                         (mhdr_res, actions, items,
7801                                          &flow_attr, dev_flow, !!(action_flags &
7802                                          MLX5_FLOW_ACTION_DECAP), error))
7803                                 return -rte_errno;
7804                         action_flags |= actions->type ==
7805                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7806                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7807                                         MLX5_FLOW_ACTION_SET_TP_DST;
7808                         break;
7809                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7810                         if (flow_dv_convert_action_modify_dec_ttl
7811                                         (mhdr_res, items, &flow_attr, dev_flow,
7812                                          !!(action_flags &
7813                                          MLX5_FLOW_ACTION_DECAP), error))
7814                                 return -rte_errno;
7815                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7816                         break;
7817                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7818                         if (flow_dv_convert_action_modify_ttl
7819                                         (mhdr_res, actions, items, &flow_attr,
7820                                          dev_flow, !!(action_flags &
7821                                          MLX5_FLOW_ACTION_DECAP), error))
7822                                 return -rte_errno;
7823                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7824                         break;
7825                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7826                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7827                         if (flow_dv_convert_action_modify_tcp_seq
7828                                         (mhdr_res, actions, error))
7829                                 return -rte_errno;
7830                         action_flags |= actions->type ==
7831                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7832                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7833                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7834                         break;
7835
7836                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7837                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7838                         if (flow_dv_convert_action_modify_tcp_ack
7839                                         (mhdr_res, actions, error))
7840                                 return -rte_errno;
7841                         action_flags |= actions->type ==
7842                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7843                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7844                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7845                         break;
7846                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7847                         if (flow_dv_convert_action_set_reg
7848                                         (mhdr_res, actions, error))
7849                                 return -rte_errno;
7850                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7851                         break;
7852                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7853                         if (flow_dv_convert_action_copy_mreg
7854                                         (dev, mhdr_res, actions, error))
7855                                 return -rte_errno;
7856                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7857                         break;
7858                 case RTE_FLOW_ACTION_TYPE_METER:
7859                         mtr = actions->conf;
7860                         if (!flow->meter) {
7861                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
7862                                                             attr, error);
7863                                 if (!fm)
7864                                         return rte_flow_error_set(error,
7865                                                 rte_errno,
7866                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7867                                                 NULL,
7868                                                 "meter not found "
7869                                                 "or invalid parameters");
7870                                 flow->meter = fm->idx;
7871                         }
7872                         /* Set the meter action. */
7873                         if (!fm) {
7874                                 fm = mlx5_ipool_get(priv->sh->ipool
7875                                                 [MLX5_IPOOL_MTR], flow->meter);
7876                                 if (!fm)
7877                                         return rte_flow_error_set(error,
7878                                                 rte_errno,
7879                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7880                                                 NULL,
7881                                                 "meter not found "
7882                                                 "or invalid parameters");
7883                         }
7884                         dev_flow->dv.actions[actions_n++] =
7885                                 fm->mfts->meter_action;
7886                         action_flags |= MLX5_FLOW_ACTION_METER;
7887                         break;
7888                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7889                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7890                                                               actions, error))
7891                                 return -rte_errno;
7892                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7893                         break;
7894                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7895                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7896                                                               actions, error))
7897                                 return -rte_errno;
7898                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7899                         break;
7900                 case RTE_FLOW_ACTION_TYPE_END:
7901                         actions_end = true;
7902                         if (mhdr_res->actions_num) {
7903                                 /* create modify action if needed. */
7904                                 if (flow_dv_modify_hdr_resource_register
7905                                         (dev, mhdr_res, dev_flow, error))
7906                                         return -rte_errno;
7907                                 dev_flow->dv.actions[modify_action_position] =
7908                                         handle->dvh.modify_hdr->verbs_action;
7909                         }
7910                         break;
7911                 default:
7912                         break;
7913                 }
7914                 if (mhdr_res->actions_num &&
7915                     modify_action_position == UINT32_MAX)
7916                         modify_action_position = actions_n++;
7917         }
7918         dev_flow->dv.actions_n = actions_n;
7919         dev_flow->act_flags = action_flags;
7920         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7921                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7922                 int item_type = items->type;
7923
7924                 switch (item_type) {
7925                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7926                         flow_dv_translate_item_port_id(dev, match_mask,
7927                                                        match_value, items);
7928                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7929                         break;
7930                 case RTE_FLOW_ITEM_TYPE_ETH:
7931                         flow_dv_translate_item_eth(match_mask, match_value,
7932                                                    items, tunnel);
7933                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7934                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7935                                              MLX5_FLOW_LAYER_OUTER_L2;
7936                         break;
7937                 case RTE_FLOW_ITEM_TYPE_VLAN:
7938                         flow_dv_translate_item_vlan(dev_flow,
7939                                                     match_mask, match_value,
7940                                                     items, tunnel);
7941                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7942                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7943                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7944                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7945                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7946                         break;
7947                 case RTE_FLOW_ITEM_TYPE_IPV4:
7948                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7949                                                   &item_flags, &tunnel);
7950                         flow_dv_translate_item_ipv4(match_mask, match_value,
7951                                                     items, item_flags, tunnel,
7952                                                     dev_flow->dv.group);
7953                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7954                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7955                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7956                         if (items->mask != NULL &&
7957                             ((const struct rte_flow_item_ipv4 *)
7958                              items->mask)->hdr.next_proto_id) {
7959                                 next_protocol =
7960                                         ((const struct rte_flow_item_ipv4 *)
7961                                          (items->spec))->hdr.next_proto_id;
7962                                 next_protocol &=
7963                                         ((const struct rte_flow_item_ipv4 *)
7964                                          (items->mask))->hdr.next_proto_id;
7965                         } else {
7966                                 /* Reset for inner layer. */
7967                                 next_protocol = 0xff;
7968                         }
7969                         break;
7970                 case RTE_FLOW_ITEM_TYPE_IPV6:
7971                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7972                                                   &item_flags, &tunnel);
7973                         flow_dv_translate_item_ipv6(match_mask, match_value,
7974                                                     items, item_flags, tunnel,
7975                                                     dev_flow->dv.group);
7976                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7977                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7978                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7979                         if (items->mask != NULL &&
7980                             ((const struct rte_flow_item_ipv6 *)
7981                              items->mask)->hdr.proto) {
7982                                 next_protocol =
7983                                         ((const struct rte_flow_item_ipv6 *)
7984                                          items->spec)->hdr.proto;
7985                                 next_protocol &=
7986                                         ((const struct rte_flow_item_ipv6 *)
7987                                          items->mask)->hdr.proto;
7988                         } else {
7989                                 /* Reset for inner layer. */
7990                                 next_protocol = 0xff;
7991                         }
7992                         break;
7993                 case RTE_FLOW_ITEM_TYPE_TCP:
7994                         flow_dv_translate_item_tcp(match_mask, match_value,
7995                                                    items, tunnel);
7996                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7997                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7998                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7999                         break;
8000                 case RTE_FLOW_ITEM_TYPE_UDP:
8001                         flow_dv_translate_item_udp(match_mask, match_value,
8002                                                    items, tunnel);
8003                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8004                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8005                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8006                         break;
8007                 case RTE_FLOW_ITEM_TYPE_GRE:
8008                         flow_dv_translate_item_gre(match_mask, match_value,
8009                                                    items, tunnel);
8010                         matcher.priority = rss_desc->level >= 2 ?
8011                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8012                         last_item = MLX5_FLOW_LAYER_GRE;
8013                         break;
8014                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8015                         flow_dv_translate_item_gre_key(match_mask,
8016                                                        match_value, items);
8017                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8018                         break;
8019                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8020                         flow_dv_translate_item_nvgre(match_mask, match_value,
8021                                                      items, tunnel);
8022                         matcher.priority = rss_desc->level >= 2 ?
8023                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8024                         last_item = MLX5_FLOW_LAYER_GRE;
8025                         break;
8026                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8027                         flow_dv_translate_item_vxlan(match_mask, match_value,
8028                                                      items, tunnel);
8029                         matcher.priority = rss_desc->level >= 2 ?
8030                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8031                         last_item = MLX5_FLOW_LAYER_VXLAN;
8032                         break;
8033                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8034                         flow_dv_translate_item_vxlan_gpe(match_mask,
8035                                                          match_value, items,
8036                                                          tunnel);
8037                         matcher.priority = rss_desc->level >= 2 ?
8038                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8039                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8040                         break;
8041                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8042                         flow_dv_translate_item_geneve(match_mask, match_value,
8043                                                       items, tunnel);
8044                         matcher.priority = rss_desc->level >= 2 ?
8045                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8046                         last_item = MLX5_FLOW_LAYER_GENEVE;
8047                         break;
8048                 case RTE_FLOW_ITEM_TYPE_MPLS:
8049                         flow_dv_translate_item_mpls(match_mask, match_value,
8050                                                     items, last_item, tunnel);
8051                         matcher.priority = rss_desc->level >= 2 ?
8052                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8053                         last_item = MLX5_FLOW_LAYER_MPLS;
8054                         break;
8055                 case RTE_FLOW_ITEM_TYPE_MARK:
8056                         flow_dv_translate_item_mark(dev, match_mask,
8057                                                     match_value, items);
8058                         last_item = MLX5_FLOW_ITEM_MARK;
8059                         break;
8060                 case RTE_FLOW_ITEM_TYPE_META:
8061                         flow_dv_translate_item_meta(dev, match_mask,
8062                                                     match_value, attr, items);
8063                         last_item = MLX5_FLOW_ITEM_METADATA;
8064                         break;
8065                 case RTE_FLOW_ITEM_TYPE_ICMP:
8066                         flow_dv_translate_item_icmp(match_mask, match_value,
8067                                                     items, tunnel);
8068                         last_item = MLX5_FLOW_LAYER_ICMP;
8069                         break;
8070                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8071                         flow_dv_translate_item_icmp6(match_mask, match_value,
8072                                                       items, tunnel);
8073                         last_item = MLX5_FLOW_LAYER_ICMP6;
8074                         break;
8075                 case RTE_FLOW_ITEM_TYPE_TAG:
8076                         flow_dv_translate_item_tag(dev, match_mask,
8077                                                    match_value, items);
8078                         last_item = MLX5_FLOW_ITEM_TAG;
8079                         break;
8080                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8081                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8082                                                         match_value, items);
8083                         last_item = MLX5_FLOW_ITEM_TAG;
8084                         break;
8085                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8086                         flow_dv_translate_item_tx_queue(dev, match_mask,
8087                                                         match_value,
8088                                                         items);
8089                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8090                         break;
8091                 case RTE_FLOW_ITEM_TYPE_GTP:
8092                         flow_dv_translate_item_gtp(match_mask, match_value,
8093                                                    items, tunnel);
8094                         matcher.priority = rss_desc->level >= 2 ?
8095                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8096                         last_item = MLX5_FLOW_LAYER_GTP;
8097                         break;
8098                 default:
8099                         break;
8100                 }
8101                 item_flags |= last_item;
8102         }
8103         /*
8104          * When E-Switch mode is enabled, we have two cases where we need to
8105          * set the source port manually.
8106          * The first one, is in case of Nic steering rule, and the second is
8107          * E-Switch rule where no port_id item was found. In both cases
8108          * the source port is set according the current port in use.
8109          */
8110         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8111             (priv->representor || priv->master)) {
8112                 if (flow_dv_translate_item_port_id(dev, match_mask,
8113                                                    match_value, NULL))
8114                         return -rte_errno;
8115         }
8116 #ifdef RTE_LIBRTE_MLX5_DEBUG
8117         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8118                                               dev_flow->dv.value.buf));
8119 #endif
8120         /*
8121          * Layers may be already initialized from prefix flow if this dev_flow
8122          * is the suffix flow.
8123          */
8124         handle->layers |= item_flags;
8125         if (action_flags & MLX5_FLOW_ACTION_RSS)
8126                 flow_dv_hashfields_set(dev_flow, rss_desc);
8127         /* Register matcher. */
8128         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8129                                     matcher.mask.size);
8130         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8131                                                      matcher.priority);
8132         /* reserved field no needs to be set to 0 here. */
8133         tbl_key.domain = attr->transfer;
8134         tbl_key.direction = attr->egress;
8135         tbl_key.table_id = dev_flow->dv.group;
8136         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8137                 return -rte_errno;
8138         return 0;
8139 }
8140
8141 /**
8142  * Apply the flow to the NIC, lock free,
8143  * (mutex should be acquired by caller).
8144  *
8145  * @param[in] dev
8146  *   Pointer to the Ethernet device structure.
8147  * @param[in, out] flow
8148  *   Pointer to flow structure.
8149  * @param[out] error
8150  *   Pointer to error structure.
8151  *
8152  * @return
8153  *   0 on success, a negative errno value otherwise and rte_errno is set.
8154  */
8155 static int
8156 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8157                 struct rte_flow_error *error)
8158 {
8159         struct mlx5_flow_dv_workspace *dv;
8160         struct mlx5_flow_handle *dh;
8161         struct mlx5_flow_handle_dv *dv_h;
8162         struct mlx5_flow *dev_flow;
8163         struct mlx5_priv *priv = dev->data->dev_private;
8164         uint32_t handle_idx;
8165         int n;
8166         int err;
8167         int idx;
8168
8169         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8170                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8171                 dv = &dev_flow->dv;
8172                 dh = dev_flow->handle;
8173                 dv_h = &dh->dvh;
8174                 n = dv->actions_n;
8175                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8176                         if (dv->transfer) {
8177                                 dv->actions[n++] = priv->sh->esw_drop_action;
8178                         } else {
8179                                 struct mlx5_hrxq *drop_hrxq;
8180                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8181                                 if (!drop_hrxq) {
8182                                         rte_flow_error_set
8183                                                 (error, errno,
8184                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8185                                                  NULL,
8186                                                  "cannot get drop hash queue");
8187                                         goto error;
8188                                 }
8189                                 /*
8190                                  * Drop queues will be released by the specify
8191                                  * mlx5_hrxq_drop_release() function. Assign
8192                                  * the special index to hrxq to mark the queue
8193                                  * has been allocated.
8194                                  */
8195                                 dh->rix_hrxq = UINT32_MAX;
8196                                 dv->actions[n++] = drop_hrxq->action;
8197                         }
8198                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8199                         struct mlx5_hrxq *hrxq;
8200                         uint32_t hrxq_idx;
8201                         struct mlx5_flow_rss_desc *rss_desc =
8202                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8203                                 [!!priv->flow_nested_idx];
8204
8205                         MLX5_ASSERT(rss_desc->queue_num);
8206                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8207                                                  MLX5_RSS_HASH_KEY_LEN,
8208                                                  dev_flow->hash_fields,
8209                                                  rss_desc->queue,
8210                                                  rss_desc->queue_num);
8211                         if (!hrxq_idx) {
8212                                 hrxq_idx = mlx5_hrxq_new
8213                                                 (dev, rss_desc->key,
8214                                                 MLX5_RSS_HASH_KEY_LEN,
8215                                                 dev_flow->hash_fields,
8216                                                 rss_desc->queue,
8217                                                 rss_desc->queue_num,
8218                                                 !!(dh->layers &
8219                                                 MLX5_FLOW_LAYER_TUNNEL));
8220                         }
8221                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8222                                               hrxq_idx);
8223                         if (!hrxq) {
8224                                 rte_flow_error_set
8225                                         (error, rte_errno,
8226                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8227                                          "cannot get hash queue");
8228                                 goto error;
8229                         }
8230                         dh->rix_hrxq = hrxq_idx;
8231                         dv->actions[n++] = hrxq->action;
8232                 }
8233                 dh->ib_flow =
8234                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8235                                                   (void *)&dv->value, n,
8236                                                   dv->actions);
8237                 if (!dh->ib_flow) {
8238                         rte_flow_error_set(error, errno,
8239                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8240                                            NULL,
8241                                            "hardware refuses to create flow");
8242                         goto error;
8243                 }
8244                 if (priv->vmwa_context &&
8245                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8246                         /*
8247                          * The rule contains the VLAN pattern.
8248                          * For VF we are going to create VLAN
8249                          * interface to make hypervisor set correct
8250                          * e-Switch vport context.
8251                          */
8252                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8253                 }
8254         }
8255         return 0;
8256 error:
8257         err = rte_errno; /* Save rte_errno before cleanup. */
8258         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8259                        handle_idx, dh, next) {
8260                 /* hrxq is union, don't clear it if the flag is not set. */
8261                 if (dh->rix_hrxq) {
8262                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8263                                 mlx5_hrxq_drop_release(dev);
8264                                 dh->rix_hrxq = 0;
8265                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8266                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8267                                 dh->rix_hrxq = 0;
8268                         }
8269                 }
8270                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8271                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8272         }
8273         rte_errno = err; /* Restore rte_errno. */
8274         return -rte_errno;
8275 }
8276
8277 /**
8278  * Release the flow matcher.
8279  *
8280  * @param dev
8281  *   Pointer to Ethernet device.
8282  * @param handle
8283  *   Pointer to mlx5_flow_handle.
8284  *
8285  * @return
8286  *   1 while a reference on it exists, 0 when freed.
8287  */
8288 static int
8289 flow_dv_matcher_release(struct rte_eth_dev *dev,
8290                         struct mlx5_flow_handle *handle)
8291 {
8292         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8293
8294         MLX5_ASSERT(matcher->matcher_object);
8295         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8296                 dev->data->port_id, (void *)matcher,
8297                 rte_atomic32_read(&matcher->refcnt));
8298         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8299                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8300                            (matcher->matcher_object));
8301                 LIST_REMOVE(matcher, next);
8302                 /* table ref-- in release interface. */
8303                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8304                 rte_free(matcher);
8305                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8306                         dev->data->port_id, (void *)matcher);
8307                 return 0;
8308         }
8309         return 1;
8310 }
8311
8312 /**
8313  * Release an encap/decap resource.
8314  *
8315  * @param dev
8316  *   Pointer to Ethernet device.
8317  * @param handle
8318  *   Pointer to mlx5_flow_handle.
8319  *
8320  * @return
8321  *   1 while a reference on it exists, 0 when freed.
8322  */
8323 static int
8324 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8325                                      struct mlx5_flow_handle *handle)
8326 {
8327         struct mlx5_priv *priv = dev->data->dev_private;
8328         uint32_t idx = handle->dvh.rix_encap_decap;
8329         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8330
8331         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8332                          idx);
8333         if (!cache_resource)
8334                 return 0;
8335         MLX5_ASSERT(cache_resource->verbs_action);
8336         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8337                 (void *)cache_resource,
8338                 rte_atomic32_read(&cache_resource->refcnt));
8339         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8340                 claim_zero(mlx5_glue->destroy_flow_action
8341                                 (cache_resource->verbs_action));
8342                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8343                              &priv->sh->encaps_decaps, idx,
8344                              cache_resource, next);
8345                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8346                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8347                         (void *)cache_resource);
8348                 return 0;
8349         }
8350         return 1;
8351 }
8352
8353 /**
8354  * Release an jump to table action resource.
8355  *
8356  * @param dev
8357  *   Pointer to Ethernet device.
8358  * @param handle
8359  *   Pointer to mlx5_flow_handle.
8360  *
8361  * @return
8362  *   1 while a reference on it exists, 0 when freed.
8363  */
8364 static int
8365 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8366                                   struct mlx5_flow_handle *handle)
8367 {
8368         struct mlx5_priv *priv = dev->data->dev_private;
8369         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8370         struct mlx5_flow_tbl_data_entry *tbl_data;
8371
8372         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8373                              handle->rix_jump);
8374         if (!tbl_data)
8375                 return 0;
8376         cache_resource = &tbl_data->jump;
8377         MLX5_ASSERT(cache_resource->action);
8378         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8379                 (void *)cache_resource,
8380                 rte_atomic32_read(&cache_resource->refcnt));
8381         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8382                 claim_zero(mlx5_glue->destroy_flow_action
8383                                 (cache_resource->action));
8384                 /* jump action memory free is inside the table release. */
8385                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8386                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8387                         (void *)cache_resource);
8388                 return 0;
8389         }
8390         return 1;
8391 }
8392
8393 /**
8394  * Release a modify-header resource.
8395  *
8396  * @param handle
8397  *   Pointer to mlx5_flow_handle.
8398  *
8399  * @return
8400  *   1 while a reference on it exists, 0 when freed.
8401  */
8402 static int
8403 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8404 {
8405         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8406                                                         handle->dvh.modify_hdr;
8407
8408         MLX5_ASSERT(cache_resource->verbs_action);
8409         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8410                 (void *)cache_resource,
8411                 rte_atomic32_read(&cache_resource->refcnt));
8412         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8413                 claim_zero(mlx5_glue->destroy_flow_action
8414                                 (cache_resource->verbs_action));
8415                 LIST_REMOVE(cache_resource, next);
8416                 rte_free(cache_resource);
8417                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8418                         (void *)cache_resource);
8419                 return 0;
8420         }
8421         return 1;
8422 }
8423
8424 /**
8425  * Release port ID action resource.
8426  *
8427  * @param dev
8428  *   Pointer to Ethernet device.
8429  * @param handle
8430  *   Pointer to mlx5_flow_handle.
8431  *
8432  * @return
8433  *   1 while a reference on it exists, 0 when freed.
8434  */
8435 static int
8436 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8437                                         struct mlx5_flow_handle *handle)
8438 {
8439         struct mlx5_priv *priv = dev->data->dev_private;
8440         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8441         uint32_t idx = handle->rix_port_id_action;
8442
8443         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8444                                         idx);
8445         if (!cache_resource)
8446                 return 0;
8447         MLX5_ASSERT(cache_resource->action);
8448         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8449                 (void *)cache_resource,
8450                 rte_atomic32_read(&cache_resource->refcnt));
8451         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8452                 claim_zero(mlx5_glue->destroy_flow_action
8453                                 (cache_resource->action));
8454                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8455                              &priv->sh->port_id_action_list, idx,
8456                              cache_resource, next);
8457                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8458                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8459                         (void *)cache_resource);
8460                 return 0;
8461         }
8462         return 1;
8463 }
8464
8465 /**
8466  * Release push vlan action resource.
8467  *
8468  * @param dev
8469  *   Pointer to Ethernet device.
8470  * @param handle
8471  *   Pointer to mlx5_flow_handle.
8472  *
8473  * @return
8474  *   1 while a reference on it exists, 0 when freed.
8475  */
8476 static int
8477 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8478                                           struct mlx5_flow_handle *handle)
8479 {
8480         struct mlx5_priv *priv = dev->data->dev_private;
8481         uint32_t idx = handle->dvh.rix_push_vlan;
8482         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8483
8484         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8485                                         idx);
8486         if (!cache_resource)
8487                 return 0;
8488         MLX5_ASSERT(cache_resource->action);
8489         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8490                 (void *)cache_resource,
8491                 rte_atomic32_read(&cache_resource->refcnt));
8492         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8493                 claim_zero(mlx5_glue->destroy_flow_action
8494                                 (cache_resource->action));
8495                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8496                              &priv->sh->push_vlan_action_list, idx,
8497                              cache_resource, next);
8498                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8499                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8500                         (void *)cache_resource);
8501                 return 0;
8502         }
8503         return 1;
8504 }
8505
8506 /**
8507  * Release the fate resource.
8508  *
8509  * @param dev
8510  *   Pointer to Ethernet device.
8511  * @param handle
8512  *   Pointer to mlx5_flow_handle.
8513  */
8514 static void
8515 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8516                                struct mlx5_flow_handle *handle)
8517 {
8518         if (!handle->rix_fate)
8519                 return;
8520         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8521                 mlx5_hrxq_drop_release(dev);
8522         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8523                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8524         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8525                 flow_dv_jump_tbl_resource_release(dev, handle);
8526         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8527                 flow_dv_port_id_action_resource_release(dev, handle);
8528         else
8529                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8530         handle->rix_fate = 0;
8531 }
8532
8533 /**
8534  * Remove the flow from the NIC but keeps it in memory.
8535  * Lock free, (mutex should be acquired by caller).
8536  *
8537  * @param[in] dev
8538  *   Pointer to Ethernet device.
8539  * @param[in, out] flow
8540  *   Pointer to flow structure.
8541  */
8542 static void
8543 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8544 {
8545         struct mlx5_flow_handle *dh;
8546         uint32_t handle_idx;
8547         struct mlx5_priv *priv = dev->data->dev_private;
8548
8549         if (!flow)
8550                 return;
8551         handle_idx = flow->dev_handles;
8552         while (handle_idx) {
8553                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8554                                     handle_idx);
8555                 if (!dh)
8556                         return;
8557                 if (dh->ib_flow) {
8558                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8559                         dh->ib_flow = NULL;
8560                 }
8561                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8562                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8563                         flow_dv_fate_resource_release(dev, dh);
8564                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8565                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8566                 handle_idx = dh->next.next;
8567         }
8568 }
8569
8570 /**
8571  * Remove the flow from the NIC and the memory.
8572  * Lock free, (mutex should be acquired by caller).
8573  *
8574  * @param[in] dev
8575  *   Pointer to the Ethernet device structure.
8576  * @param[in, out] flow
8577  *   Pointer to flow structure.
8578  */
8579 static void
8580 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8581 {
8582         struct mlx5_flow_handle *dev_handle;
8583         struct mlx5_priv *priv = dev->data->dev_private;
8584
8585         if (!flow)
8586                 return;
8587         __flow_dv_remove(dev, flow);
8588         if (flow->counter) {
8589                 flow_dv_counter_release(dev, flow->counter);
8590                 flow->counter = 0;
8591         }
8592         if (flow->meter) {
8593                 struct mlx5_flow_meter *fm;
8594
8595                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8596                                     flow->meter);
8597                 if (fm)
8598                         mlx5_flow_meter_detach(fm);
8599                 flow->meter = 0;
8600         }
8601         while (flow->dev_handles) {
8602                 uint32_t tmp_idx = flow->dev_handles;
8603
8604                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8605                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8606                 if (!dev_handle)
8607                         return;
8608                 flow->dev_handles = dev_handle->next.next;
8609                 if (dev_handle->dvh.matcher)
8610                         flow_dv_matcher_release(dev, dev_handle);
8611                 if (dev_handle->dvh.rix_encap_decap)
8612                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8613                 if (dev_handle->dvh.modify_hdr)
8614                         flow_dv_modify_hdr_resource_release(dev_handle);
8615                 if (dev_handle->dvh.rix_push_vlan)
8616                         flow_dv_push_vlan_action_resource_release(dev,
8617                                                                   dev_handle);
8618                 if (dev_handle->dvh.rix_tag)
8619                         flow_dv_tag_release(dev,
8620                                             dev_handle->dvh.rix_tag);
8621                 flow_dv_fate_resource_release(dev, dev_handle);
8622                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8623                            tmp_idx);
8624         }
8625 }
8626
8627 /**
8628  * Query a dv flow  rule for its statistics via devx.
8629  *
8630  * @param[in] dev
8631  *   Pointer to Ethernet device.
8632  * @param[in] flow
8633  *   Pointer to the sub flow.
8634  * @param[out] data
8635  *   data retrieved by the query.
8636  * @param[out] error
8637  *   Perform verbose error reporting if not NULL.
8638  *
8639  * @return
8640  *   0 on success, a negative errno value otherwise and rte_errno is set.
8641  */
8642 static int
8643 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8644                     void *data, struct rte_flow_error *error)
8645 {
8646         struct mlx5_priv *priv = dev->data->dev_private;
8647         struct rte_flow_query_count *qc = data;
8648
8649         if (!priv->config.devx)
8650                 return rte_flow_error_set(error, ENOTSUP,
8651                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8652                                           NULL,
8653                                           "counters are not supported");
8654         if (flow->counter) {
8655                 uint64_t pkts, bytes;
8656                 struct mlx5_flow_counter *cnt;
8657
8658                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8659                                                  NULL);
8660                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8661                                                &bytes);
8662
8663                 if (err)
8664                         return rte_flow_error_set(error, -err,
8665                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8666                                         NULL, "cannot read counters");
8667                 qc->hits_set = 1;
8668                 qc->bytes_set = 1;
8669                 qc->hits = pkts - cnt->hits;
8670                 qc->bytes = bytes - cnt->bytes;
8671                 if (qc->reset) {
8672                         cnt->hits = pkts;
8673                         cnt->bytes = bytes;
8674                 }
8675                 return 0;
8676         }
8677         return rte_flow_error_set(error, EINVAL,
8678                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8679                                   NULL,
8680                                   "counters are not available");
8681 }
8682
8683 /**
8684  * Query a flow.
8685  *
8686  * @see rte_flow_query()
8687  * @see rte_flow_ops
8688  */
8689 static int
8690 flow_dv_query(struct rte_eth_dev *dev,
8691               struct rte_flow *flow __rte_unused,
8692               const struct rte_flow_action *actions __rte_unused,
8693               void *data __rte_unused,
8694               struct rte_flow_error *error __rte_unused)
8695 {
8696         int ret = -EINVAL;
8697
8698         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8699                 switch (actions->type) {
8700                 case RTE_FLOW_ACTION_TYPE_VOID:
8701                         break;
8702                 case RTE_FLOW_ACTION_TYPE_COUNT:
8703                         ret = flow_dv_query_count(dev, flow, data, error);
8704                         break;
8705                 default:
8706                         return rte_flow_error_set(error, ENOTSUP,
8707                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8708                                                   actions,
8709                                                   "action not supported");
8710                 }
8711         }
8712         return ret;
8713 }
8714
8715 /**
8716  * Destroy the meter table set.
8717  * Lock free, (mutex should be acquired by caller).
8718  *
8719  * @param[in] dev
8720  *   Pointer to Ethernet device.
8721  * @param[in] tbl
8722  *   Pointer to the meter table set.
8723  *
8724  * @return
8725  *   Always 0.
8726  */
8727 static int
8728 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8729                         struct mlx5_meter_domains_infos *tbl)
8730 {
8731         struct mlx5_priv *priv = dev->data->dev_private;
8732         struct mlx5_meter_domains_infos *mtd =
8733                                 (struct mlx5_meter_domains_infos *)tbl;
8734
8735         if (!mtd || !priv->config.dv_flow_en)
8736                 return 0;
8737         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8738                 claim_zero(mlx5_glue->dv_destroy_flow
8739                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8740         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8741                 claim_zero(mlx5_glue->dv_destroy_flow
8742                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8743         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8744                 claim_zero(mlx5_glue->dv_destroy_flow
8745                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8746         if (mtd->egress.color_matcher)
8747                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8748                           (mtd->egress.color_matcher));
8749         if (mtd->egress.any_matcher)
8750                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8751                           (mtd->egress.any_matcher));
8752         if (mtd->egress.tbl)
8753                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
8754         if (mtd->egress.sfx_tbl)
8755                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
8756         if (mtd->ingress.color_matcher)
8757                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8758                           (mtd->ingress.color_matcher));
8759         if (mtd->ingress.any_matcher)
8760                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8761                           (mtd->ingress.any_matcher));
8762         if (mtd->ingress.tbl)
8763                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
8764         if (mtd->ingress.sfx_tbl)
8765                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
8766         if (mtd->transfer.color_matcher)
8767                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8768                           (mtd->transfer.color_matcher));
8769         if (mtd->transfer.any_matcher)
8770                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8771                           (mtd->transfer.any_matcher));
8772         if (mtd->transfer.tbl)
8773                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
8774         if (mtd->transfer.sfx_tbl)
8775                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
8776         if (mtd->drop_actn)
8777                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8778         rte_free(mtd);
8779         return 0;
8780 }
8781
8782 /* Number of meter flow actions, count and jump or count and drop. */
8783 #define METER_ACTIONS 2
8784
8785 /**
8786  * Create specify domain meter table and suffix table.
8787  *
8788  * @param[in] dev
8789  *   Pointer to Ethernet device.
8790  * @param[in,out] mtb
8791  *   Pointer to DV meter table set.
8792  * @param[in] egress
8793  *   Table attribute.
8794  * @param[in] transfer
8795  *   Table attribute.
8796  * @param[in] color_reg_c_idx
8797  *   Reg C index for color match.
8798  *
8799  * @return
8800  *   0 on success, -1 otherwise and rte_errno is set.
8801  */
8802 static int
8803 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8804                            struct mlx5_meter_domains_infos *mtb,
8805                            uint8_t egress, uint8_t transfer,
8806                            uint32_t color_reg_c_idx)
8807 {
8808         struct mlx5_priv *priv = dev->data->dev_private;
8809         struct mlx5_ibv_shared *sh = priv->sh;
8810         struct mlx5_flow_dv_match_params mask = {
8811                 .size = sizeof(mask.buf),
8812         };
8813         struct mlx5_flow_dv_match_params value = {
8814                 .size = sizeof(value.buf),
8815         };
8816         struct mlx5dv_flow_matcher_attr dv_attr = {
8817                 .type = IBV_FLOW_ATTR_NORMAL,
8818                 .priority = 0,
8819                 .match_criteria_enable = 0,
8820                 .match_mask = (void *)&mask,
8821         };
8822         void *actions[METER_ACTIONS];
8823         struct mlx5_meter_domain_info *dtb;
8824         struct rte_flow_error error;
8825         int i = 0;
8826
8827         if (transfer)
8828                 dtb = &mtb->transfer;
8829         else if (egress)
8830                 dtb = &mtb->egress;
8831         else
8832                 dtb = &mtb->ingress;
8833         /* Create the meter table with METER level. */
8834         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8835                                             egress, transfer, &error);
8836         if (!dtb->tbl) {
8837                 DRV_LOG(ERR, "Failed to create meter policer table.");
8838                 return -1;
8839         }
8840         /* Create the meter suffix table with SUFFIX level. */
8841         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8842                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8843                                             egress, transfer, &error);
8844         if (!dtb->sfx_tbl) {
8845                 DRV_LOG(ERR, "Failed to create meter suffix table.");
8846                 return -1;
8847         }
8848         /* Create matchers, Any and Color. */
8849         dv_attr.priority = 3;
8850         dv_attr.match_criteria_enable = 0;
8851         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8852                                                              &dv_attr,
8853                                                              dtb->tbl->obj);
8854         if (!dtb->any_matcher) {
8855                 DRV_LOG(ERR, "Failed to create meter"
8856                              " policer default matcher.");
8857                 goto error_exit;
8858         }
8859         dv_attr.priority = 0;
8860         dv_attr.match_criteria_enable =
8861                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8862         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8863                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8864         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8865                                                                &dv_attr,
8866                                                                dtb->tbl->obj);
8867         if (!dtb->color_matcher) {
8868                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8869                 goto error_exit;
8870         }
8871         if (mtb->count_actns[RTE_MTR_DROPPED])
8872                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8873         actions[i++] = mtb->drop_actn;
8874         /* Default rule: lowest priority, match any, actions: drop. */
8875         dtb->policer_rules[RTE_MTR_DROPPED] =
8876                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8877                                                  (void *)&value, i, actions);
8878         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8879                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8880                 goto error_exit;
8881         }
8882         return 0;
8883 error_exit:
8884         return -1;
8885 }
8886
8887 /**
8888  * Create the needed meter and suffix tables.
8889  * Lock free, (mutex should be acquired by caller).
8890  *
8891  * @param[in] dev
8892  *   Pointer to Ethernet device.
8893  * @param[in] fm
8894  *   Pointer to the flow meter.
8895  *
8896  * @return
8897  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8898  */
8899 static struct mlx5_meter_domains_infos *
8900 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8901                        const struct mlx5_flow_meter *fm)
8902 {
8903         struct mlx5_priv *priv = dev->data->dev_private;
8904         struct mlx5_meter_domains_infos *mtb;
8905         int ret;
8906         int i;
8907
8908         if (!priv->mtr_en) {
8909                 rte_errno = ENOTSUP;
8910                 return NULL;
8911         }
8912         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8913         if (!mtb) {
8914                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8915                 return NULL;
8916         }
8917         /* Create meter count actions */
8918         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8919                 struct mlx5_flow_counter *cnt;
8920                 if (!fm->policer_stats.cnt[i])
8921                         continue;
8922                 cnt = flow_dv_counter_get_by_idx(dev,
8923                       fm->policer_stats.cnt[i], NULL);
8924                 mtb->count_actns[i] = cnt->action;
8925         }
8926         /* Create drop action. */
8927         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8928         if (!mtb->drop_actn) {
8929                 DRV_LOG(ERR, "Failed to create drop action.");
8930                 goto error_exit;
8931         }
8932         /* Egress meter table. */
8933         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8934         if (ret) {
8935                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8936                 goto error_exit;
8937         }
8938         /* Ingress meter table. */
8939         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8940         if (ret) {
8941                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8942                 goto error_exit;
8943         }
8944         /* FDB meter table. */
8945         if (priv->config.dv_esw_en) {
8946                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8947                                                  priv->mtr_color_reg);
8948                 if (ret) {
8949                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8950                         goto error_exit;
8951                 }
8952         }
8953         return mtb;
8954 error_exit:
8955         flow_dv_destroy_mtr_tbl(dev, mtb);
8956         return NULL;
8957 }
8958
8959 /**
8960  * Destroy domain policer rule.
8961  *
8962  * @param[in] dt
8963  *   Pointer to domain table.
8964  */
8965 static void
8966 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8967 {
8968         int i;
8969
8970         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8971                 if (dt->policer_rules[i]) {
8972                         claim_zero(mlx5_glue->dv_destroy_flow
8973                                   (dt->policer_rules[i]));
8974                         dt->policer_rules[i] = NULL;
8975                 }
8976         }
8977         if (dt->jump_actn) {
8978                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8979                 dt->jump_actn = NULL;
8980         }
8981 }
8982
8983 /**
8984  * Destroy policer rules.
8985  *
8986  * @param[in] dev
8987  *   Pointer to Ethernet device.
8988  * @param[in] fm
8989  *   Pointer to flow meter structure.
8990  * @param[in] attr
8991  *   Pointer to flow attributes.
8992  *
8993  * @return
8994  *   Always 0.
8995  */
8996 static int
8997 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8998                               const struct mlx5_flow_meter *fm,
8999                               const struct rte_flow_attr *attr)
9000 {
9001         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9002
9003         if (!mtb)
9004                 return 0;
9005         if (attr->egress)
9006                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9007         if (attr->ingress)
9008                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9009         if (attr->transfer)
9010                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9011         return 0;
9012 }
9013
9014 /**
9015  * Create specify domain meter policer rule.
9016  *
9017  * @param[in] fm
9018  *   Pointer to flow meter structure.
9019  * @param[in] mtb
9020  *   Pointer to DV meter table set.
9021  * @param[in] mtr_reg_c
9022  *   Color match REG_C.
9023  *
9024  * @return
9025  *   0 on success, -1 otherwise.
9026  */
9027 static int
9028 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9029                                     struct mlx5_meter_domain_info *dtb,
9030                                     uint8_t mtr_reg_c)
9031 {
9032         struct mlx5_flow_dv_match_params matcher = {
9033                 .size = sizeof(matcher.buf),
9034         };
9035         struct mlx5_flow_dv_match_params value = {
9036                 .size = sizeof(value.buf),
9037         };
9038         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9039         void *actions[METER_ACTIONS];
9040         int i;
9041
9042         /* Create jump action. */
9043         if (!dtb->jump_actn)
9044                 dtb->jump_actn =
9045                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9046                                                         (dtb->sfx_tbl->obj);
9047         if (!dtb->jump_actn) {
9048                 DRV_LOG(ERR, "Failed to create policer jump action.");
9049                 goto error;
9050         }
9051         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9052                 int j = 0;
9053
9054                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9055                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9056                 if (mtb->count_actns[i])
9057                         actions[j++] = mtb->count_actns[i];
9058                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9059                         actions[j++] = mtb->drop_actn;
9060                 else
9061                         actions[j++] = dtb->jump_actn;
9062                 dtb->policer_rules[i] =
9063                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9064                                                  (void *)&value,
9065                                                   j, actions);
9066                 if (!dtb->policer_rules[i]) {
9067                         DRV_LOG(ERR, "Failed to create policer rule.");
9068                         goto error;
9069                 }
9070         }
9071         return 0;
9072 error:
9073         rte_errno = errno;
9074         return -1;
9075 }
9076
9077 /**
9078  * Create policer rules.
9079  *
9080  * @param[in] dev
9081  *   Pointer to Ethernet device.
9082  * @param[in] fm
9083  *   Pointer to flow meter structure.
9084  * @param[in] attr
9085  *   Pointer to flow attributes.
9086  *
9087  * @return
9088  *   0 on success, -1 otherwise.
9089  */
9090 static int
9091 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9092                              struct mlx5_flow_meter *fm,
9093                              const struct rte_flow_attr *attr)
9094 {
9095         struct mlx5_priv *priv = dev->data->dev_private;
9096         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9097         int ret;
9098
9099         if (attr->egress) {
9100                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9101                                                 priv->mtr_color_reg);
9102                 if (ret) {
9103                         DRV_LOG(ERR, "Failed to create egress policer.");
9104                         goto error;
9105                 }
9106         }
9107         if (attr->ingress) {
9108                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9109                                                 priv->mtr_color_reg);
9110                 if (ret) {
9111                         DRV_LOG(ERR, "Failed to create ingress policer.");
9112                         goto error;
9113                 }
9114         }
9115         if (attr->transfer) {
9116                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9117                                                 priv->mtr_color_reg);
9118                 if (ret) {
9119                         DRV_LOG(ERR, "Failed to create transfer policer.");
9120                         goto error;
9121                 }
9122         }
9123         return 0;
9124 error:
9125         flow_dv_destroy_policer_rules(dev, fm, attr);
9126         return -1;
9127 }
9128
9129 /**
9130  * Query a devx counter.
9131  *
9132  * @param[in] dev
9133  *   Pointer to the Ethernet device structure.
9134  * @param[in] cnt
9135  *   Index to the flow counter.
9136  * @param[in] clear
9137  *   Set to clear the counter statistics.
9138  * @param[out] pkts
9139  *   The statistics value of packets.
9140  * @param[out] bytes
9141  *   The statistics value of bytes.
9142  *
9143  * @return
9144  *   0 on success, otherwise return -1.
9145  */
9146 static int
9147 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9148                       uint64_t *pkts, uint64_t *bytes)
9149 {
9150         struct mlx5_priv *priv = dev->data->dev_private;
9151         struct mlx5_flow_counter *cnt;
9152         uint64_t inn_pkts, inn_bytes;
9153         int ret;
9154
9155         if (!priv->config.devx)
9156                 return -1;
9157
9158         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9159         if (ret)
9160                 return -1;
9161         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9162         *pkts = inn_pkts - cnt->hits;
9163         *bytes = inn_bytes - cnt->bytes;
9164         if (clear) {
9165                 cnt->hits = inn_pkts;
9166                 cnt->bytes = inn_bytes;
9167         }
9168         return 0;
9169 }
9170
9171 /*
9172  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9173  */
9174 static int
9175 flow_dv_translate(struct rte_eth_dev *dev,
9176                   struct mlx5_flow *dev_flow,
9177                   const struct rte_flow_attr *attr,
9178                   const struct rte_flow_item items[],
9179                   const struct rte_flow_action actions[],
9180                   struct rte_flow_error *error)
9181 {
9182         int ret;
9183
9184         flow_dv_shared_lock(dev);
9185         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9186         flow_dv_shared_unlock(dev);
9187         return ret;
9188 }
9189
9190 /*
9191  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9192  */
9193 static int
9194 flow_dv_apply(struct rte_eth_dev *dev,
9195               struct rte_flow *flow,
9196               struct rte_flow_error *error)
9197 {
9198         int ret;
9199
9200         flow_dv_shared_lock(dev);
9201         ret = __flow_dv_apply(dev, flow, error);
9202         flow_dv_shared_unlock(dev);
9203         return ret;
9204 }
9205
9206 /*
9207  * Mutex-protected thunk to lock-free __flow_dv_remove().
9208  */
9209 static void
9210 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9211 {
9212         flow_dv_shared_lock(dev);
9213         __flow_dv_remove(dev, flow);
9214         flow_dv_shared_unlock(dev);
9215 }
9216
9217 /*
9218  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9219  */
9220 static void
9221 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9222 {
9223         flow_dv_shared_lock(dev);
9224         __flow_dv_destroy(dev, flow);
9225         flow_dv_shared_unlock(dev);
9226 }
9227
9228 /*
9229  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9230  */
9231 static uint32_t
9232 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9233 {
9234         uint32_t cnt;
9235
9236         flow_dv_shared_lock(dev);
9237         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9238         flow_dv_shared_unlock(dev);
9239         return cnt;
9240 }
9241
9242 /*
9243  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9244  */
9245 static void
9246 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9247 {
9248         flow_dv_shared_lock(dev);
9249         flow_dv_counter_release(dev, cnt);
9250         flow_dv_shared_unlock(dev);
9251 }
9252
9253 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9254         .validate = flow_dv_validate,
9255         .prepare = flow_dv_prepare,
9256         .translate = flow_dv_translate,
9257         .apply = flow_dv_apply,
9258         .remove = flow_dv_remove,
9259         .destroy = flow_dv_destroy,
9260         .query = flow_dv_query,
9261         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9262         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9263         .create_policer_rules = flow_dv_create_policer_rules,
9264         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9265         .counter_alloc = flow_dv_counter_allocate,
9266         .counter_free = flow_dv_counter_free,
9267         .counter_query = flow_dv_counter_query,
9268 };
9269
9270 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */