1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
100 struct mlx5_common_device *cdev = priv->sh->cdev;
102 if (cdev->config.hca_attr.esw_mgr_vport_id_valid)
103 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id;
105 if (priv->pci_dev == NULL)
107 switch (priv->pci_dev->id.device_id) {
108 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
109 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
110 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
111 return (int16_t)0xfffe;
118 * Initialize flow attributes structure according to flow items' types.
120 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
121 * mode. For tunnel mode, the items to be modified are the outermost ones.
124 * Pointer to item specification.
126 * Pointer to flow attributes structure.
127 * @param[in] dev_flow
128 * Pointer to the sub flow.
129 * @param[in] tunnel_decap
130 * Whether action is after tunnel decapsulation.
133 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
134 struct mlx5_flow *dev_flow, bool tunnel_decap)
136 uint64_t layers = dev_flow->handle->layers;
139 * If layers is already initialized, it means this dev_flow is the
140 * suffix flow, the layers flags is set by the prefix flow. Need to
141 * use the layer flags from prefix flow as the suffix flow may not
142 * have the user defined items as the flow is split.
145 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
149 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
151 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
156 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
157 uint8_t next_protocol = 0xff;
158 switch (item->type) {
159 case RTE_FLOW_ITEM_TYPE_GRE:
160 case RTE_FLOW_ITEM_TYPE_NVGRE:
161 case RTE_FLOW_ITEM_TYPE_VXLAN:
162 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
163 case RTE_FLOW_ITEM_TYPE_GENEVE:
164 case RTE_FLOW_ITEM_TYPE_MPLS:
168 case RTE_FLOW_ITEM_TYPE_IPV4:
171 if (item->mask != NULL &&
172 ((const struct rte_flow_item_ipv4 *)
173 item->mask)->hdr.next_proto_id)
175 ((const struct rte_flow_item_ipv4 *)
176 (item->spec))->hdr.next_proto_id &
177 ((const struct rte_flow_item_ipv4 *)
178 (item->mask))->hdr.next_proto_id;
179 if ((next_protocol == IPPROTO_IPIP ||
180 next_protocol == IPPROTO_IPV6) && tunnel_decap)
183 case RTE_FLOW_ITEM_TYPE_IPV6:
186 if (item->mask != NULL &&
187 ((const struct rte_flow_item_ipv6 *)
188 item->mask)->hdr.proto)
190 ((const struct rte_flow_item_ipv6 *)
191 (item->spec))->hdr.proto &
192 ((const struct rte_flow_item_ipv6 *)
193 (item->mask))->hdr.proto;
194 if ((next_protocol == IPPROTO_IPIP ||
195 next_protocol == IPPROTO_IPV6) && tunnel_decap)
198 case RTE_FLOW_ITEM_TYPE_UDP:
202 case RTE_FLOW_ITEM_TYPE_TCP:
214 * Convert rte_mtr_color to mlx5 color.
223 rte_col_2_mlx5_col(enum rte_color rcol)
226 case RTE_COLOR_GREEN:
227 return MLX5_FLOW_COLOR_GREEN;
228 case RTE_COLOR_YELLOW:
229 return MLX5_FLOW_COLOR_YELLOW;
231 return MLX5_FLOW_COLOR_RED;
235 return MLX5_FLOW_COLOR_UNDEFINED;
238 struct field_modify_info {
239 uint32_t size; /* Size of field in protocol header, in bytes. */
240 uint32_t offset; /* Offset of field in protocol header, in bytes. */
241 enum mlx5_modification_field id;
244 struct field_modify_info modify_eth[] = {
245 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
246 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
247 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
248 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
252 struct field_modify_info modify_vlan_out_first_vid[] = {
253 /* Size in bits !!! */
254 {12, 0, MLX5_MODI_OUT_FIRST_VID},
258 struct field_modify_info modify_ipv4[] = {
259 {1, 1, MLX5_MODI_OUT_IP_DSCP},
260 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
261 {4, 12, MLX5_MODI_OUT_SIPV4},
262 {4, 16, MLX5_MODI_OUT_DIPV4},
266 struct field_modify_info modify_ipv6[] = {
267 {1, 0, MLX5_MODI_OUT_IP_DSCP},
268 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
269 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
270 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
271 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
272 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
273 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
274 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
275 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
276 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
280 struct field_modify_info modify_udp[] = {
281 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
282 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
286 struct field_modify_info modify_tcp[] = {
287 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
288 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
289 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
290 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
295 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
296 uint8_t next_protocol, uint64_t *item_flags,
299 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
300 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
301 if (next_protocol == IPPROTO_IPIP) {
302 *item_flags |= MLX5_FLOW_LAYER_IPIP;
305 if (next_protocol == IPPROTO_IPV6) {
306 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
311 static inline struct mlx5_hlist *
312 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
313 const char *name, uint32_t size, bool direct_key,
314 bool lcores_share, void *ctx,
315 mlx5_list_create_cb cb_create,
316 mlx5_list_match_cb cb_match,
317 mlx5_list_remove_cb cb_remove,
318 mlx5_list_clone_cb cb_clone,
319 mlx5_list_clone_free_cb cb_clone_free,
320 struct rte_flow_error *error)
322 struct mlx5_hlist *hl;
323 struct mlx5_hlist *expected = NULL;
324 char s[MLX5_NAME_SIZE];
326 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
329 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
330 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
331 ctx, cb_create, cb_match, cb_remove, cb_clone,
334 DRV_LOG(ERR, "%s hash creation failed", name);
335 rte_flow_error_set(error, ENOMEM,
336 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
337 "cannot allocate resource memory");
340 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
343 mlx5_hlist_destroy(hl);
344 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
349 /* Update VLAN's VID/PCP based on input rte_flow_action.
352 * Pointer to struct rte_flow_action.
354 * Pointer to struct rte_vlan_hdr.
357 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
358 struct rte_vlan_hdr *vlan)
361 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
363 ((const struct rte_flow_action_of_set_vlan_pcp *)
364 action->conf)->vlan_pcp;
365 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
366 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
367 vlan->vlan_tci |= vlan_tci;
368 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
369 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
370 vlan->vlan_tci |= rte_be_to_cpu_16
371 (((const struct rte_flow_action_of_set_vlan_vid *)
372 action->conf)->vlan_vid);
377 * Fetch 1, 2, 3 or 4 byte field from the byte array
378 * and return as unsigned integer in host-endian format.
381 * Pointer to data array.
383 * Size of field to extract.
386 * converted field in host endian format.
388 static inline uint32_t
389 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
398 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
401 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
402 ret = (ret << 8) | *(data + sizeof(uint16_t));
405 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
416 * Convert modify-header action to DV specification.
418 * Data length of each action is determined by provided field description
419 * and the item mask. Data bit offset and width of each action is determined
420 * by provided item mask.
423 * Pointer to item specification.
425 * Pointer to field modification information.
426 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
427 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
428 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
430 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
431 * Negative offset value sets the same offset as source offset.
432 * size field is ignored, value is taken from source field.
433 * @param[in,out] resource
434 * Pointer to the modify-header resource.
436 * Type of modification.
438 * Pointer to the error structure.
441 * 0 on success, a negative errno value otherwise and rte_errno is set.
444 flow_dv_convert_modify_action(struct rte_flow_item *item,
445 struct field_modify_info *field,
446 struct field_modify_info *dcopy,
447 struct mlx5_flow_dv_modify_hdr_resource *resource,
448 uint32_t type, struct rte_flow_error *error)
450 uint32_t i = resource->actions_num;
451 struct mlx5_modification_cmd *actions = resource->actions;
452 uint32_t carry_b = 0;
455 * The item and mask are provided in big-endian format.
456 * The fields should be presented as in big-endian format either.
457 * Mask must be always present, it defines the actual field width.
459 MLX5_ASSERT(item->mask);
460 MLX5_ASSERT(field->size);
466 bool next_field = true;
467 bool next_dcopy = true;
469 if (i >= MLX5_MAX_MODIFY_NUM)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "too many items to modify");
473 /* Fetch variable byte size mask from the array. */
474 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
475 field->offset, field->size);
480 /* Deduce actual data width in bits from mask value. */
481 off_b = rte_bsf32(mask) + carry_b;
482 size_b = sizeof(uint32_t) * CHAR_BIT -
483 off_b - __builtin_clz(mask);
485 actions[i] = (struct mlx5_modification_cmd) {
489 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
492 if (type == MLX5_MODIFICATION_TYPE_COPY) {
494 actions[i].dst_field = dcopy->id;
495 actions[i].dst_offset =
496 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
497 /* Convert entire record to big-endian format. */
498 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
500 * Destination field overflow. Copy leftovers of
501 * a source field to the next destination field.
504 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
507 dcopy->size * CHAR_BIT - dcopy->offset;
508 carry_b = actions[i].length;
512 * Not enough bits in a source filed to fill a
513 * destination field. Switch to the next source.
515 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
516 (size_b == field->size * CHAR_BIT - off_b)) {
518 field->size * CHAR_BIT - off_b;
519 dcopy->offset += actions[i].length;
525 MLX5_ASSERT(item->spec);
526 data = flow_dv_fetch_field((const uint8_t *)item->spec +
527 field->offset, field->size);
528 /* Shift out the trailing masked bits from data. */
529 data = (data & mask) >> off_b;
530 actions[i].data1 = rte_cpu_to_be_32(data);
532 /* Convert entire record to expected big-endian format. */
533 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
537 } while (field->size);
538 if (resource->actions_num == i)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "invalid modification flow item");
542 resource->actions_num = i;
547 * Convert modify-header set IPv4 address action to DV specification.
549 * @param[in,out] resource
550 * Pointer to the modify-header resource.
552 * Pointer to action specification.
554 * Pointer to the error structure.
557 * 0 on success, a negative errno value otherwise and rte_errno is set.
560 flow_dv_convert_action_modify_ipv4
561 (struct mlx5_flow_dv_modify_hdr_resource *resource,
562 const struct rte_flow_action *action,
563 struct rte_flow_error *error)
565 const struct rte_flow_action_set_ipv4 *conf =
566 (const struct rte_flow_action_set_ipv4 *)(action->conf);
567 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
568 struct rte_flow_item_ipv4 ipv4;
569 struct rte_flow_item_ipv4 ipv4_mask;
571 memset(&ipv4, 0, sizeof(ipv4));
572 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
573 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
574 ipv4.hdr.src_addr = conf->ipv4_addr;
575 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
577 ipv4.hdr.dst_addr = conf->ipv4_addr;
578 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
581 item.mask = &ipv4_mask;
582 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set IPv6 address action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_ipv6
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_set_ipv6 *conf =
606 (const struct rte_flow_action_set_ipv6 *)(action->conf);
607 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
608 struct rte_flow_item_ipv6 ipv6;
609 struct rte_flow_item_ipv6 ipv6_mask;
611 memset(&ipv6, 0, sizeof(ipv6));
612 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
613 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
614 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
615 sizeof(ipv6.hdr.src_addr));
616 memcpy(&ipv6_mask.hdr.src_addr,
617 &rte_flow_item_ipv6_mask.hdr.src_addr,
618 sizeof(ipv6.hdr.src_addr));
620 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
621 sizeof(ipv6.hdr.dst_addr));
622 memcpy(&ipv6_mask.hdr.dst_addr,
623 &rte_flow_item_ipv6_mask.hdr.dst_addr,
624 sizeof(ipv6.hdr.dst_addr));
627 item.mask = &ipv6_mask;
628 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
629 MLX5_MODIFICATION_TYPE_SET, error);
633 * Convert modify-header set MAC address action to DV specification.
635 * @param[in,out] resource
636 * Pointer to the modify-header resource.
638 * Pointer to action specification.
640 * Pointer to the error structure.
643 * 0 on success, a negative errno value otherwise and rte_errno is set.
646 flow_dv_convert_action_modify_mac
647 (struct mlx5_flow_dv_modify_hdr_resource *resource,
648 const struct rte_flow_action *action,
649 struct rte_flow_error *error)
651 const struct rte_flow_action_set_mac *conf =
652 (const struct rte_flow_action_set_mac *)(action->conf);
653 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
654 struct rte_flow_item_eth eth;
655 struct rte_flow_item_eth eth_mask;
657 memset(ð, 0, sizeof(eth));
658 memset(ð_mask, 0, sizeof(eth_mask));
659 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
660 memcpy(ð.src.addr_bytes, &conf->mac_addr,
661 sizeof(eth.src.addr_bytes));
662 memcpy(ð_mask.src.addr_bytes,
663 &rte_flow_item_eth_mask.src.addr_bytes,
664 sizeof(eth_mask.src.addr_bytes));
666 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
667 sizeof(eth.dst.addr_bytes));
668 memcpy(ð_mask.dst.addr_bytes,
669 &rte_flow_item_eth_mask.dst.addr_bytes,
670 sizeof(eth_mask.dst.addr_bytes));
673 item.mask = ð_mask;
674 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
675 MLX5_MODIFICATION_TYPE_SET, error);
679 * Convert modify-header set VLAN VID action to DV specification.
681 * @param[in,out] resource
682 * Pointer to the modify-header resource.
684 * Pointer to action specification.
686 * Pointer to the error structure.
689 * 0 on success, a negative errno value otherwise and rte_errno is set.
692 flow_dv_convert_action_modify_vlan_vid
693 (struct mlx5_flow_dv_modify_hdr_resource *resource,
694 const struct rte_flow_action *action,
695 struct rte_flow_error *error)
697 const struct rte_flow_action_of_set_vlan_vid *conf =
698 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
699 int i = resource->actions_num;
700 struct mlx5_modification_cmd *actions = resource->actions;
701 struct field_modify_info *field = modify_vlan_out_first_vid;
703 if (i >= MLX5_MAX_MODIFY_NUM)
704 return rte_flow_error_set(error, EINVAL,
705 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
706 "too many items to modify");
707 actions[i] = (struct mlx5_modification_cmd) {
708 .action_type = MLX5_MODIFICATION_TYPE_SET,
710 .length = field->size,
711 .offset = field->offset,
713 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
714 actions[i].data1 = conf->vlan_vid;
715 actions[i].data1 = actions[i].data1 << 16;
716 resource->actions_num = ++i;
721 * Convert modify-header set TP action to DV specification.
723 * @param[in,out] resource
724 * Pointer to the modify-header resource.
726 * Pointer to action specification.
728 * Pointer to rte_flow_item objects list.
730 * Pointer to flow attributes structure.
731 * @param[in] dev_flow
732 * Pointer to the sub flow.
733 * @param[in] tunnel_decap
734 * Whether action is after tunnel decapsulation.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_tp
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_action *action,
745 const struct rte_flow_item *items,
746 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
747 bool tunnel_decap, struct rte_flow_error *error)
749 const struct rte_flow_action_set_tp *conf =
750 (const struct rte_flow_action_set_tp *)(action->conf);
751 struct rte_flow_item item;
752 struct rte_flow_item_udp udp;
753 struct rte_flow_item_udp udp_mask;
754 struct rte_flow_item_tcp tcp;
755 struct rte_flow_item_tcp tcp_mask;
756 struct field_modify_info *field;
759 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
761 memset(&udp, 0, sizeof(udp));
762 memset(&udp_mask, 0, sizeof(udp_mask));
763 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
764 udp.hdr.src_port = conf->port;
765 udp_mask.hdr.src_port =
766 rte_flow_item_udp_mask.hdr.src_port;
768 udp.hdr.dst_port = conf->port;
769 udp_mask.hdr.dst_port =
770 rte_flow_item_udp_mask.hdr.dst_port;
772 item.type = RTE_FLOW_ITEM_TYPE_UDP;
774 item.mask = &udp_mask;
777 MLX5_ASSERT(attr->tcp);
778 memset(&tcp, 0, sizeof(tcp));
779 memset(&tcp_mask, 0, sizeof(tcp_mask));
780 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
781 tcp.hdr.src_port = conf->port;
782 tcp_mask.hdr.src_port =
783 rte_flow_item_tcp_mask.hdr.src_port;
785 tcp.hdr.dst_port = conf->port;
786 tcp_mask.hdr.dst_port =
787 rte_flow_item_tcp_mask.hdr.dst_port;
789 item.type = RTE_FLOW_ITEM_TYPE_TCP;
791 item.mask = &tcp_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header set TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_action *action,
823 const struct rte_flow_item *items,
824 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
825 bool tunnel_decap, struct rte_flow_error *error)
827 const struct rte_flow_action_set_ttl *conf =
828 (const struct rte_flow_action_set_ttl *)(action->conf);
829 struct rte_flow_item item;
830 struct rte_flow_item_ipv4 ipv4;
831 struct rte_flow_item_ipv4 ipv4_mask;
832 struct rte_flow_item_ipv6 ipv6;
833 struct rte_flow_item_ipv6 ipv6_mask;
834 struct field_modify_info *field;
837 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
839 memset(&ipv4, 0, sizeof(ipv4));
840 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
841 ipv4.hdr.time_to_live = conf->ttl_value;
842 ipv4_mask.hdr.time_to_live = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
845 item.mask = &ipv4_mask;
848 MLX5_ASSERT(attr->ipv6);
849 memset(&ipv6, 0, sizeof(ipv6));
850 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
851 ipv6.hdr.hop_limits = conf->ttl_value;
852 ipv6_mask.hdr.hop_limits = 0xFF;
853 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
855 item.mask = &ipv6_mask;
858 return flow_dv_convert_modify_action(&item, field, NULL, resource,
859 MLX5_MODIFICATION_TYPE_SET, error);
863 * Convert modify-header decrement TTL action to DV specification.
865 * @param[in,out] resource
866 * Pointer to the modify-header resource.
868 * Pointer to action specification.
870 * Pointer to rte_flow_item objects list.
872 * Pointer to flow attributes structure.
873 * @param[in] dev_flow
874 * Pointer to the sub flow.
875 * @param[in] tunnel_decap
876 * Whether action is after tunnel decapsulation.
878 * Pointer to the error structure.
881 * 0 on success, a negative errno value otherwise and rte_errno is set.
884 flow_dv_convert_action_modify_dec_ttl
885 (struct mlx5_flow_dv_modify_hdr_resource *resource,
886 const struct rte_flow_item *items,
887 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
888 bool tunnel_decap, struct rte_flow_error *error)
890 struct rte_flow_item item;
891 struct rte_flow_item_ipv4 ipv4;
892 struct rte_flow_item_ipv4 ipv4_mask;
893 struct rte_flow_item_ipv6 ipv6;
894 struct rte_flow_item_ipv6 ipv6_mask;
895 struct field_modify_info *field;
898 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
900 memset(&ipv4, 0, sizeof(ipv4));
901 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
902 ipv4.hdr.time_to_live = 0xFF;
903 ipv4_mask.hdr.time_to_live = 0xFF;
904 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
906 item.mask = &ipv4_mask;
909 MLX5_ASSERT(attr->ipv6);
910 memset(&ipv6, 0, sizeof(ipv6));
911 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
912 ipv6.hdr.hop_limits = 0xFF;
913 ipv6_mask.hdr.hop_limits = 0xFF;
914 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
916 item.mask = &ipv6_mask;
919 return flow_dv_convert_modify_action(&item, field, NULL, resource,
920 MLX5_MODIFICATION_TYPE_ADD, error);
924 * Convert modify-header increment/decrement TCP Sequence number
925 * to DV specification.
927 * @param[in,out] resource
928 * Pointer to the modify-header resource.
930 * Pointer to action specification.
932 * Pointer to the error structure.
935 * 0 on success, a negative errno value otherwise and rte_errno is set.
938 flow_dv_convert_action_modify_tcp_seq
939 (struct mlx5_flow_dv_modify_hdr_resource *resource,
940 const struct rte_flow_action *action,
941 struct rte_flow_error *error)
943 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
944 uint64_t value = rte_be_to_cpu_32(*conf);
945 struct rte_flow_item item;
946 struct rte_flow_item_tcp tcp;
947 struct rte_flow_item_tcp tcp_mask;
949 memset(&tcp, 0, sizeof(tcp));
950 memset(&tcp_mask, 0, sizeof(tcp_mask));
951 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
953 * The HW has no decrement operation, only increment operation.
954 * To simulate decrement X from Y using increment operation
955 * we need to add UINT32_MAX X times to Y.
956 * Each adding of UINT32_MAX decrements Y by 1.
959 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
960 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
961 item.type = RTE_FLOW_ITEM_TYPE_TCP;
963 item.mask = &tcp_mask;
964 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
965 MLX5_MODIFICATION_TYPE_ADD, error);
969 * Convert modify-header increment/decrement TCP Acknowledgment number
970 * to DV specification.
972 * @param[in,out] resource
973 * Pointer to the modify-header resource.
975 * Pointer to action specification.
977 * Pointer to the error structure.
980 * 0 on success, a negative errno value otherwise and rte_errno is set.
983 flow_dv_convert_action_modify_tcp_ack
984 (struct mlx5_flow_dv_modify_hdr_resource *resource,
985 const struct rte_flow_action *action,
986 struct rte_flow_error *error)
988 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
989 uint64_t value = rte_be_to_cpu_32(*conf);
990 struct rte_flow_item item;
991 struct rte_flow_item_tcp tcp;
992 struct rte_flow_item_tcp tcp_mask;
994 memset(&tcp, 0, sizeof(tcp));
995 memset(&tcp_mask, 0, sizeof(tcp_mask));
996 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
998 * The HW has no decrement operation, only increment operation.
999 * To simulate decrement X from Y using increment operation
1000 * we need to add UINT32_MAX X times to Y.
1001 * Each adding of UINT32_MAX decrements Y by 1.
1003 value *= UINT32_MAX;
1004 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1005 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1006 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1008 item.mask = &tcp_mask;
1009 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1010 MLX5_MODIFICATION_TYPE_ADD, error);
1013 static enum mlx5_modification_field reg_to_field[] = {
1014 [REG_NON] = MLX5_MODI_OUT_NONE,
1015 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1016 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1017 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1018 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1019 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1020 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1021 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1022 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1023 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1024 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1028 * Convert register set to DV specification.
1030 * @param[in,out] resource
1031 * Pointer to the modify-header resource.
1033 * Pointer to action specification.
1035 * Pointer to the error structure.
1038 * 0 on success, a negative errno value otherwise and rte_errno is set.
1041 flow_dv_convert_action_set_reg
1042 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1043 const struct rte_flow_action *action,
1044 struct rte_flow_error *error)
1046 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1047 struct mlx5_modification_cmd *actions = resource->actions;
1048 uint32_t i = resource->actions_num;
1050 if (i >= MLX5_MAX_MODIFY_NUM)
1051 return rte_flow_error_set(error, EINVAL,
1052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1053 "too many items to modify");
1054 MLX5_ASSERT(conf->id != REG_NON);
1055 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1056 actions[i] = (struct mlx5_modification_cmd) {
1057 .action_type = MLX5_MODIFICATION_TYPE_SET,
1058 .field = reg_to_field[conf->id],
1059 .offset = conf->offset,
1060 .length = conf->length,
1062 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1063 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1065 resource->actions_num = i;
1070 * Convert SET_TAG action to DV specification.
1073 * Pointer to the rte_eth_dev structure.
1074 * @param[in,out] resource
1075 * Pointer to the modify-header resource.
1077 * Pointer to action specification.
1079 * Pointer to the error structure.
1082 * 0 on success, a negative errno value otherwise and rte_errno is set.
1085 flow_dv_convert_action_set_tag
1086 (struct rte_eth_dev *dev,
1087 struct mlx5_flow_dv_modify_hdr_resource *resource,
1088 const struct rte_flow_action_set_tag *conf,
1089 struct rte_flow_error *error)
1091 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1092 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1093 struct rte_flow_item item = {
1097 struct field_modify_info reg_c_x[] = {
1100 enum mlx5_modification_field reg_type;
1103 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1106 MLX5_ASSERT(ret != REG_NON);
1107 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1108 reg_type = reg_to_field[ret];
1109 MLX5_ASSERT(reg_type > 0);
1110 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1111 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1112 MLX5_MODIFICATION_TYPE_SET, error);
1116 * Convert internal COPY_REG action to DV specification.
1119 * Pointer to the rte_eth_dev structure.
1120 * @param[in,out] res
1121 * Pointer to the modify-header resource.
1123 * Pointer to action specification.
1125 * Pointer to the error structure.
1128 * 0 on success, a negative errno value otherwise and rte_errno is set.
1131 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1132 struct mlx5_flow_dv_modify_hdr_resource *res,
1133 const struct rte_flow_action *action,
1134 struct rte_flow_error *error)
1136 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1137 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1138 struct rte_flow_item item = {
1142 struct field_modify_info reg_src[] = {
1143 {4, 0, reg_to_field[conf->src]},
1146 struct field_modify_info reg_dst = {
1148 .id = reg_to_field[conf->dst],
1150 /* Adjust reg_c[0] usage according to reported mask. */
1151 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1152 struct mlx5_priv *priv = dev->data->dev_private;
1153 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1155 MLX5_ASSERT(reg_c0);
1156 MLX5_ASSERT(priv->sh->config.dv_xmeta_en !=
1157 MLX5_XMETA_MODE_LEGACY);
1158 if (conf->dst == REG_C_0) {
1159 /* Copy to reg_c[0], within mask only. */
1160 reg_dst.offset = rte_bsf32(reg_c0);
1161 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1164 mask = rte_cpu_to_be_32(reg_c0);
1167 return flow_dv_convert_modify_action(&item,
1168 reg_src, ®_dst, res,
1169 MLX5_MODIFICATION_TYPE_COPY,
1174 * Convert MARK action to DV specification. This routine is used
1175 * in extensive metadata only and requires metadata register to be
1176 * handled. In legacy mode hardware tag resource is engaged.
1179 * Pointer to the rte_eth_dev structure.
1181 * Pointer to MARK action specification.
1182 * @param[in,out] resource
1183 * Pointer to the modify-header resource.
1185 * Pointer to the error structure.
1188 * 0 on success, a negative errno value otherwise and rte_errno is set.
1191 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1192 const struct rte_flow_action_mark *conf,
1193 struct mlx5_flow_dv_modify_hdr_resource *resource,
1194 struct rte_flow_error *error)
1196 struct mlx5_priv *priv = dev->data->dev_private;
1197 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1198 priv->sh->dv_mark_mask);
1199 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1200 struct rte_flow_item item = {
1204 struct field_modify_info reg_c_x[] = {
1210 return rte_flow_error_set(error, EINVAL,
1211 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1212 NULL, "zero mark action mask");
1213 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1216 MLX5_ASSERT(reg > 0);
1217 if (reg == REG_C_0) {
1218 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1219 uint32_t shl_c0 = rte_bsf32(msk_c0);
1221 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1222 mask = rte_cpu_to_be_32(mask) & msk_c0;
1223 mask = rte_cpu_to_be_32(mask << shl_c0);
1225 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1226 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1227 MLX5_MODIFICATION_TYPE_SET, error);
1231 * Get metadata register index for specified steering domain.
1234 * Pointer to the rte_eth_dev structure.
1236 * Attributes of flow to determine steering domain.
1238 * Pointer to the error structure.
1241 * positive index on success, a negative errno value otherwise
1242 * and rte_errno is set.
1244 static enum modify_reg
1245 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1246 const struct rte_flow_attr *attr,
1247 struct rte_flow_error *error)
1250 mlx5_flow_get_reg_id(dev, attr->transfer ?
1254 MLX5_METADATA_RX, 0, error);
1256 return rte_flow_error_set(error,
1257 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1258 NULL, "unavailable "
1259 "metadata register");
1264 * Convert SET_META action to DV specification.
1267 * Pointer to the rte_eth_dev structure.
1268 * @param[in,out] resource
1269 * Pointer to the modify-header resource.
1271 * Attributes of flow that includes this item.
1273 * Pointer to action specification.
1275 * Pointer to the error structure.
1278 * 0 on success, a negative errno value otherwise and rte_errno is set.
1281 flow_dv_convert_action_set_meta
1282 (struct rte_eth_dev *dev,
1283 struct mlx5_flow_dv_modify_hdr_resource *resource,
1284 const struct rte_flow_attr *attr,
1285 const struct rte_flow_action_set_meta *conf,
1286 struct rte_flow_error *error)
1288 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1289 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1290 struct rte_flow_item item = {
1294 struct field_modify_info reg_c_x[] = {
1297 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1301 MLX5_ASSERT(reg != REG_NON);
1302 if (reg == REG_C_0) {
1303 struct mlx5_priv *priv = dev->data->dev_private;
1304 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1305 uint32_t shl_c0 = rte_bsf32(msk_c0);
1307 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1308 mask = rte_cpu_to_be_32(mask) & msk_c0;
1309 mask = rte_cpu_to_be_32(mask << shl_c0);
1311 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1312 /* The routine expects parameters in memory as big-endian ones. */
1313 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1314 MLX5_MODIFICATION_TYPE_SET, error);
1318 * Convert modify-header set IPv4 DSCP action to DV specification.
1320 * @param[in,out] resource
1321 * Pointer to the modify-header resource.
1323 * Pointer to action specification.
1325 * Pointer to the error structure.
1328 * 0 on success, a negative errno value otherwise and rte_errno is set.
1331 flow_dv_convert_action_modify_ipv4_dscp
1332 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1333 const struct rte_flow_action *action,
1334 struct rte_flow_error *error)
1336 const struct rte_flow_action_set_dscp *conf =
1337 (const struct rte_flow_action_set_dscp *)(action->conf);
1338 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1339 struct rte_flow_item_ipv4 ipv4;
1340 struct rte_flow_item_ipv4 ipv4_mask;
1342 memset(&ipv4, 0, sizeof(ipv4));
1343 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1344 ipv4.hdr.type_of_service = conf->dscp;
1345 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1347 item.mask = &ipv4_mask;
1348 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1349 MLX5_MODIFICATION_TYPE_SET, error);
1353 * Convert modify-header set IPv6 DSCP action to DV specification.
1355 * @param[in,out] resource
1356 * Pointer to the modify-header resource.
1358 * Pointer to action specification.
1360 * Pointer to the error structure.
1363 * 0 on success, a negative errno value otherwise and rte_errno is set.
1366 flow_dv_convert_action_modify_ipv6_dscp
1367 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1368 const struct rte_flow_action *action,
1369 struct rte_flow_error *error)
1371 const struct rte_flow_action_set_dscp *conf =
1372 (const struct rte_flow_action_set_dscp *)(action->conf);
1373 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1374 struct rte_flow_item_ipv6 ipv6;
1375 struct rte_flow_item_ipv6 ipv6_mask;
1377 memset(&ipv6, 0, sizeof(ipv6));
1378 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1380 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1381 * rdma-core only accept the DSCP bits byte aligned start from
1382 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1383 * bits in IPv6 case as rdma-core requires byte aligned value.
1385 ipv6.hdr.vtc_flow = conf->dscp;
1386 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1388 item.mask = &ipv6_mask;
1389 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1390 MLX5_MODIFICATION_TYPE_SET, error);
1394 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1395 enum rte_flow_field_id field, int inherit,
1396 const struct rte_flow_attr *attr,
1397 struct rte_flow_error *error)
1399 struct mlx5_priv *priv = dev->data->dev_private;
1402 case RTE_FLOW_FIELD_START:
1404 case RTE_FLOW_FIELD_MAC_DST:
1405 case RTE_FLOW_FIELD_MAC_SRC:
1407 case RTE_FLOW_FIELD_VLAN_TYPE:
1409 case RTE_FLOW_FIELD_VLAN_ID:
1411 case RTE_FLOW_FIELD_MAC_TYPE:
1413 case RTE_FLOW_FIELD_IPV4_DSCP:
1415 case RTE_FLOW_FIELD_IPV4_TTL:
1417 case RTE_FLOW_FIELD_IPV4_SRC:
1418 case RTE_FLOW_FIELD_IPV4_DST:
1420 case RTE_FLOW_FIELD_IPV6_DSCP:
1422 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1424 case RTE_FLOW_FIELD_IPV6_SRC:
1425 case RTE_FLOW_FIELD_IPV6_DST:
1427 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1428 case RTE_FLOW_FIELD_TCP_PORT_DST:
1430 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1431 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1433 case RTE_FLOW_FIELD_TCP_FLAGS:
1435 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1436 case RTE_FLOW_FIELD_UDP_PORT_DST:
1438 case RTE_FLOW_FIELD_VXLAN_VNI:
1439 case RTE_FLOW_FIELD_GENEVE_VNI:
1441 case RTE_FLOW_FIELD_GTP_TEID:
1442 case RTE_FLOW_FIELD_TAG:
1444 case RTE_FLOW_FIELD_MARK:
1445 return __builtin_popcount(priv->sh->dv_mark_mask);
1446 case RTE_FLOW_FIELD_META:
1447 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1448 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1449 case RTE_FLOW_FIELD_POINTER:
1450 case RTE_FLOW_FIELD_VALUE:
1451 return inherit < 0 ? 0 : inherit;
1459 mlx5_flow_field_id_to_modify_info
1460 (const struct rte_flow_action_modify_data *data,
1461 struct field_modify_info *info, uint32_t *mask,
1462 uint32_t width, struct rte_eth_dev *dev,
1463 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1465 struct mlx5_priv *priv = dev->data->dev_private;
1469 switch (data->field) {
1470 case RTE_FLOW_FIELD_START:
1471 /* not supported yet */
1474 case RTE_FLOW_FIELD_MAC_DST:
1475 off = data->offset > 16 ? data->offset - 16 : 0;
1477 if (data->offset < 16) {
1478 info[idx] = (struct field_modify_info){2, 4,
1479 MLX5_MODI_OUT_DMAC_15_0};
1481 mask[1] = rte_cpu_to_be_16(0xffff >>
1485 mask[1] = RTE_BE16(0xffff);
1492 info[idx] = (struct field_modify_info){4, 0,
1493 MLX5_MODI_OUT_DMAC_47_16};
1494 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1495 (32 - width)) << off);
1497 if (data->offset < 16)
1498 info[idx++] = (struct field_modify_info){2, 0,
1499 MLX5_MODI_OUT_DMAC_15_0};
1500 info[idx] = (struct field_modify_info){4, off,
1501 MLX5_MODI_OUT_DMAC_47_16};
1504 case RTE_FLOW_FIELD_MAC_SRC:
1505 off = data->offset > 16 ? data->offset - 16 : 0;
1507 if (data->offset < 16) {
1508 info[idx] = (struct field_modify_info){2, 4,
1509 MLX5_MODI_OUT_SMAC_15_0};
1511 mask[1] = rte_cpu_to_be_16(0xffff >>
1515 mask[1] = RTE_BE16(0xffff);
1522 info[idx] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SMAC_47_16};
1524 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1525 (32 - width)) << off);
1527 if (data->offset < 16)
1528 info[idx++] = (struct field_modify_info){2, 0,
1529 MLX5_MODI_OUT_SMAC_15_0};
1530 info[idx] = (struct field_modify_info){4, off,
1531 MLX5_MODI_OUT_SMAC_47_16};
1534 case RTE_FLOW_FIELD_VLAN_TYPE:
1535 /* not supported yet */
1537 case RTE_FLOW_FIELD_VLAN_ID:
1538 info[idx] = (struct field_modify_info){2, 0,
1539 MLX5_MODI_OUT_FIRST_VID};
1541 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1543 case RTE_FLOW_FIELD_MAC_TYPE:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_ETHERTYPE};
1547 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1549 case RTE_FLOW_FIELD_IPV4_DSCP:
1550 info[idx] = (struct field_modify_info){1, 0,
1551 MLX5_MODI_OUT_IP_DSCP};
1553 mask[idx] = 0x3f >> (6 - width);
1555 case RTE_FLOW_FIELD_IPV4_TTL:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IPV4_TTL};
1559 mask[idx] = 0xff >> (8 - width);
1561 case RTE_FLOW_FIELD_IPV4_SRC:
1562 info[idx] = (struct field_modify_info){4, 0,
1563 MLX5_MODI_OUT_SIPV4};
1565 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1568 case RTE_FLOW_FIELD_IPV4_DST:
1569 info[idx] = (struct field_modify_info){4, 0,
1570 MLX5_MODI_OUT_DIPV4};
1572 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1575 case RTE_FLOW_FIELD_IPV6_DSCP:
1576 info[idx] = (struct field_modify_info){1, 0,
1577 MLX5_MODI_OUT_IP_DSCP};
1579 mask[idx] = 0x3f >> (6 - width);
1581 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1585 mask[idx] = 0xff >> (8 - width);
1587 case RTE_FLOW_FIELD_IPV6_SRC:
1589 if (data->offset < 32) {
1590 info[idx] = (struct field_modify_info){4, 12,
1591 MLX5_MODI_OUT_SIPV6_31_0};
1594 rte_cpu_to_be_32(0xffffffff >>
1598 mask[3] = RTE_BE32(0xffffffff);
1605 if (data->offset < 64) {
1606 info[idx] = (struct field_modify_info){4, 8,
1607 MLX5_MODI_OUT_SIPV6_63_32};
1610 rte_cpu_to_be_32(0xffffffff >>
1614 mask[2] = RTE_BE32(0xffffffff);
1621 if (data->offset < 96) {
1622 info[idx] = (struct field_modify_info){4, 4,
1623 MLX5_MODI_OUT_SIPV6_95_64};
1626 rte_cpu_to_be_32(0xffffffff >>
1630 mask[1] = RTE_BE32(0xffffffff);
1637 info[idx] = (struct field_modify_info){4, 0,
1638 MLX5_MODI_OUT_SIPV6_127_96};
1639 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1641 if (data->offset < 32)
1642 info[idx++] = (struct field_modify_info){4, 0,
1643 MLX5_MODI_OUT_SIPV6_31_0};
1644 if (data->offset < 64)
1645 info[idx++] = (struct field_modify_info){4, 0,
1646 MLX5_MODI_OUT_SIPV6_63_32};
1647 if (data->offset < 96)
1648 info[idx++] = (struct field_modify_info){4, 0,
1649 MLX5_MODI_OUT_SIPV6_95_64};
1650 if (data->offset < 128)
1651 info[idx++] = (struct field_modify_info){4, 0,
1652 MLX5_MODI_OUT_SIPV6_127_96};
1655 case RTE_FLOW_FIELD_IPV6_DST:
1657 if (data->offset < 32) {
1658 info[idx] = (struct field_modify_info){4, 12,
1659 MLX5_MODI_OUT_DIPV6_31_0};
1662 rte_cpu_to_be_32(0xffffffff >>
1666 mask[3] = RTE_BE32(0xffffffff);
1673 if (data->offset < 64) {
1674 info[idx] = (struct field_modify_info){4, 8,
1675 MLX5_MODI_OUT_DIPV6_63_32};
1678 rte_cpu_to_be_32(0xffffffff >>
1682 mask[2] = RTE_BE32(0xffffffff);
1689 if (data->offset < 96) {
1690 info[idx] = (struct field_modify_info){4, 4,
1691 MLX5_MODI_OUT_DIPV6_95_64};
1694 rte_cpu_to_be_32(0xffffffff >>
1698 mask[1] = RTE_BE32(0xffffffff);
1705 info[idx] = (struct field_modify_info){4, 0,
1706 MLX5_MODI_OUT_DIPV6_127_96};
1707 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1709 if (data->offset < 32)
1710 info[idx++] = (struct field_modify_info){4, 0,
1711 MLX5_MODI_OUT_DIPV6_31_0};
1712 if (data->offset < 64)
1713 info[idx++] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_OUT_DIPV6_63_32};
1715 if (data->offset < 96)
1716 info[idx++] = (struct field_modify_info){4, 0,
1717 MLX5_MODI_OUT_DIPV6_95_64};
1718 if (data->offset < 128)
1719 info[idx++] = (struct field_modify_info){4, 0,
1720 MLX5_MODI_OUT_DIPV6_127_96};
1723 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1724 info[idx] = (struct field_modify_info){2, 0,
1725 MLX5_MODI_OUT_TCP_SPORT};
1727 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1729 case RTE_FLOW_FIELD_TCP_PORT_DST:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_DPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1736 info[idx] = (struct field_modify_info){4, 0,
1737 MLX5_MODI_OUT_TCP_SEQ_NUM};
1739 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1742 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1743 info[idx] = (struct field_modify_info){4, 0,
1744 MLX5_MODI_OUT_TCP_ACK_NUM};
1746 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1749 case RTE_FLOW_FIELD_TCP_FLAGS:
1750 info[idx] = (struct field_modify_info){2, 0,
1751 MLX5_MODI_OUT_TCP_FLAGS};
1753 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1755 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_UDP_SPORT};
1759 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_DST:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_DPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_VXLAN_VNI:
1768 /* not supported yet */
1770 case RTE_FLOW_FIELD_GENEVE_VNI:
1771 /* not supported yet*/
1773 case RTE_FLOW_FIELD_GTP_TEID:
1774 info[idx] = (struct field_modify_info){4, 0,
1775 MLX5_MODI_GTP_TEID};
1777 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1780 case RTE_FLOW_FIELD_TAG:
1782 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1783 data->level, error);
1786 MLX5_ASSERT(reg != REG_NON);
1787 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1788 info[idx] = (struct field_modify_info){4, 0,
1792 rte_cpu_to_be_32(0xffffffff >>
1796 case RTE_FLOW_FIELD_MARK:
1798 uint32_t mark_mask = priv->sh->dv_mark_mask;
1799 uint32_t mark_count = __builtin_popcount(mark_mask);
1800 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1804 MLX5_ASSERT(reg != REG_NON);
1805 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1806 info[idx] = (struct field_modify_info){4, 0,
1809 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1810 (mark_count - width)) & mark_mask);
1813 case RTE_FLOW_FIELD_META:
1815 uint32_t meta_mask = priv->sh->dv_meta_mask;
1816 uint32_t meta_count = __builtin_popcount(meta_mask);
1817 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1820 MLX5_ASSERT(reg != REG_NON);
1821 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1822 info[idx] = (struct field_modify_info){4, 0,
1825 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1826 (meta_count - width)) & meta_mask);
1829 case RTE_FLOW_FIELD_POINTER:
1830 case RTE_FLOW_FIELD_VALUE:
1838 * Convert modify_field action to DV specification.
1841 * Pointer to the rte_eth_dev structure.
1842 * @param[in,out] resource
1843 * Pointer to the modify-header resource.
1845 * Pointer to action specification.
1847 * Attributes of flow that includes this item.
1849 * Pointer to the error structure.
1852 * 0 on success, a negative errno value otherwise and rte_errno is set.
1855 flow_dv_convert_action_modify_field
1856 (struct rte_eth_dev *dev,
1857 struct mlx5_flow_dv_modify_hdr_resource *resource,
1858 const struct rte_flow_action *action,
1859 const struct rte_flow_attr *attr,
1860 struct rte_flow_error *error)
1862 const struct rte_flow_action_modify_field *conf =
1863 (const struct rte_flow_action_modify_field *)(action->conf);
1864 struct rte_flow_item item = {
1868 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1870 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1872 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1873 uint32_t type, meta = 0;
1875 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1876 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1877 type = MLX5_MODIFICATION_TYPE_SET;
1878 /** For SET fill the destination field (field) first. */
1879 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1882 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1883 (void *)(uintptr_t)conf->src.pvalue :
1884 (void *)(uintptr_t)&conf->src.value;
1885 if (conf->dst.field == RTE_FLOW_FIELD_META) {
1886 meta = *(const unaligned_uint32_t *)item.spec;
1887 meta = rte_cpu_to_be_32(meta);
1891 type = MLX5_MODIFICATION_TYPE_COPY;
1892 /** For COPY fill the destination field (dcopy) without mask. */
1893 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1896 /** Then construct the source field (field) with mask. */
1897 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1902 return flow_dv_convert_modify_action(&item,
1903 field, dcopy, resource, type, error);
1907 * Validate MARK item.
1910 * Pointer to the rte_eth_dev structure.
1912 * Item specification.
1914 * Attributes of flow that includes this item.
1916 * Pointer to error structure.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1923 const struct rte_flow_item *item,
1924 const struct rte_flow_attr *attr __rte_unused,
1925 struct rte_flow_error *error)
1927 struct mlx5_priv *priv = dev->data->dev_private;
1928 struct mlx5_sh_config *config = &priv->sh->config;
1929 const struct rte_flow_item_mark *spec = item->spec;
1930 const struct rte_flow_item_mark *mask = item->mask;
1931 const struct rte_flow_item_mark nic_mask = {
1932 .id = priv->sh->dv_mark_mask,
1936 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ITEM, item,
1939 "extended metadata feature"
1941 if (!mlx5_flow_ext_mreg_supported(dev))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM, item,
1944 "extended metadata register"
1945 " isn't supported");
1947 return rte_flow_error_set(error, ENOTSUP,
1948 RTE_FLOW_ERROR_TYPE_ITEM, item,
1949 "extended metadata register"
1950 " isn't available");
1951 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1955 return rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1958 "data cannot be empty");
1959 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1960 return rte_flow_error_set(error, EINVAL,
1961 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1963 "mark id exceeds the limit");
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1969 "mask cannot be zero");
1971 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1972 (const uint8_t *)&nic_mask,
1973 sizeof(struct rte_flow_item_mark),
1974 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1981 * Validate META item.
1984 * Pointer to the rte_eth_dev structure.
1986 * Item specification.
1988 * Attributes of flow that includes this item.
1990 * Pointer to error structure.
1993 * 0 on success, a negative errno value otherwise and rte_errno is set.
1996 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1997 const struct rte_flow_item *item,
1998 const struct rte_flow_attr *attr,
1999 struct rte_flow_error *error)
2001 struct mlx5_priv *priv = dev->data->dev_private;
2002 struct mlx5_sh_config *config = &priv->sh->config;
2003 const struct rte_flow_item_meta *spec = item->spec;
2004 const struct rte_flow_item_meta *mask = item->mask;
2005 struct rte_flow_item_meta nic_mask = {
2012 return rte_flow_error_set(error, EINVAL,
2013 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2015 "data cannot be empty");
2016 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2017 if (!mlx5_flow_ext_mreg_supported(dev))
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ITEM, item,
2020 "extended metadata register"
2021 " isn't supported");
2022 reg = flow_dv_get_metadata_reg(dev, attr, error);
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ITEM, item,
2028 "unavailable extended metadata register");
2030 return rte_flow_error_set(error, ENOTSUP,
2031 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 nic_mask.data = priv->sh->dv_meta_mask;
2038 return rte_flow_error_set(error, ENOTSUP,
2039 RTE_FLOW_ERROR_TYPE_ITEM, item,
2040 "extended metadata feature "
2041 "should be enabled when "
2042 "meta item is requested "
2043 "with e-switch mode ");
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "match on metadata for ingress "
2048 "is not supported in legacy "
2052 mask = &rte_flow_item_meta_mask;
2054 return rte_flow_error_set(error, EINVAL,
2055 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2056 "mask cannot be zero");
2058 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2059 (const uint8_t *)&nic_mask,
2060 sizeof(struct rte_flow_item_meta),
2061 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066 * Validate TAG item.
2069 * Pointer to the rte_eth_dev structure.
2071 * Item specification.
2073 * Attributes of flow that includes this item.
2075 * Pointer to error structure.
2078 * 0 on success, a negative errno value otherwise and rte_errno is set.
2081 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2082 const struct rte_flow_item *item,
2083 const struct rte_flow_attr *attr __rte_unused,
2084 struct rte_flow_error *error)
2086 const struct rte_flow_item_tag *spec = item->spec;
2087 const struct rte_flow_item_tag *mask = item->mask;
2088 const struct rte_flow_item_tag nic_mask = {
2089 .data = RTE_BE32(UINT32_MAX),
2094 if (!mlx5_flow_ext_mreg_supported(dev))
2095 return rte_flow_error_set(error, ENOTSUP,
2096 RTE_FLOW_ERROR_TYPE_ITEM, item,
2097 "extensive metadata register"
2098 " isn't supported");
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2103 "data cannot be empty");
2105 mask = &rte_flow_item_tag_mask;
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2109 "mask cannot be zero");
2111 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2112 (const uint8_t *)&nic_mask,
2113 sizeof(struct rte_flow_item_tag),
2114 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2117 if (mask->index != 0xff)
2118 return rte_flow_error_set(error, EINVAL,
2119 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2120 "partial mask for tag index"
2121 " is not supported");
2122 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2125 MLX5_ASSERT(ret != REG_NON);
2130 * Validate vport item.
2133 * Pointer to the rte_eth_dev structure.
2135 * Item specification.
2137 * Attributes of flow that includes this item.
2138 * @param[in] item_flags
2139 * Bit-fields that holds the items detected until now.
2141 * Pointer to error structure.
2144 * 0 on success, a negative errno value otherwise and rte_errno is set.
2147 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2148 const struct rte_flow_item *item,
2149 const struct rte_flow_attr *attr,
2150 uint64_t item_flags,
2151 struct rte_flow_error *error)
2153 const struct rte_flow_item_port_id *spec = item->spec;
2154 const struct rte_flow_item_port_id *mask = item->mask;
2155 const struct rte_flow_item_port_id switch_mask = {
2158 struct mlx5_priv *esw_priv;
2159 struct mlx5_priv *dev_priv;
2162 if (!attr->transfer)
2163 return rte_flow_error_set(error, EINVAL,
2164 RTE_FLOW_ERROR_TYPE_ITEM,
2166 "match on port id is valid only"
2167 " when transfer flag is enabled");
2168 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2169 return rte_flow_error_set(error, ENOTSUP,
2170 RTE_FLOW_ERROR_TYPE_ITEM, item,
2171 "multiple source ports are not"
2174 mask = &switch_mask;
2175 if (mask->id != 0xffffffff)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2179 "no support for partial mask on"
2181 ret = mlx5_flow_item_acceptable
2182 (item, (const uint8_t *)mask,
2183 (const uint8_t *)&rte_flow_item_port_id_mask,
2184 sizeof(struct rte_flow_item_port_id),
2185 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2190 if (spec->id == MLX5_PORT_ESW_MGR)
2192 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2194 return rte_flow_error_set(error, rte_errno,
2195 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2196 "failed to obtain E-Switch info for"
2198 dev_priv = mlx5_dev_to_eswitch_info(dev);
2200 return rte_flow_error_set(error, rte_errno,
2201 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2203 "failed to obtain E-Switch info");
2204 if (esw_priv->domain_id != dev_priv->domain_id)
2205 return rte_flow_error_set(error, EINVAL,
2206 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2207 "cannot match on a port from a"
2208 " different E-Switch");
2213 * Validate VLAN item.
2216 * Item specification.
2217 * @param[in] item_flags
2218 * Bit-fields that holds the items detected until now.
2220 * Ethernet device flow is being created on.
2222 * Pointer to error structure.
2225 * 0 on success, a negative errno value otherwise and rte_errno is set.
2228 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2229 uint64_t item_flags,
2230 struct rte_eth_dev *dev,
2231 struct rte_flow_error *error)
2233 const struct rte_flow_item_vlan *mask = item->mask;
2234 const struct rte_flow_item_vlan nic_mask = {
2235 .tci = RTE_BE16(UINT16_MAX),
2236 .inner_type = RTE_BE16(UINT16_MAX),
2239 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2241 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2242 MLX5_FLOW_LAYER_INNER_L4) :
2243 (MLX5_FLOW_LAYER_OUTER_L3 |
2244 MLX5_FLOW_LAYER_OUTER_L4);
2245 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2246 MLX5_FLOW_LAYER_OUTER_VLAN;
2248 if (item_flags & vlanm)
2249 return rte_flow_error_set(error, EINVAL,
2250 RTE_FLOW_ERROR_TYPE_ITEM, item,
2251 "multiple VLAN layers not supported");
2252 else if ((item_flags & l34m) != 0)
2253 return rte_flow_error_set(error, EINVAL,
2254 RTE_FLOW_ERROR_TYPE_ITEM, item,
2255 "VLAN cannot follow L3/L4 layer");
2257 mask = &rte_flow_item_vlan_mask;
2258 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2259 (const uint8_t *)&nic_mask,
2260 sizeof(struct rte_flow_item_vlan),
2261 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2264 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2265 struct mlx5_priv *priv = dev->data->dev_private;
2267 if (priv->vmwa_context) {
2269 * Non-NULL context means we have a virtual machine
2270 * and SR-IOV enabled, we have to create VLAN interface
2271 * to make hypervisor to setup E-Switch vport
2272 * context correctly. We avoid creating the multiple
2273 * VLAN interfaces, so we cannot support VLAN tag mask.
2275 return rte_flow_error_set(error, EINVAL,
2276 RTE_FLOW_ERROR_TYPE_ITEM,
2278 "VLAN tag mask is not"
2279 " supported in virtual"
2287 * GTP flags are contained in 1 byte of the format:
2288 * -------------------------------------------
2289 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2290 * |-----------------------------------------|
2291 * | value | Version | PT | Res | E | S | PN |
2292 * -------------------------------------------
2294 * Matching is supported only for GTP flags E, S, PN.
2296 #define MLX5_GTP_FLAGS_MASK 0x07
2299 * Validate GTP item.
2302 * Pointer to the rte_eth_dev structure.
2304 * Item specification.
2305 * @param[in] item_flags
2306 * Bit-fields that holds the items detected until now.
2308 * Pointer to error structure.
2311 * 0 on success, a negative errno value otherwise and rte_errno is set.
2314 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2315 const struct rte_flow_item *item,
2316 uint64_t item_flags,
2317 struct rte_flow_error *error)
2319 struct mlx5_priv *priv = dev->data->dev_private;
2320 const struct rte_flow_item_gtp *spec = item->spec;
2321 const struct rte_flow_item_gtp *mask = item->mask;
2322 const struct rte_flow_item_gtp nic_mask = {
2323 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2325 .teid = RTE_BE32(0xffffffff),
2328 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_gtp)
2329 return rte_flow_error_set(error, ENOTSUP,
2330 RTE_FLOW_ERROR_TYPE_ITEM, item,
2331 "GTP support is not enabled");
2332 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2333 return rte_flow_error_set(error, ENOTSUP,
2334 RTE_FLOW_ERROR_TYPE_ITEM, item,
2335 "multiple tunnel layers not"
2337 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2338 return rte_flow_error_set(error, EINVAL,
2339 RTE_FLOW_ERROR_TYPE_ITEM, item,
2340 "no outer UDP layer found");
2342 mask = &rte_flow_item_gtp_mask;
2343 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2344 return rte_flow_error_set(error, ENOTSUP,
2345 RTE_FLOW_ERROR_TYPE_ITEM, item,
2346 "Match is supported for GTP"
2348 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2349 (const uint8_t *)&nic_mask,
2350 sizeof(struct rte_flow_item_gtp),
2351 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2355 * Validate GTP PSC item.
2358 * Item specification.
2359 * @param[in] last_item
2360 * Previous validated item in the pattern items.
2361 * @param[in] gtp_item
2362 * Previous GTP item specification.
2364 * Pointer to flow attributes.
2366 * Pointer to error structure.
2369 * 0 on success, a negative errno value otherwise and rte_errno is set.
2372 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2374 const struct rte_flow_item *gtp_item,
2375 const struct rte_flow_attr *attr,
2376 struct rte_flow_error *error)
2378 const struct rte_flow_item_gtp *gtp_spec;
2379 const struct rte_flow_item_gtp *gtp_mask;
2380 const struct rte_flow_item_gtp_psc *mask;
2381 const struct rte_flow_item_gtp_psc nic_mask = {
2386 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2387 return rte_flow_error_set
2388 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2389 "GTP PSC item must be preceded with GTP item");
2390 gtp_spec = gtp_item->spec;
2391 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2392 /* GTP spec and E flag is requested to match zero. */
2394 (gtp_mask->v_pt_rsv_flags &
2395 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2396 return rte_flow_error_set
2397 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2398 "GTP E flag must be 1 to match GTP PSC");
2399 /* Check the flow is not created in group zero. */
2400 if (!attr->transfer && !attr->group)
2401 return rte_flow_error_set
2402 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2403 "GTP PSC is not supported for group 0");
2404 /* GTP spec is here and E flag is requested to match zero. */
2407 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2408 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2409 (const uint8_t *)&nic_mask,
2410 sizeof(struct rte_flow_item_gtp_psc),
2411 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2415 * Validate IPV4 item.
2416 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2417 * add specific validation of fragment_offset field,
2420 * Item specification.
2421 * @param[in] item_flags
2422 * Bit-fields that holds the items detected until now.
2424 * Pointer to error structure.
2427 * 0 on success, a negative errno value otherwise and rte_errno is set.
2430 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2431 const struct rte_flow_item *item,
2432 uint64_t item_flags, uint64_t last_item,
2433 uint16_t ether_type, struct rte_flow_error *error)
2436 struct mlx5_priv *priv = dev->data->dev_private;
2437 struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
2438 const struct rte_flow_item_ipv4 *spec = item->spec;
2439 const struct rte_flow_item_ipv4 *last = item->last;
2440 const struct rte_flow_item_ipv4 *mask = item->mask;
2441 rte_be16_t fragment_offset_spec = 0;
2442 rte_be16_t fragment_offset_last = 0;
2443 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2445 .src_addr = RTE_BE32(0xffffffff),
2446 .dst_addr = RTE_BE32(0xffffffff),
2447 .type_of_service = 0xff,
2448 .fragment_offset = RTE_BE16(0xffff),
2449 .next_proto_id = 0xff,
2450 .time_to_live = 0xff,
2454 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2455 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2456 bool ihl_cap = !tunnel ?
2457 attr->outer_ipv4_ihl : attr->inner_ipv4_ihl;
2459 return rte_flow_error_set(error, ENOTSUP,
2460 RTE_FLOW_ERROR_TYPE_ITEM,
2462 "IPV4 ihl offload not supported");
2463 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2465 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2466 ether_type, &nic_ipv4_mask,
2467 MLX5_ITEM_RANGE_ACCEPTED, error);
2471 fragment_offset_spec = spec->hdr.fragment_offset &
2472 mask->hdr.fragment_offset;
2473 if (!fragment_offset_spec)
2476 * spec and mask are valid, enforce using full mask to make sure the
2477 * complete value is used correctly.
2479 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2480 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2481 return rte_flow_error_set(error, EINVAL,
2482 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483 item, "must use full mask for"
2484 " fragment_offset");
2486 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2487 * indicating this is 1st fragment of fragmented packet.
2488 * This is not yet supported in MLX5, return appropriate error message.
2490 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2491 return rte_flow_error_set(error, ENOTSUP,
2492 RTE_FLOW_ERROR_TYPE_ITEM, item,
2493 "match on first fragment not "
2495 if (fragment_offset_spec && !last)
2496 return rte_flow_error_set(error, ENOTSUP,
2497 RTE_FLOW_ERROR_TYPE_ITEM, item,
2498 "specified value not supported");
2499 /* spec and last are valid, validate the specified range. */
2500 fragment_offset_last = last->hdr.fragment_offset &
2501 mask->hdr.fragment_offset;
2503 * Match on fragment_offset spec 0x2001 and last 0x3fff
2504 * means MF is 1 and frag-offset is > 0.
2505 * This packet is fragment 2nd and onward, excluding last.
2506 * This is not yet supported in MLX5, return appropriate
2509 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2510 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2511 return rte_flow_error_set(error, ENOTSUP,
2512 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2513 last, "match on following "
2514 "fragments not supported");
2516 * Match on fragment_offset spec 0x0001 and last 0x1fff
2517 * means MF is 0 and frag-offset is > 0.
2518 * This packet is last fragment of fragmented packet.
2519 * This is not yet supported in MLX5, return appropriate
2522 if (fragment_offset_spec == RTE_BE16(1) &&
2523 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2524 return rte_flow_error_set(error, ENOTSUP,
2525 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2526 last, "match on last "
2527 "fragment not supported");
2529 * Match on fragment_offset spec 0x0001 and last 0x3fff
2530 * means MF and/or frag-offset is not 0.
2531 * This is a fragmented packet.
2532 * Other range values are invalid and rejected.
2534 if (!(fragment_offset_spec == RTE_BE16(1) &&
2535 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2536 return rte_flow_error_set(error, ENOTSUP,
2537 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2538 "specified range not supported");
2543 * Validate IPV6 fragment extension item.
2546 * Item specification.
2547 * @param[in] item_flags
2548 * Bit-fields that holds the items detected until now.
2550 * Pointer to error structure.
2553 * 0 on success, a negative errno value otherwise and rte_errno is set.
2556 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2557 uint64_t item_flags,
2558 struct rte_flow_error *error)
2560 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2561 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2562 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2563 rte_be16_t frag_data_spec = 0;
2564 rte_be16_t frag_data_last = 0;
2565 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2566 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2567 MLX5_FLOW_LAYER_OUTER_L4;
2569 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2571 .next_header = 0xff,
2572 .frag_data = RTE_BE16(0xffff),
2576 if (item_flags & l4m)
2577 return rte_flow_error_set(error, EINVAL,
2578 RTE_FLOW_ERROR_TYPE_ITEM, item,
2579 "ipv6 fragment extension item cannot "
2581 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2582 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item must "
2586 "follow ipv6 item");
2588 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2589 if (!frag_data_spec)
2592 * spec and mask are valid, enforce using full mask to make sure the
2593 * complete value is used correctly.
2595 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2596 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2597 return rte_flow_error_set(error, EINVAL,
2598 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2599 item, "must use full mask for"
2602 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2603 * This is 1st fragment of fragmented packet.
2605 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2606 return rte_flow_error_set(error, ENOTSUP,
2607 RTE_FLOW_ERROR_TYPE_ITEM, item,
2608 "match on first fragment not "
2610 if (frag_data_spec && !last)
2611 return rte_flow_error_set(error, EINVAL,
2612 RTE_FLOW_ERROR_TYPE_ITEM, item,
2613 "specified value not supported");
2614 ret = mlx5_flow_item_acceptable
2615 (item, (const uint8_t *)mask,
2616 (const uint8_t *)&nic_mask,
2617 sizeof(struct rte_flow_item_ipv6_frag_ext),
2618 MLX5_ITEM_RANGE_ACCEPTED, error);
2621 /* spec and last are valid, validate the specified range. */
2622 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2624 * Match on frag_data spec 0x0009 and last 0xfff9
2625 * means M is 1 and frag-offset is > 0.
2626 * This packet is fragment 2nd and onward, excluding last.
2627 * This is not yet supported in MLX5, return appropriate
2630 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2631 RTE_IPV6_EHDR_MF_MASK) &&
2632 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2633 return rte_flow_error_set(error, ENOTSUP,
2634 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2635 last, "match on following "
2636 "fragments not supported");
2638 * Match on frag_data spec 0x0008 and last 0xfff8
2639 * means M is 0 and frag-offset is > 0.
2640 * This packet is last fragment of fragmented packet.
2641 * This is not yet supported in MLX5, return appropriate
2644 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2645 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2646 return rte_flow_error_set(error, ENOTSUP,
2647 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2648 last, "match on last "
2649 "fragment not supported");
2650 /* Other range values are invalid and rejected. */
2651 return rte_flow_error_set(error, EINVAL,
2652 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2653 "specified range not supported");
2657 * Validate ASO CT item.
2660 * Pointer to the rte_eth_dev structure.
2662 * Item specification.
2663 * @param[in] item_flags
2664 * Pointer to bit-fields that holds the items detected until now.
2666 * Pointer to error structure.
2669 * 0 on success, a negative errno value otherwise and rte_errno is set.
2672 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2673 const struct rte_flow_item *item,
2674 uint64_t *item_flags,
2675 struct rte_flow_error *error)
2677 const struct rte_flow_item_conntrack *spec = item->spec;
2678 const struct rte_flow_item_conntrack *mask = item->mask;
2682 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2683 return rte_flow_error_set(error, EINVAL,
2684 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2685 "Only one CT is supported");
2687 mask = &rte_flow_item_conntrack_mask;
2688 flags = spec->flags & mask->flags;
2689 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2690 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2691 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2692 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2693 return rte_flow_error_set(error, EINVAL,
2694 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2695 "Conflict status bits");
2696 /* State change also needs to be considered. */
2697 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2702 * Validate the pop VLAN action.
2705 * Pointer to the rte_eth_dev structure.
2706 * @param[in] action_flags
2707 * Holds the actions detected until now.
2709 * Pointer to the pop vlan action.
2710 * @param[in] item_flags
2711 * The items found in this flow rule.
2713 * Pointer to flow attributes.
2715 * Pointer to error structure.
2718 * 0 on success, a negative errno value otherwise and rte_errno is set.
2721 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2722 uint64_t action_flags,
2723 const struct rte_flow_action *action,
2724 uint64_t item_flags,
2725 const struct rte_flow_attr *attr,
2726 struct rte_flow_error *error)
2728 const struct mlx5_priv *priv = dev->data->dev_private;
2729 struct mlx5_dev_ctx_shared *sh = priv->sh;
2730 bool direction_error = false;
2732 if (!priv->sh->pop_vlan_action)
2733 return rte_flow_error_set(error, ENOTSUP,
2734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2736 "pop vlan action is not supported");
2737 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2738 if (attr->transfer) {
2739 bool fdb_tx = priv->representor_id != UINT16_MAX;
2740 bool is_cx5 = sh->steering_format_version ==
2741 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2743 if (fdb_tx && is_cx5)
2744 direction_error = true;
2745 } else if (attr->egress) {
2746 direction_error = true;
2748 if (direction_error)
2749 return rte_flow_error_set(error, ENOTSUP,
2750 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2752 "pop vlan action not supported for egress");
2753 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2754 return rte_flow_error_set(error, ENOTSUP,
2755 RTE_FLOW_ERROR_TYPE_ACTION, action,
2756 "no support for multiple VLAN "
2758 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2759 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2760 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2761 return rte_flow_error_set(error, ENOTSUP,
2762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2764 "cannot pop vlan after decap without "
2765 "match on inner vlan in the flow");
2766 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2767 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2768 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2769 return rte_flow_error_set(error, ENOTSUP,
2770 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2772 "cannot pop vlan without a "
2773 "match on (outer) vlan in the flow");
2774 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2775 return rte_flow_error_set(error, EINVAL,
2776 RTE_FLOW_ERROR_TYPE_ACTION, action,
2777 "wrong action order, port_id should "
2778 "be after pop VLAN action");
2779 if (!attr->transfer && priv->representor)
2780 return rte_flow_error_set(error, ENOTSUP,
2781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2782 "pop vlan action for VF representor "
2783 "not supported on NIC table");
2788 * Get VLAN default info from vlan match info.
2791 * the list of item specifications.
2793 * pointer VLAN info to fill to.
2796 * 0 on success, a negative errno value otherwise and rte_errno is set.
2799 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2800 struct rte_vlan_hdr *vlan)
2802 const struct rte_flow_item_vlan nic_mask = {
2803 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2804 MLX5DV_FLOW_VLAN_VID_MASK),
2805 .inner_type = RTE_BE16(0xffff),
2810 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2811 int type = items->type;
2813 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2814 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2817 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2818 const struct rte_flow_item_vlan *vlan_m = items->mask;
2819 const struct rte_flow_item_vlan *vlan_v = items->spec;
2821 /* If VLAN item in pattern doesn't contain data, return here. */
2826 /* Only full match values are accepted */
2827 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2828 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2829 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2831 rte_be_to_cpu_16(vlan_v->tci &
2832 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2834 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2835 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2836 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2838 rte_be_to_cpu_16(vlan_v->tci &
2839 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2841 if (vlan_m->inner_type == nic_mask.inner_type)
2842 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2843 vlan_m->inner_type);
2848 * Validate the push VLAN action.
2851 * Pointer to the rte_eth_dev structure.
2852 * @param[in] action_flags
2853 * Holds the actions detected until now.
2854 * @param[in] item_flags
2855 * The items found in this flow rule.
2857 * Pointer to the action structure.
2859 * Pointer to flow attributes
2861 * Pointer to error structure.
2864 * 0 on success, a negative errno value otherwise and rte_errno is set.
2867 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2868 uint64_t action_flags,
2869 const struct rte_flow_item_vlan *vlan_m,
2870 const struct rte_flow_action *action,
2871 const struct rte_flow_attr *attr,
2872 struct rte_flow_error *error)
2874 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2875 const struct mlx5_priv *priv = dev->data->dev_private;
2876 struct mlx5_dev_ctx_shared *sh = priv->sh;
2877 bool direction_error = false;
2879 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2880 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2881 return rte_flow_error_set(error, EINVAL,
2882 RTE_FLOW_ERROR_TYPE_ACTION, action,
2883 "invalid vlan ethertype");
2884 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2885 return rte_flow_error_set(error, EINVAL,
2886 RTE_FLOW_ERROR_TYPE_ACTION, action,
2887 "wrong action order, port_id should "
2888 "be after push VLAN");
2889 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2890 if (attr->transfer) {
2891 bool fdb_tx = priv->representor_id != UINT16_MAX;
2892 bool is_cx5 = sh->steering_format_version ==
2893 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2895 if (!fdb_tx && is_cx5)
2896 direction_error = true;
2897 } else if (attr->ingress) {
2898 direction_error = true;
2900 if (direction_error)
2901 return rte_flow_error_set(error, ENOTSUP,
2902 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2904 "push vlan action not supported for ingress");
2905 if (!attr->transfer && priv->representor)
2906 return rte_flow_error_set(error, ENOTSUP,
2907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2908 "push vlan action for VF representor "
2909 "not supported on NIC table");
2911 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2912 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2913 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2914 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2915 !(mlx5_flow_find_action
2916 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2917 return rte_flow_error_set(error, EINVAL,
2918 RTE_FLOW_ERROR_TYPE_ACTION, action,
2919 "not full match mask on VLAN PCP and "
2920 "there is no of_set_vlan_pcp action, "
2921 "push VLAN action cannot figure out "
2924 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2925 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2926 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2927 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2928 !(mlx5_flow_find_action
2929 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2930 return rte_flow_error_set(error, EINVAL,
2931 RTE_FLOW_ERROR_TYPE_ACTION, action,
2932 "not full match mask on VLAN VID and "
2933 "there is no of_set_vlan_vid action, "
2934 "push VLAN action cannot figure out "
2941 * Validate the set VLAN PCP.
2943 * @param[in] action_flags
2944 * Holds the actions detected until now.
2945 * @param[in] actions
2946 * Pointer to the list of actions remaining in the flow rule.
2948 * Pointer to error structure.
2951 * 0 on success, a negative errno value otherwise and rte_errno is set.
2954 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2955 const struct rte_flow_action actions[],
2956 struct rte_flow_error *error)
2958 const struct rte_flow_action *action = actions;
2959 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2961 if (conf->vlan_pcp > 7)
2962 return rte_flow_error_set(error, EINVAL,
2963 RTE_FLOW_ERROR_TYPE_ACTION, action,
2964 "VLAN PCP value is too big");
2965 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2966 return rte_flow_error_set(error, ENOTSUP,
2967 RTE_FLOW_ERROR_TYPE_ACTION, action,
2968 "set VLAN PCP action must follow "
2969 "the push VLAN action");
2970 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2971 return rte_flow_error_set(error, ENOTSUP,
2972 RTE_FLOW_ERROR_TYPE_ACTION, action,
2973 "Multiple VLAN PCP modification are "
2975 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2976 return rte_flow_error_set(error, EINVAL,
2977 RTE_FLOW_ERROR_TYPE_ACTION, action,
2978 "wrong action order, port_id should "
2979 "be after set VLAN PCP");
2984 * Validate the set VLAN VID.
2986 * @param[in] item_flags
2987 * Holds the items detected in this rule.
2988 * @param[in] action_flags
2989 * Holds the actions detected until now.
2990 * @param[in] actions
2991 * Pointer to the list of actions remaining in the flow rule.
2993 * Pointer to error structure.
2996 * 0 on success, a negative errno value otherwise and rte_errno is set.
2999 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3000 uint64_t action_flags,
3001 const struct rte_flow_action actions[],
3002 struct rte_flow_error *error)
3004 const struct rte_flow_action *action = actions;
3005 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3007 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3008 return rte_flow_error_set(error, EINVAL,
3009 RTE_FLOW_ERROR_TYPE_ACTION, action,
3010 "VLAN VID value is too big");
3011 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3012 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3013 return rte_flow_error_set(error, ENOTSUP,
3014 RTE_FLOW_ERROR_TYPE_ACTION, action,
3015 "set VLAN VID action must follow push"
3016 " VLAN action or match on VLAN item");
3017 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3018 return rte_flow_error_set(error, ENOTSUP,
3019 RTE_FLOW_ERROR_TYPE_ACTION, action,
3020 "Multiple VLAN VID modifications are "
3022 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3023 return rte_flow_error_set(error, EINVAL,
3024 RTE_FLOW_ERROR_TYPE_ACTION, action,
3025 "wrong action order, port_id should "
3026 "be after set VLAN VID");
3031 * Validate the FLAG action.
3034 * Pointer to the rte_eth_dev structure.
3035 * @param[in] action_flags
3036 * Holds the actions detected until now.
3038 * Pointer to flow attributes
3040 * Pointer to error structure.
3043 * 0 on success, a negative errno value otherwise and rte_errno is set.
3046 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3047 uint64_t action_flags,
3048 const struct rte_flow_attr *attr,
3049 struct rte_flow_error *error)
3051 struct mlx5_priv *priv = dev->data->dev_private;
3052 struct mlx5_sh_config *config = &priv->sh->config;
3055 /* Fall back if no extended metadata register support. */
3056 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3057 return mlx5_flow_validate_action_flag(action_flags, attr,
3059 /* Extensive metadata mode requires registers. */
3060 if (!mlx5_flow_ext_mreg_supported(dev))
3061 return rte_flow_error_set(error, ENOTSUP,
3062 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3063 "no metadata registers "
3064 "to support flag action");
3065 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3066 return rte_flow_error_set(error, ENOTSUP,
3067 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3068 "extended metadata register"
3069 " isn't available");
3070 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3073 MLX5_ASSERT(ret > 0);
3074 if (action_flags & MLX5_FLOW_ACTION_MARK)
3075 return rte_flow_error_set(error, EINVAL,
3076 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3077 "can't mark and flag in same flow");
3078 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3079 return rte_flow_error_set(error, EINVAL,
3080 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3082 " actions in same flow");
3087 * Validate MARK action.
3090 * Pointer to the rte_eth_dev structure.
3092 * Pointer to action.
3093 * @param[in] action_flags
3094 * Holds the actions detected until now.
3096 * Pointer to flow attributes
3098 * Pointer to error structure.
3101 * 0 on success, a negative errno value otherwise and rte_errno is set.
3104 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3105 const struct rte_flow_action *action,
3106 uint64_t action_flags,
3107 const struct rte_flow_attr *attr,
3108 struct rte_flow_error *error)
3110 struct mlx5_priv *priv = dev->data->dev_private;
3111 struct mlx5_sh_config *config = &priv->sh->config;
3112 const struct rte_flow_action_mark *mark = action->conf;
3115 if (is_tunnel_offload_active(dev))
3116 return rte_flow_error_set(error, ENOTSUP,
3117 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3119 "if tunnel offload active");
3120 /* Fall back if no extended metadata register support. */
3121 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3122 return mlx5_flow_validate_action_mark(action, action_flags,
3124 /* Extensive metadata mode requires registers. */
3125 if (!mlx5_flow_ext_mreg_supported(dev))
3126 return rte_flow_error_set(error, ENOTSUP,
3127 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3128 "no metadata registers "
3129 "to support mark action");
3130 if (!priv->sh->dv_mark_mask)
3131 return rte_flow_error_set(error, ENOTSUP,
3132 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3133 "extended metadata register"
3134 " isn't available");
3135 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3138 MLX5_ASSERT(ret > 0);
3140 return rte_flow_error_set(error, EINVAL,
3141 RTE_FLOW_ERROR_TYPE_ACTION, action,
3142 "configuration cannot be null");
3143 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3144 return rte_flow_error_set(error, EINVAL,
3145 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3147 "mark id exceeds the limit");
3148 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3149 return rte_flow_error_set(error, EINVAL,
3150 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3151 "can't flag and mark in same flow");
3152 if (action_flags & MLX5_FLOW_ACTION_MARK)
3153 return rte_flow_error_set(error, EINVAL,
3154 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3155 "can't have 2 mark actions in same"
3161 * Validate SET_META action.
3164 * Pointer to the rte_eth_dev structure.
3166 * Pointer to the action structure.
3167 * @param[in] action_flags
3168 * Holds the actions detected until now.
3170 * Pointer to flow attributes
3172 * Pointer to error structure.
3175 * 0 on success, a negative errno value otherwise and rte_errno is set.
3178 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3179 const struct rte_flow_action *action,
3180 uint64_t action_flags __rte_unused,
3181 const struct rte_flow_attr *attr,
3182 struct rte_flow_error *error)
3184 struct mlx5_priv *priv = dev->data->dev_private;
3185 struct mlx5_sh_config *config = &priv->sh->config;
3186 const struct rte_flow_action_set_meta *conf;
3187 uint32_t nic_mask = UINT32_MAX;
3190 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3191 !mlx5_flow_ext_mreg_supported(dev))
3192 return rte_flow_error_set(error, ENOTSUP,
3193 RTE_FLOW_ERROR_TYPE_ACTION, action,
3194 "extended metadata register"
3195 " isn't supported");
3196 reg = flow_dv_get_metadata_reg(dev, attr, error);
3200 return rte_flow_error_set(error, ENOTSUP,
3201 RTE_FLOW_ERROR_TYPE_ACTION, action,
3202 "unavailable extended metadata register");
3203 if (reg != REG_A && reg != REG_B) {
3204 struct mlx5_priv *priv = dev->data->dev_private;
3206 nic_mask = priv->sh->dv_meta_mask;
3208 if (!(action->conf))
3209 return rte_flow_error_set(error, EINVAL,
3210 RTE_FLOW_ERROR_TYPE_ACTION, action,
3211 "configuration cannot be null");
3212 conf = (const struct rte_flow_action_set_meta *)action->conf;
3214 return rte_flow_error_set(error, EINVAL,
3215 RTE_FLOW_ERROR_TYPE_ACTION, action,
3216 "zero mask doesn't have any effect");
3217 if (conf->mask & ~nic_mask)
3218 return rte_flow_error_set(error, EINVAL,
3219 RTE_FLOW_ERROR_TYPE_ACTION, action,
3220 "meta data must be within reg C0");
3225 * Validate SET_TAG action.
3228 * Pointer to the rte_eth_dev structure.
3230 * Pointer to the action structure.
3231 * @param[in] action_flags
3232 * Holds the actions detected until now.
3234 * Pointer to flow attributes
3236 * Pointer to error structure.
3239 * 0 on success, a negative errno value otherwise and rte_errno is set.
3242 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3243 const struct rte_flow_action *action,
3244 uint64_t action_flags,
3245 const struct rte_flow_attr *attr,
3246 struct rte_flow_error *error)
3248 const struct rte_flow_action_set_tag *conf;
3249 const uint64_t terminal_action_flags =
3250 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3251 MLX5_FLOW_ACTION_RSS;
3254 if (!mlx5_flow_ext_mreg_supported(dev))
3255 return rte_flow_error_set(error, ENOTSUP,
3256 RTE_FLOW_ERROR_TYPE_ACTION, action,
3257 "extensive metadata register"
3258 " isn't supported");
3259 if (!(action->conf))
3260 return rte_flow_error_set(error, EINVAL,
3261 RTE_FLOW_ERROR_TYPE_ACTION, action,
3262 "configuration cannot be null");
3263 conf = (const struct rte_flow_action_set_tag *)action->conf;
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION, action,
3267 "zero mask doesn't have any effect");
3268 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3271 if (!attr->transfer && attr->ingress &&
3272 (action_flags & terminal_action_flags))
3273 return rte_flow_error_set(error, EINVAL,
3274 RTE_FLOW_ERROR_TYPE_ACTION, action,
3275 "set_tag has no effect"
3276 " with terminal actions");
3281 * Indicates whether ASO aging is supported.
3284 * Pointer to shared device context structure.
3286 * Attributes of flow that includes AGE action.
3289 * True when ASO aging is supported, false otherwise.
3292 flow_hit_aso_supported(const struct mlx5_dev_ctx_shared *sh,
3293 const struct rte_flow_attr *attr)
3295 MLX5_ASSERT(sh && attr);
3296 return (sh->flow_hit_aso_en && (attr->transfer || attr->group));
3300 * Validate count action.
3303 * Pointer to rte_eth_dev structure.
3305 * Indicator if action is shared.
3306 * @param[in] action_flags
3307 * Holds the actions detected until now.
3309 * Attributes of flow that includes this action.
3311 * Pointer to error structure.
3314 * 0 on success, a negative errno value otherwise and rte_errno is set.
3317 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3318 uint64_t action_flags,
3319 const struct rte_flow_attr *attr,
3320 struct rte_flow_error *error)
3322 struct mlx5_priv *priv = dev->data->dev_private;
3324 if (!priv->sh->cdev->config.devx)
3326 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3327 return rte_flow_error_set(error, EINVAL,
3328 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3329 "duplicate count actions set");
3330 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3331 !flow_hit_aso_supported(priv->sh, attr))
3332 return rte_flow_error_set(error, EINVAL,
3333 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3334 "old age and indirect count combination is not supported");
3335 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3339 return rte_flow_error_set
3341 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3343 "count action not supported");
3347 * Validate the L2 encap action.
3350 * Pointer to the rte_eth_dev structure.
3351 * @param[in] action_flags
3352 * Holds the actions detected until now.
3354 * Pointer to the action structure.
3356 * Pointer to flow attributes.
3358 * Pointer to error structure.
3361 * 0 on success, a negative errno value otherwise and rte_errno is set.
3364 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3365 uint64_t action_flags,
3366 const struct rte_flow_action *action,
3367 const struct rte_flow_attr *attr,
3368 struct rte_flow_error *error)
3370 const struct mlx5_priv *priv = dev->data->dev_private;
3372 if (!(action->conf))
3373 return rte_flow_error_set(error, EINVAL,
3374 RTE_FLOW_ERROR_TYPE_ACTION, action,
3375 "configuration cannot be null");
3376 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3377 return rte_flow_error_set(error, EINVAL,
3378 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3379 "can only have a single encap action "
3381 if (!attr->transfer && priv->representor)
3382 return rte_flow_error_set(error, ENOTSUP,
3383 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3384 "encap action for VF representor "
3385 "not supported on NIC table");
3390 * Validate a decap action.
3393 * Pointer to the rte_eth_dev structure.
3394 * @param[in] action_flags
3395 * Holds the actions detected until now.
3397 * Pointer to the action structure.
3398 * @param[in] item_flags
3399 * Holds the items detected.
3401 * Pointer to flow attributes
3403 * Pointer to error structure.
3406 * 0 on success, a negative errno value otherwise and rte_errno is set.
3409 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3410 uint64_t action_flags,
3411 const struct rte_flow_action *action,
3412 const uint64_t item_flags,
3413 const struct rte_flow_attr *attr,
3414 struct rte_flow_error *error)
3416 const struct mlx5_priv *priv = dev->data->dev_private;
3418 if (priv->sh->cdev->config.hca_attr.scatter_fcs_w_decap_disable &&
3419 !priv->sh->config.decap_en)
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3422 "decap is not enabled");
3423 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3424 return rte_flow_error_set(error, ENOTSUP,
3425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3427 MLX5_FLOW_ACTION_DECAP ? "can only "
3428 "have a single decap action" : "decap "
3429 "after encap is not supported");
3430 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3431 return rte_flow_error_set(error, EINVAL,
3432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3433 "can't have decap action after"
3436 return rte_flow_error_set(error, ENOTSUP,
3437 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3439 "decap action not supported for "
3441 if (!attr->transfer && priv->representor)
3442 return rte_flow_error_set(error, ENOTSUP,
3443 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3444 "decap action for VF representor "
3445 "not supported on NIC table");
3446 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3447 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3448 return rte_flow_error_set(error, ENOTSUP,
3449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3450 "VXLAN item should be present for VXLAN decap");
3454 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3457 * Validate the raw encap and decap actions.
3460 * Pointer to the rte_eth_dev structure.
3462 * Pointer to the decap action.
3464 * Pointer to the encap action.
3466 * Pointer to flow attributes
3467 * @param[in/out] action_flags
3468 * Holds the actions detected until now.
3469 * @param[out] actions_n
3470 * pointer to the number of actions counter.
3472 * Pointer to the action structure.
3473 * @param[in] item_flags
3474 * Holds the items detected.
3476 * Pointer to error structure.
3479 * 0 on success, a negative errno value otherwise and rte_errno is set.
3482 flow_dv_validate_action_raw_encap_decap
3483 (struct rte_eth_dev *dev,
3484 const struct rte_flow_action_raw_decap *decap,
3485 const struct rte_flow_action_raw_encap *encap,
3486 const struct rte_flow_attr *attr, uint64_t *action_flags,
3487 int *actions_n, const struct rte_flow_action *action,
3488 uint64_t item_flags, struct rte_flow_error *error)
3490 const struct mlx5_priv *priv = dev->data->dev_private;
3493 if (encap && (!encap->size || !encap->data))
3494 return rte_flow_error_set(error, EINVAL,
3495 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3496 "raw encap data cannot be empty");
3497 if (decap && encap) {
3498 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3499 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3502 else if (encap->size <=
3503 MLX5_ENCAPSULATION_DECISION_SIZE &&
3505 MLX5_ENCAPSULATION_DECISION_SIZE)
3508 else if (encap->size >
3509 MLX5_ENCAPSULATION_DECISION_SIZE &&
3511 MLX5_ENCAPSULATION_DECISION_SIZE)
3512 /* 2 L2 actions: encap and decap. */
3515 return rte_flow_error_set(error,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3518 NULL, "unsupported too small "
3519 "raw decap and too small raw "
3520 "encap combination");
3523 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3524 item_flags, attr, error);
3527 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3531 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3532 return rte_flow_error_set(error, ENOTSUP,
3533 RTE_FLOW_ERROR_TYPE_ACTION,
3535 "small raw encap size");
3536 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3537 return rte_flow_error_set(error, EINVAL,
3538 RTE_FLOW_ERROR_TYPE_ACTION,
3540 "more than one encap action");
3541 if (!attr->transfer && priv->representor)
3542 return rte_flow_error_set
3544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3545 "encap action for VF representor "
3546 "not supported on NIC table");
3547 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3554 * Validate the ASO CT action.
3557 * Pointer to the rte_eth_dev structure.
3558 * @param[in] action_flags
3559 * Holds the actions detected until now.
3560 * @param[in] item_flags
3561 * The items found in this flow rule.
3563 * Pointer to flow attributes.
3565 * Pointer to error structure.
3568 * 0 on success, a negative errno value otherwise and rte_errno is set.
3571 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3572 uint64_t action_flags,
3573 uint64_t item_flags,
3574 const struct rte_flow_attr *attr,
3575 struct rte_flow_error *error)
3579 if (attr->group == 0 && !attr->transfer)
3580 return rte_flow_error_set(error, ENOTSUP,
3581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3583 "Only support non-root table");
3584 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3585 return rte_flow_error_set(error, ENOTSUP,
3586 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3587 "CT cannot follow a fate action");
3588 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3589 (action_flags & MLX5_FLOW_ACTION_AGE))
3590 return rte_flow_error_set(error, EINVAL,
3591 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3592 "Only one ASO action is supported");
3593 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3594 return rte_flow_error_set(error, EINVAL,
3595 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3596 "Encap cannot exist before CT");
3597 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3598 return rte_flow_error_set(error, EINVAL,
3599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3600 "Not a outer TCP packet");
3605 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3606 struct mlx5_list_entry *entry, void *cb_ctx)
3608 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3609 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3610 struct mlx5_flow_dv_encap_decap_resource *resource;
3612 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3614 if (resource->reformat_type == ctx_resource->reformat_type &&
3615 resource->ft_type == ctx_resource->ft_type &&
3616 resource->flags == ctx_resource->flags &&
3617 resource->size == ctx_resource->size &&
3618 !memcmp((const void *)resource->buf,
3619 (const void *)ctx_resource->buf,
3625 struct mlx5_list_entry *
3626 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3628 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3629 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3630 struct mlx5dv_dr_domain *domain;
3631 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3632 struct mlx5_flow_dv_encap_decap_resource *resource;
3636 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3637 domain = sh->fdb_domain;
3638 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3639 domain = sh->rx_domain;
3641 domain = sh->tx_domain;
3642 /* Register new encap/decap resource. */
3643 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3645 rte_flow_error_set(ctx->error, ENOMEM,
3646 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3647 "cannot allocate resource memory");
3650 *resource = *ctx_resource;
3651 resource->idx = idx;
3652 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3656 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3657 rte_flow_error_set(ctx->error, ENOMEM,
3658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3659 NULL, "cannot create action");
3663 return &resource->entry;
3666 struct mlx5_list_entry *
3667 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3670 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3671 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3672 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3675 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3677 if (!cache_resource) {
3678 rte_flow_error_set(ctx->error, ENOMEM,
3679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3680 "cannot allocate resource memory");
3683 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3684 cache_resource->idx = idx;
3685 return &cache_resource->entry;
3689 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3691 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3692 struct mlx5_flow_dv_encap_decap_resource *res =
3693 container_of(entry, typeof(*res), entry);
3695 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3699 * Find existing encap/decap resource or create and register a new one.
3701 * @param[in, out] dev
3702 * Pointer to rte_eth_dev structure.
3703 * @param[in, out] resource
3704 * Pointer to encap/decap resource.
3705 * @parm[in, out] dev_flow
3706 * Pointer to the dev_flow.
3708 * pointer to error structure.
3711 * 0 on success otherwise -errno and errno is set.
3714 flow_dv_encap_decap_resource_register
3715 (struct rte_eth_dev *dev,
3716 struct mlx5_flow_dv_encap_decap_resource *resource,
3717 struct mlx5_flow *dev_flow,
3718 struct rte_flow_error *error)
3720 struct mlx5_priv *priv = dev->data->dev_private;
3721 struct mlx5_dev_ctx_shared *sh = priv->sh;
3722 struct mlx5_list_entry *entry;
3726 uint32_t refmt_type:8;
3728 * Header reformat actions can be shared between
3729 * non-root tables. One bit to indicate non-root
3733 uint32_t reserve:15;
3736 } encap_decap_key = {
3738 .ft_type = resource->ft_type,
3739 .refmt_type = resource->reformat_type,
3740 .is_root = !!dev_flow->dv.group,
3744 struct mlx5_flow_cb_ctx ctx = {
3748 struct mlx5_hlist *encaps_decaps;
3751 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3753 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3755 flow_dv_encap_decap_create_cb,
3756 flow_dv_encap_decap_match_cb,
3757 flow_dv_encap_decap_remove_cb,
3758 flow_dv_encap_decap_clone_cb,
3759 flow_dv_encap_decap_clone_free_cb,
3761 if (unlikely(!encaps_decaps))
3763 resource->flags = dev_flow->dv.group ? 0 : 1;
3764 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3765 sizeof(encap_decap_key.v32), 0);
3766 if (resource->reformat_type !=
3767 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3769 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3770 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3773 resource = container_of(entry, typeof(*resource), entry);
3774 dev_flow->dv.encap_decap = resource;
3775 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3780 * Find existing table jump resource or create and register a new one.
3782 * @param[in, out] dev
3783 * Pointer to rte_eth_dev structure.
3784 * @param[in, out] tbl
3785 * Pointer to flow table resource.
3786 * @parm[in, out] dev_flow
3787 * Pointer to the dev_flow.
3789 * pointer to error structure.
3792 * 0 on success otherwise -errno and errno is set.
3795 flow_dv_jump_tbl_resource_register
3796 (struct rte_eth_dev *dev __rte_unused,
3797 struct mlx5_flow_tbl_resource *tbl,
3798 struct mlx5_flow *dev_flow,
3799 struct rte_flow_error *error __rte_unused)
3801 struct mlx5_flow_tbl_data_entry *tbl_data =
3802 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3805 MLX5_ASSERT(tbl_data->jump.action);
3806 dev_flow->handle->rix_jump = tbl_data->idx;
3807 dev_flow->dv.jump = &tbl_data->jump;
3812 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3813 struct mlx5_list_entry *entry, void *cb_ctx)
3815 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3816 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3817 struct mlx5_flow_dv_port_id_action_resource *res =
3818 container_of(entry, typeof(*res), entry);
3820 return ref->port_id != res->port_id;
3823 struct mlx5_list_entry *
3824 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3826 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3827 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3828 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3829 struct mlx5_flow_dv_port_id_action_resource *resource;
3833 /* Register new port id action resource. */
3834 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3836 rte_flow_error_set(ctx->error, ENOMEM,
3837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3838 "cannot allocate port_id action memory");
3842 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3846 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3847 rte_flow_error_set(ctx->error, ENOMEM,
3848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3849 "cannot create action");
3852 resource->idx = idx;
3853 return &resource->entry;
3856 struct mlx5_list_entry *
3857 flow_dv_port_id_clone_cb(void *tool_ctx,
3858 struct mlx5_list_entry *entry __rte_unused,
3861 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3862 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3863 struct mlx5_flow_dv_port_id_action_resource *resource;
3866 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3868 rte_flow_error_set(ctx->error, ENOMEM,
3869 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3870 "cannot allocate port_id action memory");
3873 memcpy(resource, entry, sizeof(*resource));
3874 resource->idx = idx;
3875 return &resource->entry;
3879 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3881 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3882 struct mlx5_flow_dv_port_id_action_resource *resource =
3883 container_of(entry, typeof(*resource), entry);
3885 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3889 * Find existing table port ID resource or create and register a new one.
3891 * @param[in, out] dev
3892 * Pointer to rte_eth_dev structure.
3893 * @param[in, out] ref
3894 * Pointer to port ID action resource reference.
3895 * @parm[in, out] dev_flow
3896 * Pointer to the dev_flow.
3898 * pointer to error structure.
3901 * 0 on success otherwise -errno and errno is set.
3904 flow_dv_port_id_action_resource_register
3905 (struct rte_eth_dev *dev,
3906 struct mlx5_flow_dv_port_id_action_resource *ref,
3907 struct mlx5_flow *dev_flow,
3908 struct rte_flow_error *error)
3910 struct mlx5_priv *priv = dev->data->dev_private;
3911 struct mlx5_list_entry *entry;
3912 struct mlx5_flow_dv_port_id_action_resource *resource;
3913 struct mlx5_flow_cb_ctx ctx = {
3918 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3921 resource = container_of(entry, typeof(*resource), entry);
3922 dev_flow->dv.port_id_action = resource;
3923 dev_flow->handle->rix_port_id_action = resource->idx;
3928 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3929 struct mlx5_list_entry *entry, void *cb_ctx)
3931 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3932 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3933 struct mlx5_flow_dv_push_vlan_action_resource *res =
3934 container_of(entry, typeof(*res), entry);
3936 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3939 struct mlx5_list_entry *
3940 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3942 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3943 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3944 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3945 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3946 struct mlx5dv_dr_domain *domain;
3950 /* Register new port id action resource. */
3951 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3953 rte_flow_error_set(ctx->error, ENOMEM,
3954 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3955 "cannot allocate push_vlan action memory");
3959 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3960 domain = sh->fdb_domain;
3961 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3962 domain = sh->rx_domain;
3964 domain = sh->tx_domain;
3965 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3968 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3969 rte_flow_error_set(ctx->error, ENOMEM,
3970 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3971 "cannot create push vlan action");
3974 resource->idx = idx;
3975 return &resource->entry;
3978 struct mlx5_list_entry *
3979 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3980 struct mlx5_list_entry *entry __rte_unused,
3983 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3984 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3985 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3988 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3990 rte_flow_error_set(ctx->error, ENOMEM,
3991 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3992 "cannot allocate push_vlan action memory");
3995 memcpy(resource, entry, sizeof(*resource));
3996 resource->idx = idx;
3997 return &resource->entry;
4001 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
4003 struct mlx5_dev_ctx_shared *sh = tool_ctx;
4004 struct mlx5_flow_dv_push_vlan_action_resource *resource =
4005 container_of(entry, typeof(*resource), entry);
4007 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
4011 * Find existing push vlan resource or create and register a new one.
4013 * @param [in, out] dev
4014 * Pointer to rte_eth_dev structure.
4015 * @param[in, out] ref
4016 * Pointer to port ID action resource reference.
4017 * @parm[in, out] dev_flow
4018 * Pointer to the dev_flow.
4020 * pointer to error structure.
4023 * 0 on success otherwise -errno and errno is set.
4026 flow_dv_push_vlan_action_resource_register
4027 (struct rte_eth_dev *dev,
4028 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4029 struct mlx5_flow *dev_flow,
4030 struct rte_flow_error *error)
4032 struct mlx5_priv *priv = dev->data->dev_private;
4033 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4034 struct mlx5_list_entry *entry;
4035 struct mlx5_flow_cb_ctx ctx = {
4040 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4043 resource = container_of(entry, typeof(*resource), entry);
4045 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4046 dev_flow->dv.push_vlan_res = resource;
4051 * Get the size of specific rte_flow_item_type hdr size
4053 * @param[in] item_type
4054 * Tested rte_flow_item_type.
4057 * sizeof struct item_type, 0 if void or irrelevant.
4060 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4064 switch (item_type) {
4065 case RTE_FLOW_ITEM_TYPE_ETH:
4066 retval = sizeof(struct rte_ether_hdr);
4068 case RTE_FLOW_ITEM_TYPE_VLAN:
4069 retval = sizeof(struct rte_vlan_hdr);
4071 case RTE_FLOW_ITEM_TYPE_IPV4:
4072 retval = sizeof(struct rte_ipv4_hdr);
4074 case RTE_FLOW_ITEM_TYPE_IPV6:
4075 retval = sizeof(struct rte_ipv6_hdr);
4077 case RTE_FLOW_ITEM_TYPE_UDP:
4078 retval = sizeof(struct rte_udp_hdr);
4080 case RTE_FLOW_ITEM_TYPE_TCP:
4081 retval = sizeof(struct rte_tcp_hdr);
4083 case RTE_FLOW_ITEM_TYPE_VXLAN:
4084 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4085 retval = sizeof(struct rte_vxlan_hdr);
4087 case RTE_FLOW_ITEM_TYPE_GRE:
4088 case RTE_FLOW_ITEM_TYPE_NVGRE:
4089 retval = sizeof(struct rte_gre_hdr);
4091 case RTE_FLOW_ITEM_TYPE_MPLS:
4092 retval = sizeof(struct rte_mpls_hdr);
4094 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4102 #define MLX5_ENCAP_IPV4_VERSION 0x40
4103 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4104 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4105 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4106 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4107 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4108 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4111 * Convert the encap action data from list of rte_flow_item to raw buffer
4114 * Pointer to rte_flow_item objects list.
4116 * Pointer to the output buffer.
4118 * Pointer to the output buffer size.
4120 * Pointer to the error structure.
4123 * 0 on success, a negative errno value otherwise and rte_errno is set.
4126 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4127 size_t *size, struct rte_flow_error *error)
4129 struct rte_ether_hdr *eth = NULL;
4130 struct rte_vlan_hdr *vlan = NULL;
4131 struct rte_ipv4_hdr *ipv4 = NULL;
4132 struct rte_ipv6_hdr *ipv6 = NULL;
4133 struct rte_udp_hdr *udp = NULL;
4134 struct rte_vxlan_hdr *vxlan = NULL;
4135 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4136 struct rte_gre_hdr *gre = NULL;
4138 size_t temp_size = 0;
4141 return rte_flow_error_set(error, EINVAL,
4142 RTE_FLOW_ERROR_TYPE_ACTION,
4143 NULL, "invalid empty data");
4144 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4145 len = flow_dv_get_item_hdr_len(items->type);
4146 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4147 return rte_flow_error_set(error, EINVAL,
4148 RTE_FLOW_ERROR_TYPE_ACTION,
4149 (void *)items->type,
4150 "items total size is too big"
4151 " for encap action");
4152 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4153 switch (items->type) {
4154 case RTE_FLOW_ITEM_TYPE_ETH:
4155 eth = (struct rte_ether_hdr *)&buf[temp_size];
4157 case RTE_FLOW_ITEM_TYPE_VLAN:
4158 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4160 return rte_flow_error_set(error, EINVAL,
4161 RTE_FLOW_ERROR_TYPE_ACTION,
4162 (void *)items->type,
4163 "eth header not found");
4164 if (!eth->ether_type)
4165 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4167 case RTE_FLOW_ITEM_TYPE_IPV4:
4168 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4170 return rte_flow_error_set(error, EINVAL,
4171 RTE_FLOW_ERROR_TYPE_ACTION,
4172 (void *)items->type,
4173 "neither eth nor vlan"
4175 if (vlan && !vlan->eth_proto)
4176 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4177 else if (eth && !eth->ether_type)
4178 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4179 if (!ipv4->version_ihl)
4180 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4181 MLX5_ENCAP_IPV4_IHL_MIN;
4182 if (!ipv4->time_to_live)
4183 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4185 case RTE_FLOW_ITEM_TYPE_IPV6:
4186 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4188 return rte_flow_error_set(error, EINVAL,
4189 RTE_FLOW_ERROR_TYPE_ACTION,
4190 (void *)items->type,
4191 "neither eth nor vlan"
4193 if (vlan && !vlan->eth_proto)
4194 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4195 else if (eth && !eth->ether_type)
4196 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4197 if (!ipv6->vtc_flow)
4199 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4200 if (!ipv6->hop_limits)
4201 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4203 case RTE_FLOW_ITEM_TYPE_UDP:
4204 udp = (struct rte_udp_hdr *)&buf[temp_size];
4206 return rte_flow_error_set(error, EINVAL,
4207 RTE_FLOW_ERROR_TYPE_ACTION,
4208 (void *)items->type,
4209 "ip header not found");
4210 if (ipv4 && !ipv4->next_proto_id)
4211 ipv4->next_proto_id = IPPROTO_UDP;
4212 else if (ipv6 && !ipv6->proto)
4213 ipv6->proto = IPPROTO_UDP;
4215 case RTE_FLOW_ITEM_TYPE_VXLAN:
4216 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4218 return rte_flow_error_set(error, EINVAL,
4219 RTE_FLOW_ERROR_TYPE_ACTION,
4220 (void *)items->type,
4221 "udp header not found");
4223 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4224 if (!vxlan->vx_flags)
4226 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4228 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4229 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4231 return rte_flow_error_set(error, EINVAL,
4232 RTE_FLOW_ERROR_TYPE_ACTION,
4233 (void *)items->type,
4234 "udp header not found");
4235 if (!vxlan_gpe->proto)
4236 return rte_flow_error_set(error, EINVAL,
4237 RTE_FLOW_ERROR_TYPE_ACTION,
4238 (void *)items->type,
4239 "next protocol not found");
4242 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4243 if (!vxlan_gpe->vx_flags)
4244 vxlan_gpe->vx_flags =
4245 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4247 case RTE_FLOW_ITEM_TYPE_GRE:
4248 case RTE_FLOW_ITEM_TYPE_NVGRE:
4249 gre = (struct rte_gre_hdr *)&buf[temp_size];
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "next protocol not found");
4256 return rte_flow_error_set(error, EINVAL,
4257 RTE_FLOW_ERROR_TYPE_ACTION,
4258 (void *)items->type,
4259 "ip header not found");
4260 if (ipv4 && !ipv4->next_proto_id)
4261 ipv4->next_proto_id = IPPROTO_GRE;
4262 else if (ipv6 && !ipv6->proto)
4263 ipv6->proto = IPPROTO_GRE;
4265 case RTE_FLOW_ITEM_TYPE_VOID:
4268 return rte_flow_error_set(error, EINVAL,
4269 RTE_FLOW_ERROR_TYPE_ACTION,
4270 (void *)items->type,
4271 "unsupported item type");
4281 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4283 struct rte_ether_hdr *eth = NULL;
4284 struct rte_vlan_hdr *vlan = NULL;
4285 struct rte_ipv6_hdr *ipv6 = NULL;
4286 struct rte_udp_hdr *udp = NULL;
4290 eth = (struct rte_ether_hdr *)data;
4291 next_hdr = (char *)(eth + 1);
4292 proto = RTE_BE16(eth->ether_type);
4295 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4296 vlan = (struct rte_vlan_hdr *)next_hdr;
4297 proto = RTE_BE16(vlan->eth_proto);
4298 next_hdr += sizeof(struct rte_vlan_hdr);
4301 /* HW calculates IPv4 csum. no need to proceed */
4302 if (proto == RTE_ETHER_TYPE_IPV4)
4305 /* non IPv4/IPv6 header. not supported */
4306 if (proto != RTE_ETHER_TYPE_IPV6) {
4307 return rte_flow_error_set(error, ENOTSUP,
4308 RTE_FLOW_ERROR_TYPE_ACTION,
4309 NULL, "Cannot offload non IPv4/IPv6");
4312 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4314 /* ignore non UDP */
4315 if (ipv6->proto != IPPROTO_UDP)
4318 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4319 udp->dgram_cksum = 0;
4325 * Convert L2 encap action to DV specification.
4328 * Pointer to rte_eth_dev structure.
4330 * Pointer to action structure.
4331 * @param[in, out] dev_flow
4332 * Pointer to the mlx5_flow.
4333 * @param[in] transfer
4334 * Mark if the flow is E-Switch flow.
4336 * Pointer to the error structure.
4339 * 0 on success, a negative errno value otherwise and rte_errno is set.
4342 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4343 const struct rte_flow_action *action,
4344 struct mlx5_flow *dev_flow,
4346 struct rte_flow_error *error)
4348 const struct rte_flow_item *encap_data;
4349 const struct rte_flow_action_raw_encap *raw_encap_data;
4350 struct mlx5_flow_dv_encap_decap_resource res = {
4352 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4353 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4354 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4357 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4359 (const struct rte_flow_action_raw_encap *)action->conf;
4360 res.size = raw_encap_data->size;
4361 memcpy(res.buf, raw_encap_data->data, res.size);
4363 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4365 ((const struct rte_flow_action_vxlan_encap *)
4366 action->conf)->definition;
4369 ((const struct rte_flow_action_nvgre_encap *)
4370 action->conf)->definition;
4371 if (flow_dv_convert_encap_data(encap_data, res.buf,
4375 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4377 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4378 return rte_flow_error_set(error, EINVAL,
4379 RTE_FLOW_ERROR_TYPE_ACTION,
4380 NULL, "can't create L2 encap action");
4385 * Convert L2 decap action to DV specification.
4388 * Pointer to rte_eth_dev structure.
4389 * @param[in, out] dev_flow
4390 * Pointer to the mlx5_flow.
4391 * @param[in] transfer
4392 * Mark if the flow is E-Switch flow.
4394 * Pointer to the error structure.
4397 * 0 on success, a negative errno value otherwise and rte_errno is set.
4400 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4401 struct mlx5_flow *dev_flow,
4403 struct rte_flow_error *error)
4405 struct mlx5_flow_dv_encap_decap_resource res = {
4408 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4409 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4410 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4413 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4414 return rte_flow_error_set(error, EINVAL,
4415 RTE_FLOW_ERROR_TYPE_ACTION,
4416 NULL, "can't create L2 decap action");
4421 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4424 * Pointer to rte_eth_dev structure.
4426 * Pointer to action structure.
4427 * @param[in, out] dev_flow
4428 * Pointer to the mlx5_flow.
4430 * Pointer to the flow attributes.
4432 * Pointer to the error structure.
4435 * 0 on success, a negative errno value otherwise and rte_errno is set.
4438 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4439 const struct rte_flow_action *action,
4440 struct mlx5_flow *dev_flow,
4441 const struct rte_flow_attr *attr,
4442 struct rte_flow_error *error)
4444 const struct rte_flow_action_raw_encap *encap_data;
4445 struct mlx5_flow_dv_encap_decap_resource res;
4447 memset(&res, 0, sizeof(res));
4448 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4449 res.size = encap_data->size;
4450 memcpy(res.buf, encap_data->data, res.size);
4451 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4452 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4453 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4455 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4457 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4458 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4459 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4460 return rte_flow_error_set(error, EINVAL,
4461 RTE_FLOW_ERROR_TYPE_ACTION,
4462 NULL, "can't create encap action");
4467 * Create action push VLAN.
4470 * Pointer to rte_eth_dev structure.
4472 * Pointer to the flow attributes.
4474 * Pointer to the vlan to push to the Ethernet header.
4475 * @param[in, out] dev_flow
4476 * Pointer to the mlx5_flow.
4478 * Pointer to the error structure.
4481 * 0 on success, a negative errno value otherwise and rte_errno is set.
4484 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4485 const struct rte_flow_attr *attr,
4486 const struct rte_vlan_hdr *vlan,
4487 struct mlx5_flow *dev_flow,
4488 struct rte_flow_error *error)
4490 struct mlx5_flow_dv_push_vlan_action_resource res;
4492 memset(&res, 0, sizeof(res));
4494 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4497 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4499 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4500 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4501 return flow_dv_push_vlan_action_resource_register
4502 (dev, &res, dev_flow, error);
4506 * Validate the modify-header actions.
4508 * @param[in] action_flags
4509 * Holds the actions detected until now.
4511 * Pointer to the modify action.
4513 * Pointer to error structure.
4516 * 0 on success, a negative errno value otherwise and rte_errno is set.
4519 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4520 const struct rte_flow_action *action,
4521 struct rte_flow_error *error)
4523 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4524 return rte_flow_error_set(error, EINVAL,
4525 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4526 NULL, "action configuration not set");
4527 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4528 return rte_flow_error_set(error, EINVAL,
4529 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4530 "can't have encap action before"
4536 * Validate the modify-header MAC address actions.
4538 * @param[in] action_flags
4539 * Holds the actions detected until now.
4541 * Pointer to the modify action.
4542 * @param[in] item_flags
4543 * Holds the items detected.
4545 * Pointer to error structure.
4548 * 0 on success, a negative errno value otherwise and rte_errno is set.
4551 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4552 const struct rte_flow_action *action,
4553 const uint64_t item_flags,
4554 struct rte_flow_error *error)
4558 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4560 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4561 return rte_flow_error_set(error, EINVAL,
4562 RTE_FLOW_ERROR_TYPE_ACTION,
4564 "no L2 item in pattern");
4570 * Validate the modify-header IPv4 address actions.
4572 * @param[in] action_flags
4573 * Holds the actions detected until now.
4575 * Pointer to the modify action.
4576 * @param[in] item_flags
4577 * Holds the items detected.
4579 * Pointer to error structure.
4582 * 0 on success, a negative errno value otherwise and rte_errno is set.
4585 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4586 const struct rte_flow_action *action,
4587 const uint64_t item_flags,
4588 struct rte_flow_error *error)
4593 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4595 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4596 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4597 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4598 if (!(item_flags & layer))
4599 return rte_flow_error_set(error, EINVAL,
4600 RTE_FLOW_ERROR_TYPE_ACTION,
4602 "no ipv4 item in pattern");
4608 * Validate the modify-header IPv6 address actions.
4610 * @param[in] action_flags
4611 * Holds the actions detected until now.
4613 * Pointer to the modify action.
4614 * @param[in] item_flags
4615 * Holds the items detected.
4617 * Pointer to error structure.
4620 * 0 on success, a negative errno value otherwise and rte_errno is set.
4623 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4624 const struct rte_flow_action *action,
4625 const uint64_t item_flags,
4626 struct rte_flow_error *error)
4631 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4633 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4634 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4635 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4636 if (!(item_flags & layer))
4637 return rte_flow_error_set(error, EINVAL,
4638 RTE_FLOW_ERROR_TYPE_ACTION,
4640 "no ipv6 item in pattern");
4646 * Validate the modify-header TP actions.
4648 * @param[in] action_flags
4649 * Holds the actions detected until now.
4651 * Pointer to the modify action.
4652 * @param[in] item_flags
4653 * Holds the items detected.
4655 * Pointer to error structure.
4658 * 0 on success, a negative errno value otherwise and rte_errno is set.
4661 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4662 const struct rte_flow_action *action,
4663 const uint64_t item_flags,
4664 struct rte_flow_error *error)
4669 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4671 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4672 MLX5_FLOW_LAYER_INNER_L4 :
4673 MLX5_FLOW_LAYER_OUTER_L4;
4674 if (!(item_flags & layer))
4675 return rte_flow_error_set(error, EINVAL,
4676 RTE_FLOW_ERROR_TYPE_ACTION,
4677 NULL, "no transport layer "
4684 * Validate the modify-header actions of increment/decrement
4685 * TCP Sequence-number.
4687 * @param[in] action_flags
4688 * Holds the actions detected until now.
4690 * Pointer to the modify action.
4691 * @param[in] item_flags
4692 * Holds the items detected.
4694 * Pointer to error structure.
4697 * 0 on success, a negative errno value otherwise and rte_errno is set.
4700 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4701 const struct rte_flow_action *action,
4702 const uint64_t item_flags,
4703 struct rte_flow_error *error)
4708 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4710 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4711 MLX5_FLOW_LAYER_INNER_L4_TCP :
4712 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4713 if (!(item_flags & layer))
4714 return rte_flow_error_set(error, EINVAL,
4715 RTE_FLOW_ERROR_TYPE_ACTION,
4716 NULL, "no TCP item in"
4718 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4719 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4720 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4721 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4722 return rte_flow_error_set(error, EINVAL,
4723 RTE_FLOW_ERROR_TYPE_ACTION,
4725 "cannot decrease and increase"
4726 " TCP sequence number"
4727 " at the same time");
4733 * Validate the modify-header actions of increment/decrement
4734 * TCP Acknowledgment number.
4736 * @param[in] action_flags
4737 * Holds the actions detected until now.
4739 * Pointer to the modify action.
4740 * @param[in] item_flags
4741 * Holds the items detected.
4743 * Pointer to error structure.
4746 * 0 on success, a negative errno value otherwise and rte_errno is set.
4749 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4750 const struct rte_flow_action *action,
4751 const uint64_t item_flags,
4752 struct rte_flow_error *error)
4757 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4759 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4760 MLX5_FLOW_LAYER_INNER_L4_TCP :
4761 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4762 if (!(item_flags & layer))
4763 return rte_flow_error_set(error, EINVAL,
4764 RTE_FLOW_ERROR_TYPE_ACTION,
4765 NULL, "no TCP item in"
4767 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4768 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4769 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4770 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4771 return rte_flow_error_set(error, EINVAL,
4772 RTE_FLOW_ERROR_TYPE_ACTION,
4774 "cannot decrease and increase"
4775 " TCP acknowledgment number"
4776 " at the same time");
4782 * Validate the modify-header TTL actions.
4784 * @param[in] action_flags
4785 * Holds the actions detected until now.
4787 * Pointer to the modify action.
4788 * @param[in] item_flags
4789 * Holds the items detected.
4791 * Pointer to error structure.
4794 * 0 on success, a negative errno value otherwise and rte_errno is set.
4797 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4798 const struct rte_flow_action *action,
4799 const uint64_t item_flags,
4800 struct rte_flow_error *error)
4805 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4807 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4808 MLX5_FLOW_LAYER_INNER_L3 :
4809 MLX5_FLOW_LAYER_OUTER_L3;
4810 if (!(item_flags & layer))
4811 return rte_flow_error_set(error, EINVAL,
4812 RTE_FLOW_ERROR_TYPE_ACTION,
4814 "no IP protocol in pattern");
4820 * Validate the generic modify field actions.
4822 * Pointer to the rte_eth_dev structure.
4823 * @param[in] action_flags
4824 * Holds the actions detected until now.
4826 * Pointer to the modify action.
4828 * Pointer to the flow attributes.
4830 * Pointer to error structure.
4833 * Number of header fields to modify (0 or more) on success,
4834 * a negative errno value otherwise and rte_errno is set.
4837 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4838 const uint64_t action_flags,
4839 const struct rte_flow_action *action,
4840 const struct rte_flow_attr *attr,
4841 struct rte_flow_error *error)
4844 struct mlx5_priv *priv = dev->data->dev_private;
4845 struct mlx5_sh_config *config = &priv->sh->config;
4846 const struct rte_flow_action_modify_field *action_modify_field =
4848 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4849 action_modify_field->dst.field,
4851 uint32_t src_width = mlx5_flow_item_field_width(dev,
4852 action_modify_field->src.field,
4853 dst_width, attr, error);
4855 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4859 if (action_modify_field->width == 0)
4860 return rte_flow_error_set(error, EINVAL,
4861 RTE_FLOW_ERROR_TYPE_ACTION, action,
4862 "no bits are requested to be modified");
4863 else if (action_modify_field->width > dst_width ||
4864 action_modify_field->width > src_width)
4865 return rte_flow_error_set(error, EINVAL,
4866 RTE_FLOW_ERROR_TYPE_ACTION, action,
4867 "cannot modify more bits than"
4868 " the width of a field");
4869 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4870 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4871 if ((action_modify_field->dst.offset +
4872 action_modify_field->width > dst_width) ||
4873 (action_modify_field->dst.offset % 32))
4874 return rte_flow_error_set(error, EINVAL,
4875 RTE_FLOW_ERROR_TYPE_ACTION, action,
4876 "destination offset is too big"
4877 " or not aligned to 4 bytes");
4878 if (action_modify_field->dst.level &&
4879 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4880 return rte_flow_error_set(error, ENOTSUP,
4881 RTE_FLOW_ERROR_TYPE_ACTION, action,
4882 "inner header fields modification"
4883 " is not supported");
4885 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4886 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4887 if (!attr->transfer && !attr->group)
4888 return rte_flow_error_set(error, ENOTSUP,
4889 RTE_FLOW_ERROR_TYPE_ACTION, action,
4890 "modify field action is not"
4891 " supported for group 0");
4892 if ((action_modify_field->src.offset +
4893 action_modify_field->width > src_width) ||
4894 (action_modify_field->src.offset % 32))
4895 return rte_flow_error_set(error, EINVAL,
4896 RTE_FLOW_ERROR_TYPE_ACTION, action,
4897 "source offset is too big"
4898 " or not aligned to 4 bytes");
4899 if (action_modify_field->src.level &&
4900 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4901 return rte_flow_error_set(error, ENOTSUP,
4902 RTE_FLOW_ERROR_TYPE_ACTION, action,
4903 "inner header fields modification"
4904 " is not supported");
4906 if ((action_modify_field->dst.field ==
4907 action_modify_field->src.field) &&
4908 (action_modify_field->dst.level ==
4909 action_modify_field->src.level))
4910 return rte_flow_error_set(error, EINVAL,
4911 RTE_FLOW_ERROR_TYPE_ACTION, action,
4912 "source and destination fields"
4913 " cannot be the same");
4914 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4915 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4916 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4917 return rte_flow_error_set(error, EINVAL,
4918 RTE_FLOW_ERROR_TYPE_ACTION, action,
4919 "mark, immediate value or a pointer to it"
4920 " cannot be used as a destination");
4921 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4922 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4923 return rte_flow_error_set(error, ENOTSUP,
4924 RTE_FLOW_ERROR_TYPE_ACTION, action,
4925 "modifications of an arbitrary"
4926 " place in a packet is not supported");
4927 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4928 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4929 return rte_flow_error_set(error, ENOTSUP,
4930 RTE_FLOW_ERROR_TYPE_ACTION, action,
4931 "modifications of the 802.1Q Tag"
4932 " Identifier is not supported");
4933 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4934 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4935 return rte_flow_error_set(error, ENOTSUP,
4936 RTE_FLOW_ERROR_TYPE_ACTION, action,
4937 "modifications of the VXLAN Network"
4938 " Identifier is not supported");
4939 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4940 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4941 return rte_flow_error_set(error, ENOTSUP,
4942 RTE_FLOW_ERROR_TYPE_ACTION, action,
4943 "modifications of the GENEVE Network"
4944 " Identifier is not supported");
4945 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4946 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4947 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4948 !mlx5_flow_ext_mreg_supported(dev))
4949 return rte_flow_error_set(error, ENOTSUP,
4950 RTE_FLOW_ERROR_TYPE_ACTION, action,
4951 "cannot modify mark in legacy mode"
4952 " or without extensive registers");
4953 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4954 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4955 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4956 !mlx5_flow_ext_mreg_supported(dev))
4957 return rte_flow_error_set(error, ENOTSUP,
4958 RTE_FLOW_ERROR_TYPE_ACTION, action,
4959 "cannot modify meta without"
4960 " extensive registers support");
4961 ret = flow_dv_get_metadata_reg(dev, attr, error);
4962 if (ret < 0 || ret == REG_NON)
4963 return rte_flow_error_set(error, ENOTSUP,
4964 RTE_FLOW_ERROR_TYPE_ACTION, action,
4965 "cannot modify meta without"
4966 " extensive registers available");
4968 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4969 return rte_flow_error_set(error, ENOTSUP,
4970 RTE_FLOW_ERROR_TYPE_ACTION, action,
4971 "add and sub operations"
4972 " are not supported");
4973 return (action_modify_field->width / 32) +
4974 !!(action_modify_field->width % 32);
4978 * Validate jump action.
4981 * Pointer to the jump action.
4982 * @param[in] action_flags
4983 * Holds the actions detected until now.
4984 * @param[in] attributes
4985 * Pointer to flow attributes
4986 * @param[in] external
4987 * Action belongs to flow rule created by request external to PMD.
4989 * Pointer to error structure.
4992 * 0 on success, a negative errno value otherwise and rte_errno is set.
4995 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4996 const struct mlx5_flow_tunnel *tunnel,
4997 const struct rte_flow_action *action,
4998 uint64_t action_flags,
4999 const struct rte_flow_attr *attributes,
5000 bool external, struct rte_flow_error *error)
5002 uint32_t target_group, table = 0;
5004 struct flow_grp_info grp_info = {
5005 .external = !!external,
5006 .transfer = !!attributes->transfer,
5010 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5011 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "can't have 2 fate actions in"
5017 return rte_flow_error_set(error, EINVAL,
5018 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5019 NULL, "action configuration not set");
5021 ((const struct rte_flow_action_jump *)action->conf)->group;
5022 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5026 if (attributes->group == target_group &&
5027 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5028 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5029 return rte_flow_error_set(error, EINVAL,
5030 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5031 "target group must be other than"
5032 " the current flow group");
5034 return rte_flow_error_set(error, EINVAL,
5035 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5036 NULL, "root table shouldn't be destination");
5041 * Validate action PORT_ID / REPRESENTED_PORT.
5044 * Pointer to rte_eth_dev structure.
5045 * @param[in] action_flags
5046 * Bit-fields that holds the actions detected until now.
5048 * PORT_ID / REPRESENTED_PORT action structure.
5050 * Attributes of flow that includes this action.
5052 * Pointer to error structure.
5055 * 0 on success, a negative errno value otherwise and rte_errno is set.
5058 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5059 uint64_t action_flags,
5060 const struct rte_flow_action *action,
5061 const struct rte_flow_attr *attr,
5062 struct rte_flow_error *error)
5064 const struct rte_flow_action_port_id *port_id;
5065 const struct rte_flow_action_ethdev *ethdev;
5066 struct mlx5_priv *act_priv;
5067 struct mlx5_priv *dev_priv;
5070 if (!attr->transfer)
5071 return rte_flow_error_set(error, ENOTSUP,
5072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5074 "port action is valid in transfer"
5076 if (!action || !action->conf)
5077 return rte_flow_error_set(error, ENOTSUP,
5078 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5080 "port action parameters must be"
5082 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5083 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5084 return rte_flow_error_set(error, EINVAL,
5085 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5086 "can have only one fate actions in"
5088 dev_priv = mlx5_dev_to_eswitch_info(dev);
5090 return rte_flow_error_set(error, rte_errno,
5091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5093 "failed to obtain E-Switch info");
5094 switch (action->type) {
5095 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5096 port_id = action->conf;
5097 port = port_id->original ? dev->data->port_id : port_id->id;
5099 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5100 ethdev = action->conf;
5101 port = ethdev->port_id;
5105 return rte_flow_error_set
5107 RTE_FLOW_ERROR_TYPE_ACTION, action,
5108 "unknown E-Switch action");
5110 act_priv = mlx5_port_to_eswitch_info(port, false);
5112 return rte_flow_error_set
5114 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5115 "failed to obtain E-Switch port id for port");
5116 if (act_priv->domain_id != dev_priv->domain_id)
5117 return rte_flow_error_set
5119 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5120 "port does not belong to"
5121 " E-Switch being configured");
5126 * Get the maximum number of modify header actions.
5129 * Pointer to rte_eth_dev structure.
5131 * Whether action is on root table.
5134 * Max number of modify header actions device can support.
5136 static inline unsigned int
5137 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5141 * There's no way to directly query the max capacity from FW.
5142 * The maximal value on root table should be assumed to be supported.
5145 return MLX5_MAX_MODIFY_NUM;
5147 return MLX5_ROOT_TBL_MODIFY_NUM;
5151 * Validate the meter action.
5154 * Pointer to rte_eth_dev structure.
5155 * @param[in] action_flags
5156 * Bit-fields that holds the actions detected until now.
5157 * @param[in] item_flags
5158 * Holds the items detected.
5160 * Pointer to the meter action.
5162 * Attributes of flow that includes this action.
5163 * @param[in] port_id_item
5164 * Pointer to item indicating port id.
5166 * Pointer to error structure.
5169 * 0 on success, a negative errno value otherwise and rte_errno is set.
5172 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5173 uint64_t action_flags, uint64_t item_flags,
5174 const struct rte_flow_action *action,
5175 const struct rte_flow_attr *attr,
5176 const struct rte_flow_item *port_id_item,
5178 struct rte_flow_error *error)
5180 struct mlx5_priv *priv = dev->data->dev_private;
5181 const struct rte_flow_action_meter *am = action->conf;
5182 struct mlx5_flow_meter_info *fm;
5183 struct mlx5_flow_meter_policy *mtr_policy;
5184 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5187 return rte_flow_error_set(error, EINVAL,
5188 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5189 "meter action conf is NULL");
5191 if (action_flags & MLX5_FLOW_ACTION_METER)
5192 return rte_flow_error_set(error, ENOTSUP,
5193 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5194 "meter chaining not support");
5195 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5196 return rte_flow_error_set(error, ENOTSUP,
5197 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5198 "meter with jump not support");
5200 return rte_flow_error_set(error, ENOTSUP,
5201 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5203 "meter action not supported");
5204 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5206 return rte_flow_error_set(error, EINVAL,
5207 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5209 /* aso meter can always be shared by different domains */
5210 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5211 !(fm->transfer == attr->transfer ||
5212 (!fm->ingress && !attr->ingress && attr->egress) ||
5213 (!fm->egress && !attr->egress && attr->ingress)))
5214 return rte_flow_error_set(error, EINVAL,
5215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5216 "Flow attributes domain are either invalid "
5217 "or have a domain conflict with current "
5218 "meter attributes");
5219 if (fm->def_policy) {
5220 if (!((attr->transfer &&
5221 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5223 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5225 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5226 return rte_flow_error_set(error, EINVAL,
5227 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5228 "Flow attributes domain "
5229 "have a conflict with current "
5230 "meter domain attributes");
5233 mtr_policy = mlx5_flow_meter_policy_find(dev,
5234 fm->policy_id, NULL);
5236 return rte_flow_error_set(error, EINVAL,
5237 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5238 "Invalid policy id for meter ");
5239 if (!((attr->transfer && mtr_policy->transfer) ||
5240 (attr->egress && mtr_policy->egress) ||
5241 (attr->ingress && mtr_policy->ingress)))
5242 return rte_flow_error_set(error, EINVAL,
5243 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5244 "Flow attributes domain "
5245 "have a conflict with current "
5246 "meter domain attributes");
5247 if (attr->transfer && mtr_policy->dev) {
5249 * When policy has fate action of port_id,
5250 * the flow should have the same src port as policy.
5252 struct mlx5_priv *policy_port_priv =
5253 mtr_policy->dev->data->dev_private;
5254 int32_t flow_src_port = priv->representor_id;
5257 const struct rte_flow_item_port_id *spec =
5259 struct mlx5_priv *port_priv =
5260 mlx5_port_to_eswitch_info(spec->id,
5263 return rte_flow_error_set(error,
5265 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5267 "Failed to get port info.");
5268 flow_src_port = port_priv->representor_id;
5270 if (flow_src_port != policy_port_priv->representor_id)
5271 return rte_flow_error_set(error,
5273 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5275 "Flow and meter policy "
5276 "have different src port.");
5277 } else if (mtr_policy->is_rss) {
5278 struct mlx5_flow_meter_policy *fp;
5279 struct mlx5_meter_policy_action_container *acg;
5280 struct mlx5_meter_policy_action_container *acy;
5281 const struct rte_flow_action *rss_act;
5284 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5287 return rte_flow_error_set(error, EINVAL,
5288 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5289 "Unable to get the final "
5290 "policy in the hierarchy");
5291 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5292 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5293 MLX5_ASSERT(acg->fate_action ==
5294 MLX5_FLOW_FATE_SHARED_RSS ||
5296 MLX5_FLOW_FATE_SHARED_RSS);
5297 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5301 ret = mlx5_flow_validate_action_rss(rss_act,
5302 action_flags, dev, attr,
5307 *def_policy = false;
5313 * Validate the age action.
5315 * @param[in] action_flags
5316 * Holds the actions detected until now.
5318 * Pointer to the age action.
5320 * Pointer to the Ethernet device structure.
5322 * Pointer to error structure.
5325 * 0 on success, a negative errno value otherwise and rte_errno is set.
5328 flow_dv_validate_action_age(uint64_t action_flags,
5329 const struct rte_flow_action *action,
5330 struct rte_eth_dev *dev,
5331 struct rte_flow_error *error)
5333 struct mlx5_priv *priv = dev->data->dev_private;
5334 const struct rte_flow_action_age *age = action->conf;
5336 if (!priv->sh->cdev->config.devx ||
5337 (priv->sh->cmng.counter_fallback && !priv->sh->aso_age_mng))
5338 return rte_flow_error_set(error, ENOTSUP,
5339 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5341 "age action not supported");
5342 if (!(action->conf))
5343 return rte_flow_error_set(error, EINVAL,
5344 RTE_FLOW_ERROR_TYPE_ACTION, action,
5345 "configuration cannot be null");
5346 if (!(age->timeout))
5347 return rte_flow_error_set(error, EINVAL,
5348 RTE_FLOW_ERROR_TYPE_ACTION, action,
5349 "invalid timeout value 0");
5350 if (action_flags & MLX5_FLOW_ACTION_AGE)
5351 return rte_flow_error_set(error, EINVAL,
5352 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5353 "duplicate age actions set");
5358 * Validate the modify-header IPv4 DSCP actions.
5360 * @param[in] action_flags
5361 * Holds the actions detected until now.
5363 * Pointer to the modify action.
5364 * @param[in] item_flags
5365 * Holds the items detected.
5367 * Pointer to error structure.
5370 * 0 on success, a negative errno value otherwise and rte_errno is set.
5373 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5374 const struct rte_flow_action *action,
5375 const uint64_t item_flags,
5376 struct rte_flow_error *error)
5380 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5382 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5383 return rte_flow_error_set(error, EINVAL,
5384 RTE_FLOW_ERROR_TYPE_ACTION,
5386 "no ipv4 item in pattern");
5392 * Validate the modify-header IPv6 DSCP actions.
5394 * @param[in] action_flags
5395 * Holds the actions detected until now.
5397 * Pointer to the modify action.
5398 * @param[in] item_flags
5399 * Holds the items detected.
5401 * Pointer to error structure.
5404 * 0 on success, a negative errno value otherwise and rte_errno is set.
5407 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5408 const struct rte_flow_action *action,
5409 const uint64_t item_flags,
5410 struct rte_flow_error *error)
5414 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5416 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5417 return rte_flow_error_set(error, EINVAL,
5418 RTE_FLOW_ERROR_TYPE_ACTION,
5420 "no ipv6 item in pattern");
5426 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5427 struct mlx5_list_entry *entry, void *cb_ctx)
5429 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5430 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5431 struct mlx5_flow_dv_modify_hdr_resource *resource =
5432 container_of(entry, typeof(*resource), entry);
5433 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5435 key_len += ref->actions_num * sizeof(ref->actions[0]);
5436 return ref->actions_num != resource->actions_num ||
5437 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5440 static struct mlx5_indexed_pool *
5441 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5443 struct mlx5_indexed_pool *ipool = __atomic_load_n
5444 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5447 struct mlx5_indexed_pool *expected = NULL;
5448 struct mlx5_indexed_pool_config cfg =
5449 (struct mlx5_indexed_pool_config) {
5450 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5452 sizeof(struct mlx5_modification_cmd),
5457 .release_mem_en = !!sh->config.reclaim_mode,
5459 sh->config.reclaim_mode ? 0 : (1 << 16),
5460 .malloc = mlx5_malloc,
5462 .type = "mlx5_modify_action_resource",
5465 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5466 ipool = mlx5_ipool_create(&cfg);
5469 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5470 &expected, ipool, false,
5472 __ATOMIC_SEQ_CST)) {
5473 mlx5_ipool_destroy(ipool);
5474 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5481 struct mlx5_list_entry *
5482 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5484 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5485 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5486 struct mlx5dv_dr_domain *ns;
5487 struct mlx5_flow_dv_modify_hdr_resource *entry;
5488 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5489 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5490 ref->actions_num - 1);
5492 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5493 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5496 if (unlikely(!ipool)) {
5497 rte_flow_error_set(ctx->error, ENOMEM,
5498 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5499 NULL, "cannot allocate modify ipool");
5502 entry = mlx5_ipool_zmalloc(ipool, &idx);
5504 rte_flow_error_set(ctx->error, ENOMEM,
5505 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5506 "cannot allocate resource memory");
5509 rte_memcpy(&entry->ft_type,
5510 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5511 key_len + data_len);
5512 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5513 ns = sh->fdb_domain;
5514 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5518 ret = mlx5_flow_os_create_flow_action_modify_header
5519 (sh->cdev->ctx, ns, entry,
5520 data_len, &entry->action);
5522 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5523 rte_flow_error_set(ctx->error, ENOMEM,
5524 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5525 NULL, "cannot create modification action");
5529 return &entry->entry;
5532 struct mlx5_list_entry *
5533 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5536 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5537 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5538 struct mlx5_flow_dv_modify_hdr_resource *entry;
5539 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5540 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5543 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5546 rte_flow_error_set(ctx->error, ENOMEM,
5547 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5548 "cannot allocate resource memory");
5551 memcpy(entry, oentry, sizeof(*entry) + data_len);
5553 return &entry->entry;
5557 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5559 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5560 struct mlx5_flow_dv_modify_hdr_resource *res =
5561 container_of(entry, typeof(*res), entry);
5563 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5567 * Validate the sample action.
5569 * @param[in, out] action_flags
5570 * Holds the actions detected until now.
5572 * Pointer to the sample action.
5574 * Pointer to the Ethernet device structure.
5576 * Attributes of flow that includes this action.
5577 * @param[in] item_flags
5578 * Holds the items detected.
5580 * Pointer to the RSS action.
5581 * @param[out] sample_rss
5582 * Pointer to the RSS action in sample action list.
5584 * Pointer to the COUNT action in sample action list.
5585 * @param[out] fdb_mirror_limit
5586 * Pointer to the FDB mirror limitation flag.
5588 * Pointer to error structure.
5591 * 0 on success, a negative errno value otherwise and rte_errno is set.
5594 flow_dv_validate_action_sample(uint64_t *action_flags,
5595 const struct rte_flow_action *action,
5596 struct rte_eth_dev *dev,
5597 const struct rte_flow_attr *attr,
5598 uint64_t item_flags,
5599 const struct rte_flow_action_rss *rss,
5600 const struct rte_flow_action_rss **sample_rss,
5601 const struct rte_flow_action_count **count,
5602 int *fdb_mirror_limit,
5603 struct rte_flow_error *error)
5605 struct mlx5_priv *priv = dev->data->dev_private;
5606 struct mlx5_sh_config *dev_conf = &priv->sh->config;
5607 const struct rte_flow_action_sample *sample = action->conf;
5608 const struct rte_flow_action *act;
5609 uint64_t sub_action_flags = 0;
5610 uint16_t queue_index = 0xFFFF;
5615 return rte_flow_error_set(error, EINVAL,
5616 RTE_FLOW_ERROR_TYPE_ACTION, action,
5617 "configuration cannot be NULL");
5618 if (sample->ratio == 0)
5619 return rte_flow_error_set(error, EINVAL,
5620 RTE_FLOW_ERROR_TYPE_ACTION, action,
5621 "ratio value starts from 1");
5622 if (!priv->sh->cdev->config.devx ||
5623 (sample->ratio > 0 && !priv->sampler_en))
5624 return rte_flow_error_set(error, ENOTSUP,
5625 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5627 "sample action not supported");
5628 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5629 return rte_flow_error_set(error, EINVAL,
5630 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5631 "Multiple sample actions not "
5633 if (*action_flags & MLX5_FLOW_ACTION_METER)
5634 return rte_flow_error_set(error, EINVAL,
5635 RTE_FLOW_ERROR_TYPE_ACTION, action,
5636 "wrong action order, meter should "
5637 "be after sample action");
5638 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5639 return rte_flow_error_set(error, EINVAL,
5640 RTE_FLOW_ERROR_TYPE_ACTION, action,
5641 "wrong action order, jump should "
5642 "be after sample action");
5643 if (*action_flags & MLX5_FLOW_ACTION_CT)
5644 return rte_flow_error_set(error, EINVAL,
5645 RTE_FLOW_ERROR_TYPE_ACTION, action,
5646 "Sample after CT not supported");
5647 act = sample->actions;
5648 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5649 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5650 return rte_flow_error_set(error, ENOTSUP,
5651 RTE_FLOW_ERROR_TYPE_ACTION,
5652 act, "too many actions");
5653 switch (act->type) {
5654 case RTE_FLOW_ACTION_TYPE_QUEUE:
5655 ret = mlx5_flow_validate_action_queue(act,
5661 queue_index = ((const struct rte_flow_action_queue *)
5662 (act->conf))->index;
5663 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5666 case RTE_FLOW_ACTION_TYPE_RSS:
5667 *sample_rss = act->conf;
5668 ret = mlx5_flow_validate_action_rss(act,
5675 if (rss && *sample_rss &&
5676 ((*sample_rss)->level != rss->level ||
5677 (*sample_rss)->types != rss->types))
5678 return rte_flow_error_set(error, ENOTSUP,
5679 RTE_FLOW_ERROR_TYPE_ACTION,
5681 "Can't use the different RSS types "
5682 "or level in the same flow");
5683 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5684 queue_index = (*sample_rss)->queue[0];
5685 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5688 case RTE_FLOW_ACTION_TYPE_MARK:
5689 ret = flow_dv_validate_action_mark(dev, act,
5694 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5695 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5696 MLX5_FLOW_ACTION_MARK_EXT;
5698 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5701 case RTE_FLOW_ACTION_TYPE_COUNT:
5702 ret = flow_dv_validate_action_count
5703 (dev, false, *action_flags | sub_action_flags,
5708 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5709 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5712 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5713 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5714 ret = flow_dv_validate_action_port_id(dev,
5721 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5724 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5725 ret = flow_dv_validate_action_raw_encap_decap
5726 (dev, NULL, act->conf, attr, &sub_action_flags,
5727 &actions_n, action, item_flags, error);
5732 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5733 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5734 ret = flow_dv_validate_action_l2_encap(dev,
5740 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5744 return rte_flow_error_set(error, ENOTSUP,
5745 RTE_FLOW_ERROR_TYPE_ACTION,
5747 "Doesn't support optional "
5751 if (attr->ingress && !attr->transfer) {
5752 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5753 MLX5_FLOW_ACTION_RSS)))
5754 return rte_flow_error_set(error, EINVAL,
5755 RTE_FLOW_ERROR_TYPE_ACTION,
5757 "Ingress must has a dest "
5758 "QUEUE for Sample");
5759 } else if (attr->egress && !attr->transfer) {
5760 return rte_flow_error_set(error, ENOTSUP,
5761 RTE_FLOW_ERROR_TYPE_ACTION,
5763 "Sample Only support Ingress "
5765 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5766 MLX5_ASSERT(attr->transfer);
5767 if (sample->ratio > 1)
5768 return rte_flow_error_set(error, ENOTSUP,
5769 RTE_FLOW_ERROR_TYPE_ACTION,
5771 "E-Switch doesn't support "
5772 "any optional action "
5774 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5775 return rte_flow_error_set(error, ENOTSUP,
5776 RTE_FLOW_ERROR_TYPE_ACTION,
5778 "unsupported action QUEUE");
5779 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5780 return rte_flow_error_set(error, ENOTSUP,
5781 RTE_FLOW_ERROR_TYPE_ACTION,
5783 "unsupported action QUEUE");
5784 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5785 return rte_flow_error_set(error, EINVAL,
5786 RTE_FLOW_ERROR_TYPE_ACTION,
5788 "E-Switch must has a dest "
5789 "port for mirroring");
5790 if (!priv->sh->cdev->config.hca_attr.reg_c_preserve &&
5791 priv->representor_id != UINT16_MAX)
5792 *fdb_mirror_limit = 1;
5794 /* Continue validation for Xcap actions.*/
5795 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5796 (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index))) {
5797 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5798 MLX5_FLOW_XCAP_ACTIONS)
5799 return rte_flow_error_set(error, ENOTSUP,
5800 RTE_FLOW_ERROR_TYPE_ACTION,
5801 NULL, "encap and decap "
5802 "combination aren't "
5804 if (!attr->transfer && attr->ingress && (sub_action_flags &
5805 MLX5_FLOW_ACTION_ENCAP))
5806 return rte_flow_error_set(error, ENOTSUP,
5807 RTE_FLOW_ERROR_TYPE_ACTION,
5808 NULL, "encap is not supported"
5809 " for ingress traffic");
5815 * Find existing modify-header resource or create and register a new one.
5817 * @param dev[in, out]
5818 * Pointer to rte_eth_dev structure.
5819 * @param[in, out] resource
5820 * Pointer to modify-header resource.
5821 * @parm[in, out] dev_flow
5822 * Pointer to the dev_flow.
5824 * pointer to error structure.
5827 * 0 on success otherwise -errno and errno is set.
5830 flow_dv_modify_hdr_resource_register
5831 (struct rte_eth_dev *dev,
5832 struct mlx5_flow_dv_modify_hdr_resource *resource,
5833 struct mlx5_flow *dev_flow,
5834 struct rte_flow_error *error)
5836 struct mlx5_priv *priv = dev->data->dev_private;
5837 struct mlx5_dev_ctx_shared *sh = priv->sh;
5838 uint32_t key_len = sizeof(*resource) -
5839 offsetof(typeof(*resource), ft_type) +
5840 resource->actions_num * sizeof(resource->actions[0]);
5841 struct mlx5_list_entry *entry;
5842 struct mlx5_flow_cb_ctx ctx = {
5846 struct mlx5_hlist *modify_cmds;
5849 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5851 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5853 flow_dv_modify_create_cb,
5854 flow_dv_modify_match_cb,
5855 flow_dv_modify_remove_cb,
5856 flow_dv_modify_clone_cb,
5857 flow_dv_modify_clone_free_cb,
5859 if (unlikely(!modify_cmds))
5861 resource->root = !dev_flow->dv.group;
5862 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5864 return rte_flow_error_set(error, EOVERFLOW,
5865 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5866 "too many modify header items");
5867 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5868 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5871 resource = container_of(entry, typeof(*resource), entry);
5872 dev_flow->handle->dvh.modify_hdr = resource;
5877 * Get DV flow counter by index.
5880 * Pointer to the Ethernet device structure.
5882 * mlx5 flow counter index in the container.
5884 * mlx5 flow counter pool in the container.
5887 * Pointer to the counter, NULL otherwise.
5889 static struct mlx5_flow_counter *
5890 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5892 struct mlx5_flow_counter_pool **ppool)
5894 struct mlx5_priv *priv = dev->data->dev_private;
5895 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5896 struct mlx5_flow_counter_pool *pool;
5898 /* Decrease to original index and clear shared bit. */
5899 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5900 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5901 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5905 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5909 * Check the devx counter belongs to the pool.
5912 * Pointer to the counter pool.
5914 * The counter devx ID.
5917 * True if counter belongs to the pool, false otherwise.
5920 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5922 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5923 MLX5_COUNTERS_PER_POOL;
5925 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5931 * Get a pool by devx counter ID.
5934 * Pointer to the counter management.
5936 * The counter devx ID.
5939 * The counter pool pointer if exists, NULL otherwise,
5941 static struct mlx5_flow_counter_pool *
5942 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5945 struct mlx5_flow_counter_pool *pool = NULL;
5947 rte_spinlock_lock(&cmng->pool_update_sl);
5948 /* Check last used pool. */
5949 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5950 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5951 pool = cmng->pools[cmng->last_pool_idx];
5954 /* ID out of range means no suitable pool in the container. */
5955 if (id > cmng->max_id || id < cmng->min_id)
5958 * Find the pool from the end of the container, since mostly counter
5959 * ID is sequence increasing, and the last pool should be the needed
5964 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5966 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5972 rte_spinlock_unlock(&cmng->pool_update_sl);
5977 * Resize a counter container.
5980 * Pointer to the Ethernet device structure.
5983 * 0 on success, otherwise negative errno value and rte_errno is set.
5986 flow_dv_container_resize(struct rte_eth_dev *dev)
5988 struct mlx5_priv *priv = dev->data->dev_private;
5989 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5990 void *old_pools = cmng->pools;
5991 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5992 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5993 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6000 memcpy(pools, old_pools, cmng->n *
6001 sizeof(struct mlx5_flow_counter_pool *));
6003 cmng->pools = pools;
6005 mlx5_free(old_pools);
6010 * Query a devx flow counter.
6013 * Pointer to the Ethernet device structure.
6014 * @param[in] counter
6015 * Index to the flow counter.
6017 * The statistics value of packets.
6019 * The statistics value of bytes.
6022 * 0 on success, otherwise a negative errno value and rte_errno is set.
6025 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
6028 struct mlx5_priv *priv = dev->data->dev_private;
6029 struct mlx5_flow_counter_pool *pool = NULL;
6030 struct mlx5_flow_counter *cnt;
6033 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6035 if (priv->sh->cmng.counter_fallback)
6036 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6037 0, pkts, bytes, 0, NULL, NULL, 0);
6038 rte_spinlock_lock(&pool->sl);
6043 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6044 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6045 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6047 rte_spinlock_unlock(&pool->sl);
6052 * Create and initialize a new counter pool.
6055 * Pointer to the Ethernet device structure.
6057 * The devX counter handle.
6059 * Whether the pool is for counter that was allocated for aging.
6060 * @param[in/out] cont_cur
6061 * Pointer to the container pointer, it will be update in pool resize.
6064 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6066 static struct mlx5_flow_counter_pool *
6067 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6070 struct mlx5_priv *priv = dev->data->dev_private;
6071 struct mlx5_flow_counter_pool *pool;
6072 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6073 bool fallback = priv->sh->cmng.counter_fallback;
6074 uint32_t size = sizeof(*pool);
6076 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6077 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6078 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6084 pool->is_aged = !!age;
6085 pool->query_gen = 0;
6086 pool->min_dcs = dcs;
6087 rte_spinlock_init(&pool->sl);
6088 rte_spinlock_init(&pool->csl);
6089 TAILQ_INIT(&pool->counters[0]);
6090 TAILQ_INIT(&pool->counters[1]);
6091 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6092 rte_spinlock_lock(&cmng->pool_update_sl);
6093 pool->index = cmng->n_valid;
6094 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6096 rte_spinlock_unlock(&cmng->pool_update_sl);
6099 cmng->pools[pool->index] = pool;
6101 if (unlikely(fallback)) {
6102 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6104 if (base < cmng->min_id)
6105 cmng->min_id = base;
6106 if (base > cmng->max_id)
6107 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6108 cmng->last_pool_idx = pool->index;
6110 rte_spinlock_unlock(&cmng->pool_update_sl);
6115 * Prepare a new counter and/or a new counter pool.
6118 * Pointer to the Ethernet device structure.
6119 * @param[out] cnt_free
6120 * Where to put the pointer of a new counter.
6122 * Whether the pool is for counter that was allocated for aging.
6125 * The counter pool pointer and @p cnt_free is set on success,
6126 * NULL otherwise and rte_errno is set.
6128 static struct mlx5_flow_counter_pool *
6129 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6130 struct mlx5_flow_counter **cnt_free,
6133 struct mlx5_priv *priv = dev->data->dev_private;
6134 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6135 struct mlx5_flow_counter_pool *pool;
6136 struct mlx5_counters tmp_tq;
6137 struct mlx5_devx_obj *dcs = NULL;
6138 struct mlx5_flow_counter *cnt;
6139 enum mlx5_counter_type cnt_type =
6140 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6141 bool fallback = priv->sh->cmng.counter_fallback;
6145 /* bulk_bitmap must be 0 for single counter allocation. */
6146 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6149 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6151 pool = flow_dv_pool_create(dev, dcs, age);
6153 mlx5_devx_cmd_destroy(dcs);
6157 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6158 cnt = MLX5_POOL_GET_CNT(pool, i);
6160 cnt->dcs_when_free = dcs;
6164 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6166 rte_errno = ENODATA;
6169 pool = flow_dv_pool_create(dev, dcs, age);
6171 mlx5_devx_cmd_destroy(dcs);
6174 TAILQ_INIT(&tmp_tq);
6175 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6176 cnt = MLX5_POOL_GET_CNT(pool, i);
6178 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6180 rte_spinlock_lock(&cmng->csl[cnt_type]);
6181 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6182 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6183 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6184 (*cnt_free)->pool = pool;
6189 * Allocate a flow counter.
6192 * Pointer to the Ethernet device structure.
6194 * Whether the counter was allocated for aging.
6197 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6200 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6202 struct mlx5_priv *priv = dev->data->dev_private;
6203 struct mlx5_flow_counter_pool *pool = NULL;
6204 struct mlx5_flow_counter *cnt_free = NULL;
6205 bool fallback = priv->sh->cmng.counter_fallback;
6206 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6207 enum mlx5_counter_type cnt_type =
6208 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6211 if (!priv->sh->cdev->config.devx) {
6212 rte_errno = ENOTSUP;
6215 /* Get free counters from container. */
6216 rte_spinlock_lock(&cmng->csl[cnt_type]);
6217 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6219 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6220 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6221 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6223 pool = cnt_free->pool;
6225 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6226 /* Create a DV counter action only in the first time usage. */
6227 if (!cnt_free->action) {
6229 struct mlx5_devx_obj *dcs;
6233 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6234 dcs = pool->min_dcs;
6237 dcs = cnt_free->dcs_when_free;
6239 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6246 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6247 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6248 /* Update the counter reset values. */
6249 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6252 if (!fallback && !priv->sh->cmng.query_thread_on)
6253 /* Start the asynchronous batch query by the host thread. */
6254 mlx5_set_query_alarm(priv->sh);
6256 * When the count action isn't shared (by ID), shared_info field is
6257 * used for indirect action API's refcnt.
6258 * When the counter action is not shared neither by ID nor by indirect
6259 * action API, shared info must be 1.
6261 cnt_free->shared_info.refcnt = 1;
6265 cnt_free->pool = pool;
6267 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6268 rte_spinlock_lock(&cmng->csl[cnt_type]);
6269 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6270 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6276 * Get age param from counter index.
6279 * Pointer to the Ethernet device structure.
6280 * @param[in] counter
6281 * Index to the counter handler.
6284 * The aging parameter specified for the counter index.
6286 static struct mlx5_age_param*
6287 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6290 struct mlx5_flow_counter *cnt;
6291 struct mlx5_flow_counter_pool *pool = NULL;
6293 flow_dv_counter_get_by_idx(dev, counter, &pool);
6294 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6295 cnt = MLX5_POOL_GET_CNT(pool, counter);
6296 return MLX5_CNT_TO_AGE(cnt);
6300 * Remove a flow counter from aged counter list.
6303 * Pointer to the Ethernet device structure.
6304 * @param[in] counter
6305 * Index to the counter handler.
6307 * Pointer to the counter handler.
6310 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6311 uint32_t counter, struct mlx5_flow_counter *cnt)
6313 struct mlx5_age_info *age_info;
6314 struct mlx5_age_param *age_param;
6315 struct mlx5_priv *priv = dev->data->dev_private;
6316 uint16_t expected = AGE_CANDIDATE;
6318 age_info = GET_PORT_AGE_INFO(priv);
6319 age_param = flow_dv_counter_idx_get_age(dev, counter);
6320 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6321 AGE_FREE, false, __ATOMIC_RELAXED,
6322 __ATOMIC_RELAXED)) {
6324 * We need the lock even it is age timeout,
6325 * since counter may still in process.
6327 rte_spinlock_lock(&age_info->aged_sl);
6328 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6329 rte_spinlock_unlock(&age_info->aged_sl);
6330 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6335 * Release a flow counter.
6338 * Pointer to the Ethernet device structure.
6339 * @param[in] counter
6340 * Index to the counter handler.
6343 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6345 struct mlx5_priv *priv = dev->data->dev_private;
6346 struct mlx5_flow_counter_pool *pool = NULL;
6347 struct mlx5_flow_counter *cnt;
6348 enum mlx5_counter_type cnt_type;
6352 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6354 if (pool->is_aged) {
6355 flow_dv_counter_remove_from_age(dev, counter, cnt);
6358 * If the counter action is shared by indirect action API,
6359 * the atomic function reduces its references counter.
6360 * If after the reduction the action is still referenced, the
6361 * function returns here and does not release it.
6362 * When the counter action is not shared by
6363 * indirect action API, shared info is 1 before the reduction,
6364 * so this condition is failed and function doesn't return here.
6366 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6372 * Put the counter back to list to be updated in none fallback mode.
6373 * Currently, we are using two list alternately, while one is in query,
6374 * add the freed counter to the other list based on the pool query_gen
6375 * value. After query finishes, add counter the list to the global
6376 * container counter list. The list changes while query starts. In
6377 * this case, lock will not be needed as query callback and release
6378 * function both operate with the different list.
6380 if (!priv->sh->cmng.counter_fallback) {
6381 rte_spinlock_lock(&pool->csl);
6382 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6383 rte_spinlock_unlock(&pool->csl);
6385 cnt->dcs_when_free = cnt->dcs_when_active;
6386 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6387 MLX5_COUNTER_TYPE_ORIGIN;
6388 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6389 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6391 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6396 * Resize a meter id container.
6399 * Pointer to the Ethernet device structure.
6402 * 0 on success, otherwise negative errno value and rte_errno is set.
6405 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6407 struct mlx5_priv *priv = dev->data->dev_private;
6408 struct mlx5_aso_mtr_pools_mng *pools_mng =
6409 &priv->sh->mtrmng->pools_mng;
6410 void *old_pools = pools_mng->pools;
6411 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6412 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6413 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6420 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6425 memcpy(pools, old_pools, pools_mng->n *
6426 sizeof(struct mlx5_aso_mtr_pool *));
6427 pools_mng->n = resize;
6428 pools_mng->pools = pools;
6430 mlx5_free(old_pools);
6435 * Prepare a new meter and/or a new meter pool.
6438 * Pointer to the Ethernet device structure.
6439 * @param[out] mtr_free
6440 * Where to put the pointer of a new meter.g.
6443 * The meter pool pointer and @mtr_free is set on success,
6444 * NULL otherwise and rte_errno is set.
6446 static struct mlx5_aso_mtr_pool *
6447 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6449 struct mlx5_priv *priv = dev->data->dev_private;
6450 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6451 struct mlx5_aso_mtr_pool *pool = NULL;
6452 struct mlx5_devx_obj *dcs = NULL;
6454 uint32_t log_obj_size;
6456 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6457 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6458 priv->sh->cdev->pdn,
6461 rte_errno = ENODATA;
6464 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6467 claim_zero(mlx5_devx_cmd_destroy(dcs));
6470 pool->devx_obj = dcs;
6471 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6472 pool->index = pools_mng->n_valid;
6473 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6475 claim_zero(mlx5_devx_cmd_destroy(dcs));
6476 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6479 pools_mng->pools[pool->index] = pool;
6480 pools_mng->n_valid++;
6481 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6482 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6483 pool->mtrs[i].offset = i;
6484 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6486 pool->mtrs[0].offset = 0;
6487 *mtr_free = &pool->mtrs[0];
6492 * Release a flow meter into pool.
6495 * Pointer to the Ethernet device structure.
6496 * @param[in] mtr_idx
6497 * Index to aso flow meter.
6500 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6502 struct mlx5_priv *priv = dev->data->dev_private;
6503 struct mlx5_aso_mtr_pools_mng *pools_mng =
6504 &priv->sh->mtrmng->pools_mng;
6505 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6507 MLX5_ASSERT(aso_mtr);
6508 rte_spinlock_lock(&pools_mng->mtrsl);
6509 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6510 aso_mtr->state = ASO_METER_FREE;
6511 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6512 rte_spinlock_unlock(&pools_mng->mtrsl);
6516 * Allocate a aso flow meter.
6519 * Pointer to the Ethernet device structure.
6522 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6525 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6527 struct mlx5_priv *priv = dev->data->dev_private;
6528 struct mlx5_aso_mtr *mtr_free = NULL;
6529 struct mlx5_aso_mtr_pools_mng *pools_mng =
6530 &priv->sh->mtrmng->pools_mng;
6531 struct mlx5_aso_mtr_pool *pool;
6532 uint32_t mtr_idx = 0;
6534 if (!priv->sh->cdev->config.devx) {
6535 rte_errno = ENOTSUP;
6538 /* Allocate the flow meter memory. */
6539 /* Get free meters from management. */
6540 rte_spinlock_lock(&pools_mng->mtrsl);
6541 mtr_free = LIST_FIRST(&pools_mng->meters);
6543 LIST_REMOVE(mtr_free, next);
6544 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6545 rte_spinlock_unlock(&pools_mng->mtrsl);
6548 mtr_free->state = ASO_METER_WAIT;
6549 rte_spinlock_unlock(&pools_mng->mtrsl);
6550 pool = container_of(mtr_free,
6551 struct mlx5_aso_mtr_pool,
6552 mtrs[mtr_free->offset]);
6553 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6554 if (!mtr_free->fm.meter_action) {
6555 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6556 struct rte_flow_error error;
6559 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6560 mtr_free->fm.meter_action =
6561 mlx5_glue->dv_create_flow_action_aso
6562 (priv->sh->rx_domain,
6563 pool->devx_obj->obj,
6565 (1 << MLX5_FLOW_COLOR_GREEN),
6567 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6568 if (!mtr_free->fm.meter_action) {
6569 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6577 * Verify the @p attributes will be correctly understood by the NIC and store
6578 * them in the @p flow if everything is correct.
6581 * Pointer to dev struct.
6582 * @param[in] attributes
6583 * Pointer to flow attributes
6584 * @param[in] external
6585 * This flow rule is created by request external to PMD.
6587 * Pointer to error structure.
6590 * - 0 on success and non root table.
6591 * - 1 on success and root table.
6592 * - a negative errno value otherwise and rte_errno is set.
6595 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6596 const struct mlx5_flow_tunnel *tunnel,
6597 const struct rte_flow_attr *attributes,
6598 const struct flow_grp_info *grp_info,
6599 struct rte_flow_error *error)
6601 struct mlx5_priv *priv = dev->data->dev_private;
6602 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6605 #ifndef HAVE_MLX5DV_DR
6606 RTE_SET_USED(tunnel);
6607 RTE_SET_USED(grp_info);
6608 if (attributes->group)
6609 return rte_flow_error_set(error, ENOTSUP,
6610 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6612 "groups are not supported");
6616 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6621 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6623 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6624 attributes->priority > lowest_priority)
6625 return rte_flow_error_set(error, ENOTSUP,
6626 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6628 "priority out of range");
6629 if (attributes->transfer) {
6630 if (!priv->sh->config.dv_esw_en)
6631 return rte_flow_error_set
6633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6634 "E-Switch dr is not supported");
6635 if (attributes->egress)
6636 return rte_flow_error_set
6638 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6639 "egress is not supported");
6641 if (!(attributes->egress ^ attributes->ingress))
6642 return rte_flow_error_set(error, ENOTSUP,
6643 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6644 "must specify exactly one of "
6645 "ingress or egress");
6650 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6651 int64_t pattern_flags, uint64_t l3_flags,
6652 uint64_t l4_flags, uint64_t ip4_flag,
6653 struct rte_flow_error *error)
6655 if (mask->l3_ok && !(pattern_flags & l3_flags))
6656 return rte_flow_error_set(error, EINVAL,
6657 RTE_FLOW_ERROR_TYPE_ITEM,
6658 NULL, "missing L3 protocol");
6660 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6661 return rte_flow_error_set(error, EINVAL,
6662 RTE_FLOW_ERROR_TYPE_ITEM,
6663 NULL, "missing IPv4 protocol");
6665 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6666 return rte_flow_error_set(error, EINVAL,
6667 RTE_FLOW_ERROR_TYPE_ITEM,
6668 NULL, "missing L4 protocol");
6674 flow_dv_validate_item_integrity_post(const struct
6675 rte_flow_item *integrity_items[2],
6676 int64_t pattern_flags,
6677 struct rte_flow_error *error)
6679 const struct rte_flow_item_integrity *mask;
6682 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6683 mask = (typeof(mask))integrity_items[0]->mask;
6684 ret = validate_integrity_bits(mask, pattern_flags,
6685 MLX5_FLOW_LAYER_OUTER_L3,
6686 MLX5_FLOW_LAYER_OUTER_L4,
6687 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6692 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6693 mask = (typeof(mask))integrity_items[1]->mask;
6694 ret = validate_integrity_bits(mask, pattern_flags,
6695 MLX5_FLOW_LAYER_INNER_L3,
6696 MLX5_FLOW_LAYER_INNER_L4,
6697 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6706 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6707 const struct rte_flow_item *integrity_item,
6708 uint64_t pattern_flags, uint64_t *last_item,
6709 const struct rte_flow_item *integrity_items[2],
6710 struct rte_flow_error *error)
6712 struct mlx5_priv *priv = dev->data->dev_private;
6713 const struct rte_flow_item_integrity *mask = (typeof(mask))
6714 integrity_item->mask;
6715 const struct rte_flow_item_integrity *spec = (typeof(spec))
6716 integrity_item->spec;
6718 if (!priv->sh->cdev->config.hca_attr.pkt_integrity_match)
6719 return rte_flow_error_set(error, ENOTSUP,
6720 RTE_FLOW_ERROR_TYPE_ITEM,
6722 "packet integrity integrity_item not supported");
6724 return rte_flow_error_set(error, ENOTSUP,
6725 RTE_FLOW_ERROR_TYPE_ITEM,
6727 "no spec for integrity item");
6729 mask = &rte_flow_item_integrity_mask;
6730 if (!mlx5_validate_integrity_item(mask))
6731 return rte_flow_error_set(error, ENOTSUP,
6732 RTE_FLOW_ERROR_TYPE_ITEM,
6734 "unsupported integrity filter");
6735 if (spec->level > 1) {
6736 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6737 return rte_flow_error_set
6739 RTE_FLOW_ERROR_TYPE_ITEM,
6740 NULL, "multiple inner integrity items not supported");
6741 integrity_items[1] = integrity_item;
6742 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6744 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6745 return rte_flow_error_set
6747 RTE_FLOW_ERROR_TYPE_ITEM,
6748 NULL, "multiple outer integrity items not supported");
6749 integrity_items[0] = integrity_item;
6750 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6756 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6757 const struct rte_flow_item *item,
6758 uint64_t item_flags,
6759 uint64_t *last_item,
6761 struct rte_flow_error *error)
6763 const struct rte_flow_item_flex *flow_spec = item->spec;
6764 const struct rte_flow_item_flex *flow_mask = item->mask;
6765 struct mlx5_flex_item *flex;
6768 return rte_flow_error_set(error, EINVAL,
6769 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6770 "flex flow item spec cannot be NULL");
6772 return rte_flow_error_set(error, EINVAL,
6773 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6774 "flex flow item mask cannot be NULL");
6776 return rte_flow_error_set(error, ENOTSUP,
6777 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6778 "flex flow item last not supported");
6779 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6780 return rte_flow_error_set(error, EINVAL,
6781 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6782 "invalid flex flow item handle");
6783 flex = (struct mlx5_flex_item *)flow_spec->handle;
6784 switch (flex->tunnel_mode) {
6785 case FLEX_TUNNEL_MODE_SINGLE:
6787 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6788 rte_flow_error_set(error, EINVAL,
6789 RTE_FLOW_ERROR_TYPE_ITEM,
6790 NULL, "multiple flex items not supported");
6792 case FLEX_TUNNEL_MODE_OUTER:
6794 rte_flow_error_set(error, EINVAL,
6795 RTE_FLOW_ERROR_TYPE_ITEM,
6796 NULL, "inner flex item was not configured");
6797 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6798 rte_flow_error_set(error, ENOTSUP,
6799 RTE_FLOW_ERROR_TYPE_ITEM,
6800 NULL, "multiple flex items not supported");
6802 case FLEX_TUNNEL_MODE_INNER:
6804 rte_flow_error_set(error, EINVAL,
6805 RTE_FLOW_ERROR_TYPE_ITEM,
6806 NULL, "outer flex item was not configured");
6807 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6808 rte_flow_error_set(error, EINVAL,
6809 RTE_FLOW_ERROR_TYPE_ITEM,
6810 NULL, "multiple flex items not supported");
6812 case FLEX_TUNNEL_MODE_MULTI:
6813 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6814 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6815 rte_flow_error_set(error, EINVAL,
6816 RTE_FLOW_ERROR_TYPE_ITEM,
6817 NULL, "multiple flex items not supported");
6820 case FLEX_TUNNEL_MODE_TUNNEL:
6821 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6822 rte_flow_error_set(error, EINVAL,
6823 RTE_FLOW_ERROR_TYPE_ITEM,
6824 NULL, "multiple flex tunnel items not supported");
6827 rte_flow_error_set(error, EINVAL,
6828 RTE_FLOW_ERROR_TYPE_ITEM,
6829 NULL, "invalid flex item configuration");
6831 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6832 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6833 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6838 * Internal validation function. For validating both actions and items.
6841 * Pointer to the rte_eth_dev structure.
6843 * Pointer to the flow attributes.
6845 * Pointer to the list of items.
6846 * @param[in] actions
6847 * Pointer to the list of actions.
6848 * @param[in] external
6849 * This flow rule is created by request external to PMD.
6850 * @param[in] hairpin
6851 * Number of hairpin TX actions, 0 means classic flow.
6853 * Pointer to the error structure.
6856 * 0 on success, a negative errno value otherwise and rte_errno is set.
6859 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6860 const struct rte_flow_item items[],
6861 const struct rte_flow_action actions[],
6862 bool external, int hairpin, struct rte_flow_error *error)
6865 uint64_t action_flags = 0;
6866 uint64_t item_flags = 0;
6867 uint64_t last_item = 0;
6868 uint8_t next_protocol = 0xff;
6869 uint16_t ether_type = 0;
6871 uint8_t item_ipv6_proto = 0;
6872 int fdb_mirror_limit = 0;
6873 int modify_after_mirror = 0;
6874 const struct rte_flow_item *geneve_item = NULL;
6875 const struct rte_flow_item *gre_item = NULL;
6876 const struct rte_flow_item *gtp_item = NULL;
6877 const struct rte_flow_action_raw_decap *decap;
6878 const struct rte_flow_action_raw_encap *encap;
6879 const struct rte_flow_action_rss *rss = NULL;
6880 const struct rte_flow_action_rss *sample_rss = NULL;
6881 const struct rte_flow_action_count *sample_count = NULL;
6882 const struct rte_flow_item_tcp nic_tcp_mask = {
6885 .src_port = RTE_BE16(UINT16_MAX),
6886 .dst_port = RTE_BE16(UINT16_MAX),
6889 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6892 "\xff\xff\xff\xff\xff\xff\xff\xff"
6893 "\xff\xff\xff\xff\xff\xff\xff\xff",
6895 "\xff\xff\xff\xff\xff\xff\xff\xff"
6896 "\xff\xff\xff\xff\xff\xff\xff\xff",
6897 .vtc_flow = RTE_BE32(0xffffffff),
6903 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6907 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6911 .dummy[0] = 0xffffffff,
6914 struct mlx5_priv *priv = dev->data->dev_private;
6915 struct mlx5_sh_config *dev_conf = &priv->sh->config;
6916 uint16_t queue_index = 0xFFFF;
6917 const struct rte_flow_item_vlan *vlan_m = NULL;
6918 uint32_t rw_act_num = 0;
6920 const struct mlx5_flow_tunnel *tunnel;
6921 enum mlx5_tof_rule_type tof_rule_type;
6922 struct flow_grp_info grp_info = {
6923 .external = !!external,
6924 .transfer = !!attr->transfer,
6925 .fdb_def_rule = !!priv->fdb_def_rule,
6926 .std_tbl_fix = true,
6928 const struct rte_eth_hairpin_conf *conf;
6929 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6930 const struct rte_flow_item *port_id_item = NULL;
6931 bool def_policy = false;
6932 bool shared_count = false;
6933 uint16_t udp_dport = 0;
6937 tunnel = is_tunnel_offload_active(dev) ?
6938 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6940 if (!dev_conf->dv_flow_en)
6941 return rte_flow_error_set
6943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6944 NULL, "tunnel offload requires DV flow interface");
6945 if (priv->representor)
6946 return rte_flow_error_set
6948 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6949 NULL, "decap not supported for VF representor");
6950 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6951 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6952 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6953 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6954 MLX5_FLOW_ACTION_DECAP;
6955 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6956 (dev, attr, tunnel, tof_rule_type);
6958 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6961 is_root = (uint64_t)ret;
6962 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6963 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6964 int type = items->type;
6966 if (!mlx5_flow_os_item_supported(type))
6967 return rte_flow_error_set(error, ENOTSUP,
6968 RTE_FLOW_ERROR_TYPE_ITEM,
6969 NULL, "item not supported");
6971 case RTE_FLOW_ITEM_TYPE_VOID:
6973 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6974 ret = flow_dv_validate_item_port_id
6975 (dev, items, attr, item_flags, error);
6978 last_item = MLX5_FLOW_ITEM_PORT_ID;
6979 port_id_item = items;
6981 case RTE_FLOW_ITEM_TYPE_ETH:
6982 ret = mlx5_flow_validate_item_eth(items, item_flags,
6986 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6987 MLX5_FLOW_LAYER_OUTER_L2;
6988 if (items->mask != NULL && items->spec != NULL) {
6990 ((const struct rte_flow_item_eth *)
6993 ((const struct rte_flow_item_eth *)
6995 ether_type = rte_be_to_cpu_16(ether_type);
7000 case RTE_FLOW_ITEM_TYPE_VLAN:
7001 ret = flow_dv_validate_item_vlan(items, item_flags,
7005 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
7006 MLX5_FLOW_LAYER_OUTER_VLAN;
7007 if (items->mask != NULL && items->spec != NULL) {
7009 ((const struct rte_flow_item_vlan *)
7010 items->spec)->inner_type;
7012 ((const struct rte_flow_item_vlan *)
7013 items->mask)->inner_type;
7014 ether_type = rte_be_to_cpu_16(ether_type);
7018 /* Store outer VLAN mask for of_push_vlan action. */
7020 vlan_m = items->mask;
7022 case RTE_FLOW_ITEM_TYPE_IPV4:
7023 mlx5_flow_tunnel_ip_check(items, next_protocol,
7024 &item_flags, &tunnel);
7025 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
7026 last_item, ether_type,
7030 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7031 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7032 if (items->mask != NULL &&
7033 ((const struct rte_flow_item_ipv4 *)
7034 items->mask)->hdr.next_proto_id) {
7036 ((const struct rte_flow_item_ipv4 *)
7037 (items->spec))->hdr.next_proto_id;
7039 ((const struct rte_flow_item_ipv4 *)
7040 (items->mask))->hdr.next_proto_id;
7042 /* Reset for inner layer. */
7043 next_protocol = 0xff;
7046 case RTE_FLOW_ITEM_TYPE_IPV6:
7047 mlx5_flow_tunnel_ip_check(items, next_protocol,
7048 &item_flags, &tunnel);
7049 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7056 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7057 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7058 if (items->mask != NULL &&
7059 ((const struct rte_flow_item_ipv6 *)
7060 items->mask)->hdr.proto) {
7062 ((const struct rte_flow_item_ipv6 *)
7063 items->spec)->hdr.proto;
7065 ((const struct rte_flow_item_ipv6 *)
7066 items->spec)->hdr.proto;
7068 ((const struct rte_flow_item_ipv6 *)
7069 items->mask)->hdr.proto;
7071 /* Reset for inner layer. */
7072 next_protocol = 0xff;
7075 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7076 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7081 last_item = tunnel ?
7082 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7083 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7084 if (items->mask != NULL &&
7085 ((const struct rte_flow_item_ipv6_frag_ext *)
7086 items->mask)->hdr.next_header) {
7088 ((const struct rte_flow_item_ipv6_frag_ext *)
7089 items->spec)->hdr.next_header;
7091 ((const struct rte_flow_item_ipv6_frag_ext *)
7092 items->mask)->hdr.next_header;
7094 /* Reset for inner layer. */
7095 next_protocol = 0xff;
7098 case RTE_FLOW_ITEM_TYPE_TCP:
7099 ret = mlx5_flow_validate_item_tcp
7106 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7107 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7109 case RTE_FLOW_ITEM_TYPE_UDP:
7110 ret = mlx5_flow_validate_item_udp(items, item_flags,
7113 const struct rte_flow_item_udp *spec = items->spec;
7114 const struct rte_flow_item_udp *mask = items->mask;
7116 mask = &rte_flow_item_udp_mask;
7118 udp_dport = rte_be_to_cpu_16
7119 (spec->hdr.dst_port &
7120 mask->hdr.dst_port);
7123 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7124 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7126 case RTE_FLOW_ITEM_TYPE_GRE:
7127 ret = mlx5_flow_validate_item_gre(items, item_flags,
7128 next_protocol, error);
7132 last_item = MLX5_FLOW_LAYER_GRE;
7134 case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
7135 ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
7136 attr, gre_item, error);
7139 last_item = MLX5_FLOW_LAYER_GRE;
7141 case RTE_FLOW_ITEM_TYPE_NVGRE:
7142 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7147 last_item = MLX5_FLOW_LAYER_NVGRE;
7149 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7150 ret = mlx5_flow_validate_item_gre_key
7151 (items, item_flags, gre_item, error);
7154 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7156 case RTE_FLOW_ITEM_TYPE_VXLAN:
7157 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7162 last_item = MLX5_FLOW_LAYER_VXLAN;
7164 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7165 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7170 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7172 case RTE_FLOW_ITEM_TYPE_GENEVE:
7173 ret = mlx5_flow_validate_item_geneve(items,
7178 geneve_item = items;
7179 last_item = MLX5_FLOW_LAYER_GENEVE;
7181 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7182 ret = mlx5_flow_validate_item_geneve_opt(items,
7189 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7191 case RTE_FLOW_ITEM_TYPE_MPLS:
7192 ret = mlx5_flow_validate_item_mpls(dev, items,
7197 last_item = MLX5_FLOW_LAYER_MPLS;
7200 case RTE_FLOW_ITEM_TYPE_MARK:
7201 ret = flow_dv_validate_item_mark(dev, items, attr,
7205 last_item = MLX5_FLOW_ITEM_MARK;
7207 case RTE_FLOW_ITEM_TYPE_META:
7208 ret = flow_dv_validate_item_meta(dev, items, attr,
7212 last_item = MLX5_FLOW_ITEM_METADATA;
7214 case RTE_FLOW_ITEM_TYPE_ICMP:
7215 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7220 last_item = MLX5_FLOW_LAYER_ICMP;
7222 case RTE_FLOW_ITEM_TYPE_ICMP6:
7223 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7228 item_ipv6_proto = IPPROTO_ICMPV6;
7229 last_item = MLX5_FLOW_LAYER_ICMP6;
7231 case RTE_FLOW_ITEM_TYPE_TAG:
7232 ret = flow_dv_validate_item_tag(dev, items,
7236 last_item = MLX5_FLOW_ITEM_TAG;
7238 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7239 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7241 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7243 case RTE_FLOW_ITEM_TYPE_GTP:
7244 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7249 last_item = MLX5_FLOW_LAYER_GTP;
7251 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7252 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7257 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7259 case RTE_FLOW_ITEM_TYPE_ECPRI:
7260 /* Capacity will be checked in the translate stage. */
7261 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7268 last_item = MLX5_FLOW_LAYER_ECPRI;
7270 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7271 ret = flow_dv_validate_item_integrity(dev, items,
7279 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7280 ret = flow_dv_validate_item_aso_ct(dev, items,
7281 &item_flags, error);
7285 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7286 /* tunnel offload item was processed before
7287 * list it here as a supported type
7290 case RTE_FLOW_ITEM_TYPE_FLEX:
7291 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7293 tunnel != 0, error);
7298 return rte_flow_error_set(error, ENOTSUP,
7299 RTE_FLOW_ERROR_TYPE_ITEM,
7300 NULL, "item not supported");
7302 item_flags |= last_item;
7304 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7305 ret = flow_dv_validate_item_integrity_post(integrity_items,
7310 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7311 int type = actions->type;
7313 if (!mlx5_flow_os_action_supported(type))
7314 return rte_flow_error_set(error, ENOTSUP,
7315 RTE_FLOW_ERROR_TYPE_ACTION,
7317 "action not supported");
7318 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7319 return rte_flow_error_set(error, ENOTSUP,
7320 RTE_FLOW_ERROR_TYPE_ACTION,
7321 actions, "too many actions");
7323 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7324 return rte_flow_error_set(error, ENOTSUP,
7325 RTE_FLOW_ERROR_TYPE_ACTION,
7326 NULL, "meter action with policy "
7327 "must be the last action");
7329 case RTE_FLOW_ACTION_TYPE_VOID:
7331 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7332 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7333 ret = flow_dv_validate_action_port_id(dev,
7340 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7343 case RTE_FLOW_ACTION_TYPE_FLAG:
7344 ret = flow_dv_validate_action_flag(dev, action_flags,
7348 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7349 /* Count all modify-header actions as one. */
7350 if (!(action_flags &
7351 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7353 action_flags |= MLX5_FLOW_ACTION_FLAG |
7354 MLX5_FLOW_ACTION_MARK_EXT;
7355 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7356 modify_after_mirror = 1;
7359 action_flags |= MLX5_FLOW_ACTION_FLAG;
7362 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7364 case RTE_FLOW_ACTION_TYPE_MARK:
7365 ret = flow_dv_validate_action_mark(dev, actions,
7370 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7371 /* Count all modify-header actions as one. */
7372 if (!(action_flags &
7373 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7375 action_flags |= MLX5_FLOW_ACTION_MARK |
7376 MLX5_FLOW_ACTION_MARK_EXT;
7377 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7378 modify_after_mirror = 1;
7380 action_flags |= MLX5_FLOW_ACTION_MARK;
7383 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7385 case RTE_FLOW_ACTION_TYPE_SET_META:
7386 ret = flow_dv_validate_action_set_meta(dev, actions,
7391 /* Count all modify-header actions as one action. */
7392 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7394 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7395 modify_after_mirror = 1;
7396 action_flags |= MLX5_FLOW_ACTION_SET_META;
7397 rw_act_num += MLX5_ACT_NUM_SET_META;
7399 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7400 ret = flow_dv_validate_action_set_tag(dev, actions,
7405 /* Count all modify-header actions as one action. */
7406 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7408 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7409 modify_after_mirror = 1;
7410 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7411 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7413 case RTE_FLOW_ACTION_TYPE_DROP:
7414 ret = mlx5_flow_validate_action_drop(action_flags,
7418 action_flags |= MLX5_FLOW_ACTION_DROP;
7421 case RTE_FLOW_ACTION_TYPE_QUEUE:
7422 ret = mlx5_flow_validate_action_queue(actions,
7427 queue_index = ((const struct rte_flow_action_queue *)
7428 (actions->conf))->index;
7429 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7432 case RTE_FLOW_ACTION_TYPE_RSS:
7433 rss = actions->conf;
7434 ret = mlx5_flow_validate_action_rss(actions,
7440 if (rss && sample_rss &&
7441 (sample_rss->level != rss->level ||
7442 sample_rss->types != rss->types))
7443 return rte_flow_error_set(error, ENOTSUP,
7444 RTE_FLOW_ERROR_TYPE_ACTION,
7446 "Can't use the different RSS types "
7447 "or level in the same flow");
7448 if (rss != NULL && rss->queue_num)
7449 queue_index = rss->queue[0];
7450 action_flags |= MLX5_FLOW_ACTION_RSS;
7453 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7455 mlx5_flow_validate_action_default_miss(action_flags,
7459 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7462 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7463 shared_count = true;
7465 case RTE_FLOW_ACTION_TYPE_COUNT:
7466 ret = flow_dv_validate_action_count(dev, shared_count,
7471 action_flags |= MLX5_FLOW_ACTION_COUNT;
7474 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7475 if (flow_dv_validate_action_pop_vlan(dev,
7481 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7482 modify_after_mirror = 1;
7483 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7486 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7487 ret = flow_dv_validate_action_push_vlan(dev,
7494 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7495 modify_after_mirror = 1;
7496 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7499 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7500 ret = flow_dv_validate_action_set_vlan_pcp
7501 (action_flags, actions, error);
7504 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7505 modify_after_mirror = 1;
7506 /* Count PCP with push_vlan command. */
7507 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7509 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7510 ret = flow_dv_validate_action_set_vlan_vid
7511 (item_flags, action_flags,
7515 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7516 modify_after_mirror = 1;
7517 /* Count VID with push_vlan command. */
7518 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7519 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7521 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7522 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7523 ret = flow_dv_validate_action_l2_encap(dev,
7529 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7532 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7533 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7534 ret = flow_dv_validate_action_decap(dev, action_flags,
7535 actions, item_flags,
7539 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7540 modify_after_mirror = 1;
7541 action_flags |= MLX5_FLOW_ACTION_DECAP;
7544 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7545 ret = flow_dv_validate_action_raw_encap_decap
7546 (dev, NULL, actions->conf, attr, &action_flags,
7547 &actions_n, actions, item_flags, error);
7551 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7552 decap = actions->conf;
7553 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7555 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7559 encap = actions->conf;
7561 ret = flow_dv_validate_action_raw_encap_decap
7563 decap ? decap : &empty_decap, encap,
7564 attr, &action_flags, &actions_n,
7565 actions, item_flags, error);
7568 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7569 (action_flags & MLX5_FLOW_ACTION_DECAP))
7570 modify_after_mirror = 1;
7572 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7573 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7574 ret = flow_dv_validate_action_modify_mac(action_flags,
7580 /* Count all modify-header actions as one action. */
7581 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7583 action_flags |= actions->type ==
7584 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7585 MLX5_FLOW_ACTION_SET_MAC_SRC :
7586 MLX5_FLOW_ACTION_SET_MAC_DST;
7587 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7588 modify_after_mirror = 1;
7590 * Even if the source and destination MAC addresses have
7591 * overlap in the header with 4B alignment, the convert
7592 * function will handle them separately and 4 SW actions
7593 * will be created. And 2 actions will be added each
7594 * time no matter how many bytes of address will be set.
7596 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7598 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7599 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7600 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7606 /* Count all modify-header actions as one action. */
7607 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7609 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7610 modify_after_mirror = 1;
7611 action_flags |= actions->type ==
7612 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7613 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7614 MLX5_FLOW_ACTION_SET_IPV4_DST;
7615 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7617 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7618 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7619 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7625 if (item_ipv6_proto == IPPROTO_ICMPV6)
7626 return rte_flow_error_set(error, ENOTSUP,
7627 RTE_FLOW_ERROR_TYPE_ACTION,
7629 "Can't change header "
7630 "with ICMPv6 proto");
7631 /* Count all modify-header actions as one action. */
7632 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7634 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7635 modify_after_mirror = 1;
7636 action_flags |= actions->type ==
7637 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7638 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7639 MLX5_FLOW_ACTION_SET_IPV6_DST;
7640 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7642 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7643 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7644 ret = flow_dv_validate_action_modify_tp(action_flags,
7650 /* Count all modify-header actions as one action. */
7651 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7653 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7654 modify_after_mirror = 1;
7655 action_flags |= actions->type ==
7656 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7657 MLX5_FLOW_ACTION_SET_TP_SRC :
7658 MLX5_FLOW_ACTION_SET_TP_DST;
7659 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7661 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7662 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7663 ret = flow_dv_validate_action_modify_ttl(action_flags,
7669 /* Count all modify-header actions as one action. */
7670 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7672 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7673 modify_after_mirror = 1;
7674 action_flags |= actions->type ==
7675 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7676 MLX5_FLOW_ACTION_SET_TTL :
7677 MLX5_FLOW_ACTION_DEC_TTL;
7678 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7680 case RTE_FLOW_ACTION_TYPE_JUMP:
7681 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7687 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7689 return rte_flow_error_set(error, EINVAL,
7690 RTE_FLOW_ERROR_TYPE_ACTION,
7692 "sample and jump action combination is not supported");
7694 action_flags |= MLX5_FLOW_ACTION_JUMP;
7696 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7697 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7698 ret = flow_dv_validate_action_modify_tcp_seq
7705 /* Count all modify-header actions as one action. */
7706 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7708 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7709 modify_after_mirror = 1;
7710 action_flags |= actions->type ==
7711 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7712 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7713 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7714 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7716 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7717 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7718 ret = flow_dv_validate_action_modify_tcp_ack
7725 /* Count all modify-header actions as one action. */
7726 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7728 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7729 modify_after_mirror = 1;
7730 action_flags |= actions->type ==
7731 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7732 MLX5_FLOW_ACTION_INC_TCP_ACK :
7733 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7734 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7736 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7738 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7739 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7740 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7742 case RTE_FLOW_ACTION_TYPE_METER:
7743 ret = mlx5_flow_validate_action_meter(dev,
7752 action_flags |= MLX5_FLOW_ACTION_METER;
7755 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7757 /* Meter action will add one more TAG action. */
7758 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7760 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7761 if (!attr->transfer && !attr->group)
7762 return rte_flow_error_set(error, ENOTSUP,
7763 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7765 "Shared ASO age action is not supported for group 0");
7766 if (action_flags & MLX5_FLOW_ACTION_AGE)
7767 return rte_flow_error_set
7769 RTE_FLOW_ERROR_TYPE_ACTION,
7771 "duplicate age actions set");
7772 action_flags |= MLX5_FLOW_ACTION_AGE;
7775 case RTE_FLOW_ACTION_TYPE_AGE:
7776 ret = flow_dv_validate_action_age(action_flags,
7782 * Validate the regular AGE action (using counter)
7783 * mutual exclusion with indirect counter actions.
7785 if (!flow_hit_aso_supported(priv->sh, attr)) {
7787 return rte_flow_error_set
7789 RTE_FLOW_ERROR_TYPE_ACTION,
7791 "old age and indirect count combination is not supported");
7793 return rte_flow_error_set
7795 RTE_FLOW_ERROR_TYPE_ACTION,
7797 "old age action and count must be in the same sub flow");
7799 action_flags |= MLX5_FLOW_ACTION_AGE;
7802 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7803 ret = flow_dv_validate_action_modify_ipv4_dscp
7810 /* Count all modify-header actions as one action. */
7811 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7813 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7814 modify_after_mirror = 1;
7815 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7816 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7818 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7819 ret = flow_dv_validate_action_modify_ipv6_dscp
7826 /* Count all modify-header actions as one action. */
7827 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7829 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7830 modify_after_mirror = 1;
7831 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7832 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7834 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7835 ret = flow_dv_validate_action_sample(&action_flags,
7844 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7847 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7848 ret = flow_dv_validate_action_modify_field(dev,
7855 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7856 modify_after_mirror = 1;
7857 /* Count all modify-header actions as one action. */
7858 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7860 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7863 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7864 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7869 action_flags |= MLX5_FLOW_ACTION_CT;
7871 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7872 /* tunnel offload action was processed before
7873 * list it here as a supported type
7877 return rte_flow_error_set(error, ENOTSUP,
7878 RTE_FLOW_ERROR_TYPE_ACTION,
7880 "action not supported");
7884 * Validate actions in flow rules
7885 * - Explicit decap action is prohibited by the tunnel offload API.
7886 * - Drop action in tunnel steer rule is prohibited by the API.
7887 * - Application cannot use MARK action because it's value can mask
7888 * tunnel default miss notification.
7889 * - JUMP in tunnel match rule has no support in current PMD
7891 * - TAG & META are reserved for future uses.
7893 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7894 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7895 MLX5_FLOW_ACTION_MARK |
7896 MLX5_FLOW_ACTION_SET_TAG |
7897 MLX5_FLOW_ACTION_SET_META |
7898 MLX5_FLOW_ACTION_DROP;
7900 if (action_flags & bad_actions_mask)
7901 return rte_flow_error_set
7903 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7904 "Invalid RTE action in tunnel "
7906 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7907 return rte_flow_error_set
7909 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7910 "tunnel set decap rule must terminate "
7913 return rte_flow_error_set
7915 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7916 "tunnel flows for ingress traffic only");
7918 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7919 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7920 MLX5_FLOW_ACTION_MARK |
7921 MLX5_FLOW_ACTION_SET_TAG |
7922 MLX5_FLOW_ACTION_SET_META;
7924 if (action_flags & bad_actions_mask)
7925 return rte_flow_error_set
7927 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7928 "Invalid RTE action in tunnel "
7932 * Validate the drop action mutual exclusion with other actions.
7933 * Drop action is mutually-exclusive with any other action, except for
7935 * Drop action compatibility with tunnel offload was already validated.
7937 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7938 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7939 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7940 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7941 return rte_flow_error_set(error, EINVAL,
7942 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7943 "Drop action is mutually-exclusive "
7944 "with any other action, except for "
7946 /* Eswitch has few restrictions on using items and actions */
7947 if (attr->transfer) {
7948 if (!mlx5_flow_ext_mreg_supported(dev) &&
7949 action_flags & MLX5_FLOW_ACTION_FLAG)
7950 return rte_flow_error_set(error, ENOTSUP,
7951 RTE_FLOW_ERROR_TYPE_ACTION,
7953 "unsupported action FLAG");
7954 if (!mlx5_flow_ext_mreg_supported(dev) &&
7955 action_flags & MLX5_FLOW_ACTION_MARK)
7956 return rte_flow_error_set(error, ENOTSUP,
7957 RTE_FLOW_ERROR_TYPE_ACTION,
7959 "unsupported action MARK");
7960 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7961 return rte_flow_error_set(error, ENOTSUP,
7962 RTE_FLOW_ERROR_TYPE_ACTION,
7964 "unsupported action QUEUE");
7965 if (action_flags & MLX5_FLOW_ACTION_RSS)
7966 return rte_flow_error_set(error, ENOTSUP,
7967 RTE_FLOW_ERROR_TYPE_ACTION,
7969 "unsupported action RSS");
7970 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7971 return rte_flow_error_set(error, EINVAL,
7972 RTE_FLOW_ERROR_TYPE_ACTION,
7974 "no fate action is found");
7976 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7977 return rte_flow_error_set(error, EINVAL,
7978 RTE_FLOW_ERROR_TYPE_ACTION,
7980 "no fate action is found");
7983 * Continue validation for Xcap and VLAN actions.
7984 * If hairpin is working in explicit TX rule mode, there is no actions
7985 * splitting and the validation of hairpin ingress flow should be the
7986 * same as other standard flows.
7988 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7989 MLX5_FLOW_VLAN_ACTIONS)) &&
7990 (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index) ||
7991 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7992 conf->tx_explicit != 0))) {
7993 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7994 MLX5_FLOW_XCAP_ACTIONS)
7995 return rte_flow_error_set(error, ENOTSUP,
7996 RTE_FLOW_ERROR_TYPE_ACTION,
7997 NULL, "encap and decap "
7998 "combination aren't supported");
7999 if (!attr->transfer && attr->ingress) {
8000 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8001 return rte_flow_error_set
8003 RTE_FLOW_ERROR_TYPE_ACTION,
8004 NULL, "encap is not supported"
8005 " for ingress traffic");
8006 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8007 return rte_flow_error_set
8009 RTE_FLOW_ERROR_TYPE_ACTION,
8010 NULL, "push VLAN action not "
8011 "supported for ingress");
8012 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
8013 MLX5_FLOW_VLAN_ACTIONS)
8014 return rte_flow_error_set
8016 RTE_FLOW_ERROR_TYPE_ACTION,
8017 NULL, "no support for "
8018 "multiple VLAN actions");
8021 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
8022 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
8023 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
8025 return rte_flow_error_set
8027 RTE_FLOW_ERROR_TYPE_ACTION,
8028 NULL, "fate action not supported for "
8029 "meter with policy");
8031 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
8032 return rte_flow_error_set
8034 RTE_FLOW_ERROR_TYPE_ACTION,
8035 NULL, "modify header action in egress "
8036 "cannot be done before meter action");
8037 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8038 return rte_flow_error_set
8040 RTE_FLOW_ERROR_TYPE_ACTION,
8041 NULL, "encap action in egress "
8042 "cannot be done before meter action");
8043 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8044 return rte_flow_error_set
8046 RTE_FLOW_ERROR_TYPE_ACTION,
8047 NULL, "push vlan action in egress "
8048 "cannot be done before meter action");
8052 * Hairpin flow will add one more TAG action in TX implicit mode.
8053 * In TX explicit mode, there will be no hairpin flow ID.
8056 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8057 /* extra metadata enabled: one more TAG action will be add. */
8058 if (dev_conf->dv_flow_en &&
8059 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8060 mlx5_flow_ext_mreg_supported(dev))
8061 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8063 flow_dv_modify_hdr_action_max(dev, is_root)) {
8064 return rte_flow_error_set(error, ENOTSUP,
8065 RTE_FLOW_ERROR_TYPE_ACTION,
8066 NULL, "too many header modify"
8067 " actions to support");
8069 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8070 if (fdb_mirror_limit && modify_after_mirror)
8071 return rte_flow_error_set(error, EINVAL,
8072 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8073 "sample before modify action is not supported");
8075 * Validation the NIC Egress flow on representor, except implicit
8076 * hairpin default egress flow with TX_QUEUE item, other flows not
8077 * work due to metadata regC0 mismatch.
8079 if ((!attr->transfer && attr->egress) && priv->representor &&
8080 !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))
8081 return rte_flow_error_set(error, EINVAL,
8082 RTE_FLOW_ERROR_TYPE_ITEM,
8084 "NIC egress rules on representors"
8085 " is not supported");
8090 * Internal preparation function. Allocates the DV flow size,
8091 * this size is constant.
8094 * Pointer to the rte_eth_dev structure.
8096 * Pointer to the flow attributes.
8098 * Pointer to the list of items.
8099 * @param[in] actions
8100 * Pointer to the list of actions.
8102 * Pointer to the error structure.
8105 * Pointer to mlx5_flow object on success,
8106 * otherwise NULL and rte_errno is set.
8108 static struct mlx5_flow *
8109 flow_dv_prepare(struct rte_eth_dev *dev,
8110 const struct rte_flow_attr *attr __rte_unused,
8111 const struct rte_flow_item items[] __rte_unused,
8112 const struct rte_flow_action actions[] __rte_unused,
8113 struct rte_flow_error *error)
8115 uint32_t handle_idx = 0;
8116 struct mlx5_flow *dev_flow;
8117 struct mlx5_flow_handle *dev_handle;
8118 struct mlx5_priv *priv = dev->data->dev_private;
8119 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8122 wks->skip_matcher_reg = 0;
8124 wks->final_policy = NULL;
8125 /* In case of corrupting the memory. */
8126 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8127 rte_flow_error_set(error, ENOSPC,
8128 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8129 "not free temporary device flow");
8132 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8135 rte_flow_error_set(error, ENOMEM,
8136 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8137 "not enough memory to create flow handle");
8140 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8141 dev_flow = &wks->flows[wks->flow_idx++];
8142 memset(dev_flow, 0, sizeof(*dev_flow));
8143 dev_flow->handle = dev_handle;
8144 dev_flow->handle_idx = handle_idx;
8145 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8146 dev_flow->ingress = attr->ingress;
8147 dev_flow->dv.transfer = attr->transfer;
8151 #ifdef RTE_LIBRTE_MLX5_DEBUG
8153 * Sanity check for match mask and value. Similar to check_valid_spec() in
8154 * kernel driver. If unmasked bit is present in value, it returns failure.
8157 * pointer to match mask buffer.
8158 * @param match_value
8159 * pointer to match value buffer.
8162 * 0 if valid, -EINVAL otherwise.
8165 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8167 uint8_t *m = match_mask;
8168 uint8_t *v = match_value;
8171 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8174 "match_value differs from match_criteria"
8175 " %p[%u] != %p[%u]",
8176 match_value, i, match_mask, i);
8185 * Add match of ip_version.
8189 * @param[in] headers_v
8190 * Values header pointer.
8191 * @param[in] headers_m
8192 * Masks header pointer.
8193 * @param[in] ip_version
8194 * The IP version to set.
8197 flow_dv_set_match_ip_version(uint32_t group,
8203 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8205 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8207 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8208 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8209 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8213 * Add Ethernet item to matcher and to the value.
8215 * @param[in, out] matcher
8217 * @param[in, out] key
8218 * Flow matcher value.
8220 * Flow pattern to translate.
8222 * Item is inner pattern.
8225 flow_dv_translate_item_eth(void *matcher, void *key,
8226 const struct rte_flow_item *item, int inner,
8229 const struct rte_flow_item_eth *eth_m = item->mask;
8230 const struct rte_flow_item_eth *eth_v = item->spec;
8231 const struct rte_flow_item_eth nic_mask = {
8232 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8233 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8234 .type = RTE_BE16(0xffff),
8247 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8249 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8251 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8253 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8255 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8256 ð_m->dst, sizeof(eth_m->dst));
8257 /* The value must be in the range of the mask. */
8258 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8259 for (i = 0; i < sizeof(eth_m->dst); ++i)
8260 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8261 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8262 ð_m->src, sizeof(eth_m->src));
8263 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8264 /* The value must be in the range of the mask. */
8265 for (i = 0; i < sizeof(eth_m->dst); ++i)
8266 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8268 * HW supports match on one Ethertype, the Ethertype following the last
8269 * VLAN tag of the packet (see PRM).
8270 * Set match on ethertype only if ETH header is not followed by VLAN.
8271 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8272 * ethertype, and use ip_version field instead.
8273 * eCPRI over Ether layer will use type value 0xAEFE.
8275 if (eth_m->type == 0xFFFF) {
8276 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8277 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8278 switch (eth_v->type) {
8279 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8280 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8282 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8283 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8284 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8286 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8287 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8289 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8290 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8296 if (eth_m->has_vlan) {
8297 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8298 if (eth_v->has_vlan) {
8300 * Here, when also has_more_vlan field in VLAN item is
8301 * not set, only single-tagged packets will be matched.
8303 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8307 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8308 rte_be_to_cpu_16(eth_m->type));
8309 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8310 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8314 * Add VLAN item to matcher and to the value.
8316 * @param[in, out] dev_flow
8318 * @param[in, out] matcher
8320 * @param[in, out] key
8321 * Flow matcher value.
8323 * Flow pattern to translate.
8325 * Item is inner pattern.
8328 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8329 void *matcher, void *key,
8330 const struct rte_flow_item *item,
8331 int inner, uint32_t group)
8333 const struct rte_flow_item_vlan *vlan_m = item->mask;
8334 const struct rte_flow_item_vlan *vlan_v = item->spec;
8341 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8343 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8345 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8347 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8349 * This is workaround, masks are not supported,
8350 * and pre-validated.
8353 dev_flow->handle->vf_vlan.tag =
8354 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8357 * When VLAN item exists in flow, mark packet as tagged,
8358 * even if TCI is not specified.
8360 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8361 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8362 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8367 vlan_m = &rte_flow_item_vlan_mask;
8368 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8369 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8370 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8371 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8372 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8373 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8374 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8375 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8377 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8378 * ethertype, and use ip_version field instead.
8380 if (vlan_m->inner_type == 0xFFFF) {
8381 switch (vlan_v->inner_type) {
8382 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8383 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8384 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8385 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8387 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8388 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8390 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8391 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8397 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8398 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8399 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8400 /* Only one vlan_tag bit can be set. */
8401 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8404 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8405 rte_be_to_cpu_16(vlan_m->inner_type));
8406 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8407 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8411 * Add IPV4 item to matcher and to the value.
8413 * @param[in, out] matcher
8415 * @param[in, out] key
8416 * Flow matcher value.
8418 * Flow pattern to translate.
8420 * Item is inner pattern.
8422 * The group to insert the rule.
8425 flow_dv_translate_item_ipv4(void *matcher, void *key,
8426 const struct rte_flow_item *item,
8427 int inner, uint32_t group)
8429 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8430 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8431 const struct rte_flow_item_ipv4 nic_mask = {
8433 .src_addr = RTE_BE32(0xffffffff),
8434 .dst_addr = RTE_BE32(0xffffffff),
8435 .type_of_service = 0xff,
8436 .next_proto_id = 0xff,
8437 .time_to_live = 0xff,
8444 uint8_t tos, ihl_m, ihl_v;
8447 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8449 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8451 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8453 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8455 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8460 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8461 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8462 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8463 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8464 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8465 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8466 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8467 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8468 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8469 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8470 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8471 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8472 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8473 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8474 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8475 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8476 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8477 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8478 ipv4_m->hdr.type_of_service);
8479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8480 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8481 ipv4_m->hdr.type_of_service >> 2);
8482 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8483 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8484 ipv4_m->hdr.next_proto_id);
8485 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8486 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8487 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8488 ipv4_m->hdr.time_to_live);
8489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8490 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8491 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8492 !!(ipv4_m->hdr.fragment_offset));
8493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8494 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8498 * Add IPV6 item to matcher and to the value.
8500 * @param[in, out] matcher
8502 * @param[in, out] key
8503 * Flow matcher value.
8505 * Flow pattern to translate.
8507 * Item is inner pattern.
8509 * The group to insert the rule.
8512 flow_dv_translate_item_ipv6(void *matcher, void *key,
8513 const struct rte_flow_item *item,
8514 int inner, uint32_t group)
8516 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8517 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8518 const struct rte_flow_item_ipv6 nic_mask = {
8521 "\xff\xff\xff\xff\xff\xff\xff\xff"
8522 "\xff\xff\xff\xff\xff\xff\xff\xff",
8524 "\xff\xff\xff\xff\xff\xff\xff\xff"
8525 "\xff\xff\xff\xff\xff\xff\xff\xff",
8526 .vtc_flow = RTE_BE32(0xffffffff),
8533 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8534 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8543 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8545 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8547 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8549 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8551 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8556 size = sizeof(ipv6_m->hdr.dst_addr);
8557 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8558 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8559 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8560 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8561 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8562 for (i = 0; i < size; ++i)
8563 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8564 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8565 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8566 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8567 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8568 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8569 for (i = 0; i < size; ++i)
8570 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8572 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8573 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8574 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8576 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8577 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8580 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8582 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8585 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8587 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8591 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8594 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8596 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8597 ipv6_m->hdr.hop_limits);
8598 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8599 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8600 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8601 !!(ipv6_m->has_frag_ext));
8602 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8603 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8607 * Add IPV6 fragment extension item to matcher and to the value.
8609 * @param[in, out] matcher
8611 * @param[in, out] key
8612 * Flow matcher value.
8614 * Flow pattern to translate.
8616 * Item is inner pattern.
8619 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8620 const struct rte_flow_item *item,
8623 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8624 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8625 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8627 .next_header = 0xff,
8628 .frag_data = RTE_BE16(0xffff),
8635 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8637 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8639 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8641 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8643 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8644 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8645 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8646 if (!ipv6_frag_ext_v)
8648 if (!ipv6_frag_ext_m)
8649 ipv6_frag_ext_m = &nic_mask;
8650 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8651 ipv6_frag_ext_m->hdr.next_header);
8652 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8653 ipv6_frag_ext_v->hdr.next_header &
8654 ipv6_frag_ext_m->hdr.next_header);
8658 * Add TCP item to matcher and to the value.
8660 * @param[in, out] matcher
8662 * @param[in, out] key
8663 * Flow matcher value.
8665 * Flow pattern to translate.
8667 * Item is inner pattern.
8670 flow_dv_translate_item_tcp(void *matcher, void *key,
8671 const struct rte_flow_item *item,
8674 const struct rte_flow_item_tcp *tcp_m = item->mask;
8675 const struct rte_flow_item_tcp *tcp_v = item->spec;
8680 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8682 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8684 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8686 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8688 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8689 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8693 tcp_m = &rte_flow_item_tcp_mask;
8694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8695 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8696 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8697 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8698 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8699 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8700 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8701 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8702 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8703 tcp_m->hdr.tcp_flags);
8704 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8705 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8709 * Add UDP item to matcher and to the value.
8711 * @param[in, out] matcher
8713 * @param[in, out] key
8714 * Flow matcher value.
8716 * Flow pattern to translate.
8718 * Item is inner pattern.
8721 flow_dv_translate_item_udp(void *matcher, void *key,
8722 const struct rte_flow_item *item,
8725 const struct rte_flow_item_udp *udp_m = item->mask;
8726 const struct rte_flow_item_udp *udp_v = item->spec;
8731 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8733 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8735 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8737 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8739 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8740 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8744 udp_m = &rte_flow_item_udp_mask;
8745 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8746 rte_be_to_cpu_16(udp_m->hdr.src_port));
8747 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8748 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8749 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8750 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8751 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8752 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8756 * Add GRE optional Key item to matcher and to the value.
8758 * @param[in, out] matcher
8760 * @param[in, out] key
8761 * Flow matcher value.
8763 * Flow pattern to translate.
8765 * Item is inner pattern.
8768 flow_dv_translate_item_gre_key(void *matcher, void *key,
8769 const struct rte_flow_item *item)
8771 const rte_be32_t *key_m = item->mask;
8772 const rte_be32_t *key_v = item->spec;
8773 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8774 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8775 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8777 /* GRE K bit must be on and should already be validated */
8778 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8779 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8783 key_m = &gre_key_default_mask;
8784 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8785 rte_be_to_cpu_32(*key_m) >> 8);
8786 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8787 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8788 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8789 rte_be_to_cpu_32(*key_m) & 0xFF);
8790 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8791 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8795 * Add GRE item to matcher and to the value.
8797 * @param[in, out] matcher
8799 * @param[in, out] key
8800 * Flow matcher value.
8802 * Flow pattern to translate.
8803 * @param[in] pattern_flags
8804 * Accumulated pattern flags.
8807 flow_dv_translate_item_gre(void *matcher, void *key,
8808 const struct rte_flow_item *item,
8809 uint64_t pattern_flags)
8811 static const struct rte_flow_item_gre empty_gre = {0,};
8812 const struct rte_flow_item_gre *gre_m = item->mask;
8813 const struct rte_flow_item_gre *gre_v = item->spec;
8814 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8815 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8816 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8817 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8824 uint16_t s_present:1;
8825 uint16_t k_present:1;
8826 uint16_t rsvd_bit1:1;
8827 uint16_t c_present:1;
8831 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8832 uint16_t protocol_m, protocol_v;
8834 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8835 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8841 gre_m = &rte_flow_item_gre_mask;
8843 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8844 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8845 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8846 gre_crks_rsvd0_ver_m.c_present);
8847 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8848 gre_crks_rsvd0_ver_v.c_present &
8849 gre_crks_rsvd0_ver_m.c_present);
8850 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8851 gre_crks_rsvd0_ver_m.k_present);
8852 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8853 gre_crks_rsvd0_ver_v.k_present &
8854 gre_crks_rsvd0_ver_m.k_present);
8855 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8856 gre_crks_rsvd0_ver_m.s_present);
8857 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8858 gre_crks_rsvd0_ver_v.s_present &
8859 gre_crks_rsvd0_ver_m.s_present);
8860 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8861 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8863 /* Force next protocol to prevent matchers duplication */
8864 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8866 protocol_m = 0xFFFF;
8868 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8869 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8870 protocol_m & protocol_v);
8874 * Add GRE optional items to matcher and to the value.
8876 * @param[in, out] matcher
8878 * @param[in, out] key
8879 * Flow matcher value.
8881 * Flow pattern to translate.
8882 * @param[in] gre_item
8883 * Pointer to gre_item.
8884 * @param[in] pattern_flags
8885 * Accumulated pattern flags.
8888 flow_dv_translate_item_gre_option(void *matcher, void *key,
8889 const struct rte_flow_item *item,
8890 const struct rte_flow_item *gre_item,
8891 uint64_t pattern_flags)
8893 const struct rte_flow_item_gre_opt *option_m = item->mask;
8894 const struct rte_flow_item_gre_opt *option_v = item->spec;
8895 const struct rte_flow_item_gre *gre_m = gre_item->mask;
8896 const struct rte_flow_item_gre *gre_v = gre_item->spec;
8897 static const struct rte_flow_item_gre empty_gre = {0};
8898 struct rte_flow_item gre_key_item;
8899 uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
8900 uint16_t protocol_m, protocol_v;
8905 * If only match key field, keep using misc for matching.
8906 * If need to match checksum or sequence, using misc5 and do
8907 * not need using misc.
8909 if (!(option_m->sequence.sequence ||
8910 option_m->checksum_rsvd.checksum)) {
8911 flow_dv_translate_item_gre(matcher, key, gre_item,
8913 gre_key_item.spec = &option_v->key.key;
8914 gre_key_item.mask = &option_m->key.key;
8915 flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
8923 gre_m = &rte_flow_item_gre_mask;
8925 protocol_v = gre_v->protocol;
8926 protocol_m = gre_m->protocol;
8928 /* Force next protocol to prevent matchers duplication */
8929 uint16_t ether_type =
8930 mlx5_translate_tunnel_etypes(pattern_flags);
8932 protocol_v = rte_be_to_cpu_16(ether_type);
8933 protocol_m = UINT16_MAX;
8936 c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
8937 c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
8938 if (option_m->sequence.sequence) {
8939 c_rsvd0_ver_v |= RTE_BE16(0x1000);
8940 c_rsvd0_ver_m |= RTE_BE16(0x1000);
8942 if (option_m->key.key) {
8943 c_rsvd0_ver_v |= RTE_BE16(0x2000);
8944 c_rsvd0_ver_m |= RTE_BE16(0x2000);
8946 if (option_m->checksum_rsvd.checksum) {
8947 c_rsvd0_ver_v |= RTE_BE16(0x8000);
8948 c_rsvd0_ver_m |= RTE_BE16(0x8000);
8951 * Hardware parses GRE optional field into the fixed location,
8952 * do not need to adjust the tunnel dword indices.
8954 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8955 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8956 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
8957 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
8958 (c_rsvd0_ver_m | protocol_m << 16)));
8959 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
8960 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
8961 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
8962 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
8963 option_m->checksum_rsvd.checksum));
8964 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
8965 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
8966 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
8967 rte_be_to_cpu_32(option_v->key.key & option_m->key.key));
8968 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
8969 rte_be_to_cpu_32(option_m->key.key));
8970 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
8971 rte_be_to_cpu_32(option_v->sequence.sequence &
8972 option_m->sequence.sequence));
8973 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
8974 rte_be_to_cpu_32(option_m->sequence.sequence));
8978 * Add NVGRE item to matcher and to the value.
8980 * @param[in, out] matcher
8982 * @param[in, out] key
8983 * Flow matcher value.
8985 * Flow pattern to translate.
8986 * @param[in] pattern_flags
8987 * Accumulated pattern flags.
8990 flow_dv_translate_item_nvgre(void *matcher, void *key,
8991 const struct rte_flow_item *item,
8992 unsigned long pattern_flags)
8994 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8995 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8996 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8997 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8998 const char *tni_flow_id_m;
8999 const char *tni_flow_id_v;
9005 /* For NVGRE, GRE header fields must be set with defined values. */
9006 const struct rte_flow_item_gre gre_spec = {
9007 .c_rsvd0_ver = RTE_BE16(0x2000),
9008 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
9010 const struct rte_flow_item_gre gre_mask = {
9011 .c_rsvd0_ver = RTE_BE16(0xB000),
9012 .protocol = RTE_BE16(UINT16_MAX),
9014 const struct rte_flow_item gre_item = {
9019 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
9023 nvgre_m = &rte_flow_item_nvgre_mask;
9024 tni_flow_id_m = (const char *)nvgre_m->tni;
9025 tni_flow_id_v = (const char *)nvgre_v->tni;
9026 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
9027 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
9028 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
9029 memcpy(gre_key_m, tni_flow_id_m, size);
9030 for (i = 0; i < size; ++i)
9031 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
9035 * Add VXLAN item to matcher and to the value.
9038 * Pointer to the Ethernet device structure.
9040 * Flow rule attributes.
9041 * @param[in, out] matcher
9043 * @param[in, out] key
9044 * Flow matcher value.
9046 * Flow pattern to translate.
9048 * Item is inner pattern.
9051 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
9052 const struct rte_flow_attr *attr,
9053 void *matcher, void *key,
9054 const struct rte_flow_item *item,
9057 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
9058 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
9063 uint32_t *tunnel_header_v;
9064 uint32_t *tunnel_header_m;
9066 struct mlx5_priv *priv = dev->data->dev_private;
9067 const struct rte_flow_item_vxlan nic_mask = {
9068 .vni = "\xff\xff\xff",
9073 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9075 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9077 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9079 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9081 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
9082 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
9083 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9084 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9085 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9087 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
9091 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
9092 (attr->group && !priv->sh->misc5_cap))
9093 vxlan_m = &rte_flow_item_vxlan_mask;
9095 vxlan_m = &nic_mask;
9097 if ((priv->sh->steering_format_version ==
9098 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
9099 dport != MLX5_UDP_PORT_VXLAN) ||
9100 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
9101 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
9108 misc_m = MLX5_ADDR_OF(fte_match_param,
9109 matcher, misc_parameters);
9110 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9111 size = sizeof(vxlan_m->vni);
9112 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
9113 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
9114 memcpy(vni_m, vxlan_m->vni, size);
9115 for (i = 0; i < size; ++i)
9116 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9119 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
9120 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
9121 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
9124 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
9127 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
9128 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
9129 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
9130 if (*tunnel_header_v)
9131 *tunnel_header_m = vxlan_m->vni[0] |
9132 vxlan_m->vni[1] << 8 |
9133 vxlan_m->vni[2] << 16;
9135 *tunnel_header_m = 0x0;
9136 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
9137 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
9138 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
9142 * Add VXLAN-GPE item to matcher and to the value.
9144 * @param[in, out] matcher
9146 * @param[in, out] key
9147 * Flow matcher value.
9149 * Flow pattern to translate.
9151 * Item is inner pattern.
9155 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9156 const struct rte_flow_item *item,
9157 const uint64_t pattern_flags)
9159 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9160 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9161 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9162 /* The item was validated to be on the outer side */
9163 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9164 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9166 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9168 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9170 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9172 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9173 int i, size = sizeof(vxlan_m->vni);
9174 uint8_t flags_m = 0xff;
9175 uint8_t flags_v = 0xc;
9176 uint8_t m_protocol, v_protocol;
9178 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9179 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9180 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9181 MLX5_UDP_PORT_VXLAN_GPE);
9184 vxlan_v = &dummy_vxlan_gpe_hdr;
9185 vxlan_m = &dummy_vxlan_gpe_hdr;
9188 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9190 memcpy(vni_m, vxlan_m->vni, size);
9191 for (i = 0; i < size; ++i)
9192 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9193 if (vxlan_m->flags) {
9194 flags_m = vxlan_m->flags;
9195 flags_v = vxlan_v->flags;
9197 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9198 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9199 m_protocol = vxlan_m->protocol;
9200 v_protocol = vxlan_v->protocol;
9202 /* Force next protocol to ensure next headers parsing. */
9203 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9204 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9205 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9206 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9207 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9208 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9212 MLX5_SET(fte_match_set_misc3, misc_m,
9213 outer_vxlan_gpe_next_protocol, m_protocol);
9214 MLX5_SET(fte_match_set_misc3, misc_v,
9215 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9219 * Add Geneve item to matcher and to the value.
9221 * @param[in, out] matcher
9223 * @param[in, out] key
9224 * Flow matcher value.
9226 * Flow pattern to translate.
9228 * Item is inner pattern.
9232 flow_dv_translate_item_geneve(void *matcher, void *key,
9233 const struct rte_flow_item *item,
9234 uint64_t pattern_flags)
9236 static const struct rte_flow_item_geneve empty_geneve = {0,};
9237 const struct rte_flow_item_geneve *geneve_m = item->mask;
9238 const struct rte_flow_item_geneve *geneve_v = item->spec;
9239 /* GENEVE flow item validation allows single tunnel item */
9240 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9241 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9242 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9243 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9246 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9247 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9248 size_t size = sizeof(geneve_m->vni), i;
9249 uint16_t protocol_m, protocol_v;
9251 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9252 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9253 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9254 MLX5_UDP_PORT_GENEVE);
9257 geneve_v = &empty_geneve;
9258 geneve_m = &empty_geneve;
9261 geneve_m = &rte_flow_item_geneve_mask;
9263 memcpy(vni_m, geneve_m->vni, size);
9264 for (i = 0; i < size; ++i)
9265 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9266 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9267 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9268 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9269 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9270 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9271 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9272 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9273 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9274 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9275 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9276 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9277 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9278 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9280 /* Force next protocol to prevent matchers duplication */
9281 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9283 protocol_m = 0xFFFF;
9285 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9286 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9287 protocol_m & protocol_v);
9291 * Create Geneve TLV option resource.
9293 * @param dev[in, out]
9294 * Pointer to rte_eth_dev structure.
9295 * @param[in, out] tag_be24
9296 * Tag value in big endian then R-shift 8.
9297 * @parm[in, out] dev_flow
9298 * Pointer to the dev_flow.
9300 * pointer to error structure.
9303 * 0 on success otherwise -errno and errno is set.
9307 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9308 const struct rte_flow_item *item,
9309 struct rte_flow_error *error)
9311 struct mlx5_priv *priv = dev->data->dev_private;
9312 struct mlx5_dev_ctx_shared *sh = priv->sh;
9313 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9314 sh->geneve_tlv_option_resource;
9315 struct mlx5_devx_obj *obj;
9316 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9321 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9322 if (geneve_opt_resource != NULL) {
9323 if (geneve_opt_resource->option_class ==
9324 geneve_opt_v->option_class &&
9325 geneve_opt_resource->option_type ==
9326 geneve_opt_v->option_type &&
9327 geneve_opt_resource->length ==
9328 geneve_opt_v->option_len) {
9329 /* We already have GENEVE TLV option obj allocated. */
9330 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9333 ret = rte_flow_error_set(error, ENOMEM,
9334 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9335 "Only one GENEVE TLV option supported");
9339 /* Create a GENEVE TLV object and resource. */
9340 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9341 geneve_opt_v->option_class,
9342 geneve_opt_v->option_type,
9343 geneve_opt_v->option_len);
9345 ret = rte_flow_error_set(error, ENODATA,
9346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9347 "Failed to create GENEVE TLV Devx object");
9350 sh->geneve_tlv_option_resource =
9351 mlx5_malloc(MLX5_MEM_ZERO,
9352 sizeof(*geneve_opt_resource),
9354 if (!sh->geneve_tlv_option_resource) {
9355 claim_zero(mlx5_devx_cmd_destroy(obj));
9356 ret = rte_flow_error_set(error, ENOMEM,
9357 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9358 "GENEVE TLV object memory allocation failed");
9361 geneve_opt_resource = sh->geneve_tlv_option_resource;
9362 geneve_opt_resource->obj = obj;
9363 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9364 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9365 geneve_opt_resource->length = geneve_opt_v->option_len;
9366 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9370 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9375 * Add Geneve TLV option item to matcher.
9377 * @param[in, out] dev
9378 * Pointer to rte_eth_dev structure.
9379 * @param[in, out] matcher
9381 * @param[in, out] key
9382 * Flow matcher value.
9384 * Flow pattern to translate.
9386 * Pointer to error structure.
9389 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9390 void *key, const struct rte_flow_item *item,
9391 struct rte_flow_error *error)
9393 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9394 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9395 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9396 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9397 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9399 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9400 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9406 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9407 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9410 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9414 * Set the option length in GENEVE header if not requested.
9415 * The GENEVE TLV option length is expressed by the option length field
9416 * in the GENEVE header.
9417 * If the option length was not requested but the GENEVE TLV option item
9418 * is present we set the option length field implicitly.
9420 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9421 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9422 MLX5_GENEVE_OPTLEN_MASK);
9423 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9424 geneve_opt_v->option_len + 1);
9426 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9427 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9429 if (geneve_opt_v->data) {
9430 memcpy(&opt_data_key, geneve_opt_v->data,
9431 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9432 sizeof(opt_data_key)));
9433 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9434 sizeof(opt_data_key));
9435 memcpy(&opt_data_mask, geneve_opt_m->data,
9436 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9437 sizeof(opt_data_mask)));
9438 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9439 sizeof(opt_data_mask));
9440 MLX5_SET(fte_match_set_misc3, misc3_m,
9441 geneve_tlv_option_0_data,
9442 rte_be_to_cpu_32(opt_data_mask));
9443 MLX5_SET(fte_match_set_misc3, misc3_v,
9444 geneve_tlv_option_0_data,
9445 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9451 * Add MPLS item to matcher and to the value.
9453 * @param[in, out] matcher
9455 * @param[in, out] key
9456 * Flow matcher value.
9458 * Flow pattern to translate.
9459 * @param[in] prev_layer
9460 * The protocol layer indicated in previous item.
9462 * Item is inner pattern.
9465 flow_dv_translate_item_mpls(void *matcher, void *key,
9466 const struct rte_flow_item *item,
9467 uint64_t prev_layer,
9470 const uint32_t *in_mpls_m = item->mask;
9471 const uint32_t *in_mpls_v = item->spec;
9472 uint32_t *out_mpls_m = 0;
9473 uint32_t *out_mpls_v = 0;
9474 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9475 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9476 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9478 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9479 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9480 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9482 switch (prev_layer) {
9483 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9484 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9485 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9487 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9488 MLX5_UDP_PORT_MPLS);
9491 case MLX5_FLOW_LAYER_GRE:
9493 case MLX5_FLOW_LAYER_GRE_KEY:
9494 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9495 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9497 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9498 RTE_ETHER_TYPE_MPLS);
9507 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9508 switch (prev_layer) {
9509 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9511 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9512 outer_first_mpls_over_udp);
9514 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9515 outer_first_mpls_over_udp);
9517 case MLX5_FLOW_LAYER_GRE:
9519 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9520 outer_first_mpls_over_gre);
9522 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9523 outer_first_mpls_over_gre);
9526 /* Inner MPLS not over GRE is not supported. */
9529 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9533 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9539 if (out_mpls_m && out_mpls_v) {
9540 *out_mpls_m = *in_mpls_m;
9541 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9546 * Add metadata register item to matcher
9548 * @param[in, out] matcher
9550 * @param[in, out] key
9551 * Flow matcher value.
9552 * @param[in] reg_type
9553 * Type of device metadata register
9560 flow_dv_match_meta_reg(void *matcher, void *key,
9561 enum modify_reg reg_type,
9562 uint32_t data, uint32_t mask)
9565 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9567 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9573 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9574 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9577 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9578 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9582 * The metadata register C0 field might be divided into
9583 * source vport index and META item value, we should set
9584 * this field according to specified mask, not as whole one.
9586 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9588 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9589 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9592 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9595 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9596 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9599 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9600 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9603 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9604 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9607 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9608 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9611 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9612 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9615 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9616 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9619 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9620 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9629 * Add MARK item to matcher
9632 * The device to configure through.
9633 * @param[in, out] matcher
9635 * @param[in, out] key
9636 * Flow matcher value.
9638 * Flow pattern to translate.
9641 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9642 void *matcher, void *key,
9643 const struct rte_flow_item *item)
9645 struct mlx5_priv *priv = dev->data->dev_private;
9646 const struct rte_flow_item_mark *mark;
9650 mark = item->mask ? (const void *)item->mask :
9651 &rte_flow_item_mark_mask;
9652 mask = mark->id & priv->sh->dv_mark_mask;
9653 mark = (const void *)item->spec;
9655 value = mark->id & priv->sh->dv_mark_mask & mask;
9657 enum modify_reg reg;
9659 /* Get the metadata register index for the mark. */
9660 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9661 MLX5_ASSERT(reg > 0);
9662 if (reg == REG_C_0) {
9663 struct mlx5_priv *priv = dev->data->dev_private;
9664 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9665 uint32_t shl_c0 = rte_bsf32(msk_c0);
9671 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9676 * Add META item to matcher
9679 * The devich to configure through.
9680 * @param[in, out] matcher
9682 * @param[in, out] key
9683 * Flow matcher value.
9685 * Attributes of flow that includes this item.
9687 * Flow pattern to translate.
9690 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9691 void *matcher, void *key,
9692 const struct rte_flow_attr *attr,
9693 const struct rte_flow_item *item)
9695 const struct rte_flow_item_meta *meta_m;
9696 const struct rte_flow_item_meta *meta_v;
9698 meta_m = (const void *)item->mask;
9700 meta_m = &rte_flow_item_meta_mask;
9701 meta_v = (const void *)item->spec;
9704 uint32_t value = meta_v->data;
9705 uint32_t mask = meta_m->data;
9707 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9710 MLX5_ASSERT(reg != REG_NON);
9711 if (reg == REG_C_0) {
9712 struct mlx5_priv *priv = dev->data->dev_private;
9713 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9714 uint32_t shl_c0 = rte_bsf32(msk_c0);
9720 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9725 * Add vport metadata Reg C0 item to matcher
9727 * @param[in, out] matcher
9729 * @param[in, out] key
9730 * Flow matcher value.
9732 * Flow pattern to translate.
9735 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9736 uint32_t value, uint32_t mask)
9738 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9742 * Add tag item to matcher
9745 * The devich to configure through.
9746 * @param[in, out] matcher
9748 * @param[in, out] key
9749 * Flow matcher value.
9751 * Flow pattern to translate.
9754 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9755 void *matcher, void *key,
9756 const struct rte_flow_item *item)
9758 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9759 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9760 uint32_t mask, value;
9763 value = tag_v->data;
9764 mask = tag_m ? tag_m->data : UINT32_MAX;
9765 if (tag_v->id == REG_C_0) {
9766 struct mlx5_priv *priv = dev->data->dev_private;
9767 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9768 uint32_t shl_c0 = rte_bsf32(msk_c0);
9774 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9778 * Add TAG item to matcher
9781 * The devich to configure through.
9782 * @param[in, out] matcher
9784 * @param[in, out] key
9785 * Flow matcher value.
9787 * Flow pattern to translate.
9790 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9791 void *matcher, void *key,
9792 const struct rte_flow_item *item)
9794 const struct rte_flow_item_tag *tag_v = item->spec;
9795 const struct rte_flow_item_tag *tag_m = item->mask;
9796 enum modify_reg reg;
9799 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9800 /* Get the metadata register index for the tag. */
9801 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9802 MLX5_ASSERT(reg > 0);
9803 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9807 * Add source vport match to the specified matcher.
9809 * @param[in, out] matcher
9811 * @param[in, out] key
9812 * Flow matcher value.
9814 * Source vport value to match
9819 flow_dv_translate_item_source_vport(void *matcher, void *key,
9820 int16_t port, uint16_t mask)
9822 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9823 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9825 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9826 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9830 * Translate port-id item to eswitch match on port-id.
9833 * The devich to configure through.
9834 * @param[in, out] matcher
9836 * @param[in, out] key
9837 * Flow matcher value.
9839 * Flow pattern to translate.
9844 * 0 on success, a negative errno value otherwise.
9847 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9848 void *key, const struct rte_flow_item *item,
9849 const struct rte_flow_attr *attr)
9851 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9852 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9853 struct mlx5_priv *priv;
9856 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9857 flow_dv_translate_item_source_vport(matcher, key,
9858 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9861 mask = pid_m ? pid_m->id : 0xffff;
9862 id = pid_v ? pid_v->id : dev->data->port_id;
9863 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9867 * Translate to vport field or to metadata, depending on mode.
9868 * Kernel can use either misc.source_port or half of C0 metadata
9871 if (priv->vport_meta_mask) {
9873 * Provide the hint for SW steering library
9874 * to insert the flow into ingress domain and
9875 * save the extra vport match.
9877 if (mask == 0xffff && priv->vport_id == 0xffff &&
9878 priv->pf_bond < 0 && attr->transfer)
9879 flow_dv_translate_item_source_vport
9880 (matcher, key, priv->vport_id, mask);
9882 * We should always set the vport metadata register,
9883 * otherwise the SW steering library can drop
9884 * the rule if wire vport metadata value is not zero,
9885 * it depends on kernel configuration.
9887 flow_dv_translate_item_meta_vport(matcher, key,
9888 priv->vport_meta_tag,
9889 priv->vport_meta_mask);
9891 flow_dv_translate_item_source_vport(matcher, key,
9892 priv->vport_id, mask);
9898 * Add ICMP6 item to matcher and to the value.
9900 * @param[in, out] matcher
9902 * @param[in, out] key
9903 * Flow matcher value.
9905 * Flow pattern to translate.
9907 * Item is inner pattern.
9910 flow_dv_translate_item_icmp6(void *matcher, void *key,
9911 const struct rte_flow_item *item,
9914 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9915 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9918 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9920 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9922 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9924 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9926 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9928 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9930 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9931 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9935 icmp6_m = &rte_flow_item_icmp6_mask;
9936 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9937 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9938 icmp6_v->type & icmp6_m->type);
9939 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9940 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9941 icmp6_v->code & icmp6_m->code);
9945 * Add ICMP item to matcher and to the value.
9947 * @param[in, out] matcher
9949 * @param[in, out] key
9950 * Flow matcher value.
9952 * Flow pattern to translate.
9954 * Item is inner pattern.
9957 flow_dv_translate_item_icmp(void *matcher, void *key,
9958 const struct rte_flow_item *item,
9961 const struct rte_flow_item_icmp *icmp_m = item->mask;
9962 const struct rte_flow_item_icmp *icmp_v = item->spec;
9963 uint32_t icmp_header_data_m = 0;
9964 uint32_t icmp_header_data_v = 0;
9967 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9969 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9971 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9973 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9975 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9977 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9979 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9980 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9984 icmp_m = &rte_flow_item_icmp_mask;
9985 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9986 icmp_m->hdr.icmp_type);
9987 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9988 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9989 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9990 icmp_m->hdr.icmp_code);
9991 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9992 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9993 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9994 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9995 if (icmp_header_data_m) {
9996 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9997 icmp_header_data_v |=
9998 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9999 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
10000 icmp_header_data_m);
10001 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
10002 icmp_header_data_v & icmp_header_data_m);
10007 * Add GTP item to matcher and to the value.
10009 * @param[in, out] matcher
10011 * @param[in, out] key
10012 * Flow matcher value.
10014 * Flow pattern to translate.
10016 * Item is inner pattern.
10019 flow_dv_translate_item_gtp(void *matcher, void *key,
10020 const struct rte_flow_item *item, int inner)
10022 const struct rte_flow_item_gtp *gtp_m = item->mask;
10023 const struct rte_flow_item_gtp *gtp_v = item->spec;
10026 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
10027 misc_parameters_3);
10028 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
10029 uint16_t dport = RTE_GTPU_UDP_PORT;
10032 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
10034 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
10036 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
10038 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10040 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
10041 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
10042 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
10047 gtp_m = &rte_flow_item_gtp_mask;
10048 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
10049 gtp_m->v_pt_rsv_flags);
10050 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
10051 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
10052 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
10053 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
10054 gtp_v->msg_type & gtp_m->msg_type);
10055 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
10056 rte_be_to_cpu_32(gtp_m->teid));
10057 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
10058 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
10062 * Add GTP PSC item to matcher.
10064 * @param[in, out] matcher
10066 * @param[in, out] key
10067 * Flow matcher value.
10069 * Flow pattern to translate.
10072 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
10073 const struct rte_flow_item *item)
10075 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
10076 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
10077 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
10078 misc_parameters_3);
10079 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
10085 uint8_t next_ext_header_type;
10090 /* Always set E-flag match on one, regardless of GTP item settings. */
10091 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
10092 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
10093 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
10094 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
10095 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
10096 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
10097 /*Set next extension header type. */
10100 dw_2.next_ext_header_type = 0xff;
10101 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
10102 rte_cpu_to_be_32(dw_2.w32));
10105 dw_2.next_ext_header_type = 0x85;
10106 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
10107 rte_cpu_to_be_32(dw_2.w32));
10113 uint8_t type_flags;
10119 /*Set extension header PDU type and Qos. */
10121 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
10123 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
10124 dw_0.qfi = gtp_psc_m->hdr.qfi;
10125 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
10126 rte_cpu_to_be_32(dw_0.w32));
10128 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
10129 gtp_psc_m->hdr.type);
10130 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
10131 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
10132 rte_cpu_to_be_32(dw_0.w32));
10138 * Add eCPRI item to matcher and to the value.
10141 * The devich to configure through.
10142 * @param[in, out] matcher
10144 * @param[in, out] key
10145 * Flow matcher value.
10147 * Flow pattern to translate.
10148 * @param[in] last_item
10152 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10153 void *key, const struct rte_flow_item *item,
10154 uint64_t last_item)
10156 struct mlx5_priv *priv = dev->data->dev_private;
10157 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10158 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10159 struct rte_ecpri_common_hdr common;
10160 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10161 misc_parameters_4);
10162 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10168 * In case of eCPRI over Ethernet, if EtherType is not specified,
10169 * match on eCPRI EtherType implicitly.
10171 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10172 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10174 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10175 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10176 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10177 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10178 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10179 *(uint16_t *)l2m = UINT16_MAX;
10180 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10186 ecpri_m = &rte_flow_item_ecpri_mask;
10188 * Maximal four DW samples are supported in a single matching now.
10189 * Two are used now for a eCPRI matching:
10190 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10191 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10194 if (!ecpri_m->hdr.common.u32)
10196 samples = priv->sh->ecpri_parser.ids;
10197 /* Need to take the whole DW as the mask to fill the entry. */
10198 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10199 prog_sample_field_value_0);
10200 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10201 prog_sample_field_value_0);
10202 /* Already big endian (network order) in the header. */
10203 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10204 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10205 /* Sample#0, used for matching type, offset 0. */
10206 MLX5_SET(fte_match_set_misc4, misc4_m,
10207 prog_sample_field_id_0, samples[0]);
10208 /* It makes no sense to set the sample ID in the mask field. */
10209 MLX5_SET(fte_match_set_misc4, misc4_v,
10210 prog_sample_field_id_0, samples[0]);
10212 * Checking if message body part needs to be matched.
10213 * Some wildcard rules only matching type field should be supported.
10215 if (ecpri_m->hdr.dummy[0]) {
10216 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10217 switch (common.type) {
10218 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10219 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10220 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10221 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10222 prog_sample_field_value_1);
10223 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10224 prog_sample_field_value_1);
10225 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10226 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10227 ecpri_m->hdr.dummy[0];
10228 /* Sample#1, to match message body, offset 4. */
10229 MLX5_SET(fte_match_set_misc4, misc4_m,
10230 prog_sample_field_id_1, samples[1]);
10231 MLX5_SET(fte_match_set_misc4, misc4_v,
10232 prog_sample_field_id_1, samples[1]);
10235 /* Others, do not match any sample ID. */
10242 * Add connection tracking status item to matcher
10245 * The devich to configure through.
10246 * @param[in, out] matcher
10248 * @param[in, out] key
10249 * Flow matcher value.
10251 * Flow pattern to translate.
10254 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10255 void *matcher, void *key,
10256 const struct rte_flow_item *item)
10258 uint32_t reg_value = 0;
10260 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10261 uint32_t reg_mask = 0;
10262 const struct rte_flow_item_conntrack *spec = item->spec;
10263 const struct rte_flow_item_conntrack *mask = item->mask;
10265 struct rte_flow_error error;
10268 mask = &rte_flow_item_conntrack_mask;
10269 if (!spec || !mask->flags)
10271 flags = spec->flags & mask->flags;
10272 /* The conflict should be checked in the validation. */
10273 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10274 reg_value |= MLX5_CT_SYNDROME_VALID;
10275 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10276 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10277 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10278 reg_value |= MLX5_CT_SYNDROME_INVALID;
10279 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10280 reg_value |= MLX5_CT_SYNDROME_TRAP;
10281 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10282 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10283 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10284 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10285 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10287 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10288 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10289 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10290 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10291 /* The REG_C_x value could be saved during startup. */
10292 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10293 if (reg_id == REG_NON)
10295 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10296 reg_value, reg_mask);
10300 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10301 const struct rte_flow_item *item,
10302 struct mlx5_flow *dev_flow, bool is_inner)
10304 const struct rte_flow_item_flex *spec =
10305 (const struct rte_flow_item_flex *)item->spec;
10306 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10308 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10311 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10312 /* Don't count both inner and outer flex items in one rule. */
10313 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10314 MLX5_ASSERT(false);
10315 dev_flow->handle->flex_item |= (uint8_t)RTE_BIT32(index);
10317 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10320 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10322 #define HEADER_IS_ZERO(match_criteria, headers) \
10323 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10324 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10327 * Calculate flow matcher enable bitmap.
10329 * @param match_criteria
10330 * Pointer to flow matcher criteria.
10333 * Bitmap of enabled fields.
10336 flow_dv_matcher_enable(uint32_t *match_criteria)
10338 uint8_t match_criteria_enable;
10340 match_criteria_enable =
10341 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10342 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10343 match_criteria_enable |=
10344 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10345 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10346 match_criteria_enable |=
10347 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10348 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10349 match_criteria_enable |=
10350 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10351 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10352 match_criteria_enable |=
10353 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10354 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10355 match_criteria_enable |=
10356 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10357 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10358 match_criteria_enable |=
10359 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10360 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10361 return match_criteria_enable;
10365 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10368 * Check flow matching criteria first, subtract misc5/4 length if flow
10369 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10370 * misc5/4 are not supported, and matcher creation failure is expected
10371 * w/o subtraction. If misc5 is provided, misc4 must be counted in since
10372 * misc5 is right after misc4.
10374 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10375 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10376 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10377 if (!(match_criteria & (1 <<
10378 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10379 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10384 static struct mlx5_list_entry *
10385 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10386 struct mlx5_list_entry *entry, void *cb_ctx)
10388 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10389 struct mlx5_flow_dv_matcher *ref = ctx->data;
10390 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10391 typeof(*tbl), tbl);
10392 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10397 rte_flow_error_set(ctx->error, ENOMEM,
10398 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10399 "cannot create matcher");
10402 memcpy(resource, entry, sizeof(*resource));
10403 resource->tbl = &tbl->tbl;
10404 return &resource->entry;
10408 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10409 struct mlx5_list_entry *entry)
10414 struct mlx5_list_entry *
10415 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10417 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10418 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10419 struct rte_eth_dev *dev = ctx->dev;
10420 struct mlx5_flow_tbl_data_entry *tbl_data;
10421 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10422 struct rte_flow_error *error = ctx->error;
10423 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10424 struct mlx5_flow_tbl_resource *tbl;
10429 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10431 rte_flow_error_set(error, ENOMEM,
10432 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10434 "cannot allocate flow table data entry");
10437 tbl_data->idx = idx;
10438 tbl_data->tunnel = tt_prm->tunnel;
10439 tbl_data->group_id = tt_prm->group_id;
10440 tbl_data->external = !!tt_prm->external;
10441 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10442 tbl_data->is_egress = !!key.is_egress;
10443 tbl_data->is_transfer = !!key.is_fdb;
10444 tbl_data->dummy = !!key.dummy;
10445 tbl_data->level = key.level;
10446 tbl_data->id = key.id;
10447 tbl = &tbl_data->tbl;
10449 return &tbl_data->entry;
10451 domain = sh->fdb_domain;
10452 else if (key.is_egress)
10453 domain = sh->tx_domain;
10455 domain = sh->rx_domain;
10456 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10458 rte_flow_error_set(error, ENOMEM,
10459 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10460 NULL, "cannot create flow table object");
10461 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10464 if (key.level != 0) {
10465 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10466 (tbl->obj, &tbl_data->jump.action);
10468 rte_flow_error_set(error, ENOMEM,
10469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10471 "cannot create flow jump action");
10472 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10473 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10477 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10478 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10479 key.level, key.id);
10480 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10481 flow_dv_matcher_create_cb,
10482 flow_dv_matcher_match_cb,
10483 flow_dv_matcher_remove_cb,
10484 flow_dv_matcher_clone_cb,
10485 flow_dv_matcher_clone_free_cb);
10486 if (!tbl_data->matchers) {
10487 rte_flow_error_set(error, ENOMEM,
10488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10490 "cannot create tbl matcher list");
10491 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10492 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10493 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10496 return &tbl_data->entry;
10500 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10503 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10504 struct mlx5_flow_tbl_data_entry *tbl_data =
10505 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10506 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10508 return tbl_data->level != key.level ||
10509 tbl_data->id != key.id ||
10510 tbl_data->dummy != key.dummy ||
10511 tbl_data->is_transfer != !!key.is_fdb ||
10512 tbl_data->is_egress != !!key.is_egress;
10515 struct mlx5_list_entry *
10516 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10519 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10520 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10521 struct mlx5_flow_tbl_data_entry *tbl_data;
10522 struct rte_flow_error *error = ctx->error;
10525 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10527 rte_flow_error_set(error, ENOMEM,
10528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10530 "cannot allocate flow table data entry");
10533 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10534 tbl_data->idx = idx;
10535 return &tbl_data->entry;
10539 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10541 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10542 struct mlx5_flow_tbl_data_entry *tbl_data =
10543 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10545 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10549 * Get a flow table.
10551 * @param[in, out] dev
10552 * Pointer to rte_eth_dev structure.
10553 * @param[in] table_level
10554 * Table level to use.
10555 * @param[in] egress
10556 * Direction of the table.
10557 * @param[in] transfer
10558 * E-Switch or NIC flow.
10560 * Dummy entry for dv API.
10561 * @param[in] table_id
10563 * @param[out] error
10564 * pointer to error structure.
10567 * Returns tables resource based on the index, NULL in case of failed.
10569 struct mlx5_flow_tbl_resource *
10570 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10571 uint32_t table_level, uint8_t egress,
10574 const struct mlx5_flow_tunnel *tunnel,
10575 uint32_t group_id, uint8_t dummy,
10577 struct rte_flow_error *error)
10579 struct mlx5_priv *priv = dev->data->dev_private;
10580 union mlx5_flow_tbl_key table_key = {
10582 .level = table_level,
10586 .is_fdb = !!transfer,
10587 .is_egress = !!egress,
10590 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10592 .group_id = group_id,
10593 .external = external,
10595 struct mlx5_flow_cb_ctx ctx = {
10598 .data = &table_key.v64,
10601 struct mlx5_list_entry *entry;
10602 struct mlx5_flow_tbl_data_entry *tbl_data;
10604 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10606 rte_flow_error_set(error, ENOMEM,
10607 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10608 "cannot get table");
10611 DRV_LOG(DEBUG, "table_level %u table_id %u "
10612 "tunnel %u group %u registered.",
10613 table_level, table_id,
10614 tunnel ? tunnel->tunnel_id : 0, group_id);
10615 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10616 return &tbl_data->tbl;
10620 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10622 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10623 struct mlx5_flow_tbl_data_entry *tbl_data =
10624 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10626 MLX5_ASSERT(entry && sh);
10627 if (tbl_data->jump.action)
10628 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10629 if (tbl_data->tbl.obj)
10630 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10631 if (tbl_data->tunnel_offload && tbl_data->external) {
10632 struct mlx5_list_entry *he;
10633 struct mlx5_hlist *tunnel_grp_hash;
10634 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10635 union tunnel_tbl_key tunnel_key = {
10636 .tunnel_id = tbl_data->tunnel ?
10637 tbl_data->tunnel->tunnel_id : 0,
10638 .group = tbl_data->group_id
10640 uint32_t table_level = tbl_data->level;
10641 struct mlx5_flow_cb_ctx ctx = {
10642 .data = (void *)&tunnel_key.val,
10645 tunnel_grp_hash = tbl_data->tunnel ?
10646 tbl_data->tunnel->groups :
10648 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10650 mlx5_hlist_unregister(tunnel_grp_hash, he);
10652 "table_level %u id %u tunnel %u group %u released.",
10656 tbl_data->tunnel->tunnel_id : 0,
10657 tbl_data->group_id);
10659 if (tbl_data->matchers)
10660 mlx5_list_destroy(tbl_data->matchers);
10661 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10665 * Release a flow table.
10668 * Pointer to device shared structure.
10670 * Table resource to be released.
10673 * Returns 0 if table was released, else return 1;
10676 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10677 struct mlx5_flow_tbl_resource *tbl)
10679 struct mlx5_flow_tbl_data_entry *tbl_data =
10680 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10684 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10688 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10689 struct mlx5_list_entry *entry, void *cb_ctx)
10691 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10692 struct mlx5_flow_dv_matcher *ref = ctx->data;
10693 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10696 return cur->crc != ref->crc ||
10697 cur->priority != ref->priority ||
10698 memcmp((const void *)cur->mask.buf,
10699 (const void *)ref->mask.buf, ref->mask.size);
10702 struct mlx5_list_entry *
10703 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10705 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10706 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10707 struct mlx5_flow_dv_matcher *ref = ctx->data;
10708 struct mlx5_flow_dv_matcher *resource;
10709 struct mlx5dv_flow_matcher_attr dv_attr = {
10710 .type = IBV_FLOW_ATTR_NORMAL,
10711 .match_mask = (void *)&ref->mask,
10713 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10714 typeof(*tbl), tbl);
10717 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10720 rte_flow_error_set(ctx->error, ENOMEM,
10721 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10722 "cannot create matcher");
10726 dv_attr.match_criteria_enable =
10727 flow_dv_matcher_enable(resource->mask.buf);
10728 __flow_dv_adjust_buf_size(&ref->mask.size,
10729 dv_attr.match_criteria_enable);
10730 dv_attr.priority = ref->priority;
10731 if (tbl->is_egress)
10732 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10733 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10735 &resource->matcher_object);
10737 mlx5_free(resource);
10738 rte_flow_error_set(ctx->error, ENOMEM,
10739 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10740 "cannot create matcher");
10743 return &resource->entry;
10747 * Register the flow matcher.
10749 * @param[in, out] dev
10750 * Pointer to rte_eth_dev structure.
10751 * @param[in, out] matcher
10752 * Pointer to flow matcher.
10753 * @param[in, out] key
10754 * Pointer to flow table key.
10755 * @parm[in, out] dev_flow
10756 * Pointer to the dev_flow.
10757 * @param[out] error
10758 * pointer to error structure.
10761 * 0 on success otherwise -errno and errno is set.
10764 flow_dv_matcher_register(struct rte_eth_dev *dev,
10765 struct mlx5_flow_dv_matcher *ref,
10766 union mlx5_flow_tbl_key *key,
10767 struct mlx5_flow *dev_flow,
10768 const struct mlx5_flow_tunnel *tunnel,
10770 struct rte_flow_error *error)
10772 struct mlx5_list_entry *entry;
10773 struct mlx5_flow_dv_matcher *resource;
10774 struct mlx5_flow_tbl_resource *tbl;
10775 struct mlx5_flow_tbl_data_entry *tbl_data;
10776 struct mlx5_flow_cb_ctx ctx = {
10781 * tunnel offload API requires this registration for cases when
10782 * tunnel match rule was inserted before tunnel set rule.
10784 tbl = flow_dv_tbl_resource_get(dev, key->level,
10785 key->is_egress, key->is_fdb,
10786 dev_flow->external, tunnel,
10787 group_id, 0, key->id, error);
10789 return -rte_errno; /* No need to refill the error info */
10790 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10792 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10794 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10795 return rte_flow_error_set(error, ENOMEM,
10796 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10797 "cannot allocate ref memory");
10799 resource = container_of(entry, typeof(*resource), entry);
10800 dev_flow->handle->dvh.matcher = resource;
10804 struct mlx5_list_entry *
10805 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10807 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10808 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10809 struct mlx5_flow_dv_tag_resource *entry;
10813 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10815 rte_flow_error_set(ctx->error, ENOMEM,
10816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10817 "cannot allocate resource memory");
10821 entry->tag_id = *(uint32_t *)(ctx->data);
10822 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10825 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10826 rte_flow_error_set(ctx->error, ENOMEM,
10827 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10828 NULL, "cannot create action");
10831 return &entry->entry;
10835 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10838 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10839 struct mlx5_flow_dv_tag_resource *tag =
10840 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10842 return *(uint32_t *)(ctx->data) != tag->tag_id;
10845 struct mlx5_list_entry *
10846 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10849 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10850 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10851 struct mlx5_flow_dv_tag_resource *entry;
10854 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10856 rte_flow_error_set(ctx->error, ENOMEM,
10857 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10858 "cannot allocate tag resource memory");
10861 memcpy(entry, oentry, sizeof(*entry));
10863 return &entry->entry;
10867 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10869 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10870 struct mlx5_flow_dv_tag_resource *tag =
10871 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10873 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10877 * Find existing tag resource or create and register a new one.
10879 * @param dev[in, out]
10880 * Pointer to rte_eth_dev structure.
10881 * @param[in, out] tag_be24
10882 * Tag value in big endian then R-shift 8.
10883 * @parm[in, out] dev_flow
10884 * Pointer to the dev_flow.
10885 * @param[out] error
10886 * pointer to error structure.
10889 * 0 on success otherwise -errno and errno is set.
10892 flow_dv_tag_resource_register
10893 (struct rte_eth_dev *dev,
10895 struct mlx5_flow *dev_flow,
10896 struct rte_flow_error *error)
10898 struct mlx5_priv *priv = dev->data->dev_private;
10899 struct mlx5_flow_dv_tag_resource *resource;
10900 struct mlx5_list_entry *entry;
10901 struct mlx5_flow_cb_ctx ctx = {
10905 struct mlx5_hlist *tag_table;
10907 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10909 MLX5_TAGS_HLIST_ARRAY_SIZE,
10910 false, false, priv->sh,
10911 flow_dv_tag_create_cb,
10912 flow_dv_tag_match_cb,
10913 flow_dv_tag_remove_cb,
10914 flow_dv_tag_clone_cb,
10915 flow_dv_tag_clone_free_cb,
10917 if (unlikely(!tag_table))
10919 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10921 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10923 dev_flow->handle->dvh.rix_tag = resource->idx;
10924 dev_flow->dv.tag_resource = resource;
10931 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10933 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10934 struct mlx5_flow_dv_tag_resource *tag =
10935 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10937 MLX5_ASSERT(tag && sh && tag->action);
10938 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10939 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10940 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10947 * Pointer to Ethernet device.
10952 * 1 while a reference on it exists, 0 when freed.
10955 flow_dv_tag_release(struct rte_eth_dev *dev,
10958 struct mlx5_priv *priv = dev->data->dev_private;
10959 struct mlx5_flow_dv_tag_resource *tag;
10961 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10964 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10965 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10966 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10970 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10973 * Pointer to rte_eth_dev structure.
10974 * @param[in] action
10975 * Pointer to action PORT_ID / REPRESENTED_PORT.
10976 * @param[out] dst_port_id
10977 * The target port ID.
10978 * @param[out] error
10979 * Pointer to the error structure.
10982 * 0 on success, a negative errno value otherwise and rte_errno is set.
10985 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10986 const struct rte_flow_action *action,
10987 uint32_t *dst_port_id,
10988 struct rte_flow_error *error)
10991 struct mlx5_priv *priv;
10993 switch (action->type) {
10994 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10995 const struct rte_flow_action_port_id *conf;
10997 conf = (const struct rte_flow_action_port_id *)action->conf;
10998 port = conf->original ? dev->data->port_id : conf->id;
11001 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
11002 const struct rte_flow_action_ethdev *ethdev;
11004 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
11005 port = ethdev->port_id;
11009 MLX5_ASSERT(false);
11010 return rte_flow_error_set(error, EINVAL,
11011 RTE_FLOW_ERROR_TYPE_ACTION, action,
11012 "unknown E-Switch action");
11015 priv = mlx5_port_to_eswitch_info(port, false);
11017 return rte_flow_error_set(error, -rte_errno,
11018 RTE_FLOW_ERROR_TYPE_ACTION,
11020 "No eswitch info was found for port");
11021 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
11023 * This parameter is transferred to
11024 * mlx5dv_dr_action_create_dest_ib_port().
11026 *dst_port_id = priv->dev_port;
11029 * Legacy mode, no LAG configurations is supported.
11030 * This parameter is transferred to
11031 * mlx5dv_dr_action_create_dest_vport().
11033 *dst_port_id = priv->vport_id;
11039 * Create a counter with aging configuration.
11042 * Pointer to rte_eth_dev structure.
11043 * @param[in] dev_flow
11044 * Pointer to the mlx5_flow.
11045 * @param[out] count
11046 * Pointer to the counter action configuration.
11048 * Pointer to the aging action configuration.
11051 * Index to flow counter on success, 0 otherwise.
11054 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
11055 struct mlx5_flow *dev_flow,
11056 const struct rte_flow_action_count *count
11058 const struct rte_flow_action_age *age)
11061 struct mlx5_age_param *age_param;
11063 counter = flow_dv_counter_alloc(dev, !!age);
11064 if (!counter || age == NULL)
11066 age_param = flow_dv_counter_idx_get_age(dev, counter);
11067 age_param->context = age->context ? age->context :
11068 (void *)(uintptr_t)(dev_flow->flow_idx);
11069 age_param->timeout = age->timeout;
11070 age_param->port_id = dev->data->port_id;
11071 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
11072 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
11077 * Add Tx queue matcher
11080 * Pointer to the dev struct.
11081 * @param[in, out] matcher
11083 * @param[in, out] key
11084 * Flow matcher value.
11086 * Flow pattern to translate.
11088 * Item is inner pattern.
11091 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
11092 void *matcher, void *key,
11093 const struct rte_flow_item *item)
11095 const struct mlx5_rte_flow_item_tx_queue *queue_m;
11096 const struct mlx5_rte_flow_item_tx_queue *queue_v;
11097 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
11098 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
11099 struct mlx5_txq_ctrl *txq;
11100 uint32_t queue, mask;
11102 queue_m = (const void *)item->mask;
11103 queue_v = (const void *)item->spec;
11106 txq = mlx5_txq_get(dev, queue_v->queue);
11109 if (txq->is_hairpin)
11110 queue = txq->obj->sq->id;
11112 queue = txq->obj->sq_obj.sq->id;
11113 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
11114 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
11115 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
11116 mlx5_txq_release(dev, queue_v->queue);
11120 * Set the hash fields according to the @p flow information.
11122 * @param[in] item_flags
11123 * The match pattern item flags.
11124 * @param[in] rss_desc
11125 * Pointer to the mlx5_flow_rss_desc.
11126 * @param[out] hash_fields
11127 * Pointer to the RSS hash fields.
11130 flow_dv_hashfields_set(uint64_t item_flags,
11131 struct mlx5_flow_rss_desc *rss_desc,
11132 uint64_t *hash_fields)
11134 uint64_t items = item_flags;
11135 uint64_t fields = 0;
11137 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
11140 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
11141 if (rss_desc->level >= 2)
11144 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
11145 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4)) ||
11147 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
11148 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11149 fields |= IBV_RX_HASH_SRC_IPV4;
11150 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11151 fields |= IBV_RX_HASH_DST_IPV4;
11153 fields |= MLX5_IPV4_IBV_RX_HASH;
11155 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
11156 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6)) ||
11158 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11159 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11160 fields |= IBV_RX_HASH_SRC_IPV6;
11161 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11162 fields |= IBV_RX_HASH_DST_IPV6;
11164 fields |= MLX5_IPV6_IBV_RX_HASH;
11169 * There is no match between the RSS types and the
11170 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11173 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11174 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP)) ||
11176 if (rss_types & RTE_ETH_RSS_UDP) {
11177 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11178 fields |= IBV_RX_HASH_SRC_PORT_UDP;
11179 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11180 fields |= IBV_RX_HASH_DST_PORT_UDP;
11182 fields |= MLX5_UDP_IBV_RX_HASH;
11184 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11185 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP)) ||
11187 if (rss_types & RTE_ETH_RSS_TCP) {
11188 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11189 fields |= IBV_RX_HASH_SRC_PORT_TCP;
11190 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11191 fields |= IBV_RX_HASH_DST_PORT_TCP;
11193 fields |= MLX5_TCP_IBV_RX_HASH;
11197 fields |= IBV_RX_HASH_INNER;
11198 *hash_fields = fields;
11202 * Prepare an Rx Hash queue.
11205 * Pointer to Ethernet device.
11206 * @param[in] dev_flow
11207 * Pointer to the mlx5_flow.
11208 * @param[in] rss_desc
11209 * Pointer to the mlx5_flow_rss_desc.
11210 * @param[out] hrxq_idx
11211 * Hash Rx queue index.
11214 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11216 static struct mlx5_hrxq *
11217 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11218 struct mlx5_flow *dev_flow,
11219 struct mlx5_flow_rss_desc *rss_desc,
11220 uint32_t *hrxq_idx)
11222 struct mlx5_flow_handle *dh = dev_flow->handle;
11223 uint32_t shared_rss = rss_desc->shared_rss;
11224 struct mlx5_hrxq *hrxq;
11226 MLX5_ASSERT(rss_desc->queue_num);
11227 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11228 rss_desc->hash_fields = dev_flow->hash_fields;
11229 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11230 rss_desc->shared_rss = 0;
11231 if (rss_desc->hash_fields == 0)
11232 rss_desc->queue_num = 1;
11233 hrxq = mlx5_hrxq_get(dev, rss_desc);
11234 *hrxq_idx = hrxq ? hrxq->idx : 0;
11235 rss_desc->shared_rss = shared_rss;
11240 * Release sample sub action resource.
11242 * @param[in, out] dev
11243 * Pointer to rte_eth_dev structure.
11244 * @param[in] act_res
11245 * Pointer to sample sub action resource.
11248 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11249 struct mlx5_flow_sub_actions_idx *act_res)
11251 if (act_res->rix_hrxq) {
11252 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11253 act_res->rix_hrxq = 0;
11255 if (act_res->rix_encap_decap) {
11256 flow_dv_encap_decap_resource_release(dev,
11257 act_res->rix_encap_decap);
11258 act_res->rix_encap_decap = 0;
11260 if (act_res->rix_port_id_action) {
11261 flow_dv_port_id_action_resource_release(dev,
11262 act_res->rix_port_id_action);
11263 act_res->rix_port_id_action = 0;
11265 if (act_res->rix_tag) {
11266 flow_dv_tag_release(dev, act_res->rix_tag);
11267 act_res->rix_tag = 0;
11269 if (act_res->rix_jump) {
11270 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11271 act_res->rix_jump = 0;
11276 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11277 struct mlx5_list_entry *entry, void *cb_ctx)
11279 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11280 struct rte_eth_dev *dev = ctx->dev;
11281 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11282 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11286 if (ctx_resource->ratio == resource->ratio &&
11287 ctx_resource->ft_type == resource->ft_type &&
11288 ctx_resource->ft_id == resource->ft_id &&
11289 ctx_resource->set_action == resource->set_action &&
11290 !memcmp((void *)&ctx_resource->sample_act,
11291 (void *)&resource->sample_act,
11292 sizeof(struct mlx5_flow_sub_actions_list))) {
11294 * Existing sample action should release the prepared
11295 * sub-actions reference counter.
11297 flow_dv_sample_sub_actions_release(dev,
11298 &ctx_resource->sample_idx);
11304 struct mlx5_list_entry *
11305 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11307 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11308 struct rte_eth_dev *dev = ctx->dev;
11309 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11310 void **sample_dv_actions = ctx_resource->sub_actions;
11311 struct mlx5_flow_dv_sample_resource *resource;
11312 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11313 struct mlx5_priv *priv = dev->data->dev_private;
11314 struct mlx5_dev_ctx_shared *sh = priv->sh;
11315 struct mlx5_flow_tbl_resource *tbl;
11317 const uint32_t next_ft_step = 1;
11318 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11319 uint8_t is_egress = 0;
11320 uint8_t is_transfer = 0;
11321 struct rte_flow_error *error = ctx->error;
11323 /* Register new sample resource. */
11324 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11326 rte_flow_error_set(error, ENOMEM,
11327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11329 "cannot allocate resource memory");
11332 *resource = *ctx_resource;
11333 /* Create normal path table level */
11334 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11336 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11338 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11339 is_egress, is_transfer,
11340 true, NULL, 0, 0, 0, error);
11342 rte_flow_error_set(error, ENOMEM,
11343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11345 "fail to create normal path table "
11349 resource->normal_path_tbl = tbl;
11350 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11351 if (!sh->default_miss_action) {
11352 rte_flow_error_set(error, ENOMEM,
11353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11355 "default miss action was not "
11359 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11360 sh->default_miss_action;
11362 /* Create a DR sample action */
11363 sampler_attr.sample_ratio = resource->ratio;
11364 sampler_attr.default_next_table = tbl->obj;
11365 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11366 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11367 &sample_dv_actions[0];
11368 sampler_attr.action = resource->set_action;
11369 if (mlx5_os_flow_dr_create_flow_action_sampler
11370 (&sampler_attr, &resource->verbs_action)) {
11371 rte_flow_error_set(error, ENOMEM,
11372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11373 NULL, "cannot create sample action");
11376 resource->idx = idx;
11377 resource->dev = dev;
11378 return &resource->entry;
11380 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11381 flow_dv_sample_sub_actions_release(dev,
11382 &resource->sample_idx);
11383 if (resource->normal_path_tbl)
11384 flow_dv_tbl_resource_release(MLX5_SH(dev),
11385 resource->normal_path_tbl);
11386 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11391 struct mlx5_list_entry *
11392 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11393 struct mlx5_list_entry *entry __rte_unused,
11396 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11397 struct rte_eth_dev *dev = ctx->dev;
11398 struct mlx5_flow_dv_sample_resource *resource;
11399 struct mlx5_priv *priv = dev->data->dev_private;
11400 struct mlx5_dev_ctx_shared *sh = priv->sh;
11403 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11405 rte_flow_error_set(ctx->error, ENOMEM,
11406 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11408 "cannot allocate resource memory");
11411 memcpy(resource, entry, sizeof(*resource));
11412 resource->idx = idx;
11413 resource->dev = dev;
11414 return &resource->entry;
11418 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11419 struct mlx5_list_entry *entry)
11421 struct mlx5_flow_dv_sample_resource *resource =
11422 container_of(entry, typeof(*resource), entry);
11423 struct rte_eth_dev *dev = resource->dev;
11424 struct mlx5_priv *priv = dev->data->dev_private;
11426 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11430 * Find existing sample resource or create and register a new one.
11432 * @param[in, out] dev
11433 * Pointer to rte_eth_dev structure.
11435 * Pointer to sample resource reference.
11436 * @parm[in, out] dev_flow
11437 * Pointer to the dev_flow.
11438 * @param[out] error
11439 * pointer to error structure.
11442 * 0 on success otherwise -errno and errno is set.
11445 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11446 struct mlx5_flow_dv_sample_resource *ref,
11447 struct mlx5_flow *dev_flow,
11448 struct rte_flow_error *error)
11450 struct mlx5_flow_dv_sample_resource *resource;
11451 struct mlx5_list_entry *entry;
11452 struct mlx5_priv *priv = dev->data->dev_private;
11453 struct mlx5_flow_cb_ctx ctx = {
11459 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11462 resource = container_of(entry, typeof(*resource), entry);
11463 dev_flow->handle->dvh.rix_sample = resource->idx;
11464 dev_flow->dv.sample_res = resource;
11469 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11470 struct mlx5_list_entry *entry, void *cb_ctx)
11472 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11473 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11474 struct rte_eth_dev *dev = ctx->dev;
11475 struct mlx5_flow_dv_dest_array_resource *resource =
11476 container_of(entry, typeof(*resource), entry);
11479 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11480 ctx_resource->ft_type == resource->ft_type &&
11481 !memcmp((void *)resource->sample_act,
11482 (void *)ctx_resource->sample_act,
11483 (ctx_resource->num_of_dest *
11484 sizeof(struct mlx5_flow_sub_actions_list)))) {
11486 * Existing sample action should release the prepared
11487 * sub-actions reference counter.
11489 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11490 flow_dv_sample_sub_actions_release(dev,
11491 &ctx_resource->sample_idx[idx]);
11497 struct mlx5_list_entry *
11498 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11500 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11501 struct rte_eth_dev *dev = ctx->dev;
11502 struct mlx5_flow_dv_dest_array_resource *resource;
11503 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11504 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11505 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11506 struct mlx5_priv *priv = dev->data->dev_private;
11507 struct mlx5_dev_ctx_shared *sh = priv->sh;
11508 struct mlx5_flow_sub_actions_list *sample_act;
11509 struct mlx5dv_dr_domain *domain;
11510 uint32_t idx = 0, res_idx = 0;
11511 struct rte_flow_error *error = ctx->error;
11512 uint64_t action_flags;
11515 /* Register new destination array resource. */
11516 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11519 rte_flow_error_set(error, ENOMEM,
11520 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11522 "cannot allocate resource memory");
11525 *resource = *ctx_resource;
11526 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11527 domain = sh->fdb_domain;
11528 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11529 domain = sh->rx_domain;
11531 domain = sh->tx_domain;
11532 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11533 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11534 mlx5_malloc(MLX5_MEM_ZERO,
11535 sizeof(struct mlx5dv_dr_action_dest_attr),
11537 if (!dest_attr[idx]) {
11538 rte_flow_error_set(error, ENOMEM,
11539 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11541 "cannot allocate resource memory");
11544 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11545 sample_act = &ctx_resource->sample_act[idx];
11546 action_flags = sample_act->action_flags;
11547 switch (action_flags) {
11548 case MLX5_FLOW_ACTION_QUEUE:
11549 dest_attr[idx]->dest = sample_act->dr_queue_action;
11551 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11552 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11553 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11554 dest_attr[idx]->dest_reformat->reformat =
11555 sample_act->dr_encap_action;
11556 dest_attr[idx]->dest_reformat->dest =
11557 sample_act->dr_port_id_action;
11559 case MLX5_FLOW_ACTION_PORT_ID:
11560 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11562 case MLX5_FLOW_ACTION_JUMP:
11563 dest_attr[idx]->dest = sample_act->dr_jump_action;
11566 rte_flow_error_set(error, EINVAL,
11567 RTE_FLOW_ERROR_TYPE_ACTION,
11569 "unsupported actions type");
11573 /* create a dest array action */
11574 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11576 resource->num_of_dest,
11578 &resource->action);
11580 rte_flow_error_set(error, ENOMEM,
11581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11583 "cannot create destination array action");
11586 resource->idx = res_idx;
11587 resource->dev = dev;
11588 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11589 mlx5_free(dest_attr[idx]);
11590 return &resource->entry;
11592 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11593 flow_dv_sample_sub_actions_release(dev,
11594 &resource->sample_idx[idx]);
11595 if (dest_attr[idx])
11596 mlx5_free(dest_attr[idx]);
11598 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11602 struct mlx5_list_entry *
11603 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11604 struct mlx5_list_entry *entry __rte_unused,
11607 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11608 struct rte_eth_dev *dev = ctx->dev;
11609 struct mlx5_flow_dv_dest_array_resource *resource;
11610 struct mlx5_priv *priv = dev->data->dev_private;
11611 struct mlx5_dev_ctx_shared *sh = priv->sh;
11612 uint32_t res_idx = 0;
11613 struct rte_flow_error *error = ctx->error;
11615 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11618 rte_flow_error_set(error, ENOMEM,
11619 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11621 "cannot allocate dest-array memory");
11624 memcpy(resource, entry, sizeof(*resource));
11625 resource->idx = res_idx;
11626 resource->dev = dev;
11627 return &resource->entry;
11631 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11632 struct mlx5_list_entry *entry)
11634 struct mlx5_flow_dv_dest_array_resource *resource =
11635 container_of(entry, typeof(*resource), entry);
11636 struct rte_eth_dev *dev = resource->dev;
11637 struct mlx5_priv *priv = dev->data->dev_private;
11639 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11643 * Find existing destination array resource or create and register a new one.
11645 * @param[in, out] dev
11646 * Pointer to rte_eth_dev structure.
11648 * Pointer to destination array resource reference.
11649 * @parm[in, out] dev_flow
11650 * Pointer to the dev_flow.
11651 * @param[out] error
11652 * pointer to error structure.
11655 * 0 on success otherwise -errno and errno is set.
11658 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11659 struct mlx5_flow_dv_dest_array_resource *ref,
11660 struct mlx5_flow *dev_flow,
11661 struct rte_flow_error *error)
11663 struct mlx5_flow_dv_dest_array_resource *resource;
11664 struct mlx5_priv *priv = dev->data->dev_private;
11665 struct mlx5_list_entry *entry;
11666 struct mlx5_flow_cb_ctx ctx = {
11672 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11675 resource = container_of(entry, typeof(*resource), entry);
11676 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11677 dev_flow->dv.dest_array_res = resource;
11682 * Convert Sample action to DV specification.
11685 * Pointer to rte_eth_dev structure.
11686 * @param[in] action
11687 * Pointer to sample action structure.
11688 * @param[in, out] dev_flow
11689 * Pointer to the mlx5_flow.
11691 * Pointer to the flow attributes.
11692 * @param[in, out] num_of_dest
11693 * Pointer to the num of destination.
11694 * @param[in, out] sample_actions
11695 * Pointer to sample actions list.
11696 * @param[in, out] res
11697 * Pointer to sample resource.
11698 * @param[out] error
11699 * Pointer to the error structure.
11702 * 0 on success, a negative errno value otherwise and rte_errno is set.
11705 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11706 const struct rte_flow_action_sample *action,
11707 struct mlx5_flow *dev_flow,
11708 const struct rte_flow_attr *attr,
11709 uint32_t *num_of_dest,
11710 void **sample_actions,
11711 struct mlx5_flow_dv_sample_resource *res,
11712 struct rte_flow_error *error)
11714 struct mlx5_priv *priv = dev->data->dev_private;
11715 const struct rte_flow_action *sub_actions;
11716 struct mlx5_flow_sub_actions_list *sample_act;
11717 struct mlx5_flow_sub_actions_idx *sample_idx;
11718 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11719 struct rte_flow *flow = dev_flow->flow;
11720 struct mlx5_flow_rss_desc *rss_desc;
11721 uint64_t action_flags = 0;
11724 rss_desc = &wks->rss_desc;
11725 sample_act = &res->sample_act;
11726 sample_idx = &res->sample_idx;
11727 res->ratio = action->ratio;
11728 sub_actions = action->actions;
11729 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11730 int type = sub_actions->type;
11731 uint32_t pre_rix = 0;
11734 case RTE_FLOW_ACTION_TYPE_QUEUE:
11736 const struct rte_flow_action_queue *queue;
11737 struct mlx5_hrxq *hrxq;
11740 queue = sub_actions->conf;
11741 rss_desc->queue_num = 1;
11742 rss_desc->queue[0] = queue->index;
11743 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11744 rss_desc, &hrxq_idx);
11746 return rte_flow_error_set
11748 RTE_FLOW_ERROR_TYPE_ACTION,
11750 "cannot create fate queue");
11751 sample_act->dr_queue_action = hrxq->action;
11752 sample_idx->rix_hrxq = hrxq_idx;
11753 sample_actions[sample_act->actions_num++] =
11756 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11757 if (action_flags & MLX5_FLOW_ACTION_MARK)
11758 dev_flow->handle->rix_hrxq = hrxq_idx;
11759 dev_flow->handle->fate_action =
11760 MLX5_FLOW_FATE_QUEUE;
11763 case RTE_FLOW_ACTION_TYPE_RSS:
11765 struct mlx5_hrxq *hrxq;
11767 const struct rte_flow_action_rss *rss;
11768 const uint8_t *rss_key;
11770 rss = sub_actions->conf;
11771 memcpy(rss_desc->queue, rss->queue,
11772 rss->queue_num * sizeof(uint16_t));
11773 rss_desc->queue_num = rss->queue_num;
11774 /* NULL RSS key indicates default RSS key. */
11775 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11776 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11778 * rss->level and rss.types should be set in advance
11779 * when expanding items for RSS.
11781 flow_dv_hashfields_set(dev_flow->handle->layers,
11783 &dev_flow->hash_fields);
11784 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11785 rss_desc, &hrxq_idx);
11787 return rte_flow_error_set
11789 RTE_FLOW_ERROR_TYPE_ACTION,
11791 "cannot create fate queue");
11792 sample_act->dr_queue_action = hrxq->action;
11793 sample_idx->rix_hrxq = hrxq_idx;
11794 sample_actions[sample_act->actions_num++] =
11797 action_flags |= MLX5_FLOW_ACTION_RSS;
11798 if (action_flags & MLX5_FLOW_ACTION_MARK)
11799 dev_flow->handle->rix_hrxq = hrxq_idx;
11800 dev_flow->handle->fate_action =
11801 MLX5_FLOW_FATE_QUEUE;
11804 case RTE_FLOW_ACTION_TYPE_MARK:
11806 uint32_t tag_be = mlx5_flow_mark_set
11807 (((const struct rte_flow_action_mark *)
11808 (sub_actions->conf))->id);
11811 pre_rix = dev_flow->handle->dvh.rix_tag;
11812 /* Save the mark resource before sample */
11813 pre_r = dev_flow->dv.tag_resource;
11814 if (flow_dv_tag_resource_register(dev, tag_be,
11817 MLX5_ASSERT(dev_flow->dv.tag_resource);
11818 sample_act->dr_tag_action =
11819 dev_flow->dv.tag_resource->action;
11820 sample_idx->rix_tag =
11821 dev_flow->handle->dvh.rix_tag;
11822 sample_actions[sample_act->actions_num++] =
11823 sample_act->dr_tag_action;
11824 /* Recover the mark resource after sample */
11825 dev_flow->dv.tag_resource = pre_r;
11826 dev_flow->handle->dvh.rix_tag = pre_rix;
11827 action_flags |= MLX5_FLOW_ACTION_MARK;
11830 case RTE_FLOW_ACTION_TYPE_COUNT:
11832 if (!flow->counter) {
11834 flow_dv_translate_create_counter(dev,
11835 dev_flow, sub_actions->conf,
11837 if (!flow->counter)
11838 return rte_flow_error_set
11840 RTE_FLOW_ERROR_TYPE_ACTION,
11842 "cannot create counter"
11845 sample_act->dr_cnt_action =
11846 (flow_dv_counter_get_by_idx(dev,
11847 flow->counter, NULL))->action;
11848 sample_actions[sample_act->actions_num++] =
11849 sample_act->dr_cnt_action;
11850 action_flags |= MLX5_FLOW_ACTION_COUNT;
11853 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11854 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11856 struct mlx5_flow_dv_port_id_action_resource
11858 uint32_t port_id = 0;
11860 memset(&port_id_resource, 0, sizeof(port_id_resource));
11861 /* Save the port id resource before sample */
11862 pre_rix = dev_flow->handle->rix_port_id_action;
11863 pre_r = dev_flow->dv.port_id_action;
11864 if (flow_dv_translate_action_port_id(dev, sub_actions,
11867 port_id_resource.port_id = port_id;
11868 if (flow_dv_port_id_action_resource_register
11869 (dev, &port_id_resource, dev_flow, error))
11871 sample_act->dr_port_id_action =
11872 dev_flow->dv.port_id_action->action;
11873 sample_idx->rix_port_id_action =
11874 dev_flow->handle->rix_port_id_action;
11875 sample_actions[sample_act->actions_num++] =
11876 sample_act->dr_port_id_action;
11877 /* Recover the port id resource after sample */
11878 dev_flow->dv.port_id_action = pre_r;
11879 dev_flow->handle->rix_port_id_action = pre_rix;
11881 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11884 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11885 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11886 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11887 /* Save the encap resource before sample */
11888 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11889 pre_r = dev_flow->dv.encap_decap;
11890 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11895 sample_act->dr_encap_action =
11896 dev_flow->dv.encap_decap->action;
11897 sample_idx->rix_encap_decap =
11898 dev_flow->handle->dvh.rix_encap_decap;
11899 sample_actions[sample_act->actions_num++] =
11900 sample_act->dr_encap_action;
11901 /* Recover the encap resource after sample */
11902 dev_flow->dv.encap_decap = pre_r;
11903 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11904 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11907 return rte_flow_error_set(error, EINVAL,
11908 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11910 "Not support for sampler action");
11913 sample_act->action_flags = action_flags;
11914 res->ft_id = dev_flow->dv.group;
11915 if (attr->transfer) {
11917 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11918 uint64_t set_action;
11919 } action_ctx = { .set_action = 0 };
11921 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11922 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11923 MLX5_MODIFICATION_TYPE_SET);
11924 MLX5_SET(set_action_in, action_ctx.action_in, field,
11925 MLX5_MODI_META_REG_C_0);
11926 MLX5_SET(set_action_in, action_ctx.action_in, data,
11927 priv->vport_meta_tag);
11928 res->set_action = action_ctx.set_action;
11929 } else if (attr->ingress) {
11930 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11932 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11938 * Convert Sample action to DV specification.
11941 * Pointer to rte_eth_dev structure.
11942 * @param[in, out] dev_flow
11943 * Pointer to the mlx5_flow.
11944 * @param[in] num_of_dest
11945 * The num of destination.
11946 * @param[in, out] res
11947 * Pointer to sample resource.
11948 * @param[in, out] mdest_res
11949 * Pointer to destination array resource.
11950 * @param[in] sample_actions
11951 * Pointer to sample path actions list.
11952 * @param[in] action_flags
11953 * Holds the actions detected until now.
11954 * @param[out] error
11955 * Pointer to the error structure.
11958 * 0 on success, a negative errno value otherwise and rte_errno is set.
11961 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11962 struct mlx5_flow *dev_flow,
11963 uint32_t num_of_dest,
11964 struct mlx5_flow_dv_sample_resource *res,
11965 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11966 void **sample_actions,
11967 uint64_t action_flags,
11968 struct rte_flow_error *error)
11970 /* update normal path action resource into last index of array */
11971 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11972 struct mlx5_flow_sub_actions_list *sample_act =
11973 &mdest_res->sample_act[dest_index];
11974 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11975 struct mlx5_flow_rss_desc *rss_desc;
11976 uint32_t normal_idx = 0;
11977 struct mlx5_hrxq *hrxq;
11981 rss_desc = &wks->rss_desc;
11982 if (num_of_dest > 1) {
11983 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11984 /* Handle QP action for mirroring */
11985 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11986 rss_desc, &hrxq_idx);
11988 return rte_flow_error_set
11990 RTE_FLOW_ERROR_TYPE_ACTION,
11992 "cannot create rx queue");
11994 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11995 sample_act->dr_queue_action = hrxq->action;
11996 if (action_flags & MLX5_FLOW_ACTION_MARK)
11997 dev_flow->handle->rix_hrxq = hrxq_idx;
11998 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12000 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
12002 mdest_res->sample_idx[dest_index].rix_encap_decap =
12003 dev_flow->handle->dvh.rix_encap_decap;
12004 sample_act->dr_encap_action =
12005 dev_flow->dv.encap_decap->action;
12006 dev_flow->handle->dvh.rix_encap_decap = 0;
12008 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
12010 mdest_res->sample_idx[dest_index].rix_port_id_action =
12011 dev_flow->handle->rix_port_id_action;
12012 sample_act->dr_port_id_action =
12013 dev_flow->dv.port_id_action->action;
12014 dev_flow->handle->rix_port_id_action = 0;
12016 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
12018 mdest_res->sample_idx[dest_index].rix_jump =
12019 dev_flow->handle->rix_jump;
12020 sample_act->dr_jump_action =
12021 dev_flow->dv.jump->action;
12022 dev_flow->handle->rix_jump = 0;
12024 sample_act->actions_num = normal_idx;
12025 /* update sample action resource into first index of array */
12026 mdest_res->ft_type = res->ft_type;
12027 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
12028 sizeof(struct mlx5_flow_sub_actions_idx));
12029 memcpy(&mdest_res->sample_act[0], &res->sample_act,
12030 sizeof(struct mlx5_flow_sub_actions_list));
12031 mdest_res->num_of_dest = num_of_dest;
12032 if (flow_dv_dest_array_resource_register(dev, mdest_res,
12034 return rte_flow_error_set(error, EINVAL,
12035 RTE_FLOW_ERROR_TYPE_ACTION,
12036 NULL, "can't create sample "
12039 res->sub_actions = sample_actions;
12040 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
12041 return rte_flow_error_set(error, EINVAL,
12042 RTE_FLOW_ERROR_TYPE_ACTION,
12044 "can't create sample action");
12050 * Remove an ASO age action from age actions list.
12053 * Pointer to the Ethernet device structure.
12055 * Pointer to the aso age action handler.
12058 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
12059 struct mlx5_aso_age_action *age)
12061 struct mlx5_age_info *age_info;
12062 struct mlx5_age_param *age_param = &age->age_params;
12063 struct mlx5_priv *priv = dev->data->dev_private;
12064 uint16_t expected = AGE_CANDIDATE;
12066 age_info = GET_PORT_AGE_INFO(priv);
12067 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
12068 AGE_FREE, false, __ATOMIC_RELAXED,
12069 __ATOMIC_RELAXED)) {
12071 * We need the lock even it is age timeout,
12072 * since age action may still in process.
12074 rte_spinlock_lock(&age_info->aged_sl);
12075 LIST_REMOVE(age, next);
12076 rte_spinlock_unlock(&age_info->aged_sl);
12077 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
12082 * Release an ASO age action.
12085 * Pointer to the Ethernet device structure.
12086 * @param[in] age_idx
12087 * Index of ASO age action to release.
12089 * True if the release operation is during flow destroy operation.
12090 * False if the release operation is during action destroy operation.
12093 * 0 when age action was removed, otherwise the number of references.
12096 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
12098 struct mlx5_priv *priv = dev->data->dev_private;
12099 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12100 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
12101 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
12104 flow_dv_aso_age_remove_from_age(dev, age);
12105 rte_spinlock_lock(&mng->free_sl);
12106 LIST_INSERT_HEAD(&mng->free, age, next);
12107 rte_spinlock_unlock(&mng->free_sl);
12113 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
12116 * Pointer to the Ethernet device structure.
12119 * 0 on success, otherwise negative errno value and rte_errno is set.
12122 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
12124 struct mlx5_priv *priv = dev->data->dev_private;
12125 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12126 void *old_pools = mng->pools;
12127 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
12128 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
12129 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12132 rte_errno = ENOMEM;
12136 memcpy(pools, old_pools,
12137 mng->n * sizeof(struct mlx5_flow_counter_pool *));
12138 mlx5_free(old_pools);
12140 /* First ASO flow hit allocation - starting ASO data-path. */
12141 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
12149 mng->pools = pools;
12154 * Create and initialize a new ASO aging pool.
12157 * Pointer to the Ethernet device structure.
12158 * @param[out] age_free
12159 * Where to put the pointer of a new age action.
12162 * The age actions pool pointer and @p age_free is set on success,
12163 * NULL otherwise and rte_errno is set.
12165 static struct mlx5_aso_age_pool *
12166 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12167 struct mlx5_aso_age_action **age_free)
12169 struct mlx5_priv *priv = dev->data->dev_private;
12170 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12171 struct mlx5_aso_age_pool *pool = NULL;
12172 struct mlx5_devx_obj *obj = NULL;
12175 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12176 priv->sh->cdev->pdn);
12178 rte_errno = ENODATA;
12179 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12182 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12184 claim_zero(mlx5_devx_cmd_destroy(obj));
12185 rte_errno = ENOMEM;
12188 pool->flow_hit_aso_obj = obj;
12189 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12190 rte_rwlock_write_lock(&mng->resize_rwl);
12191 pool->index = mng->next;
12192 /* Resize pools array if there is no room for the new pool in it. */
12193 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12194 claim_zero(mlx5_devx_cmd_destroy(obj));
12196 rte_rwlock_write_unlock(&mng->resize_rwl);
12199 mng->pools[pool->index] = pool;
12201 rte_rwlock_write_unlock(&mng->resize_rwl);
12202 /* Assign the first action in the new pool, the rest go to free list. */
12203 *age_free = &pool->actions[0];
12204 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12205 pool->actions[i].offset = i;
12206 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12212 * Allocate a ASO aging bit.
12215 * Pointer to the Ethernet device structure.
12216 * @param[out] error
12217 * Pointer to the error structure.
12220 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12223 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12225 struct mlx5_priv *priv = dev->data->dev_private;
12226 const struct mlx5_aso_age_pool *pool;
12227 struct mlx5_aso_age_action *age_free = NULL;
12228 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12231 /* Try to get the next free age action bit. */
12232 rte_spinlock_lock(&mng->free_sl);
12233 age_free = LIST_FIRST(&mng->free);
12235 LIST_REMOVE(age_free, next);
12236 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12237 rte_spinlock_unlock(&mng->free_sl);
12238 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12239 NULL, "failed to create ASO age pool");
12240 return 0; /* 0 is an error. */
12242 rte_spinlock_unlock(&mng->free_sl);
12243 pool = container_of
12244 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12245 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12247 if (!age_free->dr_action) {
12248 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12252 rte_flow_error_set(error, rte_errno,
12253 RTE_FLOW_ERROR_TYPE_ACTION,
12254 NULL, "failed to get reg_c "
12255 "for ASO flow hit");
12256 return 0; /* 0 is an error. */
12258 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12259 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12260 (priv->sh->rx_domain,
12261 pool->flow_hit_aso_obj->obj, age_free->offset,
12262 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12263 (reg_c - REG_C_0));
12264 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12265 if (!age_free->dr_action) {
12267 rte_spinlock_lock(&mng->free_sl);
12268 LIST_INSERT_HEAD(&mng->free, age_free, next);
12269 rte_spinlock_unlock(&mng->free_sl);
12270 rte_flow_error_set(error, rte_errno,
12271 RTE_FLOW_ERROR_TYPE_ACTION,
12272 NULL, "failed to create ASO "
12273 "flow hit action");
12274 return 0; /* 0 is an error. */
12277 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12278 return pool->index | ((age_free->offset + 1) << 16);
12282 * Initialize flow ASO age parameters.
12285 * Pointer to rte_eth_dev structure.
12286 * @param[in] age_idx
12287 * Index of ASO age action.
12288 * @param[in] context
12289 * Pointer to flow counter age context.
12290 * @param[in] timeout
12291 * Aging timeout in seconds.
12295 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12300 struct mlx5_aso_age_action *aso_age;
12302 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12303 MLX5_ASSERT(aso_age);
12304 aso_age->age_params.context = context;
12305 aso_age->age_params.timeout = timeout;
12306 aso_age->age_params.port_id = dev->data->port_id;
12307 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12309 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12314 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12315 const struct rte_flow_item_integrity *value,
12316 void *headers_m, void *headers_v)
12319 /* RTE l4_ok filter aggregates hardware l4_ok and
12320 * l4_checksum_ok filters.
12321 * Positive RTE l4_ok match requires hardware match on both L4
12322 * hardware integrity bits.
12323 * For negative match, check hardware l4_checksum_ok bit only,
12324 * because hardware sets that bit to 0 for all packets
12327 if (value->l4_ok) {
12328 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12329 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12331 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12332 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12335 if (mask->l4_csum_ok) {
12336 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12338 value->l4_csum_ok);
12343 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12344 const struct rte_flow_item_integrity *value,
12345 void *headers_m, void *headers_v, bool is_ipv4)
12348 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12349 * ipv4_csum_ok filters.
12350 * Positive RTE l3_ok match requires hardware match on both L3
12351 * hardware integrity bits.
12352 * For negative match, check hardware l3_csum_ok bit only,
12353 * because hardware sets that bit to 0 for all packets
12357 if (value->l3_ok) {
12358 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12360 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12363 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12364 ipv4_checksum_ok, 1);
12365 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12366 ipv4_checksum_ok, !!value->l3_ok);
12368 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12369 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12373 if (mask->ipv4_csum_ok) {
12374 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12375 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12376 value->ipv4_csum_ok);
12381 set_integrity_bits(void *headers_m, void *headers_v,
12382 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12384 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12385 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12387 /* Integrity bits validation cleared spec pointer */
12388 MLX5_ASSERT(spec != NULL);
12390 mask = &rte_flow_item_integrity_mask;
12391 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12393 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12397 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12399 struct rte_flow_item *integrity_items[2],
12400 uint64_t pattern_flags)
12402 void *headers_m, *headers_v;
12405 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12406 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12408 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12409 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12411 set_integrity_bits(headers_m, headers_v,
12412 integrity_items[1], is_l3_ip4);
12414 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12415 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12417 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12418 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12420 set_integrity_bits(headers_m, headers_v,
12421 integrity_items[0], is_l3_ip4);
12426 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12427 const struct rte_flow_item *integrity_items[2],
12428 uint64_t *last_item)
12430 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12432 /* integrity bits validation cleared spec pointer */
12433 MLX5_ASSERT(spec != NULL);
12434 if (spec->level > 1) {
12435 integrity_items[1] = item;
12436 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12438 integrity_items[0] = item;
12439 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12444 * Prepares DV flow counter with aging configuration.
12445 * Gets it by index when exists, creates a new one when doesn't.
12448 * Pointer to rte_eth_dev structure.
12449 * @param[in] dev_flow
12450 * Pointer to the mlx5_flow.
12451 * @param[in, out] flow
12452 * Pointer to the sub flow.
12454 * Pointer to the counter action configuration.
12456 * Pointer to the aging action configuration.
12457 * @param[out] error
12458 * Pointer to the error structure.
12461 * Pointer to the counter, NULL otherwise.
12463 static struct mlx5_flow_counter *
12464 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12465 struct mlx5_flow *dev_flow,
12466 struct rte_flow *flow,
12467 const struct rte_flow_action_count *count,
12468 const struct rte_flow_action_age *age,
12469 struct rte_flow_error *error)
12471 if (!flow->counter) {
12472 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12474 if (!flow->counter) {
12475 rte_flow_error_set(error, rte_errno,
12476 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12477 "cannot create counter object.");
12481 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12485 * Release an ASO CT action by its own device.
12488 * Pointer to the Ethernet device structure.
12490 * Index of ASO CT action to release.
12493 * 0 when CT action was removed, otherwise the number of references.
12496 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12498 struct mlx5_priv *priv = dev->data->dev_private;
12499 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12501 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12502 enum mlx5_aso_ct_state state =
12503 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12505 /* Cannot release when CT is in the ASO SQ. */
12506 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12508 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12510 if (ct->dr_action_orig) {
12511 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12512 claim_zero(mlx5_glue->destroy_flow_action
12513 (ct->dr_action_orig));
12515 ct->dr_action_orig = NULL;
12517 if (ct->dr_action_rply) {
12518 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12519 claim_zero(mlx5_glue->destroy_flow_action
12520 (ct->dr_action_rply));
12522 ct->dr_action_rply = NULL;
12524 /* Clear the state to free, no need in 1st allocation. */
12525 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12526 rte_spinlock_lock(&mng->ct_sl);
12527 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12528 rte_spinlock_unlock(&mng->ct_sl);
12534 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12535 struct rte_flow_error *error)
12537 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12538 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12539 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12542 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12543 if (dev->data->dev_started != 1)
12544 return rte_flow_error_set(error, EAGAIN,
12545 RTE_FLOW_ERROR_TYPE_ACTION,
12547 "Indirect CT action cannot be destroyed when the port is stopped");
12548 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12550 return rte_flow_error_set(error, EAGAIN,
12551 RTE_FLOW_ERROR_TYPE_ACTION,
12553 "Current state prevents indirect CT action from being destroyed");
12558 * Resize the ASO CT pools array by 64 pools.
12561 * Pointer to the Ethernet device structure.
12564 * 0 on success, otherwise negative errno value and rte_errno is set.
12567 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12569 struct mlx5_priv *priv = dev->data->dev_private;
12570 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12571 void *old_pools = mng->pools;
12572 /* Magic number now, need a macro. */
12573 uint32_t resize = mng->n + 64;
12574 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12575 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12578 rte_errno = ENOMEM;
12581 rte_rwlock_write_lock(&mng->resize_rwl);
12582 /* ASO SQ/QP was already initialized in the startup. */
12584 /* Realloc could be an alternative choice. */
12585 rte_memcpy(pools, old_pools,
12586 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12587 mlx5_free(old_pools);
12590 mng->pools = pools;
12591 rte_rwlock_write_unlock(&mng->resize_rwl);
12596 * Create and initialize a new ASO CT pool.
12599 * Pointer to the Ethernet device structure.
12600 * @param[out] ct_free
12601 * Where to put the pointer of a new CT action.
12604 * The CT actions pool pointer and @p ct_free is set on success,
12605 * NULL otherwise and rte_errno is set.
12607 static struct mlx5_aso_ct_pool *
12608 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12609 struct mlx5_aso_ct_action **ct_free)
12611 struct mlx5_priv *priv = dev->data->dev_private;
12612 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12613 struct mlx5_aso_ct_pool *pool = NULL;
12614 struct mlx5_devx_obj *obj = NULL;
12616 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12618 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12619 priv->sh->cdev->pdn,
12622 rte_errno = ENODATA;
12623 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12626 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12628 rte_errno = ENOMEM;
12629 claim_zero(mlx5_devx_cmd_destroy(obj));
12632 pool->devx_obj = obj;
12633 pool->index = mng->next;
12634 /* Resize pools array if there is no room for the new pool in it. */
12635 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12636 claim_zero(mlx5_devx_cmd_destroy(obj));
12640 mng->pools[pool->index] = pool;
12642 /* Assign the first action in the new pool, the rest go to free list. */
12643 *ct_free = &pool->actions[0];
12644 /* Lock outside, the list operation is safe here. */
12645 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12646 /* refcnt is 0 when allocating the memory. */
12647 pool->actions[i].offset = i;
12648 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12654 * Allocate a ASO CT action from free list.
12657 * Pointer to the Ethernet device structure.
12658 * @param[out] error
12659 * Pointer to the error structure.
12662 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12665 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12667 struct mlx5_priv *priv = dev->data->dev_private;
12668 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12669 struct mlx5_aso_ct_action *ct = NULL;
12670 struct mlx5_aso_ct_pool *pool;
12675 if (!priv->sh->cdev->config.devx) {
12676 rte_errno = ENOTSUP;
12679 /* Get a free CT action, if no, a new pool will be created. */
12680 rte_spinlock_lock(&mng->ct_sl);
12681 ct = LIST_FIRST(&mng->free_cts);
12683 LIST_REMOVE(ct, next);
12684 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12685 rte_spinlock_unlock(&mng->ct_sl);
12686 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12687 NULL, "failed to create ASO CT pool");
12690 rte_spinlock_unlock(&mng->ct_sl);
12691 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12692 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12693 /* 0: inactive, 1: created, 2+: used by flows. */
12694 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12695 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12696 if (!ct->dr_action_orig) {
12697 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12698 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12699 (priv->sh->rx_domain, pool->devx_obj->obj,
12701 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12704 RTE_SET_USED(reg_c);
12706 if (!ct->dr_action_orig) {
12707 flow_dv_aso_ct_dev_release(dev, ct_idx);
12708 rte_flow_error_set(error, rte_errno,
12709 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12710 "failed to create ASO CT action");
12714 if (!ct->dr_action_rply) {
12715 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12716 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12717 (priv->sh->rx_domain, pool->devx_obj->obj,
12719 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12722 if (!ct->dr_action_rply) {
12723 flow_dv_aso_ct_dev_release(dev, ct_idx);
12724 rte_flow_error_set(error, rte_errno,
12725 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12726 "failed to create ASO CT action");
12734 * Create a conntrack object with context and actions by using ASO mechanism.
12737 * Pointer to rte_eth_dev structure.
12739 * Pointer to conntrack information profile.
12740 * @param[out] error
12741 * Pointer to the error structure.
12744 * Index to conntrack object on success, 0 otherwise.
12747 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12748 const struct rte_flow_action_conntrack *pro,
12749 struct rte_flow_error *error)
12751 struct mlx5_priv *priv = dev->data->dev_private;
12752 struct mlx5_dev_ctx_shared *sh = priv->sh;
12753 struct mlx5_aso_ct_action *ct;
12756 if (!sh->ct_aso_en)
12757 return rte_flow_error_set(error, ENOTSUP,
12758 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12759 "Connection is not supported");
12760 idx = flow_dv_aso_ct_alloc(dev, error);
12762 return rte_flow_error_set(error, rte_errno,
12763 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12764 "Failed to allocate CT object");
12765 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12766 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12767 return rte_flow_error_set(error, EBUSY,
12768 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12769 "Failed to update CT");
12770 ct->is_original = !!pro->is_original_dir;
12771 ct->peer = pro->peer_port;
12776 * Fill the flow with DV spec, lock free
12777 * (mutex should be acquired by caller).
12780 * Pointer to rte_eth_dev structure.
12781 * @param[in, out] dev_flow
12782 * Pointer to the sub flow.
12784 * Pointer to the flow attributes.
12786 * Pointer to the list of items.
12787 * @param[in] actions
12788 * Pointer to the list of actions.
12789 * @param[out] error
12790 * Pointer to the error structure.
12793 * 0 on success, a negative errno value otherwise and rte_errno is set.
12796 flow_dv_translate(struct rte_eth_dev *dev,
12797 struct mlx5_flow *dev_flow,
12798 const struct rte_flow_attr *attr,
12799 const struct rte_flow_item items[],
12800 const struct rte_flow_action actions[],
12801 struct rte_flow_error *error)
12803 struct mlx5_priv *priv = dev->data->dev_private;
12804 struct mlx5_sh_config *dev_conf = &priv->sh->config;
12805 struct rte_flow *flow = dev_flow->flow;
12806 struct mlx5_flow_handle *handle = dev_flow->handle;
12807 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12808 struct mlx5_flow_rss_desc *rss_desc;
12809 uint64_t item_flags = 0;
12810 uint64_t last_item = 0;
12811 uint64_t action_flags = 0;
12812 struct mlx5_flow_dv_matcher matcher = {
12814 .size = sizeof(matcher.mask.buf),
12818 bool actions_end = false;
12820 struct mlx5_flow_dv_modify_hdr_resource res;
12821 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12822 sizeof(struct mlx5_modification_cmd) *
12823 (MLX5_MAX_MODIFY_NUM + 1)];
12825 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12826 const struct rte_flow_action_count *count = NULL;
12827 const struct rte_flow_action_age *non_shared_age = NULL;
12828 union flow_dv_attr flow_attr = { .attr = 0 };
12830 union mlx5_flow_tbl_key tbl_key;
12831 uint32_t modify_action_position = UINT32_MAX;
12832 void *match_mask = matcher.mask.buf;
12833 void *match_value = dev_flow->dv.value.buf;
12834 uint8_t next_protocol = 0xff;
12835 struct rte_vlan_hdr vlan = { 0 };
12836 struct mlx5_flow_dv_dest_array_resource mdest_res;
12837 struct mlx5_flow_dv_sample_resource sample_res;
12838 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12839 const struct rte_flow_action_sample *sample = NULL;
12840 struct mlx5_flow_sub_actions_list *sample_act;
12841 uint32_t sample_act_pos = UINT32_MAX;
12842 uint32_t age_act_pos = UINT32_MAX;
12843 uint32_t num_of_dest = 0;
12844 int tmp_actions_n = 0;
12847 const struct mlx5_flow_tunnel *tunnel = NULL;
12848 struct flow_grp_info grp_info = {
12849 .external = !!dev_flow->external,
12850 .transfer = !!attr->transfer,
12851 .fdb_def_rule = !!priv->fdb_def_rule,
12852 .skip_scale = dev_flow->skip_scale &
12853 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12854 .std_tbl_fix = true,
12856 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12857 const struct rte_flow_item *tunnel_item = NULL;
12858 const struct rte_flow_item *gre_item = NULL;
12861 return rte_flow_error_set(error, ENOMEM,
12862 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12864 "failed to push flow workspace");
12865 rss_desc = &wks->rss_desc;
12866 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12867 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12868 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12869 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12870 /* update normal path action resource into last index of array */
12871 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12872 if (is_tunnel_offload_active(dev)) {
12873 if (dev_flow->tunnel) {
12874 RTE_VERIFY(dev_flow->tof_type ==
12875 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12876 tunnel = dev_flow->tunnel;
12878 tunnel = mlx5_get_tof(items, actions,
12879 &dev_flow->tof_type);
12880 dev_flow->tunnel = tunnel;
12882 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12883 (dev, attr, tunnel, dev_flow->tof_type);
12885 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12886 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12887 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12891 dev_flow->dv.group = table;
12892 if (attr->transfer)
12893 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12894 /* number of actions must be set to 0 in case of dirty stack. */
12895 mhdr_res->actions_num = 0;
12896 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12898 * do not add decap action if match rule drops packet
12899 * HW rejects rules with decap & drop
12901 * if tunnel match rule was inserted before matching tunnel set
12902 * rule flow table used in the match rule must be registered.
12903 * current implementation handles that in the
12904 * flow_dv_match_register() at the function end.
12906 bool add_decap = true;
12907 const struct rte_flow_action *ptr = actions;
12909 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12910 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12916 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12920 dev_flow->dv.actions[actions_n++] =
12921 dev_flow->dv.encap_decap->action;
12922 action_flags |= MLX5_FLOW_ACTION_DECAP;
12925 for (; !actions_end ; actions++) {
12926 const struct rte_flow_action_queue *queue;
12927 const struct rte_flow_action_rss *rss;
12928 const struct rte_flow_action *action = actions;
12929 const uint8_t *rss_key;
12930 struct mlx5_flow_tbl_resource *tbl;
12931 struct mlx5_aso_age_action *age_act;
12932 struct mlx5_flow_counter *cnt_act;
12933 uint32_t port_id = 0;
12934 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12935 int action_type = actions->type;
12936 const struct rte_flow_action *found_action = NULL;
12937 uint32_t jump_group = 0;
12938 uint32_t owner_idx;
12939 struct mlx5_aso_ct_action *ct;
12941 if (!mlx5_flow_os_action_supported(action_type))
12942 return rte_flow_error_set(error, ENOTSUP,
12943 RTE_FLOW_ERROR_TYPE_ACTION,
12945 "action not supported");
12946 switch (action_type) {
12947 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12948 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12950 case RTE_FLOW_ACTION_TYPE_VOID:
12952 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12953 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12954 if (flow_dv_translate_action_port_id(dev, action,
12957 port_id_resource.port_id = port_id;
12958 MLX5_ASSERT(!handle->rix_port_id_action);
12959 if (flow_dv_port_id_action_resource_register
12960 (dev, &port_id_resource, dev_flow, error))
12962 dev_flow->dv.actions[actions_n++] =
12963 dev_flow->dv.port_id_action->action;
12964 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12965 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12966 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12969 case RTE_FLOW_ACTION_TYPE_FLAG:
12970 action_flags |= MLX5_FLOW_ACTION_FLAG;
12972 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12973 struct rte_flow_action_mark mark = {
12974 .id = MLX5_FLOW_MARK_DEFAULT,
12977 if (flow_dv_convert_action_mark(dev, &mark,
12981 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12984 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12986 * Only one FLAG or MARK is supported per device flow
12987 * right now. So the pointer to the tag resource must be
12988 * zero before the register process.
12990 MLX5_ASSERT(!handle->dvh.rix_tag);
12991 if (flow_dv_tag_resource_register(dev, tag_be,
12994 MLX5_ASSERT(dev_flow->dv.tag_resource);
12995 dev_flow->dv.actions[actions_n++] =
12996 dev_flow->dv.tag_resource->action;
12998 case RTE_FLOW_ACTION_TYPE_MARK:
12999 action_flags |= MLX5_FLOW_ACTION_MARK;
13001 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
13002 const struct rte_flow_action_mark *mark =
13003 (const struct rte_flow_action_mark *)
13006 if (flow_dv_convert_action_mark(dev, mark,
13010 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
13014 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
13015 /* Legacy (non-extensive) MARK action. */
13016 tag_be = mlx5_flow_mark_set
13017 (((const struct rte_flow_action_mark *)
13018 (actions->conf))->id);
13019 MLX5_ASSERT(!handle->dvh.rix_tag);
13020 if (flow_dv_tag_resource_register(dev, tag_be,
13023 MLX5_ASSERT(dev_flow->dv.tag_resource);
13024 dev_flow->dv.actions[actions_n++] =
13025 dev_flow->dv.tag_resource->action;
13027 case RTE_FLOW_ACTION_TYPE_SET_META:
13028 if (flow_dv_convert_action_set_meta
13029 (dev, mhdr_res, attr,
13030 (const struct rte_flow_action_set_meta *)
13031 actions->conf, error))
13033 action_flags |= MLX5_FLOW_ACTION_SET_META;
13035 case RTE_FLOW_ACTION_TYPE_SET_TAG:
13036 if (flow_dv_convert_action_set_tag
13038 (const struct rte_flow_action_set_tag *)
13039 actions->conf, error))
13041 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13043 case RTE_FLOW_ACTION_TYPE_DROP:
13044 action_flags |= MLX5_FLOW_ACTION_DROP;
13045 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
13047 case RTE_FLOW_ACTION_TYPE_QUEUE:
13048 queue = actions->conf;
13049 rss_desc->queue_num = 1;
13050 rss_desc->queue[0] = queue->index;
13051 action_flags |= MLX5_FLOW_ACTION_QUEUE;
13052 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
13053 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
13056 case RTE_FLOW_ACTION_TYPE_RSS:
13057 rss = actions->conf;
13058 memcpy(rss_desc->queue, rss->queue,
13059 rss->queue_num * sizeof(uint16_t));
13060 rss_desc->queue_num = rss->queue_num;
13061 /* NULL RSS key indicates default RSS key. */
13062 rss_key = !rss->key ? rss_hash_default_key : rss->key;
13063 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13065 * rss->level and rss.types should be set in advance
13066 * when expanding items for RSS.
13068 action_flags |= MLX5_FLOW_ACTION_RSS;
13069 dev_flow->handle->fate_action = rss_desc->shared_rss ?
13070 MLX5_FLOW_FATE_SHARED_RSS :
13071 MLX5_FLOW_FATE_QUEUE;
13073 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
13074 owner_idx = (uint32_t)(uintptr_t)action->conf;
13075 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
13076 if (flow->age == 0) {
13077 flow->age = owner_idx;
13078 __atomic_fetch_add(&age_act->refcnt, 1,
13081 age_act_pos = actions_n++;
13082 action_flags |= MLX5_FLOW_ACTION_AGE;
13084 case RTE_FLOW_ACTION_TYPE_AGE:
13085 non_shared_age = action->conf;
13086 age_act_pos = actions_n++;
13087 action_flags |= MLX5_FLOW_ACTION_AGE;
13089 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
13090 owner_idx = (uint32_t)(uintptr_t)action->conf;
13091 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
13093 MLX5_ASSERT(cnt_act != NULL);
13095 * When creating meter drop flow in drop table, the
13096 * counter should not overwrite the rte flow counter.
13098 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13099 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
13100 dev_flow->dv.actions[actions_n++] =
13103 if (flow->counter == 0) {
13104 flow->counter = owner_idx;
13106 (&cnt_act->shared_info.refcnt,
13107 1, __ATOMIC_RELAXED);
13109 /* Save information first, will apply later. */
13110 action_flags |= MLX5_FLOW_ACTION_COUNT;
13113 case RTE_FLOW_ACTION_TYPE_COUNT:
13114 if (!priv->sh->cdev->config.devx) {
13115 return rte_flow_error_set
13117 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13119 "count action not supported");
13121 /* Save information first, will apply later. */
13122 count = action->conf;
13123 action_flags |= MLX5_FLOW_ACTION_COUNT;
13125 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
13126 dev_flow->dv.actions[actions_n++] =
13127 priv->sh->pop_vlan_action;
13128 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
13130 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
13131 if (!(action_flags &
13132 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
13133 flow_dev_get_vlan_info_from_items(items, &vlan);
13134 vlan.eth_proto = rte_be_to_cpu_16
13135 ((((const struct rte_flow_action_of_push_vlan *)
13136 actions->conf)->ethertype));
13137 found_action = mlx5_flow_find_action
13139 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
13141 mlx5_update_vlan_vid_pcp(found_action, &vlan);
13142 found_action = mlx5_flow_find_action
13144 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
13146 mlx5_update_vlan_vid_pcp(found_action, &vlan);
13147 if (flow_dv_create_action_push_vlan
13148 (dev, attr, &vlan, dev_flow, error))
13150 dev_flow->dv.actions[actions_n++] =
13151 dev_flow->dv.push_vlan_res->action;
13152 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
13154 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
13155 /* of_vlan_push action handled this action */
13156 MLX5_ASSERT(action_flags &
13157 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13159 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13160 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13162 flow_dev_get_vlan_info_from_items(items, &vlan);
13163 mlx5_update_vlan_vid_pcp(actions, &vlan);
13164 /* If no VLAN push - this is a modify header action */
13165 if (flow_dv_convert_action_modify_vlan_vid
13166 (mhdr_res, actions, error))
13168 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13170 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13171 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13172 if (flow_dv_create_action_l2_encap(dev, actions,
13177 dev_flow->dv.actions[actions_n++] =
13178 dev_flow->dv.encap_decap->action;
13179 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13180 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13181 sample_act->action_flags |=
13182 MLX5_FLOW_ACTION_ENCAP;
13184 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13185 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13186 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13190 dev_flow->dv.actions[actions_n++] =
13191 dev_flow->dv.encap_decap->action;
13192 action_flags |= MLX5_FLOW_ACTION_DECAP;
13194 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13195 /* Handle encap with preceding decap. */
13196 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13197 if (flow_dv_create_action_raw_encap
13198 (dev, actions, dev_flow, attr, error))
13200 dev_flow->dv.actions[actions_n++] =
13201 dev_flow->dv.encap_decap->action;
13203 /* Handle encap without preceding decap. */
13204 if (flow_dv_create_action_l2_encap
13205 (dev, actions, dev_flow, attr->transfer,
13208 dev_flow->dv.actions[actions_n++] =
13209 dev_flow->dv.encap_decap->action;
13211 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13212 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13213 sample_act->action_flags |=
13214 MLX5_FLOW_ACTION_ENCAP;
13216 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13217 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13219 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13220 if (flow_dv_create_action_l2_decap
13221 (dev, dev_flow, attr->transfer, error))
13223 dev_flow->dv.actions[actions_n++] =
13224 dev_flow->dv.encap_decap->action;
13226 /* If decap is followed by encap, handle it at encap. */
13227 action_flags |= MLX5_FLOW_ACTION_DECAP;
13229 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13230 dev_flow->dv.actions[actions_n++] =
13231 (void *)(uintptr_t)action->conf;
13232 action_flags |= MLX5_FLOW_ACTION_JUMP;
13234 case RTE_FLOW_ACTION_TYPE_JUMP:
13235 jump_group = ((const struct rte_flow_action_jump *)
13236 action->conf)->group;
13237 grp_info.std_tbl_fix = 0;
13238 if (dev_flow->skip_scale &
13239 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13240 grp_info.skip_scale = 1;
13242 grp_info.skip_scale = 0;
13243 ret = mlx5_flow_group_to_table(dev, tunnel,
13249 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13251 !!dev_flow->external,
13252 tunnel, jump_group, 0,
13255 return rte_flow_error_set
13257 RTE_FLOW_ERROR_TYPE_ACTION,
13259 "cannot create jump action.");
13260 if (flow_dv_jump_tbl_resource_register
13261 (dev, tbl, dev_flow, error)) {
13262 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13263 return rte_flow_error_set
13265 RTE_FLOW_ERROR_TYPE_ACTION,
13267 "cannot create jump action.");
13269 dev_flow->dv.actions[actions_n++] =
13270 dev_flow->dv.jump->action;
13271 action_flags |= MLX5_FLOW_ACTION_JUMP;
13272 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13273 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13276 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13277 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13278 if (flow_dv_convert_action_modify_mac
13279 (mhdr_res, actions, error))
13281 action_flags |= actions->type ==
13282 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13283 MLX5_FLOW_ACTION_SET_MAC_SRC :
13284 MLX5_FLOW_ACTION_SET_MAC_DST;
13286 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13287 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13288 if (flow_dv_convert_action_modify_ipv4
13289 (mhdr_res, actions, error))
13291 action_flags |= actions->type ==
13292 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13293 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13294 MLX5_FLOW_ACTION_SET_IPV4_DST;
13296 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13297 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13298 if (flow_dv_convert_action_modify_ipv6
13299 (mhdr_res, actions, error))
13301 action_flags |= actions->type ==
13302 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13303 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13304 MLX5_FLOW_ACTION_SET_IPV6_DST;
13306 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13307 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13308 if (flow_dv_convert_action_modify_tp
13309 (mhdr_res, actions, items,
13310 &flow_attr, dev_flow, !!(action_flags &
13311 MLX5_FLOW_ACTION_DECAP), error))
13313 action_flags |= actions->type ==
13314 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13315 MLX5_FLOW_ACTION_SET_TP_SRC :
13316 MLX5_FLOW_ACTION_SET_TP_DST;
13318 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13319 if (flow_dv_convert_action_modify_dec_ttl
13320 (mhdr_res, items, &flow_attr, dev_flow,
13322 MLX5_FLOW_ACTION_DECAP), error))
13324 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13326 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13327 if (flow_dv_convert_action_modify_ttl
13328 (mhdr_res, actions, items, &flow_attr,
13329 dev_flow, !!(action_flags &
13330 MLX5_FLOW_ACTION_DECAP), error))
13332 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13334 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13335 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13336 if (flow_dv_convert_action_modify_tcp_seq
13337 (mhdr_res, actions, error))
13339 action_flags |= actions->type ==
13340 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13341 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13342 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13345 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13346 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13347 if (flow_dv_convert_action_modify_tcp_ack
13348 (mhdr_res, actions, error))
13350 action_flags |= actions->type ==
13351 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13352 MLX5_FLOW_ACTION_INC_TCP_ACK :
13353 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13355 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13356 if (flow_dv_convert_action_set_reg
13357 (mhdr_res, actions, error))
13359 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13361 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13362 if (flow_dv_convert_action_copy_mreg
13363 (dev, mhdr_res, actions, error))
13365 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13367 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13368 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13369 dev_flow->handle->fate_action =
13370 MLX5_FLOW_FATE_DEFAULT_MISS;
13372 case RTE_FLOW_ACTION_TYPE_METER:
13374 return rte_flow_error_set(error, rte_errno,
13375 RTE_FLOW_ERROR_TYPE_ACTION,
13376 NULL, "Failed to get meter in flow.");
13377 /* Set the meter action. */
13378 dev_flow->dv.actions[actions_n++] =
13379 wks->fm->meter_action;
13380 action_flags |= MLX5_FLOW_ACTION_METER;
13382 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13383 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13386 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13388 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13389 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13392 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13394 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13395 sample_act_pos = actions_n;
13396 sample = (const struct rte_flow_action_sample *)
13399 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13400 /* put encap action into group if work with port id */
13401 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13402 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13403 sample_act->action_flags |=
13404 MLX5_FLOW_ACTION_ENCAP;
13406 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13407 if (flow_dv_convert_action_modify_field
13408 (dev, mhdr_res, actions, attr, error))
13410 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13412 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13413 owner_idx = (uint32_t)(uintptr_t)action->conf;
13414 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13416 return rte_flow_error_set(error, EINVAL,
13417 RTE_FLOW_ERROR_TYPE_ACTION,
13419 "Failed to get CT object.");
13420 if (mlx5_aso_ct_available(priv->sh, ct))
13421 return rte_flow_error_set(error, rte_errno,
13422 RTE_FLOW_ERROR_TYPE_ACTION,
13424 "CT is unavailable.");
13425 if (ct->is_original)
13426 dev_flow->dv.actions[actions_n] =
13427 ct->dr_action_orig;
13429 dev_flow->dv.actions[actions_n] =
13430 ct->dr_action_rply;
13431 if (flow->ct == 0) {
13432 flow->indirect_type =
13433 MLX5_INDIRECT_ACTION_TYPE_CT;
13434 flow->ct = owner_idx;
13435 __atomic_fetch_add(&ct->refcnt, 1,
13439 action_flags |= MLX5_FLOW_ACTION_CT;
13441 case RTE_FLOW_ACTION_TYPE_END:
13442 actions_end = true;
13443 if (mhdr_res->actions_num) {
13444 /* create modify action if needed. */
13445 if (flow_dv_modify_hdr_resource_register
13446 (dev, mhdr_res, dev_flow, error))
13448 dev_flow->dv.actions[modify_action_position] =
13449 handle->dvh.modify_hdr->action;
13452 * Handle AGE and COUNT action by single HW counter
13453 * when they are not shared.
13455 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13456 if ((non_shared_age && count) ||
13457 !flow_hit_aso_supported(priv->sh, attr)) {
13458 /* Creates age by counters. */
13459 cnt_act = flow_dv_prepare_counter
13466 dev_flow->dv.actions[age_act_pos] =
13470 if (!flow->age && non_shared_age) {
13471 flow->age = flow_dv_aso_age_alloc
13475 flow_dv_aso_age_params_init
13477 non_shared_age->context ?
13478 non_shared_age->context :
13479 (void *)(uintptr_t)
13480 (dev_flow->flow_idx),
13481 non_shared_age->timeout);
13483 age_act = flow_aso_age_get_by_idx(dev,
13485 dev_flow->dv.actions[age_act_pos] =
13486 age_act->dr_action;
13488 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13490 * Create one count action, to be used
13491 * by all sub-flows.
13493 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13498 dev_flow->dv.actions[actions_n++] =
13504 if (mhdr_res->actions_num &&
13505 modify_action_position == UINT32_MAX)
13506 modify_action_position = actions_n++;
13508 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13509 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13510 int item_type = items->type;
13512 if (!mlx5_flow_os_item_supported(item_type))
13513 return rte_flow_error_set(error, ENOTSUP,
13514 RTE_FLOW_ERROR_TYPE_ITEM,
13515 NULL, "item not supported");
13516 switch (item_type) {
13517 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13518 flow_dv_translate_item_port_id
13519 (dev, match_mask, match_value, items, attr);
13520 last_item = MLX5_FLOW_ITEM_PORT_ID;
13522 case RTE_FLOW_ITEM_TYPE_ETH:
13523 flow_dv_translate_item_eth(match_mask, match_value,
13525 dev_flow->dv.group);
13526 matcher.priority = action_flags &
13527 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13528 !dev_flow->external ?
13529 MLX5_PRIORITY_MAP_L3 :
13530 MLX5_PRIORITY_MAP_L2;
13531 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13532 MLX5_FLOW_LAYER_OUTER_L2;
13534 case RTE_FLOW_ITEM_TYPE_VLAN:
13535 flow_dv_translate_item_vlan(dev_flow,
13536 match_mask, match_value,
13538 dev_flow->dv.group);
13539 matcher.priority = MLX5_PRIORITY_MAP_L2;
13540 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13541 MLX5_FLOW_LAYER_INNER_VLAN) :
13542 (MLX5_FLOW_LAYER_OUTER_L2 |
13543 MLX5_FLOW_LAYER_OUTER_VLAN);
13545 case RTE_FLOW_ITEM_TYPE_IPV4:
13546 mlx5_flow_tunnel_ip_check(items, next_protocol,
13547 &item_flags, &tunnel);
13548 flow_dv_translate_item_ipv4(match_mask, match_value,
13550 dev_flow->dv.group);
13551 matcher.priority = MLX5_PRIORITY_MAP_L3;
13552 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13553 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13554 if (items->mask != NULL &&
13555 ((const struct rte_flow_item_ipv4 *)
13556 items->mask)->hdr.next_proto_id) {
13558 ((const struct rte_flow_item_ipv4 *)
13559 (items->spec))->hdr.next_proto_id;
13561 ((const struct rte_flow_item_ipv4 *)
13562 (items->mask))->hdr.next_proto_id;
13564 /* Reset for inner layer. */
13565 next_protocol = 0xff;
13568 case RTE_FLOW_ITEM_TYPE_IPV6:
13569 mlx5_flow_tunnel_ip_check(items, next_protocol,
13570 &item_flags, &tunnel);
13571 flow_dv_translate_item_ipv6(match_mask, match_value,
13573 dev_flow->dv.group);
13574 matcher.priority = MLX5_PRIORITY_MAP_L3;
13575 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13576 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13577 if (items->mask != NULL &&
13578 ((const struct rte_flow_item_ipv6 *)
13579 items->mask)->hdr.proto) {
13581 ((const struct rte_flow_item_ipv6 *)
13582 items->spec)->hdr.proto;
13584 ((const struct rte_flow_item_ipv6 *)
13585 items->mask)->hdr.proto;
13587 /* Reset for inner layer. */
13588 next_protocol = 0xff;
13591 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13592 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13595 last_item = tunnel ?
13596 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13597 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13598 if (items->mask != NULL &&
13599 ((const struct rte_flow_item_ipv6_frag_ext *)
13600 items->mask)->hdr.next_header) {
13602 ((const struct rte_flow_item_ipv6_frag_ext *)
13603 items->spec)->hdr.next_header;
13605 ((const struct rte_flow_item_ipv6_frag_ext *)
13606 items->mask)->hdr.next_header;
13608 /* Reset for inner layer. */
13609 next_protocol = 0xff;
13612 case RTE_FLOW_ITEM_TYPE_TCP:
13613 flow_dv_translate_item_tcp(match_mask, match_value,
13615 matcher.priority = MLX5_PRIORITY_MAP_L4;
13616 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13617 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13619 case RTE_FLOW_ITEM_TYPE_UDP:
13620 flow_dv_translate_item_udp(match_mask, match_value,
13622 matcher.priority = MLX5_PRIORITY_MAP_L4;
13623 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13624 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13626 case RTE_FLOW_ITEM_TYPE_GRE:
13627 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13628 last_item = MLX5_FLOW_LAYER_GRE;
13629 tunnel_item = items;
13632 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13633 flow_dv_translate_item_gre_key(match_mask,
13634 match_value, items);
13635 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13637 case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
13638 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13639 last_item = MLX5_FLOW_LAYER_GRE;
13640 tunnel_item = items;
13642 case RTE_FLOW_ITEM_TYPE_NVGRE:
13643 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13644 last_item = MLX5_FLOW_LAYER_GRE;
13645 tunnel_item = items;
13647 case RTE_FLOW_ITEM_TYPE_VXLAN:
13648 flow_dv_translate_item_vxlan(dev, attr,
13649 match_mask, match_value,
13651 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13652 last_item = MLX5_FLOW_LAYER_VXLAN;
13654 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13655 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13656 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13657 tunnel_item = items;
13659 case RTE_FLOW_ITEM_TYPE_GENEVE:
13660 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13661 last_item = MLX5_FLOW_LAYER_GENEVE;
13662 tunnel_item = items;
13664 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13665 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13669 return rte_flow_error_set(error, -ret,
13670 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13671 "cannot create GENEVE TLV option");
13672 flow->geneve_tlv_option = 1;
13673 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13675 case RTE_FLOW_ITEM_TYPE_MPLS:
13676 flow_dv_translate_item_mpls(match_mask, match_value,
13677 items, last_item, tunnel);
13678 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13679 last_item = MLX5_FLOW_LAYER_MPLS;
13681 case RTE_FLOW_ITEM_TYPE_MARK:
13682 flow_dv_translate_item_mark(dev, match_mask,
13683 match_value, items);
13684 last_item = MLX5_FLOW_ITEM_MARK;
13686 case RTE_FLOW_ITEM_TYPE_META:
13687 flow_dv_translate_item_meta(dev, match_mask,
13688 match_value, attr, items);
13689 last_item = MLX5_FLOW_ITEM_METADATA;
13691 case RTE_FLOW_ITEM_TYPE_ICMP:
13692 flow_dv_translate_item_icmp(match_mask, match_value,
13694 matcher.priority = MLX5_PRIORITY_MAP_L4;
13695 last_item = MLX5_FLOW_LAYER_ICMP;
13697 case RTE_FLOW_ITEM_TYPE_ICMP6:
13698 flow_dv_translate_item_icmp6(match_mask, match_value,
13700 matcher.priority = MLX5_PRIORITY_MAP_L4;
13701 last_item = MLX5_FLOW_LAYER_ICMP6;
13703 case RTE_FLOW_ITEM_TYPE_TAG:
13704 flow_dv_translate_item_tag(dev, match_mask,
13705 match_value, items);
13706 last_item = MLX5_FLOW_ITEM_TAG;
13708 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13709 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13710 match_value, items);
13711 last_item = MLX5_FLOW_ITEM_TAG;
13713 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13714 flow_dv_translate_item_tx_queue(dev, match_mask,
13717 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13719 case RTE_FLOW_ITEM_TYPE_GTP:
13720 flow_dv_translate_item_gtp(match_mask, match_value,
13722 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13723 last_item = MLX5_FLOW_LAYER_GTP;
13725 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13726 ret = flow_dv_translate_item_gtp_psc(match_mask,
13730 return rte_flow_error_set(error, -ret,
13731 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13732 "cannot create GTP PSC item");
13733 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13735 case RTE_FLOW_ITEM_TYPE_ECPRI:
13736 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13737 /* Create it only the first time to be used. */
13738 ret = mlx5_flex_parser_ecpri_alloc(dev);
13740 return rte_flow_error_set
13742 RTE_FLOW_ERROR_TYPE_ITEM,
13744 "cannot create eCPRI parser");
13746 flow_dv_translate_item_ecpri(dev, match_mask,
13747 match_value, items,
13749 /* No other protocol should follow eCPRI layer. */
13750 last_item = MLX5_FLOW_LAYER_ECPRI;
13752 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13753 flow_dv_translate_item_integrity(items, integrity_items,
13756 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13757 flow_dv_translate_item_aso_ct(dev, match_mask,
13758 match_value, items);
13760 case RTE_FLOW_ITEM_TYPE_FLEX:
13761 flow_dv_translate_item_flex(dev, match_mask,
13762 match_value, items,
13763 dev_flow, tunnel != 0);
13764 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13765 MLX5_FLOW_ITEM_OUTER_FLEX;
13770 item_flags |= last_item;
13773 * When E-Switch mode is enabled, we have two cases where we need to
13774 * set the source port manually.
13775 * The first one, is in case of NIC ingress steering rule, and the
13776 * second is E-Switch rule where no port_id item was found.
13777 * In both cases the source port is set according the current port
13780 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode &&
13781 !(attr->egress && !attr->transfer)) {
13782 if (flow_dv_translate_item_port_id(dev, match_mask,
13783 match_value, NULL, attr))
13786 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13787 flow_dv_translate_item_integrity_post(match_mask, match_value,
13791 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13792 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13793 tunnel_item, item_flags);
13794 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13795 flow_dv_translate_item_geneve(match_mask, match_value,
13796 tunnel_item, item_flags);
13797 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13798 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13799 flow_dv_translate_item_gre(match_mask, match_value,
13800 tunnel_item, item_flags);
13801 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13802 flow_dv_translate_item_nvgre(match_mask, match_value,
13803 tunnel_item, item_flags);
13804 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
13805 flow_dv_translate_item_gre_option(match_mask, match_value,
13806 tunnel_item, gre_item, item_flags);
13808 MLX5_ASSERT(false);
13810 #ifdef RTE_LIBRTE_MLX5_DEBUG
13811 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13812 dev_flow->dv.value.buf));
13815 * Layers may be already initialized from prefix flow if this dev_flow
13816 * is the suffix flow.
13818 handle->layers |= item_flags;
13819 if (action_flags & MLX5_FLOW_ACTION_RSS)
13820 flow_dv_hashfields_set(dev_flow->handle->layers,
13822 &dev_flow->hash_fields);
13823 /* If has RSS action in the sample action, the Sample/Mirror resource
13824 * should be registered after the hash filed be update.
13826 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13827 ret = flow_dv_translate_action_sample(dev,
13836 ret = flow_dv_create_action_sample(dev,
13845 return rte_flow_error_set
13847 RTE_FLOW_ERROR_TYPE_ACTION,
13849 "cannot create sample action");
13850 if (num_of_dest > 1) {
13851 dev_flow->dv.actions[sample_act_pos] =
13852 dev_flow->dv.dest_array_res->action;
13854 dev_flow->dv.actions[sample_act_pos] =
13855 dev_flow->dv.sample_res->verbs_action;
13859 * For multiple destination (sample action with ratio=1), the encap
13860 * action and port id action will be combined into group action.
13861 * So need remove the original these actions in the flow and only
13862 * use the sample action instead of.
13864 if (num_of_dest > 1 &&
13865 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13867 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13869 for (i = 0; i < actions_n; i++) {
13870 if ((sample_act->dr_encap_action &&
13871 sample_act->dr_encap_action ==
13872 dev_flow->dv.actions[i]) ||
13873 (sample_act->dr_port_id_action &&
13874 sample_act->dr_port_id_action ==
13875 dev_flow->dv.actions[i]) ||
13876 (sample_act->dr_jump_action &&
13877 sample_act->dr_jump_action ==
13878 dev_flow->dv.actions[i]))
13880 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13882 memcpy((void *)dev_flow->dv.actions,
13883 (void *)temp_actions,
13884 tmp_actions_n * sizeof(void *));
13885 actions_n = tmp_actions_n;
13887 dev_flow->dv.actions_n = actions_n;
13888 dev_flow->act_flags = action_flags;
13889 if (wks->skip_matcher_reg)
13891 /* Register matcher. */
13892 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13893 matcher.mask.size);
13894 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13896 dev_flow->external);
13898 * When creating meter drop flow in drop table, using original
13899 * 5-tuple match, the matcher priority should be lower than
13902 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13903 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13904 matcher.priority <= MLX5_REG_BITS)
13905 matcher.priority += MLX5_REG_BITS;
13906 /* reserved field no needs to be set to 0 here. */
13907 tbl_key.is_fdb = attr->transfer;
13908 tbl_key.is_egress = attr->egress;
13909 tbl_key.level = dev_flow->dv.group;
13910 tbl_key.id = dev_flow->dv.table_id;
13911 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13912 tunnel, attr->group, error))
13918 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13921 * @param[in, out] action
13922 * Shred RSS action holding hash RX queue objects.
13923 * @param[in] hash_fields
13924 * Defines combination of packet fields to participate in RX hash.
13925 * @param[in] tunnel
13927 * @param[in] hrxq_idx
13928 * Hash RX queue index to set.
13931 * 0 on success, otherwise negative errno value.
13934 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13935 const uint64_t hash_fields,
13938 uint32_t *hrxqs = action->hrxq;
13940 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13941 case MLX5_RSS_HASH_IPV4:
13942 /* fall-through. */
13943 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13944 /* fall-through. */
13945 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13946 hrxqs[0] = hrxq_idx;
13948 case MLX5_RSS_HASH_IPV4_TCP:
13949 /* fall-through. */
13950 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13951 /* fall-through. */
13952 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13953 hrxqs[1] = hrxq_idx;
13955 case MLX5_RSS_HASH_IPV4_UDP:
13956 /* fall-through. */
13957 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13958 /* fall-through. */
13959 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13960 hrxqs[2] = hrxq_idx;
13962 case MLX5_RSS_HASH_IPV6:
13963 /* fall-through. */
13964 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13965 /* fall-through. */
13966 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13967 hrxqs[3] = hrxq_idx;
13969 case MLX5_RSS_HASH_IPV6_TCP:
13970 /* fall-through. */
13971 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13972 /* fall-through. */
13973 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13974 hrxqs[4] = hrxq_idx;
13976 case MLX5_RSS_HASH_IPV6_UDP:
13977 /* fall-through. */
13978 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13979 /* fall-through. */
13980 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13981 hrxqs[5] = hrxq_idx;
13983 case MLX5_RSS_HASH_NONE:
13984 hrxqs[6] = hrxq_idx;
13992 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13996 * Pointer to the Ethernet device structure.
13998 * Shared RSS action ID holding hash RX queue objects.
13999 * @param[in] hash_fields
14000 * Defines combination of packet fields to participate in RX hash.
14001 * @param[in] tunnel
14005 * Valid hash RX queue index, otherwise 0.
14008 flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
14009 const uint64_t hash_fields)
14011 struct mlx5_priv *priv = dev->data->dev_private;
14012 struct mlx5_shared_action_rss *shared_rss =
14013 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14014 const uint32_t *hrxqs = shared_rss->hrxq;
14016 switch (hash_fields & ~IBV_RX_HASH_INNER) {
14017 case MLX5_RSS_HASH_IPV4:
14018 /* fall-through. */
14019 case MLX5_RSS_HASH_IPV4_DST_ONLY:
14020 /* fall-through. */
14021 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
14023 case MLX5_RSS_HASH_IPV4_TCP:
14024 /* fall-through. */
14025 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
14026 /* fall-through. */
14027 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
14029 case MLX5_RSS_HASH_IPV4_UDP:
14030 /* fall-through. */
14031 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
14032 /* fall-through. */
14033 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
14035 case MLX5_RSS_HASH_IPV6:
14036 /* fall-through. */
14037 case MLX5_RSS_HASH_IPV6_DST_ONLY:
14038 /* fall-through. */
14039 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
14041 case MLX5_RSS_HASH_IPV6_TCP:
14042 /* fall-through. */
14043 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
14044 /* fall-through. */
14045 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
14047 case MLX5_RSS_HASH_IPV6_UDP:
14048 /* fall-through. */
14049 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
14050 /* fall-through. */
14051 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
14053 case MLX5_RSS_HASH_NONE:
14062 * Apply the flow to the NIC, lock free,
14063 * (mutex should be acquired by caller).
14066 * Pointer to the Ethernet device structure.
14067 * @param[in, out] flow
14068 * Pointer to flow structure.
14069 * @param[out] error
14070 * Pointer to error structure.
14073 * 0 on success, a negative errno value otherwise and rte_errno is set.
14076 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
14077 struct rte_flow_error *error)
14079 struct mlx5_flow_dv_workspace *dv;
14080 struct mlx5_flow_handle *dh;
14081 struct mlx5_flow_handle_dv *dv_h;
14082 struct mlx5_flow *dev_flow;
14083 struct mlx5_priv *priv = dev->data->dev_private;
14084 uint32_t handle_idx;
14088 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
14089 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
14093 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
14094 dev_flow = &wks->flows[idx];
14095 dv = &dev_flow->dv;
14096 dh = dev_flow->handle;
14099 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
14100 if (dv->transfer) {
14101 MLX5_ASSERT(priv->sh->dr_drop_action);
14102 dv->actions[n++] = priv->sh->dr_drop_action;
14104 #ifdef HAVE_MLX5DV_DR
14105 /* DR supports drop action placeholder. */
14106 MLX5_ASSERT(priv->sh->dr_drop_action);
14107 dv->actions[n++] = dv->group ?
14108 priv->sh->dr_drop_action :
14109 priv->root_drop_action;
14111 /* For DV we use the explicit drop queue. */
14112 MLX5_ASSERT(priv->drop_queue.hrxq);
14114 priv->drop_queue.hrxq->action;
14117 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
14118 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
14119 struct mlx5_hrxq *hrxq;
14122 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
14127 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14128 "cannot get hash queue");
14131 dh->rix_hrxq = hrxq_idx;
14132 dv->actions[n++] = hrxq->action;
14133 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14134 struct mlx5_hrxq *hrxq = NULL;
14137 hrxq_idx = flow_dv_action_rss_hrxq_lookup(dev,
14138 rss_desc->shared_rss,
14139 dev_flow->hash_fields);
14141 hrxq = mlx5_ipool_get
14142 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
14147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14148 "cannot get hash queue");
14151 dh->rix_srss = rss_desc->shared_rss;
14152 dv->actions[n++] = hrxq->action;
14153 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
14154 if (!priv->sh->default_miss_action) {
14157 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14158 "default miss action not be created.");
14161 dv->actions[n++] = priv->sh->default_miss_action;
14163 misc_mask = flow_dv_matcher_enable(dv->value.buf);
14164 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
14165 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
14166 (void *)&dv->value, n,
14167 dv->actions, &dh->drv_flow);
14171 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14173 (!priv->sh->config.allow_duplicate_pattern &&
14175 "duplicating pattern is not allowed" :
14176 "hardware refuses to create flow");
14179 if (priv->vmwa_context &&
14180 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14182 * The rule contains the VLAN pattern.
14183 * For VF we are going to create VLAN
14184 * interface to make hypervisor set correct
14185 * e-Switch vport context.
14187 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14192 err = rte_errno; /* Save rte_errno before cleanup. */
14193 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14194 handle_idx, dh, next) {
14195 /* hrxq is union, don't clear it if the flag is not set. */
14196 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14197 mlx5_hrxq_release(dev, dh->rix_hrxq);
14199 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14202 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14203 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14205 rte_errno = err; /* Restore rte_errno. */
14210 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14211 struct mlx5_list_entry *entry)
14213 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14217 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14218 mlx5_free(resource);
14222 * Release the flow matcher.
14225 * Pointer to Ethernet device.
14227 * Index to port ID action resource.
14230 * 1 while a reference on it exists, 0 when freed.
14233 flow_dv_matcher_release(struct rte_eth_dev *dev,
14234 struct mlx5_flow_handle *handle)
14236 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14237 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14238 typeof(*tbl), tbl);
14241 MLX5_ASSERT(matcher->matcher_object);
14242 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14243 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14248 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14250 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14251 struct mlx5_flow_dv_encap_decap_resource *res =
14252 container_of(entry, typeof(*res), entry);
14254 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14255 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14259 * Release an encap/decap resource.
14262 * Pointer to Ethernet device.
14263 * @param encap_decap_idx
14264 * Index of encap decap resource.
14267 * 1 while a reference on it exists, 0 when freed.
14270 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14271 uint32_t encap_decap_idx)
14273 struct mlx5_priv *priv = dev->data->dev_private;
14274 struct mlx5_flow_dv_encap_decap_resource *resource;
14276 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14280 MLX5_ASSERT(resource->action);
14281 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14285 * Release an jump to table action resource.
14288 * Pointer to Ethernet device.
14290 * Index to the jump action resource.
14293 * 1 while a reference on it exists, 0 when freed.
14296 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14299 struct mlx5_priv *priv = dev->data->dev_private;
14300 struct mlx5_flow_tbl_data_entry *tbl_data;
14302 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14306 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14310 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14312 struct mlx5_flow_dv_modify_hdr_resource *res =
14313 container_of(entry, typeof(*res), entry);
14314 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14316 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14317 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14321 * Release a modify-header resource.
14324 * Pointer to Ethernet device.
14326 * Pointer to mlx5_flow_handle.
14329 * 1 while a reference on it exists, 0 when freed.
14332 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14333 struct mlx5_flow_handle *handle)
14335 struct mlx5_priv *priv = dev->data->dev_private;
14336 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14338 MLX5_ASSERT(entry->action);
14339 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14343 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14345 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14346 struct mlx5_flow_dv_port_id_action_resource *resource =
14347 container_of(entry, typeof(*resource), entry);
14349 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14350 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14354 * Release port ID action resource.
14357 * Pointer to Ethernet device.
14359 * Pointer to mlx5_flow_handle.
14362 * 1 while a reference on it exists, 0 when freed.
14365 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14368 struct mlx5_priv *priv = dev->data->dev_private;
14369 struct mlx5_flow_dv_port_id_action_resource *resource;
14371 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14374 MLX5_ASSERT(resource->action);
14375 return mlx5_list_unregister(priv->sh->port_id_action_list,
14380 * Release shared RSS action resource.
14383 * Pointer to Ethernet device.
14385 * Shared RSS action index.
14388 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14390 struct mlx5_priv *priv = dev->data->dev_private;
14391 struct mlx5_shared_action_rss *shared_rss;
14393 shared_rss = mlx5_ipool_get
14394 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14395 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14399 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14401 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14402 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14403 container_of(entry, typeof(*resource), entry);
14405 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14406 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14410 * Release push vlan action resource.
14413 * Pointer to Ethernet device.
14415 * Pointer to mlx5_flow_handle.
14418 * 1 while a reference on it exists, 0 when freed.
14421 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14422 struct mlx5_flow_handle *handle)
14424 struct mlx5_priv *priv = dev->data->dev_private;
14425 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14426 uint32_t idx = handle->dvh.rix_push_vlan;
14428 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14431 MLX5_ASSERT(resource->action);
14432 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14437 * Release the fate resource.
14440 * Pointer to Ethernet device.
14442 * Pointer to mlx5_flow_handle.
14445 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14446 struct mlx5_flow_handle *handle)
14448 if (!handle->rix_fate)
14450 switch (handle->fate_action) {
14451 case MLX5_FLOW_FATE_QUEUE:
14452 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14453 mlx5_hrxq_release(dev, handle->rix_hrxq);
14455 case MLX5_FLOW_FATE_JUMP:
14456 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14458 case MLX5_FLOW_FATE_PORT_ID:
14459 flow_dv_port_id_action_resource_release(dev,
14460 handle->rix_port_id_action);
14463 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14466 handle->rix_fate = 0;
14470 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14471 struct mlx5_list_entry *entry)
14473 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14476 struct rte_eth_dev *dev = resource->dev;
14477 struct mlx5_priv *priv = dev->data->dev_private;
14479 if (resource->verbs_action)
14480 claim_zero(mlx5_flow_os_destroy_flow_action
14481 (resource->verbs_action));
14482 if (resource->normal_path_tbl)
14483 flow_dv_tbl_resource_release(MLX5_SH(dev),
14484 resource->normal_path_tbl);
14485 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14486 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14487 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14491 * Release an sample resource.
14494 * Pointer to Ethernet device.
14496 * Pointer to mlx5_flow_handle.
14499 * 1 while a reference on it exists, 0 when freed.
14502 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14503 struct mlx5_flow_handle *handle)
14505 struct mlx5_priv *priv = dev->data->dev_private;
14506 struct mlx5_flow_dv_sample_resource *resource;
14508 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14509 handle->dvh.rix_sample);
14512 MLX5_ASSERT(resource->verbs_action);
14513 return mlx5_list_unregister(priv->sh->sample_action_list,
14518 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14519 struct mlx5_list_entry *entry)
14521 struct mlx5_flow_dv_dest_array_resource *resource =
14522 container_of(entry, typeof(*resource), entry);
14523 struct rte_eth_dev *dev = resource->dev;
14524 struct mlx5_priv *priv = dev->data->dev_private;
14527 MLX5_ASSERT(resource->action);
14528 if (resource->action)
14529 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14530 for (; i < resource->num_of_dest; i++)
14531 flow_dv_sample_sub_actions_release(dev,
14532 &resource->sample_idx[i]);
14533 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14534 DRV_LOG(DEBUG, "destination array resource %p: removed",
14539 * Release an destination array resource.
14542 * Pointer to Ethernet device.
14544 * Pointer to mlx5_flow_handle.
14547 * 1 while a reference on it exists, 0 when freed.
14550 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14551 struct mlx5_flow_handle *handle)
14553 struct mlx5_priv *priv = dev->data->dev_private;
14554 struct mlx5_flow_dv_dest_array_resource *resource;
14556 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14557 handle->dvh.rix_dest_array);
14560 MLX5_ASSERT(resource->action);
14561 return mlx5_list_unregister(priv->sh->dest_array_list,
14566 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14568 struct mlx5_priv *priv = dev->data->dev_private;
14569 struct mlx5_dev_ctx_shared *sh = priv->sh;
14570 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14571 sh->geneve_tlv_option_resource;
14572 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14573 if (geneve_opt_resource) {
14574 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14575 __ATOMIC_RELAXED))) {
14576 claim_zero(mlx5_devx_cmd_destroy
14577 (geneve_opt_resource->obj));
14578 mlx5_free(sh->geneve_tlv_option_resource);
14579 sh->geneve_tlv_option_resource = NULL;
14582 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14586 * Remove the flow from the NIC but keeps it in memory.
14587 * Lock free, (mutex should be acquired by caller).
14590 * Pointer to Ethernet device.
14591 * @param[in, out] flow
14592 * Pointer to flow structure.
14595 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14597 struct mlx5_flow_handle *dh;
14598 uint32_t handle_idx;
14599 struct mlx5_priv *priv = dev->data->dev_private;
14603 handle_idx = flow->dev_handles;
14604 while (handle_idx) {
14605 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14609 if (dh->drv_flow) {
14610 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14611 dh->drv_flow = NULL;
14613 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14614 flow_dv_fate_resource_release(dev, dh);
14615 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14616 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14617 handle_idx = dh->next.next;
14622 * Remove the flow from the NIC and the memory.
14623 * Lock free, (mutex should be acquired by caller).
14626 * Pointer to the Ethernet device structure.
14627 * @param[in, out] flow
14628 * Pointer to flow structure.
14631 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14633 struct mlx5_flow_handle *dev_handle;
14634 struct mlx5_priv *priv = dev->data->dev_private;
14635 struct mlx5_flow_meter_info *fm = NULL;
14640 flow_dv_remove(dev, flow);
14641 if (flow->counter) {
14642 flow_dv_counter_free(dev, flow->counter);
14646 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14648 mlx5_flow_meter_detach(priv, fm);
14651 /* Keep the current age handling by default. */
14652 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14653 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14654 else if (flow->age)
14655 flow_dv_aso_age_release(dev, flow->age);
14656 if (flow->geneve_tlv_option) {
14657 flow_dv_geneve_tlv_option_resource_release(dev);
14658 flow->geneve_tlv_option = 0;
14660 while (flow->dev_handles) {
14661 uint32_t tmp_idx = flow->dev_handles;
14663 dev_handle = mlx5_ipool_get(priv->sh->ipool
14664 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14667 flow->dev_handles = dev_handle->next.next;
14668 while (dev_handle->flex_item) {
14669 int index = rte_bsf32(dev_handle->flex_item);
14671 mlx5_flex_release_index(dev, index);
14672 dev_handle->flex_item &= ~(uint8_t)RTE_BIT32(index);
14674 if (dev_handle->dvh.matcher)
14675 flow_dv_matcher_release(dev, dev_handle);
14676 if (dev_handle->dvh.rix_sample)
14677 flow_dv_sample_resource_release(dev, dev_handle);
14678 if (dev_handle->dvh.rix_dest_array)
14679 flow_dv_dest_array_resource_release(dev, dev_handle);
14680 if (dev_handle->dvh.rix_encap_decap)
14681 flow_dv_encap_decap_resource_release(dev,
14682 dev_handle->dvh.rix_encap_decap);
14683 if (dev_handle->dvh.modify_hdr)
14684 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14685 if (dev_handle->dvh.rix_push_vlan)
14686 flow_dv_push_vlan_action_resource_release(dev,
14688 if (dev_handle->dvh.rix_tag)
14689 flow_dv_tag_release(dev,
14690 dev_handle->dvh.rix_tag);
14691 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14692 flow_dv_fate_resource_release(dev, dev_handle);
14694 srss = dev_handle->rix_srss;
14695 if (fm && dev_handle->is_meter_flow_id &&
14696 dev_handle->split_flow_id)
14697 mlx5_ipool_free(fm->flow_ipool,
14698 dev_handle->split_flow_id);
14699 else if (dev_handle->split_flow_id &&
14700 !dev_handle->is_meter_flow_id)
14701 mlx5_ipool_free(priv->sh->ipool
14702 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14703 dev_handle->split_flow_id);
14704 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14708 flow_dv_shared_rss_action_release(dev, srss);
14712 * Release array of hash RX queue objects.
14716 * Pointer to the Ethernet device structure.
14717 * @param[in, out] hrxqs
14718 * Array of hash RX queue objects.
14721 * Total number of references to hash RX queue objects in *hrxqs* array
14722 * after this operation.
14725 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14726 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14731 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14732 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14742 * Release all hash RX queue objects representing shared RSS action.
14745 * Pointer to the Ethernet device structure.
14746 * @param[in, out] action
14747 * Shared RSS action to remove hash RX queue objects from.
14750 * Total number of references to hash RX queue objects stored in *action*
14751 * after this operation.
14752 * Expected to be 0 if no external references held.
14755 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14756 struct mlx5_shared_action_rss *shared_rss)
14758 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14762 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14765 * Only one hash value is available for one L3+L4 combination:
14767 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14768 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14769 * same slot in mlx5_rss_hash_fields.
14771 * @param[in] rss_types
14773 * @param[in, out] hash_field
14774 * hash_field variable needed to be adjusted.
14780 flow_dv_action_rss_l34_hash_adjust(uint64_t rss_types,
14781 uint64_t *hash_field)
14783 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14784 case MLX5_RSS_HASH_IPV4:
14785 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14786 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14787 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14788 *hash_field |= IBV_RX_HASH_DST_IPV4;
14789 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14790 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14792 *hash_field |= MLX5_RSS_HASH_IPV4;
14795 case MLX5_RSS_HASH_IPV6:
14796 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14797 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14798 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14799 *hash_field |= IBV_RX_HASH_DST_IPV6;
14800 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14801 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14803 *hash_field |= MLX5_RSS_HASH_IPV6;
14806 case MLX5_RSS_HASH_IPV4_UDP:
14807 /* fall-through. */
14808 case MLX5_RSS_HASH_IPV6_UDP:
14809 if (rss_types & RTE_ETH_RSS_UDP) {
14810 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14811 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14812 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14813 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14814 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14816 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14819 case MLX5_RSS_HASH_IPV4_TCP:
14820 /* fall-through. */
14821 case MLX5_RSS_HASH_IPV6_TCP:
14822 if (rss_types & RTE_ETH_RSS_TCP) {
14823 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14824 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14825 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14826 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14827 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14829 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14838 * Setup shared RSS action.
14839 * Prepare set of hash RX queue objects sufficient to handle all valid
14840 * hash_fields combinations (see enum ibv_rx_hash_fields).
14843 * Pointer to the Ethernet device structure.
14844 * @param[in] action_idx
14845 * Shared RSS action ipool index.
14846 * @param[in, out] action
14847 * Partially initialized shared RSS action.
14848 * @param[out] error
14849 * Perform verbose error reporting if not NULL. Initialized in case of
14853 * 0 on success, otherwise negative errno value.
14856 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14857 uint32_t action_idx,
14858 struct mlx5_shared_action_rss *shared_rss,
14859 struct rte_flow_error *error)
14861 struct mlx5_priv *priv = dev->data->dev_private;
14862 struct mlx5_flow_rss_desc rss_desc = { 0 };
14866 shared_rss->ind_tbl = mlx5_ind_table_obj_new
14867 (dev, shared_rss->origin.queue,
14868 shared_rss->origin.queue_num,
14870 !!dev->data->dev_started);
14871 if (!shared_rss->ind_tbl)
14872 return rte_flow_error_set(error, rte_errno,
14873 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14874 "cannot setup indirection table");
14875 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14876 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14877 rss_desc.const_q = shared_rss->origin.queue;
14878 rss_desc.queue_num = shared_rss->origin.queue_num;
14879 /* Set non-zero value to indicate a shared RSS. */
14880 rss_desc.shared_rss = action_idx;
14881 rss_desc.ind_tbl = shared_rss->ind_tbl;
14882 if (priv->sh->config.dv_flow_en == 2)
14883 rss_desc.hws_flags = MLX5DR_ACTION_FLAG_HWS_RX;
14884 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14885 struct mlx5_hrxq *hrxq;
14886 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14889 flow_dv_action_rss_l34_hash_adjust(shared_rss->origin.types,
14891 if (shared_rss->origin.level > 1) {
14892 hash_fields |= IBV_RX_HASH_INNER;
14895 rss_desc.tunnel = tunnel;
14896 rss_desc.hash_fields = hash_fields;
14897 hrxq = mlx5_hrxq_get(dev, &rss_desc);
14901 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14902 "cannot get hash queue");
14903 goto error_hrxq_new;
14905 err = __flow_dv_action_rss_hrxq_set
14906 (shared_rss, hash_fields, hrxq->idx);
14912 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14913 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14914 shared_rss->ind_tbl = NULL;
14920 * Create shared RSS action.
14923 * Pointer to the Ethernet device structure.
14925 * Shared action configuration.
14927 * RSS action specification used to create shared action.
14928 * @param[out] error
14929 * Perform verbose error reporting if not NULL. Initialized in case of
14933 * A valid shared action ID in case of success, 0 otherwise and
14934 * rte_errno is set.
14937 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14938 const struct rte_flow_indir_action_conf *conf,
14939 const struct rte_flow_action_rss *rss,
14940 struct rte_flow_error *error)
14942 struct mlx5_priv *priv = dev->data->dev_private;
14943 struct mlx5_shared_action_rss *shared_rss = NULL;
14944 struct rte_flow_action_rss *origin;
14945 const uint8_t *rss_key;
14948 RTE_SET_USED(conf);
14949 shared_rss = mlx5_ipool_zmalloc
14950 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14952 rte_flow_error_set(error, ENOMEM,
14953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14954 "cannot allocate resource memory");
14955 goto error_rss_init;
14957 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14958 rte_flow_error_set(error, E2BIG,
14959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14960 "rss action number out of range");
14961 goto error_rss_init;
14963 origin = &shared_rss->origin;
14964 origin->func = rss->func;
14965 origin->level = rss->level;
14966 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14967 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14968 /* NULL RSS key indicates default RSS key. */
14969 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14970 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14971 origin->key = &shared_rss->key[0];
14972 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14973 origin->queue = rss->queue;
14974 origin->queue_num = rss->queue_num;
14975 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14976 goto error_rss_init;
14977 /* Update queue with indirect table queue memoyr. */
14978 origin->queue = shared_rss->ind_tbl->queues;
14979 rte_spinlock_init(&shared_rss->action_rss_sl);
14980 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14981 rte_spinlock_lock(&priv->shared_act_sl);
14982 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14983 &priv->rss_shared_actions, idx, shared_rss, next);
14984 rte_spinlock_unlock(&priv->shared_act_sl);
14988 if (shared_rss->ind_tbl)
14989 mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl,
14990 !!dev->data->dev_started);
14991 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14998 * Destroy the shared RSS action.
14999 * Release related hash RX queue objects.
15002 * Pointer to the Ethernet device structure.
15004 * The shared RSS action object ID to be removed.
15005 * @param[out] error
15006 * Perform verbose error reporting if not NULL. Initialized in case of
15010 * 0 on success, otherwise negative errno value.
15013 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
15014 struct rte_flow_error *error)
15016 struct mlx5_priv *priv = dev->data->dev_private;
15017 struct mlx5_shared_action_rss *shared_rss =
15018 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15019 uint32_t old_refcnt = 1;
15023 return rte_flow_error_set(error, EINVAL,
15024 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15025 "invalid shared action");
15026 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
15027 0, 0, __ATOMIC_ACQUIRE,
15029 return rte_flow_error_set(error, EBUSY,
15030 RTE_FLOW_ERROR_TYPE_ACTION,
15032 "shared rss has references");
15033 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
15035 return rte_flow_error_set(error, EBUSY,
15036 RTE_FLOW_ERROR_TYPE_ACTION,
15038 "shared rss hrxq has references");
15039 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl,
15040 !!dev->data->dev_started);
15042 return rte_flow_error_set(error, EBUSY,
15043 RTE_FLOW_ERROR_TYPE_ACTION,
15045 "shared rss indirection table has"
15047 rte_spinlock_lock(&priv->shared_act_sl);
15048 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15049 &priv->rss_shared_actions, idx, shared_rss, next);
15050 rte_spinlock_unlock(&priv->shared_act_sl);
15051 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15057 * Create indirect action, lock free,
15058 * (mutex should be acquired by caller).
15059 * Dispatcher for action type specific call.
15062 * Pointer to the Ethernet device structure.
15064 * Shared action configuration.
15065 * @param[in] action
15066 * Action specification used to create indirect action.
15067 * @param[out] error
15068 * Perform verbose error reporting if not NULL. Initialized in case of
15072 * A valid shared action handle in case of success, NULL otherwise and
15073 * rte_errno is set.
15075 struct rte_flow_action_handle *
15076 flow_dv_action_create(struct rte_eth_dev *dev,
15077 const struct rte_flow_indir_action_conf *conf,
15078 const struct rte_flow_action *action,
15079 struct rte_flow_error *err)
15081 struct mlx5_priv *priv = dev->data->dev_private;
15082 uint32_t age_idx = 0;
15086 switch (action->type) {
15087 case RTE_FLOW_ACTION_TYPE_RSS:
15088 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
15089 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
15090 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
15092 case RTE_FLOW_ACTION_TYPE_AGE:
15093 age_idx = flow_dv_aso_age_alloc(dev, err);
15098 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
15099 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
15100 flow_dv_aso_age_params_init(dev, age_idx,
15101 ((const struct rte_flow_action_age *)
15102 action->conf)->context ?
15103 ((const struct rte_flow_action_age *)
15104 action->conf)->context :
15105 (void *)(uintptr_t)idx,
15106 ((const struct rte_flow_action_age *)
15107 action->conf)->timeout);
15110 case RTE_FLOW_ACTION_TYPE_COUNT:
15111 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
15112 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
15113 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
15115 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
15116 ret = flow_dv_translate_create_conntrack(dev, action->conf,
15118 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
15121 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
15122 NULL, "action type not supported");
15125 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
15129 * Destroy the indirect action.
15130 * Release action related resources on the NIC and the memory.
15131 * Lock free, (mutex should be acquired by caller).
15132 * Dispatcher for action type specific call.
15135 * Pointer to the Ethernet device structure.
15136 * @param[in] handle
15137 * The indirect action object handle to be removed.
15138 * @param[out] error
15139 * Perform verbose error reporting if not NULL. Initialized in case of
15143 * 0 on success, otherwise negative errno value.
15146 flow_dv_action_destroy(struct rte_eth_dev *dev,
15147 struct rte_flow_action_handle *handle,
15148 struct rte_flow_error *error)
15150 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15151 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15152 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15153 struct mlx5_flow_counter *cnt;
15154 uint32_t no_flow_refcnt = 1;
15158 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15159 return __flow_dv_action_rss_release(dev, idx, error);
15160 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15161 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15162 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15163 &no_flow_refcnt, 1, false,
15166 return rte_flow_error_set(error, EBUSY,
15167 RTE_FLOW_ERROR_TYPE_ACTION,
15169 "Indirect count action has references");
15170 flow_dv_counter_free(dev, idx);
15172 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15173 ret = flow_dv_aso_age_release(dev, idx);
15176 * In this case, the last flow has a reference will
15177 * actually release the age action.
15179 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15180 " released with references %d.", idx, ret);
15182 case MLX5_INDIRECT_ACTION_TYPE_CT:
15183 ret = flow_dv_aso_ct_release(dev, idx, error);
15187 DRV_LOG(DEBUG, "Connection tracking object %u still "
15188 "has references %d.", idx, ret);
15191 return rte_flow_error_set(error, ENOTSUP,
15192 RTE_FLOW_ERROR_TYPE_ACTION,
15194 "action type not supported");
15199 * Updates in place shared RSS action configuration.
15202 * Pointer to the Ethernet device structure.
15204 * The shared RSS action object ID to be updated.
15205 * @param[in] action_conf
15206 * RSS action specification used to modify *shared_rss*.
15207 * @param[out] error
15208 * Perform verbose error reporting if not NULL. Initialized in case of
15212 * 0 on success, otherwise negative errno value.
15213 * @note: currently only support update of RSS queues.
15216 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15217 const struct rte_flow_action_rss *action_conf,
15218 struct rte_flow_error *error)
15220 struct mlx5_priv *priv = dev->data->dev_private;
15221 struct mlx5_shared_action_rss *shared_rss =
15222 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15224 void *queue = NULL;
15225 void *queue_i = NULL;
15226 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15227 bool dev_started = !!dev->data->dev_started;
15230 return rte_flow_error_set(error, EINVAL,
15231 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15232 "invalid shared action to update");
15233 if (priv->obj_ops.ind_table_modify == NULL)
15234 return rte_flow_error_set(error, ENOTSUP,
15235 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15236 "cannot modify indirection table");
15237 queue = mlx5_malloc(MLX5_MEM_ZERO,
15238 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15241 return rte_flow_error_set(error, ENOMEM,
15242 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15244 "cannot allocate resource memory");
15245 memcpy(queue, action_conf->queue, queue_size);
15246 MLX5_ASSERT(shared_rss->ind_tbl);
15247 rte_spinlock_lock(&shared_rss->action_rss_sl);
15248 queue_i = shared_rss->ind_tbl->queues;
15249 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15250 queue, action_conf->queue_num,
15251 true /* standalone */,
15252 dev_started /* ref_new_qs */,
15253 dev_started /* deref_old_qs */);
15255 ret = rte_flow_error_set(error, rte_errno,
15256 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15257 "cannot update indirection table");
15259 /* Restore the queue to indirect table internal queue. */
15260 memcpy(queue_i, queue, queue_size);
15261 shared_rss->ind_tbl->queues = queue_i;
15262 shared_rss->origin.queue_num = action_conf->queue_num;
15265 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15270 * Updates in place conntrack context or direction.
15271 * Context update should be synchronized.
15274 * Pointer to the Ethernet device structure.
15276 * The conntrack object ID to be updated.
15277 * @param[in] update
15278 * Pointer to the structure of information to update.
15279 * @param[out] error
15280 * Perform verbose error reporting if not NULL. Initialized in case of
15284 * 0 on success, otherwise negative errno value.
15287 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15288 const struct rte_flow_modify_conntrack *update,
15289 struct rte_flow_error *error)
15291 struct mlx5_priv *priv = dev->data->dev_private;
15292 struct mlx5_aso_ct_action *ct;
15293 const struct rte_flow_action_conntrack *new_prf;
15295 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15298 if (PORT_ID(priv) != owner)
15299 return rte_flow_error_set(error, EACCES,
15300 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15302 "CT object owned by another port");
15303 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15304 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15306 return rte_flow_error_set(error, ENOMEM,
15307 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15309 "CT object is inactive");
15310 new_prf = &update->new_ct;
15311 if (update->direction)
15312 ct->is_original = !!new_prf->is_original_dir;
15313 if (update->state) {
15314 /* Only validate the profile when it needs to be updated. */
15315 ret = mlx5_validate_action_ct(dev, new_prf, error);
15318 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15320 return rte_flow_error_set(error, EIO,
15321 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15323 "Failed to send CT context update WQE");
15324 /* Block until ready or a failure. */
15325 ret = mlx5_aso_ct_available(priv->sh, ct);
15327 rte_flow_error_set(error, rte_errno,
15328 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15330 "Timeout to get the CT update");
15336 * Updates in place shared action configuration, lock free,
15337 * (mutex should be acquired by caller).
15340 * Pointer to the Ethernet device structure.
15341 * @param[in] handle
15342 * The indirect action object handle to be updated.
15343 * @param[in] update
15344 * Action specification used to modify the action pointed by *handle*.
15345 * *update* could be of same type with the action pointed by the *handle*
15346 * handle argument, or some other structures like a wrapper, depending on
15347 * the indirect action type.
15348 * @param[out] error
15349 * Perform verbose error reporting if not NULL. Initialized in case of
15353 * 0 on success, otherwise negative errno value.
15356 flow_dv_action_update(struct rte_eth_dev *dev,
15357 struct rte_flow_action_handle *handle,
15358 const void *update,
15359 struct rte_flow_error *err)
15361 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15362 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15363 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15364 const void *action_conf;
15367 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15368 action_conf = ((const struct rte_flow_action *)update)->conf;
15369 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15370 case MLX5_INDIRECT_ACTION_TYPE_CT:
15371 return __flow_dv_action_ct_update(dev, idx, update, err);
15373 return rte_flow_error_set(err, ENOTSUP,
15374 RTE_FLOW_ERROR_TYPE_ACTION,
15376 "action type update not supported");
15381 * Destroy the meter sub policy table rules.
15382 * Lock free, (mutex should be acquired by caller).
15385 * Pointer to Ethernet device.
15386 * @param[in] sub_policy
15387 * Pointer to meter sub policy table.
15390 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15391 struct mlx5_flow_meter_sub_policy *sub_policy)
15393 struct mlx5_priv *priv = dev->data->dev_private;
15394 struct mlx5_flow_tbl_data_entry *tbl;
15395 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15396 struct mlx5_flow_meter_info *next_fm;
15397 struct mlx5_sub_policy_color_rule *color_rule;
15401 for (i = 0; i < RTE_COLORS; i++) {
15403 if (i == RTE_COLOR_GREEN && policy &&
15404 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15405 next_fm = mlx5_flow_meter_find(priv,
15406 policy->act_cnt[i].next_mtr_id, NULL);
15407 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15409 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15410 tbl = container_of(color_rule->matcher->tbl,
15411 typeof(*tbl), tbl);
15412 mlx5_list_unregister(tbl->matchers,
15413 &color_rule->matcher->entry);
15414 TAILQ_REMOVE(&sub_policy->color_rules[i],
15415 color_rule, next_port);
15416 mlx5_free(color_rule);
15418 mlx5_flow_meter_detach(priv, next_fm);
15421 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15422 if (sub_policy->rix_hrxq[i]) {
15423 if (policy && !policy->is_hierarchy)
15424 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15425 sub_policy->rix_hrxq[i] = 0;
15427 if (sub_policy->jump_tbl[i]) {
15428 flow_dv_tbl_resource_release(MLX5_SH(dev),
15429 sub_policy->jump_tbl[i]);
15430 sub_policy->jump_tbl[i] = NULL;
15433 if (sub_policy->tbl_rsc) {
15434 flow_dv_tbl_resource_release(MLX5_SH(dev),
15435 sub_policy->tbl_rsc);
15436 sub_policy->tbl_rsc = NULL;
15441 * Destroy policy rules, lock free,
15442 * (mutex should be acquired by caller).
15443 * Dispatcher for action type specific call.
15446 * Pointer to the Ethernet device structure.
15447 * @param[in] mtr_policy
15448 * Meter policy struct.
15451 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15452 struct mlx5_flow_meter_policy *mtr_policy)
15455 struct mlx5_flow_meter_sub_policy *sub_policy;
15456 uint16_t sub_policy_num;
15458 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15459 sub_policy_num = (mtr_policy->sub_policy_num >>
15460 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15461 MLX5_MTR_SUB_POLICY_NUM_MASK;
15462 for (j = 0; j < sub_policy_num; j++) {
15463 sub_policy = mtr_policy->sub_policys[i][j];
15465 __flow_dv_destroy_sub_policy_rules(dev,
15472 * Destroy policy action, lock free,
15473 * (mutex should be acquired by caller).
15474 * Dispatcher for action type specific call.
15477 * Pointer to the Ethernet device structure.
15478 * @param[in] mtr_policy
15479 * Meter policy struct.
15482 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15483 struct mlx5_flow_meter_policy *mtr_policy)
15485 struct rte_flow_action *rss_action;
15486 struct mlx5_flow_handle dev_handle;
15489 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15490 if (mtr_policy->act_cnt[i].rix_mark) {
15491 flow_dv_tag_release(dev,
15492 mtr_policy->act_cnt[i].rix_mark);
15493 mtr_policy->act_cnt[i].rix_mark = 0;
15495 if (mtr_policy->act_cnt[i].modify_hdr) {
15496 dev_handle.dvh.modify_hdr =
15497 mtr_policy->act_cnt[i].modify_hdr;
15498 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15500 switch (mtr_policy->act_cnt[i].fate_action) {
15501 case MLX5_FLOW_FATE_SHARED_RSS:
15502 rss_action = mtr_policy->act_cnt[i].rss;
15503 mlx5_free(rss_action);
15505 case MLX5_FLOW_FATE_PORT_ID:
15506 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15507 flow_dv_port_id_action_resource_release(dev,
15508 mtr_policy->act_cnt[i].rix_port_id_action);
15509 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15512 case MLX5_FLOW_FATE_DROP:
15513 case MLX5_FLOW_FATE_JUMP:
15514 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15515 mtr_policy->act_cnt[i].dr_jump_action[j] =
15519 /*Queue action do nothing*/
15523 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15524 mtr_policy->dr_drop_action[j] = NULL;
15528 * Create policy action per domain, lock free,
15529 * (mutex should be acquired by caller).
15530 * Dispatcher for action type specific call.
15533 * Pointer to the Ethernet device structure.
15534 * @param[in] mtr_policy
15535 * Meter policy struct.
15536 * @param[in] action
15537 * Action specification used to create meter actions.
15538 * @param[out] error
15539 * Perform verbose error reporting if not NULL. Initialized in case of
15543 * 0 on success, otherwise negative errno value.
15546 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15547 struct mlx5_flow_meter_policy *mtr_policy,
15548 const struct rte_flow_action *actions[RTE_COLORS],
15549 enum mlx5_meter_domain domain,
15550 struct rte_mtr_error *error)
15552 struct mlx5_priv *priv = dev->data->dev_private;
15553 struct rte_flow_error flow_err;
15554 const struct rte_flow_action *act;
15555 uint64_t action_flags;
15556 struct mlx5_flow_handle dh;
15557 struct mlx5_flow dev_flow;
15558 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15560 uint8_t egress, transfer;
15561 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15563 struct mlx5_flow_dv_modify_hdr_resource res;
15564 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15565 sizeof(struct mlx5_modification_cmd) *
15566 (MLX5_MAX_MODIFY_NUM + 1)];
15568 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15569 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
15572 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15573 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15574 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15575 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15576 memset(&port_id_action, 0,
15577 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15578 memset(mhdr_res, 0, sizeof(*mhdr_res));
15579 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15580 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15581 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15582 dev_flow.handle = &dh;
15583 dev_flow.dv.port_id_action = &port_id_action;
15584 dev_flow.external = true;
15585 for (i = 0; i < RTE_COLORS; i++) {
15586 if (i < MLX5_MTR_RTE_COLORS)
15587 act_cnt = &mtr_policy->act_cnt[i];
15588 /* Skip the color policy actions creation. */
15589 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15590 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15593 for (act = actions[i];
15594 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15595 switch (act->type) {
15596 case RTE_FLOW_ACTION_TYPE_MARK:
15598 uint32_t tag_be = mlx5_flow_mark_set
15599 (((const struct rte_flow_action_mark *)
15602 if (i >= MLX5_MTR_RTE_COLORS)
15603 return -rte_mtr_error_set(error,
15605 RTE_MTR_ERROR_TYPE_METER_POLICY,
15607 "cannot create policy "
15608 "mark action for this color");
15610 if (flow_dv_tag_resource_register(dev, tag_be,
15611 &dev_flow, &flow_err))
15612 return -rte_mtr_error_set(error,
15614 RTE_MTR_ERROR_TYPE_METER_POLICY,
15616 "cannot setup policy mark action");
15617 MLX5_ASSERT(dev_flow.dv.tag_resource);
15618 act_cnt->rix_mark =
15619 dev_flow.handle->dvh.rix_tag;
15620 action_flags |= MLX5_FLOW_ACTION_MARK;
15623 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15624 if (i >= MLX5_MTR_RTE_COLORS)
15625 return -rte_mtr_error_set(error,
15627 RTE_MTR_ERROR_TYPE_METER_POLICY,
15629 "cannot create policy "
15630 "set tag action for this color");
15631 if (flow_dv_convert_action_set_tag
15633 (const struct rte_flow_action_set_tag *)
15634 act->conf, &flow_err))
15635 return -rte_mtr_error_set(error,
15637 RTE_MTR_ERROR_TYPE_METER_POLICY,
15638 NULL, "cannot convert policy "
15640 if (!mhdr_res->actions_num)
15641 return -rte_mtr_error_set(error,
15643 RTE_MTR_ERROR_TYPE_METER_POLICY,
15644 NULL, "cannot find policy "
15646 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15648 case RTE_FLOW_ACTION_TYPE_DROP:
15650 struct mlx5_flow_mtr_mng *mtrmng =
15652 struct mlx5_flow_tbl_data_entry *tbl_data;
15655 * Create the drop table with
15656 * METER DROP level.
15658 if (!mtrmng->drop_tbl[domain]) {
15659 mtrmng->drop_tbl[domain] =
15660 flow_dv_tbl_resource_get(dev,
15661 MLX5_FLOW_TABLE_LEVEL_METER,
15662 egress, transfer, false, NULL, 0,
15663 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15664 if (!mtrmng->drop_tbl[domain])
15665 return -rte_mtr_error_set
15667 RTE_MTR_ERROR_TYPE_METER_POLICY,
15669 "Failed to create meter drop table");
15671 tbl_data = container_of
15672 (mtrmng->drop_tbl[domain],
15673 struct mlx5_flow_tbl_data_entry, tbl);
15674 if (i < MLX5_MTR_RTE_COLORS) {
15675 act_cnt->dr_jump_action[domain] =
15676 tbl_data->jump.action;
15677 act_cnt->fate_action =
15678 MLX5_FLOW_FATE_DROP;
15680 if (i == RTE_COLOR_RED)
15681 mtr_policy->dr_drop_action[domain] =
15682 tbl_data->jump.action;
15683 action_flags |= MLX5_FLOW_ACTION_DROP;
15686 case RTE_FLOW_ACTION_TYPE_QUEUE:
15688 if (i >= MLX5_MTR_RTE_COLORS)
15689 return -rte_mtr_error_set(error,
15691 RTE_MTR_ERROR_TYPE_METER_POLICY,
15692 NULL, "cannot create policy "
15693 "fate queue for this color");
15695 ((const struct rte_flow_action_queue *)
15696 (act->conf))->index;
15697 act_cnt->fate_action =
15698 MLX5_FLOW_FATE_QUEUE;
15699 dev_flow.handle->fate_action =
15700 MLX5_FLOW_FATE_QUEUE;
15701 mtr_policy->is_queue = 1;
15702 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15705 case RTE_FLOW_ACTION_TYPE_RSS:
15709 if (i >= MLX5_MTR_RTE_COLORS)
15710 return -rte_mtr_error_set(error,
15712 RTE_MTR_ERROR_TYPE_METER_POLICY,
15714 "cannot create policy "
15715 "rss action for this color");
15717 * Save RSS conf into policy struct
15718 * for translate stage.
15720 rss_size = (int)rte_flow_conv
15721 (RTE_FLOW_CONV_OP_ACTION,
15722 NULL, 0, act, &flow_err);
15724 return -rte_mtr_error_set(error,
15726 RTE_MTR_ERROR_TYPE_METER_POLICY,
15727 NULL, "Get the wrong "
15728 "rss action struct size");
15729 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15730 rss_size, 0, SOCKET_ID_ANY);
15732 return -rte_mtr_error_set(error,
15734 RTE_MTR_ERROR_TYPE_METER_POLICY,
15736 "Fail to malloc rss action memory");
15737 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15738 act_cnt->rss, rss_size,
15741 return -rte_mtr_error_set(error,
15743 RTE_MTR_ERROR_TYPE_METER_POLICY,
15744 NULL, "Fail to save "
15745 "rss action into policy struct");
15746 act_cnt->fate_action =
15747 MLX5_FLOW_FATE_SHARED_RSS;
15748 action_flags |= MLX5_FLOW_ACTION_RSS;
15751 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15752 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15754 struct mlx5_flow_dv_port_id_action_resource
15756 uint32_t port_id = 0;
15758 if (i >= MLX5_MTR_RTE_COLORS)
15759 return -rte_mtr_error_set(error,
15761 RTE_MTR_ERROR_TYPE_METER_POLICY,
15762 NULL, "cannot create policy "
15763 "port action for this color");
15764 memset(&port_id_resource, 0,
15765 sizeof(port_id_resource));
15766 if (flow_dv_translate_action_port_id(dev, act,
15767 &port_id, &flow_err))
15768 return -rte_mtr_error_set(error,
15770 RTE_MTR_ERROR_TYPE_METER_POLICY,
15771 NULL, "cannot translate "
15772 "policy port action");
15773 port_id_resource.port_id = port_id;
15774 if (flow_dv_port_id_action_resource_register
15775 (dev, &port_id_resource,
15776 &dev_flow, &flow_err))
15777 return -rte_mtr_error_set(error,
15779 RTE_MTR_ERROR_TYPE_METER_POLICY,
15780 NULL, "cannot setup "
15781 "policy port action");
15782 act_cnt->rix_port_id_action =
15783 dev_flow.handle->rix_port_id_action;
15784 act_cnt->fate_action =
15785 MLX5_FLOW_FATE_PORT_ID;
15786 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15789 case RTE_FLOW_ACTION_TYPE_JUMP:
15791 uint32_t jump_group = 0;
15792 uint32_t table = 0;
15793 struct mlx5_flow_tbl_data_entry *tbl_data;
15794 struct flow_grp_info grp_info = {
15795 .external = !!dev_flow.external,
15796 .transfer = !!transfer,
15797 .fdb_def_rule = !!priv->fdb_def_rule,
15799 .skip_scale = dev_flow.skip_scale &
15800 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15802 struct mlx5_flow_meter_sub_policy *sub_policy =
15803 mtr_policy->sub_policys[domain][0];
15805 if (i >= MLX5_MTR_RTE_COLORS)
15806 return -rte_mtr_error_set(error,
15808 RTE_MTR_ERROR_TYPE_METER_POLICY,
15810 "cannot create policy "
15811 "jump action for this color");
15813 ((const struct rte_flow_action_jump *)
15815 if (mlx5_flow_group_to_table(dev, NULL,
15818 &grp_info, &flow_err))
15819 return -rte_mtr_error_set(error,
15821 RTE_MTR_ERROR_TYPE_METER_POLICY,
15822 NULL, "cannot setup "
15823 "policy jump action");
15824 sub_policy->jump_tbl[i] =
15825 flow_dv_tbl_resource_get(dev,
15828 !!dev_flow.external,
15829 NULL, jump_group, 0,
15832 (!sub_policy->jump_tbl[i])
15833 return -rte_mtr_error_set(error,
15835 RTE_MTR_ERROR_TYPE_METER_POLICY,
15836 NULL, "cannot create jump action.");
15837 tbl_data = container_of
15838 (sub_policy->jump_tbl[i],
15839 struct mlx5_flow_tbl_data_entry, tbl);
15840 act_cnt->dr_jump_action[domain] =
15841 tbl_data->jump.action;
15842 act_cnt->fate_action =
15843 MLX5_FLOW_FATE_JUMP;
15844 action_flags |= MLX5_FLOW_ACTION_JUMP;
15848 * No need to check meter hierarchy for Y or R colors
15849 * here since it is done in the validation stage.
15851 case RTE_FLOW_ACTION_TYPE_METER:
15853 const struct rte_flow_action_meter *mtr;
15854 struct mlx5_flow_meter_info *next_fm;
15855 struct mlx5_flow_meter_policy *next_policy;
15856 struct rte_flow_action tag_action;
15857 struct mlx5_rte_flow_action_set_tag set_tag;
15858 uint32_t next_mtr_idx = 0;
15861 next_fm = mlx5_flow_meter_find(priv,
15865 return -rte_mtr_error_set(error, EINVAL,
15866 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15867 "Fail to find next meter.");
15868 if (next_fm->def_policy)
15869 return -rte_mtr_error_set(error, EINVAL,
15870 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15871 "Hierarchy only supports termination meter.");
15872 next_policy = mlx5_flow_meter_policy_find(dev,
15873 next_fm->policy_id, NULL);
15874 MLX5_ASSERT(next_policy);
15875 if (next_fm->drop_cnt) {
15878 mlx5_flow_get_reg_id(dev,
15881 (struct rte_flow_error *)error);
15882 set_tag.offset = (priv->mtr_reg_share ?
15883 MLX5_MTR_COLOR_BITS : 0);
15884 set_tag.length = (priv->mtr_reg_share ?
15885 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15887 set_tag.data = next_mtr_idx;
15889 (enum rte_flow_action_type)
15890 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15891 tag_action.conf = &set_tag;
15892 if (flow_dv_convert_action_set_reg
15893 (mhdr_res, &tag_action,
15894 (struct rte_flow_error *)error))
15897 MLX5_FLOW_ACTION_SET_TAG;
15899 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15900 act_cnt->next_mtr_id = next_fm->meter_id;
15901 act_cnt->next_sub_policy = NULL;
15902 mtr_policy->is_hierarchy = 1;
15903 mtr_policy->dev = next_policy->dev;
15905 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15909 return -rte_mtr_error_set(error, ENOTSUP,
15910 RTE_MTR_ERROR_TYPE_METER_POLICY,
15911 NULL, "action type not supported");
15913 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15914 /* create modify action if needed. */
15915 dev_flow.dv.group = 1;
15916 if (flow_dv_modify_hdr_resource_register
15917 (dev, mhdr_res, &dev_flow, &flow_err))
15918 return -rte_mtr_error_set(error,
15920 RTE_MTR_ERROR_TYPE_METER_POLICY,
15921 NULL, "cannot register policy "
15923 act_cnt->modify_hdr =
15924 dev_flow.handle->dvh.modify_hdr;
15932 * Create policy action per domain, lock free,
15933 * (mutex should be acquired by caller).
15934 * Dispatcher for action type specific call.
15937 * Pointer to the Ethernet device structure.
15938 * @param[in] mtr_policy
15939 * Meter policy struct.
15940 * @param[in] action
15941 * Action specification used to create meter actions.
15942 * @param[out] error
15943 * Perform verbose error reporting if not NULL. Initialized in case of
15947 * 0 on success, otherwise negative errno value.
15950 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15951 struct mlx5_flow_meter_policy *mtr_policy,
15952 const struct rte_flow_action *actions[RTE_COLORS],
15953 struct rte_mtr_error *error)
15956 uint16_t sub_policy_num;
15958 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15959 sub_policy_num = (mtr_policy->sub_policy_num >>
15960 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15961 MLX5_MTR_SUB_POLICY_NUM_MASK;
15962 if (sub_policy_num) {
15963 ret = __flow_dv_create_domain_policy_acts(dev,
15964 mtr_policy, actions,
15965 (enum mlx5_meter_domain)i, error);
15966 /* Cleaning resource is done in the caller level. */
15975 * Query a DV flow rule for its statistics via DevX.
15978 * Pointer to Ethernet device.
15979 * @param[in] cnt_idx
15980 * Index to the flow counter.
15982 * Data retrieved by the query.
15983 * @param[out] error
15984 * Perform verbose error reporting if not NULL.
15987 * 0 on success, a negative errno value otherwise and rte_errno is set.
15990 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15991 struct rte_flow_error *error)
15993 struct mlx5_priv *priv = dev->data->dev_private;
15994 struct rte_flow_query_count *qc = data;
15996 if (!priv->sh->cdev->config.devx)
15997 return rte_flow_error_set(error, ENOTSUP,
15998 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16000 "counters are not supported");
16002 uint64_t pkts, bytes;
16003 struct mlx5_flow_counter *cnt;
16004 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
16007 return rte_flow_error_set(error, -err,
16008 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16009 NULL, "cannot read counters");
16010 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
16013 qc->hits = pkts - cnt->hits;
16014 qc->bytes = bytes - cnt->bytes;
16017 cnt->bytes = bytes;
16021 return rte_flow_error_set(error, EINVAL,
16022 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16024 "counters are not available");
16028 flow_dv_action_query(struct rte_eth_dev *dev,
16029 const struct rte_flow_action_handle *handle, void *data,
16030 struct rte_flow_error *error)
16032 struct mlx5_age_param *age_param;
16033 struct rte_flow_query_age *resp;
16034 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
16035 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
16036 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
16037 struct mlx5_priv *priv = dev->data->dev_private;
16038 struct mlx5_aso_ct_action *ct;
16043 case MLX5_INDIRECT_ACTION_TYPE_AGE:
16044 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
16046 resp->aged = __atomic_load_n(&age_param->state,
16047 __ATOMIC_RELAXED) == AGE_TMOUT ?
16049 resp->sec_since_last_hit_valid = !resp->aged;
16050 if (resp->sec_since_last_hit_valid)
16051 resp->sec_since_last_hit = __atomic_load_n
16052 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16054 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
16055 return flow_dv_query_count(dev, idx, data, error);
16056 case MLX5_INDIRECT_ACTION_TYPE_CT:
16057 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
16058 if (owner != PORT_ID(priv))
16059 return rte_flow_error_set(error, EACCES,
16060 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16062 "CT object owned by another port");
16063 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
16064 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
16067 return rte_flow_error_set(error, EFAULT,
16068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16070 "CT object is inactive");
16071 ((struct rte_flow_action_conntrack *)data)->peer_port =
16073 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
16075 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
16076 return rte_flow_error_set(error, EIO,
16077 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16079 "Failed to query CT context");
16082 return rte_flow_error_set(error, ENOTSUP,
16083 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
16084 "action type query not supported");
16089 * Query a flow rule AGE action for aging information.
16092 * Pointer to Ethernet device.
16094 * Pointer to the sub flow.
16096 * data retrieved by the query.
16097 * @param[out] error
16098 * Perform verbose error reporting if not NULL.
16101 * 0 on success, a negative errno value otherwise and rte_errno is set.
16104 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
16105 void *data, struct rte_flow_error *error)
16107 struct rte_flow_query_age *resp = data;
16108 struct mlx5_age_param *age_param;
16111 struct mlx5_aso_age_action *act =
16112 flow_aso_age_get_by_idx(dev, flow->age);
16114 age_param = &act->age_params;
16115 } else if (flow->counter) {
16116 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16118 if (!age_param || !age_param->timeout)
16119 return rte_flow_error_set
16121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16122 NULL, "cannot read age data");
16124 return rte_flow_error_set(error, EINVAL,
16125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16126 NULL, "age data not available");
16128 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16130 resp->sec_since_last_hit_valid = !resp->aged;
16131 if (resp->sec_since_last_hit_valid)
16132 resp->sec_since_last_hit = __atomic_load_n
16133 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16140 * @see rte_flow_query()
16141 * @see rte_flow_ops
16144 flow_dv_query(struct rte_eth_dev *dev,
16145 struct rte_flow *flow __rte_unused,
16146 const struct rte_flow_action *actions __rte_unused,
16147 void *data __rte_unused,
16148 struct rte_flow_error *error __rte_unused)
16152 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16153 switch (actions->type) {
16154 case RTE_FLOW_ACTION_TYPE_VOID:
16156 case RTE_FLOW_ACTION_TYPE_COUNT:
16157 ret = flow_dv_query_count(dev, flow->counter, data,
16160 case RTE_FLOW_ACTION_TYPE_AGE:
16161 ret = flow_dv_query_age(dev, flow, data, error);
16164 return rte_flow_error_set(error, ENOTSUP,
16165 RTE_FLOW_ERROR_TYPE_ACTION,
16167 "action not supported");
16174 * Destroy the meter table set.
16175 * Lock free, (mutex should be acquired by caller).
16178 * Pointer to Ethernet device.
16180 * Meter information table.
16183 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16184 struct mlx5_flow_meter_info *fm)
16186 struct mlx5_priv *priv = dev->data->dev_private;
16189 if (!fm || !priv->sh->config.dv_flow_en)
16191 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16192 if (fm->drop_rule[i]) {
16193 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16194 fm->drop_rule[i] = NULL;
16200 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16202 struct mlx5_priv *priv = dev->data->dev_private;
16203 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16204 struct mlx5_flow_tbl_data_entry *tbl;
16207 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16208 if (mtrmng->def_rule[i]) {
16209 claim_zero(mlx5_flow_os_destroy_flow
16210 (mtrmng->def_rule[i]));
16211 mtrmng->def_rule[i] = NULL;
16213 if (mtrmng->def_matcher[i]) {
16214 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16215 struct mlx5_flow_tbl_data_entry, tbl);
16216 mlx5_list_unregister(tbl->matchers,
16217 &mtrmng->def_matcher[i]->entry);
16218 mtrmng->def_matcher[i] = NULL;
16220 for (j = 0; j < MLX5_REG_BITS; j++) {
16221 if (mtrmng->drop_matcher[i][j]) {
16223 container_of(mtrmng->drop_matcher[i][j]->tbl,
16224 struct mlx5_flow_tbl_data_entry,
16226 mlx5_list_unregister(tbl->matchers,
16227 &mtrmng->drop_matcher[i][j]->entry);
16228 mtrmng->drop_matcher[i][j] = NULL;
16231 if (mtrmng->drop_tbl[i]) {
16232 flow_dv_tbl_resource_release(MLX5_SH(dev),
16233 mtrmng->drop_tbl[i]);
16234 mtrmng->drop_tbl[i] = NULL;
16239 /* Number of meter flow actions, count and jump or count and drop. */
16240 #define METER_ACTIONS 2
16243 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16244 enum mlx5_meter_domain domain)
16246 struct mlx5_priv *priv = dev->data->dev_private;
16247 struct mlx5_flow_meter_def_policy *def_policy =
16248 priv->sh->mtrmng->def_policy[domain];
16250 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16251 mlx5_free(def_policy);
16252 priv->sh->mtrmng->def_policy[domain] = NULL;
16256 * Destroy the default policy table set.
16259 * Pointer to Ethernet device.
16262 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16264 struct mlx5_priv *priv = dev->data->dev_private;
16267 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16268 if (priv->sh->mtrmng->def_policy[i])
16269 __flow_dv_destroy_domain_def_policy(dev,
16270 (enum mlx5_meter_domain)i);
16271 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16275 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16276 uint32_t color_reg_c_idx,
16277 enum rte_color color, void *matcher_object,
16278 int actions_n, void *actions,
16279 bool match_src_port, const struct rte_flow_item *item,
16280 void **rule, const struct rte_flow_attr *attr)
16283 struct mlx5_flow_dv_match_params value = {
16284 .size = sizeof(value.buf),
16286 struct mlx5_flow_dv_match_params matcher = {
16287 .size = sizeof(matcher.buf),
16289 struct mlx5_priv *priv = dev->data->dev_private;
16292 if (match_src_port && priv->sh->esw_mode) {
16293 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16294 value.buf, item, attr)) {
16295 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16296 " value with port.", color);
16300 flow_dv_match_meta_reg(matcher.buf, value.buf,
16301 (enum modify_reg)color_reg_c_idx,
16302 rte_col_2_mlx5_col(color), UINT32_MAX);
16303 misc_mask = flow_dv_matcher_enable(value.buf);
16304 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16305 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16306 actions_n, actions, rule);
16308 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16315 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16316 uint32_t color_reg_c_idx,
16318 struct mlx5_flow_meter_sub_policy *sub_policy,
16319 const struct rte_flow_attr *attr,
16320 bool match_src_port,
16321 const struct rte_flow_item *item,
16322 struct mlx5_flow_dv_matcher **policy_matcher,
16323 struct rte_flow_error *error)
16325 struct mlx5_list_entry *entry;
16326 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16327 struct mlx5_flow_dv_matcher matcher = {
16329 .size = sizeof(matcher.mask.buf),
16333 struct mlx5_flow_dv_match_params value = {
16334 .size = sizeof(value.buf),
16336 struct mlx5_flow_cb_ctx ctx = {
16340 struct mlx5_flow_tbl_data_entry *tbl_data;
16341 struct mlx5_priv *priv = dev->data->dev_private;
16342 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16344 if (match_src_port && priv->sh->esw_mode) {
16345 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16346 value.buf, item, attr)) {
16347 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16348 " with port.", priority);
16352 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16353 if (priority < RTE_COLOR_RED)
16354 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16355 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16356 matcher.priority = priority;
16357 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16358 matcher.mask.size);
16359 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16361 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16365 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16370 * Create the policy rules per domain.
16373 * Pointer to Ethernet device.
16374 * @param[in] sub_policy
16375 * Pointer to sub policy table..
16376 * @param[in] egress
16377 * Direction of the table.
16378 * @param[in] transfer
16379 * E-Switch or NIC flow.
16381 * Pointer to policy action list per color.
16384 * 0 on success, -1 otherwise.
16387 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16388 struct mlx5_flow_meter_sub_policy *sub_policy,
16389 uint8_t egress, uint8_t transfer, bool match_src_port,
16390 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16392 struct mlx5_priv *priv = dev->data->dev_private;
16393 struct rte_flow_error flow_err;
16394 uint32_t color_reg_c_idx;
16395 struct rte_flow_attr attr = {
16396 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16399 .egress = !!egress,
16400 .transfer = !!transfer,
16404 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16405 struct mlx5_sub_policy_color_rule *color_rule;
16407 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16411 /* Create policy table with POLICY level. */
16412 if (!sub_policy->tbl_rsc)
16413 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16414 MLX5_FLOW_TABLE_LEVEL_POLICY,
16415 egress, transfer, false, NULL, 0, 0,
16416 sub_policy->idx, &flow_err);
16417 if (!sub_policy->tbl_rsc) {
16419 "Failed to create meter sub policy table.");
16422 /* Prepare matchers. */
16423 color_reg_c_idx = ret;
16424 for (i = 0; i < RTE_COLORS; i++) {
16425 TAILQ_INIT(&sub_policy->color_rules[i]);
16426 if (!acts[i].actions_n)
16428 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16429 sizeof(struct mlx5_sub_policy_color_rule),
16432 DRV_LOG(ERR, "No memory to create color rule.");
16435 tmp_rules[i] = color_rule;
16436 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16437 color_rule, next_port);
16438 color_rule->src_port = priv->representor_id;
16441 /* Create matchers for colors. */
16442 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16443 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16444 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16445 &attr, svport_match, NULL,
16446 &color_rule->matcher, &flow_err)) {
16447 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16450 /* Create flow, matching color. */
16451 if (__flow_dv_create_policy_flow(dev,
16452 color_reg_c_idx, (enum rte_color)i,
16453 color_rule->matcher->matcher_object,
16454 acts[i].actions_n, acts[i].dv_actions,
16455 svport_match, NULL, &color_rule->rule,
16457 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16463 /* All the policy rules will be cleared. */
16465 color_rule = tmp_rules[i];
16467 if (color_rule->rule)
16468 mlx5_flow_os_destroy_flow(color_rule->rule);
16469 if (color_rule->matcher) {
16470 struct mlx5_flow_tbl_data_entry *tbl =
16471 container_of(color_rule->matcher->tbl,
16472 typeof(*tbl), tbl);
16473 mlx5_list_unregister(tbl->matchers,
16474 &color_rule->matcher->entry);
16476 TAILQ_REMOVE(&sub_policy->color_rules[i],
16477 color_rule, next_port);
16478 mlx5_free(color_rule);
16485 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16486 struct mlx5_flow_meter_policy *mtr_policy,
16487 struct mlx5_flow_meter_sub_policy *sub_policy,
16490 struct mlx5_priv *priv = dev->data->dev_private;
16491 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16492 struct mlx5_flow_dv_tag_resource *tag;
16493 struct mlx5_flow_dv_port_id_action_resource *port_action;
16494 struct mlx5_hrxq *hrxq;
16495 struct mlx5_flow_meter_info *next_fm = NULL;
16496 struct mlx5_flow_meter_policy *next_policy;
16497 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16498 struct mlx5_flow_tbl_data_entry *tbl_data;
16499 struct rte_flow_error error;
16500 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16501 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16502 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16503 bool match_src_port = false;
16506 /* If RSS or Queue, no previous actions / rules is created. */
16507 for (i = 0; i < RTE_COLORS; i++) {
16508 acts[i].actions_n = 0;
16509 if (i == RTE_COLOR_RED) {
16510 /* Only support drop on red. */
16511 acts[i].dv_actions[0] =
16512 mtr_policy->dr_drop_action[domain];
16513 acts[i].actions_n = 1;
16516 if (i == RTE_COLOR_GREEN &&
16517 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16518 struct rte_flow_attr attr = {
16519 .transfer = transfer
16522 next_fm = mlx5_flow_meter_find(priv,
16523 mtr_policy->act_cnt[i].next_mtr_id,
16527 "Failed to get next hierarchy meter.");
16530 if (mlx5_flow_meter_attach(priv, next_fm,
16532 DRV_LOG(ERR, "%s", error.message);
16536 /* Meter action must be the first for TX. */
16538 acts[i].dv_actions[acts[i].actions_n] =
16539 next_fm->meter_action;
16540 acts[i].actions_n++;
16543 if (mtr_policy->act_cnt[i].rix_mark) {
16544 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16545 mtr_policy->act_cnt[i].rix_mark);
16547 DRV_LOG(ERR, "Failed to find "
16548 "mark action for policy.");
16551 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16552 acts[i].actions_n++;
16554 if (mtr_policy->act_cnt[i].modify_hdr) {
16555 acts[i].dv_actions[acts[i].actions_n] =
16556 mtr_policy->act_cnt[i].modify_hdr->action;
16557 acts[i].actions_n++;
16559 if (mtr_policy->act_cnt[i].fate_action) {
16560 switch (mtr_policy->act_cnt[i].fate_action) {
16561 case MLX5_FLOW_FATE_PORT_ID:
16562 port_action = mlx5_ipool_get
16563 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16564 mtr_policy->act_cnt[i].rix_port_id_action);
16565 if (!port_action) {
16566 DRV_LOG(ERR, "Failed to find "
16567 "port action for policy.");
16570 acts[i].dv_actions[acts[i].actions_n] =
16571 port_action->action;
16572 acts[i].actions_n++;
16573 mtr_policy->dev = dev;
16574 match_src_port = true;
16576 case MLX5_FLOW_FATE_DROP:
16577 case MLX5_FLOW_FATE_JUMP:
16578 acts[i].dv_actions[acts[i].actions_n] =
16579 mtr_policy->act_cnt[i].dr_jump_action[domain];
16580 acts[i].actions_n++;
16582 case MLX5_FLOW_FATE_SHARED_RSS:
16583 case MLX5_FLOW_FATE_QUEUE:
16584 hrxq = mlx5_ipool_get
16585 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16586 sub_policy->rix_hrxq[i]);
16588 DRV_LOG(ERR, "Failed to find "
16589 "queue action for policy.");
16592 acts[i].dv_actions[acts[i].actions_n] =
16594 acts[i].actions_n++;
16596 case MLX5_FLOW_FATE_MTR:
16599 "No next hierarchy meter.");
16603 acts[i].dv_actions[acts[i].actions_n] =
16604 next_fm->meter_action;
16605 acts[i].actions_n++;
16607 if (mtr_policy->act_cnt[i].next_sub_policy) {
16609 mtr_policy->act_cnt[i].next_sub_policy;
16612 mlx5_flow_meter_policy_find(dev,
16613 next_fm->policy_id, NULL);
16614 MLX5_ASSERT(next_policy);
16616 next_policy->sub_policys[domain][0];
16619 container_of(next_sub_policy->tbl_rsc,
16620 struct mlx5_flow_tbl_data_entry, tbl);
16621 acts[i].dv_actions[acts[i].actions_n++] =
16622 tbl_data->jump.action;
16623 if (mtr_policy->act_cnt[i].modify_hdr)
16624 match_src_port = !!transfer;
16627 /*Queue action do nothing*/
16632 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16633 egress, transfer, match_src_port, acts)) {
16635 "Failed to create policy rules per domain.");
16641 mlx5_flow_meter_detach(priv, next_fm);
16646 * Create the policy rules.
16649 * Pointer to Ethernet device.
16650 * @param[in,out] mtr_policy
16651 * Pointer to meter policy table.
16654 * 0 on success, -1 otherwise.
16657 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16658 struct mlx5_flow_meter_policy *mtr_policy)
16661 uint16_t sub_policy_num;
16663 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16664 sub_policy_num = (mtr_policy->sub_policy_num >>
16665 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16666 MLX5_MTR_SUB_POLICY_NUM_MASK;
16667 if (!sub_policy_num)
16669 /* Prepare actions list and create policy rules. */
16670 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16671 mtr_policy->sub_policys[i][0], i)) {
16672 DRV_LOG(ERR, "Failed to create policy action "
16673 "list per domain.");
16681 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16683 struct mlx5_priv *priv = dev->data->dev_private;
16684 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16685 struct mlx5_flow_meter_def_policy *def_policy;
16686 struct mlx5_flow_tbl_resource *jump_tbl;
16687 struct mlx5_flow_tbl_data_entry *tbl_data;
16688 uint8_t egress, transfer;
16689 struct rte_flow_error error;
16690 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16693 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16694 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16695 def_policy = mtrmng->def_policy[domain];
16697 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16698 sizeof(struct mlx5_flow_meter_def_policy),
16699 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16701 DRV_LOG(ERR, "Failed to alloc default policy table.");
16702 goto def_policy_error;
16704 mtrmng->def_policy[domain] = def_policy;
16705 /* Create the meter suffix table with SUFFIX level. */
16706 jump_tbl = flow_dv_tbl_resource_get(dev,
16707 MLX5_FLOW_TABLE_LEVEL_METER,
16708 egress, transfer, false, NULL, 0,
16709 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16712 "Failed to create meter suffix table.");
16713 goto def_policy_error;
16715 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16716 tbl_data = container_of(jump_tbl,
16717 struct mlx5_flow_tbl_data_entry, tbl);
16718 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16719 tbl_data->jump.action;
16720 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16721 acts[RTE_COLOR_GREEN].actions_n = 1;
16723 * YELLOW has the same default policy as GREEN does.
16724 * G & Y share the same table and action. The 2nd time of table
16725 * resource getting is just to update the reference count for
16726 * the releasing stage.
16728 jump_tbl = flow_dv_tbl_resource_get(dev,
16729 MLX5_FLOW_TABLE_LEVEL_METER,
16730 egress, transfer, false, NULL, 0,
16731 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16734 "Failed to get meter suffix table.");
16735 goto def_policy_error;
16737 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16738 tbl_data = container_of(jump_tbl,
16739 struct mlx5_flow_tbl_data_entry, tbl);
16740 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16741 tbl_data->jump.action;
16742 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16743 acts[RTE_COLOR_YELLOW].actions_n = 1;
16744 /* Create jump action to the drop table. */
16745 if (!mtrmng->drop_tbl[domain]) {
16746 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16747 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16748 egress, transfer, false, NULL, 0,
16749 0, MLX5_MTR_TABLE_ID_DROP, &error);
16750 if (!mtrmng->drop_tbl[domain]) {
16751 DRV_LOG(ERR, "Failed to create meter "
16752 "drop table for default policy.");
16753 goto def_policy_error;
16756 /* all RED: unique Drop table for jump action. */
16757 tbl_data = container_of(mtrmng->drop_tbl[domain],
16758 struct mlx5_flow_tbl_data_entry, tbl);
16759 def_policy->dr_jump_action[RTE_COLOR_RED] =
16760 tbl_data->jump.action;
16761 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16762 acts[RTE_COLOR_RED].actions_n = 1;
16763 /* Create default policy rules. */
16764 ret = __flow_dv_create_domain_policy_rules(dev,
16765 &def_policy->sub_policy,
16766 egress, transfer, false, acts);
16768 DRV_LOG(ERR, "Failed to create default policy rules.");
16769 goto def_policy_error;
16774 __flow_dv_destroy_domain_def_policy(dev,
16775 (enum mlx5_meter_domain)domain);
16780 * Create the default policy table set.
16783 * Pointer to Ethernet device.
16785 * 0 on success, -1 otherwise.
16788 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16790 struct mlx5_priv *priv = dev->data->dev_private;
16793 /* Non-termination policy table. */
16794 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16795 if (!priv->sh->config.dv_esw_en &&
16796 i == MLX5_MTR_DOMAIN_TRANSFER)
16798 if (__flow_dv_create_domain_def_policy(dev, i)) {
16799 DRV_LOG(ERR, "Failed to create default policy");
16800 /* Rollback the created default policies for others. */
16801 flow_dv_destroy_def_policy(dev);
16809 * Create the needed meter tables.
16810 * Lock free, (mutex should be acquired by caller).
16813 * Pointer to Ethernet device.
16815 * Meter information table.
16816 * @param[in] mtr_idx
16818 * @param[in] domain_bitmap
16821 * 0 on success, -1 otherwise.
16824 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16825 struct mlx5_flow_meter_info *fm,
16827 uint8_t domain_bitmap)
16829 struct mlx5_priv *priv = dev->data->dev_private;
16830 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16831 struct rte_flow_error error;
16832 struct mlx5_flow_tbl_data_entry *tbl_data;
16833 uint8_t egress, transfer;
16834 void *actions[METER_ACTIONS];
16835 int domain, ret, i;
16836 struct mlx5_flow_counter *cnt;
16837 struct mlx5_flow_dv_match_params value = {
16838 .size = sizeof(value.buf),
16840 struct mlx5_flow_dv_match_params matcher_para = {
16841 .size = sizeof(matcher_para.buf),
16843 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16845 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16846 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16847 struct mlx5_list_entry *entry;
16848 struct mlx5_flow_dv_matcher matcher = {
16850 .size = sizeof(matcher.mask.buf),
16853 struct mlx5_flow_dv_matcher *drop_matcher;
16854 struct mlx5_flow_cb_ctx ctx = {
16860 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16861 rte_errno = ENOTSUP;
16864 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16865 if (!(domain_bitmap & (1 << domain)) ||
16866 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16868 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16869 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16870 /* Create the drop table with METER DROP level. */
16871 if (!mtrmng->drop_tbl[domain]) {
16872 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16873 MLX5_FLOW_TABLE_LEVEL_METER,
16874 egress, transfer, false, NULL, 0,
16875 0, MLX5_MTR_TABLE_ID_DROP, &error);
16876 if (!mtrmng->drop_tbl[domain]) {
16877 DRV_LOG(ERR, "Failed to create meter drop table.");
16881 /* Create default matcher in drop table. */
16882 matcher.tbl = mtrmng->drop_tbl[domain],
16883 tbl_data = container_of(mtrmng->drop_tbl[domain],
16884 struct mlx5_flow_tbl_data_entry, tbl);
16885 if (!mtrmng->def_matcher[domain]) {
16886 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16887 (enum modify_reg)mtr_id_reg_c,
16889 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16890 matcher.crc = rte_raw_cksum
16891 ((const void *)matcher.mask.buf,
16892 matcher.mask.size);
16893 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16895 DRV_LOG(ERR, "Failed to register meter "
16896 "drop default matcher.");
16899 mtrmng->def_matcher[domain] = container_of(entry,
16900 struct mlx5_flow_dv_matcher, entry);
16902 /* Create default rule in drop table. */
16903 if (!mtrmng->def_rule[domain]) {
16905 actions[i++] = priv->sh->dr_drop_action;
16906 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16907 (enum modify_reg)mtr_id_reg_c, 0, 0);
16908 misc_mask = flow_dv_matcher_enable(value.buf);
16909 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16910 ret = mlx5_flow_os_create_flow
16911 (mtrmng->def_matcher[domain]->matcher_object,
16912 (void *)&value, i, actions,
16913 &mtrmng->def_rule[domain]);
16915 DRV_LOG(ERR, "Failed to create meter "
16916 "default drop rule for drop table.");
16922 MLX5_ASSERT(mtrmng->max_mtr_bits);
16923 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16924 /* Create matchers for Drop. */
16925 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16926 (enum modify_reg)mtr_id_reg_c, 0,
16927 (mtr_id_mask << mtr_id_offset));
16928 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16929 matcher.crc = rte_raw_cksum
16930 ((const void *)matcher.mask.buf,
16931 matcher.mask.size);
16932 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16935 "Failed to register meter drop matcher.");
16938 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16939 container_of(entry, struct mlx5_flow_dv_matcher,
16943 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16944 /* Create drop rule, matching meter_id only. */
16945 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16946 (enum modify_reg)mtr_id_reg_c,
16947 (mtr_idx << mtr_id_offset), UINT32_MAX);
16949 cnt = flow_dv_counter_get_by_idx(dev,
16950 fm->drop_cnt, NULL);
16951 actions[i++] = cnt->action;
16952 actions[i++] = priv->sh->dr_drop_action;
16953 misc_mask = flow_dv_matcher_enable(value.buf);
16954 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16955 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16956 (void *)&value, i, actions,
16957 &fm->drop_rule[domain]);
16959 DRV_LOG(ERR, "Failed to create meter "
16960 "drop rule for drop table.");
16966 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16967 if (fm->drop_rule[i]) {
16968 claim_zero(mlx5_flow_os_destroy_flow
16969 (fm->drop_rule[i]));
16970 fm->drop_rule[i] = NULL;
16976 static struct mlx5_flow_meter_sub_policy *
16977 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16978 struct mlx5_flow_meter_policy *mtr_policy,
16979 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16980 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16983 struct mlx5_priv *priv = dev->data->dev_private;
16984 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16985 uint32_t sub_policy_idx = 0;
16986 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16988 struct mlx5_hrxq *hrxq;
16989 struct mlx5_flow_handle dh;
16990 struct mlx5_meter_policy_action_container *act_cnt;
16991 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16992 uint16_t sub_policy_num;
16993 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
16996 rte_spinlock_lock(&mtr_policy->sl);
16997 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17000 hrxq = mlx5_hrxq_get(dev, rss_desc[i]);
17002 rte_spinlock_unlock(&mtr_policy->sl);
17005 hrxq_idx[i] = hrxq->idx;
17007 sub_policy_num = (mtr_policy->sub_policy_num >>
17008 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17009 MLX5_MTR_SUB_POLICY_NUM_MASK;
17010 for (j = 0; j < sub_policy_num; j++) {
17011 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17014 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
17017 if (i >= MLX5_MTR_RTE_COLORS) {
17019 * Found the sub policy table with
17020 * the same queue per color.
17022 rte_spinlock_unlock(&mtr_policy->sl);
17023 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
17024 mlx5_hrxq_release(dev, hrxq_idx[i]);
17026 return mtr_policy->sub_policys[domain][j];
17029 /* Create sub policy. */
17030 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
17031 /* Reuse the first pre-allocated sub_policy. */
17032 sub_policy = mtr_policy->sub_policys[domain][0];
17033 sub_policy_idx = sub_policy->idx;
17035 sub_policy = mlx5_ipool_zmalloc
17036 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17039 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
17040 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
17041 mlx5_hrxq_release(dev, hrxq_idx[i]);
17042 goto rss_sub_policy_error;
17044 sub_policy->idx = sub_policy_idx;
17045 sub_policy->main_policy = mtr_policy;
17047 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17050 sub_policy->rix_hrxq[i] = hrxq_idx[i];
17051 if (mtr_policy->is_hierarchy) {
17052 act_cnt = &mtr_policy->act_cnt[i];
17053 act_cnt->next_sub_policy = next_sub_policy;
17054 mlx5_hrxq_release(dev, hrxq_idx[i]);
17057 * Overwrite the last action from
17058 * RSS action to Queue action.
17060 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
17063 DRV_LOG(ERR, "Failed to get policy hrxq");
17064 goto rss_sub_policy_error;
17066 act_cnt = &mtr_policy->act_cnt[i];
17067 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
17068 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
17069 if (act_cnt->rix_mark)
17071 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
17072 dh.rix_hrxq = hrxq_idx[i];
17073 flow_drv_rxq_flags_set(dev, &dh);
17077 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
17078 sub_policy, domain)) {
17079 DRV_LOG(ERR, "Failed to create policy "
17080 "rules for ingress domain.");
17081 goto rss_sub_policy_error;
17083 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17084 i = (mtr_policy->sub_policy_num >>
17085 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17086 MLX5_MTR_SUB_POLICY_NUM_MASK;
17087 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
17088 DRV_LOG(ERR, "No free sub-policy slot.");
17089 goto rss_sub_policy_error;
17091 mtr_policy->sub_policys[domain][i] = sub_policy;
17093 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17094 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17095 mtr_policy->sub_policy_num |=
17096 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17097 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17099 rte_spinlock_unlock(&mtr_policy->sl);
17102 rss_sub_policy_error:
17104 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17105 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17106 i = (mtr_policy->sub_policy_num >>
17107 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17108 MLX5_MTR_SUB_POLICY_NUM_MASK;
17109 mtr_policy->sub_policys[domain][i] = NULL;
17110 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17114 rte_spinlock_unlock(&mtr_policy->sl);
17119 * Find the policy table for prefix table with RSS.
17122 * Pointer to Ethernet device.
17123 * @param[in] mtr_policy
17124 * Pointer to meter policy table.
17125 * @param[in] rss_desc
17126 * Pointer to rss_desc
17128 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17130 static struct mlx5_flow_meter_sub_policy *
17131 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17132 struct mlx5_flow_meter_policy *mtr_policy,
17133 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17135 struct mlx5_priv *priv = dev->data->dev_private;
17136 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17137 struct mlx5_flow_meter_info *next_fm;
17138 struct mlx5_flow_meter_policy *next_policy;
17139 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17140 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17141 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17142 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17143 bool reuse_sub_policy;
17148 /* Iterate hierarchy to get all policies in this hierarchy. */
17149 policies[i++] = mtr_policy;
17150 if (!mtr_policy->is_hierarchy)
17152 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17153 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17156 next_fm = mlx5_flow_meter_find(priv,
17157 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17159 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17163 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17165 MLX5_ASSERT(next_policy);
17166 mtr_policy = next_policy;
17170 * From last policy to the first one in hierarchy,
17171 * create / get the sub policy for each of them.
17173 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17177 &reuse_sub_policy);
17179 DRV_LOG(ERR, "Failed to get the sub policy.");
17182 if (!reuse_sub_policy)
17183 sub_policies[j++] = sub_policy;
17184 next_sub_policy = sub_policy;
17189 uint16_t sub_policy_num;
17191 sub_policy = sub_policies[--j];
17192 mtr_policy = sub_policy->main_policy;
17193 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17194 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17195 sub_policy_num = (mtr_policy->sub_policy_num >>
17196 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17197 MLX5_MTR_SUB_POLICY_NUM_MASK;
17198 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17201 mtr_policy->sub_policy_num &=
17202 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17203 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17204 mtr_policy->sub_policy_num |=
17205 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17206 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17207 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17215 * Create the sub policy tag rule for all meters in hierarchy.
17218 * Pointer to Ethernet device.
17220 * Meter information table.
17221 * @param[in] src_port
17222 * The src port this extra rule should use.
17224 * The src port match item.
17225 * @param[out] error
17226 * Perform verbose error reporting if not NULL.
17228 * 0 on success, a negative errno value otherwise and rte_errno is set.
17231 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17232 struct mlx5_flow_meter_info *fm,
17234 const struct rte_flow_item *item,
17235 struct rte_flow_error *error)
17237 struct mlx5_priv *priv = dev->data->dev_private;
17238 struct mlx5_flow_meter_policy *mtr_policy;
17239 struct mlx5_flow_meter_sub_policy *sub_policy;
17240 struct mlx5_flow_meter_info *next_fm = NULL;
17241 struct mlx5_flow_meter_policy *next_policy;
17242 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17243 struct mlx5_flow_tbl_data_entry *tbl_data;
17244 struct mlx5_sub_policy_color_rule *color_rule;
17245 struct mlx5_meter_policy_acts acts;
17246 uint32_t color_reg_c_idx;
17247 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17248 struct rte_flow_attr attr = {
17249 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17256 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17259 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17260 MLX5_ASSERT(mtr_policy);
17261 if (!mtr_policy->is_hierarchy)
17263 next_fm = mlx5_flow_meter_find(priv,
17264 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17266 return rte_flow_error_set(error, EINVAL,
17267 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17268 "Failed to find next meter in hierarchy.");
17270 if (!next_fm->drop_cnt)
17272 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17273 sub_policy = mtr_policy->sub_policys[domain][0];
17274 for (i = 0; i < RTE_COLORS; i++) {
17275 bool rule_exist = false;
17276 struct mlx5_meter_policy_action_container *act_cnt;
17278 if (i >= RTE_COLOR_YELLOW)
17280 TAILQ_FOREACH(color_rule,
17281 &sub_policy->color_rules[i], next_port)
17282 if (color_rule->src_port == src_port) {
17288 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17289 sizeof(struct mlx5_sub_policy_color_rule),
17292 return rte_flow_error_set(error, ENOMEM,
17293 RTE_FLOW_ERROR_TYPE_ACTION,
17294 NULL, "No memory to create tag color rule.");
17295 color_rule->src_port = src_port;
17297 next_policy = mlx5_flow_meter_policy_find(dev,
17298 next_fm->policy_id, NULL);
17299 MLX5_ASSERT(next_policy);
17300 next_sub_policy = next_policy->sub_policys[domain][0];
17301 tbl_data = container_of(next_sub_policy->tbl_rsc,
17302 struct mlx5_flow_tbl_data_entry, tbl);
17303 act_cnt = &mtr_policy->act_cnt[i];
17305 acts.dv_actions[0] = next_fm->meter_action;
17306 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17308 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17309 acts.dv_actions[1] = next_fm->meter_action;
17311 acts.dv_actions[2] = tbl_data->jump.action;
17312 acts.actions_n = 3;
17313 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17317 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17318 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17320 &color_rule->matcher, error)) {
17321 rte_flow_error_set(error, errno,
17322 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17323 "Failed to create hierarchy meter matcher.");
17326 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17328 color_rule->matcher->matcher_object,
17329 acts.actions_n, acts.dv_actions,
17331 &color_rule->rule, &attr)) {
17332 rte_flow_error_set(error, errno,
17333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17334 "Failed to create hierarchy meter rule.");
17337 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17338 color_rule, next_port);
17342 * Recursive call to iterate all meters in hierarchy and
17343 * create needed rules.
17345 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17346 src_port, item, error);
17349 if (color_rule->rule)
17350 mlx5_flow_os_destroy_flow(color_rule->rule);
17351 if (color_rule->matcher) {
17352 struct mlx5_flow_tbl_data_entry *tbl =
17353 container_of(color_rule->matcher->tbl,
17354 typeof(*tbl), tbl);
17355 mlx5_list_unregister(tbl->matchers,
17356 &color_rule->matcher->entry);
17358 mlx5_free(color_rule);
17361 mlx5_flow_meter_detach(priv, next_fm);
17366 * Destroy the sub policy table with RX queue.
17369 * Pointer to Ethernet device.
17370 * @param[in] mtr_policy
17371 * Pointer to meter policy table.
17374 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17375 struct mlx5_flow_meter_policy *mtr_policy)
17377 struct mlx5_priv *priv = dev->data->dev_private;
17378 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17379 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17381 uint16_t sub_policy_num, new_policy_num;
17383 rte_spinlock_lock(&mtr_policy->sl);
17384 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17385 switch (mtr_policy->act_cnt[i].fate_action) {
17386 case MLX5_FLOW_FATE_SHARED_RSS:
17387 sub_policy_num = (mtr_policy->sub_policy_num >>
17388 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17389 MLX5_MTR_SUB_POLICY_NUM_MASK;
17390 new_policy_num = sub_policy_num;
17391 for (j = 0; j < sub_policy_num; j++) {
17393 mtr_policy->sub_policys[domain][j];
17395 __flow_dv_destroy_sub_policy_rules(dev,
17398 mtr_policy->sub_policys[domain][0]) {
17399 mtr_policy->sub_policys[domain][j] =
17402 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17408 if (new_policy_num != sub_policy_num) {
17409 mtr_policy->sub_policy_num &=
17410 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17411 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17412 mtr_policy->sub_policy_num |=
17414 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17415 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17418 case MLX5_FLOW_FATE_QUEUE:
17419 sub_policy = mtr_policy->sub_policys[domain][0];
17420 __flow_dv_destroy_sub_policy_rules(dev,
17424 /*Other actions without queue and do nothing*/
17428 rte_spinlock_unlock(&mtr_policy->sl);
17431 * Check whether the DR drop action is supported on the root table or not.
17433 * Create a simple flow with DR drop action on root table to validate
17434 * if DR drop action on root table is supported or not.
17437 * Pointer to rte_eth_dev structure.
17440 * 0 on success, a negative errno value otherwise and rte_errno is set.
17443 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17445 struct mlx5_priv *priv = dev->data->dev_private;
17446 struct mlx5_dev_ctx_shared *sh = priv->sh;
17447 struct mlx5_flow_dv_match_params mask = {
17448 .size = sizeof(mask.buf),
17450 struct mlx5_flow_dv_match_params value = {
17451 .size = sizeof(value.buf),
17453 struct mlx5dv_flow_matcher_attr dv_attr = {
17454 .type = IBV_FLOW_ATTR_NORMAL,
17456 .match_criteria_enable = 0,
17457 .match_mask = (void *)&mask,
17459 struct mlx5_flow_tbl_resource *tbl = NULL;
17460 void *matcher = NULL;
17464 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17468 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17469 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17470 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17471 tbl->obj, &matcher);
17474 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17475 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17476 &sh->dr_drop_action, &flow);
17479 * If DR drop action is not supported on root table, flow create will
17480 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17484 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17485 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17487 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17490 claim_zero(mlx5_flow_os_destroy_flow(flow));
17493 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17495 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17500 * Validate the batch counter support in root table.
17502 * Create a simple flow with invalid counter and drop action on root table to
17503 * validate if batch counter with offset on root table is supported or not.
17506 * Pointer to rte_eth_dev structure.
17509 * 0 on success, a negative errno value otherwise and rte_errno is set.
17512 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17514 struct mlx5_priv *priv = dev->data->dev_private;
17515 struct mlx5_dev_ctx_shared *sh = priv->sh;
17516 struct mlx5_flow_dv_match_params mask = {
17517 .size = sizeof(mask.buf),
17519 struct mlx5_flow_dv_match_params value = {
17520 .size = sizeof(value.buf),
17522 struct mlx5dv_flow_matcher_attr dv_attr = {
17523 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17525 .match_criteria_enable = 0,
17526 .match_mask = (void *)&mask,
17528 void *actions[2] = { 0 };
17529 struct mlx5_flow_tbl_resource *tbl = NULL;
17530 struct mlx5_devx_obj *dcs = NULL;
17531 void *matcher = NULL;
17535 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17539 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17542 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17546 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17547 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17548 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17549 tbl->obj, &matcher);
17552 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17553 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17557 * If batch counter with offset is not supported, the driver will not
17558 * validate the invalid offset value, flow create should success.
17559 * In this case, it means batch counter is not supported in root table.
17561 * Otherwise, if flow create is failed, counter offset is supported.
17564 DRV_LOG(INFO, "Batch counter is not supported in root "
17565 "table. Switch to fallback mode.");
17566 rte_errno = ENOTSUP;
17568 claim_zero(mlx5_flow_os_destroy_flow(flow));
17570 /* Check matcher to make sure validate fail at flow create. */
17571 if (!matcher || (matcher && errno != EINVAL))
17572 DRV_LOG(ERR, "Unexpected error in counter offset "
17573 "support detection");
17577 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17579 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17581 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17583 claim_zero(mlx5_devx_cmd_destroy(dcs));
17588 * Query a devx counter.
17591 * Pointer to the Ethernet device structure.
17593 * Index to the flow counter.
17595 * Set to clear the counter statistics.
17597 * The statistics value of packets.
17598 * @param[out] bytes
17599 * The statistics value of bytes.
17602 * 0 on success, otherwise return -1.
17605 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17606 uint64_t *pkts, uint64_t *bytes, void **action)
17608 struct mlx5_priv *priv = dev->data->dev_private;
17609 struct mlx5_flow_counter *cnt;
17610 uint64_t inn_pkts, inn_bytes;
17613 if (!priv->sh->cdev->config.devx)
17616 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17619 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17621 *action = cnt->action;
17623 *pkts = inn_pkts - cnt->hits;
17624 *bytes = inn_bytes - cnt->bytes;
17626 cnt->hits = inn_pkts;
17627 cnt->bytes = inn_bytes;
17633 * Get aged-out flows.
17636 * Pointer to the Ethernet device structure.
17637 * @param[in] context
17638 * The address of an array of pointers to the aged-out flows contexts.
17639 * @param[in] nb_contexts
17640 * The length of context array pointers.
17641 * @param[out] error
17642 * Perform verbose error reporting if not NULL. Initialized in case of
17646 * how many contexts get in success, otherwise negative errno value.
17647 * if nb_contexts is 0, return the amount of all aged contexts.
17648 * if nb_contexts is not 0 , return the amount of aged flows reported
17649 * in the context array.
17650 * @note: only stub for now
17653 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17655 uint32_t nb_contexts,
17656 struct rte_flow_error *error)
17658 struct mlx5_priv *priv = dev->data->dev_private;
17659 struct mlx5_age_info *age_info;
17660 struct mlx5_age_param *age_param;
17661 struct mlx5_flow_counter *counter;
17662 struct mlx5_aso_age_action *act;
17665 if (nb_contexts && !context)
17666 return rte_flow_error_set(error, EINVAL,
17667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17668 NULL, "empty context");
17669 age_info = GET_PORT_AGE_INFO(priv);
17670 rte_spinlock_lock(&age_info->aged_sl);
17671 LIST_FOREACH(act, &age_info->aged_aso, next) {
17674 context[nb_flows - 1] =
17675 act->age_params.context;
17676 if (!(--nb_contexts))
17680 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17683 age_param = MLX5_CNT_TO_AGE(counter);
17684 context[nb_flows - 1] = age_param->context;
17685 if (!(--nb_contexts))
17689 rte_spinlock_unlock(&age_info->aged_sl);
17690 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17695 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17698 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17700 return flow_dv_counter_alloc(dev, 0);
17704 * Validate indirect action.
17705 * Dispatcher for action type specific validation.
17708 * Pointer to the Ethernet device structure.
17710 * Indirect action configuration.
17711 * @param[in] action
17712 * The indirect action object to validate.
17713 * @param[out] error
17714 * Perform verbose error reporting if not NULL. Initialized in case of
17718 * 0 on success, otherwise negative errno value.
17721 flow_dv_action_validate(struct rte_eth_dev *dev,
17722 const struct rte_flow_indir_action_conf *conf,
17723 const struct rte_flow_action *action,
17724 struct rte_flow_error *err)
17726 struct mlx5_priv *priv = dev->data->dev_private;
17728 RTE_SET_USED(conf);
17729 switch (action->type) {
17730 case RTE_FLOW_ACTION_TYPE_RSS:
17732 * priv->obj_ops is set according to driver capabilities.
17733 * When DevX capabilities are
17734 * sufficient, it is set to devx_obj_ops.
17735 * Otherwise, it is set to ibv_obj_ops.
17736 * ibv_obj_ops doesn't support ind_table_modify operation.
17737 * In this case the indirect RSS action can't be used.
17739 if (priv->obj_ops.ind_table_modify == NULL)
17740 return rte_flow_error_set
17742 RTE_FLOW_ERROR_TYPE_ACTION,
17744 "Indirect RSS action not supported");
17745 return mlx5_validate_action_rss(dev, action, err);
17746 case RTE_FLOW_ACTION_TYPE_AGE:
17747 if (!priv->sh->aso_age_mng)
17748 return rte_flow_error_set(err, ENOTSUP,
17749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17751 "Indirect age action not supported");
17752 return flow_dv_validate_action_age(0, action, dev, err);
17753 case RTE_FLOW_ACTION_TYPE_COUNT:
17754 return flow_dv_validate_action_count(dev, true, 0, NULL, err);
17755 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17756 if (!priv->sh->ct_aso_en)
17757 return rte_flow_error_set(err, ENOTSUP,
17758 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17759 "ASO CT is not supported");
17760 return mlx5_validate_action_ct(dev, action->conf, err);
17762 return rte_flow_error_set(err, ENOTSUP,
17763 RTE_FLOW_ERROR_TYPE_ACTION,
17765 "action type not supported");
17770 * Check if the RSS configurations for colors of a meter policy match
17771 * each other, except the queues.
17774 * Pointer to the first RSS flow action.
17776 * Pointer to the second RSS flow action.
17779 * 0 on match, 1 on conflict.
17782 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17783 const struct rte_flow_action_rss *r2)
17785 if (r1 == NULL || r2 == NULL)
17787 if (!(r1->level <= 1 && r2->level <= 1) &&
17788 !(r1->level > 1 && r2->level > 1))
17790 if (r1->types != r2->types &&
17791 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17792 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17794 if (r1->key || r2->key) {
17795 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17796 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17798 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17805 * Validate the meter hierarchy chain for meter policy.
17808 * Pointer to the Ethernet device structure.
17809 * @param[in] meter_id
17811 * @param[in] action_flags
17812 * Holds the actions detected until now.
17813 * @param[out] is_rss
17815 * @param[out] hierarchy_domain
17816 * The domain bitmap for hierarchy policy.
17817 * @param[out] error
17818 * Perform verbose error reporting if not NULL. Initialized in case of
17822 * 0 on success, otherwise negative errno value with error set.
17825 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17827 uint64_t action_flags,
17829 uint8_t *hierarchy_domain,
17830 struct rte_mtr_error *error)
17832 struct mlx5_priv *priv = dev->data->dev_private;
17833 struct mlx5_flow_meter_info *fm;
17834 struct mlx5_flow_meter_policy *policy;
17837 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17838 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17839 return -rte_mtr_error_set(error, EINVAL,
17840 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17842 "Multiple fate actions not supported.");
17843 *hierarchy_domain = 0;
17845 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17847 return -rte_mtr_error_set(error, EINVAL,
17848 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17849 "Meter not found in meter hierarchy.");
17850 if (fm->def_policy)
17851 return -rte_mtr_error_set(error, EINVAL,
17852 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17853 "Non termination meter not supported in hierarchy.");
17854 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17855 MLX5_ASSERT(policy);
17857 * Only inherit the supported domains of the first meter in
17859 * One meter supports at least one domain.
17861 if (!*hierarchy_domain) {
17862 if (policy->transfer)
17863 *hierarchy_domain |=
17864 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17865 if (policy->ingress)
17866 *hierarchy_domain |=
17867 MLX5_MTR_DOMAIN_INGRESS_BIT;
17868 if (policy->egress)
17869 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17871 if (!policy->is_hierarchy) {
17872 *is_rss = policy->is_rss;
17875 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17876 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17877 return -rte_mtr_error_set(error, EINVAL,
17878 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17879 "Exceed max hierarchy meter number.");
17885 * Validate meter policy actions.
17886 * Dispatcher for action type specific validation.
17889 * Pointer to the Ethernet device structure.
17890 * @param[in] action
17891 * The meter policy action object to validate.
17893 * Attributes of flow to determine steering domain.
17894 * @param[out] error
17895 * Perform verbose error reporting if not NULL. Initialized in case of
17899 * 0 on success, otherwise negative errno value.
17902 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17903 const struct rte_flow_action *actions[RTE_COLORS],
17904 struct rte_flow_attr *attr,
17906 uint8_t *domain_bitmap,
17907 uint8_t *policy_mode,
17908 struct rte_mtr_error *error)
17910 struct mlx5_priv *priv = dev->data->dev_private;
17911 struct mlx5_sh_config *dev_conf = &priv->sh->config;
17912 const struct rte_flow_action *act;
17913 uint64_t action_flags[RTE_COLORS] = {0};
17916 struct rte_flow_error flow_err;
17917 uint8_t domain_color[RTE_COLORS] = {0};
17918 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17919 uint8_t hierarchy_domain = 0;
17920 const struct rte_flow_action_meter *mtr;
17921 bool def_green = false;
17922 bool def_yellow = false;
17923 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17925 if (!dev_conf->dv_esw_en)
17926 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17927 *domain_bitmap = def_domain;
17928 /* Red color could only support DROP action. */
17929 if (!actions[RTE_COLOR_RED] ||
17930 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17931 return -rte_mtr_error_set(error, ENOTSUP,
17932 RTE_MTR_ERROR_TYPE_METER_POLICY,
17933 NULL, "Red color only supports drop action.");
17935 * Check default policy actions:
17936 * Green / Yellow: no action, Red: drop action
17937 * Either G or Y will trigger default policy actions to be created.
17939 if (!actions[RTE_COLOR_GREEN] ||
17940 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17942 if (!actions[RTE_COLOR_YELLOW] ||
17943 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17945 if (def_green && def_yellow) {
17946 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17948 } else if (!def_green && def_yellow) {
17949 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17950 } else if (def_green && !def_yellow) {
17951 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17953 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17955 /* Set to empty string in case of NULL pointer access by user. */
17956 flow_err.message = "";
17957 for (i = 0; i < RTE_COLORS; i++) {
17959 for (action_flags[i] = 0, actions_n = 0;
17960 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17962 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17963 return -rte_mtr_error_set(error, ENOTSUP,
17964 RTE_MTR_ERROR_TYPE_METER_POLICY,
17965 NULL, "too many actions");
17966 switch (act->type) {
17967 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17968 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17969 if (!dev_conf->dv_esw_en)
17970 return -rte_mtr_error_set(error,
17972 RTE_MTR_ERROR_TYPE_METER_POLICY,
17973 NULL, "PORT action validate check"
17974 " fail for ESW disable");
17975 ret = flow_dv_validate_action_port_id(dev,
17977 act, attr, &flow_err);
17979 return -rte_mtr_error_set(error,
17981 RTE_MTR_ERROR_TYPE_METER_POLICY,
17982 NULL, flow_err.message ?
17984 "PORT action validate check fail");
17986 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17988 case RTE_FLOW_ACTION_TYPE_MARK:
17989 ret = flow_dv_validate_action_mark(dev, act,
17993 return -rte_mtr_error_set(error,
17995 RTE_MTR_ERROR_TYPE_METER_POLICY,
17996 NULL, flow_err.message ?
17998 "Mark action validate check fail");
17999 if (dev_conf->dv_xmeta_en !=
18000 MLX5_XMETA_MODE_LEGACY)
18001 return -rte_mtr_error_set(error,
18003 RTE_MTR_ERROR_TYPE_METER_POLICY,
18004 NULL, "Extend MARK action is "
18005 "not supported. Please try use "
18006 "default policy for meter.");
18007 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
18010 case RTE_FLOW_ACTION_TYPE_SET_TAG:
18011 ret = flow_dv_validate_action_set_tag(dev,
18012 act, action_flags[i],
18015 return -rte_mtr_error_set(error,
18017 RTE_MTR_ERROR_TYPE_METER_POLICY,
18018 NULL, flow_err.message ?
18020 "Set tag action validate check fail");
18021 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
18024 case RTE_FLOW_ACTION_TYPE_DROP:
18025 ret = mlx5_flow_validate_action_drop
18026 (action_flags[i], attr, &flow_err);
18028 return -rte_mtr_error_set(error,
18030 RTE_MTR_ERROR_TYPE_METER_POLICY,
18031 NULL, flow_err.message ?
18033 "Drop action validate check fail");
18034 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
18037 case RTE_FLOW_ACTION_TYPE_QUEUE:
18039 * Check whether extensive
18040 * metadata feature is engaged.
18042 if (dev_conf->dv_flow_en &&
18043 (dev_conf->dv_xmeta_en !=
18044 MLX5_XMETA_MODE_LEGACY) &&
18045 mlx5_flow_ext_mreg_supported(dev))
18046 return -rte_mtr_error_set(error,
18048 RTE_MTR_ERROR_TYPE_METER_POLICY,
18049 NULL, "Queue action with meta "
18050 "is not supported. Please try use "
18051 "default policy for meter.");
18052 ret = mlx5_flow_validate_action_queue(act,
18053 action_flags[i], dev,
18056 return -rte_mtr_error_set(error,
18058 RTE_MTR_ERROR_TYPE_METER_POLICY,
18059 NULL, flow_err.message ?
18061 "Queue action validate check fail");
18062 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
18065 case RTE_FLOW_ACTION_TYPE_RSS:
18066 if (dev_conf->dv_flow_en &&
18067 (dev_conf->dv_xmeta_en !=
18068 MLX5_XMETA_MODE_LEGACY) &&
18069 mlx5_flow_ext_mreg_supported(dev))
18070 return -rte_mtr_error_set(error,
18072 RTE_MTR_ERROR_TYPE_METER_POLICY,
18073 NULL, "RSS action with meta "
18074 "is not supported. Please try use "
18075 "default policy for meter.");
18076 ret = mlx5_validate_action_rss(dev, act,
18079 return -rte_mtr_error_set(error,
18081 RTE_MTR_ERROR_TYPE_METER_POLICY,
18082 NULL, flow_err.message ?
18084 "RSS action validate check fail");
18085 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
18087 /* Either G or Y will set the RSS. */
18088 rss_color[i] = act->conf;
18090 case RTE_FLOW_ACTION_TYPE_JUMP:
18091 ret = flow_dv_validate_action_jump(dev,
18092 NULL, act, action_flags[i],
18093 attr, true, &flow_err);
18095 return -rte_mtr_error_set(error,
18097 RTE_MTR_ERROR_TYPE_METER_POLICY,
18098 NULL, flow_err.message ?
18100 "Jump action validate check fail");
18102 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
18105 * Only the last meter in the hierarchy will support
18106 * the YELLOW color steering. Then in the meter policy
18107 * actions list, there should be no other meter inside.
18109 case RTE_FLOW_ACTION_TYPE_METER:
18110 if (i != RTE_COLOR_GREEN)
18111 return -rte_mtr_error_set(error,
18113 RTE_MTR_ERROR_TYPE_METER_POLICY,
18115 "Meter hierarchy only supports GREEN color.");
18116 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
18117 return -rte_mtr_error_set(error,
18119 RTE_MTR_ERROR_TYPE_METER_POLICY,
18121 "No yellow policy should be provided in meter hierarchy.");
18123 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18133 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18136 return -rte_mtr_error_set(error, ENOTSUP,
18137 RTE_MTR_ERROR_TYPE_METER_POLICY,
18139 "Doesn't support optional action");
18142 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18143 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18144 } else if ((action_flags[i] &
18145 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18146 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18148 * Only support MLX5_XMETA_MODE_LEGACY
18149 * so MARK action is only in ingress domain.
18151 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18153 domain_color[i] = def_domain;
18154 if (action_flags[i] &&
18155 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18157 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18159 if (action_flags[i] &
18160 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18161 domain_color[i] &= hierarchy_domain;
18163 * Non-termination actions only support NIC Tx domain.
18164 * The adjustion should be skipped when there is no
18165 * action or only END is provided. The default domains
18166 * bit-mask is set to find the MIN intersection.
18167 * The action flags checking should also be skipped.
18169 if ((def_green && i == RTE_COLOR_GREEN) ||
18170 (def_yellow && i == RTE_COLOR_YELLOW))
18173 * Validate the drop action mutual exclusion
18174 * with other actions. Drop action is mutually-exclusive
18175 * with any other action, except for Count action.
18177 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18178 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18179 return -rte_mtr_error_set(error, ENOTSUP,
18180 RTE_MTR_ERROR_TYPE_METER_POLICY,
18181 NULL, "Drop action is mutually-exclusive "
18182 "with any other action");
18184 /* Eswitch has few restrictions on using items and actions */
18185 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18186 if (!mlx5_flow_ext_mreg_supported(dev) &&
18187 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18188 return -rte_mtr_error_set(error, ENOTSUP,
18189 RTE_MTR_ERROR_TYPE_METER_POLICY,
18190 NULL, "unsupported action MARK");
18191 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18192 return -rte_mtr_error_set(error, ENOTSUP,
18193 RTE_MTR_ERROR_TYPE_METER_POLICY,
18194 NULL, "unsupported action QUEUE");
18195 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18196 return -rte_mtr_error_set(error, ENOTSUP,
18197 RTE_MTR_ERROR_TYPE_METER_POLICY,
18198 NULL, "unsupported action RSS");
18199 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18200 return -rte_mtr_error_set(error, ENOTSUP,
18201 RTE_MTR_ERROR_TYPE_METER_POLICY,
18202 NULL, "no fate action is found");
18204 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18205 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18206 if ((domain_color[i] &
18207 MLX5_MTR_DOMAIN_EGRESS_BIT))
18209 MLX5_MTR_DOMAIN_EGRESS_BIT;
18211 return -rte_mtr_error_set(error,
18213 RTE_MTR_ERROR_TYPE_METER_POLICY,
18215 "no fate action is found");
18219 /* If both colors have RSS, the attributes should be the same. */
18220 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18221 rss_color[RTE_COLOR_YELLOW]))
18222 return -rte_mtr_error_set(error, EINVAL,
18223 RTE_MTR_ERROR_TYPE_METER_POLICY,
18224 NULL, "policy RSS attr conflict");
18225 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18227 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18228 if (!def_green && !def_yellow &&
18229 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18230 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18231 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18232 return -rte_mtr_error_set(error, EINVAL,
18233 RTE_MTR_ERROR_TYPE_METER_POLICY,
18234 NULL, "policy domains conflict");
18236 * At least one color policy is listed in the actions, the domains
18237 * to be supported should be the intersection.
18239 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18240 domain_color[RTE_COLOR_YELLOW];
18245 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18247 struct mlx5_priv *priv = dev->data->dev_private;
18250 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18251 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18256 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18257 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18261 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18262 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18270 * Discover the number of available flow priorities
18271 * by trying to create a flow with the highest priority value
18272 * for each possible number.
18277 * List of possible number of available priorities.
18278 * @param[in] vprio_n
18279 * Size of @p vprio array.
18281 * On success, number of available flow priorities.
18282 * On failure, a negative errno-style code and rte_errno is set.
18285 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18286 const uint16_t *vprio, int vprio_n)
18288 struct mlx5_priv *priv = dev->data->dev_private;
18289 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18290 struct rte_flow_item_eth eth;
18291 struct rte_flow_item item = {
18292 .type = RTE_FLOW_ITEM_TYPE_ETH,
18296 struct mlx5_flow_dv_matcher matcher = {
18298 .size = sizeof(matcher.mask.buf),
18301 union mlx5_flow_tbl_key tbl_key;
18302 struct mlx5_flow flow;
18304 struct rte_flow_error error;
18306 int i, err, ret = -ENOTSUP;
18309 * Prepare a flow with a catch-all pattern and a drop action.
18310 * Use drop queue, because shared drop action may be unavailable.
18312 action = priv->drop_queue.hrxq->action;
18313 if (action == NULL) {
18314 DRV_LOG(ERR, "Priority discovery requires a drop action");
18315 rte_errno = ENOTSUP;
18318 memset(&flow, 0, sizeof(flow));
18319 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18320 if (flow.handle == NULL) {
18321 DRV_LOG(ERR, "Cannot create flow handle");
18322 rte_errno = ENOMEM;
18325 flow.ingress = true;
18326 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18327 flow.dv.actions[0] = action;
18328 flow.dv.actions_n = 1;
18329 memset(ð, 0, sizeof(eth));
18330 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18331 &item, /* inner */ false, /* group */ 0);
18332 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18333 for (i = 0; i < vprio_n; i++) {
18334 /* Configure the next proposed maximum priority. */
18335 matcher.priority = vprio[i] - 1;
18336 memset(&tbl_key, 0, sizeof(tbl_key));
18337 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18342 /* This action is pure SW and must always succeed. */
18343 DRV_LOG(ERR, "Cannot register matcher");
18347 /* Try to apply the flow to HW. */
18348 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18349 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18350 err = mlx5_flow_os_create_flow
18351 (flow.handle->dvh.matcher->matcher_object,
18352 (void *)&flow.dv.value, flow.dv.actions_n,
18353 flow.dv.actions, &flow.handle->drv_flow);
18355 claim_zero(mlx5_flow_os_destroy_flow
18356 (flow.handle->drv_flow));
18357 flow.handle->drv_flow = NULL;
18359 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18364 mlx5_ipool_free(pool, flow.handle_idx);
18365 /* Set rte_errno if no expected priority value matched. */
18371 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18372 .validate = flow_dv_validate,
18373 .prepare = flow_dv_prepare,
18374 .translate = flow_dv_translate,
18375 .apply = flow_dv_apply,
18376 .remove = flow_dv_remove,
18377 .destroy = flow_dv_destroy,
18378 .query = flow_dv_query,
18379 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18380 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18381 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18382 .create_meter = flow_dv_mtr_alloc,
18383 .free_meter = flow_dv_aso_mtr_release_to_pool,
18384 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18385 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18386 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18387 .create_policy_rules = flow_dv_create_policy_rules,
18388 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18389 .create_def_policy = flow_dv_create_def_policy,
18390 .destroy_def_policy = flow_dv_destroy_def_policy,
18391 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18392 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18393 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18394 .counter_alloc = flow_dv_counter_allocate,
18395 .counter_free = flow_dv_counter_free,
18396 .counter_query = flow_dv_counter_query,
18397 .get_aged_flows = flow_dv_get_aged_flows,
18398 .action_validate = flow_dv_action_validate,
18399 .action_create = flow_dv_action_create,
18400 .action_destroy = flow_dv_action_destroy,
18401 .action_update = flow_dv_action_update,
18402 .action_query = flow_dv_action_query,
18403 .sync_domain = flow_dv_sync_domain,
18404 .discover_priorities = flow_dv_discover_priorities,
18405 .item_create = flow_dv_item_create,
18406 .item_release = flow_dv_item_release,
18409 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */