1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
78 struct mlx5_flow_tbl_resource *tbl);
81 * Initialize flow attributes structure according to flow items' types.
83 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
84 * mode. For tunnel mode, the items to be modified are the outermost ones.
87 * Pointer to item specification.
89 * Pointer to flow attributes structure.
91 * Pointer to the sub flow.
92 * @param[in] tunnel_decap
93 * Whether action is after tunnel decapsulation.
96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
97 struct mlx5_flow *dev_flow, bool tunnel_decap)
99 uint64_t layers = dev_flow->handle->layers;
102 * If layers is already initialized, it means this dev_flow is the
103 * suffix flow, the layers flags is set by the prefix flow. Need to
104 * use the layer flags from prefix flow as the suffix flow may not
105 * have the user defined items as the flow is split.
108 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
112 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
114 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
119 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
120 uint8_t next_protocol = 0xff;
121 switch (item->type) {
122 case RTE_FLOW_ITEM_TYPE_GRE:
123 case RTE_FLOW_ITEM_TYPE_NVGRE:
124 case RTE_FLOW_ITEM_TYPE_VXLAN:
125 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
126 case RTE_FLOW_ITEM_TYPE_GENEVE:
127 case RTE_FLOW_ITEM_TYPE_MPLS:
131 case RTE_FLOW_ITEM_TYPE_IPV4:
134 if (item->mask != NULL &&
135 ((const struct rte_flow_item_ipv4 *)
136 item->mask)->hdr.next_proto_id)
138 ((const struct rte_flow_item_ipv4 *)
139 (item->spec))->hdr.next_proto_id &
140 ((const struct rte_flow_item_ipv4 *)
141 (item->mask))->hdr.next_proto_id;
142 if ((next_protocol == IPPROTO_IPIP ||
143 next_protocol == IPPROTO_IPV6) && tunnel_decap)
146 case RTE_FLOW_ITEM_TYPE_IPV6:
149 if (item->mask != NULL &&
150 ((const struct rte_flow_item_ipv6 *)
151 item->mask)->hdr.proto)
153 ((const struct rte_flow_item_ipv6 *)
154 (item->spec))->hdr.proto &
155 ((const struct rte_flow_item_ipv6 *)
156 (item->mask))->hdr.proto;
157 if ((next_protocol == IPPROTO_IPIP ||
158 next_protocol == IPPROTO_IPV6) && tunnel_decap)
161 case RTE_FLOW_ITEM_TYPE_UDP:
165 case RTE_FLOW_ITEM_TYPE_TCP:
177 * Convert rte_mtr_color to mlx5 color.
186 rte_col_2_mlx5_col(enum rte_color rcol)
189 case RTE_COLOR_GREEN:
190 return MLX5_FLOW_COLOR_GREEN;
191 case RTE_COLOR_YELLOW:
192 return MLX5_FLOW_COLOR_YELLOW;
194 return MLX5_FLOW_COLOR_RED;
198 return MLX5_FLOW_COLOR_UNDEFINED;
201 struct field_modify_info {
202 uint32_t size; /* Size of field in protocol header, in bytes. */
203 uint32_t offset; /* Offset of field in protocol header, in bytes. */
204 enum mlx5_modification_field id;
207 struct field_modify_info modify_eth[] = {
208 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
209 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
210 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
211 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
215 struct field_modify_info modify_vlan_out_first_vid[] = {
216 /* Size in bits !!! */
217 {12, 0, MLX5_MODI_OUT_FIRST_VID},
221 struct field_modify_info modify_ipv4[] = {
222 {1, 1, MLX5_MODI_OUT_IP_DSCP},
223 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
224 {4, 12, MLX5_MODI_OUT_SIPV4},
225 {4, 16, MLX5_MODI_OUT_DIPV4},
229 struct field_modify_info modify_ipv6[] = {
230 {1, 0, MLX5_MODI_OUT_IP_DSCP},
231 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
232 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
233 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
234 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
235 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
236 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
237 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
238 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
239 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
243 struct field_modify_info modify_udp[] = {
244 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
245 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
249 struct field_modify_info modify_tcp[] = {
250 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
251 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
252 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
253 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
259 uint8_t next_protocol, uint64_t *item_flags,
262 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
263 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
264 if (next_protocol == IPPROTO_IPIP) {
265 *item_flags |= MLX5_FLOW_LAYER_IPIP;
268 if (next_protocol == IPPROTO_IPV6) {
269 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
275 * Acquire the synchronizing object to protect multithreaded access
276 * to shared dv context. Lock occurs only if context is actually
277 * shared, i.e. we have multiport IB device and representors are
281 * Pointer to the rte_eth_dev structure.
284 flow_dv_shared_lock(struct rte_eth_dev *dev)
286 struct mlx5_priv *priv = dev->data->dev_private;
287 struct mlx5_ibv_shared *sh = priv->sh;
289 if (sh->dv_refcnt > 1) {
292 ret = pthread_mutex_lock(&sh->dv_mutex);
299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
301 struct mlx5_priv *priv = dev->data->dev_private;
302 struct mlx5_ibv_shared *sh = priv->sh;
304 if (sh->dv_refcnt > 1) {
307 ret = pthread_mutex_unlock(&sh->dv_mutex);
313 /* Update VLAN's VID/PCP based on input rte_flow_action.
316 * Pointer to struct rte_flow_action.
318 * Pointer to struct rte_vlan_hdr.
321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
322 struct rte_vlan_hdr *vlan)
325 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
327 ((const struct rte_flow_action_of_set_vlan_pcp *)
328 action->conf)->vlan_pcp;
329 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
330 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
331 vlan->vlan_tci |= vlan_tci;
332 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
333 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
334 vlan->vlan_tci |= rte_be_to_cpu_16
335 (((const struct rte_flow_action_of_set_vlan_vid *)
336 action->conf)->vlan_vid);
341 * Fetch 1, 2, 3 or 4 byte field from the byte array
342 * and return as unsigned integer in host-endian format.
345 * Pointer to data array.
347 * Size of field to extract.
350 * converted field in host endian format.
352 static inline uint32_t
353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
362 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = (ret << 8) | *(data + sizeof(uint16_t));
369 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
380 * Convert modify-header action to DV specification.
382 * Data length of each action is determined by provided field description
383 * and the item mask. Data bit offset and width of each action is determined
384 * by provided item mask.
387 * Pointer to item specification.
389 * Pointer to field modification information.
390 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
394 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
395 * Negative offset value sets the same offset as source offset.
396 * size field is ignored, value is taken from source field.
397 * @param[in,out] resource
398 * Pointer to the modify-header resource.
400 * Type of modification.
402 * Pointer to the error structure.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 flow_dv_convert_modify_action(struct rte_flow_item *item,
409 struct field_modify_info *field,
410 struct field_modify_info *dcopy,
411 struct mlx5_flow_dv_modify_hdr_resource *resource,
412 uint32_t type, struct rte_flow_error *error)
414 uint32_t i = resource->actions_num;
415 struct mlx5_modification_cmd *actions = resource->actions;
418 * The item and mask are provided in big-endian format.
419 * The fields should be presented as in big-endian format either.
420 * Mask must be always present, it defines the actual field width.
422 MLX5_ASSERT(item->mask);
423 MLX5_ASSERT(field->size);
430 if (i >= MLX5_MAX_MODIFY_NUM)
431 return rte_flow_error_set(error, EINVAL,
432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
433 "too many items to modify");
434 /* Fetch variable byte size mask from the array. */
435 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
436 field->offset, field->size);
441 /* Deduce actual data width in bits from mask value. */
442 off_b = rte_bsf32(mask);
443 size_b = sizeof(uint32_t) * CHAR_BIT -
444 off_b - __builtin_clz(mask);
446 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
447 actions[i] = (struct mlx5_modification_cmd) {
453 /* Convert entire record to expected big-endian format. */
454 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
455 if (type == MLX5_MODIFICATION_TYPE_COPY) {
457 actions[i].dst_field = dcopy->id;
458 actions[i].dst_offset =
459 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
460 /* Convert entire record to big-endian format. */
461 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
463 MLX5_ASSERT(item->spec);
464 data = flow_dv_fetch_field((const uint8_t *)item->spec +
465 field->offset, field->size);
466 /* Shift out the trailing masked bits from data. */
467 data = (data & mask) >> off_b;
468 actions[i].data1 = rte_cpu_to_be_32(data);
472 } while (field->size);
473 if (resource->actions_num == i)
474 return rte_flow_error_set(error, EINVAL,
475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
476 "invalid modification flow item");
477 resource->actions_num = i;
482 * Convert modify-header set IPv4 address action to DV specification.
484 * @param[in,out] resource
485 * Pointer to the modify-header resource.
487 * Pointer to action specification.
489 * Pointer to the error structure.
492 * 0 on success, a negative errno value otherwise and rte_errno is set.
495 flow_dv_convert_action_modify_ipv4
496 (struct mlx5_flow_dv_modify_hdr_resource *resource,
497 const struct rte_flow_action *action,
498 struct rte_flow_error *error)
500 const struct rte_flow_action_set_ipv4 *conf =
501 (const struct rte_flow_action_set_ipv4 *)(action->conf);
502 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
503 struct rte_flow_item_ipv4 ipv4;
504 struct rte_flow_item_ipv4 ipv4_mask;
506 memset(&ipv4, 0, sizeof(ipv4));
507 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
508 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
509 ipv4.hdr.src_addr = conf->ipv4_addr;
510 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
512 ipv4.hdr.dst_addr = conf->ipv4_addr;
513 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
516 item.mask = &ipv4_mask;
517 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
518 MLX5_MODIFICATION_TYPE_SET, error);
522 * Convert modify-header set IPv6 address action to DV specification.
524 * @param[in,out] resource
525 * Pointer to the modify-header resource.
527 * Pointer to action specification.
529 * Pointer to the error structure.
532 * 0 on success, a negative errno value otherwise and rte_errno is set.
535 flow_dv_convert_action_modify_ipv6
536 (struct mlx5_flow_dv_modify_hdr_resource *resource,
537 const struct rte_flow_action *action,
538 struct rte_flow_error *error)
540 const struct rte_flow_action_set_ipv6 *conf =
541 (const struct rte_flow_action_set_ipv6 *)(action->conf);
542 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
543 struct rte_flow_item_ipv6 ipv6;
544 struct rte_flow_item_ipv6 ipv6_mask;
546 memset(&ipv6, 0, sizeof(ipv6));
547 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
548 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
549 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6_mask.hdr.src_addr,
552 &rte_flow_item_ipv6_mask.hdr.src_addr,
553 sizeof(ipv6.hdr.src_addr));
555 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
556 sizeof(ipv6.hdr.dst_addr));
557 memcpy(&ipv6_mask.hdr.dst_addr,
558 &rte_flow_item_ipv6_mask.hdr.dst_addr,
559 sizeof(ipv6.hdr.dst_addr));
562 item.mask = &ipv6_mask;
563 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
564 MLX5_MODIFICATION_TYPE_SET, error);
568 * Convert modify-header set MAC address action to DV specification.
570 * @param[in,out] resource
571 * Pointer to the modify-header resource.
573 * Pointer to action specification.
575 * Pointer to the error structure.
578 * 0 on success, a negative errno value otherwise and rte_errno is set.
581 flow_dv_convert_action_modify_mac
582 (struct mlx5_flow_dv_modify_hdr_resource *resource,
583 const struct rte_flow_action *action,
584 struct rte_flow_error *error)
586 const struct rte_flow_action_set_mac *conf =
587 (const struct rte_flow_action_set_mac *)(action->conf);
588 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
589 struct rte_flow_item_eth eth;
590 struct rte_flow_item_eth eth_mask;
592 memset(ð, 0, sizeof(eth));
593 memset(ð_mask, 0, sizeof(eth_mask));
594 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
595 memcpy(ð.src.addr_bytes, &conf->mac_addr,
596 sizeof(eth.src.addr_bytes));
597 memcpy(ð_mask.src.addr_bytes,
598 &rte_flow_item_eth_mask.src.addr_bytes,
599 sizeof(eth_mask.src.addr_bytes));
601 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
602 sizeof(eth.dst.addr_bytes));
603 memcpy(ð_mask.dst.addr_bytes,
604 &rte_flow_item_eth_mask.dst.addr_bytes,
605 sizeof(eth_mask.dst.addr_bytes));
608 item.mask = ð_mask;
609 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
610 MLX5_MODIFICATION_TYPE_SET, error);
614 * Convert modify-header set VLAN VID action to DV specification.
616 * @param[in,out] resource
617 * Pointer to the modify-header resource.
619 * Pointer to action specification.
621 * Pointer to the error structure.
624 * 0 on success, a negative errno value otherwise and rte_errno is set.
627 flow_dv_convert_action_modify_vlan_vid
628 (struct mlx5_flow_dv_modify_hdr_resource *resource,
629 const struct rte_flow_action *action,
630 struct rte_flow_error *error)
632 const struct rte_flow_action_of_set_vlan_vid *conf =
633 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
634 int i = resource->actions_num;
635 struct mlx5_modification_cmd *actions = resource->actions;
636 struct field_modify_info *field = modify_vlan_out_first_vid;
638 if (i >= MLX5_MAX_MODIFY_NUM)
639 return rte_flow_error_set(error, EINVAL,
640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
641 "too many items to modify");
642 actions[i] = (struct mlx5_modification_cmd) {
643 .action_type = MLX5_MODIFICATION_TYPE_SET,
645 .length = field->size,
646 .offset = field->offset,
648 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
649 actions[i].data1 = conf->vlan_vid;
650 actions[i].data1 = actions[i].data1 << 16;
651 resource->actions_num = ++i;
656 * Convert modify-header set TP action to DV specification.
658 * @param[in,out] resource
659 * Pointer to the modify-header resource.
661 * Pointer to action specification.
663 * Pointer to rte_flow_item objects list.
665 * Pointer to flow attributes structure.
666 * @param[in] dev_flow
667 * Pointer to the sub flow.
668 * @param[in] tunnel_decap
669 * Whether action is after tunnel decapsulation.
671 * Pointer to the error structure.
674 * 0 on success, a negative errno value otherwise and rte_errno is set.
677 flow_dv_convert_action_modify_tp
678 (struct mlx5_flow_dv_modify_hdr_resource *resource,
679 const struct rte_flow_action *action,
680 const struct rte_flow_item *items,
681 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
682 bool tunnel_decap, struct rte_flow_error *error)
684 const struct rte_flow_action_set_tp *conf =
685 (const struct rte_flow_action_set_tp *)(action->conf);
686 struct rte_flow_item item;
687 struct rte_flow_item_udp udp;
688 struct rte_flow_item_udp udp_mask;
689 struct rte_flow_item_tcp tcp;
690 struct rte_flow_item_tcp tcp_mask;
691 struct field_modify_info *field;
694 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
696 memset(&udp, 0, sizeof(udp));
697 memset(&udp_mask, 0, sizeof(udp_mask));
698 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
699 udp.hdr.src_port = conf->port;
700 udp_mask.hdr.src_port =
701 rte_flow_item_udp_mask.hdr.src_port;
703 udp.hdr.dst_port = conf->port;
704 udp_mask.hdr.dst_port =
705 rte_flow_item_udp_mask.hdr.dst_port;
707 item.type = RTE_FLOW_ITEM_TYPE_UDP;
709 item.mask = &udp_mask;
712 MLX5_ASSERT(attr->tcp);
713 memset(&tcp, 0, sizeof(tcp));
714 memset(&tcp_mask, 0, sizeof(tcp_mask));
715 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
716 tcp.hdr.src_port = conf->port;
717 tcp_mask.hdr.src_port =
718 rte_flow_item_tcp_mask.hdr.src_port;
720 tcp.hdr.dst_port = conf->port;
721 tcp_mask.hdr.dst_port =
722 rte_flow_item_tcp_mask.hdr.dst_port;
724 item.type = RTE_FLOW_ITEM_TYPE_TCP;
726 item.mask = &tcp_mask;
729 return flow_dv_convert_modify_action(&item, field, NULL, resource,
730 MLX5_MODIFICATION_TYPE_SET, error);
734 * Convert modify-header set TTL action to DV specification.
736 * @param[in,out] resource
737 * Pointer to the modify-header resource.
739 * Pointer to action specification.
741 * Pointer to rte_flow_item objects list.
743 * Pointer to flow attributes structure.
744 * @param[in] dev_flow
745 * Pointer to the sub flow.
746 * @param[in] tunnel_decap
747 * Whether action is after tunnel decapsulation.
749 * Pointer to the error structure.
752 * 0 on success, a negative errno value otherwise and rte_errno is set.
755 flow_dv_convert_action_modify_ttl
756 (struct mlx5_flow_dv_modify_hdr_resource *resource,
757 const struct rte_flow_action *action,
758 const struct rte_flow_item *items,
759 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
760 bool tunnel_decap, struct rte_flow_error *error)
762 const struct rte_flow_action_set_ttl *conf =
763 (const struct rte_flow_action_set_ttl *)(action->conf);
764 struct rte_flow_item item;
765 struct rte_flow_item_ipv4 ipv4;
766 struct rte_flow_item_ipv4 ipv4_mask;
767 struct rte_flow_item_ipv6 ipv6;
768 struct rte_flow_item_ipv6 ipv6_mask;
769 struct field_modify_info *field;
772 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
774 memset(&ipv4, 0, sizeof(ipv4));
775 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
776 ipv4.hdr.time_to_live = conf->ttl_value;
777 ipv4_mask.hdr.time_to_live = 0xFF;
778 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
780 item.mask = &ipv4_mask;
783 MLX5_ASSERT(attr->ipv6);
784 memset(&ipv6, 0, sizeof(ipv6));
785 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
786 ipv6.hdr.hop_limits = conf->ttl_value;
787 ipv6_mask.hdr.hop_limits = 0xFF;
788 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
790 item.mask = &ipv6_mask;
793 return flow_dv_convert_modify_action(&item, field, NULL, resource,
794 MLX5_MODIFICATION_TYPE_SET, error);
798 * Convert modify-header decrement TTL action to DV specification.
800 * @param[in,out] resource
801 * Pointer to the modify-header resource.
803 * Pointer to action specification.
805 * Pointer to rte_flow_item objects list.
807 * Pointer to flow attributes structure.
808 * @param[in] dev_flow
809 * Pointer to the sub flow.
810 * @param[in] tunnel_decap
811 * Whether action is after tunnel decapsulation.
813 * Pointer to the error structure.
816 * 0 on success, a negative errno value otherwise and rte_errno is set.
819 flow_dv_convert_action_modify_dec_ttl
820 (struct mlx5_flow_dv_modify_hdr_resource *resource,
821 const struct rte_flow_item *items,
822 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
823 bool tunnel_decap, struct rte_flow_error *error)
825 struct rte_flow_item item;
826 struct rte_flow_item_ipv4 ipv4;
827 struct rte_flow_item_ipv4 ipv4_mask;
828 struct rte_flow_item_ipv6 ipv6;
829 struct rte_flow_item_ipv6 ipv6_mask;
830 struct field_modify_info *field;
833 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
835 memset(&ipv4, 0, sizeof(ipv4));
836 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
837 ipv4.hdr.time_to_live = 0xFF;
838 ipv4_mask.hdr.time_to_live = 0xFF;
839 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
841 item.mask = &ipv4_mask;
844 MLX5_ASSERT(attr->ipv6);
845 memset(&ipv6, 0, sizeof(ipv6));
846 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
847 ipv6.hdr.hop_limits = 0xFF;
848 ipv6_mask.hdr.hop_limits = 0xFF;
849 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
851 item.mask = &ipv6_mask;
854 return flow_dv_convert_modify_action(&item, field, NULL, resource,
855 MLX5_MODIFICATION_TYPE_ADD, error);
859 * Convert modify-header increment/decrement TCP Sequence number
860 * to DV specification.
862 * @param[in,out] resource
863 * Pointer to the modify-header resource.
865 * Pointer to action specification.
867 * Pointer to the error structure.
870 * 0 on success, a negative errno value otherwise and rte_errno is set.
873 flow_dv_convert_action_modify_tcp_seq
874 (struct mlx5_flow_dv_modify_hdr_resource *resource,
875 const struct rte_flow_action *action,
876 struct rte_flow_error *error)
878 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
879 uint64_t value = rte_be_to_cpu_32(*conf);
880 struct rte_flow_item item;
881 struct rte_flow_item_tcp tcp;
882 struct rte_flow_item_tcp tcp_mask;
884 memset(&tcp, 0, sizeof(tcp));
885 memset(&tcp_mask, 0, sizeof(tcp_mask));
886 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
888 * The HW has no decrement operation, only increment operation.
889 * To simulate decrement X from Y using increment operation
890 * we need to add UINT32_MAX X times to Y.
891 * Each adding of UINT32_MAX decrements Y by 1.
894 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
895 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
896 item.type = RTE_FLOW_ITEM_TYPE_TCP;
898 item.mask = &tcp_mask;
899 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
900 MLX5_MODIFICATION_TYPE_ADD, error);
904 * Convert modify-header increment/decrement TCP Acknowledgment number
905 * to DV specification.
907 * @param[in,out] resource
908 * Pointer to the modify-header resource.
910 * Pointer to action specification.
912 * Pointer to the error structure.
915 * 0 on success, a negative errno value otherwise and rte_errno is set.
918 flow_dv_convert_action_modify_tcp_ack
919 (struct mlx5_flow_dv_modify_hdr_resource *resource,
920 const struct rte_flow_action *action,
921 struct rte_flow_error *error)
923 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
924 uint64_t value = rte_be_to_cpu_32(*conf);
925 struct rte_flow_item item;
926 struct rte_flow_item_tcp tcp;
927 struct rte_flow_item_tcp tcp_mask;
929 memset(&tcp, 0, sizeof(tcp));
930 memset(&tcp_mask, 0, sizeof(tcp_mask));
931 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
933 * The HW has no decrement operation, only increment operation.
934 * To simulate decrement X from Y using increment operation
935 * we need to add UINT32_MAX X times to Y.
936 * Each adding of UINT32_MAX decrements Y by 1.
939 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
940 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
941 item.type = RTE_FLOW_ITEM_TYPE_TCP;
943 item.mask = &tcp_mask;
944 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
945 MLX5_MODIFICATION_TYPE_ADD, error);
948 static enum mlx5_modification_field reg_to_field[] = {
949 [REG_NONE] = MLX5_MODI_OUT_NONE,
950 [REG_A] = MLX5_MODI_META_DATA_REG_A,
951 [REG_B] = MLX5_MODI_META_DATA_REG_B,
952 [REG_C_0] = MLX5_MODI_META_REG_C_0,
953 [REG_C_1] = MLX5_MODI_META_REG_C_1,
954 [REG_C_2] = MLX5_MODI_META_REG_C_2,
955 [REG_C_3] = MLX5_MODI_META_REG_C_3,
956 [REG_C_4] = MLX5_MODI_META_REG_C_4,
957 [REG_C_5] = MLX5_MODI_META_REG_C_5,
958 [REG_C_6] = MLX5_MODI_META_REG_C_6,
959 [REG_C_7] = MLX5_MODI_META_REG_C_7,
963 * Convert register set to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_set_reg
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
982 struct mlx5_modification_cmd *actions = resource->actions;
983 uint32_t i = resource->actions_num;
985 if (i >= MLX5_MAX_MODIFY_NUM)
986 return rte_flow_error_set(error, EINVAL,
987 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
988 "too many items to modify");
989 MLX5_ASSERT(conf->id != REG_NONE);
990 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
991 actions[i] = (struct mlx5_modification_cmd) {
992 .action_type = MLX5_MODIFICATION_TYPE_SET,
993 .field = reg_to_field[conf->id],
995 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
996 actions[i].data1 = rte_cpu_to_be_32(conf->data);
998 resource->actions_num = i;
1003 * Convert SET_TAG action to DV specification.
1006 * Pointer to the rte_eth_dev structure.
1007 * @param[in,out] resource
1008 * Pointer to the modify-header resource.
1010 * Pointer to action specification.
1012 * Pointer to the error structure.
1015 * 0 on success, a negative errno value otherwise and rte_errno is set.
1018 flow_dv_convert_action_set_tag
1019 (struct rte_eth_dev *dev,
1020 struct mlx5_flow_dv_modify_hdr_resource *resource,
1021 const struct rte_flow_action_set_tag *conf,
1022 struct rte_flow_error *error)
1024 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026 struct rte_flow_item item = {
1030 struct field_modify_info reg_c_x[] = {
1033 enum mlx5_modification_field reg_type;
1036 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1039 MLX5_ASSERT(ret != REG_NONE);
1040 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041 reg_type = reg_to_field[ret];
1042 MLX5_ASSERT(reg_type > 0);
1043 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045 MLX5_MODIFICATION_TYPE_SET, error);
1049 * Convert internal COPY_REG action to DV specification.
1052 * Pointer to the rte_eth_dev structure.
1053 * @param[in,out] res
1054 * Pointer to the modify-header resource.
1056 * Pointer to action specification.
1058 * Pointer to the error structure.
1061 * 0 on success, a negative errno value otherwise and rte_errno is set.
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065 struct mlx5_flow_dv_modify_hdr_resource *res,
1066 const struct rte_flow_action *action,
1067 struct rte_flow_error *error)
1069 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071 struct rte_flow_item item = {
1075 struct field_modify_info reg_src[] = {
1076 {4, 0, reg_to_field[conf->src]},
1079 struct field_modify_info reg_dst = {
1081 .id = reg_to_field[conf->dst],
1083 /* Adjust reg_c[0] usage according to reported mask. */
1084 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085 struct mlx5_priv *priv = dev->data->dev_private;
1086 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088 MLX5_ASSERT(reg_c0);
1089 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090 if (conf->dst == REG_C_0) {
1091 /* Copy to reg_c[0], within mask only. */
1092 reg_dst.offset = rte_bsf32(reg_c0);
1094 * Mask is ignoring the enianness, because
1095 * there is no conversion in datapath.
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098 /* Copy from destination lower bits to reg_c[0]. */
1099 mask = reg_c0 >> reg_dst.offset;
1101 /* Copy from destination upper bits to reg_c[0]. */
1102 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103 rte_fls_u32(reg_c0));
1106 mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108 /* Copy from reg_c[0] to destination lower bits. */
1111 /* Copy from reg_c[0] to destination upper bits. */
1112 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113 (rte_fls_u32(reg_c0) -
1118 return flow_dv_convert_modify_action(&item,
1119 reg_src, ®_dst, res,
1120 MLX5_MODIFICATION_TYPE_COPY,
1125 * Convert MARK action to DV specification. This routine is used
1126 * in extensive metadata only and requires metadata register to be
1127 * handled. In legacy mode hardware tag resource is engaged.
1130 * Pointer to the rte_eth_dev structure.
1132 * Pointer to MARK action specification.
1133 * @param[in,out] resource
1134 * Pointer to the modify-header resource.
1136 * Pointer to the error structure.
1139 * 0 on success, a negative errno value otherwise and rte_errno is set.
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143 const struct rte_flow_action_mark *conf,
1144 struct mlx5_flow_dv_modify_hdr_resource *resource,
1145 struct rte_flow_error *error)
1147 struct mlx5_priv *priv = dev->data->dev_private;
1148 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149 priv->sh->dv_mark_mask);
1150 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151 struct rte_flow_item item = {
1155 struct field_modify_info reg_c_x[] = {
1156 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1162 return rte_flow_error_set(error, EINVAL,
1163 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164 NULL, "zero mark action mask");
1165 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1168 MLX5_ASSERT(reg > 0);
1169 if (reg == REG_C_0) {
1170 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175 mask = rte_cpu_to_be_32(mask << shl_c0);
1177 reg_c_x[0].id = reg_to_field[reg];
1178 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179 MLX5_MODIFICATION_TYPE_SET, error);
1183 * Get metadata register index for specified steering domain.
1186 * Pointer to the rte_eth_dev structure.
1188 * Attributes of flow to determine steering domain.
1190 * Pointer to the error structure.
1193 * positive index on success, a negative errno value otherwise
1194 * and rte_errno is set.
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198 const struct rte_flow_attr *attr,
1199 struct rte_flow_error *error)
1202 mlx5_flow_get_reg_id(dev, attr->transfer ?
1206 MLX5_METADATA_RX, 0, error);
1208 return rte_flow_error_set(error,
1209 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210 NULL, "unavailable "
1211 "metadata register");
1216 * Convert SET_META action to DV specification.
1219 * Pointer to the rte_eth_dev structure.
1220 * @param[in,out] resource
1221 * Pointer to the modify-header resource.
1223 * Attributes of flow that includes this item.
1225 * Pointer to action specification.
1227 * Pointer to the error structure.
1230 * 0 on success, a negative errno value otherwise and rte_errno is set.
1233 flow_dv_convert_action_set_meta
1234 (struct rte_eth_dev *dev,
1235 struct mlx5_flow_dv_modify_hdr_resource *resource,
1236 const struct rte_flow_attr *attr,
1237 const struct rte_flow_action_set_meta *conf,
1238 struct rte_flow_error *error)
1240 uint32_t data = conf->data;
1241 uint32_t mask = conf->mask;
1242 struct rte_flow_item item = {
1246 struct field_modify_info reg_c_x[] = {
1249 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254 * In datapath code there is no endianness
1255 * coversions for perfromance reasons, all
1256 * pattern conversions are done in rte_flow.
1258 if (reg == REG_C_0) {
1259 struct mlx5_priv *priv = dev->data->dev_private;
1260 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1263 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265 shl_c0 = rte_bsf32(msk_c0);
1267 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1271 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274 /* The routine expects parameters in memory as big-endian ones. */
1275 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276 MLX5_MODIFICATION_TYPE_SET, error);
1280 * Convert modify-header set IPv4 DSCP action to DV specification.
1282 * @param[in,out] resource
1283 * Pointer to the modify-header resource.
1285 * Pointer to action specification.
1287 * Pointer to the error structure.
1290 * 0 on success, a negative errno value otherwise and rte_errno is set.
1293 flow_dv_convert_action_modify_ipv4_dscp
1294 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295 const struct rte_flow_action *action,
1296 struct rte_flow_error *error)
1298 const struct rte_flow_action_set_dscp *conf =
1299 (const struct rte_flow_action_set_dscp *)(action->conf);
1300 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301 struct rte_flow_item_ipv4 ipv4;
1302 struct rte_flow_item_ipv4 ipv4_mask;
1304 memset(&ipv4, 0, sizeof(ipv4));
1305 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306 ipv4.hdr.type_of_service = conf->dscp;
1307 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309 item.mask = &ipv4_mask;
1310 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311 MLX5_MODIFICATION_TYPE_SET, error);
1315 * Convert modify-header set IPv6 DSCP action to DV specification.
1317 * @param[in,out] resource
1318 * Pointer to the modify-header resource.
1320 * Pointer to action specification.
1322 * Pointer to the error structure.
1325 * 0 on success, a negative errno value otherwise and rte_errno is set.
1328 flow_dv_convert_action_modify_ipv6_dscp
1329 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330 const struct rte_flow_action *action,
1331 struct rte_flow_error *error)
1333 const struct rte_flow_action_set_dscp *conf =
1334 (const struct rte_flow_action_set_dscp *)(action->conf);
1335 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336 struct rte_flow_item_ipv6 ipv6;
1337 struct rte_flow_item_ipv6 ipv6_mask;
1339 memset(&ipv6, 0, sizeof(ipv6));
1340 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343 * rdma-core only accept the DSCP bits byte aligned start from
1344 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345 * bits in IPv6 case as rdma-core requires byte aligned value.
1347 ipv6.hdr.vtc_flow = conf->dscp;
1348 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350 item.mask = &ipv6_mask;
1351 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352 MLX5_MODIFICATION_TYPE_SET, error);
1356 * Validate MARK item.
1359 * Pointer to the rte_eth_dev structure.
1361 * Item specification.
1363 * Attributes of flow that includes this item.
1365 * Pointer to error structure.
1368 * 0 on success, a negative errno value otherwise and rte_errno is set.
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372 const struct rte_flow_item *item,
1373 const struct rte_flow_attr *attr __rte_unused,
1374 struct rte_flow_error *error)
1376 struct mlx5_priv *priv = dev->data->dev_private;
1377 struct mlx5_dev_config *config = &priv->config;
1378 const struct rte_flow_item_mark *spec = item->spec;
1379 const struct rte_flow_item_mark *mask = item->mask;
1380 const struct rte_flow_item_mark nic_mask = {
1381 .id = priv->sh->dv_mark_mask,
1385 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386 return rte_flow_error_set(error, ENOTSUP,
1387 RTE_FLOW_ERROR_TYPE_ITEM, item,
1388 "extended metadata feature"
1390 if (!mlx5_flow_ext_mreg_supported(dev))
1391 return rte_flow_error_set(error, ENOTSUP,
1392 RTE_FLOW_ERROR_TYPE_ITEM, item,
1393 "extended metadata register"
1394 " isn't supported");
1396 return rte_flow_error_set(error, ENOTSUP,
1397 RTE_FLOW_ERROR_TYPE_ITEM, item,
1398 "extended metadata register"
1399 " isn't available");
1400 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1404 return rte_flow_error_set(error, EINVAL,
1405 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407 "data cannot be empty");
1408 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409 return rte_flow_error_set(error, EINVAL,
1410 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412 "mark id exceeds the limit");
1416 return rte_flow_error_set(error, EINVAL,
1417 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418 "mask cannot be zero");
1420 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421 (const uint8_t *)&nic_mask,
1422 sizeof(struct rte_flow_item_mark),
1430 * Validate META item.
1433 * Pointer to the rte_eth_dev structure.
1435 * Item specification.
1437 * Attributes of flow that includes this item.
1439 * Pointer to error structure.
1442 * 0 on success, a negative errno value otherwise and rte_errno is set.
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446 const struct rte_flow_item *item,
1447 const struct rte_flow_attr *attr,
1448 struct rte_flow_error *error)
1450 struct mlx5_priv *priv = dev->data->dev_private;
1451 struct mlx5_dev_config *config = &priv->config;
1452 const struct rte_flow_item_meta *spec = item->spec;
1453 const struct rte_flow_item_meta *mask = item->mask;
1454 struct rte_flow_item_meta nic_mask = {
1461 return rte_flow_error_set(error, EINVAL,
1462 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464 "data cannot be empty");
1465 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466 if (!mlx5_flow_ext_mreg_supported(dev))
1467 return rte_flow_error_set(error, ENOTSUP,
1468 RTE_FLOW_ERROR_TYPE_ITEM, item,
1469 "extended metadata register"
1470 " isn't supported");
1471 reg = flow_dv_get_metadata_reg(dev, attr, error);
1475 return rte_flow_error_set(error, ENOTSUP,
1476 RTE_FLOW_ERROR_TYPE_ITEM, item,
1480 nic_mask.data = priv->sh->dv_meta_mask;
1483 mask = &rte_flow_item_meta_mask;
1485 return rte_flow_error_set(error, EINVAL,
1486 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487 "mask cannot be zero");
1489 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490 (const uint8_t *)&nic_mask,
1491 sizeof(struct rte_flow_item_meta),
1497 * Validate TAG item.
1500 * Pointer to the rte_eth_dev structure.
1502 * Item specification.
1504 * Attributes of flow that includes this item.
1506 * Pointer to error structure.
1509 * 0 on success, a negative errno value otherwise and rte_errno is set.
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513 const struct rte_flow_item *item,
1514 const struct rte_flow_attr *attr __rte_unused,
1515 struct rte_flow_error *error)
1517 const struct rte_flow_item_tag *spec = item->spec;
1518 const struct rte_flow_item_tag *mask = item->mask;
1519 const struct rte_flow_item_tag nic_mask = {
1520 .data = RTE_BE32(UINT32_MAX),
1525 if (!mlx5_flow_ext_mreg_supported(dev))
1526 return rte_flow_error_set(error, ENOTSUP,
1527 RTE_FLOW_ERROR_TYPE_ITEM, item,
1528 "extensive metadata register"
1529 " isn't supported");
1531 return rte_flow_error_set(error, EINVAL,
1532 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534 "data cannot be empty");
1536 mask = &rte_flow_item_tag_mask;
1538 return rte_flow_error_set(error, EINVAL,
1539 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540 "mask cannot be zero");
1542 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543 (const uint8_t *)&nic_mask,
1544 sizeof(struct rte_flow_item_tag),
1548 if (mask->index != 0xff)
1549 return rte_flow_error_set(error, EINVAL,
1550 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551 "partial mask for tag index"
1552 " is not supported");
1553 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1556 MLX5_ASSERT(ret != REG_NONE);
1561 * Validate vport item.
1564 * Pointer to the rte_eth_dev structure.
1566 * Item specification.
1568 * Attributes of flow that includes this item.
1569 * @param[in] item_flags
1570 * Bit-fields that holds the items detected until now.
1572 * Pointer to error structure.
1575 * 0 on success, a negative errno value otherwise and rte_errno is set.
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579 const struct rte_flow_item *item,
1580 const struct rte_flow_attr *attr,
1581 uint64_t item_flags,
1582 struct rte_flow_error *error)
1584 const struct rte_flow_item_port_id *spec = item->spec;
1585 const struct rte_flow_item_port_id *mask = item->mask;
1586 const struct rte_flow_item_port_id switch_mask = {
1589 struct mlx5_priv *esw_priv;
1590 struct mlx5_priv *dev_priv;
1593 if (!attr->transfer)
1594 return rte_flow_error_set(error, EINVAL,
1595 RTE_FLOW_ERROR_TYPE_ITEM,
1597 "match on port id is valid only"
1598 " when transfer flag is enabled");
1599 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600 return rte_flow_error_set(error, ENOTSUP,
1601 RTE_FLOW_ERROR_TYPE_ITEM, item,
1602 "multiple source ports are not"
1605 mask = &switch_mask;
1606 if (mask->id != 0xffffffff)
1607 return rte_flow_error_set(error, ENOTSUP,
1608 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610 "no support for partial mask on"
1612 ret = mlx5_flow_item_acceptable
1613 (item, (const uint8_t *)mask,
1614 (const uint8_t *)&rte_flow_item_port_id_mask,
1615 sizeof(struct rte_flow_item_port_id),
1621 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623 return rte_flow_error_set(error, rte_errno,
1624 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625 "failed to obtain E-Switch info for"
1627 dev_priv = mlx5_dev_to_eswitch_info(dev);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632 "failed to obtain E-Switch info");
1633 if (esw_priv->domain_id != dev_priv->domain_id)
1634 return rte_flow_error_set(error, EINVAL,
1635 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636 "cannot match on a port from a"
1637 " different E-Switch");
1642 * Validate GTP item.
1645 * Pointer to the rte_eth_dev structure.
1647 * Item specification.
1648 * @param[in] item_flags
1649 * Bit-fields that holds the items detected until now.
1651 * Pointer to error structure.
1654 * 0 on success, a negative errno value otherwise and rte_errno is set.
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658 const struct rte_flow_item *item,
1659 uint64_t item_flags,
1660 struct rte_flow_error *error)
1662 struct mlx5_priv *priv = dev->data->dev_private;
1663 const struct rte_flow_item_gtp *mask = item->mask;
1664 const struct rte_flow_item_gtp nic_mask = {
1666 .teid = RTE_BE32(0xffffffff),
1669 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "GTP support is not enabled");
1673 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674 return rte_flow_error_set(error, ENOTSUP,
1675 RTE_FLOW_ERROR_TYPE_ITEM, item,
1676 "multiple tunnel layers not"
1678 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679 return rte_flow_error_set(error, EINVAL,
1680 RTE_FLOW_ERROR_TYPE_ITEM, item,
1681 "no outer UDP layer found");
1683 mask = &rte_flow_item_gtp_mask;
1684 return mlx5_flow_item_acceptable
1685 (item, (const uint8_t *)mask,
1686 (const uint8_t *)&nic_mask,
1687 sizeof(struct rte_flow_item_gtp),
1692 * Validate the pop VLAN action.
1695 * Pointer to the rte_eth_dev structure.
1696 * @param[in] action_flags
1697 * Holds the actions detected until now.
1699 * Pointer to the pop vlan action.
1700 * @param[in] item_flags
1701 * The items found in this flow rule.
1703 * Pointer to flow attributes.
1705 * Pointer to error structure.
1708 * 0 on success, a negative errno value otherwise and rte_errno is set.
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712 uint64_t action_flags,
1713 const struct rte_flow_action *action,
1714 uint64_t item_flags,
1715 const struct rte_flow_attr *attr,
1716 struct rte_flow_error *error)
1718 const struct mlx5_priv *priv = dev->data->dev_private;
1722 if (!priv->sh->pop_vlan_action)
1723 return rte_flow_error_set(error, ENOTSUP,
1724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726 "pop vlan action is not supported");
1728 return rte_flow_error_set(error, ENOTSUP,
1729 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731 "pop vlan action not supported for "
1733 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734 return rte_flow_error_set(error, ENOTSUP,
1735 RTE_FLOW_ERROR_TYPE_ACTION, action,
1736 "no support for multiple VLAN "
1738 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739 return rte_flow_error_set(error, ENOTSUP,
1740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742 "cannot pop vlan without a "
1743 "match on (outer) vlan in the flow");
1744 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745 return rte_flow_error_set(error, EINVAL,
1746 RTE_FLOW_ERROR_TYPE_ACTION, action,
1747 "wrong action order, port_id should "
1748 "be after pop VLAN action");
1749 if (!attr->transfer && priv->representor)
1750 return rte_flow_error_set(error, ENOTSUP,
1751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752 "pop vlan action for VF representor "
1753 "not supported on NIC table");
1758 * Get VLAN default info from vlan match info.
1761 * the list of item specifications.
1763 * pointer VLAN info to fill to.
1766 * 0 on success, a negative errno value otherwise and rte_errno is set.
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770 struct rte_vlan_hdr *vlan)
1772 const struct rte_flow_item_vlan nic_mask = {
1773 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774 MLX5DV_FLOW_VLAN_VID_MASK),
1775 .inner_type = RTE_BE16(0xffff),
1780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781 int type = items->type;
1783 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1787 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789 const struct rte_flow_item_vlan *vlan_v = items->spec;
1793 /* Only full match values are accepted */
1794 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798 rte_be_to_cpu_16(vlan_v->tci &
1799 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805 rte_be_to_cpu_16(vlan_v->tci &
1806 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808 if (vlan_m->inner_type == nic_mask.inner_type)
1809 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810 vlan_m->inner_type);
1815 * Validate the push VLAN action.
1818 * Pointer to the rte_eth_dev structure.
1819 * @param[in] action_flags
1820 * Holds the actions detected until now.
1821 * @param[in] item_flags
1822 * The items found in this flow rule.
1824 * Pointer to the action structure.
1826 * Pointer to flow attributes
1828 * Pointer to error structure.
1831 * 0 on success, a negative errno value otherwise and rte_errno is set.
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835 uint64_t action_flags,
1836 const struct rte_flow_item_vlan *vlan_m,
1837 const struct rte_flow_action *action,
1838 const struct rte_flow_attr *attr,
1839 struct rte_flow_error *error)
1841 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842 const struct mlx5_priv *priv = dev->data->dev_private;
1844 if (!attr->transfer && attr->ingress)
1845 return rte_flow_error_set(error, ENOTSUP,
1846 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848 "push VLAN action not supported for "
1850 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "invalid vlan ethertype");
1855 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856 return rte_flow_error_set(error, ENOTSUP,
1857 RTE_FLOW_ERROR_TYPE_ACTION, action,
1858 "no support for multiple VLAN "
1860 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861 return rte_flow_error_set(error, EINVAL,
1862 RTE_FLOW_ERROR_TYPE_ACTION, action,
1863 "wrong action order, port_id should "
1864 "be after push VLAN");
1865 if (!attr->transfer && priv->representor)
1866 return rte_flow_error_set(error, ENOTSUP,
1867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868 "push vlan action for VF representor "
1869 "not supported on NIC table");
1871 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1872 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1873 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1874 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1875 !(mlx5_flow_find_action
1876 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1877 return rte_flow_error_set(error, EINVAL,
1878 RTE_FLOW_ERROR_TYPE_ACTION, action,
1879 "not full match mask on VLAN PCP and "
1880 "there is no of_set_vlan_pcp action, "
1881 "push VLAN action cannot figure out "
1884 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1885 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1886 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1887 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1888 !(mlx5_flow_find_action
1889 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1890 return rte_flow_error_set(error, EINVAL,
1891 RTE_FLOW_ERROR_TYPE_ACTION, action,
1892 "not full match mask on VLAN VID and "
1893 "there is no of_set_vlan_vid action, "
1894 "push VLAN action cannot figure out "
1901 * Validate the set VLAN PCP.
1903 * @param[in] action_flags
1904 * Holds the actions detected until now.
1905 * @param[in] actions
1906 * Pointer to the list of actions remaining in the flow rule.
1908 * Pointer to error structure.
1911 * 0 on success, a negative errno value otherwise and rte_errno is set.
1914 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1915 const struct rte_flow_action actions[],
1916 struct rte_flow_error *error)
1918 const struct rte_flow_action *action = actions;
1919 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1921 if (conf->vlan_pcp > 7)
1922 return rte_flow_error_set(error, EINVAL,
1923 RTE_FLOW_ERROR_TYPE_ACTION, action,
1924 "VLAN PCP value is too big");
1925 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1926 return rte_flow_error_set(error, ENOTSUP,
1927 RTE_FLOW_ERROR_TYPE_ACTION, action,
1928 "set VLAN PCP action must follow "
1929 "the push VLAN action");
1930 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1931 return rte_flow_error_set(error, ENOTSUP,
1932 RTE_FLOW_ERROR_TYPE_ACTION, action,
1933 "Multiple VLAN PCP modification are "
1935 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1936 return rte_flow_error_set(error, EINVAL,
1937 RTE_FLOW_ERROR_TYPE_ACTION, action,
1938 "wrong action order, port_id should "
1939 "be after set VLAN PCP");
1944 * Validate the set VLAN VID.
1946 * @param[in] item_flags
1947 * Holds the items detected in this rule.
1948 * @param[in] action_flags
1949 * Holds the actions detected until now.
1950 * @param[in] actions
1951 * Pointer to the list of actions remaining in the flow rule.
1953 * Pointer to error structure.
1956 * 0 on success, a negative errno value otherwise and rte_errno is set.
1959 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1960 uint64_t action_flags,
1961 const struct rte_flow_action actions[],
1962 struct rte_flow_error *error)
1964 const struct rte_flow_action *action = actions;
1965 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1967 if (conf->vlan_vid > RTE_BE16(0xFFE))
1968 return rte_flow_error_set(error, EINVAL,
1969 RTE_FLOW_ERROR_TYPE_ACTION, action,
1970 "VLAN VID value is too big");
1971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1972 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1973 return rte_flow_error_set(error, ENOTSUP,
1974 RTE_FLOW_ERROR_TYPE_ACTION, action,
1975 "set VLAN VID action must follow push"
1976 " VLAN action or match on VLAN item");
1977 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1978 return rte_flow_error_set(error, ENOTSUP,
1979 RTE_FLOW_ERROR_TYPE_ACTION, action,
1980 "Multiple VLAN VID modifications are "
1982 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ACTION, action,
1985 "wrong action order, port_id should "
1986 "be after set VLAN VID");
1991 * Validate the FLAG action.
1994 * Pointer to the rte_eth_dev structure.
1995 * @param[in] action_flags
1996 * Holds the actions detected until now.
1998 * Pointer to flow attributes
2000 * Pointer to error structure.
2003 * 0 on success, a negative errno value otherwise and rte_errno is set.
2006 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2007 uint64_t action_flags,
2008 const struct rte_flow_attr *attr,
2009 struct rte_flow_error *error)
2011 struct mlx5_priv *priv = dev->data->dev_private;
2012 struct mlx5_dev_config *config = &priv->config;
2015 /* Fall back if no extended metadata register support. */
2016 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2017 return mlx5_flow_validate_action_flag(action_flags, attr,
2019 /* Extensive metadata mode requires registers. */
2020 if (!mlx5_flow_ext_mreg_supported(dev))
2021 return rte_flow_error_set(error, ENOTSUP,
2022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2023 "no metadata registers "
2024 "to support flag action");
2025 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2028 "extended metadata register"
2029 " isn't available");
2030 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2033 MLX5_ASSERT(ret > 0);
2034 if (action_flags & MLX5_FLOW_ACTION_MARK)
2035 return rte_flow_error_set(error, EINVAL,
2036 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2037 "can't mark and flag in same flow");
2038 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2039 return rte_flow_error_set(error, EINVAL,
2040 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042 " actions in same flow");
2047 * Validate MARK action.
2050 * Pointer to the rte_eth_dev structure.
2052 * Pointer to action.
2053 * @param[in] action_flags
2054 * Holds the actions detected until now.
2056 * Pointer to flow attributes
2058 * Pointer to error structure.
2061 * 0 on success, a negative errno value otherwise and rte_errno is set.
2064 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2065 const struct rte_flow_action *action,
2066 uint64_t action_flags,
2067 const struct rte_flow_attr *attr,
2068 struct rte_flow_error *error)
2070 struct mlx5_priv *priv = dev->data->dev_private;
2071 struct mlx5_dev_config *config = &priv->config;
2072 const struct rte_flow_action_mark *mark = action->conf;
2075 /* Fall back if no extended metadata register support. */
2076 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2077 return mlx5_flow_validate_action_mark(action, action_flags,
2079 /* Extensive metadata mode requires registers. */
2080 if (!mlx5_flow_ext_mreg_supported(dev))
2081 return rte_flow_error_set(error, ENOTSUP,
2082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083 "no metadata registers "
2084 "to support mark action");
2085 if (!priv->sh->dv_mark_mask)
2086 return rte_flow_error_set(error, ENOTSUP,
2087 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2088 "extended metadata register"
2089 " isn't available");
2090 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2093 MLX5_ASSERT(ret > 0);
2095 return rte_flow_error_set(error, EINVAL,
2096 RTE_FLOW_ERROR_TYPE_ACTION, action,
2097 "configuration cannot be null");
2098 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2102 "mark id exceeds the limit");
2103 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2104 return rte_flow_error_set(error, EINVAL,
2105 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2106 "can't flag and mark in same flow");
2107 if (action_flags & MLX5_FLOW_ACTION_MARK)
2108 return rte_flow_error_set(error, EINVAL,
2109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2110 "can't have 2 mark actions in same"
2116 * Validate SET_META action.
2119 * Pointer to the rte_eth_dev structure.
2121 * Pointer to the action structure.
2122 * @param[in] action_flags
2123 * Holds the actions detected until now.
2125 * Pointer to flow attributes
2127 * Pointer to error structure.
2130 * 0 on success, a negative errno value otherwise and rte_errno is set.
2133 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2134 const struct rte_flow_action *action,
2135 uint64_t action_flags __rte_unused,
2136 const struct rte_flow_attr *attr,
2137 struct rte_flow_error *error)
2139 const struct rte_flow_action_set_meta *conf;
2140 uint32_t nic_mask = UINT32_MAX;
2143 if (!mlx5_flow_ext_mreg_supported(dev))
2144 return rte_flow_error_set(error, ENOTSUP,
2145 RTE_FLOW_ERROR_TYPE_ACTION, action,
2146 "extended metadata register"
2147 " isn't supported");
2148 reg = flow_dv_get_metadata_reg(dev, attr, error);
2151 if (reg != REG_A && reg != REG_B) {
2152 struct mlx5_priv *priv = dev->data->dev_private;
2154 nic_mask = priv->sh->dv_meta_mask;
2156 if (!(action->conf))
2157 return rte_flow_error_set(error, EINVAL,
2158 RTE_FLOW_ERROR_TYPE_ACTION, action,
2159 "configuration cannot be null");
2160 conf = (const struct rte_flow_action_set_meta *)action->conf;
2162 return rte_flow_error_set(error, EINVAL,
2163 RTE_FLOW_ERROR_TYPE_ACTION, action,
2164 "zero mask doesn't have any effect");
2165 if (conf->mask & ~nic_mask)
2166 return rte_flow_error_set(error, EINVAL,
2167 RTE_FLOW_ERROR_TYPE_ACTION, action,
2168 "meta data must be within reg C0");
2173 * Validate SET_TAG action.
2176 * Pointer to the rte_eth_dev structure.
2178 * Pointer to the action structure.
2179 * @param[in] action_flags
2180 * Holds the actions detected until now.
2182 * Pointer to flow attributes
2184 * Pointer to error structure.
2187 * 0 on success, a negative errno value otherwise and rte_errno is set.
2190 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2191 const struct rte_flow_action *action,
2192 uint64_t action_flags,
2193 const struct rte_flow_attr *attr,
2194 struct rte_flow_error *error)
2196 const struct rte_flow_action_set_tag *conf;
2197 const uint64_t terminal_action_flags =
2198 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2199 MLX5_FLOW_ACTION_RSS;
2202 if (!mlx5_flow_ext_mreg_supported(dev))
2203 return rte_flow_error_set(error, ENOTSUP,
2204 RTE_FLOW_ERROR_TYPE_ACTION, action,
2205 "extensive metadata register"
2206 " isn't supported");
2207 if (!(action->conf))
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, action,
2210 "configuration cannot be null");
2211 conf = (const struct rte_flow_action_set_tag *)action->conf;
2213 return rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ACTION, action,
2215 "zero mask doesn't have any effect");
2216 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2219 if (!attr->transfer && attr->ingress &&
2220 (action_flags & terminal_action_flags))
2221 return rte_flow_error_set(error, EINVAL,
2222 RTE_FLOW_ERROR_TYPE_ACTION, action,
2223 "set_tag has no effect"
2224 " with terminal actions");
2229 * Validate count action.
2232 * Pointer to rte_eth_dev structure.
2234 * Pointer to error structure.
2237 * 0 on success, a negative errno value otherwise and rte_errno is set.
2240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2241 struct rte_flow_error *error)
2243 struct mlx5_priv *priv = dev->data->dev_private;
2245 if (!priv->config.devx)
2247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2251 return rte_flow_error_set
2253 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2255 "count action not supported");
2259 * Validate the L2 encap action.
2262 * Pointer to the rte_eth_dev structure.
2263 * @param[in] action_flags
2264 * Holds the actions detected until now.
2266 * Pointer to the action structure.
2268 * Pointer to flow attributes.
2270 * Pointer to error structure.
2273 * 0 on success, a negative errno value otherwise and rte_errno is set.
2276 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2277 uint64_t action_flags,
2278 const struct rte_flow_action *action,
2279 const struct rte_flow_attr *attr,
2280 struct rte_flow_error *error)
2282 const struct mlx5_priv *priv = dev->data->dev_private;
2284 if (!(action->conf))
2285 return rte_flow_error_set(error, EINVAL,
2286 RTE_FLOW_ERROR_TYPE_ACTION, action,
2287 "configuration cannot be null");
2288 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2289 return rte_flow_error_set(error, EINVAL,
2290 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2291 "can only have a single encap action "
2293 if (!attr->transfer && priv->representor)
2294 return rte_flow_error_set(error, ENOTSUP,
2295 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296 "encap action for VF representor "
2297 "not supported on NIC table");
2302 * Validate a decap action.
2305 * Pointer to the rte_eth_dev structure.
2306 * @param[in] action_flags
2307 * Holds the actions detected until now.
2309 * Pointer to flow attributes
2311 * Pointer to error structure.
2314 * 0 on success, a negative errno value otherwise and rte_errno is set.
2317 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2318 uint64_t action_flags,
2319 const struct rte_flow_attr *attr,
2320 struct rte_flow_error *error)
2322 const struct mlx5_priv *priv = dev->data->dev_private;
2324 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2325 return rte_flow_error_set(error, ENOTSUP,
2326 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2328 MLX5_FLOW_ACTION_DECAP ? "can only "
2329 "have a single decap action" : "decap "
2330 "after encap is not supported");
2331 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2332 return rte_flow_error_set(error, EINVAL,
2333 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2334 "can't have decap action after"
2337 return rte_flow_error_set(error, ENOTSUP,
2338 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2340 "decap action not supported for "
2342 if (!attr->transfer && priv->representor)
2343 return rte_flow_error_set(error, ENOTSUP,
2344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2345 "decap action for VF representor "
2346 "not supported on NIC table");
2350 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2353 * Validate the raw encap and decap actions.
2356 * Pointer to the rte_eth_dev structure.
2358 * Pointer to the decap action.
2360 * Pointer to the encap action.
2362 * Pointer to flow attributes
2363 * @param[in/out] action_flags
2364 * Holds the actions detected until now.
2365 * @param[out] actions_n
2366 * pointer to the number of actions counter.
2368 * Pointer to error structure.
2371 * 0 on success, a negative errno value otherwise and rte_errno is set.
2374 flow_dv_validate_action_raw_encap_decap
2375 (struct rte_eth_dev *dev,
2376 const struct rte_flow_action_raw_decap *decap,
2377 const struct rte_flow_action_raw_encap *encap,
2378 const struct rte_flow_attr *attr, uint64_t *action_flags,
2379 int *actions_n, struct rte_flow_error *error)
2381 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (encap && (!encap->size || !encap->data))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387 "raw encap data cannot be empty");
2388 if (decap && encap) {
2389 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2390 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2393 else if (encap->size <=
2394 MLX5_ENCAPSULATION_DECISION_SIZE &&
2396 MLX5_ENCAPSULATION_DECISION_SIZE)
2399 else if (encap->size >
2400 MLX5_ENCAPSULATION_DECISION_SIZE &&
2402 MLX5_ENCAPSULATION_DECISION_SIZE)
2403 /* 2 L2 actions: encap and decap. */
2406 return rte_flow_error_set(error,
2408 RTE_FLOW_ERROR_TYPE_ACTION,
2409 NULL, "unsupported too small "
2410 "raw decap and too small raw "
2411 "encap combination");
2414 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2418 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2422 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2423 return rte_flow_error_set(error, ENOTSUP,
2424 RTE_FLOW_ERROR_TYPE_ACTION,
2426 "small raw encap size");
2427 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2428 return rte_flow_error_set(error, EINVAL,
2429 RTE_FLOW_ERROR_TYPE_ACTION,
2431 "more than one encap action");
2432 if (!attr->transfer && priv->representor)
2433 return rte_flow_error_set
2435 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2436 "encap action for VF representor "
2437 "not supported on NIC table");
2438 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2445 * Find existing encap/decap resource or create and register a new one.
2447 * @param[in, out] dev
2448 * Pointer to rte_eth_dev structure.
2449 * @param[in, out] resource
2450 * Pointer to encap/decap resource.
2451 * @parm[in, out] dev_flow
2452 * Pointer to the dev_flow.
2454 * pointer to error structure.
2457 * 0 on success otherwise -errno and errno is set.
2460 flow_dv_encap_decap_resource_register
2461 (struct rte_eth_dev *dev,
2462 struct mlx5_flow_dv_encap_decap_resource *resource,
2463 struct mlx5_flow *dev_flow,
2464 struct rte_flow_error *error)
2466 struct mlx5_priv *priv = dev->data->dev_private;
2467 struct mlx5_ibv_shared *sh = priv->sh;
2468 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2469 struct mlx5dv_dr_domain *domain;
2472 resource->flags = dev_flow->dv.group ? 0 : 1;
2473 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2474 domain = sh->fdb_domain;
2475 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2476 domain = sh->rx_domain;
2478 domain = sh->tx_domain;
2479 /* Lookup a matching resource from cache. */
2480 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2481 cache_resource, next) {
2482 if (resource->reformat_type == cache_resource->reformat_type &&
2483 resource->ft_type == cache_resource->ft_type &&
2484 resource->flags == cache_resource->flags &&
2485 resource->size == cache_resource->size &&
2486 !memcmp((const void *)resource->buf,
2487 (const void *)cache_resource->buf,
2489 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2490 (void *)cache_resource,
2491 rte_atomic32_read(&cache_resource->refcnt));
2492 rte_atomic32_inc(&cache_resource->refcnt);
2493 dev_flow->handle->dvh.encap_decap = idx;
2494 dev_flow->dv.encap_decap = cache_resource;
2498 /* Register new encap/decap resource. */
2499 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2500 &dev_flow->handle->dvh.encap_decap);
2501 if (!cache_resource)
2502 return rte_flow_error_set(error, ENOMEM,
2503 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2504 "cannot allocate resource memory");
2505 *cache_resource = *resource;
2506 cache_resource->verbs_action =
2507 mlx5_glue->dv_create_flow_action_packet_reformat
2508 (sh->ctx, cache_resource->reformat_type,
2509 cache_resource->ft_type, domain, cache_resource->flags,
2510 cache_resource->size,
2511 (cache_resource->size ? cache_resource->buf : NULL));
2512 if (!cache_resource->verbs_action) {
2513 rte_free(cache_resource);
2514 return rte_flow_error_set(error, ENOMEM,
2515 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2516 NULL, "cannot create action");
2518 rte_atomic32_init(&cache_resource->refcnt);
2519 rte_atomic32_inc(&cache_resource->refcnt);
2520 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2521 dev_flow->handle->dvh.encap_decap, cache_resource, next);
2522 dev_flow->dv.encap_decap = cache_resource;
2523 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2524 (void *)cache_resource,
2525 rte_atomic32_read(&cache_resource->refcnt));
2530 * Find existing table jump resource or create and register a new one.
2532 * @param[in, out] dev
2533 * Pointer to rte_eth_dev structure.
2534 * @param[in, out] tbl
2535 * Pointer to flow table resource.
2536 * @parm[in, out] dev_flow
2537 * Pointer to the dev_flow.
2539 * pointer to error structure.
2542 * 0 on success otherwise -errno and errno is set.
2545 flow_dv_jump_tbl_resource_register
2546 (struct rte_eth_dev *dev __rte_unused,
2547 struct mlx5_flow_tbl_resource *tbl,
2548 struct mlx5_flow *dev_flow,
2549 struct rte_flow_error *error)
2551 struct mlx5_flow_tbl_data_entry *tbl_data =
2552 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2556 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2558 tbl_data->jump.action =
2559 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2561 if (!tbl_data->jump.action)
2562 return rte_flow_error_set(error, ENOMEM,
2563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2564 NULL, "cannot create jump action");
2565 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2566 (void *)&tbl_data->jump, cnt);
2568 /* old jump should not make the table ref++. */
2569 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2570 MLX5_ASSERT(tbl_data->jump.action);
2571 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2572 (void *)&tbl_data->jump, cnt);
2574 rte_atomic32_inc(&tbl_data->jump.refcnt);
2575 dev_flow->handle->dvh.jump = &tbl_data->jump;
2580 * Find existing table port ID resource or create and register a new one.
2582 * @param[in, out] dev
2583 * Pointer to rte_eth_dev structure.
2584 * @param[in, out] resource
2585 * Pointer to port ID action resource.
2586 * @parm[in, out] dev_flow
2587 * Pointer to the dev_flow.
2589 * pointer to error structure.
2592 * 0 on success otherwise -errno and errno is set.
2595 flow_dv_port_id_action_resource_register
2596 (struct rte_eth_dev *dev,
2597 struct mlx5_flow_dv_port_id_action_resource *resource,
2598 struct mlx5_flow *dev_flow,
2599 struct rte_flow_error *error)
2601 struct mlx5_priv *priv = dev->data->dev_private;
2602 struct mlx5_ibv_shared *sh = priv->sh;
2603 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2606 /* Lookup a matching resource from cache. */
2607 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2608 idx, cache_resource, next) {
2609 if (resource->port_id == cache_resource->port_id) {
2610 DRV_LOG(DEBUG, "port id action resource resource %p: "
2612 (void *)cache_resource,
2613 rte_atomic32_read(&cache_resource->refcnt));
2614 rte_atomic32_inc(&cache_resource->refcnt);
2615 dev_flow->handle->dvh.port_id_action = idx;
2616 dev_flow->dv.port_id_action = cache_resource;
2620 /* Register new port id action resource. */
2621 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2622 &dev_flow->handle->dvh.port_id_action);
2623 if (!cache_resource)
2624 return rte_flow_error_set(error, ENOMEM,
2625 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2626 "cannot allocate resource memory");
2627 *cache_resource = *resource;
2629 * Depending on rdma_core version the glue routine calls
2630 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2631 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2633 cache_resource->action =
2634 mlx5_glue->dr_create_flow_action_dest_port
2635 (priv->sh->fdb_domain, resource->port_id);
2636 if (!cache_resource->action) {
2637 rte_free(cache_resource);
2638 return rte_flow_error_set(error, ENOMEM,
2639 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2640 NULL, "cannot create action");
2642 rte_atomic32_init(&cache_resource->refcnt);
2643 rte_atomic32_inc(&cache_resource->refcnt);
2644 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2645 dev_flow->handle->dvh.port_id_action, cache_resource,
2647 dev_flow->dv.port_id_action = cache_resource;
2648 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2649 (void *)cache_resource,
2650 rte_atomic32_read(&cache_resource->refcnt));
2655 * Find existing push vlan resource or create and register a new one.
2657 * @param [in, out] dev
2658 * Pointer to rte_eth_dev structure.
2659 * @param[in, out] resource
2660 * Pointer to port ID action resource.
2661 * @parm[in, out] dev_flow
2662 * Pointer to the dev_flow.
2664 * pointer to error structure.
2667 * 0 on success otherwise -errno and errno is set.
2670 flow_dv_push_vlan_action_resource_register
2671 (struct rte_eth_dev *dev,
2672 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2673 struct mlx5_flow *dev_flow,
2674 struct rte_flow_error *error)
2676 struct mlx5_priv *priv = dev->data->dev_private;
2677 struct mlx5_ibv_shared *sh = priv->sh;
2678 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2679 struct mlx5dv_dr_domain *domain;
2682 /* Lookup a matching resource from cache. */
2683 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2684 sh->push_vlan_action_list, idx, cache_resource, next) {
2685 if (resource->vlan_tag == cache_resource->vlan_tag &&
2686 resource->ft_type == cache_resource->ft_type) {
2687 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2689 (void *)cache_resource,
2690 rte_atomic32_read(&cache_resource->refcnt));
2691 rte_atomic32_inc(&cache_resource->refcnt);
2692 dev_flow->handle->dvh.push_vlan_res = idx;
2693 dev_flow->dv.push_vlan_res = cache_resource;
2697 /* Register new push_vlan action resource. */
2698 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2699 &dev_flow->handle->dvh.push_vlan_res);
2700 if (!cache_resource)
2701 return rte_flow_error_set(error, ENOMEM,
2702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2703 "cannot allocate resource memory");
2704 *cache_resource = *resource;
2705 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2706 domain = sh->fdb_domain;
2707 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2708 domain = sh->rx_domain;
2710 domain = sh->tx_domain;
2711 cache_resource->action =
2712 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2713 resource->vlan_tag);
2714 if (!cache_resource->action) {
2715 rte_free(cache_resource);
2716 return rte_flow_error_set(error, ENOMEM,
2717 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2718 NULL, "cannot create action");
2720 rte_atomic32_init(&cache_resource->refcnt);
2721 rte_atomic32_inc(&cache_resource->refcnt);
2722 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2723 &sh->push_vlan_action_list,
2724 dev_flow->handle->dvh.push_vlan_res,
2725 cache_resource, next);
2726 dev_flow->dv.push_vlan_res = cache_resource;
2727 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2728 (void *)cache_resource,
2729 rte_atomic32_read(&cache_resource->refcnt));
2733 * Get the size of specific rte_flow_item_type
2735 * @param[in] item_type
2736 * Tested rte_flow_item_type.
2739 * sizeof struct item_type, 0 if void or irrelevant.
2742 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2746 switch (item_type) {
2747 case RTE_FLOW_ITEM_TYPE_ETH:
2748 retval = sizeof(struct rte_flow_item_eth);
2750 case RTE_FLOW_ITEM_TYPE_VLAN:
2751 retval = sizeof(struct rte_flow_item_vlan);
2753 case RTE_FLOW_ITEM_TYPE_IPV4:
2754 retval = sizeof(struct rte_flow_item_ipv4);
2756 case RTE_FLOW_ITEM_TYPE_IPV6:
2757 retval = sizeof(struct rte_flow_item_ipv6);
2759 case RTE_FLOW_ITEM_TYPE_UDP:
2760 retval = sizeof(struct rte_flow_item_udp);
2762 case RTE_FLOW_ITEM_TYPE_TCP:
2763 retval = sizeof(struct rte_flow_item_tcp);
2765 case RTE_FLOW_ITEM_TYPE_VXLAN:
2766 retval = sizeof(struct rte_flow_item_vxlan);
2768 case RTE_FLOW_ITEM_TYPE_GRE:
2769 retval = sizeof(struct rte_flow_item_gre);
2771 case RTE_FLOW_ITEM_TYPE_NVGRE:
2772 retval = sizeof(struct rte_flow_item_nvgre);
2774 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2775 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2777 case RTE_FLOW_ITEM_TYPE_MPLS:
2778 retval = sizeof(struct rte_flow_item_mpls);
2780 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2788 #define MLX5_ENCAP_IPV4_VERSION 0x40
2789 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2790 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2791 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2792 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2793 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2794 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2797 * Convert the encap action data from list of rte_flow_item to raw buffer
2800 * Pointer to rte_flow_item objects list.
2802 * Pointer to the output buffer.
2804 * Pointer to the output buffer size.
2806 * Pointer to the error structure.
2809 * 0 on success, a negative errno value otherwise and rte_errno is set.
2812 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2813 size_t *size, struct rte_flow_error *error)
2815 struct rte_ether_hdr *eth = NULL;
2816 struct rte_vlan_hdr *vlan = NULL;
2817 struct rte_ipv4_hdr *ipv4 = NULL;
2818 struct rte_ipv6_hdr *ipv6 = NULL;
2819 struct rte_udp_hdr *udp = NULL;
2820 struct rte_vxlan_hdr *vxlan = NULL;
2821 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2822 struct rte_gre_hdr *gre = NULL;
2824 size_t temp_size = 0;
2827 return rte_flow_error_set(error, EINVAL,
2828 RTE_FLOW_ERROR_TYPE_ACTION,
2829 NULL, "invalid empty data");
2830 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2831 len = flow_dv_get_item_len(items->type);
2832 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2833 return rte_flow_error_set(error, EINVAL,
2834 RTE_FLOW_ERROR_TYPE_ACTION,
2835 (void *)items->type,
2836 "items total size is too big"
2837 " for encap action");
2838 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2839 switch (items->type) {
2840 case RTE_FLOW_ITEM_TYPE_ETH:
2841 eth = (struct rte_ether_hdr *)&buf[temp_size];
2843 case RTE_FLOW_ITEM_TYPE_VLAN:
2844 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2846 return rte_flow_error_set(error, EINVAL,
2847 RTE_FLOW_ERROR_TYPE_ACTION,
2848 (void *)items->type,
2849 "eth header not found");
2850 if (!eth->ether_type)
2851 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2853 case RTE_FLOW_ITEM_TYPE_IPV4:
2854 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2856 return rte_flow_error_set(error, EINVAL,
2857 RTE_FLOW_ERROR_TYPE_ACTION,
2858 (void *)items->type,
2859 "neither eth nor vlan"
2861 if (vlan && !vlan->eth_proto)
2862 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2863 else if (eth && !eth->ether_type)
2864 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2865 if (!ipv4->version_ihl)
2866 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2867 MLX5_ENCAP_IPV4_IHL_MIN;
2868 if (!ipv4->time_to_live)
2869 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2871 case RTE_FLOW_ITEM_TYPE_IPV6:
2872 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2874 return rte_flow_error_set(error, EINVAL,
2875 RTE_FLOW_ERROR_TYPE_ACTION,
2876 (void *)items->type,
2877 "neither eth nor vlan"
2879 if (vlan && !vlan->eth_proto)
2880 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2881 else if (eth && !eth->ether_type)
2882 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2883 if (!ipv6->vtc_flow)
2885 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2886 if (!ipv6->hop_limits)
2887 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2889 case RTE_FLOW_ITEM_TYPE_UDP:
2890 udp = (struct rte_udp_hdr *)&buf[temp_size];
2892 return rte_flow_error_set(error, EINVAL,
2893 RTE_FLOW_ERROR_TYPE_ACTION,
2894 (void *)items->type,
2895 "ip header not found");
2896 if (ipv4 && !ipv4->next_proto_id)
2897 ipv4->next_proto_id = IPPROTO_UDP;
2898 else if (ipv6 && !ipv6->proto)
2899 ipv6->proto = IPPROTO_UDP;
2901 case RTE_FLOW_ITEM_TYPE_VXLAN:
2902 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2904 return rte_flow_error_set(error, EINVAL,
2905 RTE_FLOW_ERROR_TYPE_ACTION,
2906 (void *)items->type,
2907 "udp header not found");
2909 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2910 if (!vxlan->vx_flags)
2912 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2914 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2915 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2917 return rte_flow_error_set(error, EINVAL,
2918 RTE_FLOW_ERROR_TYPE_ACTION,
2919 (void *)items->type,
2920 "udp header not found");
2921 if (!vxlan_gpe->proto)
2922 return rte_flow_error_set(error, EINVAL,
2923 RTE_FLOW_ERROR_TYPE_ACTION,
2924 (void *)items->type,
2925 "next protocol not found");
2928 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2929 if (!vxlan_gpe->vx_flags)
2930 vxlan_gpe->vx_flags =
2931 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2933 case RTE_FLOW_ITEM_TYPE_GRE:
2934 case RTE_FLOW_ITEM_TYPE_NVGRE:
2935 gre = (struct rte_gre_hdr *)&buf[temp_size];
2937 return rte_flow_error_set(error, EINVAL,
2938 RTE_FLOW_ERROR_TYPE_ACTION,
2939 (void *)items->type,
2940 "next protocol not found");
2942 return rte_flow_error_set(error, EINVAL,
2943 RTE_FLOW_ERROR_TYPE_ACTION,
2944 (void *)items->type,
2945 "ip header not found");
2946 if (ipv4 && !ipv4->next_proto_id)
2947 ipv4->next_proto_id = IPPROTO_GRE;
2948 else if (ipv6 && !ipv6->proto)
2949 ipv6->proto = IPPROTO_GRE;
2951 case RTE_FLOW_ITEM_TYPE_VOID:
2954 return rte_flow_error_set(error, EINVAL,
2955 RTE_FLOW_ERROR_TYPE_ACTION,
2956 (void *)items->type,
2957 "unsupported item type");
2967 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2969 struct rte_ether_hdr *eth = NULL;
2970 struct rte_vlan_hdr *vlan = NULL;
2971 struct rte_ipv6_hdr *ipv6 = NULL;
2972 struct rte_udp_hdr *udp = NULL;
2976 eth = (struct rte_ether_hdr *)data;
2977 next_hdr = (char *)(eth + 1);
2978 proto = RTE_BE16(eth->ether_type);
2981 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2982 vlan = (struct rte_vlan_hdr *)next_hdr;
2983 proto = RTE_BE16(vlan->eth_proto);
2984 next_hdr += sizeof(struct rte_vlan_hdr);
2987 /* HW calculates IPv4 csum. no need to proceed */
2988 if (proto == RTE_ETHER_TYPE_IPV4)
2991 /* non IPv4/IPv6 header. not supported */
2992 if (proto != RTE_ETHER_TYPE_IPV6) {
2993 return rte_flow_error_set(error, ENOTSUP,
2994 RTE_FLOW_ERROR_TYPE_ACTION,
2995 NULL, "Cannot offload non IPv4/IPv6");
2998 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3000 /* ignore non UDP */
3001 if (ipv6->proto != IPPROTO_UDP)
3004 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3005 udp->dgram_cksum = 0;
3011 * Convert L2 encap action to DV specification.
3014 * Pointer to rte_eth_dev structure.
3016 * Pointer to action structure.
3017 * @param[in, out] dev_flow
3018 * Pointer to the mlx5_flow.
3019 * @param[in] transfer
3020 * Mark if the flow is E-Switch flow.
3022 * Pointer to the error structure.
3025 * 0 on success, a negative errno value otherwise and rte_errno is set.
3028 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3029 const struct rte_flow_action *action,
3030 struct mlx5_flow *dev_flow,
3032 struct rte_flow_error *error)
3034 const struct rte_flow_item *encap_data;
3035 const struct rte_flow_action_raw_encap *raw_encap_data;
3036 struct mlx5_flow_dv_encap_decap_resource res = {
3038 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3039 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3040 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3043 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3045 (const struct rte_flow_action_raw_encap *)action->conf;
3046 res.size = raw_encap_data->size;
3047 memcpy(res.buf, raw_encap_data->data, res.size);
3049 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3051 ((const struct rte_flow_action_vxlan_encap *)
3052 action->conf)->definition;
3055 ((const struct rte_flow_action_nvgre_encap *)
3056 action->conf)->definition;
3057 if (flow_dv_convert_encap_data(encap_data, res.buf,
3061 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3063 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3064 return rte_flow_error_set(error, EINVAL,
3065 RTE_FLOW_ERROR_TYPE_ACTION,
3066 NULL, "can't create L2 encap action");
3071 * Convert L2 decap action to DV specification.
3074 * Pointer to rte_eth_dev structure.
3075 * @param[in, out] dev_flow
3076 * Pointer to the mlx5_flow.
3077 * @param[in] transfer
3078 * Mark if the flow is E-Switch flow.
3080 * Pointer to the error structure.
3083 * 0 on success, a negative errno value otherwise and rte_errno is set.
3086 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3087 struct mlx5_flow *dev_flow,
3089 struct rte_flow_error *error)
3091 struct mlx5_flow_dv_encap_decap_resource res = {
3094 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3095 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3096 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3099 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3100 return rte_flow_error_set(error, EINVAL,
3101 RTE_FLOW_ERROR_TYPE_ACTION,
3102 NULL, "can't create L2 decap action");
3107 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3110 * Pointer to rte_eth_dev structure.
3112 * Pointer to action structure.
3113 * @param[in, out] dev_flow
3114 * Pointer to the mlx5_flow.
3116 * Pointer to the flow attributes.
3118 * Pointer to the error structure.
3121 * 0 on success, a negative errno value otherwise and rte_errno is set.
3124 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3125 const struct rte_flow_action *action,
3126 struct mlx5_flow *dev_flow,
3127 const struct rte_flow_attr *attr,
3128 struct rte_flow_error *error)
3130 const struct rte_flow_action_raw_encap *encap_data;
3131 struct mlx5_flow_dv_encap_decap_resource res;
3133 memset(&res, 0, sizeof(res));
3134 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3135 res.size = encap_data->size;
3136 memcpy(res.buf, encap_data->data, res.size);
3137 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3138 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3139 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3141 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3143 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3144 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3145 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3146 return rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION,
3148 NULL, "can't create encap action");
3153 * Create action push VLAN.
3156 * Pointer to rte_eth_dev structure.
3158 * Pointer to the flow attributes.
3160 * Pointer to the vlan to push to the Ethernet header.
3161 * @param[in, out] dev_flow
3162 * Pointer to the mlx5_flow.
3164 * Pointer to the error structure.
3167 * 0 on success, a negative errno value otherwise and rte_errno is set.
3170 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3171 const struct rte_flow_attr *attr,
3172 const struct rte_vlan_hdr *vlan,
3173 struct mlx5_flow *dev_flow,
3174 struct rte_flow_error *error)
3176 struct mlx5_flow_dv_push_vlan_action_resource res;
3178 memset(&res, 0, sizeof(res));
3180 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3183 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3185 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3186 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3187 return flow_dv_push_vlan_action_resource_register
3188 (dev, &res, dev_flow, error);
3192 * Validate the modify-header actions.
3194 * @param[in] action_flags
3195 * Holds the actions detected until now.
3197 * Pointer to the modify action.
3199 * Pointer to error structure.
3202 * 0 on success, a negative errno value otherwise and rte_errno is set.
3205 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3206 const struct rte_flow_action *action,
3207 struct rte_flow_error *error)
3209 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3210 return rte_flow_error_set(error, EINVAL,
3211 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3212 NULL, "action configuration not set");
3213 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3214 return rte_flow_error_set(error, EINVAL,
3215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3216 "can't have encap action before"
3222 * Validate the modify-header MAC address actions.
3224 * @param[in] action_flags
3225 * Holds the actions detected until now.
3227 * Pointer to the modify action.
3228 * @param[in] item_flags
3229 * Holds the items detected.
3231 * Pointer to error structure.
3234 * 0 on success, a negative errno value otherwise and rte_errno is set.
3237 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3238 const struct rte_flow_action *action,
3239 const uint64_t item_flags,
3240 struct rte_flow_error *error)
3244 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3246 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3247 return rte_flow_error_set(error, EINVAL,
3248 RTE_FLOW_ERROR_TYPE_ACTION,
3250 "no L2 item in pattern");
3256 * Validate the modify-header IPv4 address actions.
3258 * @param[in] action_flags
3259 * Holds the actions detected until now.
3261 * Pointer to the modify action.
3262 * @param[in] item_flags
3263 * Holds the items detected.
3265 * Pointer to error structure.
3268 * 0 on success, a negative errno value otherwise and rte_errno is set.
3271 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3272 const struct rte_flow_action *action,
3273 const uint64_t item_flags,
3274 struct rte_flow_error *error)
3279 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3281 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3282 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3283 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3284 if (!(item_flags & layer))
3285 return rte_flow_error_set(error, EINVAL,
3286 RTE_FLOW_ERROR_TYPE_ACTION,
3288 "no ipv4 item in pattern");
3294 * Validate the modify-header IPv6 address actions.
3296 * @param[in] action_flags
3297 * Holds the actions detected until now.
3299 * Pointer to the modify action.
3300 * @param[in] item_flags
3301 * Holds the items detected.
3303 * Pointer to error structure.
3306 * 0 on success, a negative errno value otherwise and rte_errno is set.
3309 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3310 const struct rte_flow_action *action,
3311 const uint64_t item_flags,
3312 struct rte_flow_error *error)
3317 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3319 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3320 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3321 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3322 if (!(item_flags & layer))
3323 return rte_flow_error_set(error, EINVAL,
3324 RTE_FLOW_ERROR_TYPE_ACTION,
3326 "no ipv6 item in pattern");
3332 * Validate the modify-header TP actions.
3334 * @param[in] action_flags
3335 * Holds the actions detected until now.
3337 * Pointer to the modify action.
3338 * @param[in] item_flags
3339 * Holds the items detected.
3341 * Pointer to error structure.
3344 * 0 on success, a negative errno value otherwise and rte_errno is set.
3347 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3348 const struct rte_flow_action *action,
3349 const uint64_t item_flags,
3350 struct rte_flow_error *error)
3355 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3357 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3358 MLX5_FLOW_LAYER_INNER_L4 :
3359 MLX5_FLOW_LAYER_OUTER_L4;
3360 if (!(item_flags & layer))
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION,
3363 NULL, "no transport layer "
3370 * Validate the modify-header actions of increment/decrement
3371 * TCP Sequence-number.
3373 * @param[in] action_flags
3374 * Holds the actions detected until now.
3376 * Pointer to the modify action.
3377 * @param[in] item_flags
3378 * Holds the items detected.
3380 * Pointer to error structure.
3383 * 0 on success, a negative errno value otherwise and rte_errno is set.
3386 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3387 const struct rte_flow_action *action,
3388 const uint64_t item_flags,
3389 struct rte_flow_error *error)
3394 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3396 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3397 MLX5_FLOW_LAYER_INNER_L4_TCP :
3398 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3399 if (!(item_flags & layer))
3400 return rte_flow_error_set(error, EINVAL,
3401 RTE_FLOW_ERROR_TYPE_ACTION,
3402 NULL, "no TCP item in"
3404 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3405 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3406 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3407 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3408 return rte_flow_error_set(error, EINVAL,
3409 RTE_FLOW_ERROR_TYPE_ACTION,
3411 "cannot decrease and increase"
3412 " TCP sequence number"
3413 " at the same time");
3419 * Validate the modify-header actions of increment/decrement
3420 * TCP Acknowledgment number.
3422 * @param[in] action_flags
3423 * Holds the actions detected until now.
3425 * Pointer to the modify action.
3426 * @param[in] item_flags
3427 * Holds the items detected.
3429 * Pointer to error structure.
3432 * 0 on success, a negative errno value otherwise and rte_errno is set.
3435 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3436 const struct rte_flow_action *action,
3437 const uint64_t item_flags,
3438 struct rte_flow_error *error)
3443 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3445 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3446 MLX5_FLOW_LAYER_INNER_L4_TCP :
3447 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3448 if (!(item_flags & layer))
3449 return rte_flow_error_set(error, EINVAL,
3450 RTE_FLOW_ERROR_TYPE_ACTION,
3451 NULL, "no TCP item in"
3453 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3454 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3455 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3456 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3457 return rte_flow_error_set(error, EINVAL,
3458 RTE_FLOW_ERROR_TYPE_ACTION,
3460 "cannot decrease and increase"
3461 " TCP acknowledgment number"
3462 " at the same time");
3468 * Validate the modify-header TTL actions.
3470 * @param[in] action_flags
3471 * Holds the actions detected until now.
3473 * Pointer to the modify action.
3474 * @param[in] item_flags
3475 * Holds the items detected.
3477 * Pointer to error structure.
3480 * 0 on success, a negative errno value otherwise and rte_errno is set.
3483 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3484 const struct rte_flow_action *action,
3485 const uint64_t item_flags,
3486 struct rte_flow_error *error)
3491 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3493 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3494 MLX5_FLOW_LAYER_INNER_L3 :
3495 MLX5_FLOW_LAYER_OUTER_L3;
3496 if (!(item_flags & layer))
3497 return rte_flow_error_set(error, EINVAL,
3498 RTE_FLOW_ERROR_TYPE_ACTION,
3500 "no IP protocol in pattern");
3506 * Validate jump action.
3509 * Pointer to the jump action.
3510 * @param[in] action_flags
3511 * Holds the actions detected until now.
3512 * @param[in] attributes
3513 * Pointer to flow attributes
3514 * @param[in] external
3515 * Action belongs to flow rule created by request external to PMD.
3517 * Pointer to error structure.
3520 * 0 on success, a negative errno value otherwise and rte_errno is set.
3523 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3524 uint64_t action_flags,
3525 const struct rte_flow_attr *attributes,
3526 bool external, struct rte_flow_error *error)
3528 uint32_t target_group, table;
3531 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3532 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3533 return rte_flow_error_set(error, EINVAL,
3534 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3535 "can't have 2 fate actions in"
3537 if (action_flags & MLX5_FLOW_ACTION_METER)
3538 return rte_flow_error_set(error, ENOTSUP,
3539 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3540 "jump with meter not support");
3542 return rte_flow_error_set(error, EINVAL,
3543 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3544 NULL, "action configuration not set");
3546 ((const struct rte_flow_action_jump *)action->conf)->group;
3547 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3548 true, &table, error);
3551 if (attributes->group == target_group)
3552 return rte_flow_error_set(error, EINVAL,
3553 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3554 "target group must be other than"
3555 " the current flow group");
3560 * Validate the port_id action.
3563 * Pointer to rte_eth_dev structure.
3564 * @param[in] action_flags
3565 * Bit-fields that holds the actions detected until now.
3567 * Port_id RTE action structure.
3569 * Attributes of flow that includes this action.
3571 * Pointer to error structure.
3574 * 0 on success, a negative errno value otherwise and rte_errno is set.
3577 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3578 uint64_t action_flags,
3579 const struct rte_flow_action *action,
3580 const struct rte_flow_attr *attr,
3581 struct rte_flow_error *error)
3583 const struct rte_flow_action_port_id *port_id;
3584 struct mlx5_priv *act_priv;
3585 struct mlx5_priv *dev_priv;
3588 if (!attr->transfer)
3589 return rte_flow_error_set(error, ENOTSUP,
3590 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3592 "port id action is valid in transfer"
3594 if (!action || !action->conf)
3595 return rte_flow_error_set(error, ENOTSUP,
3596 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3598 "port id action parameters must be"
3600 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3601 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3602 return rte_flow_error_set(error, EINVAL,
3603 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3604 "can have only one fate actions in"
3606 dev_priv = mlx5_dev_to_eswitch_info(dev);
3608 return rte_flow_error_set(error, rte_errno,
3609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3611 "failed to obtain E-Switch info");
3612 port_id = action->conf;
3613 port = port_id->original ? dev->data->port_id : port_id->id;
3614 act_priv = mlx5_port_to_eswitch_info(port, false);
3616 return rte_flow_error_set
3618 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3619 "failed to obtain E-Switch port id for port");
3620 if (act_priv->domain_id != dev_priv->domain_id)
3621 return rte_flow_error_set
3623 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3624 "port does not belong to"
3625 " E-Switch being configured");
3630 * Get the maximum number of modify header actions.
3633 * Pointer to rte_eth_dev structure.
3635 * Flags bits to check if root level.
3638 * Max number of modify header actions device can support.
3641 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3644 * There's no way to directly query the max cap. Although it has to be
3645 * acquried by iterative trial, it is a safe assumption that more
3646 * actions are supported by FW if extensive metadata register is
3647 * supported. (Only in the root table)
3649 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3650 return MLX5_MAX_MODIFY_NUM;
3652 return mlx5_flow_ext_mreg_supported(dev) ?
3653 MLX5_ROOT_TBL_MODIFY_NUM :
3654 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3658 * Validate the meter action.
3661 * Pointer to rte_eth_dev structure.
3662 * @param[in] action_flags
3663 * Bit-fields that holds the actions detected until now.
3665 * Pointer to the meter action.
3667 * Attributes of flow that includes this action.
3669 * Pointer to error structure.
3672 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3675 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3676 uint64_t action_flags,
3677 const struct rte_flow_action *action,
3678 const struct rte_flow_attr *attr,
3679 struct rte_flow_error *error)
3681 struct mlx5_priv *priv = dev->data->dev_private;
3682 const struct rte_flow_action_meter *am = action->conf;
3683 struct mlx5_flow_meter *fm;
3686 return rte_flow_error_set(error, EINVAL,
3687 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3688 "meter action conf is NULL");
3690 if (action_flags & MLX5_FLOW_ACTION_METER)
3691 return rte_flow_error_set(error, ENOTSUP,
3692 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693 "meter chaining not support");
3694 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3695 return rte_flow_error_set(error, ENOTSUP,
3696 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697 "meter with jump not support");
3699 return rte_flow_error_set(error, ENOTSUP,
3700 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3702 "meter action not supported");
3703 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3705 return rte_flow_error_set(error, EINVAL,
3706 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3708 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3709 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3710 (!fm->attr.egress && !attr->egress && attr->ingress))))
3711 return rte_flow_error_set(error, EINVAL,
3712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3713 "Flow attributes are either invalid "
3714 "or have a conflict with current "
3715 "meter attributes");
3720 * Validate the modify-header IPv4 DSCP actions.
3722 * @param[in] action_flags
3723 * Holds the actions detected until now.
3725 * Pointer to the modify action.
3726 * @param[in] item_flags
3727 * Holds the items detected.
3729 * Pointer to error structure.
3732 * 0 on success, a negative errno value otherwise and rte_errno is set.
3735 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3736 const struct rte_flow_action *action,
3737 const uint64_t item_flags,
3738 struct rte_flow_error *error)
3742 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3744 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3745 return rte_flow_error_set(error, EINVAL,
3746 RTE_FLOW_ERROR_TYPE_ACTION,
3748 "no ipv4 item in pattern");
3754 * Validate the modify-header IPv6 DSCP actions.
3756 * @param[in] action_flags
3757 * Holds the actions detected until now.
3759 * Pointer to the modify action.
3760 * @param[in] item_flags
3761 * Holds the items detected.
3763 * Pointer to error structure.
3766 * 0 on success, a negative errno value otherwise and rte_errno is set.
3769 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3770 const struct rte_flow_action *action,
3771 const uint64_t item_flags,
3772 struct rte_flow_error *error)
3776 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3778 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3779 return rte_flow_error_set(error, EINVAL,
3780 RTE_FLOW_ERROR_TYPE_ACTION,
3782 "no ipv6 item in pattern");
3788 * Find existing modify-header resource or create and register a new one.
3790 * @param dev[in, out]
3791 * Pointer to rte_eth_dev structure.
3792 * @param[in, out] resource
3793 * Pointer to modify-header resource.
3794 * @parm[in, out] dev_flow
3795 * Pointer to the dev_flow.
3797 * pointer to error structure.
3800 * 0 on success otherwise -errno and errno is set.
3803 flow_dv_modify_hdr_resource_register
3804 (struct rte_eth_dev *dev,
3805 struct mlx5_flow_dv_modify_hdr_resource *resource,
3806 struct mlx5_flow *dev_flow,
3807 struct rte_flow_error *error)
3809 struct mlx5_priv *priv = dev->data->dev_private;
3810 struct mlx5_ibv_shared *sh = priv->sh;
3811 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3812 struct mlx5dv_dr_domain *ns;
3813 uint32_t actions_len;
3815 resource->flags = dev_flow->dv.group ? 0 :
3816 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3817 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3819 return rte_flow_error_set(error, EOVERFLOW,
3820 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3821 "too many modify header items");
3822 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3823 ns = sh->fdb_domain;
3824 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3828 /* Lookup a matching resource from cache. */
3829 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3830 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3831 if (resource->ft_type == cache_resource->ft_type &&
3832 resource->actions_num == cache_resource->actions_num &&
3833 resource->flags == cache_resource->flags &&
3834 !memcmp((const void *)resource->actions,
3835 (const void *)cache_resource->actions,
3837 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3838 (void *)cache_resource,
3839 rte_atomic32_read(&cache_resource->refcnt));
3840 rte_atomic32_inc(&cache_resource->refcnt);
3841 dev_flow->handle->dvh.modify_hdr = cache_resource;
3845 /* Register new modify-header resource. */
3846 cache_resource = rte_calloc(__func__, 1,
3847 sizeof(*cache_resource) + actions_len, 0);
3848 if (!cache_resource)
3849 return rte_flow_error_set(error, ENOMEM,
3850 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3851 "cannot allocate resource memory");
3852 *cache_resource = *resource;
3853 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3854 cache_resource->verbs_action =
3855 mlx5_glue->dv_create_flow_action_modify_header
3856 (sh->ctx, cache_resource->ft_type, ns,
3857 cache_resource->flags, actions_len,
3858 (uint64_t *)cache_resource->actions);
3859 if (!cache_resource->verbs_action) {
3860 rte_free(cache_resource);
3861 return rte_flow_error_set(error, ENOMEM,
3862 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3863 NULL, "cannot create action");
3865 rte_atomic32_init(&cache_resource->refcnt);
3866 rte_atomic32_inc(&cache_resource->refcnt);
3867 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3868 dev_flow->handle->dvh.modify_hdr = cache_resource;
3869 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3870 (void *)cache_resource,
3871 rte_atomic32_read(&cache_resource->refcnt));
3876 * Get DV flow counter by index.
3879 * Pointer to the Ethernet device structure.
3881 * mlx5 flow counter index in the container.
3883 * mlx5 flow counter pool in the container,
3886 * Pointer to the counter, NULL otherwise.
3888 static struct mlx5_flow_counter *
3889 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3891 struct mlx5_flow_counter_pool **ppool)
3893 struct mlx5_priv *priv = dev->data->dev_private;
3894 struct mlx5_pools_container *cont;
3895 struct mlx5_flow_counter_pool *pool;
3899 if (idx >= MLX5_CNT_BATCH_OFFSET) {
3900 idx -= MLX5_CNT_BATCH_OFFSET;
3903 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3904 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3905 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3909 return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3913 * Get a pool by devx counter ID.
3916 * Pointer to the counter container.
3918 * The counter devx ID.
3921 * The counter pool pointer if exists, NULL otherwise,
3923 static struct mlx5_flow_counter_pool *
3924 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3927 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3929 for (i = 0; i < n_valid; i++) {
3930 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3931 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3932 MLX5_COUNTERS_PER_POOL;
3934 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3936 * Move the pool to the head, as counter allocate
3937 * always gets the first pool in the container.
3939 if (pool != TAILQ_FIRST(&cont->pool_list)) {
3940 TAILQ_REMOVE(&cont->pool_list, pool, next);
3941 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3950 * Allocate a new memory for the counter values wrapped by all the needed
3954 * Pointer to the Ethernet device structure.
3956 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3959 * The new memory management pointer on success, otherwise NULL and rte_errno
3962 static struct mlx5_counter_stats_mem_mng *
3963 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3965 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3966 (dev->data->dev_private))->sh;
3967 struct mlx5_devx_mkey_attr mkey_attr;
3968 struct mlx5_counter_stats_mem_mng *mem_mng;
3969 volatile struct flow_counter_stats *raw_data;
3970 int size = (sizeof(struct flow_counter_stats) *
3971 MLX5_COUNTERS_PER_POOL +
3972 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3973 sizeof(struct mlx5_counter_stats_mem_mng);
3974 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3981 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3982 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3983 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3984 IBV_ACCESS_LOCAL_WRITE);
3985 if (!mem_mng->umem) {
3990 mkey_attr.addr = (uintptr_t)mem;
3991 mkey_attr.size = size;
3992 mkey_attr.umem_id = mem_mng->umem->umem_id;
3993 mkey_attr.pd = sh->pdn;
3994 mkey_attr.log_entity_size = 0;
3995 mkey_attr.pg_access = 0;
3996 mkey_attr.klm_array = NULL;
3997 mkey_attr.klm_num = 0;
3998 mkey_attr.relaxed_ordering = 1;
3999 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4001 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4006 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4007 raw_data = (volatile struct flow_counter_stats *)mem;
4008 for (i = 0; i < raws_n; ++i) {
4009 mem_mng->raws[i].mem_mng = mem_mng;
4010 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4012 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4017 * Resize a counter container.
4020 * Pointer to the Ethernet device structure.
4022 * Whether the pool is for counter that was allocated by batch command.
4025 * The new container pointer on success, otherwise NULL and rte_errno is set.
4027 static struct mlx5_pools_container *
4028 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4030 struct mlx5_priv *priv = dev->data->dev_private;
4031 struct mlx5_pools_container *cont =
4032 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4033 struct mlx5_pools_container *new_cont =
4034 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4035 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4036 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4037 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4040 /* Fallback mode has no background thread. Skip the check. */
4041 if (!priv->counter_fallback &&
4042 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4043 /* The last resize still hasn't detected by the host thread. */
4047 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4048 if (!new_cont->pools) {
4053 memcpy(new_cont->pools, cont->pools, cont->n *
4054 sizeof(struct mlx5_flow_counter_pool *));
4056 * Fallback mode query the counter directly, no background query
4057 * resources are needed.
4059 if (!priv->counter_fallback) {
4060 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4061 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4063 rte_free(new_cont->pools);
4066 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4067 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4069 MLX5_CNT_CONTAINER_RESIZE +
4073 * Release the old container pools directly as no background
4074 * thread helps that.
4076 rte_free(cont->pools);
4078 new_cont->n = resize;
4079 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4080 TAILQ_INIT(&new_cont->pool_list);
4081 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4082 new_cont->init_mem_mng = mem_mng;
4084 /* Flip the master container. */
4085 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4090 * Query a devx flow counter.
4093 * Pointer to the Ethernet device structure.
4095 * Index to the flow counter.
4097 * The statistics value of packets.
4099 * The statistics value of bytes.
4102 * 0 on success, otherwise a negative errno value and rte_errno is set.
4105 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4108 struct mlx5_priv *priv = dev->data->dev_private;
4109 struct mlx5_flow_counter_pool *pool = NULL;
4110 struct mlx5_flow_counter *cnt;
4111 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4114 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4116 if (counter < MLX5_CNT_BATCH_OFFSET) {
4117 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4118 if (priv->counter_fallback)
4119 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4120 0, pkts, bytes, 0, NULL, NULL, 0);
4123 rte_spinlock_lock(&pool->sl);
4125 * The single counters allocation may allocate smaller ID than the
4126 * current allocated in parallel to the host reading.
4127 * In this case the new counter values must be reported as 0.
4129 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4133 offset = cnt - &pool->counters_raw[0];
4134 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4135 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4137 rte_spinlock_unlock(&pool->sl);
4142 * Create and initialize a new counter pool.
4145 * Pointer to the Ethernet device structure.
4147 * The devX counter handle.
4149 * Whether the pool is for counter that was allocated by batch command.
4150 * @param[in/out] cont_cur
4151 * Pointer to the container pointer, it will be update in pool resize.
4154 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4156 static struct mlx5_pools_container *
4157 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4160 struct mlx5_priv *priv = dev->data->dev_private;
4161 struct mlx5_flow_counter_pool *pool;
4162 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4164 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4167 if (cont->n == n_valid) {
4168 cont = flow_dv_container_resize(dev, batch);
4172 size = sizeof(*pool);
4174 size += MLX5_COUNTERS_PER_POOL *
4175 sizeof(struct mlx5_flow_counter_ext);
4176 pool = rte_calloc(__func__, 1, size, 0);
4181 pool->min_dcs = dcs;
4182 if (!priv->counter_fallback)
4183 pool->raw = cont->init_mem_mng->raws + n_valid %
4184 MLX5_CNT_CONTAINER_RESIZE;
4185 pool->raw_hw = NULL;
4186 rte_spinlock_init(&pool->sl);
4188 * The generation of the new allocated counters in this pool is 0, 2 in
4189 * the pool generation makes all the counters valid for allocation.
4190 * The start and end query generation protect the counters be released
4191 * between the query and update gap period will not be reallocated
4192 * without the last query finished and stats updated to the memory.
4194 rte_atomic64_set(&pool->start_query_gen, 0x2);
4196 * There's no background query thread for fallback mode, set the
4197 * end_query_gen to the maximum value since no need to wait for
4198 * statistics update.
4200 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4202 TAILQ_INIT(&pool->counters);
4203 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4204 pool->index = n_valid;
4205 cont->pools[n_valid] = pool;
4206 /* Pool initialization must be updated before host thread access. */
4208 rte_atomic16_add(&cont->n_valid, 1);
4213 * Prepare a new counter and/or a new counter pool.
4216 * Pointer to the Ethernet device structure.
4217 * @param[out] cnt_free
4218 * Where to put the pointer of a new counter.
4220 * Whether the pool is for counter that was allocated by batch command.
4223 * The counter container pointer and @p cnt_free is set on success,
4224 * NULL otherwise and rte_errno is set.
4226 static struct mlx5_pools_container *
4227 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4228 struct mlx5_flow_counter **cnt_free,
4231 struct mlx5_priv *priv = dev->data->dev_private;
4232 struct mlx5_pools_container *cont;
4233 struct mlx5_flow_counter_pool *pool;
4234 struct mlx5_devx_obj *dcs = NULL;
4235 struct mlx5_flow_counter *cnt;
4238 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4240 /* bulk_bitmap must be 0 for single counter allocation. */
4241 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4244 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4246 cont = flow_dv_pool_create(dev, dcs, batch);
4248 mlx5_devx_cmd_destroy(dcs);
4251 pool = TAILQ_FIRST(&cont->pool_list);
4252 } else if (dcs->id < pool->min_dcs->id) {
4253 rte_atomic64_set(&pool->a64_dcs,
4254 (int64_t)(uintptr_t)dcs);
4256 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4257 cnt = &pool->counters_raw[i];
4258 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4259 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4263 /* bulk_bitmap is in 128 counters units. */
4264 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4265 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4267 rte_errno = ENODATA;
4270 cont = flow_dv_pool_create(dev, dcs, batch);
4272 mlx5_devx_cmd_destroy(dcs);
4275 pool = TAILQ_FIRST(&cont->pool_list);
4276 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4277 cnt = &pool->counters_raw[i];
4278 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4280 *cnt_free = &pool->counters_raw[0];
4285 * Search for existed shared counter.
4288 * Pointer to the relevant counter pool container.
4290 * The shared counter ID to search.
4292 * mlx5 flow counter pool in the container,
4295 * NULL if not existed, otherwise pointer to the shared extend counter.
4297 static struct mlx5_flow_counter_ext *
4298 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4299 struct mlx5_flow_counter_pool **ppool)
4301 static struct mlx5_flow_counter_ext *cnt;
4302 struct mlx5_flow_counter_pool *pool;
4304 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4306 for (i = 0; i < n_valid; i++) {
4307 pool = cont->pools[i];
4308 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4309 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4310 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4312 *ppool = cont->pools[i];
4321 * Allocate a flow counter.
4324 * Pointer to the Ethernet device structure.
4326 * Indicate if this counter is shared with other flows.
4328 * Counter identifier.
4330 * Counter flow group.
4333 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4336 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4339 struct mlx5_priv *priv = dev->data->dev_private;
4340 struct mlx5_flow_counter_pool *pool = NULL;
4341 struct mlx5_flow_counter *cnt_free = NULL;
4342 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4344 * Currently group 0 flow counter cannot be assigned to a flow if it is
4345 * not the first one in the batch counter allocation, so it is better
4346 * to allocate counters one by one for these flows in a separate
4348 * A counter can be shared between different groups so need to take
4349 * shared counters from the single container.
4351 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4352 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4356 if (!priv->config.devx) {
4357 rte_errno = ENOTSUP;
4361 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4363 if (cnt_ext->ref_cnt + 1 == 0) {
4368 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4369 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4374 /* Pools which has a free counters are in the start. */
4375 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4377 * The free counter reset values must be updated between the
4378 * counter release to the counter allocation, so, at least one
4379 * query must be done in this time. ensure it by saving the
4380 * query generation in the release time.
4381 * The free list is sorted according to the generation - so if
4382 * the first one is not updated, all the others are not
4385 cnt_free = TAILQ_FIRST(&pool->counters);
4386 if (cnt_free && cnt_free->query_gen <
4387 rte_atomic64_read(&pool->end_query_gen))
4392 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4395 pool = TAILQ_FIRST(&cont->pool_list);
4398 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4399 /* Create a DV counter action only in the first time usage. */
4400 if (!cnt_free->action) {
4402 struct mlx5_devx_obj *dcs;
4405 offset = cnt_free - &pool->counters_raw[0];
4406 dcs = pool->min_dcs;
4411 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4413 if (!cnt_free->action) {
4418 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4419 (cnt_free - pool->counters_raw));
4420 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4421 /* Update the counter reset values. */
4422 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4426 cnt_ext->shared = shared;
4427 cnt_ext->ref_cnt = 1;
4430 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4431 /* Start the asynchronous batch query by the host thread. */
4432 mlx5_set_query_alarm(priv->sh);
4433 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4434 if (TAILQ_EMPTY(&pool->counters)) {
4435 /* Move the pool to the end of the container pool list. */
4436 TAILQ_REMOVE(&cont->pool_list, pool, next);
4437 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4443 * Release a flow counter.
4446 * Pointer to the Ethernet device structure.
4447 * @param[in] counter
4448 * Index to the counter handler.
4451 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4453 struct mlx5_flow_counter_pool *pool = NULL;
4454 struct mlx5_flow_counter *cnt;
4455 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4459 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4461 if (counter < MLX5_CNT_BATCH_OFFSET) {
4462 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4463 if (cnt_ext && --cnt_ext->ref_cnt)
4466 /* Put the counter in the end - the last updated one. */
4467 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4469 * Counters released between query trigger and handler need
4470 * to wait the next round of query. Since the packets arrive
4471 * in the gap period will not be taken into account to the
4474 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4478 * Verify the @p attributes will be correctly understood by the NIC and store
4479 * them in the @p flow if everything is correct.
4482 * Pointer to dev struct.
4483 * @param[in] attributes
4484 * Pointer to flow attributes
4485 * @param[in] external
4486 * This flow rule is created by request external to PMD.
4488 * Pointer to error structure.
4491 * 0 on success, a negative errno value otherwise and rte_errno is set.
4494 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4495 const struct rte_flow_attr *attributes,
4496 bool external __rte_unused,
4497 struct rte_flow_error *error)
4499 struct mlx5_priv *priv = dev->data->dev_private;
4500 uint32_t priority_max = priv->config.flow_prio - 1;
4502 #ifndef HAVE_MLX5DV_DR
4503 if (attributes->group)
4504 return rte_flow_error_set(error, ENOTSUP,
4505 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4507 "groups are not supported");
4512 ret = mlx5_flow_group_to_table(attributes, external,
4513 attributes->group, !!priv->fdb_def_rule,
4518 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4519 attributes->priority >= priority_max)
4520 return rte_flow_error_set(error, ENOTSUP,
4521 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4523 "priority out of range");
4524 if (attributes->transfer) {
4525 if (!priv->config.dv_esw_en)
4526 return rte_flow_error_set
4528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4529 "E-Switch dr is not supported");
4530 if (!(priv->representor || priv->master))
4531 return rte_flow_error_set
4532 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4533 NULL, "E-Switch configuration can only be"
4534 " done by a master or a representor device");
4535 if (attributes->egress)
4536 return rte_flow_error_set
4538 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4539 "egress is not supported");
4541 if (!(attributes->egress ^ attributes->ingress))
4542 return rte_flow_error_set(error, ENOTSUP,
4543 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4544 "must specify exactly one of "
4545 "ingress or egress");
4550 * Internal validation function. For validating both actions and items.
4553 * Pointer to the rte_eth_dev structure.
4555 * Pointer to the flow attributes.
4557 * Pointer to the list of items.
4558 * @param[in] actions
4559 * Pointer to the list of actions.
4560 * @param[in] external
4561 * This flow rule is created by request external to PMD.
4563 * Pointer to the error structure.
4566 * 0 on success, a negative errno value otherwise and rte_errno is set.
4569 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4570 const struct rte_flow_item items[],
4571 const struct rte_flow_action actions[],
4572 bool external, struct rte_flow_error *error)
4575 uint64_t action_flags = 0;
4576 uint64_t item_flags = 0;
4577 uint64_t last_item = 0;
4578 uint8_t next_protocol = 0xff;
4579 uint16_t ether_type = 0;
4581 uint8_t item_ipv6_proto = 0;
4582 const struct rte_flow_item *gre_item = NULL;
4583 const struct rte_flow_action_raw_decap *decap;
4584 const struct rte_flow_action_raw_encap *encap;
4585 const struct rte_flow_action_rss *rss;
4586 const struct rte_flow_item_tcp nic_tcp_mask = {
4589 .src_port = RTE_BE16(UINT16_MAX),
4590 .dst_port = RTE_BE16(UINT16_MAX),
4593 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4595 .src_addr = RTE_BE32(0xffffffff),
4596 .dst_addr = RTE_BE32(0xffffffff),
4597 .type_of_service = 0xff,
4598 .next_proto_id = 0xff,
4599 .time_to_live = 0xff,
4602 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4605 "\xff\xff\xff\xff\xff\xff\xff\xff"
4606 "\xff\xff\xff\xff\xff\xff\xff\xff",
4608 "\xff\xff\xff\xff\xff\xff\xff\xff"
4609 "\xff\xff\xff\xff\xff\xff\xff\xff",
4610 .vtc_flow = RTE_BE32(0xffffffff),
4615 struct mlx5_priv *priv = dev->data->dev_private;
4616 struct mlx5_dev_config *dev_conf = &priv->config;
4617 uint16_t queue_index = 0xFFFF;
4618 const struct rte_flow_item_vlan *vlan_m = NULL;
4622 ret = flow_dv_validate_attributes(dev, attr, external, error);
4625 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4626 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4627 int type = items->type;
4630 case RTE_FLOW_ITEM_TYPE_VOID:
4632 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4633 ret = flow_dv_validate_item_port_id
4634 (dev, items, attr, item_flags, error);
4637 last_item = MLX5_FLOW_ITEM_PORT_ID;
4639 case RTE_FLOW_ITEM_TYPE_ETH:
4640 ret = mlx5_flow_validate_item_eth(items, item_flags,
4644 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4645 MLX5_FLOW_LAYER_OUTER_L2;
4646 if (items->mask != NULL && items->spec != NULL) {
4648 ((const struct rte_flow_item_eth *)
4651 ((const struct rte_flow_item_eth *)
4653 ether_type = rte_be_to_cpu_16(ether_type);
4658 case RTE_FLOW_ITEM_TYPE_VLAN:
4659 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4663 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4664 MLX5_FLOW_LAYER_OUTER_VLAN;
4665 if (items->mask != NULL && items->spec != NULL) {
4667 ((const struct rte_flow_item_vlan *)
4668 items->spec)->inner_type;
4670 ((const struct rte_flow_item_vlan *)
4671 items->mask)->inner_type;
4672 ether_type = rte_be_to_cpu_16(ether_type);
4676 /* Store outer VLAN mask for of_push_vlan action. */
4678 vlan_m = items->mask;
4680 case RTE_FLOW_ITEM_TYPE_IPV4:
4681 mlx5_flow_tunnel_ip_check(items, next_protocol,
4682 &item_flags, &tunnel);
4683 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4690 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4691 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4692 if (items->mask != NULL &&
4693 ((const struct rte_flow_item_ipv4 *)
4694 items->mask)->hdr.next_proto_id) {
4696 ((const struct rte_flow_item_ipv4 *)
4697 (items->spec))->hdr.next_proto_id;
4699 ((const struct rte_flow_item_ipv4 *)
4700 (items->mask))->hdr.next_proto_id;
4702 /* Reset for inner layer. */
4703 next_protocol = 0xff;
4706 case RTE_FLOW_ITEM_TYPE_IPV6:
4707 mlx5_flow_tunnel_ip_check(items, next_protocol,
4708 &item_flags, &tunnel);
4709 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4716 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4717 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4718 if (items->mask != NULL &&
4719 ((const struct rte_flow_item_ipv6 *)
4720 items->mask)->hdr.proto) {
4722 ((const struct rte_flow_item_ipv6 *)
4723 items->spec)->hdr.proto;
4725 ((const struct rte_flow_item_ipv6 *)
4726 items->spec)->hdr.proto;
4728 ((const struct rte_flow_item_ipv6 *)
4729 items->mask)->hdr.proto;
4731 /* Reset for inner layer. */
4732 next_protocol = 0xff;
4735 case RTE_FLOW_ITEM_TYPE_TCP:
4736 ret = mlx5_flow_validate_item_tcp
4743 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4744 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4746 case RTE_FLOW_ITEM_TYPE_UDP:
4747 ret = mlx5_flow_validate_item_udp(items, item_flags,
4752 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4753 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4755 case RTE_FLOW_ITEM_TYPE_GRE:
4756 ret = mlx5_flow_validate_item_gre(items, item_flags,
4757 next_protocol, error);
4761 last_item = MLX5_FLOW_LAYER_GRE;
4763 case RTE_FLOW_ITEM_TYPE_NVGRE:
4764 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4769 last_item = MLX5_FLOW_LAYER_NVGRE;
4771 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4772 ret = mlx5_flow_validate_item_gre_key
4773 (items, item_flags, gre_item, error);
4776 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4778 case RTE_FLOW_ITEM_TYPE_VXLAN:
4779 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4783 last_item = MLX5_FLOW_LAYER_VXLAN;
4785 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4786 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4791 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4793 case RTE_FLOW_ITEM_TYPE_GENEVE:
4794 ret = mlx5_flow_validate_item_geneve(items,
4799 last_item = MLX5_FLOW_LAYER_GENEVE;
4801 case RTE_FLOW_ITEM_TYPE_MPLS:
4802 ret = mlx5_flow_validate_item_mpls(dev, items,
4807 last_item = MLX5_FLOW_LAYER_MPLS;
4810 case RTE_FLOW_ITEM_TYPE_MARK:
4811 ret = flow_dv_validate_item_mark(dev, items, attr,
4815 last_item = MLX5_FLOW_ITEM_MARK;
4817 case RTE_FLOW_ITEM_TYPE_META:
4818 ret = flow_dv_validate_item_meta(dev, items, attr,
4822 last_item = MLX5_FLOW_ITEM_METADATA;
4824 case RTE_FLOW_ITEM_TYPE_ICMP:
4825 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4830 last_item = MLX5_FLOW_LAYER_ICMP;
4832 case RTE_FLOW_ITEM_TYPE_ICMP6:
4833 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4838 item_ipv6_proto = IPPROTO_ICMPV6;
4839 last_item = MLX5_FLOW_LAYER_ICMP6;
4841 case RTE_FLOW_ITEM_TYPE_TAG:
4842 ret = flow_dv_validate_item_tag(dev, items,
4846 last_item = MLX5_FLOW_ITEM_TAG;
4848 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4849 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4851 case RTE_FLOW_ITEM_TYPE_GTP:
4852 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4856 last_item = MLX5_FLOW_LAYER_GTP;
4859 return rte_flow_error_set(error, ENOTSUP,
4860 RTE_FLOW_ERROR_TYPE_ITEM,
4861 NULL, "item not supported");
4863 item_flags |= last_item;
4865 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4866 int type = actions->type;
4867 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4868 return rte_flow_error_set(error, ENOTSUP,
4869 RTE_FLOW_ERROR_TYPE_ACTION,
4870 actions, "too many actions");
4872 case RTE_FLOW_ACTION_TYPE_VOID:
4874 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4875 ret = flow_dv_validate_action_port_id(dev,
4882 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4885 case RTE_FLOW_ACTION_TYPE_FLAG:
4886 ret = flow_dv_validate_action_flag(dev, action_flags,
4890 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4891 /* Count all modify-header actions as one. */
4892 if (!(action_flags &
4893 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4895 action_flags |= MLX5_FLOW_ACTION_FLAG |
4896 MLX5_FLOW_ACTION_MARK_EXT;
4898 action_flags |= MLX5_FLOW_ACTION_FLAG;
4902 case RTE_FLOW_ACTION_TYPE_MARK:
4903 ret = flow_dv_validate_action_mark(dev, actions,
4908 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4909 /* Count all modify-header actions as one. */
4910 if (!(action_flags &
4911 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4913 action_flags |= MLX5_FLOW_ACTION_MARK |
4914 MLX5_FLOW_ACTION_MARK_EXT;
4916 action_flags |= MLX5_FLOW_ACTION_MARK;
4920 case RTE_FLOW_ACTION_TYPE_SET_META:
4921 ret = flow_dv_validate_action_set_meta(dev, actions,
4926 /* Count all modify-header actions as one action. */
4927 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4929 action_flags |= MLX5_FLOW_ACTION_SET_META;
4931 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4932 ret = flow_dv_validate_action_set_tag(dev, actions,
4937 /* Count all modify-header actions as one action. */
4938 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4940 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4942 case RTE_FLOW_ACTION_TYPE_DROP:
4943 ret = mlx5_flow_validate_action_drop(action_flags,
4947 action_flags |= MLX5_FLOW_ACTION_DROP;
4950 case RTE_FLOW_ACTION_TYPE_QUEUE:
4951 ret = mlx5_flow_validate_action_queue(actions,
4956 queue_index = ((const struct rte_flow_action_queue *)
4957 (actions->conf))->index;
4958 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4961 case RTE_FLOW_ACTION_TYPE_RSS:
4962 rss = actions->conf;
4963 ret = mlx5_flow_validate_action_rss(actions,
4969 if (rss != NULL && rss->queue_num)
4970 queue_index = rss->queue[0];
4971 action_flags |= MLX5_FLOW_ACTION_RSS;
4974 case RTE_FLOW_ACTION_TYPE_COUNT:
4975 ret = flow_dv_validate_action_count(dev, error);
4978 action_flags |= MLX5_FLOW_ACTION_COUNT;
4981 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4982 if (flow_dv_validate_action_pop_vlan(dev,
4988 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4991 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4992 ret = flow_dv_validate_action_push_vlan(dev,
4999 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5002 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5003 ret = flow_dv_validate_action_set_vlan_pcp
5004 (action_flags, actions, error);
5007 /* Count PCP with push_vlan command. */
5008 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5010 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5011 ret = flow_dv_validate_action_set_vlan_vid
5012 (item_flags, action_flags,
5016 /* Count VID with push_vlan command. */
5017 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5019 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5020 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5021 ret = flow_dv_validate_action_l2_encap(dev,
5027 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5030 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5031 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5032 ret = flow_dv_validate_action_decap(dev, action_flags,
5036 action_flags |= MLX5_FLOW_ACTION_DECAP;
5039 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5040 ret = flow_dv_validate_action_raw_encap_decap
5041 (dev, NULL, actions->conf, attr, &action_flags,
5046 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5047 decap = actions->conf;
5048 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5050 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5054 encap = actions->conf;
5056 ret = flow_dv_validate_action_raw_encap_decap
5058 decap ? decap : &empty_decap, encap,
5059 attr, &action_flags, &actions_n,
5064 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5065 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5066 ret = flow_dv_validate_action_modify_mac(action_flags,
5072 /* Count all modify-header actions as one action. */
5073 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5075 action_flags |= actions->type ==
5076 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5077 MLX5_FLOW_ACTION_SET_MAC_SRC :
5078 MLX5_FLOW_ACTION_SET_MAC_DST;
5081 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5082 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5083 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5089 /* Count all modify-header actions as one action. */
5090 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5092 action_flags |= actions->type ==
5093 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5094 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5095 MLX5_FLOW_ACTION_SET_IPV4_DST;
5097 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5098 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5099 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5105 if (item_ipv6_proto == IPPROTO_ICMPV6)
5106 return rte_flow_error_set(error, ENOTSUP,
5107 RTE_FLOW_ERROR_TYPE_ACTION,
5109 "Can't change header "
5110 "with ICMPv6 proto");
5111 /* Count all modify-header actions as one action. */
5112 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5114 action_flags |= actions->type ==
5115 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5116 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5117 MLX5_FLOW_ACTION_SET_IPV6_DST;
5119 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5120 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5121 ret = flow_dv_validate_action_modify_tp(action_flags,
5127 /* Count all modify-header actions as one action. */
5128 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5130 action_flags |= actions->type ==
5131 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5132 MLX5_FLOW_ACTION_SET_TP_SRC :
5133 MLX5_FLOW_ACTION_SET_TP_DST;
5135 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5136 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5137 ret = flow_dv_validate_action_modify_ttl(action_flags,
5143 /* Count all modify-header actions as one action. */
5144 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5146 action_flags |= actions->type ==
5147 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5148 MLX5_FLOW_ACTION_SET_TTL :
5149 MLX5_FLOW_ACTION_DEC_TTL;
5151 case RTE_FLOW_ACTION_TYPE_JUMP:
5152 ret = flow_dv_validate_action_jump(actions,
5159 action_flags |= MLX5_FLOW_ACTION_JUMP;
5161 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5162 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5163 ret = flow_dv_validate_action_modify_tcp_seq
5170 /* Count all modify-header actions as one action. */
5171 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5173 action_flags |= actions->type ==
5174 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5175 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5176 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5178 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5179 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5180 ret = flow_dv_validate_action_modify_tcp_ack
5187 /* Count all modify-header actions as one action. */
5188 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5190 action_flags |= actions->type ==
5191 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5192 MLX5_FLOW_ACTION_INC_TCP_ACK :
5193 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5195 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5196 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5197 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5199 case RTE_FLOW_ACTION_TYPE_METER:
5200 ret = mlx5_flow_validate_action_meter(dev,
5206 action_flags |= MLX5_FLOW_ACTION_METER;
5209 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5210 ret = flow_dv_validate_action_modify_ipv4_dscp
5217 /* Count all modify-header actions as one action. */
5218 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5220 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5222 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5223 ret = flow_dv_validate_action_modify_ipv6_dscp
5230 /* Count all modify-header actions as one action. */
5231 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5233 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5236 return rte_flow_error_set(error, ENOTSUP,
5237 RTE_FLOW_ERROR_TYPE_ACTION,
5239 "action not supported");
5243 * Validate the drop action mutual exclusion with other actions.
5244 * Drop action is mutually-exclusive with any other action, except for
5247 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5248 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5249 return rte_flow_error_set(error, EINVAL,
5250 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5251 "Drop action is mutually-exclusive "
5252 "with any other action, except for "
5254 /* Eswitch has few restrictions on using items and actions */
5255 if (attr->transfer) {
5256 if (!mlx5_flow_ext_mreg_supported(dev) &&
5257 action_flags & MLX5_FLOW_ACTION_FLAG)
5258 return rte_flow_error_set(error, ENOTSUP,
5259 RTE_FLOW_ERROR_TYPE_ACTION,
5261 "unsupported action FLAG");
5262 if (!mlx5_flow_ext_mreg_supported(dev) &&
5263 action_flags & MLX5_FLOW_ACTION_MARK)
5264 return rte_flow_error_set(error, ENOTSUP,
5265 RTE_FLOW_ERROR_TYPE_ACTION,
5267 "unsupported action MARK");
5268 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5269 return rte_flow_error_set(error, ENOTSUP,
5270 RTE_FLOW_ERROR_TYPE_ACTION,
5272 "unsupported action QUEUE");
5273 if (action_flags & MLX5_FLOW_ACTION_RSS)
5274 return rte_flow_error_set(error, ENOTSUP,
5275 RTE_FLOW_ERROR_TYPE_ACTION,
5277 "unsupported action RSS");
5278 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5279 return rte_flow_error_set(error, EINVAL,
5280 RTE_FLOW_ERROR_TYPE_ACTION,
5282 "no fate action is found");
5284 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5285 return rte_flow_error_set(error, EINVAL,
5286 RTE_FLOW_ERROR_TYPE_ACTION,
5288 "no fate action is found");
5290 /* Continue validation for Xcap actions.*/
5291 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5292 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5293 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5294 MLX5_FLOW_XCAP_ACTIONS)
5295 return rte_flow_error_set(error, ENOTSUP,
5296 RTE_FLOW_ERROR_TYPE_ACTION,
5297 NULL, "encap and decap "
5298 "combination aren't supported");
5299 if (!attr->transfer && attr->ingress && (action_flags &
5300 MLX5_FLOW_ACTION_ENCAP))
5301 return rte_flow_error_set(error, ENOTSUP,
5302 RTE_FLOW_ERROR_TYPE_ACTION,
5303 NULL, "encap is not supported"
5304 " for ingress traffic");
5310 * Internal preparation function. Allocates the DV flow size,
5311 * this size is constant.
5314 * Pointer to the rte_eth_dev structure.
5316 * Pointer to the flow attributes.
5318 * Pointer to the list of items.
5319 * @param[in] actions
5320 * Pointer to the list of actions.
5322 * Pointer to the error structure.
5325 * Pointer to mlx5_flow object on success,
5326 * otherwise NULL and rte_errno is set.
5328 static struct mlx5_flow *
5329 flow_dv_prepare(struct rte_eth_dev *dev,
5330 const struct rte_flow_attr *attr __rte_unused,
5331 const struct rte_flow_item items[] __rte_unused,
5332 const struct rte_flow_action actions[] __rte_unused,
5333 struct rte_flow_error *error)
5335 size_t size = sizeof(struct mlx5_flow_handle);
5336 struct mlx5_flow *dev_flow;
5337 struct mlx5_flow_handle *dev_handle;
5338 struct mlx5_priv *priv = dev->data->dev_private;
5340 /* In case of corrupting the memory. */
5341 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5342 rte_flow_error_set(error, ENOSPC,
5343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5344 "not free temporary device flow");
5347 dev_handle = rte_calloc(__func__, 1, size, 0);
5349 rte_flow_error_set(error, ENOMEM,
5350 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5351 "not enough memory to create flow handle");
5354 /* No multi-thread supporting. */
5355 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5356 dev_flow->handle = dev_handle;
5357 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5359 * The matching value needs to be cleared to 0 before using. In the
5360 * past, it will be automatically cleared when using rte_*alloc
5361 * API. The time consumption will be almost the same as before.
5363 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5364 dev_flow->ingress = attr->ingress;
5365 dev_flow->dv.transfer = attr->transfer;
5369 #ifdef RTE_LIBRTE_MLX5_DEBUG
5371 * Sanity check for match mask and value. Similar to check_valid_spec() in
5372 * kernel driver. If unmasked bit is present in value, it returns failure.
5375 * pointer to match mask buffer.
5376 * @param match_value
5377 * pointer to match value buffer.
5380 * 0 if valid, -EINVAL otherwise.
5383 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5385 uint8_t *m = match_mask;
5386 uint8_t *v = match_value;
5389 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5392 "match_value differs from match_criteria"
5393 " %p[%u] != %p[%u]",
5394 match_value, i, match_mask, i);
5403 * Add Ethernet item to matcher and to the value.
5405 * @param[in, out] matcher
5407 * @param[in, out] key
5408 * Flow matcher value.
5410 * Flow pattern to translate.
5412 * Item is inner pattern.
5415 flow_dv_translate_item_eth(void *matcher, void *key,
5416 const struct rte_flow_item *item, int inner)
5418 const struct rte_flow_item_eth *eth_m = item->mask;
5419 const struct rte_flow_item_eth *eth_v = item->spec;
5420 const struct rte_flow_item_eth nic_mask = {
5421 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5422 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5423 .type = RTE_BE16(0xffff),
5435 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5437 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5439 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5441 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5443 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5444 ð_m->dst, sizeof(eth_m->dst));
5445 /* The value must be in the range of the mask. */
5446 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5447 for (i = 0; i < sizeof(eth_m->dst); ++i)
5448 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5449 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5450 ð_m->src, sizeof(eth_m->src));
5451 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5452 /* The value must be in the range of the mask. */
5453 for (i = 0; i < sizeof(eth_m->dst); ++i)
5454 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5456 /* When ethertype is present set mask for tagged VLAN. */
5457 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5458 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5459 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5460 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5461 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5463 /* Return here to avoid setting match on ethertype. */
5468 * HW supports match on one Ethertype, the Ethertype following the last
5469 * VLAN tag of the packet (see PRM).
5470 * Set match on ethertype only if ETH header is not followed by VLAN.
5472 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5473 rte_be_to_cpu_16(eth_m->type));
5474 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5475 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5479 * Add VLAN item to matcher and to the value.
5481 * @param[in, out] dev_flow
5483 * @param[in, out] matcher
5485 * @param[in, out] key
5486 * Flow matcher value.
5488 * Flow pattern to translate.
5490 * Item is inner pattern.
5493 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5494 void *matcher, void *key,
5495 const struct rte_flow_item *item,
5498 const struct rte_flow_item_vlan *vlan_m = item->mask;
5499 const struct rte_flow_item_vlan *vlan_v = item->spec;
5508 vlan_m = &rte_flow_item_vlan_mask;
5510 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5512 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5514 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5516 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5518 * This is workaround, masks are not supported,
5519 * and pre-validated.
5521 dev_flow->handle->vf_vlan.tag =
5522 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5524 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5525 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5526 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5527 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5528 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5531 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5532 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5533 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5534 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5535 rte_be_to_cpu_16(vlan_m->inner_type));
5536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5537 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5541 * Add IPV4 item to matcher and to the value.
5543 * @param[in, out] matcher
5545 * @param[in, out] key
5546 * Flow matcher value.
5548 * Flow pattern to translate.
5549 * @param[in] item_flags
5550 * Bit-fields that holds the items detected until now.
5552 * Item is inner pattern.
5554 * The group to insert the rule.
5557 flow_dv_translate_item_ipv4(void *matcher, void *key,
5558 const struct rte_flow_item *item,
5559 const uint64_t item_flags,
5560 int inner, uint32_t group)
5562 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5563 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5564 const struct rte_flow_item_ipv4 nic_mask = {
5566 .src_addr = RTE_BE32(0xffffffff),
5567 .dst_addr = RTE_BE32(0xffffffff),
5568 .type_of_service = 0xff,
5569 .next_proto_id = 0xff,
5570 .time_to_live = 0xff,
5580 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5582 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5584 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5586 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5589 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5591 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5592 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5594 * On outer header (which must contains L2), or inner header with L2,
5595 * set cvlan_tag mask bit to mark this packet as untagged.
5596 * This should be done even if item->spec is empty.
5598 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5599 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5604 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5605 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5606 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5607 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5608 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5609 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5610 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5611 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5612 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5613 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5614 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5615 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5616 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5617 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5618 ipv4_m->hdr.type_of_service);
5619 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5621 ipv4_m->hdr.type_of_service >> 2);
5622 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5623 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5624 ipv4_m->hdr.next_proto_id);
5625 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5626 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5627 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5628 ipv4_m->hdr.time_to_live);
5629 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5630 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5634 * Add IPV6 item to matcher and to the value.
5636 * @param[in, out] matcher
5638 * @param[in, out] key
5639 * Flow matcher value.
5641 * Flow pattern to translate.
5642 * @param[in] item_flags
5643 * Bit-fields that holds the items detected until now.
5645 * Item is inner pattern.
5647 * The group to insert the rule.
5650 flow_dv_translate_item_ipv6(void *matcher, void *key,
5651 const struct rte_flow_item *item,
5652 const uint64_t item_flags,
5653 int inner, uint32_t group)
5655 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5656 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5657 const struct rte_flow_item_ipv6 nic_mask = {
5660 "\xff\xff\xff\xff\xff\xff\xff\xff"
5661 "\xff\xff\xff\xff\xff\xff\xff\xff",
5663 "\xff\xff\xff\xff\xff\xff\xff\xff"
5664 "\xff\xff\xff\xff\xff\xff\xff\xff",
5665 .vtc_flow = RTE_BE32(0xffffffff),
5672 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5673 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5682 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5684 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5686 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5688 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5691 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5693 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5694 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5696 * On outer header (which must contains L2), or inner header with L2,
5697 * set cvlan_tag mask bit to mark this packet as untagged.
5698 * This should be done even if item->spec is empty.
5700 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5701 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5706 size = sizeof(ipv6_m->hdr.dst_addr);
5707 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5708 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5709 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5710 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5711 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5712 for (i = 0; i < size; ++i)
5713 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5714 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5715 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5716 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5717 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5718 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5719 for (i = 0; i < size; ++i)
5720 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5722 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5723 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5724 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5725 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5730 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5732 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5735 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5737 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5741 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5743 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5744 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5746 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5747 ipv6_m->hdr.hop_limits);
5748 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5749 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5753 * Add TCP item to matcher and to the value.
5755 * @param[in, out] matcher
5757 * @param[in, out] key
5758 * Flow matcher value.
5760 * Flow pattern to translate.
5762 * Item is inner pattern.
5765 flow_dv_translate_item_tcp(void *matcher, void *key,
5766 const struct rte_flow_item *item,
5769 const struct rte_flow_item_tcp *tcp_m = item->mask;
5770 const struct rte_flow_item_tcp *tcp_v = item->spec;
5775 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5777 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5779 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5781 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5783 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5784 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5788 tcp_m = &rte_flow_item_tcp_mask;
5789 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5790 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5791 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5792 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5793 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5794 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5795 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5796 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5797 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5798 tcp_m->hdr.tcp_flags);
5799 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5800 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5804 * Add UDP item to matcher and to the value.
5806 * @param[in, out] matcher
5808 * @param[in, out] key
5809 * Flow matcher value.
5811 * Flow pattern to translate.
5813 * Item is inner pattern.
5816 flow_dv_translate_item_udp(void *matcher, void *key,
5817 const struct rte_flow_item *item,
5820 const struct rte_flow_item_udp *udp_m = item->mask;
5821 const struct rte_flow_item_udp *udp_v = item->spec;
5826 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5828 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5830 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5832 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5834 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5835 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5839 udp_m = &rte_flow_item_udp_mask;
5840 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5841 rte_be_to_cpu_16(udp_m->hdr.src_port));
5842 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5843 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5844 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5845 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5846 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5847 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5851 * Add GRE optional Key item to matcher and to the value.
5853 * @param[in, out] matcher
5855 * @param[in, out] key
5856 * Flow matcher value.
5858 * Flow pattern to translate.
5860 * Item is inner pattern.
5863 flow_dv_translate_item_gre_key(void *matcher, void *key,
5864 const struct rte_flow_item *item)
5866 const rte_be32_t *key_m = item->mask;
5867 const rte_be32_t *key_v = item->spec;
5868 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5869 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5870 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5872 /* GRE K bit must be on and should already be validated */
5873 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5874 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5878 key_m = &gre_key_default_mask;
5879 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5880 rte_be_to_cpu_32(*key_m) >> 8);
5881 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5882 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5883 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5884 rte_be_to_cpu_32(*key_m) & 0xFF);
5885 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5886 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5890 * Add GRE item to matcher and to the value.
5892 * @param[in, out] matcher
5894 * @param[in, out] key
5895 * Flow matcher value.
5897 * Flow pattern to translate.
5899 * Item is inner pattern.
5902 flow_dv_translate_item_gre(void *matcher, void *key,
5903 const struct rte_flow_item *item,
5906 const struct rte_flow_item_gre *gre_m = item->mask;
5907 const struct rte_flow_item_gre *gre_v = item->spec;
5910 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5911 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5918 uint16_t s_present:1;
5919 uint16_t k_present:1;
5920 uint16_t rsvd_bit1:1;
5921 uint16_t c_present:1;
5925 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5928 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5930 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5932 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5934 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5936 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5937 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5941 gre_m = &rte_flow_item_gre_mask;
5942 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5943 rte_be_to_cpu_16(gre_m->protocol));
5944 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5945 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5946 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5947 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5948 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5949 gre_crks_rsvd0_ver_m.c_present);
5950 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5951 gre_crks_rsvd0_ver_v.c_present &
5952 gre_crks_rsvd0_ver_m.c_present);
5953 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5954 gre_crks_rsvd0_ver_m.k_present);
5955 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5956 gre_crks_rsvd0_ver_v.k_present &
5957 gre_crks_rsvd0_ver_m.k_present);
5958 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5959 gre_crks_rsvd0_ver_m.s_present);
5960 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5961 gre_crks_rsvd0_ver_v.s_present &
5962 gre_crks_rsvd0_ver_m.s_present);
5966 * Add NVGRE item to matcher and to the value.
5968 * @param[in, out] matcher
5970 * @param[in, out] key
5971 * Flow matcher value.
5973 * Flow pattern to translate.
5975 * Item is inner pattern.
5978 flow_dv_translate_item_nvgre(void *matcher, void *key,
5979 const struct rte_flow_item *item,
5982 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5983 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5984 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5985 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5986 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5987 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5993 /* For NVGRE, GRE header fields must be set with defined values. */
5994 const struct rte_flow_item_gre gre_spec = {
5995 .c_rsvd0_ver = RTE_BE16(0x2000),
5996 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5998 const struct rte_flow_item_gre gre_mask = {
5999 .c_rsvd0_ver = RTE_BE16(0xB000),
6000 .protocol = RTE_BE16(UINT16_MAX),
6002 const struct rte_flow_item gre_item = {
6007 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6011 nvgre_m = &rte_flow_item_nvgre_mask;
6012 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6013 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6014 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6015 memcpy(gre_key_m, tni_flow_id_m, size);
6016 for (i = 0; i < size; ++i)
6017 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6021 * Add VXLAN item to matcher and to the value.
6023 * @param[in, out] matcher
6025 * @param[in, out] key
6026 * Flow matcher value.
6028 * Flow pattern to translate.
6030 * Item is inner pattern.
6033 flow_dv_translate_item_vxlan(void *matcher, void *key,
6034 const struct rte_flow_item *item,
6037 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6038 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6041 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6042 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6050 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6052 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6054 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6056 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6058 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6059 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6060 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6067 vxlan_m = &rte_flow_item_vxlan_mask;
6068 size = sizeof(vxlan_m->vni);
6069 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6070 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6071 memcpy(vni_m, vxlan_m->vni, size);
6072 for (i = 0; i < size; ++i)
6073 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6077 * Add VXLAN-GPE item to matcher and to the value.
6079 * @param[in, out] matcher
6081 * @param[in, out] key
6082 * Flow matcher value.
6084 * Flow pattern to translate.
6086 * Item is inner pattern.
6090 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6091 const struct rte_flow_item *item, int inner)
6093 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6094 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6098 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6100 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6106 uint8_t flags_m = 0xff;
6107 uint8_t flags_v = 0xc;
6110 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6112 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6114 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6116 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6118 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6119 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6120 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6121 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6122 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6127 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6128 size = sizeof(vxlan_m->vni);
6129 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6130 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6131 memcpy(vni_m, vxlan_m->vni, size);
6132 for (i = 0; i < size; ++i)
6133 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6134 if (vxlan_m->flags) {
6135 flags_m = vxlan_m->flags;
6136 flags_v = vxlan_v->flags;
6138 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6139 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6140 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6142 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6147 * Add Geneve item to matcher and to the value.
6149 * @param[in, out] matcher
6151 * @param[in, out] key
6152 * Flow matcher value.
6154 * Flow pattern to translate.
6156 * Item is inner pattern.
6160 flow_dv_translate_item_geneve(void *matcher, void *key,
6161 const struct rte_flow_item *item, int inner)
6163 const struct rte_flow_item_geneve *geneve_m = item->mask;
6164 const struct rte_flow_item_geneve *geneve_v = item->spec;
6167 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6168 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6177 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6179 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6181 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6183 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6185 dport = MLX5_UDP_PORT_GENEVE;
6186 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6187 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6188 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6193 geneve_m = &rte_flow_item_geneve_mask;
6194 size = sizeof(geneve_m->vni);
6195 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6196 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6197 memcpy(vni_m, geneve_m->vni, size);
6198 for (i = 0; i < size; ++i)
6199 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6200 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6201 rte_be_to_cpu_16(geneve_m->protocol));
6202 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6203 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6204 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6205 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6206 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6207 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6208 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6209 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6210 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6211 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6212 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6213 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6214 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6218 * Add MPLS item to matcher and to the value.
6220 * @param[in, out] matcher
6222 * @param[in, out] key
6223 * Flow matcher value.
6225 * Flow pattern to translate.
6226 * @param[in] prev_layer
6227 * The protocol layer indicated in previous item.
6229 * Item is inner pattern.
6232 flow_dv_translate_item_mpls(void *matcher, void *key,
6233 const struct rte_flow_item *item,
6234 uint64_t prev_layer,
6237 const uint32_t *in_mpls_m = item->mask;
6238 const uint32_t *in_mpls_v = item->spec;
6239 uint32_t *out_mpls_m = 0;
6240 uint32_t *out_mpls_v = 0;
6241 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6242 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6243 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6245 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6246 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6247 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6249 switch (prev_layer) {
6250 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6251 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6252 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6253 MLX5_UDP_PORT_MPLS);
6255 case MLX5_FLOW_LAYER_GRE:
6256 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6257 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6258 RTE_ETHER_TYPE_MPLS);
6261 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6262 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6269 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6270 switch (prev_layer) {
6271 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6273 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6274 outer_first_mpls_over_udp);
6276 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6277 outer_first_mpls_over_udp);
6279 case MLX5_FLOW_LAYER_GRE:
6281 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6282 outer_first_mpls_over_gre);
6284 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6285 outer_first_mpls_over_gre);
6288 /* Inner MPLS not over GRE is not supported. */
6291 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6295 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6301 if (out_mpls_m && out_mpls_v) {
6302 *out_mpls_m = *in_mpls_m;
6303 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6308 * Add metadata register item to matcher
6310 * @param[in, out] matcher
6312 * @param[in, out] key
6313 * Flow matcher value.
6314 * @param[in] reg_type
6315 * Type of device metadata register
6322 flow_dv_match_meta_reg(void *matcher, void *key,
6323 enum modify_reg reg_type,
6324 uint32_t data, uint32_t mask)
6327 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6329 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6335 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6336 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6339 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6340 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6344 * The metadata register C0 field might be divided into
6345 * source vport index and META item value, we should set
6346 * this field according to specified mask, not as whole one.
6348 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6350 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6351 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6354 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6357 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6358 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6361 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6362 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6365 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6366 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6369 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6370 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6373 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6374 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6377 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6378 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6381 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6382 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6391 * Add MARK item to matcher
6394 * The device to configure through.
6395 * @param[in, out] matcher
6397 * @param[in, out] key
6398 * Flow matcher value.
6400 * Flow pattern to translate.
6403 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6404 void *matcher, void *key,
6405 const struct rte_flow_item *item)
6407 struct mlx5_priv *priv = dev->data->dev_private;
6408 const struct rte_flow_item_mark *mark;
6412 mark = item->mask ? (const void *)item->mask :
6413 &rte_flow_item_mark_mask;
6414 mask = mark->id & priv->sh->dv_mark_mask;
6415 mark = (const void *)item->spec;
6417 value = mark->id & priv->sh->dv_mark_mask & mask;
6419 enum modify_reg reg;
6421 /* Get the metadata register index for the mark. */
6422 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6423 MLX5_ASSERT(reg > 0);
6424 if (reg == REG_C_0) {
6425 struct mlx5_priv *priv = dev->data->dev_private;
6426 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6427 uint32_t shl_c0 = rte_bsf32(msk_c0);
6433 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6438 * Add META item to matcher
6441 * The devich to configure through.
6442 * @param[in, out] matcher
6444 * @param[in, out] key
6445 * Flow matcher value.
6447 * Attributes of flow that includes this item.
6449 * Flow pattern to translate.
6452 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6453 void *matcher, void *key,
6454 const struct rte_flow_attr *attr,
6455 const struct rte_flow_item *item)
6457 const struct rte_flow_item_meta *meta_m;
6458 const struct rte_flow_item_meta *meta_v;
6460 meta_m = (const void *)item->mask;
6462 meta_m = &rte_flow_item_meta_mask;
6463 meta_v = (const void *)item->spec;
6466 uint32_t value = meta_v->data;
6467 uint32_t mask = meta_m->data;
6469 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6473 * In datapath code there is no endianness
6474 * coversions for perfromance reasons, all
6475 * pattern conversions are done in rte_flow.
6477 value = rte_cpu_to_be_32(value);
6478 mask = rte_cpu_to_be_32(mask);
6479 if (reg == REG_C_0) {
6480 struct mlx5_priv *priv = dev->data->dev_private;
6481 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6482 uint32_t shl_c0 = rte_bsf32(msk_c0);
6483 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6484 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6491 MLX5_ASSERT(msk_c0);
6492 MLX5_ASSERT(!(~msk_c0 & mask));
6494 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6499 * Add vport metadata Reg C0 item to matcher
6501 * @param[in, out] matcher
6503 * @param[in, out] key
6504 * Flow matcher value.
6506 * Flow pattern to translate.
6509 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6510 uint32_t value, uint32_t mask)
6512 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6516 * Add tag item to matcher
6519 * The devich to configure through.
6520 * @param[in, out] matcher
6522 * @param[in, out] key
6523 * Flow matcher value.
6525 * Flow pattern to translate.
6528 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6529 void *matcher, void *key,
6530 const struct rte_flow_item *item)
6532 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6533 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6534 uint32_t mask, value;
6537 value = tag_v->data;
6538 mask = tag_m ? tag_m->data : UINT32_MAX;
6539 if (tag_v->id == REG_C_0) {
6540 struct mlx5_priv *priv = dev->data->dev_private;
6541 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6542 uint32_t shl_c0 = rte_bsf32(msk_c0);
6548 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6552 * Add TAG item to matcher
6555 * The devich to configure through.
6556 * @param[in, out] matcher
6558 * @param[in, out] key
6559 * Flow matcher value.
6561 * Flow pattern to translate.
6564 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6565 void *matcher, void *key,
6566 const struct rte_flow_item *item)
6568 const struct rte_flow_item_tag *tag_v = item->spec;
6569 const struct rte_flow_item_tag *tag_m = item->mask;
6570 enum modify_reg reg;
6573 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6574 /* Get the metadata register index for the tag. */
6575 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6576 MLX5_ASSERT(reg > 0);
6577 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6581 * Add source vport match to the specified matcher.
6583 * @param[in, out] matcher
6585 * @param[in, out] key
6586 * Flow matcher value.
6588 * Source vport value to match
6593 flow_dv_translate_item_source_vport(void *matcher, void *key,
6594 int16_t port, uint16_t mask)
6596 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6597 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6599 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6600 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6604 * Translate port-id item to eswitch match on port-id.
6607 * The devich to configure through.
6608 * @param[in, out] matcher
6610 * @param[in, out] key
6611 * Flow matcher value.
6613 * Flow pattern to translate.
6616 * 0 on success, a negative errno value otherwise.
6619 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6620 void *key, const struct rte_flow_item *item)
6622 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6623 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6624 struct mlx5_priv *priv;
6627 mask = pid_m ? pid_m->id : 0xffff;
6628 id = pid_v ? pid_v->id : dev->data->port_id;
6629 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6632 /* Translate to vport field or to metadata, depending on mode. */
6633 if (priv->vport_meta_mask)
6634 flow_dv_translate_item_meta_vport(matcher, key,
6635 priv->vport_meta_tag,
6636 priv->vport_meta_mask);
6638 flow_dv_translate_item_source_vport(matcher, key,
6639 priv->vport_id, mask);
6644 * Add ICMP6 item to matcher and to the value.
6646 * @param[in, out] matcher
6648 * @param[in, out] key
6649 * Flow matcher value.
6651 * Flow pattern to translate.
6653 * Item is inner pattern.
6656 flow_dv_translate_item_icmp6(void *matcher, void *key,
6657 const struct rte_flow_item *item,
6660 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6661 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6664 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6666 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6668 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6670 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6672 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6674 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6676 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6681 icmp6_m = &rte_flow_item_icmp6_mask;
6683 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6684 * If only the protocol is specified, no need to match the frag.
6686 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6687 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6688 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6689 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6690 icmp6_v->type & icmp6_m->type);
6691 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6692 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6693 icmp6_v->code & icmp6_m->code);
6697 * Add ICMP item to matcher and to the value.
6699 * @param[in, out] matcher
6701 * @param[in, out] key
6702 * Flow matcher value.
6704 * Flow pattern to translate.
6706 * Item is inner pattern.
6709 flow_dv_translate_item_icmp(void *matcher, void *key,
6710 const struct rte_flow_item *item,
6713 const struct rte_flow_item_icmp *icmp_m = item->mask;
6714 const struct rte_flow_item_icmp *icmp_v = item->spec;
6717 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6719 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6721 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6723 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6725 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6727 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6729 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6734 icmp_m = &rte_flow_item_icmp_mask;
6736 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6737 * If only the protocol is specified, no need to match the frag.
6739 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6740 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6741 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6742 icmp_m->hdr.icmp_type);
6743 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6744 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6745 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6746 icmp_m->hdr.icmp_code);
6747 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6748 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6752 * Add GTP item to matcher and to the value.
6754 * @param[in, out] matcher
6756 * @param[in, out] key
6757 * Flow matcher value.
6759 * Flow pattern to translate.
6761 * Item is inner pattern.
6764 flow_dv_translate_item_gtp(void *matcher, void *key,
6765 const struct rte_flow_item *item, int inner)
6767 const struct rte_flow_item_gtp *gtp_m = item->mask;
6768 const struct rte_flow_item_gtp *gtp_v = item->spec;
6771 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6773 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6774 uint16_t dport = RTE_GTPU_UDP_PORT;
6777 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6779 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6781 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6783 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6785 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6786 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6792 gtp_m = &rte_flow_item_gtp_mask;
6793 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6794 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6795 gtp_v->msg_type & gtp_m->msg_type);
6796 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6797 rte_be_to_cpu_32(gtp_m->teid));
6798 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6799 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6802 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6804 #define HEADER_IS_ZERO(match_criteria, headers) \
6805 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6806 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6809 * Calculate flow matcher enable bitmap.
6811 * @param match_criteria
6812 * Pointer to flow matcher criteria.
6815 * Bitmap of enabled fields.
6818 flow_dv_matcher_enable(uint32_t *match_criteria)
6820 uint8_t match_criteria_enable;
6822 match_criteria_enable =
6823 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6824 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6825 match_criteria_enable |=
6826 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6827 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6828 match_criteria_enable |=
6829 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6830 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6831 match_criteria_enable |=
6832 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6833 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6834 match_criteria_enable |=
6835 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6836 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6837 return match_criteria_enable;
6844 * @param[in, out] dev
6845 * Pointer to rte_eth_dev structure.
6846 * @param[in] table_id
6849 * Direction of the table.
6850 * @param[in] transfer
6851 * E-Switch or NIC flow.
6853 * pointer to error structure.
6856 * Returns tables resource based on the index, NULL in case of failed.
6858 static struct mlx5_flow_tbl_resource *
6859 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6860 uint32_t table_id, uint8_t egress,
6862 struct rte_flow_error *error)
6864 struct mlx5_priv *priv = dev->data->dev_private;
6865 struct mlx5_ibv_shared *sh = priv->sh;
6866 struct mlx5_flow_tbl_resource *tbl;
6867 union mlx5_flow_tbl_key table_key = {
6869 .table_id = table_id,
6871 .domain = !!transfer,
6872 .direction = !!egress,
6875 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6877 struct mlx5_flow_tbl_data_entry *tbl_data;
6882 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6884 tbl = &tbl_data->tbl;
6885 rte_atomic32_inc(&tbl->refcnt);
6888 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6890 rte_flow_error_set(error, ENOMEM,
6891 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6893 "cannot allocate flow table data entry");
6896 tbl = &tbl_data->tbl;
6897 pos = &tbl_data->entry;
6899 domain = sh->fdb_domain;
6901 domain = sh->tx_domain;
6903 domain = sh->rx_domain;
6904 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6906 rte_flow_error_set(error, ENOMEM,
6907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6908 NULL, "cannot create flow table object");
6913 * No multi-threads now, but still better to initialize the reference
6914 * count before insert it into the hash list.
6916 rte_atomic32_init(&tbl->refcnt);
6917 /* Jump action reference count is initialized here. */
6918 rte_atomic32_init(&tbl_data->jump.refcnt);
6919 pos->key = table_key.v64;
6920 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6922 rte_flow_error_set(error, -ret,
6923 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6924 "cannot insert flow table data entry");
6925 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6928 rte_atomic32_inc(&tbl->refcnt);
6933 * Release a flow table.
6936 * Pointer to rte_eth_dev structure.
6938 * Table resource to be released.
6941 * Returns 0 if table was released, else return 1;
6944 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6945 struct mlx5_flow_tbl_resource *tbl)
6947 struct mlx5_priv *priv = dev->data->dev_private;
6948 struct mlx5_ibv_shared *sh = priv->sh;
6949 struct mlx5_flow_tbl_data_entry *tbl_data =
6950 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6954 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6955 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6957 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6959 /* remove the entry from the hash list and free memory. */
6960 mlx5_hlist_remove(sh->flow_tbls, pos);
6968 * Register the flow matcher.
6970 * @param[in, out] dev
6971 * Pointer to rte_eth_dev structure.
6972 * @param[in, out] matcher
6973 * Pointer to flow matcher.
6974 * @param[in, out] key
6975 * Pointer to flow table key.
6976 * @parm[in, out] dev_flow
6977 * Pointer to the dev_flow.
6979 * pointer to error structure.
6982 * 0 on success otherwise -errno and errno is set.
6985 flow_dv_matcher_register(struct rte_eth_dev *dev,
6986 struct mlx5_flow_dv_matcher *matcher,
6987 union mlx5_flow_tbl_key *key,
6988 struct mlx5_flow *dev_flow,
6989 struct rte_flow_error *error)
6991 struct mlx5_priv *priv = dev->data->dev_private;
6992 struct mlx5_ibv_shared *sh = priv->sh;
6993 struct mlx5_flow_dv_matcher *cache_matcher;
6994 struct mlx5dv_flow_matcher_attr dv_attr = {
6995 .type = IBV_FLOW_ATTR_NORMAL,
6996 .match_mask = (void *)&matcher->mask,
6998 struct mlx5_flow_tbl_resource *tbl;
6999 struct mlx5_flow_tbl_data_entry *tbl_data;
7001 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7002 key->domain, error);
7004 return -rte_errno; /* No need to refill the error info */
7005 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7006 /* Lookup from cache. */
7007 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7008 if (matcher->crc == cache_matcher->crc &&
7009 matcher->priority == cache_matcher->priority &&
7010 !memcmp((const void *)matcher->mask.buf,
7011 (const void *)cache_matcher->mask.buf,
7012 cache_matcher->mask.size)) {
7014 "%s group %u priority %hd use %s "
7015 "matcher %p: refcnt %d++",
7016 key->domain ? "FDB" : "NIC", key->table_id,
7017 cache_matcher->priority,
7018 key->direction ? "tx" : "rx",
7019 (void *)cache_matcher,
7020 rte_atomic32_read(&cache_matcher->refcnt));
7021 rte_atomic32_inc(&cache_matcher->refcnt);
7022 dev_flow->handle->dvh.matcher = cache_matcher;
7023 /* old matcher should not make the table ref++. */
7024 flow_dv_tbl_resource_release(dev, tbl);
7028 /* Register new matcher. */
7029 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7030 if (!cache_matcher) {
7031 flow_dv_tbl_resource_release(dev, tbl);
7032 return rte_flow_error_set(error, ENOMEM,
7033 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7034 "cannot allocate matcher memory");
7036 *cache_matcher = *matcher;
7037 dv_attr.match_criteria_enable =
7038 flow_dv_matcher_enable(cache_matcher->mask.buf);
7039 dv_attr.priority = matcher->priority;
7041 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7042 cache_matcher->matcher_object =
7043 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7044 if (!cache_matcher->matcher_object) {
7045 rte_free(cache_matcher);
7046 #ifdef HAVE_MLX5DV_DR
7047 flow_dv_tbl_resource_release(dev, tbl);
7049 return rte_flow_error_set(error, ENOMEM,
7050 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7051 NULL, "cannot create matcher");
7053 /* Save the table information */
7054 cache_matcher->tbl = tbl;
7055 rte_atomic32_init(&cache_matcher->refcnt);
7056 /* only matcher ref++, table ref++ already done above in get API. */
7057 rte_atomic32_inc(&cache_matcher->refcnt);
7058 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7059 dev_flow->handle->dvh.matcher = cache_matcher;
7060 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7061 key->domain ? "FDB" : "NIC", key->table_id,
7062 cache_matcher->priority,
7063 key->direction ? "tx" : "rx", (void *)cache_matcher,
7064 rte_atomic32_read(&cache_matcher->refcnt));
7069 * Find existing tag resource or create and register a new one.
7071 * @param dev[in, out]
7072 * Pointer to rte_eth_dev structure.
7073 * @param[in, out] tag_be24
7074 * Tag value in big endian then R-shift 8.
7075 * @parm[in, out] dev_flow
7076 * Pointer to the dev_flow.
7078 * pointer to error structure.
7081 * 0 on success otherwise -errno and errno is set.
7084 flow_dv_tag_resource_register
7085 (struct rte_eth_dev *dev,
7087 struct mlx5_flow *dev_flow,
7088 struct rte_flow_error *error)
7090 struct mlx5_priv *priv = dev->data->dev_private;
7091 struct mlx5_ibv_shared *sh = priv->sh;
7092 struct mlx5_flow_dv_tag_resource *cache_resource;
7093 struct mlx5_hlist_entry *entry;
7095 /* Lookup a matching resource from cache. */
7096 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7098 cache_resource = container_of
7099 (entry, struct mlx5_flow_dv_tag_resource, entry);
7100 rte_atomic32_inc(&cache_resource->refcnt);
7101 dev_flow->handle->dvh.tag_resource = cache_resource->idx;
7102 dev_flow->dv.tag_resource = cache_resource;
7103 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7104 (void *)cache_resource,
7105 rte_atomic32_read(&cache_resource->refcnt));
7108 /* Register new resource. */
7109 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7110 &dev_flow->handle->dvh.tag_resource);
7111 if (!cache_resource)
7112 return rte_flow_error_set(error, ENOMEM,
7113 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7114 "cannot allocate resource memory");
7115 cache_resource->entry.key = (uint64_t)tag_be24;
7116 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7117 if (!cache_resource->action) {
7118 rte_free(cache_resource);
7119 return rte_flow_error_set(error, ENOMEM,
7120 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7121 NULL, "cannot create action");
7123 rte_atomic32_init(&cache_resource->refcnt);
7124 rte_atomic32_inc(&cache_resource->refcnt);
7125 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7126 mlx5_glue->destroy_flow_action(cache_resource->action);
7127 rte_free(cache_resource);
7128 return rte_flow_error_set(error, EEXIST,
7129 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7130 NULL, "cannot insert tag");
7132 dev_flow->dv.tag_resource = cache_resource;
7133 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7134 (void *)cache_resource,
7135 rte_atomic32_read(&cache_resource->refcnt));
7143 * Pointer to Ethernet device.
7148 * 1 while a reference on it exists, 0 when freed.
7151 flow_dv_tag_release(struct rte_eth_dev *dev,
7154 struct mlx5_priv *priv = dev->data->dev_private;
7155 struct mlx5_ibv_shared *sh = priv->sh;
7156 struct mlx5_flow_dv_tag_resource *tag;
7158 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7161 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7162 dev->data->port_id, (void *)tag,
7163 rte_atomic32_read(&tag->refcnt));
7164 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7165 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7166 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7167 DRV_LOG(DEBUG, "port %u tag %p: removed",
7168 dev->data->port_id, (void *)tag);
7169 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7176 * Translate port ID action to vport.
7179 * Pointer to rte_eth_dev structure.
7181 * Pointer to the port ID action.
7182 * @param[out] dst_port_id
7183 * The target port ID.
7185 * Pointer to the error structure.
7188 * 0 on success, a negative errno value otherwise and rte_errno is set.
7191 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7192 const struct rte_flow_action *action,
7193 uint32_t *dst_port_id,
7194 struct rte_flow_error *error)
7197 struct mlx5_priv *priv;
7198 const struct rte_flow_action_port_id *conf =
7199 (const struct rte_flow_action_port_id *)action->conf;
7201 port = conf->original ? dev->data->port_id : conf->id;
7202 priv = mlx5_port_to_eswitch_info(port, false);
7204 return rte_flow_error_set(error, -rte_errno,
7205 RTE_FLOW_ERROR_TYPE_ACTION,
7207 "No eswitch info was found for port");
7208 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7210 * This parameter is transferred to
7211 * mlx5dv_dr_action_create_dest_ib_port().
7213 *dst_port_id = priv->ibv_port;
7216 * Legacy mode, no LAG configurations is supported.
7217 * This parameter is transferred to
7218 * mlx5dv_dr_action_create_dest_vport().
7220 *dst_port_id = priv->vport_id;
7226 * Add Tx queue matcher
7229 * Pointer to the dev struct.
7230 * @param[in, out] matcher
7232 * @param[in, out] key
7233 * Flow matcher value.
7235 * Flow pattern to translate.
7237 * Item is inner pattern.
7240 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7241 void *matcher, void *key,
7242 const struct rte_flow_item *item)
7244 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7245 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7247 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7249 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7250 struct mlx5_txq_ctrl *txq;
7254 queue_m = (const void *)item->mask;
7257 queue_v = (const void *)item->spec;
7260 txq = mlx5_txq_get(dev, queue_v->queue);
7263 queue = txq->obj->sq->id;
7264 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7265 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7266 queue & queue_m->queue);
7267 mlx5_txq_release(dev, queue_v->queue);
7271 * Set the hash fields according to the @p flow information.
7273 * @param[in] dev_flow
7274 * Pointer to the mlx5_flow.
7277 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7279 struct rte_flow *flow = dev_flow->flow;
7280 uint64_t items = dev_flow->handle->layers;
7282 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7284 dev_flow->hash_fields = 0;
7285 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7286 if (flow->rss.level >= 2) {
7287 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7291 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7292 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7293 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7294 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7295 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7296 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7297 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7299 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7301 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7302 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7303 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7304 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7305 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7306 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7307 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7309 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7312 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7313 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7314 if (rss_types & ETH_RSS_UDP) {
7315 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7316 dev_flow->hash_fields |=
7317 IBV_RX_HASH_SRC_PORT_UDP;
7318 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7319 dev_flow->hash_fields |=
7320 IBV_RX_HASH_DST_PORT_UDP;
7322 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7324 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7325 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7326 if (rss_types & ETH_RSS_TCP) {
7327 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7328 dev_flow->hash_fields |=
7329 IBV_RX_HASH_SRC_PORT_TCP;
7330 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7331 dev_flow->hash_fields |=
7332 IBV_RX_HASH_DST_PORT_TCP;
7334 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7340 * Fill the flow with DV spec, lock free
7341 * (mutex should be acquired by caller).
7344 * Pointer to rte_eth_dev structure.
7345 * @param[in, out] dev_flow
7346 * Pointer to the sub flow.
7348 * Pointer to the flow attributes.
7350 * Pointer to the list of items.
7351 * @param[in] actions
7352 * Pointer to the list of actions.
7354 * Pointer to the error structure.
7357 * 0 on success, a negative errno value otherwise and rte_errno is set.
7360 __flow_dv_translate(struct rte_eth_dev *dev,
7361 struct mlx5_flow *dev_flow,
7362 const struct rte_flow_attr *attr,
7363 const struct rte_flow_item items[],
7364 const struct rte_flow_action actions[],
7365 struct rte_flow_error *error)
7367 struct mlx5_priv *priv = dev->data->dev_private;
7368 struct mlx5_dev_config *dev_conf = &priv->config;
7369 struct rte_flow *flow = dev_flow->flow;
7370 struct mlx5_flow_handle *handle = dev_flow->handle;
7371 uint64_t item_flags = 0;
7372 uint64_t last_item = 0;
7373 uint64_t action_flags = 0;
7374 uint64_t priority = attr->priority;
7375 struct mlx5_flow_dv_matcher matcher = {
7377 .size = sizeof(matcher.mask.buf),
7381 bool actions_end = false;
7383 struct mlx5_flow_dv_modify_hdr_resource res;
7384 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7385 sizeof(struct mlx5_modification_cmd) *
7386 (MLX5_MAX_MODIFY_NUM + 1)];
7388 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7389 union flow_dv_attr flow_attr = { .attr = 0 };
7391 union mlx5_flow_tbl_key tbl_key;
7392 uint32_t modify_action_position = UINT32_MAX;
7393 void *match_mask = matcher.mask.buf;
7394 void *match_value = dev_flow->dv.value.buf;
7395 uint8_t next_protocol = 0xff;
7396 struct rte_vlan_hdr vlan = { 0 };
7400 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7401 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7402 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7403 !!priv->fdb_def_rule, &table, error);
7406 dev_flow->dv.group = table;
7408 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7409 if (priority == MLX5_FLOW_PRIO_RSVD)
7410 priority = dev_conf->flow_prio - 1;
7411 /* number of actions must be set to 0 in case of dirty stack. */
7412 mhdr_res->actions_num = 0;
7413 for (; !actions_end ; actions++) {
7414 const struct rte_flow_action_queue *queue;
7415 const struct rte_flow_action_rss *rss;
7416 const struct rte_flow_action *action = actions;
7417 const struct rte_flow_action_count *count = action->conf;
7418 const uint8_t *rss_key;
7419 const struct rte_flow_action_jump *jump_data;
7420 const struct rte_flow_action_meter *mtr;
7421 struct mlx5_flow_tbl_resource *tbl;
7422 uint32_t port_id = 0;
7423 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7424 int action_type = actions->type;
7425 const struct rte_flow_action *found_action = NULL;
7427 switch (action_type) {
7428 case RTE_FLOW_ACTION_TYPE_VOID:
7430 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7431 if (flow_dv_translate_action_port_id(dev, action,
7434 memset(&port_id_resource, 0, sizeof(port_id_resource));
7435 port_id_resource.port_id = port_id;
7436 if (flow_dv_port_id_action_resource_register
7437 (dev, &port_id_resource, dev_flow, error))
7439 MLX5_ASSERT(!handle->dvh.port_id_action);
7440 dev_flow->dv.actions[actions_n++] =
7441 dev_flow->dv.port_id_action->action;
7442 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7444 case RTE_FLOW_ACTION_TYPE_FLAG:
7445 action_flags |= MLX5_FLOW_ACTION_FLAG;
7446 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7447 struct rte_flow_action_mark mark = {
7448 .id = MLX5_FLOW_MARK_DEFAULT,
7451 if (flow_dv_convert_action_mark(dev, &mark,
7455 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7458 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7460 * Only one FLAG or MARK is supported per device flow
7461 * right now. So the pointer to the tag resource must be
7462 * zero before the register process.
7464 MLX5_ASSERT(!handle->dvh.tag_resource);
7465 if (flow_dv_tag_resource_register(dev, tag_be,
7468 MLX5_ASSERT(dev_flow->dv.tag_resource);
7469 dev_flow->dv.actions[actions_n++] =
7470 dev_flow->dv.tag_resource->action;
7472 case RTE_FLOW_ACTION_TYPE_MARK:
7473 action_flags |= MLX5_FLOW_ACTION_MARK;
7474 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7475 const struct rte_flow_action_mark *mark =
7476 (const struct rte_flow_action_mark *)
7479 if (flow_dv_convert_action_mark(dev, mark,
7483 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7487 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7488 /* Legacy (non-extensive) MARK action. */
7489 tag_be = mlx5_flow_mark_set
7490 (((const struct rte_flow_action_mark *)
7491 (actions->conf))->id);
7492 MLX5_ASSERT(!handle->dvh.tag_resource);
7493 if (flow_dv_tag_resource_register(dev, tag_be,
7496 MLX5_ASSERT(dev_flow->dv.tag_resource);
7497 dev_flow->dv.actions[actions_n++] =
7498 dev_flow->dv.tag_resource->action;
7500 case RTE_FLOW_ACTION_TYPE_SET_META:
7501 if (flow_dv_convert_action_set_meta
7502 (dev, mhdr_res, attr,
7503 (const struct rte_flow_action_set_meta *)
7504 actions->conf, error))
7506 action_flags |= MLX5_FLOW_ACTION_SET_META;
7508 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7509 if (flow_dv_convert_action_set_tag
7511 (const struct rte_flow_action_set_tag *)
7512 actions->conf, error))
7514 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7516 case RTE_FLOW_ACTION_TYPE_DROP:
7517 action_flags |= MLX5_FLOW_ACTION_DROP;
7519 case RTE_FLOW_ACTION_TYPE_QUEUE:
7520 MLX5_ASSERT(flow->rss.queue);
7521 queue = actions->conf;
7522 flow->rss.queue_num = 1;
7523 (*flow->rss.queue)[0] = queue->index;
7524 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7526 case RTE_FLOW_ACTION_TYPE_RSS:
7527 MLX5_ASSERT(flow->rss.queue);
7528 rss = actions->conf;
7529 if (flow->rss.queue)
7530 memcpy((*flow->rss.queue), rss->queue,
7531 rss->queue_num * sizeof(uint16_t));
7532 flow->rss.queue_num = rss->queue_num;
7533 /* NULL RSS key indicates default RSS key. */
7534 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7535 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7537 * rss->level and rss.types should be set in advance
7538 * when expanding items for RSS.
7540 action_flags |= MLX5_FLOW_ACTION_RSS;
7542 case RTE_FLOW_ACTION_TYPE_COUNT:
7543 if (!dev_conf->devx) {
7544 rte_errno = ENOTSUP;
7547 flow->counter = flow_dv_counter_alloc(dev,
7550 dev_flow->dv.group);
7553 dev_flow->dv.actions[actions_n++] =
7554 (flow_dv_counter_get_by_idx(dev,
7555 flow->counter, NULL))->action;
7556 action_flags |= MLX5_FLOW_ACTION_COUNT;
7559 if (rte_errno == ENOTSUP)
7560 return rte_flow_error_set
7562 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7564 "count action not supported");
7566 return rte_flow_error_set
7568 RTE_FLOW_ERROR_TYPE_ACTION,
7570 "cannot create counter"
7573 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7574 dev_flow->dv.actions[actions_n++] =
7575 priv->sh->pop_vlan_action;
7576 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7578 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7579 if (!(action_flags &
7580 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7581 flow_dev_get_vlan_info_from_items(items, &vlan);
7582 vlan.eth_proto = rte_be_to_cpu_16
7583 ((((const struct rte_flow_action_of_push_vlan *)
7584 actions->conf)->ethertype));
7585 found_action = mlx5_flow_find_action
7587 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7589 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7590 found_action = mlx5_flow_find_action
7592 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7594 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7595 if (flow_dv_create_action_push_vlan
7596 (dev, attr, &vlan, dev_flow, error))
7598 dev_flow->dv.actions[actions_n++] =
7599 dev_flow->dv.push_vlan_res->action;
7600 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7602 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7603 /* of_vlan_push action handled this action */
7604 MLX5_ASSERT(action_flags &
7605 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7607 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7608 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7610 flow_dev_get_vlan_info_from_items(items, &vlan);
7611 mlx5_update_vlan_vid_pcp(actions, &vlan);
7612 /* If no VLAN push - this is a modify header action */
7613 if (flow_dv_convert_action_modify_vlan_vid
7614 (mhdr_res, actions, error))
7616 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7618 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7619 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7620 if (flow_dv_create_action_l2_encap(dev, actions,
7625 dev_flow->dv.actions[actions_n++] =
7626 dev_flow->dv.encap_decap->verbs_action;
7627 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7629 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7630 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7631 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7635 dev_flow->dv.actions[actions_n++] =
7636 dev_flow->dv.encap_decap->verbs_action;
7637 action_flags |= MLX5_FLOW_ACTION_DECAP;
7639 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7640 /* Handle encap with preceding decap. */
7641 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7642 if (flow_dv_create_action_raw_encap
7643 (dev, actions, dev_flow, attr, error))
7645 dev_flow->dv.actions[actions_n++] =
7646 dev_flow->dv.encap_decap->verbs_action;
7648 /* Handle encap without preceding decap. */
7649 if (flow_dv_create_action_l2_encap
7650 (dev, actions, dev_flow, attr->transfer,
7653 dev_flow->dv.actions[actions_n++] =
7654 dev_flow->dv.encap_decap->verbs_action;
7656 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7658 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7659 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7661 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7662 if (flow_dv_create_action_l2_decap
7663 (dev, dev_flow, attr->transfer, error))
7665 dev_flow->dv.actions[actions_n++] =
7666 dev_flow->dv.encap_decap->verbs_action;
7668 /* If decap is followed by encap, handle it at encap. */
7669 action_flags |= MLX5_FLOW_ACTION_DECAP;
7671 case RTE_FLOW_ACTION_TYPE_JUMP:
7672 jump_data = action->conf;
7673 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7675 !!priv->fdb_def_rule,
7679 tbl = flow_dv_tbl_resource_get(dev, table,
7681 attr->transfer, error);
7683 return rte_flow_error_set
7685 RTE_FLOW_ERROR_TYPE_ACTION,
7687 "cannot create jump action.");
7688 if (flow_dv_jump_tbl_resource_register
7689 (dev, tbl, dev_flow, error)) {
7690 flow_dv_tbl_resource_release(dev, tbl);
7691 return rte_flow_error_set
7693 RTE_FLOW_ERROR_TYPE_ACTION,
7695 "cannot create jump action.");
7697 dev_flow->dv.actions[actions_n++] =
7698 handle->dvh.jump->action;
7699 action_flags |= MLX5_FLOW_ACTION_JUMP;
7701 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7702 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7703 if (flow_dv_convert_action_modify_mac
7704 (mhdr_res, actions, error))
7706 action_flags |= actions->type ==
7707 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7708 MLX5_FLOW_ACTION_SET_MAC_SRC :
7709 MLX5_FLOW_ACTION_SET_MAC_DST;
7711 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7712 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7713 if (flow_dv_convert_action_modify_ipv4
7714 (mhdr_res, actions, error))
7716 action_flags |= actions->type ==
7717 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7718 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7719 MLX5_FLOW_ACTION_SET_IPV4_DST;
7721 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7722 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7723 if (flow_dv_convert_action_modify_ipv6
7724 (mhdr_res, actions, error))
7726 action_flags |= actions->type ==
7727 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7728 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7729 MLX5_FLOW_ACTION_SET_IPV6_DST;
7731 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7732 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7733 if (flow_dv_convert_action_modify_tp
7734 (mhdr_res, actions, items,
7735 &flow_attr, dev_flow, !!(action_flags &
7736 MLX5_FLOW_ACTION_DECAP), error))
7738 action_flags |= actions->type ==
7739 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7740 MLX5_FLOW_ACTION_SET_TP_SRC :
7741 MLX5_FLOW_ACTION_SET_TP_DST;
7743 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7744 if (flow_dv_convert_action_modify_dec_ttl
7745 (mhdr_res, items, &flow_attr, dev_flow,
7747 MLX5_FLOW_ACTION_DECAP), error))
7749 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7751 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7752 if (flow_dv_convert_action_modify_ttl
7753 (mhdr_res, actions, items, &flow_attr,
7754 dev_flow, !!(action_flags &
7755 MLX5_FLOW_ACTION_DECAP), error))
7757 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7759 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7760 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7761 if (flow_dv_convert_action_modify_tcp_seq
7762 (mhdr_res, actions, error))
7764 action_flags |= actions->type ==
7765 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7766 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7767 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7770 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7771 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7772 if (flow_dv_convert_action_modify_tcp_ack
7773 (mhdr_res, actions, error))
7775 action_flags |= actions->type ==
7776 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7777 MLX5_FLOW_ACTION_INC_TCP_ACK :
7778 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7780 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7781 if (flow_dv_convert_action_set_reg
7782 (mhdr_res, actions, error))
7784 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7786 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7787 if (flow_dv_convert_action_copy_mreg
7788 (dev, mhdr_res, actions, error))
7790 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7792 case RTE_FLOW_ACTION_TYPE_METER:
7793 mtr = actions->conf;
7795 flow->meter = mlx5_flow_meter_attach(priv,
7799 return rte_flow_error_set(error,
7801 RTE_FLOW_ERROR_TYPE_ACTION,
7804 "or invalid parameters");
7806 /* Set the meter action. */
7807 dev_flow->dv.actions[actions_n++] =
7808 flow->meter->mfts->meter_action;
7809 action_flags |= MLX5_FLOW_ACTION_METER;
7811 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7812 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7815 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7817 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7818 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7821 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7823 case RTE_FLOW_ACTION_TYPE_END:
7825 if (mhdr_res->actions_num) {
7826 /* create modify action if needed. */
7827 if (flow_dv_modify_hdr_resource_register
7828 (dev, mhdr_res, dev_flow, error))
7830 dev_flow->dv.actions[modify_action_position] =
7831 handle->dvh.modify_hdr->verbs_action;
7837 if (mhdr_res->actions_num &&
7838 modify_action_position == UINT32_MAX)
7839 modify_action_position = actions_n++;
7841 dev_flow->dv.actions_n = actions_n;
7842 handle->act_flags = action_flags;
7843 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7844 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7845 int item_type = items->type;
7847 switch (item_type) {
7848 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7849 flow_dv_translate_item_port_id(dev, match_mask,
7850 match_value, items);
7851 last_item = MLX5_FLOW_ITEM_PORT_ID;
7853 case RTE_FLOW_ITEM_TYPE_ETH:
7854 flow_dv_translate_item_eth(match_mask, match_value,
7856 matcher.priority = MLX5_PRIORITY_MAP_L2;
7857 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7858 MLX5_FLOW_LAYER_OUTER_L2;
7860 case RTE_FLOW_ITEM_TYPE_VLAN:
7861 flow_dv_translate_item_vlan(dev_flow,
7862 match_mask, match_value,
7864 matcher.priority = MLX5_PRIORITY_MAP_L2;
7865 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7866 MLX5_FLOW_LAYER_INNER_VLAN) :
7867 (MLX5_FLOW_LAYER_OUTER_L2 |
7868 MLX5_FLOW_LAYER_OUTER_VLAN);
7870 case RTE_FLOW_ITEM_TYPE_IPV4:
7871 mlx5_flow_tunnel_ip_check(items, next_protocol,
7872 &item_flags, &tunnel);
7873 flow_dv_translate_item_ipv4(match_mask, match_value,
7874 items, item_flags, tunnel,
7875 dev_flow->dv.group);
7876 matcher.priority = MLX5_PRIORITY_MAP_L3;
7877 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7878 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7879 if (items->mask != NULL &&
7880 ((const struct rte_flow_item_ipv4 *)
7881 items->mask)->hdr.next_proto_id) {
7883 ((const struct rte_flow_item_ipv4 *)
7884 (items->spec))->hdr.next_proto_id;
7886 ((const struct rte_flow_item_ipv4 *)
7887 (items->mask))->hdr.next_proto_id;
7889 /* Reset for inner layer. */
7890 next_protocol = 0xff;
7893 case RTE_FLOW_ITEM_TYPE_IPV6:
7894 mlx5_flow_tunnel_ip_check(items, next_protocol,
7895 &item_flags, &tunnel);
7896 flow_dv_translate_item_ipv6(match_mask, match_value,
7897 items, item_flags, tunnel,
7898 dev_flow->dv.group);
7899 matcher.priority = MLX5_PRIORITY_MAP_L3;
7900 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7901 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7902 if (items->mask != NULL &&
7903 ((const struct rte_flow_item_ipv6 *)
7904 items->mask)->hdr.proto) {
7906 ((const struct rte_flow_item_ipv6 *)
7907 items->spec)->hdr.proto;
7909 ((const struct rte_flow_item_ipv6 *)
7910 items->mask)->hdr.proto;
7912 /* Reset for inner layer. */
7913 next_protocol = 0xff;
7916 case RTE_FLOW_ITEM_TYPE_TCP:
7917 flow_dv_translate_item_tcp(match_mask, match_value,
7919 matcher.priority = MLX5_PRIORITY_MAP_L4;
7920 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7921 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7923 case RTE_FLOW_ITEM_TYPE_UDP:
7924 flow_dv_translate_item_udp(match_mask, match_value,
7926 matcher.priority = MLX5_PRIORITY_MAP_L4;
7927 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7928 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7930 case RTE_FLOW_ITEM_TYPE_GRE:
7931 flow_dv_translate_item_gre(match_mask, match_value,
7933 matcher.priority = flow->rss.level >= 2 ?
7934 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7935 last_item = MLX5_FLOW_LAYER_GRE;
7937 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7938 flow_dv_translate_item_gre_key(match_mask,
7939 match_value, items);
7940 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7942 case RTE_FLOW_ITEM_TYPE_NVGRE:
7943 flow_dv_translate_item_nvgre(match_mask, match_value,
7945 matcher.priority = flow->rss.level >= 2 ?
7946 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7947 last_item = MLX5_FLOW_LAYER_GRE;
7949 case RTE_FLOW_ITEM_TYPE_VXLAN:
7950 flow_dv_translate_item_vxlan(match_mask, match_value,
7952 matcher.priority = flow->rss.level >= 2 ?
7953 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7954 last_item = MLX5_FLOW_LAYER_VXLAN;
7956 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7957 flow_dv_translate_item_vxlan_gpe(match_mask,
7960 matcher.priority = flow->rss.level >= 2 ?
7961 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7962 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7964 case RTE_FLOW_ITEM_TYPE_GENEVE:
7965 flow_dv_translate_item_geneve(match_mask, match_value,
7967 matcher.priority = flow->rss.level >= 2 ?
7968 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7969 last_item = MLX5_FLOW_LAYER_GENEVE;
7971 case RTE_FLOW_ITEM_TYPE_MPLS:
7972 flow_dv_translate_item_mpls(match_mask, match_value,
7973 items, last_item, tunnel);
7974 matcher.priority = flow->rss.level >= 2 ?
7975 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7976 last_item = MLX5_FLOW_LAYER_MPLS;
7978 case RTE_FLOW_ITEM_TYPE_MARK:
7979 flow_dv_translate_item_mark(dev, match_mask,
7980 match_value, items);
7981 last_item = MLX5_FLOW_ITEM_MARK;
7983 case RTE_FLOW_ITEM_TYPE_META:
7984 flow_dv_translate_item_meta(dev, match_mask,
7985 match_value, attr, items);
7986 last_item = MLX5_FLOW_ITEM_METADATA;
7988 case RTE_FLOW_ITEM_TYPE_ICMP:
7989 flow_dv_translate_item_icmp(match_mask, match_value,
7991 last_item = MLX5_FLOW_LAYER_ICMP;
7993 case RTE_FLOW_ITEM_TYPE_ICMP6:
7994 flow_dv_translate_item_icmp6(match_mask, match_value,
7996 last_item = MLX5_FLOW_LAYER_ICMP6;
7998 case RTE_FLOW_ITEM_TYPE_TAG:
7999 flow_dv_translate_item_tag(dev, match_mask,
8000 match_value, items);
8001 last_item = MLX5_FLOW_ITEM_TAG;
8003 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8004 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8005 match_value, items);
8006 last_item = MLX5_FLOW_ITEM_TAG;
8008 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8009 flow_dv_translate_item_tx_queue(dev, match_mask,
8012 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8014 case RTE_FLOW_ITEM_TYPE_GTP:
8015 flow_dv_translate_item_gtp(match_mask, match_value,
8017 matcher.priority = flow->rss.level >= 2 ?
8018 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8019 last_item = MLX5_FLOW_LAYER_GTP;
8024 item_flags |= last_item;
8027 * When E-Switch mode is enabled, we have two cases where we need to
8028 * set the source port manually.
8029 * The first one, is in case of Nic steering rule, and the second is
8030 * E-Switch rule where no port_id item was found. In both cases
8031 * the source port is set according the current port in use.
8033 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8034 (priv->representor || priv->master)) {
8035 if (flow_dv_translate_item_port_id(dev, match_mask,
8039 #ifdef RTE_LIBRTE_MLX5_DEBUG
8040 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8041 dev_flow->dv.value.buf));
8044 * Layers may be already initialized from prefix flow if this dev_flow
8045 * is the suffix flow.
8047 handle->layers |= item_flags;
8048 if (action_flags & MLX5_FLOW_ACTION_RSS)
8049 flow_dv_hashfields_set(dev_flow);
8050 /* Register matcher. */
8051 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8053 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8055 /* reserved field no needs to be set to 0 here. */
8056 tbl_key.domain = attr->transfer;
8057 tbl_key.direction = attr->egress;
8058 tbl_key.table_id = dev_flow->dv.group;
8059 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8065 * Apply the flow to the NIC, lock free,
8066 * (mutex should be acquired by caller).
8069 * Pointer to the Ethernet device structure.
8070 * @param[in, out] flow
8071 * Pointer to flow structure.
8073 * Pointer to error structure.
8076 * 0 on success, a negative errno value otherwise and rte_errno is set.
8079 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8080 struct rte_flow_error *error)
8082 struct mlx5_flow_dv_workspace *dv;
8083 struct mlx5_flow_handle *dh;
8084 struct mlx5_flow_handle_dv *dv_h;
8085 struct mlx5_flow *dev_flow;
8086 struct mlx5_priv *priv = dev->data->dev_private;
8091 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8092 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8094 dh = dev_flow->handle;
8097 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8099 dv->actions[n++] = priv->sh->esw_drop_action;
8101 dh->hrxq = mlx5_hrxq_drop_new(dev);
8105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8107 "cannot get drop hash queue");
8110 dv->actions[n++] = dh->hrxq->action;
8112 } else if (dh->act_flags &
8113 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8114 struct mlx5_hrxq *hrxq;
8116 MLX5_ASSERT(flow->rss.queue);
8117 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8118 MLX5_RSS_HASH_KEY_LEN,
8119 dev_flow->hash_fields,
8121 flow->rss.queue_num);
8123 hrxq = mlx5_hrxq_new
8124 (dev, flow->rss.key,
8125 MLX5_RSS_HASH_KEY_LEN,
8126 dev_flow->hash_fields,
8128 flow->rss.queue_num,
8130 MLX5_FLOW_LAYER_TUNNEL));
8135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8136 "cannot get hash queue");
8140 dv->actions[n++] = dh->hrxq->action;
8143 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8144 (void *)&dv->value, n,
8147 rte_flow_error_set(error, errno,
8148 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8150 "hardware refuses to create flow");
8153 if (priv->vmwa_context &&
8154 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8156 * The rule contains the VLAN pattern.
8157 * For VF we are going to create VLAN
8158 * interface to make hypervisor set correct
8159 * e-Switch vport context.
8161 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8166 err = rte_errno; /* Save rte_errno before cleanup. */
8167 LIST_FOREACH(dh, &flow->dev_handles, next) {
8169 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8170 mlx5_hrxq_drop_release(dev);
8172 mlx5_hrxq_release(dev, dh->hrxq);
8175 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8176 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8178 rte_errno = err; /* Restore rte_errno. */
8183 * Release the flow matcher.
8186 * Pointer to Ethernet device.
8188 * Pointer to mlx5_flow_handle.
8191 * 1 while a reference on it exists, 0 when freed.
8194 flow_dv_matcher_release(struct rte_eth_dev *dev,
8195 struct mlx5_flow_handle *handle)
8197 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8199 MLX5_ASSERT(matcher->matcher_object);
8200 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8201 dev->data->port_id, (void *)matcher,
8202 rte_atomic32_read(&matcher->refcnt));
8203 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8204 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8205 (matcher->matcher_object));
8206 LIST_REMOVE(matcher, next);
8207 /* table ref-- in release interface. */
8208 flow_dv_tbl_resource_release(dev, matcher->tbl);
8210 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8211 dev->data->port_id, (void *)matcher);
8218 * Release an encap/decap resource.
8221 * Pointer to Ethernet device.
8223 * Pointer to mlx5_flow_handle.
8226 * 1 while a reference on it exists, 0 when freed.
8229 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8230 struct mlx5_flow_handle *handle)
8232 struct mlx5_priv *priv = dev->data->dev_private;
8233 uint32_t idx = handle->dvh.encap_decap;
8234 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8236 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8238 if (!cache_resource)
8240 MLX5_ASSERT(cache_resource->verbs_action);
8241 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8242 (void *)cache_resource,
8243 rte_atomic32_read(&cache_resource->refcnt));
8244 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8245 claim_zero(mlx5_glue->destroy_flow_action
8246 (cache_resource->verbs_action));
8247 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8248 &priv->sh->encaps_decaps, idx,
8249 cache_resource, next);
8250 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8251 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8252 (void *)cache_resource);
8259 * Release an jump to table action resource.
8262 * Pointer to Ethernet device.
8264 * Pointer to mlx5_flow_handle.
8267 * 1 while a reference on it exists, 0 when freed.
8270 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8271 struct mlx5_flow_handle *handle)
8273 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8275 struct mlx5_flow_tbl_data_entry *tbl_data =
8276 container_of(cache_resource,
8277 struct mlx5_flow_tbl_data_entry, jump);
8279 MLX5_ASSERT(cache_resource->action);
8280 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8281 (void *)cache_resource,
8282 rte_atomic32_read(&cache_resource->refcnt));
8283 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8284 claim_zero(mlx5_glue->destroy_flow_action
8285 (cache_resource->action));
8286 /* jump action memory free is inside the table release. */
8287 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8288 DRV_LOG(DEBUG, "jump table resource %p: removed",
8289 (void *)cache_resource);
8296 * Release a modify-header resource.
8299 * Pointer to mlx5_flow_handle.
8302 * 1 while a reference on it exists, 0 when freed.
8305 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8307 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8308 handle->dvh.modify_hdr;
8310 MLX5_ASSERT(cache_resource->verbs_action);
8311 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8312 (void *)cache_resource,
8313 rte_atomic32_read(&cache_resource->refcnt));
8314 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8315 claim_zero(mlx5_glue->destroy_flow_action
8316 (cache_resource->verbs_action));
8317 LIST_REMOVE(cache_resource, next);
8318 rte_free(cache_resource);
8319 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8320 (void *)cache_resource);
8327 * Release port ID action resource.
8330 * Pointer to Ethernet device.
8332 * Pointer to mlx5_flow_handle.
8335 * 1 while a reference on it exists, 0 when freed.
8338 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8339 struct mlx5_flow_handle *handle)
8341 struct mlx5_priv *priv = dev->data->dev_private;
8342 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8343 uint32_t idx = handle->dvh.port_id_action;
8345 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8347 if (!cache_resource)
8349 MLX5_ASSERT(cache_resource->action);
8350 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8351 (void *)cache_resource,
8352 rte_atomic32_read(&cache_resource->refcnt));
8353 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8354 claim_zero(mlx5_glue->destroy_flow_action
8355 (cache_resource->action));
8356 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8357 &priv->sh->port_id_action_list, idx,
8358 cache_resource, next);
8359 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8360 DRV_LOG(DEBUG, "port id action resource %p: removed",
8361 (void *)cache_resource);
8368 * Release push vlan action resource.
8371 * Pointer to Ethernet device.
8373 * Pointer to mlx5_flow_handle.
8376 * 1 while a reference on it exists, 0 when freed.
8379 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8380 struct mlx5_flow_handle *handle)
8382 struct mlx5_priv *priv = dev->data->dev_private;
8383 uint32_t idx = handle->dvh.push_vlan_res;
8384 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8386 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8388 if (!cache_resource)
8390 MLX5_ASSERT(cache_resource->action);
8391 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8392 (void *)cache_resource,
8393 rte_atomic32_read(&cache_resource->refcnt));
8394 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8395 claim_zero(mlx5_glue->destroy_flow_action
8396 (cache_resource->action));
8397 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8398 &priv->sh->push_vlan_action_list, idx,
8399 cache_resource, next);
8400 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8401 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8402 (void *)cache_resource);
8409 * Remove the flow from the NIC but keeps it in memory.
8410 * Lock free, (mutex should be acquired by caller).
8413 * Pointer to Ethernet device.
8414 * @param[in, out] flow
8415 * Pointer to flow structure.
8418 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8420 struct mlx5_flow_handle *dh;
8424 LIST_FOREACH(dh, &flow->dev_handles, next) {
8426 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8430 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8431 mlx5_hrxq_drop_release(dev);
8433 mlx5_hrxq_release(dev, dh->hrxq);
8436 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8437 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8442 * Remove the flow from the NIC and the memory.
8443 * Lock free, (mutex should be acquired by caller).
8446 * Pointer to the Ethernet device structure.
8447 * @param[in, out] flow
8448 * Pointer to flow structure.
8451 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8453 struct mlx5_flow_handle *dev_handle;
8457 __flow_dv_remove(dev, flow);
8458 if (flow->counter) {
8459 flow_dv_counter_release(dev, flow->counter);
8463 mlx5_flow_meter_detach(flow->meter);
8466 while (!LIST_EMPTY(&flow->dev_handles)) {
8467 dev_handle = LIST_FIRST(&flow->dev_handles);
8468 LIST_REMOVE(dev_handle, next);
8469 if (dev_handle->dvh.matcher)
8470 flow_dv_matcher_release(dev, dev_handle);
8471 if (dev_handle->dvh.encap_decap)
8472 flow_dv_encap_decap_resource_release(dev, dev_handle);
8473 if (dev_handle->dvh.modify_hdr)
8474 flow_dv_modify_hdr_resource_release(dev_handle);
8475 if (dev_handle->dvh.jump)
8476 flow_dv_jump_tbl_resource_release(dev, dev_handle);
8477 if (dev_handle->dvh.port_id_action)
8478 flow_dv_port_id_action_resource_release(dev,
8480 if (dev_handle->dvh.push_vlan_res)
8481 flow_dv_push_vlan_action_resource_release(dev,
8483 if (dev_handle->dvh.tag_resource)
8484 flow_dv_tag_release(dev,
8485 dev_handle->dvh.tag_resource);
8486 rte_free(dev_handle);
8491 * Query a dv flow rule for its statistics via devx.
8494 * Pointer to Ethernet device.
8496 * Pointer to the sub flow.
8498 * data retrieved by the query.
8500 * Perform verbose error reporting if not NULL.
8503 * 0 on success, a negative errno value otherwise and rte_errno is set.
8506 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8507 void *data, struct rte_flow_error *error)
8509 struct mlx5_priv *priv = dev->data->dev_private;
8510 struct rte_flow_query_count *qc = data;
8512 if (!priv->config.devx)
8513 return rte_flow_error_set(error, ENOTSUP,
8514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8516 "counters are not supported");
8517 if (flow->counter) {
8518 uint64_t pkts, bytes;
8519 struct mlx5_flow_counter *cnt;
8521 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8523 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8527 return rte_flow_error_set(error, -err,
8528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8529 NULL, "cannot read counters");
8532 qc->hits = pkts - cnt->hits;
8533 qc->bytes = bytes - cnt->bytes;
8540 return rte_flow_error_set(error, EINVAL,
8541 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8543 "counters are not available");
8549 * @see rte_flow_query()
8553 flow_dv_query(struct rte_eth_dev *dev,
8554 struct rte_flow *flow __rte_unused,
8555 const struct rte_flow_action *actions __rte_unused,
8556 void *data __rte_unused,
8557 struct rte_flow_error *error __rte_unused)
8561 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8562 switch (actions->type) {
8563 case RTE_FLOW_ACTION_TYPE_VOID:
8565 case RTE_FLOW_ACTION_TYPE_COUNT:
8566 ret = flow_dv_query_count(dev, flow, data, error);
8569 return rte_flow_error_set(error, ENOTSUP,
8570 RTE_FLOW_ERROR_TYPE_ACTION,
8572 "action not supported");
8579 * Destroy the meter table set.
8580 * Lock free, (mutex should be acquired by caller).
8583 * Pointer to Ethernet device.
8585 * Pointer to the meter table set.
8591 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8592 struct mlx5_meter_domains_infos *tbl)
8594 struct mlx5_priv *priv = dev->data->dev_private;
8595 struct mlx5_meter_domains_infos *mtd =
8596 (struct mlx5_meter_domains_infos *)tbl;
8598 if (!mtd || !priv->config.dv_flow_en)
8600 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8601 claim_zero(mlx5_glue->dv_destroy_flow
8602 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8603 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8604 claim_zero(mlx5_glue->dv_destroy_flow
8605 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8606 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8607 claim_zero(mlx5_glue->dv_destroy_flow
8608 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8609 if (mtd->egress.color_matcher)
8610 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8611 (mtd->egress.color_matcher));
8612 if (mtd->egress.any_matcher)
8613 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8614 (mtd->egress.any_matcher));
8615 if (mtd->egress.tbl)
8616 claim_zero(flow_dv_tbl_resource_release(dev,
8618 if (mtd->egress.sfx_tbl)
8619 claim_zero(flow_dv_tbl_resource_release(dev,
8620 mtd->egress.sfx_tbl));
8621 if (mtd->ingress.color_matcher)
8622 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8623 (mtd->ingress.color_matcher));
8624 if (mtd->ingress.any_matcher)
8625 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8626 (mtd->ingress.any_matcher));
8627 if (mtd->ingress.tbl)
8628 claim_zero(flow_dv_tbl_resource_release(dev,
8630 if (mtd->ingress.sfx_tbl)
8631 claim_zero(flow_dv_tbl_resource_release(dev,
8632 mtd->ingress.sfx_tbl));
8633 if (mtd->transfer.color_matcher)
8634 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8635 (mtd->transfer.color_matcher));
8636 if (mtd->transfer.any_matcher)
8637 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8638 (mtd->transfer.any_matcher));
8639 if (mtd->transfer.tbl)
8640 claim_zero(flow_dv_tbl_resource_release(dev,
8641 mtd->transfer.tbl));
8642 if (mtd->transfer.sfx_tbl)
8643 claim_zero(flow_dv_tbl_resource_release(dev,
8644 mtd->transfer.sfx_tbl));
8646 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8651 /* Number of meter flow actions, count and jump or count and drop. */
8652 #define METER_ACTIONS 2
8655 * Create specify domain meter table and suffix table.
8658 * Pointer to Ethernet device.
8659 * @param[in,out] mtb
8660 * Pointer to DV meter table set.
8663 * @param[in] transfer
8665 * @param[in] color_reg_c_idx
8666 * Reg C index for color match.
8669 * 0 on success, -1 otherwise and rte_errno is set.
8672 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8673 struct mlx5_meter_domains_infos *mtb,
8674 uint8_t egress, uint8_t transfer,
8675 uint32_t color_reg_c_idx)
8677 struct mlx5_priv *priv = dev->data->dev_private;
8678 struct mlx5_ibv_shared *sh = priv->sh;
8679 struct mlx5_flow_dv_match_params mask = {
8680 .size = sizeof(mask.buf),
8682 struct mlx5_flow_dv_match_params value = {
8683 .size = sizeof(value.buf),
8685 struct mlx5dv_flow_matcher_attr dv_attr = {
8686 .type = IBV_FLOW_ATTR_NORMAL,
8688 .match_criteria_enable = 0,
8689 .match_mask = (void *)&mask,
8691 void *actions[METER_ACTIONS];
8692 struct mlx5_meter_domain_info *dtb;
8693 struct rte_flow_error error;
8697 dtb = &mtb->transfer;
8701 dtb = &mtb->ingress;
8702 /* Create the meter table with METER level. */
8703 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8704 egress, transfer, &error);
8706 DRV_LOG(ERR, "Failed to create meter policer table.");
8709 /* Create the meter suffix table with SUFFIX level. */
8710 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8711 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8712 egress, transfer, &error);
8713 if (!dtb->sfx_tbl) {
8714 DRV_LOG(ERR, "Failed to create meter suffix table.");
8717 /* Create matchers, Any and Color. */
8718 dv_attr.priority = 3;
8719 dv_attr.match_criteria_enable = 0;
8720 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8723 if (!dtb->any_matcher) {
8724 DRV_LOG(ERR, "Failed to create meter"
8725 " policer default matcher.");
8728 dv_attr.priority = 0;
8729 dv_attr.match_criteria_enable =
8730 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8731 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8732 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8733 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8736 if (!dtb->color_matcher) {
8737 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8740 if (mtb->count_actns[RTE_MTR_DROPPED])
8741 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8742 actions[i++] = mtb->drop_actn;
8743 /* Default rule: lowest priority, match any, actions: drop. */
8744 dtb->policer_rules[RTE_MTR_DROPPED] =
8745 mlx5_glue->dv_create_flow(dtb->any_matcher,
8746 (void *)&value, i, actions);
8747 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8748 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8757 * Create the needed meter and suffix tables.
8758 * Lock free, (mutex should be acquired by caller).
8761 * Pointer to Ethernet device.
8763 * Pointer to the flow meter.
8766 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8768 static struct mlx5_meter_domains_infos *
8769 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8770 const struct mlx5_flow_meter *fm)
8772 struct mlx5_priv *priv = dev->data->dev_private;
8773 struct mlx5_meter_domains_infos *mtb;
8777 if (!priv->mtr_en) {
8778 rte_errno = ENOTSUP;
8781 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8783 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8786 /* Create meter count actions */
8787 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8788 struct mlx5_flow_counter *cnt;
8789 if (!fm->policer_stats.cnt[i])
8791 cnt = flow_dv_counter_get_by_idx(dev,
8792 fm->policer_stats.cnt[i], NULL);
8793 mtb->count_actns[i] = cnt->action;
8795 /* Create drop action. */
8796 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8797 if (!mtb->drop_actn) {
8798 DRV_LOG(ERR, "Failed to create drop action.");
8801 /* Egress meter table. */
8802 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8804 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8807 /* Ingress meter table. */
8808 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8810 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8813 /* FDB meter table. */
8814 if (priv->config.dv_esw_en) {
8815 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8816 priv->mtr_color_reg);
8818 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8824 flow_dv_destroy_mtr_tbl(dev, mtb);
8829 * Destroy domain policer rule.
8832 * Pointer to domain table.
8835 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8839 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8840 if (dt->policer_rules[i]) {
8841 claim_zero(mlx5_glue->dv_destroy_flow
8842 (dt->policer_rules[i]));
8843 dt->policer_rules[i] = NULL;
8846 if (dt->jump_actn) {
8847 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8848 dt->jump_actn = NULL;
8853 * Destroy policer rules.
8856 * Pointer to Ethernet device.
8858 * Pointer to flow meter structure.
8860 * Pointer to flow attributes.
8866 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8867 const struct mlx5_flow_meter *fm,
8868 const struct rte_flow_attr *attr)
8870 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8875 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8877 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8879 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8884 * Create specify domain meter policer rule.
8887 * Pointer to flow meter structure.
8889 * Pointer to DV meter table set.
8890 * @param[in] mtr_reg_c
8891 * Color match REG_C.
8894 * 0 on success, -1 otherwise.
8897 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8898 struct mlx5_meter_domain_info *dtb,
8901 struct mlx5_flow_dv_match_params matcher = {
8902 .size = sizeof(matcher.buf),
8904 struct mlx5_flow_dv_match_params value = {
8905 .size = sizeof(value.buf),
8907 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8908 void *actions[METER_ACTIONS];
8911 /* Create jump action. */
8912 if (!dtb->jump_actn)
8914 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8915 (dtb->sfx_tbl->obj);
8916 if (!dtb->jump_actn) {
8917 DRV_LOG(ERR, "Failed to create policer jump action.");
8920 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8923 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8924 rte_col_2_mlx5_col(i), UINT8_MAX);
8925 if (mtb->count_actns[i])
8926 actions[j++] = mtb->count_actns[i];
8927 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8928 actions[j++] = mtb->drop_actn;
8930 actions[j++] = dtb->jump_actn;
8931 dtb->policer_rules[i] =
8932 mlx5_glue->dv_create_flow(dtb->color_matcher,
8935 if (!dtb->policer_rules[i]) {
8936 DRV_LOG(ERR, "Failed to create policer rule.");
8947 * Create policer rules.
8950 * Pointer to Ethernet device.
8952 * Pointer to flow meter structure.
8954 * Pointer to flow attributes.
8957 * 0 on success, -1 otherwise.
8960 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8961 struct mlx5_flow_meter *fm,
8962 const struct rte_flow_attr *attr)
8964 struct mlx5_priv *priv = dev->data->dev_private;
8965 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8969 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8970 priv->mtr_color_reg);
8972 DRV_LOG(ERR, "Failed to create egress policer.");
8976 if (attr->ingress) {
8977 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8978 priv->mtr_color_reg);
8980 DRV_LOG(ERR, "Failed to create ingress policer.");
8984 if (attr->transfer) {
8985 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8986 priv->mtr_color_reg);
8988 DRV_LOG(ERR, "Failed to create transfer policer.");
8994 flow_dv_destroy_policer_rules(dev, fm, attr);
8999 * Query a devx counter.
9002 * Pointer to the Ethernet device structure.
9004 * Index to the flow counter.
9006 * Set to clear the counter statistics.
9008 * The statistics value of packets.
9010 * The statistics value of bytes.
9013 * 0 on success, otherwise return -1.
9016 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9017 uint64_t *pkts, uint64_t *bytes)
9019 struct mlx5_priv *priv = dev->data->dev_private;
9020 struct mlx5_flow_counter *cnt;
9021 uint64_t inn_pkts, inn_bytes;
9024 if (!priv->config.devx)
9027 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9030 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9031 *pkts = inn_pkts - cnt->hits;
9032 *bytes = inn_bytes - cnt->bytes;
9034 cnt->hits = inn_pkts;
9035 cnt->bytes = inn_bytes;
9041 * Mutex-protected thunk to lock-free __flow_dv_translate().
9044 flow_dv_translate(struct rte_eth_dev *dev,
9045 struct mlx5_flow *dev_flow,
9046 const struct rte_flow_attr *attr,
9047 const struct rte_flow_item items[],
9048 const struct rte_flow_action actions[],
9049 struct rte_flow_error *error)
9053 flow_dv_shared_lock(dev);
9054 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9055 flow_dv_shared_unlock(dev);
9060 * Mutex-protected thunk to lock-free __flow_dv_apply().
9063 flow_dv_apply(struct rte_eth_dev *dev,
9064 struct rte_flow *flow,
9065 struct rte_flow_error *error)
9069 flow_dv_shared_lock(dev);
9070 ret = __flow_dv_apply(dev, flow, error);
9071 flow_dv_shared_unlock(dev);
9076 * Mutex-protected thunk to lock-free __flow_dv_remove().
9079 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9081 flow_dv_shared_lock(dev);
9082 __flow_dv_remove(dev, flow);
9083 flow_dv_shared_unlock(dev);
9087 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9090 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9092 flow_dv_shared_lock(dev);
9093 __flow_dv_destroy(dev, flow);
9094 flow_dv_shared_unlock(dev);
9098 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9101 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9105 flow_dv_shared_lock(dev);
9106 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9107 flow_dv_shared_unlock(dev);
9112 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9115 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9117 flow_dv_shared_lock(dev);
9118 flow_dv_counter_release(dev, cnt);
9119 flow_dv_shared_unlock(dev);
9122 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9123 .validate = flow_dv_validate,
9124 .prepare = flow_dv_prepare,
9125 .translate = flow_dv_translate,
9126 .apply = flow_dv_apply,
9127 .remove = flow_dv_remove,
9128 .destroy = flow_dv_destroy,
9129 .query = flow_dv_query,
9130 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9131 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9132 .create_policer_rules = flow_dv_create_policer_rules,
9133 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9134 .counter_alloc = flow_dv_counter_allocate,
9135 .counter_free = flow_dv_counter_free,
9136 .counter_query = flow_dv_counter_query,
9139 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */