1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
37 #include "rte_pmd_mlx5.h"
39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 /* VLAN header definitions */
56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
76 struct mlx5_flow_tbl_resource *tbl);
79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
80 uint32_t encap_decap_idx);
83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
93 * Initialize flow attributes structure according to flow items' types.
95 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
96 * mode. For tunnel mode, the items to be modified are the outermost ones.
99 * Pointer to item specification.
101 * Pointer to flow attributes structure.
102 * @param[in] dev_flow
103 * Pointer to the sub flow.
104 * @param[in] tunnel_decap
105 * Whether action is after tunnel decapsulation.
108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
109 struct mlx5_flow *dev_flow, bool tunnel_decap)
111 uint64_t layers = dev_flow->handle->layers;
114 * If layers is already initialized, it means this dev_flow is the
115 * suffix flow, the layers flags is set by the prefix flow. Need to
116 * use the layer flags from prefix flow as the suffix flow may not
117 * have the user defined items as the flow is split.
120 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
122 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
131 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
132 uint8_t next_protocol = 0xff;
133 switch (item->type) {
134 case RTE_FLOW_ITEM_TYPE_GRE:
135 case RTE_FLOW_ITEM_TYPE_NVGRE:
136 case RTE_FLOW_ITEM_TYPE_VXLAN:
137 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
138 case RTE_FLOW_ITEM_TYPE_GENEVE:
139 case RTE_FLOW_ITEM_TYPE_MPLS:
143 case RTE_FLOW_ITEM_TYPE_IPV4:
146 if (item->mask != NULL &&
147 ((const struct rte_flow_item_ipv4 *)
148 item->mask)->hdr.next_proto_id)
150 ((const struct rte_flow_item_ipv4 *)
151 (item->spec))->hdr.next_proto_id &
152 ((const struct rte_flow_item_ipv4 *)
153 (item->mask))->hdr.next_proto_id;
154 if ((next_protocol == IPPROTO_IPIP ||
155 next_protocol == IPPROTO_IPV6) && tunnel_decap)
158 case RTE_FLOW_ITEM_TYPE_IPV6:
161 if (item->mask != NULL &&
162 ((const struct rte_flow_item_ipv6 *)
163 item->mask)->hdr.proto)
165 ((const struct rte_flow_item_ipv6 *)
166 (item->spec))->hdr.proto &
167 ((const struct rte_flow_item_ipv6 *)
168 (item->mask))->hdr.proto;
169 if ((next_protocol == IPPROTO_IPIP ||
170 next_protocol == IPPROTO_IPV6) && tunnel_decap)
173 case RTE_FLOW_ITEM_TYPE_UDP:
177 case RTE_FLOW_ITEM_TYPE_TCP:
188 struct field_modify_info {
189 uint32_t size; /* Size of field in protocol header, in bytes. */
190 uint32_t offset; /* Offset of field in protocol header, in bytes. */
191 enum mlx5_modification_field id;
194 struct field_modify_info modify_eth[] = {
195 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
196 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
197 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
198 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
202 struct field_modify_info modify_vlan_out_first_vid[] = {
203 /* Size in bits !!! */
204 {12, 0, MLX5_MODI_OUT_FIRST_VID},
208 struct field_modify_info modify_ipv4[] = {
209 {1, 1, MLX5_MODI_OUT_IP_DSCP},
210 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
211 {4, 12, MLX5_MODI_OUT_SIPV4},
212 {4, 16, MLX5_MODI_OUT_DIPV4},
216 struct field_modify_info modify_ipv6[] = {
217 {1, 0, MLX5_MODI_OUT_IP_DSCP},
218 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
219 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
220 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
221 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
222 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
223 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
224 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
225 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
226 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
230 struct field_modify_info modify_udp[] = {
231 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
232 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
236 struct field_modify_info modify_tcp[] = {
237 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
238 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
239 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
240 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
245 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
246 uint8_t next_protocol, uint64_t *item_flags,
249 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
250 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
251 if (next_protocol == IPPROTO_IPIP) {
252 *item_flags |= MLX5_FLOW_LAYER_IPIP;
255 if (next_protocol == IPPROTO_IPV6) {
256 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
261 /* Update VLAN's VID/PCP based on input rte_flow_action.
264 * Pointer to struct rte_flow_action.
266 * Pointer to struct rte_vlan_hdr.
269 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
270 struct rte_vlan_hdr *vlan)
273 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
275 ((const struct rte_flow_action_of_set_vlan_pcp *)
276 action->conf)->vlan_pcp;
277 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
278 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
279 vlan->vlan_tci |= vlan_tci;
280 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
281 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
282 vlan->vlan_tci |= rte_be_to_cpu_16
283 (((const struct rte_flow_action_of_set_vlan_vid *)
284 action->conf)->vlan_vid);
289 * Fetch 1, 2, 3 or 4 byte field from the byte array
290 * and return as unsigned integer in host-endian format.
293 * Pointer to data array.
295 * Size of field to extract.
298 * converted field in host endian format.
300 static inline uint32_t
301 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
310 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
313 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
314 ret = (ret << 8) | *(data + sizeof(uint16_t));
317 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
328 * Convert modify-header action to DV specification.
330 * Data length of each action is determined by provided field description
331 * and the item mask. Data bit offset and width of each action is determined
332 * by provided item mask.
335 * Pointer to item specification.
337 * Pointer to field modification information.
338 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
339 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
340 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
342 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
343 * Negative offset value sets the same offset as source offset.
344 * size field is ignored, value is taken from source field.
345 * @param[in,out] resource
346 * Pointer to the modify-header resource.
348 * Type of modification.
350 * Pointer to the error structure.
353 * 0 on success, a negative errno value otherwise and rte_errno is set.
356 flow_dv_convert_modify_action(struct rte_flow_item *item,
357 struct field_modify_info *field,
358 struct field_modify_info *dcopy,
359 struct mlx5_flow_dv_modify_hdr_resource *resource,
360 uint32_t type, struct rte_flow_error *error)
362 uint32_t i = resource->actions_num;
363 struct mlx5_modification_cmd *actions = resource->actions;
366 * The item and mask are provided in big-endian format.
367 * The fields should be presented as in big-endian format either.
368 * Mask must be always present, it defines the actual field width.
370 MLX5_ASSERT(item->mask);
371 MLX5_ASSERT(field->size);
378 if (i >= MLX5_MAX_MODIFY_NUM)
379 return rte_flow_error_set(error, EINVAL,
380 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
381 "too many items to modify");
382 /* Fetch variable byte size mask from the array. */
383 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
384 field->offset, field->size);
389 /* Deduce actual data width in bits from mask value. */
390 off_b = rte_bsf32(mask);
391 size_b = sizeof(uint32_t) * CHAR_BIT -
392 off_b - __builtin_clz(mask);
394 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
395 actions[i] = (struct mlx5_modification_cmd) {
401 /* Convert entire record to expected big-endian format. */
402 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
403 if (type == MLX5_MODIFICATION_TYPE_COPY) {
405 actions[i].dst_field = dcopy->id;
406 actions[i].dst_offset =
407 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
408 /* Convert entire record to big-endian format. */
409 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
412 MLX5_ASSERT(item->spec);
413 data = flow_dv_fetch_field((const uint8_t *)item->spec +
414 field->offset, field->size);
415 /* Shift out the trailing masked bits from data. */
416 data = (data & mask) >> off_b;
417 actions[i].data1 = rte_cpu_to_be_32(data);
421 } while (field->size);
422 if (resource->actions_num == i)
423 return rte_flow_error_set(error, EINVAL,
424 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
425 "invalid modification flow item");
426 resource->actions_num = i;
431 * Convert modify-header set IPv4 address action to DV specification.
433 * @param[in,out] resource
434 * Pointer to the modify-header resource.
436 * Pointer to action specification.
438 * Pointer to the error structure.
441 * 0 on success, a negative errno value otherwise and rte_errno is set.
444 flow_dv_convert_action_modify_ipv4
445 (struct mlx5_flow_dv_modify_hdr_resource *resource,
446 const struct rte_flow_action *action,
447 struct rte_flow_error *error)
449 const struct rte_flow_action_set_ipv4 *conf =
450 (const struct rte_flow_action_set_ipv4 *)(action->conf);
451 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
452 struct rte_flow_item_ipv4 ipv4;
453 struct rte_flow_item_ipv4 ipv4_mask;
455 memset(&ipv4, 0, sizeof(ipv4));
456 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
457 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
458 ipv4.hdr.src_addr = conf->ipv4_addr;
459 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
461 ipv4.hdr.dst_addr = conf->ipv4_addr;
462 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
465 item.mask = &ipv4_mask;
466 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
467 MLX5_MODIFICATION_TYPE_SET, error);
471 * Convert modify-header set IPv6 address action to DV specification.
473 * @param[in,out] resource
474 * Pointer to the modify-header resource.
476 * Pointer to action specification.
478 * Pointer to the error structure.
481 * 0 on success, a negative errno value otherwise and rte_errno is set.
484 flow_dv_convert_action_modify_ipv6
485 (struct mlx5_flow_dv_modify_hdr_resource *resource,
486 const struct rte_flow_action *action,
487 struct rte_flow_error *error)
489 const struct rte_flow_action_set_ipv6 *conf =
490 (const struct rte_flow_action_set_ipv6 *)(action->conf);
491 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
492 struct rte_flow_item_ipv6 ipv6;
493 struct rte_flow_item_ipv6 ipv6_mask;
495 memset(&ipv6, 0, sizeof(ipv6));
496 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
497 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
498 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
499 sizeof(ipv6.hdr.src_addr));
500 memcpy(&ipv6_mask.hdr.src_addr,
501 &rte_flow_item_ipv6_mask.hdr.src_addr,
502 sizeof(ipv6.hdr.src_addr));
504 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
505 sizeof(ipv6.hdr.dst_addr));
506 memcpy(&ipv6_mask.hdr.dst_addr,
507 &rte_flow_item_ipv6_mask.hdr.dst_addr,
508 sizeof(ipv6.hdr.dst_addr));
511 item.mask = &ipv6_mask;
512 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
513 MLX5_MODIFICATION_TYPE_SET, error);
517 * Convert modify-header set MAC address action to DV specification.
519 * @param[in,out] resource
520 * Pointer to the modify-header resource.
522 * Pointer to action specification.
524 * Pointer to the error structure.
527 * 0 on success, a negative errno value otherwise and rte_errno is set.
530 flow_dv_convert_action_modify_mac
531 (struct mlx5_flow_dv_modify_hdr_resource *resource,
532 const struct rte_flow_action *action,
533 struct rte_flow_error *error)
535 const struct rte_flow_action_set_mac *conf =
536 (const struct rte_flow_action_set_mac *)(action->conf);
537 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
538 struct rte_flow_item_eth eth;
539 struct rte_flow_item_eth eth_mask;
541 memset(ð, 0, sizeof(eth));
542 memset(ð_mask, 0, sizeof(eth_mask));
543 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
544 memcpy(ð.src.addr_bytes, &conf->mac_addr,
545 sizeof(eth.src.addr_bytes));
546 memcpy(ð_mask.src.addr_bytes,
547 &rte_flow_item_eth_mask.src.addr_bytes,
548 sizeof(eth_mask.src.addr_bytes));
550 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
551 sizeof(eth.dst.addr_bytes));
552 memcpy(ð_mask.dst.addr_bytes,
553 &rte_flow_item_eth_mask.dst.addr_bytes,
554 sizeof(eth_mask.dst.addr_bytes));
557 item.mask = ð_mask;
558 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
559 MLX5_MODIFICATION_TYPE_SET, error);
563 * Convert modify-header set VLAN VID action to DV specification.
565 * @param[in,out] resource
566 * Pointer to the modify-header resource.
568 * Pointer to action specification.
570 * Pointer to the error structure.
573 * 0 on success, a negative errno value otherwise and rte_errno is set.
576 flow_dv_convert_action_modify_vlan_vid
577 (struct mlx5_flow_dv_modify_hdr_resource *resource,
578 const struct rte_flow_action *action,
579 struct rte_flow_error *error)
581 const struct rte_flow_action_of_set_vlan_vid *conf =
582 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
583 int i = resource->actions_num;
584 struct mlx5_modification_cmd *actions = resource->actions;
585 struct field_modify_info *field = modify_vlan_out_first_vid;
587 if (i >= MLX5_MAX_MODIFY_NUM)
588 return rte_flow_error_set(error, EINVAL,
589 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
590 "too many items to modify");
591 actions[i] = (struct mlx5_modification_cmd) {
592 .action_type = MLX5_MODIFICATION_TYPE_SET,
594 .length = field->size,
595 .offset = field->offset,
597 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
598 actions[i].data1 = conf->vlan_vid;
599 actions[i].data1 = actions[i].data1 << 16;
600 resource->actions_num = ++i;
605 * Convert modify-header set TP action to DV specification.
607 * @param[in,out] resource
608 * Pointer to the modify-header resource.
610 * Pointer to action specification.
612 * Pointer to rte_flow_item objects list.
614 * Pointer to flow attributes structure.
615 * @param[in] dev_flow
616 * Pointer to the sub flow.
617 * @param[in] tunnel_decap
618 * Whether action is after tunnel decapsulation.
620 * Pointer to the error structure.
623 * 0 on success, a negative errno value otherwise and rte_errno is set.
626 flow_dv_convert_action_modify_tp
627 (struct mlx5_flow_dv_modify_hdr_resource *resource,
628 const struct rte_flow_action *action,
629 const struct rte_flow_item *items,
630 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
631 bool tunnel_decap, struct rte_flow_error *error)
633 const struct rte_flow_action_set_tp *conf =
634 (const struct rte_flow_action_set_tp *)(action->conf);
635 struct rte_flow_item item;
636 struct rte_flow_item_udp udp;
637 struct rte_flow_item_udp udp_mask;
638 struct rte_flow_item_tcp tcp;
639 struct rte_flow_item_tcp tcp_mask;
640 struct field_modify_info *field;
643 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
645 memset(&udp, 0, sizeof(udp));
646 memset(&udp_mask, 0, sizeof(udp_mask));
647 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
648 udp.hdr.src_port = conf->port;
649 udp_mask.hdr.src_port =
650 rte_flow_item_udp_mask.hdr.src_port;
652 udp.hdr.dst_port = conf->port;
653 udp_mask.hdr.dst_port =
654 rte_flow_item_udp_mask.hdr.dst_port;
656 item.type = RTE_FLOW_ITEM_TYPE_UDP;
658 item.mask = &udp_mask;
661 MLX5_ASSERT(attr->tcp);
662 memset(&tcp, 0, sizeof(tcp));
663 memset(&tcp_mask, 0, sizeof(tcp_mask));
664 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
665 tcp.hdr.src_port = conf->port;
666 tcp_mask.hdr.src_port =
667 rte_flow_item_tcp_mask.hdr.src_port;
669 tcp.hdr.dst_port = conf->port;
670 tcp_mask.hdr.dst_port =
671 rte_flow_item_tcp_mask.hdr.dst_port;
673 item.type = RTE_FLOW_ITEM_TYPE_TCP;
675 item.mask = &tcp_mask;
678 return flow_dv_convert_modify_action(&item, field, NULL, resource,
679 MLX5_MODIFICATION_TYPE_SET, error);
683 * Convert modify-header set TTL action to DV specification.
685 * @param[in,out] resource
686 * Pointer to the modify-header resource.
688 * Pointer to action specification.
690 * Pointer to rte_flow_item objects list.
692 * Pointer to flow attributes structure.
693 * @param[in] dev_flow
694 * Pointer to the sub flow.
695 * @param[in] tunnel_decap
696 * Whether action is after tunnel decapsulation.
698 * Pointer to the error structure.
701 * 0 on success, a negative errno value otherwise and rte_errno is set.
704 flow_dv_convert_action_modify_ttl
705 (struct mlx5_flow_dv_modify_hdr_resource *resource,
706 const struct rte_flow_action *action,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
709 bool tunnel_decap, struct rte_flow_error *error)
711 const struct rte_flow_action_set_ttl *conf =
712 (const struct rte_flow_action_set_ttl *)(action->conf);
713 struct rte_flow_item item;
714 struct rte_flow_item_ipv4 ipv4;
715 struct rte_flow_item_ipv4 ipv4_mask;
716 struct rte_flow_item_ipv6 ipv6;
717 struct rte_flow_item_ipv6 ipv6_mask;
718 struct field_modify_info *field;
721 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
723 memset(&ipv4, 0, sizeof(ipv4));
724 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
725 ipv4.hdr.time_to_live = conf->ttl_value;
726 ipv4_mask.hdr.time_to_live = 0xFF;
727 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
729 item.mask = &ipv4_mask;
732 MLX5_ASSERT(attr->ipv6);
733 memset(&ipv6, 0, sizeof(ipv6));
734 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
735 ipv6.hdr.hop_limits = conf->ttl_value;
736 ipv6_mask.hdr.hop_limits = 0xFF;
737 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
739 item.mask = &ipv6_mask;
742 return flow_dv_convert_modify_action(&item, field, NULL, resource,
743 MLX5_MODIFICATION_TYPE_SET, error);
747 * Convert modify-header decrement TTL action to DV specification.
749 * @param[in,out] resource
750 * Pointer to the modify-header resource.
752 * Pointer to action specification.
754 * Pointer to rte_flow_item objects list.
756 * Pointer to flow attributes structure.
757 * @param[in] dev_flow
758 * Pointer to the sub flow.
759 * @param[in] tunnel_decap
760 * Whether action is after tunnel decapsulation.
762 * Pointer to the error structure.
765 * 0 on success, a negative errno value otherwise and rte_errno is set.
768 flow_dv_convert_action_modify_dec_ttl
769 (struct mlx5_flow_dv_modify_hdr_resource *resource,
770 const struct rte_flow_item *items,
771 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
772 bool tunnel_decap, struct rte_flow_error *error)
774 struct rte_flow_item item;
775 struct rte_flow_item_ipv4 ipv4;
776 struct rte_flow_item_ipv4 ipv4_mask;
777 struct rte_flow_item_ipv6 ipv6;
778 struct rte_flow_item_ipv6 ipv6_mask;
779 struct field_modify_info *field;
782 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
784 memset(&ipv4, 0, sizeof(ipv4));
785 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
786 ipv4.hdr.time_to_live = 0xFF;
787 ipv4_mask.hdr.time_to_live = 0xFF;
788 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
790 item.mask = &ipv4_mask;
793 MLX5_ASSERT(attr->ipv6);
794 memset(&ipv6, 0, sizeof(ipv6));
795 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
796 ipv6.hdr.hop_limits = 0xFF;
797 ipv6_mask.hdr.hop_limits = 0xFF;
798 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
800 item.mask = &ipv6_mask;
803 return flow_dv_convert_modify_action(&item, field, NULL, resource,
804 MLX5_MODIFICATION_TYPE_ADD, error);
808 * Convert modify-header increment/decrement TCP Sequence number
809 * to DV specification.
811 * @param[in,out] resource
812 * Pointer to the modify-header resource.
814 * Pointer to action specification.
816 * Pointer to the error structure.
819 * 0 on success, a negative errno value otherwise and rte_errno is set.
822 flow_dv_convert_action_modify_tcp_seq
823 (struct mlx5_flow_dv_modify_hdr_resource *resource,
824 const struct rte_flow_action *action,
825 struct rte_flow_error *error)
827 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
828 uint64_t value = rte_be_to_cpu_32(*conf);
829 struct rte_flow_item item;
830 struct rte_flow_item_tcp tcp;
831 struct rte_flow_item_tcp tcp_mask;
833 memset(&tcp, 0, sizeof(tcp));
834 memset(&tcp_mask, 0, sizeof(tcp_mask));
835 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
837 * The HW has no decrement operation, only increment operation.
838 * To simulate decrement X from Y using increment operation
839 * we need to add UINT32_MAX X times to Y.
840 * Each adding of UINT32_MAX decrements Y by 1.
843 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
844 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
845 item.type = RTE_FLOW_ITEM_TYPE_TCP;
847 item.mask = &tcp_mask;
848 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
849 MLX5_MODIFICATION_TYPE_ADD, error);
853 * Convert modify-header increment/decrement TCP Acknowledgment number
854 * to DV specification.
856 * @param[in,out] resource
857 * Pointer to the modify-header resource.
859 * Pointer to action specification.
861 * Pointer to the error structure.
864 * 0 on success, a negative errno value otherwise and rte_errno is set.
867 flow_dv_convert_action_modify_tcp_ack
868 (struct mlx5_flow_dv_modify_hdr_resource *resource,
869 const struct rte_flow_action *action,
870 struct rte_flow_error *error)
872 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
873 uint64_t value = rte_be_to_cpu_32(*conf);
874 struct rte_flow_item item;
875 struct rte_flow_item_tcp tcp;
876 struct rte_flow_item_tcp tcp_mask;
878 memset(&tcp, 0, sizeof(tcp));
879 memset(&tcp_mask, 0, sizeof(tcp_mask));
880 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
882 * The HW has no decrement operation, only increment operation.
883 * To simulate decrement X from Y using increment operation
884 * we need to add UINT32_MAX X times to Y.
885 * Each adding of UINT32_MAX decrements Y by 1.
888 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
889 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
890 item.type = RTE_FLOW_ITEM_TYPE_TCP;
892 item.mask = &tcp_mask;
893 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
894 MLX5_MODIFICATION_TYPE_ADD, error);
897 static enum mlx5_modification_field reg_to_field[] = {
898 [REG_NON] = MLX5_MODI_OUT_NONE,
899 [REG_A] = MLX5_MODI_META_DATA_REG_A,
900 [REG_B] = MLX5_MODI_META_DATA_REG_B,
901 [REG_C_0] = MLX5_MODI_META_REG_C_0,
902 [REG_C_1] = MLX5_MODI_META_REG_C_1,
903 [REG_C_2] = MLX5_MODI_META_REG_C_2,
904 [REG_C_3] = MLX5_MODI_META_REG_C_3,
905 [REG_C_4] = MLX5_MODI_META_REG_C_4,
906 [REG_C_5] = MLX5_MODI_META_REG_C_5,
907 [REG_C_6] = MLX5_MODI_META_REG_C_6,
908 [REG_C_7] = MLX5_MODI_META_REG_C_7,
912 * Convert register set to DV specification.
914 * @param[in,out] resource
915 * Pointer to the modify-header resource.
917 * Pointer to action specification.
919 * Pointer to the error structure.
922 * 0 on success, a negative errno value otherwise and rte_errno is set.
925 flow_dv_convert_action_set_reg
926 (struct mlx5_flow_dv_modify_hdr_resource *resource,
927 const struct rte_flow_action *action,
928 struct rte_flow_error *error)
930 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
931 struct mlx5_modification_cmd *actions = resource->actions;
932 uint32_t i = resource->actions_num;
934 if (i >= MLX5_MAX_MODIFY_NUM)
935 return rte_flow_error_set(error, EINVAL,
936 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
937 "too many items to modify");
938 MLX5_ASSERT(conf->id != REG_NON);
939 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
940 actions[i] = (struct mlx5_modification_cmd) {
941 .action_type = MLX5_MODIFICATION_TYPE_SET,
942 .field = reg_to_field[conf->id],
943 .offset = conf->offset,
944 .length = conf->length,
946 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
947 actions[i].data1 = rte_cpu_to_be_32(conf->data);
949 resource->actions_num = i;
954 * Convert SET_TAG action to DV specification.
957 * Pointer to the rte_eth_dev structure.
958 * @param[in,out] resource
959 * Pointer to the modify-header resource.
961 * Pointer to action specification.
963 * Pointer to the error structure.
966 * 0 on success, a negative errno value otherwise and rte_errno is set.
969 flow_dv_convert_action_set_tag
970 (struct rte_eth_dev *dev,
971 struct mlx5_flow_dv_modify_hdr_resource *resource,
972 const struct rte_flow_action_set_tag *conf,
973 struct rte_flow_error *error)
975 rte_be32_t data = rte_cpu_to_be_32(conf->data);
976 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
977 struct rte_flow_item item = {
981 struct field_modify_info reg_c_x[] = {
984 enum mlx5_modification_field reg_type;
987 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
990 MLX5_ASSERT(ret != REG_NON);
991 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
992 reg_type = reg_to_field[ret];
993 MLX5_ASSERT(reg_type > 0);
994 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
995 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
996 MLX5_MODIFICATION_TYPE_SET, error);
1000 * Convert internal COPY_REG action to DV specification.
1003 * Pointer to the rte_eth_dev structure.
1004 * @param[in,out] res
1005 * Pointer to the modify-header resource.
1007 * Pointer to action specification.
1009 * Pointer to the error structure.
1012 * 0 on success, a negative errno value otherwise and rte_errno is set.
1015 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1016 struct mlx5_flow_dv_modify_hdr_resource *res,
1017 const struct rte_flow_action *action,
1018 struct rte_flow_error *error)
1020 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1021 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1022 struct rte_flow_item item = {
1026 struct field_modify_info reg_src[] = {
1027 {4, 0, reg_to_field[conf->src]},
1030 struct field_modify_info reg_dst = {
1032 .id = reg_to_field[conf->dst],
1034 /* Adjust reg_c[0] usage according to reported mask. */
1035 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1036 struct mlx5_priv *priv = dev->data->dev_private;
1037 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1039 MLX5_ASSERT(reg_c0);
1040 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1041 if (conf->dst == REG_C_0) {
1042 /* Copy to reg_c[0], within mask only. */
1043 reg_dst.offset = rte_bsf32(reg_c0);
1045 * Mask is ignoring the enianness, because
1046 * there is no conversion in datapath.
1048 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1049 /* Copy from destination lower bits to reg_c[0]. */
1050 mask = reg_c0 >> reg_dst.offset;
1052 /* Copy from destination upper bits to reg_c[0]. */
1053 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1054 rte_fls_u32(reg_c0));
1057 mask = rte_cpu_to_be_32(reg_c0);
1058 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1059 /* Copy from reg_c[0] to destination lower bits. */
1062 /* Copy from reg_c[0] to destination upper bits. */
1063 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1064 (rte_fls_u32(reg_c0) -
1069 return flow_dv_convert_modify_action(&item,
1070 reg_src, ®_dst, res,
1071 MLX5_MODIFICATION_TYPE_COPY,
1076 * Convert MARK action to DV specification. This routine is used
1077 * in extensive metadata only and requires metadata register to be
1078 * handled. In legacy mode hardware tag resource is engaged.
1081 * Pointer to the rte_eth_dev structure.
1083 * Pointer to MARK action specification.
1084 * @param[in,out] resource
1085 * Pointer to the modify-header resource.
1087 * Pointer to the error structure.
1090 * 0 on success, a negative errno value otherwise and rte_errno is set.
1093 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1094 const struct rte_flow_action_mark *conf,
1095 struct mlx5_flow_dv_modify_hdr_resource *resource,
1096 struct rte_flow_error *error)
1098 struct mlx5_priv *priv = dev->data->dev_private;
1099 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1100 priv->sh->dv_mark_mask);
1101 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1102 struct rte_flow_item item = {
1106 struct field_modify_info reg_c_x[] = {
1112 return rte_flow_error_set(error, EINVAL,
1113 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1114 NULL, "zero mark action mask");
1115 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1118 MLX5_ASSERT(reg > 0);
1119 if (reg == REG_C_0) {
1120 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1121 uint32_t shl_c0 = rte_bsf32(msk_c0);
1123 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1124 mask = rte_cpu_to_be_32(mask) & msk_c0;
1125 mask = rte_cpu_to_be_32(mask << shl_c0);
1127 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1128 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1129 MLX5_MODIFICATION_TYPE_SET, error);
1133 * Get metadata register index for specified steering domain.
1136 * Pointer to the rte_eth_dev structure.
1138 * Attributes of flow to determine steering domain.
1140 * Pointer to the error structure.
1143 * positive index on success, a negative errno value otherwise
1144 * and rte_errno is set.
1146 static enum modify_reg
1147 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1148 const struct rte_flow_attr *attr,
1149 struct rte_flow_error *error)
1152 mlx5_flow_get_reg_id(dev, attr->transfer ?
1156 MLX5_METADATA_RX, 0, error);
1158 return rte_flow_error_set(error,
1159 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1160 NULL, "unavailable "
1161 "metadata register");
1166 * Convert SET_META action to DV specification.
1169 * Pointer to the rte_eth_dev structure.
1170 * @param[in,out] resource
1171 * Pointer to the modify-header resource.
1173 * Attributes of flow that includes this item.
1175 * Pointer to action specification.
1177 * Pointer to the error structure.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 flow_dv_convert_action_set_meta
1184 (struct rte_eth_dev *dev,
1185 struct mlx5_flow_dv_modify_hdr_resource *resource,
1186 const struct rte_flow_attr *attr,
1187 const struct rte_flow_action_set_meta *conf,
1188 struct rte_flow_error *error)
1190 uint32_t data = conf->data;
1191 uint32_t mask = conf->mask;
1192 struct rte_flow_item item = {
1196 struct field_modify_info reg_c_x[] = {
1199 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1203 MLX5_ASSERT(reg != REG_NON);
1205 * In datapath code there is no endianness
1206 * coversions for perfromance reasons, all
1207 * pattern conversions are done in rte_flow.
1209 if (reg == REG_C_0) {
1210 struct mlx5_priv *priv = dev->data->dev_private;
1211 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1214 MLX5_ASSERT(msk_c0);
1215 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1216 shl_c0 = rte_bsf32(msk_c0);
1218 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1222 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1224 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1225 /* The routine expects parameters in memory as big-endian ones. */
1226 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1227 MLX5_MODIFICATION_TYPE_SET, error);
1231 * Convert modify-header set IPv4 DSCP action to DV specification.
1233 * @param[in,out] resource
1234 * Pointer to the modify-header resource.
1236 * Pointer to action specification.
1238 * Pointer to the error structure.
1241 * 0 on success, a negative errno value otherwise and rte_errno is set.
1244 flow_dv_convert_action_modify_ipv4_dscp
1245 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1246 const struct rte_flow_action *action,
1247 struct rte_flow_error *error)
1249 const struct rte_flow_action_set_dscp *conf =
1250 (const struct rte_flow_action_set_dscp *)(action->conf);
1251 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1252 struct rte_flow_item_ipv4 ipv4;
1253 struct rte_flow_item_ipv4 ipv4_mask;
1255 memset(&ipv4, 0, sizeof(ipv4));
1256 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1257 ipv4.hdr.type_of_service = conf->dscp;
1258 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1260 item.mask = &ipv4_mask;
1261 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1262 MLX5_MODIFICATION_TYPE_SET, error);
1266 * Convert modify-header set IPv6 DSCP action to DV specification.
1268 * @param[in,out] resource
1269 * Pointer to the modify-header resource.
1271 * Pointer to action specification.
1273 * Pointer to the error structure.
1276 * 0 on success, a negative errno value otherwise and rte_errno is set.
1279 flow_dv_convert_action_modify_ipv6_dscp
1280 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1281 const struct rte_flow_action *action,
1282 struct rte_flow_error *error)
1284 const struct rte_flow_action_set_dscp *conf =
1285 (const struct rte_flow_action_set_dscp *)(action->conf);
1286 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1287 struct rte_flow_item_ipv6 ipv6;
1288 struct rte_flow_item_ipv6 ipv6_mask;
1290 memset(&ipv6, 0, sizeof(ipv6));
1291 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1293 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1294 * rdma-core only accept the DSCP bits byte aligned start from
1295 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1296 * bits in IPv6 case as rdma-core requires byte aligned value.
1298 ipv6.hdr.vtc_flow = conf->dscp;
1299 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1301 item.mask = &ipv6_mask;
1302 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1303 MLX5_MODIFICATION_TYPE_SET, error);
1307 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1310 case RTE_FLOW_FIELD_START:
1312 case RTE_FLOW_FIELD_MAC_DST:
1313 case RTE_FLOW_FIELD_MAC_SRC:
1315 case RTE_FLOW_FIELD_VLAN_TYPE:
1317 case RTE_FLOW_FIELD_VLAN_ID:
1319 case RTE_FLOW_FIELD_MAC_TYPE:
1321 case RTE_FLOW_FIELD_IPV4_DSCP:
1323 case RTE_FLOW_FIELD_IPV4_TTL:
1325 case RTE_FLOW_FIELD_IPV4_SRC:
1326 case RTE_FLOW_FIELD_IPV4_DST:
1328 case RTE_FLOW_FIELD_IPV6_DSCP:
1330 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1332 case RTE_FLOW_FIELD_IPV6_SRC:
1333 case RTE_FLOW_FIELD_IPV6_DST:
1335 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1336 case RTE_FLOW_FIELD_TCP_PORT_DST:
1338 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1339 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1341 case RTE_FLOW_FIELD_TCP_FLAGS:
1343 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1344 case RTE_FLOW_FIELD_UDP_PORT_DST:
1346 case RTE_FLOW_FIELD_VXLAN_VNI:
1347 case RTE_FLOW_FIELD_GENEVE_VNI:
1349 case RTE_FLOW_FIELD_GTP_TEID:
1350 case RTE_FLOW_FIELD_TAG:
1352 case RTE_FLOW_FIELD_MARK:
1354 case RTE_FLOW_FIELD_META:
1356 case RTE_FLOW_FIELD_POINTER:
1357 case RTE_FLOW_FIELD_VALUE:
1366 mlx5_flow_field_id_to_modify_info
1367 (const struct rte_flow_action_modify_data *data,
1368 struct field_modify_info *info,
1369 uint32_t *mask, uint32_t *value,
1370 uint32_t width, uint32_t dst_width,
1371 struct rte_eth_dev *dev,
1372 const struct rte_flow_attr *attr,
1373 struct rte_flow_error *error)
1377 switch (data->field) {
1378 case RTE_FLOW_FIELD_START:
1379 /* not supported yet */
1382 case RTE_FLOW_FIELD_MAC_DST:
1384 if (data->offset < 32) {
1385 info[idx] = (struct field_modify_info){4, 0,
1386 MLX5_MODI_OUT_DMAC_47_16};
1389 rte_cpu_to_be_32(0xffffffff >>
1393 mask[idx] = RTE_BE32(0xffffffff);
1400 info[idx] = (struct field_modify_info){2, 4 * idx,
1401 MLX5_MODI_OUT_DMAC_15_0};
1402 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1404 if (data->offset < 32)
1405 info[idx++] = (struct field_modify_info){4, 0,
1406 MLX5_MODI_OUT_DMAC_47_16};
1407 info[idx] = (struct field_modify_info){2, 0,
1408 MLX5_MODI_OUT_DMAC_15_0};
1411 case RTE_FLOW_FIELD_MAC_SRC:
1413 if (data->offset < 32) {
1414 info[idx] = (struct field_modify_info){4, 0,
1415 MLX5_MODI_OUT_SMAC_47_16};
1418 rte_cpu_to_be_32(0xffffffff >>
1422 mask[idx] = RTE_BE32(0xffffffff);
1429 info[idx] = (struct field_modify_info){2, 4 * idx,
1430 MLX5_MODI_OUT_SMAC_15_0};
1431 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1433 if (data->offset < 32)
1434 info[idx++] = (struct field_modify_info){4, 0,
1435 MLX5_MODI_OUT_SMAC_47_16};
1436 info[idx] = (struct field_modify_info){2, 0,
1437 MLX5_MODI_OUT_SMAC_15_0};
1440 case RTE_FLOW_FIELD_VLAN_TYPE:
1441 /* not supported yet */
1443 case RTE_FLOW_FIELD_VLAN_ID:
1444 info[idx] = (struct field_modify_info){2, 0,
1445 MLX5_MODI_OUT_FIRST_VID};
1447 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1449 case RTE_FLOW_FIELD_MAC_TYPE:
1450 info[idx] = (struct field_modify_info){2, 0,
1451 MLX5_MODI_OUT_ETHERTYPE};
1453 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1455 case RTE_FLOW_FIELD_IPV4_DSCP:
1456 info[idx] = (struct field_modify_info){1, 0,
1457 MLX5_MODI_OUT_IP_DSCP};
1459 mask[idx] = 0x3f >> (6 - width);
1461 case RTE_FLOW_FIELD_IPV4_TTL:
1462 info[idx] = (struct field_modify_info){1, 0,
1463 MLX5_MODI_OUT_IPV4_TTL};
1465 mask[idx] = 0xff >> (8 - width);
1467 case RTE_FLOW_FIELD_IPV4_SRC:
1468 info[idx] = (struct field_modify_info){4, 0,
1469 MLX5_MODI_OUT_SIPV4};
1471 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1474 case RTE_FLOW_FIELD_IPV4_DST:
1475 info[idx] = (struct field_modify_info){4, 0,
1476 MLX5_MODI_OUT_DIPV4};
1478 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1481 case RTE_FLOW_FIELD_IPV6_DSCP:
1482 info[idx] = (struct field_modify_info){1, 0,
1483 MLX5_MODI_OUT_IP_DSCP};
1485 mask[idx] = 0x3f >> (6 - width);
1487 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1488 info[idx] = (struct field_modify_info){1, 0,
1489 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1491 mask[idx] = 0xff >> (8 - width);
1493 case RTE_FLOW_FIELD_IPV6_SRC:
1495 if (data->offset < 32) {
1496 info[idx] = (struct field_modify_info){4,
1498 MLX5_MODI_OUT_SIPV6_31_0};
1501 rte_cpu_to_be_32(0xffffffff >>
1505 mask[idx] = RTE_BE32(0xffffffff);
1512 if (data->offset < 64) {
1513 info[idx] = (struct field_modify_info){4,
1515 MLX5_MODI_OUT_SIPV6_63_32};
1518 rte_cpu_to_be_32(0xffffffff >>
1522 mask[idx] = RTE_BE32(0xffffffff);
1529 if (data->offset < 96) {
1530 info[idx] = (struct field_modify_info){4,
1532 MLX5_MODI_OUT_SIPV6_95_64};
1535 rte_cpu_to_be_32(0xffffffff >>
1539 mask[idx] = RTE_BE32(0xffffffff);
1546 info[idx] = (struct field_modify_info){4, 4 * idx,
1547 MLX5_MODI_OUT_SIPV6_127_96};
1548 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1551 if (data->offset < 32)
1552 info[idx++] = (struct field_modify_info){4, 0,
1553 MLX5_MODI_OUT_SIPV6_31_0};
1554 if (data->offset < 64)
1555 info[idx++] = (struct field_modify_info){4, 0,
1556 MLX5_MODI_OUT_SIPV6_63_32};
1557 if (data->offset < 96)
1558 info[idx++] = (struct field_modify_info){4, 0,
1559 MLX5_MODI_OUT_SIPV6_95_64};
1560 if (data->offset < 128)
1561 info[idx++] = (struct field_modify_info){4, 0,
1562 MLX5_MODI_OUT_SIPV6_127_96};
1565 case RTE_FLOW_FIELD_IPV6_DST:
1567 if (data->offset < 32) {
1568 info[idx] = (struct field_modify_info){4,
1570 MLX5_MODI_OUT_DIPV6_31_0};
1573 rte_cpu_to_be_32(0xffffffff >>
1577 mask[idx] = RTE_BE32(0xffffffff);
1584 if (data->offset < 64) {
1585 info[idx] = (struct field_modify_info){4,
1587 MLX5_MODI_OUT_DIPV6_63_32};
1590 rte_cpu_to_be_32(0xffffffff >>
1594 mask[idx] = RTE_BE32(0xffffffff);
1601 if (data->offset < 96) {
1602 info[idx] = (struct field_modify_info){4,
1604 MLX5_MODI_OUT_DIPV6_95_64};
1607 rte_cpu_to_be_32(0xffffffff >>
1611 mask[idx] = RTE_BE32(0xffffffff);
1618 info[idx] = (struct field_modify_info){4, 4 * idx,
1619 MLX5_MODI_OUT_DIPV6_127_96};
1620 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1623 if (data->offset < 32)
1624 info[idx++] = (struct field_modify_info){4, 0,
1625 MLX5_MODI_OUT_DIPV6_31_0};
1626 if (data->offset < 64)
1627 info[idx++] = (struct field_modify_info){4, 0,
1628 MLX5_MODI_OUT_DIPV6_63_32};
1629 if (data->offset < 96)
1630 info[idx++] = (struct field_modify_info){4, 0,
1631 MLX5_MODI_OUT_DIPV6_95_64};
1632 if (data->offset < 128)
1633 info[idx++] = (struct field_modify_info){4, 0,
1634 MLX5_MODI_OUT_DIPV6_127_96};
1637 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1638 info[idx] = (struct field_modify_info){2, 0,
1639 MLX5_MODI_OUT_TCP_SPORT};
1641 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1643 case RTE_FLOW_FIELD_TCP_PORT_DST:
1644 info[idx] = (struct field_modify_info){2, 0,
1645 MLX5_MODI_OUT_TCP_DPORT};
1647 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1649 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1650 info[idx] = (struct field_modify_info){4, 0,
1651 MLX5_MODI_OUT_TCP_SEQ_NUM};
1653 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1656 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1657 info[idx] = (struct field_modify_info){4, 0,
1658 MLX5_MODI_OUT_TCP_ACK_NUM};
1660 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1663 case RTE_FLOW_FIELD_TCP_FLAGS:
1664 info[idx] = (struct field_modify_info){1, 0,
1665 MLX5_MODI_OUT_TCP_FLAGS};
1667 mask[idx] = 0x3f >> (6 - width);
1669 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1670 info[idx] = (struct field_modify_info){2, 0,
1671 MLX5_MODI_OUT_UDP_SPORT};
1673 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1675 case RTE_FLOW_FIELD_UDP_PORT_DST:
1676 info[idx] = (struct field_modify_info){2, 0,
1677 MLX5_MODI_OUT_UDP_DPORT};
1679 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1681 case RTE_FLOW_FIELD_VXLAN_VNI:
1682 /* not supported yet */
1684 case RTE_FLOW_FIELD_GENEVE_VNI:
1685 /* not supported yet*/
1687 case RTE_FLOW_FIELD_GTP_TEID:
1688 info[idx] = (struct field_modify_info){4, 0,
1689 MLX5_MODI_GTP_TEID};
1691 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1694 case RTE_FLOW_FIELD_TAG:
1696 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1697 data->level, error);
1700 MLX5_ASSERT(reg != REG_NON);
1701 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1702 info[idx] = (struct field_modify_info){4, 0,
1706 rte_cpu_to_be_32(0xffffffff >>
1710 case RTE_FLOW_FIELD_MARK:
1712 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1716 MLX5_ASSERT(reg != REG_NON);
1717 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1718 info[idx] = (struct field_modify_info){4, 0,
1722 rte_cpu_to_be_32(0xffffffff >>
1726 case RTE_FLOW_FIELD_META:
1728 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1731 MLX5_ASSERT(reg != REG_NON);
1732 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1733 info[idx] = (struct field_modify_info){4, 0,
1737 rte_cpu_to_be_32(0xffffffff >>
1741 case RTE_FLOW_FIELD_POINTER:
1742 case RTE_FLOW_FIELD_VALUE:
1743 if (data->field == RTE_FLOW_FIELD_POINTER)
1744 memcpy(&val, (void *)(uintptr_t)data->value,
1748 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1750 if (dst_width > 16) {
1751 value[idx] = rte_cpu_to_be_32(val);
1753 } else if (dst_width > 8) {
1754 value[idx] = rte_cpu_to_be_16(val);
1757 value[idx] = (uint8_t)val;
1772 * Convert modify_field action to DV specification.
1775 * Pointer to the rte_eth_dev structure.
1776 * @param[in,out] resource
1777 * Pointer to the modify-header resource.
1779 * Pointer to action specification.
1781 * Attributes of flow that includes this item.
1783 * Pointer to the error structure.
1786 * 0 on success, a negative errno value otherwise and rte_errno is set.
1789 flow_dv_convert_action_modify_field
1790 (struct rte_eth_dev *dev,
1791 struct mlx5_flow_dv_modify_hdr_resource *resource,
1792 const struct rte_flow_action *action,
1793 const struct rte_flow_attr *attr,
1794 struct rte_flow_error *error)
1796 const struct rte_flow_action_modify_field *conf =
1797 (const struct rte_flow_action_modify_field *)(action->conf);
1798 struct rte_flow_item item;
1799 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1801 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1803 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1804 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1806 uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1808 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1809 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1810 type = MLX5_MODIFICATION_TYPE_SET;
1811 /** For SET fill the destination field (field) first. */
1812 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1813 value, conf->width, dst_width, dev, attr, error);
1814 /** Then copy immediate value from source as per mask. */
1815 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1816 value, conf->width, dst_width, dev, attr, error);
1819 type = MLX5_MODIFICATION_TYPE_COPY;
1820 /** For COPY fill the destination field (dcopy) without mask. */
1821 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1822 value, conf->width, dst_width, dev, attr, error);
1823 /** Then construct the source field (field) with mask. */
1824 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1825 value, conf->width, dst_width, dev, attr, error);
1828 return flow_dv_convert_modify_action(&item,
1829 field, dcopy, resource, type, error);
1833 * Validate MARK item.
1836 * Pointer to the rte_eth_dev structure.
1838 * Item specification.
1840 * Attributes of flow that includes this item.
1842 * Pointer to error structure.
1845 * 0 on success, a negative errno value otherwise and rte_errno is set.
1848 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1849 const struct rte_flow_item *item,
1850 const struct rte_flow_attr *attr __rte_unused,
1851 struct rte_flow_error *error)
1853 struct mlx5_priv *priv = dev->data->dev_private;
1854 struct mlx5_dev_config *config = &priv->config;
1855 const struct rte_flow_item_mark *spec = item->spec;
1856 const struct rte_flow_item_mark *mask = item->mask;
1857 const struct rte_flow_item_mark nic_mask = {
1858 .id = priv->sh->dv_mark_mask,
1862 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1863 return rte_flow_error_set(error, ENOTSUP,
1864 RTE_FLOW_ERROR_TYPE_ITEM, item,
1865 "extended metadata feature"
1867 if (!mlx5_flow_ext_mreg_supported(dev))
1868 return rte_flow_error_set(error, ENOTSUP,
1869 RTE_FLOW_ERROR_TYPE_ITEM, item,
1870 "extended metadata register"
1871 " isn't supported");
1873 return rte_flow_error_set(error, ENOTSUP,
1874 RTE_FLOW_ERROR_TYPE_ITEM, item,
1875 "extended metadata register"
1876 " isn't available");
1877 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1881 return rte_flow_error_set(error, EINVAL,
1882 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1884 "data cannot be empty");
1885 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1886 return rte_flow_error_set(error, EINVAL,
1887 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1889 "mark id exceeds the limit");
1893 return rte_flow_error_set(error, EINVAL,
1894 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1895 "mask cannot be zero");
1897 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1898 (const uint8_t *)&nic_mask,
1899 sizeof(struct rte_flow_item_mark),
1900 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1907 * Validate META item.
1910 * Pointer to the rte_eth_dev structure.
1912 * Item specification.
1914 * Attributes of flow that includes this item.
1916 * Pointer to error structure.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1923 const struct rte_flow_item *item,
1924 const struct rte_flow_attr *attr,
1925 struct rte_flow_error *error)
1927 struct mlx5_priv *priv = dev->data->dev_private;
1928 struct mlx5_dev_config *config = &priv->config;
1929 const struct rte_flow_item_meta *spec = item->spec;
1930 const struct rte_flow_item_meta *mask = item->mask;
1931 struct rte_flow_item_meta nic_mask = {
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1941 "data cannot be empty");
1942 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1943 if (!mlx5_flow_ext_mreg_supported(dev))
1944 return rte_flow_error_set(error, ENOTSUP,
1945 RTE_FLOW_ERROR_TYPE_ITEM, item,
1946 "extended metadata register"
1947 " isn't supported");
1948 reg = flow_dv_get_metadata_reg(dev, attr, error);
1952 return rte_flow_error_set(error, ENOTSUP,
1953 RTE_FLOW_ERROR_TYPE_ITEM, item,
1954 "unavalable extended metadata register");
1956 return rte_flow_error_set(error, ENOTSUP,
1957 RTE_FLOW_ERROR_TYPE_ITEM, item,
1961 nic_mask.data = priv->sh->dv_meta_mask;
1964 return rte_flow_error_set(error, ENOTSUP,
1965 RTE_FLOW_ERROR_TYPE_ITEM, item,
1966 "extended metadata feature "
1967 "should be enabled when "
1968 "meta item is requested "
1969 "with e-switch mode ");
1971 return rte_flow_error_set(error, ENOTSUP,
1972 RTE_FLOW_ERROR_TYPE_ITEM, item,
1973 "match on metadata for ingress "
1974 "is not supported in legacy "
1978 mask = &rte_flow_item_meta_mask;
1980 return rte_flow_error_set(error, EINVAL,
1981 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1982 "mask cannot be zero");
1984 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1985 (const uint8_t *)&nic_mask,
1986 sizeof(struct rte_flow_item_meta),
1987 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1992 * Validate TAG item.
1995 * Pointer to the rte_eth_dev structure.
1997 * Item specification.
1999 * Attributes of flow that includes this item.
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2008 const struct rte_flow_item *item,
2009 const struct rte_flow_attr *attr __rte_unused,
2010 struct rte_flow_error *error)
2012 const struct rte_flow_item_tag *spec = item->spec;
2013 const struct rte_flow_item_tag *mask = item->mask;
2014 const struct rte_flow_item_tag nic_mask = {
2015 .data = RTE_BE32(UINT32_MAX),
2020 if (!mlx5_flow_ext_mreg_supported(dev))
2021 return rte_flow_error_set(error, ENOTSUP,
2022 RTE_FLOW_ERROR_TYPE_ITEM, item,
2023 "extensive metadata register"
2024 " isn't supported");
2026 return rte_flow_error_set(error, EINVAL,
2027 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2029 "data cannot be empty");
2031 mask = &rte_flow_item_tag_mask;
2033 return rte_flow_error_set(error, EINVAL,
2034 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2035 "mask cannot be zero");
2037 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2038 (const uint8_t *)&nic_mask,
2039 sizeof(struct rte_flow_item_tag),
2040 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2043 if (mask->index != 0xff)
2044 return rte_flow_error_set(error, EINVAL,
2045 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2046 "partial mask for tag index"
2047 " is not supported");
2048 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2051 MLX5_ASSERT(ret != REG_NON);
2056 * Validate vport item.
2059 * Pointer to the rte_eth_dev structure.
2061 * Item specification.
2063 * Attributes of flow that includes this item.
2064 * @param[in] item_flags
2065 * Bit-fields that holds the items detected until now.
2067 * Pointer to error structure.
2070 * 0 on success, a negative errno value otherwise and rte_errno is set.
2073 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2074 const struct rte_flow_item *item,
2075 const struct rte_flow_attr *attr,
2076 uint64_t item_flags,
2077 struct rte_flow_error *error)
2079 const struct rte_flow_item_port_id *spec = item->spec;
2080 const struct rte_flow_item_port_id *mask = item->mask;
2081 const struct rte_flow_item_port_id switch_mask = {
2084 struct mlx5_priv *esw_priv;
2085 struct mlx5_priv *dev_priv;
2088 if (!attr->transfer)
2089 return rte_flow_error_set(error, EINVAL,
2090 RTE_FLOW_ERROR_TYPE_ITEM,
2092 "match on port id is valid only"
2093 " when transfer flag is enabled");
2094 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2095 return rte_flow_error_set(error, ENOTSUP,
2096 RTE_FLOW_ERROR_TYPE_ITEM, item,
2097 "multiple source ports are not"
2100 mask = &switch_mask;
2101 if (mask->id != 0xffffffff)
2102 return rte_flow_error_set(error, ENOTSUP,
2103 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2105 "no support for partial mask on"
2107 ret = mlx5_flow_item_acceptable
2108 (item, (const uint8_t *)mask,
2109 (const uint8_t *)&rte_flow_item_port_id_mask,
2110 sizeof(struct rte_flow_item_port_id),
2111 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2116 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2118 return rte_flow_error_set(error, rte_errno,
2119 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2120 "failed to obtain E-Switch info for"
2122 dev_priv = mlx5_dev_to_eswitch_info(dev);
2124 return rte_flow_error_set(error, rte_errno,
2125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2127 "failed to obtain E-Switch info");
2128 if (esw_priv->domain_id != dev_priv->domain_id)
2129 return rte_flow_error_set(error, EINVAL,
2130 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2131 "cannot match on a port from a"
2132 " different E-Switch");
2137 * Validate VLAN item.
2140 * Item specification.
2141 * @param[in] item_flags
2142 * Bit-fields that holds the items detected until now.
2144 * Ethernet device flow is being created on.
2146 * Pointer to error structure.
2149 * 0 on success, a negative errno value otherwise and rte_errno is set.
2152 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2153 uint64_t item_flags,
2154 struct rte_eth_dev *dev,
2155 struct rte_flow_error *error)
2157 const struct rte_flow_item_vlan *mask = item->mask;
2158 const struct rte_flow_item_vlan nic_mask = {
2159 .tci = RTE_BE16(UINT16_MAX),
2160 .inner_type = RTE_BE16(UINT16_MAX),
2163 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2165 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2166 MLX5_FLOW_LAYER_INNER_L4) :
2167 (MLX5_FLOW_LAYER_OUTER_L3 |
2168 MLX5_FLOW_LAYER_OUTER_L4);
2169 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2170 MLX5_FLOW_LAYER_OUTER_VLAN;
2172 if (item_flags & vlanm)
2173 return rte_flow_error_set(error, EINVAL,
2174 RTE_FLOW_ERROR_TYPE_ITEM, item,
2175 "multiple VLAN layers not supported");
2176 else if ((item_flags & l34m) != 0)
2177 return rte_flow_error_set(error, EINVAL,
2178 RTE_FLOW_ERROR_TYPE_ITEM, item,
2179 "VLAN cannot follow L3/L4 layer");
2181 mask = &rte_flow_item_vlan_mask;
2182 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2183 (const uint8_t *)&nic_mask,
2184 sizeof(struct rte_flow_item_vlan),
2185 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2188 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2189 struct mlx5_priv *priv = dev->data->dev_private;
2191 if (priv->vmwa_context) {
2193 * Non-NULL context means we have a virtual machine
2194 * and SR-IOV enabled, we have to create VLAN interface
2195 * to make hypervisor to setup E-Switch vport
2196 * context correctly. We avoid creating the multiple
2197 * VLAN interfaces, so we cannot support VLAN tag mask.
2199 return rte_flow_error_set(error, EINVAL,
2200 RTE_FLOW_ERROR_TYPE_ITEM,
2202 "VLAN tag mask is not"
2203 " supported in virtual"
2211 * GTP flags are contained in 1 byte of the format:
2212 * -------------------------------------------
2213 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2214 * |-----------------------------------------|
2215 * | value | Version | PT | Res | E | S | PN |
2216 * -------------------------------------------
2218 * Matching is supported only for GTP flags E, S, PN.
2220 #define MLX5_GTP_FLAGS_MASK 0x07
2223 * Validate GTP item.
2226 * Pointer to the rte_eth_dev structure.
2228 * Item specification.
2229 * @param[in] item_flags
2230 * Bit-fields that holds the items detected until now.
2232 * Pointer to error structure.
2235 * 0 on success, a negative errno value otherwise and rte_errno is set.
2238 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2239 const struct rte_flow_item *item,
2240 uint64_t item_flags,
2241 struct rte_flow_error *error)
2243 struct mlx5_priv *priv = dev->data->dev_private;
2244 const struct rte_flow_item_gtp *spec = item->spec;
2245 const struct rte_flow_item_gtp *mask = item->mask;
2246 const struct rte_flow_item_gtp nic_mask = {
2247 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2249 .teid = RTE_BE32(0xffffffff),
2252 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2253 return rte_flow_error_set(error, ENOTSUP,
2254 RTE_FLOW_ERROR_TYPE_ITEM, item,
2255 "GTP support is not enabled");
2256 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2257 return rte_flow_error_set(error, ENOTSUP,
2258 RTE_FLOW_ERROR_TYPE_ITEM, item,
2259 "multiple tunnel layers not"
2261 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2262 return rte_flow_error_set(error, EINVAL,
2263 RTE_FLOW_ERROR_TYPE_ITEM, item,
2264 "no outer UDP layer found");
2266 mask = &rte_flow_item_gtp_mask;
2267 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2268 return rte_flow_error_set(error, ENOTSUP,
2269 RTE_FLOW_ERROR_TYPE_ITEM, item,
2270 "Match is supported for GTP"
2272 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2273 (const uint8_t *)&nic_mask,
2274 sizeof(struct rte_flow_item_gtp),
2275 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2279 * Validate GTP PSC item.
2282 * Item specification.
2283 * @param[in] last_item
2284 * Previous validated item in the pattern items.
2285 * @param[in] gtp_item
2286 * Previous GTP item specification.
2288 * Pointer to flow attributes.
2290 * Pointer to error structure.
2293 * 0 on success, a negative errno value otherwise and rte_errno is set.
2296 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2298 const struct rte_flow_item *gtp_item,
2299 const struct rte_flow_attr *attr,
2300 struct rte_flow_error *error)
2302 const struct rte_flow_item_gtp *gtp_spec;
2303 const struct rte_flow_item_gtp *gtp_mask;
2304 const struct rte_flow_item_gtp_psc *spec;
2305 const struct rte_flow_item_gtp_psc *mask;
2306 const struct rte_flow_item_gtp_psc nic_mask = {
2311 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2312 return rte_flow_error_set
2313 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2314 "GTP PSC item must be preceded with GTP item");
2315 gtp_spec = gtp_item->spec;
2316 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2317 /* GTP spec and E flag is requested to match zero. */
2319 (gtp_mask->v_pt_rsv_flags &
2320 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2321 return rte_flow_error_set
2322 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2323 "GTP E flag must be 1 to match GTP PSC");
2324 /* Check the flow is not created in group zero. */
2325 if (!attr->transfer && !attr->group)
2326 return rte_flow_error_set
2327 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2328 "GTP PSC is not supported for group 0");
2329 /* GTP spec is here and E flag is requested to match zero. */
2333 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2334 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2335 return rte_flow_error_set
2336 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2337 "PDU type should be smaller than 16");
2338 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2339 (const uint8_t *)&nic_mask,
2340 sizeof(struct rte_flow_item_gtp_psc),
2341 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2345 * Validate IPV4 item.
2346 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2347 * add specific validation of fragment_offset field,
2350 * Item specification.
2351 * @param[in] item_flags
2352 * Bit-fields that holds the items detected until now.
2354 * Pointer to error structure.
2357 * 0 on success, a negative errno value otherwise and rte_errno is set.
2360 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2361 uint64_t item_flags,
2363 uint16_t ether_type,
2364 struct rte_flow_error *error)
2367 const struct rte_flow_item_ipv4 *spec = item->spec;
2368 const struct rte_flow_item_ipv4 *last = item->last;
2369 const struct rte_flow_item_ipv4 *mask = item->mask;
2370 rte_be16_t fragment_offset_spec = 0;
2371 rte_be16_t fragment_offset_last = 0;
2372 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2374 .src_addr = RTE_BE32(0xffffffff),
2375 .dst_addr = RTE_BE32(0xffffffff),
2376 .type_of_service = 0xff,
2377 .fragment_offset = RTE_BE16(0xffff),
2378 .next_proto_id = 0xff,
2379 .time_to_live = 0xff,
2383 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2384 ether_type, &nic_ipv4_mask,
2385 MLX5_ITEM_RANGE_ACCEPTED, error);
2389 fragment_offset_spec = spec->hdr.fragment_offset &
2390 mask->hdr.fragment_offset;
2391 if (!fragment_offset_spec)
2394 * spec and mask are valid, enforce using full mask to make sure the
2395 * complete value is used correctly.
2397 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2398 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2399 return rte_flow_error_set(error, EINVAL,
2400 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2401 item, "must use full mask for"
2402 " fragment_offset");
2404 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2405 * indicating this is 1st fragment of fragmented packet.
2406 * This is not yet supported in MLX5, return appropriate error message.
2408 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2409 return rte_flow_error_set(error, ENOTSUP,
2410 RTE_FLOW_ERROR_TYPE_ITEM, item,
2411 "match on first fragment not "
2413 if (fragment_offset_spec && !last)
2414 return rte_flow_error_set(error, ENOTSUP,
2415 RTE_FLOW_ERROR_TYPE_ITEM, item,
2416 "specified value not supported");
2417 /* spec and last are valid, validate the specified range. */
2418 fragment_offset_last = last->hdr.fragment_offset &
2419 mask->hdr.fragment_offset;
2421 * Match on fragment_offset spec 0x2001 and last 0x3fff
2422 * means MF is 1 and frag-offset is > 0.
2423 * This packet is fragment 2nd and onward, excluding last.
2424 * This is not yet supported in MLX5, return appropriate
2427 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2428 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2429 return rte_flow_error_set(error, ENOTSUP,
2430 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2431 last, "match on following "
2432 "fragments not supported");
2434 * Match on fragment_offset spec 0x0001 and last 0x1fff
2435 * means MF is 0 and frag-offset is > 0.
2436 * This packet is last fragment of fragmented packet.
2437 * This is not yet supported in MLX5, return appropriate
2440 if (fragment_offset_spec == RTE_BE16(1) &&
2441 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2442 return rte_flow_error_set(error, ENOTSUP,
2443 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2444 last, "match on last "
2445 "fragment not supported");
2447 * Match on fragment_offset spec 0x0001 and last 0x3fff
2448 * means MF and/or frag-offset is not 0.
2449 * This is a fragmented packet.
2450 * Other range values are invalid and rejected.
2452 if (!(fragment_offset_spec == RTE_BE16(1) &&
2453 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2454 return rte_flow_error_set(error, ENOTSUP,
2455 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2456 "specified range not supported");
2461 * Validate IPV6 fragment extension item.
2464 * Item specification.
2465 * @param[in] item_flags
2466 * Bit-fields that holds the items detected until now.
2468 * Pointer to error structure.
2471 * 0 on success, a negative errno value otherwise and rte_errno is set.
2474 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2475 uint64_t item_flags,
2476 struct rte_flow_error *error)
2478 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2479 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2480 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2481 rte_be16_t frag_data_spec = 0;
2482 rte_be16_t frag_data_last = 0;
2483 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2484 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2485 MLX5_FLOW_LAYER_OUTER_L4;
2487 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2489 .next_header = 0xff,
2490 .frag_data = RTE_BE16(0xffff),
2494 if (item_flags & l4m)
2495 return rte_flow_error_set(error, EINVAL,
2496 RTE_FLOW_ERROR_TYPE_ITEM, item,
2497 "ipv6 fragment extension item cannot "
2499 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2500 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2501 return rte_flow_error_set(error, EINVAL,
2502 RTE_FLOW_ERROR_TYPE_ITEM, item,
2503 "ipv6 fragment extension item must "
2504 "follow ipv6 item");
2506 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2507 if (!frag_data_spec)
2510 * spec and mask are valid, enforce using full mask to make sure the
2511 * complete value is used correctly.
2513 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2514 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2515 return rte_flow_error_set(error, EINVAL,
2516 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2517 item, "must use full mask for"
2520 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2521 * This is 1st fragment of fragmented packet.
2523 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2524 return rte_flow_error_set(error, ENOTSUP,
2525 RTE_FLOW_ERROR_TYPE_ITEM, item,
2526 "match on first fragment not "
2528 if (frag_data_spec && !last)
2529 return rte_flow_error_set(error, EINVAL,
2530 RTE_FLOW_ERROR_TYPE_ITEM, item,
2531 "specified value not supported");
2532 ret = mlx5_flow_item_acceptable
2533 (item, (const uint8_t *)mask,
2534 (const uint8_t *)&nic_mask,
2535 sizeof(struct rte_flow_item_ipv6_frag_ext),
2536 MLX5_ITEM_RANGE_ACCEPTED, error);
2539 /* spec and last are valid, validate the specified range. */
2540 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2542 * Match on frag_data spec 0x0009 and last 0xfff9
2543 * means M is 1 and frag-offset is > 0.
2544 * This packet is fragment 2nd and onward, excluding last.
2545 * This is not yet supported in MLX5, return appropriate
2548 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2549 RTE_IPV6_EHDR_MF_MASK) &&
2550 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2551 return rte_flow_error_set(error, ENOTSUP,
2552 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2553 last, "match on following "
2554 "fragments not supported");
2556 * Match on frag_data spec 0x0008 and last 0xfff8
2557 * means M is 0 and frag-offset is > 0.
2558 * This packet is last fragment of fragmented packet.
2559 * This is not yet supported in MLX5, return appropriate
2562 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2563 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2564 return rte_flow_error_set(error, ENOTSUP,
2565 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2566 last, "match on last "
2567 "fragment not supported");
2568 /* Other range values are invalid and rejected. */
2569 return rte_flow_error_set(error, EINVAL,
2570 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2571 "specified range not supported");
2575 * Validate the pop VLAN action.
2578 * Pointer to the rte_eth_dev structure.
2579 * @param[in] action_flags
2580 * Holds the actions detected until now.
2582 * Pointer to the pop vlan action.
2583 * @param[in] item_flags
2584 * The items found in this flow rule.
2586 * Pointer to flow attributes.
2588 * Pointer to error structure.
2591 * 0 on success, a negative errno value otherwise and rte_errno is set.
2594 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2595 uint64_t action_flags,
2596 const struct rte_flow_action *action,
2597 uint64_t item_flags,
2598 const struct rte_flow_attr *attr,
2599 struct rte_flow_error *error)
2601 const struct mlx5_priv *priv = dev->data->dev_private;
2605 if (!priv->sh->pop_vlan_action)
2606 return rte_flow_error_set(error, ENOTSUP,
2607 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2609 "pop vlan action is not supported");
2611 return rte_flow_error_set(error, ENOTSUP,
2612 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2614 "pop vlan action not supported for "
2616 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2617 return rte_flow_error_set(error, ENOTSUP,
2618 RTE_FLOW_ERROR_TYPE_ACTION, action,
2619 "no support for multiple VLAN "
2621 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2622 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2623 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2624 return rte_flow_error_set(error, ENOTSUP,
2625 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2627 "cannot pop vlan after decap without "
2628 "match on inner vlan in the flow");
2629 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2630 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2631 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2632 return rte_flow_error_set(error, ENOTSUP,
2633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2635 "cannot pop vlan without a "
2636 "match on (outer) vlan in the flow");
2637 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2638 return rte_flow_error_set(error, EINVAL,
2639 RTE_FLOW_ERROR_TYPE_ACTION, action,
2640 "wrong action order, port_id should "
2641 "be after pop VLAN action");
2642 if (!attr->transfer && priv->representor)
2643 return rte_flow_error_set(error, ENOTSUP,
2644 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2645 "pop vlan action for VF representor "
2646 "not supported on NIC table");
2651 * Get VLAN default info from vlan match info.
2654 * the list of item specifications.
2656 * pointer VLAN info to fill to.
2659 * 0 on success, a negative errno value otherwise and rte_errno is set.
2662 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2663 struct rte_vlan_hdr *vlan)
2665 const struct rte_flow_item_vlan nic_mask = {
2666 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2667 MLX5DV_FLOW_VLAN_VID_MASK),
2668 .inner_type = RTE_BE16(0xffff),
2673 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2674 int type = items->type;
2676 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2677 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2680 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2681 const struct rte_flow_item_vlan *vlan_m = items->mask;
2682 const struct rte_flow_item_vlan *vlan_v = items->spec;
2684 /* If VLAN item in pattern doesn't contain data, return here. */
2689 /* Only full match values are accepted */
2690 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2691 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2692 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2694 rte_be_to_cpu_16(vlan_v->tci &
2695 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2697 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2698 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2699 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2701 rte_be_to_cpu_16(vlan_v->tci &
2702 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2704 if (vlan_m->inner_type == nic_mask.inner_type)
2705 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2706 vlan_m->inner_type);
2711 * Validate the push VLAN action.
2714 * Pointer to the rte_eth_dev structure.
2715 * @param[in] action_flags
2716 * Holds the actions detected until now.
2717 * @param[in] item_flags
2718 * The items found in this flow rule.
2720 * Pointer to the action structure.
2722 * Pointer to flow attributes
2724 * Pointer to error structure.
2727 * 0 on success, a negative errno value otherwise and rte_errno is set.
2730 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2731 uint64_t action_flags,
2732 const struct rte_flow_item_vlan *vlan_m,
2733 const struct rte_flow_action *action,
2734 const struct rte_flow_attr *attr,
2735 struct rte_flow_error *error)
2737 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2738 const struct mlx5_priv *priv = dev->data->dev_private;
2740 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2741 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2742 return rte_flow_error_set(error, EINVAL,
2743 RTE_FLOW_ERROR_TYPE_ACTION, action,
2744 "invalid vlan ethertype");
2745 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2746 return rte_flow_error_set(error, EINVAL,
2747 RTE_FLOW_ERROR_TYPE_ACTION, action,
2748 "wrong action order, port_id should "
2749 "be after push VLAN");
2750 if (!attr->transfer && priv->representor)
2751 return rte_flow_error_set(error, ENOTSUP,
2752 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2753 "push vlan action for VF representor "
2754 "not supported on NIC table");
2756 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2757 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2758 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2759 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2760 !(mlx5_flow_find_action
2761 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2762 return rte_flow_error_set(error, EINVAL,
2763 RTE_FLOW_ERROR_TYPE_ACTION, action,
2764 "not full match mask on VLAN PCP and "
2765 "there is no of_set_vlan_pcp action, "
2766 "push VLAN action cannot figure out "
2769 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2770 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2771 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2772 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2773 !(mlx5_flow_find_action
2774 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2775 return rte_flow_error_set(error, EINVAL,
2776 RTE_FLOW_ERROR_TYPE_ACTION, action,
2777 "not full match mask on VLAN VID and "
2778 "there is no of_set_vlan_vid action, "
2779 "push VLAN action cannot figure out "
2786 * Validate the set VLAN PCP.
2788 * @param[in] action_flags
2789 * Holds the actions detected until now.
2790 * @param[in] actions
2791 * Pointer to the list of actions remaining in the flow rule.
2793 * Pointer to error structure.
2796 * 0 on success, a negative errno value otherwise and rte_errno is set.
2799 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2800 const struct rte_flow_action actions[],
2801 struct rte_flow_error *error)
2803 const struct rte_flow_action *action = actions;
2804 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2806 if (conf->vlan_pcp > 7)
2807 return rte_flow_error_set(error, EINVAL,
2808 RTE_FLOW_ERROR_TYPE_ACTION, action,
2809 "VLAN PCP value is too big");
2810 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2811 return rte_flow_error_set(error, ENOTSUP,
2812 RTE_FLOW_ERROR_TYPE_ACTION, action,
2813 "set VLAN PCP action must follow "
2814 "the push VLAN action");
2815 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2816 return rte_flow_error_set(error, ENOTSUP,
2817 RTE_FLOW_ERROR_TYPE_ACTION, action,
2818 "Multiple VLAN PCP modification are "
2820 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2821 return rte_flow_error_set(error, EINVAL,
2822 RTE_FLOW_ERROR_TYPE_ACTION, action,
2823 "wrong action order, port_id should "
2824 "be after set VLAN PCP");
2829 * Validate the set VLAN VID.
2831 * @param[in] item_flags
2832 * Holds the items detected in this rule.
2833 * @param[in] action_flags
2834 * Holds the actions detected until now.
2835 * @param[in] actions
2836 * Pointer to the list of actions remaining in the flow rule.
2838 * Pointer to error structure.
2841 * 0 on success, a negative errno value otherwise and rte_errno is set.
2844 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2845 uint64_t action_flags,
2846 const struct rte_flow_action actions[],
2847 struct rte_flow_error *error)
2849 const struct rte_flow_action *action = actions;
2850 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2852 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2853 return rte_flow_error_set(error, EINVAL,
2854 RTE_FLOW_ERROR_TYPE_ACTION, action,
2855 "VLAN VID value is too big");
2856 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2857 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2858 return rte_flow_error_set(error, ENOTSUP,
2859 RTE_FLOW_ERROR_TYPE_ACTION, action,
2860 "set VLAN VID action must follow push"
2861 " VLAN action or match on VLAN item");
2862 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2863 return rte_flow_error_set(error, ENOTSUP,
2864 RTE_FLOW_ERROR_TYPE_ACTION, action,
2865 "Multiple VLAN VID modifications are "
2867 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2868 return rte_flow_error_set(error, EINVAL,
2869 RTE_FLOW_ERROR_TYPE_ACTION, action,
2870 "wrong action order, port_id should "
2871 "be after set VLAN VID");
2876 * Validate the FLAG action.
2879 * Pointer to the rte_eth_dev structure.
2880 * @param[in] action_flags
2881 * Holds the actions detected until now.
2883 * Pointer to flow attributes
2885 * Pointer to error structure.
2888 * 0 on success, a negative errno value otherwise and rte_errno is set.
2891 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2892 uint64_t action_flags,
2893 const struct rte_flow_attr *attr,
2894 struct rte_flow_error *error)
2896 struct mlx5_priv *priv = dev->data->dev_private;
2897 struct mlx5_dev_config *config = &priv->config;
2900 /* Fall back if no extended metadata register support. */
2901 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2902 return mlx5_flow_validate_action_flag(action_flags, attr,
2904 /* Extensive metadata mode requires registers. */
2905 if (!mlx5_flow_ext_mreg_supported(dev))
2906 return rte_flow_error_set(error, ENOTSUP,
2907 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2908 "no metadata registers "
2909 "to support flag action");
2910 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2911 return rte_flow_error_set(error, ENOTSUP,
2912 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2913 "extended metadata register"
2914 " isn't available");
2915 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2918 MLX5_ASSERT(ret > 0);
2919 if (action_flags & MLX5_FLOW_ACTION_MARK)
2920 return rte_flow_error_set(error, EINVAL,
2921 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2922 "can't mark and flag in same flow");
2923 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2924 return rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2927 " actions in same flow");
2932 * Validate MARK action.
2935 * Pointer to the rte_eth_dev structure.
2937 * Pointer to action.
2938 * @param[in] action_flags
2939 * Holds the actions detected until now.
2941 * Pointer to flow attributes
2943 * Pointer to error structure.
2946 * 0 on success, a negative errno value otherwise and rte_errno is set.
2949 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2950 const struct rte_flow_action *action,
2951 uint64_t action_flags,
2952 const struct rte_flow_attr *attr,
2953 struct rte_flow_error *error)
2955 struct mlx5_priv *priv = dev->data->dev_private;
2956 struct mlx5_dev_config *config = &priv->config;
2957 const struct rte_flow_action_mark *mark = action->conf;
2960 if (is_tunnel_offload_active(dev))
2961 return rte_flow_error_set(error, ENOTSUP,
2962 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2964 "if tunnel offload active");
2965 /* Fall back if no extended metadata register support. */
2966 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2967 return mlx5_flow_validate_action_mark(action, action_flags,
2969 /* Extensive metadata mode requires registers. */
2970 if (!mlx5_flow_ext_mreg_supported(dev))
2971 return rte_flow_error_set(error, ENOTSUP,
2972 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2973 "no metadata registers "
2974 "to support mark action");
2975 if (!priv->sh->dv_mark_mask)
2976 return rte_flow_error_set(error, ENOTSUP,
2977 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2978 "extended metadata register"
2979 " isn't available");
2980 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2983 MLX5_ASSERT(ret > 0);
2985 return rte_flow_error_set(error, EINVAL,
2986 RTE_FLOW_ERROR_TYPE_ACTION, action,
2987 "configuration cannot be null");
2988 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2989 return rte_flow_error_set(error, EINVAL,
2990 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2992 "mark id exceeds the limit");
2993 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2994 return rte_flow_error_set(error, EINVAL,
2995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2996 "can't flag and mark in same flow");
2997 if (action_flags & MLX5_FLOW_ACTION_MARK)
2998 return rte_flow_error_set(error, EINVAL,
2999 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3000 "can't have 2 mark actions in same"
3006 * Validate SET_META action.
3009 * Pointer to the rte_eth_dev structure.
3011 * Pointer to the action structure.
3012 * @param[in] action_flags
3013 * Holds the actions detected until now.
3015 * Pointer to flow attributes
3017 * Pointer to error structure.
3020 * 0 on success, a negative errno value otherwise and rte_errno is set.
3023 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3024 const struct rte_flow_action *action,
3025 uint64_t action_flags __rte_unused,
3026 const struct rte_flow_attr *attr,
3027 struct rte_flow_error *error)
3029 const struct rte_flow_action_set_meta *conf;
3030 uint32_t nic_mask = UINT32_MAX;
3033 if (!mlx5_flow_ext_mreg_supported(dev))
3034 return rte_flow_error_set(error, ENOTSUP,
3035 RTE_FLOW_ERROR_TYPE_ACTION, action,
3036 "extended metadata register"
3037 " isn't supported");
3038 reg = flow_dv_get_metadata_reg(dev, attr, error);
3042 return rte_flow_error_set(error, ENOTSUP,
3043 RTE_FLOW_ERROR_TYPE_ACTION, action,
3044 "unavalable extended metadata register");
3045 if (reg != REG_A && reg != REG_B) {
3046 struct mlx5_priv *priv = dev->data->dev_private;
3048 nic_mask = priv->sh->dv_meta_mask;
3050 if (!(action->conf))
3051 return rte_flow_error_set(error, EINVAL,
3052 RTE_FLOW_ERROR_TYPE_ACTION, action,
3053 "configuration cannot be null");
3054 conf = (const struct rte_flow_action_set_meta *)action->conf;
3056 return rte_flow_error_set(error, EINVAL,
3057 RTE_FLOW_ERROR_TYPE_ACTION, action,
3058 "zero mask doesn't have any effect");
3059 if (conf->mask & ~nic_mask)
3060 return rte_flow_error_set(error, EINVAL,
3061 RTE_FLOW_ERROR_TYPE_ACTION, action,
3062 "meta data must be within reg C0");
3067 * Validate SET_TAG action.
3070 * Pointer to the rte_eth_dev structure.
3072 * Pointer to the action structure.
3073 * @param[in] action_flags
3074 * Holds the actions detected until now.
3076 * Pointer to flow attributes
3078 * Pointer to error structure.
3081 * 0 on success, a negative errno value otherwise and rte_errno is set.
3084 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3085 const struct rte_flow_action *action,
3086 uint64_t action_flags,
3087 const struct rte_flow_attr *attr,
3088 struct rte_flow_error *error)
3090 const struct rte_flow_action_set_tag *conf;
3091 const uint64_t terminal_action_flags =
3092 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3093 MLX5_FLOW_ACTION_RSS;
3096 if (!mlx5_flow_ext_mreg_supported(dev))
3097 return rte_flow_error_set(error, ENOTSUP,
3098 RTE_FLOW_ERROR_TYPE_ACTION, action,
3099 "extensive metadata register"
3100 " isn't supported");
3101 if (!(action->conf))
3102 return rte_flow_error_set(error, EINVAL,
3103 RTE_FLOW_ERROR_TYPE_ACTION, action,
3104 "configuration cannot be null");
3105 conf = (const struct rte_flow_action_set_tag *)action->conf;
3107 return rte_flow_error_set(error, EINVAL,
3108 RTE_FLOW_ERROR_TYPE_ACTION, action,
3109 "zero mask doesn't have any effect");
3110 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3113 if (!attr->transfer && attr->ingress &&
3114 (action_flags & terminal_action_flags))
3115 return rte_flow_error_set(error, EINVAL,
3116 RTE_FLOW_ERROR_TYPE_ACTION, action,
3117 "set_tag has no effect"
3118 " with terminal actions");
3123 * Validate count action.
3126 * Pointer to rte_eth_dev structure.
3128 * Pointer to the action structure.
3129 * @param[in] action_flags
3130 * Holds the actions detected until now.
3132 * Pointer to error structure.
3135 * 0 on success, a negative errno value otherwise and rte_errno is set.
3138 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3139 const struct rte_flow_action *action,
3140 uint64_t action_flags,
3141 struct rte_flow_error *error)
3143 struct mlx5_priv *priv = dev->data->dev_private;
3144 const struct rte_flow_action_count *count;
3146 if (!priv->config.devx)
3148 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3149 return rte_flow_error_set(error, EINVAL,
3150 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3151 "duplicate count actions set");
3152 count = (const struct rte_flow_action_count *)action->conf;
3153 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3154 !priv->sh->flow_hit_aso_en)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "old age and shared count combination is not supported");
3158 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3162 return rte_flow_error_set
3164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3166 "count action not supported");
3170 * Validate the L2 encap action.
3173 * Pointer to the rte_eth_dev structure.
3174 * @param[in] action_flags
3175 * Holds the actions detected until now.
3177 * Pointer to the action structure.
3179 * Pointer to flow attributes.
3181 * Pointer to error structure.
3184 * 0 on success, a negative errno value otherwise and rte_errno is set.
3187 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3188 uint64_t action_flags,
3189 const struct rte_flow_action *action,
3190 const struct rte_flow_attr *attr,
3191 struct rte_flow_error *error)
3193 const struct mlx5_priv *priv = dev->data->dev_private;
3195 if (!(action->conf))
3196 return rte_flow_error_set(error, EINVAL,
3197 RTE_FLOW_ERROR_TYPE_ACTION, action,
3198 "configuration cannot be null");
3199 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3200 return rte_flow_error_set(error, EINVAL,
3201 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3202 "can only have a single encap action "
3204 if (!attr->transfer && priv->representor)
3205 return rte_flow_error_set(error, ENOTSUP,
3206 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3207 "encap action for VF representor "
3208 "not supported on NIC table");
3213 * Validate a decap action.
3216 * Pointer to the rte_eth_dev structure.
3217 * @param[in] action_flags
3218 * Holds the actions detected until now.
3220 * Pointer to the action structure.
3221 * @param[in] item_flags
3222 * Holds the items detected.
3224 * Pointer to flow attributes
3226 * Pointer to error structure.
3229 * 0 on success, a negative errno value otherwise and rte_errno is set.
3232 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3233 uint64_t action_flags,
3234 const struct rte_flow_action *action,
3235 const uint64_t item_flags,
3236 const struct rte_flow_attr *attr,
3237 struct rte_flow_error *error)
3239 const struct mlx5_priv *priv = dev->data->dev_private;
3241 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3242 !priv->config.decap_en)
3243 return rte_flow_error_set(error, ENOTSUP,
3244 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3245 "decap is not enabled");
3246 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3247 return rte_flow_error_set(error, ENOTSUP,
3248 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3250 MLX5_FLOW_ACTION_DECAP ? "can only "
3251 "have a single decap action" : "decap "
3252 "after encap is not supported");
3253 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3254 return rte_flow_error_set(error, EINVAL,
3255 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3256 "can't have decap action after"
3259 return rte_flow_error_set(error, ENOTSUP,
3260 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3262 "decap action not supported for "
3264 if (!attr->transfer && priv->representor)
3265 return rte_flow_error_set(error, ENOTSUP,
3266 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3267 "decap action for VF representor "
3268 "not supported on NIC table");
3269 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3270 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3271 return rte_flow_error_set(error, ENOTSUP,
3272 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3273 "VXLAN item should be present for VXLAN decap");
3277 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3280 * Validate the raw encap and decap actions.
3283 * Pointer to the rte_eth_dev structure.
3285 * Pointer to the decap action.
3287 * Pointer to the encap action.
3289 * Pointer to flow attributes
3290 * @param[in/out] action_flags
3291 * Holds the actions detected until now.
3292 * @param[out] actions_n
3293 * pointer to the number of actions counter.
3295 * Pointer to the action structure.
3296 * @param[in] item_flags
3297 * Holds the items detected.
3299 * Pointer to error structure.
3302 * 0 on success, a negative errno value otherwise and rte_errno is set.
3305 flow_dv_validate_action_raw_encap_decap
3306 (struct rte_eth_dev *dev,
3307 const struct rte_flow_action_raw_decap *decap,
3308 const struct rte_flow_action_raw_encap *encap,
3309 const struct rte_flow_attr *attr, uint64_t *action_flags,
3310 int *actions_n, const struct rte_flow_action *action,
3311 uint64_t item_flags, struct rte_flow_error *error)
3313 const struct mlx5_priv *priv = dev->data->dev_private;
3316 if (encap && (!encap->size || !encap->data))
3317 return rte_flow_error_set(error, EINVAL,
3318 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3319 "raw encap data cannot be empty");
3320 if (decap && encap) {
3321 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3322 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3325 else if (encap->size <=
3326 MLX5_ENCAPSULATION_DECISION_SIZE &&
3328 MLX5_ENCAPSULATION_DECISION_SIZE)
3331 else if (encap->size >
3332 MLX5_ENCAPSULATION_DECISION_SIZE &&
3334 MLX5_ENCAPSULATION_DECISION_SIZE)
3335 /* 2 L2 actions: encap and decap. */
3338 return rte_flow_error_set(error,
3340 RTE_FLOW_ERROR_TYPE_ACTION,
3341 NULL, "unsupported too small "
3342 "raw decap and too small raw "
3343 "encap combination");
3346 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3347 item_flags, attr, error);
3350 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3354 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3355 return rte_flow_error_set(error, ENOTSUP,
3356 RTE_FLOW_ERROR_TYPE_ACTION,
3358 "small raw encap size");
3359 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3360 return rte_flow_error_set(error, EINVAL,
3361 RTE_FLOW_ERROR_TYPE_ACTION,
3363 "more than one encap action");
3364 if (!attr->transfer && priv->representor)
3365 return rte_flow_error_set
3367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368 "encap action for VF representor "
3369 "not supported on NIC table");
3370 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3377 * Match encap_decap resource.
3380 * Pointer to the hash list.
3382 * Pointer to exist resource entry object.
3384 * Key of the new entry.
3386 * Pointer to new encap_decap resource.
3389 * 0 on matching, none-zero otherwise.
3392 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3393 struct mlx5_hlist_entry *entry,
3394 uint64_t key __rte_unused, void *cb_ctx)
3396 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3397 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3398 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3400 cache_resource = container_of(entry,
3401 struct mlx5_flow_dv_encap_decap_resource,
3403 if (resource->reformat_type == cache_resource->reformat_type &&
3404 resource->ft_type == cache_resource->ft_type &&
3405 resource->flags == cache_resource->flags &&
3406 resource->size == cache_resource->size &&
3407 !memcmp((const void *)resource->buf,
3408 (const void *)cache_resource->buf,
3415 * Allocate encap_decap resource.
3418 * Pointer to the hash list.
3420 * Pointer to exist resource entry object.
3422 * Pointer to new encap_decap resource.
3425 * 0 on matching, none-zero otherwise.
3427 struct mlx5_hlist_entry *
3428 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3429 uint64_t key __rte_unused,
3432 struct mlx5_dev_ctx_shared *sh = list->ctx;
3433 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3434 struct mlx5dv_dr_domain *domain;
3435 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3436 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3440 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3441 domain = sh->fdb_domain;
3442 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3443 domain = sh->rx_domain;
3445 domain = sh->tx_domain;
3446 /* Register new encap/decap resource. */
3447 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3449 if (!cache_resource) {
3450 rte_flow_error_set(ctx->error, ENOMEM,
3451 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3452 "cannot allocate resource memory");
3455 *cache_resource = *resource;
3456 cache_resource->idx = idx;
3457 ret = mlx5_flow_os_create_flow_action_packet_reformat
3458 (sh->ctx, domain, cache_resource,
3459 &cache_resource->action);
3461 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3462 rte_flow_error_set(ctx->error, ENOMEM,
3463 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3464 NULL, "cannot create action");
3468 return &cache_resource->entry;
3472 * Find existing encap/decap resource or create and register a new one.
3474 * @param[in, out] dev
3475 * Pointer to rte_eth_dev structure.
3476 * @param[in, out] resource
3477 * Pointer to encap/decap resource.
3478 * @parm[in, out] dev_flow
3479 * Pointer to the dev_flow.
3481 * pointer to error structure.
3484 * 0 on success otherwise -errno and errno is set.
3487 flow_dv_encap_decap_resource_register
3488 (struct rte_eth_dev *dev,
3489 struct mlx5_flow_dv_encap_decap_resource *resource,
3490 struct mlx5_flow *dev_flow,
3491 struct rte_flow_error *error)
3493 struct mlx5_priv *priv = dev->data->dev_private;
3494 struct mlx5_dev_ctx_shared *sh = priv->sh;
3495 struct mlx5_hlist_entry *entry;
3499 uint32_t refmt_type:8;
3501 * Header reformat actions can be shared between
3502 * non-root tables. One bit to indicate non-root
3506 uint32_t reserve:15;
3509 } encap_decap_key = {
3511 .ft_type = resource->ft_type,
3512 .refmt_type = resource->reformat_type,
3513 .is_root = !!dev_flow->dv.group,
3517 struct mlx5_flow_cb_ctx ctx = {
3523 resource->flags = dev_flow->dv.group ? 0 : 1;
3524 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3525 sizeof(encap_decap_key.v32), 0);
3526 if (resource->reformat_type !=
3527 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3529 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3530 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3533 resource = container_of(entry, typeof(*resource), entry);
3534 dev_flow->dv.encap_decap = resource;
3535 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3540 * Find existing table jump resource or create and register a new one.
3542 * @param[in, out] dev
3543 * Pointer to rte_eth_dev structure.
3544 * @param[in, out] tbl
3545 * Pointer to flow table resource.
3546 * @parm[in, out] dev_flow
3547 * Pointer to the dev_flow.
3549 * pointer to error structure.
3552 * 0 on success otherwise -errno and errno is set.
3555 flow_dv_jump_tbl_resource_register
3556 (struct rte_eth_dev *dev __rte_unused,
3557 struct mlx5_flow_tbl_resource *tbl,
3558 struct mlx5_flow *dev_flow,
3559 struct rte_flow_error *error __rte_unused)
3561 struct mlx5_flow_tbl_data_entry *tbl_data =
3562 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3565 MLX5_ASSERT(tbl_data->jump.action);
3566 dev_flow->handle->rix_jump = tbl_data->idx;
3567 dev_flow->dv.jump = &tbl_data->jump;
3572 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3573 struct mlx5_cache_entry *entry, void *cb_ctx)
3575 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3576 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3577 struct mlx5_flow_dv_port_id_action_resource *res =
3578 container_of(entry, typeof(*res), entry);
3580 return ref->port_id != res->port_id;
3583 struct mlx5_cache_entry *
3584 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3585 struct mlx5_cache_entry *entry __rte_unused,
3588 struct mlx5_dev_ctx_shared *sh = list->ctx;
3589 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3590 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3591 struct mlx5_flow_dv_port_id_action_resource *cache;
3595 /* Register new port id action resource. */
3596 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3598 rte_flow_error_set(ctx->error, ENOMEM,
3599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3600 "cannot allocate port_id action cache memory");
3604 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3608 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3609 rte_flow_error_set(ctx->error, ENOMEM,
3610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3611 "cannot create action");
3615 return &cache->entry;
3619 * Find existing table port ID resource or create and register a new one.
3621 * @param[in, out] dev
3622 * Pointer to rte_eth_dev structure.
3623 * @param[in, out] resource
3624 * Pointer to port ID action resource.
3625 * @parm[in, out] dev_flow
3626 * Pointer to the dev_flow.
3628 * pointer to error structure.
3631 * 0 on success otherwise -errno and errno is set.
3634 flow_dv_port_id_action_resource_register
3635 (struct rte_eth_dev *dev,
3636 struct mlx5_flow_dv_port_id_action_resource *resource,
3637 struct mlx5_flow *dev_flow,
3638 struct rte_flow_error *error)
3640 struct mlx5_priv *priv = dev->data->dev_private;
3641 struct mlx5_cache_entry *entry;
3642 struct mlx5_flow_dv_port_id_action_resource *cache;
3643 struct mlx5_flow_cb_ctx ctx = {
3648 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3651 cache = container_of(entry, typeof(*cache), entry);
3652 dev_flow->dv.port_id_action = cache;
3653 dev_flow->handle->rix_port_id_action = cache->idx;
3658 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3659 struct mlx5_cache_entry *entry, void *cb_ctx)
3661 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3662 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3663 struct mlx5_flow_dv_push_vlan_action_resource *res =
3664 container_of(entry, typeof(*res), entry);
3666 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3669 struct mlx5_cache_entry *
3670 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3671 struct mlx5_cache_entry *entry __rte_unused,
3674 struct mlx5_dev_ctx_shared *sh = list->ctx;
3675 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3676 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3677 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3678 struct mlx5dv_dr_domain *domain;
3682 /* Register new port id action resource. */
3683 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3685 rte_flow_error_set(ctx->error, ENOMEM,
3686 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3687 "cannot allocate push_vlan action cache memory");
3691 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3692 domain = sh->fdb_domain;
3693 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3694 domain = sh->rx_domain;
3696 domain = sh->tx_domain;
3697 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3700 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3701 rte_flow_error_set(ctx->error, ENOMEM,
3702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3703 "cannot create push vlan action");
3707 return &cache->entry;
3711 * Find existing push vlan resource or create and register a new one.
3713 * @param [in, out] dev
3714 * Pointer to rte_eth_dev structure.
3715 * @param[in, out] resource
3716 * Pointer to port ID action resource.
3717 * @parm[in, out] dev_flow
3718 * Pointer to the dev_flow.
3720 * pointer to error structure.
3723 * 0 on success otherwise -errno and errno is set.
3726 flow_dv_push_vlan_action_resource_register
3727 (struct rte_eth_dev *dev,
3728 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3729 struct mlx5_flow *dev_flow,
3730 struct rte_flow_error *error)
3732 struct mlx5_priv *priv = dev->data->dev_private;
3733 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3734 struct mlx5_cache_entry *entry;
3735 struct mlx5_flow_cb_ctx ctx = {
3740 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3743 cache = container_of(entry, typeof(*cache), entry);
3745 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3746 dev_flow->dv.push_vlan_res = cache;
3751 * Get the size of specific rte_flow_item_type hdr size
3753 * @param[in] item_type
3754 * Tested rte_flow_item_type.
3757 * sizeof struct item_type, 0 if void or irrelevant.
3760 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3764 switch (item_type) {
3765 case RTE_FLOW_ITEM_TYPE_ETH:
3766 retval = sizeof(struct rte_ether_hdr);
3768 case RTE_FLOW_ITEM_TYPE_VLAN:
3769 retval = sizeof(struct rte_vlan_hdr);
3771 case RTE_FLOW_ITEM_TYPE_IPV4:
3772 retval = sizeof(struct rte_ipv4_hdr);
3774 case RTE_FLOW_ITEM_TYPE_IPV6:
3775 retval = sizeof(struct rte_ipv6_hdr);
3777 case RTE_FLOW_ITEM_TYPE_UDP:
3778 retval = sizeof(struct rte_udp_hdr);
3780 case RTE_FLOW_ITEM_TYPE_TCP:
3781 retval = sizeof(struct rte_tcp_hdr);
3783 case RTE_FLOW_ITEM_TYPE_VXLAN:
3784 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3785 retval = sizeof(struct rte_vxlan_hdr);
3787 case RTE_FLOW_ITEM_TYPE_GRE:
3788 case RTE_FLOW_ITEM_TYPE_NVGRE:
3789 retval = sizeof(struct rte_gre_hdr);
3791 case RTE_FLOW_ITEM_TYPE_MPLS:
3792 retval = sizeof(struct rte_mpls_hdr);
3794 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3802 #define MLX5_ENCAP_IPV4_VERSION 0x40
3803 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3804 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3805 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3806 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3807 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3808 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3811 * Convert the encap action data from list of rte_flow_item to raw buffer
3814 * Pointer to rte_flow_item objects list.
3816 * Pointer to the output buffer.
3818 * Pointer to the output buffer size.
3820 * Pointer to the error structure.
3823 * 0 on success, a negative errno value otherwise and rte_errno is set.
3826 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3827 size_t *size, struct rte_flow_error *error)
3829 struct rte_ether_hdr *eth = NULL;
3830 struct rte_vlan_hdr *vlan = NULL;
3831 struct rte_ipv4_hdr *ipv4 = NULL;
3832 struct rte_ipv6_hdr *ipv6 = NULL;
3833 struct rte_udp_hdr *udp = NULL;
3834 struct rte_vxlan_hdr *vxlan = NULL;
3835 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3836 struct rte_gre_hdr *gre = NULL;
3838 size_t temp_size = 0;
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION,
3843 NULL, "invalid empty data");
3844 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3845 len = flow_dv_get_item_hdr_len(items->type);
3846 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3847 return rte_flow_error_set(error, EINVAL,
3848 RTE_FLOW_ERROR_TYPE_ACTION,
3849 (void *)items->type,
3850 "items total size is too big"
3851 " for encap action");
3852 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3853 switch (items->type) {
3854 case RTE_FLOW_ITEM_TYPE_ETH:
3855 eth = (struct rte_ether_hdr *)&buf[temp_size];
3857 case RTE_FLOW_ITEM_TYPE_VLAN:
3858 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3860 return rte_flow_error_set(error, EINVAL,
3861 RTE_FLOW_ERROR_TYPE_ACTION,
3862 (void *)items->type,
3863 "eth header not found");
3864 if (!eth->ether_type)
3865 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3867 case RTE_FLOW_ITEM_TYPE_IPV4:
3868 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3870 return rte_flow_error_set(error, EINVAL,
3871 RTE_FLOW_ERROR_TYPE_ACTION,
3872 (void *)items->type,
3873 "neither eth nor vlan"
3875 if (vlan && !vlan->eth_proto)
3876 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3877 else if (eth && !eth->ether_type)
3878 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3879 if (!ipv4->version_ihl)
3880 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3881 MLX5_ENCAP_IPV4_IHL_MIN;
3882 if (!ipv4->time_to_live)
3883 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3885 case RTE_FLOW_ITEM_TYPE_IPV6:
3886 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3888 return rte_flow_error_set(error, EINVAL,
3889 RTE_FLOW_ERROR_TYPE_ACTION,
3890 (void *)items->type,
3891 "neither eth nor vlan"
3893 if (vlan && !vlan->eth_proto)
3894 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3895 else if (eth && !eth->ether_type)
3896 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3897 if (!ipv6->vtc_flow)
3899 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3900 if (!ipv6->hop_limits)
3901 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3903 case RTE_FLOW_ITEM_TYPE_UDP:
3904 udp = (struct rte_udp_hdr *)&buf[temp_size];
3906 return rte_flow_error_set(error, EINVAL,
3907 RTE_FLOW_ERROR_TYPE_ACTION,
3908 (void *)items->type,
3909 "ip header not found");
3910 if (ipv4 && !ipv4->next_proto_id)
3911 ipv4->next_proto_id = IPPROTO_UDP;
3912 else if (ipv6 && !ipv6->proto)
3913 ipv6->proto = IPPROTO_UDP;
3915 case RTE_FLOW_ITEM_TYPE_VXLAN:
3916 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3918 return rte_flow_error_set(error, EINVAL,
3919 RTE_FLOW_ERROR_TYPE_ACTION,
3920 (void *)items->type,
3921 "udp header not found");
3923 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3924 if (!vxlan->vx_flags)
3926 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3928 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3929 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3931 return rte_flow_error_set(error, EINVAL,
3932 RTE_FLOW_ERROR_TYPE_ACTION,
3933 (void *)items->type,
3934 "udp header not found");
3935 if (!vxlan_gpe->proto)
3936 return rte_flow_error_set(error, EINVAL,
3937 RTE_FLOW_ERROR_TYPE_ACTION,
3938 (void *)items->type,
3939 "next protocol not found");
3942 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3943 if (!vxlan_gpe->vx_flags)
3944 vxlan_gpe->vx_flags =
3945 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3947 case RTE_FLOW_ITEM_TYPE_GRE:
3948 case RTE_FLOW_ITEM_TYPE_NVGRE:
3949 gre = (struct rte_gre_hdr *)&buf[temp_size];
3951 return rte_flow_error_set(error, EINVAL,
3952 RTE_FLOW_ERROR_TYPE_ACTION,
3953 (void *)items->type,
3954 "next protocol not found");
3956 return rte_flow_error_set(error, EINVAL,
3957 RTE_FLOW_ERROR_TYPE_ACTION,
3958 (void *)items->type,
3959 "ip header not found");
3960 if (ipv4 && !ipv4->next_proto_id)
3961 ipv4->next_proto_id = IPPROTO_GRE;
3962 else if (ipv6 && !ipv6->proto)
3963 ipv6->proto = IPPROTO_GRE;
3965 case RTE_FLOW_ITEM_TYPE_VOID:
3968 return rte_flow_error_set(error, EINVAL,
3969 RTE_FLOW_ERROR_TYPE_ACTION,
3970 (void *)items->type,
3971 "unsupported item type");
3981 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3983 struct rte_ether_hdr *eth = NULL;
3984 struct rte_vlan_hdr *vlan = NULL;
3985 struct rte_ipv6_hdr *ipv6 = NULL;
3986 struct rte_udp_hdr *udp = NULL;
3990 eth = (struct rte_ether_hdr *)data;
3991 next_hdr = (char *)(eth + 1);
3992 proto = RTE_BE16(eth->ether_type);
3995 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3996 vlan = (struct rte_vlan_hdr *)next_hdr;
3997 proto = RTE_BE16(vlan->eth_proto);
3998 next_hdr += sizeof(struct rte_vlan_hdr);
4001 /* HW calculates IPv4 csum. no need to proceed */
4002 if (proto == RTE_ETHER_TYPE_IPV4)
4005 /* non IPv4/IPv6 header. not supported */
4006 if (proto != RTE_ETHER_TYPE_IPV6) {
4007 return rte_flow_error_set(error, ENOTSUP,
4008 RTE_FLOW_ERROR_TYPE_ACTION,
4009 NULL, "Cannot offload non IPv4/IPv6");
4012 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4014 /* ignore non UDP */
4015 if (ipv6->proto != IPPROTO_UDP)
4018 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4019 udp->dgram_cksum = 0;
4025 * Convert L2 encap action to DV specification.
4028 * Pointer to rte_eth_dev structure.
4030 * Pointer to action structure.
4031 * @param[in, out] dev_flow
4032 * Pointer to the mlx5_flow.
4033 * @param[in] transfer
4034 * Mark if the flow is E-Switch flow.
4036 * Pointer to the error structure.
4039 * 0 on success, a negative errno value otherwise and rte_errno is set.
4042 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4043 const struct rte_flow_action *action,
4044 struct mlx5_flow *dev_flow,
4046 struct rte_flow_error *error)
4048 const struct rte_flow_item *encap_data;
4049 const struct rte_flow_action_raw_encap *raw_encap_data;
4050 struct mlx5_flow_dv_encap_decap_resource res = {
4052 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4053 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4054 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4057 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4059 (const struct rte_flow_action_raw_encap *)action->conf;
4060 res.size = raw_encap_data->size;
4061 memcpy(res.buf, raw_encap_data->data, res.size);
4063 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4065 ((const struct rte_flow_action_vxlan_encap *)
4066 action->conf)->definition;
4069 ((const struct rte_flow_action_nvgre_encap *)
4070 action->conf)->definition;
4071 if (flow_dv_convert_encap_data(encap_data, res.buf,
4075 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4077 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4078 return rte_flow_error_set(error, EINVAL,
4079 RTE_FLOW_ERROR_TYPE_ACTION,
4080 NULL, "can't create L2 encap action");
4085 * Convert L2 decap action to DV specification.
4088 * Pointer to rte_eth_dev structure.
4089 * @param[in, out] dev_flow
4090 * Pointer to the mlx5_flow.
4091 * @param[in] transfer
4092 * Mark if the flow is E-Switch flow.
4094 * Pointer to the error structure.
4097 * 0 on success, a negative errno value otherwise and rte_errno is set.
4100 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4101 struct mlx5_flow *dev_flow,
4103 struct rte_flow_error *error)
4105 struct mlx5_flow_dv_encap_decap_resource res = {
4108 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4109 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4110 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4113 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4114 return rte_flow_error_set(error, EINVAL,
4115 RTE_FLOW_ERROR_TYPE_ACTION,
4116 NULL, "can't create L2 decap action");
4121 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4124 * Pointer to rte_eth_dev structure.
4126 * Pointer to action structure.
4127 * @param[in, out] dev_flow
4128 * Pointer to the mlx5_flow.
4130 * Pointer to the flow attributes.
4132 * Pointer to the error structure.
4135 * 0 on success, a negative errno value otherwise and rte_errno is set.
4138 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4139 const struct rte_flow_action *action,
4140 struct mlx5_flow *dev_flow,
4141 const struct rte_flow_attr *attr,
4142 struct rte_flow_error *error)
4144 const struct rte_flow_action_raw_encap *encap_data;
4145 struct mlx5_flow_dv_encap_decap_resource res;
4147 memset(&res, 0, sizeof(res));
4148 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4149 res.size = encap_data->size;
4150 memcpy(res.buf, encap_data->data, res.size);
4151 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4152 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4153 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4155 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4157 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4158 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4159 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4160 return rte_flow_error_set(error, EINVAL,
4161 RTE_FLOW_ERROR_TYPE_ACTION,
4162 NULL, "can't create encap action");
4167 * Create action push VLAN.
4170 * Pointer to rte_eth_dev structure.
4172 * Pointer to the flow attributes.
4174 * Pointer to the vlan to push to the Ethernet header.
4175 * @param[in, out] dev_flow
4176 * Pointer to the mlx5_flow.
4178 * Pointer to the error structure.
4181 * 0 on success, a negative errno value otherwise and rte_errno is set.
4184 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4185 const struct rte_flow_attr *attr,
4186 const struct rte_vlan_hdr *vlan,
4187 struct mlx5_flow *dev_flow,
4188 struct rte_flow_error *error)
4190 struct mlx5_flow_dv_push_vlan_action_resource res;
4192 memset(&res, 0, sizeof(res));
4194 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4197 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4199 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4200 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4201 return flow_dv_push_vlan_action_resource_register
4202 (dev, &res, dev_flow, error);
4206 * Validate the modify-header actions.
4208 * @param[in] action_flags
4209 * Holds the actions detected until now.
4211 * Pointer to the modify action.
4213 * Pointer to error structure.
4216 * 0 on success, a negative errno value otherwise and rte_errno is set.
4219 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4220 const struct rte_flow_action *action,
4221 struct rte_flow_error *error)
4223 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4224 return rte_flow_error_set(error, EINVAL,
4225 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4226 NULL, "action configuration not set");
4227 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4228 return rte_flow_error_set(error, EINVAL,
4229 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4230 "can't have encap action before"
4236 * Validate the modify-header MAC address actions.
4238 * @param[in] action_flags
4239 * Holds the actions detected until now.
4241 * Pointer to the modify action.
4242 * @param[in] item_flags
4243 * Holds the items detected.
4245 * Pointer to error structure.
4248 * 0 on success, a negative errno value otherwise and rte_errno is set.
4251 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4252 const struct rte_flow_action *action,
4253 const uint64_t item_flags,
4254 struct rte_flow_error *error)
4258 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4260 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4261 return rte_flow_error_set(error, EINVAL,
4262 RTE_FLOW_ERROR_TYPE_ACTION,
4264 "no L2 item in pattern");
4270 * Validate the modify-header IPv4 address actions.
4272 * @param[in] action_flags
4273 * Holds the actions detected until now.
4275 * Pointer to the modify action.
4276 * @param[in] item_flags
4277 * Holds the items detected.
4279 * Pointer to error structure.
4282 * 0 on success, a negative errno value otherwise and rte_errno is set.
4285 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4286 const struct rte_flow_action *action,
4287 const uint64_t item_flags,
4288 struct rte_flow_error *error)
4293 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4295 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4296 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4297 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4298 if (!(item_flags & layer))
4299 return rte_flow_error_set(error, EINVAL,
4300 RTE_FLOW_ERROR_TYPE_ACTION,
4302 "no ipv4 item in pattern");
4308 * Validate the modify-header IPv6 address actions.
4310 * @param[in] action_flags
4311 * Holds the actions detected until now.
4313 * Pointer to the modify action.
4314 * @param[in] item_flags
4315 * Holds the items detected.
4317 * Pointer to error structure.
4320 * 0 on success, a negative errno value otherwise and rte_errno is set.
4323 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4324 const struct rte_flow_action *action,
4325 const uint64_t item_flags,
4326 struct rte_flow_error *error)
4331 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4333 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4334 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4335 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4336 if (!(item_flags & layer))
4337 return rte_flow_error_set(error, EINVAL,
4338 RTE_FLOW_ERROR_TYPE_ACTION,
4340 "no ipv6 item in pattern");
4346 * Validate the modify-header TP actions.
4348 * @param[in] action_flags
4349 * Holds the actions detected until now.
4351 * Pointer to the modify action.
4352 * @param[in] item_flags
4353 * Holds the items detected.
4355 * Pointer to error structure.
4358 * 0 on success, a negative errno value otherwise and rte_errno is set.
4361 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4362 const struct rte_flow_action *action,
4363 const uint64_t item_flags,
4364 struct rte_flow_error *error)
4369 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4371 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4372 MLX5_FLOW_LAYER_INNER_L4 :
4373 MLX5_FLOW_LAYER_OUTER_L4;
4374 if (!(item_flags & layer))
4375 return rte_flow_error_set(error, EINVAL,
4376 RTE_FLOW_ERROR_TYPE_ACTION,
4377 NULL, "no transport layer "
4384 * Validate the modify-header actions of increment/decrement
4385 * TCP Sequence-number.
4387 * @param[in] action_flags
4388 * Holds the actions detected until now.
4390 * Pointer to the modify action.
4391 * @param[in] item_flags
4392 * Holds the items detected.
4394 * Pointer to error structure.
4397 * 0 on success, a negative errno value otherwise and rte_errno is set.
4400 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4401 const struct rte_flow_action *action,
4402 const uint64_t item_flags,
4403 struct rte_flow_error *error)
4408 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4410 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4411 MLX5_FLOW_LAYER_INNER_L4_TCP :
4412 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4413 if (!(item_flags & layer))
4414 return rte_flow_error_set(error, EINVAL,
4415 RTE_FLOW_ERROR_TYPE_ACTION,
4416 NULL, "no TCP item in"
4418 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4419 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4420 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4421 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4422 return rte_flow_error_set(error, EINVAL,
4423 RTE_FLOW_ERROR_TYPE_ACTION,
4425 "cannot decrease and increase"
4426 " TCP sequence number"
4427 " at the same time");
4433 * Validate the modify-header actions of increment/decrement
4434 * TCP Acknowledgment number.
4436 * @param[in] action_flags
4437 * Holds the actions detected until now.
4439 * Pointer to the modify action.
4440 * @param[in] item_flags
4441 * Holds the items detected.
4443 * Pointer to error structure.
4446 * 0 on success, a negative errno value otherwise and rte_errno is set.
4449 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4450 const struct rte_flow_action *action,
4451 const uint64_t item_flags,
4452 struct rte_flow_error *error)
4457 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4459 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4460 MLX5_FLOW_LAYER_INNER_L4_TCP :
4461 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4462 if (!(item_flags & layer))
4463 return rte_flow_error_set(error, EINVAL,
4464 RTE_FLOW_ERROR_TYPE_ACTION,
4465 NULL, "no TCP item in"
4467 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4468 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4469 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4470 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4471 return rte_flow_error_set(error, EINVAL,
4472 RTE_FLOW_ERROR_TYPE_ACTION,
4474 "cannot decrease and increase"
4475 " TCP acknowledgment number"
4476 " at the same time");
4482 * Validate the modify-header TTL actions.
4484 * @param[in] action_flags
4485 * Holds the actions detected until now.
4487 * Pointer to the modify action.
4488 * @param[in] item_flags
4489 * Holds the items detected.
4491 * Pointer to error structure.
4494 * 0 on success, a negative errno value otherwise and rte_errno is set.
4497 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4498 const struct rte_flow_action *action,
4499 const uint64_t item_flags,
4500 struct rte_flow_error *error)
4505 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4507 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4508 MLX5_FLOW_LAYER_INNER_L3 :
4509 MLX5_FLOW_LAYER_OUTER_L3;
4510 if (!(item_flags & layer))
4511 return rte_flow_error_set(error, EINVAL,
4512 RTE_FLOW_ERROR_TYPE_ACTION,
4514 "no IP protocol in pattern");
4520 * Validate the generic modify field actions.
4522 * Pointer to the rte_eth_dev structure.
4523 * @param[in] action_flags
4524 * Holds the actions detected until now.
4526 * Pointer to the modify action.
4528 * Pointer to the flow attributes.
4530 * Pointer to error structure.
4533 * Number of header fields to modify (0 or more) on success,
4534 * a negative errno value otherwise and rte_errno is set.
4537 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4538 const uint64_t action_flags,
4539 const struct rte_flow_action *action,
4540 const struct rte_flow_attr *attr,
4541 struct rte_flow_error *error)
4544 struct mlx5_priv *priv = dev->data->dev_private;
4545 struct mlx5_dev_config *config = &priv->config;
4546 const struct rte_flow_action_modify_field *action_modify_field =
4548 uint32_t dst_width =
4549 mlx5_flow_item_field_width(action_modify_field->dst.field);
4550 uint32_t src_width =
4551 mlx5_flow_item_field_width(action_modify_field->src.field);
4553 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4557 if (action_modify_field->width == 0)
4558 return rte_flow_error_set(error, EINVAL,
4559 RTE_FLOW_ERROR_TYPE_ACTION, action,
4560 "no bits are requested to be modified");
4561 else if (action_modify_field->width > dst_width ||
4562 action_modify_field->width > src_width)
4563 return rte_flow_error_set(error, EINVAL,
4564 RTE_FLOW_ERROR_TYPE_ACTION, action,
4565 "cannot modify more bits than"
4566 " the width of a field");
4567 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4568 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4569 if ((action_modify_field->dst.offset +
4570 action_modify_field->width > dst_width) ||
4571 (action_modify_field->dst.offset % 32))
4572 return rte_flow_error_set(error, EINVAL,
4573 RTE_FLOW_ERROR_TYPE_ACTION, action,
4574 "destination offset is too big"
4575 " or not aligned to 4 bytes");
4576 if (action_modify_field->dst.level &&
4577 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4578 return rte_flow_error_set(error, ENOTSUP,
4579 RTE_FLOW_ERROR_TYPE_ACTION, action,
4580 "inner header fields modification"
4581 " is not supported");
4583 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4584 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4585 if (!attr->transfer && !attr->group)
4586 return rte_flow_error_set(error, ENOTSUP,
4587 RTE_FLOW_ERROR_TYPE_ACTION, action,
4588 "modify field action is not"
4589 " supported for group 0");
4590 if ((action_modify_field->src.offset +
4591 action_modify_field->width > src_width) ||
4592 (action_modify_field->src.offset % 32))
4593 return rte_flow_error_set(error, EINVAL,
4594 RTE_FLOW_ERROR_TYPE_ACTION, action,
4595 "source offset is too big"
4596 " or not aligned to 4 bytes");
4597 if (action_modify_field->src.level &&
4598 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4599 return rte_flow_error_set(error, ENOTSUP,
4600 RTE_FLOW_ERROR_TYPE_ACTION, action,
4601 "inner header fields modification"
4602 " is not supported");
4604 if (action_modify_field->dst.field ==
4605 action_modify_field->src.field)
4606 return rte_flow_error_set(error, EINVAL,
4607 RTE_FLOW_ERROR_TYPE_ACTION, action,
4608 "source and destination fields"
4609 " cannot be the same");
4610 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4611 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4612 return rte_flow_error_set(error, EINVAL,
4613 RTE_FLOW_ERROR_TYPE_ACTION, action,
4614 "immediate value or a pointer to it"
4615 " cannot be used as a destination");
4616 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4617 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4618 return rte_flow_error_set(error, ENOTSUP,
4619 RTE_FLOW_ERROR_TYPE_ACTION, action,
4620 "modifications of an arbitrary"
4621 " place in a packet is not supported");
4622 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4623 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4624 return rte_flow_error_set(error, ENOTSUP,
4625 RTE_FLOW_ERROR_TYPE_ACTION, action,
4626 "modifications of the 802.1Q Tag"
4627 " Identifier is not supported");
4628 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4629 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4630 return rte_flow_error_set(error, ENOTSUP,
4631 RTE_FLOW_ERROR_TYPE_ACTION, action,
4632 "modifications of the VXLAN Network"
4633 " Identifier is not supported");
4634 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4635 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4636 return rte_flow_error_set(error, ENOTSUP,
4637 RTE_FLOW_ERROR_TYPE_ACTION, action,
4638 "modifications of the GENEVE Network"
4639 " Identifier is not supported");
4640 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4641 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4642 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4643 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4644 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4645 !mlx5_flow_ext_mreg_supported(dev))
4646 return rte_flow_error_set(error, ENOTSUP,
4647 RTE_FLOW_ERROR_TYPE_ACTION, action,
4648 "cannot modify mark or metadata without"
4649 " extended metadata register support");
4651 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4652 return rte_flow_error_set(error, ENOTSUP,
4653 RTE_FLOW_ERROR_TYPE_ACTION, action,
4654 "add and sub operations"
4655 " are not supported");
4656 return (action_modify_field->width / 32) +
4657 !!(action_modify_field->width % 32);
4661 * Validate jump action.
4664 * Pointer to the jump action.
4665 * @param[in] action_flags
4666 * Holds the actions detected until now.
4667 * @param[in] attributes
4668 * Pointer to flow attributes
4669 * @param[in] external
4670 * Action belongs to flow rule created by request external to PMD.
4672 * Pointer to error structure.
4675 * 0 on success, a negative errno value otherwise and rte_errno is set.
4678 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4679 const struct mlx5_flow_tunnel *tunnel,
4680 const struct rte_flow_action *action,
4681 uint64_t action_flags,
4682 const struct rte_flow_attr *attributes,
4683 bool external, struct rte_flow_error *error)
4685 uint32_t target_group, table;
4687 struct flow_grp_info grp_info = {
4688 .external = !!external,
4689 .transfer = !!attributes->transfer,
4693 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4694 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4695 return rte_flow_error_set(error, EINVAL,
4696 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4697 "can't have 2 fate actions in"
4699 if (action_flags & MLX5_FLOW_ACTION_METER)
4700 return rte_flow_error_set(error, ENOTSUP,
4701 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4702 "jump with meter not support");
4704 return rte_flow_error_set(error, EINVAL,
4705 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4706 NULL, "action configuration not set");
4708 ((const struct rte_flow_action_jump *)action->conf)->group;
4709 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4713 if (attributes->group == target_group &&
4714 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4715 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4716 return rte_flow_error_set(error, EINVAL,
4717 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4718 "target group must be other than"
4719 " the current flow group");
4724 * Validate the port_id action.
4727 * Pointer to rte_eth_dev structure.
4728 * @param[in] action_flags
4729 * Bit-fields that holds the actions detected until now.
4731 * Port_id RTE action structure.
4733 * Attributes of flow that includes this action.
4735 * Pointer to error structure.
4738 * 0 on success, a negative errno value otherwise and rte_errno is set.
4741 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4742 uint64_t action_flags,
4743 const struct rte_flow_action *action,
4744 const struct rte_flow_attr *attr,
4745 struct rte_flow_error *error)
4747 const struct rte_flow_action_port_id *port_id;
4748 struct mlx5_priv *act_priv;
4749 struct mlx5_priv *dev_priv;
4752 if (!attr->transfer)
4753 return rte_flow_error_set(error, ENOTSUP,
4754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4756 "port id action is valid in transfer"
4758 if (!action || !action->conf)
4759 return rte_flow_error_set(error, ENOTSUP,
4760 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4762 "port id action parameters must be"
4764 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4765 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4766 return rte_flow_error_set(error, EINVAL,
4767 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4768 "can have only one fate actions in"
4770 dev_priv = mlx5_dev_to_eswitch_info(dev);
4772 return rte_flow_error_set(error, rte_errno,
4773 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4775 "failed to obtain E-Switch info");
4776 port_id = action->conf;
4777 port = port_id->original ? dev->data->port_id : port_id->id;
4778 act_priv = mlx5_port_to_eswitch_info(port, false);
4780 return rte_flow_error_set
4782 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4783 "failed to obtain E-Switch port id for port");
4784 if (act_priv->domain_id != dev_priv->domain_id)
4785 return rte_flow_error_set
4787 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4788 "port does not belong to"
4789 " E-Switch being configured");
4794 * Get the maximum number of modify header actions.
4797 * Pointer to rte_eth_dev structure.
4799 * Flags bits to check if root level.
4802 * Max number of modify header actions device can support.
4804 static inline unsigned int
4805 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4809 * There's no way to directly query the max capacity from FW.
4810 * The maximal value on root table should be assumed to be supported.
4812 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4813 return MLX5_MAX_MODIFY_NUM;
4815 return MLX5_ROOT_TBL_MODIFY_NUM;
4819 * Validate the meter action.
4822 * Pointer to rte_eth_dev structure.
4823 * @param[in] action_flags
4824 * Bit-fields that holds the actions detected until now.
4826 * Pointer to the meter action.
4828 * Attributes of flow that includes this action.
4830 * Pointer to error structure.
4833 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4836 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4837 uint64_t action_flags,
4838 const struct rte_flow_action *action,
4839 const struct rte_flow_attr *attr,
4840 struct rte_flow_error *error)
4842 struct mlx5_priv *priv = dev->data->dev_private;
4843 const struct rte_flow_action_meter *am = action->conf;
4844 struct mlx5_flow_meter_info *fm;
4847 return rte_flow_error_set(error, EINVAL,
4848 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4849 "meter action conf is NULL");
4851 if (action_flags & MLX5_FLOW_ACTION_METER)
4852 return rte_flow_error_set(error, ENOTSUP,
4853 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4854 "meter chaining not support");
4855 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4856 return rte_flow_error_set(error, ENOTSUP,
4857 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4858 "meter with jump not support");
4860 return rte_flow_error_set(error, ENOTSUP,
4861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4863 "meter action not supported");
4864 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4866 return rte_flow_error_set(error, EINVAL,
4867 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4869 /* aso meter can always be shared by different domains */
4870 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
4871 !(fm->transfer == attr->transfer ||
4872 (!fm->ingress && !attr->ingress && attr->egress) ||
4873 (!fm->egress && !attr->egress && attr->ingress)))
4874 return rte_flow_error_set(error, EINVAL,
4875 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4876 "Flow attributes are either invalid "
4877 "or have a conflict with current "
4878 "meter attributes");
4883 * Validate the age action.
4885 * @param[in] action_flags
4886 * Holds the actions detected until now.
4888 * Pointer to the age action.
4890 * Pointer to the Ethernet device structure.
4892 * Pointer to error structure.
4895 * 0 on success, a negative errno value otherwise and rte_errno is set.
4898 flow_dv_validate_action_age(uint64_t action_flags,
4899 const struct rte_flow_action *action,
4900 struct rte_eth_dev *dev,
4901 struct rte_flow_error *error)
4903 struct mlx5_priv *priv = dev->data->dev_private;
4904 const struct rte_flow_action_age *age = action->conf;
4906 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4907 !priv->sh->aso_age_mng))
4908 return rte_flow_error_set(error, ENOTSUP,
4909 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4911 "age action not supported");
4912 if (!(action->conf))
4913 return rte_flow_error_set(error, EINVAL,
4914 RTE_FLOW_ERROR_TYPE_ACTION, action,
4915 "configuration cannot be null");
4916 if (!(age->timeout))
4917 return rte_flow_error_set(error, EINVAL,
4918 RTE_FLOW_ERROR_TYPE_ACTION, action,
4919 "invalid timeout value 0");
4920 if (action_flags & MLX5_FLOW_ACTION_AGE)
4921 return rte_flow_error_set(error, EINVAL,
4922 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4923 "duplicate age actions set");
4928 * Validate the modify-header IPv4 DSCP actions.
4930 * @param[in] action_flags
4931 * Holds the actions detected until now.
4933 * Pointer to the modify action.
4934 * @param[in] item_flags
4935 * Holds the items detected.
4937 * Pointer to error structure.
4940 * 0 on success, a negative errno value otherwise and rte_errno is set.
4943 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4944 const struct rte_flow_action *action,
4945 const uint64_t item_flags,
4946 struct rte_flow_error *error)
4950 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4952 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4953 return rte_flow_error_set(error, EINVAL,
4954 RTE_FLOW_ERROR_TYPE_ACTION,
4956 "no ipv4 item in pattern");
4962 * Validate the modify-header IPv6 DSCP actions.
4964 * @param[in] action_flags
4965 * Holds the actions detected until now.
4967 * Pointer to the modify action.
4968 * @param[in] item_flags
4969 * Holds the items detected.
4971 * Pointer to error structure.
4974 * 0 on success, a negative errno value otherwise and rte_errno is set.
4977 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4978 const struct rte_flow_action *action,
4979 const uint64_t item_flags,
4980 struct rte_flow_error *error)
4984 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4986 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4987 return rte_flow_error_set(error, EINVAL,
4988 RTE_FLOW_ERROR_TYPE_ACTION,
4990 "no ipv6 item in pattern");
4996 * Match modify-header resource.
4999 * Pointer to the hash list.
5001 * Pointer to exist resource entry object.
5003 * Key of the new entry.
5005 * Pointer to new modify-header resource.
5008 * 0 on matching, non-zero otherwise.
5011 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5012 struct mlx5_hlist_entry *entry,
5013 uint64_t key __rte_unused, void *cb_ctx)
5015 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5016 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5017 struct mlx5_flow_dv_modify_hdr_resource *resource =
5018 container_of(entry, typeof(*resource), entry);
5019 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5021 key_len += ref->actions_num * sizeof(ref->actions[0]);
5022 return ref->actions_num != resource->actions_num ||
5023 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5026 struct mlx5_hlist_entry *
5027 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5030 struct mlx5_dev_ctx_shared *sh = list->ctx;
5031 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5032 struct mlx5dv_dr_domain *ns;
5033 struct mlx5_flow_dv_modify_hdr_resource *entry;
5034 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5036 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5037 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5039 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5042 rte_flow_error_set(ctx->error, ENOMEM,
5043 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5044 "cannot allocate resource memory");
5047 rte_memcpy(&entry->ft_type,
5048 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5049 key_len + data_len);
5050 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5051 ns = sh->fdb_domain;
5052 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5056 ret = mlx5_flow_os_create_flow_action_modify_header
5057 (sh->ctx, ns, entry,
5058 data_len, &entry->action);
5061 rte_flow_error_set(ctx->error, ENOMEM,
5062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5063 NULL, "cannot create modification action");
5066 return &entry->entry;
5070 * Validate the sample action.
5072 * @param[in, out] action_flags
5073 * Holds the actions detected until now.
5075 * Pointer to the sample action.
5077 * Pointer to the Ethernet device structure.
5079 * Attributes of flow that includes this action.
5080 * @param[in] item_flags
5081 * Holds the items detected.
5083 * Pointer to the RSS action.
5084 * @param[out] sample_rss
5085 * Pointer to the RSS action in sample action list.
5087 * Pointer to the COUNT action in sample action list.
5088 * @param[out] fdb_mirror_limit
5089 * Pointer to the FDB mirror limitation flag.
5091 * Pointer to error structure.
5094 * 0 on success, a negative errno value otherwise and rte_errno is set.
5097 flow_dv_validate_action_sample(uint64_t *action_flags,
5098 const struct rte_flow_action *action,
5099 struct rte_eth_dev *dev,
5100 const struct rte_flow_attr *attr,
5101 uint64_t item_flags,
5102 const struct rte_flow_action_rss *rss,
5103 const struct rte_flow_action_rss **sample_rss,
5104 const struct rte_flow_action_count **count,
5105 int *fdb_mirror_limit,
5106 struct rte_flow_error *error)
5108 struct mlx5_priv *priv = dev->data->dev_private;
5109 struct mlx5_dev_config *dev_conf = &priv->config;
5110 const struct rte_flow_action_sample *sample = action->conf;
5111 const struct rte_flow_action *act;
5112 uint64_t sub_action_flags = 0;
5113 uint16_t queue_index = 0xFFFF;
5118 return rte_flow_error_set(error, EINVAL,
5119 RTE_FLOW_ERROR_TYPE_ACTION, action,
5120 "configuration cannot be NULL");
5121 if (sample->ratio == 0)
5122 return rte_flow_error_set(error, EINVAL,
5123 RTE_FLOW_ERROR_TYPE_ACTION, action,
5124 "ratio value starts from 1");
5125 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5126 return rte_flow_error_set(error, ENOTSUP,
5127 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5129 "sample action not supported");
5130 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5131 return rte_flow_error_set(error, EINVAL,
5132 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5133 "Multiple sample actions not "
5135 if (*action_flags & MLX5_FLOW_ACTION_METER)
5136 return rte_flow_error_set(error, EINVAL,
5137 RTE_FLOW_ERROR_TYPE_ACTION, action,
5138 "wrong action order, meter should "
5139 "be after sample action");
5140 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5141 return rte_flow_error_set(error, EINVAL,
5142 RTE_FLOW_ERROR_TYPE_ACTION, action,
5143 "wrong action order, jump should "
5144 "be after sample action");
5145 act = sample->actions;
5146 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5147 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5148 return rte_flow_error_set(error, ENOTSUP,
5149 RTE_FLOW_ERROR_TYPE_ACTION,
5150 act, "too many actions");
5151 switch (act->type) {
5152 case RTE_FLOW_ACTION_TYPE_QUEUE:
5153 ret = mlx5_flow_validate_action_queue(act,
5159 queue_index = ((const struct rte_flow_action_queue *)
5160 (act->conf))->index;
5161 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5164 case RTE_FLOW_ACTION_TYPE_RSS:
5165 *sample_rss = act->conf;
5166 ret = mlx5_flow_validate_action_rss(act,
5173 if (rss && *sample_rss &&
5174 ((*sample_rss)->level != rss->level ||
5175 (*sample_rss)->types != rss->types))
5176 return rte_flow_error_set(error, ENOTSUP,
5177 RTE_FLOW_ERROR_TYPE_ACTION,
5179 "Can't use the different RSS types "
5180 "or level in the same flow");
5181 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5182 queue_index = (*sample_rss)->queue[0];
5183 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5186 case RTE_FLOW_ACTION_TYPE_MARK:
5187 ret = flow_dv_validate_action_mark(dev, act,
5192 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5193 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5194 MLX5_FLOW_ACTION_MARK_EXT;
5196 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5199 case RTE_FLOW_ACTION_TYPE_COUNT:
5200 ret = flow_dv_validate_action_count
5202 *action_flags | sub_action_flags,
5207 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5208 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5211 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5212 ret = flow_dv_validate_action_port_id(dev,
5219 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5222 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5223 ret = flow_dv_validate_action_raw_encap_decap
5224 (dev, NULL, act->conf, attr, &sub_action_flags,
5225 &actions_n, action, item_flags, error);
5230 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5231 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5232 ret = flow_dv_validate_action_l2_encap(dev,
5238 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5242 return rte_flow_error_set(error, ENOTSUP,
5243 RTE_FLOW_ERROR_TYPE_ACTION,
5245 "Doesn't support optional "
5249 if (attr->ingress && !attr->transfer) {
5250 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5251 MLX5_FLOW_ACTION_RSS)))
5252 return rte_flow_error_set(error, EINVAL,
5253 RTE_FLOW_ERROR_TYPE_ACTION,
5255 "Ingress must has a dest "
5256 "QUEUE for Sample");
5257 } else if (attr->egress && !attr->transfer) {
5258 return rte_flow_error_set(error, ENOTSUP,
5259 RTE_FLOW_ERROR_TYPE_ACTION,
5261 "Sample Only support Ingress "
5263 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5264 MLX5_ASSERT(attr->transfer);
5265 if (sample->ratio > 1)
5266 return rte_flow_error_set(error, ENOTSUP,
5267 RTE_FLOW_ERROR_TYPE_ACTION,
5269 "E-Switch doesn't support "
5270 "any optional action "
5272 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5273 return rte_flow_error_set(error, ENOTSUP,
5274 RTE_FLOW_ERROR_TYPE_ACTION,
5276 "unsupported action QUEUE");
5277 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5278 return rte_flow_error_set(error, ENOTSUP,
5279 RTE_FLOW_ERROR_TYPE_ACTION,
5281 "unsupported action QUEUE");
5282 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5283 return rte_flow_error_set(error, EINVAL,
5284 RTE_FLOW_ERROR_TYPE_ACTION,
5286 "E-Switch must has a dest "
5287 "port for mirroring");
5288 if (!priv->config.hca_attr.reg_c_preserve &&
5289 priv->representor_id != -1)
5290 *fdb_mirror_limit = 1;
5292 /* Continue validation for Xcap actions.*/
5293 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5294 (queue_index == 0xFFFF ||
5295 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5296 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5297 MLX5_FLOW_XCAP_ACTIONS)
5298 return rte_flow_error_set(error, ENOTSUP,
5299 RTE_FLOW_ERROR_TYPE_ACTION,
5300 NULL, "encap and decap "
5301 "combination aren't "
5303 if (!attr->transfer && attr->ingress && (sub_action_flags &
5304 MLX5_FLOW_ACTION_ENCAP))
5305 return rte_flow_error_set(error, ENOTSUP,
5306 RTE_FLOW_ERROR_TYPE_ACTION,
5307 NULL, "encap is not supported"
5308 " for ingress traffic");
5314 * Find existing modify-header resource or create and register a new one.
5316 * @param dev[in, out]
5317 * Pointer to rte_eth_dev structure.
5318 * @param[in, out] resource
5319 * Pointer to modify-header resource.
5320 * @parm[in, out] dev_flow
5321 * Pointer to the dev_flow.
5323 * pointer to error structure.
5326 * 0 on success otherwise -errno and errno is set.
5329 flow_dv_modify_hdr_resource_register
5330 (struct rte_eth_dev *dev,
5331 struct mlx5_flow_dv_modify_hdr_resource *resource,
5332 struct mlx5_flow *dev_flow,
5333 struct rte_flow_error *error)
5335 struct mlx5_priv *priv = dev->data->dev_private;
5336 struct mlx5_dev_ctx_shared *sh = priv->sh;
5337 uint32_t key_len = sizeof(*resource) -
5338 offsetof(typeof(*resource), ft_type) +
5339 resource->actions_num * sizeof(resource->actions[0]);
5340 struct mlx5_hlist_entry *entry;
5341 struct mlx5_flow_cb_ctx ctx = {
5347 resource->flags = dev_flow->dv.group ? 0 :
5348 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5349 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5351 return rte_flow_error_set(error, EOVERFLOW,
5352 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5353 "too many modify header items");
5354 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5355 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5358 resource = container_of(entry, typeof(*resource), entry);
5359 dev_flow->handle->dvh.modify_hdr = resource;
5364 * Get DV flow counter by index.
5367 * Pointer to the Ethernet device structure.
5369 * mlx5 flow counter index in the container.
5371 * mlx5 flow counter pool in the container,
5374 * Pointer to the counter, NULL otherwise.
5376 static struct mlx5_flow_counter *
5377 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5379 struct mlx5_flow_counter_pool **ppool)
5381 struct mlx5_priv *priv = dev->data->dev_private;
5382 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5383 struct mlx5_flow_counter_pool *pool;
5385 /* Decrease to original index and clear shared bit. */
5386 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5387 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5388 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5392 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5396 * Check the devx counter belongs to the pool.
5399 * Pointer to the counter pool.
5401 * The counter devx ID.
5404 * True if counter belongs to the pool, false otherwise.
5407 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5409 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5410 MLX5_COUNTERS_PER_POOL;
5412 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5418 * Get a pool by devx counter ID.
5421 * Pointer to the counter management.
5423 * The counter devx ID.
5426 * The counter pool pointer if exists, NULL otherwise,
5428 static struct mlx5_flow_counter_pool *
5429 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5432 struct mlx5_flow_counter_pool *pool = NULL;
5434 rte_spinlock_lock(&cmng->pool_update_sl);
5435 /* Check last used pool. */
5436 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5437 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5438 pool = cmng->pools[cmng->last_pool_idx];
5441 /* ID out of range means no suitable pool in the container. */
5442 if (id > cmng->max_id || id < cmng->min_id)
5445 * Find the pool from the end of the container, since mostly counter
5446 * ID is sequence increasing, and the last pool should be the needed
5451 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5453 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5459 rte_spinlock_unlock(&cmng->pool_update_sl);
5464 * Resize a counter container.
5467 * Pointer to the Ethernet device structure.
5470 * 0 on success, otherwise negative errno value and rte_errno is set.
5473 flow_dv_container_resize(struct rte_eth_dev *dev)
5475 struct mlx5_priv *priv = dev->data->dev_private;
5476 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5477 void *old_pools = cmng->pools;
5478 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5479 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5480 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5487 memcpy(pools, old_pools, cmng->n *
5488 sizeof(struct mlx5_flow_counter_pool *));
5490 cmng->pools = pools;
5492 mlx5_free(old_pools);
5497 * Query a devx flow counter.
5500 * Pointer to the Ethernet device structure.
5502 * Index to the flow counter.
5504 * The statistics value of packets.
5506 * The statistics value of bytes.
5509 * 0 on success, otherwise a negative errno value and rte_errno is set.
5512 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5515 struct mlx5_priv *priv = dev->data->dev_private;
5516 struct mlx5_flow_counter_pool *pool = NULL;
5517 struct mlx5_flow_counter *cnt;
5520 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5522 if (priv->sh->cmng.counter_fallback)
5523 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5524 0, pkts, bytes, 0, NULL, NULL, 0);
5525 rte_spinlock_lock(&pool->sl);
5530 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5531 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5532 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5534 rte_spinlock_unlock(&pool->sl);
5539 * Create and initialize a new counter pool.
5542 * Pointer to the Ethernet device structure.
5544 * The devX counter handle.
5546 * Whether the pool is for counter that was allocated for aging.
5547 * @param[in/out] cont_cur
5548 * Pointer to the container pointer, it will be update in pool resize.
5551 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5553 static struct mlx5_flow_counter_pool *
5554 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5557 struct mlx5_priv *priv = dev->data->dev_private;
5558 struct mlx5_flow_counter_pool *pool;
5559 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5560 bool fallback = priv->sh->cmng.counter_fallback;
5561 uint32_t size = sizeof(*pool);
5563 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5564 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5565 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5571 pool->is_aged = !!age;
5572 pool->query_gen = 0;
5573 pool->min_dcs = dcs;
5574 rte_spinlock_init(&pool->sl);
5575 rte_spinlock_init(&pool->csl);
5576 TAILQ_INIT(&pool->counters[0]);
5577 TAILQ_INIT(&pool->counters[1]);
5578 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5579 rte_spinlock_lock(&cmng->pool_update_sl);
5580 pool->index = cmng->n_valid;
5581 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5583 rte_spinlock_unlock(&cmng->pool_update_sl);
5586 cmng->pools[pool->index] = pool;
5588 if (unlikely(fallback)) {
5589 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5591 if (base < cmng->min_id)
5592 cmng->min_id = base;
5593 if (base > cmng->max_id)
5594 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5595 cmng->last_pool_idx = pool->index;
5597 rte_spinlock_unlock(&cmng->pool_update_sl);
5602 * Prepare a new counter and/or a new counter pool.
5605 * Pointer to the Ethernet device structure.
5606 * @param[out] cnt_free
5607 * Where to put the pointer of a new counter.
5609 * Whether the pool is for counter that was allocated for aging.
5612 * The counter pool pointer and @p cnt_free is set on success,
5613 * NULL otherwise and rte_errno is set.
5615 static struct mlx5_flow_counter_pool *
5616 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5617 struct mlx5_flow_counter **cnt_free,
5620 struct mlx5_priv *priv = dev->data->dev_private;
5621 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5622 struct mlx5_flow_counter_pool *pool;
5623 struct mlx5_counters tmp_tq;
5624 struct mlx5_devx_obj *dcs = NULL;
5625 struct mlx5_flow_counter *cnt;
5626 enum mlx5_counter_type cnt_type =
5627 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5628 bool fallback = priv->sh->cmng.counter_fallback;
5632 /* bulk_bitmap must be 0 for single counter allocation. */
5633 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5636 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5638 pool = flow_dv_pool_create(dev, dcs, age);
5640 mlx5_devx_cmd_destroy(dcs);
5644 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5645 cnt = MLX5_POOL_GET_CNT(pool, i);
5647 cnt->dcs_when_free = dcs;
5651 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5653 rte_errno = ENODATA;
5656 pool = flow_dv_pool_create(dev, dcs, age);
5658 mlx5_devx_cmd_destroy(dcs);
5661 TAILQ_INIT(&tmp_tq);
5662 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5663 cnt = MLX5_POOL_GET_CNT(pool, i);
5665 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5667 rte_spinlock_lock(&cmng->csl[cnt_type]);
5668 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5669 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5670 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5671 (*cnt_free)->pool = pool;
5676 * Allocate a flow counter.
5679 * Pointer to the Ethernet device structure.
5681 * Whether the counter was allocated for aging.
5684 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5687 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5689 struct mlx5_priv *priv = dev->data->dev_private;
5690 struct mlx5_flow_counter_pool *pool = NULL;
5691 struct mlx5_flow_counter *cnt_free = NULL;
5692 bool fallback = priv->sh->cmng.counter_fallback;
5693 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5694 enum mlx5_counter_type cnt_type =
5695 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5698 if (!priv->config.devx) {
5699 rte_errno = ENOTSUP;
5702 /* Get free counters from container. */
5703 rte_spinlock_lock(&cmng->csl[cnt_type]);
5704 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5706 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5707 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5708 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5710 pool = cnt_free->pool;
5712 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5713 /* Create a DV counter action only in the first time usage. */
5714 if (!cnt_free->action) {
5716 struct mlx5_devx_obj *dcs;
5720 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5721 dcs = pool->min_dcs;
5724 dcs = cnt_free->dcs_when_free;
5726 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5733 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5734 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5735 /* Update the counter reset values. */
5736 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5739 if (!fallback && !priv->sh->cmng.query_thread_on)
5740 /* Start the asynchronous batch query by the host thread. */
5741 mlx5_set_query_alarm(priv->sh);
5745 cnt_free->pool = pool;
5747 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5748 rte_spinlock_lock(&cmng->csl[cnt_type]);
5749 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5750 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5756 * Allocate a shared flow counter.
5759 * Pointer to the shared counter configuration.
5761 * Pointer to save the allocated counter index.
5764 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5768 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5770 struct mlx5_shared_counter_conf *conf = ctx;
5771 struct rte_eth_dev *dev = conf->dev;
5772 struct mlx5_flow_counter *cnt;
5774 data->dword = flow_dv_counter_alloc(dev, 0);
5775 data->dword |= MLX5_CNT_SHARED_OFFSET;
5776 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5777 cnt->shared_info.id = conf->id;
5782 * Get a shared flow counter.
5785 * Pointer to the Ethernet device structure.
5787 * Counter identifier.
5790 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5793 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5795 struct mlx5_priv *priv = dev->data->dev_private;
5796 struct mlx5_shared_counter_conf conf = {
5800 union mlx5_l3t_data data = {
5804 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5805 flow_dv_counter_alloc_shared_cb, &conf);
5810 * Get age param from counter index.
5813 * Pointer to the Ethernet device structure.
5814 * @param[in] counter
5815 * Index to the counter handler.
5818 * The aging parameter specified for the counter index.
5820 static struct mlx5_age_param*
5821 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5824 struct mlx5_flow_counter *cnt;
5825 struct mlx5_flow_counter_pool *pool = NULL;
5827 flow_dv_counter_get_by_idx(dev, counter, &pool);
5828 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5829 cnt = MLX5_POOL_GET_CNT(pool, counter);
5830 return MLX5_CNT_TO_AGE(cnt);
5834 * Remove a flow counter from aged counter list.
5837 * Pointer to the Ethernet device structure.
5838 * @param[in] counter
5839 * Index to the counter handler.
5841 * Pointer to the counter handler.
5844 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5845 uint32_t counter, struct mlx5_flow_counter *cnt)
5847 struct mlx5_age_info *age_info;
5848 struct mlx5_age_param *age_param;
5849 struct mlx5_priv *priv = dev->data->dev_private;
5850 uint16_t expected = AGE_CANDIDATE;
5852 age_info = GET_PORT_AGE_INFO(priv);
5853 age_param = flow_dv_counter_idx_get_age(dev, counter);
5854 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5855 AGE_FREE, false, __ATOMIC_RELAXED,
5856 __ATOMIC_RELAXED)) {
5858 * We need the lock even it is age timeout,
5859 * since counter may still in process.
5861 rte_spinlock_lock(&age_info->aged_sl);
5862 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5863 rte_spinlock_unlock(&age_info->aged_sl);
5864 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5869 * Release a flow counter.
5872 * Pointer to the Ethernet device structure.
5873 * @param[in] counter
5874 * Index to the counter handler.
5877 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5879 struct mlx5_priv *priv = dev->data->dev_private;
5880 struct mlx5_flow_counter_pool *pool = NULL;
5881 struct mlx5_flow_counter *cnt;
5882 enum mlx5_counter_type cnt_type;
5886 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5888 if (IS_SHARED_CNT(counter) &&
5889 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5892 flow_dv_counter_remove_from_age(dev, counter, cnt);
5895 * Put the counter back to list to be updated in none fallback mode.
5896 * Currently, we are using two list alternately, while one is in query,
5897 * add the freed counter to the other list based on the pool query_gen
5898 * value. After query finishes, add counter the list to the global
5899 * container counter list. The list changes while query starts. In
5900 * this case, lock will not be needed as query callback and release
5901 * function both operate with the different list.
5904 if (!priv->sh->cmng.counter_fallback) {
5905 rte_spinlock_lock(&pool->csl);
5906 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5907 rte_spinlock_unlock(&pool->csl);
5909 cnt->dcs_when_free = cnt->dcs_when_active;
5910 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5911 MLX5_COUNTER_TYPE_ORIGIN;
5912 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5913 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5915 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5920 * Resize a meter id container.
5923 * Pointer to the Ethernet device structure.
5926 * 0 on success, otherwise negative errno value and rte_errno is set.
5929 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
5931 struct mlx5_priv *priv = dev->data->dev_private;
5932 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5933 void *old_pools = mtrmng->pools;
5934 uint32_t resize = mtrmng->n + MLX5_MTRS_CONTAINER_RESIZE;
5935 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
5936 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5943 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
5948 memcpy(pools, old_pools, mtrmng->n *
5949 sizeof(struct mlx5_aso_mtr_pool *));
5951 mtrmng->pools = pools;
5953 mlx5_free(old_pools);
5958 * Prepare a new meter and/or a new meter pool.
5961 * Pointer to the Ethernet device structure.
5962 * @param[out] mtr_free
5963 * Where to put the pointer of a new meter.g.
5966 * The meter pool pointer and @mtr_free is set on success,
5967 * NULL otherwise and rte_errno is set.
5969 static struct mlx5_aso_mtr_pool *
5970 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
5971 struct mlx5_aso_mtr **mtr_free)
5973 struct mlx5_priv *priv = dev->data->dev_private;
5974 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5975 struct mlx5_aso_mtr_pool *pool = NULL;
5976 struct mlx5_devx_obj *dcs = NULL;
5978 uint32_t log_obj_size;
5980 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
5981 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
5982 priv->sh->pdn, log_obj_size);
5984 rte_errno = ENODATA;
5987 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
5990 claim_zero(mlx5_devx_cmd_destroy(dcs));
5993 pool->devx_obj = dcs;
5994 pool->index = mtrmng->n_valid;
5995 if (pool->index == mtrmng->n && flow_dv_mtr_container_resize(dev)) {
5997 claim_zero(mlx5_devx_cmd_destroy(dcs));
6000 mtrmng->pools[pool->index] = pool;
6002 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6003 pool->mtrs[i].offset = i;
6004 LIST_INSERT_HEAD(&mtrmng->meters,
6005 &pool->mtrs[i], next);
6007 pool->mtrs[0].offset = 0;
6008 *mtr_free = &pool->mtrs[0];
6013 * Release a flow meter into pool.
6016 * Pointer to the Ethernet device structure.
6017 * @param[in] mtr_idx
6018 * Index to aso flow meter.
6021 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6023 struct mlx5_priv *priv = dev->data->dev_private;
6024 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6025 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6027 MLX5_ASSERT(aso_mtr);
6028 rte_spinlock_lock(&mtrmng->mtrsl);
6029 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6030 aso_mtr->state = ASO_METER_FREE;
6031 LIST_INSERT_HEAD(&mtrmng->meters, aso_mtr, next);
6032 rte_spinlock_unlock(&mtrmng->mtrsl);
6036 * Allocate a aso flow meter.
6039 * Pointer to the Ethernet device structure.
6042 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6045 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6047 struct mlx5_priv *priv = dev->data->dev_private;
6048 struct mlx5_aso_mtr *mtr_free = NULL;
6049 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6050 struct mlx5_aso_mtr_pool *pool;
6051 uint32_t mtr_idx = 0;
6053 if (!priv->config.devx) {
6054 rte_errno = ENOTSUP;
6057 /* Allocate the flow meter memory. */
6058 /* Get free meters from management. */
6059 rte_spinlock_lock(&mtrmng->mtrsl);
6060 mtr_free = LIST_FIRST(&mtrmng->meters);
6062 LIST_REMOVE(mtr_free, next);
6063 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6064 rte_spinlock_unlock(&mtrmng->mtrsl);
6067 mtr_free->state = ASO_METER_WAIT;
6068 rte_spinlock_unlock(&mtrmng->mtrsl);
6069 pool = container_of(mtr_free,
6070 struct mlx5_aso_mtr_pool,
6071 mtrs[mtr_free->offset]);
6072 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6073 if (!mtr_free->fm.meter_action) {
6074 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6075 struct rte_flow_error error;
6078 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6079 mtr_free->fm.meter_action =
6080 mlx5_glue->dv_create_flow_action_aso
6081 (priv->sh->rx_domain,
6082 pool->devx_obj->obj,
6084 (1 << MLX5_FLOW_COLOR_GREEN),
6086 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6087 if (!mtr_free->fm.meter_action) {
6088 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6096 * Verify the @p attributes will be correctly understood by the NIC and store
6097 * them in the @p flow if everything is correct.
6100 * Pointer to dev struct.
6101 * @param[in] attributes
6102 * Pointer to flow attributes
6103 * @param[in] external
6104 * This flow rule is created by request external to PMD.
6106 * Pointer to error structure.
6109 * - 0 on success and non root table.
6110 * - 1 on success and root table.
6111 * - a negative errno value otherwise and rte_errno is set.
6114 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6115 const struct mlx5_flow_tunnel *tunnel,
6116 const struct rte_flow_attr *attributes,
6117 const struct flow_grp_info *grp_info,
6118 struct rte_flow_error *error)
6120 struct mlx5_priv *priv = dev->data->dev_private;
6121 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6124 #ifndef HAVE_MLX5DV_DR
6125 RTE_SET_USED(tunnel);
6126 RTE_SET_USED(grp_info);
6127 if (attributes->group)
6128 return rte_flow_error_set(error, ENOTSUP,
6129 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6131 "groups are not supported");
6135 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6140 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6142 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6143 attributes->priority > lowest_priority)
6144 return rte_flow_error_set(error, ENOTSUP,
6145 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6147 "priority out of range");
6148 if (attributes->transfer) {
6149 if (!priv->config.dv_esw_en)
6150 return rte_flow_error_set
6152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6153 "E-Switch dr is not supported");
6154 if (!(priv->representor || priv->master))
6155 return rte_flow_error_set
6156 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6157 NULL, "E-Switch configuration can only be"
6158 " done by a master or a representor device");
6159 if (attributes->egress)
6160 return rte_flow_error_set
6162 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6163 "egress is not supported");
6165 if (!(attributes->egress ^ attributes->ingress))
6166 return rte_flow_error_set(error, ENOTSUP,
6167 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6168 "must specify exactly one of "
6169 "ingress or egress");
6174 * Internal validation function. For validating both actions and items.
6177 * Pointer to the rte_eth_dev structure.
6179 * Pointer to the flow attributes.
6181 * Pointer to the list of items.
6182 * @param[in] actions
6183 * Pointer to the list of actions.
6184 * @param[in] external
6185 * This flow rule is created by request external to PMD.
6186 * @param[in] hairpin
6187 * Number of hairpin TX actions, 0 means classic flow.
6189 * Pointer to the error structure.
6192 * 0 on success, a negative errno value otherwise and rte_errno is set.
6195 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6196 const struct rte_flow_item items[],
6197 const struct rte_flow_action actions[],
6198 bool external, int hairpin, struct rte_flow_error *error)
6201 uint64_t action_flags = 0;
6202 uint64_t item_flags = 0;
6203 uint64_t last_item = 0;
6204 uint8_t next_protocol = 0xff;
6205 uint16_t ether_type = 0;
6207 uint8_t item_ipv6_proto = 0;
6208 int fdb_mirror_limit = 0;
6209 int modify_after_mirror = 0;
6210 const struct rte_flow_item *geneve_item = NULL;
6211 const struct rte_flow_item *gre_item = NULL;
6212 const struct rte_flow_item *gtp_item = NULL;
6213 const struct rte_flow_action_raw_decap *decap;
6214 const struct rte_flow_action_raw_encap *encap;
6215 const struct rte_flow_action_rss *rss = NULL;
6216 const struct rte_flow_action_rss *sample_rss = NULL;
6217 const struct rte_flow_action_count *count = NULL;
6218 const struct rte_flow_action_count *sample_count = NULL;
6219 const struct rte_flow_item_tcp nic_tcp_mask = {
6222 .src_port = RTE_BE16(UINT16_MAX),
6223 .dst_port = RTE_BE16(UINT16_MAX),
6226 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6229 "\xff\xff\xff\xff\xff\xff\xff\xff"
6230 "\xff\xff\xff\xff\xff\xff\xff\xff",
6232 "\xff\xff\xff\xff\xff\xff\xff\xff"
6233 "\xff\xff\xff\xff\xff\xff\xff\xff",
6234 .vtc_flow = RTE_BE32(0xffffffff),
6240 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6244 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6248 .dummy[0] = 0xffffffff,
6251 struct mlx5_priv *priv = dev->data->dev_private;
6252 struct mlx5_dev_config *dev_conf = &priv->config;
6253 uint16_t queue_index = 0xFFFF;
6254 const struct rte_flow_item_vlan *vlan_m = NULL;
6255 uint32_t rw_act_num = 0;
6257 const struct mlx5_flow_tunnel *tunnel;
6258 struct flow_grp_info grp_info = {
6259 .external = !!external,
6260 .transfer = !!attr->transfer,
6261 .fdb_def_rule = !!priv->fdb_def_rule,
6263 const struct rte_eth_hairpin_conf *conf;
6267 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6268 tunnel = flow_items_to_tunnel(items);
6269 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6270 MLX5_FLOW_ACTION_DECAP;
6271 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6272 tunnel = flow_actions_to_tunnel(actions);
6273 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6277 if (tunnel && priv->representor)
6278 return rte_flow_error_set(error, ENOTSUP,
6279 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6280 "decap not supported "
6281 "for VF representor");
6282 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6283 (dev, tunnel, attr, items, actions);
6284 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6287 is_root = (uint64_t)ret;
6288 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6289 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6290 int type = items->type;
6292 if (!mlx5_flow_os_item_supported(type))
6293 return rte_flow_error_set(error, ENOTSUP,
6294 RTE_FLOW_ERROR_TYPE_ITEM,
6295 NULL, "item not supported");
6297 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6298 if (items[0].type != (typeof(items[0].type))
6299 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6300 return rte_flow_error_set
6302 RTE_FLOW_ERROR_TYPE_ITEM,
6303 NULL, "MLX5 private items "
6304 "must be the first");
6306 case RTE_FLOW_ITEM_TYPE_VOID:
6308 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6309 ret = flow_dv_validate_item_port_id
6310 (dev, items, attr, item_flags, error);
6313 last_item = MLX5_FLOW_ITEM_PORT_ID;
6315 case RTE_FLOW_ITEM_TYPE_ETH:
6316 ret = mlx5_flow_validate_item_eth(items, item_flags,
6320 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6321 MLX5_FLOW_LAYER_OUTER_L2;
6322 if (items->mask != NULL && items->spec != NULL) {
6324 ((const struct rte_flow_item_eth *)
6327 ((const struct rte_flow_item_eth *)
6329 ether_type = rte_be_to_cpu_16(ether_type);
6334 case RTE_FLOW_ITEM_TYPE_VLAN:
6335 ret = flow_dv_validate_item_vlan(items, item_flags,
6339 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6340 MLX5_FLOW_LAYER_OUTER_VLAN;
6341 if (items->mask != NULL && items->spec != NULL) {
6343 ((const struct rte_flow_item_vlan *)
6344 items->spec)->inner_type;
6346 ((const struct rte_flow_item_vlan *)
6347 items->mask)->inner_type;
6348 ether_type = rte_be_to_cpu_16(ether_type);
6352 /* Store outer VLAN mask for of_push_vlan action. */
6354 vlan_m = items->mask;
6356 case RTE_FLOW_ITEM_TYPE_IPV4:
6357 mlx5_flow_tunnel_ip_check(items, next_protocol,
6358 &item_flags, &tunnel);
6359 ret = flow_dv_validate_item_ipv4(items, item_flags,
6360 last_item, ether_type,
6364 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6365 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6366 if (items->mask != NULL &&
6367 ((const struct rte_flow_item_ipv4 *)
6368 items->mask)->hdr.next_proto_id) {
6370 ((const struct rte_flow_item_ipv4 *)
6371 (items->spec))->hdr.next_proto_id;
6373 ((const struct rte_flow_item_ipv4 *)
6374 (items->mask))->hdr.next_proto_id;
6376 /* Reset for inner layer. */
6377 next_protocol = 0xff;
6380 case RTE_FLOW_ITEM_TYPE_IPV6:
6381 mlx5_flow_tunnel_ip_check(items, next_protocol,
6382 &item_flags, &tunnel);
6383 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6390 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6391 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6392 if (items->mask != NULL &&
6393 ((const struct rte_flow_item_ipv6 *)
6394 items->mask)->hdr.proto) {
6396 ((const struct rte_flow_item_ipv6 *)
6397 items->spec)->hdr.proto;
6399 ((const struct rte_flow_item_ipv6 *)
6400 items->spec)->hdr.proto;
6402 ((const struct rte_flow_item_ipv6 *)
6403 items->mask)->hdr.proto;
6405 /* Reset for inner layer. */
6406 next_protocol = 0xff;
6409 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6410 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6415 last_item = tunnel ?
6416 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6417 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6418 if (items->mask != NULL &&
6419 ((const struct rte_flow_item_ipv6_frag_ext *)
6420 items->mask)->hdr.next_header) {
6422 ((const struct rte_flow_item_ipv6_frag_ext *)
6423 items->spec)->hdr.next_header;
6425 ((const struct rte_flow_item_ipv6_frag_ext *)
6426 items->mask)->hdr.next_header;
6428 /* Reset for inner layer. */
6429 next_protocol = 0xff;
6432 case RTE_FLOW_ITEM_TYPE_TCP:
6433 ret = mlx5_flow_validate_item_tcp
6440 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6441 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6443 case RTE_FLOW_ITEM_TYPE_UDP:
6444 ret = mlx5_flow_validate_item_udp(items, item_flags,
6449 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6450 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6452 case RTE_FLOW_ITEM_TYPE_GRE:
6453 ret = mlx5_flow_validate_item_gre(items, item_flags,
6454 next_protocol, error);
6458 last_item = MLX5_FLOW_LAYER_GRE;
6460 case RTE_FLOW_ITEM_TYPE_NVGRE:
6461 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6466 last_item = MLX5_FLOW_LAYER_NVGRE;
6468 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6469 ret = mlx5_flow_validate_item_gre_key
6470 (items, item_flags, gre_item, error);
6473 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6475 case RTE_FLOW_ITEM_TYPE_VXLAN:
6476 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6480 last_item = MLX5_FLOW_LAYER_VXLAN;
6482 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6483 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6488 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6490 case RTE_FLOW_ITEM_TYPE_GENEVE:
6491 ret = mlx5_flow_validate_item_geneve(items,
6496 geneve_item = items;
6497 last_item = MLX5_FLOW_LAYER_GENEVE;
6499 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6500 ret = mlx5_flow_validate_item_geneve_opt(items,
6507 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6509 case RTE_FLOW_ITEM_TYPE_MPLS:
6510 ret = mlx5_flow_validate_item_mpls(dev, items,
6515 last_item = MLX5_FLOW_LAYER_MPLS;
6518 case RTE_FLOW_ITEM_TYPE_MARK:
6519 ret = flow_dv_validate_item_mark(dev, items, attr,
6523 last_item = MLX5_FLOW_ITEM_MARK;
6525 case RTE_FLOW_ITEM_TYPE_META:
6526 ret = flow_dv_validate_item_meta(dev, items, attr,
6530 last_item = MLX5_FLOW_ITEM_METADATA;
6532 case RTE_FLOW_ITEM_TYPE_ICMP:
6533 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6538 last_item = MLX5_FLOW_LAYER_ICMP;
6540 case RTE_FLOW_ITEM_TYPE_ICMP6:
6541 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6546 item_ipv6_proto = IPPROTO_ICMPV6;
6547 last_item = MLX5_FLOW_LAYER_ICMP6;
6549 case RTE_FLOW_ITEM_TYPE_TAG:
6550 ret = flow_dv_validate_item_tag(dev, items,
6554 last_item = MLX5_FLOW_ITEM_TAG;
6556 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6557 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6559 case RTE_FLOW_ITEM_TYPE_GTP:
6560 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6565 last_item = MLX5_FLOW_LAYER_GTP;
6567 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6568 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6573 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6575 case RTE_FLOW_ITEM_TYPE_ECPRI:
6576 /* Capacity will be checked in the translate stage. */
6577 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6584 last_item = MLX5_FLOW_LAYER_ECPRI;
6587 return rte_flow_error_set(error, ENOTSUP,
6588 RTE_FLOW_ERROR_TYPE_ITEM,
6589 NULL, "item not supported");
6591 item_flags |= last_item;
6593 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6594 int type = actions->type;
6596 if (!mlx5_flow_os_action_supported(type))
6597 return rte_flow_error_set(error, ENOTSUP,
6598 RTE_FLOW_ERROR_TYPE_ACTION,
6600 "action not supported");
6601 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6602 return rte_flow_error_set(error, ENOTSUP,
6603 RTE_FLOW_ERROR_TYPE_ACTION,
6604 actions, "too many actions");
6606 case RTE_FLOW_ACTION_TYPE_VOID:
6608 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6609 ret = flow_dv_validate_action_port_id(dev,
6616 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6619 case RTE_FLOW_ACTION_TYPE_FLAG:
6620 ret = flow_dv_validate_action_flag(dev, action_flags,
6624 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6625 /* Count all modify-header actions as one. */
6626 if (!(action_flags &
6627 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6629 action_flags |= MLX5_FLOW_ACTION_FLAG |
6630 MLX5_FLOW_ACTION_MARK_EXT;
6631 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6632 modify_after_mirror = 1;
6635 action_flags |= MLX5_FLOW_ACTION_FLAG;
6638 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6640 case RTE_FLOW_ACTION_TYPE_MARK:
6641 ret = flow_dv_validate_action_mark(dev, actions,
6646 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6647 /* Count all modify-header actions as one. */
6648 if (!(action_flags &
6649 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6651 action_flags |= MLX5_FLOW_ACTION_MARK |
6652 MLX5_FLOW_ACTION_MARK_EXT;
6653 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6654 modify_after_mirror = 1;
6656 action_flags |= MLX5_FLOW_ACTION_MARK;
6659 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6661 case RTE_FLOW_ACTION_TYPE_SET_META:
6662 ret = flow_dv_validate_action_set_meta(dev, actions,
6667 /* Count all modify-header actions as one action. */
6668 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6670 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6671 modify_after_mirror = 1;
6672 action_flags |= MLX5_FLOW_ACTION_SET_META;
6673 rw_act_num += MLX5_ACT_NUM_SET_META;
6675 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6676 ret = flow_dv_validate_action_set_tag(dev, actions,
6681 /* Count all modify-header actions as one action. */
6682 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6684 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6685 modify_after_mirror = 1;
6686 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6687 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6689 case RTE_FLOW_ACTION_TYPE_DROP:
6690 ret = mlx5_flow_validate_action_drop(action_flags,
6694 action_flags |= MLX5_FLOW_ACTION_DROP;
6697 case RTE_FLOW_ACTION_TYPE_QUEUE:
6698 ret = mlx5_flow_validate_action_queue(actions,
6703 queue_index = ((const struct rte_flow_action_queue *)
6704 (actions->conf))->index;
6705 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6708 case RTE_FLOW_ACTION_TYPE_RSS:
6709 rss = actions->conf;
6710 ret = mlx5_flow_validate_action_rss(actions,
6716 if (rss && sample_rss &&
6717 (sample_rss->level != rss->level ||
6718 sample_rss->types != rss->types))
6719 return rte_flow_error_set(error, ENOTSUP,
6720 RTE_FLOW_ERROR_TYPE_ACTION,
6722 "Can't use the different RSS types "
6723 "or level in the same flow");
6724 if (rss != NULL && rss->queue_num)
6725 queue_index = rss->queue[0];
6726 action_flags |= MLX5_FLOW_ACTION_RSS;
6729 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6731 mlx5_flow_validate_action_default_miss(action_flags,
6735 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6738 case RTE_FLOW_ACTION_TYPE_COUNT:
6739 ret = flow_dv_validate_action_count(dev, actions,
6744 count = actions->conf;
6745 action_flags |= MLX5_FLOW_ACTION_COUNT;
6748 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6749 if (flow_dv_validate_action_pop_vlan(dev,
6755 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6756 modify_after_mirror = 1;
6757 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6760 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6761 ret = flow_dv_validate_action_push_vlan(dev,
6768 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6769 modify_after_mirror = 1;
6770 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6773 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6774 ret = flow_dv_validate_action_set_vlan_pcp
6775 (action_flags, actions, error);
6778 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6779 modify_after_mirror = 1;
6780 /* Count PCP with push_vlan command. */
6781 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6783 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6784 ret = flow_dv_validate_action_set_vlan_vid
6785 (item_flags, action_flags,
6789 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6790 modify_after_mirror = 1;
6791 /* Count VID with push_vlan command. */
6792 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6793 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6795 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6796 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6797 ret = flow_dv_validate_action_l2_encap(dev,
6803 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6806 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6807 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6808 ret = flow_dv_validate_action_decap(dev, action_flags,
6809 actions, item_flags,
6813 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6814 modify_after_mirror = 1;
6815 action_flags |= MLX5_FLOW_ACTION_DECAP;
6818 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6819 ret = flow_dv_validate_action_raw_encap_decap
6820 (dev, NULL, actions->conf, attr, &action_flags,
6821 &actions_n, actions, item_flags, error);
6825 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6826 decap = actions->conf;
6827 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6829 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6833 encap = actions->conf;
6835 ret = flow_dv_validate_action_raw_encap_decap
6837 decap ? decap : &empty_decap, encap,
6838 attr, &action_flags, &actions_n,
6839 actions, item_flags, error);
6842 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6843 (action_flags & MLX5_FLOW_ACTION_DECAP))
6844 modify_after_mirror = 1;
6846 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6847 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6848 ret = flow_dv_validate_action_modify_mac(action_flags,
6854 /* Count all modify-header actions as one action. */
6855 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6857 action_flags |= actions->type ==
6858 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6859 MLX5_FLOW_ACTION_SET_MAC_SRC :
6860 MLX5_FLOW_ACTION_SET_MAC_DST;
6861 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6862 modify_after_mirror = 1;
6864 * Even if the source and destination MAC addresses have
6865 * overlap in the header with 4B alignment, the convert
6866 * function will handle them separately and 4 SW actions
6867 * will be created. And 2 actions will be added each
6868 * time no matter how many bytes of address will be set.
6870 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6872 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6873 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6874 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6880 /* Count all modify-header actions as one action. */
6881 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6883 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6884 modify_after_mirror = 1;
6885 action_flags |= actions->type ==
6886 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6887 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6888 MLX5_FLOW_ACTION_SET_IPV4_DST;
6889 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6891 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6892 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6893 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6899 if (item_ipv6_proto == IPPROTO_ICMPV6)
6900 return rte_flow_error_set(error, ENOTSUP,
6901 RTE_FLOW_ERROR_TYPE_ACTION,
6903 "Can't change header "
6904 "with ICMPv6 proto");
6905 /* Count all modify-header actions as one action. */
6906 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6908 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6909 modify_after_mirror = 1;
6910 action_flags |= actions->type ==
6911 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6912 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6913 MLX5_FLOW_ACTION_SET_IPV6_DST;
6914 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6916 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6917 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6918 ret = flow_dv_validate_action_modify_tp(action_flags,
6924 /* Count all modify-header actions as one action. */
6925 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6927 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6928 modify_after_mirror = 1;
6929 action_flags |= actions->type ==
6930 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6931 MLX5_FLOW_ACTION_SET_TP_SRC :
6932 MLX5_FLOW_ACTION_SET_TP_DST;
6933 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6935 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6936 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6937 ret = flow_dv_validate_action_modify_ttl(action_flags,
6943 /* Count all modify-header actions as one action. */
6944 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6946 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6947 modify_after_mirror = 1;
6948 action_flags |= actions->type ==
6949 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6950 MLX5_FLOW_ACTION_SET_TTL :
6951 MLX5_FLOW_ACTION_DEC_TTL;
6952 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6954 case RTE_FLOW_ACTION_TYPE_JUMP:
6955 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6961 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6963 return rte_flow_error_set(error, EINVAL,
6964 RTE_FLOW_ERROR_TYPE_ACTION,
6966 "sample and jump action combination is not supported");
6968 action_flags |= MLX5_FLOW_ACTION_JUMP;
6970 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6971 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6972 ret = flow_dv_validate_action_modify_tcp_seq
6979 /* Count all modify-header actions as one action. */
6980 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6982 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6983 modify_after_mirror = 1;
6984 action_flags |= actions->type ==
6985 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6986 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6987 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6988 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6990 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6991 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6992 ret = flow_dv_validate_action_modify_tcp_ack
6999 /* Count all modify-header actions as one action. */
7000 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7002 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7003 modify_after_mirror = 1;
7004 action_flags |= actions->type ==
7005 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7006 MLX5_FLOW_ACTION_INC_TCP_ACK :
7007 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7008 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7010 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7012 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7013 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7014 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7016 case RTE_FLOW_ACTION_TYPE_METER:
7017 ret = mlx5_flow_validate_action_meter(dev,
7023 action_flags |= MLX5_FLOW_ACTION_METER;
7025 /* Meter action will add one more TAG action. */
7026 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7028 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7029 if (!attr->transfer && !attr->group)
7030 return rte_flow_error_set(error, ENOTSUP,
7031 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7033 "Shared ASO age action is not supported for group 0");
7034 action_flags |= MLX5_FLOW_ACTION_AGE;
7037 case RTE_FLOW_ACTION_TYPE_AGE:
7038 ret = flow_dv_validate_action_age(action_flags,
7044 * Validate the regular AGE action (using counter)
7045 * mutual exclusion with share counter actions.
7047 if (!priv->sh->flow_hit_aso_en) {
7048 if (count && count->shared)
7049 return rte_flow_error_set
7051 RTE_FLOW_ERROR_TYPE_ACTION,
7053 "old age and shared count combination is not supported");
7055 return rte_flow_error_set
7057 RTE_FLOW_ERROR_TYPE_ACTION,
7059 "old age action and count must be in the same sub flow");
7061 action_flags |= MLX5_FLOW_ACTION_AGE;
7064 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7065 ret = flow_dv_validate_action_modify_ipv4_dscp
7072 /* Count all modify-header actions as one action. */
7073 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7075 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7076 modify_after_mirror = 1;
7077 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7078 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7080 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7081 ret = flow_dv_validate_action_modify_ipv6_dscp
7088 /* Count all modify-header actions as one action. */
7089 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7091 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7092 modify_after_mirror = 1;
7093 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7094 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7096 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7097 ret = flow_dv_validate_action_sample(&action_flags,
7106 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7109 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7110 if (actions[0].type != (typeof(actions[0].type))
7111 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7112 return rte_flow_error_set
7114 RTE_FLOW_ERROR_TYPE_ACTION,
7115 NULL, "MLX5 private action "
7116 "must be the first");
7118 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7120 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7121 ret = flow_dv_validate_action_modify_field(dev,
7128 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7129 modify_after_mirror = 1;
7130 /* Count all modify-header actions as one action. */
7131 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7133 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7137 return rte_flow_error_set(error, ENOTSUP,
7138 RTE_FLOW_ERROR_TYPE_ACTION,
7140 "action not supported");
7144 * Validate actions in flow rules
7145 * - Explicit decap action is prohibited by the tunnel offload API.
7146 * - Drop action in tunnel steer rule is prohibited by the API.
7147 * - Application cannot use MARK action because it's value can mask
7148 * tunnel default miss nitification.
7149 * - JUMP in tunnel match rule has no support in current PMD
7151 * - TAG & META are reserved for future uses.
7153 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7154 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7155 MLX5_FLOW_ACTION_MARK |
7156 MLX5_FLOW_ACTION_SET_TAG |
7157 MLX5_FLOW_ACTION_SET_META |
7158 MLX5_FLOW_ACTION_DROP;
7160 if (action_flags & bad_actions_mask)
7161 return rte_flow_error_set
7163 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7164 "Invalid RTE action in tunnel "
7166 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7167 return rte_flow_error_set
7169 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7170 "tunnel set decap rule must terminate "
7173 return rte_flow_error_set
7175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7176 "tunnel flows for ingress traffic only");
7178 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7179 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7180 MLX5_FLOW_ACTION_MARK |
7181 MLX5_FLOW_ACTION_SET_TAG |
7182 MLX5_FLOW_ACTION_SET_META;
7184 if (action_flags & bad_actions_mask)
7185 return rte_flow_error_set
7187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7188 "Invalid RTE action in tunnel "
7192 * Validate the drop action mutual exclusion with other actions.
7193 * Drop action is mutually-exclusive with any other action, except for
7195 * Drop action compatibility with tunnel offload was already validated.
7197 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7198 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7199 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7200 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7201 return rte_flow_error_set(error, EINVAL,
7202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7203 "Drop action is mutually-exclusive "
7204 "with any other action, except for "
7206 /* Eswitch has few restrictions on using items and actions */
7207 if (attr->transfer) {
7208 if (!mlx5_flow_ext_mreg_supported(dev) &&
7209 action_flags & MLX5_FLOW_ACTION_FLAG)
7210 return rte_flow_error_set(error, ENOTSUP,
7211 RTE_FLOW_ERROR_TYPE_ACTION,
7213 "unsupported action FLAG");
7214 if (!mlx5_flow_ext_mreg_supported(dev) &&
7215 action_flags & MLX5_FLOW_ACTION_MARK)
7216 return rte_flow_error_set(error, ENOTSUP,
7217 RTE_FLOW_ERROR_TYPE_ACTION,
7219 "unsupported action MARK");
7220 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7221 return rte_flow_error_set(error, ENOTSUP,
7222 RTE_FLOW_ERROR_TYPE_ACTION,
7224 "unsupported action QUEUE");
7225 if (action_flags & MLX5_FLOW_ACTION_RSS)
7226 return rte_flow_error_set(error, ENOTSUP,
7227 RTE_FLOW_ERROR_TYPE_ACTION,
7229 "unsupported action RSS");
7230 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7231 return rte_flow_error_set(error, EINVAL,
7232 RTE_FLOW_ERROR_TYPE_ACTION,
7234 "no fate action is found");
7236 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7237 return rte_flow_error_set(error, EINVAL,
7238 RTE_FLOW_ERROR_TYPE_ACTION,
7240 "no fate action is found");
7243 * Continue validation for Xcap and VLAN actions.
7244 * If hairpin is working in explicit TX rule mode, there is no actions
7245 * splitting and the validation of hairpin ingress flow should be the
7246 * same as other standard flows.
7248 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7249 MLX5_FLOW_VLAN_ACTIONS)) &&
7250 (queue_index == 0xFFFF ||
7251 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7252 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7253 conf->tx_explicit != 0))) {
7254 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7255 MLX5_FLOW_XCAP_ACTIONS)
7256 return rte_flow_error_set(error, ENOTSUP,
7257 RTE_FLOW_ERROR_TYPE_ACTION,
7258 NULL, "encap and decap "
7259 "combination aren't supported");
7260 if (!attr->transfer && attr->ingress) {
7261 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7262 return rte_flow_error_set
7264 RTE_FLOW_ERROR_TYPE_ACTION,
7265 NULL, "encap is not supported"
7266 " for ingress traffic");
7267 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7268 return rte_flow_error_set
7270 RTE_FLOW_ERROR_TYPE_ACTION,
7271 NULL, "push VLAN action not "
7272 "supported for ingress");
7273 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7274 MLX5_FLOW_VLAN_ACTIONS)
7275 return rte_flow_error_set
7277 RTE_FLOW_ERROR_TYPE_ACTION,
7278 NULL, "no support for "
7279 "multiple VLAN actions");
7283 * Hairpin flow will add one more TAG action in TX implicit mode.
7284 * In TX explicit mode, there will be no hairpin flow ID.
7287 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7288 /* extra metadata enabled: one more TAG action will be add. */
7289 if (dev_conf->dv_flow_en &&
7290 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7291 mlx5_flow_ext_mreg_supported(dev))
7292 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7294 flow_dv_modify_hdr_action_max(dev, is_root)) {
7295 return rte_flow_error_set(error, ENOTSUP,
7296 RTE_FLOW_ERROR_TYPE_ACTION,
7297 NULL, "too many header modify"
7298 " actions to support");
7300 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7301 if (fdb_mirror_limit && modify_after_mirror)
7302 return rte_flow_error_set(error, EINVAL,
7303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7304 "sample before modify action is not supported");
7309 * Internal preparation function. Allocates the DV flow size,
7310 * this size is constant.
7313 * Pointer to the rte_eth_dev structure.
7315 * Pointer to the flow attributes.
7317 * Pointer to the list of items.
7318 * @param[in] actions
7319 * Pointer to the list of actions.
7321 * Pointer to the error structure.
7324 * Pointer to mlx5_flow object on success,
7325 * otherwise NULL and rte_errno is set.
7327 static struct mlx5_flow *
7328 flow_dv_prepare(struct rte_eth_dev *dev,
7329 const struct rte_flow_attr *attr __rte_unused,
7330 const struct rte_flow_item items[] __rte_unused,
7331 const struct rte_flow_action actions[] __rte_unused,
7332 struct rte_flow_error *error)
7334 uint32_t handle_idx = 0;
7335 struct mlx5_flow *dev_flow;
7336 struct mlx5_flow_handle *dev_handle;
7337 struct mlx5_priv *priv = dev->data->dev_private;
7338 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7341 /* In case of corrupting the memory. */
7342 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7343 rte_flow_error_set(error, ENOSPC,
7344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7345 "not free temporary device flow");
7348 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7351 rte_flow_error_set(error, ENOMEM,
7352 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7353 "not enough memory to create flow handle");
7356 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7357 dev_flow = &wks->flows[wks->flow_idx++];
7358 memset(dev_flow, 0, sizeof(*dev_flow));
7359 dev_flow->handle = dev_handle;
7360 dev_flow->handle_idx = handle_idx;
7362 * In some old rdma-core releases, before continuing, a check of the
7363 * length of matching parameter will be done at first. It needs to use
7364 * the length without misc4 param. If the flow has misc4 support, then
7365 * the length needs to be adjusted accordingly. Each param member is
7366 * aligned with a 64B boundary naturally.
7368 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7369 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7370 dev_flow->ingress = attr->ingress;
7371 dev_flow->dv.transfer = attr->transfer;
7375 #ifdef RTE_LIBRTE_MLX5_DEBUG
7377 * Sanity check for match mask and value. Similar to check_valid_spec() in
7378 * kernel driver. If unmasked bit is present in value, it returns failure.
7381 * pointer to match mask buffer.
7382 * @param match_value
7383 * pointer to match value buffer.
7386 * 0 if valid, -EINVAL otherwise.
7389 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7391 uint8_t *m = match_mask;
7392 uint8_t *v = match_value;
7395 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7398 "match_value differs from match_criteria"
7399 " %p[%u] != %p[%u]",
7400 match_value, i, match_mask, i);
7409 * Add match of ip_version.
7413 * @param[in] headers_v
7414 * Values header pointer.
7415 * @param[in] headers_m
7416 * Masks header pointer.
7417 * @param[in] ip_version
7418 * The IP version to set.
7421 flow_dv_set_match_ip_version(uint32_t group,
7427 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7429 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7431 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7432 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7433 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7437 * Add Ethernet item to matcher and to the value.
7439 * @param[in, out] matcher
7441 * @param[in, out] key
7442 * Flow matcher value.
7444 * Flow pattern to translate.
7446 * Item is inner pattern.
7449 flow_dv_translate_item_eth(void *matcher, void *key,
7450 const struct rte_flow_item *item, int inner,
7453 const struct rte_flow_item_eth *eth_m = item->mask;
7454 const struct rte_flow_item_eth *eth_v = item->spec;
7455 const struct rte_flow_item_eth nic_mask = {
7456 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7457 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7458 .type = RTE_BE16(0xffff),
7471 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7473 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7475 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7477 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7479 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7480 ð_m->dst, sizeof(eth_m->dst));
7481 /* The value must be in the range of the mask. */
7482 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7483 for (i = 0; i < sizeof(eth_m->dst); ++i)
7484 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7485 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7486 ð_m->src, sizeof(eth_m->src));
7487 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7488 /* The value must be in the range of the mask. */
7489 for (i = 0; i < sizeof(eth_m->dst); ++i)
7490 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7492 * HW supports match on one Ethertype, the Ethertype following the last
7493 * VLAN tag of the packet (see PRM).
7494 * Set match on ethertype only if ETH header is not followed by VLAN.
7495 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7496 * ethertype, and use ip_version field instead.
7497 * eCPRI over Ether layer will use type value 0xAEFE.
7499 if (eth_m->type == 0xFFFF) {
7500 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7501 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7502 switch (eth_v->type) {
7503 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7504 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7506 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7507 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7508 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7510 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7511 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7513 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7514 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7520 if (eth_m->has_vlan) {
7521 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7522 if (eth_v->has_vlan) {
7524 * Here, when also has_more_vlan field in VLAN item is
7525 * not set, only single-tagged packets will be matched.
7527 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7531 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7532 rte_be_to_cpu_16(eth_m->type));
7533 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7534 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7538 * Add VLAN item to matcher and to the value.
7540 * @param[in, out] dev_flow
7542 * @param[in, out] matcher
7544 * @param[in, out] key
7545 * Flow matcher value.
7547 * Flow pattern to translate.
7549 * Item is inner pattern.
7552 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7553 void *matcher, void *key,
7554 const struct rte_flow_item *item,
7555 int inner, uint32_t group)
7557 const struct rte_flow_item_vlan *vlan_m = item->mask;
7558 const struct rte_flow_item_vlan *vlan_v = item->spec;
7565 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7567 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7569 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7571 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7573 * This is workaround, masks are not supported,
7574 * and pre-validated.
7577 dev_flow->handle->vf_vlan.tag =
7578 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7581 * When VLAN item exists in flow, mark packet as tagged,
7582 * even if TCI is not specified.
7584 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7585 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7586 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7591 vlan_m = &rte_flow_item_vlan_mask;
7592 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7593 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7594 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7595 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7596 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7597 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7598 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7599 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7601 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7602 * ethertype, and use ip_version field instead.
7604 if (vlan_m->inner_type == 0xFFFF) {
7605 switch (vlan_v->inner_type) {
7606 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7607 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7608 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7609 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7611 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7612 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7614 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7615 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7621 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7622 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7623 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7624 /* Only one vlan_tag bit can be set. */
7625 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7628 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7629 rte_be_to_cpu_16(vlan_m->inner_type));
7630 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7631 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7635 * Add IPV4 item to matcher and to the value.
7637 * @param[in, out] matcher
7639 * @param[in, out] key
7640 * Flow matcher value.
7642 * Flow pattern to translate.
7644 * Item is inner pattern.
7646 * The group to insert the rule.
7649 flow_dv_translate_item_ipv4(void *matcher, void *key,
7650 const struct rte_flow_item *item,
7651 int inner, uint32_t group)
7653 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7654 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7655 const struct rte_flow_item_ipv4 nic_mask = {
7657 .src_addr = RTE_BE32(0xffffffff),
7658 .dst_addr = RTE_BE32(0xffffffff),
7659 .type_of_service = 0xff,
7660 .next_proto_id = 0xff,
7661 .time_to_live = 0xff,
7671 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7673 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7675 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7677 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7679 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7684 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7685 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7686 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7687 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7688 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7689 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7690 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7691 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7692 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7693 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7694 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7695 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7696 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7697 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7698 ipv4_m->hdr.type_of_service);
7699 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7700 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7701 ipv4_m->hdr.type_of_service >> 2);
7702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7703 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7704 ipv4_m->hdr.next_proto_id);
7705 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7706 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7707 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7708 ipv4_m->hdr.time_to_live);
7709 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7710 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7711 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7712 !!(ipv4_m->hdr.fragment_offset));
7713 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7714 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7718 * Add IPV6 item to matcher and to the value.
7720 * @param[in, out] matcher
7722 * @param[in, out] key
7723 * Flow matcher value.
7725 * Flow pattern to translate.
7727 * Item is inner pattern.
7729 * The group to insert the rule.
7732 flow_dv_translate_item_ipv6(void *matcher, void *key,
7733 const struct rte_flow_item *item,
7734 int inner, uint32_t group)
7736 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7737 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7738 const struct rte_flow_item_ipv6 nic_mask = {
7741 "\xff\xff\xff\xff\xff\xff\xff\xff"
7742 "\xff\xff\xff\xff\xff\xff\xff\xff",
7744 "\xff\xff\xff\xff\xff\xff\xff\xff"
7745 "\xff\xff\xff\xff\xff\xff\xff\xff",
7746 .vtc_flow = RTE_BE32(0xffffffff),
7753 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7754 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7763 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7765 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7767 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7769 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7771 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7776 size = sizeof(ipv6_m->hdr.dst_addr);
7777 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7778 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7779 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7780 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7781 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7782 for (i = 0; i < size; ++i)
7783 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7784 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7785 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7786 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7787 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7788 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7789 for (i = 0; i < size; ++i)
7790 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7792 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7793 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7794 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7795 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7796 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7797 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7800 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7802 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7805 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7807 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7811 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7813 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7814 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7816 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7817 ipv6_m->hdr.hop_limits);
7818 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7819 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7820 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7821 !!(ipv6_m->has_frag_ext));
7822 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7823 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7827 * Add IPV6 fragment extension item to matcher and to the value.
7829 * @param[in, out] matcher
7831 * @param[in, out] key
7832 * Flow matcher value.
7834 * Flow pattern to translate.
7836 * Item is inner pattern.
7839 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7840 const struct rte_flow_item *item,
7843 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7844 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7845 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7847 .next_header = 0xff,
7848 .frag_data = RTE_BE16(0xffff),
7855 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7857 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7859 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7861 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7863 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7864 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7865 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7866 if (!ipv6_frag_ext_v)
7868 if (!ipv6_frag_ext_m)
7869 ipv6_frag_ext_m = &nic_mask;
7870 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7871 ipv6_frag_ext_m->hdr.next_header);
7872 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7873 ipv6_frag_ext_v->hdr.next_header &
7874 ipv6_frag_ext_m->hdr.next_header);
7878 * Add TCP item to matcher and to the value.
7880 * @param[in, out] matcher
7882 * @param[in, out] key
7883 * Flow matcher value.
7885 * Flow pattern to translate.
7887 * Item is inner pattern.
7890 flow_dv_translate_item_tcp(void *matcher, void *key,
7891 const struct rte_flow_item *item,
7894 const struct rte_flow_item_tcp *tcp_m = item->mask;
7895 const struct rte_flow_item_tcp *tcp_v = item->spec;
7900 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7902 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7904 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7906 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7908 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7909 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7913 tcp_m = &rte_flow_item_tcp_mask;
7914 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7915 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7916 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7917 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7918 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7919 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7920 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7921 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7922 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7923 tcp_m->hdr.tcp_flags);
7924 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7925 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7929 * Add UDP item to matcher and to the value.
7931 * @param[in, out] matcher
7933 * @param[in, out] key
7934 * Flow matcher value.
7936 * Flow pattern to translate.
7938 * Item is inner pattern.
7941 flow_dv_translate_item_udp(void *matcher, void *key,
7942 const struct rte_flow_item *item,
7945 const struct rte_flow_item_udp *udp_m = item->mask;
7946 const struct rte_flow_item_udp *udp_v = item->spec;
7951 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7953 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7955 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7957 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7959 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7960 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7964 udp_m = &rte_flow_item_udp_mask;
7965 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7966 rte_be_to_cpu_16(udp_m->hdr.src_port));
7967 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7968 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7969 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7970 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7971 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7972 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7976 * Add GRE optional Key item to matcher and to the value.
7978 * @param[in, out] matcher
7980 * @param[in, out] key
7981 * Flow matcher value.
7983 * Flow pattern to translate.
7985 * Item is inner pattern.
7988 flow_dv_translate_item_gre_key(void *matcher, void *key,
7989 const struct rte_flow_item *item)
7991 const rte_be32_t *key_m = item->mask;
7992 const rte_be32_t *key_v = item->spec;
7993 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7994 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7995 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7997 /* GRE K bit must be on and should already be validated */
7998 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7999 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8003 key_m = &gre_key_default_mask;
8004 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8005 rte_be_to_cpu_32(*key_m) >> 8);
8006 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8007 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8008 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8009 rte_be_to_cpu_32(*key_m) & 0xFF);
8010 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8011 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8015 * Add GRE item to matcher and to the value.
8017 * @param[in, out] matcher
8019 * @param[in, out] key
8020 * Flow matcher value.
8022 * Flow pattern to translate.
8024 * Item is inner pattern.
8027 flow_dv_translate_item_gre(void *matcher, void *key,
8028 const struct rte_flow_item *item,
8031 const struct rte_flow_item_gre *gre_m = item->mask;
8032 const struct rte_flow_item_gre *gre_v = item->spec;
8035 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8036 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8043 uint16_t s_present:1;
8044 uint16_t k_present:1;
8045 uint16_t rsvd_bit1:1;
8046 uint16_t c_present:1;
8050 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8053 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8055 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8059 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8066 gre_m = &rte_flow_item_gre_mask;
8067 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8068 rte_be_to_cpu_16(gre_m->protocol));
8069 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8070 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8071 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8072 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8073 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8074 gre_crks_rsvd0_ver_m.c_present);
8075 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8076 gre_crks_rsvd0_ver_v.c_present &
8077 gre_crks_rsvd0_ver_m.c_present);
8078 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8079 gre_crks_rsvd0_ver_m.k_present);
8080 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8081 gre_crks_rsvd0_ver_v.k_present &
8082 gre_crks_rsvd0_ver_m.k_present);
8083 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8084 gre_crks_rsvd0_ver_m.s_present);
8085 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8086 gre_crks_rsvd0_ver_v.s_present &
8087 gre_crks_rsvd0_ver_m.s_present);
8091 * Add NVGRE item to matcher and to the value.
8093 * @param[in, out] matcher
8095 * @param[in, out] key
8096 * Flow matcher value.
8098 * Flow pattern to translate.
8100 * Item is inner pattern.
8103 flow_dv_translate_item_nvgre(void *matcher, void *key,
8104 const struct rte_flow_item *item,
8107 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8108 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8109 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8110 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8111 const char *tni_flow_id_m;
8112 const char *tni_flow_id_v;
8118 /* For NVGRE, GRE header fields must be set with defined values. */
8119 const struct rte_flow_item_gre gre_spec = {
8120 .c_rsvd0_ver = RTE_BE16(0x2000),
8121 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8123 const struct rte_flow_item_gre gre_mask = {
8124 .c_rsvd0_ver = RTE_BE16(0xB000),
8125 .protocol = RTE_BE16(UINT16_MAX),
8127 const struct rte_flow_item gre_item = {
8132 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8136 nvgre_m = &rte_flow_item_nvgre_mask;
8137 tni_flow_id_m = (const char *)nvgre_m->tni;
8138 tni_flow_id_v = (const char *)nvgre_v->tni;
8139 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8140 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8141 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8142 memcpy(gre_key_m, tni_flow_id_m, size);
8143 for (i = 0; i < size; ++i)
8144 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8148 * Add VXLAN item to matcher and to the value.
8150 * @param[in, out] matcher
8152 * @param[in, out] key
8153 * Flow matcher value.
8155 * Flow pattern to translate.
8157 * Item is inner pattern.
8160 flow_dv_translate_item_vxlan(void *matcher, void *key,
8161 const struct rte_flow_item *item,
8164 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8165 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8168 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8169 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8177 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8179 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8181 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8183 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8185 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8186 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8187 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8188 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8189 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8194 vxlan_m = &rte_flow_item_vxlan_mask;
8195 size = sizeof(vxlan_m->vni);
8196 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8197 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8198 memcpy(vni_m, vxlan_m->vni, size);
8199 for (i = 0; i < size; ++i)
8200 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8204 * Add VXLAN-GPE item to matcher and to the value.
8206 * @param[in, out] matcher
8208 * @param[in, out] key
8209 * Flow matcher value.
8211 * Flow pattern to translate.
8213 * Item is inner pattern.
8217 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8218 const struct rte_flow_item *item, int inner)
8220 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8221 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8225 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8227 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8233 uint8_t flags_m = 0xff;
8234 uint8_t flags_v = 0xc;
8237 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8239 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8241 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8243 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8245 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8246 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8247 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8248 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8249 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8254 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8255 size = sizeof(vxlan_m->vni);
8256 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8257 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8258 memcpy(vni_m, vxlan_m->vni, size);
8259 for (i = 0; i < size; ++i)
8260 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8261 if (vxlan_m->flags) {
8262 flags_m = vxlan_m->flags;
8263 flags_v = vxlan_v->flags;
8265 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8266 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8267 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8269 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8274 * Add Geneve item to matcher and to the value.
8276 * @param[in, out] matcher
8278 * @param[in, out] key
8279 * Flow matcher value.
8281 * Flow pattern to translate.
8283 * Item is inner pattern.
8287 flow_dv_translate_item_geneve(void *matcher, void *key,
8288 const struct rte_flow_item *item, int inner)
8290 const struct rte_flow_item_geneve *geneve_m = item->mask;
8291 const struct rte_flow_item_geneve *geneve_v = item->spec;
8294 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8295 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8304 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8306 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8308 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8310 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8312 dport = MLX5_UDP_PORT_GENEVE;
8313 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8314 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8315 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8320 geneve_m = &rte_flow_item_geneve_mask;
8321 size = sizeof(geneve_m->vni);
8322 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8323 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8324 memcpy(vni_m, geneve_m->vni, size);
8325 for (i = 0; i < size; ++i)
8326 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8327 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8328 rte_be_to_cpu_16(geneve_m->protocol));
8329 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8330 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8331 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8332 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8333 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8334 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8335 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8336 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8337 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8338 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8339 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8340 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8341 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8345 * Create Geneve TLV option resource.
8347 * @param dev[in, out]
8348 * Pointer to rte_eth_dev structure.
8349 * @param[in, out] tag_be24
8350 * Tag value in big endian then R-shift 8.
8351 * @parm[in, out] dev_flow
8352 * Pointer to the dev_flow.
8354 * pointer to error structure.
8357 * 0 on success otherwise -errno and errno is set.
8361 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8362 const struct rte_flow_item *item,
8363 struct rte_flow_error *error)
8365 struct mlx5_priv *priv = dev->data->dev_private;
8366 struct mlx5_dev_ctx_shared *sh = priv->sh;
8367 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8368 sh->geneve_tlv_option_resource;
8369 struct mlx5_devx_obj *obj;
8370 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8375 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8376 if (geneve_opt_resource != NULL) {
8377 if (geneve_opt_resource->option_class ==
8378 geneve_opt_v->option_class &&
8379 geneve_opt_resource->option_type ==
8380 geneve_opt_v->option_type &&
8381 geneve_opt_resource->length ==
8382 geneve_opt_v->option_len) {
8383 /* We already have GENVE TLV option obj allocated. */
8384 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8387 ret = rte_flow_error_set(error, ENOMEM,
8388 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8389 "Only one GENEVE TLV option supported");
8393 /* Create a GENEVE TLV object and resource. */
8394 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8395 geneve_opt_v->option_class,
8396 geneve_opt_v->option_type,
8397 geneve_opt_v->option_len);
8399 ret = rte_flow_error_set(error, ENODATA,
8400 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8401 "Failed to create GENEVE TLV Devx object");
8404 sh->geneve_tlv_option_resource =
8405 mlx5_malloc(MLX5_MEM_ZERO,
8406 sizeof(*geneve_opt_resource),
8408 if (!sh->geneve_tlv_option_resource) {
8409 claim_zero(mlx5_devx_cmd_destroy(obj));
8410 ret = rte_flow_error_set(error, ENOMEM,
8411 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8412 "GENEVE TLV object memory allocation failed");
8415 geneve_opt_resource = sh->geneve_tlv_option_resource;
8416 geneve_opt_resource->obj = obj;
8417 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8418 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8419 geneve_opt_resource->length = geneve_opt_v->option_len;
8420 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8424 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8429 * Add Geneve TLV option item to matcher.
8431 * @param[in, out] dev
8432 * Pointer to rte_eth_dev structure.
8433 * @param[in, out] matcher
8435 * @param[in, out] key
8436 * Flow matcher value.
8438 * Flow pattern to translate.
8440 * Pointer to error structure.
8443 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8444 void *key, const struct rte_flow_item *item,
8445 struct rte_flow_error *error)
8447 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8448 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8449 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8450 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8451 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8453 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8454 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8460 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8461 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8464 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8468 * Set the option length in GENEVE header if not requested.
8469 * The GENEVE TLV option length is expressed by the option length field
8470 * in the GENEVE header.
8471 * If the option length was not requested but the GENEVE TLV option item
8472 * is present we set the option length field implicitly.
8474 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8475 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8476 MLX5_GENEVE_OPTLEN_MASK);
8477 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8478 geneve_opt_v->option_len + 1);
8481 if (geneve_opt_v->data) {
8482 memcpy(&opt_data_key, geneve_opt_v->data,
8483 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8484 sizeof(opt_data_key)));
8485 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8486 sizeof(opt_data_key));
8487 memcpy(&opt_data_mask, geneve_opt_m->data,
8488 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8489 sizeof(opt_data_mask)));
8490 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8491 sizeof(opt_data_mask));
8492 MLX5_SET(fte_match_set_misc3, misc3_m,
8493 geneve_tlv_option_0_data,
8494 rte_be_to_cpu_32(opt_data_mask));
8495 MLX5_SET(fte_match_set_misc3, misc3_v,
8496 geneve_tlv_option_0_data,
8497 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8503 * Add MPLS item to matcher and to the value.
8505 * @param[in, out] matcher
8507 * @param[in, out] key
8508 * Flow matcher value.
8510 * Flow pattern to translate.
8511 * @param[in] prev_layer
8512 * The protocol layer indicated in previous item.
8514 * Item is inner pattern.
8517 flow_dv_translate_item_mpls(void *matcher, void *key,
8518 const struct rte_flow_item *item,
8519 uint64_t prev_layer,
8522 const uint32_t *in_mpls_m = item->mask;
8523 const uint32_t *in_mpls_v = item->spec;
8524 uint32_t *out_mpls_m = 0;
8525 uint32_t *out_mpls_v = 0;
8526 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8527 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8528 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8530 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8531 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8532 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8534 switch (prev_layer) {
8535 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8536 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8538 MLX5_UDP_PORT_MPLS);
8540 case MLX5_FLOW_LAYER_GRE:
8541 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8542 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8543 RTE_ETHER_TYPE_MPLS);
8546 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8547 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8554 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8555 switch (prev_layer) {
8556 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8558 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8559 outer_first_mpls_over_udp);
8561 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8562 outer_first_mpls_over_udp);
8564 case MLX5_FLOW_LAYER_GRE:
8566 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8567 outer_first_mpls_over_gre);
8569 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8570 outer_first_mpls_over_gre);
8573 /* Inner MPLS not over GRE is not supported. */
8576 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8580 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8586 if (out_mpls_m && out_mpls_v) {
8587 *out_mpls_m = *in_mpls_m;
8588 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8593 * Add metadata register item to matcher
8595 * @param[in, out] matcher
8597 * @param[in, out] key
8598 * Flow matcher value.
8599 * @param[in] reg_type
8600 * Type of device metadata register
8607 flow_dv_match_meta_reg(void *matcher, void *key,
8608 enum modify_reg reg_type,
8609 uint32_t data, uint32_t mask)
8612 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8614 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8620 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8621 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8624 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8625 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8629 * The metadata register C0 field might be divided into
8630 * source vport index and META item value, we should set
8631 * this field according to specified mask, not as whole one.
8633 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8635 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8636 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8639 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8642 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8643 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8646 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8647 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8650 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8651 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8654 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8655 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8658 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8659 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8662 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8663 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8666 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8667 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8676 * Add MARK item to matcher
8679 * The device to configure through.
8680 * @param[in, out] matcher
8682 * @param[in, out] key
8683 * Flow matcher value.
8685 * Flow pattern to translate.
8688 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8689 void *matcher, void *key,
8690 const struct rte_flow_item *item)
8692 struct mlx5_priv *priv = dev->data->dev_private;
8693 const struct rte_flow_item_mark *mark;
8697 mark = item->mask ? (const void *)item->mask :
8698 &rte_flow_item_mark_mask;
8699 mask = mark->id & priv->sh->dv_mark_mask;
8700 mark = (const void *)item->spec;
8702 value = mark->id & priv->sh->dv_mark_mask & mask;
8704 enum modify_reg reg;
8706 /* Get the metadata register index for the mark. */
8707 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8708 MLX5_ASSERT(reg > 0);
8709 if (reg == REG_C_0) {
8710 struct mlx5_priv *priv = dev->data->dev_private;
8711 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8712 uint32_t shl_c0 = rte_bsf32(msk_c0);
8718 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8723 * Add META item to matcher
8726 * The devich to configure through.
8727 * @param[in, out] matcher
8729 * @param[in, out] key
8730 * Flow matcher value.
8732 * Attributes of flow that includes this item.
8734 * Flow pattern to translate.
8737 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8738 void *matcher, void *key,
8739 const struct rte_flow_attr *attr,
8740 const struct rte_flow_item *item)
8742 const struct rte_flow_item_meta *meta_m;
8743 const struct rte_flow_item_meta *meta_v;
8745 meta_m = (const void *)item->mask;
8747 meta_m = &rte_flow_item_meta_mask;
8748 meta_v = (const void *)item->spec;
8751 uint32_t value = meta_v->data;
8752 uint32_t mask = meta_m->data;
8754 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8757 MLX5_ASSERT(reg != REG_NON);
8759 * In datapath code there is no endianness
8760 * coversions for perfromance reasons, all
8761 * pattern conversions are done in rte_flow.
8763 value = rte_cpu_to_be_32(value);
8764 mask = rte_cpu_to_be_32(mask);
8765 if (reg == REG_C_0) {
8766 struct mlx5_priv *priv = dev->data->dev_private;
8767 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8768 uint32_t shl_c0 = rte_bsf32(msk_c0);
8769 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8770 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8777 MLX5_ASSERT(msk_c0);
8778 MLX5_ASSERT(!(~msk_c0 & mask));
8780 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8785 * Add vport metadata Reg C0 item to matcher
8787 * @param[in, out] matcher
8789 * @param[in, out] key
8790 * Flow matcher value.
8792 * Flow pattern to translate.
8795 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8796 uint32_t value, uint32_t mask)
8798 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8802 * Add tag item to matcher
8805 * The devich to configure through.
8806 * @param[in, out] matcher
8808 * @param[in, out] key
8809 * Flow matcher value.
8811 * Flow pattern to translate.
8814 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8815 void *matcher, void *key,
8816 const struct rte_flow_item *item)
8818 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8819 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8820 uint32_t mask, value;
8823 value = tag_v->data;
8824 mask = tag_m ? tag_m->data : UINT32_MAX;
8825 if (tag_v->id == REG_C_0) {
8826 struct mlx5_priv *priv = dev->data->dev_private;
8827 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8828 uint32_t shl_c0 = rte_bsf32(msk_c0);
8834 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8838 * Add TAG item to matcher
8841 * The devich to configure through.
8842 * @param[in, out] matcher
8844 * @param[in, out] key
8845 * Flow matcher value.
8847 * Flow pattern to translate.
8850 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8851 void *matcher, void *key,
8852 const struct rte_flow_item *item)
8854 const struct rte_flow_item_tag *tag_v = item->spec;
8855 const struct rte_flow_item_tag *tag_m = item->mask;
8856 enum modify_reg reg;
8859 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8860 /* Get the metadata register index for the tag. */
8861 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8862 MLX5_ASSERT(reg > 0);
8863 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8867 * Add source vport match to the specified matcher.
8869 * @param[in, out] matcher
8871 * @param[in, out] key
8872 * Flow matcher value.
8874 * Source vport value to match
8879 flow_dv_translate_item_source_vport(void *matcher, void *key,
8880 int16_t port, uint16_t mask)
8882 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8883 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8885 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8886 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8890 * Translate port-id item to eswitch match on port-id.
8893 * The devich to configure through.
8894 * @param[in, out] matcher
8896 * @param[in, out] key
8897 * Flow matcher value.
8899 * Flow pattern to translate.
8904 * 0 on success, a negative errno value otherwise.
8907 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8908 void *key, const struct rte_flow_item *item,
8909 const struct rte_flow_attr *attr)
8911 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8912 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8913 struct mlx5_priv *priv;
8916 mask = pid_m ? pid_m->id : 0xffff;
8917 id = pid_v ? pid_v->id : dev->data->port_id;
8918 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8922 * Translate to vport field or to metadata, depending on mode.
8923 * Kernel can use either misc.source_port or half of C0 metadata
8926 if (priv->vport_meta_mask) {
8928 * Provide the hint for SW steering library
8929 * to insert the flow into ingress domain and
8930 * save the extra vport match.
8932 if (mask == 0xffff && priv->vport_id == 0xffff &&
8933 priv->pf_bond < 0 && attr->transfer)
8934 flow_dv_translate_item_source_vport
8935 (matcher, key, priv->vport_id, mask);
8937 * We should always set the vport metadata register,
8938 * otherwise the SW steering library can drop
8939 * the rule if wire vport metadata value is not zero,
8940 * it depends on kernel configuration.
8942 flow_dv_translate_item_meta_vport(matcher, key,
8943 priv->vport_meta_tag,
8944 priv->vport_meta_mask);
8946 flow_dv_translate_item_source_vport(matcher, key,
8947 priv->vport_id, mask);
8953 * Add ICMP6 item to matcher and to the value.
8955 * @param[in, out] matcher
8957 * @param[in, out] key
8958 * Flow matcher value.
8960 * Flow pattern to translate.
8962 * Item is inner pattern.
8965 flow_dv_translate_item_icmp6(void *matcher, void *key,
8966 const struct rte_flow_item *item,
8969 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8970 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8973 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8975 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8977 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8979 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8981 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8983 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8985 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8990 icmp6_m = &rte_flow_item_icmp6_mask;
8991 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8992 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8993 icmp6_v->type & icmp6_m->type);
8994 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8995 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8996 icmp6_v->code & icmp6_m->code);
9000 * Add ICMP item to matcher and to the value.
9002 * @param[in, out] matcher
9004 * @param[in, out] key
9005 * Flow matcher value.
9007 * Flow pattern to translate.
9009 * Item is inner pattern.
9012 flow_dv_translate_item_icmp(void *matcher, void *key,
9013 const struct rte_flow_item *item,
9016 const struct rte_flow_item_icmp *icmp_m = item->mask;
9017 const struct rte_flow_item_icmp *icmp_v = item->spec;
9018 uint32_t icmp_header_data_m = 0;
9019 uint32_t icmp_header_data_v = 0;
9022 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9024 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9026 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9028 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9030 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9032 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9034 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9035 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9039 icmp_m = &rte_flow_item_icmp_mask;
9040 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9041 icmp_m->hdr.icmp_type);
9042 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9043 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9044 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9045 icmp_m->hdr.icmp_code);
9046 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9047 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9048 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9049 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9050 if (icmp_header_data_m) {
9051 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9052 icmp_header_data_v |=
9053 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9054 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9055 icmp_header_data_m);
9056 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9057 icmp_header_data_v & icmp_header_data_m);
9062 * Add GTP item to matcher and to the value.
9064 * @param[in, out] matcher
9066 * @param[in, out] key
9067 * Flow matcher value.
9069 * Flow pattern to translate.
9071 * Item is inner pattern.
9074 flow_dv_translate_item_gtp(void *matcher, void *key,
9075 const struct rte_flow_item *item, int inner)
9077 const struct rte_flow_item_gtp *gtp_m = item->mask;
9078 const struct rte_flow_item_gtp *gtp_v = item->spec;
9081 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9083 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9084 uint16_t dport = RTE_GTPU_UDP_PORT;
9087 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9089 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9091 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9093 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9095 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9096 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9097 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9102 gtp_m = &rte_flow_item_gtp_mask;
9103 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9104 gtp_m->v_pt_rsv_flags);
9105 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9106 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9107 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9108 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9109 gtp_v->msg_type & gtp_m->msg_type);
9110 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9111 rte_be_to_cpu_32(gtp_m->teid));
9112 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9113 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9117 * Add GTP PSC item to matcher.
9119 * @param[in, out] matcher
9121 * @param[in, out] key
9122 * Flow matcher value.
9124 * Flow pattern to translate.
9127 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9128 const struct rte_flow_item *item)
9130 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9131 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9132 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9134 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9140 uint8_t next_ext_header_type;
9145 /* Always set E-flag match on one, regardless of GTP item settings. */
9146 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9147 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9148 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9149 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9150 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9151 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9152 /*Set next extension header type. */
9155 dw_2.next_ext_header_type = 0xff;
9156 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9157 rte_cpu_to_be_32(dw_2.w32));
9160 dw_2.next_ext_header_type = 0x85;
9161 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9162 rte_cpu_to_be_32(dw_2.w32));
9174 /*Set extension header PDU type and Qos. */
9176 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9178 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9179 dw_0.qfi = gtp_psc_m->qfi;
9180 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9181 rte_cpu_to_be_32(dw_0.w32));
9183 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9184 gtp_psc_m->pdu_type);
9185 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9186 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9187 rte_cpu_to_be_32(dw_0.w32));
9193 * Add eCPRI item to matcher and to the value.
9196 * The devich to configure through.
9197 * @param[in, out] matcher
9199 * @param[in, out] key
9200 * Flow matcher value.
9202 * Flow pattern to translate.
9203 * @param[in] samples
9204 * Sample IDs to be used in the matching.
9207 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9208 void *key, const struct rte_flow_item *item)
9210 struct mlx5_priv *priv = dev->data->dev_private;
9211 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9212 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9213 struct rte_ecpri_common_hdr common;
9214 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9216 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9224 ecpri_m = &rte_flow_item_ecpri_mask;
9226 * Maximal four DW samples are supported in a single matching now.
9227 * Two are used now for a eCPRI matching:
9228 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9229 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9232 if (!ecpri_m->hdr.common.u32)
9234 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9235 /* Need to take the whole DW as the mask to fill the entry. */
9236 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9237 prog_sample_field_value_0);
9238 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9239 prog_sample_field_value_0);
9240 /* Already big endian (network order) in the header. */
9241 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9242 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9243 /* Sample#0, used for matching type, offset 0. */
9244 MLX5_SET(fte_match_set_misc4, misc4_m,
9245 prog_sample_field_id_0, samples[0]);
9246 /* It makes no sense to set the sample ID in the mask field. */
9247 MLX5_SET(fte_match_set_misc4, misc4_v,
9248 prog_sample_field_id_0, samples[0]);
9250 * Checking if message body part needs to be matched.
9251 * Some wildcard rules only matching type field should be supported.
9253 if (ecpri_m->hdr.dummy[0]) {
9254 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9255 switch (common.type) {
9256 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9257 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9258 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9259 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9260 prog_sample_field_value_1);
9261 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9262 prog_sample_field_value_1);
9263 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9264 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9265 ecpri_m->hdr.dummy[0];
9266 /* Sample#1, to match message body, offset 4. */
9267 MLX5_SET(fte_match_set_misc4, misc4_m,
9268 prog_sample_field_id_1, samples[1]);
9269 MLX5_SET(fte_match_set_misc4, misc4_v,
9270 prog_sample_field_id_1, samples[1]);
9273 /* Others, do not match any sample ID. */
9279 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9281 #define HEADER_IS_ZERO(match_criteria, headers) \
9282 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9283 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9286 * Calculate flow matcher enable bitmap.
9288 * @param match_criteria
9289 * Pointer to flow matcher criteria.
9292 * Bitmap of enabled fields.
9295 flow_dv_matcher_enable(uint32_t *match_criteria)
9297 uint8_t match_criteria_enable;
9299 match_criteria_enable =
9300 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9301 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9302 match_criteria_enable |=
9303 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9304 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9305 match_criteria_enable |=
9306 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9307 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9308 match_criteria_enable |=
9309 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9310 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9311 match_criteria_enable |=
9312 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9313 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9314 match_criteria_enable |=
9315 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9316 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9317 return match_criteria_enable;
9320 struct mlx5_hlist_entry *
9321 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9323 struct mlx5_dev_ctx_shared *sh = list->ctx;
9324 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9325 struct rte_eth_dev *dev = ctx->dev;
9326 struct mlx5_flow_tbl_data_entry *tbl_data;
9327 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9328 struct rte_flow_error *error = ctx->error;
9329 union mlx5_flow_tbl_key key = { .v64 = key64 };
9330 struct mlx5_flow_tbl_resource *tbl;
9335 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9337 rte_flow_error_set(error, ENOMEM,
9338 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9340 "cannot allocate flow table data entry");
9343 tbl_data->idx = idx;
9344 tbl_data->tunnel = tt_prm->tunnel;
9345 tbl_data->group_id = tt_prm->group_id;
9346 tbl_data->external = !!tt_prm->external;
9347 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9348 tbl_data->is_egress = !!key.is_egress;
9349 tbl_data->is_transfer = !!key.is_fdb;
9350 tbl_data->dummy = !!key.dummy;
9351 tbl_data->level = key.level;
9352 tbl_data->id = key.id;
9353 tbl = &tbl_data->tbl;
9355 return &tbl_data->entry;
9357 domain = sh->fdb_domain;
9358 else if (key.is_egress)
9359 domain = sh->tx_domain;
9361 domain = sh->rx_domain;
9362 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
9364 rte_flow_error_set(error, ENOMEM,
9365 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9366 NULL, "cannot create flow table object");
9367 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9370 if (key.level != 0) {
9371 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9372 (tbl->obj, &tbl_data->jump.action);
9374 rte_flow_error_set(error, ENOMEM,
9375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9377 "cannot create flow jump action");
9378 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9379 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9383 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_cache",
9384 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
9386 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9387 flow_dv_matcher_create_cb,
9388 flow_dv_matcher_match_cb,
9389 flow_dv_matcher_remove_cb);
9390 return &tbl_data->entry;
9394 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9395 struct mlx5_hlist_entry *entry, uint64_t key64,
9396 void *cb_ctx __rte_unused)
9398 struct mlx5_flow_tbl_data_entry *tbl_data =
9399 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9400 union mlx5_flow_tbl_key key = { .v64 = key64 };
9402 return tbl_data->level != key.level ||
9403 tbl_data->id != key.id ||
9404 tbl_data->dummy != key.dummy ||
9405 tbl_data->is_transfer != !!key.is_fdb ||
9406 tbl_data->is_egress != !!key.is_egress;
9412 * @param[in, out] dev
9413 * Pointer to rte_eth_dev structure.
9414 * @param[in] table_level
9415 * Table level to use.
9417 * Direction of the table.
9418 * @param[in] transfer
9419 * E-Switch or NIC flow.
9421 * Dummy entry for dv API.
9422 * @param[in] table_id
9425 * pointer to error structure.
9428 * Returns tables resource based on the index, NULL in case of failed.
9430 struct mlx5_flow_tbl_resource *
9431 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9432 uint32_t table_level, uint8_t egress,
9435 const struct mlx5_flow_tunnel *tunnel,
9436 uint32_t group_id, uint8_t dummy,
9438 struct rte_flow_error *error)
9440 struct mlx5_priv *priv = dev->data->dev_private;
9441 union mlx5_flow_tbl_key table_key = {
9443 .level = table_level,
9447 .is_fdb = !!transfer,
9448 .is_egress = !!egress,
9451 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9453 .group_id = group_id,
9454 .external = external,
9456 struct mlx5_flow_cb_ctx ctx = {
9461 struct mlx5_hlist_entry *entry;
9462 struct mlx5_flow_tbl_data_entry *tbl_data;
9464 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9466 rte_flow_error_set(error, ENOMEM,
9467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9468 "cannot get table");
9471 DRV_LOG(DEBUG, "table_level %u table_id %u "
9472 "tunnel %u group %u registered.",
9473 table_level, table_id,
9474 tunnel ? tunnel->tunnel_id : 0, group_id);
9475 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9476 return &tbl_data->tbl;
9480 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9481 struct mlx5_hlist_entry *entry)
9483 struct mlx5_dev_ctx_shared *sh = list->ctx;
9484 struct mlx5_flow_tbl_data_entry *tbl_data =
9485 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9487 MLX5_ASSERT(entry && sh);
9488 if (tbl_data->jump.action)
9489 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9490 if (tbl_data->tbl.obj)
9491 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9492 if (tbl_data->tunnel_offload && tbl_data->external) {
9493 struct mlx5_hlist_entry *he;
9494 struct mlx5_hlist *tunnel_grp_hash;
9495 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9496 union tunnel_tbl_key tunnel_key = {
9497 .tunnel_id = tbl_data->tunnel ?
9498 tbl_data->tunnel->tunnel_id : 0,
9499 .group = tbl_data->group_id
9501 uint32_t table_level = tbl_data->level;
9503 tunnel_grp_hash = tbl_data->tunnel ?
9504 tbl_data->tunnel->groups :
9506 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9508 mlx5_hlist_unregister(tunnel_grp_hash, he);
9510 "table_level %u id %u tunnel %u group %u released.",
9514 tbl_data->tunnel->tunnel_id : 0,
9515 tbl_data->group_id);
9517 mlx5_cache_list_destroy(&tbl_data->matchers);
9518 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9522 * Release a flow table.
9525 * Pointer to device shared structure.
9527 * Table resource to be released.
9530 * Returns 0 if table was released, else return 1;
9533 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9534 struct mlx5_flow_tbl_resource *tbl)
9536 struct mlx5_flow_tbl_data_entry *tbl_data =
9537 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9541 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9545 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9546 struct mlx5_cache_entry *entry, void *cb_ctx)
9548 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9549 struct mlx5_flow_dv_matcher *ref = ctx->data;
9550 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9553 return cur->crc != ref->crc ||
9554 cur->priority != ref->priority ||
9555 memcmp((const void *)cur->mask.buf,
9556 (const void *)ref->mask.buf, ref->mask.size);
9559 struct mlx5_cache_entry *
9560 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9561 struct mlx5_cache_entry *entry __rte_unused,
9564 struct mlx5_dev_ctx_shared *sh = list->ctx;
9565 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9566 struct mlx5_flow_dv_matcher *ref = ctx->data;
9567 struct mlx5_flow_dv_matcher *cache;
9568 struct mlx5dv_flow_matcher_attr dv_attr = {
9569 .type = IBV_FLOW_ATTR_NORMAL,
9570 .match_mask = (void *)&ref->mask,
9572 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9576 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9578 rte_flow_error_set(ctx->error, ENOMEM,
9579 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9580 "cannot create matcher");
9584 dv_attr.match_criteria_enable =
9585 flow_dv_matcher_enable(cache->mask.buf);
9586 dv_attr.priority = ref->priority;
9588 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9589 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9590 &cache->matcher_object);
9593 rte_flow_error_set(ctx->error, ENOMEM,
9594 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9595 "cannot create matcher");
9598 return &cache->entry;
9602 * Register the flow matcher.
9604 * @param[in, out] dev
9605 * Pointer to rte_eth_dev structure.
9606 * @param[in, out] matcher
9607 * Pointer to flow matcher.
9608 * @param[in, out] key
9609 * Pointer to flow table key.
9610 * @parm[in, out] dev_flow
9611 * Pointer to the dev_flow.
9613 * pointer to error structure.
9616 * 0 on success otherwise -errno and errno is set.
9619 flow_dv_matcher_register(struct rte_eth_dev *dev,
9620 struct mlx5_flow_dv_matcher *ref,
9621 union mlx5_flow_tbl_key *key,
9622 struct mlx5_flow *dev_flow,
9623 const struct mlx5_flow_tunnel *tunnel,
9625 struct rte_flow_error *error)
9627 struct mlx5_cache_entry *entry;
9628 struct mlx5_flow_dv_matcher *cache;
9629 struct mlx5_flow_tbl_resource *tbl;
9630 struct mlx5_flow_tbl_data_entry *tbl_data;
9631 struct mlx5_flow_cb_ctx ctx = {
9637 * tunnel offload API requires this registration for cases when
9638 * tunnel match rule was inserted before tunnel set rule.
9640 tbl = flow_dv_tbl_resource_get(dev, key->level,
9641 key->is_egress, key->is_fdb,
9642 dev_flow->external, tunnel,
9643 group_id, 0, key->id, error);
9645 return -rte_errno; /* No need to refill the error info */
9646 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9648 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9650 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9651 return rte_flow_error_set(error, ENOMEM,
9652 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9653 "cannot allocate ref memory");
9655 cache = container_of(entry, typeof(*cache), entry);
9656 dev_flow->handle->dvh.matcher = cache;
9660 struct mlx5_hlist_entry *
9661 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9663 struct mlx5_dev_ctx_shared *sh = list->ctx;
9664 struct rte_flow_error *error = ctx;
9665 struct mlx5_flow_dv_tag_resource *entry;
9669 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9671 rte_flow_error_set(error, ENOMEM,
9672 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9673 "cannot allocate resource memory");
9677 entry->tag_id = key;
9678 ret = mlx5_flow_os_create_flow_action_tag(key,
9681 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9682 rte_flow_error_set(error, ENOMEM,
9683 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9684 NULL, "cannot create action");
9687 return &entry->entry;
9691 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9692 struct mlx5_hlist_entry *entry, uint64_t key,
9693 void *cb_ctx __rte_unused)
9695 struct mlx5_flow_dv_tag_resource *tag =
9696 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9698 return key != tag->tag_id;
9702 * Find existing tag resource or create and register a new one.
9704 * @param dev[in, out]
9705 * Pointer to rte_eth_dev structure.
9706 * @param[in, out] tag_be24
9707 * Tag value in big endian then R-shift 8.
9708 * @parm[in, out] dev_flow
9709 * Pointer to the dev_flow.
9711 * pointer to error structure.
9714 * 0 on success otherwise -errno and errno is set.
9717 flow_dv_tag_resource_register
9718 (struct rte_eth_dev *dev,
9720 struct mlx5_flow *dev_flow,
9721 struct rte_flow_error *error)
9723 struct mlx5_priv *priv = dev->data->dev_private;
9724 struct mlx5_flow_dv_tag_resource *cache_resource;
9725 struct mlx5_hlist_entry *entry;
9727 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9729 cache_resource = container_of
9730 (entry, struct mlx5_flow_dv_tag_resource, entry);
9731 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9732 dev_flow->dv.tag_resource = cache_resource;
9739 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9740 struct mlx5_hlist_entry *entry)
9742 struct mlx5_dev_ctx_shared *sh = list->ctx;
9743 struct mlx5_flow_dv_tag_resource *tag =
9744 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9746 MLX5_ASSERT(tag && sh && tag->action);
9747 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9748 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9749 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9756 * Pointer to Ethernet device.
9761 * 1 while a reference on it exists, 0 when freed.
9764 flow_dv_tag_release(struct rte_eth_dev *dev,
9767 struct mlx5_priv *priv = dev->data->dev_private;
9768 struct mlx5_flow_dv_tag_resource *tag;
9770 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9773 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9774 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9775 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9779 * Translate port ID action to vport.
9782 * Pointer to rte_eth_dev structure.
9784 * Pointer to the port ID action.
9785 * @param[out] dst_port_id
9786 * The target port ID.
9788 * Pointer to the error structure.
9791 * 0 on success, a negative errno value otherwise and rte_errno is set.
9794 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9795 const struct rte_flow_action *action,
9796 uint32_t *dst_port_id,
9797 struct rte_flow_error *error)
9800 struct mlx5_priv *priv;
9801 const struct rte_flow_action_port_id *conf =
9802 (const struct rte_flow_action_port_id *)action->conf;
9804 port = conf->original ? dev->data->port_id : conf->id;
9805 priv = mlx5_port_to_eswitch_info(port, false);
9807 return rte_flow_error_set(error, -rte_errno,
9808 RTE_FLOW_ERROR_TYPE_ACTION,
9810 "No eswitch info was found for port");
9811 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9813 * This parameter is transferred to
9814 * mlx5dv_dr_action_create_dest_ib_port().
9816 *dst_port_id = priv->dev_port;
9819 * Legacy mode, no LAG configurations is supported.
9820 * This parameter is transferred to
9821 * mlx5dv_dr_action_create_dest_vport().
9823 *dst_port_id = priv->vport_id;
9829 * Create a counter with aging configuration.
9832 * Pointer to rte_eth_dev structure.
9834 * Pointer to the counter action configuration.
9836 * Pointer to the aging action configuration.
9839 * Index to flow counter on success, 0 otherwise.
9842 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9843 struct mlx5_flow *dev_flow,
9844 const struct rte_flow_action_count *count,
9845 const struct rte_flow_action_age *age)
9848 struct mlx5_age_param *age_param;
9850 if (count && count->shared)
9851 counter = flow_dv_counter_get_shared(dev, count->id);
9853 counter = flow_dv_counter_alloc(dev, !!age);
9854 if (!counter || age == NULL)
9856 age_param = flow_dv_counter_idx_get_age(dev, counter);
9857 age_param->context = age->context ? age->context :
9858 (void *)(uintptr_t)(dev_flow->flow_idx);
9859 age_param->timeout = age->timeout;
9860 age_param->port_id = dev->data->port_id;
9861 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9862 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9867 * Add Tx queue matcher
9870 * Pointer to the dev struct.
9871 * @param[in, out] matcher
9873 * @param[in, out] key
9874 * Flow matcher value.
9876 * Flow pattern to translate.
9878 * Item is inner pattern.
9881 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9882 void *matcher, void *key,
9883 const struct rte_flow_item *item)
9885 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9886 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9888 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9890 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9891 struct mlx5_txq_ctrl *txq;
9895 queue_m = (const void *)item->mask;
9898 queue_v = (const void *)item->spec;
9901 txq = mlx5_txq_get(dev, queue_v->queue);
9904 queue = txq->obj->sq->id;
9905 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9906 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9907 queue & queue_m->queue);
9908 mlx5_txq_release(dev, queue_v->queue);
9912 * Set the hash fields according to the @p flow information.
9914 * @param[in] dev_flow
9915 * Pointer to the mlx5_flow.
9916 * @param[in] rss_desc
9917 * Pointer to the mlx5_flow_rss_desc.
9920 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9921 struct mlx5_flow_rss_desc *rss_desc)
9923 uint64_t items = dev_flow->handle->layers;
9925 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9927 dev_flow->hash_fields = 0;
9928 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9929 if (rss_desc->level >= 2) {
9930 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9934 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9935 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9936 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9937 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9938 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9939 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9940 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9942 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9944 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9945 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9946 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9947 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9948 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9949 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9950 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9952 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9955 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9956 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9957 if (rss_types & ETH_RSS_UDP) {
9958 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9959 dev_flow->hash_fields |=
9960 IBV_RX_HASH_SRC_PORT_UDP;
9961 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9962 dev_flow->hash_fields |=
9963 IBV_RX_HASH_DST_PORT_UDP;
9965 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9967 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9968 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9969 if (rss_types & ETH_RSS_TCP) {
9970 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9971 dev_flow->hash_fields |=
9972 IBV_RX_HASH_SRC_PORT_TCP;
9973 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9974 dev_flow->hash_fields |=
9975 IBV_RX_HASH_DST_PORT_TCP;
9977 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9983 * Prepare an Rx Hash queue.
9986 * Pointer to Ethernet device.
9987 * @param[in] dev_flow
9988 * Pointer to the mlx5_flow.
9989 * @param[in] rss_desc
9990 * Pointer to the mlx5_flow_rss_desc.
9991 * @param[out] hrxq_idx
9992 * Hash Rx queue index.
9995 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9997 static struct mlx5_hrxq *
9998 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9999 struct mlx5_flow *dev_flow,
10000 struct mlx5_flow_rss_desc *rss_desc,
10001 uint32_t *hrxq_idx)
10003 struct mlx5_priv *priv = dev->data->dev_private;
10004 struct mlx5_flow_handle *dh = dev_flow->handle;
10005 struct mlx5_hrxq *hrxq;
10007 MLX5_ASSERT(rss_desc->queue_num);
10008 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10009 rss_desc->hash_fields = dev_flow->hash_fields;
10010 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10011 rss_desc->shared_rss = 0;
10012 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10015 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10021 * Release sample sub action resource.
10023 * @param[in, out] dev
10024 * Pointer to rte_eth_dev structure.
10025 * @param[in] act_res
10026 * Pointer to sample sub action resource.
10029 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10030 struct mlx5_flow_sub_actions_idx *act_res)
10032 if (act_res->rix_hrxq) {
10033 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10034 act_res->rix_hrxq = 0;
10036 if (act_res->rix_encap_decap) {
10037 flow_dv_encap_decap_resource_release(dev,
10038 act_res->rix_encap_decap);
10039 act_res->rix_encap_decap = 0;
10041 if (act_res->rix_port_id_action) {
10042 flow_dv_port_id_action_resource_release(dev,
10043 act_res->rix_port_id_action);
10044 act_res->rix_port_id_action = 0;
10046 if (act_res->rix_tag) {
10047 flow_dv_tag_release(dev, act_res->rix_tag);
10048 act_res->rix_tag = 0;
10050 if (act_res->rix_jump) {
10051 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10052 act_res->rix_jump = 0;
10057 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10058 struct mlx5_cache_entry *entry, void *cb_ctx)
10060 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10061 struct rte_eth_dev *dev = ctx->dev;
10062 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10063 struct mlx5_flow_dv_sample_resource *cache_resource =
10064 container_of(entry, typeof(*cache_resource), entry);
10066 if (resource->ratio == cache_resource->ratio &&
10067 resource->ft_type == cache_resource->ft_type &&
10068 resource->ft_id == cache_resource->ft_id &&
10069 resource->set_action == cache_resource->set_action &&
10070 !memcmp((void *)&resource->sample_act,
10071 (void *)&cache_resource->sample_act,
10072 sizeof(struct mlx5_flow_sub_actions_list))) {
10074 * Existing sample action should release the prepared
10075 * sub-actions reference counter.
10077 flow_dv_sample_sub_actions_release(dev,
10078 &resource->sample_idx);
10084 struct mlx5_cache_entry *
10085 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10086 struct mlx5_cache_entry *entry __rte_unused,
10089 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10090 struct rte_eth_dev *dev = ctx->dev;
10091 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10092 void **sample_dv_actions = resource->sub_actions;
10093 struct mlx5_flow_dv_sample_resource *cache_resource;
10094 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10095 struct mlx5_priv *priv = dev->data->dev_private;
10096 struct mlx5_dev_ctx_shared *sh = priv->sh;
10097 struct mlx5_flow_tbl_resource *tbl;
10099 const uint32_t next_ft_step = 1;
10100 uint32_t next_ft_id = resource->ft_id + next_ft_step;
10101 uint8_t is_egress = 0;
10102 uint8_t is_transfer = 0;
10103 struct rte_flow_error *error = ctx->error;
10105 /* Register new sample resource. */
10106 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10107 if (!cache_resource) {
10108 rte_flow_error_set(error, ENOMEM,
10109 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10111 "cannot allocate resource memory");
10114 *cache_resource = *resource;
10115 /* Create normal path table level */
10116 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10118 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10120 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10121 is_egress, is_transfer,
10122 true, NULL, 0, 0, 0, error);
10124 rte_flow_error_set(error, ENOMEM,
10125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10127 "fail to create normal path table "
10131 cache_resource->normal_path_tbl = tbl;
10132 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10133 if (!sh->default_miss_action) {
10134 rte_flow_error_set(error, ENOMEM,
10135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10137 "default miss action was not "
10141 sample_dv_actions[resource->sample_act.actions_num++] =
10142 sh->default_miss_action;
10144 /* Create a DR sample action */
10145 sampler_attr.sample_ratio = cache_resource->ratio;
10146 sampler_attr.default_next_table = tbl->obj;
10147 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10148 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10149 &sample_dv_actions[0];
10150 sampler_attr.action = cache_resource->set_action;
10151 if (mlx5_os_flow_dr_create_flow_action_sampler
10152 (&sampler_attr, &cache_resource->verbs_action)) {
10153 rte_flow_error_set(error, ENOMEM,
10154 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10155 NULL, "cannot create sample action");
10158 cache_resource->idx = idx;
10159 cache_resource->dev = dev;
10160 return &cache_resource->entry;
10162 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10163 flow_dv_sample_sub_actions_release(dev,
10164 &cache_resource->sample_idx);
10165 if (cache_resource->normal_path_tbl)
10166 flow_dv_tbl_resource_release(MLX5_SH(dev),
10167 cache_resource->normal_path_tbl);
10168 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10174 * Find existing sample resource or create and register a new one.
10176 * @param[in, out] dev
10177 * Pointer to rte_eth_dev structure.
10178 * @param[in] resource
10179 * Pointer to sample resource.
10180 * @parm[in, out] dev_flow
10181 * Pointer to the dev_flow.
10182 * @param[out] error
10183 * pointer to error structure.
10186 * 0 on success otherwise -errno and errno is set.
10189 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10190 struct mlx5_flow_dv_sample_resource *resource,
10191 struct mlx5_flow *dev_flow,
10192 struct rte_flow_error *error)
10194 struct mlx5_flow_dv_sample_resource *cache_resource;
10195 struct mlx5_cache_entry *entry;
10196 struct mlx5_priv *priv = dev->data->dev_private;
10197 struct mlx5_flow_cb_ctx ctx = {
10203 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10206 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10207 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10208 dev_flow->dv.sample_res = cache_resource;
10213 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10214 struct mlx5_cache_entry *entry, void *cb_ctx)
10216 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10217 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10218 struct rte_eth_dev *dev = ctx->dev;
10219 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10220 container_of(entry, typeof(*cache_resource), entry);
10223 if (resource->num_of_dest == cache_resource->num_of_dest &&
10224 resource->ft_type == cache_resource->ft_type &&
10225 !memcmp((void *)cache_resource->sample_act,
10226 (void *)resource->sample_act,
10227 (resource->num_of_dest *
10228 sizeof(struct mlx5_flow_sub_actions_list)))) {
10230 * Existing sample action should release the prepared
10231 * sub-actions reference counter.
10233 for (idx = 0; idx < resource->num_of_dest; idx++)
10234 flow_dv_sample_sub_actions_release(dev,
10235 &resource->sample_idx[idx]);
10241 struct mlx5_cache_entry *
10242 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10243 struct mlx5_cache_entry *entry __rte_unused,
10246 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10247 struct rte_eth_dev *dev = ctx->dev;
10248 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10249 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10250 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10251 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10252 struct mlx5_priv *priv = dev->data->dev_private;
10253 struct mlx5_dev_ctx_shared *sh = priv->sh;
10254 struct mlx5_flow_sub_actions_list *sample_act;
10255 struct mlx5dv_dr_domain *domain;
10256 uint32_t idx = 0, res_idx = 0;
10257 struct rte_flow_error *error = ctx->error;
10258 uint64_t action_flags;
10261 /* Register new destination array resource. */
10262 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10264 if (!cache_resource) {
10265 rte_flow_error_set(error, ENOMEM,
10266 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10268 "cannot allocate resource memory");
10271 *cache_resource = *resource;
10272 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10273 domain = sh->fdb_domain;
10274 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10275 domain = sh->rx_domain;
10277 domain = sh->tx_domain;
10278 for (idx = 0; idx < resource->num_of_dest; idx++) {
10279 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10280 mlx5_malloc(MLX5_MEM_ZERO,
10281 sizeof(struct mlx5dv_dr_action_dest_attr),
10283 if (!dest_attr[idx]) {
10284 rte_flow_error_set(error, ENOMEM,
10285 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10287 "cannot allocate resource memory");
10290 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10291 sample_act = &resource->sample_act[idx];
10292 action_flags = sample_act->action_flags;
10293 switch (action_flags) {
10294 case MLX5_FLOW_ACTION_QUEUE:
10295 dest_attr[idx]->dest = sample_act->dr_queue_action;
10297 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10298 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10299 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10300 dest_attr[idx]->dest_reformat->reformat =
10301 sample_act->dr_encap_action;
10302 dest_attr[idx]->dest_reformat->dest =
10303 sample_act->dr_port_id_action;
10305 case MLX5_FLOW_ACTION_PORT_ID:
10306 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10308 case MLX5_FLOW_ACTION_JUMP:
10309 dest_attr[idx]->dest = sample_act->dr_jump_action;
10312 rte_flow_error_set(error, EINVAL,
10313 RTE_FLOW_ERROR_TYPE_ACTION,
10315 "unsupported actions type");
10319 /* create a dest array actioin */
10320 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10322 cache_resource->num_of_dest,
10324 &cache_resource->action);
10326 rte_flow_error_set(error, ENOMEM,
10327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10329 "cannot create destination array action");
10332 cache_resource->idx = res_idx;
10333 cache_resource->dev = dev;
10334 for (idx = 0; idx < resource->num_of_dest; idx++)
10335 mlx5_free(dest_attr[idx]);
10336 return &cache_resource->entry;
10338 for (idx = 0; idx < resource->num_of_dest; idx++) {
10339 flow_dv_sample_sub_actions_release(dev,
10340 &cache_resource->sample_idx[idx]);
10341 if (dest_attr[idx])
10342 mlx5_free(dest_attr[idx]);
10345 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10350 * Find existing destination array resource or create and register a new one.
10352 * @param[in, out] dev
10353 * Pointer to rte_eth_dev structure.
10354 * @param[in] resource
10355 * Pointer to destination array resource.
10356 * @parm[in, out] dev_flow
10357 * Pointer to the dev_flow.
10358 * @param[out] error
10359 * pointer to error structure.
10362 * 0 on success otherwise -errno and errno is set.
10365 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10366 struct mlx5_flow_dv_dest_array_resource *resource,
10367 struct mlx5_flow *dev_flow,
10368 struct rte_flow_error *error)
10370 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10371 struct mlx5_priv *priv = dev->data->dev_private;
10372 struct mlx5_cache_entry *entry;
10373 struct mlx5_flow_cb_ctx ctx = {
10379 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10382 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10383 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10384 dev_flow->dv.dest_array_res = cache_resource;
10389 * Convert Sample action to DV specification.
10392 * Pointer to rte_eth_dev structure.
10393 * @param[in] action
10394 * Pointer to sample action structure.
10395 * @param[in, out] dev_flow
10396 * Pointer to the mlx5_flow.
10398 * Pointer to the flow attributes.
10399 * @param[in, out] num_of_dest
10400 * Pointer to the num of destination.
10401 * @param[in, out] sample_actions
10402 * Pointer to sample actions list.
10403 * @param[in, out] res
10404 * Pointer to sample resource.
10405 * @param[out] error
10406 * Pointer to the error structure.
10409 * 0 on success, a negative errno value otherwise and rte_errno is set.
10412 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10413 const struct rte_flow_action_sample *action,
10414 struct mlx5_flow *dev_flow,
10415 const struct rte_flow_attr *attr,
10416 uint32_t *num_of_dest,
10417 void **sample_actions,
10418 struct mlx5_flow_dv_sample_resource *res,
10419 struct rte_flow_error *error)
10421 struct mlx5_priv *priv = dev->data->dev_private;
10422 const struct rte_flow_action *sub_actions;
10423 struct mlx5_flow_sub_actions_list *sample_act;
10424 struct mlx5_flow_sub_actions_idx *sample_idx;
10425 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10426 struct rte_flow *flow = dev_flow->flow;
10427 struct mlx5_flow_rss_desc *rss_desc;
10428 uint64_t action_flags = 0;
10431 rss_desc = &wks->rss_desc;
10432 sample_act = &res->sample_act;
10433 sample_idx = &res->sample_idx;
10434 res->ratio = action->ratio;
10435 sub_actions = action->actions;
10436 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10437 int type = sub_actions->type;
10438 uint32_t pre_rix = 0;
10441 case RTE_FLOW_ACTION_TYPE_QUEUE:
10443 const struct rte_flow_action_queue *queue;
10444 struct mlx5_hrxq *hrxq;
10447 queue = sub_actions->conf;
10448 rss_desc->queue_num = 1;
10449 rss_desc->queue[0] = queue->index;
10450 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10451 rss_desc, &hrxq_idx);
10453 return rte_flow_error_set
10455 RTE_FLOW_ERROR_TYPE_ACTION,
10457 "cannot create fate queue");
10458 sample_act->dr_queue_action = hrxq->action;
10459 sample_idx->rix_hrxq = hrxq_idx;
10460 sample_actions[sample_act->actions_num++] =
10463 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10464 if (action_flags & MLX5_FLOW_ACTION_MARK)
10465 dev_flow->handle->rix_hrxq = hrxq_idx;
10466 dev_flow->handle->fate_action =
10467 MLX5_FLOW_FATE_QUEUE;
10470 case RTE_FLOW_ACTION_TYPE_RSS:
10472 struct mlx5_hrxq *hrxq;
10474 const struct rte_flow_action_rss *rss;
10475 const uint8_t *rss_key;
10477 rss = sub_actions->conf;
10478 memcpy(rss_desc->queue, rss->queue,
10479 rss->queue_num * sizeof(uint16_t));
10480 rss_desc->queue_num = rss->queue_num;
10481 /* NULL RSS key indicates default RSS key. */
10482 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10483 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10485 * rss->level and rss.types should be set in advance
10486 * when expanding items for RSS.
10488 flow_dv_hashfields_set(dev_flow, rss_desc);
10489 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10490 rss_desc, &hrxq_idx);
10492 return rte_flow_error_set
10494 RTE_FLOW_ERROR_TYPE_ACTION,
10496 "cannot create fate queue");
10497 sample_act->dr_queue_action = hrxq->action;
10498 sample_idx->rix_hrxq = hrxq_idx;
10499 sample_actions[sample_act->actions_num++] =
10502 action_flags |= MLX5_FLOW_ACTION_RSS;
10503 if (action_flags & MLX5_FLOW_ACTION_MARK)
10504 dev_flow->handle->rix_hrxq = hrxq_idx;
10505 dev_flow->handle->fate_action =
10506 MLX5_FLOW_FATE_QUEUE;
10509 case RTE_FLOW_ACTION_TYPE_MARK:
10511 uint32_t tag_be = mlx5_flow_mark_set
10512 (((const struct rte_flow_action_mark *)
10513 (sub_actions->conf))->id);
10515 dev_flow->handle->mark = 1;
10516 pre_rix = dev_flow->handle->dvh.rix_tag;
10517 /* Save the mark resource before sample */
10518 pre_r = dev_flow->dv.tag_resource;
10519 if (flow_dv_tag_resource_register(dev, tag_be,
10522 MLX5_ASSERT(dev_flow->dv.tag_resource);
10523 sample_act->dr_tag_action =
10524 dev_flow->dv.tag_resource->action;
10525 sample_idx->rix_tag =
10526 dev_flow->handle->dvh.rix_tag;
10527 sample_actions[sample_act->actions_num++] =
10528 sample_act->dr_tag_action;
10529 /* Recover the mark resource after sample */
10530 dev_flow->dv.tag_resource = pre_r;
10531 dev_flow->handle->dvh.rix_tag = pre_rix;
10532 action_flags |= MLX5_FLOW_ACTION_MARK;
10535 case RTE_FLOW_ACTION_TYPE_COUNT:
10537 if (!flow->counter) {
10539 flow_dv_translate_create_counter(dev,
10540 dev_flow, sub_actions->conf,
10542 if (!flow->counter)
10543 return rte_flow_error_set
10545 RTE_FLOW_ERROR_TYPE_ACTION,
10547 "cannot create counter"
10550 sample_act->dr_cnt_action =
10551 (flow_dv_counter_get_by_idx(dev,
10552 flow->counter, NULL))->action;
10553 sample_actions[sample_act->actions_num++] =
10554 sample_act->dr_cnt_action;
10555 action_flags |= MLX5_FLOW_ACTION_COUNT;
10558 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10560 struct mlx5_flow_dv_port_id_action_resource
10562 uint32_t port_id = 0;
10564 memset(&port_id_resource, 0, sizeof(port_id_resource));
10565 /* Save the port id resource before sample */
10566 pre_rix = dev_flow->handle->rix_port_id_action;
10567 pre_r = dev_flow->dv.port_id_action;
10568 if (flow_dv_translate_action_port_id(dev, sub_actions,
10571 port_id_resource.port_id = port_id;
10572 if (flow_dv_port_id_action_resource_register
10573 (dev, &port_id_resource, dev_flow, error))
10575 sample_act->dr_port_id_action =
10576 dev_flow->dv.port_id_action->action;
10577 sample_idx->rix_port_id_action =
10578 dev_flow->handle->rix_port_id_action;
10579 sample_actions[sample_act->actions_num++] =
10580 sample_act->dr_port_id_action;
10581 /* Recover the port id resource after sample */
10582 dev_flow->dv.port_id_action = pre_r;
10583 dev_flow->handle->rix_port_id_action = pre_rix;
10585 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10588 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10589 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10590 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10591 /* Save the encap resource before sample */
10592 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10593 pre_r = dev_flow->dv.encap_decap;
10594 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10599 sample_act->dr_encap_action =
10600 dev_flow->dv.encap_decap->action;
10601 sample_idx->rix_encap_decap =
10602 dev_flow->handle->dvh.rix_encap_decap;
10603 sample_actions[sample_act->actions_num++] =
10604 sample_act->dr_encap_action;
10605 /* Recover the encap resource after sample */
10606 dev_flow->dv.encap_decap = pre_r;
10607 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10608 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10611 return rte_flow_error_set(error, EINVAL,
10612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10614 "Not support for sampler action");
10617 sample_act->action_flags = action_flags;
10618 res->ft_id = dev_flow->dv.group;
10619 if (attr->transfer) {
10621 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10622 uint64_t set_action;
10623 } action_ctx = { .set_action = 0 };
10625 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10626 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10627 MLX5_MODIFICATION_TYPE_SET);
10628 MLX5_SET(set_action_in, action_ctx.action_in, field,
10629 MLX5_MODI_META_REG_C_0);
10630 MLX5_SET(set_action_in, action_ctx.action_in, data,
10631 priv->vport_meta_tag);
10632 res->set_action = action_ctx.set_action;
10633 } else if (attr->ingress) {
10634 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10636 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10642 * Convert Sample action to DV specification.
10645 * Pointer to rte_eth_dev structure.
10646 * @param[in, out] dev_flow
10647 * Pointer to the mlx5_flow.
10648 * @param[in] num_of_dest
10649 * The num of destination.
10650 * @param[in, out] res
10651 * Pointer to sample resource.
10652 * @param[in, out] mdest_res
10653 * Pointer to destination array resource.
10654 * @param[in] sample_actions
10655 * Pointer to sample path actions list.
10656 * @param[in] action_flags
10657 * Holds the actions detected until now.
10658 * @param[out] error
10659 * Pointer to the error structure.
10662 * 0 on success, a negative errno value otherwise and rte_errno is set.
10665 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10666 struct mlx5_flow *dev_flow,
10667 uint32_t num_of_dest,
10668 struct mlx5_flow_dv_sample_resource *res,
10669 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10670 void **sample_actions,
10671 uint64_t action_flags,
10672 struct rte_flow_error *error)
10674 /* update normal path action resource into last index of array */
10675 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10676 struct mlx5_flow_sub_actions_list *sample_act =
10677 &mdest_res->sample_act[dest_index];
10678 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10679 struct mlx5_flow_rss_desc *rss_desc;
10680 uint32_t normal_idx = 0;
10681 struct mlx5_hrxq *hrxq;
10685 rss_desc = &wks->rss_desc;
10686 if (num_of_dest > 1) {
10687 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10688 /* Handle QP action for mirroring */
10689 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10690 rss_desc, &hrxq_idx);
10692 return rte_flow_error_set
10694 RTE_FLOW_ERROR_TYPE_ACTION,
10696 "cannot create rx queue");
10698 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10699 sample_act->dr_queue_action = hrxq->action;
10700 if (action_flags & MLX5_FLOW_ACTION_MARK)
10701 dev_flow->handle->rix_hrxq = hrxq_idx;
10702 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10704 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10706 mdest_res->sample_idx[dest_index].rix_encap_decap =
10707 dev_flow->handle->dvh.rix_encap_decap;
10708 sample_act->dr_encap_action =
10709 dev_flow->dv.encap_decap->action;
10710 dev_flow->handle->dvh.rix_encap_decap = 0;
10712 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10714 mdest_res->sample_idx[dest_index].rix_port_id_action =
10715 dev_flow->handle->rix_port_id_action;
10716 sample_act->dr_port_id_action =
10717 dev_flow->dv.port_id_action->action;
10718 dev_flow->handle->rix_port_id_action = 0;
10720 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10722 mdest_res->sample_idx[dest_index].rix_jump =
10723 dev_flow->handle->rix_jump;
10724 sample_act->dr_jump_action =
10725 dev_flow->dv.jump->action;
10726 dev_flow->handle->rix_jump = 0;
10728 sample_act->actions_num = normal_idx;
10729 /* update sample action resource into first index of array */
10730 mdest_res->ft_type = res->ft_type;
10731 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10732 sizeof(struct mlx5_flow_sub_actions_idx));
10733 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10734 sizeof(struct mlx5_flow_sub_actions_list));
10735 mdest_res->num_of_dest = num_of_dest;
10736 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10738 return rte_flow_error_set(error, EINVAL,
10739 RTE_FLOW_ERROR_TYPE_ACTION,
10740 NULL, "can't create sample "
10743 res->sub_actions = sample_actions;
10744 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10745 return rte_flow_error_set(error, EINVAL,
10746 RTE_FLOW_ERROR_TYPE_ACTION,
10748 "can't create sample action");
10754 * Remove an ASO age action from age actions list.
10757 * Pointer to the Ethernet device structure.
10759 * Pointer to the aso age action handler.
10762 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10763 struct mlx5_aso_age_action *age)
10765 struct mlx5_age_info *age_info;
10766 struct mlx5_age_param *age_param = &age->age_params;
10767 struct mlx5_priv *priv = dev->data->dev_private;
10768 uint16_t expected = AGE_CANDIDATE;
10770 age_info = GET_PORT_AGE_INFO(priv);
10771 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10772 AGE_FREE, false, __ATOMIC_RELAXED,
10773 __ATOMIC_RELAXED)) {
10775 * We need the lock even it is age timeout,
10776 * since age action may still in process.
10778 rte_spinlock_lock(&age_info->aged_sl);
10779 LIST_REMOVE(age, next);
10780 rte_spinlock_unlock(&age_info->aged_sl);
10781 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10786 * Release an ASO age action.
10789 * Pointer to the Ethernet device structure.
10790 * @param[in] age_idx
10791 * Index of ASO age action to release.
10793 * True if the release operation is during flow destroy operation.
10794 * False if the release operation is during action destroy operation.
10797 * 0 when age action was removed, otherwise the number of references.
10800 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10802 struct mlx5_priv *priv = dev->data->dev_private;
10803 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10804 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10805 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10808 flow_dv_aso_age_remove_from_age(dev, age);
10809 rte_spinlock_lock(&mng->free_sl);
10810 LIST_INSERT_HEAD(&mng->free, age, next);
10811 rte_spinlock_unlock(&mng->free_sl);
10817 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10820 * Pointer to the Ethernet device structure.
10823 * 0 on success, otherwise negative errno value and rte_errno is set.
10826 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10828 struct mlx5_priv *priv = dev->data->dev_private;
10829 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10830 void *old_pools = mng->pools;
10831 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10832 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10833 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10836 rte_errno = ENOMEM;
10840 memcpy(pools, old_pools,
10841 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10842 mlx5_free(old_pools);
10844 /* First ASO flow hit allocation - starting ASO data-path. */
10845 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
10853 mng->pools = pools;
10858 * Create and initialize a new ASO aging pool.
10861 * Pointer to the Ethernet device structure.
10862 * @param[out] age_free
10863 * Where to put the pointer of a new age action.
10866 * The age actions pool pointer and @p age_free is set on success,
10867 * NULL otherwise and rte_errno is set.
10869 static struct mlx5_aso_age_pool *
10870 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10871 struct mlx5_aso_age_action **age_free)
10873 struct mlx5_priv *priv = dev->data->dev_private;
10874 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10875 struct mlx5_aso_age_pool *pool = NULL;
10876 struct mlx5_devx_obj *obj = NULL;
10879 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10882 rte_errno = ENODATA;
10883 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10886 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10888 claim_zero(mlx5_devx_cmd_destroy(obj));
10889 rte_errno = ENOMEM;
10892 pool->flow_hit_aso_obj = obj;
10893 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10894 rte_spinlock_lock(&mng->resize_sl);
10895 pool->index = mng->next;
10896 /* Resize pools array if there is no room for the new pool in it. */
10897 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10898 claim_zero(mlx5_devx_cmd_destroy(obj));
10900 rte_spinlock_unlock(&mng->resize_sl);
10903 mng->pools[pool->index] = pool;
10905 rte_spinlock_unlock(&mng->resize_sl);
10906 /* Assign the first action in the new pool, the rest go to free list. */
10907 *age_free = &pool->actions[0];
10908 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10909 pool->actions[i].offset = i;
10910 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10916 * Allocate a ASO aging bit.
10919 * Pointer to the Ethernet device structure.
10920 * @param[out] error
10921 * Pointer to the error structure.
10924 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10927 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10929 struct mlx5_priv *priv = dev->data->dev_private;
10930 const struct mlx5_aso_age_pool *pool;
10931 struct mlx5_aso_age_action *age_free = NULL;
10932 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10935 /* Try to get the next free age action bit. */
10936 rte_spinlock_lock(&mng->free_sl);
10937 age_free = LIST_FIRST(&mng->free);
10939 LIST_REMOVE(age_free, next);
10940 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10941 rte_spinlock_unlock(&mng->free_sl);
10942 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10943 NULL, "failed to create ASO age pool");
10944 return 0; /* 0 is an error. */
10946 rte_spinlock_unlock(&mng->free_sl);
10947 pool = container_of
10948 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10949 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10951 if (!age_free->dr_action) {
10952 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10956 rte_flow_error_set(error, rte_errno,
10957 RTE_FLOW_ERROR_TYPE_ACTION,
10958 NULL, "failed to get reg_c "
10959 "for ASO flow hit");
10960 return 0; /* 0 is an error. */
10962 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10963 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10964 (priv->sh->rx_domain,
10965 pool->flow_hit_aso_obj->obj, age_free->offset,
10966 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10967 (reg_c - REG_C_0));
10968 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10969 if (!age_free->dr_action) {
10971 rte_spinlock_lock(&mng->free_sl);
10972 LIST_INSERT_HEAD(&mng->free, age_free, next);
10973 rte_spinlock_unlock(&mng->free_sl);
10974 rte_flow_error_set(error, rte_errno,
10975 RTE_FLOW_ERROR_TYPE_ACTION,
10976 NULL, "failed to create ASO "
10977 "flow hit action");
10978 return 0; /* 0 is an error. */
10981 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10982 return pool->index | ((age_free->offset + 1) << 16);
10986 * Create a age action using ASO mechanism.
10989 * Pointer to rte_eth_dev structure.
10991 * Pointer to the aging action configuration.
10992 * @param[out] error
10993 * Pointer to the error structure.
10996 * Index to flow counter on success, 0 otherwise.
10999 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
11000 const struct rte_flow_action_age *age,
11001 struct rte_flow_error *error)
11003 uint32_t age_idx = 0;
11004 struct mlx5_aso_age_action *aso_age;
11006 age_idx = flow_dv_aso_age_alloc(dev, error);
11009 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11010 aso_age->age_params.context = age->context;
11011 aso_age->age_params.timeout = age->timeout;
11012 aso_age->age_params.port_id = dev->data->port_id;
11013 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11015 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11021 * Fill the flow with DV spec, lock free
11022 * (mutex should be acquired by caller).
11025 * Pointer to rte_eth_dev structure.
11026 * @param[in, out] dev_flow
11027 * Pointer to the sub flow.
11029 * Pointer to the flow attributes.
11031 * Pointer to the list of items.
11032 * @param[in] actions
11033 * Pointer to the list of actions.
11034 * @param[out] error
11035 * Pointer to the error structure.
11038 * 0 on success, a negative errno value otherwise and rte_errno is set.
11041 flow_dv_translate(struct rte_eth_dev *dev,
11042 struct mlx5_flow *dev_flow,
11043 const struct rte_flow_attr *attr,
11044 const struct rte_flow_item items[],
11045 const struct rte_flow_action actions[],
11046 struct rte_flow_error *error)
11048 struct mlx5_priv *priv = dev->data->dev_private;
11049 struct mlx5_dev_config *dev_conf = &priv->config;
11050 struct rte_flow *flow = dev_flow->flow;
11051 struct mlx5_flow_handle *handle = dev_flow->handle;
11052 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11053 struct mlx5_flow_rss_desc *rss_desc;
11054 uint64_t item_flags = 0;
11055 uint64_t last_item = 0;
11056 uint64_t action_flags = 0;
11057 struct mlx5_flow_dv_matcher matcher = {
11059 .size = sizeof(matcher.mask.buf) -
11060 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11064 bool actions_end = false;
11066 struct mlx5_flow_dv_modify_hdr_resource res;
11067 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11068 sizeof(struct mlx5_modification_cmd) *
11069 (MLX5_MAX_MODIFY_NUM + 1)];
11071 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11072 const struct rte_flow_action_count *count = NULL;
11073 const struct rte_flow_action_age *age = NULL;
11074 union flow_dv_attr flow_attr = { .attr = 0 };
11076 union mlx5_flow_tbl_key tbl_key;
11077 uint32_t modify_action_position = UINT32_MAX;
11078 void *match_mask = matcher.mask.buf;
11079 void *match_value = dev_flow->dv.value.buf;
11080 uint8_t next_protocol = 0xff;
11081 struct rte_vlan_hdr vlan = { 0 };
11082 struct mlx5_flow_dv_dest_array_resource mdest_res;
11083 struct mlx5_flow_dv_sample_resource sample_res;
11084 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11085 const struct rte_flow_action_sample *sample = NULL;
11086 struct mlx5_flow_sub_actions_list *sample_act;
11087 uint32_t sample_act_pos = UINT32_MAX;
11088 uint32_t num_of_dest = 0;
11089 int tmp_actions_n = 0;
11092 const struct mlx5_flow_tunnel *tunnel;
11093 struct flow_grp_info grp_info = {
11094 .external = !!dev_flow->external,
11095 .transfer = !!attr->transfer,
11096 .fdb_def_rule = !!priv->fdb_def_rule,
11097 .skip_scale = dev_flow->skip_scale &
11098 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11102 return rte_flow_error_set(error, ENOMEM,
11103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11105 "failed to push flow workspace");
11106 rss_desc = &wks->rss_desc;
11107 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11108 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11109 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11110 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11111 /* update normal path action resource into last index of array */
11112 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11113 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11114 flow_items_to_tunnel(items) :
11115 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11116 flow_actions_to_tunnel(actions) :
11117 dev_flow->tunnel ? dev_flow->tunnel : NULL;
11118 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11119 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11120 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11121 (dev, tunnel, attr, items, actions);
11122 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11126 dev_flow->dv.group = table;
11127 if (attr->transfer)
11128 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11129 /* number of actions must be set to 0 in case of dirty stack. */
11130 mhdr_res->actions_num = 0;
11131 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11133 * do not add decap action if match rule drops packet
11134 * HW rejects rules with decap & drop
11136 * if tunnel match rule was inserted before matching tunnel set
11137 * rule flow table used in the match rule must be registered.
11138 * current implementation handles that in the
11139 * flow_dv_match_register() at the function end.
11141 bool add_decap = true;
11142 const struct rte_flow_action *ptr = actions;
11144 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11145 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11151 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11155 dev_flow->dv.actions[actions_n++] =
11156 dev_flow->dv.encap_decap->action;
11157 action_flags |= MLX5_FLOW_ACTION_DECAP;
11160 for (; !actions_end ; actions++) {
11161 const struct rte_flow_action_queue *queue;
11162 const struct rte_flow_action_rss *rss;
11163 const struct rte_flow_action *action = actions;
11164 const uint8_t *rss_key;
11165 struct mlx5_flow_tbl_resource *tbl;
11166 struct mlx5_aso_age_action *age_act;
11167 uint32_t port_id = 0;
11168 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11169 int action_type = actions->type;
11170 const struct rte_flow_action *found_action = NULL;
11171 uint32_t jump_group = 0;
11173 if (!mlx5_flow_os_action_supported(action_type))
11174 return rte_flow_error_set(error, ENOTSUP,
11175 RTE_FLOW_ERROR_TYPE_ACTION,
11177 "action not supported");
11178 switch (action_type) {
11179 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11180 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11182 case RTE_FLOW_ACTION_TYPE_VOID:
11184 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11185 if (flow_dv_translate_action_port_id(dev, action,
11188 port_id_resource.port_id = port_id;
11189 MLX5_ASSERT(!handle->rix_port_id_action);
11190 if (flow_dv_port_id_action_resource_register
11191 (dev, &port_id_resource, dev_flow, error))
11193 dev_flow->dv.actions[actions_n++] =
11194 dev_flow->dv.port_id_action->action;
11195 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11196 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11197 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11200 case RTE_FLOW_ACTION_TYPE_FLAG:
11201 action_flags |= MLX5_FLOW_ACTION_FLAG;
11202 dev_flow->handle->mark = 1;
11203 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11204 struct rte_flow_action_mark mark = {
11205 .id = MLX5_FLOW_MARK_DEFAULT,
11208 if (flow_dv_convert_action_mark(dev, &mark,
11212 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11215 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11217 * Only one FLAG or MARK is supported per device flow
11218 * right now. So the pointer to the tag resource must be
11219 * zero before the register process.
11221 MLX5_ASSERT(!handle->dvh.rix_tag);
11222 if (flow_dv_tag_resource_register(dev, tag_be,
11225 MLX5_ASSERT(dev_flow->dv.tag_resource);
11226 dev_flow->dv.actions[actions_n++] =
11227 dev_flow->dv.tag_resource->action;
11229 case RTE_FLOW_ACTION_TYPE_MARK:
11230 action_flags |= MLX5_FLOW_ACTION_MARK;
11231 dev_flow->handle->mark = 1;
11232 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11233 const struct rte_flow_action_mark *mark =
11234 (const struct rte_flow_action_mark *)
11237 if (flow_dv_convert_action_mark(dev, mark,
11241 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11245 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11246 /* Legacy (non-extensive) MARK action. */
11247 tag_be = mlx5_flow_mark_set
11248 (((const struct rte_flow_action_mark *)
11249 (actions->conf))->id);
11250 MLX5_ASSERT(!handle->dvh.rix_tag);
11251 if (flow_dv_tag_resource_register(dev, tag_be,
11254 MLX5_ASSERT(dev_flow->dv.tag_resource);
11255 dev_flow->dv.actions[actions_n++] =
11256 dev_flow->dv.tag_resource->action;
11258 case RTE_FLOW_ACTION_TYPE_SET_META:
11259 if (flow_dv_convert_action_set_meta
11260 (dev, mhdr_res, attr,
11261 (const struct rte_flow_action_set_meta *)
11262 actions->conf, error))
11264 action_flags |= MLX5_FLOW_ACTION_SET_META;
11266 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11267 if (flow_dv_convert_action_set_tag
11269 (const struct rte_flow_action_set_tag *)
11270 actions->conf, error))
11272 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11274 case RTE_FLOW_ACTION_TYPE_DROP:
11275 action_flags |= MLX5_FLOW_ACTION_DROP;
11276 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11278 case RTE_FLOW_ACTION_TYPE_QUEUE:
11279 queue = actions->conf;
11280 rss_desc->queue_num = 1;
11281 rss_desc->queue[0] = queue->index;
11282 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11283 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11284 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11287 case RTE_FLOW_ACTION_TYPE_RSS:
11288 rss = actions->conf;
11289 memcpy(rss_desc->queue, rss->queue,
11290 rss->queue_num * sizeof(uint16_t));
11291 rss_desc->queue_num = rss->queue_num;
11292 /* NULL RSS key indicates default RSS key. */
11293 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11294 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11296 * rss->level and rss.types should be set in advance
11297 * when expanding items for RSS.
11299 action_flags |= MLX5_FLOW_ACTION_RSS;
11300 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11301 MLX5_FLOW_FATE_SHARED_RSS :
11302 MLX5_FLOW_FATE_QUEUE;
11304 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11305 flow->age = (uint32_t)(uintptr_t)(action->conf);
11306 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11307 __atomic_fetch_add(&age_act->refcnt, 1,
11309 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11310 action_flags |= MLX5_FLOW_ACTION_AGE;
11312 case RTE_FLOW_ACTION_TYPE_AGE:
11313 if (priv->sh->flow_hit_aso_en && attr->group) {
11315 * Create one shared age action, to be used
11316 * by all sub-flows.
11320 flow_dv_translate_create_aso_age
11321 (dev, action->conf,
11324 return rte_flow_error_set
11326 RTE_FLOW_ERROR_TYPE_ACTION,
11328 "can't create ASO age action");
11330 dev_flow->dv.actions[actions_n++] =
11331 (flow_aso_age_get_by_idx
11332 (dev, flow->age))->dr_action;
11333 action_flags |= MLX5_FLOW_ACTION_AGE;
11337 case RTE_FLOW_ACTION_TYPE_COUNT:
11338 if (!dev_conf->devx) {
11339 return rte_flow_error_set
11341 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11343 "count action not supported");
11345 /* Save information first, will apply later. */
11346 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11347 count = action->conf;
11349 age = action->conf;
11350 action_flags |= MLX5_FLOW_ACTION_COUNT;
11352 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11353 dev_flow->dv.actions[actions_n++] =
11354 priv->sh->pop_vlan_action;
11355 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11357 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11358 if (!(action_flags &
11359 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11360 flow_dev_get_vlan_info_from_items(items, &vlan);
11361 vlan.eth_proto = rte_be_to_cpu_16
11362 ((((const struct rte_flow_action_of_push_vlan *)
11363 actions->conf)->ethertype));
11364 found_action = mlx5_flow_find_action
11366 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11368 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11369 found_action = mlx5_flow_find_action
11371 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11373 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11374 if (flow_dv_create_action_push_vlan
11375 (dev, attr, &vlan, dev_flow, error))
11377 dev_flow->dv.actions[actions_n++] =
11378 dev_flow->dv.push_vlan_res->action;
11379 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11381 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11382 /* of_vlan_push action handled this action */
11383 MLX5_ASSERT(action_flags &
11384 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11386 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11387 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11389 flow_dev_get_vlan_info_from_items(items, &vlan);
11390 mlx5_update_vlan_vid_pcp(actions, &vlan);
11391 /* If no VLAN push - this is a modify header action */
11392 if (flow_dv_convert_action_modify_vlan_vid
11393 (mhdr_res, actions, error))
11395 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11397 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11398 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11399 if (flow_dv_create_action_l2_encap(dev, actions,
11404 dev_flow->dv.actions[actions_n++] =
11405 dev_flow->dv.encap_decap->action;
11406 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11407 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11408 sample_act->action_flags |=
11409 MLX5_FLOW_ACTION_ENCAP;
11411 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11412 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11413 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11417 dev_flow->dv.actions[actions_n++] =
11418 dev_flow->dv.encap_decap->action;
11419 action_flags |= MLX5_FLOW_ACTION_DECAP;
11421 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11422 /* Handle encap with preceding decap. */
11423 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11424 if (flow_dv_create_action_raw_encap
11425 (dev, actions, dev_flow, attr, error))
11427 dev_flow->dv.actions[actions_n++] =
11428 dev_flow->dv.encap_decap->action;
11430 /* Handle encap without preceding decap. */
11431 if (flow_dv_create_action_l2_encap
11432 (dev, actions, dev_flow, attr->transfer,
11435 dev_flow->dv.actions[actions_n++] =
11436 dev_flow->dv.encap_decap->action;
11438 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11439 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11440 sample_act->action_flags |=
11441 MLX5_FLOW_ACTION_ENCAP;
11443 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11444 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11446 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11447 if (flow_dv_create_action_l2_decap
11448 (dev, dev_flow, attr->transfer, error))
11450 dev_flow->dv.actions[actions_n++] =
11451 dev_flow->dv.encap_decap->action;
11453 /* If decap is followed by encap, handle it at encap. */
11454 action_flags |= MLX5_FLOW_ACTION_DECAP;
11456 case RTE_FLOW_ACTION_TYPE_JUMP:
11457 jump_group = ((const struct rte_flow_action_jump *)
11458 action->conf)->group;
11459 grp_info.std_tbl_fix = 0;
11460 if (dev_flow->skip_scale &
11461 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11462 grp_info.skip_scale = 1;
11464 grp_info.skip_scale = 0;
11465 ret = mlx5_flow_group_to_table(dev, tunnel,
11471 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11473 !!dev_flow->external,
11474 tunnel, jump_group, 0,
11477 return rte_flow_error_set
11479 RTE_FLOW_ERROR_TYPE_ACTION,
11481 "cannot create jump action.");
11482 if (flow_dv_jump_tbl_resource_register
11483 (dev, tbl, dev_flow, error)) {
11484 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11485 return rte_flow_error_set
11487 RTE_FLOW_ERROR_TYPE_ACTION,
11489 "cannot create jump action.");
11491 dev_flow->dv.actions[actions_n++] =
11492 dev_flow->dv.jump->action;
11493 action_flags |= MLX5_FLOW_ACTION_JUMP;
11494 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11495 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11498 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11499 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11500 if (flow_dv_convert_action_modify_mac
11501 (mhdr_res, actions, error))
11503 action_flags |= actions->type ==
11504 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11505 MLX5_FLOW_ACTION_SET_MAC_SRC :
11506 MLX5_FLOW_ACTION_SET_MAC_DST;
11508 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11509 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11510 if (flow_dv_convert_action_modify_ipv4
11511 (mhdr_res, actions, error))
11513 action_flags |= actions->type ==
11514 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11515 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11516 MLX5_FLOW_ACTION_SET_IPV4_DST;
11518 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11519 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11520 if (flow_dv_convert_action_modify_ipv6
11521 (mhdr_res, actions, error))
11523 action_flags |= actions->type ==
11524 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11525 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11526 MLX5_FLOW_ACTION_SET_IPV6_DST;
11528 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11529 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11530 if (flow_dv_convert_action_modify_tp
11531 (mhdr_res, actions, items,
11532 &flow_attr, dev_flow, !!(action_flags &
11533 MLX5_FLOW_ACTION_DECAP), error))
11535 action_flags |= actions->type ==
11536 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11537 MLX5_FLOW_ACTION_SET_TP_SRC :
11538 MLX5_FLOW_ACTION_SET_TP_DST;
11540 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11541 if (flow_dv_convert_action_modify_dec_ttl
11542 (mhdr_res, items, &flow_attr, dev_flow,
11544 MLX5_FLOW_ACTION_DECAP), error))
11546 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11548 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11549 if (flow_dv_convert_action_modify_ttl
11550 (mhdr_res, actions, items, &flow_attr,
11551 dev_flow, !!(action_flags &
11552 MLX5_FLOW_ACTION_DECAP), error))
11554 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11556 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11557 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11558 if (flow_dv_convert_action_modify_tcp_seq
11559 (mhdr_res, actions, error))
11561 action_flags |= actions->type ==
11562 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11563 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11564 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11567 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11568 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11569 if (flow_dv_convert_action_modify_tcp_ack
11570 (mhdr_res, actions, error))
11572 action_flags |= actions->type ==
11573 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11574 MLX5_FLOW_ACTION_INC_TCP_ACK :
11575 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11577 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11578 if (flow_dv_convert_action_set_reg
11579 (mhdr_res, actions, error))
11581 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11583 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11584 if (flow_dv_convert_action_copy_mreg
11585 (dev, mhdr_res, actions, error))
11587 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11589 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11590 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11591 dev_flow->handle->fate_action =
11592 MLX5_FLOW_FATE_DEFAULT_MISS;
11594 case RTE_FLOW_ACTION_TYPE_METER:
11596 return rte_flow_error_set(error, rte_errno,
11597 RTE_FLOW_ERROR_TYPE_ACTION,
11598 NULL, "Failed to get meter in flow.");
11599 /* Set the meter action. */
11600 dev_flow->dv.actions[actions_n++] =
11601 wks->fm->meter_action;
11602 action_flags |= MLX5_FLOW_ACTION_METER;
11604 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11605 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11608 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11610 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11611 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11614 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11616 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11617 sample_act_pos = actions_n;
11618 sample = (const struct rte_flow_action_sample *)
11621 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11622 /* put encap action into group if work with port id */
11623 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11624 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11625 sample_act->action_flags |=
11626 MLX5_FLOW_ACTION_ENCAP;
11628 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11629 if (flow_dv_convert_action_modify_field
11630 (dev, mhdr_res, actions, attr, error))
11632 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11634 case RTE_FLOW_ACTION_TYPE_END:
11635 actions_end = true;
11636 if (mhdr_res->actions_num) {
11637 /* create modify action if needed. */
11638 if (flow_dv_modify_hdr_resource_register
11639 (dev, mhdr_res, dev_flow, error))
11641 dev_flow->dv.actions[modify_action_position] =
11642 handle->dvh.modify_hdr->action;
11644 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11646 * Create one count action, to be used
11647 * by all sub-flows.
11649 if (!flow->counter) {
11651 flow_dv_translate_create_counter
11652 (dev, dev_flow, count,
11654 if (!flow->counter)
11655 return rte_flow_error_set
11657 RTE_FLOW_ERROR_TYPE_ACTION,
11658 NULL, "cannot create counter"
11661 dev_flow->dv.actions[actions_n] =
11662 (flow_dv_counter_get_by_idx(dev,
11663 flow->counter, NULL))->action;
11669 if (mhdr_res->actions_num &&
11670 modify_action_position == UINT32_MAX)
11671 modify_action_position = actions_n++;
11673 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11674 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11675 int item_type = items->type;
11677 if (!mlx5_flow_os_item_supported(item_type))
11678 return rte_flow_error_set(error, ENOTSUP,
11679 RTE_FLOW_ERROR_TYPE_ITEM,
11680 NULL, "item not supported");
11681 switch (item_type) {
11682 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11683 flow_dv_translate_item_port_id
11684 (dev, match_mask, match_value, items, attr);
11685 last_item = MLX5_FLOW_ITEM_PORT_ID;
11687 case RTE_FLOW_ITEM_TYPE_ETH:
11688 flow_dv_translate_item_eth(match_mask, match_value,
11690 dev_flow->dv.group);
11691 matcher.priority = action_flags &
11692 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11693 !dev_flow->external ?
11694 MLX5_PRIORITY_MAP_L3 :
11695 MLX5_PRIORITY_MAP_L2;
11696 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11697 MLX5_FLOW_LAYER_OUTER_L2;
11699 case RTE_FLOW_ITEM_TYPE_VLAN:
11700 flow_dv_translate_item_vlan(dev_flow,
11701 match_mask, match_value,
11703 dev_flow->dv.group);
11704 matcher.priority = MLX5_PRIORITY_MAP_L2;
11705 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11706 MLX5_FLOW_LAYER_INNER_VLAN) :
11707 (MLX5_FLOW_LAYER_OUTER_L2 |
11708 MLX5_FLOW_LAYER_OUTER_VLAN);
11710 case RTE_FLOW_ITEM_TYPE_IPV4:
11711 mlx5_flow_tunnel_ip_check(items, next_protocol,
11712 &item_flags, &tunnel);
11713 flow_dv_translate_item_ipv4(match_mask, match_value,
11715 dev_flow->dv.group);
11716 matcher.priority = MLX5_PRIORITY_MAP_L3;
11717 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11718 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11719 if (items->mask != NULL &&
11720 ((const struct rte_flow_item_ipv4 *)
11721 items->mask)->hdr.next_proto_id) {
11723 ((const struct rte_flow_item_ipv4 *)
11724 (items->spec))->hdr.next_proto_id;
11726 ((const struct rte_flow_item_ipv4 *)
11727 (items->mask))->hdr.next_proto_id;
11729 /* Reset for inner layer. */
11730 next_protocol = 0xff;
11733 case RTE_FLOW_ITEM_TYPE_IPV6:
11734 mlx5_flow_tunnel_ip_check(items, next_protocol,
11735 &item_flags, &tunnel);
11736 flow_dv_translate_item_ipv6(match_mask, match_value,
11738 dev_flow->dv.group);
11739 matcher.priority = MLX5_PRIORITY_MAP_L3;
11740 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11741 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11742 if (items->mask != NULL &&
11743 ((const struct rte_flow_item_ipv6 *)
11744 items->mask)->hdr.proto) {
11746 ((const struct rte_flow_item_ipv6 *)
11747 items->spec)->hdr.proto;
11749 ((const struct rte_flow_item_ipv6 *)
11750 items->mask)->hdr.proto;
11752 /* Reset for inner layer. */
11753 next_protocol = 0xff;
11756 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11757 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11760 last_item = tunnel ?
11761 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11762 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11763 if (items->mask != NULL &&
11764 ((const struct rte_flow_item_ipv6_frag_ext *)
11765 items->mask)->hdr.next_header) {
11767 ((const struct rte_flow_item_ipv6_frag_ext *)
11768 items->spec)->hdr.next_header;
11770 ((const struct rte_flow_item_ipv6_frag_ext *)
11771 items->mask)->hdr.next_header;
11773 /* Reset for inner layer. */
11774 next_protocol = 0xff;
11777 case RTE_FLOW_ITEM_TYPE_TCP:
11778 flow_dv_translate_item_tcp(match_mask, match_value,
11780 matcher.priority = MLX5_PRIORITY_MAP_L4;
11781 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11782 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11784 case RTE_FLOW_ITEM_TYPE_UDP:
11785 flow_dv_translate_item_udp(match_mask, match_value,
11787 matcher.priority = MLX5_PRIORITY_MAP_L4;
11788 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11789 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11791 case RTE_FLOW_ITEM_TYPE_GRE:
11792 flow_dv_translate_item_gre(match_mask, match_value,
11794 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11795 last_item = MLX5_FLOW_LAYER_GRE;
11797 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11798 flow_dv_translate_item_gre_key(match_mask,
11799 match_value, items);
11800 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11802 case RTE_FLOW_ITEM_TYPE_NVGRE:
11803 flow_dv_translate_item_nvgre(match_mask, match_value,
11805 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11806 last_item = MLX5_FLOW_LAYER_GRE;
11808 case RTE_FLOW_ITEM_TYPE_VXLAN:
11809 flow_dv_translate_item_vxlan(match_mask, match_value,
11811 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11812 last_item = MLX5_FLOW_LAYER_VXLAN;
11814 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11815 flow_dv_translate_item_vxlan_gpe(match_mask,
11816 match_value, items,
11818 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11819 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11821 case RTE_FLOW_ITEM_TYPE_GENEVE:
11822 flow_dv_translate_item_geneve(match_mask, match_value,
11824 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11825 last_item = MLX5_FLOW_LAYER_GENEVE;
11827 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11828 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11832 return rte_flow_error_set(error, -ret,
11833 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11834 "cannot create GENEVE TLV option");
11835 flow->geneve_tlv_option = 1;
11836 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11838 case RTE_FLOW_ITEM_TYPE_MPLS:
11839 flow_dv_translate_item_mpls(match_mask, match_value,
11840 items, last_item, tunnel);
11841 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11842 last_item = MLX5_FLOW_LAYER_MPLS;
11844 case RTE_FLOW_ITEM_TYPE_MARK:
11845 flow_dv_translate_item_mark(dev, match_mask,
11846 match_value, items);
11847 last_item = MLX5_FLOW_ITEM_MARK;
11849 case RTE_FLOW_ITEM_TYPE_META:
11850 flow_dv_translate_item_meta(dev, match_mask,
11851 match_value, attr, items);
11852 last_item = MLX5_FLOW_ITEM_METADATA;
11854 case RTE_FLOW_ITEM_TYPE_ICMP:
11855 flow_dv_translate_item_icmp(match_mask, match_value,
11857 last_item = MLX5_FLOW_LAYER_ICMP;
11859 case RTE_FLOW_ITEM_TYPE_ICMP6:
11860 flow_dv_translate_item_icmp6(match_mask, match_value,
11862 last_item = MLX5_FLOW_LAYER_ICMP6;
11864 case RTE_FLOW_ITEM_TYPE_TAG:
11865 flow_dv_translate_item_tag(dev, match_mask,
11866 match_value, items);
11867 last_item = MLX5_FLOW_ITEM_TAG;
11869 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11870 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11871 match_value, items);
11872 last_item = MLX5_FLOW_ITEM_TAG;
11874 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11875 flow_dv_translate_item_tx_queue(dev, match_mask,
11878 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11880 case RTE_FLOW_ITEM_TYPE_GTP:
11881 flow_dv_translate_item_gtp(match_mask, match_value,
11883 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11884 last_item = MLX5_FLOW_LAYER_GTP;
11886 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11887 ret = flow_dv_translate_item_gtp_psc(match_mask,
11891 return rte_flow_error_set(error, -ret,
11892 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11893 "cannot create GTP PSC item");
11894 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11896 case RTE_FLOW_ITEM_TYPE_ECPRI:
11897 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11898 /* Create it only the first time to be used. */
11899 ret = mlx5_flex_parser_ecpri_alloc(dev);
11901 return rte_flow_error_set
11903 RTE_FLOW_ERROR_TYPE_ITEM,
11905 "cannot create eCPRI parser");
11907 /* Adjust the length matcher and device flow value. */
11908 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11909 dev_flow->dv.value.size =
11910 MLX5_ST_SZ_BYTES(fte_match_param);
11911 flow_dv_translate_item_ecpri(dev, match_mask,
11912 match_value, items);
11913 /* No other protocol should follow eCPRI layer. */
11914 last_item = MLX5_FLOW_LAYER_ECPRI;
11919 item_flags |= last_item;
11922 * When E-Switch mode is enabled, we have two cases where we need to
11923 * set the source port manually.
11924 * The first one, is in case of Nic steering rule, and the second is
11925 * E-Switch rule where no port_id item was found. In both cases
11926 * the source port is set according the current port in use.
11928 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11929 (priv->representor || priv->master)) {
11930 if (flow_dv_translate_item_port_id(dev, match_mask,
11931 match_value, NULL, attr))
11934 #ifdef RTE_LIBRTE_MLX5_DEBUG
11935 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11936 dev_flow->dv.value.buf));
11939 * Layers may be already initialized from prefix flow if this dev_flow
11940 * is the suffix flow.
11942 handle->layers |= item_flags;
11943 if (action_flags & MLX5_FLOW_ACTION_RSS)
11944 flow_dv_hashfields_set(dev_flow, rss_desc);
11945 /* If has RSS action in the sample action, the Sample/Mirror resource
11946 * should be registered after the hash filed be update.
11948 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11949 ret = flow_dv_translate_action_sample(dev,
11958 ret = flow_dv_create_action_sample(dev,
11967 return rte_flow_error_set
11969 RTE_FLOW_ERROR_TYPE_ACTION,
11971 "cannot create sample action");
11972 if (num_of_dest > 1) {
11973 dev_flow->dv.actions[sample_act_pos] =
11974 dev_flow->dv.dest_array_res->action;
11976 dev_flow->dv.actions[sample_act_pos] =
11977 dev_flow->dv.sample_res->verbs_action;
11981 * For multiple destination (sample action with ratio=1), the encap
11982 * action and port id action will be combined into group action.
11983 * So need remove the original these actions in the flow and only
11984 * use the sample action instead of.
11986 if (num_of_dest > 1 &&
11987 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11989 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11991 for (i = 0; i < actions_n; i++) {
11992 if ((sample_act->dr_encap_action &&
11993 sample_act->dr_encap_action ==
11994 dev_flow->dv.actions[i]) ||
11995 (sample_act->dr_port_id_action &&
11996 sample_act->dr_port_id_action ==
11997 dev_flow->dv.actions[i]) ||
11998 (sample_act->dr_jump_action &&
11999 sample_act->dr_jump_action ==
12000 dev_flow->dv.actions[i]))
12002 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
12004 memcpy((void *)dev_flow->dv.actions,
12005 (void *)temp_actions,
12006 tmp_actions_n * sizeof(void *));
12007 actions_n = tmp_actions_n;
12009 dev_flow->dv.actions_n = actions_n;
12010 dev_flow->act_flags = action_flags;
12011 /* Register matcher. */
12012 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12013 matcher.mask.size);
12014 matcher.priority = mlx5_get_matcher_priority(dev, attr,
12016 /* reserved field no needs to be set to 0 here. */
12017 tbl_key.is_fdb = attr->transfer;
12018 tbl_key.is_egress = attr->egress;
12019 tbl_key.level = dev_flow->dv.group;
12020 tbl_key.id = dev_flow->dv.table_id;
12021 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12022 tunnel, attr->group, error))
12028 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12031 * @param[in, out] action
12032 * Shred RSS action holding hash RX queue objects.
12033 * @param[in] hash_fields
12034 * Defines combination of packet fields to participate in RX hash.
12035 * @param[in] tunnel
12037 * @param[in] hrxq_idx
12038 * Hash RX queue index to set.
12041 * 0 on success, otherwise negative errno value.
12044 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12045 const uint64_t hash_fields,
12048 uint32_t *hrxqs = action->hrxq;
12050 switch (hash_fields & ~IBV_RX_HASH_INNER) {
12051 case MLX5_RSS_HASH_IPV4:
12052 /* fall-through. */
12053 case MLX5_RSS_HASH_IPV4_DST_ONLY:
12054 /* fall-through. */
12055 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12056 hrxqs[0] = hrxq_idx;
12058 case MLX5_RSS_HASH_IPV4_TCP:
12059 /* fall-through. */
12060 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12061 /* fall-through. */
12062 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12063 hrxqs[1] = hrxq_idx;
12065 case MLX5_RSS_HASH_IPV4_UDP:
12066 /* fall-through. */
12067 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12068 /* fall-through. */
12069 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12070 hrxqs[2] = hrxq_idx;
12072 case MLX5_RSS_HASH_IPV6:
12073 /* fall-through. */
12074 case MLX5_RSS_HASH_IPV6_DST_ONLY:
12075 /* fall-through. */
12076 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12077 hrxqs[3] = hrxq_idx;
12079 case MLX5_RSS_HASH_IPV6_TCP:
12080 /* fall-through. */
12081 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12082 /* fall-through. */
12083 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12084 hrxqs[4] = hrxq_idx;
12086 case MLX5_RSS_HASH_IPV6_UDP:
12087 /* fall-through. */
12088 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12089 /* fall-through. */
12090 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12091 hrxqs[5] = hrxq_idx;
12093 case MLX5_RSS_HASH_NONE:
12094 hrxqs[6] = hrxq_idx;
12102 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12106 * Pointer to the Ethernet device structure.
12108 * Shared RSS action ID holding hash RX queue objects.
12109 * @param[in] hash_fields
12110 * Defines combination of packet fields to participate in RX hash.
12111 * @param[in] tunnel
12115 * Valid hash RX queue index, otherwise 0.
12118 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12119 const uint64_t hash_fields)
12121 struct mlx5_priv *priv = dev->data->dev_private;
12122 struct mlx5_shared_action_rss *shared_rss =
12123 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12124 const uint32_t *hrxqs = shared_rss->hrxq;
12126 switch (hash_fields & ~IBV_RX_HASH_INNER) {
12127 case MLX5_RSS_HASH_IPV4:
12128 /* fall-through. */
12129 case MLX5_RSS_HASH_IPV4_DST_ONLY:
12130 /* fall-through. */
12131 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12133 case MLX5_RSS_HASH_IPV4_TCP:
12134 /* fall-through. */
12135 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12136 /* fall-through. */
12137 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12139 case MLX5_RSS_HASH_IPV4_UDP:
12140 /* fall-through. */
12141 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12142 /* fall-through. */
12143 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12145 case MLX5_RSS_HASH_IPV6:
12146 /* fall-through. */
12147 case MLX5_RSS_HASH_IPV6_DST_ONLY:
12148 /* fall-through. */
12149 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12151 case MLX5_RSS_HASH_IPV6_TCP:
12152 /* fall-through. */
12153 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12154 /* fall-through. */
12155 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12157 case MLX5_RSS_HASH_IPV6_UDP:
12158 /* fall-through. */
12159 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12160 /* fall-through. */
12161 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12163 case MLX5_RSS_HASH_NONE:
12172 * Apply the flow to the NIC, lock free,
12173 * (mutex should be acquired by caller).
12176 * Pointer to the Ethernet device structure.
12177 * @param[in, out] flow
12178 * Pointer to flow structure.
12179 * @param[out] error
12180 * Pointer to error structure.
12183 * 0 on success, a negative errno value otherwise and rte_errno is set.
12186 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12187 struct rte_flow_error *error)
12189 struct mlx5_flow_dv_workspace *dv;
12190 struct mlx5_flow_handle *dh;
12191 struct mlx5_flow_handle_dv *dv_h;
12192 struct mlx5_flow *dev_flow;
12193 struct mlx5_priv *priv = dev->data->dev_private;
12194 uint32_t handle_idx;
12198 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12199 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12202 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12203 dev_flow = &wks->flows[idx];
12204 dv = &dev_flow->dv;
12205 dh = dev_flow->handle;
12208 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12209 if (dv->transfer) {
12210 MLX5_ASSERT(priv->sh->dr_drop_action);
12211 dv->actions[n++] = priv->sh->dr_drop_action;
12213 #ifdef HAVE_MLX5DV_DR
12214 /* DR supports drop action placeholder. */
12215 MLX5_ASSERT(priv->sh->dr_drop_action);
12216 dv->actions[n++] = priv->sh->dr_drop_action;
12218 /* For DV we use the explicit drop queue. */
12219 MLX5_ASSERT(priv->drop_queue.hrxq);
12221 priv->drop_queue.hrxq->action;
12224 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12225 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12226 struct mlx5_hrxq *hrxq;
12229 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12234 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12235 "cannot get hash queue");
12238 dh->rix_hrxq = hrxq_idx;
12239 dv->actions[n++] = hrxq->action;
12240 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12241 struct mlx5_hrxq *hrxq = NULL;
12244 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12245 rss_desc->shared_rss,
12246 dev_flow->hash_fields);
12248 hrxq = mlx5_ipool_get
12249 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12254 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12255 "cannot get hash queue");
12258 dh->rix_srss = rss_desc->shared_rss;
12259 dv->actions[n++] = hrxq->action;
12260 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12261 if (!priv->sh->default_miss_action) {
12264 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12265 "default miss action not be created.");
12268 dv->actions[n++] = priv->sh->default_miss_action;
12270 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12271 (void *)&dv->value, n,
12272 dv->actions, &dh->drv_flow);
12274 rte_flow_error_set(error, errno,
12275 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12277 "hardware refuses to create flow");
12280 if (priv->vmwa_context &&
12281 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12283 * The rule contains the VLAN pattern.
12284 * For VF we are going to create VLAN
12285 * interface to make hypervisor set correct
12286 * e-Switch vport context.
12288 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12293 err = rte_errno; /* Save rte_errno before cleanup. */
12294 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12295 handle_idx, dh, next) {
12296 /* hrxq is union, don't clear it if the flag is not set. */
12297 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12298 mlx5_hrxq_release(dev, dh->rix_hrxq);
12300 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12303 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12304 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12306 rte_errno = err; /* Restore rte_errno. */
12311 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12312 struct mlx5_cache_entry *entry)
12314 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12317 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12322 * Release the flow matcher.
12325 * Pointer to Ethernet device.
12327 * Index to port ID action resource.
12330 * 1 while a reference on it exists, 0 when freed.
12333 flow_dv_matcher_release(struct rte_eth_dev *dev,
12334 struct mlx5_flow_handle *handle)
12336 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12337 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12338 typeof(*tbl), tbl);
12341 MLX5_ASSERT(matcher->matcher_object);
12342 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12343 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12348 * Release encap_decap resource.
12351 * Pointer to the hash list.
12353 * Pointer to exist resource entry object.
12356 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12357 struct mlx5_hlist_entry *entry)
12359 struct mlx5_dev_ctx_shared *sh = list->ctx;
12360 struct mlx5_flow_dv_encap_decap_resource *res =
12361 container_of(entry, typeof(*res), entry);
12363 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12364 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12368 * Release an encap/decap resource.
12371 * Pointer to Ethernet device.
12372 * @param encap_decap_idx
12373 * Index of encap decap resource.
12376 * 1 while a reference on it exists, 0 when freed.
12379 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12380 uint32_t encap_decap_idx)
12382 struct mlx5_priv *priv = dev->data->dev_private;
12383 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12385 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12387 if (!cache_resource)
12389 MLX5_ASSERT(cache_resource->action);
12390 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12391 &cache_resource->entry);
12395 * Release an jump to table action resource.
12398 * Pointer to Ethernet device.
12400 * Index to the jump action resource.
12403 * 1 while a reference on it exists, 0 when freed.
12406 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12409 struct mlx5_priv *priv = dev->data->dev_private;
12410 struct mlx5_flow_tbl_data_entry *tbl_data;
12412 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12416 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12420 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12421 struct mlx5_hlist_entry *entry)
12423 struct mlx5_flow_dv_modify_hdr_resource *res =
12424 container_of(entry, typeof(*res), entry);
12426 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12431 * Release a modify-header resource.
12434 * Pointer to Ethernet device.
12436 * Pointer to mlx5_flow_handle.
12439 * 1 while a reference on it exists, 0 when freed.
12442 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12443 struct mlx5_flow_handle *handle)
12445 struct mlx5_priv *priv = dev->data->dev_private;
12446 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12448 MLX5_ASSERT(entry->action);
12449 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12453 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12454 struct mlx5_cache_entry *entry)
12456 struct mlx5_dev_ctx_shared *sh = list->ctx;
12457 struct mlx5_flow_dv_port_id_action_resource *cache =
12458 container_of(entry, typeof(*cache), entry);
12460 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12461 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12465 * Release port ID action resource.
12468 * Pointer to Ethernet device.
12470 * Pointer to mlx5_flow_handle.
12473 * 1 while a reference on it exists, 0 when freed.
12476 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12479 struct mlx5_priv *priv = dev->data->dev_private;
12480 struct mlx5_flow_dv_port_id_action_resource *cache;
12482 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12485 MLX5_ASSERT(cache->action);
12486 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12491 * Release shared RSS action resource.
12494 * Pointer to Ethernet device.
12496 * Shared RSS action index.
12499 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12501 struct mlx5_priv *priv = dev->data->dev_private;
12502 struct mlx5_shared_action_rss *shared_rss;
12504 shared_rss = mlx5_ipool_get
12505 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12506 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12510 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12511 struct mlx5_cache_entry *entry)
12513 struct mlx5_dev_ctx_shared *sh = list->ctx;
12514 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12515 container_of(entry, typeof(*cache), entry);
12517 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12518 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12522 * Release push vlan action resource.
12525 * Pointer to Ethernet device.
12527 * Pointer to mlx5_flow_handle.
12530 * 1 while a reference on it exists, 0 when freed.
12533 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12534 struct mlx5_flow_handle *handle)
12536 struct mlx5_priv *priv = dev->data->dev_private;
12537 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12538 uint32_t idx = handle->dvh.rix_push_vlan;
12540 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12543 MLX5_ASSERT(cache->action);
12544 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12549 * Release the fate resource.
12552 * Pointer to Ethernet device.
12554 * Pointer to mlx5_flow_handle.
12557 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12558 struct mlx5_flow_handle *handle)
12560 if (!handle->rix_fate)
12562 switch (handle->fate_action) {
12563 case MLX5_FLOW_FATE_QUEUE:
12564 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12565 mlx5_hrxq_release(dev, handle->rix_hrxq);
12567 case MLX5_FLOW_FATE_JUMP:
12568 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12570 case MLX5_FLOW_FATE_PORT_ID:
12571 flow_dv_port_id_action_resource_release(dev,
12572 handle->rix_port_id_action);
12575 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12578 handle->rix_fate = 0;
12582 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12583 struct mlx5_cache_entry *entry)
12585 struct mlx5_flow_dv_sample_resource *cache_resource =
12586 container_of(entry, typeof(*cache_resource), entry);
12587 struct rte_eth_dev *dev = cache_resource->dev;
12588 struct mlx5_priv *priv = dev->data->dev_private;
12590 if (cache_resource->verbs_action)
12591 claim_zero(mlx5_flow_os_destroy_flow_action
12592 (cache_resource->verbs_action));
12593 if (cache_resource->normal_path_tbl)
12594 flow_dv_tbl_resource_release(MLX5_SH(dev),
12595 cache_resource->normal_path_tbl);
12596 flow_dv_sample_sub_actions_release(dev,
12597 &cache_resource->sample_idx);
12598 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12599 cache_resource->idx);
12600 DRV_LOG(DEBUG, "sample resource %p: removed",
12601 (void *)cache_resource);
12605 * Release an sample resource.
12608 * Pointer to Ethernet device.
12610 * Pointer to mlx5_flow_handle.
12613 * 1 while a reference on it exists, 0 when freed.
12616 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12617 struct mlx5_flow_handle *handle)
12619 struct mlx5_priv *priv = dev->data->dev_private;
12620 struct mlx5_flow_dv_sample_resource *cache_resource;
12622 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12623 handle->dvh.rix_sample);
12624 if (!cache_resource)
12626 MLX5_ASSERT(cache_resource->verbs_action);
12627 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12628 &cache_resource->entry);
12632 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12633 struct mlx5_cache_entry *entry)
12635 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12636 container_of(entry, typeof(*cache_resource), entry);
12637 struct rte_eth_dev *dev = cache_resource->dev;
12638 struct mlx5_priv *priv = dev->data->dev_private;
12641 MLX5_ASSERT(cache_resource->action);
12642 if (cache_resource->action)
12643 claim_zero(mlx5_flow_os_destroy_flow_action
12644 (cache_resource->action));
12645 for (; i < cache_resource->num_of_dest; i++)
12646 flow_dv_sample_sub_actions_release(dev,
12647 &cache_resource->sample_idx[i]);
12648 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12649 cache_resource->idx);
12650 DRV_LOG(DEBUG, "destination array resource %p: removed",
12651 (void *)cache_resource);
12655 * Release an destination array resource.
12658 * Pointer to Ethernet device.
12660 * Pointer to mlx5_flow_handle.
12663 * 1 while a reference on it exists, 0 when freed.
12666 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12667 struct mlx5_flow_handle *handle)
12669 struct mlx5_priv *priv = dev->data->dev_private;
12670 struct mlx5_flow_dv_dest_array_resource *cache;
12672 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12673 handle->dvh.rix_dest_array);
12676 MLX5_ASSERT(cache->action);
12677 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12682 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12684 struct mlx5_priv *priv = dev->data->dev_private;
12685 struct mlx5_dev_ctx_shared *sh = priv->sh;
12686 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12687 sh->geneve_tlv_option_resource;
12688 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12689 if (geneve_opt_resource) {
12690 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12691 __ATOMIC_RELAXED))) {
12692 claim_zero(mlx5_devx_cmd_destroy
12693 (geneve_opt_resource->obj));
12694 mlx5_free(sh->geneve_tlv_option_resource);
12695 sh->geneve_tlv_option_resource = NULL;
12698 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12702 * Remove the flow from the NIC but keeps it in memory.
12703 * Lock free, (mutex should be acquired by caller).
12706 * Pointer to Ethernet device.
12707 * @param[in, out] flow
12708 * Pointer to flow structure.
12711 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12713 struct mlx5_flow_handle *dh;
12714 uint32_t handle_idx;
12715 struct mlx5_priv *priv = dev->data->dev_private;
12719 handle_idx = flow->dev_handles;
12720 while (handle_idx) {
12721 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12725 if (dh->drv_flow) {
12726 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12727 dh->drv_flow = NULL;
12729 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12730 flow_dv_fate_resource_release(dev, dh);
12731 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12732 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12733 handle_idx = dh->next.next;
12738 * Remove the flow from the NIC and the memory.
12739 * Lock free, (mutex should be acquired by caller).
12742 * Pointer to the Ethernet device structure.
12743 * @param[in, out] flow
12744 * Pointer to flow structure.
12747 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12749 struct mlx5_flow_handle *dev_handle;
12750 struct mlx5_priv *priv = dev->data->dev_private;
12751 struct mlx5_flow_meter_info *fm = NULL;
12756 flow_dv_remove(dev, flow);
12757 if (flow->counter) {
12758 flow_dv_counter_free(dev, flow->counter);
12762 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
12764 mlx5_flow_meter_detach(priv, fm);
12768 flow_dv_aso_age_release(dev, flow->age);
12769 if (flow->geneve_tlv_option) {
12770 flow_dv_geneve_tlv_option_resource_release(dev);
12771 flow->geneve_tlv_option = 0;
12773 while (flow->dev_handles) {
12774 uint32_t tmp_idx = flow->dev_handles;
12776 dev_handle = mlx5_ipool_get(priv->sh->ipool
12777 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12780 flow->dev_handles = dev_handle->next.next;
12781 if (dev_handle->dvh.matcher)
12782 flow_dv_matcher_release(dev, dev_handle);
12783 if (dev_handle->dvh.rix_sample)
12784 flow_dv_sample_resource_release(dev, dev_handle);
12785 if (dev_handle->dvh.rix_dest_array)
12786 flow_dv_dest_array_resource_release(dev, dev_handle);
12787 if (dev_handle->dvh.rix_encap_decap)
12788 flow_dv_encap_decap_resource_release(dev,
12789 dev_handle->dvh.rix_encap_decap);
12790 if (dev_handle->dvh.modify_hdr)
12791 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12792 if (dev_handle->dvh.rix_push_vlan)
12793 flow_dv_push_vlan_action_resource_release(dev,
12795 if (dev_handle->dvh.rix_tag)
12796 flow_dv_tag_release(dev,
12797 dev_handle->dvh.rix_tag);
12798 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12799 flow_dv_fate_resource_release(dev, dev_handle);
12801 srss = dev_handle->rix_srss;
12802 if (fm && dev_handle->is_meter_flow_id &&
12803 dev_handle->split_flow_id)
12804 mlx5_ipool_free(fm->flow_ipool,
12805 dev_handle->split_flow_id);
12806 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12810 flow_dv_shared_rss_action_release(dev, srss);
12814 * Release array of hash RX queue objects.
12818 * Pointer to the Ethernet device structure.
12819 * @param[in, out] hrxqs
12820 * Array of hash RX queue objects.
12823 * Total number of references to hash RX queue objects in *hrxqs* array
12824 * after this operation.
12827 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12828 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12833 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12834 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12844 * Release all hash RX queue objects representing shared RSS action.
12847 * Pointer to the Ethernet device structure.
12848 * @param[in, out] action
12849 * Shared RSS action to remove hash RX queue objects from.
12852 * Total number of references to hash RX queue objects stored in *action*
12853 * after this operation.
12854 * Expected to be 0 if no external references held.
12857 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12858 struct mlx5_shared_action_rss *shared_rss)
12860 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12864 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12867 * Only one hash value is available for one L3+L4 combination:
12869 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12870 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12871 * same slot in mlx5_rss_hash_fields.
12874 * Pointer to the shared action RSS conf.
12875 * @param[in, out] hash_field
12876 * hash_field variable needed to be adjusted.
12882 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12883 uint64_t *hash_field)
12885 uint64_t rss_types = rss->origin.types;
12887 switch (*hash_field & ~IBV_RX_HASH_INNER) {
12888 case MLX5_RSS_HASH_IPV4:
12889 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12890 *hash_field &= ~MLX5_RSS_HASH_IPV4;
12891 if (rss_types & ETH_RSS_L3_DST_ONLY)
12892 *hash_field |= IBV_RX_HASH_DST_IPV4;
12893 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12894 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12896 *hash_field |= MLX5_RSS_HASH_IPV4;
12899 case MLX5_RSS_HASH_IPV6:
12900 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12901 *hash_field &= ~MLX5_RSS_HASH_IPV6;
12902 if (rss_types & ETH_RSS_L3_DST_ONLY)
12903 *hash_field |= IBV_RX_HASH_DST_IPV6;
12904 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12905 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12907 *hash_field |= MLX5_RSS_HASH_IPV6;
12910 case MLX5_RSS_HASH_IPV4_UDP:
12911 /* fall-through. */
12912 case MLX5_RSS_HASH_IPV6_UDP:
12913 if (rss_types & ETH_RSS_UDP) {
12914 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12915 if (rss_types & ETH_RSS_L4_DST_ONLY)
12916 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12917 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12918 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12920 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12923 case MLX5_RSS_HASH_IPV4_TCP:
12924 /* fall-through. */
12925 case MLX5_RSS_HASH_IPV6_TCP:
12926 if (rss_types & ETH_RSS_TCP) {
12927 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12928 if (rss_types & ETH_RSS_L4_DST_ONLY)
12929 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12930 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12931 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12933 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12942 * Setup shared RSS action.
12943 * Prepare set of hash RX queue objects sufficient to handle all valid
12944 * hash_fields combinations (see enum ibv_rx_hash_fields).
12947 * Pointer to the Ethernet device structure.
12948 * @param[in] action_idx
12949 * Shared RSS action ipool index.
12950 * @param[in, out] action
12951 * Partially initialized shared RSS action.
12952 * @param[out] error
12953 * Perform verbose error reporting if not NULL. Initialized in case of
12957 * 0 on success, otherwise negative errno value.
12960 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12961 uint32_t action_idx,
12962 struct mlx5_shared_action_rss *shared_rss,
12963 struct rte_flow_error *error)
12965 struct mlx5_flow_rss_desc rss_desc = { 0 };
12969 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12970 return rte_flow_error_set(error, rte_errno,
12971 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12972 "cannot setup indirection table");
12974 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12975 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12976 rss_desc.const_q = shared_rss->origin.queue;
12977 rss_desc.queue_num = shared_rss->origin.queue_num;
12978 /* Set non-zero value to indicate a shared RSS. */
12979 rss_desc.shared_rss = action_idx;
12980 rss_desc.ind_tbl = shared_rss->ind_tbl;
12981 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12983 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12986 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12987 if (shared_rss->origin.level > 1) {
12988 hash_fields |= IBV_RX_HASH_INNER;
12991 rss_desc.tunnel = tunnel;
12992 rss_desc.hash_fields = hash_fields;
12993 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12997 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12998 "cannot get hash queue");
12999 goto error_hrxq_new;
13001 err = __flow_dv_action_rss_hrxq_set
13002 (shared_rss, hash_fields, hrxq_idx);
13008 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13009 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13010 shared_rss->ind_tbl = NULL;
13016 * Create shared RSS action.
13019 * Pointer to the Ethernet device structure.
13021 * Shared action configuration.
13023 * RSS action specification used to create shared action.
13024 * @param[out] error
13025 * Perform verbose error reporting if not NULL. Initialized in case of
13029 * A valid shared action ID in case of success, 0 otherwise and
13030 * rte_errno is set.
13033 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13034 const struct rte_flow_indir_action_conf *conf,
13035 const struct rte_flow_action_rss *rss,
13036 struct rte_flow_error *error)
13038 struct mlx5_priv *priv = dev->data->dev_private;
13039 struct mlx5_shared_action_rss *shared_rss = NULL;
13040 void *queue = NULL;
13041 struct rte_flow_action_rss *origin;
13042 const uint8_t *rss_key;
13043 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13046 RTE_SET_USED(conf);
13047 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13049 shared_rss = mlx5_ipool_zmalloc
13050 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13051 if (!shared_rss || !queue) {
13052 rte_flow_error_set(error, ENOMEM,
13053 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13054 "cannot allocate resource memory");
13055 goto error_rss_init;
13057 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13058 rte_flow_error_set(error, E2BIG,
13059 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13060 "rss action number out of range");
13061 goto error_rss_init;
13063 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13064 sizeof(*shared_rss->ind_tbl),
13066 if (!shared_rss->ind_tbl) {
13067 rte_flow_error_set(error, ENOMEM,
13068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13069 "cannot allocate resource memory");
13070 goto error_rss_init;
13072 memcpy(queue, rss->queue, queue_size);
13073 shared_rss->ind_tbl->queues = queue;
13074 shared_rss->ind_tbl->queues_n = rss->queue_num;
13075 origin = &shared_rss->origin;
13076 origin->func = rss->func;
13077 origin->level = rss->level;
13078 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13079 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13080 /* NULL RSS key indicates default RSS key. */
13081 rss_key = !rss->key ? rss_hash_default_key : rss->key;
13082 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13083 origin->key = &shared_rss->key[0];
13084 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13085 origin->queue = queue;
13086 origin->queue_num = rss->queue_num;
13087 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13088 goto error_rss_init;
13089 rte_spinlock_init(&shared_rss->action_rss_sl);
13090 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13091 rte_spinlock_lock(&priv->shared_act_sl);
13092 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13093 &priv->rss_shared_actions, idx, shared_rss, next);
13094 rte_spinlock_unlock(&priv->shared_act_sl);
13098 if (shared_rss->ind_tbl)
13099 mlx5_free(shared_rss->ind_tbl);
13100 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13109 * Destroy the shared RSS action.
13110 * Release related hash RX queue objects.
13113 * Pointer to the Ethernet device structure.
13115 * The shared RSS action object ID to be removed.
13116 * @param[out] error
13117 * Perform verbose error reporting if not NULL. Initialized in case of
13121 * 0 on success, otherwise negative errno value.
13124 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13125 struct rte_flow_error *error)
13127 struct mlx5_priv *priv = dev->data->dev_private;
13128 struct mlx5_shared_action_rss *shared_rss =
13129 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13130 uint32_t old_refcnt = 1;
13132 uint16_t *queue = NULL;
13135 return rte_flow_error_set(error, EINVAL,
13136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13137 "invalid shared action");
13138 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13140 return rte_flow_error_set(error, EBUSY,
13141 RTE_FLOW_ERROR_TYPE_ACTION,
13143 "shared rss hrxq has references");
13144 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13145 0, 0, __ATOMIC_ACQUIRE,
13147 return rte_flow_error_set(error, EBUSY,
13148 RTE_FLOW_ERROR_TYPE_ACTION,
13150 "shared rss has references");
13151 queue = shared_rss->ind_tbl->queues;
13152 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13154 return rte_flow_error_set(error, EBUSY,
13155 RTE_FLOW_ERROR_TYPE_ACTION,
13157 "shared rss indirection table has"
13160 rte_spinlock_lock(&priv->shared_act_sl);
13161 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13162 &priv->rss_shared_actions, idx, shared_rss, next);
13163 rte_spinlock_unlock(&priv->shared_act_sl);
13164 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13170 * Create indirect action, lock free,
13171 * (mutex should be acquired by caller).
13172 * Dispatcher for action type specific call.
13175 * Pointer to the Ethernet device structure.
13177 * Shared action configuration.
13178 * @param[in] action
13179 * Action specification used to create indirect action.
13180 * @param[out] error
13181 * Perform verbose error reporting if not NULL. Initialized in case of
13185 * A valid shared action handle in case of success, NULL otherwise and
13186 * rte_errno is set.
13188 static struct rte_flow_action_handle *
13189 flow_dv_action_create(struct rte_eth_dev *dev,
13190 const struct rte_flow_indir_action_conf *conf,
13191 const struct rte_flow_action *action,
13192 struct rte_flow_error *err)
13197 switch (action->type) {
13198 case RTE_FLOW_ACTION_TYPE_RSS:
13199 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13200 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13201 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13203 case RTE_FLOW_ACTION_TYPE_AGE:
13204 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13205 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13206 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13208 struct mlx5_aso_age_action *aso_age =
13209 flow_aso_age_get_by_idx(dev, ret);
13211 if (!aso_age->age_params.context)
13212 aso_age->age_params.context =
13213 (void *)(uintptr_t)idx;
13217 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13218 NULL, "action type not supported");
13221 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13225 * Destroy the indirect action.
13226 * Release action related resources on the NIC and the memory.
13227 * Lock free, (mutex should be acquired by caller).
13228 * Dispatcher for action type specific call.
13231 * Pointer to the Ethernet device structure.
13232 * @param[in] handle
13233 * The indirect action object handle to be removed.
13234 * @param[out] error
13235 * Perform verbose error reporting if not NULL. Initialized in case of
13239 * 0 on success, otherwise negative errno value.
13242 flow_dv_action_destroy(struct rte_eth_dev *dev,
13243 struct rte_flow_action_handle *handle,
13244 struct rte_flow_error *error)
13246 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13247 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13248 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13252 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13253 return __flow_dv_action_rss_release(dev, idx, error);
13254 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13255 ret = flow_dv_aso_age_release(dev, idx);
13258 * In this case, the last flow has a reference will
13259 * actually release the age action.
13261 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13262 " released with references %d.", idx, ret);
13265 return rte_flow_error_set(error, ENOTSUP,
13266 RTE_FLOW_ERROR_TYPE_ACTION,
13268 "action type not supported");
13273 * Updates in place shared RSS action configuration.
13276 * Pointer to the Ethernet device structure.
13278 * The shared RSS action object ID to be updated.
13279 * @param[in] action_conf
13280 * RSS action specification used to modify *shared_rss*.
13281 * @param[out] error
13282 * Perform verbose error reporting if not NULL. Initialized in case of
13286 * 0 on success, otherwise negative errno value.
13287 * @note: currently only support update of RSS queues.
13290 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13291 const struct rte_flow_action_rss *action_conf,
13292 struct rte_flow_error *error)
13294 struct mlx5_priv *priv = dev->data->dev_private;
13295 struct mlx5_shared_action_rss *shared_rss =
13296 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13298 void *queue = NULL;
13299 uint16_t *queue_old = NULL;
13300 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13303 return rte_flow_error_set(error, EINVAL,
13304 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13305 "invalid shared action to update");
13306 if (priv->obj_ops.ind_table_modify == NULL)
13307 return rte_flow_error_set(error, ENOTSUP,
13308 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13309 "cannot modify indirection table");
13310 queue = mlx5_malloc(MLX5_MEM_ZERO,
13311 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13314 return rte_flow_error_set(error, ENOMEM,
13315 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13317 "cannot allocate resource memory");
13318 memcpy(queue, action_conf->queue, queue_size);
13319 MLX5_ASSERT(shared_rss->ind_tbl);
13320 rte_spinlock_lock(&shared_rss->action_rss_sl);
13321 queue_old = shared_rss->ind_tbl->queues;
13322 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13323 queue, action_conf->queue_num, true);
13326 ret = rte_flow_error_set(error, rte_errno,
13327 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13328 "cannot update indirection table");
13330 mlx5_free(queue_old);
13331 shared_rss->origin.queue = queue;
13332 shared_rss->origin.queue_num = action_conf->queue_num;
13334 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13339 * Updates in place shared action configuration, lock free,
13340 * (mutex should be acquired by caller).
13343 * Pointer to the Ethernet device structure.
13344 * @param[in] handle
13345 * The indirect action object handle to be updated.
13346 * @param[in] update
13347 * Action specification used to modify the action pointed by *handle*.
13348 * *update* could be of same type with the action pointed by the *handle*
13349 * handle argument, or some other structures like a wrapper, depending on
13350 * the indirect action type.
13351 * @param[out] error
13352 * Perform verbose error reporting if not NULL. Initialized in case of
13356 * 0 on success, otherwise negative errno value.
13359 flow_dv_action_update(struct rte_eth_dev *dev,
13360 struct rte_flow_action_handle *handle,
13361 const void *update,
13362 struct rte_flow_error *err)
13364 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13365 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13366 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13367 const void *action_conf;
13370 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13371 action_conf = ((const struct rte_flow_action *)update)->conf;
13372 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13374 return rte_flow_error_set(err, ENOTSUP,
13375 RTE_FLOW_ERROR_TYPE_ACTION,
13377 "action type update not supported");
13382 flow_dv_action_query(struct rte_eth_dev *dev,
13383 const struct rte_flow_action_handle *handle, void *data,
13384 struct rte_flow_error *error)
13386 struct mlx5_age_param *age_param;
13387 struct rte_flow_query_age *resp;
13388 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13389 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13390 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13393 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13394 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13396 resp->aged = __atomic_load_n(&age_param->state,
13397 __ATOMIC_RELAXED) == AGE_TMOUT ?
13399 resp->sec_since_last_hit_valid = !resp->aged;
13400 if (resp->sec_since_last_hit_valid)
13401 resp->sec_since_last_hit = __atomic_load_n
13402 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13405 return rte_flow_error_set(error, ENOTSUP,
13406 RTE_FLOW_ERROR_TYPE_ACTION,
13408 "action type query not supported");
13413 * Query a dv flow rule for its statistics via devx.
13416 * Pointer to Ethernet device.
13418 * Pointer to the sub flow.
13420 * data retrieved by the query.
13421 * @param[out] error
13422 * Perform verbose error reporting if not NULL.
13425 * 0 on success, a negative errno value otherwise and rte_errno is set.
13428 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13429 void *data, struct rte_flow_error *error)
13431 struct mlx5_priv *priv = dev->data->dev_private;
13432 struct rte_flow_query_count *qc = data;
13434 if (!priv->config.devx)
13435 return rte_flow_error_set(error, ENOTSUP,
13436 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13438 "counters are not supported");
13439 if (flow->counter) {
13440 uint64_t pkts, bytes;
13441 struct mlx5_flow_counter *cnt;
13443 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13445 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13449 return rte_flow_error_set(error, -err,
13450 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13451 NULL, "cannot read counters");
13454 qc->hits = pkts - cnt->hits;
13455 qc->bytes = bytes - cnt->bytes;
13458 cnt->bytes = bytes;
13462 return rte_flow_error_set(error, EINVAL,
13463 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13465 "counters are not available");
13469 * Query a flow rule AGE action for aging information.
13472 * Pointer to Ethernet device.
13474 * Pointer to the sub flow.
13476 * data retrieved by the query.
13477 * @param[out] error
13478 * Perform verbose error reporting if not NULL.
13481 * 0 on success, a negative errno value otherwise and rte_errno is set.
13484 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13485 void *data, struct rte_flow_error *error)
13487 struct rte_flow_query_age *resp = data;
13488 struct mlx5_age_param *age_param;
13491 struct mlx5_aso_age_action *act =
13492 flow_aso_age_get_by_idx(dev, flow->age);
13494 age_param = &act->age_params;
13495 } else if (flow->counter) {
13496 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13498 if (!age_param || !age_param->timeout)
13499 return rte_flow_error_set
13501 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13502 NULL, "cannot read age data");
13504 return rte_flow_error_set(error, EINVAL,
13505 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13506 NULL, "age data not available");
13508 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13510 resp->sec_since_last_hit_valid = !resp->aged;
13511 if (resp->sec_since_last_hit_valid)
13512 resp->sec_since_last_hit = __atomic_load_n
13513 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13520 * @see rte_flow_query()
13521 * @see rte_flow_ops
13524 flow_dv_query(struct rte_eth_dev *dev,
13525 struct rte_flow *flow __rte_unused,
13526 const struct rte_flow_action *actions __rte_unused,
13527 void *data __rte_unused,
13528 struct rte_flow_error *error __rte_unused)
13532 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13533 switch (actions->type) {
13534 case RTE_FLOW_ACTION_TYPE_VOID:
13536 case RTE_FLOW_ACTION_TYPE_COUNT:
13537 ret = flow_dv_query_count(dev, flow, data, error);
13539 case RTE_FLOW_ACTION_TYPE_AGE:
13540 ret = flow_dv_query_age(dev, flow, data, error);
13543 return rte_flow_error_set(error, ENOTSUP,
13544 RTE_FLOW_ERROR_TYPE_ACTION,
13546 "action not supported");
13553 * Destroy the meter table set.
13554 * Lock free, (mutex should be acquired by caller).
13557 * Pointer to Ethernet device.
13559 * Pointer to the meter table set.
13565 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13566 struct mlx5_meter_domains_infos *tbl)
13568 struct mlx5_priv *priv = dev->data->dev_private;
13569 struct mlx5_meter_domains_infos *mtd =
13570 (struct mlx5_meter_domains_infos *)tbl;
13572 if (!mtd || !priv->config.dv_flow_en)
13574 if (mtd->egress.tbl)
13575 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13576 if (mtd->egress.sfx_tbl)
13577 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13578 if (mtd->ingress.tbl)
13579 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13580 if (mtd->ingress.sfx_tbl)
13581 flow_dv_tbl_resource_release(MLX5_SH(dev),
13582 mtd->ingress.sfx_tbl);
13583 if (mtd->transfer.tbl)
13584 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13585 if (mtd->transfer.sfx_tbl)
13586 flow_dv_tbl_resource_release(MLX5_SH(dev),
13587 mtd->transfer.sfx_tbl);
13592 /* Number of meter flow actions, count and jump or count and drop. */
13593 #define METER_ACTIONS 2
13596 * Create specify domain meter table and suffix table.
13599 * Pointer to Ethernet device.
13600 * @param[in,out] mtb
13601 * Pointer to DV meter table set.
13602 * @param[in] egress
13604 * @param[in] transfer
13608 * 0 on success, -1 otherwise.
13611 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13612 struct mlx5_meter_domains_infos *mtb,
13613 uint8_t egress, uint8_t transfer)
13615 struct rte_flow_error error;
13616 struct mlx5_meter_domain_info *dtb;
13619 dtb = &mtb->transfer;
13621 dtb = &mtb->egress;
13623 dtb = &mtb->ingress;
13624 /* Create the meter table with METER level. */
13625 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13626 egress, transfer, false, NULL, 0,
13629 DRV_LOG(ERR, "Failed to create meter policer table.");
13632 /* Create the meter suffix table with SUFFIX level. */
13633 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13634 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13635 egress, transfer, false, NULL, 0,
13637 if (!dtb->sfx_tbl) {
13638 DRV_LOG(ERR, "Failed to create meter suffix table.");
13645 * Create the needed meter and suffix tables.
13646 * Lock free, (mutex should be acquired by caller).
13649 * Pointer to Ethernet device.
13652 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13654 static struct mlx5_meter_domains_infos *
13655 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13657 struct mlx5_priv *priv = dev->data->dev_private;
13658 struct mlx5_meter_domains_infos *mtb;
13661 if (!priv->mtr_en) {
13662 rte_errno = ENOTSUP;
13665 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13667 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13670 /* Egress meter table. */
13671 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13673 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13676 /* Ingress meter table. */
13677 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13679 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13682 /* FDB meter table. */
13683 if (priv->config.dv_esw_en) {
13684 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13686 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13692 flow_dv_destroy_mtr_tbl(dev, mtb);
13697 * Validate the batch counter support in root table.
13699 * Create a simple flow with invalid counter and drop action on root table to
13700 * validate if batch counter with offset on root table is supported or not.
13703 * Pointer to rte_eth_dev structure.
13706 * 0 on success, a negative errno value otherwise and rte_errno is set.
13709 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13711 struct mlx5_priv *priv = dev->data->dev_private;
13712 struct mlx5_dev_ctx_shared *sh = priv->sh;
13713 struct mlx5_flow_dv_match_params mask = {
13714 .size = sizeof(mask.buf),
13716 struct mlx5_flow_dv_match_params value = {
13717 .size = sizeof(value.buf),
13719 struct mlx5dv_flow_matcher_attr dv_attr = {
13720 .type = IBV_FLOW_ATTR_NORMAL,
13722 .match_criteria_enable = 0,
13723 .match_mask = (void *)&mask,
13725 void *actions[2] = { 0 };
13726 struct mlx5_flow_tbl_resource *tbl = NULL;
13727 struct mlx5_devx_obj *dcs = NULL;
13728 void *matcher = NULL;
13732 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
13736 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13739 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13743 actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13744 priv->drop_queue.hrxq->action;
13745 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13746 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13750 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13754 * If batch counter with offset is not supported, the driver will not
13755 * validate the invalid offset value, flow create should success.
13756 * In this case, it means batch counter is not supported in root table.
13758 * Otherwise, if flow create is failed, counter offset is supported.
13761 DRV_LOG(INFO, "Batch counter is not supported in root "
13762 "table. Switch to fallback mode.");
13763 rte_errno = ENOTSUP;
13765 claim_zero(mlx5_flow_os_destroy_flow(flow));
13767 /* Check matcher to make sure validate fail at flow create. */
13768 if (!matcher || (matcher && errno != EINVAL))
13769 DRV_LOG(ERR, "Unexpected error in counter offset "
13770 "support detection");
13774 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13776 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13778 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13780 claim_zero(mlx5_devx_cmd_destroy(dcs));
13785 * Query a devx counter.
13788 * Pointer to the Ethernet device structure.
13790 * Index to the flow counter.
13792 * Set to clear the counter statistics.
13794 * The statistics value of packets.
13795 * @param[out] bytes
13796 * The statistics value of bytes.
13799 * 0 on success, otherwise return -1.
13802 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13803 uint64_t *pkts, uint64_t *bytes)
13805 struct mlx5_priv *priv = dev->data->dev_private;
13806 struct mlx5_flow_counter *cnt;
13807 uint64_t inn_pkts, inn_bytes;
13810 if (!priv->config.devx)
13813 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13816 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13817 *pkts = inn_pkts - cnt->hits;
13818 *bytes = inn_bytes - cnt->bytes;
13820 cnt->hits = inn_pkts;
13821 cnt->bytes = inn_bytes;
13827 * Get aged-out flows.
13830 * Pointer to the Ethernet device structure.
13831 * @param[in] context
13832 * The address of an array of pointers to the aged-out flows contexts.
13833 * @param[in] nb_contexts
13834 * The length of context array pointers.
13835 * @param[out] error
13836 * Perform verbose error reporting if not NULL. Initialized in case of
13840 * how many contexts get in success, otherwise negative errno value.
13841 * if nb_contexts is 0, return the amount of all aged contexts.
13842 * if nb_contexts is not 0 , return the amount of aged flows reported
13843 * in the context array.
13844 * @note: only stub for now
13847 flow_get_aged_flows(struct rte_eth_dev *dev,
13849 uint32_t nb_contexts,
13850 struct rte_flow_error *error)
13852 struct mlx5_priv *priv = dev->data->dev_private;
13853 struct mlx5_age_info *age_info;
13854 struct mlx5_age_param *age_param;
13855 struct mlx5_flow_counter *counter;
13856 struct mlx5_aso_age_action *act;
13859 if (nb_contexts && !context)
13860 return rte_flow_error_set(error, EINVAL,
13861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13862 NULL, "empty context");
13863 age_info = GET_PORT_AGE_INFO(priv);
13864 rte_spinlock_lock(&age_info->aged_sl);
13865 LIST_FOREACH(act, &age_info->aged_aso, next) {
13868 context[nb_flows - 1] =
13869 act->age_params.context;
13870 if (!(--nb_contexts))
13874 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13877 age_param = MLX5_CNT_TO_AGE(counter);
13878 context[nb_flows - 1] = age_param->context;
13879 if (!(--nb_contexts))
13883 rte_spinlock_unlock(&age_info->aged_sl);
13884 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13889 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13892 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13894 return flow_dv_counter_alloc(dev, 0);
13898 * Validate indirect action.
13899 * Dispatcher for action type specific validation.
13902 * Pointer to the Ethernet device structure.
13904 * Shared action configuration.
13905 * @param[in] action
13906 * The indirect action object to validate.
13907 * @param[out] error
13908 * Perform verbose error reporting if not NULL. Initialized in case of
13912 * 0 on success, otherwise negative errno value.
13915 flow_dv_action_validate(struct rte_eth_dev *dev,
13916 const struct rte_flow_indir_action_conf *conf,
13917 const struct rte_flow_action *action,
13918 struct rte_flow_error *err)
13920 struct mlx5_priv *priv = dev->data->dev_private;
13922 RTE_SET_USED(conf);
13923 switch (action->type) {
13924 case RTE_FLOW_ACTION_TYPE_RSS:
13926 * priv->obj_ops is set according to driver capabilities.
13927 * When DevX capabilities are
13928 * sufficient, it is set to devx_obj_ops.
13929 * Otherwise, it is set to ibv_obj_ops.
13930 * ibv_obj_ops doesn't support ind_table_modify operation.
13931 * In this case the shared RSS action can't be used.
13933 if (priv->obj_ops.ind_table_modify == NULL)
13934 return rte_flow_error_set
13936 RTE_FLOW_ERROR_TYPE_ACTION,
13938 "shared RSS action not supported");
13939 return mlx5_validate_action_rss(dev, action, err);
13940 case RTE_FLOW_ACTION_TYPE_AGE:
13941 if (!priv->sh->aso_age_mng)
13942 return rte_flow_error_set(err, ENOTSUP,
13943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13945 "shared age action not supported");
13946 return flow_dv_validate_action_age(0, action, dev, err);
13948 return rte_flow_error_set(err, ENOTSUP,
13949 RTE_FLOW_ERROR_TYPE_ACTION,
13951 "action type not supported");
13956 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13958 struct mlx5_priv *priv = dev->data->dev_private;
13961 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13962 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13967 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13968 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13972 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13973 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13980 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13981 .validate = flow_dv_validate,
13982 .prepare = flow_dv_prepare,
13983 .translate = flow_dv_translate,
13984 .apply = flow_dv_apply,
13985 .remove = flow_dv_remove,
13986 .destroy = flow_dv_destroy,
13987 .query = flow_dv_query,
13988 .create_mtr_tbls = flow_dv_create_mtr_tbl,
13989 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13990 .create_meter = flow_dv_mtr_alloc,
13991 .free_meter = flow_dv_aso_mtr_release_to_pool,
13992 .counter_alloc = flow_dv_counter_allocate,
13993 .counter_free = flow_dv_counter_free,
13994 .counter_query = flow_dv_counter_query,
13995 .get_aged_flows = flow_get_aged_flows,
13996 .action_validate = flow_dv_action_validate,
13997 .action_create = flow_dv_action_create,
13998 .action_destroy = flow_dv_action_destroy,
13999 .action_update = flow_dv_action_update,
14000 .action_query = flow_dv_action_query,
14001 .sync_domain = flow_dv_sync_domain,
14004 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */