1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_d_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_A] = MLX5_MODI_META_DATA_REG_A,
836 [REG_B] = MLX5_MODI_META_DATA_REG_B,
837 [REG_C_0] = MLX5_MODI_META_REG_C_0,
838 [REG_C_1] = MLX5_MODI_META_REG_C_1,
839 [REG_C_2] = MLX5_MODI_META_REG_C_2,
840 [REG_C_3] = MLX5_MODI_META_REG_C_3,
841 [REG_C_4] = MLX5_MODI_META_REG_C_4,
842 [REG_C_5] = MLX5_MODI_META_REG_C_5,
843 [REG_C_6] = MLX5_MODI_META_REG_C_6,
844 [REG_C_7] = MLX5_MODI_META_REG_C_7,
848 * Convert register set to DV specification.
850 * @param[in,out] resource
851 * Pointer to the modify-header resource.
853 * Pointer to action specification.
855 * Pointer to the error structure.
858 * 0 on success, a negative errno value otherwise and rte_errno is set.
861 flow_dv_convert_action_set_reg
862 (struct mlx5_flow_dv_modify_hdr_resource *resource,
863 const struct rte_flow_action *action,
864 struct rte_flow_error *error)
866 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
867 struct mlx5_modification_cmd *actions = resource->actions;
868 uint32_t i = resource->actions_num;
870 if (i >= MLX5_MODIFY_NUM)
871 return rte_flow_error_set(error, EINVAL,
872 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
873 "too many items to modify");
874 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
875 actions[i].field = reg_to_field[conf->id];
876 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
877 actions[i].data1 = conf->data;
879 resource->actions_num = i;
880 if (!resource->actions_num)
881 return rte_flow_error_set(error, EINVAL,
882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
883 "invalid modification flow item");
888 * Convert internal COPY_REG action to DV specification.
891 * Pointer to the rte_eth_dev structure.
893 * Pointer to the modify-header resource.
895 * Pointer to action specification.
897 * Pointer to the error structure.
900 * 0 on success, a negative errno value otherwise and rte_errno is set.
903 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev __rte_unused,
904 struct mlx5_flow_dv_modify_hdr_resource *res,
905 const struct rte_flow_action *action,
906 struct rte_flow_error *error)
908 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
909 uint32_t mask = RTE_BE32(UINT32_MAX);
910 struct rte_flow_item item = {
914 struct field_modify_info reg_src[] = {
915 {4, 0, reg_to_field[conf->src]},
918 struct field_modify_info reg_dst = {
919 .offset = (uint32_t)-1, /* Same as src. */
920 .id = reg_to_field[conf->dst],
922 return flow_dv_convert_modify_action(&item,
923 reg_src, ®_dst, res,
924 MLX5_MODIFICATION_TYPE_COPY,
929 * Validate META item.
932 * Pointer to the rte_eth_dev structure.
934 * Item specification.
936 * Attributes of flow that includes this item.
938 * Pointer to error structure.
941 * 0 on success, a negative errno value otherwise and rte_errno is set.
944 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
945 const struct rte_flow_item *item,
946 const struct rte_flow_attr *attr,
947 struct rte_flow_error *error)
949 const struct rte_flow_item_meta *spec = item->spec;
950 const struct rte_flow_item_meta *mask = item->mask;
951 const struct rte_flow_item_meta nic_mask = {
957 return rte_flow_error_set(error, EINVAL,
958 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
960 "data cannot be empty");
962 return rte_flow_error_set(error, EINVAL,
963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
965 "data cannot be zero");
967 mask = &rte_flow_item_meta_mask;
968 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
969 (const uint8_t *)&nic_mask,
970 sizeof(struct rte_flow_item_meta),
975 return rte_flow_error_set(error, ENOTSUP,
976 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
978 "pattern not supported for ingress");
983 * Validate vport item.
986 * Pointer to the rte_eth_dev structure.
988 * Item specification.
990 * Attributes of flow that includes this item.
991 * @param[in] item_flags
992 * Bit-fields that holds the items detected until now.
994 * Pointer to error structure.
997 * 0 on success, a negative errno value otherwise and rte_errno is set.
1000 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1001 const struct rte_flow_item *item,
1002 const struct rte_flow_attr *attr,
1003 uint64_t item_flags,
1004 struct rte_flow_error *error)
1006 const struct rte_flow_item_port_id *spec = item->spec;
1007 const struct rte_flow_item_port_id *mask = item->mask;
1008 const struct rte_flow_item_port_id switch_mask = {
1011 struct mlx5_priv *esw_priv;
1012 struct mlx5_priv *dev_priv;
1015 if (!attr->transfer)
1016 return rte_flow_error_set(error, EINVAL,
1017 RTE_FLOW_ERROR_TYPE_ITEM,
1019 "match on port id is valid only"
1020 " when transfer flag is enabled");
1021 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1022 return rte_flow_error_set(error, ENOTSUP,
1023 RTE_FLOW_ERROR_TYPE_ITEM, item,
1024 "multiple source ports are not"
1027 mask = &switch_mask;
1028 if (mask->id != 0xffffffff)
1029 return rte_flow_error_set(error, ENOTSUP,
1030 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1032 "no support for partial mask on"
1034 ret = mlx5_flow_item_acceptable
1035 (item, (const uint8_t *)mask,
1036 (const uint8_t *)&rte_flow_item_port_id_mask,
1037 sizeof(struct rte_flow_item_port_id),
1043 esw_priv = mlx5_port_to_eswitch_info(spec->id);
1045 return rte_flow_error_set(error, rte_errno,
1046 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1047 "failed to obtain E-Switch info for"
1049 dev_priv = mlx5_dev_to_eswitch_info(dev);
1051 return rte_flow_error_set(error, rte_errno,
1052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1054 "failed to obtain E-Switch info");
1055 if (esw_priv->domain_id != dev_priv->domain_id)
1056 return rte_flow_error_set(error, EINVAL,
1057 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1058 "cannot match on a port from a"
1059 " different E-Switch");
1064 * Validate the pop VLAN action.
1067 * Pointer to the rte_eth_dev structure.
1068 * @param[in] action_flags
1069 * Holds the actions detected until now.
1071 * Pointer to the pop vlan action.
1072 * @param[in] item_flags
1073 * The items found in this flow rule.
1075 * Pointer to flow attributes.
1077 * Pointer to error structure.
1080 * 0 on success, a negative errno value otherwise and rte_errno is set.
1083 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1084 uint64_t action_flags,
1085 const struct rte_flow_action *action,
1086 uint64_t item_flags,
1087 const struct rte_flow_attr *attr,
1088 struct rte_flow_error *error)
1090 struct mlx5_priv *priv = dev->data->dev_private;
1094 if (!priv->sh->pop_vlan_action)
1095 return rte_flow_error_set(error, ENOTSUP,
1096 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1098 "pop vlan action is not supported");
1100 * Check for inconsistencies:
1101 * fail strip_vlan in a flow that matches packets without VLAN tags.
1102 * fail strip_vlan in a flow that matches packets without explicitly a
1103 * matching on VLAN tag ?
1105 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1106 return rte_flow_error_set(error, ENOTSUP,
1107 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1109 "no support for multiple vlan pop "
1111 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1112 return rte_flow_error_set(error, ENOTSUP,
1113 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1115 "cannot pop vlan without a "
1116 "match on (outer) vlan in the flow");
1117 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1118 return rte_flow_error_set(error, EINVAL,
1119 RTE_FLOW_ERROR_TYPE_ACTION, action,
1120 "wrong action order, port_id should "
1121 "be after pop VLAN action");
1126 * Get VLAN default info from vlan match info.
1129 * Pointer to the rte_eth_dev structure.
1131 * the list of item specifications.
1133 * pointer VLAN info to fill to.
1135 * Pointer to error structure.
1138 * 0 on success, a negative errno value otherwise and rte_errno is set.
1141 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1142 struct rte_vlan_hdr *vlan)
1144 const struct rte_flow_item_vlan nic_mask = {
1145 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1146 MLX5DV_FLOW_VLAN_VID_MASK),
1147 .inner_type = RTE_BE16(0xffff),
1152 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1153 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1155 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1156 const struct rte_flow_item_vlan *vlan_m = items->mask;
1157 const struct rte_flow_item_vlan *vlan_v = items->spec;
1161 /* Only full match values are accepted */
1162 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1163 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1164 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1166 rte_be_to_cpu_16(vlan_v->tci &
1167 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1169 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1170 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1171 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1173 rte_be_to_cpu_16(vlan_v->tci &
1174 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1176 if (vlan_m->inner_type == nic_mask.inner_type)
1177 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1178 vlan_m->inner_type);
1183 * Validate the push VLAN action.
1185 * @param[in] action_flags
1186 * Holds the actions detected until now.
1188 * Pointer to the encap action.
1190 * Pointer to flow attributes
1192 * Pointer to error structure.
1195 * 0 on success, a negative errno value otherwise and rte_errno is set.
1198 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1199 uint64_t item_flags,
1200 const struct rte_flow_action *action,
1201 const struct rte_flow_attr *attr,
1202 struct rte_flow_error *error)
1204 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1206 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1207 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1208 return rte_flow_error_set(error, EINVAL,
1209 RTE_FLOW_ERROR_TYPE_ACTION, action,
1210 "invalid vlan ethertype");
1212 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1213 return rte_flow_error_set(error, ENOTSUP,
1214 RTE_FLOW_ERROR_TYPE_ACTION, action,
1215 "no support for multiple VLAN "
1217 if (!mlx5_flow_find_action
1218 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1219 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1220 return rte_flow_error_set(error, ENOTSUP,
1221 RTE_FLOW_ERROR_TYPE_ACTION, action,
1222 "push VLAN needs to match on VLAN in order to "
1223 "get VLAN VID information because there is "
1224 "no followed set VLAN VID action");
1225 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1226 return rte_flow_error_set(error, EINVAL,
1227 RTE_FLOW_ERROR_TYPE_ACTION, action,
1228 "wrong action order, port_id should "
1229 "be after push VLAN");
1235 * Validate the set VLAN PCP.
1237 * @param[in] action_flags
1238 * Holds the actions detected until now.
1239 * @param[in] actions
1240 * Pointer to the list of actions remaining in the flow rule.
1242 * Pointer to flow attributes
1244 * Pointer to error structure.
1247 * 0 on success, a negative errno value otherwise and rte_errno is set.
1250 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1251 const struct rte_flow_action actions[],
1252 struct rte_flow_error *error)
1254 const struct rte_flow_action *action = actions;
1255 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1257 if (conf->vlan_pcp > 7)
1258 return rte_flow_error_set(error, EINVAL,
1259 RTE_FLOW_ERROR_TYPE_ACTION, action,
1260 "VLAN PCP value is too big");
1261 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1262 return rte_flow_error_set(error, ENOTSUP,
1263 RTE_FLOW_ERROR_TYPE_ACTION, action,
1264 "set VLAN PCP action must follow "
1265 "the push VLAN action");
1266 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1267 return rte_flow_error_set(error, ENOTSUP,
1268 RTE_FLOW_ERROR_TYPE_ACTION, action,
1269 "Multiple VLAN PCP modification are "
1271 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1272 return rte_flow_error_set(error, EINVAL,
1273 RTE_FLOW_ERROR_TYPE_ACTION, action,
1274 "wrong action order, port_id should "
1275 "be after set VLAN PCP");
1280 * Validate the set VLAN VID.
1282 * @param[in] item_flags
1283 * Holds the items detected in this rule.
1284 * @param[in] actions
1285 * Pointer to the list of actions remaining in the flow rule.
1287 * Pointer to flow attributes
1289 * Pointer to error structure.
1292 * 0 on success, a negative errno value otherwise and rte_errno is set.
1295 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1296 uint64_t action_flags,
1297 const struct rte_flow_action actions[],
1298 struct rte_flow_error *error)
1300 const struct rte_flow_action *action = actions;
1301 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1303 if (conf->vlan_vid > RTE_BE16(0xFFE))
1304 return rte_flow_error_set(error, EINVAL,
1305 RTE_FLOW_ERROR_TYPE_ACTION, action,
1306 "VLAN VID value is too big");
1307 /* there is an of_push_vlan action before us */
1308 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1309 if (mlx5_flow_find_action(actions + 1,
1310 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1311 return rte_flow_error_set(error, ENOTSUP,
1312 RTE_FLOW_ERROR_TYPE_ACTION, action,
1313 "Multiple VLAN VID modifications are "
1320 * Action is on an existing VLAN header:
1321 * Need to verify this is a single modify CID action.
1322 * Rule mast include a match on outer VLAN.
1324 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1325 return rte_flow_error_set(error, ENOTSUP,
1326 RTE_FLOW_ERROR_TYPE_ACTION, action,
1327 "Multiple VLAN VID modifications are "
1329 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1330 return rte_flow_error_set(error, EINVAL,
1331 RTE_FLOW_ERROR_TYPE_ACTION, action,
1332 "match on VLAN is required in order "
1334 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1335 return rte_flow_error_set(error, EINVAL,
1336 RTE_FLOW_ERROR_TYPE_ACTION, action,
1337 "wrong action order, port_id should "
1338 "be after set VLAN VID");
1343 * Validate count action.
1348 * Pointer to error structure.
1351 * 0 on success, a negative errno value otherwise and rte_errno is set.
1354 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1355 struct rte_flow_error *error)
1357 struct mlx5_priv *priv = dev->data->dev_private;
1359 if (!priv->config.devx)
1361 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1365 return rte_flow_error_set
1367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1369 "count action not supported");
1373 * Validate the L2 encap action.
1375 * @param[in] action_flags
1376 * Holds the actions detected until now.
1378 * Pointer to the encap action.
1380 * Pointer to flow attributes
1382 * Pointer to error structure.
1385 * 0 on success, a negative errno value otherwise and rte_errno is set.
1388 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1389 const struct rte_flow_action *action,
1390 const struct rte_flow_attr *attr,
1391 struct rte_flow_error *error)
1393 if (!(action->conf))
1394 return rte_flow_error_set(error, EINVAL,
1395 RTE_FLOW_ERROR_TYPE_ACTION, action,
1396 "configuration cannot be null");
1397 if (action_flags & MLX5_FLOW_ACTION_DROP)
1398 return rte_flow_error_set(error, EINVAL,
1399 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1400 "can't drop and encap in same flow");
1401 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1402 return rte_flow_error_set(error, EINVAL,
1403 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1404 "can only have a single encap or"
1405 " decap action in a flow");
1406 if (!attr->transfer && attr->ingress)
1407 return rte_flow_error_set(error, ENOTSUP,
1408 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1410 "encap action not supported for "
1416 * Validate the L2 decap action.
1418 * @param[in] action_flags
1419 * Holds the actions detected until now.
1421 * Pointer to flow attributes
1423 * Pointer to error structure.
1426 * 0 on success, a negative errno value otherwise and rte_errno is set.
1429 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1430 const struct rte_flow_attr *attr,
1431 struct rte_flow_error *error)
1433 if (action_flags & MLX5_FLOW_ACTION_DROP)
1434 return rte_flow_error_set(error, EINVAL,
1435 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1436 "can't drop and decap in same flow");
1437 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1438 return rte_flow_error_set(error, EINVAL,
1439 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1440 "can only have a single encap or"
1441 " decap action in a flow");
1442 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1443 return rte_flow_error_set(error, EINVAL,
1444 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1445 "can't have decap action after"
1448 return rte_flow_error_set(error, ENOTSUP,
1449 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1451 "decap action not supported for "
1457 * Validate the raw encap action.
1459 * @param[in] action_flags
1460 * Holds the actions detected until now.
1462 * Pointer to the encap action.
1464 * Pointer to flow attributes
1466 * Pointer to error structure.
1469 * 0 on success, a negative errno value otherwise and rte_errno is set.
1472 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1473 const struct rte_flow_action *action,
1474 const struct rte_flow_attr *attr,
1475 struct rte_flow_error *error)
1477 const struct rte_flow_action_raw_encap *raw_encap =
1478 (const struct rte_flow_action_raw_encap *)action->conf;
1479 if (!(action->conf))
1480 return rte_flow_error_set(error, EINVAL,
1481 RTE_FLOW_ERROR_TYPE_ACTION, action,
1482 "configuration cannot be null");
1483 if (action_flags & MLX5_FLOW_ACTION_DROP)
1484 return rte_flow_error_set(error, EINVAL,
1485 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1486 "can't drop and encap in same flow");
1487 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1488 return rte_flow_error_set(error, EINVAL,
1489 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1490 "can only have a single encap"
1491 " action in a flow");
1492 /* encap without preceding decap is not supported for ingress */
1493 if (!attr->transfer && attr->ingress &&
1494 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1495 return rte_flow_error_set(error, ENOTSUP,
1496 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1498 "encap action not supported for "
1500 if (!raw_encap->size || !raw_encap->data)
1501 return rte_flow_error_set(error, EINVAL,
1502 RTE_FLOW_ERROR_TYPE_ACTION, action,
1503 "raw encap data cannot be empty");
1508 * Validate the raw decap action.
1510 * @param[in] action_flags
1511 * Holds the actions detected until now.
1513 * Pointer to the encap action.
1515 * Pointer to flow attributes
1517 * Pointer to error structure.
1520 * 0 on success, a negative errno value otherwise and rte_errno is set.
1523 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1524 const struct rte_flow_action *action,
1525 const struct rte_flow_attr *attr,
1526 struct rte_flow_error *error)
1528 if (action_flags & MLX5_FLOW_ACTION_DROP)
1529 return rte_flow_error_set(error, EINVAL,
1530 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1531 "can't drop and decap in same flow");
1532 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1533 return rte_flow_error_set(error, EINVAL,
1534 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1535 "can't have encap action before"
1537 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1538 return rte_flow_error_set(error, EINVAL,
1539 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1540 "can only have a single decap"
1541 " action in a flow");
1542 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1543 return rte_flow_error_set(error, EINVAL,
1544 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1545 "can't have decap action after"
1547 /* decap action is valid on egress only if it is followed by encap */
1549 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1550 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1553 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1554 return rte_flow_error_set
1556 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1557 NULL, "decap action not supported"
1564 * Find existing encap/decap resource or create and register a new one.
1566 * @param dev[in, out]
1567 * Pointer to rte_eth_dev structure.
1568 * @param[in, out] resource
1569 * Pointer to encap/decap resource.
1570 * @parm[in, out] dev_flow
1571 * Pointer to the dev_flow.
1573 * pointer to error structure.
1576 * 0 on success otherwise -errno and errno is set.
1579 flow_dv_encap_decap_resource_register
1580 (struct rte_eth_dev *dev,
1581 struct mlx5_flow_dv_encap_decap_resource *resource,
1582 struct mlx5_flow *dev_flow,
1583 struct rte_flow_error *error)
1585 struct mlx5_priv *priv = dev->data->dev_private;
1586 struct mlx5_ibv_shared *sh = priv->sh;
1587 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1588 struct mlx5dv_dr_domain *domain;
1590 resource->flags = dev_flow->group ? 0 : 1;
1591 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1592 domain = sh->fdb_domain;
1593 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1594 domain = sh->rx_domain;
1596 domain = sh->tx_domain;
1598 /* Lookup a matching resource from cache. */
1599 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1600 if (resource->reformat_type == cache_resource->reformat_type &&
1601 resource->ft_type == cache_resource->ft_type &&
1602 resource->flags == cache_resource->flags &&
1603 resource->size == cache_resource->size &&
1604 !memcmp((const void *)resource->buf,
1605 (const void *)cache_resource->buf,
1607 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1608 (void *)cache_resource,
1609 rte_atomic32_read(&cache_resource->refcnt));
1610 rte_atomic32_inc(&cache_resource->refcnt);
1611 dev_flow->dv.encap_decap = cache_resource;
1615 /* Register new encap/decap resource. */
1616 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1617 if (!cache_resource)
1618 return rte_flow_error_set(error, ENOMEM,
1619 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1620 "cannot allocate resource memory");
1621 *cache_resource = *resource;
1622 cache_resource->verbs_action =
1623 mlx5_glue->dv_create_flow_action_packet_reformat
1624 (sh->ctx, cache_resource->reformat_type,
1625 cache_resource->ft_type, domain, cache_resource->flags,
1626 cache_resource->size,
1627 (cache_resource->size ? cache_resource->buf : NULL));
1628 if (!cache_resource->verbs_action) {
1629 rte_free(cache_resource);
1630 return rte_flow_error_set(error, ENOMEM,
1631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632 NULL, "cannot create action");
1634 rte_atomic32_init(&cache_resource->refcnt);
1635 rte_atomic32_inc(&cache_resource->refcnt);
1636 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1637 dev_flow->dv.encap_decap = cache_resource;
1638 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1639 (void *)cache_resource,
1640 rte_atomic32_read(&cache_resource->refcnt));
1645 * Find existing table jump resource or create and register a new one.
1647 * @param dev[in, out]
1648 * Pointer to rte_eth_dev structure.
1649 * @param[in, out] resource
1650 * Pointer to jump table resource.
1651 * @parm[in, out] dev_flow
1652 * Pointer to the dev_flow.
1654 * pointer to error structure.
1657 * 0 on success otherwise -errno and errno is set.
1660 flow_dv_jump_tbl_resource_register
1661 (struct rte_eth_dev *dev,
1662 struct mlx5_flow_dv_jump_tbl_resource *resource,
1663 struct mlx5_flow *dev_flow,
1664 struct rte_flow_error *error)
1666 struct mlx5_priv *priv = dev->data->dev_private;
1667 struct mlx5_ibv_shared *sh = priv->sh;
1668 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1670 /* Lookup a matching resource from cache. */
1671 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1672 if (resource->tbl == cache_resource->tbl) {
1673 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1674 (void *)cache_resource,
1675 rte_atomic32_read(&cache_resource->refcnt));
1676 rte_atomic32_inc(&cache_resource->refcnt);
1677 dev_flow->dv.jump = cache_resource;
1681 /* Register new jump table resource. */
1682 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1683 if (!cache_resource)
1684 return rte_flow_error_set(error, ENOMEM,
1685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1686 "cannot allocate resource memory");
1687 *cache_resource = *resource;
1688 cache_resource->action =
1689 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1690 (resource->tbl->obj);
1691 if (!cache_resource->action) {
1692 rte_free(cache_resource);
1693 return rte_flow_error_set(error, ENOMEM,
1694 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1695 NULL, "cannot create action");
1697 rte_atomic32_init(&cache_resource->refcnt);
1698 rte_atomic32_inc(&cache_resource->refcnt);
1699 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1700 dev_flow->dv.jump = cache_resource;
1701 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1702 (void *)cache_resource,
1703 rte_atomic32_read(&cache_resource->refcnt));
1708 * Find existing table port ID resource or create and register a new one.
1710 * @param dev[in, out]
1711 * Pointer to rte_eth_dev structure.
1712 * @param[in, out] resource
1713 * Pointer to port ID action resource.
1714 * @parm[in, out] dev_flow
1715 * Pointer to the dev_flow.
1717 * pointer to error structure.
1720 * 0 on success otherwise -errno and errno is set.
1723 flow_dv_port_id_action_resource_register
1724 (struct rte_eth_dev *dev,
1725 struct mlx5_flow_dv_port_id_action_resource *resource,
1726 struct mlx5_flow *dev_flow,
1727 struct rte_flow_error *error)
1729 struct mlx5_priv *priv = dev->data->dev_private;
1730 struct mlx5_ibv_shared *sh = priv->sh;
1731 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1733 /* Lookup a matching resource from cache. */
1734 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1735 if (resource->port_id == cache_resource->port_id) {
1736 DRV_LOG(DEBUG, "port id action resource resource %p: "
1738 (void *)cache_resource,
1739 rte_atomic32_read(&cache_resource->refcnt));
1740 rte_atomic32_inc(&cache_resource->refcnt);
1741 dev_flow->dv.port_id_action = cache_resource;
1745 /* Register new port id action resource. */
1746 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1747 if (!cache_resource)
1748 return rte_flow_error_set(error, ENOMEM,
1749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1750 "cannot allocate resource memory");
1751 *cache_resource = *resource;
1752 cache_resource->action =
1753 mlx5_glue->dr_create_flow_action_dest_vport
1754 (priv->sh->fdb_domain, resource->port_id);
1755 if (!cache_resource->action) {
1756 rte_free(cache_resource);
1757 return rte_flow_error_set(error, ENOMEM,
1758 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1759 NULL, "cannot create action");
1761 rte_atomic32_init(&cache_resource->refcnt);
1762 rte_atomic32_inc(&cache_resource->refcnt);
1763 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1764 dev_flow->dv.port_id_action = cache_resource;
1765 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1766 (void *)cache_resource,
1767 rte_atomic32_read(&cache_resource->refcnt));
1772 * Find existing push vlan resource or create and register a new one.
1774 * @param dev[in, out]
1775 * Pointer to rte_eth_dev structure.
1776 * @param[in, out] resource
1777 * Pointer to port ID action resource.
1778 * @parm[in, out] dev_flow
1779 * Pointer to the dev_flow.
1781 * pointer to error structure.
1784 * 0 on success otherwise -errno and errno is set.
1787 flow_dv_push_vlan_action_resource_register
1788 (struct rte_eth_dev *dev,
1789 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1790 struct mlx5_flow *dev_flow,
1791 struct rte_flow_error *error)
1793 struct mlx5_priv *priv = dev->data->dev_private;
1794 struct mlx5_ibv_shared *sh = priv->sh;
1795 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1796 struct mlx5dv_dr_domain *domain;
1798 /* Lookup a matching resource from cache. */
1799 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1800 if (resource->vlan_tag == cache_resource->vlan_tag &&
1801 resource->ft_type == cache_resource->ft_type) {
1802 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1804 (void *)cache_resource,
1805 rte_atomic32_read(&cache_resource->refcnt));
1806 rte_atomic32_inc(&cache_resource->refcnt);
1807 dev_flow->dv.push_vlan_res = cache_resource;
1811 /* Register new push_vlan action resource. */
1812 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1813 if (!cache_resource)
1814 return rte_flow_error_set(error, ENOMEM,
1815 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1816 "cannot allocate resource memory");
1817 *cache_resource = *resource;
1818 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1819 domain = sh->fdb_domain;
1820 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1821 domain = sh->rx_domain;
1823 domain = sh->tx_domain;
1824 cache_resource->action =
1825 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1826 resource->vlan_tag);
1827 if (!cache_resource->action) {
1828 rte_free(cache_resource);
1829 return rte_flow_error_set(error, ENOMEM,
1830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1831 NULL, "cannot create action");
1833 rte_atomic32_init(&cache_resource->refcnt);
1834 rte_atomic32_inc(&cache_resource->refcnt);
1835 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1836 dev_flow->dv.push_vlan_res = cache_resource;
1837 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1838 (void *)cache_resource,
1839 rte_atomic32_read(&cache_resource->refcnt));
1843 * Get the size of specific rte_flow_item_type
1845 * @param[in] item_type
1846 * Tested rte_flow_item_type.
1849 * sizeof struct item_type, 0 if void or irrelevant.
1852 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1856 switch (item_type) {
1857 case RTE_FLOW_ITEM_TYPE_ETH:
1858 retval = sizeof(struct rte_flow_item_eth);
1860 case RTE_FLOW_ITEM_TYPE_VLAN:
1861 retval = sizeof(struct rte_flow_item_vlan);
1863 case RTE_FLOW_ITEM_TYPE_IPV4:
1864 retval = sizeof(struct rte_flow_item_ipv4);
1866 case RTE_FLOW_ITEM_TYPE_IPV6:
1867 retval = sizeof(struct rte_flow_item_ipv6);
1869 case RTE_FLOW_ITEM_TYPE_UDP:
1870 retval = sizeof(struct rte_flow_item_udp);
1872 case RTE_FLOW_ITEM_TYPE_TCP:
1873 retval = sizeof(struct rte_flow_item_tcp);
1875 case RTE_FLOW_ITEM_TYPE_VXLAN:
1876 retval = sizeof(struct rte_flow_item_vxlan);
1878 case RTE_FLOW_ITEM_TYPE_GRE:
1879 retval = sizeof(struct rte_flow_item_gre);
1881 case RTE_FLOW_ITEM_TYPE_NVGRE:
1882 retval = sizeof(struct rte_flow_item_nvgre);
1884 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1885 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1887 case RTE_FLOW_ITEM_TYPE_MPLS:
1888 retval = sizeof(struct rte_flow_item_mpls);
1890 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1898 #define MLX5_ENCAP_IPV4_VERSION 0x40
1899 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1900 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1901 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1902 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1903 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1904 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1907 * Convert the encap action data from list of rte_flow_item to raw buffer
1910 * Pointer to rte_flow_item objects list.
1912 * Pointer to the output buffer.
1914 * Pointer to the output buffer size.
1916 * Pointer to the error structure.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1923 size_t *size, struct rte_flow_error *error)
1925 struct rte_ether_hdr *eth = NULL;
1926 struct rte_vlan_hdr *vlan = NULL;
1927 struct rte_ipv4_hdr *ipv4 = NULL;
1928 struct rte_ipv6_hdr *ipv6 = NULL;
1929 struct rte_udp_hdr *udp = NULL;
1930 struct rte_vxlan_hdr *vxlan = NULL;
1931 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1932 struct rte_gre_hdr *gre = NULL;
1934 size_t temp_size = 0;
1937 return rte_flow_error_set(error, EINVAL,
1938 RTE_FLOW_ERROR_TYPE_ACTION,
1939 NULL, "invalid empty data");
1940 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1941 len = flow_dv_get_item_len(items->type);
1942 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1943 return rte_flow_error_set(error, EINVAL,
1944 RTE_FLOW_ERROR_TYPE_ACTION,
1945 (void *)items->type,
1946 "items total size is too big"
1947 " for encap action");
1948 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1949 switch (items->type) {
1950 case RTE_FLOW_ITEM_TYPE_ETH:
1951 eth = (struct rte_ether_hdr *)&buf[temp_size];
1953 case RTE_FLOW_ITEM_TYPE_VLAN:
1954 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1956 return rte_flow_error_set(error, EINVAL,
1957 RTE_FLOW_ERROR_TYPE_ACTION,
1958 (void *)items->type,
1959 "eth header not found");
1960 if (!eth->ether_type)
1961 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1963 case RTE_FLOW_ITEM_TYPE_IPV4:
1964 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1966 return rte_flow_error_set(error, EINVAL,
1967 RTE_FLOW_ERROR_TYPE_ACTION,
1968 (void *)items->type,
1969 "neither eth nor vlan"
1971 if (vlan && !vlan->eth_proto)
1972 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1973 else if (eth && !eth->ether_type)
1974 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1975 if (!ipv4->version_ihl)
1976 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1977 MLX5_ENCAP_IPV4_IHL_MIN;
1978 if (!ipv4->time_to_live)
1979 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1981 case RTE_FLOW_ITEM_TYPE_IPV6:
1982 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1984 return rte_flow_error_set(error, EINVAL,
1985 RTE_FLOW_ERROR_TYPE_ACTION,
1986 (void *)items->type,
1987 "neither eth nor vlan"
1989 if (vlan && !vlan->eth_proto)
1990 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1991 else if (eth && !eth->ether_type)
1992 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1993 if (!ipv6->vtc_flow)
1995 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1996 if (!ipv6->hop_limits)
1997 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1999 case RTE_FLOW_ITEM_TYPE_UDP:
2000 udp = (struct rte_udp_hdr *)&buf[temp_size];
2002 return rte_flow_error_set(error, EINVAL,
2003 RTE_FLOW_ERROR_TYPE_ACTION,
2004 (void *)items->type,
2005 "ip header not found");
2006 if (ipv4 && !ipv4->next_proto_id)
2007 ipv4->next_proto_id = IPPROTO_UDP;
2008 else if (ipv6 && !ipv6->proto)
2009 ipv6->proto = IPPROTO_UDP;
2011 case RTE_FLOW_ITEM_TYPE_VXLAN:
2012 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2014 return rte_flow_error_set(error, EINVAL,
2015 RTE_FLOW_ERROR_TYPE_ACTION,
2016 (void *)items->type,
2017 "udp header not found");
2019 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2020 if (!vxlan->vx_flags)
2022 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2024 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2025 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2027 return rte_flow_error_set(error, EINVAL,
2028 RTE_FLOW_ERROR_TYPE_ACTION,
2029 (void *)items->type,
2030 "udp header not found");
2031 if (!vxlan_gpe->proto)
2032 return rte_flow_error_set(error, EINVAL,
2033 RTE_FLOW_ERROR_TYPE_ACTION,
2034 (void *)items->type,
2035 "next protocol not found");
2038 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2039 if (!vxlan_gpe->vx_flags)
2040 vxlan_gpe->vx_flags =
2041 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2043 case RTE_FLOW_ITEM_TYPE_GRE:
2044 case RTE_FLOW_ITEM_TYPE_NVGRE:
2045 gre = (struct rte_gre_hdr *)&buf[temp_size];
2047 return rte_flow_error_set(error, EINVAL,
2048 RTE_FLOW_ERROR_TYPE_ACTION,
2049 (void *)items->type,
2050 "next protocol not found");
2052 return rte_flow_error_set(error, EINVAL,
2053 RTE_FLOW_ERROR_TYPE_ACTION,
2054 (void *)items->type,
2055 "ip header not found");
2056 if (ipv4 && !ipv4->next_proto_id)
2057 ipv4->next_proto_id = IPPROTO_GRE;
2058 else if (ipv6 && !ipv6->proto)
2059 ipv6->proto = IPPROTO_GRE;
2061 case RTE_FLOW_ITEM_TYPE_VOID:
2064 return rte_flow_error_set(error, EINVAL,
2065 RTE_FLOW_ERROR_TYPE_ACTION,
2066 (void *)items->type,
2067 "unsupported item type");
2077 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2079 struct rte_ether_hdr *eth = NULL;
2080 struct rte_vlan_hdr *vlan = NULL;
2081 struct rte_ipv6_hdr *ipv6 = NULL;
2082 struct rte_udp_hdr *udp = NULL;
2086 eth = (struct rte_ether_hdr *)data;
2087 next_hdr = (char *)(eth + 1);
2088 proto = RTE_BE16(eth->ether_type);
2091 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2092 vlan = (struct rte_vlan_hdr *)next_hdr;
2093 proto = RTE_BE16(vlan->eth_proto);
2094 next_hdr += sizeof(struct rte_vlan_hdr);
2097 /* HW calculates IPv4 csum. no need to proceed */
2098 if (proto == RTE_ETHER_TYPE_IPV4)
2101 /* non IPv4/IPv6 header. not supported */
2102 if (proto != RTE_ETHER_TYPE_IPV6) {
2103 return rte_flow_error_set(error, ENOTSUP,
2104 RTE_FLOW_ERROR_TYPE_ACTION,
2105 NULL, "Cannot offload non IPv4/IPv6");
2108 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2110 /* ignore non UDP */
2111 if (ipv6->proto != IPPROTO_UDP)
2114 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2115 udp->dgram_cksum = 0;
2121 * Convert L2 encap action to DV specification.
2124 * Pointer to rte_eth_dev structure.
2126 * Pointer to action structure.
2127 * @param[in, out] dev_flow
2128 * Pointer to the mlx5_flow.
2129 * @param[in] transfer
2130 * Mark if the flow is E-Switch flow.
2132 * Pointer to the error structure.
2135 * 0 on success, a negative errno value otherwise and rte_errno is set.
2138 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2139 const struct rte_flow_action *action,
2140 struct mlx5_flow *dev_flow,
2142 struct rte_flow_error *error)
2144 const struct rte_flow_item *encap_data;
2145 const struct rte_flow_action_raw_encap *raw_encap_data;
2146 struct mlx5_flow_dv_encap_decap_resource res = {
2148 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2149 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2150 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2153 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2155 (const struct rte_flow_action_raw_encap *)action->conf;
2156 res.size = raw_encap_data->size;
2157 memcpy(res.buf, raw_encap_data->data, res.size);
2158 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2161 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2163 ((const struct rte_flow_action_vxlan_encap *)
2164 action->conf)->definition;
2167 ((const struct rte_flow_action_nvgre_encap *)
2168 action->conf)->definition;
2169 if (flow_dv_convert_encap_data(encap_data, res.buf,
2173 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2174 return rte_flow_error_set(error, EINVAL,
2175 RTE_FLOW_ERROR_TYPE_ACTION,
2176 NULL, "can't create L2 encap action");
2181 * Convert L2 decap action to DV specification.
2184 * Pointer to rte_eth_dev structure.
2185 * @param[in, out] dev_flow
2186 * Pointer to the mlx5_flow.
2187 * @param[in] transfer
2188 * Mark if the flow is E-Switch flow.
2190 * Pointer to the error structure.
2193 * 0 on success, a negative errno value otherwise and rte_errno is set.
2196 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2197 struct mlx5_flow *dev_flow,
2199 struct rte_flow_error *error)
2201 struct mlx5_flow_dv_encap_decap_resource res = {
2204 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2205 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2206 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2209 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2210 return rte_flow_error_set(error, EINVAL,
2211 RTE_FLOW_ERROR_TYPE_ACTION,
2212 NULL, "can't create L2 decap action");
2217 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2220 * Pointer to rte_eth_dev structure.
2222 * Pointer to action structure.
2223 * @param[in, out] dev_flow
2224 * Pointer to the mlx5_flow.
2226 * Pointer to the flow attributes.
2228 * Pointer to the error structure.
2231 * 0 on success, a negative errno value otherwise and rte_errno is set.
2234 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2235 const struct rte_flow_action *action,
2236 struct mlx5_flow *dev_flow,
2237 const struct rte_flow_attr *attr,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_action_raw_encap *encap_data;
2241 struct mlx5_flow_dv_encap_decap_resource res;
2243 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2244 res.size = encap_data->size;
2245 memcpy(res.buf, encap_data->data, res.size);
2246 res.reformat_type = attr->egress ?
2247 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2248 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2250 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2252 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2253 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2254 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION,
2257 NULL, "can't create encap action");
2262 * Create action push VLAN.
2265 * Pointer to rte_eth_dev structure.
2266 * @param[in] vlan_tag
2267 * the vlan tag to push to the Ethernet header.
2268 * @param[in, out] dev_flow
2269 * Pointer to the mlx5_flow.
2271 * Pointer to the flow attributes.
2273 * Pointer to the error structure.
2276 * 0 on success, a negative errno value otherwise and rte_errno is set.
2279 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2280 const struct rte_flow_attr *attr,
2281 const struct rte_vlan_hdr *vlan,
2282 struct mlx5_flow *dev_flow,
2283 struct rte_flow_error *error)
2285 struct mlx5_flow_dv_push_vlan_action_resource res;
2288 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2291 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2293 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2294 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2295 return flow_dv_push_vlan_action_resource_register
2296 (dev, &res, dev_flow, error);
2300 * Validate the modify-header actions.
2302 * @param[in] action_flags
2303 * Holds the actions detected until now.
2305 * Pointer to the modify action.
2307 * Pointer to error structure.
2310 * 0 on success, a negative errno value otherwise and rte_errno is set.
2313 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2314 const struct rte_flow_action *action,
2315 struct rte_flow_error *error)
2317 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2318 return rte_flow_error_set(error, EINVAL,
2319 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2320 NULL, "action configuration not set");
2321 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2322 return rte_flow_error_set(error, EINVAL,
2323 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2324 "can't have encap action before"
2330 * Validate the modify-header MAC address actions.
2332 * @param[in] action_flags
2333 * Holds the actions detected until now.
2335 * Pointer to the modify action.
2336 * @param[in] item_flags
2337 * Holds the items detected.
2339 * Pointer to error structure.
2342 * 0 on success, a negative errno value otherwise and rte_errno is set.
2345 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2346 const struct rte_flow_action *action,
2347 const uint64_t item_flags,
2348 struct rte_flow_error *error)
2352 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2354 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2355 return rte_flow_error_set(error, EINVAL,
2356 RTE_FLOW_ERROR_TYPE_ACTION,
2358 "no L2 item in pattern");
2364 * Validate the modify-header IPv4 address actions.
2366 * @param[in] action_flags
2367 * Holds the actions detected until now.
2369 * Pointer to the modify action.
2370 * @param[in] item_flags
2371 * Holds the items detected.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2380 const struct rte_flow_action *action,
2381 const uint64_t item_flags,
2382 struct rte_flow_error *error)
2386 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2388 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2389 return rte_flow_error_set(error, EINVAL,
2390 RTE_FLOW_ERROR_TYPE_ACTION,
2392 "no ipv4 item in pattern");
2398 * Validate the modify-header IPv6 address actions.
2400 * @param[in] action_flags
2401 * Holds the actions detected until now.
2403 * Pointer to the modify action.
2404 * @param[in] item_flags
2405 * Holds the items detected.
2407 * Pointer to error structure.
2410 * 0 on success, a negative errno value otherwise and rte_errno is set.
2413 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2414 const struct rte_flow_action *action,
2415 const uint64_t item_flags,
2416 struct rte_flow_error *error)
2420 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2422 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2423 return rte_flow_error_set(error, EINVAL,
2424 RTE_FLOW_ERROR_TYPE_ACTION,
2426 "no ipv6 item in pattern");
2432 * Validate the modify-header TP actions.
2434 * @param[in] action_flags
2435 * Holds the actions detected until now.
2437 * Pointer to the modify action.
2438 * @param[in] item_flags
2439 * Holds the items detected.
2441 * Pointer to error structure.
2444 * 0 on success, a negative errno value otherwise and rte_errno is set.
2447 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2448 const struct rte_flow_action *action,
2449 const uint64_t item_flags,
2450 struct rte_flow_error *error)
2454 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2456 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2457 return rte_flow_error_set(error, EINVAL,
2458 RTE_FLOW_ERROR_TYPE_ACTION,
2459 NULL, "no transport layer "
2466 * Validate the modify-header actions of increment/decrement
2467 * TCP Sequence-number.
2469 * @param[in] action_flags
2470 * Holds the actions detected until now.
2472 * Pointer to the modify action.
2473 * @param[in] item_flags
2474 * Holds the items detected.
2476 * Pointer to error structure.
2479 * 0 on success, a negative errno value otherwise and rte_errno is set.
2482 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2483 const struct rte_flow_action *action,
2484 const uint64_t item_flags,
2485 struct rte_flow_error *error)
2489 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2491 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2492 return rte_flow_error_set(error, EINVAL,
2493 RTE_FLOW_ERROR_TYPE_ACTION,
2494 NULL, "no TCP item in"
2496 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2497 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2498 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2499 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2500 return rte_flow_error_set(error, EINVAL,
2501 RTE_FLOW_ERROR_TYPE_ACTION,
2503 "cannot decrease and increase"
2504 " TCP sequence number"
2505 " at the same time");
2511 * Validate the modify-header actions of increment/decrement
2512 * TCP Acknowledgment number.
2514 * @param[in] action_flags
2515 * Holds the actions detected until now.
2517 * Pointer to the modify action.
2518 * @param[in] item_flags
2519 * Holds the items detected.
2521 * Pointer to error structure.
2524 * 0 on success, a negative errno value otherwise and rte_errno is set.
2527 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2528 const struct rte_flow_action *action,
2529 const uint64_t item_flags,
2530 struct rte_flow_error *error)
2534 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2536 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2537 return rte_flow_error_set(error, EINVAL,
2538 RTE_FLOW_ERROR_TYPE_ACTION,
2539 NULL, "no TCP item in"
2541 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2542 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2543 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2544 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2545 return rte_flow_error_set(error, EINVAL,
2546 RTE_FLOW_ERROR_TYPE_ACTION,
2548 "cannot decrease and increase"
2549 " TCP acknowledgment number"
2550 " at the same time");
2556 * Validate the modify-header TTL actions.
2558 * @param[in] action_flags
2559 * Holds the actions detected until now.
2561 * Pointer to the modify action.
2562 * @param[in] item_flags
2563 * Holds the items detected.
2565 * Pointer to error structure.
2568 * 0 on success, a negative errno value otherwise and rte_errno is set.
2571 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2572 const struct rte_flow_action *action,
2573 const uint64_t item_flags,
2574 struct rte_flow_error *error)
2578 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2580 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2581 return rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ACTION,
2584 "no IP protocol in pattern");
2590 * Validate jump action.
2593 * Pointer to the jump action.
2594 * @param[in] action_flags
2595 * Holds the actions detected until now.
2596 * @param[in] attributes
2597 * Pointer to flow attributes
2598 * @param[in] external
2599 * Action belongs to flow rule created by request external to PMD.
2601 * Pointer to error structure.
2604 * 0 on success, a negative errno value otherwise and rte_errno is set.
2607 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2608 uint64_t action_flags,
2609 const struct rte_flow_attr *attributes,
2610 bool external, struct rte_flow_error *error)
2612 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2614 uint32_t target_group, table;
2617 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2618 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2619 return rte_flow_error_set(error, EINVAL,
2620 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2621 "can't have 2 fate actions in"
2624 return rte_flow_error_set(error, EINVAL,
2625 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2626 NULL, "action configuration not set");
2628 ((const struct rte_flow_action_jump *)action->conf)->group;
2629 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2633 if (table >= max_group)
2634 return rte_flow_error_set(error, EINVAL,
2635 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2636 "target group index out of range");
2637 if (attributes->group >= target_group)
2638 return rte_flow_error_set(error, EINVAL,
2639 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2640 "target group must be higher than"
2641 " the current flow group");
2646 * Validate the port_id action.
2649 * Pointer to rte_eth_dev structure.
2650 * @param[in] action_flags
2651 * Bit-fields that holds the actions detected until now.
2653 * Port_id RTE action structure.
2655 * Attributes of flow that includes this action.
2657 * Pointer to error structure.
2660 * 0 on success, a negative errno value otherwise and rte_errno is set.
2663 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2664 uint64_t action_flags,
2665 const struct rte_flow_action *action,
2666 const struct rte_flow_attr *attr,
2667 struct rte_flow_error *error)
2669 const struct rte_flow_action_port_id *port_id;
2670 struct mlx5_priv *act_priv;
2671 struct mlx5_priv *dev_priv;
2674 if (!attr->transfer)
2675 return rte_flow_error_set(error, ENOTSUP,
2676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2678 "port id action is valid in transfer"
2680 if (!action || !action->conf)
2681 return rte_flow_error_set(error, ENOTSUP,
2682 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2684 "port id action parameters must be"
2686 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2687 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2688 return rte_flow_error_set(error, EINVAL,
2689 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2690 "can have only one fate actions in"
2692 dev_priv = mlx5_dev_to_eswitch_info(dev);
2694 return rte_flow_error_set(error, rte_errno,
2695 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2697 "failed to obtain E-Switch info");
2698 port_id = action->conf;
2699 port = port_id->original ? dev->data->port_id : port_id->id;
2700 act_priv = mlx5_port_to_eswitch_info(port);
2702 return rte_flow_error_set
2704 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2705 "failed to obtain E-Switch port id for port");
2706 if (act_priv->domain_id != dev_priv->domain_id)
2707 return rte_flow_error_set
2709 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2710 "port does not belong to"
2711 " E-Switch being configured");
2716 * Find existing modify-header resource or create and register a new one.
2718 * @param dev[in, out]
2719 * Pointer to rte_eth_dev structure.
2720 * @param[in, out] resource
2721 * Pointer to modify-header resource.
2722 * @parm[in, out] dev_flow
2723 * Pointer to the dev_flow.
2725 * pointer to error structure.
2728 * 0 on success otherwise -errno and errno is set.
2731 flow_dv_modify_hdr_resource_register
2732 (struct rte_eth_dev *dev,
2733 struct mlx5_flow_dv_modify_hdr_resource *resource,
2734 struct mlx5_flow *dev_flow,
2735 struct rte_flow_error *error)
2737 struct mlx5_priv *priv = dev->data->dev_private;
2738 struct mlx5_ibv_shared *sh = priv->sh;
2739 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2740 struct mlx5dv_dr_domain *ns;
2742 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2743 ns = sh->fdb_domain;
2744 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2749 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2750 /* Lookup a matching resource from cache. */
2751 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2752 if (resource->ft_type == cache_resource->ft_type &&
2753 resource->actions_num == cache_resource->actions_num &&
2754 resource->flags == cache_resource->flags &&
2755 !memcmp((const void *)resource->actions,
2756 (const void *)cache_resource->actions,
2757 (resource->actions_num *
2758 sizeof(resource->actions[0])))) {
2759 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2760 (void *)cache_resource,
2761 rte_atomic32_read(&cache_resource->refcnt));
2762 rte_atomic32_inc(&cache_resource->refcnt);
2763 dev_flow->dv.modify_hdr = cache_resource;
2767 /* Register new modify-header resource. */
2768 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2769 if (!cache_resource)
2770 return rte_flow_error_set(error, ENOMEM,
2771 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2772 "cannot allocate resource memory");
2773 *cache_resource = *resource;
2774 cache_resource->verbs_action =
2775 mlx5_glue->dv_create_flow_action_modify_header
2776 (sh->ctx, cache_resource->ft_type,
2777 ns, cache_resource->flags,
2778 cache_resource->actions_num *
2779 sizeof(cache_resource->actions[0]),
2780 (uint64_t *)cache_resource->actions);
2781 if (!cache_resource->verbs_action) {
2782 rte_free(cache_resource);
2783 return rte_flow_error_set(error, ENOMEM,
2784 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2785 NULL, "cannot create action");
2787 rte_atomic32_init(&cache_resource->refcnt);
2788 rte_atomic32_inc(&cache_resource->refcnt);
2789 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2790 dev_flow->dv.modify_hdr = cache_resource;
2791 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2792 (void *)cache_resource,
2793 rte_atomic32_read(&cache_resource->refcnt));
2797 #define MLX5_CNT_CONTAINER_RESIZE 64
2800 * Get or create a flow counter.
2803 * Pointer to the Ethernet device structure.
2805 * Indicate if this counter is shared with other flows.
2807 * Counter identifier.
2810 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2812 static struct mlx5_flow_counter *
2813 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2816 struct mlx5_priv *priv = dev->data->dev_private;
2817 struct mlx5_flow_counter *cnt = NULL;
2818 struct mlx5_devx_obj *dcs = NULL;
2820 if (!priv->config.devx) {
2821 rte_errno = ENOTSUP;
2825 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2826 if (cnt->shared && cnt->id == id) {
2832 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2835 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2837 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2841 struct mlx5_flow_counter tmpl = {
2847 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2849 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2855 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2860 * Release a flow counter.
2863 * Pointer to the Ethernet device structure.
2864 * @param[in] counter
2865 * Pointer to the counter handler.
2868 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2869 struct mlx5_flow_counter *counter)
2871 struct mlx5_priv *priv = dev->data->dev_private;
2875 if (--counter->ref_cnt == 0) {
2876 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2877 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2883 * Query a devx flow counter.
2886 * Pointer to the Ethernet device structure.
2888 * Pointer to the flow counter.
2890 * The statistics value of packets.
2892 * The statistics value of bytes.
2895 * 0 on success, otherwise a negative errno value and rte_errno is set.
2898 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2899 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2902 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2907 * Get a pool by a counter.
2910 * Pointer to the counter.
2915 static struct mlx5_flow_counter_pool *
2916 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2919 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2920 return (struct mlx5_flow_counter_pool *)cnt - 1;
2926 * Get a pool by devx counter ID.
2929 * Pointer to the counter container.
2931 * The counter devx ID.
2934 * The counter pool pointer if exists, NULL otherwise,
2936 static struct mlx5_flow_counter_pool *
2937 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2939 struct mlx5_flow_counter_pool *pool;
2941 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2942 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2943 MLX5_COUNTERS_PER_POOL;
2945 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2952 * Allocate a new memory for the counter values wrapped by all the needed
2956 * Pointer to the Ethernet device structure.
2958 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2961 * The new memory management pointer on success, otherwise NULL and rte_errno
2964 static struct mlx5_counter_stats_mem_mng *
2965 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2967 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2968 (dev->data->dev_private))->sh;
2969 struct mlx5_devx_mkey_attr mkey_attr;
2970 struct mlx5_counter_stats_mem_mng *mem_mng;
2971 volatile struct flow_counter_stats *raw_data;
2972 int size = (sizeof(struct flow_counter_stats) *
2973 MLX5_COUNTERS_PER_POOL +
2974 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2975 sizeof(struct mlx5_counter_stats_mem_mng);
2976 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2983 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2984 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2985 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2986 IBV_ACCESS_LOCAL_WRITE);
2987 if (!mem_mng->umem) {
2992 mkey_attr.addr = (uintptr_t)mem;
2993 mkey_attr.size = size;
2994 mkey_attr.umem_id = mem_mng->umem->umem_id;
2995 mkey_attr.pd = sh->pdn;
2996 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2998 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3003 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3004 raw_data = (volatile struct flow_counter_stats *)mem;
3005 for (i = 0; i < raws_n; ++i) {
3006 mem_mng->raws[i].mem_mng = mem_mng;
3007 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3009 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3014 * Resize a counter container.
3017 * Pointer to the Ethernet device structure.
3019 * Whether the pool is for counter that was allocated by batch command.
3022 * The new container pointer on success, otherwise NULL and rte_errno is set.
3024 static struct mlx5_pools_container *
3025 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3027 struct mlx5_priv *priv = dev->data->dev_private;
3028 struct mlx5_pools_container *cont =
3029 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3030 struct mlx5_pools_container *new_cont =
3031 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3032 struct mlx5_counter_stats_mem_mng *mem_mng;
3033 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3034 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3037 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3038 /* The last resize still hasn't detected by the host thread. */
3042 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3043 if (!new_cont->pools) {
3048 memcpy(new_cont->pools, cont->pools, cont->n *
3049 sizeof(struct mlx5_flow_counter_pool *));
3050 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3051 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3053 rte_free(new_cont->pools);
3056 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3057 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3058 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3060 new_cont->n = resize;
3061 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3062 TAILQ_INIT(&new_cont->pool_list);
3063 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3064 new_cont->init_mem_mng = mem_mng;
3066 /* Flip the master container. */
3067 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3072 * Query a devx flow counter.
3075 * Pointer to the Ethernet device structure.
3077 * Pointer to the flow counter.
3079 * The statistics value of packets.
3081 * The statistics value of bytes.
3084 * 0 on success, otherwise a negative errno value and rte_errno is set.
3087 _flow_dv_query_count(struct rte_eth_dev *dev,
3088 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3091 struct mlx5_priv *priv = dev->data->dev_private;
3092 struct mlx5_flow_counter_pool *pool =
3093 flow_dv_counter_pool_get(cnt);
3094 int offset = cnt - &pool->counters_raw[0];
3096 if (priv->counter_fallback)
3097 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3099 rte_spinlock_lock(&pool->sl);
3101 * The single counters allocation may allocate smaller ID than the
3102 * current allocated in parallel to the host reading.
3103 * In this case the new counter values must be reported as 0.
3105 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3109 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3110 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3112 rte_spinlock_unlock(&pool->sl);
3117 * Create and initialize a new counter pool.
3120 * Pointer to the Ethernet device structure.
3122 * The devX counter handle.
3124 * Whether the pool is for counter that was allocated by batch command.
3127 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3129 static struct mlx5_flow_counter_pool *
3130 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3133 struct mlx5_priv *priv = dev->data->dev_private;
3134 struct mlx5_flow_counter_pool *pool;
3135 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3137 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3140 if (cont->n == n_valid) {
3141 cont = flow_dv_container_resize(dev, batch);
3145 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3146 sizeof(struct mlx5_flow_counter);
3147 pool = rte_calloc(__func__, 1, size, 0);
3152 pool->min_dcs = dcs;
3153 pool->raw = cont->init_mem_mng->raws + n_valid %
3154 MLX5_CNT_CONTAINER_RESIZE;
3155 pool->raw_hw = NULL;
3156 rte_spinlock_init(&pool->sl);
3158 * The generation of the new allocated counters in this pool is 0, 2 in
3159 * the pool generation makes all the counters valid for allocation.
3161 rte_atomic64_set(&pool->query_gen, 0x2);
3162 TAILQ_INIT(&pool->counters);
3163 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3164 cont->pools[n_valid] = pool;
3165 /* Pool initialization must be updated before host thread access. */
3167 rte_atomic16_add(&cont->n_valid, 1);
3172 * Prepare a new counter and/or a new counter pool.
3175 * Pointer to the Ethernet device structure.
3176 * @param[out] cnt_free
3177 * Where to put the pointer of a new counter.
3179 * Whether the pool is for counter that was allocated by batch command.
3182 * The free counter pool pointer and @p cnt_free is set on success,
3183 * NULL otherwise and rte_errno is set.
3185 static struct mlx5_flow_counter_pool *
3186 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3187 struct mlx5_flow_counter **cnt_free,
3190 struct mlx5_priv *priv = dev->data->dev_private;
3191 struct mlx5_flow_counter_pool *pool;
3192 struct mlx5_devx_obj *dcs = NULL;
3193 struct mlx5_flow_counter *cnt;
3197 /* bulk_bitmap must be 0 for single counter allocation. */
3198 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3201 pool = flow_dv_find_pool_by_id
3202 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3204 pool = flow_dv_pool_create(dev, dcs, batch);
3206 mlx5_devx_cmd_destroy(dcs);
3209 } else if (dcs->id < pool->min_dcs->id) {
3210 rte_atomic64_set(&pool->a64_dcs,
3211 (int64_t)(uintptr_t)dcs);
3213 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3214 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3219 /* bulk_bitmap is in 128 counters units. */
3220 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3221 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3223 rte_errno = ENODATA;
3226 pool = flow_dv_pool_create(dev, dcs, batch);
3228 mlx5_devx_cmd_destroy(dcs);
3231 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3232 cnt = &pool->counters_raw[i];
3234 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3236 *cnt_free = &pool->counters_raw[0];
3241 * Search for existed shared counter.
3244 * Pointer to the relevant counter pool container.
3246 * The shared counter ID to search.
3249 * NULL if not existed, otherwise pointer to the shared counter.
3251 static struct mlx5_flow_counter *
3252 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3255 static struct mlx5_flow_counter *cnt;
3256 struct mlx5_flow_counter_pool *pool;
3259 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3260 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3261 cnt = &pool->counters_raw[i];
3262 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3270 * Allocate a flow counter.
3273 * Pointer to the Ethernet device structure.
3275 * Indicate if this counter is shared with other flows.
3277 * Counter identifier.
3279 * Counter flow group.
3282 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3284 static struct mlx5_flow_counter *
3285 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3288 struct mlx5_priv *priv = dev->data->dev_private;
3289 struct mlx5_flow_counter_pool *pool = NULL;
3290 struct mlx5_flow_counter *cnt_free = NULL;
3292 * Currently group 0 flow counter cannot be assigned to a flow if it is
3293 * not the first one in the batch counter allocation, so it is better
3294 * to allocate counters one by one for these flows in a separate
3296 * A counter can be shared between different groups so need to take
3297 * shared counters from the single container.
3299 uint32_t batch = (group && !shared) ? 1 : 0;
3300 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3303 if (priv->counter_fallback)
3304 return flow_dv_counter_alloc_fallback(dev, shared, id);
3305 if (!priv->config.devx) {
3306 rte_errno = ENOTSUP;
3310 cnt_free = flow_dv_counter_shared_search(cont, id);
3312 if (cnt_free->ref_cnt + 1 == 0) {
3316 cnt_free->ref_cnt++;
3320 /* Pools which has a free counters are in the start. */
3321 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3323 * The free counter reset values must be updated between the
3324 * counter release to the counter allocation, so, at least one
3325 * query must be done in this time. ensure it by saving the
3326 * query generation in the release time.
3327 * The free list is sorted according to the generation - so if
3328 * the first one is not updated, all the others are not
3331 cnt_free = TAILQ_FIRST(&pool->counters);
3332 if (cnt_free && cnt_free->query_gen + 1 <
3333 rte_atomic64_read(&pool->query_gen))
3338 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3342 cnt_free->batch = batch;
3343 /* Create a DV counter action only in the first time usage. */
3344 if (!cnt_free->action) {
3346 struct mlx5_devx_obj *dcs;
3349 offset = cnt_free - &pool->counters_raw[0];
3350 dcs = pool->min_dcs;
3353 dcs = cnt_free->dcs;
3355 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3357 if (!cnt_free->action) {
3362 /* Update the counter reset values. */
3363 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3366 cnt_free->shared = shared;
3367 cnt_free->ref_cnt = 1;
3369 if (!priv->sh->cmng.query_thread_on)
3370 /* Start the asynchronous batch query by the host thread. */
3371 mlx5_set_query_alarm(priv->sh);
3372 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3373 if (TAILQ_EMPTY(&pool->counters)) {
3374 /* Move the pool to the end of the container pool list. */
3375 TAILQ_REMOVE(&cont->pool_list, pool, next);
3376 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3382 * Release a flow counter.
3385 * Pointer to the Ethernet device structure.
3386 * @param[in] counter
3387 * Pointer to the counter handler.
3390 flow_dv_counter_release(struct rte_eth_dev *dev,
3391 struct mlx5_flow_counter *counter)
3393 struct mlx5_priv *priv = dev->data->dev_private;
3397 if (priv->counter_fallback) {
3398 flow_dv_counter_release_fallback(dev, counter);
3401 if (--counter->ref_cnt == 0) {
3402 struct mlx5_flow_counter_pool *pool =
3403 flow_dv_counter_pool_get(counter);
3405 /* Put the counter in the end - the last updated one. */
3406 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3407 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3412 * Verify the @p attributes will be correctly understood by the NIC and store
3413 * them in the @p flow if everything is correct.
3416 * Pointer to dev struct.
3417 * @param[in] attributes
3418 * Pointer to flow attributes
3419 * @param[in] external
3420 * This flow rule is created by request external to PMD.
3422 * Pointer to error structure.
3425 * 0 on success, a negative errno value otherwise and rte_errno is set.
3428 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3429 const struct rte_flow_attr *attributes,
3430 bool external __rte_unused,
3431 struct rte_flow_error *error)
3433 struct mlx5_priv *priv = dev->data->dev_private;
3434 uint32_t priority_max = priv->config.flow_prio - 1;
3436 #ifndef HAVE_MLX5DV_DR
3437 if (attributes->group)
3438 return rte_flow_error_set(error, ENOTSUP,
3439 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3441 "groups are not supported");
3443 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3448 ret = mlx5_flow_group_to_table(attributes, external,
3453 if (table >= max_group)
3454 return rte_flow_error_set(error, EINVAL,
3455 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3456 "group index out of range");
3458 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3459 attributes->priority >= priority_max)
3460 return rte_flow_error_set(error, ENOTSUP,
3461 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3463 "priority out of range");
3464 if (attributes->transfer) {
3465 if (!priv->config.dv_esw_en)
3466 return rte_flow_error_set
3468 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3469 "E-Switch dr is not supported");
3470 if (!(priv->representor || priv->master))
3471 return rte_flow_error_set
3472 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3473 NULL, "E-Switch configuration can only be"
3474 " done by a master or a representor device");
3475 if (attributes->egress)
3476 return rte_flow_error_set
3478 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3479 "egress is not supported");
3481 if (!(attributes->egress ^ attributes->ingress))
3482 return rte_flow_error_set(error, ENOTSUP,
3483 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3484 "must specify exactly one of "
3485 "ingress or egress");
3490 * Internal validation function. For validating both actions and items.
3493 * Pointer to the rte_eth_dev structure.
3495 * Pointer to the flow attributes.
3497 * Pointer to the list of items.
3498 * @param[in] actions
3499 * Pointer to the list of actions.
3500 * @param[in] external
3501 * This flow rule is created by request external to PMD.
3503 * Pointer to the error structure.
3506 * 0 on success, a negative errno value otherwise and rte_errno is set.
3509 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3510 const struct rte_flow_item items[],
3511 const struct rte_flow_action actions[],
3512 bool external, struct rte_flow_error *error)
3515 uint64_t action_flags = 0;
3516 uint64_t item_flags = 0;
3517 uint64_t last_item = 0;
3518 uint8_t next_protocol = 0xff;
3519 uint16_t ether_type = 0;
3521 const struct rte_flow_item *gre_item = NULL;
3522 struct rte_flow_item_tcp nic_tcp_mask = {
3525 .src_port = RTE_BE16(UINT16_MAX),
3526 .dst_port = RTE_BE16(UINT16_MAX),
3532 ret = flow_dv_validate_attributes(dev, attr, external, error);
3535 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3536 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3537 int type = items->type;
3540 case RTE_FLOW_ITEM_TYPE_VOID:
3542 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3543 ret = flow_dv_validate_item_port_id
3544 (dev, items, attr, item_flags, error);
3547 last_item = MLX5_FLOW_ITEM_PORT_ID;
3549 case RTE_FLOW_ITEM_TYPE_ETH:
3550 ret = mlx5_flow_validate_item_eth(items, item_flags,
3554 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3555 MLX5_FLOW_LAYER_OUTER_L2;
3556 if (items->mask != NULL && items->spec != NULL) {
3558 ((const struct rte_flow_item_eth *)
3561 ((const struct rte_flow_item_eth *)
3563 ether_type = rte_be_to_cpu_16(ether_type);
3568 case RTE_FLOW_ITEM_TYPE_VLAN:
3569 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3573 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3574 MLX5_FLOW_LAYER_OUTER_VLAN;
3575 if (items->mask != NULL && items->spec != NULL) {
3577 ((const struct rte_flow_item_vlan *)
3578 items->spec)->inner_type;
3580 ((const struct rte_flow_item_vlan *)
3581 items->mask)->inner_type;
3582 ether_type = rte_be_to_cpu_16(ether_type);
3587 case RTE_FLOW_ITEM_TYPE_IPV4:
3588 mlx5_flow_tunnel_ip_check(items, next_protocol,
3589 &item_flags, &tunnel);
3590 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3596 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3597 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3598 if (items->mask != NULL &&
3599 ((const struct rte_flow_item_ipv4 *)
3600 items->mask)->hdr.next_proto_id) {
3602 ((const struct rte_flow_item_ipv4 *)
3603 (items->spec))->hdr.next_proto_id;
3605 ((const struct rte_flow_item_ipv4 *)
3606 (items->mask))->hdr.next_proto_id;
3608 /* Reset for inner layer. */
3609 next_protocol = 0xff;
3612 case RTE_FLOW_ITEM_TYPE_IPV6:
3613 mlx5_flow_tunnel_ip_check(items, next_protocol,
3614 &item_flags, &tunnel);
3615 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3621 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3622 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3623 if (items->mask != NULL &&
3624 ((const struct rte_flow_item_ipv6 *)
3625 items->mask)->hdr.proto) {
3627 ((const struct rte_flow_item_ipv6 *)
3628 items->spec)->hdr.proto;
3630 ((const struct rte_flow_item_ipv6 *)
3631 items->mask)->hdr.proto;
3633 /* Reset for inner layer. */
3634 next_protocol = 0xff;
3637 case RTE_FLOW_ITEM_TYPE_TCP:
3638 ret = mlx5_flow_validate_item_tcp
3645 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3646 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3648 case RTE_FLOW_ITEM_TYPE_UDP:
3649 ret = mlx5_flow_validate_item_udp(items, item_flags,
3654 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3655 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3657 case RTE_FLOW_ITEM_TYPE_GRE:
3658 ret = mlx5_flow_validate_item_gre(items, item_flags,
3659 next_protocol, error);
3663 last_item = MLX5_FLOW_LAYER_GRE;
3665 case RTE_FLOW_ITEM_TYPE_NVGRE:
3666 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3671 last_item = MLX5_FLOW_LAYER_NVGRE;
3673 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3674 ret = mlx5_flow_validate_item_gre_key
3675 (items, item_flags, gre_item, error);
3678 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3680 case RTE_FLOW_ITEM_TYPE_VXLAN:
3681 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3685 last_item = MLX5_FLOW_LAYER_VXLAN;
3687 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3688 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3693 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3695 case RTE_FLOW_ITEM_TYPE_GENEVE:
3696 ret = mlx5_flow_validate_item_geneve(items,
3701 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3703 case RTE_FLOW_ITEM_TYPE_MPLS:
3704 ret = mlx5_flow_validate_item_mpls(dev, items,
3709 last_item = MLX5_FLOW_LAYER_MPLS;
3711 case RTE_FLOW_ITEM_TYPE_META:
3712 ret = flow_dv_validate_item_meta(dev, items, attr,
3716 last_item = MLX5_FLOW_ITEM_METADATA;
3718 case RTE_FLOW_ITEM_TYPE_ICMP:
3719 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3724 last_item = MLX5_FLOW_LAYER_ICMP;
3726 case RTE_FLOW_ITEM_TYPE_ICMP6:
3727 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3732 last_item = MLX5_FLOW_LAYER_ICMP6;
3734 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3735 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3738 return rte_flow_error_set(error, ENOTSUP,
3739 RTE_FLOW_ERROR_TYPE_ITEM,
3740 NULL, "item not supported");
3742 item_flags |= last_item;
3744 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3745 int type = actions->type;
3746 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3747 return rte_flow_error_set(error, ENOTSUP,
3748 RTE_FLOW_ERROR_TYPE_ACTION,
3749 actions, "too many actions");
3751 case RTE_FLOW_ACTION_TYPE_VOID:
3753 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3754 ret = flow_dv_validate_action_port_id(dev,
3761 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3764 case RTE_FLOW_ACTION_TYPE_FLAG:
3765 ret = mlx5_flow_validate_action_flag(action_flags,
3769 action_flags |= MLX5_FLOW_ACTION_FLAG;
3772 case RTE_FLOW_ACTION_TYPE_MARK:
3773 ret = mlx5_flow_validate_action_mark(actions,
3778 action_flags |= MLX5_FLOW_ACTION_MARK;
3781 case RTE_FLOW_ACTION_TYPE_DROP:
3782 ret = mlx5_flow_validate_action_drop(action_flags,
3786 action_flags |= MLX5_FLOW_ACTION_DROP;
3789 case RTE_FLOW_ACTION_TYPE_QUEUE:
3790 ret = mlx5_flow_validate_action_queue(actions,
3795 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3798 case RTE_FLOW_ACTION_TYPE_RSS:
3799 ret = mlx5_flow_validate_action_rss(actions,
3805 action_flags |= MLX5_FLOW_ACTION_RSS;
3808 case RTE_FLOW_ACTION_TYPE_COUNT:
3809 ret = flow_dv_validate_action_count(dev, error);
3812 action_flags |= MLX5_FLOW_ACTION_COUNT;
3815 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3816 if (flow_dv_validate_action_pop_vlan(dev,
3822 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3825 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3826 ret = flow_dv_validate_action_push_vlan(action_flags,
3832 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3835 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3836 ret = flow_dv_validate_action_set_vlan_pcp
3837 (action_flags, actions, error);
3840 /* Count PCP with push_vlan command. */
3841 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3843 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3844 ret = flow_dv_validate_action_set_vlan_vid
3845 (item_flags, action_flags,
3849 /* Count VID with push_vlan command. */
3850 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3852 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3853 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3854 ret = flow_dv_validate_action_l2_encap(action_flags,
3859 action_flags |= actions->type ==
3860 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3861 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3862 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3865 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3866 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3867 ret = flow_dv_validate_action_l2_decap(action_flags,
3871 action_flags |= actions->type ==
3872 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3873 MLX5_FLOW_ACTION_VXLAN_DECAP :
3874 MLX5_FLOW_ACTION_NVGRE_DECAP;
3877 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3878 ret = flow_dv_validate_action_raw_encap(action_flags,
3883 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3886 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3887 ret = flow_dv_validate_action_raw_decap(action_flags,
3892 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3895 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3896 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3897 ret = flow_dv_validate_action_modify_mac(action_flags,
3903 /* Count all modify-header actions as one action. */
3904 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3906 action_flags |= actions->type ==
3907 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3908 MLX5_FLOW_ACTION_SET_MAC_SRC :
3909 MLX5_FLOW_ACTION_SET_MAC_DST;
3912 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3913 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3914 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3920 /* Count all modify-header actions as one action. */
3921 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3923 action_flags |= actions->type ==
3924 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3925 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3926 MLX5_FLOW_ACTION_SET_IPV4_DST;
3928 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3929 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3930 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3936 /* Count all modify-header actions as one action. */
3937 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3939 action_flags |= actions->type ==
3940 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3941 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3942 MLX5_FLOW_ACTION_SET_IPV6_DST;
3944 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3945 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3946 ret = flow_dv_validate_action_modify_tp(action_flags,
3952 /* Count all modify-header actions as one action. */
3953 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3955 action_flags |= actions->type ==
3956 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3957 MLX5_FLOW_ACTION_SET_TP_SRC :
3958 MLX5_FLOW_ACTION_SET_TP_DST;
3960 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3961 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3962 ret = flow_dv_validate_action_modify_ttl(action_flags,
3968 /* Count all modify-header actions as one action. */
3969 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3971 action_flags |= actions->type ==
3972 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3973 MLX5_FLOW_ACTION_SET_TTL :
3974 MLX5_FLOW_ACTION_DEC_TTL;
3976 case RTE_FLOW_ACTION_TYPE_JUMP:
3977 ret = flow_dv_validate_action_jump(actions,
3984 action_flags |= MLX5_FLOW_ACTION_JUMP;
3986 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3987 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3988 ret = flow_dv_validate_action_modify_tcp_seq
3995 /* Count all modify-header actions as one action. */
3996 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3998 action_flags |= actions->type ==
3999 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4000 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4001 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4003 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4004 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4005 ret = flow_dv_validate_action_modify_tcp_ack
4012 /* Count all modify-header actions as one action. */
4013 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4015 action_flags |= actions->type ==
4016 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4017 MLX5_FLOW_ACTION_INC_TCP_ACK :
4018 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4020 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4021 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4024 return rte_flow_error_set(error, ENOTSUP,
4025 RTE_FLOW_ERROR_TYPE_ACTION,
4027 "action not supported");
4030 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4031 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4032 return rte_flow_error_set(error, ENOTSUP,
4033 RTE_FLOW_ERROR_TYPE_ACTION,
4035 "can't have vxlan and vlan"
4036 " actions in the same rule");
4037 /* Eswitch has few restrictions on using items and actions */
4038 if (attr->transfer) {
4039 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4040 return rte_flow_error_set(error, ENOTSUP,
4041 RTE_FLOW_ERROR_TYPE_ACTION,
4043 "unsupported action FLAG");
4044 if (action_flags & MLX5_FLOW_ACTION_MARK)
4045 return rte_flow_error_set(error, ENOTSUP,
4046 RTE_FLOW_ERROR_TYPE_ACTION,
4048 "unsupported action MARK");
4049 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4050 return rte_flow_error_set(error, ENOTSUP,
4051 RTE_FLOW_ERROR_TYPE_ACTION,
4053 "unsupported action QUEUE");
4054 if (action_flags & MLX5_FLOW_ACTION_RSS)
4055 return rte_flow_error_set(error, ENOTSUP,
4056 RTE_FLOW_ERROR_TYPE_ACTION,
4058 "unsupported action RSS");
4059 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4060 return rte_flow_error_set(error, EINVAL,
4061 RTE_FLOW_ERROR_TYPE_ACTION,
4063 "no fate action is found");
4065 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4066 return rte_flow_error_set(error, EINVAL,
4067 RTE_FLOW_ERROR_TYPE_ACTION,
4069 "no fate action is found");
4075 * Internal preparation function. Allocates the DV flow size,
4076 * this size is constant.
4079 * Pointer to the flow attributes.
4081 * Pointer to the list of items.
4082 * @param[in] actions
4083 * Pointer to the list of actions.
4085 * Pointer to the error structure.
4088 * Pointer to mlx5_flow object on success,
4089 * otherwise NULL and rte_errno is set.
4091 static struct mlx5_flow *
4092 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4093 const struct rte_flow_item items[] __rte_unused,
4094 const struct rte_flow_action actions[] __rte_unused,
4095 struct rte_flow_error *error)
4097 size_t size = sizeof(struct mlx5_flow);
4098 struct mlx5_flow *dev_flow;
4100 dev_flow = rte_calloc(__func__, 1, size, 0);
4102 rte_flow_error_set(error, ENOMEM,
4103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4104 "not enough memory to create flow");
4107 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4108 dev_flow->ingress = attr->ingress;
4109 dev_flow->transfer = attr->transfer;
4115 * Sanity check for match mask and value. Similar to check_valid_spec() in
4116 * kernel driver. If unmasked bit is present in value, it returns failure.
4119 * pointer to match mask buffer.
4120 * @param match_value
4121 * pointer to match value buffer.
4124 * 0 if valid, -EINVAL otherwise.
4127 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4129 uint8_t *m = match_mask;
4130 uint8_t *v = match_value;
4133 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4136 "match_value differs from match_criteria"
4137 " %p[%u] != %p[%u]",
4138 match_value, i, match_mask, i);
4147 * Add Ethernet item to matcher and to the value.
4149 * @param[in, out] matcher
4151 * @param[in, out] key
4152 * Flow matcher value.
4154 * Flow pattern to translate.
4156 * Item is inner pattern.
4159 flow_dv_translate_item_eth(void *matcher, void *key,
4160 const struct rte_flow_item *item, int inner)
4162 const struct rte_flow_item_eth *eth_m = item->mask;
4163 const struct rte_flow_item_eth *eth_v = item->spec;
4164 const struct rte_flow_item_eth nic_mask = {
4165 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4166 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4167 .type = RTE_BE16(0xffff),
4179 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4181 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4183 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4185 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4187 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4188 ð_m->dst, sizeof(eth_m->dst));
4189 /* The value must be in the range of the mask. */
4190 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4191 for (i = 0; i < sizeof(eth_m->dst); ++i)
4192 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4193 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4194 ð_m->src, sizeof(eth_m->src));
4195 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4196 /* The value must be in the range of the mask. */
4197 for (i = 0; i < sizeof(eth_m->dst); ++i)
4198 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4199 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4200 rte_be_to_cpu_16(eth_m->type));
4201 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4202 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4206 * Add VLAN item to matcher and to the value.
4208 * @param[in, out] dev_flow
4210 * @param[in, out] matcher
4212 * @param[in, out] key
4213 * Flow matcher value.
4215 * Flow pattern to translate.
4217 * Item is inner pattern.
4220 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4221 void *matcher, void *key,
4222 const struct rte_flow_item *item,
4225 const struct rte_flow_item_vlan *vlan_m = item->mask;
4226 const struct rte_flow_item_vlan *vlan_v = item->spec;
4235 vlan_m = &rte_flow_item_vlan_mask;
4237 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4239 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4241 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4243 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4245 * This is workaround, masks are not supported,
4246 * and pre-validated.
4248 dev_flow->dv.vf_vlan.tag =
4249 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4251 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4252 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4253 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4254 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4255 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4256 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4257 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4258 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4259 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4260 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4261 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4262 rte_be_to_cpu_16(vlan_m->inner_type));
4263 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4264 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4268 * Add IPV4 item to matcher and to the value.
4270 * @param[in, out] matcher
4272 * @param[in, out] key
4273 * Flow matcher value.
4275 * Flow pattern to translate.
4277 * Item is inner pattern.
4279 * The group to insert the rule.
4282 flow_dv_translate_item_ipv4(void *matcher, void *key,
4283 const struct rte_flow_item *item,
4284 int inner, uint32_t group)
4286 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4287 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4288 const struct rte_flow_item_ipv4 nic_mask = {
4290 .src_addr = RTE_BE32(0xffffffff),
4291 .dst_addr = RTE_BE32(0xffffffff),
4292 .type_of_service = 0xff,
4293 .next_proto_id = 0xff,
4303 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4305 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4307 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4309 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4312 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4314 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4315 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4320 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4321 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4322 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4323 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4324 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4325 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4326 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4327 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4328 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4329 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4330 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4331 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4332 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4333 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4334 ipv4_m->hdr.type_of_service);
4335 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4336 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4337 ipv4_m->hdr.type_of_service >> 2);
4338 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4339 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4340 ipv4_m->hdr.next_proto_id);
4341 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4342 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4346 * Add IPV6 item to matcher and to the value.
4348 * @param[in, out] matcher
4350 * @param[in, out] key
4351 * Flow matcher value.
4353 * Flow pattern to translate.
4355 * Item is inner pattern.
4357 * The group to insert the rule.
4360 flow_dv_translate_item_ipv6(void *matcher, void *key,
4361 const struct rte_flow_item *item,
4362 int inner, uint32_t group)
4364 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4365 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4366 const struct rte_flow_item_ipv6 nic_mask = {
4369 "\xff\xff\xff\xff\xff\xff\xff\xff"
4370 "\xff\xff\xff\xff\xff\xff\xff\xff",
4372 "\xff\xff\xff\xff\xff\xff\xff\xff"
4373 "\xff\xff\xff\xff\xff\xff\xff\xff",
4374 .vtc_flow = RTE_BE32(0xffffffff),
4381 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4382 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4391 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4393 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4395 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4397 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4400 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4402 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4408 size = sizeof(ipv6_m->hdr.dst_addr);
4409 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4410 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4411 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4412 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4413 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4414 for (i = 0; i < size; ++i)
4415 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4416 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4417 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4418 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4419 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4420 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4421 for (i = 0; i < size; ++i)
4422 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4424 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4425 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4426 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4429 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4432 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4434 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4437 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4439 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4443 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4445 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4446 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4450 * Add TCP item to matcher and to the value.
4452 * @param[in, out] matcher
4454 * @param[in, out] key
4455 * Flow matcher value.
4457 * Flow pattern to translate.
4459 * Item is inner pattern.
4462 flow_dv_translate_item_tcp(void *matcher, void *key,
4463 const struct rte_flow_item *item,
4466 const struct rte_flow_item_tcp *tcp_m = item->mask;
4467 const struct rte_flow_item_tcp *tcp_v = item->spec;
4472 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4474 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4476 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4478 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4480 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4481 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4485 tcp_m = &rte_flow_item_tcp_mask;
4486 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4487 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4488 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4489 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4490 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4491 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4492 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4493 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4495 tcp_m->hdr.tcp_flags);
4496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4497 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4501 * Add UDP item to matcher and to the value.
4503 * @param[in, out] matcher
4505 * @param[in, out] key
4506 * Flow matcher value.
4508 * Flow pattern to translate.
4510 * Item is inner pattern.
4513 flow_dv_translate_item_udp(void *matcher, void *key,
4514 const struct rte_flow_item *item,
4517 const struct rte_flow_item_udp *udp_m = item->mask;
4518 const struct rte_flow_item_udp *udp_v = item->spec;
4523 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4525 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4527 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4529 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4531 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4536 udp_m = &rte_flow_item_udp_mask;
4537 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4538 rte_be_to_cpu_16(udp_m->hdr.src_port));
4539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4540 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4542 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4543 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4544 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4548 * Add GRE optional Key item to matcher and to the value.
4550 * @param[in, out] matcher
4552 * @param[in, out] key
4553 * Flow matcher value.
4555 * Flow pattern to translate.
4557 * Item is inner pattern.
4560 flow_dv_translate_item_gre_key(void *matcher, void *key,
4561 const struct rte_flow_item *item)
4563 const rte_be32_t *key_m = item->mask;
4564 const rte_be32_t *key_v = item->spec;
4565 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4566 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4567 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4572 key_m = &gre_key_default_mask;
4573 /* GRE K bit must be on and should already be validated */
4574 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4575 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4576 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4577 rte_be_to_cpu_32(*key_m) >> 8);
4578 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4579 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4580 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4581 rte_be_to_cpu_32(*key_m) & 0xFF);
4582 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4583 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4587 * Add GRE item to matcher and to the value.
4589 * @param[in, out] matcher
4591 * @param[in, out] key
4592 * Flow matcher value.
4594 * Flow pattern to translate.
4596 * Item is inner pattern.
4599 flow_dv_translate_item_gre(void *matcher, void *key,
4600 const struct rte_flow_item *item,
4603 const struct rte_flow_item_gre *gre_m = item->mask;
4604 const struct rte_flow_item_gre *gre_v = item->spec;
4607 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4608 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4615 uint16_t s_present:1;
4616 uint16_t k_present:1;
4617 uint16_t rsvd_bit1:1;
4618 uint16_t c_present:1;
4622 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4625 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4627 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4629 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4631 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4633 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4638 gre_m = &rte_flow_item_gre_mask;
4639 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4640 rte_be_to_cpu_16(gre_m->protocol));
4641 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4642 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4643 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4644 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4645 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4646 gre_crks_rsvd0_ver_m.c_present);
4647 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4648 gre_crks_rsvd0_ver_v.c_present &
4649 gre_crks_rsvd0_ver_m.c_present);
4650 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4651 gre_crks_rsvd0_ver_m.k_present);
4652 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4653 gre_crks_rsvd0_ver_v.k_present &
4654 gre_crks_rsvd0_ver_m.k_present);
4655 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4656 gre_crks_rsvd0_ver_m.s_present);
4657 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4658 gre_crks_rsvd0_ver_v.s_present &
4659 gre_crks_rsvd0_ver_m.s_present);
4663 * Add NVGRE item to matcher and to the value.
4665 * @param[in, out] matcher
4667 * @param[in, out] key
4668 * Flow matcher value.
4670 * Flow pattern to translate.
4672 * Item is inner pattern.
4675 flow_dv_translate_item_nvgre(void *matcher, void *key,
4676 const struct rte_flow_item *item,
4679 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4680 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4681 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4682 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4683 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4684 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4690 /* For NVGRE, GRE header fields must be set with defined values. */
4691 const struct rte_flow_item_gre gre_spec = {
4692 .c_rsvd0_ver = RTE_BE16(0x2000),
4693 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4695 const struct rte_flow_item_gre gre_mask = {
4696 .c_rsvd0_ver = RTE_BE16(0xB000),
4697 .protocol = RTE_BE16(UINT16_MAX),
4699 const struct rte_flow_item gre_item = {
4704 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4708 nvgre_m = &rte_flow_item_nvgre_mask;
4709 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4710 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4711 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4712 memcpy(gre_key_m, tni_flow_id_m, size);
4713 for (i = 0; i < size; ++i)
4714 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4718 * Add VXLAN item to matcher and to the value.
4720 * @param[in, out] matcher
4722 * @param[in, out] key
4723 * Flow matcher value.
4725 * Flow pattern to translate.
4727 * Item is inner pattern.
4730 flow_dv_translate_item_vxlan(void *matcher, void *key,
4731 const struct rte_flow_item *item,
4734 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4735 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4738 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4739 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4747 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4749 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4751 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4753 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4755 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4756 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4757 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4758 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4759 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4764 vxlan_m = &rte_flow_item_vxlan_mask;
4765 size = sizeof(vxlan_m->vni);
4766 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4767 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4768 memcpy(vni_m, vxlan_m->vni, size);
4769 for (i = 0; i < size; ++i)
4770 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4774 * Add Geneve item to matcher and to the value.
4776 * @param[in, out] matcher
4778 * @param[in, out] key
4779 * Flow matcher value.
4781 * Flow pattern to translate.
4783 * Item is inner pattern.
4787 flow_dv_translate_item_geneve(void *matcher, void *key,
4788 const struct rte_flow_item *item, int inner)
4790 const struct rte_flow_item_geneve *geneve_m = item->mask;
4791 const struct rte_flow_item_geneve *geneve_v = item->spec;
4794 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4795 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4804 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4806 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4808 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4810 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4812 dport = MLX5_UDP_PORT_GENEVE;
4813 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4814 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4815 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4820 geneve_m = &rte_flow_item_geneve_mask;
4821 size = sizeof(geneve_m->vni);
4822 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4823 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4824 memcpy(vni_m, geneve_m->vni, size);
4825 for (i = 0; i < size; ++i)
4826 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4827 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4828 rte_be_to_cpu_16(geneve_m->protocol));
4829 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4830 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4831 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4832 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4833 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4834 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4835 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4836 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4837 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4838 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4839 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4840 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4841 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4845 * Add MPLS item to matcher and to the value.
4847 * @param[in, out] matcher
4849 * @param[in, out] key
4850 * Flow matcher value.
4852 * Flow pattern to translate.
4853 * @param[in] prev_layer
4854 * The protocol layer indicated in previous item.
4856 * Item is inner pattern.
4859 flow_dv_translate_item_mpls(void *matcher, void *key,
4860 const struct rte_flow_item *item,
4861 uint64_t prev_layer,
4864 const uint32_t *in_mpls_m = item->mask;
4865 const uint32_t *in_mpls_v = item->spec;
4866 uint32_t *out_mpls_m = 0;
4867 uint32_t *out_mpls_v = 0;
4868 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4869 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4870 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4872 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4873 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4874 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4876 switch (prev_layer) {
4877 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4878 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4879 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4880 MLX5_UDP_PORT_MPLS);
4882 case MLX5_FLOW_LAYER_GRE:
4883 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4884 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4885 RTE_ETHER_TYPE_MPLS);
4888 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4889 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4896 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4897 switch (prev_layer) {
4898 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4900 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4901 outer_first_mpls_over_udp);
4903 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4904 outer_first_mpls_over_udp);
4906 case MLX5_FLOW_LAYER_GRE:
4908 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4909 outer_first_mpls_over_gre);
4911 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4912 outer_first_mpls_over_gre);
4915 /* Inner MPLS not over GRE is not supported. */
4918 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4922 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4928 if (out_mpls_m && out_mpls_v) {
4929 *out_mpls_m = *in_mpls_m;
4930 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4935 * Add metadata register item to matcher
4937 * @param[in, out] matcher
4939 * @param[in, out] key
4940 * Flow matcher value.
4941 * @param[in] reg_type
4942 * Type of device metadata register
4949 flow_dv_match_meta_reg(void *matcher, void *key,
4950 enum modify_reg reg_type,
4951 uint32_t data, uint32_t mask)
4954 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4956 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4961 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
4962 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
4965 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
4966 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
4969 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4970 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
4973 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
4974 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
4977 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
4978 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
4981 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
4982 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
4985 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
4986 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
4989 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
4990 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
4993 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
4994 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
4997 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
4998 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5007 * Add META item to matcher
5009 * @param[in, out] matcher
5011 * @param[in, out] key
5012 * Flow matcher value.
5014 * Flow pattern to translate.
5016 * Item is inner pattern.
5019 flow_dv_translate_item_meta(void *matcher, void *key,
5020 const struct rte_flow_item *item)
5022 const struct rte_flow_item_meta *meta_m;
5023 const struct rte_flow_item_meta *meta_v;
5025 meta_m = (const void *)item->mask;
5027 meta_m = &rte_flow_item_meta_mask;
5028 meta_v = (const void *)item->spec;
5030 flow_dv_match_meta_reg(matcher, key, REG_A,
5031 rte_cpu_to_be_32(meta_v->data),
5032 rte_cpu_to_be_32(meta_m->data));
5036 * Add vport metadata Reg C0 item to matcher
5038 * @param[in, out] matcher
5040 * @param[in, out] key
5041 * Flow matcher value.
5043 * Flow pattern to translate.
5046 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5047 uint32_t value, uint32_t mask)
5049 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5053 * Add tag item to matcher
5055 * @param[in, out] matcher
5057 * @param[in, out] key
5058 * Flow matcher value.
5060 * Flow pattern to translate.
5063 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5064 const struct rte_flow_item *item)
5066 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5067 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5068 enum modify_reg reg = tag_v->id;
5070 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5074 * Add source vport match to the specified matcher.
5076 * @param[in, out] matcher
5078 * @param[in, out] key
5079 * Flow matcher value.
5081 * Source vport value to match
5086 flow_dv_translate_item_source_vport(void *matcher, void *key,
5087 int16_t port, uint16_t mask)
5089 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5090 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5092 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5093 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5097 * Translate port-id item to eswitch match on port-id.
5100 * The devich to configure through.
5101 * @param[in, out] matcher
5103 * @param[in, out] key
5104 * Flow matcher value.
5106 * Flow pattern to translate.
5109 * 0 on success, a negative errno value otherwise.
5112 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5113 void *key, const struct rte_flow_item *item)
5115 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5116 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5117 struct mlx5_priv *priv;
5120 mask = pid_m ? pid_m->id : 0xffff;
5121 id = pid_v ? pid_v->id : dev->data->port_id;
5122 priv = mlx5_port_to_eswitch_info(id);
5125 /* Translate to vport field or to metadata, depending on mode. */
5126 if (priv->vport_meta_mask)
5127 flow_dv_translate_item_meta_vport(matcher, key,
5128 priv->vport_meta_tag,
5129 priv->vport_meta_mask);
5131 flow_dv_translate_item_source_vport(matcher, key,
5132 priv->vport_id, mask);
5137 * Add ICMP6 item to matcher and to the value.
5139 * @param[in, out] matcher
5141 * @param[in, out] key
5142 * Flow matcher value.
5144 * Flow pattern to translate.
5146 * Item is inner pattern.
5149 flow_dv_translate_item_icmp6(void *matcher, void *key,
5150 const struct rte_flow_item *item,
5153 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5154 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5157 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5159 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5161 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5163 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5165 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5167 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5169 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5170 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5174 icmp6_m = &rte_flow_item_icmp6_mask;
5175 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5176 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5177 icmp6_v->type & icmp6_m->type);
5178 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5179 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5180 icmp6_v->code & icmp6_m->code);
5184 * Add ICMP item to matcher and to the value.
5186 * @param[in, out] matcher
5188 * @param[in, out] key
5189 * Flow matcher value.
5191 * Flow pattern to translate.
5193 * Item is inner pattern.
5196 flow_dv_translate_item_icmp(void *matcher, void *key,
5197 const struct rte_flow_item *item,
5200 const struct rte_flow_item_icmp *icmp_m = item->mask;
5201 const struct rte_flow_item_icmp *icmp_v = item->spec;
5204 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5206 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5208 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5210 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5212 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5214 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5221 icmp_m = &rte_flow_item_icmp_mask;
5222 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5223 icmp_m->hdr.icmp_type);
5224 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5225 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5226 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5227 icmp_m->hdr.icmp_code);
5228 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5229 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5232 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5234 #define HEADER_IS_ZERO(match_criteria, headers) \
5235 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5236 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5239 * Calculate flow matcher enable bitmap.
5241 * @param match_criteria
5242 * Pointer to flow matcher criteria.
5245 * Bitmap of enabled fields.
5248 flow_dv_matcher_enable(uint32_t *match_criteria)
5250 uint8_t match_criteria_enable;
5252 match_criteria_enable =
5253 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5254 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5255 match_criteria_enable |=
5256 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5257 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5258 match_criteria_enable |=
5259 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5260 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5261 match_criteria_enable |=
5262 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5263 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5264 match_criteria_enable |=
5265 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5266 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5267 return match_criteria_enable;
5274 * @param dev[in, out]
5275 * Pointer to rte_eth_dev structure.
5276 * @param[in] table_id
5279 * Direction of the table.
5280 * @param[in] transfer
5281 * E-Switch or NIC flow.
5283 * pointer to error structure.
5286 * Returns tables resource based on the index, NULL in case of failed.
5288 static struct mlx5_flow_tbl_resource *
5289 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5290 uint32_t table_id, uint8_t egress,
5292 struct rte_flow_error *error)
5294 struct mlx5_priv *priv = dev->data->dev_private;
5295 struct mlx5_ibv_shared *sh = priv->sh;
5296 struct mlx5_flow_tbl_resource *tbl;
5298 #ifdef HAVE_MLX5DV_DR
5300 tbl = &sh->fdb_tbl[table_id];
5302 tbl->obj = mlx5_glue->dr_create_flow_tbl
5303 (sh->fdb_domain, table_id);
5304 } else if (egress) {
5305 tbl = &sh->tx_tbl[table_id];
5307 tbl->obj = mlx5_glue->dr_create_flow_tbl
5308 (sh->tx_domain, table_id);
5310 tbl = &sh->rx_tbl[table_id];
5312 tbl->obj = mlx5_glue->dr_create_flow_tbl
5313 (sh->rx_domain, table_id);
5316 rte_flow_error_set(error, ENOMEM,
5317 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5318 NULL, "cannot create table");
5321 rte_atomic32_inc(&tbl->refcnt);
5327 return &sh->fdb_tbl[table_id];
5329 return &sh->tx_tbl[table_id];
5331 return &sh->rx_tbl[table_id];
5336 * Release a flow table.
5339 * Table resource to be released.
5342 * Returns 0 if table was released, else return 1;
5345 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5349 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5350 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5358 * Register the flow matcher.
5360 * @param dev[in, out]
5361 * Pointer to rte_eth_dev structure.
5362 * @param[in, out] matcher
5363 * Pointer to flow matcher.
5364 * @parm[in, out] dev_flow
5365 * Pointer to the dev_flow.
5367 * pointer to error structure.
5370 * 0 on success otherwise -errno and errno is set.
5373 flow_dv_matcher_register(struct rte_eth_dev *dev,
5374 struct mlx5_flow_dv_matcher *matcher,
5375 struct mlx5_flow *dev_flow,
5376 struct rte_flow_error *error)
5378 struct mlx5_priv *priv = dev->data->dev_private;
5379 struct mlx5_ibv_shared *sh = priv->sh;
5380 struct mlx5_flow_dv_matcher *cache_matcher;
5381 struct mlx5dv_flow_matcher_attr dv_attr = {
5382 .type = IBV_FLOW_ATTR_NORMAL,
5383 .match_mask = (void *)&matcher->mask,
5385 struct mlx5_flow_tbl_resource *tbl = NULL;
5387 /* Lookup from cache. */
5388 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5389 if (matcher->crc == cache_matcher->crc &&
5390 matcher->priority == cache_matcher->priority &&
5391 matcher->egress == cache_matcher->egress &&
5392 matcher->group == cache_matcher->group &&
5393 matcher->transfer == cache_matcher->transfer &&
5394 !memcmp((const void *)matcher->mask.buf,
5395 (const void *)cache_matcher->mask.buf,
5396 cache_matcher->mask.size)) {
5398 "priority %hd use %s matcher %p: refcnt %d++",
5399 cache_matcher->priority,
5400 cache_matcher->egress ? "tx" : "rx",
5401 (void *)cache_matcher,
5402 rte_atomic32_read(&cache_matcher->refcnt));
5403 rte_atomic32_inc(&cache_matcher->refcnt);
5404 dev_flow->dv.matcher = cache_matcher;
5408 /* Register new matcher. */
5409 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5411 return rte_flow_error_set(error, ENOMEM,
5412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5413 "cannot allocate matcher memory");
5414 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5415 matcher->egress, matcher->transfer,
5418 rte_free(cache_matcher);
5419 return rte_flow_error_set(error, ENOMEM,
5420 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5421 NULL, "cannot create table");
5423 *cache_matcher = *matcher;
5424 dv_attr.match_criteria_enable =
5425 flow_dv_matcher_enable(cache_matcher->mask.buf);
5426 dv_attr.priority = matcher->priority;
5427 if (matcher->egress)
5428 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5429 cache_matcher->matcher_object =
5430 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5431 if (!cache_matcher->matcher_object) {
5432 rte_free(cache_matcher);
5433 #ifdef HAVE_MLX5DV_DR
5434 flow_dv_tbl_resource_release(tbl);
5436 return rte_flow_error_set(error, ENOMEM,
5437 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5438 NULL, "cannot create matcher");
5440 rte_atomic32_inc(&cache_matcher->refcnt);
5441 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5442 dev_flow->dv.matcher = cache_matcher;
5443 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5444 cache_matcher->priority,
5445 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5446 rte_atomic32_read(&cache_matcher->refcnt));
5447 rte_atomic32_inc(&tbl->refcnt);
5452 * Find existing tag resource or create and register a new one.
5454 * @param dev[in, out]
5455 * Pointer to rte_eth_dev structure.
5456 * @param[in, out] resource
5457 * Pointer to tag resource.
5458 * @parm[in, out] dev_flow
5459 * Pointer to the dev_flow.
5461 * pointer to error structure.
5464 * 0 on success otherwise -errno and errno is set.
5467 flow_dv_tag_resource_register
5468 (struct rte_eth_dev *dev,
5469 struct mlx5_flow_dv_tag_resource *resource,
5470 struct mlx5_flow *dev_flow,
5471 struct rte_flow_error *error)
5473 struct mlx5_priv *priv = dev->data->dev_private;
5474 struct mlx5_ibv_shared *sh = priv->sh;
5475 struct mlx5_flow_dv_tag_resource *cache_resource;
5477 /* Lookup a matching resource from cache. */
5478 LIST_FOREACH(cache_resource, &sh->tags, next) {
5479 if (resource->tag == cache_resource->tag) {
5480 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5481 (void *)cache_resource,
5482 rte_atomic32_read(&cache_resource->refcnt));
5483 rte_atomic32_inc(&cache_resource->refcnt);
5484 dev_flow->dv.tag_resource = cache_resource;
5488 /* Register new resource. */
5489 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5490 if (!cache_resource)
5491 return rte_flow_error_set(error, ENOMEM,
5492 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5493 "cannot allocate resource memory");
5494 *cache_resource = *resource;
5495 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5497 if (!cache_resource->action) {
5498 rte_free(cache_resource);
5499 return rte_flow_error_set(error, ENOMEM,
5500 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5501 NULL, "cannot create action");
5503 rte_atomic32_init(&cache_resource->refcnt);
5504 rte_atomic32_inc(&cache_resource->refcnt);
5505 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5506 dev_flow->dv.tag_resource = cache_resource;
5507 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5508 (void *)cache_resource,
5509 rte_atomic32_read(&cache_resource->refcnt));
5517 * Pointer to Ethernet device.
5519 * Pointer to mlx5_flow.
5522 * 1 while a reference on it exists, 0 when freed.
5525 flow_dv_tag_release(struct rte_eth_dev *dev,
5526 struct mlx5_flow_dv_tag_resource *tag)
5529 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5530 dev->data->port_id, (void *)tag,
5531 rte_atomic32_read(&tag->refcnt));
5532 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5533 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5534 LIST_REMOVE(tag, next);
5535 DRV_LOG(DEBUG, "port %u tag %p: removed",
5536 dev->data->port_id, (void *)tag);
5544 * Translate port ID action to vport.
5547 * Pointer to rte_eth_dev structure.
5549 * Pointer to the port ID action.
5550 * @param[out] dst_port_id
5551 * The target port ID.
5553 * Pointer to the error structure.
5556 * 0 on success, a negative errno value otherwise and rte_errno is set.
5559 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5560 const struct rte_flow_action *action,
5561 uint32_t *dst_port_id,
5562 struct rte_flow_error *error)
5565 struct mlx5_priv *priv;
5566 const struct rte_flow_action_port_id *conf =
5567 (const struct rte_flow_action_port_id *)action->conf;
5569 port = conf->original ? dev->data->port_id : conf->id;
5570 priv = mlx5_port_to_eswitch_info(port);
5572 return rte_flow_error_set(error, -rte_errno,
5573 RTE_FLOW_ERROR_TYPE_ACTION,
5575 "No eswitch info was found for port");
5576 if (priv->vport_meta_mask)
5577 *dst_port_id = priv->vport_meta_tag;
5579 *dst_port_id = priv->vport_id;
5584 * Add Tx queue matcher
5587 * Pointer to the dev struct.
5588 * @param[in, out] matcher
5590 * @param[in, out] key
5591 * Flow matcher value.
5593 * Flow pattern to translate.
5595 * Item is inner pattern.
5598 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5599 void *matcher, void *key,
5600 const struct rte_flow_item *item)
5602 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5603 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5605 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5607 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5608 struct mlx5_txq_ctrl *txq;
5612 queue_m = (const void *)item->mask;
5615 queue_v = (const void *)item->spec;
5618 txq = mlx5_txq_get(dev, queue_v->queue);
5621 queue = txq->obj->sq->id;
5622 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5623 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5624 queue & queue_m->queue);
5625 mlx5_txq_release(dev, queue_v->queue);
5629 * Fill the flow with DV spec.
5632 * Pointer to rte_eth_dev structure.
5633 * @param[in, out] dev_flow
5634 * Pointer to the sub flow.
5636 * Pointer to the flow attributes.
5638 * Pointer to the list of items.
5639 * @param[in] actions
5640 * Pointer to the list of actions.
5642 * Pointer to the error structure.
5645 * 0 on success, a negative errno value otherwise and rte_errno is set.
5648 flow_dv_translate(struct rte_eth_dev *dev,
5649 struct mlx5_flow *dev_flow,
5650 const struct rte_flow_attr *attr,
5651 const struct rte_flow_item items[],
5652 const struct rte_flow_action actions[],
5653 struct rte_flow_error *error)
5655 struct mlx5_priv *priv = dev->data->dev_private;
5656 struct rte_flow *flow = dev_flow->flow;
5657 uint64_t item_flags = 0;
5658 uint64_t last_item = 0;
5659 uint64_t action_flags = 0;
5660 uint64_t priority = attr->priority;
5661 struct mlx5_flow_dv_matcher matcher = {
5663 .size = sizeof(matcher.mask.buf),
5667 bool actions_end = false;
5668 struct mlx5_flow_dv_modify_hdr_resource res = {
5669 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5670 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5672 union flow_dv_attr flow_attr = { .attr = 0 };
5673 struct mlx5_flow_dv_tag_resource tag_resource;
5674 uint32_t modify_action_position = UINT32_MAX;
5675 void *match_mask = matcher.mask.buf;
5676 void *match_value = dev_flow->dv.value.buf;
5677 uint8_t next_protocol = 0xff;
5678 struct rte_vlan_hdr vlan = { 0 };
5682 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5686 dev_flow->group = table;
5688 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5689 if (priority == MLX5_FLOW_PRIO_RSVD)
5690 priority = priv->config.flow_prio - 1;
5691 for (; !actions_end ; actions++) {
5692 const struct rte_flow_action_queue *queue;
5693 const struct rte_flow_action_rss *rss;
5694 const struct rte_flow_action *action = actions;
5695 const struct rte_flow_action_count *count = action->conf;
5696 const uint8_t *rss_key;
5697 const struct rte_flow_action_jump *jump_data;
5698 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5699 struct mlx5_flow_tbl_resource *tbl;
5700 uint32_t port_id = 0;
5701 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5702 int action_type = actions->type;
5703 const struct rte_flow_action *found_action = NULL;
5705 switch (action_type) {
5706 case RTE_FLOW_ACTION_TYPE_VOID:
5708 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5709 if (flow_dv_translate_action_port_id(dev, action,
5712 port_id_resource.port_id = port_id;
5713 if (flow_dv_port_id_action_resource_register
5714 (dev, &port_id_resource, dev_flow, error))
5716 dev_flow->dv.actions[actions_n++] =
5717 dev_flow->dv.port_id_action->action;
5718 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5720 case RTE_FLOW_ACTION_TYPE_FLAG:
5722 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5723 if (!dev_flow->dv.tag_resource)
5724 if (flow_dv_tag_resource_register
5725 (dev, &tag_resource, dev_flow, error))
5727 dev_flow->dv.actions[actions_n++] =
5728 dev_flow->dv.tag_resource->action;
5729 action_flags |= MLX5_FLOW_ACTION_FLAG;
5731 case RTE_FLOW_ACTION_TYPE_MARK:
5732 tag_resource.tag = mlx5_flow_mark_set
5733 (((const struct rte_flow_action_mark *)
5734 (actions->conf))->id);
5735 if (!dev_flow->dv.tag_resource)
5736 if (flow_dv_tag_resource_register
5737 (dev, &tag_resource, dev_flow, error))
5739 dev_flow->dv.actions[actions_n++] =
5740 dev_flow->dv.tag_resource->action;
5741 action_flags |= MLX5_FLOW_ACTION_MARK;
5743 case RTE_FLOW_ACTION_TYPE_DROP:
5744 action_flags |= MLX5_FLOW_ACTION_DROP;
5746 case RTE_FLOW_ACTION_TYPE_QUEUE:
5747 assert(flow->rss.queue);
5748 queue = actions->conf;
5749 flow->rss.queue_num = 1;
5750 (*flow->rss.queue)[0] = queue->index;
5751 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5753 case RTE_FLOW_ACTION_TYPE_RSS:
5754 assert(flow->rss.queue);
5755 rss = actions->conf;
5756 if (flow->rss.queue)
5757 memcpy((*flow->rss.queue), rss->queue,
5758 rss->queue_num * sizeof(uint16_t));
5759 flow->rss.queue_num = rss->queue_num;
5760 /* NULL RSS key indicates default RSS key. */
5761 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5762 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5764 * rss->level and rss.types should be set in advance
5765 * when expanding items for RSS.
5767 action_flags |= MLX5_FLOW_ACTION_RSS;
5769 case RTE_FLOW_ACTION_TYPE_COUNT:
5770 if (!priv->config.devx) {
5771 rte_errno = ENOTSUP;
5774 flow->counter = flow_dv_counter_alloc(dev,
5778 if (flow->counter == NULL)
5780 dev_flow->dv.actions[actions_n++] =
5781 flow->counter->action;
5782 action_flags |= MLX5_FLOW_ACTION_COUNT;
5785 if (rte_errno == ENOTSUP)
5786 return rte_flow_error_set
5788 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5790 "count action not supported");
5792 return rte_flow_error_set
5794 RTE_FLOW_ERROR_TYPE_ACTION,
5796 "cannot create counter"
5799 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5800 dev_flow->dv.actions[actions_n++] =
5801 priv->sh->pop_vlan_action;
5802 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5804 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5805 flow_dev_get_vlan_info_from_items(items, &vlan);
5806 vlan.eth_proto = rte_be_to_cpu_16
5807 ((((const struct rte_flow_action_of_push_vlan *)
5808 actions->conf)->ethertype));
5809 found_action = mlx5_flow_find_action
5811 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5813 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5814 found_action = mlx5_flow_find_action
5816 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5818 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5819 if (flow_dv_create_action_push_vlan
5820 (dev, attr, &vlan, dev_flow, error))
5822 dev_flow->dv.actions[actions_n++] =
5823 dev_flow->dv.push_vlan_res->action;
5824 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5826 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5827 /* of_vlan_push action handled this action */
5828 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5830 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5831 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5833 flow_dev_get_vlan_info_from_items(items, &vlan);
5834 mlx5_update_vlan_vid_pcp(actions, &vlan);
5835 /* If no VLAN push - this is a modify header action */
5836 if (flow_dv_convert_action_modify_vlan_vid
5837 (&res, actions, error))
5839 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5841 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5842 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5843 if (flow_dv_create_action_l2_encap(dev, actions,
5848 dev_flow->dv.actions[actions_n++] =
5849 dev_flow->dv.encap_decap->verbs_action;
5850 action_flags |= actions->type ==
5851 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5852 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5853 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5855 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5856 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5857 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5861 dev_flow->dv.actions[actions_n++] =
5862 dev_flow->dv.encap_decap->verbs_action;
5863 action_flags |= actions->type ==
5864 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5865 MLX5_FLOW_ACTION_VXLAN_DECAP :
5866 MLX5_FLOW_ACTION_NVGRE_DECAP;
5868 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5869 /* Handle encap with preceding decap. */
5870 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5871 if (flow_dv_create_action_raw_encap
5872 (dev, actions, dev_flow, attr, error))
5874 dev_flow->dv.actions[actions_n++] =
5875 dev_flow->dv.encap_decap->verbs_action;
5877 /* Handle encap without preceding decap. */
5878 if (flow_dv_create_action_l2_encap
5879 (dev, actions, dev_flow, attr->transfer,
5882 dev_flow->dv.actions[actions_n++] =
5883 dev_flow->dv.encap_decap->verbs_action;
5885 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5887 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5888 /* Check if this decap is followed by encap. */
5889 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5890 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5893 /* Handle decap only if it isn't followed by encap. */
5894 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5895 if (flow_dv_create_action_l2_decap
5896 (dev, dev_flow, attr->transfer, error))
5898 dev_flow->dv.actions[actions_n++] =
5899 dev_flow->dv.encap_decap->verbs_action;
5901 /* If decap is followed by encap, handle it at encap. */
5902 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5904 case RTE_FLOW_ACTION_TYPE_JUMP:
5905 jump_data = action->conf;
5906 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5907 jump_data->group, &table,
5911 tbl = flow_dv_tbl_resource_get(dev, table,
5913 attr->transfer, error);
5915 return rte_flow_error_set
5917 RTE_FLOW_ERROR_TYPE_ACTION,
5919 "cannot create jump action.");
5920 jump_tbl_resource.tbl = tbl;
5921 if (flow_dv_jump_tbl_resource_register
5922 (dev, &jump_tbl_resource, dev_flow, error)) {
5923 flow_dv_tbl_resource_release(tbl);
5924 return rte_flow_error_set
5926 RTE_FLOW_ERROR_TYPE_ACTION,
5928 "cannot create jump action.");
5930 dev_flow->dv.actions[actions_n++] =
5931 dev_flow->dv.jump->action;
5932 action_flags |= MLX5_FLOW_ACTION_JUMP;
5934 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5935 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5936 if (flow_dv_convert_action_modify_mac(&res, actions,
5939 action_flags |= actions->type ==
5940 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5941 MLX5_FLOW_ACTION_SET_MAC_SRC :
5942 MLX5_FLOW_ACTION_SET_MAC_DST;
5944 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5945 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5946 if (flow_dv_convert_action_modify_ipv4(&res, actions,
5949 action_flags |= actions->type ==
5950 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5951 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5952 MLX5_FLOW_ACTION_SET_IPV4_DST;
5954 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5955 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5956 if (flow_dv_convert_action_modify_ipv6(&res, actions,
5959 action_flags |= actions->type ==
5960 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5961 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5962 MLX5_FLOW_ACTION_SET_IPV6_DST;
5964 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5965 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5966 if (flow_dv_convert_action_modify_tp(&res, actions,
5970 action_flags |= actions->type ==
5971 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5972 MLX5_FLOW_ACTION_SET_TP_SRC :
5973 MLX5_FLOW_ACTION_SET_TP_DST;
5975 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5976 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5980 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5982 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5983 if (flow_dv_convert_action_modify_ttl(&res, actions,
5987 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5989 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5990 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5991 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5994 action_flags |= actions->type ==
5995 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5996 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5997 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6000 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6001 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6002 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
6005 action_flags |= actions->type ==
6006 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6007 MLX5_FLOW_ACTION_INC_TCP_ACK :
6008 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6010 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6011 if (flow_dv_convert_action_set_reg(&res, actions,
6014 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6016 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6017 if (flow_dv_convert_action_copy_mreg(dev, &res,
6020 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6022 case RTE_FLOW_ACTION_TYPE_END:
6024 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
6025 /* create modify action if needed. */
6026 if (flow_dv_modify_hdr_resource_register
6031 dev_flow->dv.actions[modify_action_position] =
6032 dev_flow->dv.modify_hdr->verbs_action;
6038 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
6039 modify_action_position == UINT32_MAX)
6040 modify_action_position = actions_n++;
6042 dev_flow->dv.actions_n = actions_n;
6043 dev_flow->actions = action_flags;
6044 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6045 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6046 int item_type = items->type;
6048 switch (item_type) {
6049 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6050 flow_dv_translate_item_port_id(dev, match_mask,
6051 match_value, items);
6052 last_item = MLX5_FLOW_ITEM_PORT_ID;
6054 case RTE_FLOW_ITEM_TYPE_ETH:
6055 flow_dv_translate_item_eth(match_mask, match_value,
6057 matcher.priority = MLX5_PRIORITY_MAP_L2;
6058 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6059 MLX5_FLOW_LAYER_OUTER_L2;
6061 case RTE_FLOW_ITEM_TYPE_VLAN:
6062 flow_dv_translate_item_vlan(dev_flow,
6063 match_mask, match_value,
6065 matcher.priority = MLX5_PRIORITY_MAP_L2;
6066 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6067 MLX5_FLOW_LAYER_INNER_VLAN) :
6068 (MLX5_FLOW_LAYER_OUTER_L2 |
6069 MLX5_FLOW_LAYER_OUTER_VLAN);
6071 case RTE_FLOW_ITEM_TYPE_IPV4:
6072 mlx5_flow_tunnel_ip_check(items, next_protocol,
6073 &item_flags, &tunnel);
6074 flow_dv_translate_item_ipv4(match_mask, match_value,
6077 matcher.priority = MLX5_PRIORITY_MAP_L3;
6078 dev_flow->hash_fields |=
6079 mlx5_flow_hashfields_adjust
6081 MLX5_IPV4_LAYER_TYPES,
6082 MLX5_IPV4_IBV_RX_HASH);
6083 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6084 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6085 if (items->mask != NULL &&
6086 ((const struct rte_flow_item_ipv4 *)
6087 items->mask)->hdr.next_proto_id) {
6089 ((const struct rte_flow_item_ipv4 *)
6090 (items->spec))->hdr.next_proto_id;
6092 ((const struct rte_flow_item_ipv4 *)
6093 (items->mask))->hdr.next_proto_id;
6095 /* Reset for inner layer. */
6096 next_protocol = 0xff;
6099 case RTE_FLOW_ITEM_TYPE_IPV6:
6100 mlx5_flow_tunnel_ip_check(items, next_protocol,
6101 &item_flags, &tunnel);
6102 flow_dv_translate_item_ipv6(match_mask, match_value,
6105 matcher.priority = MLX5_PRIORITY_MAP_L3;
6106 dev_flow->hash_fields |=
6107 mlx5_flow_hashfields_adjust
6109 MLX5_IPV6_LAYER_TYPES,
6110 MLX5_IPV6_IBV_RX_HASH);
6111 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6112 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6113 if (items->mask != NULL &&
6114 ((const struct rte_flow_item_ipv6 *)
6115 items->mask)->hdr.proto) {
6117 ((const struct rte_flow_item_ipv6 *)
6118 items->spec)->hdr.proto;
6120 ((const struct rte_flow_item_ipv6 *)
6121 items->mask)->hdr.proto;
6123 /* Reset for inner layer. */
6124 next_protocol = 0xff;
6127 case RTE_FLOW_ITEM_TYPE_TCP:
6128 flow_dv_translate_item_tcp(match_mask, match_value,
6130 matcher.priority = MLX5_PRIORITY_MAP_L4;
6131 dev_flow->hash_fields |=
6132 mlx5_flow_hashfields_adjust
6133 (dev_flow, tunnel, ETH_RSS_TCP,
6134 IBV_RX_HASH_SRC_PORT_TCP |
6135 IBV_RX_HASH_DST_PORT_TCP);
6136 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6137 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6139 case RTE_FLOW_ITEM_TYPE_UDP:
6140 flow_dv_translate_item_udp(match_mask, match_value,
6142 matcher.priority = MLX5_PRIORITY_MAP_L4;
6143 dev_flow->hash_fields |=
6144 mlx5_flow_hashfields_adjust
6145 (dev_flow, tunnel, ETH_RSS_UDP,
6146 IBV_RX_HASH_SRC_PORT_UDP |
6147 IBV_RX_HASH_DST_PORT_UDP);
6148 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6149 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6151 case RTE_FLOW_ITEM_TYPE_GRE:
6152 flow_dv_translate_item_gre(match_mask, match_value,
6154 last_item = MLX5_FLOW_LAYER_GRE;
6156 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6157 flow_dv_translate_item_gre_key(match_mask,
6158 match_value, items);
6159 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6161 case RTE_FLOW_ITEM_TYPE_NVGRE:
6162 flow_dv_translate_item_nvgre(match_mask, match_value,
6164 last_item = MLX5_FLOW_LAYER_GRE;
6166 case RTE_FLOW_ITEM_TYPE_VXLAN:
6167 flow_dv_translate_item_vxlan(match_mask, match_value,
6169 last_item = MLX5_FLOW_LAYER_VXLAN;
6171 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6172 flow_dv_translate_item_vxlan(match_mask, match_value,
6174 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6176 case RTE_FLOW_ITEM_TYPE_GENEVE:
6177 flow_dv_translate_item_geneve(match_mask, match_value,
6179 last_item = MLX5_FLOW_LAYER_GENEVE;
6181 case RTE_FLOW_ITEM_TYPE_MPLS:
6182 flow_dv_translate_item_mpls(match_mask, match_value,
6183 items, last_item, tunnel);
6184 last_item = MLX5_FLOW_LAYER_MPLS;
6186 case RTE_FLOW_ITEM_TYPE_META:
6187 flow_dv_translate_item_meta(match_mask, match_value,
6189 last_item = MLX5_FLOW_ITEM_METADATA;
6191 case RTE_FLOW_ITEM_TYPE_ICMP:
6192 flow_dv_translate_item_icmp(match_mask, match_value,
6194 last_item = MLX5_FLOW_LAYER_ICMP;
6196 case RTE_FLOW_ITEM_TYPE_ICMP6:
6197 flow_dv_translate_item_icmp6(match_mask, match_value,
6199 last_item = MLX5_FLOW_LAYER_ICMP6;
6201 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6202 flow_dv_translate_mlx5_item_tag(match_mask,
6203 match_value, items);
6204 last_item = MLX5_FLOW_ITEM_TAG;
6206 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6207 flow_dv_translate_item_tx_queue(dev, match_mask,
6210 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6215 item_flags |= last_item;
6218 * In case of ingress traffic when E-Switch mode is enabled,
6219 * we have two cases where we need to set the source port manually.
6220 * The first one, is in case of Nic steering rule, and the second is
6221 * E-Switch rule where no port_id item was found. In both cases
6222 * the source port is set according the current port in use.
6224 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6225 (priv->representor || priv->master)) {
6226 if (flow_dv_translate_item_port_id(dev, match_mask,
6230 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6231 dev_flow->dv.value.buf));
6232 dev_flow->layers = item_flags;
6233 /* Register matcher. */
6234 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6236 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6238 matcher.egress = attr->egress;
6239 matcher.group = dev_flow->group;
6240 matcher.transfer = attr->transfer;
6241 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6247 * Apply the flow to the NIC.
6250 * Pointer to the Ethernet device structure.
6251 * @param[in, out] flow
6252 * Pointer to flow structure.
6254 * Pointer to error structure.
6257 * 0 on success, a negative errno value otherwise and rte_errno is set.
6260 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6261 struct rte_flow_error *error)
6263 struct mlx5_flow_dv *dv;
6264 struct mlx5_flow *dev_flow;
6265 struct mlx5_priv *priv = dev->data->dev_private;
6269 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6272 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6273 if (dev_flow->transfer) {
6274 dv->actions[n++] = priv->sh->esw_drop_action;
6276 dv->hrxq = mlx5_hrxq_drop_new(dev);
6280 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6282 "cannot get drop hash queue");
6285 dv->actions[n++] = dv->hrxq->action;
6287 } else if (dev_flow->actions &
6288 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6289 struct mlx5_hrxq *hrxq;
6291 assert(flow->rss.queue);
6292 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6293 MLX5_RSS_HASH_KEY_LEN,
6294 dev_flow->hash_fields,
6296 flow->rss.queue_num);
6298 hrxq = mlx5_hrxq_new
6299 (dev, flow->rss.key,
6300 MLX5_RSS_HASH_KEY_LEN,
6301 dev_flow->hash_fields,
6303 flow->rss.queue_num,
6304 !!(dev_flow->layers &
6305 MLX5_FLOW_LAYER_TUNNEL));
6310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6311 "cannot get hash queue");
6315 dv->actions[n++] = dv->hrxq->action;
6318 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6319 (void *)&dv->value, n,
6322 rte_flow_error_set(error, errno,
6323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6325 "hardware refuses to create flow");
6328 if (priv->vmwa_context &&
6329 dev_flow->dv.vf_vlan.tag &&
6330 !dev_flow->dv.vf_vlan.created) {
6332 * The rule contains the VLAN pattern.
6333 * For VF we are going to create VLAN
6334 * interface to make hypervisor set correct
6335 * e-Switch vport context.
6337 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6342 err = rte_errno; /* Save rte_errno before cleanup. */
6343 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6344 struct mlx5_flow_dv *dv = &dev_flow->dv;
6346 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6347 mlx5_hrxq_drop_release(dev);
6349 mlx5_hrxq_release(dev, dv->hrxq);
6352 if (dev_flow->dv.vf_vlan.tag &&
6353 dev_flow->dv.vf_vlan.created)
6354 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6356 rte_errno = err; /* Restore rte_errno. */
6361 * Release the flow matcher.
6364 * Pointer to Ethernet device.
6366 * Pointer to mlx5_flow.
6369 * 1 while a reference on it exists, 0 when freed.
6372 flow_dv_matcher_release(struct rte_eth_dev *dev,
6373 struct mlx5_flow *flow)
6375 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6376 struct mlx5_priv *priv = dev->data->dev_private;
6377 struct mlx5_ibv_shared *sh = priv->sh;
6378 struct mlx5_flow_tbl_resource *tbl;
6380 assert(matcher->matcher_object);
6381 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6382 dev->data->port_id, (void *)matcher,
6383 rte_atomic32_read(&matcher->refcnt));
6384 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6385 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6386 (matcher->matcher_object));
6387 LIST_REMOVE(matcher, next);
6388 if (matcher->egress)
6389 tbl = &sh->tx_tbl[matcher->group];
6391 tbl = &sh->rx_tbl[matcher->group];
6392 flow_dv_tbl_resource_release(tbl);
6394 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6395 dev->data->port_id, (void *)matcher);
6402 * Release an encap/decap resource.
6405 * Pointer to mlx5_flow.
6408 * 1 while a reference on it exists, 0 when freed.
6411 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6413 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6414 flow->dv.encap_decap;
6416 assert(cache_resource->verbs_action);
6417 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6418 (void *)cache_resource,
6419 rte_atomic32_read(&cache_resource->refcnt));
6420 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6421 claim_zero(mlx5_glue->destroy_flow_action
6422 (cache_resource->verbs_action));
6423 LIST_REMOVE(cache_resource, next);
6424 rte_free(cache_resource);
6425 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6426 (void *)cache_resource);
6433 * Release an jump to table action resource.
6436 * Pointer to mlx5_flow.
6439 * 1 while a reference on it exists, 0 when freed.
6442 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6444 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6447 assert(cache_resource->action);
6448 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6449 (void *)cache_resource,
6450 rte_atomic32_read(&cache_resource->refcnt));
6451 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6452 claim_zero(mlx5_glue->destroy_flow_action
6453 (cache_resource->action));
6454 LIST_REMOVE(cache_resource, next);
6455 flow_dv_tbl_resource_release(cache_resource->tbl);
6456 rte_free(cache_resource);
6457 DRV_LOG(DEBUG, "jump table resource %p: removed",
6458 (void *)cache_resource);
6465 * Release a modify-header resource.
6468 * Pointer to mlx5_flow.
6471 * 1 while a reference on it exists, 0 when freed.
6474 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6476 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6477 flow->dv.modify_hdr;
6479 assert(cache_resource->verbs_action);
6480 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6481 (void *)cache_resource,
6482 rte_atomic32_read(&cache_resource->refcnt));
6483 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6484 claim_zero(mlx5_glue->destroy_flow_action
6485 (cache_resource->verbs_action));
6486 LIST_REMOVE(cache_resource, next);
6487 rte_free(cache_resource);
6488 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6489 (void *)cache_resource);
6496 * Release port ID action resource.
6499 * Pointer to mlx5_flow.
6502 * 1 while a reference on it exists, 0 when freed.
6505 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6507 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6508 flow->dv.port_id_action;
6510 assert(cache_resource->action);
6511 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6512 (void *)cache_resource,
6513 rte_atomic32_read(&cache_resource->refcnt));
6514 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6515 claim_zero(mlx5_glue->destroy_flow_action
6516 (cache_resource->action));
6517 LIST_REMOVE(cache_resource, next);
6518 rte_free(cache_resource);
6519 DRV_LOG(DEBUG, "port id action resource %p: removed",
6520 (void *)cache_resource);
6527 * Release push vlan action resource.
6530 * Pointer to mlx5_flow.
6533 * 1 while a reference on it exists, 0 when freed.
6536 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6538 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6539 flow->dv.push_vlan_res;
6541 assert(cache_resource->action);
6542 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6543 (void *)cache_resource,
6544 rte_atomic32_read(&cache_resource->refcnt));
6545 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6546 claim_zero(mlx5_glue->destroy_flow_action
6547 (cache_resource->action));
6548 LIST_REMOVE(cache_resource, next);
6549 rte_free(cache_resource);
6550 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6551 (void *)cache_resource);
6558 * Remove the flow from the NIC but keeps it in memory.
6561 * Pointer to Ethernet device.
6562 * @param[in, out] flow
6563 * Pointer to flow structure.
6566 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6568 struct mlx5_flow_dv *dv;
6569 struct mlx5_flow *dev_flow;
6573 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6576 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6580 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6581 mlx5_hrxq_drop_release(dev);
6583 mlx5_hrxq_release(dev, dv->hrxq);
6586 if (dev_flow->dv.vf_vlan.tag &&
6587 dev_flow->dv.vf_vlan.created)
6588 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6593 * Remove the flow from the NIC and the memory.
6596 * Pointer to the Ethernet device structure.
6597 * @param[in, out] flow
6598 * Pointer to flow structure.
6601 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6603 struct mlx5_flow *dev_flow;
6607 flow_dv_remove(dev, flow);
6608 if (flow->counter) {
6609 flow_dv_counter_release(dev, flow->counter);
6610 flow->counter = NULL;
6612 while (!LIST_EMPTY(&flow->dev_flows)) {
6613 dev_flow = LIST_FIRST(&flow->dev_flows);
6614 LIST_REMOVE(dev_flow, next);
6615 if (dev_flow->dv.matcher)
6616 flow_dv_matcher_release(dev, dev_flow);
6617 if (dev_flow->dv.encap_decap)
6618 flow_dv_encap_decap_resource_release(dev_flow);
6619 if (dev_flow->dv.modify_hdr)
6620 flow_dv_modify_hdr_resource_release(dev_flow);
6621 if (dev_flow->dv.jump)
6622 flow_dv_jump_tbl_resource_release(dev_flow);
6623 if (dev_flow->dv.port_id_action)
6624 flow_dv_port_id_action_resource_release(dev_flow);
6625 if (dev_flow->dv.push_vlan_res)
6626 flow_dv_push_vlan_action_resource_release(dev_flow);
6627 if (dev_flow->dv.tag_resource)
6628 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
6634 * Query a dv flow rule for its statistics via devx.
6637 * Pointer to Ethernet device.
6639 * Pointer to the sub flow.
6641 * data retrieved by the query.
6643 * Perform verbose error reporting if not NULL.
6646 * 0 on success, a negative errno value otherwise and rte_errno is set.
6649 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6650 void *data, struct rte_flow_error *error)
6652 struct mlx5_priv *priv = dev->data->dev_private;
6653 struct rte_flow_query_count *qc = data;
6655 if (!priv->config.devx)
6656 return rte_flow_error_set(error, ENOTSUP,
6657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6659 "counters are not supported");
6660 if (flow->counter) {
6661 uint64_t pkts, bytes;
6662 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6666 return rte_flow_error_set(error, -err,
6667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6668 NULL, "cannot read counters");
6671 qc->hits = pkts - flow->counter->hits;
6672 qc->bytes = bytes - flow->counter->bytes;
6674 flow->counter->hits = pkts;
6675 flow->counter->bytes = bytes;
6679 return rte_flow_error_set(error, EINVAL,
6680 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6682 "counters are not available");
6688 * @see rte_flow_query()
6692 flow_dv_query(struct rte_eth_dev *dev,
6693 struct rte_flow *flow __rte_unused,
6694 const struct rte_flow_action *actions __rte_unused,
6695 void *data __rte_unused,
6696 struct rte_flow_error *error __rte_unused)
6700 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6701 switch (actions->type) {
6702 case RTE_FLOW_ACTION_TYPE_VOID:
6704 case RTE_FLOW_ACTION_TYPE_COUNT:
6705 ret = flow_dv_query_count(dev, flow, data, error);
6708 return rte_flow_error_set(error, ENOTSUP,
6709 RTE_FLOW_ERROR_TYPE_ACTION,
6711 "action not supported");
6718 * Mutex-protected thunk to flow_dv_translate().
6721 flow_d_translate(struct rte_eth_dev *dev,
6722 struct mlx5_flow *dev_flow,
6723 const struct rte_flow_attr *attr,
6724 const struct rte_flow_item items[],
6725 const struct rte_flow_action actions[],
6726 struct rte_flow_error *error)
6730 flow_d_shared_lock(dev);
6731 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6732 flow_d_shared_unlock(dev);
6737 * Mutex-protected thunk to flow_dv_apply().
6740 flow_d_apply(struct rte_eth_dev *dev,
6741 struct rte_flow *flow,
6742 struct rte_flow_error *error)
6746 flow_d_shared_lock(dev);
6747 ret = flow_dv_apply(dev, flow, error);
6748 flow_d_shared_unlock(dev);
6753 * Mutex-protected thunk to flow_dv_remove().
6756 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6758 flow_d_shared_lock(dev);
6759 flow_dv_remove(dev, flow);
6760 flow_d_shared_unlock(dev);
6764 * Mutex-protected thunk to flow_dv_destroy().
6767 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6769 flow_d_shared_lock(dev);
6770 flow_dv_destroy(dev, flow);
6771 flow_d_shared_unlock(dev);
6774 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6775 .validate = flow_dv_validate,
6776 .prepare = flow_dv_prepare,
6777 .translate = flow_d_translate,
6778 .apply = flow_d_apply,
6779 .remove = flow_d_remove,
6780 .destroy = flow_d_destroy,
6781 .query = flow_dv_query,
6784 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */