1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 static inline uint16_t
97 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
99 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
100 return RTE_ETHER_TYPE_TEB;
101 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 return RTE_ETHER_TYPE_IPV4;
103 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 return RTE_ETHER_TYPE_IPV6;
105 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
106 return RTE_ETHER_TYPE_MPLS;
111 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
113 struct mlx5_priv *priv = dev->data->dev_private;
115 if (priv->pci_dev == NULL)
117 switch (priv->pci_dev->id.device_id) {
118 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
119 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
120 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
121 return (int16_t)0xfffe;
128 * Initialize flow attributes structure according to flow items' types.
130 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
131 * mode. For tunnel mode, the items to be modified are the outermost ones.
134 * Pointer to item specification.
136 * Pointer to flow attributes structure.
137 * @param[in] dev_flow
138 * Pointer to the sub flow.
139 * @param[in] tunnel_decap
140 * Whether action is after tunnel decapsulation.
143 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
144 struct mlx5_flow *dev_flow, bool tunnel_decap)
146 uint64_t layers = dev_flow->handle->layers;
149 * If layers is already initialized, it means this dev_flow is the
150 * suffix flow, the layers flags is set by the prefix flow. Need to
151 * use the layer flags from prefix flow as the suffix flow may not
152 * have the user defined items as the flow is split.
155 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
157 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
159 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
161 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
166 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
167 uint8_t next_protocol = 0xff;
168 switch (item->type) {
169 case RTE_FLOW_ITEM_TYPE_GRE:
170 case RTE_FLOW_ITEM_TYPE_NVGRE:
171 case RTE_FLOW_ITEM_TYPE_VXLAN:
172 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
173 case RTE_FLOW_ITEM_TYPE_GENEVE:
174 case RTE_FLOW_ITEM_TYPE_MPLS:
178 case RTE_FLOW_ITEM_TYPE_IPV4:
181 if (item->mask != NULL &&
182 ((const struct rte_flow_item_ipv4 *)
183 item->mask)->hdr.next_proto_id)
185 ((const struct rte_flow_item_ipv4 *)
186 (item->spec))->hdr.next_proto_id &
187 ((const struct rte_flow_item_ipv4 *)
188 (item->mask))->hdr.next_proto_id;
189 if ((next_protocol == IPPROTO_IPIP ||
190 next_protocol == IPPROTO_IPV6) && tunnel_decap)
193 case RTE_FLOW_ITEM_TYPE_IPV6:
196 if (item->mask != NULL &&
197 ((const struct rte_flow_item_ipv6 *)
198 item->mask)->hdr.proto)
200 ((const struct rte_flow_item_ipv6 *)
201 (item->spec))->hdr.proto &
202 ((const struct rte_flow_item_ipv6 *)
203 (item->mask))->hdr.proto;
204 if ((next_protocol == IPPROTO_IPIP ||
205 next_protocol == IPPROTO_IPV6) && tunnel_decap)
208 case RTE_FLOW_ITEM_TYPE_UDP:
212 case RTE_FLOW_ITEM_TYPE_TCP:
224 * Convert rte_mtr_color to mlx5 color.
233 rte_col_2_mlx5_col(enum rte_color rcol)
236 case RTE_COLOR_GREEN:
237 return MLX5_FLOW_COLOR_GREEN;
238 case RTE_COLOR_YELLOW:
239 return MLX5_FLOW_COLOR_YELLOW;
241 return MLX5_FLOW_COLOR_RED;
245 return MLX5_FLOW_COLOR_UNDEFINED;
248 struct field_modify_info {
249 uint32_t size; /* Size of field in protocol header, in bytes. */
250 uint32_t offset; /* Offset of field in protocol header, in bytes. */
251 enum mlx5_modification_field id;
254 struct field_modify_info modify_eth[] = {
255 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
256 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
257 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
258 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
262 struct field_modify_info modify_vlan_out_first_vid[] = {
263 /* Size in bits !!! */
264 {12, 0, MLX5_MODI_OUT_FIRST_VID},
268 struct field_modify_info modify_ipv4[] = {
269 {1, 1, MLX5_MODI_OUT_IP_DSCP},
270 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
271 {4, 12, MLX5_MODI_OUT_SIPV4},
272 {4, 16, MLX5_MODI_OUT_DIPV4},
276 struct field_modify_info modify_ipv6[] = {
277 {1, 0, MLX5_MODI_OUT_IP_DSCP},
278 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
279 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
280 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
281 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
282 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
283 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
284 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
285 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
286 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
290 struct field_modify_info modify_udp[] = {
291 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
292 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
296 struct field_modify_info modify_tcp[] = {
297 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
298 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
299 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
300 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
305 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
306 uint8_t next_protocol, uint64_t *item_flags,
309 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
310 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
311 if (next_protocol == IPPROTO_IPIP) {
312 *item_flags |= MLX5_FLOW_LAYER_IPIP;
315 if (next_protocol == IPPROTO_IPV6) {
316 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
321 static inline struct mlx5_hlist *
322 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
323 const char *name, uint32_t size, bool direct_key,
324 bool lcores_share, void *ctx,
325 mlx5_list_create_cb cb_create,
326 mlx5_list_match_cb cb_match,
327 mlx5_list_remove_cb cb_remove,
328 mlx5_list_clone_cb cb_clone,
329 mlx5_list_clone_free_cb cb_clone_free)
331 struct mlx5_hlist *hl;
332 struct mlx5_hlist *expected = NULL;
333 char s[MLX5_NAME_SIZE];
335 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
338 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
339 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
340 ctx, cb_create, cb_match, cb_remove, cb_clone,
343 DRV_LOG(ERR, "%s hash creation failed", name);
347 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
350 mlx5_hlist_destroy(hl);
351 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
356 /* Update VLAN's VID/PCP based on input rte_flow_action.
359 * Pointer to struct rte_flow_action.
361 * Pointer to struct rte_vlan_hdr.
364 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
365 struct rte_vlan_hdr *vlan)
368 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
370 ((const struct rte_flow_action_of_set_vlan_pcp *)
371 action->conf)->vlan_pcp;
372 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
373 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
374 vlan->vlan_tci |= vlan_tci;
375 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
376 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
377 vlan->vlan_tci |= rte_be_to_cpu_16
378 (((const struct rte_flow_action_of_set_vlan_vid *)
379 action->conf)->vlan_vid);
384 * Fetch 1, 2, 3 or 4 byte field from the byte array
385 * and return as unsigned integer in host-endian format.
388 * Pointer to data array.
390 * Size of field to extract.
393 * converted field in host endian format.
395 static inline uint32_t
396 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
405 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
408 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
409 ret = (ret << 8) | *(data + sizeof(uint16_t));
412 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
423 * Convert modify-header action to DV specification.
425 * Data length of each action is determined by provided field description
426 * and the item mask. Data bit offset and width of each action is determined
427 * by provided item mask.
430 * Pointer to item specification.
432 * Pointer to field modification information.
433 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
434 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
435 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
437 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
438 * Negative offset value sets the same offset as source offset.
439 * size field is ignored, value is taken from source field.
440 * @param[in,out] resource
441 * Pointer to the modify-header resource.
443 * Type of modification.
445 * Pointer to the error structure.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 flow_dv_convert_modify_action(struct rte_flow_item *item,
452 struct field_modify_info *field,
453 struct field_modify_info *dcopy,
454 struct mlx5_flow_dv_modify_hdr_resource *resource,
455 uint32_t type, struct rte_flow_error *error)
457 uint32_t i = resource->actions_num;
458 struct mlx5_modification_cmd *actions = resource->actions;
459 uint32_t carry_b = 0;
462 * The item and mask are provided in big-endian format.
463 * The fields should be presented as in big-endian format either.
464 * Mask must be always present, it defines the actual field width.
466 MLX5_ASSERT(item->mask);
467 MLX5_ASSERT(field->size);
473 bool next_field = true;
474 bool next_dcopy = true;
476 if (i >= MLX5_MAX_MODIFY_NUM)
477 return rte_flow_error_set(error, EINVAL,
478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
479 "too many items to modify");
480 /* Fetch variable byte size mask from the array. */
481 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
482 field->offset, field->size);
487 /* Deduce actual data width in bits from mask value. */
488 off_b = rte_bsf32(mask) + carry_b;
489 size_b = sizeof(uint32_t) * CHAR_BIT -
490 off_b - __builtin_clz(mask);
492 actions[i] = (struct mlx5_modification_cmd) {
496 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
499 if (type == MLX5_MODIFICATION_TYPE_COPY) {
501 actions[i].dst_field = dcopy->id;
502 actions[i].dst_offset =
503 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
504 /* Convert entire record to big-endian format. */
505 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
507 * Destination field overflow. Copy leftovers of
508 * a source field to the next destination field.
511 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
514 dcopy->size * CHAR_BIT - dcopy->offset;
515 carry_b = actions[i].length;
519 * Not enough bits in a source filed to fill a
520 * destination field. Switch to the next source.
522 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
523 (size_b == field->size * CHAR_BIT - off_b)) {
525 field->size * CHAR_BIT - off_b;
526 dcopy->offset += actions[i].length;
532 MLX5_ASSERT(item->spec);
533 data = flow_dv_fetch_field((const uint8_t *)item->spec +
534 field->offset, field->size);
535 /* Shift out the trailing masked bits from data. */
536 data = (data & mask) >> off_b;
537 actions[i].data1 = rte_cpu_to_be_32(data);
539 /* Convert entire record to expected big-endian format. */
540 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
544 } while (field->size);
545 if (resource->actions_num == i)
546 return rte_flow_error_set(error, EINVAL,
547 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
548 "invalid modification flow item");
549 resource->actions_num = i;
554 * Convert modify-header set IPv4 address action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to the error structure.
564 * 0 on success, a negative errno value otherwise and rte_errno is set.
567 flow_dv_convert_action_modify_ipv4
568 (struct mlx5_flow_dv_modify_hdr_resource *resource,
569 const struct rte_flow_action *action,
570 struct rte_flow_error *error)
572 const struct rte_flow_action_set_ipv4 *conf =
573 (const struct rte_flow_action_set_ipv4 *)(action->conf);
574 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
575 struct rte_flow_item_ipv4 ipv4;
576 struct rte_flow_item_ipv4 ipv4_mask;
578 memset(&ipv4, 0, sizeof(ipv4));
579 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
580 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
581 ipv4.hdr.src_addr = conf->ipv4_addr;
582 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
584 ipv4.hdr.dst_addr = conf->ipv4_addr;
585 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
588 item.mask = &ipv4_mask;
589 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
590 MLX5_MODIFICATION_TYPE_SET, error);
594 * Convert modify-header set IPv6 address action to DV specification.
596 * @param[in,out] resource
597 * Pointer to the modify-header resource.
599 * Pointer to action specification.
601 * Pointer to the error structure.
604 * 0 on success, a negative errno value otherwise and rte_errno is set.
607 flow_dv_convert_action_modify_ipv6
608 (struct mlx5_flow_dv_modify_hdr_resource *resource,
609 const struct rte_flow_action *action,
610 struct rte_flow_error *error)
612 const struct rte_flow_action_set_ipv6 *conf =
613 (const struct rte_flow_action_set_ipv6 *)(action->conf);
614 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
615 struct rte_flow_item_ipv6 ipv6;
616 struct rte_flow_item_ipv6 ipv6_mask;
618 memset(&ipv6, 0, sizeof(ipv6));
619 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
620 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
621 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
622 sizeof(ipv6.hdr.src_addr));
623 memcpy(&ipv6_mask.hdr.src_addr,
624 &rte_flow_item_ipv6_mask.hdr.src_addr,
625 sizeof(ipv6.hdr.src_addr));
627 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
628 sizeof(ipv6.hdr.dst_addr));
629 memcpy(&ipv6_mask.hdr.dst_addr,
630 &rte_flow_item_ipv6_mask.hdr.dst_addr,
631 sizeof(ipv6.hdr.dst_addr));
634 item.mask = &ipv6_mask;
635 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
636 MLX5_MODIFICATION_TYPE_SET, error);
640 * Convert modify-header set MAC address action to DV specification.
642 * @param[in,out] resource
643 * Pointer to the modify-header resource.
645 * Pointer to action specification.
647 * Pointer to the error structure.
650 * 0 on success, a negative errno value otherwise and rte_errno is set.
653 flow_dv_convert_action_modify_mac
654 (struct mlx5_flow_dv_modify_hdr_resource *resource,
655 const struct rte_flow_action *action,
656 struct rte_flow_error *error)
658 const struct rte_flow_action_set_mac *conf =
659 (const struct rte_flow_action_set_mac *)(action->conf);
660 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
661 struct rte_flow_item_eth eth;
662 struct rte_flow_item_eth eth_mask;
664 memset(ð, 0, sizeof(eth));
665 memset(ð_mask, 0, sizeof(eth_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
667 memcpy(ð.src.addr_bytes, &conf->mac_addr,
668 sizeof(eth.src.addr_bytes));
669 memcpy(ð_mask.src.addr_bytes,
670 &rte_flow_item_eth_mask.src.addr_bytes,
671 sizeof(eth_mask.src.addr_bytes));
673 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
674 sizeof(eth.dst.addr_bytes));
675 memcpy(ð_mask.dst.addr_bytes,
676 &rte_flow_item_eth_mask.dst.addr_bytes,
677 sizeof(eth_mask.dst.addr_bytes));
680 item.mask = ð_mask;
681 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
682 MLX5_MODIFICATION_TYPE_SET, error);
686 * Convert modify-header set VLAN VID action to DV specification.
688 * @param[in,out] resource
689 * Pointer to the modify-header resource.
691 * Pointer to action specification.
693 * Pointer to the error structure.
696 * 0 on success, a negative errno value otherwise and rte_errno is set.
699 flow_dv_convert_action_modify_vlan_vid
700 (struct mlx5_flow_dv_modify_hdr_resource *resource,
701 const struct rte_flow_action *action,
702 struct rte_flow_error *error)
704 const struct rte_flow_action_of_set_vlan_vid *conf =
705 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
706 int i = resource->actions_num;
707 struct mlx5_modification_cmd *actions = resource->actions;
708 struct field_modify_info *field = modify_vlan_out_first_vid;
710 if (i >= MLX5_MAX_MODIFY_NUM)
711 return rte_flow_error_set(error, EINVAL,
712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
713 "too many items to modify");
714 actions[i] = (struct mlx5_modification_cmd) {
715 .action_type = MLX5_MODIFICATION_TYPE_SET,
717 .length = field->size,
718 .offset = field->offset,
720 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
721 actions[i].data1 = conf->vlan_vid;
722 actions[i].data1 = actions[i].data1 << 16;
723 resource->actions_num = ++i;
728 * Convert modify-header set TP action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_tp
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_tp *conf =
757 (const struct rte_flow_action_set_tp *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_udp udp;
760 struct rte_flow_item_udp udp_mask;
761 struct rte_flow_item_tcp tcp;
762 struct rte_flow_item_tcp tcp_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&udp, 0, sizeof(udp));
769 memset(&udp_mask, 0, sizeof(udp_mask));
770 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
771 udp.hdr.src_port = conf->port;
772 udp_mask.hdr.src_port =
773 rte_flow_item_udp_mask.hdr.src_port;
775 udp.hdr.dst_port = conf->port;
776 udp_mask.hdr.dst_port =
777 rte_flow_item_udp_mask.hdr.dst_port;
779 item.type = RTE_FLOW_ITEM_TYPE_UDP;
781 item.mask = &udp_mask;
784 MLX5_ASSERT(attr->tcp);
785 memset(&tcp, 0, sizeof(tcp));
786 memset(&tcp_mask, 0, sizeof(tcp_mask));
787 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
788 tcp.hdr.src_port = conf->port;
789 tcp_mask.hdr.src_port =
790 rte_flow_item_tcp_mask.hdr.src_port;
792 tcp.hdr.dst_port = conf->port;
793 tcp_mask.hdr.dst_port =
794 rte_flow_item_tcp_mask.hdr.dst_port;
796 item.type = RTE_FLOW_ITEM_TYPE_TCP;
798 item.mask = &tcp_mask;
801 return flow_dv_convert_modify_action(&item, field, NULL, resource,
802 MLX5_MODIFICATION_TYPE_SET, error);
806 * Convert modify-header set TTL action to DV specification.
808 * @param[in,out] resource
809 * Pointer to the modify-header resource.
811 * Pointer to action specification.
813 * Pointer to rte_flow_item objects list.
815 * Pointer to flow attributes structure.
816 * @param[in] dev_flow
817 * Pointer to the sub flow.
818 * @param[in] tunnel_decap
819 * Whether action is after tunnel decapsulation.
821 * Pointer to the error structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 flow_dv_convert_action_modify_ttl
828 (struct mlx5_flow_dv_modify_hdr_resource *resource,
829 const struct rte_flow_action *action,
830 const struct rte_flow_item *items,
831 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
832 bool tunnel_decap, struct rte_flow_error *error)
834 const struct rte_flow_action_set_ttl *conf =
835 (const struct rte_flow_action_set_ttl *)(action->conf);
836 struct rte_flow_item item;
837 struct rte_flow_item_ipv4 ipv4;
838 struct rte_flow_item_ipv4 ipv4_mask;
839 struct rte_flow_item_ipv6 ipv6;
840 struct rte_flow_item_ipv6 ipv6_mask;
841 struct field_modify_info *field;
844 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
846 memset(&ipv4, 0, sizeof(ipv4));
847 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
848 ipv4.hdr.time_to_live = conf->ttl_value;
849 ipv4_mask.hdr.time_to_live = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
852 item.mask = &ipv4_mask;
855 MLX5_ASSERT(attr->ipv6);
856 memset(&ipv6, 0, sizeof(ipv6));
857 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
858 ipv6.hdr.hop_limits = conf->ttl_value;
859 ipv6_mask.hdr.hop_limits = 0xFF;
860 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
862 item.mask = &ipv6_mask;
865 return flow_dv_convert_modify_action(&item, field, NULL, resource,
866 MLX5_MODIFICATION_TYPE_SET, error);
870 * Convert modify-header decrement TTL action to DV specification.
872 * @param[in,out] resource
873 * Pointer to the modify-header resource.
875 * Pointer to action specification.
877 * Pointer to rte_flow_item objects list.
879 * Pointer to flow attributes structure.
880 * @param[in] dev_flow
881 * Pointer to the sub flow.
882 * @param[in] tunnel_decap
883 * Whether action is after tunnel decapsulation.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_dec_ttl
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_item *items,
894 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
895 bool tunnel_decap, struct rte_flow_error *error)
897 struct rte_flow_item item;
898 struct rte_flow_item_ipv4 ipv4;
899 struct rte_flow_item_ipv4 ipv4_mask;
900 struct rte_flow_item_ipv6 ipv6;
901 struct rte_flow_item_ipv6 ipv6_mask;
902 struct field_modify_info *field;
905 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
907 memset(&ipv4, 0, sizeof(ipv4));
908 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
909 ipv4.hdr.time_to_live = 0xFF;
910 ipv4_mask.hdr.time_to_live = 0xFF;
911 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
913 item.mask = &ipv4_mask;
916 MLX5_ASSERT(attr->ipv6);
917 memset(&ipv6, 0, sizeof(ipv6));
918 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
919 ipv6.hdr.hop_limits = 0xFF;
920 ipv6_mask.hdr.hop_limits = 0xFF;
921 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
923 item.mask = &ipv6_mask;
926 return flow_dv_convert_modify_action(&item, field, NULL, resource,
927 MLX5_MODIFICATION_TYPE_ADD, error);
931 * Convert modify-header increment/decrement TCP Sequence number
932 * to DV specification.
934 * @param[in,out] resource
935 * Pointer to the modify-header resource.
937 * Pointer to action specification.
939 * Pointer to the error structure.
942 * 0 on success, a negative errno value otherwise and rte_errno is set.
945 flow_dv_convert_action_modify_tcp_seq
946 (struct mlx5_flow_dv_modify_hdr_resource *resource,
947 const struct rte_flow_action *action,
948 struct rte_flow_error *error)
950 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
951 uint64_t value = rte_be_to_cpu_32(*conf);
952 struct rte_flow_item item;
953 struct rte_flow_item_tcp tcp;
954 struct rte_flow_item_tcp tcp_mask;
956 memset(&tcp, 0, sizeof(tcp));
957 memset(&tcp_mask, 0, sizeof(tcp_mask));
958 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
960 * The HW has no decrement operation, only increment operation.
961 * To simulate decrement X from Y using increment operation
962 * we need to add UINT32_MAX X times to Y.
963 * Each adding of UINT32_MAX decrements Y by 1.
966 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
967 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
968 item.type = RTE_FLOW_ITEM_TYPE_TCP;
970 item.mask = &tcp_mask;
971 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
972 MLX5_MODIFICATION_TYPE_ADD, error);
976 * Convert modify-header increment/decrement TCP Acknowledgment number
977 * to DV specification.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_modify_tcp_ack
991 (struct mlx5_flow_dv_modify_hdr_resource *resource,
992 const struct rte_flow_action *action,
993 struct rte_flow_error *error)
995 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
996 uint64_t value = rte_be_to_cpu_32(*conf);
997 struct rte_flow_item item;
998 struct rte_flow_item_tcp tcp;
999 struct rte_flow_item_tcp tcp_mask;
1001 memset(&tcp, 0, sizeof(tcp));
1002 memset(&tcp_mask, 0, sizeof(tcp_mask));
1003 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
1005 * The HW has no decrement operation, only increment operation.
1006 * To simulate decrement X from Y using increment operation
1007 * we need to add UINT32_MAX X times to Y.
1008 * Each adding of UINT32_MAX decrements Y by 1.
1010 value *= UINT32_MAX;
1011 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1012 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1013 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1015 item.mask = &tcp_mask;
1016 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_ADD, error);
1020 static enum mlx5_modification_field reg_to_field[] = {
1021 [REG_NON] = MLX5_MODI_OUT_NONE,
1022 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1023 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1024 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1025 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1026 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1027 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1028 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1029 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1030 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1031 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1035 * Convert register set to DV specification.
1037 * @param[in,out] resource
1038 * Pointer to the modify-header resource.
1040 * Pointer to action specification.
1042 * Pointer to the error structure.
1045 * 0 on success, a negative errno value otherwise and rte_errno is set.
1048 flow_dv_convert_action_set_reg
1049 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1050 const struct rte_flow_action *action,
1051 struct rte_flow_error *error)
1053 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1054 struct mlx5_modification_cmd *actions = resource->actions;
1055 uint32_t i = resource->actions_num;
1057 if (i >= MLX5_MAX_MODIFY_NUM)
1058 return rte_flow_error_set(error, EINVAL,
1059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1060 "too many items to modify");
1061 MLX5_ASSERT(conf->id != REG_NON);
1062 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1063 actions[i] = (struct mlx5_modification_cmd) {
1064 .action_type = MLX5_MODIFICATION_TYPE_SET,
1065 .field = reg_to_field[conf->id],
1066 .offset = conf->offset,
1067 .length = conf->length,
1069 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1070 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1072 resource->actions_num = i;
1077 * Convert SET_TAG action to DV specification.
1080 * Pointer to the rte_eth_dev structure.
1081 * @param[in,out] resource
1082 * Pointer to the modify-header resource.
1084 * Pointer to action specification.
1086 * Pointer to the error structure.
1089 * 0 on success, a negative errno value otherwise and rte_errno is set.
1092 flow_dv_convert_action_set_tag
1093 (struct rte_eth_dev *dev,
1094 struct mlx5_flow_dv_modify_hdr_resource *resource,
1095 const struct rte_flow_action_set_tag *conf,
1096 struct rte_flow_error *error)
1098 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1099 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1100 struct rte_flow_item item = {
1104 struct field_modify_info reg_c_x[] = {
1107 enum mlx5_modification_field reg_type;
1110 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1113 MLX5_ASSERT(ret != REG_NON);
1114 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1115 reg_type = reg_to_field[ret];
1116 MLX5_ASSERT(reg_type > 0);
1117 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1118 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1119 MLX5_MODIFICATION_TYPE_SET, error);
1123 * Convert internal COPY_REG action to DV specification.
1126 * Pointer to the rte_eth_dev structure.
1127 * @param[in,out] res
1128 * Pointer to the modify-header resource.
1130 * Pointer to action specification.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1139 struct mlx5_flow_dv_modify_hdr_resource *res,
1140 const struct rte_flow_action *action,
1141 struct rte_flow_error *error)
1143 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1144 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_src[] = {
1150 {4, 0, reg_to_field[conf->src]},
1153 struct field_modify_info reg_dst = {
1155 .id = reg_to_field[conf->dst],
1157 /* Adjust reg_c[0] usage according to reported mask. */
1158 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1159 struct mlx5_priv *priv = dev->data->dev_private;
1160 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1162 MLX5_ASSERT(reg_c0);
1163 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1164 if (conf->dst == REG_C_0) {
1165 /* Copy to reg_c[0], within mask only. */
1166 reg_dst.offset = rte_bsf32(reg_c0);
1167 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1170 mask = rte_cpu_to_be_32(reg_c0);
1173 return flow_dv_convert_modify_action(&item,
1174 reg_src, ®_dst, res,
1175 MLX5_MODIFICATION_TYPE_COPY,
1180 * Convert MARK action to DV specification. This routine is used
1181 * in extensive metadata only and requires metadata register to be
1182 * handled. In legacy mode hardware tag resource is engaged.
1185 * Pointer to the rte_eth_dev structure.
1187 * Pointer to MARK action specification.
1188 * @param[in,out] resource
1189 * Pointer to the modify-header resource.
1191 * Pointer to the error structure.
1194 * 0 on success, a negative errno value otherwise and rte_errno is set.
1197 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1198 const struct rte_flow_action_mark *conf,
1199 struct mlx5_flow_dv_modify_hdr_resource *resource,
1200 struct rte_flow_error *error)
1202 struct mlx5_priv *priv = dev->data->dev_private;
1203 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1204 priv->sh->dv_mark_mask);
1205 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1206 struct rte_flow_item item = {
1210 struct field_modify_info reg_c_x[] = {
1216 return rte_flow_error_set(error, EINVAL,
1217 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1218 NULL, "zero mark action mask");
1219 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1222 MLX5_ASSERT(reg > 0);
1223 if (reg == REG_C_0) {
1224 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1225 uint32_t shl_c0 = rte_bsf32(msk_c0);
1227 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1228 mask = rte_cpu_to_be_32(mask) & msk_c0;
1229 mask = rte_cpu_to_be_32(mask << shl_c0);
1231 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1232 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1233 MLX5_MODIFICATION_TYPE_SET, error);
1237 * Get metadata register index for specified steering domain.
1240 * Pointer to the rte_eth_dev structure.
1242 * Attributes of flow to determine steering domain.
1244 * Pointer to the error structure.
1247 * positive index on success, a negative errno value otherwise
1248 * and rte_errno is set.
1250 static enum modify_reg
1251 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1252 const struct rte_flow_attr *attr,
1253 struct rte_flow_error *error)
1256 mlx5_flow_get_reg_id(dev, attr->transfer ?
1260 MLX5_METADATA_RX, 0, error);
1262 return rte_flow_error_set(error,
1263 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1264 NULL, "unavailable "
1265 "metadata register");
1270 * Convert SET_META action to DV specification.
1273 * Pointer to the rte_eth_dev structure.
1274 * @param[in,out] resource
1275 * Pointer to the modify-header resource.
1277 * Attributes of flow that includes this item.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_set_meta
1288 (struct rte_eth_dev *dev,
1289 struct mlx5_flow_dv_modify_hdr_resource *resource,
1290 const struct rte_flow_attr *attr,
1291 const struct rte_flow_action_set_meta *conf,
1292 struct rte_flow_error *error)
1294 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1295 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1296 struct rte_flow_item item = {
1300 struct field_modify_info reg_c_x[] = {
1303 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1307 MLX5_ASSERT(reg != REG_NON);
1308 if (reg == REG_C_0) {
1309 struct mlx5_priv *priv = dev->data->dev_private;
1310 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1311 uint32_t shl_c0 = rte_bsf32(msk_c0);
1313 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1314 mask = rte_cpu_to_be_32(mask) & msk_c0;
1315 mask = rte_cpu_to_be_32(mask << shl_c0);
1317 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1318 /* The routine expects parameters in memory as big-endian ones. */
1319 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Convert modify-header set IPv4 DSCP action to DV specification.
1326 * @param[in,out] resource
1327 * Pointer to the modify-header resource.
1329 * Pointer to action specification.
1331 * Pointer to the error structure.
1334 * 0 on success, a negative errno value otherwise and rte_errno is set.
1337 flow_dv_convert_action_modify_ipv4_dscp
1338 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1339 const struct rte_flow_action *action,
1340 struct rte_flow_error *error)
1342 const struct rte_flow_action_set_dscp *conf =
1343 (const struct rte_flow_action_set_dscp *)(action->conf);
1344 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1345 struct rte_flow_item_ipv4 ipv4;
1346 struct rte_flow_item_ipv4 ipv4_mask;
1348 memset(&ipv4, 0, sizeof(ipv4));
1349 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1350 ipv4.hdr.type_of_service = conf->dscp;
1351 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1353 item.mask = &ipv4_mask;
1354 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1355 MLX5_MODIFICATION_TYPE_SET, error);
1359 * Convert modify-header set IPv6 DSCP action to DV specification.
1361 * @param[in,out] resource
1362 * Pointer to the modify-header resource.
1364 * Pointer to action specification.
1366 * Pointer to the error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_convert_action_modify_ipv6_dscp
1373 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1374 const struct rte_flow_action *action,
1375 struct rte_flow_error *error)
1377 const struct rte_flow_action_set_dscp *conf =
1378 (const struct rte_flow_action_set_dscp *)(action->conf);
1379 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1380 struct rte_flow_item_ipv6 ipv6;
1381 struct rte_flow_item_ipv6 ipv6_mask;
1383 memset(&ipv6, 0, sizeof(ipv6));
1384 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1386 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1387 * rdma-core only accept the DSCP bits byte aligned start from
1388 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1389 * bits in IPv6 case as rdma-core requires byte aligned value.
1391 ipv6.hdr.vtc_flow = conf->dscp;
1392 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1394 item.mask = &ipv6_mask;
1395 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1396 MLX5_MODIFICATION_TYPE_SET, error);
1400 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1401 enum rte_flow_field_id field, int inherit,
1402 const struct rte_flow_attr *attr,
1403 struct rte_flow_error *error)
1405 struct mlx5_priv *priv = dev->data->dev_private;
1408 case RTE_FLOW_FIELD_START:
1410 case RTE_FLOW_FIELD_MAC_DST:
1411 case RTE_FLOW_FIELD_MAC_SRC:
1413 case RTE_FLOW_FIELD_VLAN_TYPE:
1415 case RTE_FLOW_FIELD_VLAN_ID:
1417 case RTE_FLOW_FIELD_MAC_TYPE:
1419 case RTE_FLOW_FIELD_IPV4_DSCP:
1421 case RTE_FLOW_FIELD_IPV4_TTL:
1423 case RTE_FLOW_FIELD_IPV4_SRC:
1424 case RTE_FLOW_FIELD_IPV4_DST:
1426 case RTE_FLOW_FIELD_IPV6_DSCP:
1428 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1430 case RTE_FLOW_FIELD_IPV6_SRC:
1431 case RTE_FLOW_FIELD_IPV6_DST:
1433 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1434 case RTE_FLOW_FIELD_TCP_PORT_DST:
1436 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1437 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1439 case RTE_FLOW_FIELD_TCP_FLAGS:
1441 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1442 case RTE_FLOW_FIELD_UDP_PORT_DST:
1444 case RTE_FLOW_FIELD_VXLAN_VNI:
1445 case RTE_FLOW_FIELD_GENEVE_VNI:
1447 case RTE_FLOW_FIELD_GTP_TEID:
1448 case RTE_FLOW_FIELD_TAG:
1450 case RTE_FLOW_FIELD_MARK:
1451 return __builtin_popcount(priv->sh->dv_mark_mask);
1452 case RTE_FLOW_FIELD_META:
1453 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1454 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1455 case RTE_FLOW_FIELD_POINTER:
1456 case RTE_FLOW_FIELD_VALUE:
1457 return inherit < 0 ? 0 : inherit;
1465 mlx5_flow_field_id_to_modify_info
1466 (const struct rte_flow_action_modify_data *data,
1467 struct field_modify_info *info, uint32_t *mask,
1468 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1469 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1471 struct mlx5_priv *priv = dev->data->dev_private;
1475 switch (data->field) {
1476 case RTE_FLOW_FIELD_START:
1477 /* not supported yet */
1480 case RTE_FLOW_FIELD_MAC_DST:
1481 off = data->offset > 16 ? data->offset - 16 : 0;
1483 if (data->offset < 16) {
1484 info[idx] = (struct field_modify_info){2, 4,
1485 MLX5_MODI_OUT_DMAC_15_0};
1487 mask[1] = rte_cpu_to_be_16(0xffff >>
1491 mask[1] = RTE_BE16(0xffff);
1498 info[idx] = (struct field_modify_info){4, 0,
1499 MLX5_MODI_OUT_DMAC_47_16};
1500 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1501 (32 - width)) << off);
1503 if (data->offset < 16)
1504 info[idx++] = (struct field_modify_info){2, 0,
1505 MLX5_MODI_OUT_DMAC_15_0};
1506 info[idx] = (struct field_modify_info){4, off,
1507 MLX5_MODI_OUT_DMAC_47_16};
1510 case RTE_FLOW_FIELD_MAC_SRC:
1511 off = data->offset > 16 ? data->offset - 16 : 0;
1513 if (data->offset < 16) {
1514 info[idx] = (struct field_modify_info){2, 4,
1515 MLX5_MODI_OUT_SMAC_15_0};
1517 mask[1] = rte_cpu_to_be_16(0xffff >>
1521 mask[1] = RTE_BE16(0xffff);
1528 info[idx] = (struct field_modify_info){4, 0,
1529 MLX5_MODI_OUT_SMAC_47_16};
1530 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1531 (32 - width)) << off);
1533 if (data->offset < 16)
1534 info[idx++] = (struct field_modify_info){2, 0,
1535 MLX5_MODI_OUT_SMAC_15_0};
1536 info[idx] = (struct field_modify_info){4, off,
1537 MLX5_MODI_OUT_SMAC_47_16};
1540 case RTE_FLOW_FIELD_VLAN_TYPE:
1541 /* not supported yet */
1543 case RTE_FLOW_FIELD_VLAN_ID:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_FIRST_VID};
1547 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1549 case RTE_FLOW_FIELD_MAC_TYPE:
1550 info[idx] = (struct field_modify_info){2, 0,
1551 MLX5_MODI_OUT_ETHERTYPE};
1553 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1555 case RTE_FLOW_FIELD_IPV4_DSCP:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IP_DSCP};
1559 mask[idx] = 0x3f >> (6 - width);
1561 case RTE_FLOW_FIELD_IPV4_TTL:
1562 info[idx] = (struct field_modify_info){1, 0,
1563 MLX5_MODI_OUT_IPV4_TTL};
1565 mask[idx] = 0xff >> (8 - width);
1567 case RTE_FLOW_FIELD_IPV4_SRC:
1568 info[idx] = (struct field_modify_info){4, 0,
1569 MLX5_MODI_OUT_SIPV4};
1571 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574 case RTE_FLOW_FIELD_IPV4_DST:
1575 info[idx] = (struct field_modify_info){4, 0,
1576 MLX5_MODI_OUT_DIPV4};
1578 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1581 case RTE_FLOW_FIELD_IPV6_DSCP:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IP_DSCP};
1585 mask[idx] = 0x3f >> (6 - width);
1587 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1588 info[idx] = (struct field_modify_info){1, 0,
1589 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1591 mask[idx] = 0xff >> (8 - width);
1593 case RTE_FLOW_FIELD_IPV6_SRC:
1595 if (data->offset < 32) {
1596 info[idx] = (struct field_modify_info){4, 12,
1597 MLX5_MODI_OUT_SIPV6_31_0};
1600 rte_cpu_to_be_32(0xffffffff >>
1604 mask[3] = RTE_BE32(0xffffffff);
1611 if (data->offset < 64) {
1612 info[idx] = (struct field_modify_info){4, 8,
1613 MLX5_MODI_OUT_SIPV6_63_32};
1616 rte_cpu_to_be_32(0xffffffff >>
1620 mask[2] = RTE_BE32(0xffffffff);
1627 if (data->offset < 96) {
1628 info[idx] = (struct field_modify_info){4, 4,
1629 MLX5_MODI_OUT_SIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[1] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1645 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1647 if (data->offset < 32)
1648 info[idx++] = (struct field_modify_info){4, 0,
1649 MLX5_MODI_OUT_SIPV6_31_0};
1650 if (data->offset < 64)
1651 info[idx++] = (struct field_modify_info){4, 0,
1652 MLX5_MODI_OUT_SIPV6_63_32};
1653 if (data->offset < 96)
1654 info[idx++] = (struct field_modify_info){4, 0,
1655 MLX5_MODI_OUT_SIPV6_95_64};
1656 if (data->offset < 128)
1657 info[idx++] = (struct field_modify_info){4, 0,
1658 MLX5_MODI_OUT_SIPV6_127_96};
1661 case RTE_FLOW_FIELD_IPV6_DST:
1663 if (data->offset < 32) {
1664 info[idx] = (struct field_modify_info){4, 12,
1665 MLX5_MODI_OUT_DIPV6_31_0};
1668 rte_cpu_to_be_32(0xffffffff >>
1672 mask[3] = RTE_BE32(0xffffffff);
1679 if (data->offset < 64) {
1680 info[idx] = (struct field_modify_info){4, 8,
1681 MLX5_MODI_OUT_DIPV6_63_32};
1684 rte_cpu_to_be_32(0xffffffff >>
1688 mask[2] = RTE_BE32(0xffffffff);
1695 if (data->offset < 96) {
1696 info[idx] = (struct field_modify_info){4, 4,
1697 MLX5_MODI_OUT_DIPV6_95_64};
1700 rte_cpu_to_be_32(0xffffffff >>
1704 mask[1] = RTE_BE32(0xffffffff);
1711 info[idx] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1713 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1715 if (data->offset < 32)
1716 info[idx++] = (struct field_modify_info){4, 0,
1717 MLX5_MODI_OUT_DIPV6_31_0};
1718 if (data->offset < 64)
1719 info[idx++] = (struct field_modify_info){4, 0,
1720 MLX5_MODI_OUT_DIPV6_63_32};
1721 if (data->offset < 96)
1722 info[idx++] = (struct field_modify_info){4, 0,
1723 MLX5_MODI_OUT_DIPV6_95_64};
1724 if (data->offset < 128)
1725 info[idx++] = (struct field_modify_info){4, 0,
1726 MLX5_MODI_OUT_DIPV6_127_96};
1729 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_SPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_PORT_DST:
1736 info[idx] = (struct field_modify_info){2, 0,
1737 MLX5_MODI_OUT_TCP_DPORT};
1739 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1741 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1742 info[idx] = (struct field_modify_info){4, 0,
1743 MLX5_MODI_OUT_TCP_SEQ_NUM};
1745 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1748 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1749 info[idx] = (struct field_modify_info){4, 0,
1750 MLX5_MODI_OUT_TCP_ACK_NUM};
1752 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1755 case RTE_FLOW_FIELD_TCP_FLAGS:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_TCP_FLAGS};
1759 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_SPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_UDP_PORT_DST:
1768 info[idx] = (struct field_modify_info){2, 0,
1769 MLX5_MODI_OUT_UDP_DPORT};
1771 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1773 case RTE_FLOW_FIELD_VXLAN_VNI:
1774 /* not supported yet */
1776 case RTE_FLOW_FIELD_GENEVE_VNI:
1777 /* not supported yet*/
1779 case RTE_FLOW_FIELD_GTP_TEID:
1780 info[idx] = (struct field_modify_info){4, 0,
1781 MLX5_MODI_GTP_TEID};
1783 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1786 case RTE_FLOW_FIELD_TAG:
1788 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1789 data->level, error);
1792 MLX5_ASSERT(reg != REG_NON);
1793 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1794 info[idx] = (struct field_modify_info){4, 0,
1798 rte_cpu_to_be_32(0xffffffff >>
1802 case RTE_FLOW_FIELD_MARK:
1804 uint32_t mark_mask = priv->sh->dv_mark_mask;
1805 uint32_t mark_count = __builtin_popcount(mark_mask);
1806 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1810 MLX5_ASSERT(reg != REG_NON);
1811 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1812 info[idx] = (struct field_modify_info){4, 0,
1815 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1816 (mark_count - width)) & mark_mask);
1819 case RTE_FLOW_FIELD_META:
1821 uint32_t meta_mask = priv->sh->dv_meta_mask;
1822 uint32_t meta_count = __builtin_popcount(meta_mask);
1824 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1825 uint32_t shl_c0 = rte_bsf32(msk_c0);
1826 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1829 MLX5_ASSERT(reg != REG_NON);
1830 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1833 info[idx] = (struct field_modify_info){4, 0,
1836 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1837 (meta_count - width)) & meta_mask);
1840 case RTE_FLOW_FIELD_POINTER:
1841 case RTE_FLOW_FIELD_VALUE:
1849 * Convert modify_field action to DV specification.
1852 * Pointer to the rte_eth_dev structure.
1853 * @param[in,out] resource
1854 * Pointer to the modify-header resource.
1856 * Pointer to action specification.
1858 * Attributes of flow that includes this item.
1860 * Pointer to the error structure.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 flow_dv_convert_action_modify_field
1867 (struct rte_eth_dev *dev,
1868 struct mlx5_flow_dv_modify_hdr_resource *resource,
1869 const struct rte_flow_action *action,
1870 const struct rte_flow_attr *attr,
1871 struct rte_flow_error *error)
1873 const struct rte_flow_action_modify_field *conf =
1874 (const struct rte_flow_action_modify_field *)(action->conf);
1875 struct rte_flow_item item = {
1879 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1881 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1883 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1887 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1888 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1889 type = MLX5_MODIFICATION_TYPE_SET;
1890 /** For SET fill the destination field (field) first. */
1891 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1892 conf->width, &shift, dev,
1894 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1895 (void *)(uintptr_t)conf->src.pvalue :
1896 (void *)(uintptr_t)&conf->src.value;
1898 type = MLX5_MODIFICATION_TYPE_COPY;
1899 /** For COPY fill the destination field (dcopy) without mask. */
1900 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1901 conf->width, &shift, dev,
1903 /** Then construct the source field (field) with mask. */
1904 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1905 conf->width, &shift,
1909 return flow_dv_convert_modify_action(&item,
1910 field, dcopy, resource, type, error);
1914 * Validate MARK item.
1917 * Pointer to the rte_eth_dev structure.
1919 * Item specification.
1921 * Attributes of flow that includes this item.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1930 const struct rte_flow_item *item,
1931 const struct rte_flow_attr *attr __rte_unused,
1932 struct rte_flow_error *error)
1934 struct mlx5_priv *priv = dev->data->dev_private;
1935 struct mlx5_dev_config *config = &priv->config;
1936 const struct rte_flow_item_mark *spec = item->spec;
1937 const struct rte_flow_item_mark *mask = item->mask;
1938 const struct rte_flow_item_mark nic_mask = {
1939 .id = priv->sh->dv_mark_mask,
1943 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1944 return rte_flow_error_set(error, ENOTSUP,
1945 RTE_FLOW_ERROR_TYPE_ITEM, item,
1946 "extended metadata feature"
1948 if (!mlx5_flow_ext_mreg_supported(dev))
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ITEM, item,
1951 "extended metadata register"
1952 " isn't supported");
1954 return rte_flow_error_set(error, ENOTSUP,
1955 RTE_FLOW_ERROR_TYPE_ITEM, item,
1956 "extended metadata register"
1957 " isn't available");
1958 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965 "data cannot be empty");
1966 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1970 "mark id exceeds the limit");
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1976 "mask cannot be zero");
1978 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1979 (const uint8_t *)&nic_mask,
1980 sizeof(struct rte_flow_item_mark),
1981 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1988 * Validate META item.
1991 * Pointer to the rte_eth_dev structure.
1993 * Item specification.
1995 * Attributes of flow that includes this item.
1997 * Pointer to error structure.
2000 * 0 on success, a negative errno value otherwise and rte_errno is set.
2003 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2004 const struct rte_flow_item *item,
2005 const struct rte_flow_attr *attr,
2006 struct rte_flow_error *error)
2008 struct mlx5_priv *priv = dev->data->dev_private;
2009 struct mlx5_dev_config *config = &priv->config;
2010 const struct rte_flow_item_meta *spec = item->spec;
2011 const struct rte_flow_item_meta *mask = item->mask;
2012 struct rte_flow_item_meta nic_mask = {
2019 return rte_flow_error_set(error, EINVAL,
2020 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2022 "data cannot be empty");
2023 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2024 if (!mlx5_flow_ext_mreg_supported(dev))
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 "extended metadata register"
2028 " isn't supported");
2029 reg = flow_dv_get_metadata_reg(dev, attr, error);
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "unavailable extended metadata register");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 nic_mask.data = priv->sh->dv_meta_mask;
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "extended metadata feature "
2048 "should be enabled when "
2049 "meta item is requested "
2050 "with e-switch mode ");
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM, item,
2054 "match on metadata for ingress "
2055 "is not supported in legacy "
2059 mask = &rte_flow_item_meta_mask;
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2063 "mask cannot be zero");
2065 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2066 (const uint8_t *)&nic_mask,
2067 sizeof(struct rte_flow_item_meta),
2068 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2073 * Validate TAG item.
2076 * Pointer to the rte_eth_dev structure.
2078 * Item specification.
2080 * Attributes of flow that includes this item.
2082 * Pointer to error structure.
2085 * 0 on success, a negative errno value otherwise and rte_errno is set.
2088 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2089 const struct rte_flow_item *item,
2090 const struct rte_flow_attr *attr __rte_unused,
2091 struct rte_flow_error *error)
2093 const struct rte_flow_item_tag *spec = item->spec;
2094 const struct rte_flow_item_tag *mask = item->mask;
2095 const struct rte_flow_item_tag nic_mask = {
2096 .data = RTE_BE32(UINT32_MAX),
2101 if (!mlx5_flow_ext_mreg_supported(dev))
2102 return rte_flow_error_set(error, ENOTSUP,
2103 RTE_FLOW_ERROR_TYPE_ITEM, item,
2104 "extensive metadata register"
2105 " isn't supported");
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2110 "data cannot be empty");
2112 mask = &rte_flow_item_tag_mask;
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2116 "mask cannot be zero");
2118 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2119 (const uint8_t *)&nic_mask,
2120 sizeof(struct rte_flow_item_tag),
2121 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2124 if (mask->index != 0xff)
2125 return rte_flow_error_set(error, EINVAL,
2126 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2127 "partial mask for tag index"
2128 " is not supported");
2129 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2132 MLX5_ASSERT(ret != REG_NON);
2137 * Validate vport item.
2140 * Pointer to the rte_eth_dev structure.
2142 * Item specification.
2144 * Attributes of flow that includes this item.
2145 * @param[in] item_flags
2146 * Bit-fields that holds the items detected until now.
2148 * Pointer to error structure.
2151 * 0 on success, a negative errno value otherwise and rte_errno is set.
2154 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2155 const struct rte_flow_item *item,
2156 const struct rte_flow_attr *attr,
2157 uint64_t item_flags,
2158 struct rte_flow_error *error)
2160 const struct rte_flow_item_port_id *spec = item->spec;
2161 const struct rte_flow_item_port_id *mask = item->mask;
2162 const struct rte_flow_item_port_id switch_mask = {
2165 struct mlx5_priv *esw_priv;
2166 struct mlx5_priv *dev_priv;
2169 if (!attr->transfer)
2170 return rte_flow_error_set(error, EINVAL,
2171 RTE_FLOW_ERROR_TYPE_ITEM,
2173 "match on port id is valid only"
2174 " when transfer flag is enabled");
2175 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM, item,
2178 "multiple source ports are not"
2181 mask = &switch_mask;
2182 if (mask->id != 0xffffffff)
2183 return rte_flow_error_set(error, ENOTSUP,
2184 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2186 "no support for partial mask on"
2188 ret = mlx5_flow_item_acceptable
2189 (item, (const uint8_t *)mask,
2190 (const uint8_t *)&rte_flow_item_port_id_mask,
2191 sizeof(struct rte_flow_item_port_id),
2192 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2197 if (spec->id == MLX5_PORT_ESW_MGR)
2199 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2201 return rte_flow_error_set(error, rte_errno,
2202 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2203 "failed to obtain E-Switch info for"
2205 dev_priv = mlx5_dev_to_eswitch_info(dev);
2207 return rte_flow_error_set(error, rte_errno,
2208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2210 "failed to obtain E-Switch info");
2211 if (esw_priv->domain_id != dev_priv->domain_id)
2212 return rte_flow_error_set(error, EINVAL,
2213 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2214 "cannot match on a port from a"
2215 " different E-Switch");
2220 * Validate VLAN item.
2223 * Item specification.
2224 * @param[in] item_flags
2225 * Bit-fields that holds the items detected until now.
2227 * Ethernet device flow is being created on.
2229 * Pointer to error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2236 uint64_t item_flags,
2237 struct rte_eth_dev *dev,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_item_vlan *mask = item->mask;
2241 const struct rte_flow_item_vlan nic_mask = {
2242 .tci = RTE_BE16(UINT16_MAX),
2243 .inner_type = RTE_BE16(UINT16_MAX),
2246 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2248 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2249 MLX5_FLOW_LAYER_INNER_L4) :
2250 (MLX5_FLOW_LAYER_OUTER_L3 |
2251 MLX5_FLOW_LAYER_OUTER_L4);
2252 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2253 MLX5_FLOW_LAYER_OUTER_VLAN;
2255 if (item_flags & vlanm)
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ITEM, item,
2258 "multiple VLAN layers not supported");
2259 else if ((item_flags & l34m) != 0)
2260 return rte_flow_error_set(error, EINVAL,
2261 RTE_FLOW_ERROR_TYPE_ITEM, item,
2262 "VLAN cannot follow L3/L4 layer");
2264 mask = &rte_flow_item_vlan_mask;
2265 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2266 (const uint8_t *)&nic_mask,
2267 sizeof(struct rte_flow_item_vlan),
2268 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2271 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2272 struct mlx5_priv *priv = dev->data->dev_private;
2274 if (priv->vmwa_context) {
2276 * Non-NULL context means we have a virtual machine
2277 * and SR-IOV enabled, we have to create VLAN interface
2278 * to make hypervisor to setup E-Switch vport
2279 * context correctly. We avoid creating the multiple
2280 * VLAN interfaces, so we cannot support VLAN tag mask.
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ITEM,
2285 "VLAN tag mask is not"
2286 " supported in virtual"
2294 * GTP flags are contained in 1 byte of the format:
2295 * -------------------------------------------
2296 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2297 * |-----------------------------------------|
2298 * | value | Version | PT | Res | E | S | PN |
2299 * -------------------------------------------
2301 * Matching is supported only for GTP flags E, S, PN.
2303 #define MLX5_GTP_FLAGS_MASK 0x07
2306 * Validate GTP item.
2309 * Pointer to the rte_eth_dev structure.
2311 * Item specification.
2312 * @param[in] item_flags
2313 * Bit-fields that holds the items detected until now.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2322 const struct rte_flow_item *item,
2323 uint64_t item_flags,
2324 struct rte_flow_error *error)
2326 struct mlx5_priv *priv = dev->data->dev_private;
2327 const struct rte_flow_item_gtp *spec = item->spec;
2328 const struct rte_flow_item_gtp *mask = item->mask;
2329 const struct rte_flow_item_gtp nic_mask = {
2330 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2332 .teid = RTE_BE32(0xffffffff),
2335 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "GTP support is not enabled");
2339 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2340 return rte_flow_error_set(error, ENOTSUP,
2341 RTE_FLOW_ERROR_TYPE_ITEM, item,
2342 "multiple tunnel layers not"
2344 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2345 return rte_flow_error_set(error, EINVAL,
2346 RTE_FLOW_ERROR_TYPE_ITEM, item,
2347 "no outer UDP layer found");
2349 mask = &rte_flow_item_gtp_mask;
2350 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ITEM, item,
2353 "Match is supported for GTP"
2355 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2356 (const uint8_t *)&nic_mask,
2357 sizeof(struct rte_flow_item_gtp),
2358 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2362 * Validate GTP PSC item.
2365 * Item specification.
2366 * @param[in] last_item
2367 * Previous validated item in the pattern items.
2368 * @param[in] gtp_item
2369 * Previous GTP item specification.
2371 * Pointer to flow attributes.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2381 const struct rte_flow_item *gtp_item,
2382 const struct rte_flow_attr *attr,
2383 struct rte_flow_error *error)
2385 const struct rte_flow_item_gtp *gtp_spec;
2386 const struct rte_flow_item_gtp *gtp_mask;
2387 const struct rte_flow_item_gtp_psc *mask;
2388 const struct rte_flow_item_gtp_psc nic_mask = {
2393 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2394 return rte_flow_error_set
2395 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2396 "GTP PSC item must be preceded with GTP item");
2397 gtp_spec = gtp_item->spec;
2398 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2399 /* GTP spec and E flag is requested to match zero. */
2401 (gtp_mask->v_pt_rsv_flags &
2402 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2403 return rte_flow_error_set
2404 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2405 "GTP E flag must be 1 to match GTP PSC");
2406 /* Check the flow is not created in group zero. */
2407 if (!attr->transfer && !attr->group)
2408 return rte_flow_error_set
2409 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2410 "GTP PSC is not supported for group 0");
2411 /* GTP spec is here and E flag is requested to match zero. */
2414 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2415 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2416 (const uint8_t *)&nic_mask,
2417 sizeof(struct rte_flow_item_gtp_psc),
2418 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2422 * Validate IPV4 item.
2423 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2424 * add specific validation of fragment_offset field,
2427 * Item specification.
2428 * @param[in] item_flags
2429 * Bit-fields that holds the items detected until now.
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2438 const struct rte_flow_item *item,
2439 uint64_t item_flags, uint64_t last_item,
2440 uint16_t ether_type, struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 const struct rte_flow_item_ipv4 *spec = item->spec;
2445 const struct rte_flow_item_ipv4 *last = item->last;
2446 const struct rte_flow_item_ipv4 *mask = item->mask;
2447 rte_be16_t fragment_offset_spec = 0;
2448 rte_be16_t fragment_offset_last = 0;
2449 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2451 .src_addr = RTE_BE32(0xffffffff),
2452 .dst_addr = RTE_BE32(0xffffffff),
2453 .type_of_service = 0xff,
2454 .fragment_offset = RTE_BE16(0xffff),
2455 .next_proto_id = 0xff,
2456 .time_to_live = 0xff,
2460 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2461 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2462 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2463 priv->config.hca_attr.inner_ipv4_ihl;
2465 return rte_flow_error_set(error, ENOTSUP,
2466 RTE_FLOW_ERROR_TYPE_ITEM,
2468 "IPV4 ihl offload not supported");
2469 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2471 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2472 ether_type, &nic_ipv4_mask,
2473 MLX5_ITEM_RANGE_ACCEPTED, error);
2477 fragment_offset_spec = spec->hdr.fragment_offset &
2478 mask->hdr.fragment_offset;
2479 if (!fragment_offset_spec)
2482 * spec and mask are valid, enforce using full mask to make sure the
2483 * complete value is used correctly.
2485 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2486 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2487 return rte_flow_error_set(error, EINVAL,
2488 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2489 item, "must use full mask for"
2490 " fragment_offset");
2492 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2493 * indicating this is 1st fragment of fragmented packet.
2494 * This is not yet supported in MLX5, return appropriate error message.
2496 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2497 return rte_flow_error_set(error, ENOTSUP,
2498 RTE_FLOW_ERROR_TYPE_ITEM, item,
2499 "match on first fragment not "
2501 if (fragment_offset_spec && !last)
2502 return rte_flow_error_set(error, ENOTSUP,
2503 RTE_FLOW_ERROR_TYPE_ITEM, item,
2504 "specified value not supported");
2505 /* spec and last are valid, validate the specified range. */
2506 fragment_offset_last = last->hdr.fragment_offset &
2507 mask->hdr.fragment_offset;
2509 * Match on fragment_offset spec 0x2001 and last 0x3fff
2510 * means MF is 1 and frag-offset is > 0.
2511 * This packet is fragment 2nd and onward, excluding last.
2512 * This is not yet supported in MLX5, return appropriate
2515 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2516 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519 last, "match on following "
2520 "fragments not supported");
2522 * Match on fragment_offset spec 0x0001 and last 0x1fff
2523 * means MF is 0 and frag-offset is > 0.
2524 * This packet is last fragment of fragmented packet.
2525 * This is not yet supported in MLX5, return appropriate
2528 if (fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532 last, "match on last "
2533 "fragment not supported");
2535 * Match on fragment_offset spec 0x0001 and last 0x3fff
2536 * means MF and/or frag-offset is not 0.
2537 * This is a fragmented packet.
2538 * Other range values are invalid and rejected.
2540 if (!(fragment_offset_spec == RTE_BE16(1) &&
2541 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2542 return rte_flow_error_set(error, ENOTSUP,
2543 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2544 "specified range not supported");
2549 * Validate IPV6 fragment extension item.
2552 * Item specification.
2553 * @param[in] item_flags
2554 * Bit-fields that holds the items detected until now.
2556 * Pointer to error structure.
2559 * 0 on success, a negative errno value otherwise and rte_errno is set.
2562 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2563 uint64_t item_flags,
2564 struct rte_flow_error *error)
2566 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2567 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2568 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2569 rte_be16_t frag_data_spec = 0;
2570 rte_be16_t frag_data_last = 0;
2571 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2572 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2573 MLX5_FLOW_LAYER_OUTER_L4;
2575 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2577 .next_header = 0xff,
2578 .frag_data = RTE_BE16(0xffff),
2582 if (item_flags & l4m)
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item cannot "
2587 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2588 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM, item,
2591 "ipv6 fragment extension item must "
2592 "follow ipv6 item");
2594 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2595 if (!frag_data_spec)
2598 * spec and mask are valid, enforce using full mask to make sure the
2599 * complete value is used correctly.
2601 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2602 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2605 item, "must use full mask for"
2608 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2609 * This is 1st fragment of fragmented packet.
2611 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2612 return rte_flow_error_set(error, ENOTSUP,
2613 RTE_FLOW_ERROR_TYPE_ITEM, item,
2614 "match on first fragment not "
2616 if (frag_data_spec && !last)
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ITEM, item,
2619 "specified value not supported");
2620 ret = mlx5_flow_item_acceptable
2621 (item, (const uint8_t *)mask,
2622 (const uint8_t *)&nic_mask,
2623 sizeof(struct rte_flow_item_ipv6_frag_ext),
2624 MLX5_ITEM_RANGE_ACCEPTED, error);
2627 /* spec and last are valid, validate the specified range. */
2628 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2630 * Match on frag_data spec 0x0009 and last 0xfff9
2631 * means M is 1 and frag-offset is > 0.
2632 * This packet is fragment 2nd and onward, excluding last.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2637 RTE_IPV6_EHDR_MF_MASK) &&
2638 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2639 return rte_flow_error_set(error, ENOTSUP,
2640 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2641 last, "match on following "
2642 "fragments not supported");
2644 * Match on frag_data spec 0x0008 and last 0xfff8
2645 * means M is 0 and frag-offset is > 0.
2646 * This packet is last fragment of fragmented packet.
2647 * This is not yet supported in MLX5, return appropriate
2650 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2651 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2652 return rte_flow_error_set(error, ENOTSUP,
2653 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2654 last, "match on last "
2655 "fragment not supported");
2656 /* Other range values are invalid and rejected. */
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2659 "specified range not supported");
2663 * Validate ASO CT item.
2666 * Pointer to the rte_eth_dev structure.
2668 * Item specification.
2669 * @param[in] item_flags
2670 * Pointer to bit-fields that holds the items detected until now.
2672 * Pointer to error structure.
2675 * 0 on success, a negative errno value otherwise and rte_errno is set.
2678 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2679 const struct rte_flow_item *item,
2680 uint64_t *item_flags,
2681 struct rte_flow_error *error)
2683 const struct rte_flow_item_conntrack *spec = item->spec;
2684 const struct rte_flow_item_conntrack *mask = item->mask;
2688 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2691 "Only one CT is supported");
2693 mask = &rte_flow_item_conntrack_mask;
2694 flags = spec->flags & mask->flags;
2695 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2696 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2697 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2698 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2701 "Conflict status bits");
2702 /* State change also needs to be considered. */
2703 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2708 * Validate the pop VLAN action.
2711 * Pointer to the rte_eth_dev structure.
2712 * @param[in] action_flags
2713 * Holds the actions detected until now.
2715 * Pointer to the pop vlan action.
2716 * @param[in] item_flags
2717 * The items found in this flow rule.
2719 * Pointer to flow attributes.
2721 * Pointer to error structure.
2724 * 0 on success, a negative errno value otherwise and rte_errno is set.
2727 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2728 uint64_t action_flags,
2729 const struct rte_flow_action *action,
2730 uint64_t item_flags,
2731 const struct rte_flow_attr *attr,
2732 struct rte_flow_error *error)
2734 const struct mlx5_priv *priv = dev->data->dev_private;
2735 struct mlx5_dev_ctx_shared *sh = priv->sh;
2736 bool direction_error = false;
2738 if (!priv->sh->pop_vlan_action)
2739 return rte_flow_error_set(error, ENOTSUP,
2740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2742 "pop vlan action is not supported");
2743 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2744 if (attr->transfer) {
2745 bool fdb_tx = priv->representor_id != UINT16_MAX;
2746 bool is_cx5 = sh->steering_format_version ==
2747 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2749 if (fdb_tx && is_cx5)
2750 direction_error = true;
2751 } else if (attr->egress) {
2752 direction_error = true;
2754 if (direction_error)
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2758 "pop vlan action not supported for egress");
2759 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2760 return rte_flow_error_set(error, ENOTSUP,
2761 RTE_FLOW_ERROR_TYPE_ACTION, action,
2762 "no support for multiple VLAN "
2764 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2765 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2766 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2767 return rte_flow_error_set(error, ENOTSUP,
2768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2770 "cannot pop vlan after decap without "
2771 "match on inner vlan in the flow");
2772 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2773 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2774 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2775 return rte_flow_error_set(error, ENOTSUP,
2776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2778 "cannot pop vlan without a "
2779 "match on (outer) vlan in the flow");
2780 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION, action,
2783 "wrong action order, port_id should "
2784 "be after pop VLAN action");
2785 if (!attr->transfer && priv->representor)
2786 return rte_flow_error_set(error, ENOTSUP,
2787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2788 "pop vlan action for VF representor "
2789 "not supported on NIC table");
2794 * Get VLAN default info from vlan match info.
2797 * the list of item specifications.
2799 * pointer VLAN info to fill to.
2802 * 0 on success, a negative errno value otherwise and rte_errno is set.
2805 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2806 struct rte_vlan_hdr *vlan)
2808 const struct rte_flow_item_vlan nic_mask = {
2809 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2810 MLX5DV_FLOW_VLAN_VID_MASK),
2811 .inner_type = RTE_BE16(0xffff),
2816 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2817 int type = items->type;
2819 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2820 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2823 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2824 const struct rte_flow_item_vlan *vlan_m = items->mask;
2825 const struct rte_flow_item_vlan *vlan_v = items->spec;
2827 /* If VLAN item in pattern doesn't contain data, return here. */
2832 /* Only full match values are accepted */
2833 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2834 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2835 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2837 rte_be_to_cpu_16(vlan_v->tci &
2838 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2840 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2841 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2842 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2844 rte_be_to_cpu_16(vlan_v->tci &
2845 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2847 if (vlan_m->inner_type == nic_mask.inner_type)
2848 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2849 vlan_m->inner_type);
2854 * Validate the push VLAN action.
2857 * Pointer to the rte_eth_dev structure.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] item_flags
2861 * The items found in this flow rule.
2863 * Pointer to the action structure.
2865 * Pointer to flow attributes
2867 * Pointer to error structure.
2870 * 0 on success, a negative errno value otherwise and rte_errno is set.
2873 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2874 uint64_t action_flags,
2875 const struct rte_flow_item_vlan *vlan_m,
2876 const struct rte_flow_action *action,
2877 const struct rte_flow_attr *attr,
2878 struct rte_flow_error *error)
2880 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2881 const struct mlx5_priv *priv = dev->data->dev_private;
2882 struct mlx5_dev_ctx_shared *sh = priv->sh;
2883 bool direction_error = false;
2885 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2886 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, action,
2889 "invalid vlan ethertype");
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after push VLAN");
2895 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2896 if (attr->transfer) {
2897 bool fdb_tx = priv->representor_id != UINT16_MAX;
2898 bool is_cx5 = sh->steering_format_version ==
2899 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2901 if (!fdb_tx && is_cx5)
2902 direction_error = true;
2903 } else if (attr->ingress) {
2904 direction_error = true;
2906 if (direction_error)
2907 return rte_flow_error_set(error, ENOTSUP,
2908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2910 "push vlan action not supported for ingress");
2911 if (!attr->transfer && priv->representor)
2912 return rte_flow_error_set(error, ENOTSUP,
2913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914 "push vlan action for VF representor "
2915 "not supported on NIC table");
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2919 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2920 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2921 !(mlx5_flow_find_action
2922 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2923 return rte_flow_error_set(error, EINVAL,
2924 RTE_FLOW_ERROR_TYPE_ACTION, action,
2925 "not full match mask on VLAN PCP and "
2926 "there is no of_set_vlan_pcp action, "
2927 "push VLAN action cannot figure out "
2930 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2931 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2932 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2933 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2934 !(mlx5_flow_find_action
2935 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2936 return rte_flow_error_set(error, EINVAL,
2937 RTE_FLOW_ERROR_TYPE_ACTION, action,
2938 "not full match mask on VLAN VID and "
2939 "there is no of_set_vlan_vid action, "
2940 "push VLAN action cannot figure out "
2947 * Validate the set VLAN PCP.
2949 * @param[in] action_flags
2950 * Holds the actions detected until now.
2951 * @param[in] actions
2952 * Pointer to the list of actions remaining in the flow rule.
2954 * Pointer to error structure.
2957 * 0 on success, a negative errno value otherwise and rte_errno is set.
2960 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2961 const struct rte_flow_action actions[],
2962 struct rte_flow_error *error)
2964 const struct rte_flow_action *action = actions;
2965 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2967 if (conf->vlan_pcp > 7)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "VLAN PCP value is too big");
2971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2972 return rte_flow_error_set(error, ENOTSUP,
2973 RTE_FLOW_ERROR_TYPE_ACTION, action,
2974 "set VLAN PCP action must follow "
2975 "the push VLAN action");
2976 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2977 return rte_flow_error_set(error, ENOTSUP,
2978 RTE_FLOW_ERROR_TYPE_ACTION, action,
2979 "Multiple VLAN PCP modification are "
2981 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2982 return rte_flow_error_set(error, EINVAL,
2983 RTE_FLOW_ERROR_TYPE_ACTION, action,
2984 "wrong action order, port_id should "
2985 "be after set VLAN PCP");
2990 * Validate the set VLAN VID.
2992 * @param[in] item_flags
2993 * Holds the items detected in this rule.
2994 * @param[in] action_flags
2995 * Holds the actions detected until now.
2996 * @param[in] actions
2997 * Pointer to the list of actions remaining in the flow rule.
2999 * Pointer to error structure.
3002 * 0 on success, a negative errno value otherwise and rte_errno is set.
3005 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3006 uint64_t action_flags,
3007 const struct rte_flow_action actions[],
3008 struct rte_flow_error *error)
3010 const struct rte_flow_action *action = actions;
3011 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3013 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION, action,
3016 "VLAN VID value is too big");
3017 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3018 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3019 return rte_flow_error_set(error, ENOTSUP,
3020 RTE_FLOW_ERROR_TYPE_ACTION, action,
3021 "set VLAN VID action must follow push"
3022 " VLAN action or match on VLAN item");
3023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3024 return rte_flow_error_set(error, ENOTSUP,
3025 RTE_FLOW_ERROR_TYPE_ACTION, action,
3026 "Multiple VLAN VID modifications are "
3028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3029 return rte_flow_error_set(error, EINVAL,
3030 RTE_FLOW_ERROR_TYPE_ACTION, action,
3031 "wrong action order, port_id should "
3032 "be after set VLAN VID");
3037 * Validate the FLAG action.
3040 * Pointer to the rte_eth_dev structure.
3041 * @param[in] action_flags
3042 * Holds the actions detected until now.
3044 * Pointer to flow attributes
3046 * Pointer to error structure.
3049 * 0 on success, a negative errno value otherwise and rte_errno is set.
3052 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3053 uint64_t action_flags,
3054 const struct rte_flow_attr *attr,
3055 struct rte_flow_error *error)
3057 struct mlx5_priv *priv = dev->data->dev_private;
3058 struct mlx5_dev_config *config = &priv->config;
3061 /* Fall back if no extended metadata register support. */
3062 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3063 return mlx5_flow_validate_action_flag(action_flags, attr,
3065 /* Extensive metadata mode requires registers. */
3066 if (!mlx5_flow_ext_mreg_supported(dev))
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "no metadata registers "
3070 "to support flag action");
3071 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3072 return rte_flow_error_set(error, ENOTSUP,
3073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 "extended metadata register"
3075 " isn't available");
3076 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3079 MLX5_ASSERT(ret > 0);
3080 if (action_flags & MLX5_FLOW_ACTION_MARK)
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3083 "can't mark and flag in same flow");
3084 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3088 " actions in same flow");
3093 * Validate MARK action.
3096 * Pointer to the rte_eth_dev structure.
3098 * Pointer to action.
3099 * @param[in] action_flags
3100 * Holds the actions detected until now.
3102 * Pointer to flow attributes
3104 * Pointer to error structure.
3107 * 0 on success, a negative errno value otherwise and rte_errno is set.
3110 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3111 const struct rte_flow_action *action,
3112 uint64_t action_flags,
3113 const struct rte_flow_attr *attr,
3114 struct rte_flow_error *error)
3116 struct mlx5_priv *priv = dev->data->dev_private;
3117 struct mlx5_dev_config *config = &priv->config;
3118 const struct rte_flow_action_mark *mark = action->conf;
3121 if (is_tunnel_offload_active(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "if tunnel offload active");
3126 /* Fall back if no extended metadata register support. */
3127 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3128 return mlx5_flow_validate_action_mark(action, action_flags,
3130 /* Extensive metadata mode requires registers. */
3131 if (!mlx5_flow_ext_mreg_supported(dev))
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3134 "no metadata registers "
3135 "to support mark action");
3136 if (!priv->sh->dv_mark_mask)
3137 return rte_flow_error_set(error, ENOTSUP,
3138 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3139 "extended metadata register"
3140 " isn't available");
3141 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3144 MLX5_ASSERT(ret > 0);
3146 return rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION, action,
3148 "configuration cannot be null");
3149 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3150 return rte_flow_error_set(error, EINVAL,
3151 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3153 "mark id exceeds the limit");
3154 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "can't flag and mark in same flow");
3158 if (action_flags & MLX5_FLOW_ACTION_MARK)
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3161 "can't have 2 mark actions in same"
3167 * Validate SET_META action.
3170 * Pointer to the rte_eth_dev structure.
3172 * Pointer to the action structure.
3173 * @param[in] action_flags
3174 * Holds the actions detected until now.
3176 * Pointer to flow attributes
3178 * Pointer to error structure.
3181 * 0 on success, a negative errno value otherwise and rte_errno is set.
3184 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3185 const struct rte_flow_action *action,
3186 uint64_t action_flags __rte_unused,
3187 const struct rte_flow_attr *attr,
3188 struct rte_flow_error *error)
3190 struct mlx5_priv *priv = dev->data->dev_private;
3191 struct mlx5_dev_config *config = &priv->config;
3192 const struct rte_flow_action_set_meta *conf;
3193 uint32_t nic_mask = UINT32_MAX;
3196 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3197 !mlx5_flow_ext_mreg_supported(dev))
3198 return rte_flow_error_set(error, ENOTSUP,
3199 RTE_FLOW_ERROR_TYPE_ACTION, action,
3200 "extended metadata register"
3201 " isn't supported");
3202 reg = flow_dv_get_metadata_reg(dev, attr, error);
3206 return rte_flow_error_set(error, ENOTSUP,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "unavailable extended metadata register");
3209 if (reg != REG_A && reg != REG_B) {
3210 struct mlx5_priv *priv = dev->data->dev_private;
3212 nic_mask = priv->sh->dv_meta_mask;
3214 if (!(action->conf))
3215 return rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ACTION, action,
3217 "configuration cannot be null");
3218 conf = (const struct rte_flow_action_set_meta *)action->conf;
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION, action,
3222 "zero mask doesn't have any effect");
3223 if (conf->mask & ~nic_mask)
3224 return rte_flow_error_set(error, EINVAL,
3225 RTE_FLOW_ERROR_TYPE_ACTION, action,
3226 "meta data must be within reg C0");
3231 * Validate SET_TAG action.
3234 * Pointer to the rte_eth_dev structure.
3236 * Pointer to the action structure.
3237 * @param[in] action_flags
3238 * Holds the actions detected until now.
3240 * Pointer to flow attributes
3242 * Pointer to error structure.
3245 * 0 on success, a negative errno value otherwise and rte_errno is set.
3248 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3249 const struct rte_flow_action *action,
3250 uint64_t action_flags,
3251 const struct rte_flow_attr *attr,
3252 struct rte_flow_error *error)
3254 const struct rte_flow_action_set_tag *conf;
3255 const uint64_t terminal_action_flags =
3256 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3257 MLX5_FLOW_ACTION_RSS;
3260 if (!mlx5_flow_ext_mreg_supported(dev))
3261 return rte_flow_error_set(error, ENOTSUP,
3262 RTE_FLOW_ERROR_TYPE_ACTION, action,
3263 "extensive metadata register"
3264 " isn't supported");
3265 if (!(action->conf))
3266 return rte_flow_error_set(error, EINVAL,
3267 RTE_FLOW_ERROR_TYPE_ACTION, action,
3268 "configuration cannot be null");
3269 conf = (const struct rte_flow_action_set_tag *)action->conf;
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION, action,
3273 "zero mask doesn't have any effect");
3274 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3277 if (!attr->transfer && attr->ingress &&
3278 (action_flags & terminal_action_flags))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, action,
3281 "set_tag has no effect"
3282 " with terminal actions");
3287 * Validate count action.
3290 * Pointer to rte_eth_dev structure.
3292 * Indicator if action is shared.
3293 * @param[in] action_flags
3294 * Holds the actions detected until now.
3296 * Pointer to error structure.
3299 * 0 on success, a negative errno value otherwise and rte_errno is set.
3302 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3303 uint64_t action_flags,
3304 struct rte_flow_error *error)
3306 struct mlx5_priv *priv = dev->data->dev_private;
3308 if (!priv->sh->devx)
3310 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3313 "duplicate count actions set");
3314 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3315 !priv->sh->flow_hit_aso_en)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3318 "old age and shared count combination is not supported");
3319 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3323 return rte_flow_error_set
3325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3327 "count action not supported");
3331 * Validate the L2 encap action.
3334 * Pointer to the rte_eth_dev structure.
3335 * @param[in] action_flags
3336 * Holds the actions detected until now.
3338 * Pointer to the action structure.
3340 * Pointer to flow attributes.
3342 * Pointer to error structure.
3345 * 0 on success, a negative errno value otherwise and rte_errno is set.
3348 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3349 uint64_t action_flags,
3350 const struct rte_flow_action *action,
3351 const struct rte_flow_attr *attr,
3352 struct rte_flow_error *error)
3354 const struct mlx5_priv *priv = dev->data->dev_private;
3356 if (!(action->conf))
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION, action,
3359 "configuration cannot be null");
3360 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3363 "can only have a single encap action "
3365 if (!attr->transfer && priv->representor)
3366 return rte_flow_error_set(error, ENOTSUP,
3367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368 "encap action for VF representor "
3369 "not supported on NIC table");
3374 * Validate a decap action.
3377 * Pointer to the rte_eth_dev structure.
3378 * @param[in] action_flags
3379 * Holds the actions detected until now.
3381 * Pointer to the action structure.
3382 * @param[in] item_flags
3383 * Holds the items detected.
3385 * Pointer to flow attributes
3387 * Pointer to error structure.
3390 * 0 on success, a negative errno value otherwise and rte_errno is set.
3393 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3394 uint64_t action_flags,
3395 const struct rte_flow_action *action,
3396 const uint64_t item_flags,
3397 const struct rte_flow_attr *attr,
3398 struct rte_flow_error *error)
3400 const struct mlx5_priv *priv = dev->data->dev_private;
3402 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3403 !priv->config.decap_en)
3404 return rte_flow_error_set(error, ENOTSUP,
3405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3406 "decap is not enabled");
3407 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3411 MLX5_FLOW_ACTION_DECAP ? "can only "
3412 "have a single decap action" : "decap "
3413 "after encap is not supported");
3414 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3415 return rte_flow_error_set(error, EINVAL,
3416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3417 "can't have decap action after"
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3423 "decap action not supported for "
3425 if (!attr->transfer && priv->representor)
3426 return rte_flow_error_set(error, ENOTSUP,
3427 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3428 "decap action for VF representor "
3429 "not supported on NIC table");
3430 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3431 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3432 return rte_flow_error_set(error, ENOTSUP,
3433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3434 "VXLAN item should be present for VXLAN decap");
3438 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3441 * Validate the raw encap and decap actions.
3444 * Pointer to the rte_eth_dev structure.
3446 * Pointer to the decap action.
3448 * Pointer to the encap action.
3450 * Pointer to flow attributes
3451 * @param[in/out] action_flags
3452 * Holds the actions detected until now.
3453 * @param[out] actions_n
3454 * pointer to the number of actions counter.
3456 * Pointer to the action structure.
3457 * @param[in] item_flags
3458 * Holds the items detected.
3460 * Pointer to error structure.
3463 * 0 on success, a negative errno value otherwise and rte_errno is set.
3466 flow_dv_validate_action_raw_encap_decap
3467 (struct rte_eth_dev *dev,
3468 const struct rte_flow_action_raw_decap *decap,
3469 const struct rte_flow_action_raw_encap *encap,
3470 const struct rte_flow_attr *attr, uint64_t *action_flags,
3471 int *actions_n, const struct rte_flow_action *action,
3472 uint64_t item_flags, struct rte_flow_error *error)
3474 const struct mlx5_priv *priv = dev->data->dev_private;
3477 if (encap && (!encap->size || !encap->data))
3478 return rte_flow_error_set(error, EINVAL,
3479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3480 "raw encap data cannot be empty");
3481 if (decap && encap) {
3482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3486 else if (encap->size <=
3487 MLX5_ENCAPSULATION_DECISION_SIZE &&
3489 MLX5_ENCAPSULATION_DECISION_SIZE)
3492 else if (encap->size >
3493 MLX5_ENCAPSULATION_DECISION_SIZE &&
3495 MLX5_ENCAPSULATION_DECISION_SIZE)
3496 /* 2 L2 actions: encap and decap. */
3499 return rte_flow_error_set(error,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "unsupported too small "
3503 "raw decap and too small raw "
3504 "encap combination");
3507 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3508 item_flags, attr, error);
3511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3516 return rte_flow_error_set(error, ENOTSUP,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3519 "small raw encap size");
3520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3521 return rte_flow_error_set(error, EINVAL,
3522 RTE_FLOW_ERROR_TYPE_ACTION,
3524 "more than one encap action");
3525 if (!attr->transfer && priv->representor)
3526 return rte_flow_error_set
3528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3529 "encap action for VF representor "
3530 "not supported on NIC table");
3531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3538 * Validate the ASO CT action.
3541 * Pointer to the rte_eth_dev structure.
3542 * @param[in] action_flags
3543 * Holds the actions detected until now.
3544 * @param[in] item_flags
3545 * The items found in this flow rule.
3547 * Pointer to flow attributes.
3549 * Pointer to error structure.
3552 * 0 on success, a negative errno value otherwise and rte_errno is set.
3555 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3556 uint64_t action_flags,
3557 uint64_t item_flags,
3558 const struct rte_flow_attr *attr,
3559 struct rte_flow_error *error)
3563 if (attr->group == 0 && !attr->transfer)
3564 return rte_flow_error_set(error, ENOTSUP,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3567 "Only support non-root table");
3568 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3569 return rte_flow_error_set(error, ENOTSUP,
3570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3571 "CT cannot follow a fate action");
3572 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3573 (action_flags & MLX5_FLOW_ACTION_AGE))
3574 return rte_flow_error_set(error, EINVAL,
3575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3576 "Only one ASO action is supported");
3577 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3578 return rte_flow_error_set(error, EINVAL,
3579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3580 "Encap cannot exist before CT");
3581 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3584 "Not a outer TCP packet");
3589 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3590 struct mlx5_list_entry *entry, void *cb_ctx)
3592 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3593 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3594 struct mlx5_flow_dv_encap_decap_resource *resource;
3596 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3598 if (resource->reformat_type == ctx_resource->reformat_type &&
3599 resource->ft_type == ctx_resource->ft_type &&
3600 resource->flags == ctx_resource->flags &&
3601 resource->size == ctx_resource->size &&
3602 !memcmp((const void *)resource->buf,
3603 (const void *)ctx_resource->buf,
3609 struct mlx5_list_entry *
3610 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3612 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3613 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3614 struct mlx5dv_dr_domain *domain;
3615 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3616 struct mlx5_flow_dv_encap_decap_resource *resource;
3620 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621 domain = sh->fdb_domain;
3622 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3623 domain = sh->rx_domain;
3625 domain = sh->tx_domain;
3626 /* Register new encap/decap resource. */
3627 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3629 rte_flow_error_set(ctx->error, ENOMEM,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3631 "cannot allocate resource memory");
3634 *resource = *ctx_resource;
3635 resource->idx = idx;
3636 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3640 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3641 rte_flow_error_set(ctx->error, ENOMEM,
3642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3643 NULL, "cannot create action");
3647 return &resource->entry;
3650 struct mlx5_list_entry *
3651 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3654 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3655 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3656 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3659 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3661 if (!cache_resource) {
3662 rte_flow_error_set(ctx->error, ENOMEM,
3663 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3664 "cannot allocate resource memory");
3667 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3668 cache_resource->idx = idx;
3669 return &cache_resource->entry;
3673 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3675 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3676 struct mlx5_flow_dv_encap_decap_resource *res =
3677 container_of(entry, typeof(*res), entry);
3679 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3683 * Find existing encap/decap resource or create and register a new one.
3685 * @param[in, out] dev
3686 * Pointer to rte_eth_dev structure.
3687 * @param[in, out] resource
3688 * Pointer to encap/decap resource.
3689 * @parm[in, out] dev_flow
3690 * Pointer to the dev_flow.
3692 * pointer to error structure.
3695 * 0 on success otherwise -errno and errno is set.
3698 flow_dv_encap_decap_resource_register
3699 (struct rte_eth_dev *dev,
3700 struct mlx5_flow_dv_encap_decap_resource *resource,
3701 struct mlx5_flow *dev_flow,
3702 struct rte_flow_error *error)
3704 struct mlx5_priv *priv = dev->data->dev_private;
3705 struct mlx5_dev_ctx_shared *sh = priv->sh;
3706 struct mlx5_list_entry *entry;
3710 uint32_t refmt_type:8;
3712 * Header reformat actions can be shared between
3713 * non-root tables. One bit to indicate non-root
3717 uint32_t reserve:15;
3720 } encap_decap_key = {
3722 .ft_type = resource->ft_type,
3723 .refmt_type = resource->reformat_type,
3724 .is_root = !!dev_flow->dv.group,
3728 struct mlx5_flow_cb_ctx ctx = {
3732 struct mlx5_hlist *encaps_decaps;
3735 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3737 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3739 flow_dv_encap_decap_create_cb,
3740 flow_dv_encap_decap_match_cb,
3741 flow_dv_encap_decap_remove_cb,
3742 flow_dv_encap_decap_clone_cb,
3743 flow_dv_encap_decap_clone_free_cb);
3744 if (unlikely(!encaps_decaps))
3746 resource->flags = dev_flow->dv.group ? 0 : 1;
3747 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3748 sizeof(encap_decap_key.v32), 0);
3749 if (resource->reformat_type !=
3750 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3752 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3753 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3756 resource = container_of(entry, typeof(*resource), entry);
3757 dev_flow->dv.encap_decap = resource;
3758 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3763 * Find existing table jump resource or create and register a new one.
3765 * @param[in, out] dev
3766 * Pointer to rte_eth_dev structure.
3767 * @param[in, out] tbl
3768 * Pointer to flow table resource.
3769 * @parm[in, out] dev_flow
3770 * Pointer to the dev_flow.
3772 * pointer to error structure.
3775 * 0 on success otherwise -errno and errno is set.
3778 flow_dv_jump_tbl_resource_register
3779 (struct rte_eth_dev *dev __rte_unused,
3780 struct mlx5_flow_tbl_resource *tbl,
3781 struct mlx5_flow *dev_flow,
3782 struct rte_flow_error *error __rte_unused)
3784 struct mlx5_flow_tbl_data_entry *tbl_data =
3785 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3788 MLX5_ASSERT(tbl_data->jump.action);
3789 dev_flow->handle->rix_jump = tbl_data->idx;
3790 dev_flow->dv.jump = &tbl_data->jump;
3795 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3796 struct mlx5_list_entry *entry, void *cb_ctx)
3798 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3799 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3800 struct mlx5_flow_dv_port_id_action_resource *res =
3801 container_of(entry, typeof(*res), entry);
3803 return ref->port_id != res->port_id;
3806 struct mlx5_list_entry *
3807 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3809 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3810 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3811 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3812 struct mlx5_flow_dv_port_id_action_resource *resource;
3816 /* Register new port id action resource. */
3817 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3819 rte_flow_error_set(ctx->error, ENOMEM,
3820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3821 "cannot allocate port_id action memory");
3825 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3829 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3830 rte_flow_error_set(ctx->error, ENOMEM,
3831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3832 "cannot create action");
3835 resource->idx = idx;
3836 return &resource->entry;
3839 struct mlx5_list_entry *
3840 flow_dv_port_id_clone_cb(void *tool_ctx,
3841 struct mlx5_list_entry *entry __rte_unused,
3844 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3845 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3846 struct mlx5_flow_dv_port_id_action_resource *resource;
3849 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3851 rte_flow_error_set(ctx->error, ENOMEM,
3852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3853 "cannot allocate port_id action memory");
3856 memcpy(resource, entry, sizeof(*resource));
3857 resource->idx = idx;
3858 return &resource->entry;
3862 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3864 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3865 struct mlx5_flow_dv_port_id_action_resource *resource =
3866 container_of(entry, typeof(*resource), entry);
3868 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3872 * Find existing table port ID resource or create and register a new one.
3874 * @param[in, out] dev
3875 * Pointer to rte_eth_dev structure.
3876 * @param[in, out] ref
3877 * Pointer to port ID action resource reference.
3878 * @parm[in, out] dev_flow
3879 * Pointer to the dev_flow.
3881 * pointer to error structure.
3884 * 0 on success otherwise -errno and errno is set.
3887 flow_dv_port_id_action_resource_register
3888 (struct rte_eth_dev *dev,
3889 struct mlx5_flow_dv_port_id_action_resource *ref,
3890 struct mlx5_flow *dev_flow,
3891 struct rte_flow_error *error)
3893 struct mlx5_priv *priv = dev->data->dev_private;
3894 struct mlx5_list_entry *entry;
3895 struct mlx5_flow_dv_port_id_action_resource *resource;
3896 struct mlx5_flow_cb_ctx ctx = {
3901 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3904 resource = container_of(entry, typeof(*resource), entry);
3905 dev_flow->dv.port_id_action = resource;
3906 dev_flow->handle->rix_port_id_action = resource->idx;
3911 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3912 struct mlx5_list_entry *entry, void *cb_ctx)
3914 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3915 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3916 struct mlx5_flow_dv_push_vlan_action_resource *res =
3917 container_of(entry, typeof(*res), entry);
3919 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3922 struct mlx5_list_entry *
3923 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3925 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3926 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3927 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3928 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3929 struct mlx5dv_dr_domain *domain;
3933 /* Register new port id action resource. */
3934 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3936 rte_flow_error_set(ctx->error, ENOMEM,
3937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3938 "cannot allocate push_vlan action memory");
3942 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3943 domain = sh->fdb_domain;
3944 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3945 domain = sh->rx_domain;
3947 domain = sh->tx_domain;
3948 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3951 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3952 rte_flow_error_set(ctx->error, ENOMEM,
3953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3954 "cannot create push vlan action");
3957 resource->idx = idx;
3958 return &resource->entry;
3961 struct mlx5_list_entry *
3962 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3963 struct mlx5_list_entry *entry __rte_unused,
3966 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3967 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3968 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3971 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3973 rte_flow_error_set(ctx->error, ENOMEM,
3974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3975 "cannot allocate push_vlan action memory");
3978 memcpy(resource, entry, sizeof(*resource));
3979 resource->idx = idx;
3980 return &resource->entry;
3984 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3986 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3987 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3988 container_of(entry, typeof(*resource), entry);
3990 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3994 * Find existing push vlan resource or create and register a new one.
3996 * @param [in, out] dev
3997 * Pointer to rte_eth_dev structure.
3998 * @param[in, out] ref
3999 * Pointer to port ID action resource reference.
4000 * @parm[in, out] dev_flow
4001 * Pointer to the dev_flow.
4003 * pointer to error structure.
4006 * 0 on success otherwise -errno and errno is set.
4009 flow_dv_push_vlan_action_resource_register
4010 (struct rte_eth_dev *dev,
4011 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4012 struct mlx5_flow *dev_flow,
4013 struct rte_flow_error *error)
4015 struct mlx5_priv *priv = dev->data->dev_private;
4016 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4017 struct mlx5_list_entry *entry;
4018 struct mlx5_flow_cb_ctx ctx = {
4023 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4026 resource = container_of(entry, typeof(*resource), entry);
4028 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4029 dev_flow->dv.push_vlan_res = resource;
4034 * Get the size of specific rte_flow_item_type hdr size
4036 * @param[in] item_type
4037 * Tested rte_flow_item_type.
4040 * sizeof struct item_type, 0 if void or irrelevant.
4043 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4047 switch (item_type) {
4048 case RTE_FLOW_ITEM_TYPE_ETH:
4049 retval = sizeof(struct rte_ether_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VLAN:
4052 retval = sizeof(struct rte_vlan_hdr);
4054 case RTE_FLOW_ITEM_TYPE_IPV4:
4055 retval = sizeof(struct rte_ipv4_hdr);
4057 case RTE_FLOW_ITEM_TYPE_IPV6:
4058 retval = sizeof(struct rte_ipv6_hdr);
4060 case RTE_FLOW_ITEM_TYPE_UDP:
4061 retval = sizeof(struct rte_udp_hdr);
4063 case RTE_FLOW_ITEM_TYPE_TCP:
4064 retval = sizeof(struct rte_tcp_hdr);
4066 case RTE_FLOW_ITEM_TYPE_VXLAN:
4067 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4068 retval = sizeof(struct rte_vxlan_hdr);
4070 case RTE_FLOW_ITEM_TYPE_GRE:
4071 case RTE_FLOW_ITEM_TYPE_NVGRE:
4072 retval = sizeof(struct rte_gre_hdr);
4074 case RTE_FLOW_ITEM_TYPE_MPLS:
4075 retval = sizeof(struct rte_mpls_hdr);
4077 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4085 #define MLX5_ENCAP_IPV4_VERSION 0x40
4086 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4087 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4088 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4089 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4090 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4091 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4094 * Convert the encap action data from list of rte_flow_item to raw buffer
4097 * Pointer to rte_flow_item objects list.
4099 * Pointer to the output buffer.
4101 * Pointer to the output buffer size.
4103 * Pointer to the error structure.
4106 * 0 on success, a negative errno value otherwise and rte_errno is set.
4109 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4110 size_t *size, struct rte_flow_error *error)
4112 struct rte_ether_hdr *eth = NULL;
4113 struct rte_vlan_hdr *vlan = NULL;
4114 struct rte_ipv4_hdr *ipv4 = NULL;
4115 struct rte_ipv6_hdr *ipv6 = NULL;
4116 struct rte_udp_hdr *udp = NULL;
4117 struct rte_vxlan_hdr *vxlan = NULL;
4118 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4119 struct rte_gre_hdr *gre = NULL;
4121 size_t temp_size = 0;
4124 return rte_flow_error_set(error, EINVAL,
4125 RTE_FLOW_ERROR_TYPE_ACTION,
4126 NULL, "invalid empty data");
4127 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4128 len = flow_dv_get_item_hdr_len(items->type);
4129 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4130 return rte_flow_error_set(error, EINVAL,
4131 RTE_FLOW_ERROR_TYPE_ACTION,
4132 (void *)items->type,
4133 "items total size is too big"
4134 " for encap action");
4135 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4136 switch (items->type) {
4137 case RTE_FLOW_ITEM_TYPE_ETH:
4138 eth = (struct rte_ether_hdr *)&buf[temp_size];
4140 case RTE_FLOW_ITEM_TYPE_VLAN:
4141 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4143 return rte_flow_error_set(error, EINVAL,
4144 RTE_FLOW_ERROR_TYPE_ACTION,
4145 (void *)items->type,
4146 "eth header not found");
4147 if (!eth->ether_type)
4148 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4150 case RTE_FLOW_ITEM_TYPE_IPV4:
4151 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4153 return rte_flow_error_set(error, EINVAL,
4154 RTE_FLOW_ERROR_TYPE_ACTION,
4155 (void *)items->type,
4156 "neither eth nor vlan"
4158 if (vlan && !vlan->eth_proto)
4159 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4160 else if (eth && !eth->ether_type)
4161 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4162 if (!ipv4->version_ihl)
4163 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4164 MLX5_ENCAP_IPV4_IHL_MIN;
4165 if (!ipv4->time_to_live)
4166 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4168 case RTE_FLOW_ITEM_TYPE_IPV6:
4169 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4171 return rte_flow_error_set(error, EINVAL,
4172 RTE_FLOW_ERROR_TYPE_ACTION,
4173 (void *)items->type,
4174 "neither eth nor vlan"
4176 if (vlan && !vlan->eth_proto)
4177 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4178 else if (eth && !eth->ether_type)
4179 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4180 if (!ipv6->vtc_flow)
4182 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4183 if (!ipv6->hop_limits)
4184 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4186 case RTE_FLOW_ITEM_TYPE_UDP:
4187 udp = (struct rte_udp_hdr *)&buf[temp_size];
4189 return rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ACTION,
4191 (void *)items->type,
4192 "ip header not found");
4193 if (ipv4 && !ipv4->next_proto_id)
4194 ipv4->next_proto_id = IPPROTO_UDP;
4195 else if (ipv6 && !ipv6->proto)
4196 ipv6->proto = IPPROTO_UDP;
4198 case RTE_FLOW_ITEM_TYPE_VXLAN:
4199 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4201 return rte_flow_error_set(error, EINVAL,
4202 RTE_FLOW_ERROR_TYPE_ACTION,
4203 (void *)items->type,
4204 "udp header not found");
4206 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4207 if (!vxlan->vx_flags)
4209 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4211 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4212 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4214 return rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ACTION,
4216 (void *)items->type,
4217 "udp header not found");
4218 if (!vxlan_gpe->proto)
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4225 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4226 if (!vxlan_gpe->vx_flags)
4227 vxlan_gpe->vx_flags =
4228 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4230 case RTE_FLOW_ITEM_TYPE_GRE:
4231 case RTE_FLOW_ITEM_TYPE_NVGRE:
4232 gre = (struct rte_gre_hdr *)&buf[temp_size];
4234 return rte_flow_error_set(error, EINVAL,
4235 RTE_FLOW_ERROR_TYPE_ACTION,
4236 (void *)items->type,
4237 "next protocol not found");
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION,
4241 (void *)items->type,
4242 "ip header not found");
4243 if (ipv4 && !ipv4->next_proto_id)
4244 ipv4->next_proto_id = IPPROTO_GRE;
4245 else if (ipv6 && !ipv6->proto)
4246 ipv6->proto = IPPROTO_GRE;
4248 case RTE_FLOW_ITEM_TYPE_VOID:
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "unsupported item type");
4264 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4266 struct rte_ether_hdr *eth = NULL;
4267 struct rte_vlan_hdr *vlan = NULL;
4268 struct rte_ipv6_hdr *ipv6 = NULL;
4269 struct rte_udp_hdr *udp = NULL;
4273 eth = (struct rte_ether_hdr *)data;
4274 next_hdr = (char *)(eth + 1);
4275 proto = RTE_BE16(eth->ether_type);
4278 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4279 vlan = (struct rte_vlan_hdr *)next_hdr;
4280 proto = RTE_BE16(vlan->eth_proto);
4281 next_hdr += sizeof(struct rte_vlan_hdr);
4284 /* HW calculates IPv4 csum. no need to proceed */
4285 if (proto == RTE_ETHER_TYPE_IPV4)
4288 /* non IPv4/IPv6 header. not supported */
4289 if (proto != RTE_ETHER_TYPE_IPV6) {
4290 return rte_flow_error_set(error, ENOTSUP,
4291 RTE_FLOW_ERROR_TYPE_ACTION,
4292 NULL, "Cannot offload non IPv4/IPv6");
4295 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4297 /* ignore non UDP */
4298 if (ipv6->proto != IPPROTO_UDP)
4301 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4302 udp->dgram_cksum = 0;
4308 * Convert L2 encap action to DV specification.
4311 * Pointer to rte_eth_dev structure.
4313 * Pointer to action structure.
4314 * @param[in, out] dev_flow
4315 * Pointer to the mlx5_flow.
4316 * @param[in] transfer
4317 * Mark if the flow is E-Switch flow.
4319 * Pointer to the error structure.
4322 * 0 on success, a negative errno value otherwise and rte_errno is set.
4325 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4326 const struct rte_flow_action *action,
4327 struct mlx5_flow *dev_flow,
4329 struct rte_flow_error *error)
4331 const struct rte_flow_item *encap_data;
4332 const struct rte_flow_action_raw_encap *raw_encap_data;
4333 struct mlx5_flow_dv_encap_decap_resource res = {
4335 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4336 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4337 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4340 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4342 (const struct rte_flow_action_raw_encap *)action->conf;
4343 res.size = raw_encap_data->size;
4344 memcpy(res.buf, raw_encap_data->data, res.size);
4346 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4348 ((const struct rte_flow_action_vxlan_encap *)
4349 action->conf)->definition;
4352 ((const struct rte_flow_action_nvgre_encap *)
4353 action->conf)->definition;
4354 if (flow_dv_convert_encap_data(encap_data, res.buf,
4358 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4360 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4361 return rte_flow_error_set(error, EINVAL,
4362 RTE_FLOW_ERROR_TYPE_ACTION,
4363 NULL, "can't create L2 encap action");
4368 * Convert L2 decap action to DV specification.
4371 * Pointer to rte_eth_dev structure.
4372 * @param[in, out] dev_flow
4373 * Pointer to the mlx5_flow.
4374 * @param[in] transfer
4375 * Mark if the flow is E-Switch flow.
4377 * Pointer to the error structure.
4380 * 0 on success, a negative errno value otherwise and rte_errno is set.
4383 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4384 struct mlx5_flow *dev_flow,
4386 struct rte_flow_error *error)
4388 struct mlx5_flow_dv_encap_decap_resource res = {
4391 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4392 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4393 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4396 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4397 return rte_flow_error_set(error, EINVAL,
4398 RTE_FLOW_ERROR_TYPE_ACTION,
4399 NULL, "can't create L2 decap action");
4404 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4407 * Pointer to rte_eth_dev structure.
4409 * Pointer to action structure.
4410 * @param[in, out] dev_flow
4411 * Pointer to the mlx5_flow.
4413 * Pointer to the flow attributes.
4415 * Pointer to the error structure.
4418 * 0 on success, a negative errno value otherwise and rte_errno is set.
4421 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4422 const struct rte_flow_action *action,
4423 struct mlx5_flow *dev_flow,
4424 const struct rte_flow_attr *attr,
4425 struct rte_flow_error *error)
4427 const struct rte_flow_action_raw_encap *encap_data;
4428 struct mlx5_flow_dv_encap_decap_resource res;
4430 memset(&res, 0, sizeof(res));
4431 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4432 res.size = encap_data->size;
4433 memcpy(res.buf, encap_data->data, res.size);
4434 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4435 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4436 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4438 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4440 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4441 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4442 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4443 return rte_flow_error_set(error, EINVAL,
4444 RTE_FLOW_ERROR_TYPE_ACTION,
4445 NULL, "can't create encap action");
4450 * Create action push VLAN.
4453 * Pointer to rte_eth_dev structure.
4455 * Pointer to the flow attributes.
4457 * Pointer to the vlan to push to the Ethernet header.
4458 * @param[in, out] dev_flow
4459 * Pointer to the mlx5_flow.
4461 * Pointer to the error structure.
4464 * 0 on success, a negative errno value otherwise and rte_errno is set.
4467 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4468 const struct rte_flow_attr *attr,
4469 const struct rte_vlan_hdr *vlan,
4470 struct mlx5_flow *dev_flow,
4471 struct rte_flow_error *error)
4473 struct mlx5_flow_dv_push_vlan_action_resource res;
4475 memset(&res, 0, sizeof(res));
4477 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4480 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4482 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4483 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4484 return flow_dv_push_vlan_action_resource_register
4485 (dev, &res, dev_flow, error);
4489 * Validate the modify-header actions.
4491 * @param[in] action_flags
4492 * Holds the actions detected until now.
4494 * Pointer to the modify action.
4496 * Pointer to error structure.
4499 * 0 on success, a negative errno value otherwise and rte_errno is set.
4502 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4503 const struct rte_flow_action *action,
4504 struct rte_flow_error *error)
4506 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4507 return rte_flow_error_set(error, EINVAL,
4508 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4509 NULL, "action configuration not set");
4510 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4511 return rte_flow_error_set(error, EINVAL,
4512 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4513 "can't have encap action before"
4519 * Validate the modify-header MAC address actions.
4521 * @param[in] action_flags
4522 * Holds the actions detected until now.
4524 * Pointer to the modify action.
4525 * @param[in] item_flags
4526 * Holds the items detected.
4528 * Pointer to error structure.
4531 * 0 on success, a negative errno value otherwise and rte_errno is set.
4534 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4535 const struct rte_flow_action *action,
4536 const uint64_t item_flags,
4537 struct rte_flow_error *error)
4541 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4543 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4544 return rte_flow_error_set(error, EINVAL,
4545 RTE_FLOW_ERROR_TYPE_ACTION,
4547 "no L2 item in pattern");
4553 * Validate the modify-header IPv4 address actions.
4555 * @param[in] action_flags
4556 * Holds the actions detected until now.
4558 * Pointer to the modify action.
4559 * @param[in] item_flags
4560 * Holds the items detected.
4562 * Pointer to error structure.
4565 * 0 on success, a negative errno value otherwise and rte_errno is set.
4568 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4569 const struct rte_flow_action *action,
4570 const uint64_t item_flags,
4571 struct rte_flow_error *error)
4576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4579 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4580 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4581 if (!(item_flags & layer))
4582 return rte_flow_error_set(error, EINVAL,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "no ipv4 item in pattern");
4591 * Validate the modify-header IPv6 address actions.
4593 * @param[in] action_flags
4594 * Holds the actions detected until now.
4596 * Pointer to the modify action.
4597 * @param[in] item_flags
4598 * Holds the items detected.
4600 * Pointer to error structure.
4603 * 0 on success, a negative errno value otherwise and rte_errno is set.
4606 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4607 const struct rte_flow_action *action,
4608 const uint64_t item_flags,
4609 struct rte_flow_error *error)
4614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4616 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4617 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4618 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4619 if (!(item_flags & layer))
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "no ipv6 item in pattern");
4629 * Validate the modify-header TP actions.
4631 * @param[in] action_flags
4632 * Holds the actions detected until now.
4634 * Pointer to the modify action.
4635 * @param[in] item_flags
4636 * Holds the items detected.
4638 * Pointer to error structure.
4641 * 0 on success, a negative errno value otherwise and rte_errno is set.
4644 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4645 const struct rte_flow_action *action,
4646 const uint64_t item_flags,
4647 struct rte_flow_error *error)
4652 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4654 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4655 MLX5_FLOW_LAYER_INNER_L4 :
4656 MLX5_FLOW_LAYER_OUTER_L4;
4657 if (!(item_flags & layer))
4658 return rte_flow_error_set(error, EINVAL,
4659 RTE_FLOW_ERROR_TYPE_ACTION,
4660 NULL, "no transport layer "
4667 * Validate the modify-header actions of increment/decrement
4668 * TCP Sequence-number.
4670 * @param[in] action_flags
4671 * Holds the actions detected until now.
4673 * Pointer to the modify action.
4674 * @param[in] item_flags
4675 * Holds the items detected.
4677 * Pointer to error structure.
4680 * 0 on success, a negative errno value otherwise and rte_errno is set.
4683 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4684 const struct rte_flow_action *action,
4685 const uint64_t item_flags,
4686 struct rte_flow_error *error)
4691 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4693 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4694 MLX5_FLOW_LAYER_INNER_L4_TCP :
4695 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4696 if (!(item_flags & layer))
4697 return rte_flow_error_set(error, EINVAL,
4698 RTE_FLOW_ERROR_TYPE_ACTION,
4699 NULL, "no TCP item in"
4701 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4702 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4703 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4704 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4705 return rte_flow_error_set(error, EINVAL,
4706 RTE_FLOW_ERROR_TYPE_ACTION,
4708 "cannot decrease and increase"
4709 " TCP sequence number"
4710 " at the same time");
4716 * Validate the modify-header actions of increment/decrement
4717 * TCP Acknowledgment number.
4719 * @param[in] action_flags
4720 * Holds the actions detected until now.
4722 * Pointer to the modify action.
4723 * @param[in] item_flags
4724 * Holds the items detected.
4726 * Pointer to error structure.
4729 * 0 on success, a negative errno value otherwise and rte_errno is set.
4732 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4733 const struct rte_flow_action *action,
4734 const uint64_t item_flags,
4735 struct rte_flow_error *error)
4740 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4742 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4743 MLX5_FLOW_LAYER_INNER_L4_TCP :
4744 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4745 if (!(item_flags & layer))
4746 return rte_flow_error_set(error, EINVAL,
4747 RTE_FLOW_ERROR_TYPE_ACTION,
4748 NULL, "no TCP item in"
4750 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4751 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4752 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4753 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4754 return rte_flow_error_set(error, EINVAL,
4755 RTE_FLOW_ERROR_TYPE_ACTION,
4757 "cannot decrease and increase"
4758 " TCP acknowledgment number"
4759 " at the same time");
4765 * Validate the modify-header TTL actions.
4767 * @param[in] action_flags
4768 * Holds the actions detected until now.
4770 * Pointer to the modify action.
4771 * @param[in] item_flags
4772 * Holds the items detected.
4774 * Pointer to error structure.
4777 * 0 on success, a negative errno value otherwise and rte_errno is set.
4780 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4781 const struct rte_flow_action *action,
4782 const uint64_t item_flags,
4783 struct rte_flow_error *error)
4788 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4790 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4791 MLX5_FLOW_LAYER_INNER_L3 :
4792 MLX5_FLOW_LAYER_OUTER_L3;
4793 if (!(item_flags & layer))
4794 return rte_flow_error_set(error, EINVAL,
4795 RTE_FLOW_ERROR_TYPE_ACTION,
4797 "no IP protocol in pattern");
4803 * Validate the generic modify field actions.
4805 * Pointer to the rte_eth_dev structure.
4806 * @param[in] action_flags
4807 * Holds the actions detected until now.
4809 * Pointer to the modify action.
4811 * Pointer to the flow attributes.
4813 * Pointer to error structure.
4816 * Number of header fields to modify (0 or more) on success,
4817 * a negative errno value otherwise and rte_errno is set.
4820 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4821 const uint64_t action_flags,
4822 const struct rte_flow_action *action,
4823 const struct rte_flow_attr *attr,
4824 struct rte_flow_error *error)
4827 struct mlx5_priv *priv = dev->data->dev_private;
4828 struct mlx5_dev_config *config = &priv->config;
4829 const struct rte_flow_action_modify_field *action_modify_field =
4831 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4832 action_modify_field->dst.field,
4834 uint32_t src_width = mlx5_flow_item_field_width(dev,
4835 action_modify_field->src.field,
4836 dst_width, attr, error);
4838 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4842 if (action_modify_field->width == 0)
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "no bits are requested to be modified");
4846 else if (action_modify_field->width > dst_width ||
4847 action_modify_field->width > src_width)
4848 return rte_flow_error_set(error, EINVAL,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "cannot modify more bits than"
4851 " the width of a field");
4852 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4853 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4854 if ((action_modify_field->dst.offset +
4855 action_modify_field->width > dst_width) ||
4856 (action_modify_field->dst.offset % 32))
4857 return rte_flow_error_set(error, EINVAL,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "destination offset is too big"
4860 " or not aligned to 4 bytes");
4861 if (action_modify_field->dst.level &&
4862 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4863 return rte_flow_error_set(error, ENOTSUP,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "inner header fields modification"
4866 " is not supported");
4868 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4870 if (!attr->transfer && !attr->group)
4871 return rte_flow_error_set(error, ENOTSUP,
4872 RTE_FLOW_ERROR_TYPE_ACTION, action,
4873 "modify field action is not"
4874 " supported for group 0");
4875 if ((action_modify_field->src.offset +
4876 action_modify_field->width > src_width) ||
4877 (action_modify_field->src.offset % 32))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source offset is too big"
4881 " or not aligned to 4 bytes");
4882 if (action_modify_field->src.level &&
4883 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4884 return rte_flow_error_set(error, ENOTSUP,
4885 RTE_FLOW_ERROR_TYPE_ACTION, action,
4886 "inner header fields modification"
4887 " is not supported");
4889 if ((action_modify_field->dst.field ==
4890 action_modify_field->src.field) &&
4891 (action_modify_field->dst.level ==
4892 action_modify_field->src.level))
4893 return rte_flow_error_set(error, EINVAL,
4894 RTE_FLOW_ERROR_TYPE_ACTION, action,
4895 "source and destination fields"
4896 " cannot be the same");
4897 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4898 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4899 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4900 return rte_flow_error_set(error, EINVAL,
4901 RTE_FLOW_ERROR_TYPE_ACTION, action,
4902 "mark, immediate value or a pointer to it"
4903 " cannot be used as a destination");
4904 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4905 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4906 return rte_flow_error_set(error, ENOTSUP,
4907 RTE_FLOW_ERROR_TYPE_ACTION, action,
4908 "modifications of an arbitrary"
4909 " place in a packet is not supported");
4910 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4911 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION, action,
4914 "modifications of the 802.1Q Tag"
4915 " Identifier is not supported");
4916 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4917 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "modifications of the VXLAN Network"
4921 " Identifier is not supported");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4924 return rte_flow_error_set(error, ENOTSUP,
4925 RTE_FLOW_ERROR_TYPE_ACTION, action,
4926 "modifications of the GENEVE Network"
4927 " Identifier is not supported");
4928 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4929 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4930 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4931 !mlx5_flow_ext_mreg_supported(dev))
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify mark in legacy mode"
4935 " or without extensive registers");
4936 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4937 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4938 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4939 !mlx5_flow_ext_mreg_supported(dev))
4940 return rte_flow_error_set(error, ENOTSUP,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "cannot modify meta without"
4943 " extensive registers support");
4944 ret = flow_dv_get_metadata_reg(dev, attr, error);
4945 if (ret < 0 || ret == REG_NON)
4946 return rte_flow_error_set(error, ENOTSUP,
4947 RTE_FLOW_ERROR_TYPE_ACTION, action,
4948 "cannot modify meta without"
4949 " extensive registers available");
4951 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4952 return rte_flow_error_set(error, ENOTSUP,
4953 RTE_FLOW_ERROR_TYPE_ACTION, action,
4954 "add and sub operations"
4955 " are not supported");
4956 return (action_modify_field->width / 32) +
4957 !!(action_modify_field->width % 32);
4961 * Validate jump action.
4964 * Pointer to the jump action.
4965 * @param[in] action_flags
4966 * Holds the actions detected until now.
4967 * @param[in] attributes
4968 * Pointer to flow attributes
4969 * @param[in] external
4970 * Action belongs to flow rule created by request external to PMD.
4972 * Pointer to error structure.
4975 * 0 on success, a negative errno value otherwise and rte_errno is set.
4978 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4979 const struct mlx5_flow_tunnel *tunnel,
4980 const struct rte_flow_action *action,
4981 uint64_t action_flags,
4982 const struct rte_flow_attr *attributes,
4983 bool external, struct rte_flow_error *error)
4985 uint32_t target_group, table;
4987 struct flow_grp_info grp_info = {
4988 .external = !!external,
4989 .transfer = !!attributes->transfer,
4993 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4994 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4995 return rte_flow_error_set(error, EINVAL,
4996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4997 "can't have 2 fate actions in"
5000 return rte_flow_error_set(error, EINVAL,
5001 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5002 NULL, "action configuration not set");
5004 ((const struct rte_flow_action_jump *)action->conf)->group;
5005 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5009 if (attributes->group == target_group &&
5010 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5011 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "target group must be other than"
5015 " the current flow group");
5020 * Validate action PORT_ID / REPRESENTED_PORT.
5023 * Pointer to rte_eth_dev structure.
5024 * @param[in] action_flags
5025 * Bit-fields that holds the actions detected until now.
5027 * PORT_ID / REPRESENTED_PORT action structure.
5029 * Attributes of flow that includes this action.
5031 * Pointer to error structure.
5034 * 0 on success, a negative errno value otherwise and rte_errno is set.
5037 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5038 uint64_t action_flags,
5039 const struct rte_flow_action *action,
5040 const struct rte_flow_attr *attr,
5041 struct rte_flow_error *error)
5043 const struct rte_flow_action_port_id *port_id;
5044 const struct rte_flow_action_ethdev *ethdev;
5045 struct mlx5_priv *act_priv;
5046 struct mlx5_priv *dev_priv;
5049 if (!attr->transfer)
5050 return rte_flow_error_set(error, ENOTSUP,
5051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5053 "port action is valid in transfer"
5055 if (!action || !action->conf)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5059 "port action parameters must be"
5061 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5062 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5063 return rte_flow_error_set(error, EINVAL,
5064 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5065 "can have only one fate actions in"
5067 dev_priv = mlx5_dev_to_eswitch_info(dev);
5069 return rte_flow_error_set(error, rte_errno,
5070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5072 "failed to obtain E-Switch info");
5073 switch (action->type) {
5074 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5075 port_id = action->conf;
5076 port = port_id->original ? dev->data->port_id : port_id->id;
5078 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5079 ethdev = action->conf;
5080 port = ethdev->port_id;
5084 return rte_flow_error_set
5086 RTE_FLOW_ERROR_TYPE_ACTION, action,
5087 "unknown E-Switch action");
5089 act_priv = mlx5_port_to_eswitch_info(port, false);
5091 return rte_flow_error_set
5093 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5094 "failed to obtain E-Switch port id for port");
5095 if (act_priv->domain_id != dev_priv->domain_id)
5096 return rte_flow_error_set
5098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5099 "port does not belong to"
5100 " E-Switch being configured");
5105 * Get the maximum number of modify header actions.
5108 * Pointer to rte_eth_dev structure.
5110 * Whether action is on root table.
5113 * Max number of modify header actions device can support.
5115 static inline unsigned int
5116 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5120 * There's no way to directly query the max capacity from FW.
5121 * The maximal value on root table should be assumed to be supported.
5124 return MLX5_MAX_MODIFY_NUM;
5126 return MLX5_ROOT_TBL_MODIFY_NUM;
5130 * Validate the meter action.
5133 * Pointer to rte_eth_dev structure.
5134 * @param[in] action_flags
5135 * Bit-fields that holds the actions detected until now.
5136 * @param[in] item_flags
5137 * Holds the items detected.
5139 * Pointer to the meter action.
5141 * Attributes of flow that includes this action.
5142 * @param[in] port_id_item
5143 * Pointer to item indicating port id.
5145 * Pointer to error structure.
5148 * 0 on success, a negative errno value otherwise and rte_errno is set.
5151 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5152 uint64_t action_flags, uint64_t item_flags,
5153 const struct rte_flow_action *action,
5154 const struct rte_flow_attr *attr,
5155 const struct rte_flow_item *port_id_item,
5157 struct rte_flow_error *error)
5159 struct mlx5_priv *priv = dev->data->dev_private;
5160 const struct rte_flow_action_meter *am = action->conf;
5161 struct mlx5_flow_meter_info *fm;
5162 struct mlx5_flow_meter_policy *mtr_policy;
5163 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5166 return rte_flow_error_set(error, EINVAL,
5167 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5168 "meter action conf is NULL");
5170 if (action_flags & MLX5_FLOW_ACTION_METER)
5171 return rte_flow_error_set(error, ENOTSUP,
5172 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5173 "meter chaining not support");
5174 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5175 return rte_flow_error_set(error, ENOTSUP,
5176 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5177 "meter with jump not support");
5179 return rte_flow_error_set(error, ENOTSUP,
5180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5182 "meter action not supported");
5183 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5185 return rte_flow_error_set(error, EINVAL,
5186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5188 /* aso meter can always be shared by different domains */
5189 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5190 !(fm->transfer == attr->transfer ||
5191 (!fm->ingress && !attr->ingress && attr->egress) ||
5192 (!fm->egress && !attr->egress && attr->ingress)))
5193 return rte_flow_error_set(error, EINVAL,
5194 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5195 "Flow attributes domain are either invalid "
5196 "or have a domain conflict with current "
5197 "meter attributes");
5198 if (fm->def_policy) {
5199 if (!((attr->transfer &&
5200 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5202 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5204 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5205 return rte_flow_error_set(error, EINVAL,
5206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5207 "Flow attributes domain "
5208 "have a conflict with current "
5209 "meter domain attributes");
5212 mtr_policy = mlx5_flow_meter_policy_find(dev,
5213 fm->policy_id, NULL);
5215 return rte_flow_error_set(error, EINVAL,
5216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5217 "Invalid policy id for meter ");
5218 if (!((attr->transfer && mtr_policy->transfer) ||
5219 (attr->egress && mtr_policy->egress) ||
5220 (attr->ingress && mtr_policy->ingress)))
5221 return rte_flow_error_set(error, EINVAL,
5222 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5223 "Flow attributes domain "
5224 "have a conflict with current "
5225 "meter domain attributes");
5226 if (attr->transfer && mtr_policy->dev) {
5228 * When policy has fate action of port_id,
5229 * the flow should have the same src port as policy.
5231 struct mlx5_priv *policy_port_priv =
5232 mtr_policy->dev->data->dev_private;
5233 int32_t flow_src_port = priv->representor_id;
5236 const struct rte_flow_item_port_id *spec =
5238 struct mlx5_priv *port_priv =
5239 mlx5_port_to_eswitch_info(spec->id,
5242 return rte_flow_error_set(error,
5244 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5246 "Failed to get port info.");
5247 flow_src_port = port_priv->representor_id;
5249 if (flow_src_port != policy_port_priv->representor_id)
5250 return rte_flow_error_set(error,
5252 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5254 "Flow and meter policy "
5255 "have different src port.");
5256 } else if (mtr_policy->is_rss) {
5257 struct mlx5_flow_meter_policy *fp;
5258 struct mlx5_meter_policy_action_container *acg;
5259 struct mlx5_meter_policy_action_container *acy;
5260 const struct rte_flow_action *rss_act;
5263 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5266 return rte_flow_error_set(error, EINVAL,
5267 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5268 "Unable to get the final "
5269 "policy in the hierarchy");
5270 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5271 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5272 MLX5_ASSERT(acg->fate_action ==
5273 MLX5_FLOW_FATE_SHARED_RSS ||
5275 MLX5_FLOW_FATE_SHARED_RSS);
5276 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5280 ret = mlx5_flow_validate_action_rss(rss_act,
5281 action_flags, dev, attr,
5286 *def_policy = false;
5292 * Validate the age action.
5294 * @param[in] action_flags
5295 * Holds the actions detected until now.
5297 * Pointer to the age action.
5299 * Pointer to the Ethernet device structure.
5301 * Pointer to error structure.
5304 * 0 on success, a negative errno value otherwise and rte_errno is set.
5307 flow_dv_validate_action_age(uint64_t action_flags,
5308 const struct rte_flow_action *action,
5309 struct rte_eth_dev *dev,
5310 struct rte_flow_error *error)
5312 struct mlx5_priv *priv = dev->data->dev_private;
5313 const struct rte_flow_action_age *age = action->conf;
5315 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5316 !priv->sh->aso_age_mng))
5317 return rte_flow_error_set(error, ENOTSUP,
5318 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5320 "age action not supported");
5321 if (!(action->conf))
5322 return rte_flow_error_set(error, EINVAL,
5323 RTE_FLOW_ERROR_TYPE_ACTION, action,
5324 "configuration cannot be null");
5325 if (!(age->timeout))
5326 return rte_flow_error_set(error, EINVAL,
5327 RTE_FLOW_ERROR_TYPE_ACTION, action,
5328 "invalid timeout value 0");
5329 if (action_flags & MLX5_FLOW_ACTION_AGE)
5330 return rte_flow_error_set(error, EINVAL,
5331 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5332 "duplicate age actions set");
5337 * Validate the modify-header IPv4 DSCP actions.
5339 * @param[in] action_flags
5340 * Holds the actions detected until now.
5342 * Pointer to the modify action.
5343 * @param[in] item_flags
5344 * Holds the items detected.
5346 * Pointer to error structure.
5349 * 0 on success, a negative errno value otherwise and rte_errno is set.
5352 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5353 const struct rte_flow_action *action,
5354 const uint64_t item_flags,
5355 struct rte_flow_error *error)
5359 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5361 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5362 return rte_flow_error_set(error, EINVAL,
5363 RTE_FLOW_ERROR_TYPE_ACTION,
5365 "no ipv4 item in pattern");
5371 * Validate the modify-header IPv6 DSCP actions.
5373 * @param[in] action_flags
5374 * Holds the actions detected until now.
5376 * Pointer to the modify action.
5377 * @param[in] item_flags
5378 * Holds the items detected.
5380 * Pointer to error structure.
5383 * 0 on success, a negative errno value otherwise and rte_errno is set.
5386 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5387 const struct rte_flow_action *action,
5388 const uint64_t item_flags,
5389 struct rte_flow_error *error)
5393 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5395 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5396 return rte_flow_error_set(error, EINVAL,
5397 RTE_FLOW_ERROR_TYPE_ACTION,
5399 "no ipv6 item in pattern");
5405 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5406 struct mlx5_list_entry *entry, void *cb_ctx)
5408 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5409 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5410 struct mlx5_flow_dv_modify_hdr_resource *resource =
5411 container_of(entry, typeof(*resource), entry);
5412 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5414 key_len += ref->actions_num * sizeof(ref->actions[0]);
5415 return ref->actions_num != resource->actions_num ||
5416 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5419 static struct mlx5_indexed_pool *
5420 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5422 struct mlx5_indexed_pool *ipool = __atomic_load_n
5423 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5426 struct mlx5_indexed_pool *expected = NULL;
5427 struct mlx5_indexed_pool_config cfg =
5428 (struct mlx5_indexed_pool_config) {
5429 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5431 sizeof(struct mlx5_modification_cmd),
5436 .release_mem_en = !!sh->reclaim_mode,
5437 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5438 .malloc = mlx5_malloc,
5440 .type = "mlx5_modify_action_resource",
5443 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5444 ipool = mlx5_ipool_create(&cfg);
5447 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5448 &expected, ipool, false,
5450 __ATOMIC_SEQ_CST)) {
5451 mlx5_ipool_destroy(ipool);
5452 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5459 struct mlx5_list_entry *
5460 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5462 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5463 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5464 struct mlx5dv_dr_domain *ns;
5465 struct mlx5_flow_dv_modify_hdr_resource *entry;
5466 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5467 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5468 ref->actions_num - 1);
5470 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5471 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5474 if (unlikely(!ipool)) {
5475 rte_flow_error_set(ctx->error, ENOMEM,
5476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5477 NULL, "cannot allocate modify ipool");
5480 entry = mlx5_ipool_zmalloc(ipool, &idx);
5482 rte_flow_error_set(ctx->error, ENOMEM,
5483 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5484 "cannot allocate resource memory");
5487 rte_memcpy(&entry->ft_type,
5488 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5489 key_len + data_len);
5490 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5491 ns = sh->fdb_domain;
5492 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5496 ret = mlx5_flow_os_create_flow_action_modify_header
5497 (sh->cdev->ctx, ns, entry,
5498 data_len, &entry->action);
5500 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5501 rte_flow_error_set(ctx->error, ENOMEM,
5502 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5503 NULL, "cannot create modification action");
5507 return &entry->entry;
5510 struct mlx5_list_entry *
5511 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5514 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5515 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5516 struct mlx5_flow_dv_modify_hdr_resource *entry;
5517 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5518 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5521 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5524 rte_flow_error_set(ctx->error, ENOMEM,
5525 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5526 "cannot allocate resource memory");
5529 memcpy(entry, oentry, sizeof(*entry) + data_len);
5531 return &entry->entry;
5535 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5537 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5538 struct mlx5_flow_dv_modify_hdr_resource *res =
5539 container_of(entry, typeof(*res), entry);
5541 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5545 * Validate the sample action.
5547 * @param[in, out] action_flags
5548 * Holds the actions detected until now.
5550 * Pointer to the sample action.
5552 * Pointer to the Ethernet device structure.
5554 * Attributes of flow that includes this action.
5555 * @param[in] item_flags
5556 * Holds the items detected.
5558 * Pointer to the RSS action.
5559 * @param[out] sample_rss
5560 * Pointer to the RSS action in sample action list.
5562 * Pointer to the COUNT action in sample action list.
5563 * @param[out] fdb_mirror_limit
5564 * Pointer to the FDB mirror limitation flag.
5566 * Pointer to error structure.
5569 * 0 on success, a negative errno value otherwise and rte_errno is set.
5572 flow_dv_validate_action_sample(uint64_t *action_flags,
5573 const struct rte_flow_action *action,
5574 struct rte_eth_dev *dev,
5575 const struct rte_flow_attr *attr,
5576 uint64_t item_flags,
5577 const struct rte_flow_action_rss *rss,
5578 const struct rte_flow_action_rss **sample_rss,
5579 const struct rte_flow_action_count **count,
5580 int *fdb_mirror_limit,
5581 struct rte_flow_error *error)
5583 struct mlx5_priv *priv = dev->data->dev_private;
5584 struct mlx5_dev_config *dev_conf = &priv->config;
5585 const struct rte_flow_action_sample *sample = action->conf;
5586 const struct rte_flow_action *act;
5587 uint64_t sub_action_flags = 0;
5588 uint16_t queue_index = 0xFFFF;
5593 return rte_flow_error_set(error, EINVAL,
5594 RTE_FLOW_ERROR_TYPE_ACTION, action,
5595 "configuration cannot be NULL");
5596 if (sample->ratio == 0)
5597 return rte_flow_error_set(error, EINVAL,
5598 RTE_FLOW_ERROR_TYPE_ACTION, action,
5599 "ratio value starts from 1");
5600 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5601 return rte_flow_error_set(error, ENOTSUP,
5602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5604 "sample action not supported");
5605 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5606 return rte_flow_error_set(error, EINVAL,
5607 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5608 "Multiple sample actions not "
5610 if (*action_flags & MLX5_FLOW_ACTION_METER)
5611 return rte_flow_error_set(error, EINVAL,
5612 RTE_FLOW_ERROR_TYPE_ACTION, action,
5613 "wrong action order, meter should "
5614 "be after sample action");
5615 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5616 return rte_flow_error_set(error, EINVAL,
5617 RTE_FLOW_ERROR_TYPE_ACTION, action,
5618 "wrong action order, jump should "
5619 "be after sample action");
5620 if (*action_flags & MLX5_FLOW_ACTION_CT)
5621 return rte_flow_error_set(error, EINVAL,
5622 RTE_FLOW_ERROR_TYPE_ACTION, action,
5623 "Sample after CT not supported");
5624 act = sample->actions;
5625 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5626 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5627 return rte_flow_error_set(error, ENOTSUP,
5628 RTE_FLOW_ERROR_TYPE_ACTION,
5629 act, "too many actions");
5630 switch (act->type) {
5631 case RTE_FLOW_ACTION_TYPE_QUEUE:
5632 ret = mlx5_flow_validate_action_queue(act,
5638 queue_index = ((const struct rte_flow_action_queue *)
5639 (act->conf))->index;
5640 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5643 case RTE_FLOW_ACTION_TYPE_RSS:
5644 *sample_rss = act->conf;
5645 ret = mlx5_flow_validate_action_rss(act,
5652 if (rss && *sample_rss &&
5653 ((*sample_rss)->level != rss->level ||
5654 (*sample_rss)->types != rss->types))
5655 return rte_flow_error_set(error, ENOTSUP,
5656 RTE_FLOW_ERROR_TYPE_ACTION,
5658 "Can't use the different RSS types "
5659 "or level in the same flow");
5660 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5661 queue_index = (*sample_rss)->queue[0];
5662 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5665 case RTE_FLOW_ACTION_TYPE_MARK:
5666 ret = flow_dv_validate_action_mark(dev, act,
5671 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5672 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5673 MLX5_FLOW_ACTION_MARK_EXT;
5675 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5678 case RTE_FLOW_ACTION_TYPE_COUNT:
5679 ret = flow_dv_validate_action_count
5680 (dev, false, *action_flags | sub_action_flags,
5685 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5686 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5689 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5690 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5691 ret = flow_dv_validate_action_port_id(dev,
5698 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5701 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5702 ret = flow_dv_validate_action_raw_encap_decap
5703 (dev, NULL, act->conf, attr, &sub_action_flags,
5704 &actions_n, action, item_flags, error);
5709 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5710 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5711 ret = flow_dv_validate_action_l2_encap(dev,
5717 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5721 return rte_flow_error_set(error, ENOTSUP,
5722 RTE_FLOW_ERROR_TYPE_ACTION,
5724 "Doesn't support optional "
5728 if (attr->ingress && !attr->transfer) {
5729 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5730 MLX5_FLOW_ACTION_RSS)))
5731 return rte_flow_error_set(error, EINVAL,
5732 RTE_FLOW_ERROR_TYPE_ACTION,
5734 "Ingress must has a dest "
5735 "QUEUE for Sample");
5736 } else if (attr->egress && !attr->transfer) {
5737 return rte_flow_error_set(error, ENOTSUP,
5738 RTE_FLOW_ERROR_TYPE_ACTION,
5740 "Sample Only support Ingress "
5742 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5743 MLX5_ASSERT(attr->transfer);
5744 if (sample->ratio > 1)
5745 return rte_flow_error_set(error, ENOTSUP,
5746 RTE_FLOW_ERROR_TYPE_ACTION,
5748 "E-Switch doesn't support "
5749 "any optional action "
5751 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5752 return rte_flow_error_set(error, ENOTSUP,
5753 RTE_FLOW_ERROR_TYPE_ACTION,
5755 "unsupported action QUEUE");
5756 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5757 return rte_flow_error_set(error, ENOTSUP,
5758 RTE_FLOW_ERROR_TYPE_ACTION,
5760 "unsupported action QUEUE");
5761 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5762 return rte_flow_error_set(error, EINVAL,
5763 RTE_FLOW_ERROR_TYPE_ACTION,
5765 "E-Switch must has a dest "
5766 "port for mirroring");
5767 if (!priv->config.hca_attr.reg_c_preserve &&
5768 priv->representor_id != UINT16_MAX)
5769 *fdb_mirror_limit = 1;
5771 /* Continue validation for Xcap actions.*/
5772 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5773 (queue_index == 0xFFFF ||
5774 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5775 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5776 MLX5_FLOW_XCAP_ACTIONS)
5777 return rte_flow_error_set(error, ENOTSUP,
5778 RTE_FLOW_ERROR_TYPE_ACTION,
5779 NULL, "encap and decap "
5780 "combination aren't "
5782 if (!attr->transfer && attr->ingress && (sub_action_flags &
5783 MLX5_FLOW_ACTION_ENCAP))
5784 return rte_flow_error_set(error, ENOTSUP,
5785 RTE_FLOW_ERROR_TYPE_ACTION,
5786 NULL, "encap is not supported"
5787 " for ingress traffic");
5793 * Find existing modify-header resource or create and register a new one.
5795 * @param dev[in, out]
5796 * Pointer to rte_eth_dev structure.
5797 * @param[in, out] resource
5798 * Pointer to modify-header resource.
5799 * @parm[in, out] dev_flow
5800 * Pointer to the dev_flow.
5802 * pointer to error structure.
5805 * 0 on success otherwise -errno and errno is set.
5808 flow_dv_modify_hdr_resource_register
5809 (struct rte_eth_dev *dev,
5810 struct mlx5_flow_dv_modify_hdr_resource *resource,
5811 struct mlx5_flow *dev_flow,
5812 struct rte_flow_error *error)
5814 struct mlx5_priv *priv = dev->data->dev_private;
5815 struct mlx5_dev_ctx_shared *sh = priv->sh;
5816 uint32_t key_len = sizeof(*resource) -
5817 offsetof(typeof(*resource), ft_type) +
5818 resource->actions_num * sizeof(resource->actions[0]);
5819 struct mlx5_list_entry *entry;
5820 struct mlx5_flow_cb_ctx ctx = {
5824 struct mlx5_hlist *modify_cmds;
5827 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5829 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5831 flow_dv_modify_create_cb,
5832 flow_dv_modify_match_cb,
5833 flow_dv_modify_remove_cb,
5834 flow_dv_modify_clone_cb,
5835 flow_dv_modify_clone_free_cb);
5836 if (unlikely(!modify_cmds))
5838 resource->root = !dev_flow->dv.group;
5839 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5841 return rte_flow_error_set(error, EOVERFLOW,
5842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5843 "too many modify header items");
5844 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5845 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5848 resource = container_of(entry, typeof(*resource), entry);
5849 dev_flow->handle->dvh.modify_hdr = resource;
5854 * Get DV flow counter by index.
5857 * Pointer to the Ethernet device structure.
5859 * mlx5 flow counter index in the container.
5861 * mlx5 flow counter pool in the container.
5864 * Pointer to the counter, NULL otherwise.
5866 static struct mlx5_flow_counter *
5867 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5869 struct mlx5_flow_counter_pool **ppool)
5871 struct mlx5_priv *priv = dev->data->dev_private;
5872 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5873 struct mlx5_flow_counter_pool *pool;
5875 /* Decrease to original index and clear shared bit. */
5876 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5877 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5878 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5882 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5886 * Check the devx counter belongs to the pool.
5889 * Pointer to the counter pool.
5891 * The counter devx ID.
5894 * True if counter belongs to the pool, false otherwise.
5897 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5899 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5900 MLX5_COUNTERS_PER_POOL;
5902 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5908 * Get a pool by devx counter ID.
5911 * Pointer to the counter management.
5913 * The counter devx ID.
5916 * The counter pool pointer if exists, NULL otherwise,
5918 static struct mlx5_flow_counter_pool *
5919 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5922 struct mlx5_flow_counter_pool *pool = NULL;
5924 rte_spinlock_lock(&cmng->pool_update_sl);
5925 /* Check last used pool. */
5926 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5927 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5928 pool = cmng->pools[cmng->last_pool_idx];
5931 /* ID out of range means no suitable pool in the container. */
5932 if (id > cmng->max_id || id < cmng->min_id)
5935 * Find the pool from the end of the container, since mostly counter
5936 * ID is sequence increasing, and the last pool should be the needed
5941 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5943 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5949 rte_spinlock_unlock(&cmng->pool_update_sl);
5954 * Resize a counter container.
5957 * Pointer to the Ethernet device structure.
5960 * 0 on success, otherwise negative errno value and rte_errno is set.
5963 flow_dv_container_resize(struct rte_eth_dev *dev)
5965 struct mlx5_priv *priv = dev->data->dev_private;
5966 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5967 void *old_pools = cmng->pools;
5968 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5969 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5970 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5977 memcpy(pools, old_pools, cmng->n *
5978 sizeof(struct mlx5_flow_counter_pool *));
5980 cmng->pools = pools;
5982 mlx5_free(old_pools);
5987 * Query a devx flow counter.
5990 * Pointer to the Ethernet device structure.
5991 * @param[in] counter
5992 * Index to the flow counter.
5994 * The statistics value of packets.
5996 * The statistics value of bytes.
5999 * 0 on success, otherwise a negative errno value and rte_errno is set.
6002 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
6005 struct mlx5_priv *priv = dev->data->dev_private;
6006 struct mlx5_flow_counter_pool *pool = NULL;
6007 struct mlx5_flow_counter *cnt;
6010 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6012 if (priv->sh->cmng.counter_fallback)
6013 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6014 0, pkts, bytes, 0, NULL, NULL, 0);
6015 rte_spinlock_lock(&pool->sl);
6020 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6021 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6022 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6024 rte_spinlock_unlock(&pool->sl);
6029 * Create and initialize a new counter pool.
6032 * Pointer to the Ethernet device structure.
6034 * The devX counter handle.
6036 * Whether the pool is for counter that was allocated for aging.
6037 * @param[in/out] cont_cur
6038 * Pointer to the container pointer, it will be update in pool resize.
6041 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6043 static struct mlx5_flow_counter_pool *
6044 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6047 struct mlx5_priv *priv = dev->data->dev_private;
6048 struct mlx5_flow_counter_pool *pool;
6049 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6050 bool fallback = priv->sh->cmng.counter_fallback;
6051 uint32_t size = sizeof(*pool);
6053 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6054 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6055 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6061 pool->is_aged = !!age;
6062 pool->query_gen = 0;
6063 pool->min_dcs = dcs;
6064 rte_spinlock_init(&pool->sl);
6065 rte_spinlock_init(&pool->csl);
6066 TAILQ_INIT(&pool->counters[0]);
6067 TAILQ_INIT(&pool->counters[1]);
6068 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6069 rte_spinlock_lock(&cmng->pool_update_sl);
6070 pool->index = cmng->n_valid;
6071 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6073 rte_spinlock_unlock(&cmng->pool_update_sl);
6076 cmng->pools[pool->index] = pool;
6078 if (unlikely(fallback)) {
6079 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6081 if (base < cmng->min_id)
6082 cmng->min_id = base;
6083 if (base > cmng->max_id)
6084 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6085 cmng->last_pool_idx = pool->index;
6087 rte_spinlock_unlock(&cmng->pool_update_sl);
6092 * Prepare a new counter and/or a new counter pool.
6095 * Pointer to the Ethernet device structure.
6096 * @param[out] cnt_free
6097 * Where to put the pointer of a new counter.
6099 * Whether the pool is for counter that was allocated for aging.
6102 * The counter pool pointer and @p cnt_free is set on success,
6103 * NULL otherwise and rte_errno is set.
6105 static struct mlx5_flow_counter_pool *
6106 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6107 struct mlx5_flow_counter **cnt_free,
6110 struct mlx5_priv *priv = dev->data->dev_private;
6111 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6112 struct mlx5_flow_counter_pool *pool;
6113 struct mlx5_counters tmp_tq;
6114 struct mlx5_devx_obj *dcs = NULL;
6115 struct mlx5_flow_counter *cnt;
6116 enum mlx5_counter_type cnt_type =
6117 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6118 bool fallback = priv->sh->cmng.counter_fallback;
6122 /* bulk_bitmap must be 0 for single counter allocation. */
6123 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6126 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6128 pool = flow_dv_pool_create(dev, dcs, age);
6130 mlx5_devx_cmd_destroy(dcs);
6134 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6135 cnt = MLX5_POOL_GET_CNT(pool, i);
6137 cnt->dcs_when_free = dcs;
6141 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6143 rte_errno = ENODATA;
6146 pool = flow_dv_pool_create(dev, dcs, age);
6148 mlx5_devx_cmd_destroy(dcs);
6151 TAILQ_INIT(&tmp_tq);
6152 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6153 cnt = MLX5_POOL_GET_CNT(pool, i);
6155 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6157 rte_spinlock_lock(&cmng->csl[cnt_type]);
6158 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6159 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6160 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6161 (*cnt_free)->pool = pool;
6166 * Allocate a flow counter.
6169 * Pointer to the Ethernet device structure.
6171 * Whether the counter was allocated for aging.
6174 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6177 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6179 struct mlx5_priv *priv = dev->data->dev_private;
6180 struct mlx5_flow_counter_pool *pool = NULL;
6181 struct mlx5_flow_counter *cnt_free = NULL;
6182 bool fallback = priv->sh->cmng.counter_fallback;
6183 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6184 enum mlx5_counter_type cnt_type =
6185 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6188 if (!priv->sh->devx) {
6189 rte_errno = ENOTSUP;
6192 /* Get free counters from container. */
6193 rte_spinlock_lock(&cmng->csl[cnt_type]);
6194 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6196 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6197 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6198 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6200 pool = cnt_free->pool;
6202 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6203 /* Create a DV counter action only in the first time usage. */
6204 if (!cnt_free->action) {
6206 struct mlx5_devx_obj *dcs;
6210 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6211 dcs = pool->min_dcs;
6214 dcs = cnt_free->dcs_when_free;
6216 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6223 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6224 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6225 /* Update the counter reset values. */
6226 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6229 if (!fallback && !priv->sh->cmng.query_thread_on)
6230 /* Start the asynchronous batch query by the host thread. */
6231 mlx5_set_query_alarm(priv->sh);
6233 * When the count action isn't shared (by ID), shared_info field is
6234 * used for indirect action API's refcnt.
6235 * When the counter action is not shared neither by ID nor by indirect
6236 * action API, shared info must be 1.
6238 cnt_free->shared_info.refcnt = 1;
6242 cnt_free->pool = pool;
6244 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6245 rte_spinlock_lock(&cmng->csl[cnt_type]);
6246 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6247 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6253 * Get age param from counter index.
6256 * Pointer to the Ethernet device structure.
6257 * @param[in] counter
6258 * Index to the counter handler.
6261 * The aging parameter specified for the counter index.
6263 static struct mlx5_age_param*
6264 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6267 struct mlx5_flow_counter *cnt;
6268 struct mlx5_flow_counter_pool *pool = NULL;
6270 flow_dv_counter_get_by_idx(dev, counter, &pool);
6271 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6272 cnt = MLX5_POOL_GET_CNT(pool, counter);
6273 return MLX5_CNT_TO_AGE(cnt);
6277 * Remove a flow counter from aged counter list.
6280 * Pointer to the Ethernet device structure.
6281 * @param[in] counter
6282 * Index to the counter handler.
6284 * Pointer to the counter handler.
6287 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6288 uint32_t counter, struct mlx5_flow_counter *cnt)
6290 struct mlx5_age_info *age_info;
6291 struct mlx5_age_param *age_param;
6292 struct mlx5_priv *priv = dev->data->dev_private;
6293 uint16_t expected = AGE_CANDIDATE;
6295 age_info = GET_PORT_AGE_INFO(priv);
6296 age_param = flow_dv_counter_idx_get_age(dev, counter);
6297 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6298 AGE_FREE, false, __ATOMIC_RELAXED,
6299 __ATOMIC_RELAXED)) {
6301 * We need the lock even it is age timeout,
6302 * since counter may still in process.
6304 rte_spinlock_lock(&age_info->aged_sl);
6305 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6306 rte_spinlock_unlock(&age_info->aged_sl);
6307 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6312 * Release a flow counter.
6315 * Pointer to the Ethernet device structure.
6316 * @param[in] counter
6317 * Index to the counter handler.
6320 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6322 struct mlx5_priv *priv = dev->data->dev_private;
6323 struct mlx5_flow_counter_pool *pool = NULL;
6324 struct mlx5_flow_counter *cnt;
6325 enum mlx5_counter_type cnt_type;
6329 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6331 if (pool->is_aged) {
6332 flow_dv_counter_remove_from_age(dev, counter, cnt);
6335 * If the counter action is shared by indirect action API,
6336 * the atomic function reduces its references counter.
6337 * If after the reduction the action is still referenced, the
6338 * function returns here and does not release it.
6339 * When the counter action is not shared by
6340 * indirect action API, shared info is 1 before the reduction,
6341 * so this condition is failed and function doesn't return here.
6343 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6349 * Put the counter back to list to be updated in none fallback mode.
6350 * Currently, we are using two list alternately, while one is in query,
6351 * add the freed counter to the other list based on the pool query_gen
6352 * value. After query finishes, add counter the list to the global
6353 * container counter list. The list changes while query starts. In
6354 * this case, lock will not be needed as query callback and release
6355 * function both operate with the different list.
6357 if (!priv->sh->cmng.counter_fallback) {
6358 rte_spinlock_lock(&pool->csl);
6359 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6360 rte_spinlock_unlock(&pool->csl);
6362 cnt->dcs_when_free = cnt->dcs_when_active;
6363 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6364 MLX5_COUNTER_TYPE_ORIGIN;
6365 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6366 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6368 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6373 * Resize a meter id container.
6376 * Pointer to the Ethernet device structure.
6379 * 0 on success, otherwise negative errno value and rte_errno is set.
6382 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6384 struct mlx5_priv *priv = dev->data->dev_private;
6385 struct mlx5_aso_mtr_pools_mng *pools_mng =
6386 &priv->sh->mtrmng->pools_mng;
6387 void *old_pools = pools_mng->pools;
6388 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6389 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6390 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6397 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6402 memcpy(pools, old_pools, pools_mng->n *
6403 sizeof(struct mlx5_aso_mtr_pool *));
6404 pools_mng->n = resize;
6405 pools_mng->pools = pools;
6407 mlx5_free(old_pools);
6412 * Prepare a new meter and/or a new meter pool.
6415 * Pointer to the Ethernet device structure.
6416 * @param[out] mtr_free
6417 * Where to put the pointer of a new meter.g.
6420 * The meter pool pointer and @mtr_free is set on success,
6421 * NULL otherwise and rte_errno is set.
6423 static struct mlx5_aso_mtr_pool *
6424 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6426 struct mlx5_priv *priv = dev->data->dev_private;
6427 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6428 struct mlx5_aso_mtr_pool *pool = NULL;
6429 struct mlx5_devx_obj *dcs = NULL;
6431 uint32_t log_obj_size;
6433 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6434 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6435 priv->sh->cdev->pdn,
6438 rte_errno = ENODATA;
6441 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6444 claim_zero(mlx5_devx_cmd_destroy(dcs));
6447 pool->devx_obj = dcs;
6448 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6449 pool->index = pools_mng->n_valid;
6450 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6452 claim_zero(mlx5_devx_cmd_destroy(dcs));
6453 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6456 pools_mng->pools[pool->index] = pool;
6457 pools_mng->n_valid++;
6458 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6459 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6460 pool->mtrs[i].offset = i;
6461 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6463 pool->mtrs[0].offset = 0;
6464 *mtr_free = &pool->mtrs[0];
6469 * Release a flow meter into pool.
6472 * Pointer to the Ethernet device structure.
6473 * @param[in] mtr_idx
6474 * Index to aso flow meter.
6477 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6479 struct mlx5_priv *priv = dev->data->dev_private;
6480 struct mlx5_aso_mtr_pools_mng *pools_mng =
6481 &priv->sh->mtrmng->pools_mng;
6482 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6484 MLX5_ASSERT(aso_mtr);
6485 rte_spinlock_lock(&pools_mng->mtrsl);
6486 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6487 aso_mtr->state = ASO_METER_FREE;
6488 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6489 rte_spinlock_unlock(&pools_mng->mtrsl);
6493 * Allocate a aso flow meter.
6496 * Pointer to the Ethernet device structure.
6499 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6502 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6504 struct mlx5_priv *priv = dev->data->dev_private;
6505 struct mlx5_aso_mtr *mtr_free = NULL;
6506 struct mlx5_aso_mtr_pools_mng *pools_mng =
6507 &priv->sh->mtrmng->pools_mng;
6508 struct mlx5_aso_mtr_pool *pool;
6509 uint32_t mtr_idx = 0;
6511 if (!priv->sh->devx) {
6512 rte_errno = ENOTSUP;
6515 /* Allocate the flow meter memory. */
6516 /* Get free meters from management. */
6517 rte_spinlock_lock(&pools_mng->mtrsl);
6518 mtr_free = LIST_FIRST(&pools_mng->meters);
6520 LIST_REMOVE(mtr_free, next);
6521 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6522 rte_spinlock_unlock(&pools_mng->mtrsl);
6525 mtr_free->state = ASO_METER_WAIT;
6526 rte_spinlock_unlock(&pools_mng->mtrsl);
6527 pool = container_of(mtr_free,
6528 struct mlx5_aso_mtr_pool,
6529 mtrs[mtr_free->offset]);
6530 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6531 if (!mtr_free->fm.meter_action) {
6532 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6533 struct rte_flow_error error;
6536 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6537 mtr_free->fm.meter_action =
6538 mlx5_glue->dv_create_flow_action_aso
6539 (priv->sh->rx_domain,
6540 pool->devx_obj->obj,
6542 (1 << MLX5_FLOW_COLOR_GREEN),
6544 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6545 if (!mtr_free->fm.meter_action) {
6546 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6554 * Verify the @p attributes will be correctly understood by the NIC and store
6555 * them in the @p flow if everything is correct.
6558 * Pointer to dev struct.
6559 * @param[in] attributes
6560 * Pointer to flow attributes
6561 * @param[in] external
6562 * This flow rule is created by request external to PMD.
6564 * Pointer to error structure.
6567 * - 0 on success and non root table.
6568 * - 1 on success and root table.
6569 * - a negative errno value otherwise and rte_errno is set.
6572 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6573 const struct mlx5_flow_tunnel *tunnel,
6574 const struct rte_flow_attr *attributes,
6575 const struct flow_grp_info *grp_info,
6576 struct rte_flow_error *error)
6578 struct mlx5_priv *priv = dev->data->dev_private;
6579 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6582 #ifndef HAVE_MLX5DV_DR
6583 RTE_SET_USED(tunnel);
6584 RTE_SET_USED(grp_info);
6585 if (attributes->group)
6586 return rte_flow_error_set(error, ENOTSUP,
6587 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6589 "groups are not supported");
6593 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6598 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6600 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6601 attributes->priority > lowest_priority)
6602 return rte_flow_error_set(error, ENOTSUP,
6603 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6605 "priority out of range");
6606 if (attributes->transfer) {
6607 if (!priv->config.dv_esw_en)
6608 return rte_flow_error_set
6610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6611 "E-Switch dr is not supported");
6612 if (!(priv->representor || priv->master))
6613 return rte_flow_error_set
6614 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6615 NULL, "E-Switch configuration can only be"
6616 " done by a master or a representor device");
6617 if (attributes->egress)
6618 return rte_flow_error_set
6620 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6621 "egress is not supported");
6623 if (!(attributes->egress ^ attributes->ingress))
6624 return rte_flow_error_set(error, ENOTSUP,
6625 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6626 "must specify exactly one of "
6627 "ingress or egress");
6632 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6633 int64_t pattern_flags, uint64_t l3_flags,
6634 uint64_t l4_flags, uint64_t ip4_flag,
6635 struct rte_flow_error *error)
6637 if (mask->l3_ok && !(pattern_flags & l3_flags))
6638 return rte_flow_error_set(error, EINVAL,
6639 RTE_FLOW_ERROR_TYPE_ITEM,
6640 NULL, "missing L3 protocol");
6642 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6643 return rte_flow_error_set(error, EINVAL,
6644 RTE_FLOW_ERROR_TYPE_ITEM,
6645 NULL, "missing IPv4 protocol");
6647 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6648 return rte_flow_error_set(error, EINVAL,
6649 RTE_FLOW_ERROR_TYPE_ITEM,
6650 NULL, "missing L4 protocol");
6656 flow_dv_validate_item_integrity_post(const struct
6657 rte_flow_item *integrity_items[2],
6658 int64_t pattern_flags,
6659 struct rte_flow_error *error)
6661 const struct rte_flow_item_integrity *mask;
6664 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6665 mask = (typeof(mask))integrity_items[0]->mask;
6666 ret = validate_integrity_bits(mask, pattern_flags,
6667 MLX5_FLOW_LAYER_OUTER_L3,
6668 MLX5_FLOW_LAYER_OUTER_L4,
6669 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6674 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6675 mask = (typeof(mask))integrity_items[1]->mask;
6676 ret = validate_integrity_bits(mask, pattern_flags,
6677 MLX5_FLOW_LAYER_INNER_L3,
6678 MLX5_FLOW_LAYER_INNER_L4,
6679 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6688 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6689 const struct rte_flow_item *integrity_item,
6690 uint64_t pattern_flags, uint64_t *last_item,
6691 const struct rte_flow_item *integrity_items[2],
6692 struct rte_flow_error *error)
6694 struct mlx5_priv *priv = dev->data->dev_private;
6695 const struct rte_flow_item_integrity *mask = (typeof(mask))
6696 integrity_item->mask;
6697 const struct rte_flow_item_integrity *spec = (typeof(spec))
6698 integrity_item->spec;
6700 if (!priv->config.hca_attr.pkt_integrity_match)
6701 return rte_flow_error_set(error, ENOTSUP,
6702 RTE_FLOW_ERROR_TYPE_ITEM,
6704 "packet integrity integrity_item not supported");
6706 return rte_flow_error_set(error, ENOTSUP,
6707 RTE_FLOW_ERROR_TYPE_ITEM,
6709 "no spec for integrity item");
6711 mask = &rte_flow_item_integrity_mask;
6712 if (!mlx5_validate_integrity_item(mask))
6713 return rte_flow_error_set(error, ENOTSUP,
6714 RTE_FLOW_ERROR_TYPE_ITEM,
6716 "unsupported integrity filter");
6717 if (spec->level > 1) {
6718 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6719 return rte_flow_error_set
6721 RTE_FLOW_ERROR_TYPE_ITEM,
6722 NULL, "multiple inner integrity items not supported");
6723 integrity_items[1] = integrity_item;
6724 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6726 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6727 return rte_flow_error_set
6729 RTE_FLOW_ERROR_TYPE_ITEM,
6730 NULL, "multiple outer integrity items not supported");
6731 integrity_items[0] = integrity_item;
6732 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6738 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6739 const struct rte_flow_item *item,
6740 uint64_t item_flags,
6741 uint64_t *last_item,
6743 struct rte_flow_error *error)
6745 const struct rte_flow_item_flex *flow_spec = item->spec;
6746 const struct rte_flow_item_flex *flow_mask = item->mask;
6747 struct mlx5_flex_item *flex;
6750 return rte_flow_error_set(error, EINVAL,
6751 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6752 "flex flow item spec cannot be NULL");
6754 return rte_flow_error_set(error, EINVAL,
6755 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6756 "flex flow item mask cannot be NULL");
6758 return rte_flow_error_set(error, ENOTSUP,
6759 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6760 "flex flow item last not supported");
6761 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6762 return rte_flow_error_set(error, EINVAL,
6763 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6764 "invalid flex flow item handle");
6765 flex = (struct mlx5_flex_item *)flow_spec->handle;
6766 switch (flex->tunnel_mode) {
6767 case FLEX_TUNNEL_MODE_SINGLE:
6769 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6770 rte_flow_error_set(error, EINVAL,
6771 RTE_FLOW_ERROR_TYPE_ITEM,
6772 NULL, "multiple flex items not supported");
6774 case FLEX_TUNNEL_MODE_OUTER:
6776 rte_flow_error_set(error, EINVAL,
6777 RTE_FLOW_ERROR_TYPE_ITEM,
6778 NULL, "inner flex item was not configured");
6779 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6780 rte_flow_error_set(error, ENOTSUP,
6781 RTE_FLOW_ERROR_TYPE_ITEM,
6782 NULL, "multiple flex items not supported");
6784 case FLEX_TUNNEL_MODE_INNER:
6786 rte_flow_error_set(error, EINVAL,
6787 RTE_FLOW_ERROR_TYPE_ITEM,
6788 NULL, "outer flex item was not configured");
6789 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6790 rte_flow_error_set(error, EINVAL,
6791 RTE_FLOW_ERROR_TYPE_ITEM,
6792 NULL, "multiple flex items not supported");
6794 case FLEX_TUNNEL_MODE_MULTI:
6795 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6796 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6797 rte_flow_error_set(error, EINVAL,
6798 RTE_FLOW_ERROR_TYPE_ITEM,
6799 NULL, "multiple flex items not supported");
6802 case FLEX_TUNNEL_MODE_TUNNEL:
6803 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6804 rte_flow_error_set(error, EINVAL,
6805 RTE_FLOW_ERROR_TYPE_ITEM,
6806 NULL, "multiple flex tunnel items not supported");
6809 rte_flow_error_set(error, EINVAL,
6810 RTE_FLOW_ERROR_TYPE_ITEM,
6811 NULL, "invalid flex item configuration");
6813 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6814 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6815 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6820 * Internal validation function. For validating both actions and items.
6823 * Pointer to the rte_eth_dev structure.
6825 * Pointer to the flow attributes.
6827 * Pointer to the list of items.
6828 * @param[in] actions
6829 * Pointer to the list of actions.
6830 * @param[in] external
6831 * This flow rule is created by request external to PMD.
6832 * @param[in] hairpin
6833 * Number of hairpin TX actions, 0 means classic flow.
6835 * Pointer to the error structure.
6838 * 0 on success, a negative errno value otherwise and rte_errno is set.
6841 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6842 const struct rte_flow_item items[],
6843 const struct rte_flow_action actions[],
6844 bool external, int hairpin, struct rte_flow_error *error)
6847 uint64_t action_flags = 0;
6848 uint64_t item_flags = 0;
6849 uint64_t last_item = 0;
6850 uint8_t next_protocol = 0xff;
6851 uint16_t ether_type = 0;
6853 uint8_t item_ipv6_proto = 0;
6854 int fdb_mirror_limit = 0;
6855 int modify_after_mirror = 0;
6856 const struct rte_flow_item *geneve_item = NULL;
6857 const struct rte_flow_item *gre_item = NULL;
6858 const struct rte_flow_item *gtp_item = NULL;
6859 const struct rte_flow_action_raw_decap *decap;
6860 const struct rte_flow_action_raw_encap *encap;
6861 const struct rte_flow_action_rss *rss = NULL;
6862 const struct rte_flow_action_rss *sample_rss = NULL;
6863 const struct rte_flow_action_count *sample_count = NULL;
6864 const struct rte_flow_item_tcp nic_tcp_mask = {
6867 .src_port = RTE_BE16(UINT16_MAX),
6868 .dst_port = RTE_BE16(UINT16_MAX),
6871 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6874 "\xff\xff\xff\xff\xff\xff\xff\xff"
6875 "\xff\xff\xff\xff\xff\xff\xff\xff",
6877 "\xff\xff\xff\xff\xff\xff\xff\xff"
6878 "\xff\xff\xff\xff\xff\xff\xff\xff",
6879 .vtc_flow = RTE_BE32(0xffffffff),
6885 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6889 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6893 .dummy[0] = 0xffffffff,
6896 struct mlx5_priv *priv = dev->data->dev_private;
6897 struct mlx5_dev_config *dev_conf = &priv->config;
6898 uint16_t queue_index = 0xFFFF;
6899 const struct rte_flow_item_vlan *vlan_m = NULL;
6900 uint32_t rw_act_num = 0;
6902 const struct mlx5_flow_tunnel *tunnel;
6903 enum mlx5_tof_rule_type tof_rule_type;
6904 struct flow_grp_info grp_info = {
6905 .external = !!external,
6906 .transfer = !!attr->transfer,
6907 .fdb_def_rule = !!priv->fdb_def_rule,
6908 .std_tbl_fix = true,
6910 const struct rte_eth_hairpin_conf *conf;
6911 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6912 const struct rte_flow_item *port_id_item = NULL;
6913 bool def_policy = false;
6914 uint16_t udp_dport = 0;
6918 tunnel = is_tunnel_offload_active(dev) ?
6919 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6921 if (!priv->config.dv_flow_en)
6922 return rte_flow_error_set
6924 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6925 NULL, "tunnel offload requires DV flow interface");
6926 if (priv->representor)
6927 return rte_flow_error_set
6929 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6930 NULL, "decap not supported for VF representor");
6931 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6932 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6933 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6934 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6935 MLX5_FLOW_ACTION_DECAP;
6936 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6937 (dev, attr, tunnel, tof_rule_type);
6939 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6942 is_root = (uint64_t)ret;
6943 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6944 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6945 int type = items->type;
6947 if (!mlx5_flow_os_item_supported(type))
6948 return rte_flow_error_set(error, ENOTSUP,
6949 RTE_FLOW_ERROR_TYPE_ITEM,
6950 NULL, "item not supported");
6952 case RTE_FLOW_ITEM_TYPE_VOID:
6954 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6955 ret = flow_dv_validate_item_port_id
6956 (dev, items, attr, item_flags, error);
6959 last_item = MLX5_FLOW_ITEM_PORT_ID;
6960 port_id_item = items;
6962 case RTE_FLOW_ITEM_TYPE_ETH:
6963 ret = mlx5_flow_validate_item_eth(items, item_flags,
6967 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6968 MLX5_FLOW_LAYER_OUTER_L2;
6969 if (items->mask != NULL && items->spec != NULL) {
6971 ((const struct rte_flow_item_eth *)
6974 ((const struct rte_flow_item_eth *)
6976 ether_type = rte_be_to_cpu_16(ether_type);
6981 case RTE_FLOW_ITEM_TYPE_VLAN:
6982 ret = flow_dv_validate_item_vlan(items, item_flags,
6986 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6987 MLX5_FLOW_LAYER_OUTER_VLAN;
6988 if (items->mask != NULL && items->spec != NULL) {
6990 ((const struct rte_flow_item_vlan *)
6991 items->spec)->inner_type;
6993 ((const struct rte_flow_item_vlan *)
6994 items->mask)->inner_type;
6995 ether_type = rte_be_to_cpu_16(ether_type);
6999 /* Store outer VLAN mask for of_push_vlan action. */
7001 vlan_m = items->mask;
7003 case RTE_FLOW_ITEM_TYPE_IPV4:
7004 mlx5_flow_tunnel_ip_check(items, next_protocol,
7005 &item_flags, &tunnel);
7006 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
7007 last_item, ether_type,
7011 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7012 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7013 if (items->mask != NULL &&
7014 ((const struct rte_flow_item_ipv4 *)
7015 items->mask)->hdr.next_proto_id) {
7017 ((const struct rte_flow_item_ipv4 *)
7018 (items->spec))->hdr.next_proto_id;
7020 ((const struct rte_flow_item_ipv4 *)
7021 (items->mask))->hdr.next_proto_id;
7023 /* Reset for inner layer. */
7024 next_protocol = 0xff;
7027 case RTE_FLOW_ITEM_TYPE_IPV6:
7028 mlx5_flow_tunnel_ip_check(items, next_protocol,
7029 &item_flags, &tunnel);
7030 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7037 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7038 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7039 if (items->mask != NULL &&
7040 ((const struct rte_flow_item_ipv6 *)
7041 items->mask)->hdr.proto) {
7043 ((const struct rte_flow_item_ipv6 *)
7044 items->spec)->hdr.proto;
7046 ((const struct rte_flow_item_ipv6 *)
7047 items->spec)->hdr.proto;
7049 ((const struct rte_flow_item_ipv6 *)
7050 items->mask)->hdr.proto;
7052 /* Reset for inner layer. */
7053 next_protocol = 0xff;
7056 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7057 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7062 last_item = tunnel ?
7063 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7064 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7065 if (items->mask != NULL &&
7066 ((const struct rte_flow_item_ipv6_frag_ext *)
7067 items->mask)->hdr.next_header) {
7069 ((const struct rte_flow_item_ipv6_frag_ext *)
7070 items->spec)->hdr.next_header;
7072 ((const struct rte_flow_item_ipv6_frag_ext *)
7073 items->mask)->hdr.next_header;
7075 /* Reset for inner layer. */
7076 next_protocol = 0xff;
7079 case RTE_FLOW_ITEM_TYPE_TCP:
7080 ret = mlx5_flow_validate_item_tcp
7087 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7088 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7090 case RTE_FLOW_ITEM_TYPE_UDP:
7091 ret = mlx5_flow_validate_item_udp(items, item_flags,
7094 const struct rte_flow_item_udp *spec = items->spec;
7095 const struct rte_flow_item_udp *mask = items->mask;
7097 mask = &rte_flow_item_udp_mask;
7099 udp_dport = rte_be_to_cpu_16
7100 (spec->hdr.dst_port &
7101 mask->hdr.dst_port);
7104 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7105 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7107 case RTE_FLOW_ITEM_TYPE_GRE:
7108 ret = mlx5_flow_validate_item_gre(items, item_flags,
7109 next_protocol, error);
7113 last_item = MLX5_FLOW_LAYER_GRE;
7115 case RTE_FLOW_ITEM_TYPE_NVGRE:
7116 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7121 last_item = MLX5_FLOW_LAYER_NVGRE;
7123 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7124 ret = mlx5_flow_validate_item_gre_key
7125 (items, item_flags, gre_item, error);
7128 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7130 case RTE_FLOW_ITEM_TYPE_VXLAN:
7131 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7136 last_item = MLX5_FLOW_LAYER_VXLAN;
7138 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7139 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7144 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7146 case RTE_FLOW_ITEM_TYPE_GENEVE:
7147 ret = mlx5_flow_validate_item_geneve(items,
7152 geneve_item = items;
7153 last_item = MLX5_FLOW_LAYER_GENEVE;
7155 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7156 ret = mlx5_flow_validate_item_geneve_opt(items,
7163 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7165 case RTE_FLOW_ITEM_TYPE_MPLS:
7166 ret = mlx5_flow_validate_item_mpls(dev, items,
7171 last_item = MLX5_FLOW_LAYER_MPLS;
7174 case RTE_FLOW_ITEM_TYPE_MARK:
7175 ret = flow_dv_validate_item_mark(dev, items, attr,
7179 last_item = MLX5_FLOW_ITEM_MARK;
7181 case RTE_FLOW_ITEM_TYPE_META:
7182 ret = flow_dv_validate_item_meta(dev, items, attr,
7186 last_item = MLX5_FLOW_ITEM_METADATA;
7188 case RTE_FLOW_ITEM_TYPE_ICMP:
7189 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7194 last_item = MLX5_FLOW_LAYER_ICMP;
7196 case RTE_FLOW_ITEM_TYPE_ICMP6:
7197 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7202 item_ipv6_proto = IPPROTO_ICMPV6;
7203 last_item = MLX5_FLOW_LAYER_ICMP6;
7205 case RTE_FLOW_ITEM_TYPE_TAG:
7206 ret = flow_dv_validate_item_tag(dev, items,
7210 last_item = MLX5_FLOW_ITEM_TAG;
7212 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7213 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7215 case RTE_FLOW_ITEM_TYPE_GTP:
7216 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7221 last_item = MLX5_FLOW_LAYER_GTP;
7223 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7224 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7229 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7231 case RTE_FLOW_ITEM_TYPE_ECPRI:
7232 /* Capacity will be checked in the translate stage. */
7233 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7240 last_item = MLX5_FLOW_LAYER_ECPRI;
7242 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7243 ret = flow_dv_validate_item_integrity(dev, items,
7251 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7252 ret = flow_dv_validate_item_aso_ct(dev, items,
7253 &item_flags, error);
7257 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7258 /* tunnel offload item was processed before
7259 * list it here as a supported type
7262 case RTE_FLOW_ITEM_TYPE_FLEX:
7263 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7265 tunnel != 0, error);
7270 return rte_flow_error_set(error, ENOTSUP,
7271 RTE_FLOW_ERROR_TYPE_ITEM,
7272 NULL, "item not supported");
7274 item_flags |= last_item;
7276 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7277 ret = flow_dv_validate_item_integrity_post(integrity_items,
7282 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7283 int type = actions->type;
7284 bool shared_count = false;
7286 if (!mlx5_flow_os_action_supported(type))
7287 return rte_flow_error_set(error, ENOTSUP,
7288 RTE_FLOW_ERROR_TYPE_ACTION,
7290 "action not supported");
7291 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7292 return rte_flow_error_set(error, ENOTSUP,
7293 RTE_FLOW_ERROR_TYPE_ACTION,
7294 actions, "too many actions");
7296 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7297 return rte_flow_error_set(error, ENOTSUP,
7298 RTE_FLOW_ERROR_TYPE_ACTION,
7299 NULL, "meter action with policy "
7300 "must be the last action");
7302 case RTE_FLOW_ACTION_TYPE_VOID:
7304 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7305 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7306 ret = flow_dv_validate_action_port_id(dev,
7313 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7316 case RTE_FLOW_ACTION_TYPE_FLAG:
7317 ret = flow_dv_validate_action_flag(dev, action_flags,
7321 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7322 /* Count all modify-header actions as one. */
7323 if (!(action_flags &
7324 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7326 action_flags |= MLX5_FLOW_ACTION_FLAG |
7327 MLX5_FLOW_ACTION_MARK_EXT;
7328 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7329 modify_after_mirror = 1;
7332 action_flags |= MLX5_FLOW_ACTION_FLAG;
7335 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7337 case RTE_FLOW_ACTION_TYPE_MARK:
7338 ret = flow_dv_validate_action_mark(dev, actions,
7343 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7344 /* Count all modify-header actions as one. */
7345 if (!(action_flags &
7346 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7348 action_flags |= MLX5_FLOW_ACTION_MARK |
7349 MLX5_FLOW_ACTION_MARK_EXT;
7350 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7351 modify_after_mirror = 1;
7353 action_flags |= MLX5_FLOW_ACTION_MARK;
7356 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7358 case RTE_FLOW_ACTION_TYPE_SET_META:
7359 ret = flow_dv_validate_action_set_meta(dev, actions,
7364 /* Count all modify-header actions as one action. */
7365 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7367 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7368 modify_after_mirror = 1;
7369 action_flags |= MLX5_FLOW_ACTION_SET_META;
7370 rw_act_num += MLX5_ACT_NUM_SET_META;
7372 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7373 ret = flow_dv_validate_action_set_tag(dev, actions,
7378 /* Count all modify-header actions as one action. */
7379 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7381 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7382 modify_after_mirror = 1;
7383 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7384 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7386 case RTE_FLOW_ACTION_TYPE_DROP:
7387 ret = mlx5_flow_validate_action_drop(action_flags,
7391 action_flags |= MLX5_FLOW_ACTION_DROP;
7394 case RTE_FLOW_ACTION_TYPE_QUEUE:
7395 ret = mlx5_flow_validate_action_queue(actions,
7400 queue_index = ((const struct rte_flow_action_queue *)
7401 (actions->conf))->index;
7402 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7405 case RTE_FLOW_ACTION_TYPE_RSS:
7406 rss = actions->conf;
7407 ret = mlx5_flow_validate_action_rss(actions,
7413 if (rss && sample_rss &&
7414 (sample_rss->level != rss->level ||
7415 sample_rss->types != rss->types))
7416 return rte_flow_error_set(error, ENOTSUP,
7417 RTE_FLOW_ERROR_TYPE_ACTION,
7419 "Can't use the different RSS types "
7420 "or level in the same flow");
7421 if (rss != NULL && rss->queue_num)
7422 queue_index = rss->queue[0];
7423 action_flags |= MLX5_FLOW_ACTION_RSS;
7426 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7428 mlx5_flow_validate_action_default_miss(action_flags,
7432 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7435 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7436 shared_count = true;
7438 case RTE_FLOW_ACTION_TYPE_COUNT:
7439 ret = flow_dv_validate_action_count(dev, shared_count,
7444 action_flags |= MLX5_FLOW_ACTION_COUNT;
7447 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7448 if (flow_dv_validate_action_pop_vlan(dev,
7454 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7455 modify_after_mirror = 1;
7456 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7459 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7460 ret = flow_dv_validate_action_push_vlan(dev,
7467 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7468 modify_after_mirror = 1;
7469 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7472 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7473 ret = flow_dv_validate_action_set_vlan_pcp
7474 (action_flags, actions, error);
7477 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7478 modify_after_mirror = 1;
7479 /* Count PCP with push_vlan command. */
7480 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7482 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7483 ret = flow_dv_validate_action_set_vlan_vid
7484 (item_flags, action_flags,
7488 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7489 modify_after_mirror = 1;
7490 /* Count VID with push_vlan command. */
7491 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7492 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7494 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7495 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7496 ret = flow_dv_validate_action_l2_encap(dev,
7502 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7505 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7506 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7507 ret = flow_dv_validate_action_decap(dev, action_flags,
7508 actions, item_flags,
7512 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7513 modify_after_mirror = 1;
7514 action_flags |= MLX5_FLOW_ACTION_DECAP;
7517 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7518 ret = flow_dv_validate_action_raw_encap_decap
7519 (dev, NULL, actions->conf, attr, &action_flags,
7520 &actions_n, actions, item_flags, error);
7524 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7525 decap = actions->conf;
7526 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7528 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7532 encap = actions->conf;
7534 ret = flow_dv_validate_action_raw_encap_decap
7536 decap ? decap : &empty_decap, encap,
7537 attr, &action_flags, &actions_n,
7538 actions, item_flags, error);
7541 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7542 (action_flags & MLX5_FLOW_ACTION_DECAP))
7543 modify_after_mirror = 1;
7545 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7546 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7547 ret = flow_dv_validate_action_modify_mac(action_flags,
7553 /* Count all modify-header actions as one action. */
7554 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7556 action_flags |= actions->type ==
7557 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7558 MLX5_FLOW_ACTION_SET_MAC_SRC :
7559 MLX5_FLOW_ACTION_SET_MAC_DST;
7560 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7561 modify_after_mirror = 1;
7563 * Even if the source and destination MAC addresses have
7564 * overlap in the header with 4B alignment, the convert
7565 * function will handle them separately and 4 SW actions
7566 * will be created. And 2 actions will be added each
7567 * time no matter how many bytes of address will be set.
7569 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7571 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7572 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7573 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7579 /* Count all modify-header actions as one action. */
7580 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7582 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7583 modify_after_mirror = 1;
7584 action_flags |= actions->type ==
7585 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7586 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7587 MLX5_FLOW_ACTION_SET_IPV4_DST;
7588 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7590 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7591 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7592 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7598 if (item_ipv6_proto == IPPROTO_ICMPV6)
7599 return rte_flow_error_set(error, ENOTSUP,
7600 RTE_FLOW_ERROR_TYPE_ACTION,
7602 "Can't change header "
7603 "with ICMPv6 proto");
7604 /* Count all modify-header actions as one action. */
7605 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7607 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7608 modify_after_mirror = 1;
7609 action_flags |= actions->type ==
7610 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7611 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7612 MLX5_FLOW_ACTION_SET_IPV6_DST;
7613 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7615 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7616 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7617 ret = flow_dv_validate_action_modify_tp(action_flags,
7623 /* Count all modify-header actions as one action. */
7624 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7626 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7627 modify_after_mirror = 1;
7628 action_flags |= actions->type ==
7629 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7630 MLX5_FLOW_ACTION_SET_TP_SRC :
7631 MLX5_FLOW_ACTION_SET_TP_DST;
7632 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7634 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7635 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7636 ret = flow_dv_validate_action_modify_ttl(action_flags,
7642 /* Count all modify-header actions as one action. */
7643 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7645 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7646 modify_after_mirror = 1;
7647 action_flags |= actions->type ==
7648 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7649 MLX5_FLOW_ACTION_SET_TTL :
7650 MLX5_FLOW_ACTION_DEC_TTL;
7651 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7653 case RTE_FLOW_ACTION_TYPE_JUMP:
7654 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7660 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7662 return rte_flow_error_set(error, EINVAL,
7663 RTE_FLOW_ERROR_TYPE_ACTION,
7665 "sample and jump action combination is not supported");
7667 action_flags |= MLX5_FLOW_ACTION_JUMP;
7669 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7670 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7671 ret = flow_dv_validate_action_modify_tcp_seq
7678 /* Count all modify-header actions as one action. */
7679 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7681 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7682 modify_after_mirror = 1;
7683 action_flags |= actions->type ==
7684 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7685 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7686 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7687 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7689 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7690 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7691 ret = flow_dv_validate_action_modify_tcp_ack
7698 /* Count all modify-header actions as one action. */
7699 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7701 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7702 modify_after_mirror = 1;
7703 action_flags |= actions->type ==
7704 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7705 MLX5_FLOW_ACTION_INC_TCP_ACK :
7706 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7707 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7709 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7711 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7712 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7713 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7715 case RTE_FLOW_ACTION_TYPE_METER:
7716 ret = mlx5_flow_validate_action_meter(dev,
7725 action_flags |= MLX5_FLOW_ACTION_METER;
7728 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7730 /* Meter action will add one more TAG action. */
7731 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7733 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7734 if (!attr->transfer && !attr->group)
7735 return rte_flow_error_set(error, ENOTSUP,
7736 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7738 "Shared ASO age action is not supported for group 0");
7739 if (action_flags & MLX5_FLOW_ACTION_AGE)
7740 return rte_flow_error_set
7742 RTE_FLOW_ERROR_TYPE_ACTION,
7744 "duplicate age actions set");
7745 action_flags |= MLX5_FLOW_ACTION_AGE;
7748 case RTE_FLOW_ACTION_TYPE_AGE:
7749 ret = flow_dv_validate_action_age(action_flags,
7755 * Validate the regular AGE action (using counter)
7756 * mutual exclusion with share counter actions.
7758 if (!priv->sh->flow_hit_aso_en) {
7760 return rte_flow_error_set
7762 RTE_FLOW_ERROR_TYPE_ACTION,
7764 "old age and shared count combination is not supported");
7766 return rte_flow_error_set
7768 RTE_FLOW_ERROR_TYPE_ACTION,
7770 "old age action and count must be in the same sub flow");
7772 action_flags |= MLX5_FLOW_ACTION_AGE;
7775 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7776 ret = flow_dv_validate_action_modify_ipv4_dscp
7783 /* Count all modify-header actions as one action. */
7784 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7786 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7787 modify_after_mirror = 1;
7788 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7789 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7791 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7792 ret = flow_dv_validate_action_modify_ipv6_dscp
7799 /* Count all modify-header actions as one action. */
7800 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7802 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7803 modify_after_mirror = 1;
7804 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7805 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7807 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7808 ret = flow_dv_validate_action_sample(&action_flags,
7817 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7820 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7821 ret = flow_dv_validate_action_modify_field(dev,
7828 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7829 modify_after_mirror = 1;
7830 /* Count all modify-header actions as one action. */
7831 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7833 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7836 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7837 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7842 action_flags |= MLX5_FLOW_ACTION_CT;
7844 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7845 /* tunnel offload action was processed before
7846 * list it here as a supported type
7850 return rte_flow_error_set(error, ENOTSUP,
7851 RTE_FLOW_ERROR_TYPE_ACTION,
7853 "action not supported");
7857 * Validate actions in flow rules
7858 * - Explicit decap action is prohibited by the tunnel offload API.
7859 * - Drop action in tunnel steer rule is prohibited by the API.
7860 * - Application cannot use MARK action because it's value can mask
7861 * tunnel default miss notification.
7862 * - JUMP in tunnel match rule has no support in current PMD
7864 * - TAG & META are reserved for future uses.
7866 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7867 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7868 MLX5_FLOW_ACTION_MARK |
7869 MLX5_FLOW_ACTION_SET_TAG |
7870 MLX5_FLOW_ACTION_SET_META |
7871 MLX5_FLOW_ACTION_DROP;
7873 if (action_flags & bad_actions_mask)
7874 return rte_flow_error_set
7876 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7877 "Invalid RTE action in tunnel "
7879 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7880 return rte_flow_error_set
7882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7883 "tunnel set decap rule must terminate "
7886 return rte_flow_error_set
7888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7889 "tunnel flows for ingress traffic only");
7891 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7892 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7893 MLX5_FLOW_ACTION_MARK |
7894 MLX5_FLOW_ACTION_SET_TAG |
7895 MLX5_FLOW_ACTION_SET_META;
7897 if (action_flags & bad_actions_mask)
7898 return rte_flow_error_set
7900 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7901 "Invalid RTE action in tunnel "
7905 * Validate the drop action mutual exclusion with other actions.
7906 * Drop action is mutually-exclusive with any other action, except for
7908 * Drop action compatibility with tunnel offload was already validated.
7910 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7911 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7912 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7913 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7914 return rte_flow_error_set(error, EINVAL,
7915 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7916 "Drop action is mutually-exclusive "
7917 "with any other action, except for "
7919 /* Eswitch has few restrictions on using items and actions */
7920 if (attr->transfer) {
7921 if (!mlx5_flow_ext_mreg_supported(dev) &&
7922 action_flags & MLX5_FLOW_ACTION_FLAG)
7923 return rte_flow_error_set(error, ENOTSUP,
7924 RTE_FLOW_ERROR_TYPE_ACTION,
7926 "unsupported action FLAG");
7927 if (!mlx5_flow_ext_mreg_supported(dev) &&
7928 action_flags & MLX5_FLOW_ACTION_MARK)
7929 return rte_flow_error_set(error, ENOTSUP,
7930 RTE_FLOW_ERROR_TYPE_ACTION,
7932 "unsupported action MARK");
7933 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7934 return rte_flow_error_set(error, ENOTSUP,
7935 RTE_FLOW_ERROR_TYPE_ACTION,
7937 "unsupported action QUEUE");
7938 if (action_flags & MLX5_FLOW_ACTION_RSS)
7939 return rte_flow_error_set(error, ENOTSUP,
7940 RTE_FLOW_ERROR_TYPE_ACTION,
7942 "unsupported action RSS");
7943 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7944 return rte_flow_error_set(error, EINVAL,
7945 RTE_FLOW_ERROR_TYPE_ACTION,
7947 "no fate action is found");
7949 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7950 return rte_flow_error_set(error, EINVAL,
7951 RTE_FLOW_ERROR_TYPE_ACTION,
7953 "no fate action is found");
7956 * Continue validation for Xcap and VLAN actions.
7957 * If hairpin is working in explicit TX rule mode, there is no actions
7958 * splitting and the validation of hairpin ingress flow should be the
7959 * same as other standard flows.
7961 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7962 MLX5_FLOW_VLAN_ACTIONS)) &&
7963 (queue_index == 0xFFFF ||
7964 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7965 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7966 conf->tx_explicit != 0))) {
7967 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7968 MLX5_FLOW_XCAP_ACTIONS)
7969 return rte_flow_error_set(error, ENOTSUP,
7970 RTE_FLOW_ERROR_TYPE_ACTION,
7971 NULL, "encap and decap "
7972 "combination aren't supported");
7973 if (!attr->transfer && attr->ingress) {
7974 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7975 return rte_flow_error_set
7977 RTE_FLOW_ERROR_TYPE_ACTION,
7978 NULL, "encap is not supported"
7979 " for ingress traffic");
7980 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7981 return rte_flow_error_set
7983 RTE_FLOW_ERROR_TYPE_ACTION,
7984 NULL, "push VLAN action not "
7985 "supported for ingress");
7986 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7987 MLX5_FLOW_VLAN_ACTIONS)
7988 return rte_flow_error_set
7990 RTE_FLOW_ERROR_TYPE_ACTION,
7991 NULL, "no support for "
7992 "multiple VLAN actions");
7995 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7996 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7997 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7999 return rte_flow_error_set
8001 RTE_FLOW_ERROR_TYPE_ACTION,
8002 NULL, "fate action not supported for "
8003 "meter with policy");
8005 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
8006 return rte_flow_error_set
8008 RTE_FLOW_ERROR_TYPE_ACTION,
8009 NULL, "modify header action in egress "
8010 "cannot be done before meter action");
8011 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8012 return rte_flow_error_set
8014 RTE_FLOW_ERROR_TYPE_ACTION,
8015 NULL, "encap action in egress "
8016 "cannot be done before meter action");
8017 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8018 return rte_flow_error_set
8020 RTE_FLOW_ERROR_TYPE_ACTION,
8021 NULL, "push vlan action in egress "
8022 "cannot be done before meter action");
8026 * Hairpin flow will add one more TAG action in TX implicit mode.
8027 * In TX explicit mode, there will be no hairpin flow ID.
8030 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8031 /* extra metadata enabled: one more TAG action will be add. */
8032 if (dev_conf->dv_flow_en &&
8033 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8034 mlx5_flow_ext_mreg_supported(dev))
8035 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8037 flow_dv_modify_hdr_action_max(dev, is_root)) {
8038 return rte_flow_error_set(error, ENOTSUP,
8039 RTE_FLOW_ERROR_TYPE_ACTION,
8040 NULL, "too many header modify"
8041 " actions to support");
8043 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8044 if (fdb_mirror_limit && modify_after_mirror)
8045 return rte_flow_error_set(error, EINVAL,
8046 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8047 "sample before modify action is not supported");
8052 * Internal preparation function. Allocates the DV flow size,
8053 * this size is constant.
8056 * Pointer to the rte_eth_dev structure.
8058 * Pointer to the flow attributes.
8060 * Pointer to the list of items.
8061 * @param[in] actions
8062 * Pointer to the list of actions.
8064 * Pointer to the error structure.
8067 * Pointer to mlx5_flow object on success,
8068 * otherwise NULL and rte_errno is set.
8070 static struct mlx5_flow *
8071 flow_dv_prepare(struct rte_eth_dev *dev,
8072 const struct rte_flow_attr *attr __rte_unused,
8073 const struct rte_flow_item items[] __rte_unused,
8074 const struct rte_flow_action actions[] __rte_unused,
8075 struct rte_flow_error *error)
8077 uint32_t handle_idx = 0;
8078 struct mlx5_flow *dev_flow;
8079 struct mlx5_flow_handle *dev_handle;
8080 struct mlx5_priv *priv = dev->data->dev_private;
8081 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8084 wks->skip_matcher_reg = 0;
8086 wks->final_policy = NULL;
8087 /* In case of corrupting the memory. */
8088 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8089 rte_flow_error_set(error, ENOSPC,
8090 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8091 "not free temporary device flow");
8094 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8097 rte_flow_error_set(error, ENOMEM,
8098 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8099 "not enough memory to create flow handle");
8102 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8103 dev_flow = &wks->flows[wks->flow_idx++];
8104 memset(dev_flow, 0, sizeof(*dev_flow));
8105 dev_flow->handle = dev_handle;
8106 dev_flow->handle_idx = handle_idx;
8107 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8108 dev_flow->ingress = attr->ingress;
8109 dev_flow->dv.transfer = attr->transfer;
8113 #ifdef RTE_LIBRTE_MLX5_DEBUG
8115 * Sanity check for match mask and value. Similar to check_valid_spec() in
8116 * kernel driver. If unmasked bit is present in value, it returns failure.
8119 * pointer to match mask buffer.
8120 * @param match_value
8121 * pointer to match value buffer.
8124 * 0 if valid, -EINVAL otherwise.
8127 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8129 uint8_t *m = match_mask;
8130 uint8_t *v = match_value;
8133 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8136 "match_value differs from match_criteria"
8137 " %p[%u] != %p[%u]",
8138 match_value, i, match_mask, i);
8147 * Add match of ip_version.
8151 * @param[in] headers_v
8152 * Values header pointer.
8153 * @param[in] headers_m
8154 * Masks header pointer.
8155 * @param[in] ip_version
8156 * The IP version to set.
8159 flow_dv_set_match_ip_version(uint32_t group,
8165 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8167 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8169 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8170 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8175 * Add Ethernet item to matcher and to the value.
8177 * @param[in, out] matcher
8179 * @param[in, out] key
8180 * Flow matcher value.
8182 * Flow pattern to translate.
8184 * Item is inner pattern.
8187 flow_dv_translate_item_eth(void *matcher, void *key,
8188 const struct rte_flow_item *item, int inner,
8191 const struct rte_flow_item_eth *eth_m = item->mask;
8192 const struct rte_flow_item_eth *eth_v = item->spec;
8193 const struct rte_flow_item_eth nic_mask = {
8194 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8195 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8196 .type = RTE_BE16(0xffff),
8209 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8211 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8213 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8215 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8217 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8218 ð_m->dst, sizeof(eth_m->dst));
8219 /* The value must be in the range of the mask. */
8220 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8221 for (i = 0; i < sizeof(eth_m->dst); ++i)
8222 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8223 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8224 ð_m->src, sizeof(eth_m->src));
8225 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8226 /* The value must be in the range of the mask. */
8227 for (i = 0; i < sizeof(eth_m->dst); ++i)
8228 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8230 * HW supports match on one Ethertype, the Ethertype following the last
8231 * VLAN tag of the packet (see PRM).
8232 * Set match on ethertype only if ETH header is not followed by VLAN.
8233 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8234 * ethertype, and use ip_version field instead.
8235 * eCPRI over Ether layer will use type value 0xAEFE.
8237 if (eth_m->type == 0xFFFF) {
8238 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8239 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8240 switch (eth_v->type) {
8241 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8242 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8244 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8245 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8246 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8248 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8249 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8251 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8252 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8258 if (eth_m->has_vlan) {
8259 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8260 if (eth_v->has_vlan) {
8262 * Here, when also has_more_vlan field in VLAN item is
8263 * not set, only single-tagged packets will be matched.
8265 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8269 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8270 rte_be_to_cpu_16(eth_m->type));
8271 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8272 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8276 * Add VLAN item to matcher and to the value.
8278 * @param[in, out] dev_flow
8280 * @param[in, out] matcher
8282 * @param[in, out] key
8283 * Flow matcher value.
8285 * Flow pattern to translate.
8287 * Item is inner pattern.
8290 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8291 void *matcher, void *key,
8292 const struct rte_flow_item *item,
8293 int inner, uint32_t group)
8295 const struct rte_flow_item_vlan *vlan_m = item->mask;
8296 const struct rte_flow_item_vlan *vlan_v = item->spec;
8303 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8305 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8307 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8309 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8311 * This is workaround, masks are not supported,
8312 * and pre-validated.
8315 dev_flow->handle->vf_vlan.tag =
8316 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8319 * When VLAN item exists in flow, mark packet as tagged,
8320 * even if TCI is not specified.
8322 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8323 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8329 vlan_m = &rte_flow_item_vlan_mask;
8330 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8331 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8332 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8333 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8334 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8335 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8336 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8337 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8339 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8340 * ethertype, and use ip_version field instead.
8342 if (vlan_m->inner_type == 0xFFFF) {
8343 switch (vlan_v->inner_type) {
8344 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8345 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8346 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8347 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8349 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8350 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8352 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8353 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8359 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8360 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8361 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8362 /* Only one vlan_tag bit can be set. */
8363 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8366 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8367 rte_be_to_cpu_16(vlan_m->inner_type));
8368 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8369 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8373 * Add IPV4 item to matcher and to the value.
8375 * @param[in, out] matcher
8377 * @param[in, out] key
8378 * Flow matcher value.
8380 * Flow pattern to translate.
8382 * Item is inner pattern.
8384 * The group to insert the rule.
8387 flow_dv_translate_item_ipv4(void *matcher, void *key,
8388 const struct rte_flow_item *item,
8389 int inner, uint32_t group)
8391 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8392 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8393 const struct rte_flow_item_ipv4 nic_mask = {
8395 .src_addr = RTE_BE32(0xffffffff),
8396 .dst_addr = RTE_BE32(0xffffffff),
8397 .type_of_service = 0xff,
8398 .next_proto_id = 0xff,
8399 .time_to_live = 0xff,
8406 uint8_t tos, ihl_m, ihl_v;
8409 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8411 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8413 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8415 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8417 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8422 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8423 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8424 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8425 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8426 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8427 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8428 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8429 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8430 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8431 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8432 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8433 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8434 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8435 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8436 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8437 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8438 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8439 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8440 ipv4_m->hdr.type_of_service);
8441 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8442 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8443 ipv4_m->hdr.type_of_service >> 2);
8444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8445 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8446 ipv4_m->hdr.next_proto_id);
8447 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8448 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8449 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8450 ipv4_m->hdr.time_to_live);
8451 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8452 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8453 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8454 !!(ipv4_m->hdr.fragment_offset));
8455 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8456 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8460 * Add IPV6 item to matcher and to the value.
8462 * @param[in, out] matcher
8464 * @param[in, out] key
8465 * Flow matcher value.
8467 * Flow pattern to translate.
8469 * Item is inner pattern.
8471 * The group to insert the rule.
8474 flow_dv_translate_item_ipv6(void *matcher, void *key,
8475 const struct rte_flow_item *item,
8476 int inner, uint32_t group)
8478 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8479 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8480 const struct rte_flow_item_ipv6 nic_mask = {
8483 "\xff\xff\xff\xff\xff\xff\xff\xff"
8484 "\xff\xff\xff\xff\xff\xff\xff\xff",
8486 "\xff\xff\xff\xff\xff\xff\xff\xff"
8487 "\xff\xff\xff\xff\xff\xff\xff\xff",
8488 .vtc_flow = RTE_BE32(0xffffffff),
8495 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8496 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8505 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8507 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8509 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8511 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8513 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8518 size = sizeof(ipv6_m->hdr.dst_addr);
8519 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8520 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8521 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8522 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8523 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8524 for (i = 0; i < size; ++i)
8525 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8526 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8527 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8528 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8529 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8530 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8531 for (i = 0; i < size; ++i)
8532 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8534 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8535 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8536 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8538 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8542 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8544 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8547 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8549 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8553 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8555 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8556 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8558 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8559 ipv6_m->hdr.hop_limits);
8560 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8561 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8562 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8563 !!(ipv6_m->has_frag_ext));
8564 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8565 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8569 * Add IPV6 fragment extension item to matcher and to the value.
8571 * @param[in, out] matcher
8573 * @param[in, out] key
8574 * Flow matcher value.
8576 * Flow pattern to translate.
8578 * Item is inner pattern.
8581 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8582 const struct rte_flow_item *item,
8585 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8586 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8587 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8589 .next_header = 0xff,
8590 .frag_data = RTE_BE16(0xffff),
8597 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8599 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8601 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8603 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8605 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8606 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8607 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8608 if (!ipv6_frag_ext_v)
8610 if (!ipv6_frag_ext_m)
8611 ipv6_frag_ext_m = &nic_mask;
8612 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8613 ipv6_frag_ext_m->hdr.next_header);
8614 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8615 ipv6_frag_ext_v->hdr.next_header &
8616 ipv6_frag_ext_m->hdr.next_header);
8620 * Add TCP item to matcher and to the value.
8622 * @param[in, out] matcher
8624 * @param[in, out] key
8625 * Flow matcher value.
8627 * Flow pattern to translate.
8629 * Item is inner pattern.
8632 flow_dv_translate_item_tcp(void *matcher, void *key,
8633 const struct rte_flow_item *item,
8636 const struct rte_flow_item_tcp *tcp_m = item->mask;
8637 const struct rte_flow_item_tcp *tcp_v = item->spec;
8642 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8644 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8646 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8648 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8650 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8651 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8655 tcp_m = &rte_flow_item_tcp_mask;
8656 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8657 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8659 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8660 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8661 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8663 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8664 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8665 tcp_m->hdr.tcp_flags);
8666 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8667 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8671 * Add UDP item to matcher and to the value.
8673 * @param[in, out] matcher
8675 * @param[in, out] key
8676 * Flow matcher value.
8678 * Flow pattern to translate.
8680 * Item is inner pattern.
8683 flow_dv_translate_item_udp(void *matcher, void *key,
8684 const struct rte_flow_item *item,
8687 const struct rte_flow_item_udp *udp_m = item->mask;
8688 const struct rte_flow_item_udp *udp_v = item->spec;
8693 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8695 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8697 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8699 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8701 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8706 udp_m = &rte_flow_item_udp_mask;
8707 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8708 rte_be_to_cpu_16(udp_m->hdr.src_port));
8709 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8710 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8711 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8712 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8713 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8714 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8718 * Add GRE optional Key item to matcher and to the value.
8720 * @param[in, out] matcher
8722 * @param[in, out] key
8723 * Flow matcher value.
8725 * Flow pattern to translate.
8727 * Item is inner pattern.
8730 flow_dv_translate_item_gre_key(void *matcher, void *key,
8731 const struct rte_flow_item *item)
8733 const rte_be32_t *key_m = item->mask;
8734 const rte_be32_t *key_v = item->spec;
8735 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8736 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8737 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8739 /* GRE K bit must be on and should already be validated */
8740 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8741 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8745 key_m = &gre_key_default_mask;
8746 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8747 rte_be_to_cpu_32(*key_m) >> 8);
8748 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8749 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8750 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8751 rte_be_to_cpu_32(*key_m) & 0xFF);
8752 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8753 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8757 * Add GRE item to matcher and to the value.
8759 * @param[in, out] matcher
8761 * @param[in, out] key
8762 * Flow matcher value.
8764 * Flow pattern to translate.
8765 * @param[in] pattern_flags
8766 * Accumulated pattern flags.
8769 flow_dv_translate_item_gre(void *matcher, void *key,
8770 const struct rte_flow_item *item,
8771 uint64_t pattern_flags)
8773 static const struct rte_flow_item_gre empty_gre = {0,};
8774 const struct rte_flow_item_gre *gre_m = item->mask;
8775 const struct rte_flow_item_gre *gre_v = item->spec;
8776 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8777 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8778 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8779 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8786 uint16_t s_present:1;
8787 uint16_t k_present:1;
8788 uint16_t rsvd_bit1:1;
8789 uint16_t c_present:1;
8793 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8794 uint16_t protocol_m, protocol_v;
8796 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8797 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8803 gre_m = &rte_flow_item_gre_mask;
8805 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8806 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8807 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8808 gre_crks_rsvd0_ver_m.c_present);
8809 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8810 gre_crks_rsvd0_ver_v.c_present &
8811 gre_crks_rsvd0_ver_m.c_present);
8812 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8813 gre_crks_rsvd0_ver_m.k_present);
8814 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8815 gre_crks_rsvd0_ver_v.k_present &
8816 gre_crks_rsvd0_ver_m.k_present);
8817 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8818 gre_crks_rsvd0_ver_m.s_present);
8819 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8820 gre_crks_rsvd0_ver_v.s_present &
8821 gre_crks_rsvd0_ver_m.s_present);
8822 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8823 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8825 /* Force next protocol to prevent matchers duplication */
8826 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8828 protocol_m = 0xFFFF;
8830 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8831 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8832 protocol_m & protocol_v);
8836 * Add NVGRE item to matcher and to the value.
8838 * @param[in, out] matcher
8840 * @param[in, out] key
8841 * Flow matcher value.
8843 * Flow pattern to translate.
8844 * @param[in] pattern_flags
8845 * Accumulated pattern flags.
8848 flow_dv_translate_item_nvgre(void *matcher, void *key,
8849 const struct rte_flow_item *item,
8850 unsigned long pattern_flags)
8852 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8853 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8854 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8855 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8856 const char *tni_flow_id_m;
8857 const char *tni_flow_id_v;
8863 /* For NVGRE, GRE header fields must be set with defined values. */
8864 const struct rte_flow_item_gre gre_spec = {
8865 .c_rsvd0_ver = RTE_BE16(0x2000),
8866 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8868 const struct rte_flow_item_gre gre_mask = {
8869 .c_rsvd0_ver = RTE_BE16(0xB000),
8870 .protocol = RTE_BE16(UINT16_MAX),
8872 const struct rte_flow_item gre_item = {
8877 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
8881 nvgre_m = &rte_flow_item_nvgre_mask;
8882 tni_flow_id_m = (const char *)nvgre_m->tni;
8883 tni_flow_id_v = (const char *)nvgre_v->tni;
8884 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8885 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8886 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8887 memcpy(gre_key_m, tni_flow_id_m, size);
8888 for (i = 0; i < size; ++i)
8889 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8893 * Add VXLAN item to matcher and to the value.
8896 * Pointer to the Ethernet device structure.
8898 * Flow rule attributes.
8899 * @param[in, out] matcher
8901 * @param[in, out] key
8902 * Flow matcher value.
8904 * Flow pattern to translate.
8906 * Item is inner pattern.
8909 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8910 const struct rte_flow_attr *attr,
8911 void *matcher, void *key,
8912 const struct rte_flow_item *item,
8915 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8916 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8921 uint32_t *tunnel_header_v;
8922 uint32_t *tunnel_header_m;
8924 struct mlx5_priv *priv = dev->data->dev_private;
8925 const struct rte_flow_item_vxlan nic_mask = {
8926 .vni = "\xff\xff\xff",
8931 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8933 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8935 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8937 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8939 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8940 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8941 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8942 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8943 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8945 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8949 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8950 (attr->group && !priv->sh->misc5_cap))
8951 vxlan_m = &rte_flow_item_vxlan_mask;
8953 vxlan_m = &nic_mask;
8955 if ((priv->sh->steering_format_version ==
8956 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8957 dport != MLX5_UDP_PORT_VXLAN) ||
8958 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8959 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8966 misc_m = MLX5_ADDR_OF(fte_match_param,
8967 matcher, misc_parameters);
8968 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8969 size = sizeof(vxlan_m->vni);
8970 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8971 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8972 memcpy(vni_m, vxlan_m->vni, size);
8973 for (i = 0; i < size; ++i)
8974 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8977 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8978 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8979 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8982 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8985 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8986 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8987 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8988 if (*tunnel_header_v)
8989 *tunnel_header_m = vxlan_m->vni[0] |
8990 vxlan_m->vni[1] << 8 |
8991 vxlan_m->vni[2] << 16;
8993 *tunnel_header_m = 0x0;
8994 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8995 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8996 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
9000 * Add VXLAN-GPE item to matcher and to the value.
9002 * @param[in, out] matcher
9004 * @param[in, out] key
9005 * Flow matcher value.
9007 * Flow pattern to translate.
9009 * Item is inner pattern.
9013 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9014 const struct rte_flow_item *item,
9015 const uint64_t pattern_flags)
9017 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9018 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9019 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9020 /* The item was validated to be on the outer side */
9021 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9022 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9024 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9026 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9028 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9030 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9031 int i, size = sizeof(vxlan_m->vni);
9032 uint8_t flags_m = 0xff;
9033 uint8_t flags_v = 0xc;
9034 uint8_t m_protocol, v_protocol;
9036 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9037 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9038 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9039 MLX5_UDP_PORT_VXLAN_GPE);
9042 vxlan_v = &dummy_vxlan_gpe_hdr;
9043 vxlan_m = &dummy_vxlan_gpe_hdr;
9046 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9048 memcpy(vni_m, vxlan_m->vni, size);
9049 for (i = 0; i < size; ++i)
9050 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9051 if (vxlan_m->flags) {
9052 flags_m = vxlan_m->flags;
9053 flags_v = vxlan_v->flags;
9055 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9056 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9057 m_protocol = vxlan_m->protocol;
9058 v_protocol = vxlan_v->protocol;
9060 /* Force next protocol to ensure next headers parsing. */
9061 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9062 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9063 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9064 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9065 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9066 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9070 MLX5_SET(fte_match_set_misc3, misc_m,
9071 outer_vxlan_gpe_next_protocol, m_protocol);
9072 MLX5_SET(fte_match_set_misc3, misc_v,
9073 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9077 * Add Geneve item to matcher and to the value.
9079 * @param[in, out] matcher
9081 * @param[in, out] key
9082 * Flow matcher value.
9084 * Flow pattern to translate.
9086 * Item is inner pattern.
9090 flow_dv_translate_item_geneve(void *matcher, void *key,
9091 const struct rte_flow_item *item,
9092 uint64_t pattern_flags)
9094 static const struct rte_flow_item_geneve empty_geneve = {0,};
9095 const struct rte_flow_item_geneve *geneve_m = item->mask;
9096 const struct rte_flow_item_geneve *geneve_v = item->spec;
9097 /* GENEVE flow item validation allows single tunnel item */
9098 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9099 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9100 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9101 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9104 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9105 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9106 size_t size = sizeof(geneve_m->vni), i;
9107 uint16_t protocol_m, protocol_v;
9109 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9110 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9111 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9112 MLX5_UDP_PORT_GENEVE);
9115 geneve_v = &empty_geneve;
9116 geneve_m = &empty_geneve;
9119 geneve_m = &rte_flow_item_geneve_mask;
9121 memcpy(vni_m, geneve_m->vni, size);
9122 for (i = 0; i < size; ++i)
9123 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9124 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9125 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9126 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9127 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9128 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9129 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9130 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9131 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9132 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9133 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9134 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9135 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9136 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9138 /* Force next protocol to prevent matchers duplication */
9139 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9141 protocol_m = 0xFFFF;
9143 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9144 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9145 protocol_m & protocol_v);
9149 * Create Geneve TLV option resource.
9151 * @param dev[in, out]
9152 * Pointer to rte_eth_dev structure.
9153 * @param[in, out] tag_be24
9154 * Tag value in big endian then R-shift 8.
9155 * @parm[in, out] dev_flow
9156 * Pointer to the dev_flow.
9158 * pointer to error structure.
9161 * 0 on success otherwise -errno and errno is set.
9165 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9166 const struct rte_flow_item *item,
9167 struct rte_flow_error *error)
9169 struct mlx5_priv *priv = dev->data->dev_private;
9170 struct mlx5_dev_ctx_shared *sh = priv->sh;
9171 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9172 sh->geneve_tlv_option_resource;
9173 struct mlx5_devx_obj *obj;
9174 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9179 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9180 if (geneve_opt_resource != NULL) {
9181 if (geneve_opt_resource->option_class ==
9182 geneve_opt_v->option_class &&
9183 geneve_opt_resource->option_type ==
9184 geneve_opt_v->option_type &&
9185 geneve_opt_resource->length ==
9186 geneve_opt_v->option_len) {
9187 /* We already have GENEVE TLV option obj allocated. */
9188 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9191 ret = rte_flow_error_set(error, ENOMEM,
9192 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9193 "Only one GENEVE TLV option supported");
9197 /* Create a GENEVE TLV object and resource. */
9198 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9199 geneve_opt_v->option_class,
9200 geneve_opt_v->option_type,
9201 geneve_opt_v->option_len);
9203 ret = rte_flow_error_set(error, ENODATA,
9204 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9205 "Failed to create GENEVE TLV Devx object");
9208 sh->geneve_tlv_option_resource =
9209 mlx5_malloc(MLX5_MEM_ZERO,
9210 sizeof(*geneve_opt_resource),
9212 if (!sh->geneve_tlv_option_resource) {
9213 claim_zero(mlx5_devx_cmd_destroy(obj));
9214 ret = rte_flow_error_set(error, ENOMEM,
9215 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9216 "GENEVE TLV object memory allocation failed");
9219 geneve_opt_resource = sh->geneve_tlv_option_resource;
9220 geneve_opt_resource->obj = obj;
9221 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9222 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9223 geneve_opt_resource->length = geneve_opt_v->option_len;
9224 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9228 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9233 * Add Geneve TLV option item to matcher.
9235 * @param[in, out] dev
9236 * Pointer to rte_eth_dev structure.
9237 * @param[in, out] matcher
9239 * @param[in, out] key
9240 * Flow matcher value.
9242 * Flow pattern to translate.
9244 * Pointer to error structure.
9247 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9248 void *key, const struct rte_flow_item *item,
9249 struct rte_flow_error *error)
9251 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9252 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9253 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9254 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9255 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9257 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9258 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9264 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9265 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9268 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9272 * Set the option length in GENEVE header if not requested.
9273 * The GENEVE TLV option length is expressed by the option length field
9274 * in the GENEVE header.
9275 * If the option length was not requested but the GENEVE TLV option item
9276 * is present we set the option length field implicitly.
9278 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9279 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9280 MLX5_GENEVE_OPTLEN_MASK);
9281 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9282 geneve_opt_v->option_len + 1);
9284 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9285 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9287 if (geneve_opt_v->data) {
9288 memcpy(&opt_data_key, geneve_opt_v->data,
9289 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9290 sizeof(opt_data_key)));
9291 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9292 sizeof(opt_data_key));
9293 memcpy(&opt_data_mask, geneve_opt_m->data,
9294 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9295 sizeof(opt_data_mask)));
9296 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9297 sizeof(opt_data_mask));
9298 MLX5_SET(fte_match_set_misc3, misc3_m,
9299 geneve_tlv_option_0_data,
9300 rte_be_to_cpu_32(opt_data_mask));
9301 MLX5_SET(fte_match_set_misc3, misc3_v,
9302 geneve_tlv_option_0_data,
9303 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9309 * Add MPLS item to matcher and to the value.
9311 * @param[in, out] matcher
9313 * @param[in, out] key
9314 * Flow matcher value.
9316 * Flow pattern to translate.
9317 * @param[in] prev_layer
9318 * The protocol layer indicated in previous item.
9320 * Item is inner pattern.
9323 flow_dv_translate_item_mpls(void *matcher, void *key,
9324 const struct rte_flow_item *item,
9325 uint64_t prev_layer,
9328 const uint32_t *in_mpls_m = item->mask;
9329 const uint32_t *in_mpls_v = item->spec;
9330 uint32_t *out_mpls_m = 0;
9331 uint32_t *out_mpls_v = 0;
9332 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9333 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9334 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9336 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9337 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9338 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9340 switch (prev_layer) {
9341 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9342 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9343 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9346 MLX5_UDP_PORT_MPLS);
9349 case MLX5_FLOW_LAYER_GRE:
9351 case MLX5_FLOW_LAYER_GRE_KEY:
9352 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9353 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9355 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9356 RTE_ETHER_TYPE_MPLS);
9365 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9366 switch (prev_layer) {
9367 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9369 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9370 outer_first_mpls_over_udp);
9372 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9373 outer_first_mpls_over_udp);
9375 case MLX5_FLOW_LAYER_GRE:
9377 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9378 outer_first_mpls_over_gre);
9380 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9381 outer_first_mpls_over_gre);
9384 /* Inner MPLS not over GRE is not supported. */
9387 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9391 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9397 if (out_mpls_m && out_mpls_v) {
9398 *out_mpls_m = *in_mpls_m;
9399 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9404 * Add metadata register item to matcher
9406 * @param[in, out] matcher
9408 * @param[in, out] key
9409 * Flow matcher value.
9410 * @param[in] reg_type
9411 * Type of device metadata register
9418 flow_dv_match_meta_reg(void *matcher, void *key,
9419 enum modify_reg reg_type,
9420 uint32_t data, uint32_t mask)
9423 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9425 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9431 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9432 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9435 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9436 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9440 * The metadata register C0 field might be divided into
9441 * source vport index and META item value, we should set
9442 * this field according to specified mask, not as whole one.
9444 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9446 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9447 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9450 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9453 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9454 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9457 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9458 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9461 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9462 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9465 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9466 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9469 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9470 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9473 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9474 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9477 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9478 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9487 * Add MARK item to matcher
9490 * The device to configure through.
9491 * @param[in, out] matcher
9493 * @param[in, out] key
9494 * Flow matcher value.
9496 * Flow pattern to translate.
9499 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9500 void *matcher, void *key,
9501 const struct rte_flow_item *item)
9503 struct mlx5_priv *priv = dev->data->dev_private;
9504 const struct rte_flow_item_mark *mark;
9508 mark = item->mask ? (const void *)item->mask :
9509 &rte_flow_item_mark_mask;
9510 mask = mark->id & priv->sh->dv_mark_mask;
9511 mark = (const void *)item->spec;
9513 value = mark->id & priv->sh->dv_mark_mask & mask;
9515 enum modify_reg reg;
9517 /* Get the metadata register index for the mark. */
9518 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9519 MLX5_ASSERT(reg > 0);
9520 if (reg == REG_C_0) {
9521 struct mlx5_priv *priv = dev->data->dev_private;
9522 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9523 uint32_t shl_c0 = rte_bsf32(msk_c0);
9529 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9534 * Add META item to matcher
9537 * The devich to configure through.
9538 * @param[in, out] matcher
9540 * @param[in, out] key
9541 * Flow matcher value.
9543 * Attributes of flow that includes this item.
9545 * Flow pattern to translate.
9548 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9549 void *matcher, void *key,
9550 const struct rte_flow_attr *attr,
9551 const struct rte_flow_item *item)
9553 const struct rte_flow_item_meta *meta_m;
9554 const struct rte_flow_item_meta *meta_v;
9556 meta_m = (const void *)item->mask;
9558 meta_m = &rte_flow_item_meta_mask;
9559 meta_v = (const void *)item->spec;
9562 uint32_t value = meta_v->data;
9563 uint32_t mask = meta_m->data;
9565 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9568 MLX5_ASSERT(reg != REG_NON);
9569 if (reg == REG_C_0) {
9570 struct mlx5_priv *priv = dev->data->dev_private;
9571 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9572 uint32_t shl_c0 = rte_bsf32(msk_c0);
9578 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9583 * Add vport metadata Reg C0 item to matcher
9585 * @param[in, out] matcher
9587 * @param[in, out] key
9588 * Flow matcher value.
9590 * Flow pattern to translate.
9593 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9594 uint32_t value, uint32_t mask)
9596 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9600 * Add tag item to matcher
9603 * The devich to configure through.
9604 * @param[in, out] matcher
9606 * @param[in, out] key
9607 * Flow matcher value.
9609 * Flow pattern to translate.
9612 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9613 void *matcher, void *key,
9614 const struct rte_flow_item *item)
9616 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9617 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9618 uint32_t mask, value;
9621 value = tag_v->data;
9622 mask = tag_m ? tag_m->data : UINT32_MAX;
9623 if (tag_v->id == REG_C_0) {
9624 struct mlx5_priv *priv = dev->data->dev_private;
9625 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9626 uint32_t shl_c0 = rte_bsf32(msk_c0);
9632 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9636 * Add TAG item to matcher
9639 * The devich to configure through.
9640 * @param[in, out] matcher
9642 * @param[in, out] key
9643 * Flow matcher value.
9645 * Flow pattern to translate.
9648 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9649 void *matcher, void *key,
9650 const struct rte_flow_item *item)
9652 const struct rte_flow_item_tag *tag_v = item->spec;
9653 const struct rte_flow_item_tag *tag_m = item->mask;
9654 enum modify_reg reg;
9657 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9658 /* Get the metadata register index for the tag. */
9659 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9660 MLX5_ASSERT(reg > 0);
9661 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9665 * Add source vport match to the specified matcher.
9667 * @param[in, out] matcher
9669 * @param[in, out] key
9670 * Flow matcher value.
9672 * Source vport value to match
9677 flow_dv_translate_item_source_vport(void *matcher, void *key,
9678 int16_t port, uint16_t mask)
9680 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9681 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9683 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9684 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9688 * Translate port-id item to eswitch match on port-id.
9691 * The devich to configure through.
9692 * @param[in, out] matcher
9694 * @param[in, out] key
9695 * Flow matcher value.
9697 * Flow pattern to translate.
9702 * 0 on success, a negative errno value otherwise.
9705 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9706 void *key, const struct rte_flow_item *item,
9707 const struct rte_flow_attr *attr)
9709 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9710 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9711 struct mlx5_priv *priv;
9714 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9715 flow_dv_translate_item_source_vport(matcher, key,
9716 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9719 mask = pid_m ? pid_m->id : 0xffff;
9720 id = pid_v ? pid_v->id : dev->data->port_id;
9721 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9725 * Translate to vport field or to metadata, depending on mode.
9726 * Kernel can use either misc.source_port or half of C0 metadata
9729 if (priv->vport_meta_mask) {
9731 * Provide the hint for SW steering library
9732 * to insert the flow into ingress domain and
9733 * save the extra vport match.
9735 if (mask == 0xffff && priv->vport_id == 0xffff &&
9736 priv->pf_bond < 0 && attr->transfer)
9737 flow_dv_translate_item_source_vport
9738 (matcher, key, priv->vport_id, mask);
9740 * We should always set the vport metadata register,
9741 * otherwise the SW steering library can drop
9742 * the rule if wire vport metadata value is not zero,
9743 * it depends on kernel configuration.
9745 flow_dv_translate_item_meta_vport(matcher, key,
9746 priv->vport_meta_tag,
9747 priv->vport_meta_mask);
9749 flow_dv_translate_item_source_vport(matcher, key,
9750 priv->vport_id, mask);
9756 * Add ICMP6 item to matcher and to the value.
9758 * @param[in, out] matcher
9760 * @param[in, out] key
9761 * Flow matcher value.
9763 * Flow pattern to translate.
9765 * Item is inner pattern.
9768 flow_dv_translate_item_icmp6(void *matcher, void *key,
9769 const struct rte_flow_item *item,
9772 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9773 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9776 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9778 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9780 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9782 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9784 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9786 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9788 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9789 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9793 icmp6_m = &rte_flow_item_icmp6_mask;
9794 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9795 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9796 icmp6_v->type & icmp6_m->type);
9797 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9798 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9799 icmp6_v->code & icmp6_m->code);
9803 * Add ICMP item to matcher and to the value.
9805 * @param[in, out] matcher
9807 * @param[in, out] key
9808 * Flow matcher value.
9810 * Flow pattern to translate.
9812 * Item is inner pattern.
9815 flow_dv_translate_item_icmp(void *matcher, void *key,
9816 const struct rte_flow_item *item,
9819 const struct rte_flow_item_icmp *icmp_m = item->mask;
9820 const struct rte_flow_item_icmp *icmp_v = item->spec;
9821 uint32_t icmp_header_data_m = 0;
9822 uint32_t icmp_header_data_v = 0;
9825 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9827 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9829 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9831 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9833 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9835 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9837 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9838 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9842 icmp_m = &rte_flow_item_icmp_mask;
9843 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9844 icmp_m->hdr.icmp_type);
9845 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9846 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9847 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9848 icmp_m->hdr.icmp_code);
9849 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9850 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9851 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9852 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9853 if (icmp_header_data_m) {
9854 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9855 icmp_header_data_v |=
9856 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9857 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9858 icmp_header_data_m);
9859 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9860 icmp_header_data_v & icmp_header_data_m);
9865 * Add GTP item to matcher and to the value.
9867 * @param[in, out] matcher
9869 * @param[in, out] key
9870 * Flow matcher value.
9872 * Flow pattern to translate.
9874 * Item is inner pattern.
9877 flow_dv_translate_item_gtp(void *matcher, void *key,
9878 const struct rte_flow_item *item, int inner)
9880 const struct rte_flow_item_gtp *gtp_m = item->mask;
9881 const struct rte_flow_item_gtp *gtp_v = item->spec;
9884 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9886 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9887 uint16_t dport = RTE_GTPU_UDP_PORT;
9890 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9892 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9894 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9896 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9898 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9899 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9900 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9905 gtp_m = &rte_flow_item_gtp_mask;
9906 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9907 gtp_m->v_pt_rsv_flags);
9908 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9909 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9910 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9911 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9912 gtp_v->msg_type & gtp_m->msg_type);
9913 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9914 rte_be_to_cpu_32(gtp_m->teid));
9915 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9916 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9920 * Add GTP PSC item to matcher.
9922 * @param[in, out] matcher
9924 * @param[in, out] key
9925 * Flow matcher value.
9927 * Flow pattern to translate.
9930 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9931 const struct rte_flow_item *item)
9933 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9934 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9935 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9937 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9943 uint8_t next_ext_header_type;
9948 /* Always set E-flag match on one, regardless of GTP item settings. */
9949 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9950 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9951 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9952 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9953 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9954 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9955 /*Set next extension header type. */
9958 dw_2.next_ext_header_type = 0xff;
9959 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9960 rte_cpu_to_be_32(dw_2.w32));
9963 dw_2.next_ext_header_type = 0x85;
9964 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9965 rte_cpu_to_be_32(dw_2.w32));
9977 /*Set extension header PDU type and Qos. */
9979 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9981 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9982 dw_0.qfi = gtp_psc_m->hdr.qfi;
9983 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9984 rte_cpu_to_be_32(dw_0.w32));
9986 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9987 gtp_psc_m->hdr.type);
9988 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9989 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9990 rte_cpu_to_be_32(dw_0.w32));
9996 * Add eCPRI item to matcher and to the value.
9999 * The devich to configure through.
10000 * @param[in, out] matcher
10002 * @param[in, out] key
10003 * Flow matcher value.
10005 * Flow pattern to translate.
10006 * @param[in] last_item
10010 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10011 void *key, const struct rte_flow_item *item,
10012 uint64_t last_item)
10014 struct mlx5_priv *priv = dev->data->dev_private;
10015 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10016 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10017 struct rte_ecpri_common_hdr common;
10018 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10019 misc_parameters_4);
10020 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10026 * In case of eCPRI over Ethernet, if EtherType is not specified,
10027 * match on eCPRI EtherType implicitly.
10029 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10030 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10032 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10033 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10034 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10035 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10036 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10037 *(uint16_t *)l2m = UINT16_MAX;
10038 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10044 ecpri_m = &rte_flow_item_ecpri_mask;
10046 * Maximal four DW samples are supported in a single matching now.
10047 * Two are used now for a eCPRI matching:
10048 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10049 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10052 if (!ecpri_m->hdr.common.u32)
10054 samples = priv->sh->ecpri_parser.ids;
10055 /* Need to take the whole DW as the mask to fill the entry. */
10056 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10057 prog_sample_field_value_0);
10058 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10059 prog_sample_field_value_0);
10060 /* Already big endian (network order) in the header. */
10061 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10062 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10063 /* Sample#0, used for matching type, offset 0. */
10064 MLX5_SET(fte_match_set_misc4, misc4_m,
10065 prog_sample_field_id_0, samples[0]);
10066 /* It makes no sense to set the sample ID in the mask field. */
10067 MLX5_SET(fte_match_set_misc4, misc4_v,
10068 prog_sample_field_id_0, samples[0]);
10070 * Checking if message body part needs to be matched.
10071 * Some wildcard rules only matching type field should be supported.
10073 if (ecpri_m->hdr.dummy[0]) {
10074 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10075 switch (common.type) {
10076 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10077 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10078 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10079 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10080 prog_sample_field_value_1);
10081 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10082 prog_sample_field_value_1);
10083 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10084 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10085 ecpri_m->hdr.dummy[0];
10086 /* Sample#1, to match message body, offset 4. */
10087 MLX5_SET(fte_match_set_misc4, misc4_m,
10088 prog_sample_field_id_1, samples[1]);
10089 MLX5_SET(fte_match_set_misc4, misc4_v,
10090 prog_sample_field_id_1, samples[1]);
10093 /* Others, do not match any sample ID. */
10100 * Add connection tracking status item to matcher
10103 * The devich to configure through.
10104 * @param[in, out] matcher
10106 * @param[in, out] key
10107 * Flow matcher value.
10109 * Flow pattern to translate.
10112 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10113 void *matcher, void *key,
10114 const struct rte_flow_item *item)
10116 uint32_t reg_value = 0;
10118 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10119 uint32_t reg_mask = 0;
10120 const struct rte_flow_item_conntrack *spec = item->spec;
10121 const struct rte_flow_item_conntrack *mask = item->mask;
10123 struct rte_flow_error error;
10126 mask = &rte_flow_item_conntrack_mask;
10127 if (!spec || !mask->flags)
10129 flags = spec->flags & mask->flags;
10130 /* The conflict should be checked in the validation. */
10131 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10132 reg_value |= MLX5_CT_SYNDROME_VALID;
10133 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10134 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10135 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10136 reg_value |= MLX5_CT_SYNDROME_INVALID;
10137 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10138 reg_value |= MLX5_CT_SYNDROME_TRAP;
10139 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10140 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10141 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10142 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10143 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10145 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10146 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10147 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10148 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10149 /* The REG_C_x value could be saved during startup. */
10150 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10151 if (reg_id == REG_NON)
10153 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10154 reg_value, reg_mask);
10158 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10159 const struct rte_flow_item *item,
10160 struct mlx5_flow *dev_flow, bool is_inner)
10162 const struct rte_flow_item_flex *spec =
10163 (const struct rte_flow_item_flex *)item->spec;
10164 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10166 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10169 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10170 /* Don't count both inner and outer flex items in one rule. */
10171 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10172 MLX5_ASSERT(false);
10173 dev_flow->handle->flex_item |= RTE_BIT32(index);
10175 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10178 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10180 #define HEADER_IS_ZERO(match_criteria, headers) \
10181 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10182 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10185 * Calculate flow matcher enable bitmap.
10187 * @param match_criteria
10188 * Pointer to flow matcher criteria.
10191 * Bitmap of enabled fields.
10194 flow_dv_matcher_enable(uint32_t *match_criteria)
10196 uint8_t match_criteria_enable;
10198 match_criteria_enable =
10199 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10200 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10201 match_criteria_enable |=
10202 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10203 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10204 match_criteria_enable |=
10205 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10206 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10207 match_criteria_enable |=
10208 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10209 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10210 match_criteria_enable |=
10211 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10212 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10213 match_criteria_enable |=
10214 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10215 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10216 match_criteria_enable |=
10217 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10218 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10219 return match_criteria_enable;
10223 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10226 * Check flow matching criteria first, subtract misc5/4 length if flow
10227 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10228 * misc5/4 are not supported, and matcher creation failure is expected
10229 * w/o subtraction. If misc5 is provided, misc4 must be counted in since
10230 * misc5 is right after misc4.
10232 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10233 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10234 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10235 if (!(match_criteria & (1 <<
10236 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10237 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10242 static struct mlx5_list_entry *
10243 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10244 struct mlx5_list_entry *entry, void *cb_ctx)
10246 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10247 struct mlx5_flow_dv_matcher *ref = ctx->data;
10248 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10249 typeof(*tbl), tbl);
10250 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10255 rte_flow_error_set(ctx->error, ENOMEM,
10256 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10257 "cannot create matcher");
10260 memcpy(resource, entry, sizeof(*resource));
10261 resource->tbl = &tbl->tbl;
10262 return &resource->entry;
10266 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10267 struct mlx5_list_entry *entry)
10272 struct mlx5_list_entry *
10273 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10275 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10276 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10277 struct rte_eth_dev *dev = ctx->dev;
10278 struct mlx5_flow_tbl_data_entry *tbl_data;
10279 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10280 struct rte_flow_error *error = ctx->error;
10281 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10282 struct mlx5_flow_tbl_resource *tbl;
10287 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10289 rte_flow_error_set(error, ENOMEM,
10290 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10292 "cannot allocate flow table data entry");
10295 tbl_data->idx = idx;
10296 tbl_data->tunnel = tt_prm->tunnel;
10297 tbl_data->group_id = tt_prm->group_id;
10298 tbl_data->external = !!tt_prm->external;
10299 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10300 tbl_data->is_egress = !!key.is_egress;
10301 tbl_data->is_transfer = !!key.is_fdb;
10302 tbl_data->dummy = !!key.dummy;
10303 tbl_data->level = key.level;
10304 tbl_data->id = key.id;
10305 tbl = &tbl_data->tbl;
10307 return &tbl_data->entry;
10309 domain = sh->fdb_domain;
10310 else if (key.is_egress)
10311 domain = sh->tx_domain;
10313 domain = sh->rx_domain;
10314 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10316 rte_flow_error_set(error, ENOMEM,
10317 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10318 NULL, "cannot create flow table object");
10319 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10322 if (key.level != 0) {
10323 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10324 (tbl->obj, &tbl_data->jump.action);
10326 rte_flow_error_set(error, ENOMEM,
10327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10329 "cannot create flow jump action");
10330 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10331 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10335 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10336 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10337 key.level, key.id);
10338 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10339 flow_dv_matcher_create_cb,
10340 flow_dv_matcher_match_cb,
10341 flow_dv_matcher_remove_cb,
10342 flow_dv_matcher_clone_cb,
10343 flow_dv_matcher_clone_free_cb);
10344 if (!tbl_data->matchers) {
10345 rte_flow_error_set(error, ENOMEM,
10346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10348 "cannot create tbl matcher list");
10349 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10350 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10351 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10354 return &tbl_data->entry;
10358 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10361 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10362 struct mlx5_flow_tbl_data_entry *tbl_data =
10363 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10364 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10366 return tbl_data->level != key.level ||
10367 tbl_data->id != key.id ||
10368 tbl_data->dummy != key.dummy ||
10369 tbl_data->is_transfer != !!key.is_fdb ||
10370 tbl_data->is_egress != !!key.is_egress;
10373 struct mlx5_list_entry *
10374 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10377 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10378 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10379 struct mlx5_flow_tbl_data_entry *tbl_data;
10380 struct rte_flow_error *error = ctx->error;
10383 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10385 rte_flow_error_set(error, ENOMEM,
10386 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10388 "cannot allocate flow table data entry");
10391 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10392 tbl_data->idx = idx;
10393 return &tbl_data->entry;
10397 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10399 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10400 struct mlx5_flow_tbl_data_entry *tbl_data =
10401 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10403 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10407 * Get a flow table.
10409 * @param[in, out] dev
10410 * Pointer to rte_eth_dev structure.
10411 * @param[in] table_level
10412 * Table level to use.
10413 * @param[in] egress
10414 * Direction of the table.
10415 * @param[in] transfer
10416 * E-Switch or NIC flow.
10418 * Dummy entry for dv API.
10419 * @param[in] table_id
10421 * @param[out] error
10422 * pointer to error structure.
10425 * Returns tables resource based on the index, NULL in case of failed.
10427 struct mlx5_flow_tbl_resource *
10428 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10429 uint32_t table_level, uint8_t egress,
10432 const struct mlx5_flow_tunnel *tunnel,
10433 uint32_t group_id, uint8_t dummy,
10435 struct rte_flow_error *error)
10437 struct mlx5_priv *priv = dev->data->dev_private;
10438 union mlx5_flow_tbl_key table_key = {
10440 .level = table_level,
10444 .is_fdb = !!transfer,
10445 .is_egress = !!egress,
10448 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10450 .group_id = group_id,
10451 .external = external,
10453 struct mlx5_flow_cb_ctx ctx = {
10456 .data = &table_key.v64,
10459 struct mlx5_list_entry *entry;
10460 struct mlx5_flow_tbl_data_entry *tbl_data;
10462 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10464 rte_flow_error_set(error, ENOMEM,
10465 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10466 "cannot get table");
10469 DRV_LOG(DEBUG, "table_level %u table_id %u "
10470 "tunnel %u group %u registered.",
10471 table_level, table_id,
10472 tunnel ? tunnel->tunnel_id : 0, group_id);
10473 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10474 return &tbl_data->tbl;
10478 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10480 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10481 struct mlx5_flow_tbl_data_entry *tbl_data =
10482 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10484 MLX5_ASSERT(entry && sh);
10485 if (tbl_data->jump.action)
10486 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10487 if (tbl_data->tbl.obj)
10488 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10489 if (tbl_data->tunnel_offload && tbl_data->external) {
10490 struct mlx5_list_entry *he;
10491 struct mlx5_hlist *tunnel_grp_hash;
10492 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10493 union tunnel_tbl_key tunnel_key = {
10494 .tunnel_id = tbl_data->tunnel ?
10495 tbl_data->tunnel->tunnel_id : 0,
10496 .group = tbl_data->group_id
10498 uint32_t table_level = tbl_data->level;
10499 struct mlx5_flow_cb_ctx ctx = {
10500 .data = (void *)&tunnel_key.val,
10503 tunnel_grp_hash = tbl_data->tunnel ?
10504 tbl_data->tunnel->groups :
10506 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10508 mlx5_hlist_unregister(tunnel_grp_hash, he);
10510 "table_level %u id %u tunnel %u group %u released.",
10514 tbl_data->tunnel->tunnel_id : 0,
10515 tbl_data->group_id);
10517 mlx5_list_destroy(tbl_data->matchers);
10518 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10522 * Release a flow table.
10525 * Pointer to device shared structure.
10527 * Table resource to be released.
10530 * Returns 0 if table was released, else return 1;
10533 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10534 struct mlx5_flow_tbl_resource *tbl)
10536 struct mlx5_flow_tbl_data_entry *tbl_data =
10537 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10541 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10545 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10546 struct mlx5_list_entry *entry, void *cb_ctx)
10548 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10549 struct mlx5_flow_dv_matcher *ref = ctx->data;
10550 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10553 return cur->crc != ref->crc ||
10554 cur->priority != ref->priority ||
10555 memcmp((const void *)cur->mask.buf,
10556 (const void *)ref->mask.buf, ref->mask.size);
10559 struct mlx5_list_entry *
10560 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10562 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10563 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10564 struct mlx5_flow_dv_matcher *ref = ctx->data;
10565 struct mlx5_flow_dv_matcher *resource;
10566 struct mlx5dv_flow_matcher_attr dv_attr = {
10567 .type = IBV_FLOW_ATTR_NORMAL,
10568 .match_mask = (void *)&ref->mask,
10570 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10571 typeof(*tbl), tbl);
10574 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10577 rte_flow_error_set(ctx->error, ENOMEM,
10578 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10579 "cannot create matcher");
10583 dv_attr.match_criteria_enable =
10584 flow_dv_matcher_enable(resource->mask.buf);
10585 __flow_dv_adjust_buf_size(&ref->mask.size,
10586 dv_attr.match_criteria_enable);
10587 dv_attr.priority = ref->priority;
10588 if (tbl->is_egress)
10589 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10590 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10592 &resource->matcher_object);
10594 mlx5_free(resource);
10595 rte_flow_error_set(ctx->error, ENOMEM,
10596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10597 "cannot create matcher");
10600 return &resource->entry;
10604 * Register the flow matcher.
10606 * @param[in, out] dev
10607 * Pointer to rte_eth_dev structure.
10608 * @param[in, out] matcher
10609 * Pointer to flow matcher.
10610 * @param[in, out] key
10611 * Pointer to flow table key.
10612 * @parm[in, out] dev_flow
10613 * Pointer to the dev_flow.
10614 * @param[out] error
10615 * pointer to error structure.
10618 * 0 on success otherwise -errno and errno is set.
10621 flow_dv_matcher_register(struct rte_eth_dev *dev,
10622 struct mlx5_flow_dv_matcher *ref,
10623 union mlx5_flow_tbl_key *key,
10624 struct mlx5_flow *dev_flow,
10625 const struct mlx5_flow_tunnel *tunnel,
10627 struct rte_flow_error *error)
10629 struct mlx5_list_entry *entry;
10630 struct mlx5_flow_dv_matcher *resource;
10631 struct mlx5_flow_tbl_resource *tbl;
10632 struct mlx5_flow_tbl_data_entry *tbl_data;
10633 struct mlx5_flow_cb_ctx ctx = {
10638 * tunnel offload API requires this registration for cases when
10639 * tunnel match rule was inserted before tunnel set rule.
10641 tbl = flow_dv_tbl_resource_get(dev, key->level,
10642 key->is_egress, key->is_fdb,
10643 dev_flow->external, tunnel,
10644 group_id, 0, key->id, error);
10646 return -rte_errno; /* No need to refill the error info */
10647 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10649 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10651 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10652 return rte_flow_error_set(error, ENOMEM,
10653 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10654 "cannot allocate ref memory");
10656 resource = container_of(entry, typeof(*resource), entry);
10657 dev_flow->handle->dvh.matcher = resource;
10661 struct mlx5_list_entry *
10662 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10664 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10665 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10666 struct mlx5_flow_dv_tag_resource *entry;
10670 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10672 rte_flow_error_set(ctx->error, ENOMEM,
10673 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10674 "cannot allocate resource memory");
10678 entry->tag_id = *(uint32_t *)(ctx->data);
10679 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10682 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10683 rte_flow_error_set(ctx->error, ENOMEM,
10684 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10685 NULL, "cannot create action");
10688 return &entry->entry;
10692 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10695 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10696 struct mlx5_flow_dv_tag_resource *tag =
10697 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10699 return *(uint32_t *)(ctx->data) != tag->tag_id;
10702 struct mlx5_list_entry *
10703 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10706 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10707 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10708 struct mlx5_flow_dv_tag_resource *entry;
10711 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10713 rte_flow_error_set(ctx->error, ENOMEM,
10714 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10715 "cannot allocate tag resource memory");
10718 memcpy(entry, oentry, sizeof(*entry));
10720 return &entry->entry;
10724 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10726 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10727 struct mlx5_flow_dv_tag_resource *tag =
10728 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10730 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10734 * Find existing tag resource or create and register a new one.
10736 * @param dev[in, out]
10737 * Pointer to rte_eth_dev structure.
10738 * @param[in, out] tag_be24
10739 * Tag value in big endian then R-shift 8.
10740 * @parm[in, out] dev_flow
10741 * Pointer to the dev_flow.
10742 * @param[out] error
10743 * pointer to error structure.
10746 * 0 on success otherwise -errno and errno is set.
10749 flow_dv_tag_resource_register
10750 (struct rte_eth_dev *dev,
10752 struct mlx5_flow *dev_flow,
10753 struct rte_flow_error *error)
10755 struct mlx5_priv *priv = dev->data->dev_private;
10756 struct mlx5_flow_dv_tag_resource *resource;
10757 struct mlx5_list_entry *entry;
10758 struct mlx5_flow_cb_ctx ctx = {
10762 struct mlx5_hlist *tag_table;
10764 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10766 MLX5_TAGS_HLIST_ARRAY_SIZE,
10767 false, false, priv->sh,
10768 flow_dv_tag_create_cb,
10769 flow_dv_tag_match_cb,
10770 flow_dv_tag_remove_cb,
10771 flow_dv_tag_clone_cb,
10772 flow_dv_tag_clone_free_cb);
10773 if (unlikely(!tag_table))
10775 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10777 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10779 dev_flow->handle->dvh.rix_tag = resource->idx;
10780 dev_flow->dv.tag_resource = resource;
10787 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10789 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10790 struct mlx5_flow_dv_tag_resource *tag =
10791 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10793 MLX5_ASSERT(tag && sh && tag->action);
10794 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10795 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10796 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10803 * Pointer to Ethernet device.
10808 * 1 while a reference on it exists, 0 when freed.
10811 flow_dv_tag_release(struct rte_eth_dev *dev,
10814 struct mlx5_priv *priv = dev->data->dev_private;
10815 struct mlx5_flow_dv_tag_resource *tag;
10817 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10820 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10821 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10822 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10826 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10829 * Pointer to rte_eth_dev structure.
10830 * @param[in] action
10831 * Pointer to action PORT_ID / REPRESENTED_PORT.
10832 * @param[out] dst_port_id
10833 * The target port ID.
10834 * @param[out] error
10835 * Pointer to the error structure.
10838 * 0 on success, a negative errno value otherwise and rte_errno is set.
10841 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10842 const struct rte_flow_action *action,
10843 uint32_t *dst_port_id,
10844 struct rte_flow_error *error)
10847 struct mlx5_priv *priv;
10849 switch (action->type) {
10850 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10851 const struct rte_flow_action_port_id *conf;
10853 conf = (const struct rte_flow_action_port_id *)action->conf;
10854 port = conf->original ? dev->data->port_id : conf->id;
10857 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10858 const struct rte_flow_action_ethdev *ethdev;
10860 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10861 port = ethdev->port_id;
10865 MLX5_ASSERT(false);
10866 return rte_flow_error_set(error, EINVAL,
10867 RTE_FLOW_ERROR_TYPE_ACTION, action,
10868 "unknown E-Switch action");
10871 priv = mlx5_port_to_eswitch_info(port, false);
10873 return rte_flow_error_set(error, -rte_errno,
10874 RTE_FLOW_ERROR_TYPE_ACTION,
10876 "No eswitch info was found for port");
10877 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10879 * This parameter is transferred to
10880 * mlx5dv_dr_action_create_dest_ib_port().
10882 *dst_port_id = priv->dev_port;
10885 * Legacy mode, no LAG configurations is supported.
10886 * This parameter is transferred to
10887 * mlx5dv_dr_action_create_dest_vport().
10889 *dst_port_id = priv->vport_id;
10895 * Create a counter with aging configuration.
10898 * Pointer to rte_eth_dev structure.
10899 * @param[in] dev_flow
10900 * Pointer to the mlx5_flow.
10901 * @param[out] count
10902 * Pointer to the counter action configuration.
10904 * Pointer to the aging action configuration.
10907 * Index to flow counter on success, 0 otherwise.
10910 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10911 struct mlx5_flow *dev_flow,
10912 const struct rte_flow_action_count *count
10914 const struct rte_flow_action_age *age)
10917 struct mlx5_age_param *age_param;
10919 counter = flow_dv_counter_alloc(dev, !!age);
10920 if (!counter || age == NULL)
10922 age_param = flow_dv_counter_idx_get_age(dev, counter);
10923 age_param->context = age->context ? age->context :
10924 (void *)(uintptr_t)(dev_flow->flow_idx);
10925 age_param->timeout = age->timeout;
10926 age_param->port_id = dev->data->port_id;
10927 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10928 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10933 * Add Tx queue matcher
10936 * Pointer to the dev struct.
10937 * @param[in, out] matcher
10939 * @param[in, out] key
10940 * Flow matcher value.
10942 * Flow pattern to translate.
10944 * Item is inner pattern.
10947 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10948 void *matcher, void *key,
10949 const struct rte_flow_item *item)
10951 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10952 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10954 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10956 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10957 struct mlx5_txq_ctrl *txq;
10958 uint32_t queue, mask;
10960 queue_m = (const void *)item->mask;
10961 queue_v = (const void *)item->spec;
10964 txq = mlx5_txq_get(dev, queue_v->queue);
10967 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10968 queue = txq->obj->sq->id;
10970 queue = txq->obj->sq_obj.sq->id;
10971 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10972 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10973 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10974 mlx5_txq_release(dev, queue_v->queue);
10978 * Set the hash fields according to the @p flow information.
10980 * @param[in] dev_flow
10981 * Pointer to the mlx5_flow.
10982 * @param[in] rss_desc
10983 * Pointer to the mlx5_flow_rss_desc.
10986 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10987 struct mlx5_flow_rss_desc *rss_desc)
10989 uint64_t items = dev_flow->handle->layers;
10991 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10993 dev_flow->hash_fields = 0;
10994 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10995 if (rss_desc->level >= 2)
10998 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10999 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
11000 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
11001 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11002 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
11003 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11004 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
11006 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
11008 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
11009 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
11010 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11011 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11012 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
11013 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11014 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
11016 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
11019 if (dev_flow->hash_fields == 0)
11021 * There is no match between the RSS types and the
11022 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11025 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11026 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
11027 if (rss_types & RTE_ETH_RSS_UDP) {
11028 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11029 dev_flow->hash_fields |=
11030 IBV_RX_HASH_SRC_PORT_UDP;
11031 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11032 dev_flow->hash_fields |=
11033 IBV_RX_HASH_DST_PORT_UDP;
11035 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
11037 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11038 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
11039 if (rss_types & RTE_ETH_RSS_TCP) {
11040 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11041 dev_flow->hash_fields |=
11042 IBV_RX_HASH_SRC_PORT_TCP;
11043 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11044 dev_flow->hash_fields |=
11045 IBV_RX_HASH_DST_PORT_TCP;
11047 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11051 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11055 * Prepare an Rx Hash queue.
11058 * Pointer to Ethernet device.
11059 * @param[in] dev_flow
11060 * Pointer to the mlx5_flow.
11061 * @param[in] rss_desc
11062 * Pointer to the mlx5_flow_rss_desc.
11063 * @param[out] hrxq_idx
11064 * Hash Rx queue index.
11067 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11069 static struct mlx5_hrxq *
11070 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11071 struct mlx5_flow *dev_flow,
11072 struct mlx5_flow_rss_desc *rss_desc,
11073 uint32_t *hrxq_idx)
11075 struct mlx5_priv *priv = dev->data->dev_private;
11076 struct mlx5_flow_handle *dh = dev_flow->handle;
11077 struct mlx5_hrxq *hrxq;
11079 MLX5_ASSERT(rss_desc->queue_num);
11080 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11081 rss_desc->hash_fields = dev_flow->hash_fields;
11082 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11083 rss_desc->shared_rss = 0;
11084 if (rss_desc->hash_fields == 0)
11085 rss_desc->queue_num = 1;
11086 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11089 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11095 * Release sample sub action resource.
11097 * @param[in, out] dev
11098 * Pointer to rte_eth_dev structure.
11099 * @param[in] act_res
11100 * Pointer to sample sub action resource.
11103 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11104 struct mlx5_flow_sub_actions_idx *act_res)
11106 if (act_res->rix_hrxq) {
11107 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11108 act_res->rix_hrxq = 0;
11110 if (act_res->rix_encap_decap) {
11111 flow_dv_encap_decap_resource_release(dev,
11112 act_res->rix_encap_decap);
11113 act_res->rix_encap_decap = 0;
11115 if (act_res->rix_port_id_action) {
11116 flow_dv_port_id_action_resource_release(dev,
11117 act_res->rix_port_id_action);
11118 act_res->rix_port_id_action = 0;
11120 if (act_res->rix_tag) {
11121 flow_dv_tag_release(dev, act_res->rix_tag);
11122 act_res->rix_tag = 0;
11124 if (act_res->rix_jump) {
11125 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11126 act_res->rix_jump = 0;
11131 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11132 struct mlx5_list_entry *entry, void *cb_ctx)
11134 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11135 struct rte_eth_dev *dev = ctx->dev;
11136 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11137 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11141 if (ctx_resource->ratio == resource->ratio &&
11142 ctx_resource->ft_type == resource->ft_type &&
11143 ctx_resource->ft_id == resource->ft_id &&
11144 ctx_resource->set_action == resource->set_action &&
11145 !memcmp((void *)&ctx_resource->sample_act,
11146 (void *)&resource->sample_act,
11147 sizeof(struct mlx5_flow_sub_actions_list))) {
11149 * Existing sample action should release the prepared
11150 * sub-actions reference counter.
11152 flow_dv_sample_sub_actions_release(dev,
11153 &ctx_resource->sample_idx);
11159 struct mlx5_list_entry *
11160 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11162 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11163 struct rte_eth_dev *dev = ctx->dev;
11164 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11165 void **sample_dv_actions = ctx_resource->sub_actions;
11166 struct mlx5_flow_dv_sample_resource *resource;
11167 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11168 struct mlx5_priv *priv = dev->data->dev_private;
11169 struct mlx5_dev_ctx_shared *sh = priv->sh;
11170 struct mlx5_flow_tbl_resource *tbl;
11172 const uint32_t next_ft_step = 1;
11173 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11174 uint8_t is_egress = 0;
11175 uint8_t is_transfer = 0;
11176 struct rte_flow_error *error = ctx->error;
11178 /* Register new sample resource. */
11179 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11181 rte_flow_error_set(error, ENOMEM,
11182 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11184 "cannot allocate resource memory");
11187 *resource = *ctx_resource;
11188 /* Create normal path table level */
11189 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11191 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11193 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11194 is_egress, is_transfer,
11195 true, NULL, 0, 0, 0, error);
11197 rte_flow_error_set(error, ENOMEM,
11198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11200 "fail to create normal path table "
11204 resource->normal_path_tbl = tbl;
11205 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11206 if (!sh->default_miss_action) {
11207 rte_flow_error_set(error, ENOMEM,
11208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11210 "default miss action was not "
11214 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11215 sh->default_miss_action;
11217 /* Create a DR sample action */
11218 sampler_attr.sample_ratio = resource->ratio;
11219 sampler_attr.default_next_table = tbl->obj;
11220 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11221 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11222 &sample_dv_actions[0];
11223 sampler_attr.action = resource->set_action;
11224 if (mlx5_os_flow_dr_create_flow_action_sampler
11225 (&sampler_attr, &resource->verbs_action)) {
11226 rte_flow_error_set(error, ENOMEM,
11227 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11228 NULL, "cannot create sample action");
11231 resource->idx = idx;
11232 resource->dev = dev;
11233 return &resource->entry;
11235 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11236 flow_dv_sample_sub_actions_release(dev,
11237 &resource->sample_idx);
11238 if (resource->normal_path_tbl)
11239 flow_dv_tbl_resource_release(MLX5_SH(dev),
11240 resource->normal_path_tbl);
11241 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11246 struct mlx5_list_entry *
11247 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11248 struct mlx5_list_entry *entry __rte_unused,
11251 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11252 struct rte_eth_dev *dev = ctx->dev;
11253 struct mlx5_flow_dv_sample_resource *resource;
11254 struct mlx5_priv *priv = dev->data->dev_private;
11255 struct mlx5_dev_ctx_shared *sh = priv->sh;
11258 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11260 rte_flow_error_set(ctx->error, ENOMEM,
11261 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11263 "cannot allocate resource memory");
11266 memcpy(resource, entry, sizeof(*resource));
11267 resource->idx = idx;
11268 resource->dev = dev;
11269 return &resource->entry;
11273 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11274 struct mlx5_list_entry *entry)
11276 struct mlx5_flow_dv_sample_resource *resource =
11277 container_of(entry, typeof(*resource), entry);
11278 struct rte_eth_dev *dev = resource->dev;
11279 struct mlx5_priv *priv = dev->data->dev_private;
11281 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11285 * Find existing sample resource or create and register a new one.
11287 * @param[in, out] dev
11288 * Pointer to rte_eth_dev structure.
11290 * Pointer to sample resource reference.
11291 * @parm[in, out] dev_flow
11292 * Pointer to the dev_flow.
11293 * @param[out] error
11294 * pointer to error structure.
11297 * 0 on success otherwise -errno and errno is set.
11300 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11301 struct mlx5_flow_dv_sample_resource *ref,
11302 struct mlx5_flow *dev_flow,
11303 struct rte_flow_error *error)
11305 struct mlx5_flow_dv_sample_resource *resource;
11306 struct mlx5_list_entry *entry;
11307 struct mlx5_priv *priv = dev->data->dev_private;
11308 struct mlx5_flow_cb_ctx ctx = {
11314 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11317 resource = container_of(entry, typeof(*resource), entry);
11318 dev_flow->handle->dvh.rix_sample = resource->idx;
11319 dev_flow->dv.sample_res = resource;
11324 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11325 struct mlx5_list_entry *entry, void *cb_ctx)
11327 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11328 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11329 struct rte_eth_dev *dev = ctx->dev;
11330 struct mlx5_flow_dv_dest_array_resource *resource =
11331 container_of(entry, typeof(*resource), entry);
11334 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11335 ctx_resource->ft_type == resource->ft_type &&
11336 !memcmp((void *)resource->sample_act,
11337 (void *)ctx_resource->sample_act,
11338 (ctx_resource->num_of_dest *
11339 sizeof(struct mlx5_flow_sub_actions_list)))) {
11341 * Existing sample action should release the prepared
11342 * sub-actions reference counter.
11344 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11345 flow_dv_sample_sub_actions_release(dev,
11346 &ctx_resource->sample_idx[idx]);
11352 struct mlx5_list_entry *
11353 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11355 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11356 struct rte_eth_dev *dev = ctx->dev;
11357 struct mlx5_flow_dv_dest_array_resource *resource;
11358 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11359 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11360 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11361 struct mlx5_priv *priv = dev->data->dev_private;
11362 struct mlx5_dev_ctx_shared *sh = priv->sh;
11363 struct mlx5_flow_sub_actions_list *sample_act;
11364 struct mlx5dv_dr_domain *domain;
11365 uint32_t idx = 0, res_idx = 0;
11366 struct rte_flow_error *error = ctx->error;
11367 uint64_t action_flags;
11370 /* Register new destination array resource. */
11371 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11374 rte_flow_error_set(error, ENOMEM,
11375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11377 "cannot allocate resource memory");
11380 *resource = *ctx_resource;
11381 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11382 domain = sh->fdb_domain;
11383 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11384 domain = sh->rx_domain;
11386 domain = sh->tx_domain;
11387 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11388 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11389 mlx5_malloc(MLX5_MEM_ZERO,
11390 sizeof(struct mlx5dv_dr_action_dest_attr),
11392 if (!dest_attr[idx]) {
11393 rte_flow_error_set(error, ENOMEM,
11394 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11396 "cannot allocate resource memory");
11399 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11400 sample_act = &ctx_resource->sample_act[idx];
11401 action_flags = sample_act->action_flags;
11402 switch (action_flags) {
11403 case MLX5_FLOW_ACTION_QUEUE:
11404 dest_attr[idx]->dest = sample_act->dr_queue_action;
11406 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11407 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11408 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11409 dest_attr[idx]->dest_reformat->reformat =
11410 sample_act->dr_encap_action;
11411 dest_attr[idx]->dest_reformat->dest =
11412 sample_act->dr_port_id_action;
11414 case MLX5_FLOW_ACTION_PORT_ID:
11415 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11417 case MLX5_FLOW_ACTION_JUMP:
11418 dest_attr[idx]->dest = sample_act->dr_jump_action;
11421 rte_flow_error_set(error, EINVAL,
11422 RTE_FLOW_ERROR_TYPE_ACTION,
11424 "unsupported actions type");
11428 /* create a dest array action */
11429 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11431 resource->num_of_dest,
11433 &resource->action);
11435 rte_flow_error_set(error, ENOMEM,
11436 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11438 "cannot create destination array action");
11441 resource->idx = res_idx;
11442 resource->dev = dev;
11443 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11444 mlx5_free(dest_attr[idx]);
11445 return &resource->entry;
11447 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11448 flow_dv_sample_sub_actions_release(dev,
11449 &resource->sample_idx[idx]);
11450 if (dest_attr[idx])
11451 mlx5_free(dest_attr[idx]);
11453 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11457 struct mlx5_list_entry *
11458 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11459 struct mlx5_list_entry *entry __rte_unused,
11462 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11463 struct rte_eth_dev *dev = ctx->dev;
11464 struct mlx5_flow_dv_dest_array_resource *resource;
11465 struct mlx5_priv *priv = dev->data->dev_private;
11466 struct mlx5_dev_ctx_shared *sh = priv->sh;
11467 uint32_t res_idx = 0;
11468 struct rte_flow_error *error = ctx->error;
11470 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11473 rte_flow_error_set(error, ENOMEM,
11474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11476 "cannot allocate dest-array memory");
11479 memcpy(resource, entry, sizeof(*resource));
11480 resource->idx = res_idx;
11481 resource->dev = dev;
11482 return &resource->entry;
11486 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11487 struct mlx5_list_entry *entry)
11489 struct mlx5_flow_dv_dest_array_resource *resource =
11490 container_of(entry, typeof(*resource), entry);
11491 struct rte_eth_dev *dev = resource->dev;
11492 struct mlx5_priv *priv = dev->data->dev_private;
11494 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11498 * Find existing destination array resource or create and register a new one.
11500 * @param[in, out] dev
11501 * Pointer to rte_eth_dev structure.
11503 * Pointer to destination array resource reference.
11504 * @parm[in, out] dev_flow
11505 * Pointer to the dev_flow.
11506 * @param[out] error
11507 * pointer to error structure.
11510 * 0 on success otherwise -errno and errno is set.
11513 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11514 struct mlx5_flow_dv_dest_array_resource *ref,
11515 struct mlx5_flow *dev_flow,
11516 struct rte_flow_error *error)
11518 struct mlx5_flow_dv_dest_array_resource *resource;
11519 struct mlx5_priv *priv = dev->data->dev_private;
11520 struct mlx5_list_entry *entry;
11521 struct mlx5_flow_cb_ctx ctx = {
11527 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11530 resource = container_of(entry, typeof(*resource), entry);
11531 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11532 dev_flow->dv.dest_array_res = resource;
11537 * Convert Sample action to DV specification.
11540 * Pointer to rte_eth_dev structure.
11541 * @param[in] action
11542 * Pointer to sample action structure.
11543 * @param[in, out] dev_flow
11544 * Pointer to the mlx5_flow.
11546 * Pointer to the flow attributes.
11547 * @param[in, out] num_of_dest
11548 * Pointer to the num of destination.
11549 * @param[in, out] sample_actions
11550 * Pointer to sample actions list.
11551 * @param[in, out] res
11552 * Pointer to sample resource.
11553 * @param[out] error
11554 * Pointer to the error structure.
11557 * 0 on success, a negative errno value otherwise and rte_errno is set.
11560 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11561 const struct rte_flow_action_sample *action,
11562 struct mlx5_flow *dev_flow,
11563 const struct rte_flow_attr *attr,
11564 uint32_t *num_of_dest,
11565 void **sample_actions,
11566 struct mlx5_flow_dv_sample_resource *res,
11567 struct rte_flow_error *error)
11569 struct mlx5_priv *priv = dev->data->dev_private;
11570 const struct rte_flow_action *sub_actions;
11571 struct mlx5_flow_sub_actions_list *sample_act;
11572 struct mlx5_flow_sub_actions_idx *sample_idx;
11573 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11574 struct rte_flow *flow = dev_flow->flow;
11575 struct mlx5_flow_rss_desc *rss_desc;
11576 uint64_t action_flags = 0;
11579 rss_desc = &wks->rss_desc;
11580 sample_act = &res->sample_act;
11581 sample_idx = &res->sample_idx;
11582 res->ratio = action->ratio;
11583 sub_actions = action->actions;
11584 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11585 int type = sub_actions->type;
11586 uint32_t pre_rix = 0;
11589 case RTE_FLOW_ACTION_TYPE_QUEUE:
11591 const struct rte_flow_action_queue *queue;
11592 struct mlx5_hrxq *hrxq;
11595 queue = sub_actions->conf;
11596 rss_desc->queue_num = 1;
11597 rss_desc->queue[0] = queue->index;
11598 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11599 rss_desc, &hrxq_idx);
11601 return rte_flow_error_set
11603 RTE_FLOW_ERROR_TYPE_ACTION,
11605 "cannot create fate queue");
11606 sample_act->dr_queue_action = hrxq->action;
11607 sample_idx->rix_hrxq = hrxq_idx;
11608 sample_actions[sample_act->actions_num++] =
11611 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11612 if (action_flags & MLX5_FLOW_ACTION_MARK)
11613 dev_flow->handle->rix_hrxq = hrxq_idx;
11614 dev_flow->handle->fate_action =
11615 MLX5_FLOW_FATE_QUEUE;
11618 case RTE_FLOW_ACTION_TYPE_RSS:
11620 struct mlx5_hrxq *hrxq;
11622 const struct rte_flow_action_rss *rss;
11623 const uint8_t *rss_key;
11625 rss = sub_actions->conf;
11626 memcpy(rss_desc->queue, rss->queue,
11627 rss->queue_num * sizeof(uint16_t));
11628 rss_desc->queue_num = rss->queue_num;
11629 /* NULL RSS key indicates default RSS key. */
11630 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11631 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11633 * rss->level and rss.types should be set in advance
11634 * when expanding items for RSS.
11636 flow_dv_hashfields_set(dev_flow, rss_desc);
11637 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11638 rss_desc, &hrxq_idx);
11640 return rte_flow_error_set
11642 RTE_FLOW_ERROR_TYPE_ACTION,
11644 "cannot create fate queue");
11645 sample_act->dr_queue_action = hrxq->action;
11646 sample_idx->rix_hrxq = hrxq_idx;
11647 sample_actions[sample_act->actions_num++] =
11650 action_flags |= MLX5_FLOW_ACTION_RSS;
11651 if (action_flags & MLX5_FLOW_ACTION_MARK)
11652 dev_flow->handle->rix_hrxq = hrxq_idx;
11653 dev_flow->handle->fate_action =
11654 MLX5_FLOW_FATE_QUEUE;
11657 case RTE_FLOW_ACTION_TYPE_MARK:
11659 uint32_t tag_be = mlx5_flow_mark_set
11660 (((const struct rte_flow_action_mark *)
11661 (sub_actions->conf))->id);
11663 dev_flow->handle->mark = 1;
11664 pre_rix = dev_flow->handle->dvh.rix_tag;
11665 /* Save the mark resource before sample */
11666 pre_r = dev_flow->dv.tag_resource;
11667 if (flow_dv_tag_resource_register(dev, tag_be,
11670 MLX5_ASSERT(dev_flow->dv.tag_resource);
11671 sample_act->dr_tag_action =
11672 dev_flow->dv.tag_resource->action;
11673 sample_idx->rix_tag =
11674 dev_flow->handle->dvh.rix_tag;
11675 sample_actions[sample_act->actions_num++] =
11676 sample_act->dr_tag_action;
11677 /* Recover the mark resource after sample */
11678 dev_flow->dv.tag_resource = pre_r;
11679 dev_flow->handle->dvh.rix_tag = pre_rix;
11680 action_flags |= MLX5_FLOW_ACTION_MARK;
11683 case RTE_FLOW_ACTION_TYPE_COUNT:
11685 if (!flow->counter) {
11687 flow_dv_translate_create_counter(dev,
11688 dev_flow, sub_actions->conf,
11690 if (!flow->counter)
11691 return rte_flow_error_set
11693 RTE_FLOW_ERROR_TYPE_ACTION,
11695 "cannot create counter"
11698 sample_act->dr_cnt_action =
11699 (flow_dv_counter_get_by_idx(dev,
11700 flow->counter, NULL))->action;
11701 sample_actions[sample_act->actions_num++] =
11702 sample_act->dr_cnt_action;
11703 action_flags |= MLX5_FLOW_ACTION_COUNT;
11706 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11707 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11709 struct mlx5_flow_dv_port_id_action_resource
11711 uint32_t port_id = 0;
11713 memset(&port_id_resource, 0, sizeof(port_id_resource));
11714 /* Save the port id resource before sample */
11715 pre_rix = dev_flow->handle->rix_port_id_action;
11716 pre_r = dev_flow->dv.port_id_action;
11717 if (flow_dv_translate_action_port_id(dev, sub_actions,
11720 port_id_resource.port_id = port_id;
11721 if (flow_dv_port_id_action_resource_register
11722 (dev, &port_id_resource, dev_flow, error))
11724 sample_act->dr_port_id_action =
11725 dev_flow->dv.port_id_action->action;
11726 sample_idx->rix_port_id_action =
11727 dev_flow->handle->rix_port_id_action;
11728 sample_actions[sample_act->actions_num++] =
11729 sample_act->dr_port_id_action;
11730 /* Recover the port id resource after sample */
11731 dev_flow->dv.port_id_action = pre_r;
11732 dev_flow->handle->rix_port_id_action = pre_rix;
11734 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11737 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11738 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11739 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11740 /* Save the encap resource before sample */
11741 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11742 pre_r = dev_flow->dv.encap_decap;
11743 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11748 sample_act->dr_encap_action =
11749 dev_flow->dv.encap_decap->action;
11750 sample_idx->rix_encap_decap =
11751 dev_flow->handle->dvh.rix_encap_decap;
11752 sample_actions[sample_act->actions_num++] =
11753 sample_act->dr_encap_action;
11754 /* Recover the encap resource after sample */
11755 dev_flow->dv.encap_decap = pre_r;
11756 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11757 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11760 return rte_flow_error_set(error, EINVAL,
11761 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11763 "Not support for sampler action");
11766 sample_act->action_flags = action_flags;
11767 res->ft_id = dev_flow->dv.group;
11768 if (attr->transfer) {
11770 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11771 uint64_t set_action;
11772 } action_ctx = { .set_action = 0 };
11774 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11775 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11776 MLX5_MODIFICATION_TYPE_SET);
11777 MLX5_SET(set_action_in, action_ctx.action_in, field,
11778 MLX5_MODI_META_REG_C_0);
11779 MLX5_SET(set_action_in, action_ctx.action_in, data,
11780 priv->vport_meta_tag);
11781 res->set_action = action_ctx.set_action;
11782 } else if (attr->ingress) {
11783 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11785 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11791 * Convert Sample action to DV specification.
11794 * Pointer to rte_eth_dev structure.
11795 * @param[in, out] dev_flow
11796 * Pointer to the mlx5_flow.
11797 * @param[in] num_of_dest
11798 * The num of destination.
11799 * @param[in, out] res
11800 * Pointer to sample resource.
11801 * @param[in, out] mdest_res
11802 * Pointer to destination array resource.
11803 * @param[in] sample_actions
11804 * Pointer to sample path actions list.
11805 * @param[in] action_flags
11806 * Holds the actions detected until now.
11807 * @param[out] error
11808 * Pointer to the error structure.
11811 * 0 on success, a negative errno value otherwise and rte_errno is set.
11814 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11815 struct mlx5_flow *dev_flow,
11816 uint32_t num_of_dest,
11817 struct mlx5_flow_dv_sample_resource *res,
11818 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11819 void **sample_actions,
11820 uint64_t action_flags,
11821 struct rte_flow_error *error)
11823 /* update normal path action resource into last index of array */
11824 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11825 struct mlx5_flow_sub_actions_list *sample_act =
11826 &mdest_res->sample_act[dest_index];
11827 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11828 struct mlx5_flow_rss_desc *rss_desc;
11829 uint32_t normal_idx = 0;
11830 struct mlx5_hrxq *hrxq;
11834 rss_desc = &wks->rss_desc;
11835 if (num_of_dest > 1) {
11836 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11837 /* Handle QP action for mirroring */
11838 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11839 rss_desc, &hrxq_idx);
11841 return rte_flow_error_set
11843 RTE_FLOW_ERROR_TYPE_ACTION,
11845 "cannot create rx queue");
11847 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11848 sample_act->dr_queue_action = hrxq->action;
11849 if (action_flags & MLX5_FLOW_ACTION_MARK)
11850 dev_flow->handle->rix_hrxq = hrxq_idx;
11851 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11853 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11855 mdest_res->sample_idx[dest_index].rix_encap_decap =
11856 dev_flow->handle->dvh.rix_encap_decap;
11857 sample_act->dr_encap_action =
11858 dev_flow->dv.encap_decap->action;
11859 dev_flow->handle->dvh.rix_encap_decap = 0;
11861 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11863 mdest_res->sample_idx[dest_index].rix_port_id_action =
11864 dev_flow->handle->rix_port_id_action;
11865 sample_act->dr_port_id_action =
11866 dev_flow->dv.port_id_action->action;
11867 dev_flow->handle->rix_port_id_action = 0;
11869 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11871 mdest_res->sample_idx[dest_index].rix_jump =
11872 dev_flow->handle->rix_jump;
11873 sample_act->dr_jump_action =
11874 dev_flow->dv.jump->action;
11875 dev_flow->handle->rix_jump = 0;
11877 sample_act->actions_num = normal_idx;
11878 /* update sample action resource into first index of array */
11879 mdest_res->ft_type = res->ft_type;
11880 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11881 sizeof(struct mlx5_flow_sub_actions_idx));
11882 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11883 sizeof(struct mlx5_flow_sub_actions_list));
11884 mdest_res->num_of_dest = num_of_dest;
11885 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11887 return rte_flow_error_set(error, EINVAL,
11888 RTE_FLOW_ERROR_TYPE_ACTION,
11889 NULL, "can't create sample "
11892 res->sub_actions = sample_actions;
11893 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11894 return rte_flow_error_set(error, EINVAL,
11895 RTE_FLOW_ERROR_TYPE_ACTION,
11897 "can't create sample action");
11903 * Remove an ASO age action from age actions list.
11906 * Pointer to the Ethernet device structure.
11908 * Pointer to the aso age action handler.
11911 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11912 struct mlx5_aso_age_action *age)
11914 struct mlx5_age_info *age_info;
11915 struct mlx5_age_param *age_param = &age->age_params;
11916 struct mlx5_priv *priv = dev->data->dev_private;
11917 uint16_t expected = AGE_CANDIDATE;
11919 age_info = GET_PORT_AGE_INFO(priv);
11920 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11921 AGE_FREE, false, __ATOMIC_RELAXED,
11922 __ATOMIC_RELAXED)) {
11924 * We need the lock even it is age timeout,
11925 * since age action may still in process.
11927 rte_spinlock_lock(&age_info->aged_sl);
11928 LIST_REMOVE(age, next);
11929 rte_spinlock_unlock(&age_info->aged_sl);
11930 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11935 * Release an ASO age action.
11938 * Pointer to the Ethernet device structure.
11939 * @param[in] age_idx
11940 * Index of ASO age action to release.
11942 * True if the release operation is during flow destroy operation.
11943 * False if the release operation is during action destroy operation.
11946 * 0 when age action was removed, otherwise the number of references.
11949 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11951 struct mlx5_priv *priv = dev->data->dev_private;
11952 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11953 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11954 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11957 flow_dv_aso_age_remove_from_age(dev, age);
11958 rte_spinlock_lock(&mng->free_sl);
11959 LIST_INSERT_HEAD(&mng->free, age, next);
11960 rte_spinlock_unlock(&mng->free_sl);
11966 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11969 * Pointer to the Ethernet device structure.
11972 * 0 on success, otherwise negative errno value and rte_errno is set.
11975 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11977 struct mlx5_priv *priv = dev->data->dev_private;
11978 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11979 void *old_pools = mng->pools;
11980 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11981 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11982 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11985 rte_errno = ENOMEM;
11989 memcpy(pools, old_pools,
11990 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11991 mlx5_free(old_pools);
11993 /* First ASO flow hit allocation - starting ASO data-path. */
11994 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
12002 mng->pools = pools;
12007 * Create and initialize a new ASO aging pool.
12010 * Pointer to the Ethernet device structure.
12011 * @param[out] age_free
12012 * Where to put the pointer of a new age action.
12015 * The age actions pool pointer and @p age_free is set on success,
12016 * NULL otherwise and rte_errno is set.
12018 static struct mlx5_aso_age_pool *
12019 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12020 struct mlx5_aso_age_action **age_free)
12022 struct mlx5_priv *priv = dev->data->dev_private;
12023 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12024 struct mlx5_aso_age_pool *pool = NULL;
12025 struct mlx5_devx_obj *obj = NULL;
12028 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12029 priv->sh->cdev->pdn);
12031 rte_errno = ENODATA;
12032 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12035 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12037 claim_zero(mlx5_devx_cmd_destroy(obj));
12038 rte_errno = ENOMEM;
12041 pool->flow_hit_aso_obj = obj;
12042 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12043 rte_rwlock_write_lock(&mng->resize_rwl);
12044 pool->index = mng->next;
12045 /* Resize pools array if there is no room for the new pool in it. */
12046 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12047 claim_zero(mlx5_devx_cmd_destroy(obj));
12049 rte_rwlock_write_unlock(&mng->resize_rwl);
12052 mng->pools[pool->index] = pool;
12054 rte_rwlock_write_unlock(&mng->resize_rwl);
12055 /* Assign the first action in the new pool, the rest go to free list. */
12056 *age_free = &pool->actions[0];
12057 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12058 pool->actions[i].offset = i;
12059 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12065 * Allocate a ASO aging bit.
12068 * Pointer to the Ethernet device structure.
12069 * @param[out] error
12070 * Pointer to the error structure.
12073 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12076 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12078 struct mlx5_priv *priv = dev->data->dev_private;
12079 const struct mlx5_aso_age_pool *pool;
12080 struct mlx5_aso_age_action *age_free = NULL;
12081 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12084 /* Try to get the next free age action bit. */
12085 rte_spinlock_lock(&mng->free_sl);
12086 age_free = LIST_FIRST(&mng->free);
12088 LIST_REMOVE(age_free, next);
12089 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12090 rte_spinlock_unlock(&mng->free_sl);
12091 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12092 NULL, "failed to create ASO age pool");
12093 return 0; /* 0 is an error. */
12095 rte_spinlock_unlock(&mng->free_sl);
12096 pool = container_of
12097 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12098 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12100 if (!age_free->dr_action) {
12101 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12105 rte_flow_error_set(error, rte_errno,
12106 RTE_FLOW_ERROR_TYPE_ACTION,
12107 NULL, "failed to get reg_c "
12108 "for ASO flow hit");
12109 return 0; /* 0 is an error. */
12111 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12112 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12113 (priv->sh->rx_domain,
12114 pool->flow_hit_aso_obj->obj, age_free->offset,
12115 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12116 (reg_c - REG_C_0));
12117 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12118 if (!age_free->dr_action) {
12120 rte_spinlock_lock(&mng->free_sl);
12121 LIST_INSERT_HEAD(&mng->free, age_free, next);
12122 rte_spinlock_unlock(&mng->free_sl);
12123 rte_flow_error_set(error, rte_errno,
12124 RTE_FLOW_ERROR_TYPE_ACTION,
12125 NULL, "failed to create ASO "
12126 "flow hit action");
12127 return 0; /* 0 is an error. */
12130 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12131 return pool->index | ((age_free->offset + 1) << 16);
12135 * Initialize flow ASO age parameters.
12138 * Pointer to rte_eth_dev structure.
12139 * @param[in] age_idx
12140 * Index of ASO age action.
12141 * @param[in] context
12142 * Pointer to flow counter age context.
12143 * @param[in] timeout
12144 * Aging timeout in seconds.
12148 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12153 struct mlx5_aso_age_action *aso_age;
12155 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12156 MLX5_ASSERT(aso_age);
12157 aso_age->age_params.context = context;
12158 aso_age->age_params.timeout = timeout;
12159 aso_age->age_params.port_id = dev->data->port_id;
12160 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12162 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12167 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12168 const struct rte_flow_item_integrity *value,
12169 void *headers_m, void *headers_v)
12172 /* RTE l4_ok filter aggregates hardware l4_ok and
12173 * l4_checksum_ok filters.
12174 * Positive RTE l4_ok match requires hardware match on both L4
12175 * hardware integrity bits.
12176 * For negative match, check hardware l4_checksum_ok bit only,
12177 * because hardware sets that bit to 0 for all packets
12180 if (value->l4_ok) {
12181 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12182 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12184 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12185 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12188 if (mask->l4_csum_ok) {
12189 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12190 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12191 value->l4_csum_ok);
12196 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12197 const struct rte_flow_item_integrity *value,
12198 void *headers_m, void *headers_v, bool is_ipv4)
12201 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12202 * ipv4_csum_ok filters.
12203 * Positive RTE l3_ok match requires hardware match on both L3
12204 * hardware integrity bits.
12205 * For negative match, check hardware l3_csum_ok bit only,
12206 * because hardware sets that bit to 0 for all packets
12210 if (value->l3_ok) {
12211 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12213 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12216 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12217 ipv4_checksum_ok, 1);
12218 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12219 ipv4_checksum_ok, !!value->l3_ok);
12221 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12222 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12226 if (mask->ipv4_csum_ok) {
12227 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12228 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12229 value->ipv4_csum_ok);
12234 set_integrity_bits(void *headers_m, void *headers_v,
12235 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12237 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12238 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12240 /* Integrity bits validation cleared spec pointer */
12241 MLX5_ASSERT(spec != NULL);
12243 mask = &rte_flow_item_integrity_mask;
12244 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12246 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12250 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12252 struct rte_flow_item *integrity_items[2],
12253 uint64_t pattern_flags)
12255 void *headers_m, *headers_v;
12258 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12259 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12261 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12262 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12264 set_integrity_bits(headers_m, headers_v,
12265 integrity_items[1], is_l3_ip4);
12267 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12268 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12270 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12271 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12273 set_integrity_bits(headers_m, headers_v,
12274 integrity_items[0], is_l3_ip4);
12279 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12280 const struct rte_flow_item *integrity_items[2],
12281 uint64_t *last_item)
12283 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12285 /* integrity bits validation cleared spec pointer */
12286 MLX5_ASSERT(spec != NULL);
12287 if (spec->level > 1) {
12288 integrity_items[1] = item;
12289 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12291 integrity_items[0] = item;
12292 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12297 * Prepares DV flow counter with aging configuration.
12298 * Gets it by index when exists, creates a new one when doesn't.
12301 * Pointer to rte_eth_dev structure.
12302 * @param[in] dev_flow
12303 * Pointer to the mlx5_flow.
12304 * @param[in, out] flow
12305 * Pointer to the sub flow.
12307 * Pointer to the counter action configuration.
12309 * Pointer to the aging action configuration.
12310 * @param[out] error
12311 * Pointer to the error structure.
12314 * Pointer to the counter, NULL otherwise.
12316 static struct mlx5_flow_counter *
12317 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12318 struct mlx5_flow *dev_flow,
12319 struct rte_flow *flow,
12320 const struct rte_flow_action_count *count,
12321 const struct rte_flow_action_age *age,
12322 struct rte_flow_error *error)
12324 if (!flow->counter) {
12325 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12327 if (!flow->counter) {
12328 rte_flow_error_set(error, rte_errno,
12329 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12330 "cannot create counter object.");
12334 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12338 * Release an ASO CT action by its own device.
12341 * Pointer to the Ethernet device structure.
12343 * Index of ASO CT action to release.
12346 * 0 when CT action was removed, otherwise the number of references.
12349 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12351 struct mlx5_priv *priv = dev->data->dev_private;
12352 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12354 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12355 enum mlx5_aso_ct_state state =
12356 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12358 /* Cannot release when CT is in the ASO SQ. */
12359 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12361 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12363 if (ct->dr_action_orig) {
12364 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12365 claim_zero(mlx5_glue->destroy_flow_action
12366 (ct->dr_action_orig));
12368 ct->dr_action_orig = NULL;
12370 if (ct->dr_action_rply) {
12371 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12372 claim_zero(mlx5_glue->destroy_flow_action
12373 (ct->dr_action_rply));
12375 ct->dr_action_rply = NULL;
12377 /* Clear the state to free, no need in 1st allocation. */
12378 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12379 rte_spinlock_lock(&mng->ct_sl);
12380 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12381 rte_spinlock_unlock(&mng->ct_sl);
12387 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12388 struct rte_flow_error *error)
12390 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12391 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12392 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12395 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12396 if (dev->data->dev_started != 1)
12397 return rte_flow_error_set(error, EAGAIN,
12398 RTE_FLOW_ERROR_TYPE_ACTION,
12400 "Indirect CT action cannot be destroyed when the port is stopped");
12401 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12403 return rte_flow_error_set(error, EAGAIN,
12404 RTE_FLOW_ERROR_TYPE_ACTION,
12406 "Current state prevents indirect CT action from being destroyed");
12411 * Resize the ASO CT pools array by 64 pools.
12414 * Pointer to the Ethernet device structure.
12417 * 0 on success, otherwise negative errno value and rte_errno is set.
12420 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12422 struct mlx5_priv *priv = dev->data->dev_private;
12423 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12424 void *old_pools = mng->pools;
12425 /* Magic number now, need a macro. */
12426 uint32_t resize = mng->n + 64;
12427 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12428 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12431 rte_errno = ENOMEM;
12434 rte_rwlock_write_lock(&mng->resize_rwl);
12435 /* ASO SQ/QP was already initialized in the startup. */
12437 /* Realloc could be an alternative choice. */
12438 rte_memcpy(pools, old_pools,
12439 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12440 mlx5_free(old_pools);
12443 mng->pools = pools;
12444 rte_rwlock_write_unlock(&mng->resize_rwl);
12449 * Create and initialize a new ASO CT pool.
12452 * Pointer to the Ethernet device structure.
12453 * @param[out] ct_free
12454 * Where to put the pointer of a new CT action.
12457 * The CT actions pool pointer and @p ct_free is set on success,
12458 * NULL otherwise and rte_errno is set.
12460 static struct mlx5_aso_ct_pool *
12461 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12462 struct mlx5_aso_ct_action **ct_free)
12464 struct mlx5_priv *priv = dev->data->dev_private;
12465 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12466 struct mlx5_aso_ct_pool *pool = NULL;
12467 struct mlx5_devx_obj *obj = NULL;
12469 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12471 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12472 priv->sh->cdev->pdn,
12475 rte_errno = ENODATA;
12476 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12479 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12481 rte_errno = ENOMEM;
12482 claim_zero(mlx5_devx_cmd_destroy(obj));
12485 pool->devx_obj = obj;
12486 pool->index = mng->next;
12487 /* Resize pools array if there is no room for the new pool in it. */
12488 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12489 claim_zero(mlx5_devx_cmd_destroy(obj));
12493 mng->pools[pool->index] = pool;
12495 /* Assign the first action in the new pool, the rest go to free list. */
12496 *ct_free = &pool->actions[0];
12497 /* Lock outside, the list operation is safe here. */
12498 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12499 /* refcnt is 0 when allocating the memory. */
12500 pool->actions[i].offset = i;
12501 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12507 * Allocate a ASO CT action from free list.
12510 * Pointer to the Ethernet device structure.
12511 * @param[out] error
12512 * Pointer to the error structure.
12515 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12518 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12520 struct mlx5_priv *priv = dev->data->dev_private;
12521 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12522 struct mlx5_aso_ct_action *ct = NULL;
12523 struct mlx5_aso_ct_pool *pool;
12528 if (!priv->sh->devx) {
12529 rte_errno = ENOTSUP;
12532 /* Get a free CT action, if no, a new pool will be created. */
12533 rte_spinlock_lock(&mng->ct_sl);
12534 ct = LIST_FIRST(&mng->free_cts);
12536 LIST_REMOVE(ct, next);
12537 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12538 rte_spinlock_unlock(&mng->ct_sl);
12539 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12540 NULL, "failed to create ASO CT pool");
12543 rte_spinlock_unlock(&mng->ct_sl);
12544 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12545 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12546 /* 0: inactive, 1: created, 2+: used by flows. */
12547 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12548 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12549 if (!ct->dr_action_orig) {
12550 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12551 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12552 (priv->sh->rx_domain, pool->devx_obj->obj,
12554 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12557 RTE_SET_USED(reg_c);
12559 if (!ct->dr_action_orig) {
12560 flow_dv_aso_ct_dev_release(dev, ct_idx);
12561 rte_flow_error_set(error, rte_errno,
12562 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12563 "failed to create ASO CT action");
12567 if (!ct->dr_action_rply) {
12568 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12569 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12570 (priv->sh->rx_domain, pool->devx_obj->obj,
12572 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12575 if (!ct->dr_action_rply) {
12576 flow_dv_aso_ct_dev_release(dev, ct_idx);
12577 rte_flow_error_set(error, rte_errno,
12578 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12579 "failed to create ASO CT action");
12587 * Create a conntrack object with context and actions by using ASO mechanism.
12590 * Pointer to rte_eth_dev structure.
12592 * Pointer to conntrack information profile.
12593 * @param[out] error
12594 * Pointer to the error structure.
12597 * Index to conntrack object on success, 0 otherwise.
12600 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12601 const struct rte_flow_action_conntrack *pro,
12602 struct rte_flow_error *error)
12604 struct mlx5_priv *priv = dev->data->dev_private;
12605 struct mlx5_dev_ctx_shared *sh = priv->sh;
12606 struct mlx5_aso_ct_action *ct;
12609 if (!sh->ct_aso_en)
12610 return rte_flow_error_set(error, ENOTSUP,
12611 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12612 "Connection is not supported");
12613 idx = flow_dv_aso_ct_alloc(dev, error);
12615 return rte_flow_error_set(error, rte_errno,
12616 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12617 "Failed to allocate CT object");
12618 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12619 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12620 return rte_flow_error_set(error, EBUSY,
12621 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12622 "Failed to update CT");
12623 ct->is_original = !!pro->is_original_dir;
12624 ct->peer = pro->peer_port;
12629 * Fill the flow with DV spec, lock free
12630 * (mutex should be acquired by caller).
12633 * Pointer to rte_eth_dev structure.
12634 * @param[in, out] dev_flow
12635 * Pointer to the sub flow.
12637 * Pointer to the flow attributes.
12639 * Pointer to the list of items.
12640 * @param[in] actions
12641 * Pointer to the list of actions.
12642 * @param[out] error
12643 * Pointer to the error structure.
12646 * 0 on success, a negative errno value otherwise and rte_errno is set.
12649 flow_dv_translate(struct rte_eth_dev *dev,
12650 struct mlx5_flow *dev_flow,
12651 const struct rte_flow_attr *attr,
12652 const struct rte_flow_item items[],
12653 const struct rte_flow_action actions[],
12654 struct rte_flow_error *error)
12656 struct mlx5_priv *priv = dev->data->dev_private;
12657 struct mlx5_dev_config *dev_conf = &priv->config;
12658 struct rte_flow *flow = dev_flow->flow;
12659 struct mlx5_flow_handle *handle = dev_flow->handle;
12660 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12661 struct mlx5_flow_rss_desc *rss_desc;
12662 uint64_t item_flags = 0;
12663 uint64_t last_item = 0;
12664 uint64_t action_flags = 0;
12665 struct mlx5_flow_dv_matcher matcher = {
12667 .size = sizeof(matcher.mask.buf),
12671 bool actions_end = false;
12673 struct mlx5_flow_dv_modify_hdr_resource res;
12674 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12675 sizeof(struct mlx5_modification_cmd) *
12676 (MLX5_MAX_MODIFY_NUM + 1)];
12678 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12679 const struct rte_flow_action_count *count = NULL;
12680 const struct rte_flow_action_age *non_shared_age = NULL;
12681 union flow_dv_attr flow_attr = { .attr = 0 };
12683 union mlx5_flow_tbl_key tbl_key;
12684 uint32_t modify_action_position = UINT32_MAX;
12685 void *match_mask = matcher.mask.buf;
12686 void *match_value = dev_flow->dv.value.buf;
12687 uint8_t next_protocol = 0xff;
12688 struct rte_vlan_hdr vlan = { 0 };
12689 struct mlx5_flow_dv_dest_array_resource mdest_res;
12690 struct mlx5_flow_dv_sample_resource sample_res;
12691 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12692 const struct rte_flow_action_sample *sample = NULL;
12693 struct mlx5_flow_sub_actions_list *sample_act;
12694 uint32_t sample_act_pos = UINT32_MAX;
12695 uint32_t age_act_pos = UINT32_MAX;
12696 uint32_t num_of_dest = 0;
12697 int tmp_actions_n = 0;
12700 const struct mlx5_flow_tunnel *tunnel = NULL;
12701 struct flow_grp_info grp_info = {
12702 .external = !!dev_flow->external,
12703 .transfer = !!attr->transfer,
12704 .fdb_def_rule = !!priv->fdb_def_rule,
12705 .skip_scale = dev_flow->skip_scale &
12706 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12707 .std_tbl_fix = true,
12709 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12710 const struct rte_flow_item *tunnel_item = NULL;
12713 return rte_flow_error_set(error, ENOMEM,
12714 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12716 "failed to push flow workspace");
12717 rss_desc = &wks->rss_desc;
12718 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12719 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12720 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12721 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12722 /* update normal path action resource into last index of array */
12723 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12724 if (is_tunnel_offload_active(dev)) {
12725 if (dev_flow->tunnel) {
12726 RTE_VERIFY(dev_flow->tof_type ==
12727 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12728 tunnel = dev_flow->tunnel;
12730 tunnel = mlx5_get_tof(items, actions,
12731 &dev_flow->tof_type);
12732 dev_flow->tunnel = tunnel;
12734 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12735 (dev, attr, tunnel, dev_flow->tof_type);
12737 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12738 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12739 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12743 dev_flow->dv.group = table;
12744 if (attr->transfer)
12745 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12746 /* number of actions must be set to 0 in case of dirty stack. */
12747 mhdr_res->actions_num = 0;
12748 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12750 * do not add decap action if match rule drops packet
12751 * HW rejects rules with decap & drop
12753 * if tunnel match rule was inserted before matching tunnel set
12754 * rule flow table used in the match rule must be registered.
12755 * current implementation handles that in the
12756 * flow_dv_match_register() at the function end.
12758 bool add_decap = true;
12759 const struct rte_flow_action *ptr = actions;
12761 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12762 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12768 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12772 dev_flow->dv.actions[actions_n++] =
12773 dev_flow->dv.encap_decap->action;
12774 action_flags |= MLX5_FLOW_ACTION_DECAP;
12777 for (; !actions_end ; actions++) {
12778 const struct rte_flow_action_queue *queue;
12779 const struct rte_flow_action_rss *rss;
12780 const struct rte_flow_action *action = actions;
12781 const uint8_t *rss_key;
12782 struct mlx5_flow_tbl_resource *tbl;
12783 struct mlx5_aso_age_action *age_act;
12784 struct mlx5_flow_counter *cnt_act;
12785 uint32_t port_id = 0;
12786 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12787 int action_type = actions->type;
12788 const struct rte_flow_action *found_action = NULL;
12789 uint32_t jump_group = 0;
12790 uint32_t owner_idx;
12791 struct mlx5_aso_ct_action *ct;
12793 if (!mlx5_flow_os_action_supported(action_type))
12794 return rte_flow_error_set(error, ENOTSUP,
12795 RTE_FLOW_ERROR_TYPE_ACTION,
12797 "action not supported");
12798 switch (action_type) {
12799 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12800 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12802 case RTE_FLOW_ACTION_TYPE_VOID:
12804 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12805 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12806 if (flow_dv_translate_action_port_id(dev, action,
12809 port_id_resource.port_id = port_id;
12810 MLX5_ASSERT(!handle->rix_port_id_action);
12811 if (flow_dv_port_id_action_resource_register
12812 (dev, &port_id_resource, dev_flow, error))
12814 dev_flow->dv.actions[actions_n++] =
12815 dev_flow->dv.port_id_action->action;
12816 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12817 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12818 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12821 case RTE_FLOW_ACTION_TYPE_FLAG:
12822 action_flags |= MLX5_FLOW_ACTION_FLAG;
12823 dev_flow->handle->mark = 1;
12824 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12825 struct rte_flow_action_mark mark = {
12826 .id = MLX5_FLOW_MARK_DEFAULT,
12829 if (flow_dv_convert_action_mark(dev, &mark,
12833 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12836 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12838 * Only one FLAG or MARK is supported per device flow
12839 * right now. So the pointer to the tag resource must be
12840 * zero before the register process.
12842 MLX5_ASSERT(!handle->dvh.rix_tag);
12843 if (flow_dv_tag_resource_register(dev, tag_be,
12846 MLX5_ASSERT(dev_flow->dv.tag_resource);
12847 dev_flow->dv.actions[actions_n++] =
12848 dev_flow->dv.tag_resource->action;
12850 case RTE_FLOW_ACTION_TYPE_MARK:
12851 action_flags |= MLX5_FLOW_ACTION_MARK;
12852 dev_flow->handle->mark = 1;
12853 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12854 const struct rte_flow_action_mark *mark =
12855 (const struct rte_flow_action_mark *)
12858 if (flow_dv_convert_action_mark(dev, mark,
12862 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12866 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12867 /* Legacy (non-extensive) MARK action. */
12868 tag_be = mlx5_flow_mark_set
12869 (((const struct rte_flow_action_mark *)
12870 (actions->conf))->id);
12871 MLX5_ASSERT(!handle->dvh.rix_tag);
12872 if (flow_dv_tag_resource_register(dev, tag_be,
12875 MLX5_ASSERT(dev_flow->dv.tag_resource);
12876 dev_flow->dv.actions[actions_n++] =
12877 dev_flow->dv.tag_resource->action;
12879 case RTE_FLOW_ACTION_TYPE_SET_META:
12880 if (flow_dv_convert_action_set_meta
12881 (dev, mhdr_res, attr,
12882 (const struct rte_flow_action_set_meta *)
12883 actions->conf, error))
12885 action_flags |= MLX5_FLOW_ACTION_SET_META;
12887 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12888 if (flow_dv_convert_action_set_tag
12890 (const struct rte_flow_action_set_tag *)
12891 actions->conf, error))
12893 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12895 case RTE_FLOW_ACTION_TYPE_DROP:
12896 action_flags |= MLX5_FLOW_ACTION_DROP;
12897 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12899 case RTE_FLOW_ACTION_TYPE_QUEUE:
12900 queue = actions->conf;
12901 rss_desc->queue_num = 1;
12902 rss_desc->queue[0] = queue->index;
12903 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12904 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12905 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12908 case RTE_FLOW_ACTION_TYPE_RSS:
12909 rss = actions->conf;
12910 memcpy(rss_desc->queue, rss->queue,
12911 rss->queue_num * sizeof(uint16_t));
12912 rss_desc->queue_num = rss->queue_num;
12913 /* NULL RSS key indicates default RSS key. */
12914 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12915 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12917 * rss->level and rss.types should be set in advance
12918 * when expanding items for RSS.
12920 action_flags |= MLX5_FLOW_ACTION_RSS;
12921 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12922 MLX5_FLOW_FATE_SHARED_RSS :
12923 MLX5_FLOW_FATE_QUEUE;
12925 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12926 owner_idx = (uint32_t)(uintptr_t)action->conf;
12927 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12928 if (flow->age == 0) {
12929 flow->age = owner_idx;
12930 __atomic_fetch_add(&age_act->refcnt, 1,
12933 age_act_pos = actions_n++;
12934 action_flags |= MLX5_FLOW_ACTION_AGE;
12936 case RTE_FLOW_ACTION_TYPE_AGE:
12937 non_shared_age = action->conf;
12938 age_act_pos = actions_n++;
12939 action_flags |= MLX5_FLOW_ACTION_AGE;
12941 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12942 owner_idx = (uint32_t)(uintptr_t)action->conf;
12943 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12945 MLX5_ASSERT(cnt_act != NULL);
12947 * When creating meter drop flow in drop table, the
12948 * counter should not overwrite the rte flow counter.
12950 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12951 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12952 dev_flow->dv.actions[actions_n++] =
12955 if (flow->counter == 0) {
12956 flow->counter = owner_idx;
12958 (&cnt_act->shared_info.refcnt,
12959 1, __ATOMIC_RELAXED);
12961 /* Save information first, will apply later. */
12962 action_flags |= MLX5_FLOW_ACTION_COUNT;
12965 case RTE_FLOW_ACTION_TYPE_COUNT:
12966 if (!priv->sh->devx) {
12967 return rte_flow_error_set
12969 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12971 "count action not supported");
12973 /* Save information first, will apply later. */
12974 count = action->conf;
12975 action_flags |= MLX5_FLOW_ACTION_COUNT;
12977 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12978 dev_flow->dv.actions[actions_n++] =
12979 priv->sh->pop_vlan_action;
12980 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12982 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12983 if (!(action_flags &
12984 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12985 flow_dev_get_vlan_info_from_items(items, &vlan);
12986 vlan.eth_proto = rte_be_to_cpu_16
12987 ((((const struct rte_flow_action_of_push_vlan *)
12988 actions->conf)->ethertype));
12989 found_action = mlx5_flow_find_action
12991 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12993 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12994 found_action = mlx5_flow_find_action
12996 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12998 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12999 if (flow_dv_create_action_push_vlan
13000 (dev, attr, &vlan, dev_flow, error))
13002 dev_flow->dv.actions[actions_n++] =
13003 dev_flow->dv.push_vlan_res->action;
13004 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
13006 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
13007 /* of_vlan_push action handled this action */
13008 MLX5_ASSERT(action_flags &
13009 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13011 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13012 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13014 flow_dev_get_vlan_info_from_items(items, &vlan);
13015 mlx5_update_vlan_vid_pcp(actions, &vlan);
13016 /* If no VLAN push - this is a modify header action */
13017 if (flow_dv_convert_action_modify_vlan_vid
13018 (mhdr_res, actions, error))
13020 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13022 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13023 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13024 if (flow_dv_create_action_l2_encap(dev, actions,
13029 dev_flow->dv.actions[actions_n++] =
13030 dev_flow->dv.encap_decap->action;
13031 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13032 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13033 sample_act->action_flags |=
13034 MLX5_FLOW_ACTION_ENCAP;
13036 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13037 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13038 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13042 dev_flow->dv.actions[actions_n++] =
13043 dev_flow->dv.encap_decap->action;
13044 action_flags |= MLX5_FLOW_ACTION_DECAP;
13046 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13047 /* Handle encap with preceding decap. */
13048 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13049 if (flow_dv_create_action_raw_encap
13050 (dev, actions, dev_flow, attr, error))
13052 dev_flow->dv.actions[actions_n++] =
13053 dev_flow->dv.encap_decap->action;
13055 /* Handle encap without preceding decap. */
13056 if (flow_dv_create_action_l2_encap
13057 (dev, actions, dev_flow, attr->transfer,
13060 dev_flow->dv.actions[actions_n++] =
13061 dev_flow->dv.encap_decap->action;
13063 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13064 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13065 sample_act->action_flags |=
13066 MLX5_FLOW_ACTION_ENCAP;
13068 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13069 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13071 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13072 if (flow_dv_create_action_l2_decap
13073 (dev, dev_flow, attr->transfer, error))
13075 dev_flow->dv.actions[actions_n++] =
13076 dev_flow->dv.encap_decap->action;
13078 /* If decap is followed by encap, handle it at encap. */
13079 action_flags |= MLX5_FLOW_ACTION_DECAP;
13081 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13082 dev_flow->dv.actions[actions_n++] =
13083 (void *)(uintptr_t)action->conf;
13084 action_flags |= MLX5_FLOW_ACTION_JUMP;
13086 case RTE_FLOW_ACTION_TYPE_JUMP:
13087 jump_group = ((const struct rte_flow_action_jump *)
13088 action->conf)->group;
13089 grp_info.std_tbl_fix = 0;
13090 if (dev_flow->skip_scale &
13091 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13092 grp_info.skip_scale = 1;
13094 grp_info.skip_scale = 0;
13095 ret = mlx5_flow_group_to_table(dev, tunnel,
13101 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13103 !!dev_flow->external,
13104 tunnel, jump_group, 0,
13107 return rte_flow_error_set
13109 RTE_FLOW_ERROR_TYPE_ACTION,
13111 "cannot create jump action.");
13112 if (flow_dv_jump_tbl_resource_register
13113 (dev, tbl, dev_flow, error)) {
13114 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13115 return rte_flow_error_set
13117 RTE_FLOW_ERROR_TYPE_ACTION,
13119 "cannot create jump action.");
13121 dev_flow->dv.actions[actions_n++] =
13122 dev_flow->dv.jump->action;
13123 action_flags |= MLX5_FLOW_ACTION_JUMP;
13124 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13125 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13128 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13129 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13130 if (flow_dv_convert_action_modify_mac
13131 (mhdr_res, actions, error))
13133 action_flags |= actions->type ==
13134 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13135 MLX5_FLOW_ACTION_SET_MAC_SRC :
13136 MLX5_FLOW_ACTION_SET_MAC_DST;
13138 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13139 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13140 if (flow_dv_convert_action_modify_ipv4
13141 (mhdr_res, actions, error))
13143 action_flags |= actions->type ==
13144 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13145 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13146 MLX5_FLOW_ACTION_SET_IPV4_DST;
13148 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13149 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13150 if (flow_dv_convert_action_modify_ipv6
13151 (mhdr_res, actions, error))
13153 action_flags |= actions->type ==
13154 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13155 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13156 MLX5_FLOW_ACTION_SET_IPV6_DST;
13158 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13159 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13160 if (flow_dv_convert_action_modify_tp
13161 (mhdr_res, actions, items,
13162 &flow_attr, dev_flow, !!(action_flags &
13163 MLX5_FLOW_ACTION_DECAP), error))
13165 action_flags |= actions->type ==
13166 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13167 MLX5_FLOW_ACTION_SET_TP_SRC :
13168 MLX5_FLOW_ACTION_SET_TP_DST;
13170 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13171 if (flow_dv_convert_action_modify_dec_ttl
13172 (mhdr_res, items, &flow_attr, dev_flow,
13174 MLX5_FLOW_ACTION_DECAP), error))
13176 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13178 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13179 if (flow_dv_convert_action_modify_ttl
13180 (mhdr_res, actions, items, &flow_attr,
13181 dev_flow, !!(action_flags &
13182 MLX5_FLOW_ACTION_DECAP), error))
13184 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13186 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13187 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13188 if (flow_dv_convert_action_modify_tcp_seq
13189 (mhdr_res, actions, error))
13191 action_flags |= actions->type ==
13192 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13193 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13194 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13197 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13198 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13199 if (flow_dv_convert_action_modify_tcp_ack
13200 (mhdr_res, actions, error))
13202 action_flags |= actions->type ==
13203 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13204 MLX5_FLOW_ACTION_INC_TCP_ACK :
13205 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13207 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13208 if (flow_dv_convert_action_set_reg
13209 (mhdr_res, actions, error))
13211 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13213 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13214 if (flow_dv_convert_action_copy_mreg
13215 (dev, mhdr_res, actions, error))
13217 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13219 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13220 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13221 dev_flow->handle->fate_action =
13222 MLX5_FLOW_FATE_DEFAULT_MISS;
13224 case RTE_FLOW_ACTION_TYPE_METER:
13226 return rte_flow_error_set(error, rte_errno,
13227 RTE_FLOW_ERROR_TYPE_ACTION,
13228 NULL, "Failed to get meter in flow.");
13229 /* Set the meter action. */
13230 dev_flow->dv.actions[actions_n++] =
13231 wks->fm->meter_action;
13232 action_flags |= MLX5_FLOW_ACTION_METER;
13234 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13235 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13238 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13240 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13241 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13244 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13246 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13247 sample_act_pos = actions_n;
13248 sample = (const struct rte_flow_action_sample *)
13251 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13252 /* put encap action into group if work with port id */
13253 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13254 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13255 sample_act->action_flags |=
13256 MLX5_FLOW_ACTION_ENCAP;
13258 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13259 if (flow_dv_convert_action_modify_field
13260 (dev, mhdr_res, actions, attr, error))
13262 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13264 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13265 owner_idx = (uint32_t)(uintptr_t)action->conf;
13266 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13268 return rte_flow_error_set(error, EINVAL,
13269 RTE_FLOW_ERROR_TYPE_ACTION,
13271 "Failed to get CT object.");
13272 if (mlx5_aso_ct_available(priv->sh, ct))
13273 return rte_flow_error_set(error, rte_errno,
13274 RTE_FLOW_ERROR_TYPE_ACTION,
13276 "CT is unavailable.");
13277 if (ct->is_original)
13278 dev_flow->dv.actions[actions_n] =
13279 ct->dr_action_orig;
13281 dev_flow->dv.actions[actions_n] =
13282 ct->dr_action_rply;
13283 if (flow->ct == 0) {
13284 flow->indirect_type =
13285 MLX5_INDIRECT_ACTION_TYPE_CT;
13286 flow->ct = owner_idx;
13287 __atomic_fetch_add(&ct->refcnt, 1,
13291 action_flags |= MLX5_FLOW_ACTION_CT;
13293 case RTE_FLOW_ACTION_TYPE_END:
13294 actions_end = true;
13295 if (mhdr_res->actions_num) {
13296 /* create modify action if needed. */
13297 if (flow_dv_modify_hdr_resource_register
13298 (dev, mhdr_res, dev_flow, error))
13300 dev_flow->dv.actions[modify_action_position] =
13301 handle->dvh.modify_hdr->action;
13304 * Handle AGE and COUNT action by single HW counter
13305 * when they are not shared.
13307 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13308 if ((non_shared_age && count) ||
13309 !(priv->sh->flow_hit_aso_en &&
13310 (attr->group || attr->transfer))) {
13311 /* Creates age by counters. */
13312 cnt_act = flow_dv_prepare_counter
13319 dev_flow->dv.actions[age_act_pos] =
13323 if (!flow->age && non_shared_age) {
13324 flow->age = flow_dv_aso_age_alloc
13328 flow_dv_aso_age_params_init
13330 non_shared_age->context ?
13331 non_shared_age->context :
13332 (void *)(uintptr_t)
13333 (dev_flow->flow_idx),
13334 non_shared_age->timeout);
13336 age_act = flow_aso_age_get_by_idx(dev,
13338 dev_flow->dv.actions[age_act_pos] =
13339 age_act->dr_action;
13341 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13343 * Create one count action, to be used
13344 * by all sub-flows.
13346 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13351 dev_flow->dv.actions[actions_n++] =
13357 if (mhdr_res->actions_num &&
13358 modify_action_position == UINT32_MAX)
13359 modify_action_position = actions_n++;
13361 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13362 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13363 int item_type = items->type;
13365 if (!mlx5_flow_os_item_supported(item_type))
13366 return rte_flow_error_set(error, ENOTSUP,
13367 RTE_FLOW_ERROR_TYPE_ITEM,
13368 NULL, "item not supported");
13369 switch (item_type) {
13370 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13371 flow_dv_translate_item_port_id
13372 (dev, match_mask, match_value, items, attr);
13373 last_item = MLX5_FLOW_ITEM_PORT_ID;
13375 case RTE_FLOW_ITEM_TYPE_ETH:
13376 flow_dv_translate_item_eth(match_mask, match_value,
13378 dev_flow->dv.group);
13379 matcher.priority = action_flags &
13380 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13381 !dev_flow->external ?
13382 MLX5_PRIORITY_MAP_L3 :
13383 MLX5_PRIORITY_MAP_L2;
13384 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13385 MLX5_FLOW_LAYER_OUTER_L2;
13387 case RTE_FLOW_ITEM_TYPE_VLAN:
13388 flow_dv_translate_item_vlan(dev_flow,
13389 match_mask, match_value,
13391 dev_flow->dv.group);
13392 matcher.priority = MLX5_PRIORITY_MAP_L2;
13393 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13394 MLX5_FLOW_LAYER_INNER_VLAN) :
13395 (MLX5_FLOW_LAYER_OUTER_L2 |
13396 MLX5_FLOW_LAYER_OUTER_VLAN);
13398 case RTE_FLOW_ITEM_TYPE_IPV4:
13399 mlx5_flow_tunnel_ip_check(items, next_protocol,
13400 &item_flags, &tunnel);
13401 flow_dv_translate_item_ipv4(match_mask, match_value,
13403 dev_flow->dv.group);
13404 matcher.priority = MLX5_PRIORITY_MAP_L3;
13405 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13406 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13407 if (items->mask != NULL &&
13408 ((const struct rte_flow_item_ipv4 *)
13409 items->mask)->hdr.next_proto_id) {
13411 ((const struct rte_flow_item_ipv4 *)
13412 (items->spec))->hdr.next_proto_id;
13414 ((const struct rte_flow_item_ipv4 *)
13415 (items->mask))->hdr.next_proto_id;
13417 /* Reset for inner layer. */
13418 next_protocol = 0xff;
13421 case RTE_FLOW_ITEM_TYPE_IPV6:
13422 mlx5_flow_tunnel_ip_check(items, next_protocol,
13423 &item_flags, &tunnel);
13424 flow_dv_translate_item_ipv6(match_mask, match_value,
13426 dev_flow->dv.group);
13427 matcher.priority = MLX5_PRIORITY_MAP_L3;
13428 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13429 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13430 if (items->mask != NULL &&
13431 ((const struct rte_flow_item_ipv6 *)
13432 items->mask)->hdr.proto) {
13434 ((const struct rte_flow_item_ipv6 *)
13435 items->spec)->hdr.proto;
13437 ((const struct rte_flow_item_ipv6 *)
13438 items->mask)->hdr.proto;
13440 /* Reset for inner layer. */
13441 next_protocol = 0xff;
13444 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13445 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13448 last_item = tunnel ?
13449 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13450 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13451 if (items->mask != NULL &&
13452 ((const struct rte_flow_item_ipv6_frag_ext *)
13453 items->mask)->hdr.next_header) {
13455 ((const struct rte_flow_item_ipv6_frag_ext *)
13456 items->spec)->hdr.next_header;
13458 ((const struct rte_flow_item_ipv6_frag_ext *)
13459 items->mask)->hdr.next_header;
13461 /* Reset for inner layer. */
13462 next_protocol = 0xff;
13465 case RTE_FLOW_ITEM_TYPE_TCP:
13466 flow_dv_translate_item_tcp(match_mask, match_value,
13468 matcher.priority = MLX5_PRIORITY_MAP_L4;
13469 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13470 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13472 case RTE_FLOW_ITEM_TYPE_UDP:
13473 flow_dv_translate_item_udp(match_mask, match_value,
13475 matcher.priority = MLX5_PRIORITY_MAP_L4;
13476 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13477 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13479 case RTE_FLOW_ITEM_TYPE_GRE:
13480 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13481 last_item = MLX5_FLOW_LAYER_GRE;
13482 tunnel_item = items;
13484 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13485 flow_dv_translate_item_gre_key(match_mask,
13486 match_value, items);
13487 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13489 case RTE_FLOW_ITEM_TYPE_NVGRE:
13490 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13491 last_item = MLX5_FLOW_LAYER_GRE;
13492 tunnel_item = items;
13494 case RTE_FLOW_ITEM_TYPE_VXLAN:
13495 flow_dv_translate_item_vxlan(dev, attr,
13496 match_mask, match_value,
13498 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13499 last_item = MLX5_FLOW_LAYER_VXLAN;
13501 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13502 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13503 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13504 tunnel_item = items;
13506 case RTE_FLOW_ITEM_TYPE_GENEVE:
13507 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13508 last_item = MLX5_FLOW_LAYER_GENEVE;
13509 tunnel_item = items;
13511 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13512 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13516 return rte_flow_error_set(error, -ret,
13517 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13518 "cannot create GENEVE TLV option");
13519 flow->geneve_tlv_option = 1;
13520 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13522 case RTE_FLOW_ITEM_TYPE_MPLS:
13523 flow_dv_translate_item_mpls(match_mask, match_value,
13524 items, last_item, tunnel);
13525 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13526 last_item = MLX5_FLOW_LAYER_MPLS;
13528 case RTE_FLOW_ITEM_TYPE_MARK:
13529 flow_dv_translate_item_mark(dev, match_mask,
13530 match_value, items);
13531 last_item = MLX5_FLOW_ITEM_MARK;
13533 case RTE_FLOW_ITEM_TYPE_META:
13534 flow_dv_translate_item_meta(dev, match_mask,
13535 match_value, attr, items);
13536 last_item = MLX5_FLOW_ITEM_METADATA;
13538 case RTE_FLOW_ITEM_TYPE_ICMP:
13539 flow_dv_translate_item_icmp(match_mask, match_value,
13541 last_item = MLX5_FLOW_LAYER_ICMP;
13543 case RTE_FLOW_ITEM_TYPE_ICMP6:
13544 flow_dv_translate_item_icmp6(match_mask, match_value,
13546 last_item = MLX5_FLOW_LAYER_ICMP6;
13548 case RTE_FLOW_ITEM_TYPE_TAG:
13549 flow_dv_translate_item_tag(dev, match_mask,
13550 match_value, items);
13551 last_item = MLX5_FLOW_ITEM_TAG;
13553 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13554 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13555 match_value, items);
13556 last_item = MLX5_FLOW_ITEM_TAG;
13558 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13559 flow_dv_translate_item_tx_queue(dev, match_mask,
13562 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13564 case RTE_FLOW_ITEM_TYPE_GTP:
13565 flow_dv_translate_item_gtp(match_mask, match_value,
13567 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13568 last_item = MLX5_FLOW_LAYER_GTP;
13570 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13571 ret = flow_dv_translate_item_gtp_psc(match_mask,
13575 return rte_flow_error_set(error, -ret,
13576 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13577 "cannot create GTP PSC item");
13578 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13580 case RTE_FLOW_ITEM_TYPE_ECPRI:
13581 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13582 /* Create it only the first time to be used. */
13583 ret = mlx5_flex_parser_ecpri_alloc(dev);
13585 return rte_flow_error_set
13587 RTE_FLOW_ERROR_TYPE_ITEM,
13589 "cannot create eCPRI parser");
13591 flow_dv_translate_item_ecpri(dev, match_mask,
13592 match_value, items,
13594 /* No other protocol should follow eCPRI layer. */
13595 last_item = MLX5_FLOW_LAYER_ECPRI;
13597 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13598 flow_dv_translate_item_integrity(items, integrity_items,
13601 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13602 flow_dv_translate_item_aso_ct(dev, match_mask,
13603 match_value, items);
13605 case RTE_FLOW_ITEM_TYPE_FLEX:
13606 flow_dv_translate_item_flex(dev, match_mask,
13607 match_value, items,
13608 dev_flow, tunnel != 0);
13609 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13610 MLX5_FLOW_ITEM_OUTER_FLEX;
13615 item_flags |= last_item;
13618 * When E-Switch mode is enabled, we have two cases where we need to
13619 * set the source port manually.
13620 * The first one, is in case of Nic steering rule, and the second is
13621 * E-Switch rule where no port_id item was found. In both cases
13622 * the source port is set according the current port in use.
13624 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13625 (priv->representor || priv->master)) {
13626 if (flow_dv_translate_item_port_id(dev, match_mask,
13627 match_value, NULL, attr))
13630 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13631 flow_dv_translate_item_integrity_post(match_mask, match_value,
13635 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13636 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13637 tunnel_item, item_flags);
13638 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13639 flow_dv_translate_item_geneve(match_mask, match_value,
13640 tunnel_item, item_flags);
13641 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13642 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13643 flow_dv_translate_item_gre(match_mask, match_value,
13644 tunnel_item, item_flags);
13645 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13646 flow_dv_translate_item_nvgre(match_mask, match_value,
13647 tunnel_item, item_flags);
13649 MLX5_ASSERT(false);
13651 #ifdef RTE_LIBRTE_MLX5_DEBUG
13652 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13653 dev_flow->dv.value.buf));
13656 * Layers may be already initialized from prefix flow if this dev_flow
13657 * is the suffix flow.
13659 handle->layers |= item_flags;
13660 if (action_flags & MLX5_FLOW_ACTION_RSS)
13661 flow_dv_hashfields_set(dev_flow, rss_desc);
13662 /* If has RSS action in the sample action, the Sample/Mirror resource
13663 * should be registered after the hash filed be update.
13665 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13666 ret = flow_dv_translate_action_sample(dev,
13675 ret = flow_dv_create_action_sample(dev,
13684 return rte_flow_error_set
13686 RTE_FLOW_ERROR_TYPE_ACTION,
13688 "cannot create sample action");
13689 if (num_of_dest > 1) {
13690 dev_flow->dv.actions[sample_act_pos] =
13691 dev_flow->dv.dest_array_res->action;
13693 dev_flow->dv.actions[sample_act_pos] =
13694 dev_flow->dv.sample_res->verbs_action;
13698 * For multiple destination (sample action with ratio=1), the encap
13699 * action and port id action will be combined into group action.
13700 * So need remove the original these actions in the flow and only
13701 * use the sample action instead of.
13703 if (num_of_dest > 1 &&
13704 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13706 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13708 for (i = 0; i < actions_n; i++) {
13709 if ((sample_act->dr_encap_action &&
13710 sample_act->dr_encap_action ==
13711 dev_flow->dv.actions[i]) ||
13712 (sample_act->dr_port_id_action &&
13713 sample_act->dr_port_id_action ==
13714 dev_flow->dv.actions[i]) ||
13715 (sample_act->dr_jump_action &&
13716 sample_act->dr_jump_action ==
13717 dev_flow->dv.actions[i]))
13719 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13721 memcpy((void *)dev_flow->dv.actions,
13722 (void *)temp_actions,
13723 tmp_actions_n * sizeof(void *));
13724 actions_n = tmp_actions_n;
13726 dev_flow->dv.actions_n = actions_n;
13727 dev_flow->act_flags = action_flags;
13728 if (wks->skip_matcher_reg)
13730 /* Register matcher. */
13731 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13732 matcher.mask.size);
13733 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13735 dev_flow->external);
13737 * When creating meter drop flow in drop table, using original
13738 * 5-tuple match, the matcher priority should be lower than
13741 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13742 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13743 matcher.priority <= MLX5_REG_BITS)
13744 matcher.priority += MLX5_REG_BITS;
13745 /* reserved field no needs to be set to 0 here. */
13746 tbl_key.is_fdb = attr->transfer;
13747 tbl_key.is_egress = attr->egress;
13748 tbl_key.level = dev_flow->dv.group;
13749 tbl_key.id = dev_flow->dv.table_id;
13750 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13751 tunnel, attr->group, error))
13757 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13760 * @param[in, out] action
13761 * Shred RSS action holding hash RX queue objects.
13762 * @param[in] hash_fields
13763 * Defines combination of packet fields to participate in RX hash.
13764 * @param[in] tunnel
13766 * @param[in] hrxq_idx
13767 * Hash RX queue index to set.
13770 * 0 on success, otherwise negative errno value.
13773 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13774 const uint64_t hash_fields,
13777 uint32_t *hrxqs = action->hrxq;
13779 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13780 case MLX5_RSS_HASH_IPV4:
13781 /* fall-through. */
13782 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13783 /* fall-through. */
13784 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13785 hrxqs[0] = hrxq_idx;
13787 case MLX5_RSS_HASH_IPV4_TCP:
13788 /* fall-through. */
13789 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13790 /* fall-through. */
13791 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13792 hrxqs[1] = hrxq_idx;
13794 case MLX5_RSS_HASH_IPV4_UDP:
13795 /* fall-through. */
13796 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13797 /* fall-through. */
13798 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13799 hrxqs[2] = hrxq_idx;
13801 case MLX5_RSS_HASH_IPV6:
13802 /* fall-through. */
13803 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13804 /* fall-through. */
13805 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13806 hrxqs[3] = hrxq_idx;
13808 case MLX5_RSS_HASH_IPV6_TCP:
13809 /* fall-through. */
13810 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13811 /* fall-through. */
13812 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13813 hrxqs[4] = hrxq_idx;
13815 case MLX5_RSS_HASH_IPV6_UDP:
13816 /* fall-through. */
13817 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13818 /* fall-through. */
13819 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13820 hrxqs[5] = hrxq_idx;
13822 case MLX5_RSS_HASH_NONE:
13823 hrxqs[6] = hrxq_idx;
13831 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13835 * Pointer to the Ethernet device structure.
13837 * Shared RSS action ID holding hash RX queue objects.
13838 * @param[in] hash_fields
13839 * Defines combination of packet fields to participate in RX hash.
13840 * @param[in] tunnel
13844 * Valid hash RX queue index, otherwise 0.
13847 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13848 const uint64_t hash_fields)
13850 struct mlx5_priv *priv = dev->data->dev_private;
13851 struct mlx5_shared_action_rss *shared_rss =
13852 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13853 const uint32_t *hrxqs = shared_rss->hrxq;
13855 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13856 case MLX5_RSS_HASH_IPV4:
13857 /* fall-through. */
13858 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13859 /* fall-through. */
13860 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13862 case MLX5_RSS_HASH_IPV4_TCP:
13863 /* fall-through. */
13864 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13865 /* fall-through. */
13866 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13868 case MLX5_RSS_HASH_IPV4_UDP:
13869 /* fall-through. */
13870 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13871 /* fall-through. */
13872 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13874 case MLX5_RSS_HASH_IPV6:
13875 /* fall-through. */
13876 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13877 /* fall-through. */
13878 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13880 case MLX5_RSS_HASH_IPV6_TCP:
13881 /* fall-through. */
13882 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13883 /* fall-through. */
13884 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13886 case MLX5_RSS_HASH_IPV6_UDP:
13887 /* fall-through. */
13888 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13889 /* fall-through. */
13890 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13892 case MLX5_RSS_HASH_NONE:
13901 * Apply the flow to the NIC, lock free,
13902 * (mutex should be acquired by caller).
13905 * Pointer to the Ethernet device structure.
13906 * @param[in, out] flow
13907 * Pointer to flow structure.
13908 * @param[out] error
13909 * Pointer to error structure.
13912 * 0 on success, a negative errno value otherwise and rte_errno is set.
13915 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13916 struct rte_flow_error *error)
13918 struct mlx5_flow_dv_workspace *dv;
13919 struct mlx5_flow_handle *dh;
13920 struct mlx5_flow_handle_dv *dv_h;
13921 struct mlx5_flow *dev_flow;
13922 struct mlx5_priv *priv = dev->data->dev_private;
13923 uint32_t handle_idx;
13927 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13928 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13932 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13933 dev_flow = &wks->flows[idx];
13934 dv = &dev_flow->dv;
13935 dh = dev_flow->handle;
13938 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13939 if (dv->transfer) {
13940 MLX5_ASSERT(priv->sh->dr_drop_action);
13941 dv->actions[n++] = priv->sh->dr_drop_action;
13943 #ifdef HAVE_MLX5DV_DR
13944 /* DR supports drop action placeholder. */
13945 MLX5_ASSERT(priv->sh->dr_drop_action);
13946 dv->actions[n++] = dv->group ?
13947 priv->sh->dr_drop_action :
13948 priv->root_drop_action;
13950 /* For DV we use the explicit drop queue. */
13951 MLX5_ASSERT(priv->drop_queue.hrxq);
13953 priv->drop_queue.hrxq->action;
13956 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13957 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13958 struct mlx5_hrxq *hrxq;
13961 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13966 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13967 "cannot get hash queue");
13970 dh->rix_hrxq = hrxq_idx;
13971 dv->actions[n++] = hrxq->action;
13972 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13973 struct mlx5_hrxq *hrxq = NULL;
13976 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13977 rss_desc->shared_rss,
13978 dev_flow->hash_fields);
13980 hrxq = mlx5_ipool_get
13981 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13986 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13987 "cannot get hash queue");
13990 dh->rix_srss = rss_desc->shared_rss;
13991 dv->actions[n++] = hrxq->action;
13992 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13993 if (!priv->sh->default_miss_action) {
13996 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13997 "default miss action not be created.");
14000 dv->actions[n++] = priv->sh->default_miss_action;
14002 misc_mask = flow_dv_matcher_enable(dv->value.buf);
14003 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
14004 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
14005 (void *)&dv->value, n,
14006 dv->actions, &dh->drv_flow);
14010 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14012 (!priv->config.allow_duplicate_pattern &&
14014 "duplicating pattern is not allowed" :
14015 "hardware refuses to create flow");
14018 if (priv->vmwa_context &&
14019 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14021 * The rule contains the VLAN pattern.
14022 * For VF we are going to create VLAN
14023 * interface to make hypervisor set correct
14024 * e-Switch vport context.
14026 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14031 err = rte_errno; /* Save rte_errno before cleanup. */
14032 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14033 handle_idx, dh, next) {
14034 /* hrxq is union, don't clear it if the flag is not set. */
14035 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14036 mlx5_hrxq_release(dev, dh->rix_hrxq);
14038 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14041 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14042 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14044 rte_errno = err; /* Restore rte_errno. */
14049 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14050 struct mlx5_list_entry *entry)
14052 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14056 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14057 mlx5_free(resource);
14061 * Release the flow matcher.
14064 * Pointer to Ethernet device.
14066 * Index to port ID action resource.
14069 * 1 while a reference on it exists, 0 when freed.
14072 flow_dv_matcher_release(struct rte_eth_dev *dev,
14073 struct mlx5_flow_handle *handle)
14075 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14076 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14077 typeof(*tbl), tbl);
14080 MLX5_ASSERT(matcher->matcher_object);
14081 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14082 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14087 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14089 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14090 struct mlx5_flow_dv_encap_decap_resource *res =
14091 container_of(entry, typeof(*res), entry);
14093 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14094 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14098 * Release an encap/decap resource.
14101 * Pointer to Ethernet device.
14102 * @param encap_decap_idx
14103 * Index of encap decap resource.
14106 * 1 while a reference on it exists, 0 when freed.
14109 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14110 uint32_t encap_decap_idx)
14112 struct mlx5_priv *priv = dev->data->dev_private;
14113 struct mlx5_flow_dv_encap_decap_resource *resource;
14115 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14119 MLX5_ASSERT(resource->action);
14120 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14124 * Release an jump to table action resource.
14127 * Pointer to Ethernet device.
14129 * Index to the jump action resource.
14132 * 1 while a reference on it exists, 0 when freed.
14135 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14138 struct mlx5_priv *priv = dev->data->dev_private;
14139 struct mlx5_flow_tbl_data_entry *tbl_data;
14141 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14145 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14149 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14151 struct mlx5_flow_dv_modify_hdr_resource *res =
14152 container_of(entry, typeof(*res), entry);
14153 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14155 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14156 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14160 * Release a modify-header resource.
14163 * Pointer to Ethernet device.
14165 * Pointer to mlx5_flow_handle.
14168 * 1 while a reference on it exists, 0 when freed.
14171 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14172 struct mlx5_flow_handle *handle)
14174 struct mlx5_priv *priv = dev->data->dev_private;
14175 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14177 MLX5_ASSERT(entry->action);
14178 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14182 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14184 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14185 struct mlx5_flow_dv_port_id_action_resource *resource =
14186 container_of(entry, typeof(*resource), entry);
14188 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14189 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14193 * Release port ID action resource.
14196 * Pointer to Ethernet device.
14198 * Pointer to mlx5_flow_handle.
14201 * 1 while a reference on it exists, 0 when freed.
14204 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14207 struct mlx5_priv *priv = dev->data->dev_private;
14208 struct mlx5_flow_dv_port_id_action_resource *resource;
14210 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14213 MLX5_ASSERT(resource->action);
14214 return mlx5_list_unregister(priv->sh->port_id_action_list,
14219 * Release shared RSS action resource.
14222 * Pointer to Ethernet device.
14224 * Shared RSS action index.
14227 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14229 struct mlx5_priv *priv = dev->data->dev_private;
14230 struct mlx5_shared_action_rss *shared_rss;
14232 shared_rss = mlx5_ipool_get
14233 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14234 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14238 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14240 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14241 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14242 container_of(entry, typeof(*resource), entry);
14244 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14245 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14249 * Release push vlan action resource.
14252 * Pointer to Ethernet device.
14254 * Pointer to mlx5_flow_handle.
14257 * 1 while a reference on it exists, 0 when freed.
14260 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14261 struct mlx5_flow_handle *handle)
14263 struct mlx5_priv *priv = dev->data->dev_private;
14264 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14265 uint32_t idx = handle->dvh.rix_push_vlan;
14267 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14270 MLX5_ASSERT(resource->action);
14271 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14276 * Release the fate resource.
14279 * Pointer to Ethernet device.
14281 * Pointer to mlx5_flow_handle.
14284 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14285 struct mlx5_flow_handle *handle)
14287 if (!handle->rix_fate)
14289 switch (handle->fate_action) {
14290 case MLX5_FLOW_FATE_QUEUE:
14291 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14292 mlx5_hrxq_release(dev, handle->rix_hrxq);
14294 case MLX5_FLOW_FATE_JUMP:
14295 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14297 case MLX5_FLOW_FATE_PORT_ID:
14298 flow_dv_port_id_action_resource_release(dev,
14299 handle->rix_port_id_action);
14302 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14305 handle->rix_fate = 0;
14309 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14310 struct mlx5_list_entry *entry)
14312 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14315 struct rte_eth_dev *dev = resource->dev;
14316 struct mlx5_priv *priv = dev->data->dev_private;
14318 if (resource->verbs_action)
14319 claim_zero(mlx5_flow_os_destroy_flow_action
14320 (resource->verbs_action));
14321 if (resource->normal_path_tbl)
14322 flow_dv_tbl_resource_release(MLX5_SH(dev),
14323 resource->normal_path_tbl);
14324 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14325 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14326 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14330 * Release an sample resource.
14333 * Pointer to Ethernet device.
14335 * Pointer to mlx5_flow_handle.
14338 * 1 while a reference on it exists, 0 when freed.
14341 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14342 struct mlx5_flow_handle *handle)
14344 struct mlx5_priv *priv = dev->data->dev_private;
14345 struct mlx5_flow_dv_sample_resource *resource;
14347 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14348 handle->dvh.rix_sample);
14351 MLX5_ASSERT(resource->verbs_action);
14352 return mlx5_list_unregister(priv->sh->sample_action_list,
14357 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14358 struct mlx5_list_entry *entry)
14360 struct mlx5_flow_dv_dest_array_resource *resource =
14361 container_of(entry, typeof(*resource), entry);
14362 struct rte_eth_dev *dev = resource->dev;
14363 struct mlx5_priv *priv = dev->data->dev_private;
14366 MLX5_ASSERT(resource->action);
14367 if (resource->action)
14368 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14369 for (; i < resource->num_of_dest; i++)
14370 flow_dv_sample_sub_actions_release(dev,
14371 &resource->sample_idx[i]);
14372 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14373 DRV_LOG(DEBUG, "destination array resource %p: removed",
14378 * Release an destination array resource.
14381 * Pointer to Ethernet device.
14383 * Pointer to mlx5_flow_handle.
14386 * 1 while a reference on it exists, 0 when freed.
14389 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14390 struct mlx5_flow_handle *handle)
14392 struct mlx5_priv *priv = dev->data->dev_private;
14393 struct mlx5_flow_dv_dest_array_resource *resource;
14395 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14396 handle->dvh.rix_dest_array);
14399 MLX5_ASSERT(resource->action);
14400 return mlx5_list_unregister(priv->sh->dest_array_list,
14405 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14407 struct mlx5_priv *priv = dev->data->dev_private;
14408 struct mlx5_dev_ctx_shared *sh = priv->sh;
14409 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14410 sh->geneve_tlv_option_resource;
14411 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14412 if (geneve_opt_resource) {
14413 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14414 __ATOMIC_RELAXED))) {
14415 claim_zero(mlx5_devx_cmd_destroy
14416 (geneve_opt_resource->obj));
14417 mlx5_free(sh->geneve_tlv_option_resource);
14418 sh->geneve_tlv_option_resource = NULL;
14421 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14425 * Remove the flow from the NIC but keeps it in memory.
14426 * Lock free, (mutex should be acquired by caller).
14429 * Pointer to Ethernet device.
14430 * @param[in, out] flow
14431 * Pointer to flow structure.
14434 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14436 struct mlx5_flow_handle *dh;
14437 uint32_t handle_idx;
14438 struct mlx5_priv *priv = dev->data->dev_private;
14442 handle_idx = flow->dev_handles;
14443 while (handle_idx) {
14444 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14448 if (dh->drv_flow) {
14449 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14450 dh->drv_flow = NULL;
14452 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14453 flow_dv_fate_resource_release(dev, dh);
14454 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14455 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14456 handle_idx = dh->next.next;
14461 * Remove the flow from the NIC and the memory.
14462 * Lock free, (mutex should be acquired by caller).
14465 * Pointer to the Ethernet device structure.
14466 * @param[in, out] flow
14467 * Pointer to flow structure.
14470 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14472 struct mlx5_flow_handle *dev_handle;
14473 struct mlx5_priv *priv = dev->data->dev_private;
14474 struct mlx5_flow_meter_info *fm = NULL;
14479 flow_dv_remove(dev, flow);
14480 if (flow->counter) {
14481 flow_dv_counter_free(dev, flow->counter);
14485 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14487 mlx5_flow_meter_detach(priv, fm);
14490 /* Keep the current age handling by default. */
14491 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14492 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14493 else if (flow->age)
14494 flow_dv_aso_age_release(dev, flow->age);
14495 if (flow->geneve_tlv_option) {
14496 flow_dv_geneve_tlv_option_resource_release(dev);
14497 flow->geneve_tlv_option = 0;
14499 while (flow->dev_handles) {
14500 uint32_t tmp_idx = flow->dev_handles;
14502 dev_handle = mlx5_ipool_get(priv->sh->ipool
14503 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14506 flow->dev_handles = dev_handle->next.next;
14507 while (dev_handle->flex_item) {
14508 int index = rte_bsf32(dev_handle->flex_item);
14510 mlx5_flex_release_index(dev, index);
14511 dev_handle->flex_item &= ~RTE_BIT32(index);
14513 if (dev_handle->dvh.matcher)
14514 flow_dv_matcher_release(dev, dev_handle);
14515 if (dev_handle->dvh.rix_sample)
14516 flow_dv_sample_resource_release(dev, dev_handle);
14517 if (dev_handle->dvh.rix_dest_array)
14518 flow_dv_dest_array_resource_release(dev, dev_handle);
14519 if (dev_handle->dvh.rix_encap_decap)
14520 flow_dv_encap_decap_resource_release(dev,
14521 dev_handle->dvh.rix_encap_decap);
14522 if (dev_handle->dvh.modify_hdr)
14523 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14524 if (dev_handle->dvh.rix_push_vlan)
14525 flow_dv_push_vlan_action_resource_release(dev,
14527 if (dev_handle->dvh.rix_tag)
14528 flow_dv_tag_release(dev,
14529 dev_handle->dvh.rix_tag);
14530 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14531 flow_dv_fate_resource_release(dev, dev_handle);
14533 srss = dev_handle->rix_srss;
14534 if (fm && dev_handle->is_meter_flow_id &&
14535 dev_handle->split_flow_id)
14536 mlx5_ipool_free(fm->flow_ipool,
14537 dev_handle->split_flow_id);
14538 else if (dev_handle->split_flow_id &&
14539 !dev_handle->is_meter_flow_id)
14540 mlx5_ipool_free(priv->sh->ipool
14541 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14542 dev_handle->split_flow_id);
14543 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14547 flow_dv_shared_rss_action_release(dev, srss);
14551 * Release array of hash RX queue objects.
14555 * Pointer to the Ethernet device structure.
14556 * @param[in, out] hrxqs
14557 * Array of hash RX queue objects.
14560 * Total number of references to hash RX queue objects in *hrxqs* array
14561 * after this operation.
14564 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14565 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14570 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14571 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14581 * Release all hash RX queue objects representing shared RSS action.
14584 * Pointer to the Ethernet device structure.
14585 * @param[in, out] action
14586 * Shared RSS action to remove hash RX queue objects from.
14589 * Total number of references to hash RX queue objects stored in *action*
14590 * after this operation.
14591 * Expected to be 0 if no external references held.
14594 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14595 struct mlx5_shared_action_rss *shared_rss)
14597 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14601 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14604 * Only one hash value is available for one L3+L4 combination:
14606 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14607 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14608 * same slot in mlx5_rss_hash_fields.
14611 * Pointer to the shared action RSS conf.
14612 * @param[in, out] hash_field
14613 * hash_field variable needed to be adjusted.
14619 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14620 uint64_t *hash_field)
14622 uint64_t rss_types = rss->origin.types;
14624 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14625 case MLX5_RSS_HASH_IPV4:
14626 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14627 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14628 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14629 *hash_field |= IBV_RX_HASH_DST_IPV4;
14630 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14631 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14633 *hash_field |= MLX5_RSS_HASH_IPV4;
14636 case MLX5_RSS_HASH_IPV6:
14637 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14638 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14639 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14640 *hash_field |= IBV_RX_HASH_DST_IPV6;
14641 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14642 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14644 *hash_field |= MLX5_RSS_HASH_IPV6;
14647 case MLX5_RSS_HASH_IPV4_UDP:
14648 /* fall-through. */
14649 case MLX5_RSS_HASH_IPV6_UDP:
14650 if (rss_types & RTE_ETH_RSS_UDP) {
14651 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14652 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14653 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14654 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14655 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14657 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14660 case MLX5_RSS_HASH_IPV4_TCP:
14661 /* fall-through. */
14662 case MLX5_RSS_HASH_IPV6_TCP:
14663 if (rss_types & RTE_ETH_RSS_TCP) {
14664 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14665 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14666 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14667 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14668 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14670 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14679 * Setup shared RSS action.
14680 * Prepare set of hash RX queue objects sufficient to handle all valid
14681 * hash_fields combinations (see enum ibv_rx_hash_fields).
14684 * Pointer to the Ethernet device structure.
14685 * @param[in] action_idx
14686 * Shared RSS action ipool index.
14687 * @param[in, out] action
14688 * Partially initialized shared RSS action.
14689 * @param[out] error
14690 * Perform verbose error reporting if not NULL. Initialized in case of
14694 * 0 on success, otherwise negative errno value.
14697 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14698 uint32_t action_idx,
14699 struct mlx5_shared_action_rss *shared_rss,
14700 struct rte_flow_error *error)
14702 struct mlx5_flow_rss_desc rss_desc = { 0 };
14706 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl,
14707 !!dev->data->dev_started)) {
14708 return rte_flow_error_set(error, rte_errno,
14709 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14710 "cannot setup indirection table");
14712 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14713 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14714 rss_desc.const_q = shared_rss->origin.queue;
14715 rss_desc.queue_num = shared_rss->origin.queue_num;
14716 /* Set non-zero value to indicate a shared RSS. */
14717 rss_desc.shared_rss = action_idx;
14718 rss_desc.ind_tbl = shared_rss->ind_tbl;
14719 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14721 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14724 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14725 if (shared_rss->origin.level > 1) {
14726 hash_fields |= IBV_RX_HASH_INNER;
14729 rss_desc.tunnel = tunnel;
14730 rss_desc.hash_fields = hash_fields;
14731 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14735 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14736 "cannot get hash queue");
14737 goto error_hrxq_new;
14739 err = __flow_dv_action_rss_hrxq_set
14740 (shared_rss, hash_fields, hrxq_idx);
14746 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14747 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true, true))
14748 shared_rss->ind_tbl = NULL;
14754 * Create shared RSS action.
14757 * Pointer to the Ethernet device structure.
14759 * Shared action configuration.
14761 * RSS action specification used to create shared action.
14762 * @param[out] error
14763 * Perform verbose error reporting if not NULL. Initialized in case of
14767 * A valid shared action ID in case of success, 0 otherwise and
14768 * rte_errno is set.
14771 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14772 const struct rte_flow_indir_action_conf *conf,
14773 const struct rte_flow_action_rss *rss,
14774 struct rte_flow_error *error)
14776 struct mlx5_priv *priv = dev->data->dev_private;
14777 struct mlx5_shared_action_rss *shared_rss = NULL;
14778 void *queue = NULL;
14779 struct rte_flow_action_rss *origin;
14780 const uint8_t *rss_key;
14781 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14784 RTE_SET_USED(conf);
14785 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14787 shared_rss = mlx5_ipool_zmalloc
14788 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14789 if (!shared_rss || !queue) {
14790 rte_flow_error_set(error, ENOMEM,
14791 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14792 "cannot allocate resource memory");
14793 goto error_rss_init;
14795 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14796 rte_flow_error_set(error, E2BIG,
14797 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14798 "rss action number out of range");
14799 goto error_rss_init;
14801 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14802 sizeof(*shared_rss->ind_tbl),
14804 if (!shared_rss->ind_tbl) {
14805 rte_flow_error_set(error, ENOMEM,
14806 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14807 "cannot allocate resource memory");
14808 goto error_rss_init;
14810 memcpy(queue, rss->queue, queue_size);
14811 shared_rss->ind_tbl->queues = queue;
14812 shared_rss->ind_tbl->queues_n = rss->queue_num;
14813 origin = &shared_rss->origin;
14814 origin->func = rss->func;
14815 origin->level = rss->level;
14816 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14817 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14818 /* NULL RSS key indicates default RSS key. */
14819 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14820 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14821 origin->key = &shared_rss->key[0];
14822 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14823 origin->queue = queue;
14824 origin->queue_num = rss->queue_num;
14825 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14826 goto error_rss_init;
14827 rte_spinlock_init(&shared_rss->action_rss_sl);
14828 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14829 rte_spinlock_lock(&priv->shared_act_sl);
14830 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14831 &priv->rss_shared_actions, idx, shared_rss, next);
14832 rte_spinlock_unlock(&priv->shared_act_sl);
14836 if (shared_rss->ind_tbl)
14837 mlx5_free(shared_rss->ind_tbl);
14838 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14847 * Destroy the shared RSS action.
14848 * Release related hash RX queue objects.
14851 * Pointer to the Ethernet device structure.
14853 * The shared RSS action object ID to be removed.
14854 * @param[out] error
14855 * Perform verbose error reporting if not NULL. Initialized in case of
14859 * 0 on success, otherwise negative errno value.
14862 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14863 struct rte_flow_error *error)
14865 struct mlx5_priv *priv = dev->data->dev_private;
14866 struct mlx5_shared_action_rss *shared_rss =
14867 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14868 uint32_t old_refcnt = 1;
14870 uint16_t *queue = NULL;
14873 return rte_flow_error_set(error, EINVAL,
14874 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14875 "invalid shared action");
14876 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14877 0, 0, __ATOMIC_ACQUIRE,
14879 return rte_flow_error_set(error, EBUSY,
14880 RTE_FLOW_ERROR_TYPE_ACTION,
14882 "shared rss has references");
14883 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14885 return rte_flow_error_set(error, EBUSY,
14886 RTE_FLOW_ERROR_TYPE_ACTION,
14888 "shared rss hrxq has references");
14889 queue = shared_rss->ind_tbl->queues;
14890 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true,
14891 !!dev->data->dev_started);
14893 return rte_flow_error_set(error, EBUSY,
14894 RTE_FLOW_ERROR_TYPE_ACTION,
14896 "shared rss indirection table has"
14899 rte_spinlock_lock(&priv->shared_act_sl);
14900 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14901 &priv->rss_shared_actions, idx, shared_rss, next);
14902 rte_spinlock_unlock(&priv->shared_act_sl);
14903 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14909 * Create indirect action, lock free,
14910 * (mutex should be acquired by caller).
14911 * Dispatcher for action type specific call.
14914 * Pointer to the Ethernet device structure.
14916 * Shared action configuration.
14917 * @param[in] action
14918 * Action specification used to create indirect action.
14919 * @param[out] error
14920 * Perform verbose error reporting if not NULL. Initialized in case of
14924 * A valid shared action handle in case of success, NULL otherwise and
14925 * rte_errno is set.
14927 static struct rte_flow_action_handle *
14928 flow_dv_action_create(struct rte_eth_dev *dev,
14929 const struct rte_flow_indir_action_conf *conf,
14930 const struct rte_flow_action *action,
14931 struct rte_flow_error *err)
14933 struct mlx5_priv *priv = dev->data->dev_private;
14934 uint32_t age_idx = 0;
14938 switch (action->type) {
14939 case RTE_FLOW_ACTION_TYPE_RSS:
14940 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14941 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14942 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14944 case RTE_FLOW_ACTION_TYPE_AGE:
14945 age_idx = flow_dv_aso_age_alloc(dev, err);
14950 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14951 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14952 flow_dv_aso_age_params_init(dev, age_idx,
14953 ((const struct rte_flow_action_age *)
14954 action->conf)->context ?
14955 ((const struct rte_flow_action_age *)
14956 action->conf)->context :
14957 (void *)(uintptr_t)idx,
14958 ((const struct rte_flow_action_age *)
14959 action->conf)->timeout);
14962 case RTE_FLOW_ACTION_TYPE_COUNT:
14963 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14964 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14965 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14967 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14968 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14970 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14973 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14974 NULL, "action type not supported");
14977 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14981 * Destroy the indirect action.
14982 * Release action related resources on the NIC and the memory.
14983 * Lock free, (mutex should be acquired by caller).
14984 * Dispatcher for action type specific call.
14987 * Pointer to the Ethernet device structure.
14988 * @param[in] handle
14989 * The indirect action object handle to be removed.
14990 * @param[out] error
14991 * Perform verbose error reporting if not NULL. Initialized in case of
14995 * 0 on success, otherwise negative errno value.
14998 flow_dv_action_destroy(struct rte_eth_dev *dev,
14999 struct rte_flow_action_handle *handle,
15000 struct rte_flow_error *error)
15002 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15003 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15004 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15005 struct mlx5_flow_counter *cnt;
15006 uint32_t no_flow_refcnt = 1;
15010 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15011 return __flow_dv_action_rss_release(dev, idx, error);
15012 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15013 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15014 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15015 &no_flow_refcnt, 1, false,
15018 return rte_flow_error_set(error, EBUSY,
15019 RTE_FLOW_ERROR_TYPE_ACTION,
15021 "Indirect count action has references");
15022 flow_dv_counter_free(dev, idx);
15024 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15025 ret = flow_dv_aso_age_release(dev, idx);
15028 * In this case, the last flow has a reference will
15029 * actually release the age action.
15031 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15032 " released with references %d.", idx, ret);
15034 case MLX5_INDIRECT_ACTION_TYPE_CT:
15035 ret = flow_dv_aso_ct_release(dev, idx, error);
15039 DRV_LOG(DEBUG, "Connection tracking object %u still "
15040 "has references %d.", idx, ret);
15043 return rte_flow_error_set(error, ENOTSUP,
15044 RTE_FLOW_ERROR_TYPE_ACTION,
15046 "action type not supported");
15051 * Updates in place shared RSS action configuration.
15054 * Pointer to the Ethernet device structure.
15056 * The shared RSS action object ID to be updated.
15057 * @param[in] action_conf
15058 * RSS action specification used to modify *shared_rss*.
15059 * @param[out] error
15060 * Perform verbose error reporting if not NULL. Initialized in case of
15064 * 0 on success, otherwise negative errno value.
15065 * @note: currently only support update of RSS queues.
15068 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15069 const struct rte_flow_action_rss *action_conf,
15070 struct rte_flow_error *error)
15072 struct mlx5_priv *priv = dev->data->dev_private;
15073 struct mlx5_shared_action_rss *shared_rss =
15074 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15076 void *queue = NULL;
15077 uint16_t *queue_old = NULL;
15078 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15079 bool dev_started = !!dev->data->dev_started;
15082 return rte_flow_error_set(error, EINVAL,
15083 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15084 "invalid shared action to update");
15085 if (priv->obj_ops.ind_table_modify == NULL)
15086 return rte_flow_error_set(error, ENOTSUP,
15087 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15088 "cannot modify indirection table");
15089 queue = mlx5_malloc(MLX5_MEM_ZERO,
15090 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15093 return rte_flow_error_set(error, ENOMEM,
15094 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15096 "cannot allocate resource memory");
15097 memcpy(queue, action_conf->queue, queue_size);
15098 MLX5_ASSERT(shared_rss->ind_tbl);
15099 rte_spinlock_lock(&shared_rss->action_rss_sl);
15100 queue_old = shared_rss->ind_tbl->queues;
15101 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15102 queue, action_conf->queue_num,
15103 true /* standalone */,
15104 dev_started /* ref_new_qs */,
15105 dev_started /* deref_old_qs */);
15108 ret = rte_flow_error_set(error, rte_errno,
15109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15110 "cannot update indirection table");
15112 mlx5_free(queue_old);
15113 shared_rss->origin.queue = queue;
15114 shared_rss->origin.queue_num = action_conf->queue_num;
15116 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15121 * Updates in place conntrack context or direction.
15122 * Context update should be synchronized.
15125 * Pointer to the Ethernet device structure.
15127 * The conntrack object ID to be updated.
15128 * @param[in] update
15129 * Pointer to the structure of information to update.
15130 * @param[out] error
15131 * Perform verbose error reporting if not NULL. Initialized in case of
15135 * 0 on success, otherwise negative errno value.
15138 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15139 const struct rte_flow_modify_conntrack *update,
15140 struct rte_flow_error *error)
15142 struct mlx5_priv *priv = dev->data->dev_private;
15143 struct mlx5_aso_ct_action *ct;
15144 const struct rte_flow_action_conntrack *new_prf;
15146 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15149 if (PORT_ID(priv) != owner)
15150 return rte_flow_error_set(error, EACCES,
15151 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15153 "CT object owned by another port");
15154 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15155 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15157 return rte_flow_error_set(error, ENOMEM,
15158 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15160 "CT object is inactive");
15161 new_prf = &update->new_ct;
15162 if (update->direction)
15163 ct->is_original = !!new_prf->is_original_dir;
15164 if (update->state) {
15165 /* Only validate the profile when it needs to be updated. */
15166 ret = mlx5_validate_action_ct(dev, new_prf, error);
15169 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15171 return rte_flow_error_set(error, EIO,
15172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15174 "Failed to send CT context update WQE");
15175 /* Block until ready or a failure. */
15176 ret = mlx5_aso_ct_available(priv->sh, ct);
15178 rte_flow_error_set(error, rte_errno,
15179 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15181 "Timeout to get the CT update");
15187 * Updates in place shared action configuration, lock free,
15188 * (mutex should be acquired by caller).
15191 * Pointer to the Ethernet device structure.
15192 * @param[in] handle
15193 * The indirect action object handle to be updated.
15194 * @param[in] update
15195 * Action specification used to modify the action pointed by *handle*.
15196 * *update* could be of same type with the action pointed by the *handle*
15197 * handle argument, or some other structures like a wrapper, depending on
15198 * the indirect action type.
15199 * @param[out] error
15200 * Perform verbose error reporting if not NULL. Initialized in case of
15204 * 0 on success, otherwise negative errno value.
15207 flow_dv_action_update(struct rte_eth_dev *dev,
15208 struct rte_flow_action_handle *handle,
15209 const void *update,
15210 struct rte_flow_error *err)
15212 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15213 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15214 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15215 const void *action_conf;
15218 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15219 action_conf = ((const struct rte_flow_action *)update)->conf;
15220 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15221 case MLX5_INDIRECT_ACTION_TYPE_CT:
15222 return __flow_dv_action_ct_update(dev, idx, update, err);
15224 return rte_flow_error_set(err, ENOTSUP,
15225 RTE_FLOW_ERROR_TYPE_ACTION,
15227 "action type update not supported");
15232 * Destroy the meter sub policy table rules.
15233 * Lock free, (mutex should be acquired by caller).
15236 * Pointer to Ethernet device.
15237 * @param[in] sub_policy
15238 * Pointer to meter sub policy table.
15241 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15242 struct mlx5_flow_meter_sub_policy *sub_policy)
15244 struct mlx5_priv *priv = dev->data->dev_private;
15245 struct mlx5_flow_tbl_data_entry *tbl;
15246 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15247 struct mlx5_flow_meter_info *next_fm;
15248 struct mlx5_sub_policy_color_rule *color_rule;
15252 for (i = 0; i < RTE_COLORS; i++) {
15254 if (i == RTE_COLOR_GREEN && policy &&
15255 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15256 next_fm = mlx5_flow_meter_find(priv,
15257 policy->act_cnt[i].next_mtr_id, NULL);
15258 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15260 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15261 tbl = container_of(color_rule->matcher->tbl,
15262 typeof(*tbl), tbl);
15263 mlx5_list_unregister(tbl->matchers,
15264 &color_rule->matcher->entry);
15265 TAILQ_REMOVE(&sub_policy->color_rules[i],
15266 color_rule, next_port);
15267 mlx5_free(color_rule);
15269 mlx5_flow_meter_detach(priv, next_fm);
15272 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15273 if (sub_policy->rix_hrxq[i]) {
15274 if (policy && !policy->is_hierarchy)
15275 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15276 sub_policy->rix_hrxq[i] = 0;
15278 if (sub_policy->jump_tbl[i]) {
15279 flow_dv_tbl_resource_release(MLX5_SH(dev),
15280 sub_policy->jump_tbl[i]);
15281 sub_policy->jump_tbl[i] = NULL;
15284 if (sub_policy->tbl_rsc) {
15285 flow_dv_tbl_resource_release(MLX5_SH(dev),
15286 sub_policy->tbl_rsc);
15287 sub_policy->tbl_rsc = NULL;
15292 * Destroy policy rules, lock free,
15293 * (mutex should be acquired by caller).
15294 * Dispatcher for action type specific call.
15297 * Pointer to the Ethernet device structure.
15298 * @param[in] mtr_policy
15299 * Meter policy struct.
15302 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15303 struct mlx5_flow_meter_policy *mtr_policy)
15306 struct mlx5_flow_meter_sub_policy *sub_policy;
15307 uint16_t sub_policy_num;
15309 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15310 sub_policy_num = (mtr_policy->sub_policy_num >>
15311 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15312 MLX5_MTR_SUB_POLICY_NUM_MASK;
15313 for (j = 0; j < sub_policy_num; j++) {
15314 sub_policy = mtr_policy->sub_policys[i][j];
15316 __flow_dv_destroy_sub_policy_rules(dev,
15323 * Destroy policy action, lock free,
15324 * (mutex should be acquired by caller).
15325 * Dispatcher for action type specific call.
15328 * Pointer to the Ethernet device structure.
15329 * @param[in] mtr_policy
15330 * Meter policy struct.
15333 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15334 struct mlx5_flow_meter_policy *mtr_policy)
15336 struct rte_flow_action *rss_action;
15337 struct mlx5_flow_handle dev_handle;
15340 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15341 if (mtr_policy->act_cnt[i].rix_mark) {
15342 flow_dv_tag_release(dev,
15343 mtr_policy->act_cnt[i].rix_mark);
15344 mtr_policy->act_cnt[i].rix_mark = 0;
15346 if (mtr_policy->act_cnt[i].modify_hdr) {
15347 dev_handle.dvh.modify_hdr =
15348 mtr_policy->act_cnt[i].modify_hdr;
15349 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15351 switch (mtr_policy->act_cnt[i].fate_action) {
15352 case MLX5_FLOW_FATE_SHARED_RSS:
15353 rss_action = mtr_policy->act_cnt[i].rss;
15354 mlx5_free(rss_action);
15356 case MLX5_FLOW_FATE_PORT_ID:
15357 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15358 flow_dv_port_id_action_resource_release(dev,
15359 mtr_policy->act_cnt[i].rix_port_id_action);
15360 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15363 case MLX5_FLOW_FATE_DROP:
15364 case MLX5_FLOW_FATE_JUMP:
15365 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15366 mtr_policy->act_cnt[i].dr_jump_action[j] =
15370 /*Queue action do nothing*/
15374 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15375 mtr_policy->dr_drop_action[j] = NULL;
15379 * Create policy action per domain, lock free,
15380 * (mutex should be acquired by caller).
15381 * Dispatcher for action type specific call.
15384 * Pointer to the Ethernet device structure.
15385 * @param[in] mtr_policy
15386 * Meter policy struct.
15387 * @param[in] action
15388 * Action specification used to create meter actions.
15389 * @param[out] error
15390 * Perform verbose error reporting if not NULL. Initialized in case of
15394 * 0 on success, otherwise negative errno value.
15397 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15398 struct mlx5_flow_meter_policy *mtr_policy,
15399 const struct rte_flow_action *actions[RTE_COLORS],
15400 enum mlx5_meter_domain domain,
15401 struct rte_mtr_error *error)
15403 struct mlx5_priv *priv = dev->data->dev_private;
15404 struct rte_flow_error flow_err;
15405 const struct rte_flow_action *act;
15406 uint64_t action_flags;
15407 struct mlx5_flow_handle dh;
15408 struct mlx5_flow dev_flow;
15409 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15411 uint8_t egress, transfer;
15412 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15414 struct mlx5_flow_dv_modify_hdr_resource res;
15415 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15416 sizeof(struct mlx5_modification_cmd) *
15417 (MLX5_MAX_MODIFY_NUM + 1)];
15419 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15421 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15422 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15423 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15424 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15425 memset(&port_id_action, 0,
15426 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15427 memset(mhdr_res, 0, sizeof(*mhdr_res));
15428 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15429 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15430 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15431 dev_flow.handle = &dh;
15432 dev_flow.dv.port_id_action = &port_id_action;
15433 dev_flow.external = true;
15434 for (i = 0; i < RTE_COLORS; i++) {
15435 if (i < MLX5_MTR_RTE_COLORS)
15436 act_cnt = &mtr_policy->act_cnt[i];
15437 /* Skip the color policy actions creation. */
15438 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15439 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15442 for (act = actions[i];
15443 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15444 switch (act->type) {
15445 case RTE_FLOW_ACTION_TYPE_MARK:
15447 uint32_t tag_be = mlx5_flow_mark_set
15448 (((const struct rte_flow_action_mark *)
15451 if (i >= MLX5_MTR_RTE_COLORS)
15452 return -rte_mtr_error_set(error,
15454 RTE_MTR_ERROR_TYPE_METER_POLICY,
15456 "cannot create policy "
15457 "mark action for this color");
15458 dev_flow.handle->mark = 1;
15459 if (flow_dv_tag_resource_register(dev, tag_be,
15460 &dev_flow, &flow_err))
15461 return -rte_mtr_error_set(error,
15463 RTE_MTR_ERROR_TYPE_METER_POLICY,
15465 "cannot setup policy mark action");
15466 MLX5_ASSERT(dev_flow.dv.tag_resource);
15467 act_cnt->rix_mark =
15468 dev_flow.handle->dvh.rix_tag;
15469 action_flags |= MLX5_FLOW_ACTION_MARK;
15472 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15473 if (i >= MLX5_MTR_RTE_COLORS)
15474 return -rte_mtr_error_set(error,
15476 RTE_MTR_ERROR_TYPE_METER_POLICY,
15478 "cannot create policy "
15479 "set tag action for this color");
15480 if (flow_dv_convert_action_set_tag
15482 (const struct rte_flow_action_set_tag *)
15483 act->conf, &flow_err))
15484 return -rte_mtr_error_set(error,
15486 RTE_MTR_ERROR_TYPE_METER_POLICY,
15487 NULL, "cannot convert policy "
15489 if (!mhdr_res->actions_num)
15490 return -rte_mtr_error_set(error,
15492 RTE_MTR_ERROR_TYPE_METER_POLICY,
15493 NULL, "cannot find policy "
15495 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15497 case RTE_FLOW_ACTION_TYPE_DROP:
15499 struct mlx5_flow_mtr_mng *mtrmng =
15501 struct mlx5_flow_tbl_data_entry *tbl_data;
15504 * Create the drop table with
15505 * METER DROP level.
15507 if (!mtrmng->drop_tbl[domain]) {
15508 mtrmng->drop_tbl[domain] =
15509 flow_dv_tbl_resource_get(dev,
15510 MLX5_FLOW_TABLE_LEVEL_METER,
15511 egress, transfer, false, NULL, 0,
15512 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15513 if (!mtrmng->drop_tbl[domain])
15514 return -rte_mtr_error_set
15516 RTE_MTR_ERROR_TYPE_METER_POLICY,
15518 "Failed to create meter drop table");
15520 tbl_data = container_of
15521 (mtrmng->drop_tbl[domain],
15522 struct mlx5_flow_tbl_data_entry, tbl);
15523 if (i < MLX5_MTR_RTE_COLORS) {
15524 act_cnt->dr_jump_action[domain] =
15525 tbl_data->jump.action;
15526 act_cnt->fate_action =
15527 MLX5_FLOW_FATE_DROP;
15529 if (i == RTE_COLOR_RED)
15530 mtr_policy->dr_drop_action[domain] =
15531 tbl_data->jump.action;
15532 action_flags |= MLX5_FLOW_ACTION_DROP;
15535 case RTE_FLOW_ACTION_TYPE_QUEUE:
15537 if (i >= MLX5_MTR_RTE_COLORS)
15538 return -rte_mtr_error_set(error,
15540 RTE_MTR_ERROR_TYPE_METER_POLICY,
15541 NULL, "cannot create policy "
15542 "fate queue for this color");
15544 ((const struct rte_flow_action_queue *)
15545 (act->conf))->index;
15546 act_cnt->fate_action =
15547 MLX5_FLOW_FATE_QUEUE;
15548 dev_flow.handle->fate_action =
15549 MLX5_FLOW_FATE_QUEUE;
15550 mtr_policy->is_queue = 1;
15551 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15554 case RTE_FLOW_ACTION_TYPE_RSS:
15558 if (i >= MLX5_MTR_RTE_COLORS)
15559 return -rte_mtr_error_set(error,
15561 RTE_MTR_ERROR_TYPE_METER_POLICY,
15563 "cannot create policy "
15564 "rss action for this color");
15566 * Save RSS conf into policy struct
15567 * for translate stage.
15569 rss_size = (int)rte_flow_conv
15570 (RTE_FLOW_CONV_OP_ACTION,
15571 NULL, 0, act, &flow_err);
15573 return -rte_mtr_error_set(error,
15575 RTE_MTR_ERROR_TYPE_METER_POLICY,
15576 NULL, "Get the wrong "
15577 "rss action struct size");
15578 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15579 rss_size, 0, SOCKET_ID_ANY);
15581 return -rte_mtr_error_set(error,
15583 RTE_MTR_ERROR_TYPE_METER_POLICY,
15585 "Fail to malloc rss action memory");
15586 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15587 act_cnt->rss, rss_size,
15590 return -rte_mtr_error_set(error,
15592 RTE_MTR_ERROR_TYPE_METER_POLICY,
15593 NULL, "Fail to save "
15594 "rss action into policy struct");
15595 act_cnt->fate_action =
15596 MLX5_FLOW_FATE_SHARED_RSS;
15597 action_flags |= MLX5_FLOW_ACTION_RSS;
15600 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15601 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15603 struct mlx5_flow_dv_port_id_action_resource
15605 uint32_t port_id = 0;
15607 if (i >= MLX5_MTR_RTE_COLORS)
15608 return -rte_mtr_error_set(error,
15610 RTE_MTR_ERROR_TYPE_METER_POLICY,
15611 NULL, "cannot create policy "
15612 "port action for this color");
15613 memset(&port_id_resource, 0,
15614 sizeof(port_id_resource));
15615 if (flow_dv_translate_action_port_id(dev, act,
15616 &port_id, &flow_err))
15617 return -rte_mtr_error_set(error,
15619 RTE_MTR_ERROR_TYPE_METER_POLICY,
15620 NULL, "cannot translate "
15621 "policy port action");
15622 port_id_resource.port_id = port_id;
15623 if (flow_dv_port_id_action_resource_register
15624 (dev, &port_id_resource,
15625 &dev_flow, &flow_err))
15626 return -rte_mtr_error_set(error,
15628 RTE_MTR_ERROR_TYPE_METER_POLICY,
15629 NULL, "cannot setup "
15630 "policy port action");
15631 act_cnt->rix_port_id_action =
15632 dev_flow.handle->rix_port_id_action;
15633 act_cnt->fate_action =
15634 MLX5_FLOW_FATE_PORT_ID;
15635 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15638 case RTE_FLOW_ACTION_TYPE_JUMP:
15640 uint32_t jump_group = 0;
15641 uint32_t table = 0;
15642 struct mlx5_flow_tbl_data_entry *tbl_data;
15643 struct flow_grp_info grp_info = {
15644 .external = !!dev_flow.external,
15645 .transfer = !!transfer,
15646 .fdb_def_rule = !!priv->fdb_def_rule,
15648 .skip_scale = dev_flow.skip_scale &
15649 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15651 struct mlx5_flow_meter_sub_policy *sub_policy =
15652 mtr_policy->sub_policys[domain][0];
15654 if (i >= MLX5_MTR_RTE_COLORS)
15655 return -rte_mtr_error_set(error,
15657 RTE_MTR_ERROR_TYPE_METER_POLICY,
15659 "cannot create policy "
15660 "jump action for this color");
15662 ((const struct rte_flow_action_jump *)
15664 if (mlx5_flow_group_to_table(dev, NULL,
15667 &grp_info, &flow_err))
15668 return -rte_mtr_error_set(error,
15670 RTE_MTR_ERROR_TYPE_METER_POLICY,
15671 NULL, "cannot setup "
15672 "policy jump action");
15673 sub_policy->jump_tbl[i] =
15674 flow_dv_tbl_resource_get(dev,
15677 !!dev_flow.external,
15678 NULL, jump_group, 0,
15681 (!sub_policy->jump_tbl[i])
15682 return -rte_mtr_error_set(error,
15684 RTE_MTR_ERROR_TYPE_METER_POLICY,
15685 NULL, "cannot create jump action.");
15686 tbl_data = container_of
15687 (sub_policy->jump_tbl[i],
15688 struct mlx5_flow_tbl_data_entry, tbl);
15689 act_cnt->dr_jump_action[domain] =
15690 tbl_data->jump.action;
15691 act_cnt->fate_action =
15692 MLX5_FLOW_FATE_JUMP;
15693 action_flags |= MLX5_FLOW_ACTION_JUMP;
15697 * No need to check meter hierarchy for Y or R colors
15698 * here since it is done in the validation stage.
15700 case RTE_FLOW_ACTION_TYPE_METER:
15702 const struct rte_flow_action_meter *mtr;
15703 struct mlx5_flow_meter_info *next_fm;
15704 struct mlx5_flow_meter_policy *next_policy;
15705 struct rte_flow_action tag_action;
15706 struct mlx5_rte_flow_action_set_tag set_tag;
15707 uint32_t next_mtr_idx = 0;
15710 next_fm = mlx5_flow_meter_find(priv,
15714 return -rte_mtr_error_set(error, EINVAL,
15715 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15716 "Fail to find next meter.");
15717 if (next_fm->def_policy)
15718 return -rte_mtr_error_set(error, EINVAL,
15719 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15720 "Hierarchy only supports termination meter.");
15721 next_policy = mlx5_flow_meter_policy_find(dev,
15722 next_fm->policy_id, NULL);
15723 MLX5_ASSERT(next_policy);
15724 if (next_fm->drop_cnt) {
15727 mlx5_flow_get_reg_id(dev,
15730 (struct rte_flow_error *)error);
15731 set_tag.offset = (priv->mtr_reg_share ?
15732 MLX5_MTR_COLOR_BITS : 0);
15733 set_tag.length = (priv->mtr_reg_share ?
15734 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15736 set_tag.data = next_mtr_idx;
15738 (enum rte_flow_action_type)
15739 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15740 tag_action.conf = &set_tag;
15741 if (flow_dv_convert_action_set_reg
15742 (mhdr_res, &tag_action,
15743 (struct rte_flow_error *)error))
15746 MLX5_FLOW_ACTION_SET_TAG;
15748 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15749 act_cnt->next_mtr_id = next_fm->meter_id;
15750 act_cnt->next_sub_policy = NULL;
15751 mtr_policy->is_hierarchy = 1;
15752 mtr_policy->dev = next_policy->dev;
15754 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15758 return -rte_mtr_error_set(error, ENOTSUP,
15759 RTE_MTR_ERROR_TYPE_METER_POLICY,
15760 NULL, "action type not supported");
15762 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15763 /* create modify action if needed. */
15764 dev_flow.dv.group = 1;
15765 if (flow_dv_modify_hdr_resource_register
15766 (dev, mhdr_res, &dev_flow, &flow_err))
15767 return -rte_mtr_error_set(error,
15769 RTE_MTR_ERROR_TYPE_METER_POLICY,
15770 NULL, "cannot register policy "
15772 act_cnt->modify_hdr =
15773 dev_flow.handle->dvh.modify_hdr;
15781 * Create policy action per domain, lock free,
15782 * (mutex should be acquired by caller).
15783 * Dispatcher for action type specific call.
15786 * Pointer to the Ethernet device structure.
15787 * @param[in] mtr_policy
15788 * Meter policy struct.
15789 * @param[in] action
15790 * Action specification used to create meter actions.
15791 * @param[out] error
15792 * Perform verbose error reporting if not NULL. Initialized in case of
15796 * 0 on success, otherwise negative errno value.
15799 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15800 struct mlx5_flow_meter_policy *mtr_policy,
15801 const struct rte_flow_action *actions[RTE_COLORS],
15802 struct rte_mtr_error *error)
15805 uint16_t sub_policy_num;
15807 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15808 sub_policy_num = (mtr_policy->sub_policy_num >>
15809 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15810 MLX5_MTR_SUB_POLICY_NUM_MASK;
15811 if (sub_policy_num) {
15812 ret = __flow_dv_create_domain_policy_acts(dev,
15813 mtr_policy, actions,
15814 (enum mlx5_meter_domain)i, error);
15815 /* Cleaning resource is done in the caller level. */
15824 * Query a DV flow rule for its statistics via DevX.
15827 * Pointer to Ethernet device.
15828 * @param[in] cnt_idx
15829 * Index to the flow counter.
15831 * Data retrieved by the query.
15832 * @param[out] error
15833 * Perform verbose error reporting if not NULL.
15836 * 0 on success, a negative errno value otherwise and rte_errno is set.
15839 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15840 struct rte_flow_error *error)
15842 struct mlx5_priv *priv = dev->data->dev_private;
15843 struct rte_flow_query_count *qc = data;
15845 if (!priv->sh->devx)
15846 return rte_flow_error_set(error, ENOTSUP,
15847 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15849 "counters are not supported");
15851 uint64_t pkts, bytes;
15852 struct mlx5_flow_counter *cnt;
15853 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15856 return rte_flow_error_set(error, -err,
15857 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15858 NULL, "cannot read counters");
15859 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15862 qc->hits = pkts - cnt->hits;
15863 qc->bytes = bytes - cnt->bytes;
15866 cnt->bytes = bytes;
15870 return rte_flow_error_set(error, EINVAL,
15871 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15873 "counters are not available");
15878 * Query counter's action pointer for a DV flow rule via DevX.
15881 * Pointer to Ethernet device.
15882 * @param[in] cnt_idx
15883 * Index to the flow counter.
15884 * @param[out] action_ptr
15885 * Action pointer for counter.
15886 * @param[out] error
15887 * Perform verbose error reporting if not NULL.
15890 * 0 on success, a negative errno value otherwise and rte_errno is set.
15893 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15894 void **action_ptr, struct rte_flow_error *error)
15896 struct mlx5_priv *priv = dev->data->dev_private;
15898 if (!priv->sh->devx || !action_ptr)
15899 return rte_flow_error_set(error, ENOTSUP,
15900 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15902 "counters are not supported");
15905 struct mlx5_flow_counter *cnt = NULL;
15906 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15908 *action_ptr = cnt->action;
15912 return rte_flow_error_set(error, EINVAL,
15913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15915 "counters are not available");
15919 flow_dv_action_query(struct rte_eth_dev *dev,
15920 const struct rte_flow_action_handle *handle, void *data,
15921 struct rte_flow_error *error)
15923 struct mlx5_age_param *age_param;
15924 struct rte_flow_query_age *resp;
15925 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15926 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15927 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15928 struct mlx5_priv *priv = dev->data->dev_private;
15929 struct mlx5_aso_ct_action *ct;
15934 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15935 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15937 resp->aged = __atomic_load_n(&age_param->state,
15938 __ATOMIC_RELAXED) == AGE_TMOUT ?
15940 resp->sec_since_last_hit_valid = !resp->aged;
15941 if (resp->sec_since_last_hit_valid)
15942 resp->sec_since_last_hit = __atomic_load_n
15943 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15945 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15946 return flow_dv_query_count(dev, idx, data, error);
15947 case MLX5_INDIRECT_ACTION_TYPE_CT:
15948 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15949 if (owner != PORT_ID(priv))
15950 return rte_flow_error_set(error, EACCES,
15951 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15953 "CT object owned by another port");
15954 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15955 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15958 return rte_flow_error_set(error, EFAULT,
15959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15961 "CT object is inactive");
15962 ((struct rte_flow_action_conntrack *)data)->peer_port =
15964 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15966 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15967 return rte_flow_error_set(error, EIO,
15968 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15970 "Failed to query CT context");
15973 return rte_flow_error_set(error, ENOTSUP,
15974 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15975 "action type query not supported");
15980 * Query a flow rule AGE action for aging information.
15983 * Pointer to Ethernet device.
15985 * Pointer to the sub flow.
15987 * data retrieved by the query.
15988 * @param[out] error
15989 * Perform verbose error reporting if not NULL.
15992 * 0 on success, a negative errno value otherwise and rte_errno is set.
15995 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15996 void *data, struct rte_flow_error *error)
15998 struct rte_flow_query_age *resp = data;
15999 struct mlx5_age_param *age_param;
16002 struct mlx5_aso_age_action *act =
16003 flow_aso_age_get_by_idx(dev, flow->age);
16005 age_param = &act->age_params;
16006 } else if (flow->counter) {
16007 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16009 if (!age_param || !age_param->timeout)
16010 return rte_flow_error_set
16012 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16013 NULL, "cannot read age data");
16015 return rte_flow_error_set(error, EINVAL,
16016 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16017 NULL, "age data not available");
16019 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16021 resp->sec_since_last_hit_valid = !resp->aged;
16022 if (resp->sec_since_last_hit_valid)
16023 resp->sec_since_last_hit = __atomic_load_n
16024 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16031 * @see rte_flow_query()
16032 * @see rte_flow_ops
16035 flow_dv_query(struct rte_eth_dev *dev,
16036 struct rte_flow *flow __rte_unused,
16037 const struct rte_flow_action *actions __rte_unused,
16038 void *data __rte_unused,
16039 struct rte_flow_error *error __rte_unused)
16043 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16044 switch (actions->type) {
16045 case RTE_FLOW_ACTION_TYPE_VOID:
16047 case RTE_FLOW_ACTION_TYPE_COUNT:
16048 ret = flow_dv_query_count(dev, flow->counter, data,
16051 case RTE_FLOW_ACTION_TYPE_AGE:
16052 ret = flow_dv_query_age(dev, flow, data, error);
16055 return rte_flow_error_set(error, ENOTSUP,
16056 RTE_FLOW_ERROR_TYPE_ACTION,
16058 "action not supported");
16065 * Destroy the meter table set.
16066 * Lock free, (mutex should be acquired by caller).
16069 * Pointer to Ethernet device.
16071 * Meter information table.
16074 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16075 struct mlx5_flow_meter_info *fm)
16077 struct mlx5_priv *priv = dev->data->dev_private;
16080 if (!fm || !priv->config.dv_flow_en)
16082 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16083 if (fm->drop_rule[i]) {
16084 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16085 fm->drop_rule[i] = NULL;
16091 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16093 struct mlx5_priv *priv = dev->data->dev_private;
16094 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16095 struct mlx5_flow_tbl_data_entry *tbl;
16098 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16099 if (mtrmng->def_rule[i]) {
16100 claim_zero(mlx5_flow_os_destroy_flow
16101 (mtrmng->def_rule[i]));
16102 mtrmng->def_rule[i] = NULL;
16104 if (mtrmng->def_matcher[i]) {
16105 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16106 struct mlx5_flow_tbl_data_entry, tbl);
16107 mlx5_list_unregister(tbl->matchers,
16108 &mtrmng->def_matcher[i]->entry);
16109 mtrmng->def_matcher[i] = NULL;
16111 for (j = 0; j < MLX5_REG_BITS; j++) {
16112 if (mtrmng->drop_matcher[i][j]) {
16114 container_of(mtrmng->drop_matcher[i][j]->tbl,
16115 struct mlx5_flow_tbl_data_entry,
16117 mlx5_list_unregister(tbl->matchers,
16118 &mtrmng->drop_matcher[i][j]->entry);
16119 mtrmng->drop_matcher[i][j] = NULL;
16122 if (mtrmng->drop_tbl[i]) {
16123 flow_dv_tbl_resource_release(MLX5_SH(dev),
16124 mtrmng->drop_tbl[i]);
16125 mtrmng->drop_tbl[i] = NULL;
16130 /* Number of meter flow actions, count and jump or count and drop. */
16131 #define METER_ACTIONS 2
16134 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16135 enum mlx5_meter_domain domain)
16137 struct mlx5_priv *priv = dev->data->dev_private;
16138 struct mlx5_flow_meter_def_policy *def_policy =
16139 priv->sh->mtrmng->def_policy[domain];
16141 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16142 mlx5_free(def_policy);
16143 priv->sh->mtrmng->def_policy[domain] = NULL;
16147 * Destroy the default policy table set.
16150 * Pointer to Ethernet device.
16153 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16155 struct mlx5_priv *priv = dev->data->dev_private;
16158 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16159 if (priv->sh->mtrmng->def_policy[i])
16160 __flow_dv_destroy_domain_def_policy(dev,
16161 (enum mlx5_meter_domain)i);
16162 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16166 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16167 uint32_t color_reg_c_idx,
16168 enum rte_color color, void *matcher_object,
16169 int actions_n, void *actions,
16170 bool match_src_port, const struct rte_flow_item *item,
16171 void **rule, const struct rte_flow_attr *attr)
16174 struct mlx5_flow_dv_match_params value = {
16175 .size = sizeof(value.buf),
16177 struct mlx5_flow_dv_match_params matcher = {
16178 .size = sizeof(matcher.buf),
16180 struct mlx5_priv *priv = dev->data->dev_private;
16183 if (match_src_port && (priv->representor || priv->master)) {
16184 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16185 value.buf, item, attr)) {
16186 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16187 " value with port.", color);
16191 flow_dv_match_meta_reg(matcher.buf, value.buf,
16192 (enum modify_reg)color_reg_c_idx,
16193 rte_col_2_mlx5_col(color), UINT32_MAX);
16194 misc_mask = flow_dv_matcher_enable(value.buf);
16195 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16196 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16197 actions_n, actions, rule);
16199 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16206 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16207 uint32_t color_reg_c_idx,
16209 struct mlx5_flow_meter_sub_policy *sub_policy,
16210 const struct rte_flow_attr *attr,
16211 bool match_src_port,
16212 const struct rte_flow_item *item,
16213 struct mlx5_flow_dv_matcher **policy_matcher,
16214 struct rte_flow_error *error)
16216 struct mlx5_list_entry *entry;
16217 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16218 struct mlx5_flow_dv_matcher matcher = {
16220 .size = sizeof(matcher.mask.buf),
16224 struct mlx5_flow_dv_match_params value = {
16225 .size = sizeof(value.buf),
16227 struct mlx5_flow_cb_ctx ctx = {
16231 struct mlx5_flow_tbl_data_entry *tbl_data;
16232 struct mlx5_priv *priv = dev->data->dev_private;
16233 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16235 if (match_src_port && (priv->representor || priv->master)) {
16236 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16237 value.buf, item, attr)) {
16238 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16239 " with port.", priority);
16243 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16244 if (priority < RTE_COLOR_RED)
16245 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16246 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16247 matcher.priority = priority;
16248 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16249 matcher.mask.size);
16250 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16252 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16256 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16261 * Create the policy rules per domain.
16264 * Pointer to Ethernet device.
16265 * @param[in] sub_policy
16266 * Pointer to sub policy table..
16267 * @param[in] egress
16268 * Direction of the table.
16269 * @param[in] transfer
16270 * E-Switch or NIC flow.
16272 * Pointer to policy action list per color.
16275 * 0 on success, -1 otherwise.
16278 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16279 struct mlx5_flow_meter_sub_policy *sub_policy,
16280 uint8_t egress, uint8_t transfer, bool match_src_port,
16281 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16283 struct mlx5_priv *priv = dev->data->dev_private;
16284 struct rte_flow_error flow_err;
16285 uint32_t color_reg_c_idx;
16286 struct rte_flow_attr attr = {
16287 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16290 .egress = !!egress,
16291 .transfer = !!transfer,
16295 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16296 struct mlx5_sub_policy_color_rule *color_rule;
16298 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16302 /* Create policy table with POLICY level. */
16303 if (!sub_policy->tbl_rsc)
16304 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16305 MLX5_FLOW_TABLE_LEVEL_POLICY,
16306 egress, transfer, false, NULL, 0, 0,
16307 sub_policy->idx, &flow_err);
16308 if (!sub_policy->tbl_rsc) {
16310 "Failed to create meter sub policy table.");
16313 /* Prepare matchers. */
16314 color_reg_c_idx = ret;
16315 for (i = 0; i < RTE_COLORS; i++) {
16316 TAILQ_INIT(&sub_policy->color_rules[i]);
16317 if (!acts[i].actions_n)
16319 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16320 sizeof(struct mlx5_sub_policy_color_rule),
16323 DRV_LOG(ERR, "No memory to create color rule.");
16326 tmp_rules[i] = color_rule;
16327 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16328 color_rule, next_port);
16329 color_rule->src_port = priv->representor_id;
16332 /* Create matchers for colors. */
16333 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16334 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16335 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16336 &attr, svport_match, NULL,
16337 &color_rule->matcher, &flow_err)) {
16338 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16341 /* Create flow, matching color. */
16342 if (__flow_dv_create_policy_flow(dev,
16343 color_reg_c_idx, (enum rte_color)i,
16344 color_rule->matcher->matcher_object,
16345 acts[i].actions_n, acts[i].dv_actions,
16346 svport_match, NULL, &color_rule->rule,
16348 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16354 /* All the policy rules will be cleared. */
16356 color_rule = tmp_rules[i];
16358 if (color_rule->rule)
16359 mlx5_flow_os_destroy_flow(color_rule->rule);
16360 if (color_rule->matcher) {
16361 struct mlx5_flow_tbl_data_entry *tbl =
16362 container_of(color_rule->matcher->tbl,
16363 typeof(*tbl), tbl);
16364 mlx5_list_unregister(tbl->matchers,
16365 &color_rule->matcher->entry);
16367 TAILQ_REMOVE(&sub_policy->color_rules[i],
16368 color_rule, next_port);
16369 mlx5_free(color_rule);
16376 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16377 struct mlx5_flow_meter_policy *mtr_policy,
16378 struct mlx5_flow_meter_sub_policy *sub_policy,
16381 struct mlx5_priv *priv = dev->data->dev_private;
16382 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16383 struct mlx5_flow_dv_tag_resource *tag;
16384 struct mlx5_flow_dv_port_id_action_resource *port_action;
16385 struct mlx5_hrxq *hrxq;
16386 struct mlx5_flow_meter_info *next_fm = NULL;
16387 struct mlx5_flow_meter_policy *next_policy;
16388 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16389 struct mlx5_flow_tbl_data_entry *tbl_data;
16390 struct rte_flow_error error;
16391 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16392 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16393 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16394 bool match_src_port = false;
16397 /* If RSS or Queue, no previous actions / rules is created. */
16398 for (i = 0; i < RTE_COLORS; i++) {
16399 acts[i].actions_n = 0;
16400 if (i == RTE_COLOR_RED) {
16401 /* Only support drop on red. */
16402 acts[i].dv_actions[0] =
16403 mtr_policy->dr_drop_action[domain];
16404 acts[i].actions_n = 1;
16407 if (i == RTE_COLOR_GREEN &&
16408 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16409 struct rte_flow_attr attr = {
16410 .transfer = transfer
16413 next_fm = mlx5_flow_meter_find(priv,
16414 mtr_policy->act_cnt[i].next_mtr_id,
16418 "Failed to get next hierarchy meter.");
16421 if (mlx5_flow_meter_attach(priv, next_fm,
16423 DRV_LOG(ERR, "%s", error.message);
16427 /* Meter action must be the first for TX. */
16429 acts[i].dv_actions[acts[i].actions_n] =
16430 next_fm->meter_action;
16431 acts[i].actions_n++;
16434 if (mtr_policy->act_cnt[i].rix_mark) {
16435 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16436 mtr_policy->act_cnt[i].rix_mark);
16438 DRV_LOG(ERR, "Failed to find "
16439 "mark action for policy.");
16442 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16443 acts[i].actions_n++;
16445 if (mtr_policy->act_cnt[i].modify_hdr) {
16446 acts[i].dv_actions[acts[i].actions_n] =
16447 mtr_policy->act_cnt[i].modify_hdr->action;
16448 acts[i].actions_n++;
16450 if (mtr_policy->act_cnt[i].fate_action) {
16451 switch (mtr_policy->act_cnt[i].fate_action) {
16452 case MLX5_FLOW_FATE_PORT_ID:
16453 port_action = mlx5_ipool_get
16454 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16455 mtr_policy->act_cnt[i].rix_port_id_action);
16456 if (!port_action) {
16457 DRV_LOG(ERR, "Failed to find "
16458 "port action for policy.");
16461 acts[i].dv_actions[acts[i].actions_n] =
16462 port_action->action;
16463 acts[i].actions_n++;
16464 mtr_policy->dev = dev;
16465 match_src_port = true;
16467 case MLX5_FLOW_FATE_DROP:
16468 case MLX5_FLOW_FATE_JUMP:
16469 acts[i].dv_actions[acts[i].actions_n] =
16470 mtr_policy->act_cnt[i].dr_jump_action[domain];
16471 acts[i].actions_n++;
16473 case MLX5_FLOW_FATE_SHARED_RSS:
16474 case MLX5_FLOW_FATE_QUEUE:
16475 hrxq = mlx5_ipool_get
16476 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16477 sub_policy->rix_hrxq[i]);
16479 DRV_LOG(ERR, "Failed to find "
16480 "queue action for policy.");
16483 acts[i].dv_actions[acts[i].actions_n] =
16485 acts[i].actions_n++;
16487 case MLX5_FLOW_FATE_MTR:
16490 "No next hierarchy meter.");
16494 acts[i].dv_actions[acts[i].actions_n] =
16495 next_fm->meter_action;
16496 acts[i].actions_n++;
16498 if (mtr_policy->act_cnt[i].next_sub_policy) {
16500 mtr_policy->act_cnt[i].next_sub_policy;
16503 mlx5_flow_meter_policy_find(dev,
16504 next_fm->policy_id, NULL);
16505 MLX5_ASSERT(next_policy);
16507 next_policy->sub_policys[domain][0];
16510 container_of(next_sub_policy->tbl_rsc,
16511 struct mlx5_flow_tbl_data_entry, tbl);
16512 acts[i].dv_actions[acts[i].actions_n++] =
16513 tbl_data->jump.action;
16514 if (mtr_policy->act_cnt[i].modify_hdr)
16515 match_src_port = !!transfer;
16518 /*Queue action do nothing*/
16523 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16524 egress, transfer, match_src_port, acts)) {
16526 "Failed to create policy rules per domain.");
16532 mlx5_flow_meter_detach(priv, next_fm);
16537 * Create the policy rules.
16540 * Pointer to Ethernet device.
16541 * @param[in,out] mtr_policy
16542 * Pointer to meter policy table.
16545 * 0 on success, -1 otherwise.
16548 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16549 struct mlx5_flow_meter_policy *mtr_policy)
16552 uint16_t sub_policy_num;
16554 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16555 sub_policy_num = (mtr_policy->sub_policy_num >>
16556 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16557 MLX5_MTR_SUB_POLICY_NUM_MASK;
16558 if (!sub_policy_num)
16560 /* Prepare actions list and create policy rules. */
16561 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16562 mtr_policy->sub_policys[i][0], i)) {
16563 DRV_LOG(ERR, "Failed to create policy action "
16564 "list per domain.");
16572 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16574 struct mlx5_priv *priv = dev->data->dev_private;
16575 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16576 struct mlx5_flow_meter_def_policy *def_policy;
16577 struct mlx5_flow_tbl_resource *jump_tbl;
16578 struct mlx5_flow_tbl_data_entry *tbl_data;
16579 uint8_t egress, transfer;
16580 struct rte_flow_error error;
16581 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16584 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16585 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16586 def_policy = mtrmng->def_policy[domain];
16588 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16589 sizeof(struct mlx5_flow_meter_def_policy),
16590 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16592 DRV_LOG(ERR, "Failed to alloc default policy table.");
16593 goto def_policy_error;
16595 mtrmng->def_policy[domain] = def_policy;
16596 /* Create the meter suffix table with SUFFIX level. */
16597 jump_tbl = flow_dv_tbl_resource_get(dev,
16598 MLX5_FLOW_TABLE_LEVEL_METER,
16599 egress, transfer, false, NULL, 0,
16600 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16603 "Failed to create meter suffix table.");
16604 goto def_policy_error;
16606 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16607 tbl_data = container_of(jump_tbl,
16608 struct mlx5_flow_tbl_data_entry, tbl);
16609 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16610 tbl_data->jump.action;
16611 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16612 acts[RTE_COLOR_GREEN].actions_n = 1;
16614 * YELLOW has the same default policy as GREEN does.
16615 * G & Y share the same table and action. The 2nd time of table
16616 * resource getting is just to update the reference count for
16617 * the releasing stage.
16619 jump_tbl = flow_dv_tbl_resource_get(dev,
16620 MLX5_FLOW_TABLE_LEVEL_METER,
16621 egress, transfer, false, NULL, 0,
16622 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16625 "Failed to get meter suffix table.");
16626 goto def_policy_error;
16628 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16629 tbl_data = container_of(jump_tbl,
16630 struct mlx5_flow_tbl_data_entry, tbl);
16631 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16632 tbl_data->jump.action;
16633 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16634 acts[RTE_COLOR_YELLOW].actions_n = 1;
16635 /* Create jump action to the drop table. */
16636 if (!mtrmng->drop_tbl[domain]) {
16637 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16638 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16639 egress, transfer, false, NULL, 0,
16640 0, MLX5_MTR_TABLE_ID_DROP, &error);
16641 if (!mtrmng->drop_tbl[domain]) {
16642 DRV_LOG(ERR, "Failed to create meter "
16643 "drop table for default policy.");
16644 goto def_policy_error;
16647 /* all RED: unique Drop table for jump action. */
16648 tbl_data = container_of(mtrmng->drop_tbl[domain],
16649 struct mlx5_flow_tbl_data_entry, tbl);
16650 def_policy->dr_jump_action[RTE_COLOR_RED] =
16651 tbl_data->jump.action;
16652 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16653 acts[RTE_COLOR_RED].actions_n = 1;
16654 /* Create default policy rules. */
16655 ret = __flow_dv_create_domain_policy_rules(dev,
16656 &def_policy->sub_policy,
16657 egress, transfer, false, acts);
16659 DRV_LOG(ERR, "Failed to create default policy rules.");
16660 goto def_policy_error;
16665 __flow_dv_destroy_domain_def_policy(dev,
16666 (enum mlx5_meter_domain)domain);
16671 * Create the default policy table set.
16674 * Pointer to Ethernet device.
16676 * 0 on success, -1 otherwise.
16679 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16681 struct mlx5_priv *priv = dev->data->dev_private;
16684 /* Non-termination policy table. */
16685 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16686 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16688 if (__flow_dv_create_domain_def_policy(dev, i)) {
16689 DRV_LOG(ERR, "Failed to create default policy");
16690 /* Rollback the created default policies for others. */
16691 flow_dv_destroy_def_policy(dev);
16699 * Create the needed meter tables.
16700 * Lock free, (mutex should be acquired by caller).
16703 * Pointer to Ethernet device.
16705 * Meter information table.
16706 * @param[in] mtr_idx
16708 * @param[in] domain_bitmap
16711 * 0 on success, -1 otherwise.
16714 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16715 struct mlx5_flow_meter_info *fm,
16717 uint8_t domain_bitmap)
16719 struct mlx5_priv *priv = dev->data->dev_private;
16720 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16721 struct rte_flow_error error;
16722 struct mlx5_flow_tbl_data_entry *tbl_data;
16723 uint8_t egress, transfer;
16724 void *actions[METER_ACTIONS];
16725 int domain, ret, i;
16726 struct mlx5_flow_counter *cnt;
16727 struct mlx5_flow_dv_match_params value = {
16728 .size = sizeof(value.buf),
16730 struct mlx5_flow_dv_match_params matcher_para = {
16731 .size = sizeof(matcher_para.buf),
16733 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16735 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16736 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16737 struct mlx5_list_entry *entry;
16738 struct mlx5_flow_dv_matcher matcher = {
16740 .size = sizeof(matcher.mask.buf),
16743 struct mlx5_flow_dv_matcher *drop_matcher;
16744 struct mlx5_flow_cb_ctx ctx = {
16750 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16751 rte_errno = ENOTSUP;
16754 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16755 if (!(domain_bitmap & (1 << domain)) ||
16756 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16758 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16759 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16760 /* Create the drop table with METER DROP level. */
16761 if (!mtrmng->drop_tbl[domain]) {
16762 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16763 MLX5_FLOW_TABLE_LEVEL_METER,
16764 egress, transfer, false, NULL, 0,
16765 0, MLX5_MTR_TABLE_ID_DROP, &error);
16766 if (!mtrmng->drop_tbl[domain]) {
16767 DRV_LOG(ERR, "Failed to create meter drop table.");
16771 /* Create default matcher in drop table. */
16772 matcher.tbl = mtrmng->drop_tbl[domain],
16773 tbl_data = container_of(mtrmng->drop_tbl[domain],
16774 struct mlx5_flow_tbl_data_entry, tbl);
16775 if (!mtrmng->def_matcher[domain]) {
16776 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16777 (enum modify_reg)mtr_id_reg_c,
16779 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16780 matcher.crc = rte_raw_cksum
16781 ((const void *)matcher.mask.buf,
16782 matcher.mask.size);
16783 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16785 DRV_LOG(ERR, "Failed to register meter "
16786 "drop default matcher.");
16789 mtrmng->def_matcher[domain] = container_of(entry,
16790 struct mlx5_flow_dv_matcher, entry);
16792 /* Create default rule in drop table. */
16793 if (!mtrmng->def_rule[domain]) {
16795 actions[i++] = priv->sh->dr_drop_action;
16796 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16797 (enum modify_reg)mtr_id_reg_c, 0, 0);
16798 misc_mask = flow_dv_matcher_enable(value.buf);
16799 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16800 ret = mlx5_flow_os_create_flow
16801 (mtrmng->def_matcher[domain]->matcher_object,
16802 (void *)&value, i, actions,
16803 &mtrmng->def_rule[domain]);
16805 DRV_LOG(ERR, "Failed to create meter "
16806 "default drop rule for drop table.");
16812 MLX5_ASSERT(mtrmng->max_mtr_bits);
16813 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16814 /* Create matchers for Drop. */
16815 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16816 (enum modify_reg)mtr_id_reg_c, 0,
16817 (mtr_id_mask << mtr_id_offset));
16818 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16819 matcher.crc = rte_raw_cksum
16820 ((const void *)matcher.mask.buf,
16821 matcher.mask.size);
16822 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16825 "Failed to register meter drop matcher.");
16828 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16829 container_of(entry, struct mlx5_flow_dv_matcher,
16833 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16834 /* Create drop rule, matching meter_id only. */
16835 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16836 (enum modify_reg)mtr_id_reg_c,
16837 (mtr_idx << mtr_id_offset), UINT32_MAX);
16839 cnt = flow_dv_counter_get_by_idx(dev,
16840 fm->drop_cnt, NULL);
16841 actions[i++] = cnt->action;
16842 actions[i++] = priv->sh->dr_drop_action;
16843 misc_mask = flow_dv_matcher_enable(value.buf);
16844 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16845 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16846 (void *)&value, i, actions,
16847 &fm->drop_rule[domain]);
16849 DRV_LOG(ERR, "Failed to create meter "
16850 "drop rule for drop table.");
16856 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16857 if (fm->drop_rule[i]) {
16858 claim_zero(mlx5_flow_os_destroy_flow
16859 (fm->drop_rule[i]));
16860 fm->drop_rule[i] = NULL;
16866 static struct mlx5_flow_meter_sub_policy *
16867 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16868 struct mlx5_flow_meter_policy *mtr_policy,
16869 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16870 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16873 struct mlx5_priv *priv = dev->data->dev_private;
16874 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16875 uint32_t sub_policy_idx = 0;
16876 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16878 struct mlx5_hrxq *hrxq;
16879 struct mlx5_flow_handle dh;
16880 struct mlx5_meter_policy_action_container *act_cnt;
16881 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16882 uint16_t sub_policy_num;
16884 rte_spinlock_lock(&mtr_policy->sl);
16885 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16888 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16889 if (!hrxq_idx[i]) {
16890 rte_spinlock_unlock(&mtr_policy->sl);
16894 sub_policy_num = (mtr_policy->sub_policy_num >>
16895 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16896 MLX5_MTR_SUB_POLICY_NUM_MASK;
16897 for (j = 0; j < sub_policy_num; j++) {
16898 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16901 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16904 if (i >= MLX5_MTR_RTE_COLORS) {
16906 * Found the sub policy table with
16907 * the same queue per color.
16909 rte_spinlock_unlock(&mtr_policy->sl);
16910 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16911 mlx5_hrxq_release(dev, hrxq_idx[i]);
16913 return mtr_policy->sub_policys[domain][j];
16916 /* Create sub policy. */
16917 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16918 /* Reuse the first pre-allocated sub_policy. */
16919 sub_policy = mtr_policy->sub_policys[domain][0];
16920 sub_policy_idx = sub_policy->idx;
16922 sub_policy = mlx5_ipool_zmalloc
16923 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16926 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16927 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16928 mlx5_hrxq_release(dev, hrxq_idx[i]);
16929 goto rss_sub_policy_error;
16931 sub_policy->idx = sub_policy_idx;
16932 sub_policy->main_policy = mtr_policy;
16934 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16937 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16938 if (mtr_policy->is_hierarchy) {
16939 act_cnt = &mtr_policy->act_cnt[i];
16940 act_cnt->next_sub_policy = next_sub_policy;
16941 mlx5_hrxq_release(dev, hrxq_idx[i]);
16944 * Overwrite the last action from
16945 * RSS action to Queue action.
16947 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16950 DRV_LOG(ERR, "Failed to get policy hrxq");
16951 goto rss_sub_policy_error;
16953 act_cnt = &mtr_policy->act_cnt[i];
16954 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16955 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16956 if (act_cnt->rix_mark)
16958 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16959 dh.rix_hrxq = hrxq_idx[i];
16960 flow_drv_rxq_flags_set(dev, &dh);
16964 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16965 sub_policy, domain)) {
16966 DRV_LOG(ERR, "Failed to create policy "
16967 "rules for ingress domain.");
16968 goto rss_sub_policy_error;
16970 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16971 i = (mtr_policy->sub_policy_num >>
16972 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16973 MLX5_MTR_SUB_POLICY_NUM_MASK;
16974 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16975 DRV_LOG(ERR, "No free sub-policy slot.");
16976 goto rss_sub_policy_error;
16978 mtr_policy->sub_policys[domain][i] = sub_policy;
16980 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16981 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16982 mtr_policy->sub_policy_num |=
16983 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16984 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16986 rte_spinlock_unlock(&mtr_policy->sl);
16989 rss_sub_policy_error:
16991 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16992 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16993 i = (mtr_policy->sub_policy_num >>
16994 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16995 MLX5_MTR_SUB_POLICY_NUM_MASK;
16996 mtr_policy->sub_policys[domain][i] = NULL;
16997 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17001 rte_spinlock_unlock(&mtr_policy->sl);
17006 * Find the policy table for prefix table with RSS.
17009 * Pointer to Ethernet device.
17010 * @param[in] mtr_policy
17011 * Pointer to meter policy table.
17012 * @param[in] rss_desc
17013 * Pointer to rss_desc
17015 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17017 static struct mlx5_flow_meter_sub_policy *
17018 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17019 struct mlx5_flow_meter_policy *mtr_policy,
17020 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17022 struct mlx5_priv *priv = dev->data->dev_private;
17023 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17024 struct mlx5_flow_meter_info *next_fm;
17025 struct mlx5_flow_meter_policy *next_policy;
17026 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17027 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17028 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17029 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17030 bool reuse_sub_policy;
17035 /* Iterate hierarchy to get all policies in this hierarchy. */
17036 policies[i++] = mtr_policy;
17037 if (!mtr_policy->is_hierarchy)
17039 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17040 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17043 next_fm = mlx5_flow_meter_find(priv,
17044 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17046 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17050 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17052 MLX5_ASSERT(next_policy);
17053 mtr_policy = next_policy;
17057 * From last policy to the first one in hierarchy,
17058 * create / get the sub policy for each of them.
17060 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17064 &reuse_sub_policy);
17066 DRV_LOG(ERR, "Failed to get the sub policy.");
17069 if (!reuse_sub_policy)
17070 sub_policies[j++] = sub_policy;
17071 next_sub_policy = sub_policy;
17076 uint16_t sub_policy_num;
17078 sub_policy = sub_policies[--j];
17079 mtr_policy = sub_policy->main_policy;
17080 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17081 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17082 sub_policy_num = (mtr_policy->sub_policy_num >>
17083 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17084 MLX5_MTR_SUB_POLICY_NUM_MASK;
17085 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17088 mtr_policy->sub_policy_num &=
17089 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17090 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17091 mtr_policy->sub_policy_num |=
17092 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17093 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17094 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17102 * Create the sub policy tag rule for all meters in hierarchy.
17105 * Pointer to Ethernet device.
17107 * Meter information table.
17108 * @param[in] src_port
17109 * The src port this extra rule should use.
17111 * The src port match item.
17112 * @param[out] error
17113 * Perform verbose error reporting if not NULL.
17115 * 0 on success, a negative errno value otherwise and rte_errno is set.
17118 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17119 struct mlx5_flow_meter_info *fm,
17121 const struct rte_flow_item *item,
17122 struct rte_flow_error *error)
17124 struct mlx5_priv *priv = dev->data->dev_private;
17125 struct mlx5_flow_meter_policy *mtr_policy;
17126 struct mlx5_flow_meter_sub_policy *sub_policy;
17127 struct mlx5_flow_meter_info *next_fm = NULL;
17128 struct mlx5_flow_meter_policy *next_policy;
17129 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17130 struct mlx5_flow_tbl_data_entry *tbl_data;
17131 struct mlx5_sub_policy_color_rule *color_rule;
17132 struct mlx5_meter_policy_acts acts;
17133 uint32_t color_reg_c_idx;
17134 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17135 struct rte_flow_attr attr = {
17136 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17143 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17146 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17147 MLX5_ASSERT(mtr_policy);
17148 if (!mtr_policy->is_hierarchy)
17150 next_fm = mlx5_flow_meter_find(priv,
17151 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17153 return rte_flow_error_set(error, EINVAL,
17154 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17155 "Failed to find next meter in hierarchy.");
17157 if (!next_fm->drop_cnt)
17159 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17160 sub_policy = mtr_policy->sub_policys[domain][0];
17161 for (i = 0; i < RTE_COLORS; i++) {
17162 bool rule_exist = false;
17163 struct mlx5_meter_policy_action_container *act_cnt;
17165 if (i >= RTE_COLOR_YELLOW)
17167 TAILQ_FOREACH(color_rule,
17168 &sub_policy->color_rules[i], next_port)
17169 if (color_rule->src_port == src_port) {
17175 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17176 sizeof(struct mlx5_sub_policy_color_rule),
17179 return rte_flow_error_set(error, ENOMEM,
17180 RTE_FLOW_ERROR_TYPE_ACTION,
17181 NULL, "No memory to create tag color rule.");
17182 color_rule->src_port = src_port;
17184 next_policy = mlx5_flow_meter_policy_find(dev,
17185 next_fm->policy_id, NULL);
17186 MLX5_ASSERT(next_policy);
17187 next_sub_policy = next_policy->sub_policys[domain][0];
17188 tbl_data = container_of(next_sub_policy->tbl_rsc,
17189 struct mlx5_flow_tbl_data_entry, tbl);
17190 act_cnt = &mtr_policy->act_cnt[i];
17192 acts.dv_actions[0] = next_fm->meter_action;
17193 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17195 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17196 acts.dv_actions[1] = next_fm->meter_action;
17198 acts.dv_actions[2] = tbl_data->jump.action;
17199 acts.actions_n = 3;
17200 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17204 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17205 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17207 &color_rule->matcher, error)) {
17208 rte_flow_error_set(error, errno,
17209 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17210 "Failed to create hierarchy meter matcher.");
17213 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17215 color_rule->matcher->matcher_object,
17216 acts.actions_n, acts.dv_actions,
17218 &color_rule->rule, &attr)) {
17219 rte_flow_error_set(error, errno,
17220 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17221 "Failed to create hierarchy meter rule.");
17224 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17225 color_rule, next_port);
17229 * Recursive call to iterate all meters in hierarchy and
17230 * create needed rules.
17232 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17233 src_port, item, error);
17236 if (color_rule->rule)
17237 mlx5_flow_os_destroy_flow(color_rule->rule);
17238 if (color_rule->matcher) {
17239 struct mlx5_flow_tbl_data_entry *tbl =
17240 container_of(color_rule->matcher->tbl,
17241 typeof(*tbl), tbl);
17242 mlx5_list_unregister(tbl->matchers,
17243 &color_rule->matcher->entry);
17245 mlx5_free(color_rule);
17248 mlx5_flow_meter_detach(priv, next_fm);
17253 * Destroy the sub policy table with RX queue.
17256 * Pointer to Ethernet device.
17257 * @param[in] mtr_policy
17258 * Pointer to meter policy table.
17261 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17262 struct mlx5_flow_meter_policy *mtr_policy)
17264 struct mlx5_priv *priv = dev->data->dev_private;
17265 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17266 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17268 uint16_t sub_policy_num, new_policy_num;
17270 rte_spinlock_lock(&mtr_policy->sl);
17271 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17272 switch (mtr_policy->act_cnt[i].fate_action) {
17273 case MLX5_FLOW_FATE_SHARED_RSS:
17274 sub_policy_num = (mtr_policy->sub_policy_num >>
17275 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17276 MLX5_MTR_SUB_POLICY_NUM_MASK;
17277 new_policy_num = sub_policy_num;
17278 for (j = 0; j < sub_policy_num; j++) {
17280 mtr_policy->sub_policys[domain][j];
17282 __flow_dv_destroy_sub_policy_rules(dev,
17285 mtr_policy->sub_policys[domain][0]) {
17286 mtr_policy->sub_policys[domain][j] =
17289 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17295 if (new_policy_num != sub_policy_num) {
17296 mtr_policy->sub_policy_num &=
17297 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17298 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17299 mtr_policy->sub_policy_num |=
17301 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17302 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17305 case MLX5_FLOW_FATE_QUEUE:
17306 sub_policy = mtr_policy->sub_policys[domain][0];
17307 __flow_dv_destroy_sub_policy_rules(dev,
17311 /*Other actions without queue and do nothing*/
17315 rte_spinlock_unlock(&mtr_policy->sl);
17318 * Check whether the DR drop action is supported on the root table or not.
17320 * Create a simple flow with DR drop action on root table to validate
17321 * if DR drop action on root table is supported or not.
17324 * Pointer to rte_eth_dev structure.
17327 * 0 on success, a negative errno value otherwise and rte_errno is set.
17330 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17332 struct mlx5_priv *priv = dev->data->dev_private;
17333 struct mlx5_dev_ctx_shared *sh = priv->sh;
17334 struct mlx5_flow_dv_match_params mask = {
17335 .size = sizeof(mask.buf),
17337 struct mlx5_flow_dv_match_params value = {
17338 .size = sizeof(value.buf),
17340 struct mlx5dv_flow_matcher_attr dv_attr = {
17341 .type = IBV_FLOW_ATTR_NORMAL,
17343 .match_criteria_enable = 0,
17344 .match_mask = (void *)&mask,
17346 struct mlx5_flow_tbl_resource *tbl = NULL;
17347 void *matcher = NULL;
17351 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17355 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17356 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17357 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17358 tbl->obj, &matcher);
17361 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17362 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17363 &sh->dr_drop_action, &flow);
17366 * If DR drop action is not supported on root table, flow create will
17367 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17371 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17372 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17374 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17377 claim_zero(mlx5_flow_os_destroy_flow(flow));
17380 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17382 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17387 * Validate the batch counter support in root table.
17389 * Create a simple flow with invalid counter and drop action on root table to
17390 * validate if batch counter with offset on root table is supported or not.
17393 * Pointer to rte_eth_dev structure.
17396 * 0 on success, a negative errno value otherwise and rte_errno is set.
17399 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17401 struct mlx5_priv *priv = dev->data->dev_private;
17402 struct mlx5_dev_ctx_shared *sh = priv->sh;
17403 struct mlx5_flow_dv_match_params mask = {
17404 .size = sizeof(mask.buf),
17406 struct mlx5_flow_dv_match_params value = {
17407 .size = sizeof(value.buf),
17409 struct mlx5dv_flow_matcher_attr dv_attr = {
17410 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17412 .match_criteria_enable = 0,
17413 .match_mask = (void *)&mask,
17415 void *actions[2] = { 0 };
17416 struct mlx5_flow_tbl_resource *tbl = NULL;
17417 struct mlx5_devx_obj *dcs = NULL;
17418 void *matcher = NULL;
17422 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17426 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17429 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17433 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17434 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17435 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17436 tbl->obj, &matcher);
17439 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17440 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17444 * If batch counter with offset is not supported, the driver will not
17445 * validate the invalid offset value, flow create should success.
17446 * In this case, it means batch counter is not supported in root table.
17448 * Otherwise, if flow create is failed, counter offset is supported.
17451 DRV_LOG(INFO, "Batch counter is not supported in root "
17452 "table. Switch to fallback mode.");
17453 rte_errno = ENOTSUP;
17455 claim_zero(mlx5_flow_os_destroy_flow(flow));
17457 /* Check matcher to make sure validate fail at flow create. */
17458 if (!matcher || (matcher && errno != EINVAL))
17459 DRV_LOG(ERR, "Unexpected error in counter offset "
17460 "support detection");
17464 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17466 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17468 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17470 claim_zero(mlx5_devx_cmd_destroy(dcs));
17475 * Query a devx counter.
17478 * Pointer to the Ethernet device structure.
17480 * Index to the flow counter.
17482 * Set to clear the counter statistics.
17484 * The statistics value of packets.
17485 * @param[out] bytes
17486 * The statistics value of bytes.
17489 * 0 on success, otherwise return -1.
17492 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17493 uint64_t *pkts, uint64_t *bytes)
17495 struct mlx5_priv *priv = dev->data->dev_private;
17496 struct mlx5_flow_counter *cnt;
17497 uint64_t inn_pkts, inn_bytes;
17500 if (!priv->sh->devx)
17503 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17506 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17507 *pkts = inn_pkts - cnt->hits;
17508 *bytes = inn_bytes - cnt->bytes;
17510 cnt->hits = inn_pkts;
17511 cnt->bytes = inn_bytes;
17517 * Get aged-out flows.
17520 * Pointer to the Ethernet device structure.
17521 * @param[in] context
17522 * The address of an array of pointers to the aged-out flows contexts.
17523 * @param[in] nb_contexts
17524 * The length of context array pointers.
17525 * @param[out] error
17526 * Perform verbose error reporting if not NULL. Initialized in case of
17530 * how many contexts get in success, otherwise negative errno value.
17531 * if nb_contexts is 0, return the amount of all aged contexts.
17532 * if nb_contexts is not 0 , return the amount of aged flows reported
17533 * in the context array.
17534 * @note: only stub for now
17537 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17539 uint32_t nb_contexts,
17540 struct rte_flow_error *error)
17542 struct mlx5_priv *priv = dev->data->dev_private;
17543 struct mlx5_age_info *age_info;
17544 struct mlx5_age_param *age_param;
17545 struct mlx5_flow_counter *counter;
17546 struct mlx5_aso_age_action *act;
17549 if (nb_contexts && !context)
17550 return rte_flow_error_set(error, EINVAL,
17551 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17552 NULL, "empty context");
17553 age_info = GET_PORT_AGE_INFO(priv);
17554 rte_spinlock_lock(&age_info->aged_sl);
17555 LIST_FOREACH(act, &age_info->aged_aso, next) {
17558 context[nb_flows - 1] =
17559 act->age_params.context;
17560 if (!(--nb_contexts))
17564 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17567 age_param = MLX5_CNT_TO_AGE(counter);
17568 context[nb_flows - 1] = age_param->context;
17569 if (!(--nb_contexts))
17573 rte_spinlock_unlock(&age_info->aged_sl);
17574 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17579 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17582 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17584 return flow_dv_counter_alloc(dev, 0);
17588 * Validate indirect action.
17589 * Dispatcher for action type specific validation.
17592 * Pointer to the Ethernet device structure.
17594 * Indirect action configuration.
17595 * @param[in] action
17596 * The indirect action object to validate.
17597 * @param[out] error
17598 * Perform verbose error reporting if not NULL. Initialized in case of
17602 * 0 on success, otherwise negative errno value.
17605 flow_dv_action_validate(struct rte_eth_dev *dev,
17606 const struct rte_flow_indir_action_conf *conf,
17607 const struct rte_flow_action *action,
17608 struct rte_flow_error *err)
17610 struct mlx5_priv *priv = dev->data->dev_private;
17612 RTE_SET_USED(conf);
17613 switch (action->type) {
17614 case RTE_FLOW_ACTION_TYPE_RSS:
17616 * priv->obj_ops is set according to driver capabilities.
17617 * When DevX capabilities are
17618 * sufficient, it is set to devx_obj_ops.
17619 * Otherwise, it is set to ibv_obj_ops.
17620 * ibv_obj_ops doesn't support ind_table_modify operation.
17621 * In this case the indirect RSS action can't be used.
17623 if (priv->obj_ops.ind_table_modify == NULL)
17624 return rte_flow_error_set
17626 RTE_FLOW_ERROR_TYPE_ACTION,
17628 "Indirect RSS action not supported");
17629 return mlx5_validate_action_rss(dev, action, err);
17630 case RTE_FLOW_ACTION_TYPE_AGE:
17631 if (!priv->sh->aso_age_mng)
17632 return rte_flow_error_set(err, ENOTSUP,
17633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17635 "Indirect age action not supported");
17636 return flow_dv_validate_action_age(0, action, dev, err);
17637 case RTE_FLOW_ACTION_TYPE_COUNT:
17638 return flow_dv_validate_action_count(dev, true, 0, err);
17639 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17640 if (!priv->sh->ct_aso_en)
17641 return rte_flow_error_set(err, ENOTSUP,
17642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17643 "ASO CT is not supported");
17644 return mlx5_validate_action_ct(dev, action->conf, err);
17646 return rte_flow_error_set(err, ENOTSUP,
17647 RTE_FLOW_ERROR_TYPE_ACTION,
17649 "action type not supported");
17654 * Check if the RSS configurations for colors of a meter policy match
17655 * each other, except the queues.
17658 * Pointer to the first RSS flow action.
17660 * Pointer to the second RSS flow action.
17663 * 0 on match, 1 on conflict.
17666 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17667 const struct rte_flow_action_rss *r2)
17669 if (r1 == NULL || r2 == NULL)
17671 if (!(r1->level <= 1 && r2->level <= 1) &&
17672 !(r1->level > 1 && r2->level > 1))
17674 if (r1->types != r2->types &&
17675 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17676 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17678 if (r1->key || r2->key) {
17679 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17680 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17682 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17689 * Validate the meter hierarchy chain for meter policy.
17692 * Pointer to the Ethernet device structure.
17693 * @param[in] meter_id
17695 * @param[in] action_flags
17696 * Holds the actions detected until now.
17697 * @param[out] is_rss
17699 * @param[out] hierarchy_domain
17700 * The domain bitmap for hierarchy policy.
17701 * @param[out] error
17702 * Perform verbose error reporting if not NULL. Initialized in case of
17706 * 0 on success, otherwise negative errno value with error set.
17709 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17711 uint64_t action_flags,
17713 uint8_t *hierarchy_domain,
17714 struct rte_mtr_error *error)
17716 struct mlx5_priv *priv = dev->data->dev_private;
17717 struct mlx5_flow_meter_info *fm;
17718 struct mlx5_flow_meter_policy *policy;
17721 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17722 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17723 return -rte_mtr_error_set(error, EINVAL,
17724 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17726 "Multiple fate actions not supported.");
17727 *hierarchy_domain = 0;
17729 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17731 return -rte_mtr_error_set(error, EINVAL,
17732 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17733 "Meter not found in meter hierarchy.");
17734 if (fm->def_policy)
17735 return -rte_mtr_error_set(error, EINVAL,
17736 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17737 "Non termination meter not supported in hierarchy.");
17738 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17739 MLX5_ASSERT(policy);
17741 * Only inherit the supported domains of the first meter in
17743 * One meter supports at least one domain.
17745 if (!*hierarchy_domain) {
17746 if (policy->transfer)
17747 *hierarchy_domain |=
17748 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17749 if (policy->ingress)
17750 *hierarchy_domain |=
17751 MLX5_MTR_DOMAIN_INGRESS_BIT;
17752 if (policy->egress)
17753 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17755 if (!policy->is_hierarchy) {
17756 *is_rss = policy->is_rss;
17759 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17760 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17761 return -rte_mtr_error_set(error, EINVAL,
17762 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17763 "Exceed max hierarchy meter number.");
17769 * Validate meter policy actions.
17770 * Dispatcher for action type specific validation.
17773 * Pointer to the Ethernet device structure.
17774 * @param[in] action
17775 * The meter policy action object to validate.
17777 * Attributes of flow to determine steering domain.
17778 * @param[out] error
17779 * Perform verbose error reporting if not NULL. Initialized in case of
17783 * 0 on success, otherwise negative errno value.
17786 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17787 const struct rte_flow_action *actions[RTE_COLORS],
17788 struct rte_flow_attr *attr,
17790 uint8_t *domain_bitmap,
17791 uint8_t *policy_mode,
17792 struct rte_mtr_error *error)
17794 struct mlx5_priv *priv = dev->data->dev_private;
17795 struct mlx5_dev_config *dev_conf = &priv->config;
17796 const struct rte_flow_action *act;
17797 uint64_t action_flags[RTE_COLORS] = {0};
17800 struct rte_flow_error flow_err;
17801 uint8_t domain_color[RTE_COLORS] = {0};
17802 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17803 uint8_t hierarchy_domain = 0;
17804 const struct rte_flow_action_meter *mtr;
17805 bool def_green = false;
17806 bool def_yellow = false;
17807 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17809 if (!priv->config.dv_esw_en)
17810 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17811 *domain_bitmap = def_domain;
17812 /* Red color could only support DROP action. */
17813 if (!actions[RTE_COLOR_RED] ||
17814 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17815 return -rte_mtr_error_set(error, ENOTSUP,
17816 RTE_MTR_ERROR_TYPE_METER_POLICY,
17817 NULL, "Red color only supports drop action.");
17819 * Check default policy actions:
17820 * Green / Yellow: no action, Red: drop action
17821 * Either G or Y will trigger default policy actions to be created.
17823 if (!actions[RTE_COLOR_GREEN] ||
17824 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17826 if (!actions[RTE_COLOR_YELLOW] ||
17827 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17829 if (def_green && def_yellow) {
17830 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17832 } else if (!def_green && def_yellow) {
17833 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17834 } else if (def_green && !def_yellow) {
17835 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17837 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17839 /* Set to empty string in case of NULL pointer access by user. */
17840 flow_err.message = "";
17841 for (i = 0; i < RTE_COLORS; i++) {
17843 for (action_flags[i] = 0, actions_n = 0;
17844 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17846 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17847 return -rte_mtr_error_set(error, ENOTSUP,
17848 RTE_MTR_ERROR_TYPE_METER_POLICY,
17849 NULL, "too many actions");
17850 switch (act->type) {
17851 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17852 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17853 if (!priv->config.dv_esw_en)
17854 return -rte_mtr_error_set(error,
17856 RTE_MTR_ERROR_TYPE_METER_POLICY,
17857 NULL, "PORT action validate check"
17858 " fail for ESW disable");
17859 ret = flow_dv_validate_action_port_id(dev,
17861 act, attr, &flow_err);
17863 return -rte_mtr_error_set(error,
17865 RTE_MTR_ERROR_TYPE_METER_POLICY,
17866 NULL, flow_err.message ?
17868 "PORT action validate check fail");
17870 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17872 case RTE_FLOW_ACTION_TYPE_MARK:
17873 ret = flow_dv_validate_action_mark(dev, act,
17877 return -rte_mtr_error_set(error,
17879 RTE_MTR_ERROR_TYPE_METER_POLICY,
17880 NULL, flow_err.message ?
17882 "Mark action validate check fail");
17883 if (dev_conf->dv_xmeta_en !=
17884 MLX5_XMETA_MODE_LEGACY)
17885 return -rte_mtr_error_set(error,
17887 RTE_MTR_ERROR_TYPE_METER_POLICY,
17888 NULL, "Extend MARK action is "
17889 "not supported. Please try use "
17890 "default policy for meter.");
17891 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17894 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17895 ret = flow_dv_validate_action_set_tag(dev,
17896 act, action_flags[i],
17899 return -rte_mtr_error_set(error,
17901 RTE_MTR_ERROR_TYPE_METER_POLICY,
17902 NULL, flow_err.message ?
17904 "Set tag action validate check fail");
17905 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17908 case RTE_FLOW_ACTION_TYPE_DROP:
17909 ret = mlx5_flow_validate_action_drop
17910 (action_flags[i], attr, &flow_err);
17912 return -rte_mtr_error_set(error,
17914 RTE_MTR_ERROR_TYPE_METER_POLICY,
17915 NULL, flow_err.message ?
17917 "Drop action validate check fail");
17918 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17921 case RTE_FLOW_ACTION_TYPE_QUEUE:
17923 * Check whether extensive
17924 * metadata feature is engaged.
17926 if (dev_conf->dv_flow_en &&
17927 (dev_conf->dv_xmeta_en !=
17928 MLX5_XMETA_MODE_LEGACY) &&
17929 mlx5_flow_ext_mreg_supported(dev))
17930 return -rte_mtr_error_set(error,
17932 RTE_MTR_ERROR_TYPE_METER_POLICY,
17933 NULL, "Queue action with meta "
17934 "is not supported. Please try use "
17935 "default policy for meter.");
17936 ret = mlx5_flow_validate_action_queue(act,
17937 action_flags[i], dev,
17940 return -rte_mtr_error_set(error,
17942 RTE_MTR_ERROR_TYPE_METER_POLICY,
17943 NULL, flow_err.message ?
17945 "Queue action validate check fail");
17946 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17949 case RTE_FLOW_ACTION_TYPE_RSS:
17950 if (dev_conf->dv_flow_en &&
17951 (dev_conf->dv_xmeta_en !=
17952 MLX5_XMETA_MODE_LEGACY) &&
17953 mlx5_flow_ext_mreg_supported(dev))
17954 return -rte_mtr_error_set(error,
17956 RTE_MTR_ERROR_TYPE_METER_POLICY,
17957 NULL, "RSS action with meta "
17958 "is not supported. Please try use "
17959 "default policy for meter.");
17960 ret = mlx5_validate_action_rss(dev, act,
17963 return -rte_mtr_error_set(error,
17965 RTE_MTR_ERROR_TYPE_METER_POLICY,
17966 NULL, flow_err.message ?
17968 "RSS action validate check fail");
17969 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17971 /* Either G or Y will set the RSS. */
17972 rss_color[i] = act->conf;
17974 case RTE_FLOW_ACTION_TYPE_JUMP:
17975 ret = flow_dv_validate_action_jump(dev,
17976 NULL, act, action_flags[i],
17977 attr, true, &flow_err);
17979 return -rte_mtr_error_set(error,
17981 RTE_MTR_ERROR_TYPE_METER_POLICY,
17982 NULL, flow_err.message ?
17984 "Jump action validate check fail");
17986 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17989 * Only the last meter in the hierarchy will support
17990 * the YELLOW color steering. Then in the meter policy
17991 * actions list, there should be no other meter inside.
17993 case RTE_FLOW_ACTION_TYPE_METER:
17994 if (i != RTE_COLOR_GREEN)
17995 return -rte_mtr_error_set(error,
17997 RTE_MTR_ERROR_TYPE_METER_POLICY,
17999 "Meter hierarchy only supports GREEN color.");
18000 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
18001 return -rte_mtr_error_set(error,
18003 RTE_MTR_ERROR_TYPE_METER_POLICY,
18005 "No yellow policy should be provided in meter hierarchy.");
18007 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18017 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18020 return -rte_mtr_error_set(error, ENOTSUP,
18021 RTE_MTR_ERROR_TYPE_METER_POLICY,
18023 "Doesn't support optional action");
18026 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18027 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18028 } else if ((action_flags[i] &
18029 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18030 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18032 * Only support MLX5_XMETA_MODE_LEGACY
18033 * so MARK action is only in ingress domain.
18035 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18037 domain_color[i] = def_domain;
18038 if (action_flags[i] &&
18039 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18041 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18043 if (action_flags[i] &
18044 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18045 domain_color[i] &= hierarchy_domain;
18047 * Non-termination actions only support NIC Tx domain.
18048 * The adjustion should be skipped when there is no
18049 * action or only END is provided. The default domains
18050 * bit-mask is set to find the MIN intersection.
18051 * The action flags checking should also be skipped.
18053 if ((def_green && i == RTE_COLOR_GREEN) ||
18054 (def_yellow && i == RTE_COLOR_YELLOW))
18057 * Validate the drop action mutual exclusion
18058 * with other actions. Drop action is mutually-exclusive
18059 * with any other action, except for Count action.
18061 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18062 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18063 return -rte_mtr_error_set(error, ENOTSUP,
18064 RTE_MTR_ERROR_TYPE_METER_POLICY,
18065 NULL, "Drop action is mutually-exclusive "
18066 "with any other action");
18068 /* Eswitch has few restrictions on using items and actions */
18069 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18070 if (!mlx5_flow_ext_mreg_supported(dev) &&
18071 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18072 return -rte_mtr_error_set(error, ENOTSUP,
18073 RTE_MTR_ERROR_TYPE_METER_POLICY,
18074 NULL, "unsupported action MARK");
18075 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18076 return -rte_mtr_error_set(error, ENOTSUP,
18077 RTE_MTR_ERROR_TYPE_METER_POLICY,
18078 NULL, "unsupported action QUEUE");
18079 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18080 return -rte_mtr_error_set(error, ENOTSUP,
18081 RTE_MTR_ERROR_TYPE_METER_POLICY,
18082 NULL, "unsupported action RSS");
18083 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18084 return -rte_mtr_error_set(error, ENOTSUP,
18085 RTE_MTR_ERROR_TYPE_METER_POLICY,
18086 NULL, "no fate action is found");
18088 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18089 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18090 if ((domain_color[i] &
18091 MLX5_MTR_DOMAIN_EGRESS_BIT))
18093 MLX5_MTR_DOMAIN_EGRESS_BIT;
18095 return -rte_mtr_error_set(error,
18097 RTE_MTR_ERROR_TYPE_METER_POLICY,
18099 "no fate action is found");
18103 /* If both colors have RSS, the attributes should be the same. */
18104 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18105 rss_color[RTE_COLOR_YELLOW]))
18106 return -rte_mtr_error_set(error, EINVAL,
18107 RTE_MTR_ERROR_TYPE_METER_POLICY,
18108 NULL, "policy RSS attr conflict");
18109 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18111 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18112 if (!def_green && !def_yellow &&
18113 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18114 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18115 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18116 return -rte_mtr_error_set(error, EINVAL,
18117 RTE_MTR_ERROR_TYPE_METER_POLICY,
18118 NULL, "policy domains conflict");
18120 * At least one color policy is listed in the actions, the domains
18121 * to be supported should be the intersection.
18123 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18124 domain_color[RTE_COLOR_YELLOW];
18129 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18131 struct mlx5_priv *priv = dev->data->dev_private;
18134 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18135 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18140 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18141 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18145 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18146 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18154 * Discover the number of available flow priorities
18155 * by trying to create a flow with the highest priority value
18156 * for each possible number.
18161 * List of possible number of available priorities.
18162 * @param[in] vprio_n
18163 * Size of @p vprio array.
18165 * On success, number of available flow priorities.
18166 * On failure, a negative errno-style code and rte_errno is set.
18169 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18170 const uint16_t *vprio, int vprio_n)
18172 struct mlx5_priv *priv = dev->data->dev_private;
18173 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18174 struct rte_flow_item_eth eth;
18175 struct rte_flow_item item = {
18176 .type = RTE_FLOW_ITEM_TYPE_ETH,
18180 struct mlx5_flow_dv_matcher matcher = {
18182 .size = sizeof(matcher.mask.buf),
18185 union mlx5_flow_tbl_key tbl_key;
18186 struct mlx5_flow flow;
18188 struct rte_flow_error error;
18190 int i, err, ret = -ENOTSUP;
18193 * Prepare a flow with a catch-all pattern and a drop action.
18194 * Use drop queue, because shared drop action may be unavailable.
18196 action = priv->drop_queue.hrxq->action;
18197 if (action == NULL) {
18198 DRV_LOG(ERR, "Priority discovery requires a drop action");
18199 rte_errno = ENOTSUP;
18202 memset(&flow, 0, sizeof(flow));
18203 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18204 if (flow.handle == NULL) {
18205 DRV_LOG(ERR, "Cannot create flow handle");
18206 rte_errno = ENOMEM;
18209 flow.ingress = true;
18210 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18211 flow.dv.actions[0] = action;
18212 flow.dv.actions_n = 1;
18213 memset(ð, 0, sizeof(eth));
18214 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18215 &item, /* inner */ false, /* group */ 0);
18216 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18217 for (i = 0; i < vprio_n; i++) {
18218 /* Configure the next proposed maximum priority. */
18219 matcher.priority = vprio[i] - 1;
18220 memset(&tbl_key, 0, sizeof(tbl_key));
18221 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18226 /* This action is pure SW and must always succeed. */
18227 DRV_LOG(ERR, "Cannot register matcher");
18231 /* Try to apply the flow to HW. */
18232 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18233 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18234 err = mlx5_flow_os_create_flow
18235 (flow.handle->dvh.matcher->matcher_object,
18236 (void *)&flow.dv.value, flow.dv.actions_n,
18237 flow.dv.actions, &flow.handle->drv_flow);
18239 claim_zero(mlx5_flow_os_destroy_flow
18240 (flow.handle->drv_flow));
18241 flow.handle->drv_flow = NULL;
18243 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18248 mlx5_ipool_free(pool, flow.handle_idx);
18249 /* Set rte_errno if no expected priority value matched. */
18255 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18256 .validate = flow_dv_validate,
18257 .prepare = flow_dv_prepare,
18258 .translate = flow_dv_translate,
18259 .apply = flow_dv_apply,
18260 .remove = flow_dv_remove,
18261 .destroy = flow_dv_destroy,
18262 .query = flow_dv_query,
18263 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18264 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18265 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18266 .create_meter = flow_dv_mtr_alloc,
18267 .free_meter = flow_dv_aso_mtr_release_to_pool,
18268 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18269 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18270 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18271 .create_policy_rules = flow_dv_create_policy_rules,
18272 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18273 .create_def_policy = flow_dv_create_def_policy,
18274 .destroy_def_policy = flow_dv_destroy_def_policy,
18275 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18276 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18277 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18278 .counter_alloc = flow_dv_counter_allocate,
18279 .counter_free = flow_dv_counter_free,
18280 .counter_query = flow_dv_counter_query,
18281 .get_aged_flows = flow_dv_get_aged_flows,
18282 .action_validate = flow_dv_action_validate,
18283 .action_create = flow_dv_action_create,
18284 .action_destroy = flow_dv_action_destroy,
18285 .action_update = flow_dv_action_update,
18286 .action_query = flow_dv_action_query,
18287 .sync_domain = flow_dv_sync_domain,
18288 .discover_priorities = flow_dv_discover_priorities,
18289 .item_create = flow_dv_item_create,
18290 .item_release = flow_dv_item_release,
18293 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */