1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
53 /* VLAN header definitions */
54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
74 struct mlx5_flow_tbl_resource *tbl);
77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
80 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
81 uint32_t encap_decap_idx);
84 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
88 * Initialize flow attributes structure according to flow items' types.
90 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
91 * mode. For tunnel mode, the items to be modified are the outermost ones.
94 * Pointer to item specification.
96 * Pointer to flow attributes structure.
98 * Pointer to the sub flow.
99 * @param[in] tunnel_decap
100 * Whether action is after tunnel decapsulation.
103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
104 struct mlx5_flow *dev_flow, bool tunnel_decap)
106 uint64_t layers = dev_flow->handle->layers;
109 * If layers is already initialized, it means this dev_flow is the
110 * suffix flow, the layers flags is set by the prefix flow. Need to
111 * use the layer flags from prefix flow as the suffix flow may not
112 * have the user defined items as the flow is split.
115 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
117 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
119 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
126 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
127 uint8_t next_protocol = 0xff;
128 switch (item->type) {
129 case RTE_FLOW_ITEM_TYPE_GRE:
130 case RTE_FLOW_ITEM_TYPE_NVGRE:
131 case RTE_FLOW_ITEM_TYPE_VXLAN:
132 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
133 case RTE_FLOW_ITEM_TYPE_GENEVE:
134 case RTE_FLOW_ITEM_TYPE_MPLS:
138 case RTE_FLOW_ITEM_TYPE_IPV4:
141 if (item->mask != NULL &&
142 ((const struct rte_flow_item_ipv4 *)
143 item->mask)->hdr.next_proto_id)
145 ((const struct rte_flow_item_ipv4 *)
146 (item->spec))->hdr.next_proto_id &
147 ((const struct rte_flow_item_ipv4 *)
148 (item->mask))->hdr.next_proto_id;
149 if ((next_protocol == IPPROTO_IPIP ||
150 next_protocol == IPPROTO_IPV6) && tunnel_decap)
153 case RTE_FLOW_ITEM_TYPE_IPV6:
156 if (item->mask != NULL &&
157 ((const struct rte_flow_item_ipv6 *)
158 item->mask)->hdr.proto)
160 ((const struct rte_flow_item_ipv6 *)
161 (item->spec))->hdr.proto &
162 ((const struct rte_flow_item_ipv6 *)
163 (item->mask))->hdr.proto;
164 if ((next_protocol == IPPROTO_IPIP ||
165 next_protocol == IPPROTO_IPV6) && tunnel_decap)
168 case RTE_FLOW_ITEM_TYPE_UDP:
172 case RTE_FLOW_ITEM_TYPE_TCP:
184 * Convert rte_mtr_color to mlx5 color.
193 rte_col_2_mlx5_col(enum rte_color rcol)
196 case RTE_COLOR_GREEN:
197 return MLX5_FLOW_COLOR_GREEN;
198 case RTE_COLOR_YELLOW:
199 return MLX5_FLOW_COLOR_YELLOW;
201 return MLX5_FLOW_COLOR_RED;
205 return MLX5_FLOW_COLOR_UNDEFINED;
208 struct field_modify_info {
209 uint32_t size; /* Size of field in protocol header, in bytes. */
210 uint32_t offset; /* Offset of field in protocol header, in bytes. */
211 enum mlx5_modification_field id;
214 struct field_modify_info modify_eth[] = {
215 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
216 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
217 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
218 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
222 struct field_modify_info modify_vlan_out_first_vid[] = {
223 /* Size in bits !!! */
224 {12, 0, MLX5_MODI_OUT_FIRST_VID},
228 struct field_modify_info modify_ipv4[] = {
229 {1, 1, MLX5_MODI_OUT_IP_DSCP},
230 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
231 {4, 12, MLX5_MODI_OUT_SIPV4},
232 {4, 16, MLX5_MODI_OUT_DIPV4},
236 struct field_modify_info modify_ipv6[] = {
237 {1, 0, MLX5_MODI_OUT_IP_DSCP},
238 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
239 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
240 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
241 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
242 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
243 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
244 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
245 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
246 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
250 struct field_modify_info modify_udp[] = {
251 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
252 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
256 struct field_modify_info modify_tcp[] = {
257 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
258 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
259 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
260 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
266 uint8_t next_protocol, uint64_t *item_flags,
269 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
270 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
271 if (next_protocol == IPPROTO_IPIP) {
272 *item_flags |= MLX5_FLOW_LAYER_IPIP;
275 if (next_protocol == IPPROTO_IPV6) {
276 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
282 * Acquire the synchronizing object to protect multithreaded access
283 * to shared dv context. Lock occurs only if context is actually
284 * shared, i.e. we have multiport IB device and representors are
288 * Pointer to the rte_eth_dev structure.
291 flow_dv_shared_lock(struct rte_eth_dev *dev)
293 struct mlx5_priv *priv = dev->data->dev_private;
294 struct mlx5_dev_ctx_shared *sh = priv->sh;
296 if (sh->refcnt > 1) {
299 ret = pthread_mutex_lock(&sh->dv_mutex);
306 flow_dv_shared_unlock(struct rte_eth_dev *dev)
308 struct mlx5_priv *priv = dev->data->dev_private;
309 struct mlx5_dev_ctx_shared *sh = priv->sh;
311 if (sh->refcnt > 1) {
314 ret = pthread_mutex_unlock(&sh->dv_mutex);
320 /* Update VLAN's VID/PCP based on input rte_flow_action.
323 * Pointer to struct rte_flow_action.
325 * Pointer to struct rte_vlan_hdr.
328 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
329 struct rte_vlan_hdr *vlan)
332 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
334 ((const struct rte_flow_action_of_set_vlan_pcp *)
335 action->conf)->vlan_pcp;
336 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
337 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
338 vlan->vlan_tci |= vlan_tci;
339 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
340 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
341 vlan->vlan_tci |= rte_be_to_cpu_16
342 (((const struct rte_flow_action_of_set_vlan_vid *)
343 action->conf)->vlan_vid);
348 * Fetch 1, 2, 3 or 4 byte field from the byte array
349 * and return as unsigned integer in host-endian format.
352 * Pointer to data array.
354 * Size of field to extract.
357 * converted field in host endian format.
359 static inline uint32_t
360 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
369 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
372 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
373 ret = (ret << 8) | *(data + sizeof(uint16_t));
376 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
387 * Convert modify-header action to DV specification.
389 * Data length of each action is determined by provided field description
390 * and the item mask. Data bit offset and width of each action is determined
391 * by provided item mask.
394 * Pointer to item specification.
396 * Pointer to field modification information.
397 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
398 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
399 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
401 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
402 * Negative offset value sets the same offset as source offset.
403 * size field is ignored, value is taken from source field.
404 * @param[in,out] resource
405 * Pointer to the modify-header resource.
407 * Type of modification.
409 * Pointer to the error structure.
412 * 0 on success, a negative errno value otherwise and rte_errno is set.
415 flow_dv_convert_modify_action(struct rte_flow_item *item,
416 struct field_modify_info *field,
417 struct field_modify_info *dcopy,
418 struct mlx5_flow_dv_modify_hdr_resource *resource,
419 uint32_t type, struct rte_flow_error *error)
421 uint32_t i = resource->actions_num;
422 struct mlx5_modification_cmd *actions = resource->actions;
425 * The item and mask are provided in big-endian format.
426 * The fields should be presented as in big-endian format either.
427 * Mask must be always present, it defines the actual field width.
429 MLX5_ASSERT(item->mask);
430 MLX5_ASSERT(field->size);
437 if (i >= MLX5_MAX_MODIFY_NUM)
438 return rte_flow_error_set(error, EINVAL,
439 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
440 "too many items to modify");
441 /* Fetch variable byte size mask from the array. */
442 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
443 field->offset, field->size);
448 /* Deduce actual data width in bits from mask value. */
449 off_b = rte_bsf32(mask);
450 size_b = sizeof(uint32_t) * CHAR_BIT -
451 off_b - __builtin_clz(mask);
453 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
454 actions[i] = (struct mlx5_modification_cmd) {
460 /* Convert entire record to expected big-endian format. */
461 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
462 if (type == MLX5_MODIFICATION_TYPE_COPY) {
464 actions[i].dst_field = dcopy->id;
465 actions[i].dst_offset =
466 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
467 /* Convert entire record to big-endian format. */
468 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
470 MLX5_ASSERT(item->spec);
471 data = flow_dv_fetch_field((const uint8_t *)item->spec +
472 field->offset, field->size);
473 /* Shift out the trailing masked bits from data. */
474 data = (data & mask) >> off_b;
475 actions[i].data1 = rte_cpu_to_be_32(data);
479 } while (field->size);
480 if (resource->actions_num == i)
481 return rte_flow_error_set(error, EINVAL,
482 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
483 "invalid modification flow item");
484 resource->actions_num = i;
489 * Convert modify-header set IPv4 address action to DV specification.
491 * @param[in,out] resource
492 * Pointer to the modify-header resource.
494 * Pointer to action specification.
496 * Pointer to the error structure.
499 * 0 on success, a negative errno value otherwise and rte_errno is set.
502 flow_dv_convert_action_modify_ipv4
503 (struct mlx5_flow_dv_modify_hdr_resource *resource,
504 const struct rte_flow_action *action,
505 struct rte_flow_error *error)
507 const struct rte_flow_action_set_ipv4 *conf =
508 (const struct rte_flow_action_set_ipv4 *)(action->conf);
509 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
510 struct rte_flow_item_ipv4 ipv4;
511 struct rte_flow_item_ipv4 ipv4_mask;
513 memset(&ipv4, 0, sizeof(ipv4));
514 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
515 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
516 ipv4.hdr.src_addr = conf->ipv4_addr;
517 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
519 ipv4.hdr.dst_addr = conf->ipv4_addr;
520 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
523 item.mask = &ipv4_mask;
524 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
525 MLX5_MODIFICATION_TYPE_SET, error);
529 * Convert modify-header set IPv6 address action to DV specification.
531 * @param[in,out] resource
532 * Pointer to the modify-header resource.
534 * Pointer to action specification.
536 * Pointer to the error structure.
539 * 0 on success, a negative errno value otherwise and rte_errno is set.
542 flow_dv_convert_action_modify_ipv6
543 (struct mlx5_flow_dv_modify_hdr_resource *resource,
544 const struct rte_flow_action *action,
545 struct rte_flow_error *error)
547 const struct rte_flow_action_set_ipv6 *conf =
548 (const struct rte_flow_action_set_ipv6 *)(action->conf);
549 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
550 struct rte_flow_item_ipv6 ipv6;
551 struct rte_flow_item_ipv6 ipv6_mask;
553 memset(&ipv6, 0, sizeof(ipv6));
554 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
555 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
556 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
557 sizeof(ipv6.hdr.src_addr));
558 memcpy(&ipv6_mask.hdr.src_addr,
559 &rte_flow_item_ipv6_mask.hdr.src_addr,
560 sizeof(ipv6.hdr.src_addr));
562 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
563 sizeof(ipv6.hdr.dst_addr));
564 memcpy(&ipv6_mask.hdr.dst_addr,
565 &rte_flow_item_ipv6_mask.hdr.dst_addr,
566 sizeof(ipv6.hdr.dst_addr));
569 item.mask = &ipv6_mask;
570 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
571 MLX5_MODIFICATION_TYPE_SET, error);
575 * Convert modify-header set MAC address action to DV specification.
577 * @param[in,out] resource
578 * Pointer to the modify-header resource.
580 * Pointer to action specification.
582 * Pointer to the error structure.
585 * 0 on success, a negative errno value otherwise and rte_errno is set.
588 flow_dv_convert_action_modify_mac
589 (struct mlx5_flow_dv_modify_hdr_resource *resource,
590 const struct rte_flow_action *action,
591 struct rte_flow_error *error)
593 const struct rte_flow_action_set_mac *conf =
594 (const struct rte_flow_action_set_mac *)(action->conf);
595 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
596 struct rte_flow_item_eth eth;
597 struct rte_flow_item_eth eth_mask;
599 memset(ð, 0, sizeof(eth));
600 memset(ð_mask, 0, sizeof(eth_mask));
601 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
602 memcpy(ð.src.addr_bytes, &conf->mac_addr,
603 sizeof(eth.src.addr_bytes));
604 memcpy(ð_mask.src.addr_bytes,
605 &rte_flow_item_eth_mask.src.addr_bytes,
606 sizeof(eth_mask.src.addr_bytes));
608 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
609 sizeof(eth.dst.addr_bytes));
610 memcpy(ð_mask.dst.addr_bytes,
611 &rte_flow_item_eth_mask.dst.addr_bytes,
612 sizeof(eth_mask.dst.addr_bytes));
615 item.mask = ð_mask;
616 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
617 MLX5_MODIFICATION_TYPE_SET, error);
621 * Convert modify-header set VLAN VID action to DV specification.
623 * @param[in,out] resource
624 * Pointer to the modify-header resource.
626 * Pointer to action specification.
628 * Pointer to the error structure.
631 * 0 on success, a negative errno value otherwise and rte_errno is set.
634 flow_dv_convert_action_modify_vlan_vid
635 (struct mlx5_flow_dv_modify_hdr_resource *resource,
636 const struct rte_flow_action *action,
637 struct rte_flow_error *error)
639 const struct rte_flow_action_of_set_vlan_vid *conf =
640 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
641 int i = resource->actions_num;
642 struct mlx5_modification_cmd *actions = resource->actions;
643 struct field_modify_info *field = modify_vlan_out_first_vid;
645 if (i >= MLX5_MAX_MODIFY_NUM)
646 return rte_flow_error_set(error, EINVAL,
647 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
648 "too many items to modify");
649 actions[i] = (struct mlx5_modification_cmd) {
650 .action_type = MLX5_MODIFICATION_TYPE_SET,
652 .length = field->size,
653 .offset = field->offset,
655 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
656 actions[i].data1 = conf->vlan_vid;
657 actions[i].data1 = actions[i].data1 << 16;
658 resource->actions_num = ++i;
663 * Convert modify-header set TP action to DV specification.
665 * @param[in,out] resource
666 * Pointer to the modify-header resource.
668 * Pointer to action specification.
670 * Pointer to rte_flow_item objects list.
672 * Pointer to flow attributes structure.
673 * @param[in] dev_flow
674 * Pointer to the sub flow.
675 * @param[in] tunnel_decap
676 * Whether action is after tunnel decapsulation.
678 * Pointer to the error structure.
681 * 0 on success, a negative errno value otherwise and rte_errno is set.
684 flow_dv_convert_action_modify_tp
685 (struct mlx5_flow_dv_modify_hdr_resource *resource,
686 const struct rte_flow_action *action,
687 const struct rte_flow_item *items,
688 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
689 bool tunnel_decap, struct rte_flow_error *error)
691 const struct rte_flow_action_set_tp *conf =
692 (const struct rte_flow_action_set_tp *)(action->conf);
693 struct rte_flow_item item;
694 struct rte_flow_item_udp udp;
695 struct rte_flow_item_udp udp_mask;
696 struct rte_flow_item_tcp tcp;
697 struct rte_flow_item_tcp tcp_mask;
698 struct field_modify_info *field;
701 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
703 memset(&udp, 0, sizeof(udp));
704 memset(&udp_mask, 0, sizeof(udp_mask));
705 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
706 udp.hdr.src_port = conf->port;
707 udp_mask.hdr.src_port =
708 rte_flow_item_udp_mask.hdr.src_port;
710 udp.hdr.dst_port = conf->port;
711 udp_mask.hdr.dst_port =
712 rte_flow_item_udp_mask.hdr.dst_port;
714 item.type = RTE_FLOW_ITEM_TYPE_UDP;
716 item.mask = &udp_mask;
719 MLX5_ASSERT(attr->tcp);
720 memset(&tcp, 0, sizeof(tcp));
721 memset(&tcp_mask, 0, sizeof(tcp_mask));
722 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
723 tcp.hdr.src_port = conf->port;
724 tcp_mask.hdr.src_port =
725 rte_flow_item_tcp_mask.hdr.src_port;
727 tcp.hdr.dst_port = conf->port;
728 tcp_mask.hdr.dst_port =
729 rte_flow_item_tcp_mask.hdr.dst_port;
731 item.type = RTE_FLOW_ITEM_TYPE_TCP;
733 item.mask = &tcp_mask;
736 return flow_dv_convert_modify_action(&item, field, NULL, resource,
737 MLX5_MODIFICATION_TYPE_SET, error);
741 * Convert modify-header set TTL action to DV specification.
743 * @param[in,out] resource
744 * Pointer to the modify-header resource.
746 * Pointer to action specification.
748 * Pointer to rte_flow_item objects list.
750 * Pointer to flow attributes structure.
751 * @param[in] dev_flow
752 * Pointer to the sub flow.
753 * @param[in] tunnel_decap
754 * Whether action is after tunnel decapsulation.
756 * Pointer to the error structure.
759 * 0 on success, a negative errno value otherwise and rte_errno is set.
762 flow_dv_convert_action_modify_ttl
763 (struct mlx5_flow_dv_modify_hdr_resource *resource,
764 const struct rte_flow_action *action,
765 const struct rte_flow_item *items,
766 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
767 bool tunnel_decap, struct rte_flow_error *error)
769 const struct rte_flow_action_set_ttl *conf =
770 (const struct rte_flow_action_set_ttl *)(action->conf);
771 struct rte_flow_item item;
772 struct rte_flow_item_ipv4 ipv4;
773 struct rte_flow_item_ipv4 ipv4_mask;
774 struct rte_flow_item_ipv6 ipv6;
775 struct rte_flow_item_ipv6 ipv6_mask;
776 struct field_modify_info *field;
779 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
781 memset(&ipv4, 0, sizeof(ipv4));
782 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
783 ipv4.hdr.time_to_live = conf->ttl_value;
784 ipv4_mask.hdr.time_to_live = 0xFF;
785 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
787 item.mask = &ipv4_mask;
790 MLX5_ASSERT(attr->ipv6);
791 memset(&ipv6, 0, sizeof(ipv6));
792 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
793 ipv6.hdr.hop_limits = conf->ttl_value;
794 ipv6_mask.hdr.hop_limits = 0xFF;
795 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
797 item.mask = &ipv6_mask;
800 return flow_dv_convert_modify_action(&item, field, NULL, resource,
801 MLX5_MODIFICATION_TYPE_SET, error);
805 * Convert modify-header decrement TTL action to DV specification.
807 * @param[in,out] resource
808 * Pointer to the modify-header resource.
810 * Pointer to action specification.
812 * Pointer to rte_flow_item objects list.
814 * Pointer to flow attributes structure.
815 * @param[in] dev_flow
816 * Pointer to the sub flow.
817 * @param[in] tunnel_decap
818 * Whether action is after tunnel decapsulation.
820 * Pointer to the error structure.
823 * 0 on success, a negative errno value otherwise and rte_errno is set.
826 flow_dv_convert_action_modify_dec_ttl
827 (struct mlx5_flow_dv_modify_hdr_resource *resource,
828 const struct rte_flow_item *items,
829 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
830 bool tunnel_decap, struct rte_flow_error *error)
832 struct rte_flow_item item;
833 struct rte_flow_item_ipv4 ipv4;
834 struct rte_flow_item_ipv4 ipv4_mask;
835 struct rte_flow_item_ipv6 ipv6;
836 struct rte_flow_item_ipv6 ipv6_mask;
837 struct field_modify_info *field;
840 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
842 memset(&ipv4, 0, sizeof(ipv4));
843 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
844 ipv4.hdr.time_to_live = 0xFF;
845 ipv4_mask.hdr.time_to_live = 0xFF;
846 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
848 item.mask = &ipv4_mask;
851 MLX5_ASSERT(attr->ipv6);
852 memset(&ipv6, 0, sizeof(ipv6));
853 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
854 ipv6.hdr.hop_limits = 0xFF;
855 ipv6_mask.hdr.hop_limits = 0xFF;
856 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
858 item.mask = &ipv6_mask;
861 return flow_dv_convert_modify_action(&item, field, NULL, resource,
862 MLX5_MODIFICATION_TYPE_ADD, error);
866 * Convert modify-header increment/decrement TCP Sequence number
867 * to DV specification.
869 * @param[in,out] resource
870 * Pointer to the modify-header resource.
872 * Pointer to action specification.
874 * Pointer to the error structure.
877 * 0 on success, a negative errno value otherwise and rte_errno is set.
880 flow_dv_convert_action_modify_tcp_seq
881 (struct mlx5_flow_dv_modify_hdr_resource *resource,
882 const struct rte_flow_action *action,
883 struct rte_flow_error *error)
885 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
886 uint64_t value = rte_be_to_cpu_32(*conf);
887 struct rte_flow_item item;
888 struct rte_flow_item_tcp tcp;
889 struct rte_flow_item_tcp tcp_mask;
891 memset(&tcp, 0, sizeof(tcp));
892 memset(&tcp_mask, 0, sizeof(tcp_mask));
893 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
895 * The HW has no decrement operation, only increment operation.
896 * To simulate decrement X from Y using increment operation
897 * we need to add UINT32_MAX X times to Y.
898 * Each adding of UINT32_MAX decrements Y by 1.
901 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
902 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
903 item.type = RTE_FLOW_ITEM_TYPE_TCP;
905 item.mask = &tcp_mask;
906 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
907 MLX5_MODIFICATION_TYPE_ADD, error);
911 * Convert modify-header increment/decrement TCP Acknowledgment number
912 * to DV specification.
914 * @param[in,out] resource
915 * Pointer to the modify-header resource.
917 * Pointer to action specification.
919 * Pointer to the error structure.
922 * 0 on success, a negative errno value otherwise and rte_errno is set.
925 flow_dv_convert_action_modify_tcp_ack
926 (struct mlx5_flow_dv_modify_hdr_resource *resource,
927 const struct rte_flow_action *action,
928 struct rte_flow_error *error)
930 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
931 uint64_t value = rte_be_to_cpu_32(*conf);
932 struct rte_flow_item item;
933 struct rte_flow_item_tcp tcp;
934 struct rte_flow_item_tcp tcp_mask;
936 memset(&tcp, 0, sizeof(tcp));
937 memset(&tcp_mask, 0, sizeof(tcp_mask));
938 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
940 * The HW has no decrement operation, only increment operation.
941 * To simulate decrement X from Y using increment operation
942 * we need to add UINT32_MAX X times to Y.
943 * Each adding of UINT32_MAX decrements Y by 1.
946 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
947 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
948 item.type = RTE_FLOW_ITEM_TYPE_TCP;
950 item.mask = &tcp_mask;
951 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
952 MLX5_MODIFICATION_TYPE_ADD, error);
955 static enum mlx5_modification_field reg_to_field[] = {
956 [REG_NON] = MLX5_MODI_OUT_NONE,
957 [REG_A] = MLX5_MODI_META_DATA_REG_A,
958 [REG_B] = MLX5_MODI_META_DATA_REG_B,
959 [REG_C_0] = MLX5_MODI_META_REG_C_0,
960 [REG_C_1] = MLX5_MODI_META_REG_C_1,
961 [REG_C_2] = MLX5_MODI_META_REG_C_2,
962 [REG_C_3] = MLX5_MODI_META_REG_C_3,
963 [REG_C_4] = MLX5_MODI_META_REG_C_4,
964 [REG_C_5] = MLX5_MODI_META_REG_C_5,
965 [REG_C_6] = MLX5_MODI_META_REG_C_6,
966 [REG_C_7] = MLX5_MODI_META_REG_C_7,
970 * Convert register set to DV specification.
972 * @param[in,out] resource
973 * Pointer to the modify-header resource.
975 * Pointer to action specification.
977 * Pointer to the error structure.
980 * 0 on success, a negative errno value otherwise and rte_errno is set.
983 flow_dv_convert_action_set_reg
984 (struct mlx5_flow_dv_modify_hdr_resource *resource,
985 const struct rte_flow_action *action,
986 struct rte_flow_error *error)
988 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
989 struct mlx5_modification_cmd *actions = resource->actions;
990 uint32_t i = resource->actions_num;
992 if (i >= MLX5_MAX_MODIFY_NUM)
993 return rte_flow_error_set(error, EINVAL,
994 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
995 "too many items to modify");
996 MLX5_ASSERT(conf->id != REG_NON);
997 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
998 actions[i] = (struct mlx5_modification_cmd) {
999 .action_type = MLX5_MODIFICATION_TYPE_SET,
1000 .field = reg_to_field[conf->id],
1002 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1003 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1005 resource->actions_num = i;
1010 * Convert SET_TAG action to DV specification.
1013 * Pointer to the rte_eth_dev structure.
1014 * @param[in,out] resource
1015 * Pointer to the modify-header resource.
1017 * Pointer to action specification.
1019 * Pointer to the error structure.
1022 * 0 on success, a negative errno value otherwise and rte_errno is set.
1025 flow_dv_convert_action_set_tag
1026 (struct rte_eth_dev *dev,
1027 struct mlx5_flow_dv_modify_hdr_resource *resource,
1028 const struct rte_flow_action_set_tag *conf,
1029 struct rte_flow_error *error)
1031 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1032 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1033 struct rte_flow_item item = {
1037 struct field_modify_info reg_c_x[] = {
1040 enum mlx5_modification_field reg_type;
1043 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1046 MLX5_ASSERT(ret != REG_NON);
1047 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1048 reg_type = reg_to_field[ret];
1049 MLX5_ASSERT(reg_type > 0);
1050 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1051 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1052 MLX5_MODIFICATION_TYPE_SET, error);
1056 * Convert internal COPY_REG action to DV specification.
1059 * Pointer to the rte_eth_dev structure.
1060 * @param[in,out] res
1061 * Pointer to the modify-header resource.
1063 * Pointer to action specification.
1065 * Pointer to the error structure.
1068 * 0 on success, a negative errno value otherwise and rte_errno is set.
1071 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1072 struct mlx5_flow_dv_modify_hdr_resource *res,
1073 const struct rte_flow_action *action,
1074 struct rte_flow_error *error)
1076 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1077 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1078 struct rte_flow_item item = {
1082 struct field_modify_info reg_src[] = {
1083 {4, 0, reg_to_field[conf->src]},
1086 struct field_modify_info reg_dst = {
1088 .id = reg_to_field[conf->dst],
1090 /* Adjust reg_c[0] usage according to reported mask. */
1091 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1092 struct mlx5_priv *priv = dev->data->dev_private;
1093 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1095 MLX5_ASSERT(reg_c0);
1096 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1097 if (conf->dst == REG_C_0) {
1098 /* Copy to reg_c[0], within mask only. */
1099 reg_dst.offset = rte_bsf32(reg_c0);
1101 * Mask is ignoring the enianness, because
1102 * there is no conversion in datapath.
1104 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1105 /* Copy from destination lower bits to reg_c[0]. */
1106 mask = reg_c0 >> reg_dst.offset;
1108 /* Copy from destination upper bits to reg_c[0]. */
1109 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1110 rte_fls_u32(reg_c0));
1113 mask = rte_cpu_to_be_32(reg_c0);
1114 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1115 /* Copy from reg_c[0] to destination lower bits. */
1118 /* Copy from reg_c[0] to destination upper bits. */
1119 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1120 (rte_fls_u32(reg_c0) -
1125 return flow_dv_convert_modify_action(&item,
1126 reg_src, ®_dst, res,
1127 MLX5_MODIFICATION_TYPE_COPY,
1132 * Convert MARK action to DV specification. This routine is used
1133 * in extensive metadata only and requires metadata register to be
1134 * handled. In legacy mode hardware tag resource is engaged.
1137 * Pointer to the rte_eth_dev structure.
1139 * Pointer to MARK action specification.
1140 * @param[in,out] resource
1141 * Pointer to the modify-header resource.
1143 * Pointer to the error structure.
1146 * 0 on success, a negative errno value otherwise and rte_errno is set.
1149 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1150 const struct rte_flow_action_mark *conf,
1151 struct mlx5_flow_dv_modify_hdr_resource *resource,
1152 struct rte_flow_error *error)
1154 struct mlx5_priv *priv = dev->data->dev_private;
1155 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1156 priv->sh->dv_mark_mask);
1157 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1158 struct rte_flow_item item = {
1162 struct field_modify_info reg_c_x[] = {
1168 return rte_flow_error_set(error, EINVAL,
1169 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1170 NULL, "zero mark action mask");
1171 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1174 MLX5_ASSERT(reg > 0);
1175 if (reg == REG_C_0) {
1176 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1177 uint32_t shl_c0 = rte_bsf32(msk_c0);
1179 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1180 mask = rte_cpu_to_be_32(mask) & msk_c0;
1181 mask = rte_cpu_to_be_32(mask << shl_c0);
1183 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1184 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1185 MLX5_MODIFICATION_TYPE_SET, error);
1189 * Get metadata register index for specified steering domain.
1192 * Pointer to the rte_eth_dev structure.
1194 * Attributes of flow to determine steering domain.
1196 * Pointer to the error structure.
1199 * positive index on success, a negative errno value otherwise
1200 * and rte_errno is set.
1202 static enum modify_reg
1203 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1204 const struct rte_flow_attr *attr,
1205 struct rte_flow_error *error)
1208 mlx5_flow_get_reg_id(dev, attr->transfer ?
1212 MLX5_METADATA_RX, 0, error);
1214 return rte_flow_error_set(error,
1215 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1216 NULL, "unavailable "
1217 "metadata register");
1222 * Convert SET_META action to DV specification.
1225 * Pointer to the rte_eth_dev structure.
1226 * @param[in,out] resource
1227 * Pointer to the modify-header resource.
1229 * Attributes of flow that includes this item.
1231 * Pointer to action specification.
1233 * Pointer to the error structure.
1236 * 0 on success, a negative errno value otherwise and rte_errno is set.
1239 flow_dv_convert_action_set_meta
1240 (struct rte_eth_dev *dev,
1241 struct mlx5_flow_dv_modify_hdr_resource *resource,
1242 const struct rte_flow_attr *attr,
1243 const struct rte_flow_action_set_meta *conf,
1244 struct rte_flow_error *error)
1246 uint32_t data = conf->data;
1247 uint32_t mask = conf->mask;
1248 struct rte_flow_item item = {
1252 struct field_modify_info reg_c_x[] = {
1255 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1260 * In datapath code there is no endianness
1261 * coversions for perfromance reasons, all
1262 * pattern conversions are done in rte_flow.
1264 if (reg == REG_C_0) {
1265 struct mlx5_priv *priv = dev->data->dev_private;
1266 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1269 MLX5_ASSERT(msk_c0);
1270 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1271 shl_c0 = rte_bsf32(msk_c0);
1273 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1277 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1279 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1280 /* The routine expects parameters in memory as big-endian ones. */
1281 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1282 MLX5_MODIFICATION_TYPE_SET, error);
1286 * Convert modify-header set IPv4 DSCP action to DV specification.
1288 * @param[in,out] resource
1289 * Pointer to the modify-header resource.
1291 * Pointer to action specification.
1293 * Pointer to the error structure.
1296 * 0 on success, a negative errno value otherwise and rte_errno is set.
1299 flow_dv_convert_action_modify_ipv4_dscp
1300 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1301 const struct rte_flow_action *action,
1302 struct rte_flow_error *error)
1304 const struct rte_flow_action_set_dscp *conf =
1305 (const struct rte_flow_action_set_dscp *)(action->conf);
1306 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1307 struct rte_flow_item_ipv4 ipv4;
1308 struct rte_flow_item_ipv4 ipv4_mask;
1310 memset(&ipv4, 0, sizeof(ipv4));
1311 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1312 ipv4.hdr.type_of_service = conf->dscp;
1313 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1315 item.mask = &ipv4_mask;
1316 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1317 MLX5_MODIFICATION_TYPE_SET, error);
1321 * Convert modify-header set IPv6 DSCP action to DV specification.
1323 * @param[in,out] resource
1324 * Pointer to the modify-header resource.
1326 * Pointer to action specification.
1328 * Pointer to the error structure.
1331 * 0 on success, a negative errno value otherwise and rte_errno is set.
1334 flow_dv_convert_action_modify_ipv6_dscp
1335 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1336 const struct rte_flow_action *action,
1337 struct rte_flow_error *error)
1339 const struct rte_flow_action_set_dscp *conf =
1340 (const struct rte_flow_action_set_dscp *)(action->conf);
1341 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1342 struct rte_flow_item_ipv6 ipv6;
1343 struct rte_flow_item_ipv6 ipv6_mask;
1345 memset(&ipv6, 0, sizeof(ipv6));
1346 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1348 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1349 * rdma-core only accept the DSCP bits byte aligned start from
1350 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1351 * bits in IPv6 case as rdma-core requires byte aligned value.
1353 ipv6.hdr.vtc_flow = conf->dscp;
1354 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1356 item.mask = &ipv6_mask;
1357 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1358 MLX5_MODIFICATION_TYPE_SET, error);
1362 * Validate MARK item.
1365 * Pointer to the rte_eth_dev structure.
1367 * Item specification.
1369 * Attributes of flow that includes this item.
1371 * Pointer to error structure.
1374 * 0 on success, a negative errno value otherwise and rte_errno is set.
1377 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1378 const struct rte_flow_item *item,
1379 const struct rte_flow_attr *attr __rte_unused,
1380 struct rte_flow_error *error)
1382 struct mlx5_priv *priv = dev->data->dev_private;
1383 struct mlx5_dev_config *config = &priv->config;
1384 const struct rte_flow_item_mark *spec = item->spec;
1385 const struct rte_flow_item_mark *mask = item->mask;
1386 const struct rte_flow_item_mark nic_mask = {
1387 .id = priv->sh->dv_mark_mask,
1391 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata feature"
1396 if (!mlx5_flow_ext_mreg_supported(dev))
1397 return rte_flow_error_set(error, ENOTSUP,
1398 RTE_FLOW_ERROR_TYPE_ITEM, item,
1399 "extended metadata register"
1400 " isn't supported");
1402 return rte_flow_error_set(error, ENOTSUP,
1403 RTE_FLOW_ERROR_TYPE_ITEM, item,
1404 "extended metadata register"
1405 " isn't available");
1406 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1410 return rte_flow_error_set(error, EINVAL,
1411 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1413 "data cannot be empty");
1414 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1418 "mark id exceeds the limit");
1422 return rte_flow_error_set(error, EINVAL,
1423 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1424 "mask cannot be zero");
1426 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1427 (const uint8_t *)&nic_mask,
1428 sizeof(struct rte_flow_item_mark),
1429 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1436 * Validate META item.
1439 * Pointer to the rte_eth_dev structure.
1441 * Item specification.
1443 * Attributes of flow that includes this item.
1445 * Pointer to error structure.
1448 * 0 on success, a negative errno value otherwise and rte_errno is set.
1451 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1452 const struct rte_flow_item *item,
1453 const struct rte_flow_attr *attr,
1454 struct rte_flow_error *error)
1456 struct mlx5_priv *priv = dev->data->dev_private;
1457 struct mlx5_dev_config *config = &priv->config;
1458 const struct rte_flow_item_meta *spec = item->spec;
1459 const struct rte_flow_item_meta *mask = item->mask;
1460 struct rte_flow_item_meta nic_mask = {
1467 return rte_flow_error_set(error, EINVAL,
1468 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1470 "data cannot be empty");
1471 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1472 if (!mlx5_flow_ext_mreg_supported(dev))
1473 return rte_flow_error_set(error, ENOTSUP,
1474 RTE_FLOW_ERROR_TYPE_ITEM, item,
1475 "extended metadata register"
1476 " isn't supported");
1477 reg = flow_dv_get_metadata_reg(dev, attr, error);
1481 return rte_flow_error_set(error, ENOTSUP,
1482 RTE_FLOW_ERROR_TYPE_ITEM, item,
1486 nic_mask.data = priv->sh->dv_meta_mask;
1487 } else if (attr->transfer) {
1488 return rte_flow_error_set(error, ENOTSUP,
1489 RTE_FLOW_ERROR_TYPE_ITEM, item,
1490 "extended metadata feature "
1491 "should be enabled when "
1492 "meta item is requested "
1493 "with e-switch mode ");
1496 mask = &rte_flow_item_meta_mask;
1498 return rte_flow_error_set(error, EINVAL,
1499 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1500 "mask cannot be zero");
1502 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1503 (const uint8_t *)&nic_mask,
1504 sizeof(struct rte_flow_item_meta),
1505 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1510 * Validate TAG item.
1513 * Pointer to the rte_eth_dev structure.
1515 * Item specification.
1517 * Attributes of flow that includes this item.
1519 * Pointer to error structure.
1522 * 0 on success, a negative errno value otherwise and rte_errno is set.
1525 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1526 const struct rte_flow_item *item,
1527 const struct rte_flow_attr *attr __rte_unused,
1528 struct rte_flow_error *error)
1530 const struct rte_flow_item_tag *spec = item->spec;
1531 const struct rte_flow_item_tag *mask = item->mask;
1532 const struct rte_flow_item_tag nic_mask = {
1533 .data = RTE_BE32(UINT32_MAX),
1538 if (!mlx5_flow_ext_mreg_supported(dev))
1539 return rte_flow_error_set(error, ENOTSUP,
1540 RTE_FLOW_ERROR_TYPE_ITEM, item,
1541 "extensive metadata register"
1542 " isn't supported");
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1547 "data cannot be empty");
1549 mask = &rte_flow_item_tag_mask;
1551 return rte_flow_error_set(error, EINVAL,
1552 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1553 "mask cannot be zero");
1555 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1556 (const uint8_t *)&nic_mask,
1557 sizeof(struct rte_flow_item_tag),
1558 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1561 if (mask->index != 0xff)
1562 return rte_flow_error_set(error, EINVAL,
1563 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1564 "partial mask for tag index"
1565 " is not supported");
1566 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1569 MLX5_ASSERT(ret != REG_NON);
1574 * Validate vport item.
1577 * Pointer to the rte_eth_dev structure.
1579 * Item specification.
1581 * Attributes of flow that includes this item.
1582 * @param[in] item_flags
1583 * Bit-fields that holds the items detected until now.
1585 * Pointer to error structure.
1588 * 0 on success, a negative errno value otherwise and rte_errno is set.
1591 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1592 const struct rte_flow_item *item,
1593 const struct rte_flow_attr *attr,
1594 uint64_t item_flags,
1595 struct rte_flow_error *error)
1597 const struct rte_flow_item_port_id *spec = item->spec;
1598 const struct rte_flow_item_port_id *mask = item->mask;
1599 const struct rte_flow_item_port_id switch_mask = {
1602 struct mlx5_priv *esw_priv;
1603 struct mlx5_priv *dev_priv;
1606 if (!attr->transfer)
1607 return rte_flow_error_set(error, EINVAL,
1608 RTE_FLOW_ERROR_TYPE_ITEM,
1610 "match on port id is valid only"
1611 " when transfer flag is enabled");
1612 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1613 return rte_flow_error_set(error, ENOTSUP,
1614 RTE_FLOW_ERROR_TYPE_ITEM, item,
1615 "multiple source ports are not"
1618 mask = &switch_mask;
1619 if (mask->id != 0xffffffff)
1620 return rte_flow_error_set(error, ENOTSUP,
1621 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1623 "no support for partial mask on"
1625 ret = mlx5_flow_item_acceptable
1626 (item, (const uint8_t *)mask,
1627 (const uint8_t *)&rte_flow_item_port_id_mask,
1628 sizeof(struct rte_flow_item_port_id),
1629 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1634 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1636 return rte_flow_error_set(error, rte_errno,
1637 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1638 "failed to obtain E-Switch info for"
1640 dev_priv = mlx5_dev_to_eswitch_info(dev);
1642 return rte_flow_error_set(error, rte_errno,
1643 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1645 "failed to obtain E-Switch info");
1646 if (esw_priv->domain_id != dev_priv->domain_id)
1647 return rte_flow_error_set(error, EINVAL,
1648 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1649 "cannot match on a port from a"
1650 " different E-Switch");
1655 * Validate VLAN item.
1658 * Item specification.
1659 * @param[in] item_flags
1660 * Bit-fields that holds the items detected until now.
1662 * Ethernet device flow is being created on.
1664 * Pointer to error structure.
1667 * 0 on success, a negative errno value otherwise and rte_errno is set.
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671 uint64_t item_flags,
1672 struct rte_eth_dev *dev,
1673 struct rte_flow_error *error)
1675 const struct rte_flow_item_vlan *mask = item->mask;
1676 const struct rte_flow_item_vlan nic_mask = {
1677 .tci = RTE_BE16(UINT16_MAX),
1678 .inner_type = RTE_BE16(UINT16_MAX),
1680 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1682 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683 MLX5_FLOW_LAYER_INNER_L4) :
1684 (MLX5_FLOW_LAYER_OUTER_L3 |
1685 MLX5_FLOW_LAYER_OUTER_L4);
1686 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687 MLX5_FLOW_LAYER_OUTER_VLAN;
1689 if (item_flags & vlanm)
1690 return rte_flow_error_set(error, EINVAL,
1691 RTE_FLOW_ERROR_TYPE_ITEM, item,
1692 "multiple VLAN layers not supported");
1693 else if ((item_flags & l34m) != 0)
1694 return rte_flow_error_set(error, EINVAL,
1695 RTE_FLOW_ERROR_TYPE_ITEM, item,
1696 "VLAN cannot follow L3/L4 layer");
1698 mask = &rte_flow_item_vlan_mask;
1699 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700 (const uint8_t *)&nic_mask,
1701 sizeof(struct rte_flow_item_vlan),
1702 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1705 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706 struct mlx5_priv *priv = dev->data->dev_private;
1708 if (priv->vmwa_context) {
1710 * Non-NULL context means we have a virtual machine
1711 * and SR-IOV enabled, we have to create VLAN interface
1712 * to make hypervisor to setup E-Switch vport
1713 * context correctly. We avoid creating the multiple
1714 * VLAN interfaces, so we cannot support VLAN tag mask.
1716 return rte_flow_error_set(error, EINVAL,
1717 RTE_FLOW_ERROR_TYPE_ITEM,
1719 "VLAN tag mask is not"
1720 " supported in virtual"
1728 * GTP flags are contained in 1 byte of the format:
1729 * -------------------------------------------
1730 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1731 * |-----------------------------------------|
1732 * | value | Version | PT | Res | E | S | PN |
1733 * -------------------------------------------
1735 * Matching is supported only for GTP flags E, S, PN.
1737 #define MLX5_GTP_FLAGS_MASK 0x07
1740 * Validate GTP item.
1743 * Pointer to the rte_eth_dev structure.
1745 * Item specification.
1746 * @param[in] item_flags
1747 * Bit-fields that holds the items detected until now.
1749 * Pointer to error structure.
1752 * 0 on success, a negative errno value otherwise and rte_errno is set.
1755 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1756 const struct rte_flow_item *item,
1757 uint64_t item_flags,
1758 struct rte_flow_error *error)
1760 struct mlx5_priv *priv = dev->data->dev_private;
1761 const struct rte_flow_item_gtp *spec = item->spec;
1762 const struct rte_flow_item_gtp *mask = item->mask;
1763 const struct rte_flow_item_gtp nic_mask = {
1764 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1766 .teid = RTE_BE32(0xffffffff),
1769 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1770 return rte_flow_error_set(error, ENOTSUP,
1771 RTE_FLOW_ERROR_TYPE_ITEM, item,
1772 "GTP support is not enabled");
1773 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1774 return rte_flow_error_set(error, ENOTSUP,
1775 RTE_FLOW_ERROR_TYPE_ITEM, item,
1776 "multiple tunnel layers not"
1778 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1779 return rte_flow_error_set(error, EINVAL,
1780 RTE_FLOW_ERROR_TYPE_ITEM, item,
1781 "no outer UDP layer found");
1783 mask = &rte_flow_item_gtp_mask;
1784 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1785 return rte_flow_error_set(error, ENOTSUP,
1786 RTE_FLOW_ERROR_TYPE_ITEM, item,
1787 "Match is supported for GTP"
1789 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1790 (const uint8_t *)&nic_mask,
1791 sizeof(struct rte_flow_item_gtp),
1792 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1796 * Validate IPV4 item.
1797 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1798 * add specific validation of fragment_offset field,
1801 * Item specification.
1802 * @param[in] item_flags
1803 * Bit-fields that holds the items detected until now.
1805 * Pointer to error structure.
1808 * 0 on success, a negative errno value otherwise and rte_errno is set.
1811 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1812 uint64_t item_flags,
1814 uint16_t ether_type,
1815 struct rte_flow_error *error)
1818 const struct rte_flow_item_ipv4 *spec = item->spec;
1819 const struct rte_flow_item_ipv4 *last = item->last;
1820 const struct rte_flow_item_ipv4 *mask = item->mask;
1821 rte_be16_t fragment_offset_spec = 0;
1822 rte_be16_t fragment_offset_last = 0;
1823 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1825 .src_addr = RTE_BE32(0xffffffff),
1826 .dst_addr = RTE_BE32(0xffffffff),
1827 .type_of_service = 0xff,
1828 .fragment_offset = RTE_BE16(0xffff),
1829 .next_proto_id = 0xff,
1830 .time_to_live = 0xff,
1834 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1835 ether_type, &nic_ipv4_mask,
1836 MLX5_ITEM_RANGE_ACCEPTED, error);
1840 fragment_offset_spec = spec->hdr.fragment_offset &
1841 mask->hdr.fragment_offset;
1842 if (!fragment_offset_spec)
1845 * spec and mask are valid, enforce using full mask to make sure the
1846 * complete value is used correctly.
1848 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1849 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1850 return rte_flow_error_set(error, EINVAL,
1851 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1852 item, "must use full mask for"
1853 " fragment_offset");
1855 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1856 * indicating this is 1st fragment of fragmented packet.
1857 * This is not yet supported in MLX5, return appropriate error message.
1859 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1860 return rte_flow_error_set(error, ENOTSUP,
1861 RTE_FLOW_ERROR_TYPE_ITEM, item,
1862 "match on first fragment not "
1864 if (fragment_offset_spec && !last)
1865 return rte_flow_error_set(error, ENOTSUP,
1866 RTE_FLOW_ERROR_TYPE_ITEM, item,
1867 "specified value not supported");
1868 /* spec and last are valid, validate the specified range. */
1869 fragment_offset_last = last->hdr.fragment_offset &
1870 mask->hdr.fragment_offset;
1872 * Match on fragment_offset spec 0x2001 and last 0x3fff
1873 * means MF is 1 and frag-offset is > 0.
1874 * This packet is fragment 2nd and onward, excluding last.
1875 * This is not yet supported in MLX5, return appropriate
1878 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1879 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1880 return rte_flow_error_set(error, ENOTSUP,
1881 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1882 last, "match on following "
1883 "fragments not supported");
1885 * Match on fragment_offset spec 0x0001 and last 0x1fff
1886 * means MF is 0 and frag-offset is > 0.
1887 * This packet is last fragment of fragmented packet.
1888 * This is not yet supported in MLX5, return appropriate
1891 if (fragment_offset_spec == RTE_BE16(1) &&
1892 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1893 return rte_flow_error_set(error, ENOTSUP,
1894 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1895 last, "match on last "
1896 "fragment not supported");
1898 * Match on fragment_offset spec 0x0001 and last 0x3fff
1899 * means MF and/or frag-offset is not 0.
1900 * This is a fragmented packet.
1901 * Other range values are invalid and rejected.
1903 if (!(fragment_offset_spec == RTE_BE16(1) &&
1904 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1905 return rte_flow_error_set(error, ENOTSUP,
1906 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1907 "specified range not supported");
1912 * Validate IPV6 fragment extension item.
1915 * Item specification.
1916 * @param[in] item_flags
1917 * Bit-fields that holds the items detected until now.
1919 * Pointer to error structure.
1922 * 0 on success, a negative errno value otherwise and rte_errno is set.
1925 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1926 uint64_t item_flags,
1927 struct rte_flow_error *error)
1929 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1930 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1931 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1932 rte_be16_t frag_data_spec = 0;
1933 rte_be16_t frag_data_last = 0;
1934 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1935 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1936 MLX5_FLOW_LAYER_OUTER_L4;
1938 struct rte_flow_item_ipv6_frag_ext nic_mask = {
1940 .next_header = 0xff,
1941 .frag_data = RTE_BE16(0xffff),
1945 if (item_flags & l4m)
1946 return rte_flow_error_set(error, EINVAL,
1947 RTE_FLOW_ERROR_TYPE_ITEM, item,
1948 "ipv6 fragment extension item cannot "
1950 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1951 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1952 return rte_flow_error_set(error, EINVAL,
1953 RTE_FLOW_ERROR_TYPE_ITEM, item,
1954 "ipv6 fragment extension item must "
1955 "follow ipv6 item");
1957 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1958 if (!frag_data_spec)
1961 * spec and mask are valid, enforce using full mask to make sure the
1962 * complete value is used correctly.
1964 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1965 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1966 return rte_flow_error_set(error, EINVAL,
1967 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1968 item, "must use full mask for"
1971 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1972 * This is 1st fragment of fragmented packet.
1974 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1975 return rte_flow_error_set(error, ENOTSUP,
1976 RTE_FLOW_ERROR_TYPE_ITEM, item,
1977 "match on first fragment not "
1979 if (frag_data_spec && !last)
1980 return rte_flow_error_set(error, EINVAL,
1981 RTE_FLOW_ERROR_TYPE_ITEM, item,
1982 "specified value not supported");
1983 ret = mlx5_flow_item_acceptable
1984 (item, (const uint8_t *)mask,
1985 (const uint8_t *)&nic_mask,
1986 sizeof(struct rte_flow_item_ipv6_frag_ext),
1987 MLX5_ITEM_RANGE_ACCEPTED, error);
1990 /* spec and last are valid, validate the specified range. */
1991 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1993 * Match on frag_data spec 0x0009 and last 0xfff9
1994 * means M is 1 and frag-offset is > 0.
1995 * This packet is fragment 2nd and onward, excluding last.
1996 * This is not yet supported in MLX5, return appropriate
1999 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2000 RTE_IPV6_EHDR_MF_MASK) &&
2001 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2002 return rte_flow_error_set(error, ENOTSUP,
2003 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2004 last, "match on following "
2005 "fragments not supported");
2007 * Match on frag_data spec 0x0008 and last 0xfff8
2008 * means M is 0 and frag-offset is > 0.
2009 * This packet is last fragment of fragmented packet.
2010 * This is not yet supported in MLX5, return appropriate
2013 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2014 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2015 return rte_flow_error_set(error, ENOTSUP,
2016 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2017 last, "match on last "
2018 "fragment not supported");
2019 /* Other range values are invalid and rejected. */
2020 return rte_flow_error_set(error, EINVAL,
2021 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2022 "specified range not supported");
2026 * Validate the pop VLAN action.
2029 * Pointer to the rte_eth_dev structure.
2030 * @param[in] action_flags
2031 * Holds the actions detected until now.
2033 * Pointer to the pop vlan action.
2034 * @param[in] item_flags
2035 * The items found in this flow rule.
2037 * Pointer to flow attributes.
2039 * Pointer to error structure.
2042 * 0 on success, a negative errno value otherwise and rte_errno is set.
2045 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2046 uint64_t action_flags,
2047 const struct rte_flow_action *action,
2048 uint64_t item_flags,
2049 const struct rte_flow_attr *attr,
2050 struct rte_flow_error *error)
2052 const struct mlx5_priv *priv = dev->data->dev_private;
2056 if (!priv->sh->pop_vlan_action)
2057 return rte_flow_error_set(error, ENOTSUP,
2058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2060 "pop vlan action is not supported");
2062 return rte_flow_error_set(error, ENOTSUP,
2063 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2065 "pop vlan action not supported for "
2067 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2068 return rte_flow_error_set(error, ENOTSUP,
2069 RTE_FLOW_ERROR_TYPE_ACTION, action,
2070 "no support for multiple VLAN "
2072 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2073 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2074 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2075 return rte_flow_error_set(error, ENOTSUP,
2076 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2078 "cannot pop vlan after decap without "
2079 "match on inner vlan in the flow");
2080 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2081 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2082 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2083 return rte_flow_error_set(error, ENOTSUP,
2084 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2086 "cannot pop vlan without a "
2087 "match on (outer) vlan in the flow");
2088 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2089 return rte_flow_error_set(error, EINVAL,
2090 RTE_FLOW_ERROR_TYPE_ACTION, action,
2091 "wrong action order, port_id should "
2092 "be after pop VLAN action");
2093 if (!attr->transfer && priv->representor)
2094 return rte_flow_error_set(error, ENOTSUP,
2095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2096 "pop vlan action for VF representor "
2097 "not supported on NIC table");
2102 * Get VLAN default info from vlan match info.
2105 * the list of item specifications.
2107 * pointer VLAN info to fill to.
2110 * 0 on success, a negative errno value otherwise and rte_errno is set.
2113 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2114 struct rte_vlan_hdr *vlan)
2116 const struct rte_flow_item_vlan nic_mask = {
2117 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2118 MLX5DV_FLOW_VLAN_VID_MASK),
2119 .inner_type = RTE_BE16(0xffff),
2124 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2125 int type = items->type;
2127 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2128 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2131 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2132 const struct rte_flow_item_vlan *vlan_m = items->mask;
2133 const struct rte_flow_item_vlan *vlan_v = items->spec;
2135 /* If VLAN item in pattern doesn't contain data, return here. */
2140 /* Only full match values are accepted */
2141 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2142 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2143 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2145 rte_be_to_cpu_16(vlan_v->tci &
2146 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2148 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2149 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2150 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2152 rte_be_to_cpu_16(vlan_v->tci &
2153 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2155 if (vlan_m->inner_type == nic_mask.inner_type)
2156 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2157 vlan_m->inner_type);
2162 * Validate the push VLAN action.
2165 * Pointer to the rte_eth_dev structure.
2166 * @param[in] action_flags
2167 * Holds the actions detected until now.
2168 * @param[in] item_flags
2169 * The items found in this flow rule.
2171 * Pointer to the action structure.
2173 * Pointer to flow attributes
2175 * Pointer to error structure.
2178 * 0 on success, a negative errno value otherwise and rte_errno is set.
2181 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2182 uint64_t action_flags,
2183 const struct rte_flow_item_vlan *vlan_m,
2184 const struct rte_flow_action *action,
2185 const struct rte_flow_attr *attr,
2186 struct rte_flow_error *error)
2188 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2189 const struct mlx5_priv *priv = dev->data->dev_private;
2191 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2192 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2193 return rte_flow_error_set(error, EINVAL,
2194 RTE_FLOW_ERROR_TYPE_ACTION, action,
2195 "invalid vlan ethertype");
2196 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2197 return rte_flow_error_set(error, EINVAL,
2198 RTE_FLOW_ERROR_TYPE_ACTION, action,
2199 "wrong action order, port_id should "
2200 "be after push VLAN");
2201 if (!attr->transfer && priv->representor)
2202 return rte_flow_error_set(error, ENOTSUP,
2203 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2204 "push vlan action for VF representor "
2205 "not supported on NIC table");
2207 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2208 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2209 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2210 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2211 !(mlx5_flow_find_action
2212 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2213 return rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ACTION, action,
2215 "not full match mask on VLAN PCP and "
2216 "there is no of_set_vlan_pcp action, "
2217 "push VLAN action cannot figure out "
2220 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2221 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2222 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2223 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2224 !(mlx5_flow_find_action
2225 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2226 return rte_flow_error_set(error, EINVAL,
2227 RTE_FLOW_ERROR_TYPE_ACTION, action,
2228 "not full match mask on VLAN VID and "
2229 "there is no of_set_vlan_vid action, "
2230 "push VLAN action cannot figure out "
2237 * Validate the set VLAN PCP.
2239 * @param[in] action_flags
2240 * Holds the actions detected until now.
2241 * @param[in] actions
2242 * Pointer to the list of actions remaining in the flow rule.
2244 * Pointer to error structure.
2247 * 0 on success, a negative errno value otherwise and rte_errno is set.
2250 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2251 const struct rte_flow_action actions[],
2252 struct rte_flow_error *error)
2254 const struct rte_flow_action *action = actions;
2255 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2257 if (conf->vlan_pcp > 7)
2258 return rte_flow_error_set(error, EINVAL,
2259 RTE_FLOW_ERROR_TYPE_ACTION, action,
2260 "VLAN PCP value is too big");
2261 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2262 return rte_flow_error_set(error, ENOTSUP,
2263 RTE_FLOW_ERROR_TYPE_ACTION, action,
2264 "set VLAN PCP action must follow "
2265 "the push VLAN action");
2266 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2267 return rte_flow_error_set(error, ENOTSUP,
2268 RTE_FLOW_ERROR_TYPE_ACTION, action,
2269 "Multiple VLAN PCP modification are "
2271 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2272 return rte_flow_error_set(error, EINVAL,
2273 RTE_FLOW_ERROR_TYPE_ACTION, action,
2274 "wrong action order, port_id should "
2275 "be after set VLAN PCP");
2280 * Validate the set VLAN VID.
2282 * @param[in] item_flags
2283 * Holds the items detected in this rule.
2284 * @param[in] action_flags
2285 * Holds the actions detected until now.
2286 * @param[in] actions
2287 * Pointer to the list of actions remaining in the flow rule.
2289 * Pointer to error structure.
2292 * 0 on success, a negative errno value otherwise and rte_errno is set.
2295 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2296 uint64_t action_flags,
2297 const struct rte_flow_action actions[],
2298 struct rte_flow_error *error)
2300 const struct rte_flow_action *action = actions;
2301 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2303 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2304 return rte_flow_error_set(error, EINVAL,
2305 RTE_FLOW_ERROR_TYPE_ACTION, action,
2306 "VLAN VID value is too big");
2307 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2308 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2309 return rte_flow_error_set(error, ENOTSUP,
2310 RTE_FLOW_ERROR_TYPE_ACTION, action,
2311 "set VLAN VID action must follow push"
2312 " VLAN action or match on VLAN item");
2313 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2314 return rte_flow_error_set(error, ENOTSUP,
2315 RTE_FLOW_ERROR_TYPE_ACTION, action,
2316 "Multiple VLAN VID modifications are "
2318 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2319 return rte_flow_error_set(error, EINVAL,
2320 RTE_FLOW_ERROR_TYPE_ACTION, action,
2321 "wrong action order, port_id should "
2322 "be after set VLAN VID");
2327 * Validate the FLAG action.
2330 * Pointer to the rte_eth_dev structure.
2331 * @param[in] action_flags
2332 * Holds the actions detected until now.
2334 * Pointer to flow attributes
2336 * Pointer to error structure.
2339 * 0 on success, a negative errno value otherwise and rte_errno is set.
2342 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2343 uint64_t action_flags,
2344 const struct rte_flow_attr *attr,
2345 struct rte_flow_error *error)
2347 struct mlx5_priv *priv = dev->data->dev_private;
2348 struct mlx5_dev_config *config = &priv->config;
2351 /* Fall back if no extended metadata register support. */
2352 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2353 return mlx5_flow_validate_action_flag(action_flags, attr,
2355 /* Extensive metadata mode requires registers. */
2356 if (!mlx5_flow_ext_mreg_supported(dev))
2357 return rte_flow_error_set(error, ENOTSUP,
2358 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2359 "no metadata registers "
2360 "to support flag action");
2361 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2362 return rte_flow_error_set(error, ENOTSUP,
2363 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2364 "extended metadata register"
2365 " isn't available");
2366 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2369 MLX5_ASSERT(ret > 0);
2370 if (action_flags & MLX5_FLOW_ACTION_MARK)
2371 return rte_flow_error_set(error, EINVAL,
2372 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2373 "can't mark and flag in same flow");
2374 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2375 return rte_flow_error_set(error, EINVAL,
2376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2378 " actions in same flow");
2383 * Validate MARK action.
2386 * Pointer to the rte_eth_dev structure.
2388 * Pointer to action.
2389 * @param[in] action_flags
2390 * Holds the actions detected until now.
2392 * Pointer to flow attributes
2394 * Pointer to error structure.
2397 * 0 on success, a negative errno value otherwise and rte_errno is set.
2400 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2401 const struct rte_flow_action *action,
2402 uint64_t action_flags,
2403 const struct rte_flow_attr *attr,
2404 struct rte_flow_error *error)
2406 struct mlx5_priv *priv = dev->data->dev_private;
2407 struct mlx5_dev_config *config = &priv->config;
2408 const struct rte_flow_action_mark *mark = action->conf;
2411 /* Fall back if no extended metadata register support. */
2412 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2413 return mlx5_flow_validate_action_mark(action, action_flags,
2415 /* Extensive metadata mode requires registers. */
2416 if (!mlx5_flow_ext_mreg_supported(dev))
2417 return rte_flow_error_set(error, ENOTSUP,
2418 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2419 "no metadata registers "
2420 "to support mark action");
2421 if (!priv->sh->dv_mark_mask)
2422 return rte_flow_error_set(error, ENOTSUP,
2423 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2424 "extended metadata register"
2425 " isn't available");
2426 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2429 MLX5_ASSERT(ret > 0);
2431 return rte_flow_error_set(error, EINVAL,
2432 RTE_FLOW_ERROR_TYPE_ACTION, action,
2433 "configuration cannot be null");
2434 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2435 return rte_flow_error_set(error, EINVAL,
2436 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2438 "mark id exceeds the limit");
2439 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2440 return rte_flow_error_set(error, EINVAL,
2441 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2442 "can't flag and mark in same flow");
2443 if (action_flags & MLX5_FLOW_ACTION_MARK)
2444 return rte_flow_error_set(error, EINVAL,
2445 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2446 "can't have 2 mark actions in same"
2452 * Validate SET_META action.
2455 * Pointer to the rte_eth_dev structure.
2457 * Pointer to the action structure.
2458 * @param[in] action_flags
2459 * Holds the actions detected until now.
2461 * Pointer to flow attributes
2463 * Pointer to error structure.
2466 * 0 on success, a negative errno value otherwise and rte_errno is set.
2469 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2470 const struct rte_flow_action *action,
2471 uint64_t action_flags __rte_unused,
2472 const struct rte_flow_attr *attr,
2473 struct rte_flow_error *error)
2475 const struct rte_flow_action_set_meta *conf;
2476 uint32_t nic_mask = UINT32_MAX;
2479 if (!mlx5_flow_ext_mreg_supported(dev))
2480 return rte_flow_error_set(error, ENOTSUP,
2481 RTE_FLOW_ERROR_TYPE_ACTION, action,
2482 "extended metadata register"
2483 " isn't supported");
2484 reg = flow_dv_get_metadata_reg(dev, attr, error);
2487 if (reg != REG_A && reg != REG_B) {
2488 struct mlx5_priv *priv = dev->data->dev_private;
2490 nic_mask = priv->sh->dv_meta_mask;
2492 if (!(action->conf))
2493 return rte_flow_error_set(error, EINVAL,
2494 RTE_FLOW_ERROR_TYPE_ACTION, action,
2495 "configuration cannot be null");
2496 conf = (const struct rte_flow_action_set_meta *)action->conf;
2498 return rte_flow_error_set(error, EINVAL,
2499 RTE_FLOW_ERROR_TYPE_ACTION, action,
2500 "zero mask doesn't have any effect");
2501 if (conf->mask & ~nic_mask)
2502 return rte_flow_error_set(error, EINVAL,
2503 RTE_FLOW_ERROR_TYPE_ACTION, action,
2504 "meta data must be within reg C0");
2509 * Validate SET_TAG action.
2512 * Pointer to the rte_eth_dev structure.
2514 * Pointer to the action structure.
2515 * @param[in] action_flags
2516 * Holds the actions detected until now.
2518 * Pointer to flow attributes
2520 * Pointer to error structure.
2523 * 0 on success, a negative errno value otherwise and rte_errno is set.
2526 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2527 const struct rte_flow_action *action,
2528 uint64_t action_flags,
2529 const struct rte_flow_attr *attr,
2530 struct rte_flow_error *error)
2532 const struct rte_flow_action_set_tag *conf;
2533 const uint64_t terminal_action_flags =
2534 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2535 MLX5_FLOW_ACTION_RSS;
2538 if (!mlx5_flow_ext_mreg_supported(dev))
2539 return rte_flow_error_set(error, ENOTSUP,
2540 RTE_FLOW_ERROR_TYPE_ACTION, action,
2541 "extensive metadata register"
2542 " isn't supported");
2543 if (!(action->conf))
2544 return rte_flow_error_set(error, EINVAL,
2545 RTE_FLOW_ERROR_TYPE_ACTION, action,
2546 "configuration cannot be null");
2547 conf = (const struct rte_flow_action_set_tag *)action->conf;
2549 return rte_flow_error_set(error, EINVAL,
2550 RTE_FLOW_ERROR_TYPE_ACTION, action,
2551 "zero mask doesn't have any effect");
2552 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2555 if (!attr->transfer && attr->ingress &&
2556 (action_flags & terminal_action_flags))
2557 return rte_flow_error_set(error, EINVAL,
2558 RTE_FLOW_ERROR_TYPE_ACTION, action,
2559 "set_tag has no effect"
2560 " with terminal actions");
2565 * Validate count action.
2568 * Pointer to rte_eth_dev structure.
2570 * Pointer to error structure.
2573 * 0 on success, a negative errno value otherwise and rte_errno is set.
2576 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2577 struct rte_flow_error *error)
2579 struct mlx5_priv *priv = dev->data->dev_private;
2581 if (!priv->config.devx)
2583 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2587 return rte_flow_error_set
2589 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2591 "count action not supported");
2595 * Validate the L2 encap action.
2598 * Pointer to the rte_eth_dev structure.
2599 * @param[in] action_flags
2600 * Holds the actions detected until now.
2602 * Pointer to the action structure.
2604 * Pointer to flow attributes.
2606 * Pointer to error structure.
2609 * 0 on success, a negative errno value otherwise and rte_errno is set.
2612 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2613 uint64_t action_flags,
2614 const struct rte_flow_action *action,
2615 const struct rte_flow_attr *attr,
2616 struct rte_flow_error *error)
2618 const struct mlx5_priv *priv = dev->data->dev_private;
2620 if (!(action->conf))
2621 return rte_flow_error_set(error, EINVAL,
2622 RTE_FLOW_ERROR_TYPE_ACTION, action,
2623 "configuration cannot be null");
2624 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2625 return rte_flow_error_set(error, EINVAL,
2626 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2627 "can only have a single encap action "
2629 if (!attr->transfer && priv->representor)
2630 return rte_flow_error_set(error, ENOTSUP,
2631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2632 "encap action for VF representor "
2633 "not supported on NIC table");
2638 * Validate a decap action.
2641 * Pointer to the rte_eth_dev structure.
2642 * @param[in] action_flags
2643 * Holds the actions detected until now.
2645 * Pointer to flow attributes
2647 * Pointer to error structure.
2650 * 0 on success, a negative errno value otherwise and rte_errno is set.
2653 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2654 uint64_t action_flags,
2655 const struct rte_flow_attr *attr,
2656 struct rte_flow_error *error)
2658 const struct mlx5_priv *priv = dev->data->dev_private;
2660 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2661 !priv->config.decap_en)
2662 return rte_flow_error_set(error, ENOTSUP,
2663 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2664 "decap is not enabled");
2665 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2666 return rte_flow_error_set(error, ENOTSUP,
2667 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2669 MLX5_FLOW_ACTION_DECAP ? "can only "
2670 "have a single decap action" : "decap "
2671 "after encap is not supported");
2672 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2673 return rte_flow_error_set(error, EINVAL,
2674 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2675 "can't have decap action after"
2678 return rte_flow_error_set(error, ENOTSUP,
2679 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2681 "decap action not supported for "
2683 if (!attr->transfer && priv->representor)
2684 return rte_flow_error_set(error, ENOTSUP,
2685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2686 "decap action for VF representor "
2687 "not supported on NIC table");
2691 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2694 * Validate the raw encap and decap actions.
2697 * Pointer to the rte_eth_dev structure.
2699 * Pointer to the decap action.
2701 * Pointer to the encap action.
2703 * Pointer to flow attributes
2704 * @param[in/out] action_flags
2705 * Holds the actions detected until now.
2706 * @param[out] actions_n
2707 * pointer to the number of actions counter.
2709 * Pointer to error structure.
2712 * 0 on success, a negative errno value otherwise and rte_errno is set.
2715 flow_dv_validate_action_raw_encap_decap
2716 (struct rte_eth_dev *dev,
2717 const struct rte_flow_action_raw_decap *decap,
2718 const struct rte_flow_action_raw_encap *encap,
2719 const struct rte_flow_attr *attr, uint64_t *action_flags,
2720 int *actions_n, struct rte_flow_error *error)
2722 const struct mlx5_priv *priv = dev->data->dev_private;
2725 if (encap && (!encap->size || !encap->data))
2726 return rte_flow_error_set(error, EINVAL,
2727 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2728 "raw encap data cannot be empty");
2729 if (decap && encap) {
2730 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2731 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2734 else if (encap->size <=
2735 MLX5_ENCAPSULATION_DECISION_SIZE &&
2737 MLX5_ENCAPSULATION_DECISION_SIZE)
2740 else if (encap->size >
2741 MLX5_ENCAPSULATION_DECISION_SIZE &&
2743 MLX5_ENCAPSULATION_DECISION_SIZE)
2744 /* 2 L2 actions: encap and decap. */
2747 return rte_flow_error_set(error,
2749 RTE_FLOW_ERROR_TYPE_ACTION,
2750 NULL, "unsupported too small "
2751 "raw decap and too small raw "
2752 "encap combination");
2755 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2759 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2763 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2764 return rte_flow_error_set(error, ENOTSUP,
2765 RTE_FLOW_ERROR_TYPE_ACTION,
2767 "small raw encap size");
2768 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2769 return rte_flow_error_set(error, EINVAL,
2770 RTE_FLOW_ERROR_TYPE_ACTION,
2772 "more than one encap action");
2773 if (!attr->transfer && priv->representor)
2774 return rte_flow_error_set
2776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2777 "encap action for VF representor "
2778 "not supported on NIC table");
2779 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2786 * Match encap_decap resource.
2789 * Pointer to exist resource entry object.
2791 * Pointer to new encap_decap resource.
2794 * 0 on matching, -1 otherwise.
2797 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2799 struct mlx5_flow_dv_encap_decap_resource *resource;
2800 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2802 resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2803 cache_resource = container_of(entry,
2804 struct mlx5_flow_dv_encap_decap_resource,
2806 if (resource->entry.key == cache_resource->entry.key &&
2807 resource->reformat_type == cache_resource->reformat_type &&
2808 resource->ft_type == cache_resource->ft_type &&
2809 resource->flags == cache_resource->flags &&
2810 resource->size == cache_resource->size &&
2811 !memcmp((const void *)resource->buf,
2812 (const void *)cache_resource->buf,
2819 * Find existing encap/decap resource or create and register a new one.
2821 * @param[in, out] dev
2822 * Pointer to rte_eth_dev structure.
2823 * @param[in, out] resource
2824 * Pointer to encap/decap resource.
2825 * @parm[in, out] dev_flow
2826 * Pointer to the dev_flow.
2828 * pointer to error structure.
2831 * 0 on success otherwise -errno and errno is set.
2834 flow_dv_encap_decap_resource_register
2835 (struct rte_eth_dev *dev,
2836 struct mlx5_flow_dv_encap_decap_resource *resource,
2837 struct mlx5_flow *dev_flow,
2838 struct rte_flow_error *error)
2840 struct mlx5_priv *priv = dev->data->dev_private;
2841 struct mlx5_dev_ctx_shared *sh = priv->sh;
2842 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2843 struct mlx5dv_dr_domain *domain;
2844 struct mlx5_hlist_entry *entry;
2845 union mlx5_flow_encap_decap_key encap_decap_key = {
2847 .ft_type = resource->ft_type,
2848 .refmt_type = resource->reformat_type,
2849 .buf_size = resource->size,
2850 .table_level = !!dev_flow->dv.group,
2856 resource->flags = dev_flow->dv.group ? 0 : 1;
2857 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2858 domain = sh->fdb_domain;
2859 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2860 domain = sh->rx_domain;
2862 domain = sh->tx_domain;
2863 encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2865 resource->entry.key = encap_decap_key.v64;
2866 /* Lookup a matching resource from cache. */
2867 entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2868 flow_dv_encap_decap_resource_match,
2871 cache_resource = container_of(entry,
2872 struct mlx5_flow_dv_encap_decap_resource, entry);
2873 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2874 (void *)cache_resource,
2875 rte_atomic32_read(&cache_resource->refcnt));
2876 rte_atomic32_inc(&cache_resource->refcnt);
2877 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2878 dev_flow->dv.encap_decap = cache_resource;
2881 /* Register new encap/decap resource. */
2882 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2883 &dev_flow->handle->dvh.rix_encap_decap);
2884 if (!cache_resource)
2885 return rte_flow_error_set(error, ENOMEM,
2886 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2887 "cannot allocate resource memory");
2888 *cache_resource = *resource;
2889 cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2890 ret = mlx5_flow_os_create_flow_action_packet_reformat
2891 (sh->ctx, domain, cache_resource,
2892 &cache_resource->action);
2894 mlx5_free(cache_resource);
2895 return rte_flow_error_set(error, ENOMEM,
2896 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2897 NULL, "cannot create action");
2899 rte_atomic32_init(&cache_resource->refcnt);
2900 rte_atomic32_inc(&cache_resource->refcnt);
2901 if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2902 flow_dv_encap_decap_resource_match,
2903 (void *)cache_resource)) {
2904 claim_zero(mlx5_flow_os_destroy_flow_action
2905 (cache_resource->action));
2906 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2907 cache_resource->idx);
2908 return rte_flow_error_set(error, EEXIST,
2909 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2910 NULL, "action exist");
2912 dev_flow->dv.encap_decap = cache_resource;
2913 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2914 (void *)cache_resource,
2915 rte_atomic32_read(&cache_resource->refcnt));
2920 * Find existing table jump resource or create and register a new one.
2922 * @param[in, out] dev
2923 * Pointer to rte_eth_dev structure.
2924 * @param[in, out] tbl
2925 * Pointer to flow table resource.
2926 * @parm[in, out] dev_flow
2927 * Pointer to the dev_flow.
2929 * pointer to error structure.
2932 * 0 on success otherwise -errno and errno is set.
2935 flow_dv_jump_tbl_resource_register
2936 (struct rte_eth_dev *dev __rte_unused,
2937 struct mlx5_flow_tbl_resource *tbl,
2938 struct mlx5_flow *dev_flow,
2939 struct rte_flow_error *error)
2941 struct mlx5_flow_tbl_data_entry *tbl_data =
2942 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2946 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2948 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2949 (tbl->obj, &tbl_data->jump.action);
2951 return rte_flow_error_set(error, ENOMEM,
2952 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2953 NULL, "cannot create jump action");
2954 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2955 (void *)&tbl_data->jump, cnt);
2957 /* old jump should not make the table ref++. */
2958 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2959 MLX5_ASSERT(tbl_data->jump.action);
2960 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2961 (void *)&tbl_data->jump, cnt);
2963 rte_atomic32_inc(&tbl_data->jump.refcnt);
2964 dev_flow->handle->rix_jump = tbl_data->idx;
2965 dev_flow->dv.jump = &tbl_data->jump;
2970 * Find existing default miss resource or create and register a new one.
2972 * @param[in, out] dev
2973 * Pointer to rte_eth_dev structure.
2975 * pointer to error structure.
2978 * 0 on success otherwise -errno and errno is set.
2981 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2982 struct rte_flow_error *error)
2984 struct mlx5_priv *priv = dev->data->dev_private;
2985 struct mlx5_dev_ctx_shared *sh = priv->sh;
2986 struct mlx5_flow_default_miss_resource *cache_resource =
2988 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2991 MLX5_ASSERT(cache_resource->action);
2992 cache_resource->action =
2993 mlx5_glue->dr_create_flow_action_default_miss();
2994 if (!cache_resource->action)
2995 return rte_flow_error_set(error, ENOMEM,
2996 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2997 "cannot create default miss action");
2998 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2999 (void *)cache_resource->action, cnt);
3001 rte_atomic32_inc(&cache_resource->refcnt);
3006 * Find existing table port ID resource or create and register a new one.
3008 * @param[in, out] dev
3009 * Pointer to rte_eth_dev structure.
3010 * @param[in, out] resource
3011 * Pointer to port ID action resource.
3012 * @parm[in, out] dev_flow
3013 * Pointer to the dev_flow.
3015 * pointer to error structure.
3018 * 0 on success otherwise -errno and errno is set.
3021 flow_dv_port_id_action_resource_register
3022 (struct rte_eth_dev *dev,
3023 struct mlx5_flow_dv_port_id_action_resource *resource,
3024 struct mlx5_flow *dev_flow,
3025 struct rte_flow_error *error)
3027 struct mlx5_priv *priv = dev->data->dev_private;
3028 struct mlx5_dev_ctx_shared *sh = priv->sh;
3029 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
3033 /* Lookup a matching resource from cache. */
3034 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
3035 idx, cache_resource, next) {
3036 if (resource->port_id == cache_resource->port_id) {
3037 DRV_LOG(DEBUG, "port id action resource resource %p: "
3039 (void *)cache_resource,
3040 rte_atomic32_read(&cache_resource->refcnt));
3041 rte_atomic32_inc(&cache_resource->refcnt);
3042 dev_flow->handle->rix_port_id_action = idx;
3043 dev_flow->dv.port_id_action = cache_resource;
3047 /* Register new port id action resource. */
3048 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
3049 &dev_flow->handle->rix_port_id_action);
3050 if (!cache_resource)
3051 return rte_flow_error_set(error, ENOMEM,
3052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3053 "cannot allocate resource memory");
3054 *cache_resource = *resource;
3055 ret = mlx5_flow_os_create_flow_action_dest_port
3056 (priv->sh->fdb_domain, resource->port_id,
3057 &cache_resource->action);
3059 mlx5_free(cache_resource);
3060 return rte_flow_error_set(error, ENOMEM,
3061 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3062 NULL, "cannot create action");
3064 rte_atomic32_init(&cache_resource->refcnt);
3065 rte_atomic32_inc(&cache_resource->refcnt);
3066 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
3067 dev_flow->handle->rix_port_id_action, cache_resource,
3069 dev_flow->dv.port_id_action = cache_resource;
3070 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
3071 (void *)cache_resource,
3072 rte_atomic32_read(&cache_resource->refcnt));
3077 * Find existing push vlan resource or create and register a new one.
3079 * @param [in, out] dev
3080 * Pointer to rte_eth_dev structure.
3081 * @param[in, out] resource
3082 * Pointer to port ID action resource.
3083 * @parm[in, out] dev_flow
3084 * Pointer to the dev_flow.
3086 * pointer to error structure.
3089 * 0 on success otherwise -errno and errno is set.
3092 flow_dv_push_vlan_action_resource_register
3093 (struct rte_eth_dev *dev,
3094 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3095 struct mlx5_flow *dev_flow,
3096 struct rte_flow_error *error)
3098 struct mlx5_priv *priv = dev->data->dev_private;
3099 struct mlx5_dev_ctx_shared *sh = priv->sh;
3100 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
3101 struct mlx5dv_dr_domain *domain;
3105 /* Lookup a matching resource from cache. */
3106 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3107 sh->push_vlan_action_list, idx, cache_resource, next) {
3108 if (resource->vlan_tag == cache_resource->vlan_tag &&
3109 resource->ft_type == cache_resource->ft_type) {
3110 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
3112 (void *)cache_resource,
3113 rte_atomic32_read(&cache_resource->refcnt));
3114 rte_atomic32_inc(&cache_resource->refcnt);
3115 dev_flow->handle->dvh.rix_push_vlan = idx;
3116 dev_flow->dv.push_vlan_res = cache_resource;
3120 /* Register new push_vlan action resource. */
3121 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3122 &dev_flow->handle->dvh.rix_push_vlan);
3123 if (!cache_resource)
3124 return rte_flow_error_set(error, ENOMEM,
3125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3126 "cannot allocate resource memory");
3127 *cache_resource = *resource;
3128 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3129 domain = sh->fdb_domain;
3130 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3131 domain = sh->rx_domain;
3133 domain = sh->tx_domain;
3134 ret = mlx5_flow_os_create_flow_action_push_vlan
3135 (domain, resource->vlan_tag,
3136 &cache_resource->action);
3138 mlx5_free(cache_resource);
3139 return rte_flow_error_set(error, ENOMEM,
3140 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3141 NULL, "cannot create action");
3143 rte_atomic32_init(&cache_resource->refcnt);
3144 rte_atomic32_inc(&cache_resource->refcnt);
3145 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3146 &sh->push_vlan_action_list,
3147 dev_flow->handle->dvh.rix_push_vlan,
3148 cache_resource, next);
3149 dev_flow->dv.push_vlan_res = cache_resource;
3150 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
3151 (void *)cache_resource,
3152 rte_atomic32_read(&cache_resource->refcnt));
3156 * Get the size of specific rte_flow_item_type hdr size
3158 * @param[in] item_type
3159 * Tested rte_flow_item_type.
3162 * sizeof struct item_type, 0 if void or irrelevant.
3165 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3169 switch (item_type) {
3170 case RTE_FLOW_ITEM_TYPE_ETH:
3171 retval = sizeof(struct rte_ether_hdr);
3173 case RTE_FLOW_ITEM_TYPE_VLAN:
3174 retval = sizeof(struct rte_vlan_hdr);
3176 case RTE_FLOW_ITEM_TYPE_IPV4:
3177 retval = sizeof(struct rte_ipv4_hdr);
3179 case RTE_FLOW_ITEM_TYPE_IPV6:
3180 retval = sizeof(struct rte_ipv6_hdr);
3182 case RTE_FLOW_ITEM_TYPE_UDP:
3183 retval = sizeof(struct rte_udp_hdr);
3185 case RTE_FLOW_ITEM_TYPE_TCP:
3186 retval = sizeof(struct rte_tcp_hdr);
3188 case RTE_FLOW_ITEM_TYPE_VXLAN:
3189 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3190 retval = sizeof(struct rte_vxlan_hdr);
3192 case RTE_FLOW_ITEM_TYPE_GRE:
3193 case RTE_FLOW_ITEM_TYPE_NVGRE:
3194 retval = sizeof(struct rte_gre_hdr);
3196 case RTE_FLOW_ITEM_TYPE_MPLS:
3197 retval = sizeof(struct rte_mpls_hdr);
3199 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3207 #define MLX5_ENCAP_IPV4_VERSION 0x40
3208 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3209 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3210 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3211 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3212 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3213 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3216 * Convert the encap action data from list of rte_flow_item to raw buffer
3219 * Pointer to rte_flow_item objects list.
3221 * Pointer to the output buffer.
3223 * Pointer to the output buffer size.
3225 * Pointer to the error structure.
3228 * 0 on success, a negative errno value otherwise and rte_errno is set.
3231 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3232 size_t *size, struct rte_flow_error *error)
3234 struct rte_ether_hdr *eth = NULL;
3235 struct rte_vlan_hdr *vlan = NULL;
3236 struct rte_ipv4_hdr *ipv4 = NULL;
3237 struct rte_ipv6_hdr *ipv6 = NULL;
3238 struct rte_udp_hdr *udp = NULL;
3239 struct rte_vxlan_hdr *vxlan = NULL;
3240 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3241 struct rte_gre_hdr *gre = NULL;
3243 size_t temp_size = 0;
3246 return rte_flow_error_set(error, EINVAL,
3247 RTE_FLOW_ERROR_TYPE_ACTION,
3248 NULL, "invalid empty data");
3249 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3250 len = flow_dv_get_item_hdr_len(items->type);
3251 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3252 return rte_flow_error_set(error, EINVAL,
3253 RTE_FLOW_ERROR_TYPE_ACTION,
3254 (void *)items->type,
3255 "items total size is too big"
3256 " for encap action");
3257 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3258 switch (items->type) {
3259 case RTE_FLOW_ITEM_TYPE_ETH:
3260 eth = (struct rte_ether_hdr *)&buf[temp_size];
3262 case RTE_FLOW_ITEM_TYPE_VLAN:
3263 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION,
3267 (void *)items->type,
3268 "eth header not found");
3269 if (!eth->ether_type)
3270 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3272 case RTE_FLOW_ITEM_TYPE_IPV4:
3273 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3275 return rte_flow_error_set(error, EINVAL,
3276 RTE_FLOW_ERROR_TYPE_ACTION,
3277 (void *)items->type,
3278 "neither eth nor vlan"
3280 if (vlan && !vlan->eth_proto)
3281 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3282 else if (eth && !eth->ether_type)
3283 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3284 if (!ipv4->version_ihl)
3285 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3286 MLX5_ENCAP_IPV4_IHL_MIN;
3287 if (!ipv4->time_to_live)
3288 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3290 case RTE_FLOW_ITEM_TYPE_IPV6:
3291 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3293 return rte_flow_error_set(error, EINVAL,
3294 RTE_FLOW_ERROR_TYPE_ACTION,
3295 (void *)items->type,
3296 "neither eth nor vlan"
3298 if (vlan && !vlan->eth_proto)
3299 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3300 else if (eth && !eth->ether_type)
3301 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3302 if (!ipv6->vtc_flow)
3304 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3305 if (!ipv6->hop_limits)
3306 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3308 case RTE_FLOW_ITEM_TYPE_UDP:
3309 udp = (struct rte_udp_hdr *)&buf[temp_size];
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION,
3313 (void *)items->type,
3314 "ip header not found");
3315 if (ipv4 && !ipv4->next_proto_id)
3316 ipv4->next_proto_id = IPPROTO_UDP;
3317 else if (ipv6 && !ipv6->proto)
3318 ipv6->proto = IPPROTO_UDP;
3320 case RTE_FLOW_ITEM_TYPE_VXLAN:
3321 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3323 return rte_flow_error_set(error, EINVAL,
3324 RTE_FLOW_ERROR_TYPE_ACTION,
3325 (void *)items->type,
3326 "udp header not found");
3328 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3329 if (!vxlan->vx_flags)
3331 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3333 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3334 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3336 return rte_flow_error_set(error, EINVAL,
3337 RTE_FLOW_ERROR_TYPE_ACTION,
3338 (void *)items->type,
3339 "udp header not found");
3340 if (!vxlan_gpe->proto)
3341 return rte_flow_error_set(error, EINVAL,
3342 RTE_FLOW_ERROR_TYPE_ACTION,
3343 (void *)items->type,
3344 "next protocol not found");
3347 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3348 if (!vxlan_gpe->vx_flags)
3349 vxlan_gpe->vx_flags =
3350 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3352 case RTE_FLOW_ITEM_TYPE_GRE:
3353 case RTE_FLOW_ITEM_TYPE_NVGRE:
3354 gre = (struct rte_gre_hdr *)&buf[temp_size];
3356 return rte_flow_error_set(error, EINVAL,
3357 RTE_FLOW_ERROR_TYPE_ACTION,
3358 (void *)items->type,
3359 "next protocol not found");
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION,
3363 (void *)items->type,
3364 "ip header not found");
3365 if (ipv4 && !ipv4->next_proto_id)
3366 ipv4->next_proto_id = IPPROTO_GRE;
3367 else if (ipv6 && !ipv6->proto)
3368 ipv6->proto = IPPROTO_GRE;
3370 case RTE_FLOW_ITEM_TYPE_VOID:
3373 return rte_flow_error_set(error, EINVAL,
3374 RTE_FLOW_ERROR_TYPE_ACTION,
3375 (void *)items->type,
3376 "unsupported item type");
3386 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3388 struct rte_ether_hdr *eth = NULL;
3389 struct rte_vlan_hdr *vlan = NULL;
3390 struct rte_ipv6_hdr *ipv6 = NULL;
3391 struct rte_udp_hdr *udp = NULL;
3395 eth = (struct rte_ether_hdr *)data;
3396 next_hdr = (char *)(eth + 1);
3397 proto = RTE_BE16(eth->ether_type);
3400 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3401 vlan = (struct rte_vlan_hdr *)next_hdr;
3402 proto = RTE_BE16(vlan->eth_proto);
3403 next_hdr += sizeof(struct rte_vlan_hdr);
3406 /* HW calculates IPv4 csum. no need to proceed */
3407 if (proto == RTE_ETHER_TYPE_IPV4)
3410 /* non IPv4/IPv6 header. not supported */
3411 if (proto != RTE_ETHER_TYPE_IPV6) {
3412 return rte_flow_error_set(error, ENOTSUP,
3413 RTE_FLOW_ERROR_TYPE_ACTION,
3414 NULL, "Cannot offload non IPv4/IPv6");
3417 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3419 /* ignore non UDP */
3420 if (ipv6->proto != IPPROTO_UDP)
3423 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3424 udp->dgram_cksum = 0;
3430 * Convert L2 encap action to DV specification.
3433 * Pointer to rte_eth_dev structure.
3435 * Pointer to action structure.
3436 * @param[in, out] dev_flow
3437 * Pointer to the mlx5_flow.
3438 * @param[in] transfer
3439 * Mark if the flow is E-Switch flow.
3441 * Pointer to the error structure.
3444 * 0 on success, a negative errno value otherwise and rte_errno is set.
3447 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3448 const struct rte_flow_action *action,
3449 struct mlx5_flow *dev_flow,
3451 struct rte_flow_error *error)
3453 const struct rte_flow_item *encap_data;
3454 const struct rte_flow_action_raw_encap *raw_encap_data;
3455 struct mlx5_flow_dv_encap_decap_resource res = {
3457 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3458 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3459 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3462 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3464 (const struct rte_flow_action_raw_encap *)action->conf;
3465 res.size = raw_encap_data->size;
3466 memcpy(res.buf, raw_encap_data->data, res.size);
3468 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3470 ((const struct rte_flow_action_vxlan_encap *)
3471 action->conf)->definition;
3474 ((const struct rte_flow_action_nvgre_encap *)
3475 action->conf)->definition;
3476 if (flow_dv_convert_encap_data(encap_data, res.buf,
3480 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3482 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3483 return rte_flow_error_set(error, EINVAL,
3484 RTE_FLOW_ERROR_TYPE_ACTION,
3485 NULL, "can't create L2 encap action");
3490 * Convert L2 decap action to DV specification.
3493 * Pointer to rte_eth_dev structure.
3494 * @param[in, out] dev_flow
3495 * Pointer to the mlx5_flow.
3496 * @param[in] transfer
3497 * Mark if the flow is E-Switch flow.
3499 * Pointer to the error structure.
3502 * 0 on success, a negative errno value otherwise and rte_errno is set.
3505 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3506 struct mlx5_flow *dev_flow,
3508 struct rte_flow_error *error)
3510 struct mlx5_flow_dv_encap_decap_resource res = {
3513 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3514 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3515 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3518 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3519 return rte_flow_error_set(error, EINVAL,
3520 RTE_FLOW_ERROR_TYPE_ACTION,
3521 NULL, "can't create L2 decap action");
3526 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3529 * Pointer to rte_eth_dev structure.
3531 * Pointer to action structure.
3532 * @param[in, out] dev_flow
3533 * Pointer to the mlx5_flow.
3535 * Pointer to the flow attributes.
3537 * Pointer to the error structure.
3540 * 0 on success, a negative errno value otherwise and rte_errno is set.
3543 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3544 const struct rte_flow_action *action,
3545 struct mlx5_flow *dev_flow,
3546 const struct rte_flow_attr *attr,
3547 struct rte_flow_error *error)
3549 const struct rte_flow_action_raw_encap *encap_data;
3550 struct mlx5_flow_dv_encap_decap_resource res;
3552 memset(&res, 0, sizeof(res));
3553 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3554 res.size = encap_data->size;
3555 memcpy(res.buf, encap_data->data, res.size);
3556 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3557 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3558 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3560 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3562 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3563 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3564 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3565 return rte_flow_error_set(error, EINVAL,
3566 RTE_FLOW_ERROR_TYPE_ACTION,
3567 NULL, "can't create encap action");
3572 * Create action push VLAN.
3575 * Pointer to rte_eth_dev structure.
3577 * Pointer to the flow attributes.
3579 * Pointer to the vlan to push to the Ethernet header.
3580 * @param[in, out] dev_flow
3581 * Pointer to the mlx5_flow.
3583 * Pointer to the error structure.
3586 * 0 on success, a negative errno value otherwise and rte_errno is set.
3589 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3590 const struct rte_flow_attr *attr,
3591 const struct rte_vlan_hdr *vlan,
3592 struct mlx5_flow *dev_flow,
3593 struct rte_flow_error *error)
3595 struct mlx5_flow_dv_push_vlan_action_resource res;
3597 memset(&res, 0, sizeof(res));
3599 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3602 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3604 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3605 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3606 return flow_dv_push_vlan_action_resource_register
3607 (dev, &res, dev_flow, error);
3610 static int fdb_mirror;
3613 * Validate the modify-header actions.
3615 * @param[in] action_flags
3616 * Holds the actions detected until now.
3618 * Pointer to the modify action.
3620 * Pointer to error structure.
3623 * 0 on success, a negative errno value otherwise and rte_errno is set.
3626 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3627 const struct rte_flow_action *action,
3628 struct rte_flow_error *error)
3630 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3631 return rte_flow_error_set(error, EINVAL,
3632 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3633 NULL, "action configuration not set");
3634 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3635 return rte_flow_error_set(error, EINVAL,
3636 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3637 "can't have encap action before"
3639 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3640 return rte_flow_error_set(error, EINVAL,
3641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3642 "can't support sample action before"
3643 " modify action for E-Switch"
3649 * Validate the modify-header MAC address actions.
3651 * @param[in] action_flags
3652 * Holds the actions detected until now.
3654 * Pointer to the modify action.
3655 * @param[in] item_flags
3656 * Holds the items detected.
3658 * Pointer to error structure.
3661 * 0 on success, a negative errno value otherwise and rte_errno is set.
3664 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3665 const struct rte_flow_action *action,
3666 const uint64_t item_flags,
3667 struct rte_flow_error *error)
3671 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3673 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3674 return rte_flow_error_set(error, EINVAL,
3675 RTE_FLOW_ERROR_TYPE_ACTION,
3677 "no L2 item in pattern");
3683 * Validate the modify-header IPv4 address actions.
3685 * @param[in] action_flags
3686 * Holds the actions detected until now.
3688 * Pointer to the modify action.
3689 * @param[in] item_flags
3690 * Holds the items detected.
3692 * Pointer to error structure.
3695 * 0 on success, a negative errno value otherwise and rte_errno is set.
3698 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3699 const struct rte_flow_action *action,
3700 const uint64_t item_flags,
3701 struct rte_flow_error *error)
3706 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3708 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3709 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3710 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3711 if (!(item_flags & layer))
3712 return rte_flow_error_set(error, EINVAL,
3713 RTE_FLOW_ERROR_TYPE_ACTION,
3715 "no ipv4 item in pattern");
3721 * Validate the modify-header IPv6 address actions.
3723 * @param[in] action_flags
3724 * Holds the actions detected until now.
3726 * Pointer to the modify action.
3727 * @param[in] item_flags
3728 * Holds the items detected.
3730 * Pointer to error structure.
3733 * 0 on success, a negative errno value otherwise and rte_errno is set.
3736 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3737 const struct rte_flow_action *action,
3738 const uint64_t item_flags,
3739 struct rte_flow_error *error)
3744 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3746 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3747 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3748 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3749 if (!(item_flags & layer))
3750 return rte_flow_error_set(error, EINVAL,
3751 RTE_FLOW_ERROR_TYPE_ACTION,
3753 "no ipv6 item in pattern");
3759 * Validate the modify-header TP actions.
3761 * @param[in] action_flags
3762 * Holds the actions detected until now.
3764 * Pointer to the modify action.
3765 * @param[in] item_flags
3766 * Holds the items detected.
3768 * Pointer to error structure.
3771 * 0 on success, a negative errno value otherwise and rte_errno is set.
3774 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3775 const struct rte_flow_action *action,
3776 const uint64_t item_flags,
3777 struct rte_flow_error *error)
3782 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3784 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3785 MLX5_FLOW_LAYER_INNER_L4 :
3786 MLX5_FLOW_LAYER_OUTER_L4;
3787 if (!(item_flags & layer))
3788 return rte_flow_error_set(error, EINVAL,
3789 RTE_FLOW_ERROR_TYPE_ACTION,
3790 NULL, "no transport layer "
3797 * Validate the modify-header actions of increment/decrement
3798 * TCP Sequence-number.
3800 * @param[in] action_flags
3801 * Holds the actions detected until now.
3803 * Pointer to the modify action.
3804 * @param[in] item_flags
3805 * Holds the items detected.
3807 * Pointer to error structure.
3810 * 0 on success, a negative errno value otherwise and rte_errno is set.
3813 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3814 const struct rte_flow_action *action,
3815 const uint64_t item_flags,
3816 struct rte_flow_error *error)
3821 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3823 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3824 MLX5_FLOW_LAYER_INNER_L4_TCP :
3825 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3826 if (!(item_flags & layer))
3827 return rte_flow_error_set(error, EINVAL,
3828 RTE_FLOW_ERROR_TYPE_ACTION,
3829 NULL, "no TCP item in"
3831 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3832 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3833 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3834 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3835 return rte_flow_error_set(error, EINVAL,
3836 RTE_FLOW_ERROR_TYPE_ACTION,
3838 "cannot decrease and increase"
3839 " TCP sequence number"
3840 " at the same time");
3846 * Validate the modify-header actions of increment/decrement
3847 * TCP Acknowledgment number.
3849 * @param[in] action_flags
3850 * Holds the actions detected until now.
3852 * Pointer to the modify action.
3853 * @param[in] item_flags
3854 * Holds the items detected.
3856 * Pointer to error structure.
3859 * 0 on success, a negative errno value otherwise and rte_errno is set.
3862 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3863 const struct rte_flow_action *action,
3864 const uint64_t item_flags,
3865 struct rte_flow_error *error)
3870 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3872 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3873 MLX5_FLOW_LAYER_INNER_L4_TCP :
3874 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3875 if (!(item_flags & layer))
3876 return rte_flow_error_set(error, EINVAL,
3877 RTE_FLOW_ERROR_TYPE_ACTION,
3878 NULL, "no TCP item in"
3880 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3881 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3882 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3883 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3884 return rte_flow_error_set(error, EINVAL,
3885 RTE_FLOW_ERROR_TYPE_ACTION,
3887 "cannot decrease and increase"
3888 " TCP acknowledgment number"
3889 " at the same time");
3895 * Validate the modify-header TTL actions.
3897 * @param[in] action_flags
3898 * Holds the actions detected until now.
3900 * Pointer to the modify action.
3901 * @param[in] item_flags
3902 * Holds the items detected.
3904 * Pointer to error structure.
3907 * 0 on success, a negative errno value otherwise and rte_errno is set.
3910 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3911 const struct rte_flow_action *action,
3912 const uint64_t item_flags,
3913 struct rte_flow_error *error)
3918 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3920 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3921 MLX5_FLOW_LAYER_INNER_L3 :
3922 MLX5_FLOW_LAYER_OUTER_L3;
3923 if (!(item_flags & layer))
3924 return rte_flow_error_set(error, EINVAL,
3925 RTE_FLOW_ERROR_TYPE_ACTION,
3927 "no IP protocol in pattern");
3933 * Validate jump action.
3936 * Pointer to the jump action.
3937 * @param[in] action_flags
3938 * Holds the actions detected until now.
3939 * @param[in] attributes
3940 * Pointer to flow attributes
3941 * @param[in] external
3942 * Action belongs to flow rule created by request external to PMD.
3944 * Pointer to error structure.
3947 * 0 on success, a negative errno value otherwise and rte_errno is set.
3950 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3951 const struct mlx5_flow_tunnel *tunnel,
3952 const struct rte_flow_action *action,
3953 uint64_t action_flags,
3954 const struct rte_flow_attr *attributes,
3955 bool external, struct rte_flow_error *error)
3957 uint32_t target_group, table;
3959 struct flow_grp_info grp_info = {
3960 .external = !!external,
3961 .transfer = !!attributes->transfer,
3965 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3966 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3967 return rte_flow_error_set(error, EINVAL,
3968 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3969 "can't have 2 fate actions in"
3971 if (action_flags & MLX5_FLOW_ACTION_METER)
3972 return rte_flow_error_set(error, ENOTSUP,
3973 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3974 "jump with meter not support");
3975 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3976 return rte_flow_error_set(error, EINVAL,
3977 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3978 "E-Switch mirroring can't support"
3979 " Sample action and jump action in"
3982 return rte_flow_error_set(error, EINVAL,
3983 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3984 NULL, "action configuration not set");
3986 ((const struct rte_flow_action_jump *)action->conf)->group;
3987 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3991 if (attributes->group == target_group &&
3992 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3993 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3994 return rte_flow_error_set(error, EINVAL,
3995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996 "target group must be other than"
3997 " the current flow group");
4002 * Validate the port_id action.
4005 * Pointer to rte_eth_dev structure.
4006 * @param[in] action_flags
4007 * Bit-fields that holds the actions detected until now.
4009 * Port_id RTE action structure.
4011 * Attributes of flow that includes this action.
4013 * Pointer to error structure.
4016 * 0 on success, a negative errno value otherwise and rte_errno is set.
4019 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4020 uint64_t action_flags,
4021 const struct rte_flow_action *action,
4022 const struct rte_flow_attr *attr,
4023 struct rte_flow_error *error)
4025 const struct rte_flow_action_port_id *port_id;
4026 struct mlx5_priv *act_priv;
4027 struct mlx5_priv *dev_priv;
4030 if (!attr->transfer)
4031 return rte_flow_error_set(error, ENOTSUP,
4032 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4034 "port id action is valid in transfer"
4036 if (!action || !action->conf)
4037 return rte_flow_error_set(error, ENOTSUP,
4038 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4040 "port id action parameters must be"
4042 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4043 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4044 return rte_flow_error_set(error, EINVAL,
4045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4046 "can have only one fate actions in"
4048 dev_priv = mlx5_dev_to_eswitch_info(dev);
4050 return rte_flow_error_set(error, rte_errno,
4051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4053 "failed to obtain E-Switch info");
4054 port_id = action->conf;
4055 port = port_id->original ? dev->data->port_id : port_id->id;
4056 act_priv = mlx5_port_to_eswitch_info(port, false);
4058 return rte_flow_error_set
4060 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4061 "failed to obtain E-Switch port id for port");
4062 if (act_priv->domain_id != dev_priv->domain_id)
4063 return rte_flow_error_set
4065 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4066 "port does not belong to"
4067 " E-Switch being configured");
4072 * Get the maximum number of modify header actions.
4075 * Pointer to rte_eth_dev structure.
4077 * Flags bits to check if root level.
4080 * Max number of modify header actions device can support.
4082 static inline unsigned int
4083 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4087 * There's no way to directly query the max capacity from FW.
4088 * The maximal value on root table should be assumed to be supported.
4090 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4091 return MLX5_MAX_MODIFY_NUM;
4093 return MLX5_ROOT_TBL_MODIFY_NUM;
4097 * Validate the meter action.
4100 * Pointer to rte_eth_dev structure.
4101 * @param[in] action_flags
4102 * Bit-fields that holds the actions detected until now.
4104 * Pointer to the meter action.
4106 * Attributes of flow that includes this action.
4108 * Pointer to error structure.
4111 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4114 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4115 uint64_t action_flags,
4116 const struct rte_flow_action *action,
4117 const struct rte_flow_attr *attr,
4118 struct rte_flow_error *error)
4120 struct mlx5_priv *priv = dev->data->dev_private;
4121 const struct rte_flow_action_meter *am = action->conf;
4122 struct mlx5_flow_meter *fm;
4125 return rte_flow_error_set(error, EINVAL,
4126 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4127 "meter action conf is NULL");
4129 if (action_flags & MLX5_FLOW_ACTION_METER)
4130 return rte_flow_error_set(error, ENOTSUP,
4131 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4132 "meter chaining not support");
4133 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4134 return rte_flow_error_set(error, ENOTSUP,
4135 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4136 "meter with jump not support");
4138 return rte_flow_error_set(error, ENOTSUP,
4139 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4141 "meter action not supported");
4142 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4144 return rte_flow_error_set(error, EINVAL,
4145 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4147 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4148 (!fm->ingress && !attr->ingress && attr->egress) ||
4149 (!fm->egress && !attr->egress && attr->ingress))))
4150 return rte_flow_error_set(error, EINVAL,
4151 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4152 "Flow attributes are either invalid "
4153 "or have a conflict with current "
4154 "meter attributes");
4159 * Validate the age action.
4161 * @param[in] action_flags
4162 * Holds the actions detected until now.
4164 * Pointer to the age action.
4166 * Pointer to the Ethernet device structure.
4168 * Pointer to error structure.
4171 * 0 on success, a negative errno value otherwise and rte_errno is set.
4174 flow_dv_validate_action_age(uint64_t action_flags,
4175 const struct rte_flow_action *action,
4176 struct rte_eth_dev *dev,
4177 struct rte_flow_error *error)
4179 struct mlx5_priv *priv = dev->data->dev_private;
4180 const struct rte_flow_action_age *age = action->conf;
4182 if (!priv->config.devx || priv->sh->cmng.counter_fallback)
4183 return rte_flow_error_set(error, ENOTSUP,
4184 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4186 "age action not supported");
4187 if (!(action->conf))
4188 return rte_flow_error_set(error, EINVAL,
4189 RTE_FLOW_ERROR_TYPE_ACTION, action,
4190 "configuration cannot be null");
4191 if (!(age->timeout))
4192 return rte_flow_error_set(error, EINVAL,
4193 RTE_FLOW_ERROR_TYPE_ACTION, action,
4194 "invalid timeout value 0");
4195 if (action_flags & MLX5_FLOW_ACTION_AGE)
4196 return rte_flow_error_set(error, EINVAL,
4197 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4198 "duplicate age actions set");
4203 * Validate the modify-header IPv4 DSCP actions.
4205 * @param[in] action_flags
4206 * Holds the actions detected until now.
4208 * Pointer to the modify action.
4209 * @param[in] item_flags
4210 * Holds the items detected.
4212 * Pointer to error structure.
4215 * 0 on success, a negative errno value otherwise and rte_errno is set.
4218 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4219 const struct rte_flow_action *action,
4220 const uint64_t item_flags,
4221 struct rte_flow_error *error)
4225 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4227 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4228 return rte_flow_error_set(error, EINVAL,
4229 RTE_FLOW_ERROR_TYPE_ACTION,
4231 "no ipv4 item in pattern");
4237 * Validate the modify-header IPv6 DSCP actions.
4239 * @param[in] action_flags
4240 * Holds the actions detected until now.
4242 * Pointer to the modify action.
4243 * @param[in] item_flags
4244 * Holds the items detected.
4246 * Pointer to error structure.
4249 * 0 on success, a negative errno value otherwise and rte_errno is set.
4252 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4253 const struct rte_flow_action *action,
4254 const uint64_t item_flags,
4255 struct rte_flow_error *error)
4259 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4261 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4262 return rte_flow_error_set(error, EINVAL,
4263 RTE_FLOW_ERROR_TYPE_ACTION,
4265 "no ipv6 item in pattern");
4271 * Match modify-header resource.
4274 * Pointer to exist resource entry object.
4276 * Pointer to new modify-header resource.
4279 * 0 on matching, -1 otherwise.
4282 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4284 struct mlx5_flow_dv_modify_hdr_resource *resource;
4285 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4286 uint32_t actions_len;
4288 resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4289 cache_resource = container_of(entry,
4290 struct mlx5_flow_dv_modify_hdr_resource,
4292 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4293 if (resource->entry.key == cache_resource->entry.key &&
4294 resource->ft_type == cache_resource->ft_type &&
4295 resource->actions_num == cache_resource->actions_num &&
4296 resource->flags == cache_resource->flags &&
4297 !memcmp((const void *)resource->actions,
4298 (const void *)cache_resource->actions,
4305 * Validate the sample action.
4307 * @param[in] action_flags
4308 * Holds the actions detected until now.
4310 * Pointer to the sample action.
4312 * Pointer to the Ethernet device structure.
4314 * Attributes of flow that includes this action.
4316 * Pointer to error structure.
4319 * 0 on success, a negative errno value otherwise and rte_errno is set.
4322 flow_dv_validate_action_sample(uint64_t action_flags,
4323 const struct rte_flow_action *action,
4324 struct rte_eth_dev *dev,
4325 const struct rte_flow_attr *attr,
4326 struct rte_flow_error *error)
4328 struct mlx5_priv *priv = dev->data->dev_private;
4329 struct mlx5_dev_config *dev_conf = &priv->config;
4330 const struct rte_flow_action_sample *sample = action->conf;
4331 const struct rte_flow_action *act;
4332 uint64_t sub_action_flags = 0;
4333 uint16_t queue_index = 0xFFFF;
4339 return rte_flow_error_set(error, EINVAL,
4340 RTE_FLOW_ERROR_TYPE_ACTION, action,
4341 "configuration cannot be NULL");
4342 if (sample->ratio == 0)
4343 return rte_flow_error_set(error, EINVAL,
4344 RTE_FLOW_ERROR_TYPE_ACTION, action,
4345 "ratio value starts from 1");
4346 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4347 return rte_flow_error_set(error, ENOTSUP,
4348 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4350 "sample action not supported");
4351 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4352 return rte_flow_error_set(error, EINVAL,
4353 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4354 "Multiple sample actions not "
4356 if (action_flags & MLX5_FLOW_ACTION_METER)
4357 return rte_flow_error_set(error, EINVAL,
4358 RTE_FLOW_ERROR_TYPE_ACTION, action,
4359 "wrong action order, meter should "
4360 "be after sample action");
4361 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4362 return rte_flow_error_set(error, EINVAL,
4363 RTE_FLOW_ERROR_TYPE_ACTION, action,
4364 "wrong action order, jump should "
4365 "be after sample action");
4366 act = sample->actions;
4367 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4368 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4369 return rte_flow_error_set(error, ENOTSUP,
4370 RTE_FLOW_ERROR_TYPE_ACTION,
4371 act, "too many actions");
4372 switch (act->type) {
4373 case RTE_FLOW_ACTION_TYPE_QUEUE:
4374 ret = mlx5_flow_validate_action_queue(act,
4380 queue_index = ((const struct rte_flow_action_queue *)
4381 (act->conf))->index;
4382 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4385 case RTE_FLOW_ACTION_TYPE_MARK:
4386 ret = flow_dv_validate_action_mark(dev, act,
4391 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4392 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4393 MLX5_FLOW_ACTION_MARK_EXT;
4395 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4398 case RTE_FLOW_ACTION_TYPE_COUNT:
4399 ret = flow_dv_validate_action_count(dev, error);
4402 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4405 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4406 ret = flow_dv_validate_action_port_id(dev,
4413 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4416 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4417 ret = flow_dv_validate_action_raw_encap_decap
4418 (dev, NULL, act->conf, attr, &sub_action_flags,
4425 return rte_flow_error_set(error, ENOTSUP,
4426 RTE_FLOW_ERROR_TYPE_ACTION,
4428 "Doesn't support optional "
4432 if (attr->ingress && !attr->transfer) {
4433 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4434 return rte_flow_error_set(error, EINVAL,
4435 RTE_FLOW_ERROR_TYPE_ACTION,
4437 "Ingress must has a dest "
4438 "QUEUE for Sample");
4439 } else if (attr->egress && !attr->transfer) {
4440 return rte_flow_error_set(error, ENOTSUP,
4441 RTE_FLOW_ERROR_TYPE_ACTION,
4443 "Sample Only support Ingress "
4445 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4446 MLX5_ASSERT(attr->transfer);
4447 if (sample->ratio > 1)
4448 return rte_flow_error_set(error, ENOTSUP,
4449 RTE_FLOW_ERROR_TYPE_ACTION,
4451 "E-Switch doesn't support "
4452 "any optional action "
4455 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4456 return rte_flow_error_set(error, ENOTSUP,
4457 RTE_FLOW_ERROR_TYPE_ACTION,
4459 "unsupported action QUEUE");
4460 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4461 return rte_flow_error_set(error, EINVAL,
4462 RTE_FLOW_ERROR_TYPE_ACTION,
4464 "E-Switch must has a dest "
4465 "port for mirroring");
4467 /* Continue validation for Xcap actions.*/
4468 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4469 (queue_index == 0xFFFF ||
4470 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4471 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4472 MLX5_FLOW_XCAP_ACTIONS)
4473 return rte_flow_error_set(error, ENOTSUP,
4474 RTE_FLOW_ERROR_TYPE_ACTION,
4475 NULL, "encap and decap "
4476 "combination aren't "
4478 if (!attr->transfer && attr->ingress && (sub_action_flags &
4479 MLX5_FLOW_ACTION_ENCAP))
4480 return rte_flow_error_set(error, ENOTSUP,
4481 RTE_FLOW_ERROR_TYPE_ACTION,
4482 NULL, "encap is not supported"
4483 " for ingress traffic");
4489 * Find existing modify-header resource or create and register a new one.
4491 * @param dev[in, out]
4492 * Pointer to rte_eth_dev structure.
4493 * @param[in, out] resource
4494 * Pointer to modify-header resource.
4495 * @parm[in, out] dev_flow
4496 * Pointer to the dev_flow.
4498 * pointer to error structure.
4501 * 0 on success otherwise -errno and errno is set.
4504 flow_dv_modify_hdr_resource_register
4505 (struct rte_eth_dev *dev,
4506 struct mlx5_flow_dv_modify_hdr_resource *resource,
4507 struct mlx5_flow *dev_flow,
4508 struct rte_flow_error *error)
4510 struct mlx5_priv *priv = dev->data->dev_private;
4511 struct mlx5_dev_ctx_shared *sh = priv->sh;
4512 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4513 struct mlx5dv_dr_domain *ns;
4514 uint32_t actions_len;
4515 struct mlx5_hlist_entry *entry;
4516 union mlx5_flow_modify_hdr_key hdr_mod_key = {
4518 .ft_type = resource->ft_type,
4519 .actions_num = resource->actions_num,
4520 .group = dev_flow->dv.group,
4526 resource->flags = dev_flow->dv.group ? 0 :
4527 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4528 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4530 return rte_flow_error_set(error, EOVERFLOW,
4531 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4532 "too many modify header items");
4533 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4534 ns = sh->fdb_domain;
4535 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4539 /* Lookup a matching resource from cache. */
4540 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4541 hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4542 resource->entry.key = hdr_mod_key.v64;
4543 entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4544 flow_dv_modify_hdr_resource_match,
4547 cache_resource = container_of(entry,
4548 struct mlx5_flow_dv_modify_hdr_resource,
4550 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4551 (void *)cache_resource,
4552 rte_atomic32_read(&cache_resource->refcnt));
4553 rte_atomic32_inc(&cache_resource->refcnt);
4554 dev_flow->handle->dvh.modify_hdr = cache_resource;
4558 /* Register new modify-header resource. */
4559 cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4560 sizeof(*cache_resource) + actions_len, 0,
4562 if (!cache_resource)
4563 return rte_flow_error_set(error, ENOMEM,
4564 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4565 "cannot allocate resource memory");
4566 *cache_resource = *resource;
4567 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4568 ret = mlx5_flow_os_create_flow_action_modify_header
4569 (sh->ctx, ns, cache_resource,
4570 actions_len, &cache_resource->action);
4572 mlx5_free(cache_resource);
4573 return rte_flow_error_set(error, ENOMEM,
4574 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4575 NULL, "cannot create action");
4577 rte_atomic32_init(&cache_resource->refcnt);
4578 rte_atomic32_inc(&cache_resource->refcnt);
4579 if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4580 flow_dv_modify_hdr_resource_match,
4581 (void *)cache_resource)) {
4582 claim_zero(mlx5_flow_os_destroy_flow_action
4583 (cache_resource->action));
4584 mlx5_free(cache_resource);
4585 return rte_flow_error_set(error, EEXIST,
4586 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4587 NULL, "action exist");
4589 dev_flow->handle->dvh.modify_hdr = cache_resource;
4590 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4591 (void *)cache_resource,
4592 rte_atomic32_read(&cache_resource->refcnt));
4597 * Get DV flow counter by index.
4600 * Pointer to the Ethernet device structure.
4602 * mlx5 flow counter index in the container.
4604 * mlx5 flow counter pool in the container,
4607 * Pointer to the counter, NULL otherwise.
4609 static struct mlx5_flow_counter *
4610 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4612 struct mlx5_flow_counter_pool **ppool)
4614 struct mlx5_priv *priv = dev->data->dev_private;
4615 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4616 struct mlx5_flow_counter_pool *pool;
4618 /* Decrease to original index and clear shared bit. */
4619 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4620 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4621 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4625 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4629 * Check the devx counter belongs to the pool.
4632 * Pointer to the counter pool.
4634 * The counter devx ID.
4637 * True if counter belongs to the pool, false otherwise.
4640 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4642 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4643 MLX5_COUNTERS_PER_POOL;
4645 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4651 * Get a pool by devx counter ID.
4654 * Pointer to the counter management.
4656 * The counter devx ID.
4659 * The counter pool pointer if exists, NULL otherwise,
4661 static struct mlx5_flow_counter_pool *
4662 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4665 struct mlx5_flow_counter_pool *pool = NULL;
4667 rte_spinlock_lock(&cmng->pool_update_sl);
4668 /* Check last used pool. */
4669 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4670 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4671 pool = cmng->pools[cmng->last_pool_idx];
4674 /* ID out of range means no suitable pool in the container. */
4675 if (id > cmng->max_id || id < cmng->min_id)
4678 * Find the pool from the end of the container, since mostly counter
4679 * ID is sequence increasing, and the last pool should be the needed
4684 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4686 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4692 rte_spinlock_unlock(&cmng->pool_update_sl);
4697 * Resize a counter container.
4700 * Pointer to the Ethernet device structure.
4703 * 0 on success, otherwise negative errno value and rte_errno is set.
4706 flow_dv_container_resize(struct rte_eth_dev *dev)
4708 struct mlx5_priv *priv = dev->data->dev_private;
4709 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4710 void *old_pools = cmng->pools;
4711 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4712 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4713 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4720 memcpy(pools, old_pools, cmng->n *
4721 sizeof(struct mlx5_flow_counter_pool *));
4723 cmng->pools = pools;
4725 mlx5_free(old_pools);
4730 * Query a devx flow counter.
4733 * Pointer to the Ethernet device structure.
4735 * Index to the flow counter.
4737 * The statistics value of packets.
4739 * The statistics value of bytes.
4742 * 0 on success, otherwise a negative errno value and rte_errno is set.
4745 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4748 struct mlx5_priv *priv = dev->data->dev_private;
4749 struct mlx5_flow_counter_pool *pool = NULL;
4750 struct mlx5_flow_counter *cnt;
4753 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4755 if (priv->sh->cmng.counter_fallback)
4756 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4757 0, pkts, bytes, 0, NULL, NULL, 0);
4758 rte_spinlock_lock(&pool->sl);
4763 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4764 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4765 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4767 rte_spinlock_unlock(&pool->sl);
4772 * Create and initialize a new counter pool.
4775 * Pointer to the Ethernet device structure.
4777 * The devX counter handle.
4779 * Whether the pool is for counter that was allocated for aging.
4780 * @param[in/out] cont_cur
4781 * Pointer to the container pointer, it will be update in pool resize.
4784 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4786 static struct mlx5_flow_counter_pool *
4787 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4790 struct mlx5_priv *priv = dev->data->dev_private;
4791 struct mlx5_flow_counter_pool *pool;
4792 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4793 bool fallback = priv->sh->cmng.counter_fallback;
4794 uint32_t size = sizeof(*pool);
4796 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4797 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4798 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4804 pool->is_aged = !!age;
4805 pool->query_gen = 0;
4806 pool->min_dcs = dcs;
4807 rte_spinlock_init(&pool->sl);
4808 rte_spinlock_init(&pool->csl);
4809 TAILQ_INIT(&pool->counters[0]);
4810 TAILQ_INIT(&pool->counters[1]);
4811 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4812 rte_spinlock_lock(&cmng->pool_update_sl);
4813 pool->index = cmng->n_valid;
4814 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4816 rte_spinlock_unlock(&cmng->pool_update_sl);
4819 cmng->pools[pool->index] = pool;
4821 if (unlikely(fallback)) {
4822 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4824 if (base < cmng->min_id)
4825 cmng->min_id = base;
4826 if (base > cmng->max_id)
4827 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4828 cmng->last_pool_idx = pool->index;
4830 rte_spinlock_unlock(&cmng->pool_update_sl);
4835 * Prepare a new counter and/or a new counter pool.
4838 * Pointer to the Ethernet device structure.
4839 * @param[out] cnt_free
4840 * Where to put the pointer of a new counter.
4842 * Whether the pool is for counter that was allocated for aging.
4845 * The counter pool pointer and @p cnt_free is set on success,
4846 * NULL otherwise and rte_errno is set.
4848 static struct mlx5_flow_counter_pool *
4849 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4850 struct mlx5_flow_counter **cnt_free,
4853 struct mlx5_priv *priv = dev->data->dev_private;
4854 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4855 struct mlx5_flow_counter_pool *pool;
4856 struct mlx5_counters tmp_tq;
4857 struct mlx5_devx_obj *dcs = NULL;
4858 struct mlx5_flow_counter *cnt;
4859 enum mlx5_counter_type cnt_type =
4860 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4861 bool fallback = priv->sh->cmng.counter_fallback;
4865 /* bulk_bitmap must be 0 for single counter allocation. */
4866 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4869 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4871 pool = flow_dv_pool_create(dev, dcs, age);
4873 mlx5_devx_cmd_destroy(dcs);
4877 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4878 cnt = MLX5_POOL_GET_CNT(pool, i);
4880 cnt->dcs_when_free = dcs;
4884 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4886 rte_errno = ENODATA;
4889 pool = flow_dv_pool_create(dev, dcs, age);
4891 mlx5_devx_cmd_destroy(dcs);
4894 TAILQ_INIT(&tmp_tq);
4895 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4896 cnt = MLX5_POOL_GET_CNT(pool, i);
4898 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4900 rte_spinlock_lock(&cmng->csl[cnt_type]);
4901 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4902 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4903 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4904 (*cnt_free)->pool = pool;
4909 * Allocate a flow counter.
4912 * Pointer to the Ethernet device structure.
4914 * Whether the counter was allocated for aging.
4917 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4920 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4922 struct mlx5_priv *priv = dev->data->dev_private;
4923 struct mlx5_flow_counter_pool *pool = NULL;
4924 struct mlx5_flow_counter *cnt_free = NULL;
4925 bool fallback = priv->sh->cmng.counter_fallback;
4926 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4927 enum mlx5_counter_type cnt_type =
4928 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4931 if (!priv->config.devx) {
4932 rte_errno = ENOTSUP;
4935 /* Get free counters from container. */
4936 rte_spinlock_lock(&cmng->csl[cnt_type]);
4937 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4939 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4940 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4941 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4943 pool = cnt_free->pool;
4945 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4946 /* Create a DV counter action only in the first time usage. */
4947 if (!cnt_free->action) {
4949 struct mlx5_devx_obj *dcs;
4953 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4954 dcs = pool->min_dcs;
4957 dcs = cnt_free->dcs_when_free;
4959 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4966 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4967 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4968 /* Update the counter reset values. */
4969 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4972 if (!fallback && !priv->sh->cmng.query_thread_on)
4973 /* Start the asynchronous batch query by the host thread. */
4974 mlx5_set_query_alarm(priv->sh);
4978 cnt_free->pool = pool;
4980 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4981 rte_spinlock_lock(&cmng->csl[cnt_type]);
4982 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4983 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4989 * Allocate a shared flow counter.
4992 * Pointer to the shared counter configuration.
4994 * Pointer to save the allocated counter index.
4997 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5001 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5003 struct mlx5_shared_counter_conf *conf = ctx;
5004 struct rte_eth_dev *dev = conf->dev;
5005 struct mlx5_flow_counter *cnt;
5007 data->dword = flow_dv_counter_alloc(dev, 0);
5008 data->dword |= MLX5_CNT_SHARED_OFFSET;
5009 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5010 cnt->shared_info.id = conf->id;
5015 * Get a shared flow counter.
5018 * Pointer to the Ethernet device structure.
5020 * Counter identifier.
5023 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5026 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5028 struct mlx5_priv *priv = dev->data->dev_private;
5029 struct mlx5_shared_counter_conf conf = {
5033 union mlx5_l3t_data data = {
5037 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5038 flow_dv_counter_alloc_shared_cb, &conf);
5043 * Get age param from counter index.
5046 * Pointer to the Ethernet device structure.
5047 * @param[in] counter
5048 * Index to the counter handler.
5051 * The aging parameter specified for the counter index.
5053 static struct mlx5_age_param*
5054 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5057 struct mlx5_flow_counter *cnt;
5058 struct mlx5_flow_counter_pool *pool = NULL;
5060 flow_dv_counter_get_by_idx(dev, counter, &pool);
5061 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5062 cnt = MLX5_POOL_GET_CNT(pool, counter);
5063 return MLX5_CNT_TO_AGE(cnt);
5067 * Remove a flow counter from aged counter list.
5070 * Pointer to the Ethernet device structure.
5071 * @param[in] counter
5072 * Index to the counter handler.
5074 * Pointer to the counter handler.
5077 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5078 uint32_t counter, struct mlx5_flow_counter *cnt)
5080 struct mlx5_age_info *age_info;
5081 struct mlx5_age_param *age_param;
5082 struct mlx5_priv *priv = dev->data->dev_private;
5083 uint16_t expected = AGE_CANDIDATE;
5085 age_info = GET_PORT_AGE_INFO(priv);
5086 age_param = flow_dv_counter_idx_get_age(dev, counter);
5087 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5088 AGE_FREE, false, __ATOMIC_RELAXED,
5089 __ATOMIC_RELAXED)) {
5091 * We need the lock even it is age timeout,
5092 * since counter may still in process.
5094 rte_spinlock_lock(&age_info->aged_sl);
5095 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5096 rte_spinlock_unlock(&age_info->aged_sl);
5097 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5102 * Release a flow counter.
5105 * Pointer to the Ethernet device structure.
5106 * @param[in] counter
5107 * Index to the counter handler.
5110 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5112 struct mlx5_priv *priv = dev->data->dev_private;
5113 struct mlx5_flow_counter_pool *pool = NULL;
5114 struct mlx5_flow_counter *cnt;
5115 enum mlx5_counter_type cnt_type;
5119 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5121 if (IS_SHARED_CNT(counter) &&
5122 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5125 flow_dv_counter_remove_from_age(dev, counter, cnt);
5128 * Put the counter back to list to be updated in none fallback mode.
5129 * Currently, we are using two list alternately, while one is in query,
5130 * add the freed counter to the other list based on the pool query_gen
5131 * value. After query finishes, add counter the list to the global
5132 * container counter list. The list changes while query starts. In
5133 * this case, lock will not be needed as query callback and release
5134 * function both operate with the different list.
5137 if (!priv->sh->cmng.counter_fallback) {
5138 rte_spinlock_lock(&pool->csl);
5139 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5140 rte_spinlock_unlock(&pool->csl);
5142 cnt->dcs_when_free = cnt->dcs_when_active;
5143 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5144 MLX5_COUNTER_TYPE_ORIGIN;
5145 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5146 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5148 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5153 * Verify the @p attributes will be correctly understood by the NIC and store
5154 * them in the @p flow if everything is correct.
5157 * Pointer to dev struct.
5158 * @param[in] attributes
5159 * Pointer to flow attributes
5160 * @param[in] external
5161 * This flow rule is created by request external to PMD.
5163 * Pointer to error structure.
5166 * - 0 on success and non root table.
5167 * - 1 on success and root table.
5168 * - a negative errno value otherwise and rte_errno is set.
5171 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5172 const struct mlx5_flow_tunnel *tunnel,
5173 const struct rte_flow_attr *attributes,
5174 struct flow_grp_info grp_info,
5175 struct rte_flow_error *error)
5177 struct mlx5_priv *priv = dev->data->dev_private;
5178 uint32_t priority_max = priv->config.flow_prio - 1;
5181 #ifndef HAVE_MLX5DV_DR
5182 RTE_SET_USED(tunnel);
5183 RTE_SET_USED(grp_info);
5184 if (attributes->group)
5185 return rte_flow_error_set(error, ENOTSUP,
5186 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5188 "groups are not supported");
5192 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5197 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5199 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5200 attributes->priority >= priority_max)
5201 return rte_flow_error_set(error, ENOTSUP,
5202 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5204 "priority out of range");
5205 if (attributes->transfer) {
5206 if (!priv->config.dv_esw_en)
5207 return rte_flow_error_set
5209 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5210 "E-Switch dr is not supported");
5211 if (!(priv->representor || priv->master))
5212 return rte_flow_error_set
5213 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5214 NULL, "E-Switch configuration can only be"
5215 " done by a master or a representor device");
5216 if (attributes->egress)
5217 return rte_flow_error_set
5219 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5220 "egress is not supported");
5222 if (!(attributes->egress ^ attributes->ingress))
5223 return rte_flow_error_set(error, ENOTSUP,
5224 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5225 "must specify exactly one of "
5226 "ingress or egress");
5231 * Internal validation function. For validating both actions and items.
5234 * Pointer to the rte_eth_dev structure.
5236 * Pointer to the flow attributes.
5238 * Pointer to the list of items.
5239 * @param[in] actions
5240 * Pointer to the list of actions.
5241 * @param[in] external
5242 * This flow rule is created by request external to PMD.
5243 * @param[in] hairpin
5244 * Number of hairpin TX actions, 0 means classic flow.
5246 * Pointer to the error structure.
5249 * 0 on success, a negative errno value otherwise and rte_errno is set.
5252 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5253 const struct rte_flow_item items[],
5254 const struct rte_flow_action actions[],
5255 bool external, int hairpin, struct rte_flow_error *error)
5258 uint64_t action_flags = 0;
5259 uint64_t item_flags = 0;
5260 uint64_t last_item = 0;
5261 uint8_t next_protocol = 0xff;
5262 uint16_t ether_type = 0;
5264 uint8_t item_ipv6_proto = 0;
5265 const struct rte_flow_item *gre_item = NULL;
5266 const struct rte_flow_action_raw_decap *decap;
5267 const struct rte_flow_action_raw_encap *encap;
5268 const struct rte_flow_action_rss *rss;
5269 const struct rte_flow_item_tcp nic_tcp_mask = {
5272 .src_port = RTE_BE16(UINT16_MAX),
5273 .dst_port = RTE_BE16(UINT16_MAX),
5276 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5279 "\xff\xff\xff\xff\xff\xff\xff\xff"
5280 "\xff\xff\xff\xff\xff\xff\xff\xff",
5282 "\xff\xff\xff\xff\xff\xff\xff\xff"
5283 "\xff\xff\xff\xff\xff\xff\xff\xff",
5284 .vtc_flow = RTE_BE32(0xffffffff),
5290 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5294 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5298 .dummy[0] = 0xffffffff,
5301 struct mlx5_priv *priv = dev->data->dev_private;
5302 struct mlx5_dev_config *dev_conf = &priv->config;
5303 uint16_t queue_index = 0xFFFF;
5304 const struct rte_flow_item_vlan *vlan_m = NULL;
5305 int16_t rw_act_num = 0;
5307 const struct mlx5_flow_tunnel *tunnel;
5308 struct flow_grp_info grp_info = {
5309 .external = !!external,
5310 .transfer = !!attr->transfer,
5311 .fdb_def_rule = !!priv->fdb_def_rule,
5313 const struct rte_eth_hairpin_conf *conf;
5317 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5318 tunnel = flow_items_to_tunnel(items);
5319 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5320 MLX5_FLOW_ACTION_DECAP;
5321 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5322 tunnel = flow_actions_to_tunnel(actions);
5323 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5327 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5328 (dev, tunnel, attr, items, actions);
5329 ret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);
5332 is_root = (uint64_t)ret;
5333 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5334 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5335 int type = items->type;
5337 if (!mlx5_flow_os_item_supported(type))
5338 return rte_flow_error_set(error, ENOTSUP,
5339 RTE_FLOW_ERROR_TYPE_ITEM,
5340 NULL, "item not supported");
5342 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5343 if (items[0].type != (typeof(items[0].type))
5344 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5345 return rte_flow_error_set
5347 RTE_FLOW_ERROR_TYPE_ITEM,
5348 NULL, "MLX5 private items "
5349 "must be the first");
5351 case RTE_FLOW_ITEM_TYPE_VOID:
5353 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5354 ret = flow_dv_validate_item_port_id
5355 (dev, items, attr, item_flags, error);
5358 last_item = MLX5_FLOW_ITEM_PORT_ID;
5360 case RTE_FLOW_ITEM_TYPE_ETH:
5361 ret = mlx5_flow_validate_item_eth(items, item_flags,
5365 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5366 MLX5_FLOW_LAYER_OUTER_L2;
5367 if (items->mask != NULL && items->spec != NULL) {
5369 ((const struct rte_flow_item_eth *)
5372 ((const struct rte_flow_item_eth *)
5374 ether_type = rte_be_to_cpu_16(ether_type);
5379 case RTE_FLOW_ITEM_TYPE_VLAN:
5380 ret = flow_dv_validate_item_vlan(items, item_flags,
5384 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5385 MLX5_FLOW_LAYER_OUTER_VLAN;
5386 if (items->mask != NULL && items->spec != NULL) {
5388 ((const struct rte_flow_item_vlan *)
5389 items->spec)->inner_type;
5391 ((const struct rte_flow_item_vlan *)
5392 items->mask)->inner_type;
5393 ether_type = rte_be_to_cpu_16(ether_type);
5397 /* Store outer VLAN mask for of_push_vlan action. */
5399 vlan_m = items->mask;
5401 case RTE_FLOW_ITEM_TYPE_IPV4:
5402 mlx5_flow_tunnel_ip_check(items, next_protocol,
5403 &item_flags, &tunnel);
5404 ret = flow_dv_validate_item_ipv4(items, item_flags,
5405 last_item, ether_type,
5409 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5410 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5411 if (items->mask != NULL &&
5412 ((const struct rte_flow_item_ipv4 *)
5413 items->mask)->hdr.next_proto_id) {
5415 ((const struct rte_flow_item_ipv4 *)
5416 (items->spec))->hdr.next_proto_id;
5418 ((const struct rte_flow_item_ipv4 *)
5419 (items->mask))->hdr.next_proto_id;
5421 /* Reset for inner layer. */
5422 next_protocol = 0xff;
5425 case RTE_FLOW_ITEM_TYPE_IPV6:
5426 mlx5_flow_tunnel_ip_check(items, next_protocol,
5427 &item_flags, &tunnel);
5428 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5435 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5436 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5437 if (items->mask != NULL &&
5438 ((const struct rte_flow_item_ipv6 *)
5439 items->mask)->hdr.proto) {
5441 ((const struct rte_flow_item_ipv6 *)
5442 items->spec)->hdr.proto;
5444 ((const struct rte_flow_item_ipv6 *)
5445 items->spec)->hdr.proto;
5447 ((const struct rte_flow_item_ipv6 *)
5448 items->mask)->hdr.proto;
5450 /* Reset for inner layer. */
5451 next_protocol = 0xff;
5454 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5455 ret = flow_dv_validate_item_ipv6_frag_ext(items,
5460 last_item = tunnel ?
5461 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5462 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5463 if (items->mask != NULL &&
5464 ((const struct rte_flow_item_ipv6_frag_ext *)
5465 items->mask)->hdr.next_header) {
5467 ((const struct rte_flow_item_ipv6_frag_ext *)
5468 items->spec)->hdr.next_header;
5470 ((const struct rte_flow_item_ipv6_frag_ext *)
5471 items->mask)->hdr.next_header;
5473 /* Reset for inner layer. */
5474 next_protocol = 0xff;
5477 case RTE_FLOW_ITEM_TYPE_TCP:
5478 ret = mlx5_flow_validate_item_tcp
5485 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5486 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5488 case RTE_FLOW_ITEM_TYPE_UDP:
5489 ret = mlx5_flow_validate_item_udp(items, item_flags,
5494 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5495 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5497 case RTE_FLOW_ITEM_TYPE_GRE:
5498 ret = mlx5_flow_validate_item_gre(items, item_flags,
5499 next_protocol, error);
5503 last_item = MLX5_FLOW_LAYER_GRE;
5505 case RTE_FLOW_ITEM_TYPE_NVGRE:
5506 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5511 last_item = MLX5_FLOW_LAYER_NVGRE;
5513 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5514 ret = mlx5_flow_validate_item_gre_key
5515 (items, item_flags, gre_item, error);
5518 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5520 case RTE_FLOW_ITEM_TYPE_VXLAN:
5521 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5525 last_item = MLX5_FLOW_LAYER_VXLAN;
5527 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5528 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5533 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5535 case RTE_FLOW_ITEM_TYPE_GENEVE:
5536 ret = mlx5_flow_validate_item_geneve(items,
5541 last_item = MLX5_FLOW_LAYER_GENEVE;
5543 case RTE_FLOW_ITEM_TYPE_MPLS:
5544 ret = mlx5_flow_validate_item_mpls(dev, items,
5549 last_item = MLX5_FLOW_LAYER_MPLS;
5552 case RTE_FLOW_ITEM_TYPE_MARK:
5553 ret = flow_dv_validate_item_mark(dev, items, attr,
5557 last_item = MLX5_FLOW_ITEM_MARK;
5559 case RTE_FLOW_ITEM_TYPE_META:
5560 ret = flow_dv_validate_item_meta(dev, items, attr,
5564 last_item = MLX5_FLOW_ITEM_METADATA;
5566 case RTE_FLOW_ITEM_TYPE_ICMP:
5567 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5572 last_item = MLX5_FLOW_LAYER_ICMP;
5574 case RTE_FLOW_ITEM_TYPE_ICMP6:
5575 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5580 item_ipv6_proto = IPPROTO_ICMPV6;
5581 last_item = MLX5_FLOW_LAYER_ICMP6;
5583 case RTE_FLOW_ITEM_TYPE_TAG:
5584 ret = flow_dv_validate_item_tag(dev, items,
5588 last_item = MLX5_FLOW_ITEM_TAG;
5590 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5591 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5593 case RTE_FLOW_ITEM_TYPE_GTP:
5594 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5598 last_item = MLX5_FLOW_LAYER_GTP;
5600 case RTE_FLOW_ITEM_TYPE_ECPRI:
5601 /* Capacity will be checked in the translate stage. */
5602 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5609 last_item = MLX5_FLOW_LAYER_ECPRI;
5612 return rte_flow_error_set(error, ENOTSUP,
5613 RTE_FLOW_ERROR_TYPE_ITEM,
5614 NULL, "item not supported");
5616 item_flags |= last_item;
5618 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5619 int type = actions->type;
5621 if (!mlx5_flow_os_action_supported(type))
5622 return rte_flow_error_set(error, ENOTSUP,
5623 RTE_FLOW_ERROR_TYPE_ACTION,
5625 "action not supported");
5626 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5627 return rte_flow_error_set(error, ENOTSUP,
5628 RTE_FLOW_ERROR_TYPE_ACTION,
5629 actions, "too many actions");
5631 case RTE_FLOW_ACTION_TYPE_VOID:
5633 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5634 ret = flow_dv_validate_action_port_id(dev,
5641 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5644 case RTE_FLOW_ACTION_TYPE_FLAG:
5645 ret = flow_dv_validate_action_flag(dev, action_flags,
5649 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5650 /* Count all modify-header actions as one. */
5651 if (!(action_flags &
5652 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5654 action_flags |= MLX5_FLOW_ACTION_FLAG |
5655 MLX5_FLOW_ACTION_MARK_EXT;
5657 action_flags |= MLX5_FLOW_ACTION_FLAG;
5660 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5662 case RTE_FLOW_ACTION_TYPE_MARK:
5663 ret = flow_dv_validate_action_mark(dev, actions,
5668 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5669 /* Count all modify-header actions as one. */
5670 if (!(action_flags &
5671 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5673 action_flags |= MLX5_FLOW_ACTION_MARK |
5674 MLX5_FLOW_ACTION_MARK_EXT;
5676 action_flags |= MLX5_FLOW_ACTION_MARK;
5679 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5681 case RTE_FLOW_ACTION_TYPE_SET_META:
5682 ret = flow_dv_validate_action_set_meta(dev, actions,
5687 /* Count all modify-header actions as one action. */
5688 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5690 action_flags |= MLX5_FLOW_ACTION_SET_META;
5691 rw_act_num += MLX5_ACT_NUM_SET_META;
5693 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5694 ret = flow_dv_validate_action_set_tag(dev, actions,
5699 /* Count all modify-header actions as one action. */
5700 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5702 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5703 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5705 case RTE_FLOW_ACTION_TYPE_DROP:
5706 ret = mlx5_flow_validate_action_drop(action_flags,
5710 action_flags |= MLX5_FLOW_ACTION_DROP;
5713 case RTE_FLOW_ACTION_TYPE_QUEUE:
5714 ret = mlx5_flow_validate_action_queue(actions,
5719 queue_index = ((const struct rte_flow_action_queue *)
5720 (actions->conf))->index;
5721 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5724 case RTE_FLOW_ACTION_TYPE_RSS:
5725 rss = actions->conf;
5726 ret = mlx5_flow_validate_action_rss(actions,
5732 if (rss != NULL && rss->queue_num)
5733 queue_index = rss->queue[0];
5734 action_flags |= MLX5_FLOW_ACTION_RSS;
5737 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5739 mlx5_flow_validate_action_default_miss(action_flags,
5743 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5746 case RTE_FLOW_ACTION_TYPE_COUNT:
5747 ret = flow_dv_validate_action_count(dev, error);
5750 action_flags |= MLX5_FLOW_ACTION_COUNT;
5753 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5754 if (flow_dv_validate_action_pop_vlan(dev,
5760 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5763 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5764 ret = flow_dv_validate_action_push_vlan(dev,
5771 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5774 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5775 ret = flow_dv_validate_action_set_vlan_pcp
5776 (action_flags, actions, error);
5779 /* Count PCP with push_vlan command. */
5780 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5782 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5783 ret = flow_dv_validate_action_set_vlan_vid
5784 (item_flags, action_flags,
5788 /* Count VID with push_vlan command. */
5789 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5790 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5792 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5793 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5794 ret = flow_dv_validate_action_l2_encap(dev,
5800 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5803 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5804 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5805 ret = flow_dv_validate_action_decap(dev, action_flags,
5809 action_flags |= MLX5_FLOW_ACTION_DECAP;
5812 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5813 ret = flow_dv_validate_action_raw_encap_decap
5814 (dev, NULL, actions->conf, attr, &action_flags,
5819 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5820 decap = actions->conf;
5821 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5823 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5827 encap = actions->conf;
5829 ret = flow_dv_validate_action_raw_encap_decap
5831 decap ? decap : &empty_decap, encap,
5832 attr, &action_flags, &actions_n,
5837 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5838 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5839 ret = flow_dv_validate_action_modify_mac(action_flags,
5845 /* Count all modify-header actions as one action. */
5846 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5848 action_flags |= actions->type ==
5849 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5850 MLX5_FLOW_ACTION_SET_MAC_SRC :
5851 MLX5_FLOW_ACTION_SET_MAC_DST;
5853 * Even if the source and destination MAC addresses have
5854 * overlap in the header with 4B alignment, the convert
5855 * function will handle them separately and 4 SW actions
5856 * will be created. And 2 actions will be added each
5857 * time no matter how many bytes of address will be set.
5859 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5861 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5862 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5863 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5869 /* Count all modify-header actions as one action. */
5870 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5872 action_flags |= actions->type ==
5873 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5874 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5875 MLX5_FLOW_ACTION_SET_IPV4_DST;
5876 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5878 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5879 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5880 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5886 if (item_ipv6_proto == IPPROTO_ICMPV6)
5887 return rte_flow_error_set(error, ENOTSUP,
5888 RTE_FLOW_ERROR_TYPE_ACTION,
5890 "Can't change header "
5891 "with ICMPv6 proto");
5892 /* Count all modify-header actions as one action. */
5893 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5895 action_flags |= actions->type ==
5896 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5897 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5898 MLX5_FLOW_ACTION_SET_IPV6_DST;
5899 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5901 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5902 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5903 ret = flow_dv_validate_action_modify_tp(action_flags,
5909 /* Count all modify-header actions as one action. */
5910 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5912 action_flags |= actions->type ==
5913 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5914 MLX5_FLOW_ACTION_SET_TP_SRC :
5915 MLX5_FLOW_ACTION_SET_TP_DST;
5916 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5918 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5919 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5920 ret = flow_dv_validate_action_modify_ttl(action_flags,
5926 /* Count all modify-header actions as one action. */
5927 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5929 action_flags |= actions->type ==
5930 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5931 MLX5_FLOW_ACTION_SET_TTL :
5932 MLX5_FLOW_ACTION_DEC_TTL;
5933 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5935 case RTE_FLOW_ACTION_TYPE_JUMP:
5936 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5943 action_flags |= MLX5_FLOW_ACTION_JUMP;
5945 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5946 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5947 ret = flow_dv_validate_action_modify_tcp_seq
5954 /* Count all modify-header actions as one action. */
5955 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5957 action_flags |= actions->type ==
5958 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5959 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5960 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5961 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5963 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5964 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5965 ret = flow_dv_validate_action_modify_tcp_ack
5972 /* Count all modify-header actions as one action. */
5973 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5975 action_flags |= actions->type ==
5976 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5977 MLX5_FLOW_ACTION_INC_TCP_ACK :
5978 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5979 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5981 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5983 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5984 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5985 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5987 case RTE_FLOW_ACTION_TYPE_METER:
5988 ret = mlx5_flow_validate_action_meter(dev,
5994 action_flags |= MLX5_FLOW_ACTION_METER;
5996 /* Meter action will add one more TAG action. */
5997 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5999 case RTE_FLOW_ACTION_TYPE_AGE:
6000 ret = flow_dv_validate_action_age(action_flags,
6005 action_flags |= MLX5_FLOW_ACTION_AGE;
6008 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6009 ret = flow_dv_validate_action_modify_ipv4_dscp
6016 /* Count all modify-header actions as one action. */
6017 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6019 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6020 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6022 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6023 ret = flow_dv_validate_action_modify_ipv6_dscp
6030 /* Count all modify-header actions as one action. */
6031 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6033 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6034 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6036 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6037 ret = flow_dv_validate_action_sample(action_flags,
6042 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6045 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6046 if (actions[0].type != (typeof(actions[0].type))
6047 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6048 return rte_flow_error_set
6050 RTE_FLOW_ERROR_TYPE_ACTION,
6051 NULL, "MLX5 private action "
6052 "must be the first");
6054 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6057 return rte_flow_error_set(error, ENOTSUP,
6058 RTE_FLOW_ERROR_TYPE_ACTION,
6060 "action not supported");
6064 * Validate actions in flow rules
6065 * - Explicit decap action is prohibited by the tunnel offload API.
6066 * - Drop action in tunnel steer rule is prohibited by the API.
6067 * - Application cannot use MARK action because it's value can mask
6068 * tunnel default miss nitification.
6069 * - JUMP in tunnel match rule has no support in current PMD
6071 * - TAG & META are reserved for future uses.
6073 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6074 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6075 MLX5_FLOW_ACTION_MARK |
6076 MLX5_FLOW_ACTION_SET_TAG |
6077 MLX5_FLOW_ACTION_SET_META |
6078 MLX5_FLOW_ACTION_DROP;
6080 if (action_flags & bad_actions_mask)
6081 return rte_flow_error_set
6083 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6084 "Invalid RTE action in tunnel "
6086 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6087 return rte_flow_error_set
6089 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6090 "tunnel set decap rule must terminate "
6093 return rte_flow_error_set
6095 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6096 "tunnel flows for ingress traffic only");
6098 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6099 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6100 MLX5_FLOW_ACTION_MARK |
6101 MLX5_FLOW_ACTION_SET_TAG |
6102 MLX5_FLOW_ACTION_SET_META;
6104 if (action_flags & bad_actions_mask)
6105 return rte_flow_error_set
6107 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6108 "Invalid RTE action in tunnel "
6112 * Validate the drop action mutual exclusion with other actions.
6113 * Drop action is mutually-exclusive with any other action, except for
6116 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6117 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6118 return rte_flow_error_set(error, EINVAL,
6119 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6120 "Drop action is mutually-exclusive "
6121 "with any other action, except for "
6123 /* Eswitch has few restrictions on using items and actions */
6124 if (attr->transfer) {
6125 if (!mlx5_flow_ext_mreg_supported(dev) &&
6126 action_flags & MLX5_FLOW_ACTION_FLAG)
6127 return rte_flow_error_set(error, ENOTSUP,
6128 RTE_FLOW_ERROR_TYPE_ACTION,
6130 "unsupported action FLAG");
6131 if (!mlx5_flow_ext_mreg_supported(dev) &&
6132 action_flags & MLX5_FLOW_ACTION_MARK)
6133 return rte_flow_error_set(error, ENOTSUP,
6134 RTE_FLOW_ERROR_TYPE_ACTION,
6136 "unsupported action MARK");
6137 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6138 return rte_flow_error_set(error, ENOTSUP,
6139 RTE_FLOW_ERROR_TYPE_ACTION,
6141 "unsupported action QUEUE");
6142 if (action_flags & MLX5_FLOW_ACTION_RSS)
6143 return rte_flow_error_set(error, ENOTSUP,
6144 RTE_FLOW_ERROR_TYPE_ACTION,
6146 "unsupported action RSS");
6147 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6148 return rte_flow_error_set(error, EINVAL,
6149 RTE_FLOW_ERROR_TYPE_ACTION,
6151 "no fate action is found");
6153 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6154 return rte_flow_error_set(error, EINVAL,
6155 RTE_FLOW_ERROR_TYPE_ACTION,
6157 "no fate action is found");
6160 * Continue validation for Xcap and VLAN actions.
6161 * If hairpin is working in explicit TX rule mode, there is no actions
6162 * splitting and the validation of hairpin ingress flow should be the
6163 * same as other standard flows.
6165 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6166 MLX5_FLOW_VLAN_ACTIONS)) &&
6167 (queue_index == 0xFFFF ||
6168 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6169 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6170 conf->tx_explicit != 0))) {
6171 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6172 MLX5_FLOW_XCAP_ACTIONS)
6173 return rte_flow_error_set(error, ENOTSUP,
6174 RTE_FLOW_ERROR_TYPE_ACTION,
6175 NULL, "encap and decap "
6176 "combination aren't supported");
6177 if (!attr->transfer && attr->ingress) {
6178 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6179 return rte_flow_error_set
6181 RTE_FLOW_ERROR_TYPE_ACTION,
6182 NULL, "encap is not supported"
6183 " for ingress traffic");
6184 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6185 return rte_flow_error_set
6187 RTE_FLOW_ERROR_TYPE_ACTION,
6188 NULL, "push VLAN action not "
6189 "supported for ingress");
6190 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6191 MLX5_FLOW_VLAN_ACTIONS)
6192 return rte_flow_error_set
6194 RTE_FLOW_ERROR_TYPE_ACTION,
6195 NULL, "no support for "
6196 "multiple VLAN actions");
6200 * Hairpin flow will add one more TAG action in TX implicit mode.
6201 * In TX explicit mode, there will be no hairpin flow ID.
6204 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6205 /* extra metadata enabled: one more TAG action will be add. */
6206 if (dev_conf->dv_flow_en &&
6207 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6208 mlx5_flow_ext_mreg_supported(dev))
6209 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6210 if ((uint32_t)rw_act_num >
6211 flow_dv_modify_hdr_action_max(dev, is_root)) {
6212 return rte_flow_error_set(error, ENOTSUP,
6213 RTE_FLOW_ERROR_TYPE_ACTION,
6214 NULL, "too many header modify"
6215 " actions to support");
6221 * Internal preparation function. Allocates the DV flow size,
6222 * this size is constant.
6225 * Pointer to the rte_eth_dev structure.
6227 * Pointer to the flow attributes.
6229 * Pointer to the list of items.
6230 * @param[in] actions
6231 * Pointer to the list of actions.
6233 * Pointer to the error structure.
6236 * Pointer to mlx5_flow object on success,
6237 * otherwise NULL and rte_errno is set.
6239 static struct mlx5_flow *
6240 flow_dv_prepare(struct rte_eth_dev *dev,
6241 const struct rte_flow_attr *attr __rte_unused,
6242 const struct rte_flow_item items[] __rte_unused,
6243 const struct rte_flow_action actions[] __rte_unused,
6244 struct rte_flow_error *error)
6246 uint32_t handle_idx = 0;
6247 struct mlx5_flow *dev_flow;
6248 struct mlx5_flow_handle *dev_handle;
6249 struct mlx5_priv *priv = dev->data->dev_private;
6251 /* In case of corrupting the memory. */
6252 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6253 rte_flow_error_set(error, ENOSPC,
6254 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6255 "not free temporary device flow");
6258 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6261 rte_flow_error_set(error, ENOMEM,
6262 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6263 "not enough memory to create flow handle");
6266 /* No multi-thread supporting. */
6267 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
6268 dev_flow->handle = dev_handle;
6269 dev_flow->handle_idx = handle_idx;
6271 * In some old rdma-core releases, before continuing, a check of the
6272 * length of matching parameter will be done at first. It needs to use
6273 * the length without misc4 param. If the flow has misc4 support, then
6274 * the length needs to be adjusted accordingly. Each param member is
6275 * aligned with a 64B boundary naturally.
6277 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6278 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6280 * The matching value needs to be cleared to 0 before using. In the
6281 * past, it will be automatically cleared when using rte_*alloc
6282 * API. The time consumption will be almost the same as before.
6284 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6285 dev_flow->ingress = attr->ingress;
6286 dev_flow->dv.transfer = attr->transfer;
6290 #ifdef RTE_LIBRTE_MLX5_DEBUG
6292 * Sanity check for match mask and value. Similar to check_valid_spec() in
6293 * kernel driver. If unmasked bit is present in value, it returns failure.
6296 * pointer to match mask buffer.
6297 * @param match_value
6298 * pointer to match value buffer.
6301 * 0 if valid, -EINVAL otherwise.
6304 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6306 uint8_t *m = match_mask;
6307 uint8_t *v = match_value;
6310 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6313 "match_value differs from match_criteria"
6314 " %p[%u] != %p[%u]",
6315 match_value, i, match_mask, i);
6324 * Add match of ip_version.
6328 * @param[in] headers_v
6329 * Values header pointer.
6330 * @param[in] headers_m
6331 * Masks header pointer.
6332 * @param[in] ip_version
6333 * The IP version to set.
6336 flow_dv_set_match_ip_version(uint32_t group,
6342 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6344 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6346 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6347 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6348 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6352 * Add Ethernet item to matcher and to the value.
6354 * @param[in, out] matcher
6356 * @param[in, out] key
6357 * Flow matcher value.
6359 * Flow pattern to translate.
6361 * Item is inner pattern.
6364 flow_dv_translate_item_eth(void *matcher, void *key,
6365 const struct rte_flow_item *item, int inner,
6368 const struct rte_flow_item_eth *eth_m = item->mask;
6369 const struct rte_flow_item_eth *eth_v = item->spec;
6370 const struct rte_flow_item_eth nic_mask = {
6371 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6372 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6373 .type = RTE_BE16(0xffff),
6385 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6387 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6389 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6391 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6393 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
6394 ð_m->dst, sizeof(eth_m->dst));
6395 /* The value must be in the range of the mask. */
6396 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
6397 for (i = 0; i < sizeof(eth_m->dst); ++i)
6398 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6399 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
6400 ð_m->src, sizeof(eth_m->src));
6401 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
6402 /* The value must be in the range of the mask. */
6403 for (i = 0; i < sizeof(eth_m->dst); ++i)
6404 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6406 /* When ethertype is present set mask for tagged VLAN. */
6407 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6408 /* Set value for tagged VLAN if ethertype is 802.1Q. */
6409 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
6410 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
6411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
6413 /* Return here to avoid setting match on ethertype. */
6418 * HW supports match on one Ethertype, the Ethertype following the last
6419 * VLAN tag of the packet (see PRM).
6420 * Set match on ethertype only if ETH header is not followed by VLAN.
6421 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6422 * ethertype, and use ip_version field instead.
6423 * eCPRI over Ether layer will use type value 0xAEFE.
6425 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6426 eth_m->type == 0xFFFF) {
6427 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6428 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6429 eth_m->type == 0xFFFF) {
6430 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6432 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6433 rte_be_to_cpu_16(eth_m->type));
6434 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6436 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6441 * Add VLAN item to matcher and to the value.
6443 * @param[in, out] dev_flow
6445 * @param[in, out] matcher
6447 * @param[in, out] key
6448 * Flow matcher value.
6450 * Flow pattern to translate.
6452 * Item is inner pattern.
6455 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6456 void *matcher, void *key,
6457 const struct rte_flow_item *item,
6458 int inner, uint32_t group)
6460 const struct rte_flow_item_vlan *vlan_m = item->mask;
6461 const struct rte_flow_item_vlan *vlan_v = item->spec;
6468 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6470 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6472 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6474 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6476 * This is workaround, masks are not supported,
6477 * and pre-validated.
6480 dev_flow->handle->vf_vlan.tag =
6481 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6484 * When VLAN item exists in flow, mark packet as tagged,
6485 * even if TCI is not specified.
6487 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6488 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6492 vlan_m = &rte_flow_item_vlan_mask;
6493 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6494 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6495 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6499 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6502 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6503 * ethertype, and use ip_version field instead.
6505 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6506 vlan_m->inner_type == 0xFFFF) {
6507 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6508 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6509 vlan_m->inner_type == 0xFFFF) {
6510 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6512 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6513 rte_be_to_cpu_16(vlan_m->inner_type));
6514 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6515 rte_be_to_cpu_16(vlan_m->inner_type &
6516 vlan_v->inner_type));
6521 * Add IPV4 item to matcher and to the value.
6523 * @param[in, out] matcher
6525 * @param[in, out] key
6526 * Flow matcher value.
6528 * Flow pattern to translate.
6529 * @param[in] item_flags
6530 * Bit-fields that holds the items detected until now.
6532 * Item is inner pattern.
6534 * The group to insert the rule.
6537 flow_dv_translate_item_ipv4(void *matcher, void *key,
6538 const struct rte_flow_item *item,
6539 const uint64_t item_flags,
6540 int inner, uint32_t group)
6542 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6543 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6544 const struct rte_flow_item_ipv4 nic_mask = {
6546 .src_addr = RTE_BE32(0xffffffff),
6547 .dst_addr = RTE_BE32(0xffffffff),
6548 .type_of_service = 0xff,
6549 .next_proto_id = 0xff,
6550 .time_to_live = 0xff,
6560 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6562 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6564 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6566 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6568 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6570 * On outer header (which must contains L2), or inner header with L2,
6571 * set cvlan_tag mask bit to mark this packet as untagged.
6572 * This should be done even if item->spec is empty.
6574 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6575 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6580 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6581 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6582 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6583 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6584 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6585 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6586 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6587 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6588 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6589 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6590 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6591 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6592 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6593 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6594 ipv4_m->hdr.type_of_service);
6595 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6596 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6597 ipv4_m->hdr.type_of_service >> 2);
6598 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6599 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6600 ipv4_m->hdr.next_proto_id);
6601 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6602 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6603 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6604 ipv4_m->hdr.time_to_live);
6605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6606 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6607 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6608 !!(ipv4_m->hdr.fragment_offset));
6609 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6610 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6614 * Add IPV6 item to matcher and to the value.
6616 * @param[in, out] matcher
6618 * @param[in, out] key
6619 * Flow matcher value.
6621 * Flow pattern to translate.
6622 * @param[in] item_flags
6623 * Bit-fields that holds the items detected until now.
6625 * Item is inner pattern.
6627 * The group to insert the rule.
6630 flow_dv_translate_item_ipv6(void *matcher, void *key,
6631 const struct rte_flow_item *item,
6632 const uint64_t item_flags,
6633 int inner, uint32_t group)
6635 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6636 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6637 const struct rte_flow_item_ipv6 nic_mask = {
6640 "\xff\xff\xff\xff\xff\xff\xff\xff"
6641 "\xff\xff\xff\xff\xff\xff\xff\xff",
6643 "\xff\xff\xff\xff\xff\xff\xff\xff"
6644 "\xff\xff\xff\xff\xff\xff\xff\xff",
6645 .vtc_flow = RTE_BE32(0xffffffff),
6652 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6653 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6662 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6664 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6666 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6668 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6670 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6672 * On outer header (which must contains L2), or inner header with L2,
6673 * set cvlan_tag mask bit to mark this packet as untagged.
6674 * This should be done even if item->spec is empty.
6676 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6677 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6682 size = sizeof(ipv6_m->hdr.dst_addr);
6683 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6684 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6685 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6686 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6687 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6688 for (i = 0; i < size; ++i)
6689 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6690 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6691 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6692 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6693 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6694 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6695 for (i = 0; i < size; ++i)
6696 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6698 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6699 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6700 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6701 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6702 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6703 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6706 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6708 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6711 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6713 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6717 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6719 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6720 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6722 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6723 ipv6_m->hdr.hop_limits);
6724 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6725 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6727 !!(ipv6_m->has_frag_ext));
6728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6729 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6733 * Add IPV6 fragment extension item to matcher and to the value.
6735 * @param[in, out] matcher
6737 * @param[in, out] key
6738 * Flow matcher value.
6740 * Flow pattern to translate.
6742 * Item is inner pattern.
6745 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6746 const struct rte_flow_item *item,
6749 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6750 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6751 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6753 .next_header = 0xff,
6754 .frag_data = RTE_BE16(0xffff),
6761 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6763 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6765 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6767 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6769 /* IPv6 fragment extension item exists, so packet is IP fragment. */
6770 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6771 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6772 if (!ipv6_frag_ext_v)
6774 if (!ipv6_frag_ext_m)
6775 ipv6_frag_ext_m = &nic_mask;
6776 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6777 ipv6_frag_ext_m->hdr.next_header);
6778 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6779 ipv6_frag_ext_v->hdr.next_header &
6780 ipv6_frag_ext_m->hdr.next_header);
6784 * Add TCP item to matcher and to the value.
6786 * @param[in, out] matcher
6788 * @param[in, out] key
6789 * Flow matcher value.
6791 * Flow pattern to translate.
6793 * Item is inner pattern.
6796 flow_dv_translate_item_tcp(void *matcher, void *key,
6797 const struct rte_flow_item *item,
6800 const struct rte_flow_item_tcp *tcp_m = item->mask;
6801 const struct rte_flow_item_tcp *tcp_v = item->spec;
6806 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6808 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6810 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6812 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6814 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6815 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6819 tcp_m = &rte_flow_item_tcp_mask;
6820 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6821 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6822 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6823 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6824 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6825 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6826 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6827 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6828 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6829 tcp_m->hdr.tcp_flags);
6830 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6831 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6835 * Add UDP item to matcher and to the value.
6837 * @param[in, out] matcher
6839 * @param[in, out] key
6840 * Flow matcher value.
6842 * Flow pattern to translate.
6844 * Item is inner pattern.
6847 flow_dv_translate_item_udp(void *matcher, void *key,
6848 const struct rte_flow_item *item,
6851 const struct rte_flow_item_udp *udp_m = item->mask;
6852 const struct rte_flow_item_udp *udp_v = item->spec;
6857 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6859 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6861 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6863 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6865 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6866 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6870 udp_m = &rte_flow_item_udp_mask;
6871 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6872 rte_be_to_cpu_16(udp_m->hdr.src_port));
6873 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6874 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6875 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6876 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6877 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6878 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6882 * Add GRE optional Key item to matcher and to the value.
6884 * @param[in, out] matcher
6886 * @param[in, out] key
6887 * Flow matcher value.
6889 * Flow pattern to translate.
6891 * Item is inner pattern.
6894 flow_dv_translate_item_gre_key(void *matcher, void *key,
6895 const struct rte_flow_item *item)
6897 const rte_be32_t *key_m = item->mask;
6898 const rte_be32_t *key_v = item->spec;
6899 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6900 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6901 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6903 /* GRE K bit must be on and should already be validated */
6904 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6905 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6909 key_m = &gre_key_default_mask;
6910 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6911 rte_be_to_cpu_32(*key_m) >> 8);
6912 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6913 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6914 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6915 rte_be_to_cpu_32(*key_m) & 0xFF);
6916 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6917 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6921 * Add GRE item to matcher and to the value.
6923 * @param[in, out] matcher
6925 * @param[in, out] key
6926 * Flow matcher value.
6928 * Flow pattern to translate.
6930 * Item is inner pattern.
6933 flow_dv_translate_item_gre(void *matcher, void *key,
6934 const struct rte_flow_item *item,
6937 const struct rte_flow_item_gre *gre_m = item->mask;
6938 const struct rte_flow_item_gre *gre_v = item->spec;
6941 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6942 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6949 uint16_t s_present:1;
6950 uint16_t k_present:1;
6951 uint16_t rsvd_bit1:1;
6952 uint16_t c_present:1;
6956 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6959 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6961 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6963 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6965 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6967 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6968 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6972 gre_m = &rte_flow_item_gre_mask;
6973 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6974 rte_be_to_cpu_16(gre_m->protocol));
6975 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6976 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6977 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6978 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6979 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6980 gre_crks_rsvd0_ver_m.c_present);
6981 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6982 gre_crks_rsvd0_ver_v.c_present &
6983 gre_crks_rsvd0_ver_m.c_present);
6984 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6985 gre_crks_rsvd0_ver_m.k_present);
6986 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6987 gre_crks_rsvd0_ver_v.k_present &
6988 gre_crks_rsvd0_ver_m.k_present);
6989 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6990 gre_crks_rsvd0_ver_m.s_present);
6991 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6992 gre_crks_rsvd0_ver_v.s_present &
6993 gre_crks_rsvd0_ver_m.s_present);
6997 * Add NVGRE item to matcher and to the value.
6999 * @param[in, out] matcher
7001 * @param[in, out] key
7002 * Flow matcher value.
7004 * Flow pattern to translate.
7006 * Item is inner pattern.
7009 flow_dv_translate_item_nvgre(void *matcher, void *key,
7010 const struct rte_flow_item *item,
7013 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7014 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7015 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7016 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7017 const char *tni_flow_id_m;
7018 const char *tni_flow_id_v;
7024 /* For NVGRE, GRE header fields must be set with defined values. */
7025 const struct rte_flow_item_gre gre_spec = {
7026 .c_rsvd0_ver = RTE_BE16(0x2000),
7027 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7029 const struct rte_flow_item_gre gre_mask = {
7030 .c_rsvd0_ver = RTE_BE16(0xB000),
7031 .protocol = RTE_BE16(UINT16_MAX),
7033 const struct rte_flow_item gre_item = {
7038 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7042 nvgre_m = &rte_flow_item_nvgre_mask;
7043 tni_flow_id_m = (const char *)nvgre_m->tni;
7044 tni_flow_id_v = (const char *)nvgre_v->tni;
7045 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7046 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7047 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7048 memcpy(gre_key_m, tni_flow_id_m, size);
7049 for (i = 0; i < size; ++i)
7050 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7054 * Add VXLAN item to matcher and to the value.
7056 * @param[in, out] matcher
7058 * @param[in, out] key
7059 * Flow matcher value.
7061 * Flow pattern to translate.
7063 * Item is inner pattern.
7066 flow_dv_translate_item_vxlan(void *matcher, void *key,
7067 const struct rte_flow_item *item,
7070 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7071 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7074 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7075 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7083 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7085 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7087 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7089 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7091 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7092 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7093 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7094 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7095 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7100 vxlan_m = &rte_flow_item_vxlan_mask;
7101 size = sizeof(vxlan_m->vni);
7102 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7103 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7104 memcpy(vni_m, vxlan_m->vni, size);
7105 for (i = 0; i < size; ++i)
7106 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7110 * Add VXLAN-GPE item to matcher and to the value.
7112 * @param[in, out] matcher
7114 * @param[in, out] key
7115 * Flow matcher value.
7117 * Flow pattern to translate.
7119 * Item is inner pattern.
7123 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7124 const struct rte_flow_item *item, int inner)
7126 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7127 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7131 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7133 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7139 uint8_t flags_m = 0xff;
7140 uint8_t flags_v = 0xc;
7143 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7145 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7147 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7149 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7151 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7152 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7153 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7154 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7155 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7160 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7161 size = sizeof(vxlan_m->vni);
7162 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7163 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7164 memcpy(vni_m, vxlan_m->vni, size);
7165 for (i = 0; i < size; ++i)
7166 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7167 if (vxlan_m->flags) {
7168 flags_m = vxlan_m->flags;
7169 flags_v = vxlan_v->flags;
7171 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7172 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7173 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7175 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7180 * Add Geneve item to matcher and to the value.
7182 * @param[in, out] matcher
7184 * @param[in, out] key
7185 * Flow matcher value.
7187 * Flow pattern to translate.
7189 * Item is inner pattern.
7193 flow_dv_translate_item_geneve(void *matcher, void *key,
7194 const struct rte_flow_item *item, int inner)
7196 const struct rte_flow_item_geneve *geneve_m = item->mask;
7197 const struct rte_flow_item_geneve *geneve_v = item->spec;
7200 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7201 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7210 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7212 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7214 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7216 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7218 dport = MLX5_UDP_PORT_GENEVE;
7219 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7220 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7221 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7226 geneve_m = &rte_flow_item_geneve_mask;
7227 size = sizeof(geneve_m->vni);
7228 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7229 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7230 memcpy(vni_m, geneve_m->vni, size);
7231 for (i = 0; i < size; ++i)
7232 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7233 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7234 rte_be_to_cpu_16(geneve_m->protocol));
7235 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7236 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7237 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7238 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7239 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7240 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7241 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7242 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7243 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7244 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7245 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7246 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7247 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7251 * Add MPLS item to matcher and to the value.
7253 * @param[in, out] matcher
7255 * @param[in, out] key
7256 * Flow matcher value.
7258 * Flow pattern to translate.
7259 * @param[in] prev_layer
7260 * The protocol layer indicated in previous item.
7262 * Item is inner pattern.
7265 flow_dv_translate_item_mpls(void *matcher, void *key,
7266 const struct rte_flow_item *item,
7267 uint64_t prev_layer,
7270 const uint32_t *in_mpls_m = item->mask;
7271 const uint32_t *in_mpls_v = item->spec;
7272 uint32_t *out_mpls_m = 0;
7273 uint32_t *out_mpls_v = 0;
7274 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7275 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7276 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7278 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7279 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7280 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7282 switch (prev_layer) {
7283 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7284 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7285 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7286 MLX5_UDP_PORT_MPLS);
7288 case MLX5_FLOW_LAYER_GRE:
7289 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7290 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7291 RTE_ETHER_TYPE_MPLS);
7294 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7295 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7302 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7303 switch (prev_layer) {
7304 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7306 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7307 outer_first_mpls_over_udp);
7309 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7310 outer_first_mpls_over_udp);
7312 case MLX5_FLOW_LAYER_GRE:
7314 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7315 outer_first_mpls_over_gre);
7317 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7318 outer_first_mpls_over_gre);
7321 /* Inner MPLS not over GRE is not supported. */
7324 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7328 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7334 if (out_mpls_m && out_mpls_v) {
7335 *out_mpls_m = *in_mpls_m;
7336 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7341 * Add metadata register item to matcher
7343 * @param[in, out] matcher
7345 * @param[in, out] key
7346 * Flow matcher value.
7347 * @param[in] reg_type
7348 * Type of device metadata register
7355 flow_dv_match_meta_reg(void *matcher, void *key,
7356 enum modify_reg reg_type,
7357 uint32_t data, uint32_t mask)
7360 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7362 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7368 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7369 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7372 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7373 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7377 * The metadata register C0 field might be divided into
7378 * source vport index and META item value, we should set
7379 * this field according to specified mask, not as whole one.
7381 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7383 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7384 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7387 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7390 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7391 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7394 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7395 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7398 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7399 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7402 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7403 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7406 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7407 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7410 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7411 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7414 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7415 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7424 * Add MARK item to matcher
7427 * The device to configure through.
7428 * @param[in, out] matcher
7430 * @param[in, out] key
7431 * Flow matcher value.
7433 * Flow pattern to translate.
7436 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7437 void *matcher, void *key,
7438 const struct rte_flow_item *item)
7440 struct mlx5_priv *priv = dev->data->dev_private;
7441 const struct rte_flow_item_mark *mark;
7445 mark = item->mask ? (const void *)item->mask :
7446 &rte_flow_item_mark_mask;
7447 mask = mark->id & priv->sh->dv_mark_mask;
7448 mark = (const void *)item->spec;
7450 value = mark->id & priv->sh->dv_mark_mask & mask;
7452 enum modify_reg reg;
7454 /* Get the metadata register index for the mark. */
7455 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7456 MLX5_ASSERT(reg > 0);
7457 if (reg == REG_C_0) {
7458 struct mlx5_priv *priv = dev->data->dev_private;
7459 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7460 uint32_t shl_c0 = rte_bsf32(msk_c0);
7466 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7471 * Add META item to matcher
7474 * The devich to configure through.
7475 * @param[in, out] matcher
7477 * @param[in, out] key
7478 * Flow matcher value.
7480 * Attributes of flow that includes this item.
7482 * Flow pattern to translate.
7485 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7486 void *matcher, void *key,
7487 const struct rte_flow_attr *attr,
7488 const struct rte_flow_item *item)
7490 const struct rte_flow_item_meta *meta_m;
7491 const struct rte_flow_item_meta *meta_v;
7493 meta_m = (const void *)item->mask;
7495 meta_m = &rte_flow_item_meta_mask;
7496 meta_v = (const void *)item->spec;
7499 uint32_t value = meta_v->data;
7500 uint32_t mask = meta_m->data;
7502 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7506 * In datapath code there is no endianness
7507 * coversions for perfromance reasons, all
7508 * pattern conversions are done in rte_flow.
7510 value = rte_cpu_to_be_32(value);
7511 mask = rte_cpu_to_be_32(mask);
7512 if (reg == REG_C_0) {
7513 struct mlx5_priv *priv = dev->data->dev_private;
7514 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7515 uint32_t shl_c0 = rte_bsf32(msk_c0);
7516 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7517 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7524 MLX5_ASSERT(msk_c0);
7525 MLX5_ASSERT(!(~msk_c0 & mask));
7527 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7532 * Add vport metadata Reg C0 item to matcher
7534 * @param[in, out] matcher
7536 * @param[in, out] key
7537 * Flow matcher value.
7539 * Flow pattern to translate.
7542 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7543 uint32_t value, uint32_t mask)
7545 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7549 * Add tag item to matcher
7552 * The devich to configure through.
7553 * @param[in, out] matcher
7555 * @param[in, out] key
7556 * Flow matcher value.
7558 * Flow pattern to translate.
7561 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7562 void *matcher, void *key,
7563 const struct rte_flow_item *item)
7565 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7566 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7567 uint32_t mask, value;
7570 value = tag_v->data;
7571 mask = tag_m ? tag_m->data : UINT32_MAX;
7572 if (tag_v->id == REG_C_0) {
7573 struct mlx5_priv *priv = dev->data->dev_private;
7574 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7575 uint32_t shl_c0 = rte_bsf32(msk_c0);
7581 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7585 * Add TAG item to matcher
7588 * The devich to configure through.
7589 * @param[in, out] matcher
7591 * @param[in, out] key
7592 * Flow matcher value.
7594 * Flow pattern to translate.
7597 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7598 void *matcher, void *key,
7599 const struct rte_flow_item *item)
7601 const struct rte_flow_item_tag *tag_v = item->spec;
7602 const struct rte_flow_item_tag *tag_m = item->mask;
7603 enum modify_reg reg;
7606 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7607 /* Get the metadata register index for the tag. */
7608 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7609 MLX5_ASSERT(reg > 0);
7610 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7614 * Add source vport match to the specified matcher.
7616 * @param[in, out] matcher
7618 * @param[in, out] key
7619 * Flow matcher value.
7621 * Source vport value to match
7626 flow_dv_translate_item_source_vport(void *matcher, void *key,
7627 int16_t port, uint16_t mask)
7629 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7630 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7632 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7633 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7637 * Translate port-id item to eswitch match on port-id.
7640 * The devich to configure through.
7641 * @param[in, out] matcher
7643 * @param[in, out] key
7644 * Flow matcher value.
7646 * Flow pattern to translate.
7649 * 0 on success, a negative errno value otherwise.
7652 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7653 void *key, const struct rte_flow_item *item)
7655 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7656 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7657 struct mlx5_priv *priv;
7660 mask = pid_m ? pid_m->id : 0xffff;
7661 id = pid_v ? pid_v->id : dev->data->port_id;
7662 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7665 /* Translate to vport field or to metadata, depending on mode. */
7666 if (priv->vport_meta_mask)
7667 flow_dv_translate_item_meta_vport(matcher, key,
7668 priv->vport_meta_tag,
7669 priv->vport_meta_mask);
7671 flow_dv_translate_item_source_vport(matcher, key,
7672 priv->vport_id, mask);
7677 * Add ICMP6 item to matcher and to the value.
7679 * @param[in, out] matcher
7681 * @param[in, out] key
7682 * Flow matcher value.
7684 * Flow pattern to translate.
7686 * Item is inner pattern.
7689 flow_dv_translate_item_icmp6(void *matcher, void *key,
7690 const struct rte_flow_item *item,
7693 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7694 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7697 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7699 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7701 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7703 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7705 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7707 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7709 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7710 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7714 icmp6_m = &rte_flow_item_icmp6_mask;
7715 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7716 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7717 icmp6_v->type & icmp6_m->type);
7718 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7719 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7720 icmp6_v->code & icmp6_m->code);
7724 * Add ICMP item to matcher and to the value.
7726 * @param[in, out] matcher
7728 * @param[in, out] key
7729 * Flow matcher value.
7731 * Flow pattern to translate.
7733 * Item is inner pattern.
7736 flow_dv_translate_item_icmp(void *matcher, void *key,
7737 const struct rte_flow_item *item,
7740 const struct rte_flow_item_icmp *icmp_m = item->mask;
7741 const struct rte_flow_item_icmp *icmp_v = item->spec;
7742 uint32_t icmp_header_data_m = 0;
7743 uint32_t icmp_header_data_v = 0;
7746 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7748 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7750 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7752 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7754 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7756 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7758 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7759 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7763 icmp_m = &rte_flow_item_icmp_mask;
7764 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7765 icmp_m->hdr.icmp_type);
7766 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7767 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7768 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7769 icmp_m->hdr.icmp_code);
7770 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7771 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7772 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7773 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7774 if (icmp_header_data_m) {
7775 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7776 icmp_header_data_v |=
7777 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7778 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7779 icmp_header_data_m);
7780 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7781 icmp_header_data_v & icmp_header_data_m);
7786 * Add GTP item to matcher and to the value.
7788 * @param[in, out] matcher
7790 * @param[in, out] key
7791 * Flow matcher value.
7793 * Flow pattern to translate.
7795 * Item is inner pattern.
7798 flow_dv_translate_item_gtp(void *matcher, void *key,
7799 const struct rte_flow_item *item, int inner)
7801 const struct rte_flow_item_gtp *gtp_m = item->mask;
7802 const struct rte_flow_item_gtp *gtp_v = item->spec;
7805 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7807 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7808 uint16_t dport = RTE_GTPU_UDP_PORT;
7811 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7813 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7815 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7817 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7819 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7820 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7821 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7826 gtp_m = &rte_flow_item_gtp_mask;
7827 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7828 gtp_m->v_pt_rsv_flags);
7829 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7830 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7831 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7832 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7833 gtp_v->msg_type & gtp_m->msg_type);
7834 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7835 rte_be_to_cpu_32(gtp_m->teid));
7836 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7837 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7841 * Add eCPRI item to matcher and to the value.
7844 * The devich to configure through.
7845 * @param[in, out] matcher
7847 * @param[in, out] key
7848 * Flow matcher value.
7850 * Flow pattern to translate.
7851 * @param[in] samples
7852 * Sample IDs to be used in the matching.
7855 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7856 void *key, const struct rte_flow_item *item)
7858 struct mlx5_priv *priv = dev->data->dev_private;
7859 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7860 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7861 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7863 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7871 ecpri_m = &rte_flow_item_ecpri_mask;
7873 * Maximal four DW samples are supported in a single matching now.
7874 * Two are used now for a eCPRI matching:
7875 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7876 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7879 if (!ecpri_m->hdr.common.u32)
7881 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7882 /* Need to take the whole DW as the mask to fill the entry. */
7883 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7884 prog_sample_field_value_0);
7885 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7886 prog_sample_field_value_0);
7887 /* Already big endian (network order) in the header. */
7888 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7889 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7890 /* Sample#0, used for matching type, offset 0. */
7891 MLX5_SET(fte_match_set_misc4, misc4_m,
7892 prog_sample_field_id_0, samples[0]);
7893 /* It makes no sense to set the sample ID in the mask field. */
7894 MLX5_SET(fte_match_set_misc4, misc4_v,
7895 prog_sample_field_id_0, samples[0]);
7897 * Checking if message body part needs to be matched.
7898 * Some wildcard rules only matching type field should be supported.
7900 if (ecpri_m->hdr.dummy[0]) {
7901 switch (ecpri_v->hdr.common.type) {
7902 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7903 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7904 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7905 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7906 prog_sample_field_value_1);
7907 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7908 prog_sample_field_value_1);
7909 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7910 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7911 /* Sample#1, to match message body, offset 4. */
7912 MLX5_SET(fte_match_set_misc4, misc4_m,
7913 prog_sample_field_id_1, samples[1]);
7914 MLX5_SET(fte_match_set_misc4, misc4_v,
7915 prog_sample_field_id_1, samples[1]);
7918 /* Others, do not match any sample ID. */
7924 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7926 #define HEADER_IS_ZERO(match_criteria, headers) \
7927 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7928 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7931 * Calculate flow matcher enable bitmap.
7933 * @param match_criteria
7934 * Pointer to flow matcher criteria.
7937 * Bitmap of enabled fields.
7940 flow_dv_matcher_enable(uint32_t *match_criteria)
7942 uint8_t match_criteria_enable;
7944 match_criteria_enable =
7945 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7946 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7947 match_criteria_enable |=
7948 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7949 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7950 match_criteria_enable |=
7951 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7952 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7953 match_criteria_enable |=
7954 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7955 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7956 match_criteria_enable |=
7957 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7958 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7959 match_criteria_enable |=
7960 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7961 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7962 return match_criteria_enable;
7969 * @param[in, out] dev
7970 * Pointer to rte_eth_dev structure.
7971 * @param[in] table_id
7974 * Direction of the table.
7975 * @param[in] transfer
7976 * E-Switch or NIC flow.
7978 * pointer to error structure.
7981 * Returns tables resource based on the index, NULL in case of failed.
7983 static struct mlx5_flow_tbl_resource *
7984 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7985 uint32_t table_id, uint8_t egress,
7988 const struct mlx5_flow_tunnel *tunnel,
7990 struct rte_flow_error *error)
7992 struct mlx5_priv *priv = dev->data->dev_private;
7993 struct mlx5_dev_ctx_shared *sh = priv->sh;
7994 struct mlx5_flow_tbl_resource *tbl;
7995 union mlx5_flow_tbl_key table_key = {
7997 .table_id = table_id,
7999 .domain = !!transfer,
8000 .direction = !!egress,
8003 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
8005 struct mlx5_flow_tbl_data_entry *tbl_data;
8011 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
8013 tbl = &tbl_data->tbl;
8014 rte_atomic32_inc(&tbl->refcnt);
8017 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8019 rte_flow_error_set(error, ENOMEM,
8020 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8022 "cannot allocate flow table data entry");
8025 tbl_data->idx = idx;
8026 tbl_data->tunnel = tunnel;
8027 tbl_data->group_id = group_id;
8028 tbl_data->external = external;
8029 tbl = &tbl_data->tbl;
8030 pos = &tbl_data->entry;
8032 domain = sh->fdb_domain;
8034 domain = sh->tx_domain;
8036 domain = sh->rx_domain;
8037 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
8039 rte_flow_error_set(error, ENOMEM,
8040 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8041 NULL, "cannot create flow table object");
8042 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8046 * No multi-threads now, but still better to initialize the reference
8047 * count before insert it into the hash list.
8049 rte_atomic32_init(&tbl->refcnt);
8050 /* Jump action reference count is initialized here. */
8051 rte_atomic32_init(&tbl_data->jump.refcnt);
8052 pos->key = table_key.v64;
8053 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
8055 rte_flow_error_set(error, -ret,
8056 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8057 "cannot insert flow table data entry");
8058 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8059 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8061 rte_atomic32_inc(&tbl->refcnt);
8066 * Release a flow table.
8069 * Pointer to rte_eth_dev structure.
8071 * Table resource to be released.
8074 * Returns 0 if table was released, else return 1;
8077 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
8078 struct mlx5_flow_tbl_resource *tbl)
8080 struct mlx5_priv *priv = dev->data->dev_private;
8081 struct mlx5_dev_ctx_shared *sh = priv->sh;
8082 struct mlx5_flow_tbl_data_entry *tbl_data =
8083 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8087 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
8088 struct mlx5_hlist_entry *pos = &tbl_data->entry;
8090 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8092 if (is_tunnel_offload_active(dev) && tbl_data->external) {
8093 struct mlx5_hlist_entry *he;
8094 struct mlx5_hlist *tunnel_grp_hash;
8095 struct mlx5_flow_tunnel_hub *thub =
8096 mlx5_tunnel_hub(dev);
8097 union tunnel_tbl_key tunnel_key = {
8098 .tunnel_id = tbl_data->tunnel ?
8099 tbl_data->tunnel->tunnel_id : 0,
8100 .group = tbl_data->group_id
8102 union mlx5_flow_tbl_key table_key = {
8105 uint32_t table_id = table_key.table_id;
8107 tunnel_grp_hash = tbl_data->tunnel ?
8108 tbl_data->tunnel->groups :
8110 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val);
8112 struct tunnel_tbl_entry *tte;
8113 tte = container_of(he, typeof(*tte), hash);
8114 MLX5_ASSERT(tte->flow_table == table_id);
8115 mlx5_hlist_remove(tunnel_grp_hash, he);
8118 mlx5_flow_id_release(mlx5_tunnel_hub(dev)->table_ids,
8119 tunnel_flow_tbl_to_id(table_id));
8121 "port %u release table_id %#x tunnel %u group %u",
8122 dev->data->port_id, table_id,
8124 tbl_data->tunnel->tunnel_id : 0,
8125 tbl_data->group_id);
8127 /* remove the entry from the hash list and free memory. */
8128 mlx5_hlist_remove(sh->flow_tbls, pos);
8129 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
8137 * Register the flow matcher.
8139 * @param[in, out] dev
8140 * Pointer to rte_eth_dev structure.
8141 * @param[in, out] matcher
8142 * Pointer to flow matcher.
8143 * @param[in, out] key
8144 * Pointer to flow table key.
8145 * @parm[in, out] dev_flow
8146 * Pointer to the dev_flow.
8148 * pointer to error structure.
8151 * 0 on success otherwise -errno and errno is set.
8154 flow_dv_matcher_register(struct rte_eth_dev *dev,
8155 struct mlx5_flow_dv_matcher *matcher,
8156 union mlx5_flow_tbl_key *key,
8157 struct mlx5_flow *dev_flow,
8158 struct rte_flow_error *error)
8160 struct mlx5_priv *priv = dev->data->dev_private;
8161 struct mlx5_dev_ctx_shared *sh = priv->sh;
8162 struct mlx5_flow_dv_matcher *cache_matcher;
8163 struct mlx5dv_flow_matcher_attr dv_attr = {
8164 .type = IBV_FLOW_ATTR_NORMAL,
8165 .match_mask = (void *)&matcher->mask,
8167 struct mlx5_flow_tbl_resource *tbl;
8168 struct mlx5_flow_tbl_data_entry *tbl_data;
8171 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
8172 key->domain, false, NULL, 0, error);
8174 return -rte_errno; /* No need to refill the error info */
8175 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8176 /* Lookup from cache. */
8177 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
8178 if (matcher->crc == cache_matcher->crc &&
8179 matcher->priority == cache_matcher->priority &&
8180 !memcmp((const void *)matcher->mask.buf,
8181 (const void *)cache_matcher->mask.buf,
8182 cache_matcher->mask.size)) {
8184 "%s group %u priority %hd use %s "
8185 "matcher %p: refcnt %d++",
8186 key->domain ? "FDB" : "NIC", key->table_id,
8187 cache_matcher->priority,
8188 key->direction ? "tx" : "rx",
8189 (void *)cache_matcher,
8190 rte_atomic32_read(&cache_matcher->refcnt));
8191 rte_atomic32_inc(&cache_matcher->refcnt);
8192 dev_flow->handle->dvh.matcher = cache_matcher;
8193 /* old matcher should not make the table ref++. */
8194 flow_dv_tbl_resource_release(dev, tbl);
8198 /* Register new matcher. */
8199 cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
8201 if (!cache_matcher) {
8202 flow_dv_tbl_resource_release(dev, tbl);
8203 return rte_flow_error_set(error, ENOMEM,
8204 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8205 "cannot allocate matcher memory");
8207 *cache_matcher = *matcher;
8208 dv_attr.match_criteria_enable =
8209 flow_dv_matcher_enable(cache_matcher->mask.buf);
8210 dv_attr.priority = matcher->priority;
8212 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8213 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
8214 &cache_matcher->matcher_object);
8216 mlx5_free(cache_matcher);
8217 #ifdef HAVE_MLX5DV_DR
8218 flow_dv_tbl_resource_release(dev, tbl);
8220 return rte_flow_error_set(error, ENOMEM,
8221 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8222 NULL, "cannot create matcher");
8224 /* Save the table information */
8225 cache_matcher->tbl = tbl;
8226 rte_atomic32_init(&cache_matcher->refcnt);
8227 /* only matcher ref++, table ref++ already done above in get API. */
8228 rte_atomic32_inc(&cache_matcher->refcnt);
8229 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
8230 dev_flow->handle->dvh.matcher = cache_matcher;
8231 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
8232 key->domain ? "FDB" : "NIC", key->table_id,
8233 cache_matcher->priority,
8234 key->direction ? "tx" : "rx", (void *)cache_matcher,
8235 rte_atomic32_read(&cache_matcher->refcnt));
8240 * Find existing tag resource or create and register a new one.
8242 * @param dev[in, out]
8243 * Pointer to rte_eth_dev structure.
8244 * @param[in, out] tag_be24
8245 * Tag value in big endian then R-shift 8.
8246 * @parm[in, out] dev_flow
8247 * Pointer to the dev_flow.
8249 * pointer to error structure.
8252 * 0 on success otherwise -errno and errno is set.
8255 flow_dv_tag_resource_register
8256 (struct rte_eth_dev *dev,
8258 struct mlx5_flow *dev_flow,
8259 struct rte_flow_error *error)
8261 struct mlx5_priv *priv = dev->data->dev_private;
8262 struct mlx5_dev_ctx_shared *sh = priv->sh;
8263 struct mlx5_flow_dv_tag_resource *cache_resource;
8264 struct mlx5_hlist_entry *entry;
8267 /* Lookup a matching resource from cache. */
8268 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
8270 cache_resource = container_of
8271 (entry, struct mlx5_flow_dv_tag_resource, entry);
8272 rte_atomic32_inc(&cache_resource->refcnt);
8273 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8274 dev_flow->dv.tag_resource = cache_resource;
8275 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8276 (void *)cache_resource,
8277 rte_atomic32_read(&cache_resource->refcnt));
8280 /* Register new resource. */
8281 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8282 &dev_flow->handle->dvh.rix_tag);
8283 if (!cache_resource)
8284 return rte_flow_error_set(error, ENOMEM,
8285 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8286 "cannot allocate resource memory");
8287 cache_resource->entry.key = (uint64_t)tag_be24;
8288 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8289 &cache_resource->action);
8291 mlx5_free(cache_resource);
8292 return rte_flow_error_set(error, ENOMEM,
8293 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8294 NULL, "cannot create action");
8296 rte_atomic32_init(&cache_resource->refcnt);
8297 rte_atomic32_inc(&cache_resource->refcnt);
8298 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8299 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8300 mlx5_free(cache_resource);
8301 return rte_flow_error_set(error, EEXIST,
8302 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8303 NULL, "cannot insert tag");
8305 dev_flow->dv.tag_resource = cache_resource;
8306 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8307 (void *)cache_resource,
8308 rte_atomic32_read(&cache_resource->refcnt));
8316 * Pointer to Ethernet device.
8321 * 1 while a reference on it exists, 0 when freed.
8324 flow_dv_tag_release(struct rte_eth_dev *dev,
8327 struct mlx5_priv *priv = dev->data->dev_private;
8328 struct mlx5_dev_ctx_shared *sh = priv->sh;
8329 struct mlx5_flow_dv_tag_resource *tag;
8331 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8334 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8335 dev->data->port_id, (void *)tag,
8336 rte_atomic32_read(&tag->refcnt));
8337 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
8338 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8339 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8340 DRV_LOG(DEBUG, "port %u tag %p: removed",
8341 dev->data->port_id, (void *)tag);
8342 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8349 * Translate port ID action to vport.
8352 * Pointer to rte_eth_dev structure.
8354 * Pointer to the port ID action.
8355 * @param[out] dst_port_id
8356 * The target port ID.
8358 * Pointer to the error structure.
8361 * 0 on success, a negative errno value otherwise and rte_errno is set.
8364 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8365 const struct rte_flow_action *action,
8366 uint32_t *dst_port_id,
8367 struct rte_flow_error *error)
8370 struct mlx5_priv *priv;
8371 const struct rte_flow_action_port_id *conf =
8372 (const struct rte_flow_action_port_id *)action->conf;
8374 port = conf->original ? dev->data->port_id : conf->id;
8375 priv = mlx5_port_to_eswitch_info(port, false);
8377 return rte_flow_error_set(error, -rte_errno,
8378 RTE_FLOW_ERROR_TYPE_ACTION,
8380 "No eswitch info was found for port");
8381 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8383 * This parameter is transferred to
8384 * mlx5dv_dr_action_create_dest_ib_port().
8386 *dst_port_id = priv->dev_port;
8389 * Legacy mode, no LAG configurations is supported.
8390 * This parameter is transferred to
8391 * mlx5dv_dr_action_create_dest_vport().
8393 *dst_port_id = priv->vport_id;
8399 * Create a counter with aging configuration.
8402 * Pointer to rte_eth_dev structure.
8404 * Pointer to the counter action configuration.
8406 * Pointer to the aging action configuration.
8409 * Index to flow counter on success, 0 otherwise.
8412 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8413 struct mlx5_flow *dev_flow,
8414 const struct rte_flow_action_count *count,
8415 const struct rte_flow_action_age *age)
8418 struct mlx5_age_param *age_param;
8420 if (count && count->shared)
8421 counter = flow_dv_counter_get_shared(dev, count->id);
8423 counter = flow_dv_counter_alloc(dev, !!age);
8424 if (!counter || age == NULL)
8426 age_param = flow_dv_counter_idx_get_age(dev, counter);
8427 age_param->context = age->context ? age->context :
8428 (void *)(uintptr_t)(dev_flow->flow_idx);
8429 age_param->timeout = age->timeout;
8430 age_param->port_id = dev->data->port_id;
8431 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8432 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8436 * Add Tx queue matcher
8439 * Pointer to the dev struct.
8440 * @param[in, out] matcher
8442 * @param[in, out] key
8443 * Flow matcher value.
8445 * Flow pattern to translate.
8447 * Item is inner pattern.
8450 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8451 void *matcher, void *key,
8452 const struct rte_flow_item *item)
8454 const struct mlx5_rte_flow_item_tx_queue *queue_m;
8455 const struct mlx5_rte_flow_item_tx_queue *queue_v;
8457 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8459 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8460 struct mlx5_txq_ctrl *txq;
8464 queue_m = (const void *)item->mask;
8467 queue_v = (const void *)item->spec;
8470 txq = mlx5_txq_get(dev, queue_v->queue);
8473 queue = txq->obj->sq->id;
8474 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8475 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8476 queue & queue_m->queue);
8477 mlx5_txq_release(dev, queue_v->queue);
8481 * Set the hash fields according to the @p flow information.
8483 * @param[in] dev_flow
8484 * Pointer to the mlx5_flow.
8485 * @param[in] rss_desc
8486 * Pointer to the mlx5_flow_rss_desc.
8489 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8490 struct mlx5_flow_rss_desc *rss_desc)
8492 uint64_t items = dev_flow->handle->layers;
8494 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8496 dev_flow->hash_fields = 0;
8497 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8498 if (rss_desc->level >= 2) {
8499 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8503 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8504 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8505 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8506 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8507 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8508 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8509 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8511 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8513 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8514 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8515 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8516 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8517 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8518 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8519 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8521 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8524 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8525 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8526 if (rss_types & ETH_RSS_UDP) {
8527 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8528 dev_flow->hash_fields |=
8529 IBV_RX_HASH_SRC_PORT_UDP;
8530 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8531 dev_flow->hash_fields |=
8532 IBV_RX_HASH_DST_PORT_UDP;
8534 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8536 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8537 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8538 if (rss_types & ETH_RSS_TCP) {
8539 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8540 dev_flow->hash_fields |=
8541 IBV_RX_HASH_SRC_PORT_TCP;
8542 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8543 dev_flow->hash_fields |=
8544 IBV_RX_HASH_DST_PORT_TCP;
8546 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8552 * Create an Rx Hash queue.
8555 * Pointer to Ethernet device.
8556 * @param[in] dev_flow
8557 * Pointer to the mlx5_flow.
8558 * @param[in] rss_desc
8559 * Pointer to the mlx5_flow_rss_desc.
8560 * @param[out] hrxq_idx
8561 * Hash Rx queue index.
8564 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8566 static struct mlx5_hrxq *
8567 flow_dv_handle_rx_queue(struct rte_eth_dev *dev,
8568 struct mlx5_flow *dev_flow,
8569 struct mlx5_flow_rss_desc *rss_desc,
8572 struct mlx5_priv *priv = dev->data->dev_private;
8573 struct mlx5_flow_handle *dh = dev_flow->handle;
8574 struct mlx5_hrxq *hrxq;
8576 MLX5_ASSERT(rss_desc->queue_num);
8577 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8578 dev_flow->hash_fields,
8579 rss_desc->queue, rss_desc->queue_num);
8581 *hrxq_idx = mlx5_hrxq_new
8582 (dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8583 dev_flow->hash_fields,
8584 rss_desc->queue, rss_desc->queue_num,
8585 !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL),
8590 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8596 * Find existing sample resource or create and register a new one.
8598 * @param[in, out] dev
8599 * Pointer to rte_eth_dev structure.
8601 * Attributes of flow that includes this item.
8602 * @param[in] resource
8603 * Pointer to sample resource.
8604 * @parm[in, out] dev_flow
8605 * Pointer to the dev_flow.
8606 * @param[in, out] sample_dv_actions
8607 * Pointer to sample actions list.
8609 * pointer to error structure.
8612 * 0 on success otherwise -errno and errno is set.
8615 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8616 const struct rte_flow_attr *attr,
8617 struct mlx5_flow_dv_sample_resource *resource,
8618 struct mlx5_flow *dev_flow,
8619 void **sample_dv_actions,
8620 struct rte_flow_error *error)
8622 struct mlx5_flow_dv_sample_resource *cache_resource;
8623 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8624 struct mlx5_priv *priv = dev->data->dev_private;
8625 struct mlx5_dev_ctx_shared *sh = priv->sh;
8626 struct mlx5_flow_tbl_resource *tbl;
8628 const uint32_t next_ft_step = 1;
8629 uint32_t next_ft_id = resource->ft_id + next_ft_step;
8631 /* Lookup a matching resource from cache. */
8632 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8633 idx, cache_resource, next) {
8634 if (resource->ratio == cache_resource->ratio &&
8635 resource->ft_type == cache_resource->ft_type &&
8636 resource->ft_id == cache_resource->ft_id &&
8637 resource->set_action == cache_resource->set_action &&
8638 !memcmp((void *)&resource->sample_act,
8639 (void *)&cache_resource->sample_act,
8640 sizeof(struct mlx5_flow_sub_actions_list))) {
8641 DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8642 (void *)cache_resource,
8643 __atomic_load_n(&cache_resource->refcnt,
8645 __atomic_fetch_add(&cache_resource->refcnt, 1,
8647 dev_flow->handle->dvh.rix_sample = idx;
8648 dev_flow->dv.sample_res = cache_resource;
8652 /* Register new sample resource. */
8653 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8654 &dev_flow->handle->dvh.rix_sample);
8655 if (!cache_resource)
8656 return rte_flow_error_set(error, ENOMEM,
8657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8659 "cannot allocate resource memory");
8660 *cache_resource = *resource;
8661 /* Create normal path table level */
8662 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8663 attr->egress, attr->transfer,
8664 dev_flow->external, NULL, 0, error);
8666 rte_flow_error_set(error, ENOMEM,
8667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8669 "fail to create normal path table "
8673 cache_resource->normal_path_tbl = tbl;
8674 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8675 cache_resource->default_miss =
8676 mlx5_glue->dr_create_flow_action_default_miss();
8677 if (!cache_resource->default_miss) {
8678 rte_flow_error_set(error, ENOMEM,
8679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8681 "cannot create default miss "
8685 sample_dv_actions[resource->sample_act.actions_num++] =
8686 cache_resource->default_miss;
8688 /* Create a DR sample action */
8689 sampler_attr.sample_ratio = cache_resource->ratio;
8690 sampler_attr.default_next_table = tbl->obj;
8691 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8692 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8693 &sample_dv_actions[0];
8694 sampler_attr.action = cache_resource->set_action;
8695 cache_resource->verbs_action =
8696 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8697 if (!cache_resource->verbs_action) {
8698 rte_flow_error_set(error, ENOMEM,
8699 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8700 NULL, "cannot create sample action");
8703 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8704 ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8705 dev_flow->handle->dvh.rix_sample, cache_resource,
8707 dev_flow->dv.sample_res = cache_resource;
8708 DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8709 (void *)cache_resource,
8710 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8713 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8714 if (cache_resource->default_miss)
8715 claim_zero(mlx5_glue->destroy_flow_action
8716 (cache_resource->default_miss));
8718 if (cache_resource->sample_idx.rix_hrxq &&
8719 !mlx5_hrxq_release(dev,
8720 cache_resource->sample_idx.rix_hrxq))
8721 cache_resource->sample_idx.rix_hrxq = 0;
8722 if (cache_resource->sample_idx.rix_tag &&
8723 !flow_dv_tag_release(dev,
8724 cache_resource->sample_idx.rix_tag))
8725 cache_resource->sample_idx.rix_tag = 0;
8726 if (cache_resource->sample_idx.cnt) {
8727 flow_dv_counter_release(dev,
8728 cache_resource->sample_idx.cnt);
8729 cache_resource->sample_idx.cnt = 0;
8732 if (cache_resource->normal_path_tbl)
8733 flow_dv_tbl_resource_release(dev,
8734 cache_resource->normal_path_tbl);
8735 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8736 dev_flow->handle->dvh.rix_sample);
8737 dev_flow->handle->dvh.rix_sample = 0;
8742 * Find existing destination array resource or create and register a new one.
8744 * @param[in, out] dev
8745 * Pointer to rte_eth_dev structure.
8747 * Attributes of flow that includes this item.
8748 * @param[in] resource
8749 * Pointer to destination array resource.
8750 * @parm[in, out] dev_flow
8751 * Pointer to the dev_flow.
8753 * pointer to error structure.
8756 * 0 on success otherwise -errno and errno is set.
8759 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8760 const struct rte_flow_attr *attr,
8761 struct mlx5_flow_dv_dest_array_resource *resource,
8762 struct mlx5_flow *dev_flow,
8763 struct rte_flow_error *error)
8765 struct mlx5_flow_dv_dest_array_resource *cache_resource;
8766 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8767 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8768 struct mlx5_priv *priv = dev->data->dev_private;
8769 struct mlx5_dev_ctx_shared *sh = priv->sh;
8770 struct mlx5_flow_sub_actions_list *sample_act;
8771 struct mlx5dv_dr_domain *domain;
8774 /* Lookup a matching resource from cache. */
8775 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8776 sh->dest_array_list,
8777 idx, cache_resource, next) {
8778 if (resource->num_of_dest == cache_resource->num_of_dest &&
8779 resource->ft_type == cache_resource->ft_type &&
8780 !memcmp((void *)cache_resource->sample_act,
8781 (void *)resource->sample_act,
8782 (resource->num_of_dest *
8783 sizeof(struct mlx5_flow_sub_actions_list)))) {
8784 DRV_LOG(DEBUG, "dest array resource %p: refcnt %d++",
8785 (void *)cache_resource,
8786 __atomic_load_n(&cache_resource->refcnt,
8788 __atomic_fetch_add(&cache_resource->refcnt, 1,
8790 dev_flow->handle->dvh.rix_dest_array = idx;
8791 dev_flow->dv.dest_array_res = cache_resource;
8795 /* Register new destination array resource. */
8796 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8797 &dev_flow->handle->dvh.rix_dest_array);
8798 if (!cache_resource)
8799 return rte_flow_error_set(error, ENOMEM,
8800 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8802 "cannot allocate resource memory");
8803 *cache_resource = *resource;
8805 domain = sh->fdb_domain;
8806 else if (attr->ingress)
8807 domain = sh->rx_domain;
8809 domain = sh->tx_domain;
8810 for (idx = 0; idx < resource->num_of_dest; idx++) {
8811 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8812 mlx5_malloc(MLX5_MEM_ZERO,
8813 sizeof(struct mlx5dv_dr_action_dest_attr),
8815 if (!dest_attr[idx]) {
8816 rte_flow_error_set(error, ENOMEM,
8817 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8819 "cannot allocate resource memory");
8822 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8823 sample_act = &resource->sample_act[idx];
8824 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8825 dest_attr[idx]->dest = sample_act->dr_queue_action;
8826 } else if (sample_act->action_flags ==
8827 (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8828 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8829 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8830 dest_attr[idx]->dest_reformat->reformat =
8831 sample_act->dr_encap_action;
8832 dest_attr[idx]->dest_reformat->dest =
8833 sample_act->dr_port_id_action;
8834 } else if (sample_act->action_flags ==
8835 MLX5_FLOW_ACTION_PORT_ID) {
8836 dest_attr[idx]->dest = sample_act->dr_port_id_action;
8839 /* create a dest array actioin */
8840 cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8842 cache_resource->num_of_dest,
8844 if (!cache_resource->action) {
8845 rte_flow_error_set(error, ENOMEM,
8846 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8848 "cannot create destination array action");
8851 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8852 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8853 &sh->dest_array_list,
8854 dev_flow->handle->dvh.rix_dest_array, cache_resource,
8856 dev_flow->dv.dest_array_res = cache_resource;
8857 DRV_LOG(DEBUG, "new destination array resource %p: refcnt %d++",
8858 (void *)cache_resource,
8859 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8860 for (idx = 0; idx < resource->num_of_dest; idx++)
8861 mlx5_free(dest_attr[idx]);
8864 for (idx = 0; idx < resource->num_of_dest; idx++) {
8865 struct mlx5_flow_sub_actions_idx *act_res =
8866 &cache_resource->sample_idx[idx];
8867 if (act_res->rix_hrxq &&
8868 !mlx5_hrxq_release(dev,
8870 act_res->rix_hrxq = 0;
8871 if (act_res->rix_encap_decap &&
8872 !flow_dv_encap_decap_resource_release(dev,
8873 act_res->rix_encap_decap))
8874 act_res->rix_encap_decap = 0;
8875 if (act_res->rix_port_id_action &&
8876 !flow_dv_port_id_action_resource_release(dev,
8877 act_res->rix_port_id_action))
8878 act_res->rix_port_id_action = 0;
8880 mlx5_free(dest_attr[idx]);
8883 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8884 dev_flow->handle->dvh.rix_dest_array);
8885 dev_flow->handle->dvh.rix_dest_array = 0;
8890 * Convert Sample action to DV specification.
8893 * Pointer to rte_eth_dev structure.
8895 * Pointer to action structure.
8896 * @param[in, out] dev_flow
8897 * Pointer to the mlx5_flow.
8899 * Pointer to the flow attributes.
8900 * @param[in, out] num_of_dest
8901 * Pointer to the num of destination.
8902 * @param[in, out] sample_actions
8903 * Pointer to sample actions list.
8904 * @param[in, out] res
8905 * Pointer to sample resource.
8907 * Pointer to the error structure.
8910 * 0 on success, a negative errno value otherwise and rte_errno is set.
8913 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8914 const struct rte_flow_action *action,
8915 struct mlx5_flow *dev_flow,
8916 const struct rte_flow_attr *attr,
8917 uint32_t *num_of_dest,
8918 void **sample_actions,
8919 struct mlx5_flow_dv_sample_resource *res,
8920 struct rte_flow_error *error)
8922 struct mlx5_priv *priv = dev->data->dev_private;
8923 const struct rte_flow_action_sample *sample_action;
8924 const struct rte_flow_action *sub_actions;
8925 const struct rte_flow_action_queue *queue;
8926 struct mlx5_flow_sub_actions_list *sample_act;
8927 struct mlx5_flow_sub_actions_idx *sample_idx;
8928 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8930 [!!priv->flow_nested_idx];
8931 uint64_t action_flags = 0;
8933 sample_act = &res->sample_act;
8934 sample_idx = &res->sample_idx;
8935 sample_action = (const struct rte_flow_action_sample *)action->conf;
8936 res->ratio = sample_action->ratio;
8937 sub_actions = sample_action->actions;
8938 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8939 int type = sub_actions->type;
8940 uint32_t pre_rix = 0;
8943 case RTE_FLOW_ACTION_TYPE_QUEUE:
8945 struct mlx5_hrxq *hrxq;
8948 queue = sub_actions->conf;
8949 rss_desc->queue_num = 1;
8950 rss_desc->queue[0] = queue->index;
8951 hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
8952 rss_desc, &hrxq_idx);
8954 return rte_flow_error_set
8956 RTE_FLOW_ERROR_TYPE_ACTION,
8958 "cannot create fate queue");
8959 sample_act->dr_queue_action = hrxq->action;
8960 sample_idx->rix_hrxq = hrxq_idx;
8961 sample_actions[sample_act->actions_num++] =
8964 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8965 if (action_flags & MLX5_FLOW_ACTION_MARK)
8966 dev_flow->handle->rix_hrxq = hrxq_idx;
8967 dev_flow->handle->fate_action =
8968 MLX5_FLOW_FATE_QUEUE;
8971 case RTE_FLOW_ACTION_TYPE_MARK:
8973 uint32_t tag_be = mlx5_flow_mark_set
8974 (((const struct rte_flow_action_mark *)
8975 (sub_actions->conf))->id);
8977 dev_flow->handle->mark = 1;
8978 pre_rix = dev_flow->handle->dvh.rix_tag;
8979 /* Save the mark resource before sample */
8980 pre_r = dev_flow->dv.tag_resource;
8981 if (flow_dv_tag_resource_register(dev, tag_be,
8984 MLX5_ASSERT(dev_flow->dv.tag_resource);
8985 sample_act->dr_tag_action =
8986 dev_flow->dv.tag_resource->action;
8987 sample_idx->rix_tag =
8988 dev_flow->handle->dvh.rix_tag;
8989 sample_actions[sample_act->actions_num++] =
8990 sample_act->dr_tag_action;
8991 /* Recover the mark resource after sample */
8992 dev_flow->dv.tag_resource = pre_r;
8993 dev_flow->handle->dvh.rix_tag = pre_rix;
8994 action_flags |= MLX5_FLOW_ACTION_MARK;
8997 case RTE_FLOW_ACTION_TYPE_COUNT:
9001 counter = flow_dv_translate_create_counter(dev,
9002 dev_flow, sub_actions->conf, 0);
9004 return rte_flow_error_set
9006 RTE_FLOW_ERROR_TYPE_ACTION,
9008 "cannot create counter"
9010 sample_idx->cnt = counter;
9011 sample_act->dr_cnt_action =
9012 (flow_dv_counter_get_by_idx(dev,
9013 counter, NULL))->action;
9014 sample_actions[sample_act->actions_num++] =
9015 sample_act->dr_cnt_action;
9016 action_flags |= MLX5_FLOW_ACTION_COUNT;
9019 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9021 struct mlx5_flow_dv_port_id_action_resource
9023 uint32_t port_id = 0;
9025 memset(&port_id_resource, 0, sizeof(port_id_resource));
9026 /* Save the port id resource before sample */
9027 pre_rix = dev_flow->handle->rix_port_id_action;
9028 pre_r = dev_flow->dv.port_id_action;
9029 if (flow_dv_translate_action_port_id(dev, sub_actions,
9032 port_id_resource.port_id = port_id;
9033 if (flow_dv_port_id_action_resource_register
9034 (dev, &port_id_resource, dev_flow, error))
9036 sample_act->dr_port_id_action =
9037 dev_flow->dv.port_id_action->action;
9038 sample_idx->rix_port_id_action =
9039 dev_flow->handle->rix_port_id_action;
9040 sample_actions[sample_act->actions_num++] =
9041 sample_act->dr_port_id_action;
9042 /* Recover the port id resource after sample */
9043 dev_flow->dv.port_id_action = pre_r;
9044 dev_flow->handle->rix_port_id_action = pre_rix;
9046 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9049 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9050 /* Save the encap resource before sample */
9051 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9052 pre_r = dev_flow->dv.encap_decap;
9053 if (flow_dv_create_action_l2_encap(dev, sub_actions,
9058 sample_act->dr_encap_action =
9059 dev_flow->dv.encap_decap->action;
9060 sample_idx->rix_encap_decap =
9061 dev_flow->handle->dvh.rix_encap_decap;
9062 sample_actions[sample_act->actions_num++] =
9063 sample_act->dr_encap_action;
9064 /* Recover the encap resource after sample */
9065 dev_flow->dv.encap_decap = pre_r;
9066 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9067 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9070 return rte_flow_error_set(error, EINVAL,
9071 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9073 "Not support for sampler action");
9076 sample_act->action_flags = action_flags;
9077 res->ft_id = dev_flow->dv.group;
9078 if (attr->transfer) {
9080 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9081 uint64_t set_action;
9082 } action_ctx = { .set_action = 0 };
9084 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9085 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9086 MLX5_MODIFICATION_TYPE_SET);
9087 MLX5_SET(set_action_in, action_ctx.action_in, field,
9088 MLX5_MODI_META_REG_C_0);
9089 MLX5_SET(set_action_in, action_ctx.action_in, data,
9090 priv->vport_meta_tag);
9091 res->set_action = action_ctx.set_action;
9092 } else if (attr->ingress) {
9093 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9099 * Convert Sample action to DV specification.
9102 * Pointer to rte_eth_dev structure.
9103 * @param[in, out] dev_flow
9104 * Pointer to the mlx5_flow.
9106 * Pointer to the flow attributes.
9107 * @param[in] num_of_dest
9108 * The num of destination.
9109 * @param[in, out] res
9110 * Pointer to sample resource.
9111 * @param[in, out] mdest_res
9112 * Pointer to destination array resource.
9113 * @param[in] sample_actions
9114 * Pointer to sample path actions list.
9115 * @param[in] action_flags
9116 * Holds the actions detected until now.
9118 * Pointer to the error structure.
9121 * 0 on success, a negative errno value otherwise and rte_errno is set.
9124 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9125 struct mlx5_flow *dev_flow,
9126 const struct rte_flow_attr *attr,
9127 uint32_t num_of_dest,
9128 struct mlx5_flow_dv_sample_resource *res,
9129 struct mlx5_flow_dv_dest_array_resource *mdest_res,
9130 void **sample_actions,
9131 uint64_t action_flags,
9132 struct rte_flow_error *error)
9134 struct mlx5_priv *priv = dev->data->dev_private;
9135 /* update normal path action resource into last index of array */
9136 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9137 struct mlx5_flow_sub_actions_list *sample_act =
9138 &mdest_res->sample_act[dest_index];
9139 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
9141 [!!priv->flow_nested_idx];
9142 uint32_t normal_idx = 0;
9143 struct mlx5_hrxq *hrxq;
9146 if (num_of_dest > 1) {
9147 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9148 /* Handle QP action for mirroring */
9149 hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
9150 rss_desc, &hrxq_idx);
9152 return rte_flow_error_set
9154 RTE_FLOW_ERROR_TYPE_ACTION,
9156 "cannot create rx queue");
9158 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9159 sample_act->dr_queue_action = hrxq->action;
9160 if (action_flags & MLX5_FLOW_ACTION_MARK)
9161 dev_flow->handle->rix_hrxq = hrxq_idx;
9162 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9164 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9166 mdest_res->sample_idx[dest_index].rix_encap_decap =
9167 dev_flow->handle->dvh.rix_encap_decap;
9168 sample_act->dr_encap_action =
9169 dev_flow->dv.encap_decap->action;
9171 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9173 mdest_res->sample_idx[dest_index].rix_port_id_action =
9174 dev_flow->handle->rix_port_id_action;
9175 sample_act->dr_port_id_action =
9176 dev_flow->dv.port_id_action->action;
9178 sample_act->actions_num = normal_idx;
9179 /* update sample action resource into first index of array */
9180 mdest_res->ft_type = res->ft_type;
9181 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9182 sizeof(struct mlx5_flow_sub_actions_idx));
9183 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9184 sizeof(struct mlx5_flow_sub_actions_list));
9185 mdest_res->num_of_dest = num_of_dest;
9186 if (flow_dv_dest_array_resource_register(dev, attr, mdest_res,
9188 return rte_flow_error_set(error, EINVAL,
9189 RTE_FLOW_ERROR_TYPE_ACTION,
9190 NULL, "can't create sample "
9193 if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
9194 sample_actions, error))
9195 return rte_flow_error_set(error, EINVAL,
9196 RTE_FLOW_ERROR_TYPE_ACTION,
9198 "can't create sample action");
9204 * Fill the flow with DV spec, lock free
9205 * (mutex should be acquired by caller).
9208 * Pointer to rte_eth_dev structure.
9209 * @param[in, out] dev_flow
9210 * Pointer to the sub flow.
9212 * Pointer to the flow attributes.
9214 * Pointer to the list of items.
9215 * @param[in] actions
9216 * Pointer to the list of actions.
9218 * Pointer to the error structure.
9221 * 0 on success, a negative errno value otherwise and rte_errno is set.
9224 __flow_dv_translate(struct rte_eth_dev *dev,
9225 struct mlx5_flow *dev_flow,
9226 const struct rte_flow_attr *attr,
9227 const struct rte_flow_item items[],
9228 const struct rte_flow_action actions[],
9229 struct rte_flow_error *error)
9231 struct mlx5_priv *priv = dev->data->dev_private;
9232 struct mlx5_dev_config *dev_conf = &priv->config;
9233 struct rte_flow *flow = dev_flow->flow;
9234 struct mlx5_flow_handle *handle = dev_flow->handle;
9235 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
9237 [!!priv->flow_nested_idx];
9238 uint64_t item_flags = 0;
9239 uint64_t last_item = 0;
9240 uint64_t action_flags = 0;
9241 uint64_t priority = attr->priority;
9242 struct mlx5_flow_dv_matcher matcher = {
9244 .size = sizeof(matcher.mask.buf) -
9245 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9249 bool actions_end = false;
9251 struct mlx5_flow_dv_modify_hdr_resource res;
9252 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9253 sizeof(struct mlx5_modification_cmd) *
9254 (MLX5_MAX_MODIFY_NUM + 1)];
9256 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9257 const struct rte_flow_action_count *count = NULL;
9258 const struct rte_flow_action_age *age = NULL;
9259 union flow_dv_attr flow_attr = { .attr = 0 };
9261 union mlx5_flow_tbl_key tbl_key;
9262 uint32_t modify_action_position = UINT32_MAX;
9263 void *match_mask = matcher.mask.buf;
9264 void *match_value = dev_flow->dv.value.buf;
9265 uint8_t next_protocol = 0xff;
9266 struct rte_vlan_hdr vlan = { 0 };
9267 struct mlx5_flow_dv_dest_array_resource mdest_res;
9268 struct mlx5_flow_dv_sample_resource sample_res;
9269 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9270 struct mlx5_flow_sub_actions_list *sample_act;
9271 uint32_t sample_act_pos = UINT32_MAX;
9272 uint32_t num_of_dest = 0;
9273 int tmp_actions_n = 0;
9276 const struct mlx5_flow_tunnel *tunnel;
9277 struct flow_grp_info grp_info = {
9278 .external = !!dev_flow->external,
9279 .transfer = !!attr->transfer,
9280 .fdb_def_rule = !!priv->fdb_def_rule,
9283 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9284 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9285 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9286 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9287 /* update normal path action resource into last index of array */
9288 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9289 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9290 flow_items_to_tunnel(items) :
9291 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9292 flow_actions_to_tunnel(actions) :
9293 dev_flow->tunnel ? dev_flow->tunnel : NULL;
9294 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9295 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9296 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9297 (dev, tunnel, attr, items, actions);
9298 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9302 dev_flow->dv.group = table;
9304 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9305 if (priority == MLX5_FLOW_PRIO_RSVD)
9306 priority = dev_conf->flow_prio - 1;
9307 /* number of actions must be set to 0 in case of dirty stack. */
9308 mhdr_res->actions_num = 0;
9309 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9311 * do not add decap action if match rule drops packet
9312 * HW rejects rules with decap & drop
9314 bool add_decap = true;
9315 const struct rte_flow_action *ptr = actions;
9316 struct mlx5_flow_tbl_resource *tbl;
9318 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9319 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9325 if (flow_dv_create_action_l2_decap(dev, dev_flow,
9329 dev_flow->dv.actions[actions_n++] =
9330 dev_flow->dv.encap_decap->action;
9331 action_flags |= MLX5_FLOW_ACTION_DECAP;
9334 * bind table_id with <group, table> for tunnel match rule.
9335 * Tunnel set rule establishes that bind in JUMP action handler.
9336 * Required for scenario when application creates tunnel match
9337 * rule before tunnel set rule.
9339 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9341 !!dev_flow->external, tunnel,
9342 attr->group, error);
9344 return rte_flow_error_set
9345 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
9346 actions, "cannot register tunnel group");
9348 for (; !actions_end ; actions++) {
9349 const struct rte_flow_action_queue *queue;
9350 const struct rte_flow_action_rss *rss;
9351 const struct rte_flow_action *action = actions;
9352 const uint8_t *rss_key;
9353 const struct rte_flow_action_meter *mtr;
9354 struct mlx5_flow_tbl_resource *tbl;
9355 uint32_t port_id = 0;
9356 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9357 int action_type = actions->type;
9358 const struct rte_flow_action *found_action = NULL;
9359 struct mlx5_flow_meter *fm = NULL;
9360 uint32_t jump_group = 0;
9362 if (!mlx5_flow_os_action_supported(action_type))
9363 return rte_flow_error_set(error, ENOTSUP,
9364 RTE_FLOW_ERROR_TYPE_ACTION,
9366 "action not supported");
9367 switch (action_type) {
9368 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9369 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9371 case RTE_FLOW_ACTION_TYPE_VOID:
9373 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9374 if (flow_dv_translate_action_port_id(dev, action,
9377 port_id_resource.port_id = port_id;
9378 MLX5_ASSERT(!handle->rix_port_id_action);
9379 if (flow_dv_port_id_action_resource_register
9380 (dev, &port_id_resource, dev_flow, error))
9382 dev_flow->dv.actions[actions_n++] =
9383 dev_flow->dv.port_id_action->action;
9384 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9385 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9386 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9389 case RTE_FLOW_ACTION_TYPE_FLAG:
9390 action_flags |= MLX5_FLOW_ACTION_FLAG;
9391 dev_flow->handle->mark = 1;
9392 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9393 struct rte_flow_action_mark mark = {
9394 .id = MLX5_FLOW_MARK_DEFAULT,
9397 if (flow_dv_convert_action_mark(dev, &mark,
9401 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9404 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9406 * Only one FLAG or MARK is supported per device flow
9407 * right now. So the pointer to the tag resource must be
9408 * zero before the register process.
9410 MLX5_ASSERT(!handle->dvh.rix_tag);
9411 if (flow_dv_tag_resource_register(dev, tag_be,
9414 MLX5_ASSERT(dev_flow->dv.tag_resource);
9415 dev_flow->dv.actions[actions_n++] =
9416 dev_flow->dv.tag_resource->action;
9418 case RTE_FLOW_ACTION_TYPE_MARK:
9419 action_flags |= MLX5_FLOW_ACTION_MARK;
9420 dev_flow->handle->mark = 1;
9421 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9422 const struct rte_flow_action_mark *mark =
9423 (const struct rte_flow_action_mark *)
9426 if (flow_dv_convert_action_mark(dev, mark,
9430 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9434 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9435 /* Legacy (non-extensive) MARK action. */
9436 tag_be = mlx5_flow_mark_set
9437 (((const struct rte_flow_action_mark *)
9438 (actions->conf))->id);
9439 MLX5_ASSERT(!handle->dvh.rix_tag);
9440 if (flow_dv_tag_resource_register(dev, tag_be,
9443 MLX5_ASSERT(dev_flow->dv.tag_resource);
9444 dev_flow->dv.actions[actions_n++] =
9445 dev_flow->dv.tag_resource->action;
9447 case RTE_FLOW_ACTION_TYPE_SET_META:
9448 if (flow_dv_convert_action_set_meta
9449 (dev, mhdr_res, attr,
9450 (const struct rte_flow_action_set_meta *)
9451 actions->conf, error))
9453 action_flags |= MLX5_FLOW_ACTION_SET_META;
9455 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9456 if (flow_dv_convert_action_set_tag
9458 (const struct rte_flow_action_set_tag *)
9459 actions->conf, error))
9461 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9463 case RTE_FLOW_ACTION_TYPE_DROP:
9464 action_flags |= MLX5_FLOW_ACTION_DROP;
9465 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9467 case RTE_FLOW_ACTION_TYPE_QUEUE:
9468 queue = actions->conf;
9469 rss_desc->queue_num = 1;
9470 rss_desc->queue[0] = queue->index;
9471 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9472 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9473 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9476 case RTE_FLOW_ACTION_TYPE_RSS:
9477 rss = actions->conf;
9478 memcpy(rss_desc->queue, rss->queue,
9479 rss->queue_num * sizeof(uint16_t));
9480 rss_desc->queue_num = rss->queue_num;
9481 /* NULL RSS key indicates default RSS key. */
9482 rss_key = !rss->key ? rss_hash_default_key : rss->key;
9483 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9485 * rss->level and rss.types should be set in advance
9486 * when expanding items for RSS.
9488 action_flags |= MLX5_FLOW_ACTION_RSS;
9489 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9491 case RTE_FLOW_ACTION_TYPE_AGE:
9492 case RTE_FLOW_ACTION_TYPE_COUNT:
9493 if (!dev_conf->devx) {
9494 return rte_flow_error_set
9496 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9498 "count action not supported");
9500 /* Save information first, will apply later. */
9501 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9502 count = action->conf;
9505 action_flags |= MLX5_FLOW_ACTION_COUNT;
9507 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9508 dev_flow->dv.actions[actions_n++] =
9509 priv->sh->pop_vlan_action;
9510 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9512 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9513 if (!(action_flags &
9514 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9515 flow_dev_get_vlan_info_from_items(items, &vlan);
9516 vlan.eth_proto = rte_be_to_cpu_16
9517 ((((const struct rte_flow_action_of_push_vlan *)
9518 actions->conf)->ethertype));
9519 found_action = mlx5_flow_find_action
9521 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9523 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9524 found_action = mlx5_flow_find_action
9526 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9528 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9529 if (flow_dv_create_action_push_vlan
9530 (dev, attr, &vlan, dev_flow, error))
9532 dev_flow->dv.actions[actions_n++] =
9533 dev_flow->dv.push_vlan_res->action;
9534 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9536 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9537 /* of_vlan_push action handled this action */
9538 MLX5_ASSERT(action_flags &
9539 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9541 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9542 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9544 flow_dev_get_vlan_info_from_items(items, &vlan);
9545 mlx5_update_vlan_vid_pcp(actions, &vlan);
9546 /* If no VLAN push - this is a modify header action */
9547 if (flow_dv_convert_action_modify_vlan_vid
9548 (mhdr_res, actions, error))
9550 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9552 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9553 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9554 if (flow_dv_create_action_l2_encap(dev, actions,
9559 dev_flow->dv.actions[actions_n++] =
9560 dev_flow->dv.encap_decap->action;
9561 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9562 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9563 sample_act->action_flags |=
9564 MLX5_FLOW_ACTION_ENCAP;
9566 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9567 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9568 if (flow_dv_create_action_l2_decap(dev, dev_flow,
9572 dev_flow->dv.actions[actions_n++] =
9573 dev_flow->dv.encap_decap->action;
9574 action_flags |= MLX5_FLOW_ACTION_DECAP;
9576 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9577 /* Handle encap with preceding decap. */
9578 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9579 if (flow_dv_create_action_raw_encap
9580 (dev, actions, dev_flow, attr, error))
9582 dev_flow->dv.actions[actions_n++] =
9583 dev_flow->dv.encap_decap->action;
9585 /* Handle encap without preceding decap. */
9586 if (flow_dv_create_action_l2_encap
9587 (dev, actions, dev_flow, attr->transfer,
9590 dev_flow->dv.actions[actions_n++] =
9591 dev_flow->dv.encap_decap->action;
9593 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9594 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9595 sample_act->action_flags |=
9596 MLX5_FLOW_ACTION_ENCAP;
9598 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9599 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9601 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9602 if (flow_dv_create_action_l2_decap
9603 (dev, dev_flow, attr->transfer, error))
9605 dev_flow->dv.actions[actions_n++] =
9606 dev_flow->dv.encap_decap->action;
9608 /* If decap is followed by encap, handle it at encap. */
9609 action_flags |= MLX5_FLOW_ACTION_DECAP;
9611 case RTE_FLOW_ACTION_TYPE_JUMP:
9612 jump_group = ((const struct rte_flow_action_jump *)
9613 action->conf)->group;
9614 grp_info.std_tbl_fix = 0;
9615 ret = mlx5_flow_group_to_table(dev, tunnel,
9621 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9623 !!dev_flow->external,
9627 return rte_flow_error_set
9629 RTE_FLOW_ERROR_TYPE_ACTION,
9631 "cannot create jump action.");
9632 if (flow_dv_jump_tbl_resource_register
9633 (dev, tbl, dev_flow, error)) {
9634 flow_dv_tbl_resource_release(dev, tbl);
9635 return rte_flow_error_set
9637 RTE_FLOW_ERROR_TYPE_ACTION,
9639 "cannot create jump action.");
9641 dev_flow->dv.actions[actions_n++] =
9642 dev_flow->dv.jump->action;
9643 action_flags |= MLX5_FLOW_ACTION_JUMP;
9644 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9646 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9647 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9648 if (flow_dv_convert_action_modify_mac
9649 (mhdr_res, actions, error))
9651 action_flags |= actions->type ==
9652 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9653 MLX5_FLOW_ACTION_SET_MAC_SRC :
9654 MLX5_FLOW_ACTION_SET_MAC_DST;
9656 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9657 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9658 if (flow_dv_convert_action_modify_ipv4
9659 (mhdr_res, actions, error))
9661 action_flags |= actions->type ==
9662 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9663 MLX5_FLOW_ACTION_SET_IPV4_SRC :
9664 MLX5_FLOW_ACTION_SET_IPV4_DST;
9666 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9667 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9668 if (flow_dv_convert_action_modify_ipv6
9669 (mhdr_res, actions, error))
9671 action_flags |= actions->type ==
9672 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9673 MLX5_FLOW_ACTION_SET_IPV6_SRC :
9674 MLX5_FLOW_ACTION_SET_IPV6_DST;
9676 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9677 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9678 if (flow_dv_convert_action_modify_tp
9679 (mhdr_res, actions, items,
9680 &flow_attr, dev_flow, !!(action_flags &
9681 MLX5_FLOW_ACTION_DECAP), error))
9683 action_flags |= actions->type ==
9684 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9685 MLX5_FLOW_ACTION_SET_TP_SRC :
9686 MLX5_FLOW_ACTION_SET_TP_DST;
9688 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9689 if (flow_dv_convert_action_modify_dec_ttl
9690 (mhdr_res, items, &flow_attr, dev_flow,
9692 MLX5_FLOW_ACTION_DECAP), error))
9694 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9696 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9697 if (flow_dv_convert_action_modify_ttl
9698 (mhdr_res, actions, items, &flow_attr,
9699 dev_flow, !!(action_flags &
9700 MLX5_FLOW_ACTION_DECAP), error))
9702 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9704 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9705 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9706 if (flow_dv_convert_action_modify_tcp_seq
9707 (mhdr_res, actions, error))
9709 action_flags |= actions->type ==
9710 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9711 MLX5_FLOW_ACTION_INC_TCP_SEQ :
9712 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9715 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9716 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9717 if (flow_dv_convert_action_modify_tcp_ack
9718 (mhdr_res, actions, error))
9720 action_flags |= actions->type ==
9721 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9722 MLX5_FLOW_ACTION_INC_TCP_ACK :
9723 MLX5_FLOW_ACTION_DEC_TCP_ACK;
9725 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9726 if (flow_dv_convert_action_set_reg
9727 (mhdr_res, actions, error))
9729 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9731 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9732 if (flow_dv_convert_action_copy_mreg
9733 (dev, mhdr_res, actions, error))
9735 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9737 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9738 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9739 dev_flow->handle->fate_action =
9740 MLX5_FLOW_FATE_DEFAULT_MISS;
9742 case RTE_FLOW_ACTION_TYPE_METER:
9743 mtr = actions->conf;
9745 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9748 return rte_flow_error_set(error,
9750 RTE_FLOW_ERROR_TYPE_ACTION,
9753 "or invalid parameters");
9754 flow->meter = fm->idx;
9756 /* Set the meter action. */
9758 fm = mlx5_ipool_get(priv->sh->ipool
9759 [MLX5_IPOOL_MTR], flow->meter);
9761 return rte_flow_error_set(error,
9763 RTE_FLOW_ERROR_TYPE_ACTION,
9766 "or invalid parameters");
9768 dev_flow->dv.actions[actions_n++] =
9769 fm->mfts->meter_action;
9770 action_flags |= MLX5_FLOW_ACTION_METER;
9772 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9773 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9776 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9778 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9779 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9782 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9784 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9785 sample_act_pos = actions_n;
9786 ret = flow_dv_translate_action_sample(dev,
9796 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9797 /* put encap action into group if work with port id */
9798 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
9799 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
9800 sample_act->action_flags |=
9801 MLX5_FLOW_ACTION_ENCAP;
9803 case RTE_FLOW_ACTION_TYPE_END:
9805 if (mhdr_res->actions_num) {
9806 /* create modify action if needed. */
9807 if (flow_dv_modify_hdr_resource_register
9808 (dev, mhdr_res, dev_flow, error))
9810 dev_flow->dv.actions[modify_action_position] =
9811 handle->dvh.modify_hdr->action;
9813 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9815 flow_dv_translate_create_counter(dev,
9816 dev_flow, count, age);
9819 return rte_flow_error_set
9821 RTE_FLOW_ERROR_TYPE_ACTION,
9823 "cannot create counter"
9825 dev_flow->dv.actions[actions_n] =
9826 (flow_dv_counter_get_by_idx(dev,
9827 flow->counter, NULL))->action;
9830 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9831 ret = flow_dv_create_action_sample(dev,
9840 return rte_flow_error_set
9842 RTE_FLOW_ERROR_TYPE_ACTION,
9844 "cannot create sample action");
9845 if (num_of_dest > 1) {
9846 dev_flow->dv.actions[sample_act_pos] =
9847 dev_flow->dv.dest_array_res->action;
9849 dev_flow->dv.actions[sample_act_pos] =
9850 dev_flow->dv.sample_res->verbs_action;
9857 if (mhdr_res->actions_num &&
9858 modify_action_position == UINT32_MAX)
9859 modify_action_position = actions_n++;
9862 * For multiple destination (sample action with ratio=1), the encap
9863 * action and port id action will be combined into group action.
9864 * So need remove the original these actions in the flow and only
9865 * use the sample action instead of.
9867 if (num_of_dest > 1 && sample_act->dr_port_id_action) {
9869 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9871 for (i = 0; i < actions_n; i++) {
9872 if ((sample_act->dr_encap_action &&
9873 sample_act->dr_encap_action ==
9874 dev_flow->dv.actions[i]) ||
9875 (sample_act->dr_port_id_action &&
9876 sample_act->dr_port_id_action ==
9877 dev_flow->dv.actions[i]))
9879 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
9881 memcpy((void *)dev_flow->dv.actions,
9882 (void *)temp_actions,
9883 tmp_actions_n * sizeof(void *));
9884 actions_n = tmp_actions_n;
9886 dev_flow->dv.actions_n = actions_n;
9887 dev_flow->act_flags = action_flags;
9888 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9889 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9890 int item_type = items->type;
9892 if (!mlx5_flow_os_item_supported(item_type))
9893 return rte_flow_error_set(error, ENOTSUP,
9894 RTE_FLOW_ERROR_TYPE_ITEM,
9895 NULL, "item not supported");
9896 switch (item_type) {
9897 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9898 flow_dv_translate_item_port_id(dev, match_mask,
9899 match_value, items);
9900 last_item = MLX5_FLOW_ITEM_PORT_ID;
9902 case RTE_FLOW_ITEM_TYPE_ETH:
9903 flow_dv_translate_item_eth(match_mask, match_value,
9905 dev_flow->dv.group);
9906 matcher.priority = action_flags &
9907 MLX5_FLOW_ACTION_DEFAULT_MISS &&
9908 !dev_flow->external ?
9909 MLX5_PRIORITY_MAP_L3 :
9910 MLX5_PRIORITY_MAP_L2;
9911 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9912 MLX5_FLOW_LAYER_OUTER_L2;
9914 case RTE_FLOW_ITEM_TYPE_VLAN:
9915 flow_dv_translate_item_vlan(dev_flow,
9916 match_mask, match_value,
9918 dev_flow->dv.group);
9919 matcher.priority = MLX5_PRIORITY_MAP_L2;
9920 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9921 MLX5_FLOW_LAYER_INNER_VLAN) :
9922 (MLX5_FLOW_LAYER_OUTER_L2 |
9923 MLX5_FLOW_LAYER_OUTER_VLAN);
9925 case RTE_FLOW_ITEM_TYPE_IPV4:
9926 mlx5_flow_tunnel_ip_check(items, next_protocol,
9927 &item_flags, &tunnel);
9928 flow_dv_translate_item_ipv4(match_mask, match_value,
9929 items, item_flags, tunnel,
9930 dev_flow->dv.group);
9931 matcher.priority = MLX5_PRIORITY_MAP_L3;
9932 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9933 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9934 if (items->mask != NULL &&
9935 ((const struct rte_flow_item_ipv4 *)
9936 items->mask)->hdr.next_proto_id) {
9938 ((const struct rte_flow_item_ipv4 *)
9939 (items->spec))->hdr.next_proto_id;
9941 ((const struct rte_flow_item_ipv4 *)
9942 (items->mask))->hdr.next_proto_id;
9944 /* Reset for inner layer. */
9945 next_protocol = 0xff;
9948 case RTE_FLOW_ITEM_TYPE_IPV6:
9949 mlx5_flow_tunnel_ip_check(items, next_protocol,
9950 &item_flags, &tunnel);
9951 flow_dv_translate_item_ipv6(match_mask, match_value,
9952 items, item_flags, tunnel,
9953 dev_flow->dv.group);
9954 matcher.priority = MLX5_PRIORITY_MAP_L3;
9955 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9956 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9957 if (items->mask != NULL &&
9958 ((const struct rte_flow_item_ipv6 *)
9959 items->mask)->hdr.proto) {
9961 ((const struct rte_flow_item_ipv6 *)
9962 items->spec)->hdr.proto;
9964 ((const struct rte_flow_item_ipv6 *)
9965 items->mask)->hdr.proto;
9967 /* Reset for inner layer. */
9968 next_protocol = 0xff;
9971 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9972 flow_dv_translate_item_ipv6_frag_ext(match_mask,
9975 last_item = tunnel ?
9976 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
9977 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
9978 if (items->mask != NULL &&
9979 ((const struct rte_flow_item_ipv6_frag_ext *)
9980 items->mask)->hdr.next_header) {
9982 ((const struct rte_flow_item_ipv6_frag_ext *)
9983 items->spec)->hdr.next_header;
9985 ((const struct rte_flow_item_ipv6_frag_ext *)
9986 items->mask)->hdr.next_header;
9988 /* Reset for inner layer. */
9989 next_protocol = 0xff;
9992 case RTE_FLOW_ITEM_TYPE_TCP:
9993 flow_dv_translate_item_tcp(match_mask, match_value,
9995 matcher.priority = MLX5_PRIORITY_MAP_L4;
9996 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9997 MLX5_FLOW_LAYER_OUTER_L4_TCP;
9999 case RTE_FLOW_ITEM_TYPE_UDP:
10000 flow_dv_translate_item_udp(match_mask, match_value,
10002 matcher.priority = MLX5_PRIORITY_MAP_L4;
10003 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10004 MLX5_FLOW_LAYER_OUTER_L4_UDP;
10006 case RTE_FLOW_ITEM_TYPE_GRE:
10007 flow_dv_translate_item_gre(match_mask, match_value,
10009 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10010 last_item = MLX5_FLOW_LAYER_GRE;
10012 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10013 flow_dv_translate_item_gre_key(match_mask,
10014 match_value, items);
10015 last_item = MLX5_FLOW_LAYER_GRE_KEY;
10017 case RTE_FLOW_ITEM_TYPE_NVGRE:
10018 flow_dv_translate_item_nvgre(match_mask, match_value,
10020 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10021 last_item = MLX5_FLOW_LAYER_GRE;
10023 case RTE_FLOW_ITEM_TYPE_VXLAN:
10024 flow_dv_translate_item_vxlan(match_mask, match_value,
10026 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10027 last_item = MLX5_FLOW_LAYER_VXLAN;
10029 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10030 flow_dv_translate_item_vxlan_gpe(match_mask,
10031 match_value, items,
10033 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10034 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10036 case RTE_FLOW_ITEM_TYPE_GENEVE:
10037 flow_dv_translate_item_geneve(match_mask, match_value,
10039 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10040 last_item = MLX5_FLOW_LAYER_GENEVE;
10042 case RTE_FLOW_ITEM_TYPE_MPLS:
10043 flow_dv_translate_item_mpls(match_mask, match_value,
10044 items, last_item, tunnel);
10045 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10046 last_item = MLX5_FLOW_LAYER_MPLS;
10048 case RTE_FLOW_ITEM_TYPE_MARK:
10049 flow_dv_translate_item_mark(dev, match_mask,
10050 match_value, items);
10051 last_item = MLX5_FLOW_ITEM_MARK;
10053 case RTE_FLOW_ITEM_TYPE_META:
10054 flow_dv_translate_item_meta(dev, match_mask,
10055 match_value, attr, items);
10056 last_item = MLX5_FLOW_ITEM_METADATA;
10058 case RTE_FLOW_ITEM_TYPE_ICMP:
10059 flow_dv_translate_item_icmp(match_mask, match_value,
10061 last_item = MLX5_FLOW_LAYER_ICMP;
10063 case RTE_FLOW_ITEM_TYPE_ICMP6:
10064 flow_dv_translate_item_icmp6(match_mask, match_value,
10066 last_item = MLX5_FLOW_LAYER_ICMP6;
10068 case RTE_FLOW_ITEM_TYPE_TAG:
10069 flow_dv_translate_item_tag(dev, match_mask,
10070 match_value, items);
10071 last_item = MLX5_FLOW_ITEM_TAG;
10073 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10074 flow_dv_translate_mlx5_item_tag(dev, match_mask,
10075 match_value, items);
10076 last_item = MLX5_FLOW_ITEM_TAG;
10078 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10079 flow_dv_translate_item_tx_queue(dev, match_mask,
10082 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10084 case RTE_FLOW_ITEM_TYPE_GTP:
10085 flow_dv_translate_item_gtp(match_mask, match_value,
10087 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10088 last_item = MLX5_FLOW_LAYER_GTP;
10090 case RTE_FLOW_ITEM_TYPE_ECPRI:
10091 if (!mlx5_flex_parser_ecpri_exist(dev)) {
10092 /* Create it only the first time to be used. */
10093 ret = mlx5_flex_parser_ecpri_alloc(dev);
10095 return rte_flow_error_set
10097 RTE_FLOW_ERROR_TYPE_ITEM,
10099 "cannot create eCPRI parser");
10101 /* Adjust the length matcher and device flow value. */
10102 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10103 dev_flow->dv.value.size =
10104 MLX5_ST_SZ_BYTES(fte_match_param);
10105 flow_dv_translate_item_ecpri(dev, match_mask,
10106 match_value, items);
10107 /* No other protocol should follow eCPRI layer. */
10108 last_item = MLX5_FLOW_LAYER_ECPRI;
10113 item_flags |= last_item;
10116 * When E-Switch mode is enabled, we have two cases where we need to
10117 * set the source port manually.
10118 * The first one, is in case of Nic steering rule, and the second is
10119 * E-Switch rule where no port_id item was found. In both cases
10120 * the source port is set according the current port in use.
10122 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10123 (priv->representor || priv->master)) {
10124 if (flow_dv_translate_item_port_id(dev, match_mask,
10125 match_value, NULL))
10128 #ifdef RTE_LIBRTE_MLX5_DEBUG
10129 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10130 dev_flow->dv.value.buf));
10133 * Layers may be already initialized from prefix flow if this dev_flow
10134 * is the suffix flow.
10136 handle->layers |= item_flags;
10137 if (action_flags & MLX5_FLOW_ACTION_RSS)
10138 flow_dv_hashfields_set(dev_flow, rss_desc);
10139 /* Register matcher. */
10140 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10141 matcher.mask.size);
10142 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10144 /* reserved field no needs to be set to 0 here. */
10145 tbl_key.domain = attr->transfer;
10146 tbl_key.direction = attr->egress;
10147 tbl_key.table_id = dev_flow->dv.group;
10148 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
10154 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10157 * @param[in, out] action
10158 * Shred RSS action holding hash RX queue objects.
10159 * @param[in] hash_fields
10160 * Defines combination of packet fields to participate in RX hash.
10161 * @param[in] tunnel
10163 * @param[in] hrxq_idx
10164 * Hash RX queue index to set.
10167 * 0 on success, otherwise negative errno value.
10170 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10171 const uint64_t hash_fields,
10175 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10177 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10178 case MLX5_RSS_HASH_IPV4:
10179 hrxqs[0] = hrxq_idx;
10181 case MLX5_RSS_HASH_IPV4_TCP:
10182 hrxqs[1] = hrxq_idx;
10184 case MLX5_RSS_HASH_IPV4_UDP:
10185 hrxqs[2] = hrxq_idx;
10187 case MLX5_RSS_HASH_IPV6:
10188 hrxqs[3] = hrxq_idx;
10190 case MLX5_RSS_HASH_IPV6_TCP:
10191 hrxqs[4] = hrxq_idx;
10193 case MLX5_RSS_HASH_IPV6_UDP:
10194 hrxqs[5] = hrxq_idx;
10196 case MLX5_RSS_HASH_NONE:
10197 hrxqs[6] = hrxq_idx;
10205 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10208 * @param[in] action
10209 * Shred RSS action holding hash RX queue objects.
10210 * @param[in] hash_fields
10211 * Defines combination of packet fields to participate in RX hash.
10212 * @param[in] tunnel
10216 * Valid hash RX queue index, otherwise 0.
10219 __flow_dv_action_rss_hrxq_lookup(const struct mlx5_shared_action_rss *action,
10220 const uint64_t hash_fields,
10223 const uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10225 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10226 case MLX5_RSS_HASH_IPV4:
10228 case MLX5_RSS_HASH_IPV4_TCP:
10230 case MLX5_RSS_HASH_IPV4_UDP:
10232 case MLX5_RSS_HASH_IPV6:
10234 case MLX5_RSS_HASH_IPV6_TCP:
10236 case MLX5_RSS_HASH_IPV6_UDP:
10238 case MLX5_RSS_HASH_NONE:
10246 * Retrieves hash RX queue suitable for the *flow*.
10247 * If shared action configured for *flow* suitable hash RX queue will be
10248 * retrieved from attached shared action.
10251 * Shred RSS action holding hash RX queue objects.
10252 * @param[in] dev_flow
10253 * Pointer to the sub flow.
10255 * Pointer to retrieved hash RX queue object.
10258 * Valid hash RX queue index, otherwise 0 and rte_errno is set.
10261 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,
10262 struct mlx5_flow *dev_flow,
10263 struct mlx5_hrxq **hrxq)
10265 struct mlx5_priv *priv = dev->data->dev_private;
10268 if (flow->shared_rss) {
10269 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10270 (flow->shared_rss, dev_flow->hash_fields,
10271 !!(dev_flow->handle->layers &
10272 MLX5_FLOW_LAYER_TUNNEL));
10274 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10276 rte_atomic32_inc(&(*hrxq)->refcnt);
10279 struct mlx5_flow_rss_desc *rss_desc =
10280 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
10281 [!!priv->flow_nested_idx];
10283 MLX5_ASSERT(rss_desc->queue_num);
10284 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
10285 MLX5_RSS_HASH_KEY_LEN,
10286 dev_flow->hash_fields,
10287 rss_desc->queue, rss_desc->queue_num);
10289 hrxq_idx = mlx5_hrxq_new(dev,
10291 MLX5_RSS_HASH_KEY_LEN,
10292 dev_flow->hash_fields,
10294 rss_desc->queue_num,
10295 !!(dev_flow->handle->layers &
10296 MLX5_FLOW_LAYER_TUNNEL),
10299 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10306 * Apply the flow to the NIC, lock free,
10307 * (mutex should be acquired by caller).
10310 * Pointer to the Ethernet device structure.
10311 * @param[in, out] flow
10312 * Pointer to flow structure.
10313 * @param[out] error
10314 * Pointer to error structure.
10317 * 0 on success, a negative errno value otherwise and rte_errno is set.
10320 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10321 struct rte_flow_error *error)
10323 struct mlx5_flow_dv_workspace *dv;
10324 struct mlx5_flow_handle *dh;
10325 struct mlx5_flow_handle_dv *dv_h;
10326 struct mlx5_flow *dev_flow;
10327 struct mlx5_priv *priv = dev->data->dev_private;
10328 uint32_t handle_idx;
10333 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
10334 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
10335 dv = &dev_flow->dv;
10336 dh = dev_flow->handle;
10339 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10340 if (dv->transfer) {
10341 dv->actions[n++] = priv->sh->esw_drop_action;
10343 struct mlx5_hrxq *drop_hrxq;
10344 drop_hrxq = mlx5_drop_action_create(dev);
10348 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10350 "cannot get drop hash queue");
10354 * Drop queues will be released by the specify
10355 * mlx5_drop_action_destroy() function. Assign
10356 * the special index to hrxq to mark the queue
10357 * has been allocated.
10359 dh->rix_hrxq = UINT32_MAX;
10360 dv->actions[n++] = drop_hrxq->action;
10362 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10363 !dv_h->rix_sample && !dv_h->rix_dest_array) {
10364 struct mlx5_hrxq *hrxq = NULL;
10365 uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10366 (dev, flow, dev_flow, &hrxq);
10371 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10372 "cannot get hash queue");
10375 dh->rix_hrxq = hrxq_idx;
10376 dv->actions[n++] = hrxq->action;
10377 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10378 if (flow_dv_default_miss_resource_register
10382 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10383 "cannot create default miss resource");
10384 goto error_default_miss;
10386 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
10387 dv->actions[n++] = priv->sh->default_miss.action;
10389 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10390 (void *)&dv->value, n,
10391 dv->actions, &dh->drv_flow);
10393 rte_flow_error_set(error, errno,
10394 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10396 "hardware refuses to create flow");
10399 if (priv->vmwa_context &&
10400 dh->vf_vlan.tag && !dh->vf_vlan.created) {
10402 * The rule contains the VLAN pattern.
10403 * For VF we are going to create VLAN
10404 * interface to make hypervisor set correct
10405 * e-Switch vport context.
10407 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10412 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10413 flow_dv_default_miss_resource_release(dev);
10414 error_default_miss:
10415 err = rte_errno; /* Save rte_errno before cleanup. */
10416 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10417 handle_idx, dh, next) {
10418 /* hrxq is union, don't clear it if the flag is not set. */
10419 if (dh->rix_hrxq) {
10420 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10421 mlx5_drop_action_destroy(dev);
10423 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
10424 mlx5_hrxq_release(dev, dh->rix_hrxq);
10428 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10429 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10431 rte_errno = err; /* Restore rte_errno. */
10436 * Release the flow matcher.
10439 * Pointer to Ethernet device.
10441 * Pointer to mlx5_flow_handle.
10444 * 1 while a reference on it exists, 0 when freed.
10447 flow_dv_matcher_release(struct rte_eth_dev *dev,
10448 struct mlx5_flow_handle *handle)
10450 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10452 MLX5_ASSERT(matcher->matcher_object);
10453 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
10454 dev->data->port_id, (void *)matcher,
10455 rte_atomic32_read(&matcher->refcnt));
10456 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
10457 claim_zero(mlx5_flow_os_destroy_flow_matcher
10458 (matcher->matcher_object));
10459 LIST_REMOVE(matcher, next);
10460 /* table ref-- in release interface. */
10461 flow_dv_tbl_resource_release(dev, matcher->tbl);
10462 mlx5_free(matcher);
10463 DRV_LOG(DEBUG, "port %u matcher %p: removed",
10464 dev->data->port_id, (void *)matcher);
10471 * Release an encap/decap resource.
10474 * Pointer to Ethernet device.
10475 * @param encap_decap_idx
10476 * Index of encap decap resource.
10479 * 1 while a reference on it exists, 0 when freed.
10482 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10483 uint32_t encap_decap_idx)
10485 struct mlx5_priv *priv = dev->data->dev_private;
10486 uint32_t idx = encap_decap_idx;
10487 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10489 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10491 if (!cache_resource)
10493 MLX5_ASSERT(cache_resource->action);
10494 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
10495 (void *)cache_resource,
10496 rte_atomic32_read(&cache_resource->refcnt));
10497 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10498 claim_zero(mlx5_flow_os_destroy_flow_action
10499 (cache_resource->action));
10500 mlx5_hlist_remove(priv->sh->encaps_decaps,
10501 &cache_resource->entry);
10502 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
10503 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
10504 (void *)cache_resource);
10511 * Release an jump to table action resource.
10514 * Pointer to Ethernet device.
10516 * Pointer to mlx5_flow_handle.
10519 * 1 while a reference on it exists, 0 when freed.
10522 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10523 struct mlx5_flow_handle *handle)
10525 struct mlx5_priv *priv = dev->data->dev_private;
10526 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
10527 struct mlx5_flow_tbl_data_entry *tbl_data;
10529 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10533 cache_resource = &tbl_data->jump;
10534 MLX5_ASSERT(cache_resource->action);
10535 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
10536 (void *)cache_resource,
10537 rte_atomic32_read(&cache_resource->refcnt));
10538 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10539 claim_zero(mlx5_flow_os_destroy_flow_action
10540 (cache_resource->action));
10541 /* jump action memory free is inside the table release. */
10542 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
10543 DRV_LOG(DEBUG, "jump table resource %p: removed",
10544 (void *)cache_resource);
10551 * Release a default miss resource.
10554 * Pointer to Ethernet device.
10556 * 1 while a reference on it exists, 0 when freed.
10559 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
10561 struct mlx5_priv *priv = dev->data->dev_private;
10562 struct mlx5_dev_ctx_shared *sh = priv->sh;
10563 struct mlx5_flow_default_miss_resource *cache_resource =
10566 MLX5_ASSERT(cache_resource->action);
10567 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
10568 (void *)cache_resource->action,
10569 rte_atomic32_read(&cache_resource->refcnt));
10570 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10571 claim_zero(mlx5_glue->destroy_flow_action
10572 (cache_resource->action));
10573 DRV_LOG(DEBUG, "default miss resource %p: removed",
10574 (void *)cache_resource->action);
10581 * Release a modify-header resource.
10584 * Pointer to Ethernet device.
10586 * Pointer to mlx5_flow_handle.
10589 * 1 while a reference on it exists, 0 when freed.
10592 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10593 struct mlx5_flow_handle *handle)
10595 struct mlx5_priv *priv = dev->data->dev_private;
10596 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
10597 handle->dvh.modify_hdr;
10599 MLX5_ASSERT(cache_resource->action);
10600 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
10601 (void *)cache_resource,
10602 rte_atomic32_read(&cache_resource->refcnt));
10603 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10604 claim_zero(mlx5_flow_os_destroy_flow_action
10605 (cache_resource->action));
10606 mlx5_hlist_remove(priv->sh->modify_cmds,
10607 &cache_resource->entry);
10608 mlx5_free(cache_resource);
10609 DRV_LOG(DEBUG, "modify-header resource %p: removed",
10610 (void *)cache_resource);
10617 * Release port ID action resource.
10620 * Pointer to Ethernet device.
10622 * Pointer to mlx5_flow_handle.
10625 * 1 while a reference on it exists, 0 when freed.
10628 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10631 struct mlx5_priv *priv = dev->data->dev_private;
10632 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
10633 uint32_t idx = port_id;
10635 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10637 if (!cache_resource)
10639 MLX5_ASSERT(cache_resource->action);
10640 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
10641 (void *)cache_resource,
10642 rte_atomic32_read(&cache_resource->refcnt));
10643 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10644 claim_zero(mlx5_flow_os_destroy_flow_action
10645 (cache_resource->action));
10646 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10647 &priv->sh->port_id_action_list, idx,
10648 cache_resource, next);
10649 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
10650 DRV_LOG(DEBUG, "port id action resource %p: removed",
10651 (void *)cache_resource);
10658 * Release push vlan action resource.
10661 * Pointer to Ethernet device.
10663 * Pointer to mlx5_flow_handle.
10666 * 1 while a reference on it exists, 0 when freed.
10669 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
10670 struct mlx5_flow_handle *handle)
10672 struct mlx5_priv *priv = dev->data->dev_private;
10673 uint32_t idx = handle->dvh.rix_push_vlan;
10674 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
10676 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10678 if (!cache_resource)
10680 MLX5_ASSERT(cache_resource->action);
10681 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
10682 (void *)cache_resource,
10683 rte_atomic32_read(&cache_resource->refcnt));
10684 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10685 claim_zero(mlx5_flow_os_destroy_flow_action
10686 (cache_resource->action));
10687 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10688 &priv->sh->push_vlan_action_list, idx,
10689 cache_resource, next);
10690 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
10691 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
10692 (void *)cache_resource);
10699 * Release the fate resource.
10702 * Pointer to Ethernet device.
10704 * Pointer to mlx5_flow_handle.
10707 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
10708 struct mlx5_flow_handle *handle)
10710 if (!handle->rix_fate)
10712 switch (handle->fate_action) {
10713 case MLX5_FLOW_FATE_DROP:
10714 mlx5_drop_action_destroy(dev);
10716 case MLX5_FLOW_FATE_QUEUE:
10717 mlx5_hrxq_release(dev, handle->rix_hrxq);
10719 case MLX5_FLOW_FATE_JUMP:
10720 flow_dv_jump_tbl_resource_release(dev, handle);
10722 case MLX5_FLOW_FATE_PORT_ID:
10723 flow_dv_port_id_action_resource_release(dev,
10724 handle->rix_port_id_action);
10726 case MLX5_FLOW_FATE_DEFAULT_MISS:
10727 flow_dv_default_miss_resource_release(dev);
10730 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
10733 handle->rix_fate = 0;
10737 * Release an sample resource.
10740 * Pointer to Ethernet device.
10742 * Pointer to mlx5_flow_handle.
10745 * 1 while a reference on it exists, 0 when freed.
10748 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
10749 struct mlx5_flow_handle *handle)
10751 struct mlx5_priv *priv = dev->data->dev_private;
10752 uint32_t idx = handle->dvh.rix_sample;
10753 struct mlx5_flow_dv_sample_resource *cache_resource;
10755 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10757 if (!cache_resource)
10759 MLX5_ASSERT(cache_resource->verbs_action);
10760 DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
10761 (void *)cache_resource,
10762 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10763 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10764 __ATOMIC_RELAXED) == 0) {
10765 if (cache_resource->verbs_action)
10766 claim_zero(mlx5_glue->destroy_flow_action
10767 (cache_resource->verbs_action));
10768 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10769 if (cache_resource->default_miss)
10770 claim_zero(mlx5_glue->destroy_flow_action
10771 (cache_resource->default_miss));
10773 if (cache_resource->normal_path_tbl)
10774 flow_dv_tbl_resource_release(dev,
10775 cache_resource->normal_path_tbl);
10777 if (cache_resource->sample_idx.rix_hrxq &&
10778 !mlx5_hrxq_release(dev,
10779 cache_resource->sample_idx.rix_hrxq))
10780 cache_resource->sample_idx.rix_hrxq = 0;
10781 if (cache_resource->sample_idx.rix_tag &&
10782 !flow_dv_tag_release(dev,
10783 cache_resource->sample_idx.rix_tag))
10784 cache_resource->sample_idx.rix_tag = 0;
10785 if (cache_resource->sample_idx.cnt) {
10786 flow_dv_counter_release(dev,
10787 cache_resource->sample_idx.cnt);
10788 cache_resource->sample_idx.cnt = 0;
10790 if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10791 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10792 &priv->sh->sample_action_list, idx,
10793 cache_resource, next);
10794 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10795 DRV_LOG(DEBUG, "sample resource %p: removed",
10796 (void *)cache_resource);
10803 * Release an destination array resource.
10806 * Pointer to Ethernet device.
10808 * Pointer to mlx5_flow_handle.
10811 * 1 while a reference on it exists, 0 when freed.
10814 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
10815 struct mlx5_flow_handle *handle)
10817 struct mlx5_priv *priv = dev->data->dev_private;
10818 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10819 struct mlx5_flow_sub_actions_idx *mdest_act_res;
10820 uint32_t idx = handle->dvh.rix_dest_array;
10823 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10825 if (!cache_resource)
10827 MLX5_ASSERT(cache_resource->action);
10828 DRV_LOG(DEBUG, "destination array resource %p: refcnt %d--",
10829 (void *)cache_resource,
10830 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10831 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10832 __ATOMIC_RELAXED) == 0) {
10833 if (cache_resource->action)
10834 claim_zero(mlx5_glue->destroy_flow_action
10835 (cache_resource->action));
10836 for (; i < cache_resource->num_of_dest; i++) {
10837 mdest_act_res = &cache_resource->sample_idx[i];
10838 if (mdest_act_res->rix_hrxq) {
10839 mlx5_hrxq_release(dev,
10840 mdest_act_res->rix_hrxq);
10841 mdest_act_res->rix_hrxq = 0;
10843 if (mdest_act_res->rix_encap_decap) {
10844 flow_dv_encap_decap_resource_release(dev,
10845 mdest_act_res->rix_encap_decap);
10846 mdest_act_res->rix_encap_decap = 0;
10848 if (mdest_act_res->rix_port_id_action) {
10849 flow_dv_port_id_action_resource_release(dev,
10850 mdest_act_res->rix_port_id_action);
10851 mdest_act_res->rix_port_id_action = 0;
10853 if (mdest_act_res->rix_tag) {
10854 flow_dv_tag_release(dev,
10855 mdest_act_res->rix_tag);
10856 mdest_act_res->rix_tag = 0;
10859 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10860 &priv->sh->dest_array_list, idx,
10861 cache_resource, next);
10862 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], idx);
10863 DRV_LOG(DEBUG, "destination array resource %p: removed",
10864 (void *)cache_resource);
10871 * Remove the flow from the NIC but keeps it in memory.
10872 * Lock free, (mutex should be acquired by caller).
10875 * Pointer to Ethernet device.
10876 * @param[in, out] flow
10877 * Pointer to flow structure.
10880 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10882 struct mlx5_flow_handle *dh;
10883 uint32_t handle_idx;
10884 struct mlx5_priv *priv = dev->data->dev_private;
10888 handle_idx = flow->dev_handles;
10889 while (handle_idx) {
10890 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10894 if (dh->drv_flow) {
10895 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10896 dh->drv_flow = NULL;
10898 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
10899 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
10900 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10901 flow_dv_fate_resource_release(dev, dh);
10902 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10903 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10904 handle_idx = dh->next.next;
10909 * Remove the flow from the NIC and the memory.
10910 * Lock free, (mutex should be acquired by caller).
10913 * Pointer to the Ethernet device structure.
10914 * @param[in, out] flow
10915 * Pointer to flow structure.
10918 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10920 struct rte_flow_shared_action *shared;
10921 struct mlx5_flow_handle *dev_handle;
10922 struct mlx5_priv *priv = dev->data->dev_private;
10926 __flow_dv_remove(dev, flow);
10927 shared = mlx5_flow_get_shared_rss(flow);
10929 __atomic_sub_fetch(&shared->refcnt, 1, __ATOMIC_RELAXED);
10930 if (flow->counter) {
10931 flow_dv_counter_release(dev, flow->counter);
10935 struct mlx5_flow_meter *fm;
10937 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10940 mlx5_flow_meter_detach(fm);
10943 while (flow->dev_handles) {
10944 uint32_t tmp_idx = flow->dev_handles;
10946 dev_handle = mlx5_ipool_get(priv->sh->ipool
10947 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10950 flow->dev_handles = dev_handle->next.next;
10951 if (dev_handle->dvh.matcher)
10952 flow_dv_matcher_release(dev, dev_handle);
10953 if (dev_handle->dvh.rix_sample)
10954 flow_dv_sample_resource_release(dev, dev_handle);
10955 if (dev_handle->dvh.rix_dest_array)
10956 flow_dv_dest_array_resource_release(dev, dev_handle);
10957 if (dev_handle->dvh.rix_encap_decap)
10958 flow_dv_encap_decap_resource_release(dev,
10959 dev_handle->dvh.rix_encap_decap);
10960 if (dev_handle->dvh.modify_hdr)
10961 flow_dv_modify_hdr_resource_release(dev, dev_handle);
10962 if (dev_handle->dvh.rix_push_vlan)
10963 flow_dv_push_vlan_action_resource_release(dev,
10965 if (dev_handle->dvh.rix_tag)
10966 flow_dv_tag_release(dev,
10967 dev_handle->dvh.rix_tag);
10968 flow_dv_fate_resource_release(dev, dev_handle);
10969 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10975 * Release array of hash RX queue objects.
10979 * Pointer to the Ethernet device structure.
10980 * @param[in, out] hrxqs
10981 * Array of hash RX queue objects.
10984 * Total number of references to hash RX queue objects in *hrxqs* array
10985 * after this operation.
10988 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
10989 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
10994 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
10995 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11005 * Release all hash RX queue objects representing shared RSS action.
11008 * Pointer to the Ethernet device structure.
11009 * @param[in, out] action
11010 * Shared RSS action to remove hash RX queue objects from.
11013 * Total number of references to hash RX queue objects stored in *action*
11014 * after this operation.
11015 * Expected to be 0 if no external references held.
11018 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11019 struct mlx5_shared_action_rss *action)
11021 return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11022 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11026 * Setup shared RSS action.
11027 * Prepare set of hash RX queue objects sufficient to handle all valid
11028 * hash_fields combinations (see enum ibv_rx_hash_fields).
11031 * Pointer to the Ethernet device structure.
11032 * @param[in, out] action
11033 * Partially initialized shared RSS action.
11034 * @param[out] error
11035 * Perform verbose error reporting if not NULL. Initialized in case of
11039 * 0 on success, otherwise negative errno value.
11042 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11043 struct mlx5_shared_action_rss *action,
11044 struct rte_flow_error *error)
11049 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11051 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11054 for (tunnel = 0; tunnel < 2; tunnel++) {
11055 hrxq_idx = mlx5_hrxq_new(dev, action->origin.key,
11056 MLX5_RSS_HASH_KEY_LEN,
11058 action->origin.queue,
11059 action->origin.queue_num,
11064 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11065 "cannot get hash queue");
11066 goto error_hrxq_new;
11068 err = __flow_dv_action_rss_hrxq_set
11069 (action, hash_fields, tunnel, hrxq_idx);
11076 __flow_dv_action_rss_hrxqs_release(dev, action);
11082 * Create shared RSS action.
11085 * Pointer to the Ethernet device structure.
11087 * Shared action configuration.
11089 * RSS action specification used to create shared action.
11090 * @param[out] error
11091 * Perform verbose error reporting if not NULL. Initialized in case of
11095 * A valid shared action handle in case of success, NULL otherwise and
11096 * rte_errno is set.
11098 static struct rte_flow_shared_action *
11099 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11100 const struct rte_flow_shared_action_conf *conf,
11101 const struct rte_flow_action_rss *rss,
11102 struct rte_flow_error *error)
11104 struct rte_flow_shared_action *shared_action = NULL;
11105 void *queue = NULL;
11106 struct mlx5_shared_action_rss *shared_rss;
11107 struct rte_flow_action_rss *origin;
11108 const uint8_t *rss_key;
11109 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11111 RTE_SET_USED(conf);
11112 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11114 shared_action = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*shared_action), 0,
11116 if (!shared_action || !queue) {
11117 rte_flow_error_set(error, ENOMEM,
11118 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11119 "cannot allocate resource memory");
11120 goto error_rss_init;
11122 shared_rss = &shared_action->rss;
11123 shared_rss->queue = queue;
11124 origin = &shared_rss->origin;
11125 origin->func = rss->func;
11126 origin->level = rss->level;
11127 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11128 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11129 /* NULL RSS key indicates default RSS key. */
11130 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11131 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11132 origin->key = &shared_rss->key[0];
11133 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11134 memcpy(shared_rss->queue, rss->queue, queue_size);
11135 origin->queue = shared_rss->queue;
11136 origin->queue_num = rss->queue_num;
11137 if (__flow_dv_action_rss_setup(dev, shared_rss, error))
11138 goto error_rss_init;
11139 shared_action->type = MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS;
11140 return shared_action;
11142 mlx5_free(shared_action);
11148 * Destroy the shared RSS action.
11149 * Release related hash RX queue objects.
11152 * Pointer to the Ethernet device structure.
11153 * @param[in] shared_rss
11154 * The shared RSS action object to be removed.
11155 * @param[out] error
11156 * Perform verbose error reporting if not NULL. Initialized in case of
11160 * 0 on success, otherwise negative errno value.
11163 __flow_dv_action_rss_release(struct rte_eth_dev *dev,
11164 struct mlx5_shared_action_rss *shared_rss,
11165 struct rte_flow_error *error)
11167 struct rte_flow_shared_action *shared_action = NULL;
11168 uint32_t old_refcnt = 1;
11169 int remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11172 return rte_flow_error_set(error, ETOOMANYREFS,
11173 RTE_FLOW_ERROR_TYPE_ACTION,
11175 "shared rss hrxq has references");
11177 shared_action = container_of(shared_rss,
11178 struct rte_flow_shared_action, rss);
11179 if (!__atomic_compare_exchange_n(&shared_action->refcnt, &old_refcnt,
11181 __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
11182 return rte_flow_error_set(error, ETOOMANYREFS,
11183 RTE_FLOW_ERROR_TYPE_ACTION,
11185 "shared rss has references");
11187 rte_free(shared_rss->queue);
11192 * Create shared action, lock free,
11193 * (mutex should be acquired by caller).
11194 * Dispatcher for action type specific call.
11197 * Pointer to the Ethernet device structure.
11199 * Shared action configuration.
11200 * @param[in] action
11201 * Action specification used to create shared action.
11202 * @param[out] error
11203 * Perform verbose error reporting if not NULL. Initialized in case of
11207 * A valid shared action handle in case of success, NULL otherwise and
11208 * rte_errno is set.
11210 static struct rte_flow_shared_action *
11211 __flow_dv_action_create(struct rte_eth_dev *dev,
11212 const struct rte_flow_shared_action_conf *conf,
11213 const struct rte_flow_action *action,
11214 struct rte_flow_error *error)
11216 struct rte_flow_shared_action *shared_action = NULL;
11217 struct mlx5_priv *priv = dev->data->dev_private;
11219 switch (action->type) {
11220 case RTE_FLOW_ACTION_TYPE_RSS:
11221 shared_action = __flow_dv_action_rss_create(dev, conf,
11226 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11227 NULL, "action type not supported");
11230 if (shared_action) {
11231 __atomic_add_fetch(&shared_action->refcnt, 1,
11233 LIST_INSERT_HEAD(&priv->shared_actions, shared_action, next);
11235 return shared_action;
11239 * Destroy the shared action.
11240 * Release action related resources on the NIC and the memory.
11241 * Lock free, (mutex should be acquired by caller).
11242 * Dispatcher for action type specific call.
11245 * Pointer to the Ethernet device structure.
11246 * @param[in] action
11247 * The shared action object to be removed.
11248 * @param[out] error
11249 * Perform verbose error reporting if not NULL. Initialized in case of
11253 * 0 on success, otherwise negative errno value.
11256 __flow_dv_action_destroy(struct rte_eth_dev *dev,
11257 struct rte_flow_shared_action *action,
11258 struct rte_flow_error *error)
11262 switch (action->type) {
11263 case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11264 ret = __flow_dv_action_rss_release(dev, &action->rss, error);
11267 return rte_flow_error_set(error, ENOTSUP,
11268 RTE_FLOW_ERROR_TYPE_ACTION,
11270 "action type not supported");
11274 LIST_REMOVE(action, next);
11280 * Updates in place shared RSS action configuration.
11283 * Pointer to the Ethernet device structure.
11284 * @param[in] shared_rss
11285 * The shared RSS action object to be updated.
11286 * @param[in] action_conf
11287 * RSS action specification used to modify *shared_rss*.
11288 * @param[out] error
11289 * Perform verbose error reporting if not NULL. Initialized in case of
11293 * 0 on success, otherwise negative errno value.
11294 * @note: currently only support update of RSS queues.
11297 __flow_dv_action_rss_update(struct rte_eth_dev *dev,
11298 struct mlx5_shared_action_rss *shared_rss,
11299 const struct rte_flow_action_rss *action_conf,
11300 struct rte_flow_error *error)
11304 void *queue = NULL;
11305 const uint8_t *rss_key;
11306 uint32_t rss_key_len;
11307 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11309 queue = mlx5_malloc(MLX5_MEM_ZERO,
11310 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11313 return rte_flow_error_set(error, ENOMEM,
11314 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11316 "cannot allocate resource memory");
11317 if (action_conf->key) {
11318 rss_key = action_conf->key;
11319 rss_key_len = action_conf->key_len;
11321 rss_key = rss_hash_default_key;
11322 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11324 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11326 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11329 for (tunnel = 0; tunnel < 2; tunnel++) {
11330 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11331 (shared_rss, hash_fields, tunnel);
11332 MLX5_ASSERT(hrxq_idx);
11333 ret = mlx5_hrxq_modify
11335 rss_key, rss_key_len,
11337 action_conf->queue, action_conf->queue_num);
11340 return rte_flow_error_set
11342 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11343 "cannot update hash queue");
11347 mlx5_free(shared_rss->queue);
11348 shared_rss->queue = queue;
11349 memcpy(shared_rss->queue, action_conf->queue, queue_size);
11350 shared_rss->origin.queue = shared_rss->queue;
11351 shared_rss->origin.queue_num = action_conf->queue_num;
11356 * Updates in place shared action configuration, lock free,
11357 * (mutex should be acquired by caller).
11360 * Pointer to the Ethernet device structure.
11361 * @param[in] action
11362 * The shared action object to be updated.
11363 * @param[in] action_conf
11364 * Action specification used to modify *action*.
11365 * *action_conf* should be of type correlating with type of the *action*,
11366 * otherwise considered as invalid.
11367 * @param[out] error
11368 * Perform verbose error reporting if not NULL. Initialized in case of
11372 * 0 on success, otherwise negative errno value.
11375 __flow_dv_action_update(struct rte_eth_dev *dev,
11376 struct rte_flow_shared_action *action,
11377 const void *action_conf,
11378 struct rte_flow_error *error)
11380 switch (action->type) {
11381 case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11382 return __flow_dv_action_rss_update(dev, &action->rss,
11383 action_conf, error);
11385 return rte_flow_error_set(error, ENOTSUP,
11386 RTE_FLOW_ERROR_TYPE_ACTION,
11388 "action type not supported");
11392 * Query a dv flow rule for its statistics via devx.
11395 * Pointer to Ethernet device.
11397 * Pointer to the sub flow.
11399 * data retrieved by the query.
11400 * @param[out] error
11401 * Perform verbose error reporting if not NULL.
11404 * 0 on success, a negative errno value otherwise and rte_errno is set.
11407 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11408 void *data, struct rte_flow_error *error)
11410 struct mlx5_priv *priv = dev->data->dev_private;
11411 struct rte_flow_query_count *qc = data;
11413 if (!priv->config.devx)
11414 return rte_flow_error_set(error, ENOTSUP,
11415 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11417 "counters are not supported");
11418 if (flow->counter) {
11419 uint64_t pkts, bytes;
11420 struct mlx5_flow_counter *cnt;
11422 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11424 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11428 return rte_flow_error_set(error, -err,
11429 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11430 NULL, "cannot read counters");
11433 qc->hits = pkts - cnt->hits;
11434 qc->bytes = bytes - cnt->bytes;
11437 cnt->bytes = bytes;
11441 return rte_flow_error_set(error, EINVAL,
11442 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11444 "counters are not available");
11448 * Query a flow rule AGE action for aging information.
11451 * Pointer to Ethernet device.
11453 * Pointer to the sub flow.
11455 * data retrieved by the query.
11456 * @param[out] error
11457 * Perform verbose error reporting if not NULL.
11460 * 0 on success, a negative errno value otherwise and rte_errno is set.
11463 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11464 void *data, struct rte_flow_error *error)
11466 struct rte_flow_query_age *resp = data;
11468 if (flow->counter) {
11469 struct mlx5_age_param *age_param =
11470 flow_dv_counter_idx_get_age(dev, flow->counter);
11472 if (!age_param || !age_param->timeout)
11473 return rte_flow_error_set
11475 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11476 NULL, "cannot read age data");
11477 resp->aged = __atomic_load_n(&age_param->state,
11478 __ATOMIC_RELAXED) ==
11480 resp->sec_since_last_hit_valid = !resp->aged;
11481 if (resp->sec_since_last_hit_valid)
11482 resp->sec_since_last_hit =
11483 __atomic_load_n(&age_param->sec_since_last_hit,
11487 return rte_flow_error_set(error, EINVAL,
11488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11490 "age data not available");
11496 * @see rte_flow_query()
11497 * @see rte_flow_ops
11500 flow_dv_query(struct rte_eth_dev *dev,
11501 struct rte_flow *flow __rte_unused,
11502 const struct rte_flow_action *actions __rte_unused,
11503 void *data __rte_unused,
11504 struct rte_flow_error *error __rte_unused)
11508 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11509 switch (actions->type) {
11510 case RTE_FLOW_ACTION_TYPE_VOID:
11512 case RTE_FLOW_ACTION_TYPE_COUNT:
11513 ret = flow_dv_query_count(dev, flow, data, error);
11515 case RTE_FLOW_ACTION_TYPE_AGE:
11516 ret = flow_dv_query_age(dev, flow, data, error);
11519 return rte_flow_error_set(error, ENOTSUP,
11520 RTE_FLOW_ERROR_TYPE_ACTION,
11522 "action not supported");
11529 * Destroy the meter table set.
11530 * Lock free, (mutex should be acquired by caller).
11533 * Pointer to Ethernet device.
11535 * Pointer to the meter table set.
11541 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11542 struct mlx5_meter_domains_infos *tbl)
11544 struct mlx5_priv *priv = dev->data->dev_private;
11545 struct mlx5_meter_domains_infos *mtd =
11546 (struct mlx5_meter_domains_infos *)tbl;
11548 if (!mtd || !priv->config.dv_flow_en)
11550 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11551 claim_zero(mlx5_flow_os_destroy_flow
11552 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11553 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11554 claim_zero(mlx5_flow_os_destroy_flow
11555 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11556 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11557 claim_zero(mlx5_flow_os_destroy_flow
11558 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11559 if (mtd->egress.color_matcher)
11560 claim_zero(mlx5_flow_os_destroy_flow_matcher
11561 (mtd->egress.color_matcher));
11562 if (mtd->egress.any_matcher)
11563 claim_zero(mlx5_flow_os_destroy_flow_matcher
11564 (mtd->egress.any_matcher));
11565 if (mtd->egress.tbl)
11566 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
11567 if (mtd->egress.sfx_tbl)
11568 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
11569 if (mtd->ingress.color_matcher)
11570 claim_zero(mlx5_flow_os_destroy_flow_matcher
11571 (mtd->ingress.color_matcher));
11572 if (mtd->ingress.any_matcher)
11573 claim_zero(mlx5_flow_os_destroy_flow_matcher
11574 (mtd->ingress.any_matcher));
11575 if (mtd->ingress.tbl)
11576 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
11577 if (mtd->ingress.sfx_tbl)
11578 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
11579 if (mtd->transfer.color_matcher)
11580 claim_zero(mlx5_flow_os_destroy_flow_matcher
11581 (mtd->transfer.color_matcher));
11582 if (mtd->transfer.any_matcher)
11583 claim_zero(mlx5_flow_os_destroy_flow_matcher
11584 (mtd->transfer.any_matcher));
11585 if (mtd->transfer.tbl)
11586 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
11587 if (mtd->transfer.sfx_tbl)
11588 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
11589 if (mtd->drop_actn)
11590 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11595 /* Number of meter flow actions, count and jump or count and drop. */
11596 #define METER_ACTIONS 2
11599 * Create specify domain meter table and suffix table.
11602 * Pointer to Ethernet device.
11603 * @param[in,out] mtb
11604 * Pointer to DV meter table set.
11605 * @param[in] egress
11607 * @param[in] transfer
11609 * @param[in] color_reg_c_idx
11610 * Reg C index for color match.
11613 * 0 on success, -1 otherwise and rte_errno is set.
11616 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11617 struct mlx5_meter_domains_infos *mtb,
11618 uint8_t egress, uint8_t transfer,
11619 uint32_t color_reg_c_idx)
11621 struct mlx5_priv *priv = dev->data->dev_private;
11622 struct mlx5_dev_ctx_shared *sh = priv->sh;
11623 struct mlx5_flow_dv_match_params mask = {
11624 .size = sizeof(mask.buf),
11626 struct mlx5_flow_dv_match_params value = {
11627 .size = sizeof(value.buf),
11629 struct mlx5dv_flow_matcher_attr dv_attr = {
11630 .type = IBV_FLOW_ATTR_NORMAL,
11632 .match_criteria_enable = 0,
11633 .match_mask = (void *)&mask,
11635 void *actions[METER_ACTIONS];
11636 struct mlx5_meter_domain_info *dtb;
11637 struct rte_flow_error error;
11642 dtb = &mtb->transfer;
11644 dtb = &mtb->egress;
11646 dtb = &mtb->ingress;
11647 /* Create the meter table with METER level. */
11648 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
11649 egress, transfer, false, NULL, 0,
11652 DRV_LOG(ERR, "Failed to create meter policer table.");
11655 /* Create the meter suffix table with SUFFIX level. */
11656 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
11657 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
11658 egress, transfer, false, NULL, 0,
11660 if (!dtb->sfx_tbl) {
11661 DRV_LOG(ERR, "Failed to create meter suffix table.");
11664 /* Create matchers, Any and Color. */
11665 dv_attr.priority = 3;
11666 dv_attr.match_criteria_enable = 0;
11667 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11668 &dtb->any_matcher);
11670 DRV_LOG(ERR, "Failed to create meter"
11671 " policer default matcher.");
11674 dv_attr.priority = 0;
11675 dv_attr.match_criteria_enable =
11676 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
11677 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
11678 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
11679 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11680 &dtb->color_matcher);
11682 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
11685 if (mtb->count_actns[RTE_MTR_DROPPED])
11686 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
11687 actions[i++] = mtb->drop_actn;
11688 /* Default rule: lowest priority, match any, actions: drop. */
11689 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
11691 &dtb->policer_rules[RTE_MTR_DROPPED]);
11693 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
11702 * Create the needed meter and suffix tables.
11703 * Lock free, (mutex should be acquired by caller).
11706 * Pointer to Ethernet device.
11708 * Pointer to the flow meter.
11711 * Pointer to table set on success, NULL otherwise and rte_errno is set.
11713 static struct mlx5_meter_domains_infos *
11714 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
11715 const struct mlx5_flow_meter *fm)
11717 struct mlx5_priv *priv = dev->data->dev_private;
11718 struct mlx5_meter_domains_infos *mtb;
11722 if (!priv->mtr_en) {
11723 rte_errno = ENOTSUP;
11726 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
11728 DRV_LOG(ERR, "Failed to allocate memory for meter.");
11731 /* Create meter count actions */
11732 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
11733 struct mlx5_flow_counter *cnt;
11734 if (!fm->policer_stats.cnt[i])
11736 cnt = flow_dv_counter_get_by_idx(dev,
11737 fm->policer_stats.cnt[i], NULL);
11738 mtb->count_actns[i] = cnt->action;
11740 /* Create drop action. */
11741 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
11743 DRV_LOG(ERR, "Failed to create drop action.");
11746 /* Egress meter table. */
11747 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
11749 DRV_LOG(ERR, "Failed to prepare egress meter table.");
11752 /* Ingress meter table. */
11753 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
11755 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
11758 /* FDB meter table. */
11759 if (priv->config.dv_esw_en) {
11760 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
11761 priv->mtr_color_reg);
11763 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
11769 flow_dv_destroy_mtr_tbl(dev, mtb);
11774 * Destroy domain policer rule.
11777 * Pointer to domain table.
11780 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
11784 for (i = 0; i < RTE_MTR_DROPPED; i++) {
11785 if (dt->policer_rules[i]) {
11786 claim_zero(mlx5_flow_os_destroy_flow
11787 (dt->policer_rules[i]));
11788 dt->policer_rules[i] = NULL;
11791 if (dt->jump_actn) {
11792 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
11793 dt->jump_actn = NULL;
11798 * Destroy policer rules.
11801 * Pointer to Ethernet device.
11803 * Pointer to flow meter structure.
11805 * Pointer to flow attributes.
11811 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
11812 const struct mlx5_flow_meter *fm,
11813 const struct rte_flow_attr *attr)
11815 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
11820 flow_dv_destroy_domain_policer_rule(&mtb->egress);
11822 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
11823 if (attr->transfer)
11824 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
11829 * Create specify domain meter policer rule.
11832 * Pointer to flow meter structure.
11834 * Pointer to DV meter table set.
11835 * @param[in] mtr_reg_c
11836 * Color match REG_C.
11839 * 0 on success, -1 otherwise.
11842 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
11843 struct mlx5_meter_domain_info *dtb,
11846 struct mlx5_flow_dv_match_params matcher = {
11847 .size = sizeof(matcher.buf),
11849 struct mlx5_flow_dv_match_params value = {
11850 .size = sizeof(value.buf),
11852 struct mlx5_meter_domains_infos *mtb = fm->mfts;
11853 void *actions[METER_ACTIONS];
11857 /* Create jump action. */
11858 if (!dtb->jump_actn)
11859 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11860 (dtb->sfx_tbl->obj, &dtb->jump_actn);
11862 DRV_LOG(ERR, "Failed to create policer jump action.");
11865 for (i = 0; i < RTE_MTR_DROPPED; i++) {
11868 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
11869 rte_col_2_mlx5_col(i), UINT8_MAX);
11870 if (mtb->count_actns[i])
11871 actions[j++] = mtb->count_actns[i];
11872 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
11873 actions[j++] = mtb->drop_actn;
11875 actions[j++] = dtb->jump_actn;
11876 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
11877 (void *)&value, j, actions,
11878 &dtb->policer_rules[i]);
11880 DRV_LOG(ERR, "Failed to create policer rule.");
11891 * Create policer rules.
11894 * Pointer to Ethernet device.
11896 * Pointer to flow meter structure.
11898 * Pointer to flow attributes.
11901 * 0 on success, -1 otherwise.
11904 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
11905 struct mlx5_flow_meter *fm,
11906 const struct rte_flow_attr *attr)
11908 struct mlx5_priv *priv = dev->data->dev_private;
11909 struct mlx5_meter_domains_infos *mtb = fm->mfts;
11912 if (attr->egress) {
11913 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
11914 priv->mtr_color_reg);
11916 DRV_LOG(ERR, "Failed to create egress policer.");
11920 if (attr->ingress) {
11921 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
11922 priv->mtr_color_reg);
11924 DRV_LOG(ERR, "Failed to create ingress policer.");
11928 if (attr->transfer) {
11929 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
11930 priv->mtr_color_reg);
11932 DRV_LOG(ERR, "Failed to create transfer policer.");
11938 flow_dv_destroy_policer_rules(dev, fm, attr);
11943 * Validate the batch counter support in root table.
11945 * Create a simple flow with invalid counter and drop action on root table to
11946 * validate if batch counter with offset on root table is supported or not.
11949 * Pointer to rte_eth_dev structure.
11952 * 0 on success, a negative errno value otherwise and rte_errno is set.
11955 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
11957 struct mlx5_priv *priv = dev->data->dev_private;
11958 struct mlx5_dev_ctx_shared *sh = priv->sh;
11959 struct mlx5_flow_dv_match_params mask = {
11960 .size = sizeof(mask.buf),
11962 struct mlx5_flow_dv_match_params value = {
11963 .size = sizeof(value.buf),
11965 struct mlx5dv_flow_matcher_attr dv_attr = {
11966 .type = IBV_FLOW_ATTR_NORMAL,
11968 .match_criteria_enable = 0,
11969 .match_mask = (void *)&mask,
11971 void *actions[2] = { 0 };
11972 struct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;
11973 struct mlx5_devx_obj *dcs = NULL;
11974 void *matcher = NULL;
11978 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, NULL);
11981 dest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false, NULL, 0, NULL);
11984 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
11987 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
11991 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11992 (dest_tbl->obj, &actions[1]);
11995 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
11996 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12000 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12004 * If batch counter with offset is not supported, the driver will not
12005 * validate the invalid offset value, flow create should success.
12006 * In this case, it means batch counter is not supported in root table.
12008 * Otherwise, if flow create is failed, counter offset is supported.
12011 DRV_LOG(INFO, "Batch counter is not supported in root "
12012 "table. Switch to fallback mode.");
12013 rte_errno = ENOTSUP;
12015 claim_zero(mlx5_flow_os_destroy_flow(flow));
12017 /* Check matcher to make sure validate fail at flow create. */
12018 if (!matcher || (matcher && errno != EINVAL))
12019 DRV_LOG(ERR, "Unexpected error in counter offset "
12020 "support detection");
12023 for (i = 0; i < 2; i++) {
12025 claim_zero(mlx5_flow_os_destroy_flow_action
12029 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12031 flow_dv_tbl_resource_release(dev, tbl);
12033 flow_dv_tbl_resource_release(dev, dest_tbl);
12035 claim_zero(mlx5_devx_cmd_destroy(dcs));
12040 * Query a devx counter.
12043 * Pointer to the Ethernet device structure.
12045 * Index to the flow counter.
12047 * Set to clear the counter statistics.
12049 * The statistics value of packets.
12050 * @param[out] bytes
12051 * The statistics value of bytes.
12054 * 0 on success, otherwise return -1.
12057 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12058 uint64_t *pkts, uint64_t *bytes)
12060 struct mlx5_priv *priv = dev->data->dev_private;
12061 struct mlx5_flow_counter *cnt;
12062 uint64_t inn_pkts, inn_bytes;
12065 if (!priv->config.devx)
12068 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12071 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12072 *pkts = inn_pkts - cnt->hits;
12073 *bytes = inn_bytes - cnt->bytes;
12075 cnt->hits = inn_pkts;
12076 cnt->bytes = inn_bytes;
12082 * Get aged-out flows.
12085 * Pointer to the Ethernet device structure.
12086 * @param[in] context
12087 * The address of an array of pointers to the aged-out flows contexts.
12088 * @param[in] nb_contexts
12089 * The length of context array pointers.
12090 * @param[out] error
12091 * Perform verbose error reporting if not NULL. Initialized in case of
12095 * how many contexts get in success, otherwise negative errno value.
12096 * if nb_contexts is 0, return the amount of all aged contexts.
12097 * if nb_contexts is not 0 , return the amount of aged flows reported
12098 * in the context array.
12099 * @note: only stub for now
12102 flow_get_aged_flows(struct rte_eth_dev *dev,
12104 uint32_t nb_contexts,
12105 struct rte_flow_error *error)
12107 struct mlx5_priv *priv = dev->data->dev_private;
12108 struct mlx5_age_info *age_info;
12109 struct mlx5_age_param *age_param;
12110 struct mlx5_flow_counter *counter;
12113 if (nb_contexts && !context)
12114 return rte_flow_error_set(error, EINVAL,
12115 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12117 "Should assign at least one flow or"
12118 " context to get if nb_contexts != 0");
12119 age_info = GET_PORT_AGE_INFO(priv);
12120 rte_spinlock_lock(&age_info->aged_sl);
12121 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12124 age_param = MLX5_CNT_TO_AGE(counter);
12125 context[nb_flows - 1] = age_param->context;
12126 if (!(--nb_contexts))
12130 rte_spinlock_unlock(&age_info->aged_sl);
12131 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12136 * Mutex-protected thunk to lock-free __flow_dv_translate().
12139 flow_dv_translate(struct rte_eth_dev *dev,
12140 struct mlx5_flow *dev_flow,
12141 const struct rte_flow_attr *attr,
12142 const struct rte_flow_item items[],
12143 const struct rte_flow_action actions[],
12144 struct rte_flow_error *error)
12148 flow_dv_shared_lock(dev);
12149 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
12150 flow_dv_shared_unlock(dev);
12155 * Mutex-protected thunk to lock-free __flow_dv_apply().
12158 flow_dv_apply(struct rte_eth_dev *dev,
12159 struct rte_flow *flow,
12160 struct rte_flow_error *error)
12164 flow_dv_shared_lock(dev);
12165 ret = __flow_dv_apply(dev, flow, error);
12166 flow_dv_shared_unlock(dev);
12171 * Mutex-protected thunk to lock-free __flow_dv_remove().
12174 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12176 flow_dv_shared_lock(dev);
12177 __flow_dv_remove(dev, flow);
12178 flow_dv_shared_unlock(dev);
12182 * Mutex-protected thunk to lock-free __flow_dv_destroy().
12185 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12187 flow_dv_shared_lock(dev);
12188 __flow_dv_destroy(dev, flow);
12189 flow_dv_shared_unlock(dev);
12193 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12196 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12200 flow_dv_shared_lock(dev);
12201 cnt = flow_dv_counter_alloc(dev, 0);
12202 flow_dv_shared_unlock(dev);
12207 * Mutex-protected thunk to lock-free flow_dv_counter_release().
12210 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
12212 flow_dv_shared_lock(dev);
12213 flow_dv_counter_release(dev, cnt);
12214 flow_dv_shared_unlock(dev);
12218 * Validate shared action.
12219 * Dispatcher for action type specific validation.
12222 * Pointer to the Ethernet device structure.
12224 * Shared action configuration.
12225 * @param[in] action
12226 * The shared action object to validate.
12227 * @param[out] error
12228 * Perform verbose error reporting if not NULL. Initialized in case of
12232 * 0 on success, otherwise negative errno value.
12235 flow_dv_action_validate(struct rte_eth_dev *dev,
12236 const struct rte_flow_shared_action_conf *conf,
12237 const struct rte_flow_action *action,
12238 struct rte_flow_error *error)
12240 RTE_SET_USED(conf);
12241 switch (action->type) {
12242 case RTE_FLOW_ACTION_TYPE_RSS:
12243 return mlx5_validate_action_rss(dev, action, error);
12245 return rte_flow_error_set(error, ENOTSUP,
12246 RTE_FLOW_ERROR_TYPE_ACTION,
12248 "action type not supported");
12253 * Mutex-protected thunk to lock-free __flow_dv_action_create().
12255 static struct rte_flow_shared_action *
12256 flow_dv_action_create(struct rte_eth_dev *dev,
12257 const struct rte_flow_shared_action_conf *conf,
12258 const struct rte_flow_action *action,
12259 struct rte_flow_error *error)
12261 struct rte_flow_shared_action *shared_action = NULL;
12263 flow_dv_shared_lock(dev);
12264 shared_action = __flow_dv_action_create(dev, conf, action, error);
12265 flow_dv_shared_unlock(dev);
12266 return shared_action;
12270 * Mutex-protected thunk to lock-free __flow_dv_action_destroy().
12273 flow_dv_action_destroy(struct rte_eth_dev *dev,
12274 struct rte_flow_shared_action *action,
12275 struct rte_flow_error *error)
12279 flow_dv_shared_lock(dev);
12280 ret = __flow_dv_action_destroy(dev, action, error);
12281 flow_dv_shared_unlock(dev);
12286 * Mutex-protected thunk to lock-free __flow_dv_action_update().
12289 flow_dv_action_update(struct rte_eth_dev *dev,
12290 struct rte_flow_shared_action *action,
12291 const void *action_conf,
12292 struct rte_flow_error *error)
12296 flow_dv_shared_lock(dev);
12297 ret = __flow_dv_action_update(dev, action, action_conf,
12299 flow_dv_shared_unlock(dev);
12303 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12304 .validate = flow_dv_validate,
12305 .prepare = flow_dv_prepare,
12306 .translate = flow_dv_translate,
12307 .apply = flow_dv_apply,
12308 .remove = flow_dv_remove,
12309 .destroy = flow_dv_destroy,
12310 .query = flow_dv_query,
12311 .create_mtr_tbls = flow_dv_create_mtr_tbl,
12312 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12313 .create_policer_rules = flow_dv_create_policer_rules,
12314 .destroy_policer_rules = flow_dv_destroy_policer_rules,
12315 .counter_alloc = flow_dv_counter_allocate,
12316 .counter_free = flow_dv_counter_free,
12317 .counter_query = flow_dv_counter_query,
12318 .get_aged_flows = flow_get_aged_flows,
12319 .action_validate = flow_dv_action_validate,
12320 .action_create = flow_dv_action_create,
12321 .action_destroy = flow_dv_action_destroy,
12322 .action_update = flow_dv_action_update,
12325 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */