1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
55 sizeof(struct rte_flow_item_ipv4))
56 /* VLAN header definitions */
57 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
58 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
59 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
60 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
61 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
76 * Initialize flow attributes structure according to flow items' types.
78 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
79 * mode. For tunnel mode, the items to be modified are the outermost ones.
82 * Pointer to item specification.
84 * Pointer to flow attributes structure.
87 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
89 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
91 case RTE_FLOW_ITEM_TYPE_IPV4:
95 case RTE_FLOW_ITEM_TYPE_IPV6:
99 case RTE_FLOW_ITEM_TYPE_UDP:
103 case RTE_FLOW_ITEM_TYPE_TCP:
115 * Convert rte_mtr_color to mlx5 color.
124 rte_col_2_mlx5_col(enum rte_color rcol)
127 case RTE_COLOR_GREEN:
128 return MLX5_FLOW_COLOR_GREEN;
129 case RTE_COLOR_YELLOW:
130 return MLX5_FLOW_COLOR_YELLOW;
132 return MLX5_FLOW_COLOR_RED;
136 return MLX5_FLOW_COLOR_UNDEFINED;
139 struct field_modify_info {
140 uint32_t size; /* Size of field in protocol header, in bytes. */
141 uint32_t offset; /* Offset of field in protocol header, in bytes. */
142 enum mlx5_modification_field id;
145 struct field_modify_info modify_eth[] = {
146 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
147 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
148 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
149 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
153 struct field_modify_info modify_vlan_out_first_vid[] = {
154 /* Size in bits !!! */
155 {12, 0, MLX5_MODI_OUT_FIRST_VID},
159 struct field_modify_info modify_ipv4[] = {
160 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
161 {4, 12, MLX5_MODI_OUT_SIPV4},
162 {4, 16, MLX5_MODI_OUT_DIPV4},
166 struct field_modify_info modify_ipv6[] = {
167 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
168 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
169 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
170 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
171 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
172 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
173 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
174 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
175 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
179 struct field_modify_info modify_udp[] = {
180 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
181 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
185 struct field_modify_info modify_tcp[] = {
186 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
187 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
188 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
189 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
194 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
195 uint8_t next_protocol, uint64_t *item_flags,
198 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
199 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
200 if (next_protocol == IPPROTO_IPIP) {
201 *item_flags |= MLX5_FLOW_LAYER_IPIP;
204 if (next_protocol == IPPROTO_IPV6) {
205 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
211 * Acquire the synchronizing object to protect multithreaded access
212 * to shared dv context. Lock occurs only if context is actually
213 * shared, i.e. we have multiport IB device and representors are
217 * Pointer to the rte_eth_dev structure.
220 flow_dv_shared_lock(struct rte_eth_dev *dev)
222 struct mlx5_priv *priv = dev->data->dev_private;
223 struct mlx5_ibv_shared *sh = priv->sh;
225 if (sh->dv_refcnt > 1) {
228 ret = pthread_mutex_lock(&sh->dv_mutex);
235 flow_dv_shared_unlock(struct rte_eth_dev *dev)
237 struct mlx5_priv *priv = dev->data->dev_private;
238 struct mlx5_ibv_shared *sh = priv->sh;
240 if (sh->dv_refcnt > 1) {
243 ret = pthread_mutex_unlock(&sh->dv_mutex);
249 /* Update VLAN's VID/PCP based on input rte_flow_action.
252 * Pointer to struct rte_flow_action.
254 * Pointer to struct rte_vlan_hdr.
257 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
258 struct rte_vlan_hdr *vlan)
261 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
263 ((const struct rte_flow_action_of_set_vlan_pcp *)
264 action->conf)->vlan_pcp;
265 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
266 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
267 vlan->vlan_tci |= vlan_tci;
268 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
269 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
270 vlan->vlan_tci |= rte_be_to_cpu_16
271 (((const struct rte_flow_action_of_set_vlan_vid *)
272 action->conf)->vlan_vid);
277 * Fetch 1, 2, 3 or 4 byte field from the byte array
278 * and return as unsigned integer in host-endian format.
281 * Pointer to data array.
283 * Size of field to extract.
286 * converted field in host endian format.
288 static inline uint32_t
289 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
298 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
301 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
302 ret = (ret << 8) | *(data + sizeof(uint16_t));
305 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
316 * Convert modify-header action to DV specification.
318 * Data length of each action is determined by provided field description
319 * and the item mask. Data bit offset and width of each action is determined
320 * by provided item mask.
323 * Pointer to item specification.
325 * Pointer to field modification information.
326 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
327 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
328 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
330 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
331 * Negative offset value sets the same offset as source offset.
332 * size field is ignored, value is taken from source field.
333 * @param[in,out] resource
334 * Pointer to the modify-header resource.
336 * Type of modification.
338 * Pointer to the error structure.
341 * 0 on success, a negative errno value otherwise and rte_errno is set.
344 flow_dv_convert_modify_action(struct rte_flow_item *item,
345 struct field_modify_info *field,
346 struct field_modify_info *dcopy,
347 struct mlx5_flow_dv_modify_hdr_resource *resource,
348 uint32_t type, struct rte_flow_error *error)
350 uint32_t i = resource->actions_num;
351 struct mlx5_modification_cmd *actions = resource->actions;
354 * The item and mask are provided in big-endian format.
355 * The fields should be presented as in big-endian format either.
356 * Mask must be always present, it defines the actual field width.
366 if (i >= MLX5_MODIFY_NUM)
367 return rte_flow_error_set(error, EINVAL,
368 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
369 "too many items to modify");
370 /* Fetch variable byte size mask from the array. */
371 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
372 field->offset, field->size);
377 /* Deduce actual data width in bits from mask value. */
378 off_b = rte_bsf32(mask);
379 size_b = sizeof(uint32_t) * CHAR_BIT -
380 off_b - __builtin_clz(mask);
382 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
383 actions[i].action_type = type;
384 actions[i].field = field->id;
385 actions[i].offset = off_b;
386 actions[i].length = size_b;
387 /* Convert entire record to expected big-endian format. */
388 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
389 if (type == MLX5_MODIFICATION_TYPE_COPY) {
391 actions[i].dst_field = dcopy->id;
392 actions[i].dst_offset =
393 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
394 /* Convert entire record to big-endian format. */
395 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
398 data = flow_dv_fetch_field((const uint8_t *)item->spec +
399 field->offset, field->size);
400 /* Shift out the trailing masked bits from data. */
401 data = (data & mask) >> off_b;
402 actions[i].data1 = rte_cpu_to_be_32(data);
406 } while (field->size);
407 resource->actions_num = i;
408 if (!resource->actions_num)
409 return rte_flow_error_set(error, EINVAL,
410 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
411 "invalid modification flow item");
416 * Convert modify-header set IPv4 address action to DV specification.
418 * @param[in,out] resource
419 * Pointer to the modify-header resource.
421 * Pointer to action specification.
423 * Pointer to the error structure.
426 * 0 on success, a negative errno value otherwise and rte_errno is set.
429 flow_dv_convert_action_modify_ipv4
430 (struct mlx5_flow_dv_modify_hdr_resource *resource,
431 const struct rte_flow_action *action,
432 struct rte_flow_error *error)
434 const struct rte_flow_action_set_ipv4 *conf =
435 (const struct rte_flow_action_set_ipv4 *)(action->conf);
436 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
437 struct rte_flow_item_ipv4 ipv4;
438 struct rte_flow_item_ipv4 ipv4_mask;
440 memset(&ipv4, 0, sizeof(ipv4));
441 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
442 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
443 ipv4.hdr.src_addr = conf->ipv4_addr;
444 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
446 ipv4.hdr.dst_addr = conf->ipv4_addr;
447 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
450 item.mask = &ipv4_mask;
451 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
452 MLX5_MODIFICATION_TYPE_SET, error);
456 * Convert modify-header set IPv6 address action to DV specification.
458 * @param[in,out] resource
459 * Pointer to the modify-header resource.
461 * Pointer to action specification.
463 * Pointer to the error structure.
466 * 0 on success, a negative errno value otherwise and rte_errno is set.
469 flow_dv_convert_action_modify_ipv6
470 (struct mlx5_flow_dv_modify_hdr_resource *resource,
471 const struct rte_flow_action *action,
472 struct rte_flow_error *error)
474 const struct rte_flow_action_set_ipv6 *conf =
475 (const struct rte_flow_action_set_ipv6 *)(action->conf);
476 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
477 struct rte_flow_item_ipv6 ipv6;
478 struct rte_flow_item_ipv6 ipv6_mask;
480 memset(&ipv6, 0, sizeof(ipv6));
481 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
482 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
483 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
484 sizeof(ipv6.hdr.src_addr));
485 memcpy(&ipv6_mask.hdr.src_addr,
486 &rte_flow_item_ipv6_mask.hdr.src_addr,
487 sizeof(ipv6.hdr.src_addr));
489 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
490 sizeof(ipv6.hdr.dst_addr));
491 memcpy(&ipv6_mask.hdr.dst_addr,
492 &rte_flow_item_ipv6_mask.hdr.dst_addr,
493 sizeof(ipv6.hdr.dst_addr));
496 item.mask = &ipv6_mask;
497 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
498 MLX5_MODIFICATION_TYPE_SET, error);
502 * Convert modify-header set MAC address action to DV specification.
504 * @param[in,out] resource
505 * Pointer to the modify-header resource.
507 * Pointer to action specification.
509 * Pointer to the error structure.
512 * 0 on success, a negative errno value otherwise and rte_errno is set.
515 flow_dv_convert_action_modify_mac
516 (struct mlx5_flow_dv_modify_hdr_resource *resource,
517 const struct rte_flow_action *action,
518 struct rte_flow_error *error)
520 const struct rte_flow_action_set_mac *conf =
521 (const struct rte_flow_action_set_mac *)(action->conf);
522 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
523 struct rte_flow_item_eth eth;
524 struct rte_flow_item_eth eth_mask;
526 memset(ð, 0, sizeof(eth));
527 memset(ð_mask, 0, sizeof(eth_mask));
528 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
529 memcpy(ð.src.addr_bytes, &conf->mac_addr,
530 sizeof(eth.src.addr_bytes));
531 memcpy(ð_mask.src.addr_bytes,
532 &rte_flow_item_eth_mask.src.addr_bytes,
533 sizeof(eth_mask.src.addr_bytes));
535 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
536 sizeof(eth.dst.addr_bytes));
537 memcpy(ð_mask.dst.addr_bytes,
538 &rte_flow_item_eth_mask.dst.addr_bytes,
539 sizeof(eth_mask.dst.addr_bytes));
542 item.mask = ð_mask;
543 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
544 MLX5_MODIFICATION_TYPE_SET, error);
548 * Convert modify-header set VLAN VID action to DV specification.
550 * @param[in,out] resource
551 * Pointer to the modify-header resource.
553 * Pointer to action specification.
555 * Pointer to the error structure.
558 * 0 on success, a negative errno value otherwise and rte_errno is set.
561 flow_dv_convert_action_modify_vlan_vid
562 (struct mlx5_flow_dv_modify_hdr_resource *resource,
563 const struct rte_flow_action *action,
564 struct rte_flow_error *error)
566 const struct rte_flow_action_of_set_vlan_vid *conf =
567 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
568 int i = resource->actions_num;
569 struct mlx5_modification_cmd *actions = &resource->actions[i];
570 struct field_modify_info *field = modify_vlan_out_first_vid;
572 if (i >= MLX5_MODIFY_NUM)
573 return rte_flow_error_set(error, EINVAL,
574 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
575 "too many items to modify");
576 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
577 actions[i].field = field->id;
578 actions[i].length = field->size;
579 actions[i].offset = field->offset;
580 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
581 actions[i].data1 = conf->vlan_vid;
582 actions[i].data1 = actions[i].data1 << 16;
583 resource->actions_num = ++i;
588 * Convert modify-header set TP action to DV specification.
590 * @param[in,out] resource
591 * Pointer to the modify-header resource.
593 * Pointer to action specification.
595 * Pointer to rte_flow_item objects list.
597 * Pointer to flow attributes structure.
599 * Pointer to the error structure.
602 * 0 on success, a negative errno value otherwise and rte_errno is set.
605 flow_dv_convert_action_modify_tp
606 (struct mlx5_flow_dv_modify_hdr_resource *resource,
607 const struct rte_flow_action *action,
608 const struct rte_flow_item *items,
609 union flow_dv_attr *attr,
610 struct rte_flow_error *error)
612 const struct rte_flow_action_set_tp *conf =
613 (const struct rte_flow_action_set_tp *)(action->conf);
614 struct rte_flow_item item;
615 struct rte_flow_item_udp udp;
616 struct rte_flow_item_udp udp_mask;
617 struct rte_flow_item_tcp tcp;
618 struct rte_flow_item_tcp tcp_mask;
619 struct field_modify_info *field;
622 flow_dv_attr_init(items, attr);
624 memset(&udp, 0, sizeof(udp));
625 memset(&udp_mask, 0, sizeof(udp_mask));
626 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
627 udp.hdr.src_port = conf->port;
628 udp_mask.hdr.src_port =
629 rte_flow_item_udp_mask.hdr.src_port;
631 udp.hdr.dst_port = conf->port;
632 udp_mask.hdr.dst_port =
633 rte_flow_item_udp_mask.hdr.dst_port;
635 item.type = RTE_FLOW_ITEM_TYPE_UDP;
637 item.mask = &udp_mask;
641 memset(&tcp, 0, sizeof(tcp));
642 memset(&tcp_mask, 0, sizeof(tcp_mask));
643 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
644 tcp.hdr.src_port = conf->port;
645 tcp_mask.hdr.src_port =
646 rte_flow_item_tcp_mask.hdr.src_port;
648 tcp.hdr.dst_port = conf->port;
649 tcp_mask.hdr.dst_port =
650 rte_flow_item_tcp_mask.hdr.dst_port;
652 item.type = RTE_FLOW_ITEM_TYPE_TCP;
654 item.mask = &tcp_mask;
657 return flow_dv_convert_modify_action(&item, field, NULL, resource,
658 MLX5_MODIFICATION_TYPE_SET, error);
662 * Convert modify-header set TTL action to DV specification.
664 * @param[in,out] resource
665 * Pointer to the modify-header resource.
667 * Pointer to action specification.
669 * Pointer to rte_flow_item objects list.
671 * Pointer to flow attributes structure.
673 * Pointer to the error structure.
676 * 0 on success, a negative errno value otherwise and rte_errno is set.
679 flow_dv_convert_action_modify_ttl
680 (struct mlx5_flow_dv_modify_hdr_resource *resource,
681 const struct rte_flow_action *action,
682 const struct rte_flow_item *items,
683 union flow_dv_attr *attr,
684 struct rte_flow_error *error)
686 const struct rte_flow_action_set_ttl *conf =
687 (const struct rte_flow_action_set_ttl *)(action->conf);
688 struct rte_flow_item item;
689 struct rte_flow_item_ipv4 ipv4;
690 struct rte_flow_item_ipv4 ipv4_mask;
691 struct rte_flow_item_ipv6 ipv6;
692 struct rte_flow_item_ipv6 ipv6_mask;
693 struct field_modify_info *field;
696 flow_dv_attr_init(items, attr);
698 memset(&ipv4, 0, sizeof(ipv4));
699 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
700 ipv4.hdr.time_to_live = conf->ttl_value;
701 ipv4_mask.hdr.time_to_live = 0xFF;
702 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
704 item.mask = &ipv4_mask;
708 memset(&ipv6, 0, sizeof(ipv6));
709 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
710 ipv6.hdr.hop_limits = conf->ttl_value;
711 ipv6_mask.hdr.hop_limits = 0xFF;
712 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
714 item.mask = &ipv6_mask;
717 return flow_dv_convert_modify_action(&item, field, NULL, resource,
718 MLX5_MODIFICATION_TYPE_SET, error);
722 * Convert modify-header decrement TTL action to DV specification.
724 * @param[in,out] resource
725 * Pointer to the modify-header resource.
727 * Pointer to action specification.
729 * Pointer to rte_flow_item objects list.
731 * Pointer to flow attributes structure.
733 * Pointer to the error structure.
736 * 0 on success, a negative errno value otherwise and rte_errno is set.
739 flow_dv_convert_action_modify_dec_ttl
740 (struct mlx5_flow_dv_modify_hdr_resource *resource,
741 const struct rte_flow_item *items,
742 union flow_dv_attr *attr,
743 struct rte_flow_error *error)
745 struct rte_flow_item item;
746 struct rte_flow_item_ipv4 ipv4;
747 struct rte_flow_item_ipv4 ipv4_mask;
748 struct rte_flow_item_ipv6 ipv6;
749 struct rte_flow_item_ipv6 ipv6_mask;
750 struct field_modify_info *field;
753 flow_dv_attr_init(items, attr);
755 memset(&ipv4, 0, sizeof(ipv4));
756 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
757 ipv4.hdr.time_to_live = 0xFF;
758 ipv4_mask.hdr.time_to_live = 0xFF;
759 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
761 item.mask = &ipv4_mask;
765 memset(&ipv6, 0, sizeof(ipv6));
766 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
767 ipv6.hdr.hop_limits = 0xFF;
768 ipv6_mask.hdr.hop_limits = 0xFF;
769 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
771 item.mask = &ipv6_mask;
774 return flow_dv_convert_modify_action(&item, field, NULL, resource,
775 MLX5_MODIFICATION_TYPE_ADD, error);
779 * Convert modify-header increment/decrement TCP Sequence number
780 * to DV specification.
782 * @param[in,out] resource
783 * Pointer to the modify-header resource.
785 * Pointer to action specification.
787 * Pointer to the error structure.
790 * 0 on success, a negative errno value otherwise and rte_errno is set.
793 flow_dv_convert_action_modify_tcp_seq
794 (struct mlx5_flow_dv_modify_hdr_resource *resource,
795 const struct rte_flow_action *action,
796 struct rte_flow_error *error)
798 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
799 uint64_t value = rte_be_to_cpu_32(*conf);
800 struct rte_flow_item item;
801 struct rte_flow_item_tcp tcp;
802 struct rte_flow_item_tcp tcp_mask;
804 memset(&tcp, 0, sizeof(tcp));
805 memset(&tcp_mask, 0, sizeof(tcp_mask));
806 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
808 * The HW has no decrement operation, only increment operation.
809 * To simulate decrement X from Y using increment operation
810 * we need to add UINT32_MAX X times to Y.
811 * Each adding of UINT32_MAX decrements Y by 1.
814 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
815 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
816 item.type = RTE_FLOW_ITEM_TYPE_TCP;
818 item.mask = &tcp_mask;
819 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
820 MLX5_MODIFICATION_TYPE_ADD, error);
824 * Convert modify-header increment/decrement TCP Acknowledgment number
825 * to DV specification.
827 * @param[in,out] resource
828 * Pointer to the modify-header resource.
830 * Pointer to action specification.
832 * Pointer to the error structure.
835 * 0 on success, a negative errno value otherwise and rte_errno is set.
838 flow_dv_convert_action_modify_tcp_ack
839 (struct mlx5_flow_dv_modify_hdr_resource *resource,
840 const struct rte_flow_action *action,
841 struct rte_flow_error *error)
843 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
844 uint64_t value = rte_be_to_cpu_32(*conf);
845 struct rte_flow_item item;
846 struct rte_flow_item_tcp tcp;
847 struct rte_flow_item_tcp tcp_mask;
849 memset(&tcp, 0, sizeof(tcp));
850 memset(&tcp_mask, 0, sizeof(tcp_mask));
851 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
853 * The HW has no decrement operation, only increment operation.
854 * To simulate decrement X from Y using increment operation
855 * we need to add UINT32_MAX X times to Y.
856 * Each adding of UINT32_MAX decrements Y by 1.
859 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
860 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
861 item.type = RTE_FLOW_ITEM_TYPE_TCP;
863 item.mask = &tcp_mask;
864 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
865 MLX5_MODIFICATION_TYPE_ADD, error);
868 static enum mlx5_modification_field reg_to_field[] = {
869 [REG_NONE] = MLX5_MODI_OUT_NONE,
870 [REG_A] = MLX5_MODI_META_DATA_REG_A,
871 [REG_B] = MLX5_MODI_META_DATA_REG_B,
872 [REG_C_0] = MLX5_MODI_META_REG_C_0,
873 [REG_C_1] = MLX5_MODI_META_REG_C_1,
874 [REG_C_2] = MLX5_MODI_META_REG_C_2,
875 [REG_C_3] = MLX5_MODI_META_REG_C_3,
876 [REG_C_4] = MLX5_MODI_META_REG_C_4,
877 [REG_C_5] = MLX5_MODI_META_REG_C_5,
878 [REG_C_6] = MLX5_MODI_META_REG_C_6,
879 [REG_C_7] = MLX5_MODI_META_REG_C_7,
883 * Convert register set to DV specification.
885 * @param[in,out] resource
886 * Pointer to the modify-header resource.
888 * Pointer to action specification.
890 * Pointer to the error structure.
893 * 0 on success, a negative errno value otherwise and rte_errno is set.
896 flow_dv_convert_action_set_reg
897 (struct mlx5_flow_dv_modify_hdr_resource *resource,
898 const struct rte_flow_action *action,
899 struct rte_flow_error *error)
901 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
902 struct mlx5_modification_cmd *actions = resource->actions;
903 uint32_t i = resource->actions_num;
905 if (i >= MLX5_MODIFY_NUM)
906 return rte_flow_error_set(error, EINVAL,
907 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
908 "too many items to modify");
909 assert(conf->id != REG_NONE);
910 assert(conf->id < RTE_DIM(reg_to_field));
911 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
912 actions[i].field = reg_to_field[conf->id];
913 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
914 actions[i].data1 = rte_cpu_to_be_32(conf->data);
916 resource->actions_num = i;
917 if (!resource->actions_num)
918 return rte_flow_error_set(error, EINVAL,
919 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
920 "invalid modification flow item");
925 * Convert SET_TAG action to DV specification.
928 * Pointer to the rte_eth_dev structure.
929 * @param[in,out] resource
930 * Pointer to the modify-header resource.
932 * Pointer to action specification.
934 * Pointer to the error structure.
937 * 0 on success, a negative errno value otherwise and rte_errno is set.
940 flow_dv_convert_action_set_tag
941 (struct rte_eth_dev *dev,
942 struct mlx5_flow_dv_modify_hdr_resource *resource,
943 const struct rte_flow_action_set_tag *conf,
944 struct rte_flow_error *error)
946 rte_be32_t data = rte_cpu_to_be_32(conf->data);
947 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
948 struct rte_flow_item item = {
952 struct field_modify_info reg_c_x[] = {
955 enum mlx5_modification_field reg_type;
958 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
961 assert(ret != REG_NONE);
962 assert((unsigned int)ret < RTE_DIM(reg_to_field));
963 reg_type = reg_to_field[ret];
964 assert(reg_type > 0);
965 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
966 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
967 MLX5_MODIFICATION_TYPE_SET, error);
971 * Convert internal COPY_REG action to DV specification.
974 * Pointer to the rte_eth_dev structure.
976 * Pointer to the modify-header resource.
978 * Pointer to action specification.
980 * Pointer to the error structure.
983 * 0 on success, a negative errno value otherwise and rte_errno is set.
986 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
987 struct mlx5_flow_dv_modify_hdr_resource *res,
988 const struct rte_flow_action *action,
989 struct rte_flow_error *error)
991 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
992 rte_be32_t mask = RTE_BE32(UINT32_MAX);
993 struct rte_flow_item item = {
997 struct field_modify_info reg_src[] = {
998 {4, 0, reg_to_field[conf->src]},
1001 struct field_modify_info reg_dst = {
1003 .id = reg_to_field[conf->dst],
1005 /* Adjust reg_c[0] usage according to reported mask. */
1006 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1007 struct mlx5_priv *priv = dev->data->dev_private;
1008 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1011 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1012 if (conf->dst == REG_C_0) {
1013 /* Copy to reg_c[0], within mask only. */
1014 reg_dst.offset = rte_bsf32(reg_c0);
1016 * Mask is ignoring the enianness, because
1017 * there is no conversion in datapath.
1019 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1020 /* Copy from destination lower bits to reg_c[0]. */
1021 mask = reg_c0 >> reg_dst.offset;
1023 /* Copy from destination upper bits to reg_c[0]. */
1024 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1025 rte_fls_u32(reg_c0));
1028 mask = rte_cpu_to_be_32(reg_c0);
1029 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1030 /* Copy from reg_c[0] to destination lower bits. */
1033 /* Copy from reg_c[0] to destination upper bits. */
1034 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1035 (rte_fls_u32(reg_c0) -
1040 return flow_dv_convert_modify_action(&item,
1041 reg_src, ®_dst, res,
1042 MLX5_MODIFICATION_TYPE_COPY,
1047 * Convert MARK action to DV specification. This routine is used
1048 * in extensive metadata only and requires metadata register to be
1049 * handled. In legacy mode hardware tag resource is engaged.
1052 * Pointer to the rte_eth_dev structure.
1054 * Pointer to MARK action specification.
1055 * @param[in,out] resource
1056 * Pointer to the modify-header resource.
1058 * Pointer to the error structure.
1061 * 0 on success, a negative errno value otherwise and rte_errno is set.
1064 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1065 const struct rte_flow_action_mark *conf,
1066 struct mlx5_flow_dv_modify_hdr_resource *resource,
1067 struct rte_flow_error *error)
1069 struct mlx5_priv *priv = dev->data->dev_private;
1070 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1071 priv->sh->dv_mark_mask);
1072 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1073 struct rte_flow_item item = {
1077 struct field_modify_info reg_c_x[] = {
1078 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1081 enum modify_reg reg;
1084 return rte_flow_error_set(error, EINVAL,
1085 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1086 NULL, "zero mark action mask");
1087 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1091 reg_c_x[0].id = reg_to_field[reg];
1092 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1093 MLX5_MODIFICATION_TYPE_SET, error);
1097 * Get metadata register index for specified steering domain.
1100 * Pointer to the rte_eth_dev structure.
1102 * Attributes of flow to determine steering domain.
1104 * Pointer to the error structure.
1107 * positive index on success, a negative errno value otherwise
1108 * and rte_errno is set.
1110 static enum modify_reg
1111 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1112 const struct rte_flow_attr *attr,
1113 struct rte_flow_error *error)
1115 enum modify_reg reg =
1116 mlx5_flow_get_reg_id(dev, attr->transfer ?
1120 MLX5_METADATA_RX, 0, error);
1122 return rte_flow_error_set(error,
1123 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1124 NULL, "unavailable "
1125 "metadata register");
1130 * Convert SET_META action to DV specification.
1133 * Pointer to the rte_eth_dev structure.
1134 * @param[in,out] resource
1135 * Pointer to the modify-header resource.
1137 * Attributes of flow that includes this item.
1139 * Pointer to action specification.
1141 * Pointer to the error structure.
1144 * 0 on success, a negative errno value otherwise and rte_errno is set.
1147 flow_dv_convert_action_set_meta
1148 (struct rte_eth_dev *dev,
1149 struct mlx5_flow_dv_modify_hdr_resource *resource,
1150 const struct rte_flow_attr *attr,
1151 const struct rte_flow_action_set_meta *conf,
1152 struct rte_flow_error *error)
1154 uint32_t data = conf->data;
1155 uint32_t mask = conf->mask;
1156 struct rte_flow_item item = {
1160 struct field_modify_info reg_c_x[] = {
1163 enum modify_reg reg = flow_dv_get_metadata_reg(dev, attr, error);
1168 * In datapath code there is no endianness
1169 * coversions for perfromance reasons, all
1170 * pattern conversions are done in rte_flow.
1172 if (reg == REG_C_0) {
1173 struct mlx5_priv *priv = dev->data->dev_private;
1174 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1178 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1179 shl_c0 = rte_bsf32(msk_c0);
1181 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1185 assert(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1187 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1188 /* The routine expects parameters in memory as big-endian ones. */
1189 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1190 MLX5_MODIFICATION_TYPE_SET, error);
1194 * Validate MARK item.
1197 * Pointer to the rte_eth_dev structure.
1199 * Item specification.
1201 * Attributes of flow that includes this item.
1203 * Pointer to error structure.
1206 * 0 on success, a negative errno value otherwise and rte_errno is set.
1209 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1210 const struct rte_flow_item *item,
1211 const struct rte_flow_attr *attr __rte_unused,
1212 struct rte_flow_error *error)
1214 struct mlx5_priv *priv = dev->data->dev_private;
1215 struct mlx5_dev_config *config = &priv->config;
1216 const struct rte_flow_item_mark *spec = item->spec;
1217 const struct rte_flow_item_mark *mask = item->mask;
1218 const struct rte_flow_item_mark nic_mask = {
1219 .id = priv->sh->dv_mark_mask,
1223 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1224 return rte_flow_error_set(error, ENOTSUP,
1225 RTE_FLOW_ERROR_TYPE_ITEM, item,
1226 "extended metadata feature"
1228 if (!mlx5_flow_ext_mreg_supported(dev))
1229 return rte_flow_error_set(error, ENOTSUP,
1230 RTE_FLOW_ERROR_TYPE_ITEM, item,
1231 "extended metadata register"
1232 " isn't supported");
1234 return rte_flow_error_set(error, ENOTSUP,
1235 RTE_FLOW_ERROR_TYPE_ITEM, item,
1236 "extended metadata register"
1237 " isn't available");
1238 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1242 return rte_flow_error_set(error, EINVAL,
1243 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1245 "data cannot be empty");
1246 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1247 return rte_flow_error_set(error, EINVAL,
1248 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1250 "mark id exceeds the limit");
1253 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1254 (const uint8_t *)&nic_mask,
1255 sizeof(struct rte_flow_item_mark),
1263 * Validate META item.
1266 * Pointer to the rte_eth_dev structure.
1268 * Item specification.
1270 * Attributes of flow that includes this item.
1272 * Pointer to error structure.
1275 * 0 on success, a negative errno value otherwise and rte_errno is set.
1278 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1279 const struct rte_flow_item *item,
1280 const struct rte_flow_attr *attr,
1281 struct rte_flow_error *error)
1283 struct mlx5_priv *priv = dev->data->dev_private;
1284 struct mlx5_dev_config *config = &priv->config;
1285 const struct rte_flow_item_meta *spec = item->spec;
1286 const struct rte_flow_item_meta *mask = item->mask;
1287 struct rte_flow_item_meta nic_mask = {
1290 enum modify_reg reg;
1294 return rte_flow_error_set(error, EINVAL,
1295 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1297 "data cannot be empty");
1299 return rte_flow_error_set(error, EINVAL,
1300 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1301 "data cannot be zero");
1302 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1303 if (!mlx5_flow_ext_mreg_supported(dev))
1304 return rte_flow_error_set(error, ENOTSUP,
1305 RTE_FLOW_ERROR_TYPE_ITEM, item,
1306 "extended metadata register"
1307 " isn't supported");
1308 reg = flow_dv_get_metadata_reg(dev, attr, error);
1312 return rte_flow_error_set(error, ENOTSUP,
1313 RTE_FLOW_ERROR_TYPE_ITEM, item,
1317 nic_mask.data = priv->sh->dv_meta_mask;
1320 mask = &rte_flow_item_meta_mask;
1321 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1322 (const uint8_t *)&nic_mask,
1323 sizeof(struct rte_flow_item_meta),
1329 * Validate TAG item.
1332 * Pointer to the rte_eth_dev structure.
1334 * Item specification.
1336 * Attributes of flow that includes this item.
1338 * Pointer to error structure.
1341 * 0 on success, a negative errno value otherwise and rte_errno is set.
1344 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1345 const struct rte_flow_item *item,
1346 const struct rte_flow_attr *attr __rte_unused,
1347 struct rte_flow_error *error)
1349 const struct rte_flow_item_tag *spec = item->spec;
1350 const struct rte_flow_item_tag *mask = item->mask;
1351 const struct rte_flow_item_tag nic_mask = {
1352 .data = RTE_BE32(UINT32_MAX),
1357 if (!mlx5_flow_ext_mreg_supported(dev))
1358 return rte_flow_error_set(error, ENOTSUP,
1359 RTE_FLOW_ERROR_TYPE_ITEM, item,
1360 "extensive metadata register"
1361 " isn't supported");
1363 return rte_flow_error_set(error, EINVAL,
1364 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1366 "data cannot be empty");
1368 mask = &rte_flow_item_tag_mask;
1369 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1370 (const uint8_t *)&nic_mask,
1371 sizeof(struct rte_flow_item_tag),
1375 if (mask->index != 0xff)
1376 return rte_flow_error_set(error, EINVAL,
1377 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1378 "partial mask for tag index"
1379 " is not supported");
1380 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1383 assert(ret != REG_NONE);
1388 * Validate vport item.
1391 * Pointer to the rte_eth_dev structure.
1393 * Item specification.
1395 * Attributes of flow that includes this item.
1396 * @param[in] item_flags
1397 * Bit-fields that holds the items detected until now.
1399 * Pointer to error structure.
1402 * 0 on success, a negative errno value otherwise and rte_errno is set.
1405 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1406 const struct rte_flow_item *item,
1407 const struct rte_flow_attr *attr,
1408 uint64_t item_flags,
1409 struct rte_flow_error *error)
1411 const struct rte_flow_item_port_id *spec = item->spec;
1412 const struct rte_flow_item_port_id *mask = item->mask;
1413 const struct rte_flow_item_port_id switch_mask = {
1416 struct mlx5_priv *esw_priv;
1417 struct mlx5_priv *dev_priv;
1420 if (!attr->transfer)
1421 return rte_flow_error_set(error, EINVAL,
1422 RTE_FLOW_ERROR_TYPE_ITEM,
1424 "match on port id is valid only"
1425 " when transfer flag is enabled");
1426 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1427 return rte_flow_error_set(error, ENOTSUP,
1428 RTE_FLOW_ERROR_TYPE_ITEM, item,
1429 "multiple source ports are not"
1432 mask = &switch_mask;
1433 if (mask->id != 0xffffffff)
1434 return rte_flow_error_set(error, ENOTSUP,
1435 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1437 "no support for partial mask on"
1439 ret = mlx5_flow_item_acceptable
1440 (item, (const uint8_t *)mask,
1441 (const uint8_t *)&rte_flow_item_port_id_mask,
1442 sizeof(struct rte_flow_item_port_id),
1448 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1450 return rte_flow_error_set(error, rte_errno,
1451 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1452 "failed to obtain E-Switch info for"
1454 dev_priv = mlx5_dev_to_eswitch_info(dev);
1456 return rte_flow_error_set(error, rte_errno,
1457 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1459 "failed to obtain E-Switch info");
1460 if (esw_priv->domain_id != dev_priv->domain_id)
1461 return rte_flow_error_set(error, EINVAL,
1462 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1463 "cannot match on a port from a"
1464 " different E-Switch");
1469 * Validate the pop VLAN action.
1472 * Pointer to the rte_eth_dev structure.
1473 * @param[in] action_flags
1474 * Holds the actions detected until now.
1476 * Pointer to the pop vlan action.
1477 * @param[in] item_flags
1478 * The items found in this flow rule.
1480 * Pointer to flow attributes.
1482 * Pointer to error structure.
1485 * 0 on success, a negative errno value otherwise and rte_errno is set.
1488 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1489 uint64_t action_flags,
1490 const struct rte_flow_action *action,
1491 uint64_t item_flags,
1492 const struct rte_flow_attr *attr,
1493 struct rte_flow_error *error)
1495 struct mlx5_priv *priv = dev->data->dev_private;
1499 if (!priv->sh->pop_vlan_action)
1500 return rte_flow_error_set(error, ENOTSUP,
1501 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1503 "pop vlan action is not supported");
1505 * Check for inconsistencies:
1506 * fail strip_vlan in a flow that matches packets without VLAN tags.
1507 * fail strip_vlan in a flow that matches packets without explicitly a
1508 * matching on VLAN tag ?
1510 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1511 return rte_flow_error_set(error, ENOTSUP,
1512 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1514 "no support for multiple vlan pop "
1516 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1517 return rte_flow_error_set(error, ENOTSUP,
1518 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1520 "cannot pop vlan without a "
1521 "match on (outer) vlan in the flow");
1522 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1523 return rte_flow_error_set(error, EINVAL,
1524 RTE_FLOW_ERROR_TYPE_ACTION, action,
1525 "wrong action order, port_id should "
1526 "be after pop VLAN action");
1531 * Get VLAN default info from vlan match info.
1534 * Pointer to the rte_eth_dev structure.
1536 * the list of item specifications.
1538 * pointer VLAN info to fill to.
1540 * Pointer to error structure.
1543 * 0 on success, a negative errno value otherwise and rte_errno is set.
1546 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1547 struct rte_vlan_hdr *vlan)
1549 const struct rte_flow_item_vlan nic_mask = {
1550 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1551 MLX5DV_FLOW_VLAN_VID_MASK),
1552 .inner_type = RTE_BE16(0xffff),
1557 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1558 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1560 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1561 const struct rte_flow_item_vlan *vlan_m = items->mask;
1562 const struct rte_flow_item_vlan *vlan_v = items->spec;
1566 /* Only full match values are accepted */
1567 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1568 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1569 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1571 rte_be_to_cpu_16(vlan_v->tci &
1572 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1574 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1575 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1576 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1578 rte_be_to_cpu_16(vlan_v->tci &
1579 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1581 if (vlan_m->inner_type == nic_mask.inner_type)
1582 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1583 vlan_m->inner_type);
1588 * Validate the push VLAN action.
1590 * @param[in] action_flags
1591 * Holds the actions detected until now.
1593 * Pointer to the encap action.
1595 * Pointer to flow attributes
1597 * Pointer to error structure.
1600 * 0 on success, a negative errno value otherwise and rte_errno is set.
1603 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1604 uint64_t item_flags,
1605 const struct rte_flow_action *action,
1606 const struct rte_flow_attr *attr,
1607 struct rte_flow_error *error)
1609 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1611 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1612 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1613 return rte_flow_error_set(error, EINVAL,
1614 RTE_FLOW_ERROR_TYPE_ACTION, action,
1615 "invalid vlan ethertype");
1617 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1618 return rte_flow_error_set(error, ENOTSUP,
1619 RTE_FLOW_ERROR_TYPE_ACTION, action,
1620 "no support for multiple VLAN "
1622 if (!mlx5_flow_find_action
1623 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1624 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1625 return rte_flow_error_set(error, ENOTSUP,
1626 RTE_FLOW_ERROR_TYPE_ACTION, action,
1627 "push VLAN needs to match on VLAN in order to "
1628 "get VLAN VID information because there is "
1629 "no followed set VLAN VID action");
1630 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1631 return rte_flow_error_set(error, EINVAL,
1632 RTE_FLOW_ERROR_TYPE_ACTION, action,
1633 "wrong action order, port_id should "
1634 "be after push VLAN");
1640 * Validate the set VLAN PCP.
1642 * @param[in] action_flags
1643 * Holds the actions detected until now.
1644 * @param[in] actions
1645 * Pointer to the list of actions remaining in the flow rule.
1647 * Pointer to flow attributes
1649 * Pointer to error structure.
1652 * 0 on success, a negative errno value otherwise and rte_errno is set.
1655 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1656 const struct rte_flow_action actions[],
1657 struct rte_flow_error *error)
1659 const struct rte_flow_action *action = actions;
1660 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1662 if (conf->vlan_pcp > 7)
1663 return rte_flow_error_set(error, EINVAL,
1664 RTE_FLOW_ERROR_TYPE_ACTION, action,
1665 "VLAN PCP value is too big");
1666 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1667 return rte_flow_error_set(error, ENOTSUP,
1668 RTE_FLOW_ERROR_TYPE_ACTION, action,
1669 "set VLAN PCP action must follow "
1670 "the push VLAN action");
1671 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1672 return rte_flow_error_set(error, ENOTSUP,
1673 RTE_FLOW_ERROR_TYPE_ACTION, action,
1674 "Multiple VLAN PCP modification are "
1676 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1677 return rte_flow_error_set(error, EINVAL,
1678 RTE_FLOW_ERROR_TYPE_ACTION, action,
1679 "wrong action order, port_id should "
1680 "be after set VLAN PCP");
1685 * Validate the set VLAN VID.
1687 * @param[in] item_flags
1688 * Holds the items detected in this rule.
1689 * @param[in] actions
1690 * Pointer to the list of actions remaining in the flow rule.
1692 * Pointer to flow attributes
1694 * Pointer to error structure.
1697 * 0 on success, a negative errno value otherwise and rte_errno is set.
1700 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1701 uint64_t action_flags,
1702 const struct rte_flow_action actions[],
1703 struct rte_flow_error *error)
1705 const struct rte_flow_action *action = actions;
1706 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1708 if (conf->vlan_vid > RTE_BE16(0xFFE))
1709 return rte_flow_error_set(error, EINVAL,
1710 RTE_FLOW_ERROR_TYPE_ACTION, action,
1711 "VLAN VID value is too big");
1712 /* there is an of_push_vlan action before us */
1713 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1714 if (mlx5_flow_find_action(actions + 1,
1715 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1716 return rte_flow_error_set(error, ENOTSUP,
1717 RTE_FLOW_ERROR_TYPE_ACTION, action,
1718 "Multiple VLAN VID modifications are "
1725 * Action is on an existing VLAN header:
1726 * Need to verify this is a single modify CID action.
1727 * Rule mast include a match on outer VLAN.
1729 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1730 return rte_flow_error_set(error, ENOTSUP,
1731 RTE_FLOW_ERROR_TYPE_ACTION, action,
1732 "Multiple VLAN VID modifications are "
1734 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1735 return rte_flow_error_set(error, EINVAL,
1736 RTE_FLOW_ERROR_TYPE_ACTION, action,
1737 "match on VLAN is required in order "
1739 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1740 return rte_flow_error_set(error, EINVAL,
1741 RTE_FLOW_ERROR_TYPE_ACTION, action,
1742 "wrong action order, port_id should "
1743 "be after set VLAN VID");
1748 * Validate the FLAG action.
1751 * Pointer to the rte_eth_dev structure.
1752 * @param[in] action_flags
1753 * Holds the actions detected until now.
1755 * Pointer to flow attributes
1757 * Pointer to error structure.
1760 * 0 on success, a negative errno value otherwise and rte_errno is set.
1763 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1764 uint64_t action_flags,
1765 const struct rte_flow_attr *attr,
1766 struct rte_flow_error *error)
1768 struct mlx5_priv *priv = dev->data->dev_private;
1769 struct mlx5_dev_config *config = &priv->config;
1772 /* Fall back if no extended metadata register support. */
1773 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1774 return mlx5_flow_validate_action_flag(action_flags, attr,
1776 /* Extensive metadata mode requires registers. */
1777 if (!mlx5_flow_ext_mreg_supported(dev))
1778 return rte_flow_error_set(error, ENOTSUP,
1779 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1780 "no metadata registers "
1781 "to support flag action");
1782 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1783 return rte_flow_error_set(error, ENOTSUP,
1784 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1785 "extended metadata register"
1786 " isn't available");
1787 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1791 if (action_flags & MLX5_FLOW_ACTION_DROP)
1792 return rte_flow_error_set(error, EINVAL,
1793 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1794 "can't drop and flag in same flow");
1795 if (action_flags & MLX5_FLOW_ACTION_MARK)
1796 return rte_flow_error_set(error, EINVAL,
1797 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1798 "can't mark and flag in same flow");
1799 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1800 return rte_flow_error_set(error, EINVAL,
1801 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1803 " actions in same flow");
1808 * Validate MARK action.
1811 * Pointer to the rte_eth_dev structure.
1813 * Pointer to action.
1814 * @param[in] action_flags
1815 * Holds the actions detected until now.
1817 * Pointer to flow attributes
1819 * Pointer to error structure.
1822 * 0 on success, a negative errno value otherwise and rte_errno is set.
1825 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1826 const struct rte_flow_action *action,
1827 uint64_t action_flags,
1828 const struct rte_flow_attr *attr,
1829 struct rte_flow_error *error)
1831 struct mlx5_priv *priv = dev->data->dev_private;
1832 struct mlx5_dev_config *config = &priv->config;
1833 const struct rte_flow_action_mark *mark = action->conf;
1836 /* Fall back if no extended metadata register support. */
1837 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1838 return mlx5_flow_validate_action_mark(action, action_flags,
1840 /* Extensive metadata mode requires registers. */
1841 if (!mlx5_flow_ext_mreg_supported(dev))
1842 return rte_flow_error_set(error, ENOTSUP,
1843 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1844 "no metadata registers "
1845 "to support mark action");
1846 if (!priv->sh->dv_mark_mask)
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1849 "extended metadata register"
1850 " isn't available");
1851 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1856 return rte_flow_error_set(error, EINVAL,
1857 RTE_FLOW_ERROR_TYPE_ACTION, action,
1858 "configuration cannot be null");
1859 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1860 return rte_flow_error_set(error, EINVAL,
1861 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1863 "mark id exceeds the limit");
1864 if (action_flags & MLX5_FLOW_ACTION_DROP)
1865 return rte_flow_error_set(error, EINVAL,
1866 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1867 "can't drop and mark in same flow");
1868 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1869 return rte_flow_error_set(error, EINVAL,
1870 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1871 "can't flag and mark in same flow");
1872 if (action_flags & MLX5_FLOW_ACTION_MARK)
1873 return rte_flow_error_set(error, EINVAL,
1874 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1875 "can't have 2 mark actions in same"
1881 * Validate SET_META action.
1884 * Pointer to the rte_eth_dev structure.
1886 * Pointer to the encap action.
1887 * @param[in] action_flags
1888 * Holds the actions detected until now.
1890 * Pointer to flow attributes
1892 * Pointer to error structure.
1895 * 0 on success, a negative errno value otherwise and rte_errno is set.
1898 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
1899 const struct rte_flow_action *action,
1900 uint64_t action_flags __rte_unused,
1901 const struct rte_flow_attr *attr,
1902 struct rte_flow_error *error)
1904 const struct rte_flow_action_set_meta *conf;
1905 uint32_t nic_mask = UINT32_MAX;
1906 enum modify_reg reg;
1908 if (!mlx5_flow_ext_mreg_supported(dev))
1909 return rte_flow_error_set(error, ENOTSUP,
1910 RTE_FLOW_ERROR_TYPE_ACTION, action,
1911 "extended metadata register"
1912 " isn't supported");
1913 reg = flow_dv_get_metadata_reg(dev, attr, error);
1916 if (reg != REG_A && reg != REG_B) {
1917 struct mlx5_priv *priv = dev->data->dev_private;
1919 nic_mask = priv->sh->dv_meta_mask;
1921 if (!(action->conf))
1922 return rte_flow_error_set(error, EINVAL,
1923 RTE_FLOW_ERROR_TYPE_ACTION, action,
1924 "configuration cannot be null");
1925 conf = (const struct rte_flow_action_set_meta *)action->conf;
1927 return rte_flow_error_set(error, EINVAL,
1928 RTE_FLOW_ERROR_TYPE_ACTION, action,
1929 "zero mask doesn't have any effect");
1930 if (conf->mask & ~nic_mask)
1931 return rte_flow_error_set(error, EINVAL,
1932 RTE_FLOW_ERROR_TYPE_ACTION, action,
1933 "meta data must be within reg C0");
1934 if (!(conf->data & conf->mask))
1935 return rte_flow_error_set(error, EINVAL,
1936 RTE_FLOW_ERROR_TYPE_ACTION, action,
1937 "zero value has no effect");
1942 * Validate SET_TAG action.
1945 * Pointer to the rte_eth_dev structure.
1947 * Pointer to the encap action.
1948 * @param[in] action_flags
1949 * Holds the actions detected until now.
1951 * Pointer to flow attributes
1953 * Pointer to error structure.
1956 * 0 on success, a negative errno value otherwise and rte_errno is set.
1959 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
1960 const struct rte_flow_action *action,
1961 uint64_t action_flags,
1962 const struct rte_flow_attr *attr,
1963 struct rte_flow_error *error)
1965 const struct rte_flow_action_set_tag *conf;
1966 const uint64_t terminal_action_flags =
1967 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
1968 MLX5_FLOW_ACTION_RSS;
1971 if (!mlx5_flow_ext_mreg_supported(dev))
1972 return rte_flow_error_set(error, ENOTSUP,
1973 RTE_FLOW_ERROR_TYPE_ACTION, action,
1974 "extensive metadata register"
1975 " isn't supported");
1976 if (!(action->conf))
1977 return rte_flow_error_set(error, EINVAL,
1978 RTE_FLOW_ERROR_TYPE_ACTION, action,
1979 "configuration cannot be null");
1980 conf = (const struct rte_flow_action_set_tag *)action->conf;
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ACTION, action,
1984 "zero mask doesn't have any effect");
1985 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1988 if (!attr->transfer && attr->ingress &&
1989 (action_flags & terminal_action_flags))
1990 return rte_flow_error_set(error, EINVAL,
1991 RTE_FLOW_ERROR_TYPE_ACTION, action,
1992 "set_tag has no effect"
1993 " with terminal actions");
1998 * Validate count action.
2003 * Pointer to error structure.
2006 * 0 on success, a negative errno value otherwise and rte_errno is set.
2009 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2010 struct rte_flow_error *error)
2012 struct mlx5_priv *priv = dev->data->dev_private;
2014 if (!priv->config.devx)
2016 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2020 return rte_flow_error_set
2022 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2024 "count action not supported");
2028 * Validate the L2 encap action.
2030 * @param[in] action_flags
2031 * Holds the actions detected until now.
2033 * Pointer to the encap action.
2035 * Pointer to flow attributes
2037 * Pointer to error structure.
2040 * 0 on success, a negative errno value otherwise and rte_errno is set.
2043 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2044 const struct rte_flow_action *action,
2045 const struct rte_flow_attr *attr,
2046 struct rte_flow_error *error)
2048 if (!(action->conf))
2049 return rte_flow_error_set(error, EINVAL,
2050 RTE_FLOW_ERROR_TYPE_ACTION, action,
2051 "configuration cannot be null");
2052 if (action_flags & MLX5_FLOW_ACTION_DROP)
2053 return rte_flow_error_set(error, EINVAL,
2054 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2055 "can't drop and encap in same flow");
2056 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2057 return rte_flow_error_set(error, EINVAL,
2058 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2059 "can only have a single encap or"
2060 " decap action in a flow");
2061 if (!attr->transfer && attr->ingress)
2062 return rte_flow_error_set(error, ENOTSUP,
2063 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2065 "encap action not supported for "
2071 * Validate the L2 decap action.
2073 * @param[in] action_flags
2074 * Holds the actions detected until now.
2076 * Pointer to flow attributes
2078 * Pointer to error structure.
2081 * 0 on success, a negative errno value otherwise and rte_errno is set.
2084 flow_dv_validate_action_l2_decap(uint64_t action_flags,
2085 const struct rte_flow_attr *attr,
2086 struct rte_flow_error *error)
2088 if (action_flags & MLX5_FLOW_ACTION_DROP)
2089 return rte_flow_error_set(error, EINVAL,
2090 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2091 "can't drop and decap in same flow");
2092 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2093 return rte_flow_error_set(error, EINVAL,
2094 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2095 "can only have a single encap or"
2096 " decap action in a flow");
2097 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2098 return rte_flow_error_set(error, EINVAL,
2099 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2100 "can't have decap action after"
2103 return rte_flow_error_set(error, ENOTSUP,
2104 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2106 "decap action not supported for "
2112 * Validate the raw encap action.
2114 * @param[in] action_flags
2115 * Holds the actions detected until now.
2117 * Pointer to the encap action.
2119 * Pointer to flow attributes
2121 * Pointer to error structure.
2124 * 0 on success, a negative errno value otherwise and rte_errno is set.
2127 flow_dv_validate_action_raw_encap(uint64_t action_flags,
2128 const struct rte_flow_action *action,
2129 const struct rte_flow_attr *attr,
2130 struct rte_flow_error *error)
2132 const struct rte_flow_action_raw_encap *raw_encap =
2133 (const struct rte_flow_action_raw_encap *)action->conf;
2134 if (!(action->conf))
2135 return rte_flow_error_set(error, EINVAL,
2136 RTE_FLOW_ERROR_TYPE_ACTION, action,
2137 "configuration cannot be null");
2138 if (action_flags & MLX5_FLOW_ACTION_DROP)
2139 return rte_flow_error_set(error, EINVAL,
2140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2141 "can't drop and encap in same flow");
2142 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2143 return rte_flow_error_set(error, EINVAL,
2144 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2145 "can only have a single encap"
2146 " action in a flow");
2147 /* encap without preceding decap is not supported for ingress */
2148 if (!attr->transfer && attr->ingress &&
2149 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
2150 return rte_flow_error_set(error, ENOTSUP,
2151 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2153 "encap action not supported for "
2155 if (!raw_encap->size || !raw_encap->data)
2156 return rte_flow_error_set(error, EINVAL,
2157 RTE_FLOW_ERROR_TYPE_ACTION, action,
2158 "raw encap data cannot be empty");
2163 * Validate the raw decap action.
2165 * @param[in] action_flags
2166 * Holds the actions detected until now.
2168 * Pointer to the encap action.
2170 * Pointer to flow attributes
2172 * Pointer to error structure.
2175 * 0 on success, a negative errno value otherwise and rte_errno is set.
2178 flow_dv_validate_action_raw_decap(uint64_t action_flags,
2179 const struct rte_flow_action *action,
2180 const struct rte_flow_attr *attr,
2181 struct rte_flow_error *error)
2183 const struct rte_flow_action_raw_decap *decap = action->conf;
2185 if (action_flags & MLX5_FLOW_ACTION_DROP)
2186 return rte_flow_error_set(error, EINVAL,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "can't drop and decap in same flow");
2189 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2190 return rte_flow_error_set(error, EINVAL,
2191 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2192 "can't have encap action before"
2194 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2197 "can only have a single decap"
2198 " action in a flow");
2199 /* decap action is valid on egress only if it is followed by encap */
2200 if (attr->egress && decap &&
2201 decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) {
2202 return rte_flow_error_set(error, ENOTSUP,
2203 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2204 NULL, "decap action not supported"
2206 } else if (decap && decap->size > MLX5_ENCAPSULATION_DECISION_SIZE &&
2207 (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)) {
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION,
2211 "can't have decap action "
2212 "after modify action");
2218 * Find existing encap/decap resource or create and register a new one.
2220 * @param[in, out] dev
2221 * Pointer to rte_eth_dev structure.
2222 * @param[in, out] resource
2223 * Pointer to encap/decap resource.
2224 * @parm[in, out] dev_flow
2225 * Pointer to the dev_flow.
2227 * pointer to error structure.
2230 * 0 on success otherwise -errno and errno is set.
2233 flow_dv_encap_decap_resource_register
2234 (struct rte_eth_dev *dev,
2235 struct mlx5_flow_dv_encap_decap_resource *resource,
2236 struct mlx5_flow *dev_flow,
2237 struct rte_flow_error *error)
2239 struct mlx5_priv *priv = dev->data->dev_private;
2240 struct mlx5_ibv_shared *sh = priv->sh;
2241 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2242 struct mlx5dv_dr_domain *domain;
2244 resource->flags = dev_flow->group ? 0 : 1;
2245 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2246 domain = sh->fdb_domain;
2247 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2248 domain = sh->rx_domain;
2250 domain = sh->tx_domain;
2252 /* Lookup a matching resource from cache. */
2253 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2254 if (resource->reformat_type == cache_resource->reformat_type &&
2255 resource->ft_type == cache_resource->ft_type &&
2256 resource->flags == cache_resource->flags &&
2257 resource->size == cache_resource->size &&
2258 !memcmp((const void *)resource->buf,
2259 (const void *)cache_resource->buf,
2261 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2262 (void *)cache_resource,
2263 rte_atomic32_read(&cache_resource->refcnt));
2264 rte_atomic32_inc(&cache_resource->refcnt);
2265 dev_flow->dv.encap_decap = cache_resource;
2269 /* Register new encap/decap resource. */
2270 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2271 if (!cache_resource)
2272 return rte_flow_error_set(error, ENOMEM,
2273 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2274 "cannot allocate resource memory");
2275 *cache_resource = *resource;
2276 cache_resource->verbs_action =
2277 mlx5_glue->dv_create_flow_action_packet_reformat
2278 (sh->ctx, cache_resource->reformat_type,
2279 cache_resource->ft_type, domain, cache_resource->flags,
2280 cache_resource->size,
2281 (cache_resource->size ? cache_resource->buf : NULL));
2282 if (!cache_resource->verbs_action) {
2283 rte_free(cache_resource);
2284 return rte_flow_error_set(error, ENOMEM,
2285 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2286 NULL, "cannot create action");
2288 rte_atomic32_init(&cache_resource->refcnt);
2289 rte_atomic32_inc(&cache_resource->refcnt);
2290 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2291 dev_flow->dv.encap_decap = cache_resource;
2292 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2293 (void *)cache_resource,
2294 rte_atomic32_read(&cache_resource->refcnt));
2299 * Find existing table jump resource or create and register a new one.
2301 * @param[in, out] dev
2302 * Pointer to rte_eth_dev structure.
2303 * @param[in, out] tbl
2304 * Pointer to flow table resource.
2305 * @parm[in, out] dev_flow
2306 * Pointer to the dev_flow.
2308 * pointer to error structure.
2311 * 0 on success otherwise -errno and errno is set.
2314 flow_dv_jump_tbl_resource_register
2315 (struct rte_eth_dev *dev __rte_unused,
2316 struct mlx5_flow_tbl_resource *tbl,
2317 struct mlx5_flow *dev_flow,
2318 struct rte_flow_error *error)
2320 struct mlx5_flow_tbl_data_entry *tbl_data =
2321 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2325 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2327 tbl_data->jump.action =
2328 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2330 if (!tbl_data->jump.action)
2331 return rte_flow_error_set(error, ENOMEM,
2332 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2333 NULL, "cannot create jump action");
2334 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2335 (void *)&tbl_data->jump, cnt);
2337 assert(tbl_data->jump.action);
2338 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2339 (void *)&tbl_data->jump, cnt);
2341 rte_atomic32_inc(&tbl_data->jump.refcnt);
2342 dev_flow->dv.jump = &tbl_data->jump;
2347 * Find existing table port ID resource or create and register a new one.
2349 * @param[in, out] dev
2350 * Pointer to rte_eth_dev structure.
2351 * @param[in, out] resource
2352 * Pointer to port ID action resource.
2353 * @parm[in, out] dev_flow
2354 * Pointer to the dev_flow.
2356 * pointer to error structure.
2359 * 0 on success otherwise -errno and errno is set.
2362 flow_dv_port_id_action_resource_register
2363 (struct rte_eth_dev *dev,
2364 struct mlx5_flow_dv_port_id_action_resource *resource,
2365 struct mlx5_flow *dev_flow,
2366 struct rte_flow_error *error)
2368 struct mlx5_priv *priv = dev->data->dev_private;
2369 struct mlx5_ibv_shared *sh = priv->sh;
2370 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2372 /* Lookup a matching resource from cache. */
2373 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2374 if (resource->port_id == cache_resource->port_id) {
2375 DRV_LOG(DEBUG, "port id action resource resource %p: "
2377 (void *)cache_resource,
2378 rte_atomic32_read(&cache_resource->refcnt));
2379 rte_atomic32_inc(&cache_resource->refcnt);
2380 dev_flow->dv.port_id_action = cache_resource;
2384 /* Register new port id action resource. */
2385 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2386 if (!cache_resource)
2387 return rte_flow_error_set(error, ENOMEM,
2388 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2389 "cannot allocate resource memory");
2390 *cache_resource = *resource;
2392 * Depending on rdma_core version the glue routine calls
2393 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2394 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2396 cache_resource->action =
2397 mlx5_glue->dr_create_flow_action_dest_port
2398 (priv->sh->fdb_domain, resource->port_id);
2399 if (!cache_resource->action) {
2400 rte_free(cache_resource);
2401 return rte_flow_error_set(error, ENOMEM,
2402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2403 NULL, "cannot create action");
2405 rte_atomic32_init(&cache_resource->refcnt);
2406 rte_atomic32_inc(&cache_resource->refcnt);
2407 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2408 dev_flow->dv.port_id_action = cache_resource;
2409 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2410 (void *)cache_resource,
2411 rte_atomic32_read(&cache_resource->refcnt));
2416 * Find existing push vlan resource or create and register a new one.
2418 * @param [in, out] dev
2419 * Pointer to rte_eth_dev structure.
2420 * @param[in, out] resource
2421 * Pointer to port ID action resource.
2422 * @parm[in, out] dev_flow
2423 * Pointer to the dev_flow.
2425 * pointer to error structure.
2428 * 0 on success otherwise -errno and errno is set.
2431 flow_dv_push_vlan_action_resource_register
2432 (struct rte_eth_dev *dev,
2433 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2434 struct mlx5_flow *dev_flow,
2435 struct rte_flow_error *error)
2437 struct mlx5_priv *priv = dev->data->dev_private;
2438 struct mlx5_ibv_shared *sh = priv->sh;
2439 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2440 struct mlx5dv_dr_domain *domain;
2442 /* Lookup a matching resource from cache. */
2443 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2444 if (resource->vlan_tag == cache_resource->vlan_tag &&
2445 resource->ft_type == cache_resource->ft_type) {
2446 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2448 (void *)cache_resource,
2449 rte_atomic32_read(&cache_resource->refcnt));
2450 rte_atomic32_inc(&cache_resource->refcnt);
2451 dev_flow->dv.push_vlan_res = cache_resource;
2455 /* Register new push_vlan action resource. */
2456 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2457 if (!cache_resource)
2458 return rte_flow_error_set(error, ENOMEM,
2459 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2460 "cannot allocate resource memory");
2461 *cache_resource = *resource;
2462 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2463 domain = sh->fdb_domain;
2464 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2465 domain = sh->rx_domain;
2467 domain = sh->tx_domain;
2468 cache_resource->action =
2469 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2470 resource->vlan_tag);
2471 if (!cache_resource->action) {
2472 rte_free(cache_resource);
2473 return rte_flow_error_set(error, ENOMEM,
2474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2475 NULL, "cannot create action");
2477 rte_atomic32_init(&cache_resource->refcnt);
2478 rte_atomic32_inc(&cache_resource->refcnt);
2479 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2480 dev_flow->dv.push_vlan_res = cache_resource;
2481 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2482 (void *)cache_resource,
2483 rte_atomic32_read(&cache_resource->refcnt));
2487 * Get the size of specific rte_flow_item_type
2489 * @param[in] item_type
2490 * Tested rte_flow_item_type.
2493 * sizeof struct item_type, 0 if void or irrelevant.
2496 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2500 switch (item_type) {
2501 case RTE_FLOW_ITEM_TYPE_ETH:
2502 retval = sizeof(struct rte_flow_item_eth);
2504 case RTE_FLOW_ITEM_TYPE_VLAN:
2505 retval = sizeof(struct rte_flow_item_vlan);
2507 case RTE_FLOW_ITEM_TYPE_IPV4:
2508 retval = sizeof(struct rte_flow_item_ipv4);
2510 case RTE_FLOW_ITEM_TYPE_IPV6:
2511 retval = sizeof(struct rte_flow_item_ipv6);
2513 case RTE_FLOW_ITEM_TYPE_UDP:
2514 retval = sizeof(struct rte_flow_item_udp);
2516 case RTE_FLOW_ITEM_TYPE_TCP:
2517 retval = sizeof(struct rte_flow_item_tcp);
2519 case RTE_FLOW_ITEM_TYPE_VXLAN:
2520 retval = sizeof(struct rte_flow_item_vxlan);
2522 case RTE_FLOW_ITEM_TYPE_GRE:
2523 retval = sizeof(struct rte_flow_item_gre);
2525 case RTE_FLOW_ITEM_TYPE_NVGRE:
2526 retval = sizeof(struct rte_flow_item_nvgre);
2528 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2529 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2531 case RTE_FLOW_ITEM_TYPE_MPLS:
2532 retval = sizeof(struct rte_flow_item_mpls);
2534 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2542 #define MLX5_ENCAP_IPV4_VERSION 0x40
2543 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2544 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2545 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2546 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2547 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2548 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2551 * Convert the encap action data from list of rte_flow_item to raw buffer
2554 * Pointer to rte_flow_item objects list.
2556 * Pointer to the output buffer.
2558 * Pointer to the output buffer size.
2560 * Pointer to the error structure.
2563 * 0 on success, a negative errno value otherwise and rte_errno is set.
2566 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2567 size_t *size, struct rte_flow_error *error)
2569 struct rte_ether_hdr *eth = NULL;
2570 struct rte_vlan_hdr *vlan = NULL;
2571 struct rte_ipv4_hdr *ipv4 = NULL;
2572 struct rte_ipv6_hdr *ipv6 = NULL;
2573 struct rte_udp_hdr *udp = NULL;
2574 struct rte_vxlan_hdr *vxlan = NULL;
2575 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2576 struct rte_gre_hdr *gre = NULL;
2578 size_t temp_size = 0;
2581 return rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ACTION,
2583 NULL, "invalid empty data");
2584 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2585 len = flow_dv_get_item_len(items->type);
2586 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2587 return rte_flow_error_set(error, EINVAL,
2588 RTE_FLOW_ERROR_TYPE_ACTION,
2589 (void *)items->type,
2590 "items total size is too big"
2591 " for encap action");
2592 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2593 switch (items->type) {
2594 case RTE_FLOW_ITEM_TYPE_ETH:
2595 eth = (struct rte_ether_hdr *)&buf[temp_size];
2597 case RTE_FLOW_ITEM_TYPE_VLAN:
2598 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2600 return rte_flow_error_set(error, EINVAL,
2601 RTE_FLOW_ERROR_TYPE_ACTION,
2602 (void *)items->type,
2603 "eth header not found");
2604 if (!eth->ether_type)
2605 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2607 case RTE_FLOW_ITEM_TYPE_IPV4:
2608 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2610 return rte_flow_error_set(error, EINVAL,
2611 RTE_FLOW_ERROR_TYPE_ACTION,
2612 (void *)items->type,
2613 "neither eth nor vlan"
2615 if (vlan && !vlan->eth_proto)
2616 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2617 else if (eth && !eth->ether_type)
2618 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2619 if (!ipv4->version_ihl)
2620 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2621 MLX5_ENCAP_IPV4_IHL_MIN;
2622 if (!ipv4->time_to_live)
2623 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2625 case RTE_FLOW_ITEM_TYPE_IPV6:
2626 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2628 return rte_flow_error_set(error, EINVAL,
2629 RTE_FLOW_ERROR_TYPE_ACTION,
2630 (void *)items->type,
2631 "neither eth nor vlan"
2633 if (vlan && !vlan->eth_proto)
2634 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2635 else if (eth && !eth->ether_type)
2636 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2637 if (!ipv6->vtc_flow)
2639 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2640 if (!ipv6->hop_limits)
2641 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2643 case RTE_FLOW_ITEM_TYPE_UDP:
2644 udp = (struct rte_udp_hdr *)&buf[temp_size];
2646 return rte_flow_error_set(error, EINVAL,
2647 RTE_FLOW_ERROR_TYPE_ACTION,
2648 (void *)items->type,
2649 "ip header not found");
2650 if (ipv4 && !ipv4->next_proto_id)
2651 ipv4->next_proto_id = IPPROTO_UDP;
2652 else if (ipv6 && !ipv6->proto)
2653 ipv6->proto = IPPROTO_UDP;
2655 case RTE_FLOW_ITEM_TYPE_VXLAN:
2656 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2658 return rte_flow_error_set(error, EINVAL,
2659 RTE_FLOW_ERROR_TYPE_ACTION,
2660 (void *)items->type,
2661 "udp header not found");
2663 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2664 if (!vxlan->vx_flags)
2666 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2668 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2669 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2671 return rte_flow_error_set(error, EINVAL,
2672 RTE_FLOW_ERROR_TYPE_ACTION,
2673 (void *)items->type,
2674 "udp header not found");
2675 if (!vxlan_gpe->proto)
2676 return rte_flow_error_set(error, EINVAL,
2677 RTE_FLOW_ERROR_TYPE_ACTION,
2678 (void *)items->type,
2679 "next protocol not found");
2682 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2683 if (!vxlan_gpe->vx_flags)
2684 vxlan_gpe->vx_flags =
2685 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2687 case RTE_FLOW_ITEM_TYPE_GRE:
2688 case RTE_FLOW_ITEM_TYPE_NVGRE:
2689 gre = (struct rte_gre_hdr *)&buf[temp_size];
2691 return rte_flow_error_set(error, EINVAL,
2692 RTE_FLOW_ERROR_TYPE_ACTION,
2693 (void *)items->type,
2694 "next protocol not found");
2696 return rte_flow_error_set(error, EINVAL,
2697 RTE_FLOW_ERROR_TYPE_ACTION,
2698 (void *)items->type,
2699 "ip header not found");
2700 if (ipv4 && !ipv4->next_proto_id)
2701 ipv4->next_proto_id = IPPROTO_GRE;
2702 else if (ipv6 && !ipv6->proto)
2703 ipv6->proto = IPPROTO_GRE;
2705 case RTE_FLOW_ITEM_TYPE_VOID:
2708 return rte_flow_error_set(error, EINVAL,
2709 RTE_FLOW_ERROR_TYPE_ACTION,
2710 (void *)items->type,
2711 "unsupported item type");
2721 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2723 struct rte_ether_hdr *eth = NULL;
2724 struct rte_vlan_hdr *vlan = NULL;
2725 struct rte_ipv6_hdr *ipv6 = NULL;
2726 struct rte_udp_hdr *udp = NULL;
2730 eth = (struct rte_ether_hdr *)data;
2731 next_hdr = (char *)(eth + 1);
2732 proto = RTE_BE16(eth->ether_type);
2735 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2736 vlan = (struct rte_vlan_hdr *)next_hdr;
2737 proto = RTE_BE16(vlan->eth_proto);
2738 next_hdr += sizeof(struct rte_vlan_hdr);
2741 /* HW calculates IPv4 csum. no need to proceed */
2742 if (proto == RTE_ETHER_TYPE_IPV4)
2745 /* non IPv4/IPv6 header. not supported */
2746 if (proto != RTE_ETHER_TYPE_IPV6) {
2747 return rte_flow_error_set(error, ENOTSUP,
2748 RTE_FLOW_ERROR_TYPE_ACTION,
2749 NULL, "Cannot offload non IPv4/IPv6");
2752 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2754 /* ignore non UDP */
2755 if (ipv6->proto != IPPROTO_UDP)
2758 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2759 udp->dgram_cksum = 0;
2765 * Convert L2 encap action to DV specification.
2768 * Pointer to rte_eth_dev structure.
2770 * Pointer to action structure.
2771 * @param[in, out] dev_flow
2772 * Pointer to the mlx5_flow.
2773 * @param[in] transfer
2774 * Mark if the flow is E-Switch flow.
2776 * Pointer to the error structure.
2779 * 0 on success, a negative errno value otherwise and rte_errno is set.
2782 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2783 const struct rte_flow_action *action,
2784 struct mlx5_flow *dev_flow,
2786 struct rte_flow_error *error)
2788 const struct rte_flow_item *encap_data;
2789 const struct rte_flow_action_raw_encap *raw_encap_data;
2790 struct mlx5_flow_dv_encap_decap_resource res = {
2792 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2793 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2794 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2797 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2799 (const struct rte_flow_action_raw_encap *)action->conf;
2800 res.size = raw_encap_data->size;
2801 memcpy(res.buf, raw_encap_data->data, res.size);
2802 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2805 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2807 ((const struct rte_flow_action_vxlan_encap *)
2808 action->conf)->definition;
2811 ((const struct rte_flow_action_nvgre_encap *)
2812 action->conf)->definition;
2813 if (flow_dv_convert_encap_data(encap_data, res.buf,
2817 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2818 return rte_flow_error_set(error, EINVAL,
2819 RTE_FLOW_ERROR_TYPE_ACTION,
2820 NULL, "can't create L2 encap action");
2825 * Convert L2 decap action to DV specification.
2828 * Pointer to rte_eth_dev structure.
2829 * @param[in, out] dev_flow
2830 * Pointer to the mlx5_flow.
2831 * @param[in] transfer
2832 * Mark if the flow is E-Switch flow.
2834 * Pointer to the error structure.
2837 * 0 on success, a negative errno value otherwise and rte_errno is set.
2840 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2841 struct mlx5_flow *dev_flow,
2843 struct rte_flow_error *error)
2845 struct mlx5_flow_dv_encap_decap_resource res = {
2848 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2849 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2850 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2853 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2854 return rte_flow_error_set(error, EINVAL,
2855 RTE_FLOW_ERROR_TYPE_ACTION,
2856 NULL, "can't create L2 decap action");
2861 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2864 * Pointer to rte_eth_dev structure.
2866 * Pointer to action structure.
2867 * @param[in, out] dev_flow
2868 * Pointer to the mlx5_flow.
2870 * Pointer to the flow attributes.
2872 * Pointer to the error structure.
2875 * 0 on success, a negative errno value otherwise and rte_errno is set.
2878 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2879 const struct rte_flow_action *action,
2880 struct mlx5_flow *dev_flow,
2881 const struct rte_flow_attr *attr,
2882 struct rte_flow_error *error)
2884 const struct rte_flow_action_raw_encap *encap_data;
2885 struct mlx5_flow_dv_encap_decap_resource res;
2887 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2888 res.size = encap_data->size;
2889 memcpy(res.buf, encap_data->data, res.size);
2890 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
2891 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
2892 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
2894 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2896 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2897 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2898 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2899 return rte_flow_error_set(error, EINVAL,
2900 RTE_FLOW_ERROR_TYPE_ACTION,
2901 NULL, "can't create encap action");
2906 * Create action push VLAN.
2909 * Pointer to rte_eth_dev structure.
2910 * @param[in] vlan_tag
2911 * the vlan tag to push to the Ethernet header.
2912 * @param[in, out] dev_flow
2913 * Pointer to the mlx5_flow.
2915 * Pointer to the flow attributes.
2917 * Pointer to the error structure.
2920 * 0 on success, a negative errno value otherwise and rte_errno is set.
2923 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2924 const struct rte_flow_attr *attr,
2925 const struct rte_vlan_hdr *vlan,
2926 struct mlx5_flow *dev_flow,
2927 struct rte_flow_error *error)
2929 struct mlx5_flow_dv_push_vlan_action_resource res;
2932 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2935 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2937 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2938 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2939 return flow_dv_push_vlan_action_resource_register
2940 (dev, &res, dev_flow, error);
2944 * Validate the modify-header actions.
2946 * @param[in] action_flags
2947 * Holds the actions detected until now.
2949 * Pointer to the modify action.
2951 * Pointer to error structure.
2954 * 0 on success, a negative errno value otherwise and rte_errno is set.
2957 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2958 const struct rte_flow_action *action,
2959 struct rte_flow_error *error)
2961 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2962 return rte_flow_error_set(error, EINVAL,
2963 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2964 NULL, "action configuration not set");
2965 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2968 "can't have encap action before"
2974 * Validate the modify-header MAC address actions.
2976 * @param[in] action_flags
2977 * Holds the actions detected until now.
2979 * Pointer to the modify action.
2980 * @param[in] item_flags
2981 * Holds the items detected.
2983 * Pointer to error structure.
2986 * 0 on success, a negative errno value otherwise and rte_errno is set.
2989 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2990 const struct rte_flow_action *action,
2991 const uint64_t item_flags,
2992 struct rte_flow_error *error)
2996 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2998 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2999 return rte_flow_error_set(error, EINVAL,
3000 RTE_FLOW_ERROR_TYPE_ACTION,
3002 "no L2 item in pattern");
3008 * Validate the modify-header IPv4 address actions.
3010 * @param[in] action_flags
3011 * Holds the actions detected until now.
3013 * Pointer to the modify action.
3014 * @param[in] item_flags
3015 * Holds the items detected.
3017 * Pointer to error structure.
3020 * 0 on success, a negative errno value otherwise and rte_errno is set.
3023 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3024 const struct rte_flow_action *action,
3025 const uint64_t item_flags,
3026 struct rte_flow_error *error)
3030 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3032 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3033 return rte_flow_error_set(error, EINVAL,
3034 RTE_FLOW_ERROR_TYPE_ACTION,
3036 "no ipv4 item in pattern");
3042 * Validate the modify-header IPv6 address actions.
3044 * @param[in] action_flags
3045 * Holds the actions detected until now.
3047 * Pointer to the modify action.
3048 * @param[in] item_flags
3049 * Holds the items detected.
3051 * Pointer to error structure.
3054 * 0 on success, a negative errno value otherwise and rte_errno is set.
3057 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3058 const struct rte_flow_action *action,
3059 const uint64_t item_flags,
3060 struct rte_flow_error *error)
3064 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3066 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3067 return rte_flow_error_set(error, EINVAL,
3068 RTE_FLOW_ERROR_TYPE_ACTION,
3070 "no ipv6 item in pattern");
3076 * Validate the modify-header TP actions.
3078 * @param[in] action_flags
3079 * Holds the actions detected until now.
3081 * Pointer to the modify action.
3082 * @param[in] item_flags
3083 * Holds the items detected.
3085 * Pointer to error structure.
3088 * 0 on success, a negative errno value otherwise and rte_errno is set.
3091 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3092 const struct rte_flow_action *action,
3093 const uint64_t item_flags,
3094 struct rte_flow_error *error)
3098 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3100 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3101 return rte_flow_error_set(error, EINVAL,
3102 RTE_FLOW_ERROR_TYPE_ACTION,
3103 NULL, "no transport layer "
3110 * Validate the modify-header actions of increment/decrement
3111 * TCP Sequence-number.
3113 * @param[in] action_flags
3114 * Holds the actions detected until now.
3116 * Pointer to the modify action.
3117 * @param[in] item_flags
3118 * Holds the items detected.
3120 * Pointer to error structure.
3123 * 0 on success, a negative errno value otherwise and rte_errno is set.
3126 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3127 const struct rte_flow_action *action,
3128 const uint64_t item_flags,
3129 struct rte_flow_error *error)
3133 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3135 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3136 return rte_flow_error_set(error, EINVAL,
3137 RTE_FLOW_ERROR_TYPE_ACTION,
3138 NULL, "no TCP item in"
3140 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3141 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3142 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3143 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3144 return rte_flow_error_set(error, EINVAL,
3145 RTE_FLOW_ERROR_TYPE_ACTION,
3147 "cannot decrease and increase"
3148 " TCP sequence number"
3149 " at the same time");
3155 * Validate the modify-header actions of increment/decrement
3156 * TCP Acknowledgment number.
3158 * @param[in] action_flags
3159 * Holds the actions detected until now.
3161 * Pointer to the modify action.
3162 * @param[in] item_flags
3163 * Holds the items detected.
3165 * Pointer to error structure.
3168 * 0 on success, a negative errno value otherwise and rte_errno is set.
3171 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3172 const struct rte_flow_action *action,
3173 const uint64_t item_flags,
3174 struct rte_flow_error *error)
3178 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3180 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3181 return rte_flow_error_set(error, EINVAL,
3182 RTE_FLOW_ERROR_TYPE_ACTION,
3183 NULL, "no TCP item in"
3185 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3186 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3187 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3188 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3189 return rte_flow_error_set(error, EINVAL,
3190 RTE_FLOW_ERROR_TYPE_ACTION,
3192 "cannot decrease and increase"
3193 " TCP acknowledgment number"
3194 " at the same time");
3200 * Validate the modify-header TTL actions.
3202 * @param[in] action_flags
3203 * Holds the actions detected until now.
3205 * Pointer to the modify action.
3206 * @param[in] item_flags
3207 * Holds the items detected.
3209 * Pointer to error structure.
3212 * 0 on success, a negative errno value otherwise and rte_errno is set.
3215 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3216 const struct rte_flow_action *action,
3217 const uint64_t item_flags,
3218 struct rte_flow_error *error)
3222 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3224 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3225 return rte_flow_error_set(error, EINVAL,
3226 RTE_FLOW_ERROR_TYPE_ACTION,
3228 "no IP protocol in pattern");
3234 * Validate jump action.
3237 * Pointer to the jump action.
3238 * @param[in] action_flags
3239 * Holds the actions detected until now.
3240 * @param[in] attributes
3241 * Pointer to flow attributes
3242 * @param[in] external
3243 * Action belongs to flow rule created by request external to PMD.
3245 * Pointer to error structure.
3248 * 0 on success, a negative errno value otherwise and rte_errno is set.
3251 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3252 uint64_t action_flags,
3253 const struct rte_flow_attr *attributes,
3254 bool external, struct rte_flow_error *error)
3256 uint32_t target_group, table;
3259 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3260 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3261 return rte_flow_error_set(error, EINVAL,
3262 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3263 "can't have 2 fate actions in"
3265 if (action_flags & MLX5_FLOW_ACTION_METER)
3266 return rte_flow_error_set(error, ENOTSUP,
3267 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3268 "jump with meter not support");
3270 return rte_flow_error_set(error, EINVAL,
3271 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3272 NULL, "action configuration not set");
3274 ((const struct rte_flow_action_jump *)action->conf)->group;
3275 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3279 if (attributes->group == target_group)
3280 return rte_flow_error_set(error, EINVAL,
3281 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3282 "target group must be other than"
3283 " the current flow group");
3288 * Validate the port_id action.
3291 * Pointer to rte_eth_dev structure.
3292 * @param[in] action_flags
3293 * Bit-fields that holds the actions detected until now.
3295 * Port_id RTE action structure.
3297 * Attributes of flow that includes this action.
3299 * Pointer to error structure.
3302 * 0 on success, a negative errno value otherwise and rte_errno is set.
3305 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3306 uint64_t action_flags,
3307 const struct rte_flow_action *action,
3308 const struct rte_flow_attr *attr,
3309 struct rte_flow_error *error)
3311 const struct rte_flow_action_port_id *port_id;
3312 struct mlx5_priv *act_priv;
3313 struct mlx5_priv *dev_priv;
3316 if (!attr->transfer)
3317 return rte_flow_error_set(error, ENOTSUP,
3318 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3320 "port id action is valid in transfer"
3322 if (!action || !action->conf)
3323 return rte_flow_error_set(error, ENOTSUP,
3324 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3326 "port id action parameters must be"
3328 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3329 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3330 return rte_flow_error_set(error, EINVAL,
3331 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3332 "can have only one fate actions in"
3334 dev_priv = mlx5_dev_to_eswitch_info(dev);
3336 return rte_flow_error_set(error, rte_errno,
3337 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3339 "failed to obtain E-Switch info");
3340 port_id = action->conf;
3341 port = port_id->original ? dev->data->port_id : port_id->id;
3342 act_priv = mlx5_port_to_eswitch_info(port, false);
3344 return rte_flow_error_set
3346 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3347 "failed to obtain E-Switch port id for port");
3348 if (act_priv->domain_id != dev_priv->domain_id)
3349 return rte_flow_error_set
3351 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3352 "port does not belong to"
3353 " E-Switch being configured");
3358 * Get the maximum number of modify header actions.
3361 * Pointer to rte_eth_dev structure.
3364 * Max number of modify header actions device can support.
3367 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev)
3370 * There's no way to directly query the max cap. Although it has to be
3371 * acquried by iterative trial, it is a safe assumption that more
3372 * actions are supported by FW if extensive metadata register is
3375 return mlx5_flow_ext_mreg_supported(dev) ? MLX5_MODIFY_NUM :
3376 MLX5_MODIFY_NUM_NO_MREG;
3380 * Validate the meter action.
3383 * Pointer to rte_eth_dev structure.
3384 * @param[in] action_flags
3385 * Bit-fields that holds the actions detected until now.
3387 * Pointer to the meter action.
3389 * Attributes of flow that includes this action.
3391 * Pointer to error structure.
3394 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3397 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3398 uint64_t action_flags,
3399 const struct rte_flow_action *action,
3400 const struct rte_flow_attr *attr,
3401 struct rte_flow_error *error)
3403 struct mlx5_priv *priv = dev->data->dev_private;
3404 const struct rte_flow_action_meter *am = action->conf;
3405 struct mlx5_flow_meter *fm = mlx5_flow_meter_find(priv, am->mtr_id);
3407 if (action_flags & MLX5_FLOW_ACTION_METER)
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3410 "meter chaining not support");
3411 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3412 return rte_flow_error_set(error, ENOTSUP,
3413 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3414 "meter with jump not support");
3416 return rte_flow_error_set(error, ENOTSUP,
3417 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3419 "meter action not supported");
3421 return rte_flow_error_set(error, EINVAL,
3422 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3424 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3425 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3426 (!fm->attr.egress && !attr->egress && attr->ingress))))
3427 return rte_flow_error_set(error, EINVAL,
3428 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3429 "Flow attributes are either invalid "
3430 "or have a conflict with current "
3431 "meter attributes");
3436 * Find existing modify-header resource or create and register a new one.
3438 * @param dev[in, out]
3439 * Pointer to rte_eth_dev structure.
3440 * @param[in, out] resource
3441 * Pointer to modify-header resource.
3442 * @parm[in, out] dev_flow
3443 * Pointer to the dev_flow.
3445 * pointer to error structure.
3448 * 0 on success otherwise -errno and errno is set.
3451 flow_dv_modify_hdr_resource_register
3452 (struct rte_eth_dev *dev,
3453 struct mlx5_flow_dv_modify_hdr_resource *resource,
3454 struct mlx5_flow *dev_flow,
3455 struct rte_flow_error *error)
3457 struct mlx5_priv *priv = dev->data->dev_private;
3458 struct mlx5_ibv_shared *sh = priv->sh;
3459 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3460 struct mlx5dv_dr_domain *ns;
3462 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev))
3463 return rte_flow_error_set(error, EOVERFLOW,
3464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3465 "too many modify header items");
3466 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3467 ns = sh->fdb_domain;
3468 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3473 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3474 /* Lookup a matching resource from cache. */
3475 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3476 if (resource->ft_type == cache_resource->ft_type &&
3477 resource->actions_num == cache_resource->actions_num &&
3478 resource->flags == cache_resource->flags &&
3479 !memcmp((const void *)resource->actions,
3480 (const void *)cache_resource->actions,
3481 (resource->actions_num *
3482 sizeof(resource->actions[0])))) {
3483 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3484 (void *)cache_resource,
3485 rte_atomic32_read(&cache_resource->refcnt));
3486 rte_atomic32_inc(&cache_resource->refcnt);
3487 dev_flow->dv.modify_hdr = cache_resource;
3491 /* Register new modify-header resource. */
3492 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
3493 if (!cache_resource)
3494 return rte_flow_error_set(error, ENOMEM,
3495 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3496 "cannot allocate resource memory");
3497 *cache_resource = *resource;
3498 cache_resource->verbs_action =
3499 mlx5_glue->dv_create_flow_action_modify_header
3500 (sh->ctx, cache_resource->ft_type,
3501 ns, cache_resource->flags,
3502 cache_resource->actions_num *
3503 sizeof(cache_resource->actions[0]),
3504 (uint64_t *)cache_resource->actions);
3505 if (!cache_resource->verbs_action) {
3506 rte_free(cache_resource);
3507 return rte_flow_error_set(error, ENOMEM,
3508 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3509 NULL, "cannot create action");
3511 rte_atomic32_init(&cache_resource->refcnt);
3512 rte_atomic32_inc(&cache_resource->refcnt);
3513 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3514 dev_flow->dv.modify_hdr = cache_resource;
3515 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3516 (void *)cache_resource,
3517 rte_atomic32_read(&cache_resource->refcnt));
3521 #define MLX5_CNT_CONTAINER_RESIZE 64
3524 * Get or create a flow counter.
3527 * Pointer to the Ethernet device structure.
3529 * Indicate if this counter is shared with other flows.
3531 * Counter identifier.
3534 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3536 static struct mlx5_flow_counter *
3537 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3540 struct mlx5_priv *priv = dev->data->dev_private;
3541 struct mlx5_flow_counter *cnt = NULL;
3542 struct mlx5_devx_obj *dcs = NULL;
3544 if (!priv->config.devx) {
3545 rte_errno = ENOTSUP;
3549 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3550 if (cnt->shared && cnt->id == id) {
3556 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3559 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3561 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3565 struct mlx5_flow_counter tmpl = {
3571 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3573 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3579 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3584 * Release a flow counter.
3587 * Pointer to the Ethernet device structure.
3588 * @param[in] counter
3589 * Pointer to the counter handler.
3592 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3593 struct mlx5_flow_counter *counter)
3595 struct mlx5_priv *priv = dev->data->dev_private;
3599 if (--counter->ref_cnt == 0) {
3600 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3601 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3607 * Query a devx flow counter.
3610 * Pointer to the Ethernet device structure.
3612 * Pointer to the flow counter.
3614 * The statistics value of packets.
3616 * The statistics value of bytes.
3619 * 0 on success, otherwise a negative errno value and rte_errno is set.
3622 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3623 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3626 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3631 * Get a pool by a counter.
3634 * Pointer to the counter.
3639 static struct mlx5_flow_counter_pool *
3640 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3643 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3644 return (struct mlx5_flow_counter_pool *)cnt - 1;
3650 * Get a pool by devx counter ID.
3653 * Pointer to the counter container.
3655 * The counter devx ID.
3658 * The counter pool pointer if exists, NULL otherwise,
3660 static struct mlx5_flow_counter_pool *
3661 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3663 struct mlx5_flow_counter_pool *pool;
3665 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3666 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3667 MLX5_COUNTERS_PER_POOL;
3669 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3676 * Allocate a new memory for the counter values wrapped by all the needed
3680 * Pointer to the Ethernet device structure.
3682 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3685 * The new memory management pointer on success, otherwise NULL and rte_errno
3688 static struct mlx5_counter_stats_mem_mng *
3689 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3691 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3692 (dev->data->dev_private))->sh;
3693 struct mlx5_devx_mkey_attr mkey_attr;
3694 struct mlx5_counter_stats_mem_mng *mem_mng;
3695 volatile struct flow_counter_stats *raw_data;
3696 int size = (sizeof(struct flow_counter_stats) *
3697 MLX5_COUNTERS_PER_POOL +
3698 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3699 sizeof(struct mlx5_counter_stats_mem_mng);
3700 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3707 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3708 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3709 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3710 IBV_ACCESS_LOCAL_WRITE);
3711 if (!mem_mng->umem) {
3716 mkey_attr.addr = (uintptr_t)mem;
3717 mkey_attr.size = size;
3718 mkey_attr.umem_id = mem_mng->umem->umem_id;
3719 mkey_attr.pd = sh->pdn;
3720 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3722 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3727 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3728 raw_data = (volatile struct flow_counter_stats *)mem;
3729 for (i = 0; i < raws_n; ++i) {
3730 mem_mng->raws[i].mem_mng = mem_mng;
3731 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3733 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3738 * Resize a counter container.
3741 * Pointer to the Ethernet device structure.
3743 * Whether the pool is for counter that was allocated by batch command.
3746 * The new container pointer on success, otherwise NULL and rte_errno is set.
3748 static struct mlx5_pools_container *
3749 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3751 struct mlx5_priv *priv = dev->data->dev_private;
3752 struct mlx5_pools_container *cont =
3753 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3754 struct mlx5_pools_container *new_cont =
3755 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3756 struct mlx5_counter_stats_mem_mng *mem_mng;
3757 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3758 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3761 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3762 /* The last resize still hasn't detected by the host thread. */
3766 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3767 if (!new_cont->pools) {
3772 memcpy(new_cont->pools, cont->pools, cont->n *
3773 sizeof(struct mlx5_flow_counter_pool *));
3774 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3775 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3777 rte_free(new_cont->pools);
3780 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3781 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3782 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3784 new_cont->n = resize;
3785 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3786 TAILQ_INIT(&new_cont->pool_list);
3787 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3788 new_cont->init_mem_mng = mem_mng;
3790 /* Flip the master container. */
3791 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3796 * Query a devx flow counter.
3799 * Pointer to the Ethernet device structure.
3801 * Pointer to the flow counter.
3803 * The statistics value of packets.
3805 * The statistics value of bytes.
3808 * 0 on success, otherwise a negative errno value and rte_errno is set.
3811 _flow_dv_query_count(struct rte_eth_dev *dev,
3812 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3815 struct mlx5_priv *priv = dev->data->dev_private;
3816 struct mlx5_flow_counter_pool *pool =
3817 flow_dv_counter_pool_get(cnt);
3818 int offset = cnt - &pool->counters_raw[0];
3820 if (priv->counter_fallback)
3821 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3823 rte_spinlock_lock(&pool->sl);
3825 * The single counters allocation may allocate smaller ID than the
3826 * current allocated in parallel to the host reading.
3827 * In this case the new counter values must be reported as 0.
3829 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3833 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3834 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3836 rte_spinlock_unlock(&pool->sl);
3841 * Create and initialize a new counter pool.
3844 * Pointer to the Ethernet device structure.
3846 * The devX counter handle.
3848 * Whether the pool is for counter that was allocated by batch command.
3851 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3853 static struct mlx5_flow_counter_pool *
3854 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3857 struct mlx5_priv *priv = dev->data->dev_private;
3858 struct mlx5_flow_counter_pool *pool;
3859 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3861 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3864 if (cont->n == n_valid) {
3865 cont = flow_dv_container_resize(dev, batch);
3869 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3870 sizeof(struct mlx5_flow_counter);
3871 pool = rte_calloc(__func__, 1, size, 0);
3876 pool->min_dcs = dcs;
3877 pool->raw = cont->init_mem_mng->raws + n_valid %
3878 MLX5_CNT_CONTAINER_RESIZE;
3879 pool->raw_hw = NULL;
3880 rte_spinlock_init(&pool->sl);
3882 * The generation of the new allocated counters in this pool is 0, 2 in
3883 * the pool generation makes all the counters valid for allocation.
3885 rte_atomic64_set(&pool->query_gen, 0x2);
3886 TAILQ_INIT(&pool->counters);
3887 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3888 cont->pools[n_valid] = pool;
3889 /* Pool initialization must be updated before host thread access. */
3891 rte_atomic16_add(&cont->n_valid, 1);
3896 * Prepare a new counter and/or a new counter pool.
3899 * Pointer to the Ethernet device structure.
3900 * @param[out] cnt_free
3901 * Where to put the pointer of a new counter.
3903 * Whether the pool is for counter that was allocated by batch command.
3906 * The free counter pool pointer and @p cnt_free is set on success,
3907 * NULL otherwise and rte_errno is set.
3909 static struct mlx5_flow_counter_pool *
3910 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3911 struct mlx5_flow_counter **cnt_free,
3914 struct mlx5_priv *priv = dev->data->dev_private;
3915 struct mlx5_flow_counter_pool *pool;
3916 struct mlx5_devx_obj *dcs = NULL;
3917 struct mlx5_flow_counter *cnt;
3921 /* bulk_bitmap must be 0 for single counter allocation. */
3922 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3925 pool = flow_dv_find_pool_by_id
3926 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3928 pool = flow_dv_pool_create(dev, dcs, batch);
3930 mlx5_devx_cmd_destroy(dcs);
3933 } else if (dcs->id < pool->min_dcs->id) {
3934 rte_atomic64_set(&pool->a64_dcs,
3935 (int64_t)(uintptr_t)dcs);
3937 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3938 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3943 /* bulk_bitmap is in 128 counters units. */
3944 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3945 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3947 rte_errno = ENODATA;
3950 pool = flow_dv_pool_create(dev, dcs, batch);
3952 mlx5_devx_cmd_destroy(dcs);
3955 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3956 cnt = &pool->counters_raw[i];
3958 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3960 *cnt_free = &pool->counters_raw[0];
3965 * Search for existed shared counter.
3968 * Pointer to the relevant counter pool container.
3970 * The shared counter ID to search.
3973 * NULL if not existed, otherwise pointer to the shared counter.
3975 static struct mlx5_flow_counter *
3976 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3979 static struct mlx5_flow_counter *cnt;
3980 struct mlx5_flow_counter_pool *pool;
3983 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3984 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3985 cnt = &pool->counters_raw[i];
3986 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3994 * Allocate a flow counter.
3997 * Pointer to the Ethernet device structure.
3999 * Indicate if this counter is shared with other flows.
4001 * Counter identifier.
4003 * Counter flow group.
4006 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4008 static struct mlx5_flow_counter *
4009 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4012 struct mlx5_priv *priv = dev->data->dev_private;
4013 struct mlx5_flow_counter_pool *pool = NULL;
4014 struct mlx5_flow_counter *cnt_free = NULL;
4016 * Currently group 0 flow counter cannot be assigned to a flow if it is
4017 * not the first one in the batch counter allocation, so it is better
4018 * to allocate counters one by one for these flows in a separate
4020 * A counter can be shared between different groups so need to take
4021 * shared counters from the single container.
4023 uint32_t batch = (group && !shared) ? 1 : 0;
4024 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4027 if (priv->counter_fallback)
4028 return flow_dv_counter_alloc_fallback(dev, shared, id);
4029 if (!priv->config.devx) {
4030 rte_errno = ENOTSUP;
4034 cnt_free = flow_dv_counter_shared_search(cont, id);
4036 if (cnt_free->ref_cnt + 1 == 0) {
4040 cnt_free->ref_cnt++;
4044 /* Pools which has a free counters are in the start. */
4045 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4047 * The free counter reset values must be updated between the
4048 * counter release to the counter allocation, so, at least one
4049 * query must be done in this time. ensure it by saving the
4050 * query generation in the release time.
4051 * The free list is sorted according to the generation - so if
4052 * the first one is not updated, all the others are not
4055 cnt_free = TAILQ_FIRST(&pool->counters);
4056 if (cnt_free && cnt_free->query_gen + 1 <
4057 rte_atomic64_read(&pool->query_gen))
4062 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4066 cnt_free->batch = batch;
4067 /* Create a DV counter action only in the first time usage. */
4068 if (!cnt_free->action) {
4070 struct mlx5_devx_obj *dcs;
4073 offset = cnt_free - &pool->counters_raw[0];
4074 dcs = pool->min_dcs;
4077 dcs = cnt_free->dcs;
4079 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4081 if (!cnt_free->action) {
4086 /* Update the counter reset values. */
4087 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4090 cnt_free->shared = shared;
4091 cnt_free->ref_cnt = 1;
4093 if (!priv->sh->cmng.query_thread_on)
4094 /* Start the asynchronous batch query by the host thread. */
4095 mlx5_set_query_alarm(priv->sh);
4096 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4097 if (TAILQ_EMPTY(&pool->counters)) {
4098 /* Move the pool to the end of the container pool list. */
4099 TAILQ_REMOVE(&cont->pool_list, pool, next);
4100 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4106 * Release a flow counter.
4109 * Pointer to the Ethernet device structure.
4110 * @param[in] counter
4111 * Pointer to the counter handler.
4114 flow_dv_counter_release(struct rte_eth_dev *dev,
4115 struct mlx5_flow_counter *counter)
4117 struct mlx5_priv *priv = dev->data->dev_private;
4121 if (priv->counter_fallback) {
4122 flow_dv_counter_release_fallback(dev, counter);
4125 if (--counter->ref_cnt == 0) {
4126 struct mlx5_flow_counter_pool *pool =
4127 flow_dv_counter_pool_get(counter);
4129 /* Put the counter in the end - the last updated one. */
4130 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4131 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4136 * Verify the @p attributes will be correctly understood by the NIC and store
4137 * them in the @p flow if everything is correct.
4140 * Pointer to dev struct.
4141 * @param[in] attributes
4142 * Pointer to flow attributes
4143 * @param[in] external
4144 * This flow rule is created by request external to PMD.
4146 * Pointer to error structure.
4149 * 0 on success, a negative errno value otherwise and rte_errno is set.
4152 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4153 const struct rte_flow_attr *attributes,
4154 bool external __rte_unused,
4155 struct rte_flow_error *error)
4157 struct mlx5_priv *priv = dev->data->dev_private;
4158 uint32_t priority_max = priv->config.flow_prio - 1;
4160 #ifndef HAVE_MLX5DV_DR
4161 if (attributes->group)
4162 return rte_flow_error_set(error, ENOTSUP,
4163 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4165 "groups are not supported");
4170 ret = mlx5_flow_group_to_table(attributes, external,
4176 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4177 attributes->priority >= priority_max)
4178 return rte_flow_error_set(error, ENOTSUP,
4179 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4181 "priority out of range");
4182 if (attributes->transfer) {
4183 if (!priv->config.dv_esw_en)
4184 return rte_flow_error_set
4186 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4187 "E-Switch dr is not supported");
4188 if (!(priv->representor || priv->master))
4189 return rte_flow_error_set
4190 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4191 NULL, "E-Switch configuration can only be"
4192 " done by a master or a representor device");
4193 if (attributes->egress)
4194 return rte_flow_error_set
4196 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4197 "egress is not supported");
4199 if (!(attributes->egress ^ attributes->ingress))
4200 return rte_flow_error_set(error, ENOTSUP,
4201 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4202 "must specify exactly one of "
4203 "ingress or egress");
4208 * Internal validation function. For validating both actions and items.
4211 * Pointer to the rte_eth_dev structure.
4213 * Pointer to the flow attributes.
4215 * Pointer to the list of items.
4216 * @param[in] actions
4217 * Pointer to the list of actions.
4218 * @param[in] external
4219 * This flow rule is created by request external to PMD.
4221 * Pointer to the error structure.
4224 * 0 on success, a negative errno value otherwise and rte_errno is set.
4227 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4228 const struct rte_flow_item items[],
4229 const struct rte_flow_action actions[],
4230 bool external, struct rte_flow_error *error)
4233 uint64_t action_flags = 0;
4234 uint64_t item_flags = 0;
4235 uint64_t last_item = 0;
4236 uint8_t next_protocol = 0xff;
4237 uint16_t ether_type = 0;
4239 const struct rte_flow_item *gre_item = NULL;
4240 struct rte_flow_item_tcp nic_tcp_mask = {
4243 .src_port = RTE_BE16(UINT16_MAX),
4244 .dst_port = RTE_BE16(UINT16_MAX),
4247 struct mlx5_priv *priv = dev->data->dev_private;
4248 struct mlx5_dev_config *dev_conf = &priv->config;
4252 ret = flow_dv_validate_attributes(dev, attr, external, error);
4255 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4256 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4257 int type = items->type;
4260 case RTE_FLOW_ITEM_TYPE_VOID:
4262 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4263 ret = flow_dv_validate_item_port_id
4264 (dev, items, attr, item_flags, error);
4267 last_item = MLX5_FLOW_ITEM_PORT_ID;
4269 case RTE_FLOW_ITEM_TYPE_ETH:
4270 ret = mlx5_flow_validate_item_eth(items, item_flags,
4274 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4275 MLX5_FLOW_LAYER_OUTER_L2;
4276 if (items->mask != NULL && items->spec != NULL) {
4278 ((const struct rte_flow_item_eth *)
4281 ((const struct rte_flow_item_eth *)
4283 ether_type = rte_be_to_cpu_16(ether_type);
4288 case RTE_FLOW_ITEM_TYPE_VLAN:
4289 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4293 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4294 MLX5_FLOW_LAYER_OUTER_VLAN;
4295 if (items->mask != NULL && items->spec != NULL) {
4297 ((const struct rte_flow_item_vlan *)
4298 items->spec)->inner_type;
4300 ((const struct rte_flow_item_vlan *)
4301 items->mask)->inner_type;
4302 ether_type = rte_be_to_cpu_16(ether_type);
4307 case RTE_FLOW_ITEM_TYPE_IPV4:
4308 mlx5_flow_tunnel_ip_check(items, next_protocol,
4309 &item_flags, &tunnel);
4310 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4316 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4317 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4318 if (items->mask != NULL &&
4319 ((const struct rte_flow_item_ipv4 *)
4320 items->mask)->hdr.next_proto_id) {
4322 ((const struct rte_flow_item_ipv4 *)
4323 (items->spec))->hdr.next_proto_id;
4325 ((const struct rte_flow_item_ipv4 *)
4326 (items->mask))->hdr.next_proto_id;
4328 /* Reset for inner layer. */
4329 next_protocol = 0xff;
4332 case RTE_FLOW_ITEM_TYPE_IPV6:
4333 mlx5_flow_tunnel_ip_check(items, next_protocol,
4334 &item_flags, &tunnel);
4335 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4341 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4342 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4343 if (items->mask != NULL &&
4344 ((const struct rte_flow_item_ipv6 *)
4345 items->mask)->hdr.proto) {
4347 ((const struct rte_flow_item_ipv6 *)
4348 items->spec)->hdr.proto;
4350 ((const struct rte_flow_item_ipv6 *)
4351 items->mask)->hdr.proto;
4353 /* Reset for inner layer. */
4354 next_protocol = 0xff;
4357 case RTE_FLOW_ITEM_TYPE_TCP:
4358 ret = mlx5_flow_validate_item_tcp
4365 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4366 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4368 case RTE_FLOW_ITEM_TYPE_UDP:
4369 ret = mlx5_flow_validate_item_udp(items, item_flags,
4374 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4375 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4377 case RTE_FLOW_ITEM_TYPE_GRE:
4378 ret = mlx5_flow_validate_item_gre(items, item_flags,
4379 next_protocol, error);
4383 last_item = MLX5_FLOW_LAYER_GRE;
4385 case RTE_FLOW_ITEM_TYPE_NVGRE:
4386 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4391 last_item = MLX5_FLOW_LAYER_NVGRE;
4393 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4394 ret = mlx5_flow_validate_item_gre_key
4395 (items, item_flags, gre_item, error);
4398 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4400 case RTE_FLOW_ITEM_TYPE_VXLAN:
4401 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4405 last_item = MLX5_FLOW_LAYER_VXLAN;
4407 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4408 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4413 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4415 case RTE_FLOW_ITEM_TYPE_GENEVE:
4416 ret = mlx5_flow_validate_item_geneve(items,
4421 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4423 case RTE_FLOW_ITEM_TYPE_MPLS:
4424 ret = mlx5_flow_validate_item_mpls(dev, items,
4429 last_item = MLX5_FLOW_LAYER_MPLS;
4432 case RTE_FLOW_ITEM_TYPE_MARK:
4433 ret = flow_dv_validate_item_mark(dev, items, attr,
4437 last_item = MLX5_FLOW_ITEM_MARK;
4439 case RTE_FLOW_ITEM_TYPE_META:
4440 ret = flow_dv_validate_item_meta(dev, items, attr,
4444 last_item = MLX5_FLOW_ITEM_METADATA;
4446 case RTE_FLOW_ITEM_TYPE_ICMP:
4447 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4452 last_item = MLX5_FLOW_LAYER_ICMP;
4454 case RTE_FLOW_ITEM_TYPE_ICMP6:
4455 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4460 last_item = MLX5_FLOW_LAYER_ICMP6;
4462 case RTE_FLOW_ITEM_TYPE_TAG:
4463 ret = flow_dv_validate_item_tag(dev, items,
4467 last_item = MLX5_FLOW_ITEM_TAG;
4469 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4470 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4473 return rte_flow_error_set(error, ENOTSUP,
4474 RTE_FLOW_ERROR_TYPE_ITEM,
4475 NULL, "item not supported");
4477 item_flags |= last_item;
4479 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4480 int type = actions->type;
4481 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4482 return rte_flow_error_set(error, ENOTSUP,
4483 RTE_FLOW_ERROR_TYPE_ACTION,
4484 actions, "too many actions");
4486 case RTE_FLOW_ACTION_TYPE_VOID:
4488 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4489 ret = flow_dv_validate_action_port_id(dev,
4496 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4499 case RTE_FLOW_ACTION_TYPE_FLAG:
4500 ret = flow_dv_validate_action_flag(dev, action_flags,
4504 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4505 /* Count all modify-header actions as one. */
4506 if (!(action_flags &
4507 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4509 action_flags |= MLX5_FLOW_ACTION_FLAG |
4510 MLX5_FLOW_ACTION_MARK_EXT;
4512 action_flags |= MLX5_FLOW_ACTION_FLAG;
4516 case RTE_FLOW_ACTION_TYPE_MARK:
4517 ret = flow_dv_validate_action_mark(dev, actions,
4522 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4523 /* Count all modify-header actions as one. */
4524 if (!(action_flags &
4525 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4527 action_flags |= MLX5_FLOW_ACTION_MARK |
4528 MLX5_FLOW_ACTION_MARK_EXT;
4530 action_flags |= MLX5_FLOW_ACTION_MARK;
4534 case RTE_FLOW_ACTION_TYPE_SET_META:
4535 ret = flow_dv_validate_action_set_meta(dev, actions,
4540 /* Count all modify-header actions as one action. */
4541 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4543 action_flags |= MLX5_FLOW_ACTION_SET_META;
4545 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4546 ret = flow_dv_validate_action_set_tag(dev, actions,
4551 /* Count all modify-header actions as one action. */
4552 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4554 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4556 case RTE_FLOW_ACTION_TYPE_DROP:
4557 ret = mlx5_flow_validate_action_drop(action_flags,
4561 action_flags |= MLX5_FLOW_ACTION_DROP;
4564 case RTE_FLOW_ACTION_TYPE_QUEUE:
4565 ret = mlx5_flow_validate_action_queue(actions,
4570 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4573 case RTE_FLOW_ACTION_TYPE_RSS:
4574 ret = mlx5_flow_validate_action_rss(actions,
4580 action_flags |= MLX5_FLOW_ACTION_RSS;
4583 case RTE_FLOW_ACTION_TYPE_COUNT:
4584 ret = flow_dv_validate_action_count(dev, error);
4587 action_flags |= MLX5_FLOW_ACTION_COUNT;
4590 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4591 if (flow_dv_validate_action_pop_vlan(dev,
4597 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4600 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4601 ret = flow_dv_validate_action_push_vlan(action_flags,
4607 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4610 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4611 ret = flow_dv_validate_action_set_vlan_pcp
4612 (action_flags, actions, error);
4615 /* Count PCP with push_vlan command. */
4616 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4618 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4619 ret = flow_dv_validate_action_set_vlan_vid
4620 (item_flags, action_flags,
4624 /* Count VID with push_vlan command. */
4625 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4627 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4628 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4629 ret = flow_dv_validate_action_l2_encap(action_flags,
4634 action_flags |= actions->type ==
4635 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4636 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4637 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4640 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4641 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4642 ret = flow_dv_validate_action_l2_decap(action_flags,
4646 action_flags |= actions->type ==
4647 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4648 MLX5_FLOW_ACTION_VXLAN_DECAP :
4649 MLX5_FLOW_ACTION_NVGRE_DECAP;
4652 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4653 ret = flow_dv_validate_action_raw_encap(action_flags,
4658 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4661 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4662 ret = flow_dv_validate_action_raw_decap(action_flags,
4667 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4670 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4671 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4672 ret = flow_dv_validate_action_modify_mac(action_flags,
4678 /* Count all modify-header actions as one action. */
4679 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4681 action_flags |= actions->type ==
4682 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4683 MLX5_FLOW_ACTION_SET_MAC_SRC :
4684 MLX5_FLOW_ACTION_SET_MAC_DST;
4687 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4688 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4689 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4695 /* Count all modify-header actions as one action. */
4696 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4698 action_flags |= actions->type ==
4699 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4700 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4701 MLX5_FLOW_ACTION_SET_IPV4_DST;
4703 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4704 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4705 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4711 /* Count all modify-header actions as one action. */
4712 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4714 action_flags |= actions->type ==
4715 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4716 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4717 MLX5_FLOW_ACTION_SET_IPV6_DST;
4719 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4720 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4721 ret = flow_dv_validate_action_modify_tp(action_flags,
4727 /* Count all modify-header actions as one action. */
4728 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4730 action_flags |= actions->type ==
4731 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4732 MLX5_FLOW_ACTION_SET_TP_SRC :
4733 MLX5_FLOW_ACTION_SET_TP_DST;
4735 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4736 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4737 ret = flow_dv_validate_action_modify_ttl(action_flags,
4743 /* Count all modify-header actions as one action. */
4744 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4746 action_flags |= actions->type ==
4747 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4748 MLX5_FLOW_ACTION_SET_TTL :
4749 MLX5_FLOW_ACTION_DEC_TTL;
4751 case RTE_FLOW_ACTION_TYPE_JUMP:
4752 ret = flow_dv_validate_action_jump(actions,
4759 action_flags |= MLX5_FLOW_ACTION_JUMP;
4761 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4762 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4763 ret = flow_dv_validate_action_modify_tcp_seq
4770 /* Count all modify-header actions as one action. */
4771 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4773 action_flags |= actions->type ==
4774 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4775 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4776 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4778 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4779 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4780 ret = flow_dv_validate_action_modify_tcp_ack
4787 /* Count all modify-header actions as one action. */
4788 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4790 action_flags |= actions->type ==
4791 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4792 MLX5_FLOW_ACTION_INC_TCP_ACK :
4793 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4795 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4796 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4797 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4799 case RTE_FLOW_ACTION_TYPE_METER:
4800 ret = mlx5_flow_validate_action_meter(dev,
4806 action_flags |= MLX5_FLOW_ACTION_METER;
4810 return rte_flow_error_set(error, ENOTSUP,
4811 RTE_FLOW_ERROR_TYPE_ACTION,
4813 "action not supported");
4816 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4817 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4818 return rte_flow_error_set(error, ENOTSUP,
4819 RTE_FLOW_ERROR_TYPE_ACTION,
4821 "can't have vxlan and vlan"
4822 " actions in the same rule");
4823 /* Eswitch has few restrictions on using items and actions */
4824 if (attr->transfer) {
4825 if (!mlx5_flow_ext_mreg_supported(dev) &&
4826 action_flags & MLX5_FLOW_ACTION_FLAG)
4827 return rte_flow_error_set(error, ENOTSUP,
4828 RTE_FLOW_ERROR_TYPE_ACTION,
4830 "unsupported action FLAG");
4831 if (!mlx5_flow_ext_mreg_supported(dev) &&
4832 action_flags & MLX5_FLOW_ACTION_MARK)
4833 return rte_flow_error_set(error, ENOTSUP,
4834 RTE_FLOW_ERROR_TYPE_ACTION,
4836 "unsupported action MARK");
4837 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4838 return rte_flow_error_set(error, ENOTSUP,
4839 RTE_FLOW_ERROR_TYPE_ACTION,
4841 "unsupported action QUEUE");
4842 if (action_flags & MLX5_FLOW_ACTION_RSS)
4843 return rte_flow_error_set(error, ENOTSUP,
4844 RTE_FLOW_ERROR_TYPE_ACTION,
4846 "unsupported action RSS");
4847 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4848 return rte_flow_error_set(error, EINVAL,
4849 RTE_FLOW_ERROR_TYPE_ACTION,
4851 "no fate action is found");
4853 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4854 return rte_flow_error_set(error, EINVAL,
4855 RTE_FLOW_ERROR_TYPE_ACTION,
4857 "no fate action is found");
4863 * Internal preparation function. Allocates the DV flow size,
4864 * this size is constant.
4867 * Pointer to the flow attributes.
4869 * Pointer to the list of items.
4870 * @param[in] actions
4871 * Pointer to the list of actions.
4873 * Pointer to the error structure.
4876 * Pointer to mlx5_flow object on success,
4877 * otherwise NULL and rte_errno is set.
4879 static struct mlx5_flow *
4880 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4881 const struct rte_flow_item items[] __rte_unused,
4882 const struct rte_flow_action actions[] __rte_unused,
4883 struct rte_flow_error *error)
4885 size_t size = sizeof(struct mlx5_flow);
4886 struct mlx5_flow *dev_flow;
4888 dev_flow = rte_calloc(__func__, 1, size, 0);
4890 rte_flow_error_set(error, ENOMEM,
4891 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4892 "not enough memory to create flow");
4895 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4896 dev_flow->ingress = attr->ingress;
4897 dev_flow->transfer = attr->transfer;
4903 * Sanity check for match mask and value. Similar to check_valid_spec() in
4904 * kernel driver. If unmasked bit is present in value, it returns failure.
4907 * pointer to match mask buffer.
4908 * @param match_value
4909 * pointer to match value buffer.
4912 * 0 if valid, -EINVAL otherwise.
4915 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4917 uint8_t *m = match_mask;
4918 uint8_t *v = match_value;
4921 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4924 "match_value differs from match_criteria"
4925 " %p[%u] != %p[%u]",
4926 match_value, i, match_mask, i);
4935 * Add Ethernet item to matcher and to the value.
4937 * @param[in, out] matcher
4939 * @param[in, out] key
4940 * Flow matcher value.
4942 * Flow pattern to translate.
4944 * Item is inner pattern.
4947 flow_dv_translate_item_eth(void *matcher, void *key,
4948 const struct rte_flow_item *item, int inner)
4950 const struct rte_flow_item_eth *eth_m = item->mask;
4951 const struct rte_flow_item_eth *eth_v = item->spec;
4952 const struct rte_flow_item_eth nic_mask = {
4953 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4954 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4955 .type = RTE_BE16(0xffff),
4967 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4969 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4971 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4973 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4975 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4976 ð_m->dst, sizeof(eth_m->dst));
4977 /* The value must be in the range of the mask. */
4978 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4979 for (i = 0; i < sizeof(eth_m->dst); ++i)
4980 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4981 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4982 ð_m->src, sizeof(eth_m->src));
4983 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4984 /* The value must be in the range of the mask. */
4985 for (i = 0; i < sizeof(eth_m->dst); ++i)
4986 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4987 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4988 rte_be_to_cpu_16(eth_m->type));
4989 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4990 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4994 * Add VLAN item to matcher and to the value.
4996 * @param[in, out] dev_flow
4998 * @param[in, out] matcher
5000 * @param[in, out] key
5001 * Flow matcher value.
5003 * Flow pattern to translate.
5005 * Item is inner pattern.
5008 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5009 void *matcher, void *key,
5010 const struct rte_flow_item *item,
5013 const struct rte_flow_item_vlan *vlan_m = item->mask;
5014 const struct rte_flow_item_vlan *vlan_v = item->spec;
5023 vlan_m = &rte_flow_item_vlan_mask;
5025 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5027 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5029 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5031 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5033 * This is workaround, masks are not supported,
5034 * and pre-validated.
5036 dev_flow->dv.vf_vlan.tag =
5037 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5039 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5040 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5041 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5042 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5043 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5044 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5045 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5046 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5047 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5048 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5049 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5050 rte_be_to_cpu_16(vlan_m->inner_type));
5051 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5052 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5056 * Add IPV4 item to matcher and to the value.
5058 * @param[in, out] matcher
5060 * @param[in, out] key
5061 * Flow matcher value.
5063 * Flow pattern to translate.
5065 * Item is inner pattern.
5067 * The group to insert the rule.
5070 flow_dv_translate_item_ipv4(void *matcher, void *key,
5071 const struct rte_flow_item *item,
5072 int inner, uint32_t group)
5074 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5075 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5076 const struct rte_flow_item_ipv4 nic_mask = {
5078 .src_addr = RTE_BE32(0xffffffff),
5079 .dst_addr = RTE_BE32(0xffffffff),
5080 .type_of_service = 0xff,
5081 .next_proto_id = 0xff,
5091 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5093 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5095 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5097 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5100 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5102 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5103 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5108 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5109 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5110 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5111 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5112 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5113 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5114 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5115 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5116 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5117 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5118 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5119 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5120 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5121 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5122 ipv4_m->hdr.type_of_service);
5123 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5124 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5125 ipv4_m->hdr.type_of_service >> 2);
5126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5127 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5128 ipv4_m->hdr.next_proto_id);
5129 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5130 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5134 * Add IPV6 item to matcher and to the value.
5136 * @param[in, out] matcher
5138 * @param[in, out] key
5139 * Flow matcher value.
5141 * Flow pattern to translate.
5143 * Item is inner pattern.
5145 * The group to insert the rule.
5148 flow_dv_translate_item_ipv6(void *matcher, void *key,
5149 const struct rte_flow_item *item,
5150 int inner, uint32_t group)
5152 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5153 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5154 const struct rte_flow_item_ipv6 nic_mask = {
5157 "\xff\xff\xff\xff\xff\xff\xff\xff"
5158 "\xff\xff\xff\xff\xff\xff\xff\xff",
5160 "\xff\xff\xff\xff\xff\xff\xff\xff"
5161 "\xff\xff\xff\xff\xff\xff\xff\xff",
5162 .vtc_flow = RTE_BE32(0xffffffff),
5169 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5170 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5179 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5181 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5183 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5185 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5188 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5190 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5191 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5196 size = sizeof(ipv6_m->hdr.dst_addr);
5197 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5198 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5199 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5200 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5201 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5202 for (i = 0; i < size; ++i)
5203 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5204 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5205 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5206 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5207 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5208 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5209 for (i = 0; i < size; ++i)
5210 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5212 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5213 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5214 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5215 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5220 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5222 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5225 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5227 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5231 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5233 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5234 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5238 * Add TCP item to matcher and to the value.
5240 * @param[in, out] matcher
5242 * @param[in, out] key
5243 * Flow matcher value.
5245 * Flow pattern to translate.
5247 * Item is inner pattern.
5250 flow_dv_translate_item_tcp(void *matcher, void *key,
5251 const struct rte_flow_item *item,
5254 const struct rte_flow_item_tcp *tcp_m = item->mask;
5255 const struct rte_flow_item_tcp *tcp_v = item->spec;
5260 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5262 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5264 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5266 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5268 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5269 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5273 tcp_m = &rte_flow_item_tcp_mask;
5274 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5275 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5276 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5277 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5278 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5279 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5280 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5281 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5282 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5283 tcp_m->hdr.tcp_flags);
5284 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5285 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5289 * Add UDP item to matcher and to the value.
5291 * @param[in, out] matcher
5293 * @param[in, out] key
5294 * Flow matcher value.
5296 * Flow pattern to translate.
5298 * Item is inner pattern.
5301 flow_dv_translate_item_udp(void *matcher, void *key,
5302 const struct rte_flow_item *item,
5305 const struct rte_flow_item_udp *udp_m = item->mask;
5306 const struct rte_flow_item_udp *udp_v = item->spec;
5311 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5313 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5315 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5317 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5319 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5320 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5324 udp_m = &rte_flow_item_udp_mask;
5325 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5326 rte_be_to_cpu_16(udp_m->hdr.src_port));
5327 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5328 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5329 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5330 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5331 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5332 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5336 * Add GRE optional Key item to matcher and to the value.
5338 * @param[in, out] matcher
5340 * @param[in, out] key
5341 * Flow matcher value.
5343 * Flow pattern to translate.
5345 * Item is inner pattern.
5348 flow_dv_translate_item_gre_key(void *matcher, void *key,
5349 const struct rte_flow_item *item)
5351 const rte_be32_t *key_m = item->mask;
5352 const rte_be32_t *key_v = item->spec;
5353 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5354 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5355 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5360 key_m = &gre_key_default_mask;
5361 /* GRE K bit must be on and should already be validated */
5362 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5363 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5364 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5365 rte_be_to_cpu_32(*key_m) >> 8);
5366 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5367 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5368 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5369 rte_be_to_cpu_32(*key_m) & 0xFF);
5370 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5371 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5375 * Add GRE item to matcher and to the value.
5377 * @param[in, out] matcher
5379 * @param[in, out] key
5380 * Flow matcher value.
5382 * Flow pattern to translate.
5384 * Item is inner pattern.
5387 flow_dv_translate_item_gre(void *matcher, void *key,
5388 const struct rte_flow_item *item,
5391 const struct rte_flow_item_gre *gre_m = item->mask;
5392 const struct rte_flow_item_gre *gre_v = item->spec;
5395 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5396 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5403 uint16_t s_present:1;
5404 uint16_t k_present:1;
5405 uint16_t rsvd_bit1:1;
5406 uint16_t c_present:1;
5410 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5413 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5415 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5417 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5419 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5421 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5422 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5426 gre_m = &rte_flow_item_gre_mask;
5427 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5428 rte_be_to_cpu_16(gre_m->protocol));
5429 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5430 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5431 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5432 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5433 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5434 gre_crks_rsvd0_ver_m.c_present);
5435 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5436 gre_crks_rsvd0_ver_v.c_present &
5437 gre_crks_rsvd0_ver_m.c_present);
5438 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5439 gre_crks_rsvd0_ver_m.k_present);
5440 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5441 gre_crks_rsvd0_ver_v.k_present &
5442 gre_crks_rsvd0_ver_m.k_present);
5443 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5444 gre_crks_rsvd0_ver_m.s_present);
5445 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5446 gre_crks_rsvd0_ver_v.s_present &
5447 gre_crks_rsvd0_ver_m.s_present);
5451 * Add NVGRE item to matcher and to the value.
5453 * @param[in, out] matcher
5455 * @param[in, out] key
5456 * Flow matcher value.
5458 * Flow pattern to translate.
5460 * Item is inner pattern.
5463 flow_dv_translate_item_nvgre(void *matcher, void *key,
5464 const struct rte_flow_item *item,
5467 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5468 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5469 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5470 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5471 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5472 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5478 /* For NVGRE, GRE header fields must be set with defined values. */
5479 const struct rte_flow_item_gre gre_spec = {
5480 .c_rsvd0_ver = RTE_BE16(0x2000),
5481 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5483 const struct rte_flow_item_gre gre_mask = {
5484 .c_rsvd0_ver = RTE_BE16(0xB000),
5485 .protocol = RTE_BE16(UINT16_MAX),
5487 const struct rte_flow_item gre_item = {
5492 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5496 nvgre_m = &rte_flow_item_nvgre_mask;
5497 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5498 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5499 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5500 memcpy(gre_key_m, tni_flow_id_m, size);
5501 for (i = 0; i < size; ++i)
5502 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5506 * Add VXLAN item to matcher and to the value.
5508 * @param[in, out] matcher
5510 * @param[in, out] key
5511 * Flow matcher value.
5513 * Flow pattern to translate.
5515 * Item is inner pattern.
5518 flow_dv_translate_item_vxlan(void *matcher, void *key,
5519 const struct rte_flow_item *item,
5522 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5523 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5526 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5527 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5535 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5537 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5539 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5541 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5543 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5544 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5545 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5546 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5547 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5552 vxlan_m = &rte_flow_item_vxlan_mask;
5553 size = sizeof(vxlan_m->vni);
5554 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5555 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5556 memcpy(vni_m, vxlan_m->vni, size);
5557 for (i = 0; i < size; ++i)
5558 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5562 * Add Geneve item to matcher and to the value.
5564 * @param[in, out] matcher
5566 * @param[in, out] key
5567 * Flow matcher value.
5569 * Flow pattern to translate.
5571 * Item is inner pattern.
5575 flow_dv_translate_item_geneve(void *matcher, void *key,
5576 const struct rte_flow_item *item, int inner)
5578 const struct rte_flow_item_geneve *geneve_m = item->mask;
5579 const struct rte_flow_item_geneve *geneve_v = item->spec;
5582 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5583 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5592 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5594 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5596 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5598 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5600 dport = MLX5_UDP_PORT_GENEVE;
5601 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5602 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5603 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5608 geneve_m = &rte_flow_item_geneve_mask;
5609 size = sizeof(geneve_m->vni);
5610 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5611 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5612 memcpy(vni_m, geneve_m->vni, size);
5613 for (i = 0; i < size; ++i)
5614 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5615 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5616 rte_be_to_cpu_16(geneve_m->protocol));
5617 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5618 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5619 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5620 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5621 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5622 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5623 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5624 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5625 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5626 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5627 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5628 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5629 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5633 * Add MPLS item to matcher and to the value.
5635 * @param[in, out] matcher
5637 * @param[in, out] key
5638 * Flow matcher value.
5640 * Flow pattern to translate.
5641 * @param[in] prev_layer
5642 * The protocol layer indicated in previous item.
5644 * Item is inner pattern.
5647 flow_dv_translate_item_mpls(void *matcher, void *key,
5648 const struct rte_flow_item *item,
5649 uint64_t prev_layer,
5652 const uint32_t *in_mpls_m = item->mask;
5653 const uint32_t *in_mpls_v = item->spec;
5654 uint32_t *out_mpls_m = 0;
5655 uint32_t *out_mpls_v = 0;
5656 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5657 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5658 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5660 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5661 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5662 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5664 switch (prev_layer) {
5665 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5666 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5667 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5668 MLX5_UDP_PORT_MPLS);
5670 case MLX5_FLOW_LAYER_GRE:
5671 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5672 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5673 RTE_ETHER_TYPE_MPLS);
5676 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5684 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5685 switch (prev_layer) {
5686 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5688 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5689 outer_first_mpls_over_udp);
5691 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5692 outer_first_mpls_over_udp);
5694 case MLX5_FLOW_LAYER_GRE:
5696 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5697 outer_first_mpls_over_gre);
5699 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5700 outer_first_mpls_over_gre);
5703 /* Inner MPLS not over GRE is not supported. */
5706 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5710 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5716 if (out_mpls_m && out_mpls_v) {
5717 *out_mpls_m = *in_mpls_m;
5718 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5723 * Add metadata register item to matcher
5725 * @param[in, out] matcher
5727 * @param[in, out] key
5728 * Flow matcher value.
5729 * @param[in] reg_type
5730 * Type of device metadata register
5737 flow_dv_match_meta_reg(void *matcher, void *key,
5738 enum modify_reg reg_type,
5739 uint32_t data, uint32_t mask)
5742 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5744 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5749 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5750 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5753 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5754 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5757 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5758 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5761 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5762 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5765 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5766 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5769 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5770 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5773 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5774 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5777 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5778 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5781 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5782 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5785 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5786 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5795 * Add MARK item to matcher
5798 * The device to configure through.
5799 * @param[in, out] matcher
5801 * @param[in, out] key
5802 * Flow matcher value.
5804 * Flow pattern to translate.
5807 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
5808 void *matcher, void *key,
5809 const struct rte_flow_item *item)
5811 struct mlx5_priv *priv = dev->data->dev_private;
5812 const struct rte_flow_item_mark *mark;
5816 mark = item->mask ? (const void *)item->mask :
5817 &rte_flow_item_mark_mask;
5818 mask = mark->id & priv->sh->dv_mark_mask;
5819 mark = (const void *)item->spec;
5821 value = mark->id & priv->sh->dv_mark_mask & mask;
5823 enum modify_reg reg;
5825 /* Get the metadata register index for the mark. */
5826 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
5828 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
5833 * Add META item to matcher
5836 * The devich to configure through.
5837 * @param[in, out] matcher
5839 * @param[in, out] key
5840 * Flow matcher value.
5842 * Attributes of flow that includes this item.
5844 * Flow pattern to translate.
5847 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
5848 void *matcher, void *key,
5849 const struct rte_flow_attr *attr,
5850 const struct rte_flow_item *item)
5852 const struct rte_flow_item_meta *meta_m;
5853 const struct rte_flow_item_meta *meta_v;
5855 meta_m = (const void *)item->mask;
5857 meta_m = &rte_flow_item_meta_mask;
5858 meta_v = (const void *)item->spec;
5860 enum modify_reg reg;
5861 uint32_t value = meta_v->data;
5862 uint32_t mask = meta_m->data;
5864 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
5868 * In datapath code there is no endianness
5869 * coversions for perfromance reasons, all
5870 * pattern conversions are done in rte_flow.
5872 value = rte_cpu_to_be_32(value);
5873 mask = rte_cpu_to_be_32(mask);
5874 if (reg == REG_C_0) {
5875 struct mlx5_priv *priv = dev->data->dev_private;
5876 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
5877 uint32_t shl_c0 = rte_bsf32(msk_c0);
5879 msk_c0 = rte_cpu_to_be_32(msk_c0);
5883 assert(!(~msk_c0 & mask));
5885 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
5890 * Add vport metadata Reg C0 item to matcher
5892 * @param[in, out] matcher
5894 * @param[in, out] key
5895 * Flow matcher value.
5897 * Flow pattern to translate.
5900 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5901 uint32_t value, uint32_t mask)
5903 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5907 * Add tag item to matcher
5909 * @param[in, out] matcher
5911 * @param[in, out] key
5912 * Flow matcher value.
5914 * Flow pattern to translate.
5917 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5918 const struct rte_flow_item *item)
5920 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5921 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5924 flow_dv_match_meta_reg(matcher, key, tag_v->id, tag_v->data,
5925 tag_m ? tag_m->data : UINT32_MAX);
5929 * Add TAG item to matcher
5932 * The devich to configure through.
5933 * @param[in, out] matcher
5935 * @param[in, out] key
5936 * Flow matcher value.
5938 * Flow pattern to translate.
5941 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
5942 void *matcher, void *key,
5943 const struct rte_flow_item *item)
5945 const struct rte_flow_item_tag *tag_v = item->spec;
5946 const struct rte_flow_item_tag *tag_m = item->mask;
5947 enum modify_reg reg;
5950 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
5951 /* Get the metadata register index for the tag. */
5952 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
5954 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5958 * Add source vport match to the specified matcher.
5960 * @param[in, out] matcher
5962 * @param[in, out] key
5963 * Flow matcher value.
5965 * Source vport value to match
5970 flow_dv_translate_item_source_vport(void *matcher, void *key,
5971 int16_t port, uint16_t mask)
5973 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5974 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5976 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5977 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5981 * Translate port-id item to eswitch match on port-id.
5984 * The devich to configure through.
5985 * @param[in, out] matcher
5987 * @param[in, out] key
5988 * Flow matcher value.
5990 * Flow pattern to translate.
5993 * 0 on success, a negative errno value otherwise.
5996 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5997 void *key, const struct rte_flow_item *item)
5999 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6000 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6001 struct mlx5_priv *priv;
6004 mask = pid_m ? pid_m->id : 0xffff;
6005 id = pid_v ? pid_v->id : dev->data->port_id;
6006 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6009 /* Translate to vport field or to metadata, depending on mode. */
6010 if (priv->vport_meta_mask)
6011 flow_dv_translate_item_meta_vport(matcher, key,
6012 priv->vport_meta_tag,
6013 priv->vport_meta_mask);
6015 flow_dv_translate_item_source_vport(matcher, key,
6016 priv->vport_id, mask);
6021 * Add ICMP6 item to matcher and to the value.
6023 * @param[in, out] matcher
6025 * @param[in, out] key
6026 * Flow matcher value.
6028 * Flow pattern to translate.
6030 * Item is inner pattern.
6033 flow_dv_translate_item_icmp6(void *matcher, void *key,
6034 const struct rte_flow_item *item,
6037 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6038 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6041 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6043 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6045 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6047 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6049 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6051 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6053 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6054 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6058 icmp6_m = &rte_flow_item_icmp6_mask;
6059 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6060 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6061 icmp6_v->type & icmp6_m->type);
6062 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6063 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6064 icmp6_v->code & icmp6_m->code);
6068 * Add ICMP item to matcher and to the value.
6070 * @param[in, out] matcher
6072 * @param[in, out] key
6073 * Flow matcher value.
6075 * Flow pattern to translate.
6077 * Item is inner pattern.
6080 flow_dv_translate_item_icmp(void *matcher, void *key,
6081 const struct rte_flow_item *item,
6084 const struct rte_flow_item_icmp *icmp_m = item->mask;
6085 const struct rte_flow_item_icmp *icmp_v = item->spec;
6088 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6090 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6092 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6094 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6096 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6098 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6100 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6101 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6105 icmp_m = &rte_flow_item_icmp_mask;
6106 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6107 icmp_m->hdr.icmp_type);
6108 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6109 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6110 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6111 icmp_m->hdr.icmp_code);
6112 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6113 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6116 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6118 #define HEADER_IS_ZERO(match_criteria, headers) \
6119 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6120 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6123 * Calculate flow matcher enable bitmap.
6125 * @param match_criteria
6126 * Pointer to flow matcher criteria.
6129 * Bitmap of enabled fields.
6132 flow_dv_matcher_enable(uint32_t *match_criteria)
6134 uint8_t match_criteria_enable;
6136 match_criteria_enable =
6137 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6138 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6139 match_criteria_enable |=
6140 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6141 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6142 match_criteria_enable |=
6143 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6144 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6145 match_criteria_enable |=
6146 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6147 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6148 match_criteria_enable |=
6149 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6150 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6151 return match_criteria_enable;
6158 * @param[in, out] dev
6159 * Pointer to rte_eth_dev structure.
6160 * @param[in] table_id
6163 * Direction of the table.
6164 * @param[in] transfer
6165 * E-Switch or NIC flow.
6167 * pointer to error structure.
6170 * Returns tables resource based on the index, NULL in case of failed.
6172 static struct mlx5_flow_tbl_resource *
6173 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6174 uint32_t table_id, uint8_t egress,
6176 struct rte_flow_error *error)
6178 struct mlx5_priv *priv = dev->data->dev_private;
6179 struct mlx5_ibv_shared *sh = priv->sh;
6180 struct mlx5_flow_tbl_resource *tbl;
6181 union mlx5_flow_tbl_key table_key = {
6183 .table_id = table_id,
6185 .domain = !!transfer,
6186 .direction = !!egress,
6189 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6191 struct mlx5_flow_tbl_data_entry *tbl_data;
6196 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6198 tbl = &tbl_data->tbl;
6199 rte_atomic32_inc(&tbl->refcnt);
6202 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6204 rte_flow_error_set(error, ENOMEM,
6205 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6207 "cannot allocate flow table data entry");
6210 tbl = &tbl_data->tbl;
6211 pos = &tbl_data->entry;
6213 domain = sh->fdb_domain;
6215 domain = sh->tx_domain;
6217 domain = sh->rx_domain;
6218 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6220 rte_flow_error_set(error, ENOMEM,
6221 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6222 NULL, "cannot create flow table object");
6227 * No multi-threads now, but still better to initialize the reference
6228 * count before insert it into the hash list.
6230 rte_atomic32_init(&tbl->refcnt);
6231 /* Jump action reference count is initialized here. */
6232 rte_atomic32_init(&tbl_data->jump.refcnt);
6233 pos->key = table_key.v64;
6234 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6236 rte_flow_error_set(error, -ret,
6237 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6238 "cannot insert flow table data entry");
6239 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6242 rte_atomic32_inc(&tbl->refcnt);
6247 * Release a flow table.
6250 * Pointer to rte_eth_dev structure.
6252 * Table resource to be released.
6255 * Returns 0 if table was released, else return 1;
6258 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6259 struct mlx5_flow_tbl_resource *tbl)
6261 struct mlx5_priv *priv = dev->data->dev_private;
6262 struct mlx5_ibv_shared *sh = priv->sh;
6263 struct mlx5_flow_tbl_data_entry *tbl_data =
6264 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6268 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6269 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6271 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6273 /* remove the entry from the hash list and free memory. */
6274 mlx5_hlist_remove(sh->flow_tbls, pos);
6282 * Register the flow matcher.
6284 * @param[in, out] dev
6285 * Pointer to rte_eth_dev structure.
6286 * @param[in, out] matcher
6287 * Pointer to flow matcher.
6288 * @param[in, out] key
6289 * Pointer to flow table key.
6290 * @parm[in, out] dev_flow
6291 * Pointer to the dev_flow.
6293 * pointer to error structure.
6296 * 0 on success otherwise -errno and errno is set.
6299 flow_dv_matcher_register(struct rte_eth_dev *dev,
6300 struct mlx5_flow_dv_matcher *matcher,
6301 union mlx5_flow_tbl_key *key,
6302 struct mlx5_flow *dev_flow,
6303 struct rte_flow_error *error)
6305 struct mlx5_priv *priv = dev->data->dev_private;
6306 struct mlx5_ibv_shared *sh = priv->sh;
6307 struct mlx5_flow_dv_matcher *cache_matcher;
6308 struct mlx5dv_flow_matcher_attr dv_attr = {
6309 .type = IBV_FLOW_ATTR_NORMAL,
6310 .match_mask = (void *)&matcher->mask,
6312 struct mlx5_flow_tbl_resource *tbl;
6313 struct mlx5_flow_tbl_data_entry *tbl_data;
6315 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6316 key->domain, error);
6318 return -rte_errno; /* No need to refill the error info */
6319 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6320 /* Lookup from cache. */
6321 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6322 if (matcher->crc == cache_matcher->crc &&
6323 matcher->priority == cache_matcher->priority &&
6324 !memcmp((const void *)matcher->mask.buf,
6325 (const void *)cache_matcher->mask.buf,
6326 cache_matcher->mask.size)) {
6328 "%s group %u priority %hd use %s "
6329 "matcher %p: refcnt %d++",
6330 key->domain ? "FDB" : "NIC", key->table_id,
6331 cache_matcher->priority,
6332 key->direction ? "tx" : "rx",
6333 (void *)cache_matcher,
6334 rte_atomic32_read(&cache_matcher->refcnt));
6335 rte_atomic32_inc(&cache_matcher->refcnt);
6336 dev_flow->dv.matcher = cache_matcher;
6337 /* old matcher should not make the table ref++. */
6338 flow_dv_tbl_resource_release(dev, tbl);
6342 /* Register new matcher. */
6343 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6344 if (!cache_matcher) {
6345 flow_dv_tbl_resource_release(dev, tbl);
6346 return rte_flow_error_set(error, ENOMEM,
6347 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6348 "cannot allocate matcher memory");
6350 *cache_matcher = *matcher;
6351 dv_attr.match_criteria_enable =
6352 flow_dv_matcher_enable(cache_matcher->mask.buf);
6353 dv_attr.priority = matcher->priority;
6355 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6356 cache_matcher->matcher_object =
6357 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6358 if (!cache_matcher->matcher_object) {
6359 rte_free(cache_matcher);
6360 #ifdef HAVE_MLX5DV_DR
6361 flow_dv_tbl_resource_release(dev, tbl);
6363 return rte_flow_error_set(error, ENOMEM,
6364 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6365 NULL, "cannot create matcher");
6367 /* Save the table information */
6368 cache_matcher->tbl = tbl;
6369 rte_atomic32_init(&cache_matcher->refcnt);
6370 /* only matcher ref++, table ref++ already done above in get API. */
6371 rte_atomic32_inc(&cache_matcher->refcnt);
6372 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6373 dev_flow->dv.matcher = cache_matcher;
6374 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6375 key->domain ? "FDB" : "NIC", key->table_id,
6376 cache_matcher->priority,
6377 key->direction ? "tx" : "rx", (void *)cache_matcher,
6378 rte_atomic32_read(&cache_matcher->refcnt));
6383 * Find existing tag resource or create and register a new one.
6385 * @param dev[in, out]
6386 * Pointer to rte_eth_dev structure.
6387 * @param[in, out] tag_be24
6388 * Tag value in big endian then R-shift 8.
6389 * @parm[in, out] dev_flow
6390 * Pointer to the dev_flow.
6392 * pointer to error structure.
6395 * 0 on success otherwise -errno and errno is set.
6398 flow_dv_tag_resource_register
6399 (struct rte_eth_dev *dev,
6401 struct mlx5_flow *dev_flow,
6402 struct rte_flow_error *error)
6404 struct mlx5_priv *priv = dev->data->dev_private;
6405 struct mlx5_ibv_shared *sh = priv->sh;
6406 struct mlx5_flow_dv_tag_resource *cache_resource;
6407 struct mlx5_hlist_entry *entry;
6409 /* Lookup a matching resource from cache. */
6410 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6412 cache_resource = container_of
6413 (entry, struct mlx5_flow_dv_tag_resource, entry);
6414 rte_atomic32_inc(&cache_resource->refcnt);
6415 dev_flow->dv.tag_resource = cache_resource;
6416 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6417 (void *)cache_resource,
6418 rte_atomic32_read(&cache_resource->refcnt));
6421 /* Register new resource. */
6422 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6423 if (!cache_resource)
6424 return rte_flow_error_set(error, ENOMEM,
6425 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6426 "cannot allocate resource memory");
6427 cache_resource->entry.key = (uint64_t)tag_be24;
6428 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6429 if (!cache_resource->action) {
6430 rte_free(cache_resource);
6431 return rte_flow_error_set(error, ENOMEM,
6432 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6433 NULL, "cannot create action");
6435 rte_atomic32_init(&cache_resource->refcnt);
6436 rte_atomic32_inc(&cache_resource->refcnt);
6437 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6438 mlx5_glue->destroy_flow_action(cache_resource->action);
6439 rte_free(cache_resource);
6440 return rte_flow_error_set(error, EEXIST,
6441 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6442 NULL, "cannot insert tag");
6444 dev_flow->dv.tag_resource = cache_resource;
6445 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6446 (void *)cache_resource,
6447 rte_atomic32_read(&cache_resource->refcnt));
6455 * Pointer to Ethernet device.
6457 * Pointer to mlx5_flow.
6460 * 1 while a reference on it exists, 0 when freed.
6463 flow_dv_tag_release(struct rte_eth_dev *dev,
6464 struct mlx5_flow_dv_tag_resource *tag)
6466 struct mlx5_priv *priv = dev->data->dev_private;
6467 struct mlx5_ibv_shared *sh = priv->sh;
6470 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6471 dev->data->port_id, (void *)tag,
6472 rte_atomic32_read(&tag->refcnt));
6473 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6474 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6475 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6476 DRV_LOG(DEBUG, "port %u tag %p: removed",
6477 dev->data->port_id, (void *)tag);
6485 * Translate port ID action to vport.
6488 * Pointer to rte_eth_dev structure.
6490 * Pointer to the port ID action.
6491 * @param[out] dst_port_id
6492 * The target port ID.
6494 * Pointer to the error structure.
6497 * 0 on success, a negative errno value otherwise and rte_errno is set.
6500 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6501 const struct rte_flow_action *action,
6502 uint32_t *dst_port_id,
6503 struct rte_flow_error *error)
6506 struct mlx5_priv *priv;
6507 const struct rte_flow_action_port_id *conf =
6508 (const struct rte_flow_action_port_id *)action->conf;
6510 port = conf->original ? dev->data->port_id : conf->id;
6511 priv = mlx5_port_to_eswitch_info(port, false);
6513 return rte_flow_error_set(error, -rte_errno,
6514 RTE_FLOW_ERROR_TYPE_ACTION,
6516 "No eswitch info was found for port");
6517 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6519 * This parameter is transferred to
6520 * mlx5dv_dr_action_create_dest_ib_port().
6522 *dst_port_id = priv->ibv_port;
6525 * Legacy mode, no LAG configurations is supported.
6526 * This parameter is transferred to
6527 * mlx5dv_dr_action_create_dest_vport().
6529 *dst_port_id = priv->vport_id;
6535 * Add Tx queue matcher
6538 * Pointer to the dev struct.
6539 * @param[in, out] matcher
6541 * @param[in, out] key
6542 * Flow matcher value.
6544 * Flow pattern to translate.
6546 * Item is inner pattern.
6549 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6550 void *matcher, void *key,
6551 const struct rte_flow_item *item)
6553 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6554 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6556 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6558 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6559 struct mlx5_txq_ctrl *txq;
6563 queue_m = (const void *)item->mask;
6566 queue_v = (const void *)item->spec;
6569 txq = mlx5_txq_get(dev, queue_v->queue);
6572 queue = txq->obj->sq->id;
6573 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6574 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6575 queue & queue_m->queue);
6576 mlx5_txq_release(dev, queue_v->queue);
6580 * Fill the flow with DV spec, lock free
6581 * (mutex should be acquired by caller).
6584 * Pointer to rte_eth_dev structure.
6585 * @param[in, out] dev_flow
6586 * Pointer to the sub flow.
6588 * Pointer to the flow attributes.
6590 * Pointer to the list of items.
6591 * @param[in] actions
6592 * Pointer to the list of actions.
6594 * Pointer to the error structure.
6597 * 0 on success, a negative errno value otherwise and rte_errno is set.
6600 __flow_dv_translate(struct rte_eth_dev *dev,
6601 struct mlx5_flow *dev_flow,
6602 const struct rte_flow_attr *attr,
6603 const struct rte_flow_item items[],
6604 const struct rte_flow_action actions[],
6605 struct rte_flow_error *error)
6607 struct mlx5_priv *priv = dev->data->dev_private;
6608 struct mlx5_dev_config *dev_conf = &priv->config;
6609 struct rte_flow *flow = dev_flow->flow;
6610 uint64_t item_flags = 0;
6611 uint64_t last_item = 0;
6612 uint64_t action_flags = 0;
6613 uint64_t priority = attr->priority;
6614 struct mlx5_flow_dv_matcher matcher = {
6616 .size = sizeof(matcher.mask.buf),
6620 bool actions_end = false;
6621 struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
6622 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
6623 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
6625 union flow_dv_attr flow_attr = { .attr = 0 };
6627 union mlx5_flow_tbl_key tbl_key;
6628 uint32_t modify_action_position = UINT32_MAX;
6629 void *match_mask = matcher.mask.buf;
6630 void *match_value = dev_flow->dv.value.buf;
6631 uint8_t next_protocol = 0xff;
6632 struct rte_vlan_hdr vlan = { 0 };
6636 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
6640 dev_flow->group = table;
6642 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
6643 if (priority == MLX5_FLOW_PRIO_RSVD)
6644 priority = dev_conf->flow_prio - 1;
6645 for (; !actions_end ; actions++) {
6646 const struct rte_flow_action_queue *queue;
6647 const struct rte_flow_action_rss *rss;
6648 const struct rte_flow_action *action = actions;
6649 const struct rte_flow_action_count *count = action->conf;
6650 const uint8_t *rss_key;
6651 const struct rte_flow_action_jump *jump_data;
6652 const struct rte_flow_action_meter *mtr;
6653 struct mlx5_flow_tbl_resource *tbl;
6654 uint32_t port_id = 0;
6655 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
6656 int action_type = actions->type;
6657 const struct rte_flow_action *found_action = NULL;
6659 switch (action_type) {
6660 case RTE_FLOW_ACTION_TYPE_VOID:
6662 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6663 if (flow_dv_translate_action_port_id(dev, action,
6666 port_id_resource.port_id = port_id;
6667 if (flow_dv_port_id_action_resource_register
6668 (dev, &port_id_resource, dev_flow, error))
6670 dev_flow->dv.actions[actions_n++] =
6671 dev_flow->dv.port_id_action->action;
6672 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6674 case RTE_FLOW_ACTION_TYPE_FLAG:
6675 action_flags |= MLX5_FLOW_ACTION_FLAG;
6676 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6677 struct rte_flow_action_mark mark = {
6678 .id = MLX5_FLOW_MARK_DEFAULT,
6681 if (flow_dv_convert_action_mark(dev, &mark,
6685 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
6688 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
6689 if (!dev_flow->dv.tag_resource)
6690 if (flow_dv_tag_resource_register
6691 (dev, tag_be, dev_flow, error))
6693 dev_flow->dv.actions[actions_n++] =
6694 dev_flow->dv.tag_resource->action;
6696 case RTE_FLOW_ACTION_TYPE_MARK:
6697 action_flags |= MLX5_FLOW_ACTION_MARK;
6698 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6699 const struct rte_flow_action_mark *mark =
6700 (const struct rte_flow_action_mark *)
6703 if (flow_dv_convert_action_mark(dev, mark,
6707 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
6711 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6712 /* Legacy (non-extensive) MARK action. */
6713 tag_be = mlx5_flow_mark_set
6714 (((const struct rte_flow_action_mark *)
6715 (actions->conf))->id);
6716 if (!dev_flow->dv.tag_resource)
6717 if (flow_dv_tag_resource_register
6718 (dev, tag_be, dev_flow, error))
6720 dev_flow->dv.actions[actions_n++] =
6721 dev_flow->dv.tag_resource->action;
6723 case RTE_FLOW_ACTION_TYPE_SET_META:
6724 if (flow_dv_convert_action_set_meta
6725 (dev, &mhdr_res, attr,
6726 (const struct rte_flow_action_set_meta *)
6727 actions->conf, error))
6729 action_flags |= MLX5_FLOW_ACTION_SET_META;
6731 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6732 if (flow_dv_convert_action_set_tag
6734 (const struct rte_flow_action_set_tag *)
6735 actions->conf, error))
6737 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6739 case RTE_FLOW_ACTION_TYPE_DROP:
6740 action_flags |= MLX5_FLOW_ACTION_DROP;
6742 case RTE_FLOW_ACTION_TYPE_QUEUE:
6743 assert(flow->rss.queue);
6744 queue = actions->conf;
6745 flow->rss.queue_num = 1;
6746 (*flow->rss.queue)[0] = queue->index;
6747 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6749 case RTE_FLOW_ACTION_TYPE_RSS:
6750 assert(flow->rss.queue);
6751 rss = actions->conf;
6752 if (flow->rss.queue)
6753 memcpy((*flow->rss.queue), rss->queue,
6754 rss->queue_num * sizeof(uint16_t));
6755 flow->rss.queue_num = rss->queue_num;
6756 /* NULL RSS key indicates default RSS key. */
6757 rss_key = !rss->key ? rss_hash_default_key : rss->key;
6758 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
6760 * rss->level and rss.types should be set in advance
6761 * when expanding items for RSS.
6763 action_flags |= MLX5_FLOW_ACTION_RSS;
6765 case RTE_FLOW_ACTION_TYPE_COUNT:
6766 if (!dev_conf->devx) {
6767 rte_errno = ENOTSUP;
6770 flow->counter = flow_dv_counter_alloc(dev,
6774 if (flow->counter == NULL)
6776 dev_flow->dv.actions[actions_n++] =
6777 flow->counter->action;
6778 action_flags |= MLX5_FLOW_ACTION_COUNT;
6781 if (rte_errno == ENOTSUP)
6782 return rte_flow_error_set
6784 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6786 "count action not supported");
6788 return rte_flow_error_set
6790 RTE_FLOW_ERROR_TYPE_ACTION,
6792 "cannot create counter"
6795 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6796 dev_flow->dv.actions[actions_n++] =
6797 priv->sh->pop_vlan_action;
6798 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6800 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6801 flow_dev_get_vlan_info_from_items(items, &vlan);
6802 vlan.eth_proto = rte_be_to_cpu_16
6803 ((((const struct rte_flow_action_of_push_vlan *)
6804 actions->conf)->ethertype));
6805 found_action = mlx5_flow_find_action
6807 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
6809 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6810 found_action = mlx5_flow_find_action
6812 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
6814 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6815 if (flow_dv_create_action_push_vlan
6816 (dev, attr, &vlan, dev_flow, error))
6818 dev_flow->dv.actions[actions_n++] =
6819 dev_flow->dv.push_vlan_res->action;
6820 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6822 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6823 /* of_vlan_push action handled this action */
6824 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
6826 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6827 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6829 flow_dev_get_vlan_info_from_items(items, &vlan);
6830 mlx5_update_vlan_vid_pcp(actions, &vlan);
6831 /* If no VLAN push - this is a modify header action */
6832 if (flow_dv_convert_action_modify_vlan_vid
6833 (&mhdr_res, actions, error))
6835 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6837 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6838 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6839 if (flow_dv_create_action_l2_encap(dev, actions,
6844 dev_flow->dv.actions[actions_n++] =
6845 dev_flow->dv.encap_decap->verbs_action;
6846 action_flags |= actions->type ==
6847 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
6848 MLX5_FLOW_ACTION_VXLAN_ENCAP :
6849 MLX5_FLOW_ACTION_NVGRE_ENCAP;
6851 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6852 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6853 if (flow_dv_create_action_l2_decap(dev, dev_flow,
6857 dev_flow->dv.actions[actions_n++] =
6858 dev_flow->dv.encap_decap->verbs_action;
6859 action_flags |= actions->type ==
6860 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
6861 MLX5_FLOW_ACTION_VXLAN_DECAP :
6862 MLX5_FLOW_ACTION_NVGRE_DECAP;
6864 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6865 /* Handle encap with preceding decap. */
6866 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
6867 if (flow_dv_create_action_raw_encap
6868 (dev, actions, dev_flow, attr, error))
6870 dev_flow->dv.actions[actions_n++] =
6871 dev_flow->dv.encap_decap->verbs_action;
6873 /* Handle encap without preceding decap. */
6874 if (flow_dv_create_action_l2_encap
6875 (dev, actions, dev_flow, attr->transfer,
6878 dev_flow->dv.actions[actions_n++] =
6879 dev_flow->dv.encap_decap->verbs_action;
6881 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
6883 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6884 /* Check if this decap is followed by encap. */
6885 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
6886 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
6889 /* Handle decap only if it isn't followed by encap. */
6890 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6891 if (flow_dv_create_action_l2_decap
6892 (dev, dev_flow, attr->transfer, error))
6894 dev_flow->dv.actions[actions_n++] =
6895 dev_flow->dv.encap_decap->verbs_action;
6897 /* If decap is followed by encap, handle it at encap. */
6898 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
6900 case RTE_FLOW_ACTION_TYPE_JUMP:
6901 jump_data = action->conf;
6902 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
6903 jump_data->group, &table,
6907 tbl = flow_dv_tbl_resource_get(dev, table,
6909 attr->transfer, error);
6911 return rte_flow_error_set
6913 RTE_FLOW_ERROR_TYPE_ACTION,
6915 "cannot create jump action.");
6916 if (flow_dv_jump_tbl_resource_register
6917 (dev, tbl, dev_flow, error)) {
6918 flow_dv_tbl_resource_release(dev, tbl);
6919 return rte_flow_error_set
6921 RTE_FLOW_ERROR_TYPE_ACTION,
6923 "cannot create jump action.");
6925 dev_flow->dv.actions[actions_n++] =
6926 dev_flow->dv.jump->action;
6927 action_flags |= MLX5_FLOW_ACTION_JUMP;
6929 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6930 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6931 if (flow_dv_convert_action_modify_mac
6932 (&mhdr_res, actions, error))
6934 action_flags |= actions->type ==
6935 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6936 MLX5_FLOW_ACTION_SET_MAC_SRC :
6937 MLX5_FLOW_ACTION_SET_MAC_DST;
6939 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6940 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6941 if (flow_dv_convert_action_modify_ipv4
6942 (&mhdr_res, actions, error))
6944 action_flags |= actions->type ==
6945 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6946 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6947 MLX5_FLOW_ACTION_SET_IPV4_DST;
6949 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6950 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6951 if (flow_dv_convert_action_modify_ipv6
6952 (&mhdr_res, actions, error))
6954 action_flags |= actions->type ==
6955 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6956 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6957 MLX5_FLOW_ACTION_SET_IPV6_DST;
6959 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6960 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6961 if (flow_dv_convert_action_modify_tp
6962 (&mhdr_res, actions, items,
6965 action_flags |= actions->type ==
6966 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6967 MLX5_FLOW_ACTION_SET_TP_SRC :
6968 MLX5_FLOW_ACTION_SET_TP_DST;
6970 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6971 if (flow_dv_convert_action_modify_dec_ttl
6972 (&mhdr_res, items, &flow_attr, error))
6974 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6976 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6977 if (flow_dv_convert_action_modify_ttl
6978 (&mhdr_res, actions, items,
6981 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6983 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6984 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6985 if (flow_dv_convert_action_modify_tcp_seq
6986 (&mhdr_res, actions, error))
6988 action_flags |= actions->type ==
6989 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6990 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6991 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6994 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6995 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6996 if (flow_dv_convert_action_modify_tcp_ack
6997 (&mhdr_res, actions, error))
6999 action_flags |= actions->type ==
7000 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7001 MLX5_FLOW_ACTION_INC_TCP_ACK :
7002 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7004 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7005 if (flow_dv_convert_action_set_reg
7006 (&mhdr_res, actions, error))
7008 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7010 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7011 if (flow_dv_convert_action_copy_mreg
7012 (dev, &mhdr_res, actions, error))
7014 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7016 case RTE_FLOW_ACTION_TYPE_METER:
7017 mtr = actions->conf;
7019 flow->meter = mlx5_flow_meter_attach(priv,
7023 return rte_flow_error_set(error,
7025 RTE_FLOW_ERROR_TYPE_ACTION,
7028 "or invalid parameters");
7030 /* Set the meter action. */
7031 dev_flow->dv.actions[actions_n++] =
7032 flow->meter->mfts->meter_action;
7033 action_flags |= MLX5_FLOW_ACTION_METER;
7035 case RTE_FLOW_ACTION_TYPE_END:
7037 if (mhdr_res.actions_num) {
7038 /* create modify action if needed. */
7039 if (flow_dv_modify_hdr_resource_register
7040 (dev, &mhdr_res, dev_flow, error))
7042 dev_flow->dv.actions[modify_action_position] =
7043 dev_flow->dv.modify_hdr->verbs_action;
7049 if (mhdr_res.actions_num &&
7050 modify_action_position == UINT32_MAX)
7051 modify_action_position = actions_n++;
7053 dev_flow->dv.actions_n = actions_n;
7054 dev_flow->actions = action_flags;
7055 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7056 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7057 int item_type = items->type;
7059 switch (item_type) {
7060 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7061 flow_dv_translate_item_port_id(dev, match_mask,
7062 match_value, items);
7063 last_item = MLX5_FLOW_ITEM_PORT_ID;
7065 case RTE_FLOW_ITEM_TYPE_ETH:
7066 flow_dv_translate_item_eth(match_mask, match_value,
7068 matcher.priority = MLX5_PRIORITY_MAP_L2;
7069 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7070 MLX5_FLOW_LAYER_OUTER_L2;
7072 case RTE_FLOW_ITEM_TYPE_VLAN:
7073 flow_dv_translate_item_vlan(dev_flow,
7074 match_mask, match_value,
7076 matcher.priority = MLX5_PRIORITY_MAP_L2;
7077 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7078 MLX5_FLOW_LAYER_INNER_VLAN) :
7079 (MLX5_FLOW_LAYER_OUTER_L2 |
7080 MLX5_FLOW_LAYER_OUTER_VLAN);
7082 case RTE_FLOW_ITEM_TYPE_IPV4:
7083 mlx5_flow_tunnel_ip_check(items, next_protocol,
7084 &item_flags, &tunnel);
7085 flow_dv_translate_item_ipv4(match_mask, match_value,
7088 matcher.priority = MLX5_PRIORITY_MAP_L3;
7089 dev_flow->hash_fields |=
7090 mlx5_flow_hashfields_adjust
7092 MLX5_IPV4_LAYER_TYPES,
7093 MLX5_IPV4_IBV_RX_HASH);
7094 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7095 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7096 if (items->mask != NULL &&
7097 ((const struct rte_flow_item_ipv4 *)
7098 items->mask)->hdr.next_proto_id) {
7100 ((const struct rte_flow_item_ipv4 *)
7101 (items->spec))->hdr.next_proto_id;
7103 ((const struct rte_flow_item_ipv4 *)
7104 (items->mask))->hdr.next_proto_id;
7106 /* Reset for inner layer. */
7107 next_protocol = 0xff;
7110 case RTE_FLOW_ITEM_TYPE_IPV6:
7111 mlx5_flow_tunnel_ip_check(items, next_protocol,
7112 &item_flags, &tunnel);
7113 flow_dv_translate_item_ipv6(match_mask, match_value,
7116 matcher.priority = MLX5_PRIORITY_MAP_L3;
7117 dev_flow->hash_fields |=
7118 mlx5_flow_hashfields_adjust
7120 MLX5_IPV6_LAYER_TYPES,
7121 MLX5_IPV6_IBV_RX_HASH);
7122 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7123 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7124 if (items->mask != NULL &&
7125 ((const struct rte_flow_item_ipv6 *)
7126 items->mask)->hdr.proto) {
7128 ((const struct rte_flow_item_ipv6 *)
7129 items->spec)->hdr.proto;
7131 ((const struct rte_flow_item_ipv6 *)
7132 items->mask)->hdr.proto;
7134 /* Reset for inner layer. */
7135 next_protocol = 0xff;
7138 case RTE_FLOW_ITEM_TYPE_TCP:
7139 flow_dv_translate_item_tcp(match_mask, match_value,
7141 matcher.priority = MLX5_PRIORITY_MAP_L4;
7142 dev_flow->hash_fields |=
7143 mlx5_flow_hashfields_adjust
7144 (dev_flow, tunnel, ETH_RSS_TCP,
7145 IBV_RX_HASH_SRC_PORT_TCP |
7146 IBV_RX_HASH_DST_PORT_TCP);
7147 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7148 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7150 case RTE_FLOW_ITEM_TYPE_UDP:
7151 flow_dv_translate_item_udp(match_mask, match_value,
7153 matcher.priority = MLX5_PRIORITY_MAP_L4;
7154 dev_flow->hash_fields |=
7155 mlx5_flow_hashfields_adjust
7156 (dev_flow, tunnel, ETH_RSS_UDP,
7157 IBV_RX_HASH_SRC_PORT_UDP |
7158 IBV_RX_HASH_DST_PORT_UDP);
7159 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7160 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7162 case RTE_FLOW_ITEM_TYPE_GRE:
7163 flow_dv_translate_item_gre(match_mask, match_value,
7165 last_item = MLX5_FLOW_LAYER_GRE;
7167 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7168 flow_dv_translate_item_gre_key(match_mask,
7169 match_value, items);
7170 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7172 case RTE_FLOW_ITEM_TYPE_NVGRE:
7173 flow_dv_translate_item_nvgre(match_mask, match_value,
7175 last_item = MLX5_FLOW_LAYER_GRE;
7177 case RTE_FLOW_ITEM_TYPE_VXLAN:
7178 flow_dv_translate_item_vxlan(match_mask, match_value,
7180 last_item = MLX5_FLOW_LAYER_VXLAN;
7182 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7183 flow_dv_translate_item_vxlan(match_mask, match_value,
7185 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7187 case RTE_FLOW_ITEM_TYPE_GENEVE:
7188 flow_dv_translate_item_geneve(match_mask, match_value,
7190 last_item = MLX5_FLOW_LAYER_GENEVE;
7192 case RTE_FLOW_ITEM_TYPE_MPLS:
7193 flow_dv_translate_item_mpls(match_mask, match_value,
7194 items, last_item, tunnel);
7195 last_item = MLX5_FLOW_LAYER_MPLS;
7197 case RTE_FLOW_ITEM_TYPE_MARK:
7198 flow_dv_translate_item_mark(dev, match_mask,
7199 match_value, items);
7200 last_item = MLX5_FLOW_ITEM_MARK;
7202 case RTE_FLOW_ITEM_TYPE_META:
7203 flow_dv_translate_item_meta(dev, match_mask,
7204 match_value, attr, items);
7205 last_item = MLX5_FLOW_ITEM_METADATA;
7207 case RTE_FLOW_ITEM_TYPE_ICMP:
7208 flow_dv_translate_item_icmp(match_mask, match_value,
7210 last_item = MLX5_FLOW_LAYER_ICMP;
7212 case RTE_FLOW_ITEM_TYPE_ICMP6:
7213 flow_dv_translate_item_icmp6(match_mask, match_value,
7215 last_item = MLX5_FLOW_LAYER_ICMP6;
7217 case RTE_FLOW_ITEM_TYPE_TAG:
7218 flow_dv_translate_item_tag(dev, match_mask,
7219 match_value, items);
7220 last_item = MLX5_FLOW_ITEM_TAG;
7222 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7223 flow_dv_translate_mlx5_item_tag(match_mask,
7224 match_value, items);
7225 last_item = MLX5_FLOW_ITEM_TAG;
7227 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7228 flow_dv_translate_item_tx_queue(dev, match_mask,
7231 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7236 item_flags |= last_item;
7239 * In case of ingress traffic when E-Switch mode is enabled,
7240 * we have two cases where we need to set the source port manually.
7241 * The first one, is in case of Nic steering rule, and the second is
7242 * E-Switch rule where no port_id item was found. In both cases
7243 * the source port is set according the current port in use.
7245 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
7246 (priv->representor || priv->master)) {
7247 if (flow_dv_translate_item_port_id(dev, match_mask,
7251 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
7252 dev_flow->dv.value.buf));
7253 dev_flow->layers = item_flags;
7254 /* Register matcher. */
7255 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7257 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7259 /* reserved field no needs to be set to 0 here. */
7260 tbl_key.domain = attr->transfer;
7261 tbl_key.direction = attr->egress;
7262 tbl_key.table_id = dev_flow->group;
7263 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7269 * Apply the flow to the NIC, lock free,
7270 * (mutex should be acquired by caller).
7273 * Pointer to the Ethernet device structure.
7274 * @param[in, out] flow
7275 * Pointer to flow structure.
7277 * Pointer to error structure.
7280 * 0 on success, a negative errno value otherwise and rte_errno is set.
7283 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7284 struct rte_flow_error *error)
7286 struct mlx5_flow_dv *dv;
7287 struct mlx5_flow *dev_flow;
7288 struct mlx5_priv *priv = dev->data->dev_private;
7292 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7295 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7296 if (dev_flow->transfer) {
7297 dv->actions[n++] = priv->sh->esw_drop_action;
7299 dv->hrxq = mlx5_hrxq_drop_new(dev);
7303 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7305 "cannot get drop hash queue");
7308 dv->actions[n++] = dv->hrxq->action;
7310 } else if (dev_flow->actions &
7311 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7312 struct mlx5_hrxq *hrxq;
7314 assert(flow->rss.queue);
7315 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7316 MLX5_RSS_HASH_KEY_LEN,
7317 dev_flow->hash_fields,
7319 flow->rss.queue_num);
7321 hrxq = mlx5_hrxq_new
7322 (dev, flow->rss.key,
7323 MLX5_RSS_HASH_KEY_LEN,
7324 dev_flow->hash_fields,
7326 flow->rss.queue_num,
7327 !!(dev_flow->layers &
7328 MLX5_FLOW_LAYER_TUNNEL));
7333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7334 "cannot get hash queue");
7338 dv->actions[n++] = dv->hrxq->action;
7341 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7342 (void *)&dv->value, n,
7345 rte_flow_error_set(error, errno,
7346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7348 "hardware refuses to create flow");
7351 if (priv->vmwa_context &&
7352 dev_flow->dv.vf_vlan.tag &&
7353 !dev_flow->dv.vf_vlan.created) {
7355 * The rule contains the VLAN pattern.
7356 * For VF we are going to create VLAN
7357 * interface to make hypervisor set correct
7358 * e-Switch vport context.
7360 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7365 err = rte_errno; /* Save rte_errno before cleanup. */
7366 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7367 struct mlx5_flow_dv *dv = &dev_flow->dv;
7369 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7370 mlx5_hrxq_drop_release(dev);
7372 mlx5_hrxq_release(dev, dv->hrxq);
7375 if (dev_flow->dv.vf_vlan.tag &&
7376 dev_flow->dv.vf_vlan.created)
7377 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7379 rte_errno = err; /* Restore rte_errno. */
7384 * Release the flow matcher.
7387 * Pointer to Ethernet device.
7389 * Pointer to mlx5_flow.
7392 * 1 while a reference on it exists, 0 when freed.
7395 flow_dv_matcher_release(struct rte_eth_dev *dev,
7396 struct mlx5_flow *flow)
7398 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7400 assert(matcher->matcher_object);
7401 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7402 dev->data->port_id, (void *)matcher,
7403 rte_atomic32_read(&matcher->refcnt));
7404 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7405 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7406 (matcher->matcher_object));
7407 LIST_REMOVE(matcher, next);
7408 /* table ref-- in release interface. */
7409 flow_dv_tbl_resource_release(dev, matcher->tbl);
7411 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7412 dev->data->port_id, (void *)matcher);
7419 * Release an encap/decap resource.
7422 * Pointer to mlx5_flow.
7425 * 1 while a reference on it exists, 0 when freed.
7428 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7430 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7431 flow->dv.encap_decap;
7433 assert(cache_resource->verbs_action);
7434 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7435 (void *)cache_resource,
7436 rte_atomic32_read(&cache_resource->refcnt));
7437 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7438 claim_zero(mlx5_glue->destroy_flow_action
7439 (cache_resource->verbs_action));
7440 LIST_REMOVE(cache_resource, next);
7441 rte_free(cache_resource);
7442 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7443 (void *)cache_resource);
7450 * Release an jump to table action resource.
7453 * Pointer to Ethernet device.
7455 * Pointer to mlx5_flow.
7458 * 1 while a reference on it exists, 0 when freed.
7461 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7462 struct mlx5_flow *flow)
7464 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7465 struct mlx5_flow_tbl_data_entry *tbl_data =
7466 container_of(cache_resource,
7467 struct mlx5_flow_tbl_data_entry, jump);
7469 assert(cache_resource->action);
7470 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7471 (void *)cache_resource,
7472 rte_atomic32_read(&cache_resource->refcnt));
7473 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7474 claim_zero(mlx5_glue->destroy_flow_action
7475 (cache_resource->action));
7476 /* jump action memory free is inside the table release. */
7477 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7478 DRV_LOG(DEBUG, "jump table resource %p: removed",
7479 (void *)cache_resource);
7486 * Release a modify-header resource.
7489 * Pointer to mlx5_flow.
7492 * 1 while a reference on it exists, 0 when freed.
7495 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7497 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7498 flow->dv.modify_hdr;
7500 assert(cache_resource->verbs_action);
7501 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7502 (void *)cache_resource,
7503 rte_atomic32_read(&cache_resource->refcnt));
7504 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7505 claim_zero(mlx5_glue->destroy_flow_action
7506 (cache_resource->verbs_action));
7507 LIST_REMOVE(cache_resource, next);
7508 rte_free(cache_resource);
7509 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7510 (void *)cache_resource);
7517 * Release port ID action resource.
7520 * Pointer to mlx5_flow.
7523 * 1 while a reference on it exists, 0 when freed.
7526 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7528 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7529 flow->dv.port_id_action;
7531 assert(cache_resource->action);
7532 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7533 (void *)cache_resource,
7534 rte_atomic32_read(&cache_resource->refcnt));
7535 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7536 claim_zero(mlx5_glue->destroy_flow_action
7537 (cache_resource->action));
7538 LIST_REMOVE(cache_resource, next);
7539 rte_free(cache_resource);
7540 DRV_LOG(DEBUG, "port id action resource %p: removed",
7541 (void *)cache_resource);
7548 * Release push vlan action resource.
7551 * Pointer to mlx5_flow.
7554 * 1 while a reference on it exists, 0 when freed.
7557 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
7559 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
7560 flow->dv.push_vlan_res;
7562 assert(cache_resource->action);
7563 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
7564 (void *)cache_resource,
7565 rte_atomic32_read(&cache_resource->refcnt));
7566 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7567 claim_zero(mlx5_glue->destroy_flow_action
7568 (cache_resource->action));
7569 LIST_REMOVE(cache_resource, next);
7570 rte_free(cache_resource);
7571 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
7572 (void *)cache_resource);
7579 * Remove the flow from the NIC but keeps it in memory.
7580 * Lock free, (mutex should be acquired by caller).
7583 * Pointer to Ethernet device.
7584 * @param[in, out] flow
7585 * Pointer to flow structure.
7588 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7590 struct mlx5_flow_dv *dv;
7591 struct mlx5_flow *dev_flow;
7595 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7598 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
7602 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7603 mlx5_hrxq_drop_release(dev);
7605 mlx5_hrxq_release(dev, dv->hrxq);
7608 if (dev_flow->dv.vf_vlan.tag &&
7609 dev_flow->dv.vf_vlan.created)
7610 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7615 * Remove the flow from the NIC and the memory.
7616 * Lock free, (mutex should be acquired by caller).
7619 * Pointer to the Ethernet device structure.
7620 * @param[in, out] flow
7621 * Pointer to flow structure.
7624 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
7626 struct mlx5_flow *dev_flow;
7630 __flow_dv_remove(dev, flow);
7631 if (flow->counter) {
7632 flow_dv_counter_release(dev, flow->counter);
7633 flow->counter = NULL;
7636 mlx5_flow_meter_detach(flow->meter);
7639 while (!LIST_EMPTY(&flow->dev_flows)) {
7640 dev_flow = LIST_FIRST(&flow->dev_flows);
7641 LIST_REMOVE(dev_flow, next);
7642 if (dev_flow->dv.matcher)
7643 flow_dv_matcher_release(dev, dev_flow);
7644 if (dev_flow->dv.encap_decap)
7645 flow_dv_encap_decap_resource_release(dev_flow);
7646 if (dev_flow->dv.modify_hdr)
7647 flow_dv_modify_hdr_resource_release(dev_flow);
7648 if (dev_flow->dv.jump)
7649 flow_dv_jump_tbl_resource_release(dev, dev_flow);
7650 if (dev_flow->dv.port_id_action)
7651 flow_dv_port_id_action_resource_release(dev_flow);
7652 if (dev_flow->dv.push_vlan_res)
7653 flow_dv_push_vlan_action_resource_release(dev_flow);
7654 if (dev_flow->dv.tag_resource)
7655 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
7661 * Query a dv flow rule for its statistics via devx.
7664 * Pointer to Ethernet device.
7666 * Pointer to the sub flow.
7668 * data retrieved by the query.
7670 * Perform verbose error reporting if not NULL.
7673 * 0 on success, a negative errno value otherwise and rte_errno is set.
7676 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
7677 void *data, struct rte_flow_error *error)
7679 struct mlx5_priv *priv = dev->data->dev_private;
7680 struct rte_flow_query_count *qc = data;
7682 if (!priv->config.devx)
7683 return rte_flow_error_set(error, ENOTSUP,
7684 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7686 "counters are not supported");
7687 if (flow->counter) {
7688 uint64_t pkts, bytes;
7689 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
7693 return rte_flow_error_set(error, -err,
7694 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7695 NULL, "cannot read counters");
7698 qc->hits = pkts - flow->counter->hits;
7699 qc->bytes = bytes - flow->counter->bytes;
7701 flow->counter->hits = pkts;
7702 flow->counter->bytes = bytes;
7706 return rte_flow_error_set(error, EINVAL,
7707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7709 "counters are not available");
7715 * @see rte_flow_query()
7719 flow_dv_query(struct rte_eth_dev *dev,
7720 struct rte_flow *flow __rte_unused,
7721 const struct rte_flow_action *actions __rte_unused,
7722 void *data __rte_unused,
7723 struct rte_flow_error *error __rte_unused)
7727 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7728 switch (actions->type) {
7729 case RTE_FLOW_ACTION_TYPE_VOID:
7731 case RTE_FLOW_ACTION_TYPE_COUNT:
7732 ret = flow_dv_query_count(dev, flow, data, error);
7735 return rte_flow_error_set(error, ENOTSUP,
7736 RTE_FLOW_ERROR_TYPE_ACTION,
7738 "action not supported");
7745 * Destroy the meter table set.
7746 * Lock free, (mutex should be acquired by caller).
7749 * Pointer to Ethernet device.
7751 * Pointer to the meter table set.
7757 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
7758 struct mlx5_meter_domains_infos *tbl)
7760 struct mlx5_priv *priv = dev->data->dev_private;
7761 struct mlx5_meter_domains_infos *mtd =
7762 (struct mlx5_meter_domains_infos *)tbl;
7764 if (!mtd || !priv->config.dv_flow_en)
7766 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
7767 claim_zero(mlx5_glue->dv_destroy_flow
7768 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
7769 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
7770 claim_zero(mlx5_glue->dv_destroy_flow
7771 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
7772 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
7773 claim_zero(mlx5_glue->dv_destroy_flow
7774 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
7775 if (mtd->egress.color_matcher)
7776 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7777 (mtd->egress.color_matcher));
7778 if (mtd->egress.any_matcher)
7779 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7780 (mtd->egress.any_matcher));
7781 if (mtd->egress.tbl)
7782 claim_zero(flow_dv_tbl_resource_release(dev,
7784 if (mtd->ingress.color_matcher)
7785 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7786 (mtd->ingress.color_matcher));
7787 if (mtd->ingress.any_matcher)
7788 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7789 (mtd->ingress.any_matcher));
7790 if (mtd->ingress.tbl)
7791 claim_zero(flow_dv_tbl_resource_release(dev,
7793 if (mtd->transfer.color_matcher)
7794 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7795 (mtd->transfer.color_matcher));
7796 if (mtd->transfer.any_matcher)
7797 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7798 (mtd->transfer.any_matcher));
7799 if (mtd->transfer.tbl)
7800 claim_zero(flow_dv_tbl_resource_release(dev,
7801 mtd->transfer.tbl));
7803 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
7808 /* Number of meter flow actions, count and jump or count and drop. */
7809 #define METER_ACTIONS 2
7812 * Create specify domain meter table and suffix table.
7815 * Pointer to Ethernet device.
7816 * @param[in,out] mtb
7817 * Pointer to DV meter table set.
7820 * @param[in] transfer
7822 * @param[in] color_reg_c_idx
7823 * Reg C index for color match.
7826 * 0 on success, -1 otherwise and rte_errno is set.
7829 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
7830 struct mlx5_meter_domains_infos *mtb,
7831 uint8_t egress, uint8_t transfer,
7832 uint32_t color_reg_c_idx)
7834 struct mlx5_priv *priv = dev->data->dev_private;
7835 struct mlx5_ibv_shared *sh = priv->sh;
7836 struct mlx5_flow_dv_match_params mask = {
7837 .size = sizeof(mask.buf),
7839 struct mlx5_flow_dv_match_params value = {
7840 .size = sizeof(value.buf),
7842 struct mlx5dv_flow_matcher_attr dv_attr = {
7843 .type = IBV_FLOW_ATTR_NORMAL,
7845 .match_criteria_enable = 0,
7846 .match_mask = (void *)&mask,
7848 void *actions[METER_ACTIONS];
7849 struct mlx5_flow_tbl_resource **sfx_tbl;
7850 struct mlx5_meter_domain_info *dtb;
7851 struct rte_flow_error error;
7855 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
7856 dtb = &mtb->transfer;
7857 } else if (egress) {
7858 sfx_tbl = &sh->tx_mtr_sfx_tbl;
7861 sfx_tbl = &sh->rx_mtr_sfx_tbl;
7862 dtb = &mtb->ingress;
7864 /* If the suffix table in missing, create it. */
7866 *sfx_tbl = flow_dv_tbl_resource_get(dev,
7867 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
7868 egress, transfer, &error);
7870 DRV_LOG(ERR, "Failed to create meter suffix table.");
7874 /* Create the meter table with METER level. */
7875 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
7876 egress, transfer, &error);
7878 DRV_LOG(ERR, "Failed to create meter policer table.");
7881 /* Create matchers, Any and Color. */
7882 dv_attr.priority = 3;
7883 dv_attr.match_criteria_enable = 0;
7884 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
7887 if (!dtb->any_matcher) {
7888 DRV_LOG(ERR, "Failed to create meter"
7889 " policer default matcher.");
7892 dv_attr.priority = 0;
7893 dv_attr.match_criteria_enable =
7894 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7895 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
7896 rte_col_2_mlx5_col(RTE_COLORS), UINT32_MAX);
7897 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
7900 if (!dtb->color_matcher) {
7901 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
7904 if (mtb->count_actns[RTE_MTR_DROPPED])
7905 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
7906 actions[i++] = mtb->drop_actn;
7907 /* Default rule: lowest priority, match any, actions: drop. */
7908 dtb->policer_rules[RTE_MTR_DROPPED] =
7909 mlx5_glue->dv_create_flow(dtb->any_matcher,
7910 (void *)&value, i, actions);
7911 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
7912 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
7921 * Create the needed meter and suffix tables.
7922 * Lock free, (mutex should be acquired by caller).
7925 * Pointer to Ethernet device.
7927 * Pointer to the flow meter.
7930 * Pointer to table set on success, NULL otherwise and rte_errno is set.
7932 static struct mlx5_meter_domains_infos *
7933 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
7934 const struct mlx5_flow_meter *fm)
7936 struct mlx5_priv *priv = dev->data->dev_private;
7937 struct mlx5_meter_domains_infos *mtb;
7941 if (!priv->mtr_en) {
7942 rte_errno = ENOTSUP;
7945 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
7947 DRV_LOG(ERR, "Failed to allocate memory for meter.");
7950 /* Create meter count actions */
7951 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
7952 if (!fm->policer_stats.cnt[i])
7954 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
7956 /* Create drop action. */
7957 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
7958 if (!mtb->drop_actn) {
7959 DRV_LOG(ERR, "Failed to create drop action.");
7962 /* Egress meter table. */
7963 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
7965 DRV_LOG(ERR, "Failed to prepare egress meter table.");
7968 /* Ingress meter table. */
7969 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
7971 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
7974 /* FDB meter table. */
7975 if (priv->config.dv_esw_en) {
7976 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
7977 priv->mtr_color_reg);
7979 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
7985 flow_dv_destroy_mtr_tbl(dev, mtb);
7990 * Destroy domain policer rule.
7993 * Pointer to domain table.
7996 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8000 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8001 if (dt->policer_rules[i]) {
8002 claim_zero(mlx5_glue->dv_destroy_flow
8003 (dt->policer_rules[i]));
8004 dt->policer_rules[i] = NULL;
8007 if (dt->jump_actn) {
8008 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8009 dt->jump_actn = NULL;
8014 * Destroy policer rules.
8017 * Pointer to Ethernet device.
8019 * Pointer to flow meter structure.
8021 * Pointer to flow attributes.
8027 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8028 const struct mlx5_flow_meter *fm,
8029 const struct rte_flow_attr *attr)
8031 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8036 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8038 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8040 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8045 * Create specify domain meter policer rule.
8048 * Pointer to flow meter structure.
8050 * Pointer to DV meter table set.
8052 * Pointer to suffix table.
8053 * @param[in] mtr_reg_c
8054 * Color match REG_C.
8057 * 0 on success, -1 otherwise.
8060 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8061 struct mlx5_meter_domain_info *dtb,
8062 struct mlx5_flow_tbl_resource *sfx_tb,
8065 struct mlx5_flow_dv_match_params matcher = {
8066 .size = sizeof(matcher.buf),
8068 struct mlx5_flow_dv_match_params value = {
8069 .size = sizeof(value.buf),
8071 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8072 void *actions[METER_ACTIONS];
8075 /* Create jump action. */
8078 if (!dtb->jump_actn)
8080 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8082 if (!dtb->jump_actn) {
8083 DRV_LOG(ERR, "Failed to create policer jump action.");
8086 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8089 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8090 rte_col_2_mlx5_col(i), UINT32_MAX);
8091 if (mtb->count_actns[i])
8092 actions[j++] = mtb->count_actns[i];
8093 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8094 actions[j++] = mtb->drop_actn;
8096 actions[j++] = dtb->jump_actn;
8097 dtb->policer_rules[i] =
8098 mlx5_glue->dv_create_flow(dtb->color_matcher,
8101 if (!dtb->policer_rules[i]) {
8102 DRV_LOG(ERR, "Failed to create policer rule.");
8113 * Create policer rules.
8116 * Pointer to Ethernet device.
8118 * Pointer to flow meter structure.
8120 * Pointer to flow attributes.
8123 * 0 on success, -1 otherwise.
8126 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8127 struct mlx5_flow_meter *fm,
8128 const struct rte_flow_attr *attr)
8130 struct mlx5_priv *priv = dev->data->dev_private;
8131 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8135 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8136 priv->sh->tx_mtr_sfx_tbl,
8137 priv->mtr_color_reg);
8139 DRV_LOG(ERR, "Failed to create egress policer.");
8143 if (attr->ingress) {
8144 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8145 priv->sh->rx_mtr_sfx_tbl,
8146 priv->mtr_color_reg);
8148 DRV_LOG(ERR, "Failed to create ingress policer.");
8152 if (attr->transfer) {
8153 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8154 priv->sh->fdb_mtr_sfx_tbl,
8155 priv->mtr_color_reg);
8157 DRV_LOG(ERR, "Failed to create transfer policer.");
8163 flow_dv_destroy_policer_rules(dev, fm, attr);
8168 * Query a devx counter.
8171 * Pointer to the Ethernet device structure.
8173 * Pointer to the flow counter.
8175 * Set to clear the counter statistics.
8177 * The statistics value of packets.
8179 * The statistics value of bytes.
8182 * 0 on success, otherwise return -1.
8185 flow_dv_counter_query(struct rte_eth_dev *dev,
8186 struct mlx5_flow_counter *cnt, bool clear,
8187 uint64_t *pkts, uint64_t *bytes)
8189 struct mlx5_priv *priv = dev->data->dev_private;
8190 uint64_t inn_pkts, inn_bytes;
8193 if (!priv->config.devx)
8195 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8198 *pkts = inn_pkts - cnt->hits;
8199 *bytes = inn_bytes - cnt->bytes;
8201 cnt->hits = inn_pkts;
8202 cnt->bytes = inn_bytes;
8208 * Mutex-protected thunk to lock-free __flow_dv_translate().
8211 flow_dv_translate(struct rte_eth_dev *dev,
8212 struct mlx5_flow *dev_flow,
8213 const struct rte_flow_attr *attr,
8214 const struct rte_flow_item items[],
8215 const struct rte_flow_action actions[],
8216 struct rte_flow_error *error)
8220 flow_dv_shared_lock(dev);
8221 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8222 flow_dv_shared_unlock(dev);
8227 * Mutex-protected thunk to lock-free __flow_dv_apply().
8230 flow_dv_apply(struct rte_eth_dev *dev,
8231 struct rte_flow *flow,
8232 struct rte_flow_error *error)
8236 flow_dv_shared_lock(dev);
8237 ret = __flow_dv_apply(dev, flow, error);
8238 flow_dv_shared_unlock(dev);
8243 * Mutex-protected thunk to lock-free __flow_dv_remove().
8246 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8248 flow_dv_shared_lock(dev);
8249 __flow_dv_remove(dev, flow);
8250 flow_dv_shared_unlock(dev);
8254 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8257 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8259 flow_dv_shared_lock(dev);
8260 __flow_dv_destroy(dev, flow);
8261 flow_dv_shared_unlock(dev);
8265 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8267 static struct mlx5_flow_counter *
8268 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8270 struct mlx5_flow_counter *cnt;
8272 flow_dv_shared_lock(dev);
8273 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8274 flow_dv_shared_unlock(dev);
8279 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8282 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8284 flow_dv_shared_lock(dev);
8285 flow_dv_counter_release(dev, cnt);
8286 flow_dv_shared_unlock(dev);
8289 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8290 .validate = flow_dv_validate,
8291 .prepare = flow_dv_prepare,
8292 .translate = flow_dv_translate,
8293 .apply = flow_dv_apply,
8294 .remove = flow_dv_remove,
8295 .destroy = flow_dv_destroy,
8296 .query = flow_dv_query,
8297 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8298 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8299 .create_policer_rules = flow_dv_create_policer_rules,
8300 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8301 .counter_alloc = flow_dv_counter_allocate,
8302 .counter_free = flow_dv_counter_free,
8303 .counter_query = flow_dv_counter_query,
8306 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */