1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
24 #include <mlx5_glue.h>
25 #include <mlx5_devx_cmds.h>
27 #include <mlx5_malloc.h>
29 #include "mlx5_defs.h"
31 #include "mlx5_common_os.h"
32 #include "mlx5_flow.h"
33 #include "mlx5_flow_os.h"
34 #include "mlx5_rxtx.h"
36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
38 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
39 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
42 #ifndef HAVE_MLX5DV_DR_ESWITCH
43 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
44 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
48 #ifndef HAVE_MLX5DV_DR
49 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
52 /* VLAN header definitions */
53 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
54 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
55 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
56 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
57 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
72 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
73 struct mlx5_flow_tbl_resource *tbl);
76 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
79 * Initialize flow attributes structure according to flow items' types.
81 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
82 * mode. For tunnel mode, the items to be modified are the outermost ones.
85 * Pointer to item specification.
87 * Pointer to flow attributes structure.
89 * Pointer to the sub flow.
90 * @param[in] tunnel_decap
91 * Whether action is after tunnel decapsulation.
94 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
95 struct mlx5_flow *dev_flow, bool tunnel_decap)
97 uint64_t layers = dev_flow->handle->layers;
100 * If layers is already initialized, it means this dev_flow is the
101 * suffix flow, the layers flags is set by the prefix flow. Need to
102 * use the layer flags from prefix flow as the suffix flow may not
103 * have the user defined items as the flow is split.
106 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
108 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
110 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
112 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
117 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
118 uint8_t next_protocol = 0xff;
119 switch (item->type) {
120 case RTE_FLOW_ITEM_TYPE_GRE:
121 case RTE_FLOW_ITEM_TYPE_NVGRE:
122 case RTE_FLOW_ITEM_TYPE_VXLAN:
123 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
124 case RTE_FLOW_ITEM_TYPE_GENEVE:
125 case RTE_FLOW_ITEM_TYPE_MPLS:
129 case RTE_FLOW_ITEM_TYPE_IPV4:
132 if (item->mask != NULL &&
133 ((const struct rte_flow_item_ipv4 *)
134 item->mask)->hdr.next_proto_id)
136 ((const struct rte_flow_item_ipv4 *)
137 (item->spec))->hdr.next_proto_id &
138 ((const struct rte_flow_item_ipv4 *)
139 (item->mask))->hdr.next_proto_id;
140 if ((next_protocol == IPPROTO_IPIP ||
141 next_protocol == IPPROTO_IPV6) && tunnel_decap)
144 case RTE_FLOW_ITEM_TYPE_IPV6:
147 if (item->mask != NULL &&
148 ((const struct rte_flow_item_ipv6 *)
149 item->mask)->hdr.proto)
151 ((const struct rte_flow_item_ipv6 *)
152 (item->spec))->hdr.proto &
153 ((const struct rte_flow_item_ipv6 *)
154 (item->mask))->hdr.proto;
155 if ((next_protocol == IPPROTO_IPIP ||
156 next_protocol == IPPROTO_IPV6) && tunnel_decap)
159 case RTE_FLOW_ITEM_TYPE_UDP:
163 case RTE_FLOW_ITEM_TYPE_TCP:
175 * Convert rte_mtr_color to mlx5 color.
184 rte_col_2_mlx5_col(enum rte_color rcol)
187 case RTE_COLOR_GREEN:
188 return MLX5_FLOW_COLOR_GREEN;
189 case RTE_COLOR_YELLOW:
190 return MLX5_FLOW_COLOR_YELLOW;
192 return MLX5_FLOW_COLOR_RED;
196 return MLX5_FLOW_COLOR_UNDEFINED;
199 struct field_modify_info {
200 uint32_t size; /* Size of field in protocol header, in bytes. */
201 uint32_t offset; /* Offset of field in protocol header, in bytes. */
202 enum mlx5_modification_field id;
205 struct field_modify_info modify_eth[] = {
206 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
207 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
208 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
209 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
213 struct field_modify_info modify_vlan_out_first_vid[] = {
214 /* Size in bits !!! */
215 {12, 0, MLX5_MODI_OUT_FIRST_VID},
219 struct field_modify_info modify_ipv4[] = {
220 {1, 1, MLX5_MODI_OUT_IP_DSCP},
221 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
222 {4, 12, MLX5_MODI_OUT_SIPV4},
223 {4, 16, MLX5_MODI_OUT_DIPV4},
227 struct field_modify_info modify_ipv6[] = {
228 {1, 0, MLX5_MODI_OUT_IP_DSCP},
229 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
230 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
231 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
232 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
233 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
234 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
235 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
236 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
237 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
241 struct field_modify_info modify_udp[] = {
242 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
243 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
247 struct field_modify_info modify_tcp[] = {
248 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
249 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
250 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
251 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
256 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
257 uint8_t next_protocol, uint64_t *item_flags,
260 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
261 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
262 if (next_protocol == IPPROTO_IPIP) {
263 *item_flags |= MLX5_FLOW_LAYER_IPIP;
266 if (next_protocol == IPPROTO_IPV6) {
267 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
273 * Acquire the synchronizing object to protect multithreaded access
274 * to shared dv context. Lock occurs only if context is actually
275 * shared, i.e. we have multiport IB device and representors are
279 * Pointer to the rte_eth_dev structure.
282 flow_dv_shared_lock(struct rte_eth_dev *dev)
284 struct mlx5_priv *priv = dev->data->dev_private;
285 struct mlx5_dev_ctx_shared *sh = priv->sh;
287 if (sh->dv_refcnt > 1) {
290 ret = pthread_mutex_lock(&sh->dv_mutex);
297 flow_dv_shared_unlock(struct rte_eth_dev *dev)
299 struct mlx5_priv *priv = dev->data->dev_private;
300 struct mlx5_dev_ctx_shared *sh = priv->sh;
302 if (sh->dv_refcnt > 1) {
305 ret = pthread_mutex_unlock(&sh->dv_mutex);
311 /* Update VLAN's VID/PCP based on input rte_flow_action.
314 * Pointer to struct rte_flow_action.
316 * Pointer to struct rte_vlan_hdr.
319 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
320 struct rte_vlan_hdr *vlan)
323 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
325 ((const struct rte_flow_action_of_set_vlan_pcp *)
326 action->conf)->vlan_pcp;
327 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
328 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
329 vlan->vlan_tci |= vlan_tci;
330 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
331 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
332 vlan->vlan_tci |= rte_be_to_cpu_16
333 (((const struct rte_flow_action_of_set_vlan_vid *)
334 action->conf)->vlan_vid);
339 * Fetch 1, 2, 3 or 4 byte field from the byte array
340 * and return as unsigned integer in host-endian format.
343 * Pointer to data array.
345 * Size of field to extract.
348 * converted field in host endian format.
350 static inline uint32_t
351 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
360 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
363 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
364 ret = (ret << 8) | *(data + sizeof(uint16_t));
367 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
378 * Convert modify-header action to DV specification.
380 * Data length of each action is determined by provided field description
381 * and the item mask. Data bit offset and width of each action is determined
382 * by provided item mask.
385 * Pointer to item specification.
387 * Pointer to field modification information.
388 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
389 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
390 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
392 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
393 * Negative offset value sets the same offset as source offset.
394 * size field is ignored, value is taken from source field.
395 * @param[in,out] resource
396 * Pointer to the modify-header resource.
398 * Type of modification.
400 * Pointer to the error structure.
403 * 0 on success, a negative errno value otherwise and rte_errno is set.
406 flow_dv_convert_modify_action(struct rte_flow_item *item,
407 struct field_modify_info *field,
408 struct field_modify_info *dcopy,
409 struct mlx5_flow_dv_modify_hdr_resource *resource,
410 uint32_t type, struct rte_flow_error *error)
412 uint32_t i = resource->actions_num;
413 struct mlx5_modification_cmd *actions = resource->actions;
416 * The item and mask are provided in big-endian format.
417 * The fields should be presented as in big-endian format either.
418 * Mask must be always present, it defines the actual field width.
420 MLX5_ASSERT(item->mask);
421 MLX5_ASSERT(field->size);
428 if (i >= MLX5_MAX_MODIFY_NUM)
429 return rte_flow_error_set(error, EINVAL,
430 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
431 "too many items to modify");
432 /* Fetch variable byte size mask from the array. */
433 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
434 field->offset, field->size);
439 /* Deduce actual data width in bits from mask value. */
440 off_b = rte_bsf32(mask);
441 size_b = sizeof(uint32_t) * CHAR_BIT -
442 off_b - __builtin_clz(mask);
444 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
445 actions[i] = (struct mlx5_modification_cmd) {
451 /* Convert entire record to expected big-endian format. */
452 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
453 if (type == MLX5_MODIFICATION_TYPE_COPY) {
455 actions[i].dst_field = dcopy->id;
456 actions[i].dst_offset =
457 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
458 /* Convert entire record to big-endian format. */
459 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
461 MLX5_ASSERT(item->spec);
462 data = flow_dv_fetch_field((const uint8_t *)item->spec +
463 field->offset, field->size);
464 /* Shift out the trailing masked bits from data. */
465 data = (data & mask) >> off_b;
466 actions[i].data1 = rte_cpu_to_be_32(data);
470 } while (field->size);
471 if (resource->actions_num == i)
472 return rte_flow_error_set(error, EINVAL,
473 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
474 "invalid modification flow item");
475 resource->actions_num = i;
480 * Convert modify-header set IPv4 address action to DV specification.
482 * @param[in,out] resource
483 * Pointer to the modify-header resource.
485 * Pointer to action specification.
487 * Pointer to the error structure.
490 * 0 on success, a negative errno value otherwise and rte_errno is set.
493 flow_dv_convert_action_modify_ipv4
494 (struct mlx5_flow_dv_modify_hdr_resource *resource,
495 const struct rte_flow_action *action,
496 struct rte_flow_error *error)
498 const struct rte_flow_action_set_ipv4 *conf =
499 (const struct rte_flow_action_set_ipv4 *)(action->conf);
500 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
501 struct rte_flow_item_ipv4 ipv4;
502 struct rte_flow_item_ipv4 ipv4_mask;
504 memset(&ipv4, 0, sizeof(ipv4));
505 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
506 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
507 ipv4.hdr.src_addr = conf->ipv4_addr;
508 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
510 ipv4.hdr.dst_addr = conf->ipv4_addr;
511 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
514 item.mask = &ipv4_mask;
515 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
516 MLX5_MODIFICATION_TYPE_SET, error);
520 * Convert modify-header set IPv6 address action to DV specification.
522 * @param[in,out] resource
523 * Pointer to the modify-header resource.
525 * Pointer to action specification.
527 * Pointer to the error structure.
530 * 0 on success, a negative errno value otherwise and rte_errno is set.
533 flow_dv_convert_action_modify_ipv6
534 (struct mlx5_flow_dv_modify_hdr_resource *resource,
535 const struct rte_flow_action *action,
536 struct rte_flow_error *error)
538 const struct rte_flow_action_set_ipv6 *conf =
539 (const struct rte_flow_action_set_ipv6 *)(action->conf);
540 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
541 struct rte_flow_item_ipv6 ipv6;
542 struct rte_flow_item_ipv6 ipv6_mask;
544 memset(&ipv6, 0, sizeof(ipv6));
545 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
546 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
547 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
548 sizeof(ipv6.hdr.src_addr));
549 memcpy(&ipv6_mask.hdr.src_addr,
550 &rte_flow_item_ipv6_mask.hdr.src_addr,
551 sizeof(ipv6.hdr.src_addr));
553 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
554 sizeof(ipv6.hdr.dst_addr));
555 memcpy(&ipv6_mask.hdr.dst_addr,
556 &rte_flow_item_ipv6_mask.hdr.dst_addr,
557 sizeof(ipv6.hdr.dst_addr));
560 item.mask = &ipv6_mask;
561 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
562 MLX5_MODIFICATION_TYPE_SET, error);
566 * Convert modify-header set MAC address action to DV specification.
568 * @param[in,out] resource
569 * Pointer to the modify-header resource.
571 * Pointer to action specification.
573 * Pointer to the error structure.
576 * 0 on success, a negative errno value otherwise and rte_errno is set.
579 flow_dv_convert_action_modify_mac
580 (struct mlx5_flow_dv_modify_hdr_resource *resource,
581 const struct rte_flow_action *action,
582 struct rte_flow_error *error)
584 const struct rte_flow_action_set_mac *conf =
585 (const struct rte_flow_action_set_mac *)(action->conf);
586 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
587 struct rte_flow_item_eth eth;
588 struct rte_flow_item_eth eth_mask;
590 memset(ð, 0, sizeof(eth));
591 memset(ð_mask, 0, sizeof(eth_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
593 memcpy(ð.src.addr_bytes, &conf->mac_addr,
594 sizeof(eth.src.addr_bytes));
595 memcpy(ð_mask.src.addr_bytes,
596 &rte_flow_item_eth_mask.src.addr_bytes,
597 sizeof(eth_mask.src.addr_bytes));
599 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
600 sizeof(eth.dst.addr_bytes));
601 memcpy(ð_mask.dst.addr_bytes,
602 &rte_flow_item_eth_mask.dst.addr_bytes,
603 sizeof(eth_mask.dst.addr_bytes));
606 item.mask = ð_mask;
607 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
608 MLX5_MODIFICATION_TYPE_SET, error);
612 * Convert modify-header set VLAN VID action to DV specification.
614 * @param[in,out] resource
615 * Pointer to the modify-header resource.
617 * Pointer to action specification.
619 * Pointer to the error structure.
622 * 0 on success, a negative errno value otherwise and rte_errno is set.
625 flow_dv_convert_action_modify_vlan_vid
626 (struct mlx5_flow_dv_modify_hdr_resource *resource,
627 const struct rte_flow_action *action,
628 struct rte_flow_error *error)
630 const struct rte_flow_action_of_set_vlan_vid *conf =
631 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
632 int i = resource->actions_num;
633 struct mlx5_modification_cmd *actions = resource->actions;
634 struct field_modify_info *field = modify_vlan_out_first_vid;
636 if (i >= MLX5_MAX_MODIFY_NUM)
637 return rte_flow_error_set(error, EINVAL,
638 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
639 "too many items to modify");
640 actions[i] = (struct mlx5_modification_cmd) {
641 .action_type = MLX5_MODIFICATION_TYPE_SET,
643 .length = field->size,
644 .offset = field->offset,
646 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
647 actions[i].data1 = conf->vlan_vid;
648 actions[i].data1 = actions[i].data1 << 16;
649 resource->actions_num = ++i;
654 * Convert modify-header set TP action to DV specification.
656 * @param[in,out] resource
657 * Pointer to the modify-header resource.
659 * Pointer to action specification.
661 * Pointer to rte_flow_item objects list.
663 * Pointer to flow attributes structure.
664 * @param[in] dev_flow
665 * Pointer to the sub flow.
666 * @param[in] tunnel_decap
667 * Whether action is after tunnel decapsulation.
669 * Pointer to the error structure.
672 * 0 on success, a negative errno value otherwise and rte_errno is set.
675 flow_dv_convert_action_modify_tp
676 (struct mlx5_flow_dv_modify_hdr_resource *resource,
677 const struct rte_flow_action *action,
678 const struct rte_flow_item *items,
679 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
680 bool tunnel_decap, struct rte_flow_error *error)
682 const struct rte_flow_action_set_tp *conf =
683 (const struct rte_flow_action_set_tp *)(action->conf);
684 struct rte_flow_item item;
685 struct rte_flow_item_udp udp;
686 struct rte_flow_item_udp udp_mask;
687 struct rte_flow_item_tcp tcp;
688 struct rte_flow_item_tcp tcp_mask;
689 struct field_modify_info *field;
692 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
694 memset(&udp, 0, sizeof(udp));
695 memset(&udp_mask, 0, sizeof(udp_mask));
696 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
697 udp.hdr.src_port = conf->port;
698 udp_mask.hdr.src_port =
699 rte_flow_item_udp_mask.hdr.src_port;
701 udp.hdr.dst_port = conf->port;
702 udp_mask.hdr.dst_port =
703 rte_flow_item_udp_mask.hdr.dst_port;
705 item.type = RTE_FLOW_ITEM_TYPE_UDP;
707 item.mask = &udp_mask;
710 MLX5_ASSERT(attr->tcp);
711 memset(&tcp, 0, sizeof(tcp));
712 memset(&tcp_mask, 0, sizeof(tcp_mask));
713 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
714 tcp.hdr.src_port = conf->port;
715 tcp_mask.hdr.src_port =
716 rte_flow_item_tcp_mask.hdr.src_port;
718 tcp.hdr.dst_port = conf->port;
719 tcp_mask.hdr.dst_port =
720 rte_flow_item_tcp_mask.hdr.dst_port;
722 item.type = RTE_FLOW_ITEM_TYPE_TCP;
724 item.mask = &tcp_mask;
727 return flow_dv_convert_modify_action(&item, field, NULL, resource,
728 MLX5_MODIFICATION_TYPE_SET, error);
732 * Convert modify-header set TTL action to DV specification.
734 * @param[in,out] resource
735 * Pointer to the modify-header resource.
737 * Pointer to action specification.
739 * Pointer to rte_flow_item objects list.
741 * Pointer to flow attributes structure.
742 * @param[in] dev_flow
743 * Pointer to the sub flow.
744 * @param[in] tunnel_decap
745 * Whether action is after tunnel decapsulation.
747 * Pointer to the error structure.
750 * 0 on success, a negative errno value otherwise and rte_errno is set.
753 flow_dv_convert_action_modify_ttl
754 (struct mlx5_flow_dv_modify_hdr_resource *resource,
755 const struct rte_flow_action *action,
756 const struct rte_flow_item *items,
757 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
758 bool tunnel_decap, struct rte_flow_error *error)
760 const struct rte_flow_action_set_ttl *conf =
761 (const struct rte_flow_action_set_ttl *)(action->conf);
762 struct rte_flow_item item;
763 struct rte_flow_item_ipv4 ipv4;
764 struct rte_flow_item_ipv4 ipv4_mask;
765 struct rte_flow_item_ipv6 ipv6;
766 struct rte_flow_item_ipv6 ipv6_mask;
767 struct field_modify_info *field;
770 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
772 memset(&ipv4, 0, sizeof(ipv4));
773 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
774 ipv4.hdr.time_to_live = conf->ttl_value;
775 ipv4_mask.hdr.time_to_live = 0xFF;
776 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
778 item.mask = &ipv4_mask;
781 MLX5_ASSERT(attr->ipv6);
782 memset(&ipv6, 0, sizeof(ipv6));
783 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
784 ipv6.hdr.hop_limits = conf->ttl_value;
785 ipv6_mask.hdr.hop_limits = 0xFF;
786 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
788 item.mask = &ipv6_mask;
791 return flow_dv_convert_modify_action(&item, field, NULL, resource,
792 MLX5_MODIFICATION_TYPE_SET, error);
796 * Convert modify-header decrement TTL action to DV specification.
798 * @param[in,out] resource
799 * Pointer to the modify-header resource.
801 * Pointer to action specification.
803 * Pointer to rte_flow_item objects list.
805 * Pointer to flow attributes structure.
806 * @param[in] dev_flow
807 * Pointer to the sub flow.
808 * @param[in] tunnel_decap
809 * Whether action is after tunnel decapsulation.
811 * Pointer to the error structure.
814 * 0 on success, a negative errno value otherwise and rte_errno is set.
817 flow_dv_convert_action_modify_dec_ttl
818 (struct mlx5_flow_dv_modify_hdr_resource *resource,
819 const struct rte_flow_item *items,
820 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
821 bool tunnel_decap, struct rte_flow_error *error)
823 struct rte_flow_item item;
824 struct rte_flow_item_ipv4 ipv4;
825 struct rte_flow_item_ipv4 ipv4_mask;
826 struct rte_flow_item_ipv6 ipv6;
827 struct rte_flow_item_ipv6 ipv6_mask;
828 struct field_modify_info *field;
831 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
833 memset(&ipv4, 0, sizeof(ipv4));
834 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
835 ipv4.hdr.time_to_live = 0xFF;
836 ipv4_mask.hdr.time_to_live = 0xFF;
837 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
839 item.mask = &ipv4_mask;
842 MLX5_ASSERT(attr->ipv6);
843 memset(&ipv6, 0, sizeof(ipv6));
844 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
845 ipv6.hdr.hop_limits = 0xFF;
846 ipv6_mask.hdr.hop_limits = 0xFF;
847 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
849 item.mask = &ipv6_mask;
852 return flow_dv_convert_modify_action(&item, field, NULL, resource,
853 MLX5_MODIFICATION_TYPE_ADD, error);
857 * Convert modify-header increment/decrement TCP Sequence number
858 * to DV specification.
860 * @param[in,out] resource
861 * Pointer to the modify-header resource.
863 * Pointer to action specification.
865 * Pointer to the error structure.
868 * 0 on success, a negative errno value otherwise and rte_errno is set.
871 flow_dv_convert_action_modify_tcp_seq
872 (struct mlx5_flow_dv_modify_hdr_resource *resource,
873 const struct rte_flow_action *action,
874 struct rte_flow_error *error)
876 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
877 uint64_t value = rte_be_to_cpu_32(*conf);
878 struct rte_flow_item item;
879 struct rte_flow_item_tcp tcp;
880 struct rte_flow_item_tcp tcp_mask;
882 memset(&tcp, 0, sizeof(tcp));
883 memset(&tcp_mask, 0, sizeof(tcp_mask));
884 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
886 * The HW has no decrement operation, only increment operation.
887 * To simulate decrement X from Y using increment operation
888 * we need to add UINT32_MAX X times to Y.
889 * Each adding of UINT32_MAX decrements Y by 1.
892 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
893 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
894 item.type = RTE_FLOW_ITEM_TYPE_TCP;
896 item.mask = &tcp_mask;
897 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
898 MLX5_MODIFICATION_TYPE_ADD, error);
902 * Convert modify-header increment/decrement TCP Acknowledgment number
903 * to DV specification.
905 * @param[in,out] resource
906 * Pointer to the modify-header resource.
908 * Pointer to action specification.
910 * Pointer to the error structure.
913 * 0 on success, a negative errno value otherwise and rte_errno is set.
916 flow_dv_convert_action_modify_tcp_ack
917 (struct mlx5_flow_dv_modify_hdr_resource *resource,
918 const struct rte_flow_action *action,
919 struct rte_flow_error *error)
921 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
922 uint64_t value = rte_be_to_cpu_32(*conf);
923 struct rte_flow_item item;
924 struct rte_flow_item_tcp tcp;
925 struct rte_flow_item_tcp tcp_mask;
927 memset(&tcp, 0, sizeof(tcp));
928 memset(&tcp_mask, 0, sizeof(tcp_mask));
929 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
931 * The HW has no decrement operation, only increment operation.
932 * To simulate decrement X from Y using increment operation
933 * we need to add UINT32_MAX X times to Y.
934 * Each adding of UINT32_MAX decrements Y by 1.
937 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
938 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
939 item.type = RTE_FLOW_ITEM_TYPE_TCP;
941 item.mask = &tcp_mask;
942 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
943 MLX5_MODIFICATION_TYPE_ADD, error);
946 static enum mlx5_modification_field reg_to_field[] = {
947 [REG_NONE] = MLX5_MODI_OUT_NONE,
948 [REG_A] = MLX5_MODI_META_DATA_REG_A,
949 [REG_B] = MLX5_MODI_META_DATA_REG_B,
950 [REG_C_0] = MLX5_MODI_META_REG_C_0,
951 [REG_C_1] = MLX5_MODI_META_REG_C_1,
952 [REG_C_2] = MLX5_MODI_META_REG_C_2,
953 [REG_C_3] = MLX5_MODI_META_REG_C_3,
954 [REG_C_4] = MLX5_MODI_META_REG_C_4,
955 [REG_C_5] = MLX5_MODI_META_REG_C_5,
956 [REG_C_6] = MLX5_MODI_META_REG_C_6,
957 [REG_C_7] = MLX5_MODI_META_REG_C_7,
961 * Convert register set to DV specification.
963 * @param[in,out] resource
964 * Pointer to the modify-header resource.
966 * Pointer to action specification.
968 * Pointer to the error structure.
971 * 0 on success, a negative errno value otherwise and rte_errno is set.
974 flow_dv_convert_action_set_reg
975 (struct mlx5_flow_dv_modify_hdr_resource *resource,
976 const struct rte_flow_action *action,
977 struct rte_flow_error *error)
979 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
980 struct mlx5_modification_cmd *actions = resource->actions;
981 uint32_t i = resource->actions_num;
983 if (i >= MLX5_MAX_MODIFY_NUM)
984 return rte_flow_error_set(error, EINVAL,
985 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
986 "too many items to modify");
987 MLX5_ASSERT(conf->id != REG_NONE);
988 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
989 actions[i] = (struct mlx5_modification_cmd) {
990 .action_type = MLX5_MODIFICATION_TYPE_SET,
991 .field = reg_to_field[conf->id],
993 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
994 actions[i].data1 = rte_cpu_to_be_32(conf->data);
996 resource->actions_num = i;
1001 * Convert SET_TAG action to DV specification.
1004 * Pointer to the rte_eth_dev structure.
1005 * @param[in,out] resource
1006 * Pointer to the modify-header resource.
1008 * Pointer to action specification.
1010 * Pointer to the error structure.
1013 * 0 on success, a negative errno value otherwise and rte_errno is set.
1016 flow_dv_convert_action_set_tag
1017 (struct rte_eth_dev *dev,
1018 struct mlx5_flow_dv_modify_hdr_resource *resource,
1019 const struct rte_flow_action_set_tag *conf,
1020 struct rte_flow_error *error)
1022 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1023 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1024 struct rte_flow_item item = {
1028 struct field_modify_info reg_c_x[] = {
1031 enum mlx5_modification_field reg_type;
1034 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1037 MLX5_ASSERT(ret != REG_NONE);
1038 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1039 reg_type = reg_to_field[ret];
1040 MLX5_ASSERT(reg_type > 0);
1041 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1042 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1043 MLX5_MODIFICATION_TYPE_SET, error);
1047 * Convert internal COPY_REG action to DV specification.
1050 * Pointer to the rte_eth_dev structure.
1051 * @param[in,out] res
1052 * Pointer to the modify-header resource.
1054 * Pointer to action specification.
1056 * Pointer to the error structure.
1059 * 0 on success, a negative errno value otherwise and rte_errno is set.
1062 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1063 struct mlx5_flow_dv_modify_hdr_resource *res,
1064 const struct rte_flow_action *action,
1065 struct rte_flow_error *error)
1067 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1068 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1069 struct rte_flow_item item = {
1073 struct field_modify_info reg_src[] = {
1074 {4, 0, reg_to_field[conf->src]},
1077 struct field_modify_info reg_dst = {
1079 .id = reg_to_field[conf->dst],
1081 /* Adjust reg_c[0] usage according to reported mask. */
1082 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1083 struct mlx5_priv *priv = dev->data->dev_private;
1084 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1086 MLX5_ASSERT(reg_c0);
1087 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1088 if (conf->dst == REG_C_0) {
1089 /* Copy to reg_c[0], within mask only. */
1090 reg_dst.offset = rte_bsf32(reg_c0);
1092 * Mask is ignoring the enianness, because
1093 * there is no conversion in datapath.
1095 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1096 /* Copy from destination lower bits to reg_c[0]. */
1097 mask = reg_c0 >> reg_dst.offset;
1099 /* Copy from destination upper bits to reg_c[0]. */
1100 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1101 rte_fls_u32(reg_c0));
1104 mask = rte_cpu_to_be_32(reg_c0);
1105 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1106 /* Copy from reg_c[0] to destination lower bits. */
1109 /* Copy from reg_c[0] to destination upper bits. */
1110 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1111 (rte_fls_u32(reg_c0) -
1116 return flow_dv_convert_modify_action(&item,
1117 reg_src, ®_dst, res,
1118 MLX5_MODIFICATION_TYPE_COPY,
1123 * Convert MARK action to DV specification. This routine is used
1124 * in extensive metadata only and requires metadata register to be
1125 * handled. In legacy mode hardware tag resource is engaged.
1128 * Pointer to the rte_eth_dev structure.
1130 * Pointer to MARK action specification.
1131 * @param[in,out] resource
1132 * Pointer to the modify-header resource.
1134 * Pointer to the error structure.
1137 * 0 on success, a negative errno value otherwise and rte_errno is set.
1140 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1141 const struct rte_flow_action_mark *conf,
1142 struct mlx5_flow_dv_modify_hdr_resource *resource,
1143 struct rte_flow_error *error)
1145 struct mlx5_priv *priv = dev->data->dev_private;
1146 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1147 priv->sh->dv_mark_mask);
1148 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1149 struct rte_flow_item item = {
1153 struct field_modify_info reg_c_x[] = {
1154 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1160 return rte_flow_error_set(error, EINVAL,
1161 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1162 NULL, "zero mark action mask");
1163 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1166 MLX5_ASSERT(reg > 0);
1167 if (reg == REG_C_0) {
1168 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1169 uint32_t shl_c0 = rte_bsf32(msk_c0);
1171 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1172 mask = rte_cpu_to_be_32(mask) & msk_c0;
1173 mask = rte_cpu_to_be_32(mask << shl_c0);
1175 reg_c_x[0].id = reg_to_field[reg];
1176 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1177 MLX5_MODIFICATION_TYPE_SET, error);
1181 * Get metadata register index for specified steering domain.
1184 * Pointer to the rte_eth_dev structure.
1186 * Attributes of flow to determine steering domain.
1188 * Pointer to the error structure.
1191 * positive index on success, a negative errno value otherwise
1192 * and rte_errno is set.
1194 static enum modify_reg
1195 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1196 const struct rte_flow_attr *attr,
1197 struct rte_flow_error *error)
1200 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204 MLX5_METADATA_RX, 0, error);
1206 return rte_flow_error_set(error,
1207 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1208 NULL, "unavailable "
1209 "metadata register");
1214 * Convert SET_META action to DV specification.
1217 * Pointer to the rte_eth_dev structure.
1218 * @param[in,out] resource
1219 * Pointer to the modify-header resource.
1221 * Attributes of flow that includes this item.
1223 * Pointer to action specification.
1225 * Pointer to the error structure.
1228 * 0 on success, a negative errno value otherwise and rte_errno is set.
1231 flow_dv_convert_action_set_meta
1232 (struct rte_eth_dev *dev,
1233 struct mlx5_flow_dv_modify_hdr_resource *resource,
1234 const struct rte_flow_attr *attr,
1235 const struct rte_flow_action_set_meta *conf,
1236 struct rte_flow_error *error)
1238 uint32_t data = conf->data;
1239 uint32_t mask = conf->mask;
1240 struct rte_flow_item item = {
1244 struct field_modify_info reg_c_x[] = {
1247 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1252 * In datapath code there is no endianness
1253 * coversions for perfromance reasons, all
1254 * pattern conversions are done in rte_flow.
1256 if (reg == REG_C_0) {
1257 struct mlx5_priv *priv = dev->data->dev_private;
1258 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1261 MLX5_ASSERT(msk_c0);
1262 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1263 shl_c0 = rte_bsf32(msk_c0);
1265 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1271 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1272 /* The routine expects parameters in memory as big-endian ones. */
1273 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1274 MLX5_MODIFICATION_TYPE_SET, error);
1278 * Convert modify-header set IPv4 DSCP action to DV specification.
1280 * @param[in,out] resource
1281 * Pointer to the modify-header resource.
1283 * Pointer to action specification.
1285 * Pointer to the error structure.
1288 * 0 on success, a negative errno value otherwise and rte_errno is set.
1291 flow_dv_convert_action_modify_ipv4_dscp
1292 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1293 const struct rte_flow_action *action,
1294 struct rte_flow_error *error)
1296 const struct rte_flow_action_set_dscp *conf =
1297 (const struct rte_flow_action_set_dscp *)(action->conf);
1298 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1299 struct rte_flow_item_ipv4 ipv4;
1300 struct rte_flow_item_ipv4 ipv4_mask;
1302 memset(&ipv4, 0, sizeof(ipv4));
1303 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1304 ipv4.hdr.type_of_service = conf->dscp;
1305 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1307 item.mask = &ipv4_mask;
1308 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1309 MLX5_MODIFICATION_TYPE_SET, error);
1313 * Convert modify-header set IPv6 DSCP action to DV specification.
1315 * @param[in,out] resource
1316 * Pointer to the modify-header resource.
1318 * Pointer to action specification.
1320 * Pointer to the error structure.
1323 * 0 on success, a negative errno value otherwise and rte_errno is set.
1326 flow_dv_convert_action_modify_ipv6_dscp
1327 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1328 const struct rte_flow_action *action,
1329 struct rte_flow_error *error)
1331 const struct rte_flow_action_set_dscp *conf =
1332 (const struct rte_flow_action_set_dscp *)(action->conf);
1333 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1334 struct rte_flow_item_ipv6 ipv6;
1335 struct rte_flow_item_ipv6 ipv6_mask;
1337 memset(&ipv6, 0, sizeof(ipv6));
1338 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1340 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1341 * rdma-core only accept the DSCP bits byte aligned start from
1342 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1343 * bits in IPv6 case as rdma-core requires byte aligned value.
1345 ipv6.hdr.vtc_flow = conf->dscp;
1346 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1348 item.mask = &ipv6_mask;
1349 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1350 MLX5_MODIFICATION_TYPE_SET, error);
1354 * Validate MARK item.
1357 * Pointer to the rte_eth_dev structure.
1359 * Item specification.
1361 * Attributes of flow that includes this item.
1363 * Pointer to error structure.
1366 * 0 on success, a negative errno value otherwise and rte_errno is set.
1369 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1370 const struct rte_flow_item *item,
1371 const struct rte_flow_attr *attr __rte_unused,
1372 struct rte_flow_error *error)
1374 struct mlx5_priv *priv = dev->data->dev_private;
1375 struct mlx5_dev_config *config = &priv->config;
1376 const struct rte_flow_item_mark *spec = item->spec;
1377 const struct rte_flow_item_mark *mask = item->mask;
1378 const struct rte_flow_item_mark nic_mask = {
1379 .id = priv->sh->dv_mark_mask,
1383 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1384 return rte_flow_error_set(error, ENOTSUP,
1385 RTE_FLOW_ERROR_TYPE_ITEM, item,
1386 "extended metadata feature"
1388 if (!mlx5_flow_ext_mreg_supported(dev))
1389 return rte_flow_error_set(error, ENOTSUP,
1390 RTE_FLOW_ERROR_TYPE_ITEM, item,
1391 "extended metadata register"
1392 " isn't supported");
1394 return rte_flow_error_set(error, ENOTSUP,
1395 RTE_FLOW_ERROR_TYPE_ITEM, item,
1396 "extended metadata register"
1397 " isn't available");
1398 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402 return rte_flow_error_set(error, EINVAL,
1403 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1405 "data cannot be empty");
1406 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1407 return rte_flow_error_set(error, EINVAL,
1408 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1410 "mark id exceeds the limit");
1414 return rte_flow_error_set(error, EINVAL,
1415 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1416 "mask cannot be zero");
1418 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1419 (const uint8_t *)&nic_mask,
1420 sizeof(struct rte_flow_item_mark),
1428 * Validate META item.
1431 * Pointer to the rte_eth_dev structure.
1433 * Item specification.
1435 * Attributes of flow that includes this item.
1437 * Pointer to error structure.
1440 * 0 on success, a negative errno value otherwise and rte_errno is set.
1443 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1444 const struct rte_flow_item *item,
1445 const struct rte_flow_attr *attr,
1446 struct rte_flow_error *error)
1448 struct mlx5_priv *priv = dev->data->dev_private;
1449 struct mlx5_dev_config *config = &priv->config;
1450 const struct rte_flow_item_meta *spec = item->spec;
1451 const struct rte_flow_item_meta *mask = item->mask;
1452 struct rte_flow_item_meta nic_mask = {
1459 return rte_flow_error_set(error, EINVAL,
1460 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1462 "data cannot be empty");
1463 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1464 if (!mlx5_flow_ext_mreg_supported(dev))
1465 return rte_flow_error_set(error, ENOTSUP,
1466 RTE_FLOW_ERROR_TYPE_ITEM, item,
1467 "extended metadata register"
1468 " isn't supported");
1469 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473 return rte_flow_error_set(error, ENOTSUP,
1474 RTE_FLOW_ERROR_TYPE_ITEM, item,
1478 nic_mask.data = priv->sh->dv_meta_mask;
1479 } else if (attr->transfer) {
1480 return rte_flow_error_set(error, ENOTSUP,
1481 RTE_FLOW_ERROR_TYPE_ITEM, item,
1482 "extended metadata feature "
1483 "should be enabled when "
1484 "meta item is requested "
1485 "with e-switch mode ");
1488 mask = &rte_flow_item_meta_mask;
1490 return rte_flow_error_set(error, EINVAL,
1491 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1492 "mask cannot be zero");
1494 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1495 (const uint8_t *)&nic_mask,
1496 sizeof(struct rte_flow_item_meta),
1502 * Validate TAG item.
1505 * Pointer to the rte_eth_dev structure.
1507 * Item specification.
1509 * Attributes of flow that includes this item.
1511 * Pointer to error structure.
1514 * 0 on success, a negative errno value otherwise and rte_errno is set.
1517 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1518 const struct rte_flow_item *item,
1519 const struct rte_flow_attr *attr __rte_unused,
1520 struct rte_flow_error *error)
1522 const struct rte_flow_item_tag *spec = item->spec;
1523 const struct rte_flow_item_tag *mask = item->mask;
1524 const struct rte_flow_item_tag nic_mask = {
1525 .data = RTE_BE32(UINT32_MAX),
1530 if (!mlx5_flow_ext_mreg_supported(dev))
1531 return rte_flow_error_set(error, ENOTSUP,
1532 RTE_FLOW_ERROR_TYPE_ITEM, item,
1533 "extensive metadata register"
1534 " isn't supported");
1536 return rte_flow_error_set(error, EINVAL,
1537 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1539 "data cannot be empty");
1541 mask = &rte_flow_item_tag_mask;
1543 return rte_flow_error_set(error, EINVAL,
1544 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1545 "mask cannot be zero");
1547 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1548 (const uint8_t *)&nic_mask,
1549 sizeof(struct rte_flow_item_tag),
1553 if (mask->index != 0xff)
1554 return rte_flow_error_set(error, EINVAL,
1555 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1556 "partial mask for tag index"
1557 " is not supported");
1558 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1561 MLX5_ASSERT(ret != REG_NONE);
1566 * Validate vport item.
1569 * Pointer to the rte_eth_dev structure.
1571 * Item specification.
1573 * Attributes of flow that includes this item.
1574 * @param[in] item_flags
1575 * Bit-fields that holds the items detected until now.
1577 * Pointer to error structure.
1580 * 0 on success, a negative errno value otherwise and rte_errno is set.
1583 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1584 const struct rte_flow_item *item,
1585 const struct rte_flow_attr *attr,
1586 uint64_t item_flags,
1587 struct rte_flow_error *error)
1589 const struct rte_flow_item_port_id *spec = item->spec;
1590 const struct rte_flow_item_port_id *mask = item->mask;
1591 const struct rte_flow_item_port_id switch_mask = {
1594 struct mlx5_priv *esw_priv;
1595 struct mlx5_priv *dev_priv;
1598 if (!attr->transfer)
1599 return rte_flow_error_set(error, EINVAL,
1600 RTE_FLOW_ERROR_TYPE_ITEM,
1602 "match on port id is valid only"
1603 " when transfer flag is enabled");
1604 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1605 return rte_flow_error_set(error, ENOTSUP,
1606 RTE_FLOW_ERROR_TYPE_ITEM, item,
1607 "multiple source ports are not"
1610 mask = &switch_mask;
1611 if (mask->id != 0xffffffff)
1612 return rte_flow_error_set(error, ENOTSUP,
1613 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1615 "no support for partial mask on"
1617 ret = mlx5_flow_item_acceptable
1618 (item, (const uint8_t *)mask,
1619 (const uint8_t *)&rte_flow_item_port_id_mask,
1620 sizeof(struct rte_flow_item_port_id),
1626 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1628 return rte_flow_error_set(error, rte_errno,
1629 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1630 "failed to obtain E-Switch info for"
1632 dev_priv = mlx5_dev_to_eswitch_info(dev);
1634 return rte_flow_error_set(error, rte_errno,
1635 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1637 "failed to obtain E-Switch info");
1638 if (esw_priv->domain_id != dev_priv->domain_id)
1639 return rte_flow_error_set(error, EINVAL,
1640 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1641 "cannot match on a port from a"
1642 " different E-Switch");
1647 * Validate VLAN item.
1650 * Item specification.
1651 * @param[in] item_flags
1652 * Bit-fields that holds the items detected until now.
1654 * Ethernet device flow is being created on.
1656 * Pointer to error structure.
1659 * 0 on success, a negative errno value otherwise and rte_errno is set.
1662 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1663 uint64_t item_flags,
1664 struct rte_eth_dev *dev,
1665 struct rte_flow_error *error)
1667 const struct rte_flow_item_vlan *mask = item->mask;
1668 const struct rte_flow_item_vlan nic_mask = {
1669 .tci = RTE_BE16(UINT16_MAX),
1670 .inner_type = RTE_BE16(UINT16_MAX),
1672 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1674 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1675 MLX5_FLOW_LAYER_INNER_L4) :
1676 (MLX5_FLOW_LAYER_OUTER_L3 |
1677 MLX5_FLOW_LAYER_OUTER_L4);
1678 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1679 MLX5_FLOW_LAYER_OUTER_VLAN;
1681 if (item_flags & vlanm)
1682 return rte_flow_error_set(error, EINVAL,
1683 RTE_FLOW_ERROR_TYPE_ITEM, item,
1684 "multiple VLAN layers not supported");
1685 else if ((item_flags & l34m) != 0)
1686 return rte_flow_error_set(error, EINVAL,
1687 RTE_FLOW_ERROR_TYPE_ITEM, item,
1688 "VLAN cannot follow L3/L4 layer");
1690 mask = &rte_flow_item_vlan_mask;
1691 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1692 (const uint8_t *)&nic_mask,
1693 sizeof(struct rte_flow_item_vlan),
1697 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1698 struct mlx5_priv *priv = dev->data->dev_private;
1700 if (priv->vmwa_context) {
1702 * Non-NULL context means we have a virtual machine
1703 * and SR-IOV enabled, we have to create VLAN interface
1704 * to make hypervisor to setup E-Switch vport
1705 * context correctly. We avoid creating the multiple
1706 * VLAN interfaces, so we cannot support VLAN tag mask.
1708 return rte_flow_error_set(error, EINVAL,
1709 RTE_FLOW_ERROR_TYPE_ITEM,
1711 "VLAN tag mask is not"
1712 " supported in virtual"
1720 * GTP flags are contained in 1 byte of the format:
1721 * -------------------------------------------
1722 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1723 * |-----------------------------------------|
1724 * | value | Version | PT | Res | E | S | PN |
1725 * -------------------------------------------
1727 * Matching is supported only for GTP flags E, S, PN.
1729 #define MLX5_GTP_FLAGS_MASK 0x07
1732 * Validate GTP item.
1735 * Pointer to the rte_eth_dev structure.
1737 * Item specification.
1738 * @param[in] item_flags
1739 * Bit-fields that holds the items detected until now.
1741 * Pointer to error structure.
1744 * 0 on success, a negative errno value otherwise and rte_errno is set.
1747 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1748 const struct rte_flow_item *item,
1749 uint64_t item_flags,
1750 struct rte_flow_error *error)
1752 struct mlx5_priv *priv = dev->data->dev_private;
1753 const struct rte_flow_item_gtp *spec = item->spec;
1754 const struct rte_flow_item_gtp *mask = item->mask;
1755 const struct rte_flow_item_gtp nic_mask = {
1756 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1758 .teid = RTE_BE32(0xffffffff),
1761 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1762 return rte_flow_error_set(error, ENOTSUP,
1763 RTE_FLOW_ERROR_TYPE_ITEM, item,
1764 "GTP support is not enabled");
1765 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1766 return rte_flow_error_set(error, ENOTSUP,
1767 RTE_FLOW_ERROR_TYPE_ITEM, item,
1768 "multiple tunnel layers not"
1770 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1771 return rte_flow_error_set(error, EINVAL,
1772 RTE_FLOW_ERROR_TYPE_ITEM, item,
1773 "no outer UDP layer found");
1775 mask = &rte_flow_item_gtp_mask;
1776 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1777 return rte_flow_error_set(error, ENOTSUP,
1778 RTE_FLOW_ERROR_TYPE_ITEM, item,
1779 "Match is supported for GTP"
1781 return mlx5_flow_item_acceptable
1782 (item, (const uint8_t *)mask,
1783 (const uint8_t *)&nic_mask,
1784 sizeof(struct rte_flow_item_gtp),
1789 * Validate the pop VLAN action.
1792 * Pointer to the rte_eth_dev structure.
1793 * @param[in] action_flags
1794 * Holds the actions detected until now.
1796 * Pointer to the pop vlan action.
1797 * @param[in] item_flags
1798 * The items found in this flow rule.
1800 * Pointer to flow attributes.
1802 * Pointer to error structure.
1805 * 0 on success, a negative errno value otherwise and rte_errno is set.
1808 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1809 uint64_t action_flags,
1810 const struct rte_flow_action *action,
1811 uint64_t item_flags,
1812 const struct rte_flow_attr *attr,
1813 struct rte_flow_error *error)
1815 const struct mlx5_priv *priv = dev->data->dev_private;
1819 if (!priv->sh->pop_vlan_action)
1820 return rte_flow_error_set(error, ENOTSUP,
1821 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1823 "pop vlan action is not supported");
1825 return rte_flow_error_set(error, ENOTSUP,
1826 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1828 "pop vlan action not supported for "
1830 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1831 return rte_flow_error_set(error, ENOTSUP,
1832 RTE_FLOW_ERROR_TYPE_ACTION, action,
1833 "no support for multiple VLAN "
1835 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1836 return rte_flow_error_set(error, ENOTSUP,
1837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1839 "cannot pop vlan without a "
1840 "match on (outer) vlan in the flow");
1841 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1842 return rte_flow_error_set(error, EINVAL,
1843 RTE_FLOW_ERROR_TYPE_ACTION, action,
1844 "wrong action order, port_id should "
1845 "be after pop VLAN action");
1846 if (!attr->transfer && priv->representor)
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1849 "pop vlan action for VF representor "
1850 "not supported on NIC table");
1855 * Get VLAN default info from vlan match info.
1858 * the list of item specifications.
1860 * pointer VLAN info to fill to.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1867 struct rte_vlan_hdr *vlan)
1869 const struct rte_flow_item_vlan nic_mask = {
1870 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1871 MLX5DV_FLOW_VLAN_VID_MASK),
1872 .inner_type = RTE_BE16(0xffff),
1877 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1878 int type = items->type;
1880 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1881 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1884 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1885 const struct rte_flow_item_vlan *vlan_m = items->mask;
1886 const struct rte_flow_item_vlan *vlan_v = items->spec;
1888 /* If VLAN item in pattern doesn't contain data, return here. */
1893 /* Only full match values are accepted */
1894 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1895 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1896 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1898 rte_be_to_cpu_16(vlan_v->tci &
1899 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1901 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1902 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1903 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1905 rte_be_to_cpu_16(vlan_v->tci &
1906 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1908 if (vlan_m->inner_type == nic_mask.inner_type)
1909 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1910 vlan_m->inner_type);
1915 * Validate the push VLAN action.
1918 * Pointer to the rte_eth_dev structure.
1919 * @param[in] action_flags
1920 * Holds the actions detected until now.
1921 * @param[in] item_flags
1922 * The items found in this flow rule.
1924 * Pointer to the action structure.
1926 * Pointer to flow attributes
1928 * Pointer to error structure.
1931 * 0 on success, a negative errno value otherwise and rte_errno is set.
1934 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1935 uint64_t action_flags,
1936 const struct rte_flow_item_vlan *vlan_m,
1937 const struct rte_flow_action *action,
1938 const struct rte_flow_attr *attr,
1939 struct rte_flow_error *error)
1941 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1942 const struct mlx5_priv *priv = dev->data->dev_private;
1944 if (!attr->transfer && attr->ingress)
1945 return rte_flow_error_set(error, ENOTSUP,
1946 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1948 "push VLAN action not supported for "
1950 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1951 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1952 return rte_flow_error_set(error, EINVAL,
1953 RTE_FLOW_ERROR_TYPE_ACTION, action,
1954 "invalid vlan ethertype");
1955 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1956 return rte_flow_error_set(error, ENOTSUP,
1957 RTE_FLOW_ERROR_TYPE_ACTION, action,
1958 "no support for multiple VLAN "
1960 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ACTION, action,
1963 "wrong action order, port_id should "
1964 "be after push VLAN");
1965 if (!attr->transfer && priv->representor)
1966 return rte_flow_error_set(error, ENOTSUP,
1967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1968 "push vlan action for VF representor "
1969 "not supported on NIC table");
1971 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1972 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1973 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1974 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1975 !(mlx5_flow_find_action
1976 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1977 return rte_flow_error_set(error, EINVAL,
1978 RTE_FLOW_ERROR_TYPE_ACTION, action,
1979 "not full match mask on VLAN PCP and "
1980 "there is no of_set_vlan_pcp action, "
1981 "push VLAN action cannot figure out "
1984 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1985 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1986 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1987 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1988 !(mlx5_flow_find_action
1989 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1990 return rte_flow_error_set(error, EINVAL,
1991 RTE_FLOW_ERROR_TYPE_ACTION, action,
1992 "not full match mask on VLAN VID and "
1993 "there is no of_set_vlan_vid action, "
1994 "push VLAN action cannot figure out "
2001 * Validate the set VLAN PCP.
2003 * @param[in] action_flags
2004 * Holds the actions detected until now.
2005 * @param[in] actions
2006 * Pointer to the list of actions remaining in the flow rule.
2008 * Pointer to error structure.
2011 * 0 on success, a negative errno value otherwise and rte_errno is set.
2014 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2015 const struct rte_flow_action actions[],
2016 struct rte_flow_error *error)
2018 const struct rte_flow_action *action = actions;
2019 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2021 if (conf->vlan_pcp > 7)
2022 return rte_flow_error_set(error, EINVAL,
2023 RTE_FLOW_ERROR_TYPE_ACTION, action,
2024 "VLAN PCP value is too big");
2025 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, action,
2028 "set VLAN PCP action must follow "
2029 "the push VLAN action");
2030 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2031 return rte_flow_error_set(error, ENOTSUP,
2032 RTE_FLOW_ERROR_TYPE_ACTION, action,
2033 "Multiple VLAN PCP modification are "
2035 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "wrong action order, port_id should "
2039 "be after set VLAN PCP");
2044 * Validate the set VLAN VID.
2046 * @param[in] item_flags
2047 * Holds the items detected in this rule.
2048 * @param[in] action_flags
2049 * Holds the actions detected until now.
2050 * @param[in] actions
2051 * Pointer to the list of actions remaining in the flow rule.
2053 * Pointer to error structure.
2056 * 0 on success, a negative errno value otherwise and rte_errno is set.
2059 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2060 uint64_t action_flags,
2061 const struct rte_flow_action actions[],
2062 struct rte_flow_error *error)
2064 const struct rte_flow_action *action = actions;
2065 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2067 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION, action,
2070 "VLAN VID value is too big");
2071 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2072 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2073 return rte_flow_error_set(error, ENOTSUP,
2074 RTE_FLOW_ERROR_TYPE_ACTION, action,
2075 "set VLAN VID action must follow push"
2076 " VLAN action or match on VLAN item");
2077 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2078 return rte_flow_error_set(error, ENOTSUP,
2079 RTE_FLOW_ERROR_TYPE_ACTION, action,
2080 "Multiple VLAN VID modifications are "
2082 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION, action,
2085 "wrong action order, port_id should "
2086 "be after set VLAN VID");
2091 * Validate the FLAG action.
2094 * Pointer to the rte_eth_dev structure.
2095 * @param[in] action_flags
2096 * Holds the actions detected until now.
2098 * Pointer to flow attributes
2100 * Pointer to error structure.
2103 * 0 on success, a negative errno value otherwise and rte_errno is set.
2106 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2107 uint64_t action_flags,
2108 const struct rte_flow_attr *attr,
2109 struct rte_flow_error *error)
2111 struct mlx5_priv *priv = dev->data->dev_private;
2112 struct mlx5_dev_config *config = &priv->config;
2115 /* Fall back if no extended metadata register support. */
2116 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2117 return mlx5_flow_validate_action_flag(action_flags, attr,
2119 /* Extensive metadata mode requires registers. */
2120 if (!mlx5_flow_ext_mreg_supported(dev))
2121 return rte_flow_error_set(error, ENOTSUP,
2122 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2123 "no metadata registers "
2124 "to support flag action");
2125 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2126 return rte_flow_error_set(error, ENOTSUP,
2127 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2128 "extended metadata register"
2129 " isn't available");
2130 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2133 MLX5_ASSERT(ret > 0);
2134 if (action_flags & MLX5_FLOW_ACTION_MARK)
2135 return rte_flow_error_set(error, EINVAL,
2136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137 "can't mark and flag in same flow");
2138 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2139 return rte_flow_error_set(error, EINVAL,
2140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2142 " actions in same flow");
2147 * Validate MARK action.
2150 * Pointer to the rte_eth_dev structure.
2152 * Pointer to action.
2153 * @param[in] action_flags
2154 * Holds the actions detected until now.
2156 * Pointer to flow attributes
2158 * Pointer to error structure.
2161 * 0 on success, a negative errno value otherwise and rte_errno is set.
2164 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2165 const struct rte_flow_action *action,
2166 uint64_t action_flags,
2167 const struct rte_flow_attr *attr,
2168 struct rte_flow_error *error)
2170 struct mlx5_priv *priv = dev->data->dev_private;
2171 struct mlx5_dev_config *config = &priv->config;
2172 const struct rte_flow_action_mark *mark = action->conf;
2175 /* Fall back if no extended metadata register support. */
2176 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2177 return mlx5_flow_validate_action_mark(action, action_flags,
2179 /* Extensive metadata mode requires registers. */
2180 if (!mlx5_flow_ext_mreg_supported(dev))
2181 return rte_flow_error_set(error, ENOTSUP,
2182 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183 "no metadata registers "
2184 "to support mark action");
2185 if (!priv->sh->dv_mark_mask)
2186 return rte_flow_error_set(error, ENOTSUP,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "extended metadata register"
2189 " isn't available");
2190 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2193 MLX5_ASSERT(ret > 0);
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, action,
2197 "configuration cannot be null");
2198 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2199 return rte_flow_error_set(error, EINVAL,
2200 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2202 "mark id exceeds the limit");
2203 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2204 return rte_flow_error_set(error, EINVAL,
2205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206 "can't flag and mark in same flow");
2207 if (action_flags & MLX5_FLOW_ACTION_MARK)
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2210 "can't have 2 mark actions in same"
2216 * Validate SET_META action.
2219 * Pointer to the rte_eth_dev structure.
2221 * Pointer to the action structure.
2222 * @param[in] action_flags
2223 * Holds the actions detected until now.
2225 * Pointer to flow attributes
2227 * Pointer to error structure.
2230 * 0 on success, a negative errno value otherwise and rte_errno is set.
2233 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2234 const struct rte_flow_action *action,
2235 uint64_t action_flags __rte_unused,
2236 const struct rte_flow_attr *attr,
2237 struct rte_flow_error *error)
2239 const struct rte_flow_action_set_meta *conf;
2240 uint32_t nic_mask = UINT32_MAX;
2243 if (!mlx5_flow_ext_mreg_supported(dev))
2244 return rte_flow_error_set(error, ENOTSUP,
2245 RTE_FLOW_ERROR_TYPE_ACTION, action,
2246 "extended metadata register"
2247 " isn't supported");
2248 reg = flow_dv_get_metadata_reg(dev, attr, error);
2251 if (reg != REG_A && reg != REG_B) {
2252 struct mlx5_priv *priv = dev->data->dev_private;
2254 nic_mask = priv->sh->dv_meta_mask;
2256 if (!(action->conf))
2257 return rte_flow_error_set(error, EINVAL,
2258 RTE_FLOW_ERROR_TYPE_ACTION, action,
2259 "configuration cannot be null");
2260 conf = (const struct rte_flow_action_set_meta *)action->conf;
2262 return rte_flow_error_set(error, EINVAL,
2263 RTE_FLOW_ERROR_TYPE_ACTION, action,
2264 "zero mask doesn't have any effect");
2265 if (conf->mask & ~nic_mask)
2266 return rte_flow_error_set(error, EINVAL,
2267 RTE_FLOW_ERROR_TYPE_ACTION, action,
2268 "meta data must be within reg C0");
2273 * Validate SET_TAG action.
2276 * Pointer to the rte_eth_dev structure.
2278 * Pointer to the action structure.
2279 * @param[in] action_flags
2280 * Holds the actions detected until now.
2282 * Pointer to flow attributes
2284 * Pointer to error structure.
2287 * 0 on success, a negative errno value otherwise and rte_errno is set.
2290 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2291 const struct rte_flow_action *action,
2292 uint64_t action_flags,
2293 const struct rte_flow_attr *attr,
2294 struct rte_flow_error *error)
2296 const struct rte_flow_action_set_tag *conf;
2297 const uint64_t terminal_action_flags =
2298 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2299 MLX5_FLOW_ACTION_RSS;
2302 if (!mlx5_flow_ext_mreg_supported(dev))
2303 return rte_flow_error_set(error, ENOTSUP,
2304 RTE_FLOW_ERROR_TYPE_ACTION, action,
2305 "extensive metadata register"
2306 " isn't supported");
2307 if (!(action->conf))
2308 return rte_flow_error_set(error, EINVAL,
2309 RTE_FLOW_ERROR_TYPE_ACTION, action,
2310 "configuration cannot be null");
2311 conf = (const struct rte_flow_action_set_tag *)action->conf;
2313 return rte_flow_error_set(error, EINVAL,
2314 RTE_FLOW_ERROR_TYPE_ACTION, action,
2315 "zero mask doesn't have any effect");
2316 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2319 if (!attr->transfer && attr->ingress &&
2320 (action_flags & terminal_action_flags))
2321 return rte_flow_error_set(error, EINVAL,
2322 RTE_FLOW_ERROR_TYPE_ACTION, action,
2323 "set_tag has no effect"
2324 " with terminal actions");
2329 * Validate count action.
2332 * Pointer to rte_eth_dev structure.
2334 * Pointer to error structure.
2337 * 0 on success, a negative errno value otherwise and rte_errno is set.
2340 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2341 struct rte_flow_error *error)
2343 struct mlx5_priv *priv = dev->data->dev_private;
2345 if (!priv->config.devx)
2347 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2351 return rte_flow_error_set
2353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2355 "count action not supported");
2359 * Validate the L2 encap action.
2362 * Pointer to the rte_eth_dev structure.
2363 * @param[in] action_flags
2364 * Holds the actions detected until now.
2366 * Pointer to the action structure.
2368 * Pointer to flow attributes.
2370 * Pointer to error structure.
2373 * 0 on success, a negative errno value otherwise and rte_errno is set.
2376 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2377 uint64_t action_flags,
2378 const struct rte_flow_action *action,
2379 const struct rte_flow_attr *attr,
2380 struct rte_flow_error *error)
2382 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (!(action->conf))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, action,
2387 "configuration cannot be null");
2388 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2389 return rte_flow_error_set(error, EINVAL,
2390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391 "can only have a single encap action "
2393 if (!attr->transfer && priv->representor)
2394 return rte_flow_error_set(error, ENOTSUP,
2395 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396 "encap action for VF representor "
2397 "not supported on NIC table");
2402 * Validate a decap action.
2405 * Pointer to the rte_eth_dev structure.
2406 * @param[in] action_flags
2407 * Holds the actions detected until now.
2409 * Pointer to flow attributes
2411 * Pointer to error structure.
2414 * 0 on success, a negative errno value otherwise and rte_errno is set.
2417 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2418 uint64_t action_flags,
2419 const struct rte_flow_attr *attr,
2420 struct rte_flow_error *error)
2422 const struct mlx5_priv *priv = dev->data->dev_private;
2424 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2425 !priv->config.decap_en)
2426 return rte_flow_error_set(error, ENOTSUP,
2427 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2428 "decap is not enabled");
2429 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2433 MLX5_FLOW_ACTION_DECAP ? "can only "
2434 "have a single decap action" : "decap "
2435 "after encap is not supported");
2436 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2437 return rte_flow_error_set(error, EINVAL,
2438 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2439 "can't have decap action after"
2442 return rte_flow_error_set(error, ENOTSUP,
2443 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2445 "decap action not supported for "
2447 if (!attr->transfer && priv->representor)
2448 return rte_flow_error_set(error, ENOTSUP,
2449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2450 "decap action for VF representor "
2451 "not supported on NIC table");
2455 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2458 * Validate the raw encap and decap actions.
2461 * Pointer to the rte_eth_dev structure.
2463 * Pointer to the decap action.
2465 * Pointer to the encap action.
2467 * Pointer to flow attributes
2468 * @param[in/out] action_flags
2469 * Holds the actions detected until now.
2470 * @param[out] actions_n
2471 * pointer to the number of actions counter.
2473 * Pointer to error structure.
2476 * 0 on success, a negative errno value otherwise and rte_errno is set.
2479 flow_dv_validate_action_raw_encap_decap
2480 (struct rte_eth_dev *dev,
2481 const struct rte_flow_action_raw_decap *decap,
2482 const struct rte_flow_action_raw_encap *encap,
2483 const struct rte_flow_attr *attr, uint64_t *action_flags,
2484 int *actions_n, struct rte_flow_error *error)
2486 const struct mlx5_priv *priv = dev->data->dev_private;
2489 if (encap && (!encap->size || !encap->data))
2490 return rte_flow_error_set(error, EINVAL,
2491 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2492 "raw encap data cannot be empty");
2493 if (decap && encap) {
2494 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2495 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2498 else if (encap->size <=
2499 MLX5_ENCAPSULATION_DECISION_SIZE &&
2501 MLX5_ENCAPSULATION_DECISION_SIZE)
2504 else if (encap->size >
2505 MLX5_ENCAPSULATION_DECISION_SIZE &&
2507 MLX5_ENCAPSULATION_DECISION_SIZE)
2508 /* 2 L2 actions: encap and decap. */
2511 return rte_flow_error_set(error,
2513 RTE_FLOW_ERROR_TYPE_ACTION,
2514 NULL, "unsupported too small "
2515 "raw decap and too small raw "
2516 "encap combination");
2519 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2523 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2527 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2528 return rte_flow_error_set(error, ENOTSUP,
2529 RTE_FLOW_ERROR_TYPE_ACTION,
2531 "small raw encap size");
2532 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2533 return rte_flow_error_set(error, EINVAL,
2534 RTE_FLOW_ERROR_TYPE_ACTION,
2536 "more than one encap action");
2537 if (!attr->transfer && priv->representor)
2538 return rte_flow_error_set
2540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2541 "encap action for VF representor "
2542 "not supported on NIC table");
2543 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2550 * Find existing encap/decap resource or create and register a new one.
2552 * @param[in, out] dev
2553 * Pointer to rte_eth_dev structure.
2554 * @param[in, out] resource
2555 * Pointer to encap/decap resource.
2556 * @parm[in, out] dev_flow
2557 * Pointer to the dev_flow.
2559 * pointer to error structure.
2562 * 0 on success otherwise -errno and errno is set.
2565 flow_dv_encap_decap_resource_register
2566 (struct rte_eth_dev *dev,
2567 struct mlx5_flow_dv_encap_decap_resource *resource,
2568 struct mlx5_flow *dev_flow,
2569 struct rte_flow_error *error)
2571 struct mlx5_priv *priv = dev->data->dev_private;
2572 struct mlx5_dev_ctx_shared *sh = priv->sh;
2573 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2574 struct mlx5dv_dr_domain *domain;
2578 resource->flags = dev_flow->dv.group ? 0 : 1;
2579 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2580 domain = sh->fdb_domain;
2581 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2582 domain = sh->rx_domain;
2584 domain = sh->tx_domain;
2585 /* Lookup a matching resource from cache. */
2586 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2587 cache_resource, next) {
2588 if (resource->reformat_type == cache_resource->reformat_type &&
2589 resource->ft_type == cache_resource->ft_type &&
2590 resource->flags == cache_resource->flags &&
2591 resource->size == cache_resource->size &&
2592 !memcmp((const void *)resource->buf,
2593 (const void *)cache_resource->buf,
2595 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2596 (void *)cache_resource,
2597 rte_atomic32_read(&cache_resource->refcnt));
2598 rte_atomic32_inc(&cache_resource->refcnt);
2599 dev_flow->handle->dvh.rix_encap_decap = idx;
2600 dev_flow->dv.encap_decap = cache_resource;
2604 /* Register new encap/decap resource. */
2605 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2606 &dev_flow->handle->dvh.rix_encap_decap);
2607 if (!cache_resource)
2608 return rte_flow_error_set(error, ENOMEM,
2609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2610 "cannot allocate resource memory");
2611 *cache_resource = *resource;
2612 ret = mlx5_flow_os_create_flow_action_packet_reformat
2613 (sh->ctx, domain, cache_resource,
2614 &cache_resource->action);
2616 mlx5_free(cache_resource);
2617 return rte_flow_error_set(error, ENOMEM,
2618 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2619 NULL, "cannot create action");
2621 rte_atomic32_init(&cache_resource->refcnt);
2622 rte_atomic32_inc(&cache_resource->refcnt);
2623 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2624 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2626 dev_flow->dv.encap_decap = cache_resource;
2627 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2628 (void *)cache_resource,
2629 rte_atomic32_read(&cache_resource->refcnt));
2634 * Find existing table jump resource or create and register a new one.
2636 * @param[in, out] dev
2637 * Pointer to rte_eth_dev structure.
2638 * @param[in, out] tbl
2639 * Pointer to flow table resource.
2640 * @parm[in, out] dev_flow
2641 * Pointer to the dev_flow.
2643 * pointer to error structure.
2646 * 0 on success otherwise -errno and errno is set.
2649 flow_dv_jump_tbl_resource_register
2650 (struct rte_eth_dev *dev __rte_unused,
2651 struct mlx5_flow_tbl_resource *tbl,
2652 struct mlx5_flow *dev_flow,
2653 struct rte_flow_error *error)
2655 struct mlx5_flow_tbl_data_entry *tbl_data =
2656 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2660 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2662 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2663 (tbl->obj, &tbl_data->jump.action);
2665 return rte_flow_error_set(error, ENOMEM,
2666 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2667 NULL, "cannot create jump action");
2668 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2669 (void *)&tbl_data->jump, cnt);
2671 /* old jump should not make the table ref++. */
2672 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2673 MLX5_ASSERT(tbl_data->jump.action);
2674 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2675 (void *)&tbl_data->jump, cnt);
2677 rte_atomic32_inc(&tbl_data->jump.refcnt);
2678 dev_flow->handle->rix_jump = tbl_data->idx;
2679 dev_flow->dv.jump = &tbl_data->jump;
2684 * Find existing default miss resource or create and register a new one.
2686 * @param[in, out] dev
2687 * Pointer to rte_eth_dev structure.
2689 * pointer to error structure.
2692 * 0 on success otherwise -errno and errno is set.
2695 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2696 struct rte_flow_error *error)
2698 struct mlx5_priv *priv = dev->data->dev_private;
2699 struct mlx5_dev_ctx_shared *sh = priv->sh;
2700 struct mlx5_flow_default_miss_resource *cache_resource =
2702 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2705 MLX5_ASSERT(cache_resource->action);
2706 cache_resource->action =
2707 mlx5_glue->dr_create_flow_action_default_miss();
2708 if (!cache_resource->action)
2709 return rte_flow_error_set(error, ENOMEM,
2710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2711 "cannot create default miss action");
2712 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2713 (void *)cache_resource->action, cnt);
2715 rte_atomic32_inc(&cache_resource->refcnt);
2720 * Find existing table port ID resource or create and register a new one.
2722 * @param[in, out] dev
2723 * Pointer to rte_eth_dev structure.
2724 * @param[in, out] resource
2725 * Pointer to port ID action resource.
2726 * @parm[in, out] dev_flow
2727 * Pointer to the dev_flow.
2729 * pointer to error structure.
2732 * 0 on success otherwise -errno and errno is set.
2735 flow_dv_port_id_action_resource_register
2736 (struct rte_eth_dev *dev,
2737 struct mlx5_flow_dv_port_id_action_resource *resource,
2738 struct mlx5_flow *dev_flow,
2739 struct rte_flow_error *error)
2741 struct mlx5_priv *priv = dev->data->dev_private;
2742 struct mlx5_dev_ctx_shared *sh = priv->sh;
2743 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2747 /* Lookup a matching resource from cache. */
2748 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2749 idx, cache_resource, next) {
2750 if (resource->port_id == cache_resource->port_id) {
2751 DRV_LOG(DEBUG, "port id action resource resource %p: "
2753 (void *)cache_resource,
2754 rte_atomic32_read(&cache_resource->refcnt));
2755 rte_atomic32_inc(&cache_resource->refcnt);
2756 dev_flow->handle->rix_port_id_action = idx;
2757 dev_flow->dv.port_id_action = cache_resource;
2761 /* Register new port id action resource. */
2762 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2763 &dev_flow->handle->rix_port_id_action);
2764 if (!cache_resource)
2765 return rte_flow_error_set(error, ENOMEM,
2766 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2767 "cannot allocate resource memory");
2768 *cache_resource = *resource;
2769 ret = mlx5_flow_os_create_flow_action_dest_port
2770 (priv->sh->fdb_domain, resource->port_id,
2771 &cache_resource->action);
2773 mlx5_free(cache_resource);
2774 return rte_flow_error_set(error, ENOMEM,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2776 NULL, "cannot create action");
2778 rte_atomic32_init(&cache_resource->refcnt);
2779 rte_atomic32_inc(&cache_resource->refcnt);
2780 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2781 dev_flow->handle->rix_port_id_action, cache_resource,
2783 dev_flow->dv.port_id_action = cache_resource;
2784 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2785 (void *)cache_resource,
2786 rte_atomic32_read(&cache_resource->refcnt));
2791 * Find existing push vlan resource or create and register a new one.
2793 * @param [in, out] dev
2794 * Pointer to rte_eth_dev structure.
2795 * @param[in, out] resource
2796 * Pointer to port ID action resource.
2797 * @parm[in, out] dev_flow
2798 * Pointer to the dev_flow.
2800 * pointer to error structure.
2803 * 0 on success otherwise -errno and errno is set.
2806 flow_dv_push_vlan_action_resource_register
2807 (struct rte_eth_dev *dev,
2808 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2809 struct mlx5_flow *dev_flow,
2810 struct rte_flow_error *error)
2812 struct mlx5_priv *priv = dev->data->dev_private;
2813 struct mlx5_dev_ctx_shared *sh = priv->sh;
2814 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2815 struct mlx5dv_dr_domain *domain;
2819 /* Lookup a matching resource from cache. */
2820 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821 sh->push_vlan_action_list, idx, cache_resource, next) {
2822 if (resource->vlan_tag == cache_resource->vlan_tag &&
2823 resource->ft_type == cache_resource->ft_type) {
2824 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2826 (void *)cache_resource,
2827 rte_atomic32_read(&cache_resource->refcnt));
2828 rte_atomic32_inc(&cache_resource->refcnt);
2829 dev_flow->handle->dvh.rix_push_vlan = idx;
2830 dev_flow->dv.push_vlan_res = cache_resource;
2834 /* Register new push_vlan action resource. */
2835 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2836 &dev_flow->handle->dvh.rix_push_vlan);
2837 if (!cache_resource)
2838 return rte_flow_error_set(error, ENOMEM,
2839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2840 "cannot allocate resource memory");
2841 *cache_resource = *resource;
2842 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2843 domain = sh->fdb_domain;
2844 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2845 domain = sh->rx_domain;
2847 domain = sh->tx_domain;
2848 ret = mlx5_flow_os_create_flow_action_push_vlan
2849 (domain, resource->vlan_tag,
2850 &cache_resource->action);
2852 mlx5_free(cache_resource);
2853 return rte_flow_error_set(error, ENOMEM,
2854 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2855 NULL, "cannot create action");
2857 rte_atomic32_init(&cache_resource->refcnt);
2858 rte_atomic32_inc(&cache_resource->refcnt);
2859 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2860 &sh->push_vlan_action_list,
2861 dev_flow->handle->dvh.rix_push_vlan,
2862 cache_resource, next);
2863 dev_flow->dv.push_vlan_res = cache_resource;
2864 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2865 (void *)cache_resource,
2866 rte_atomic32_read(&cache_resource->refcnt));
2870 * Get the size of specific rte_flow_item_type
2872 * @param[in] item_type
2873 * Tested rte_flow_item_type.
2876 * sizeof struct item_type, 0 if void or irrelevant.
2879 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2883 switch (item_type) {
2884 case RTE_FLOW_ITEM_TYPE_ETH:
2885 retval = sizeof(struct rte_flow_item_eth);
2887 case RTE_FLOW_ITEM_TYPE_VLAN:
2888 retval = sizeof(struct rte_flow_item_vlan);
2890 case RTE_FLOW_ITEM_TYPE_IPV4:
2891 retval = sizeof(struct rte_flow_item_ipv4);
2893 case RTE_FLOW_ITEM_TYPE_IPV6:
2894 retval = sizeof(struct rte_flow_item_ipv6);
2896 case RTE_FLOW_ITEM_TYPE_UDP:
2897 retval = sizeof(struct rte_flow_item_udp);
2899 case RTE_FLOW_ITEM_TYPE_TCP:
2900 retval = sizeof(struct rte_flow_item_tcp);
2902 case RTE_FLOW_ITEM_TYPE_VXLAN:
2903 retval = sizeof(struct rte_flow_item_vxlan);
2905 case RTE_FLOW_ITEM_TYPE_GRE:
2906 retval = sizeof(struct rte_flow_item_gre);
2908 case RTE_FLOW_ITEM_TYPE_NVGRE:
2909 retval = sizeof(struct rte_flow_item_nvgre);
2911 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2912 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2914 case RTE_FLOW_ITEM_TYPE_MPLS:
2915 retval = sizeof(struct rte_flow_item_mpls);
2917 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2925 #define MLX5_ENCAP_IPV4_VERSION 0x40
2926 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2927 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2928 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2929 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2930 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2931 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2934 * Convert the encap action data from list of rte_flow_item to raw buffer
2937 * Pointer to rte_flow_item objects list.
2939 * Pointer to the output buffer.
2941 * Pointer to the output buffer size.
2943 * Pointer to the error structure.
2946 * 0 on success, a negative errno value otherwise and rte_errno is set.
2949 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2950 size_t *size, struct rte_flow_error *error)
2952 struct rte_ether_hdr *eth = NULL;
2953 struct rte_vlan_hdr *vlan = NULL;
2954 struct rte_ipv4_hdr *ipv4 = NULL;
2955 struct rte_ipv6_hdr *ipv6 = NULL;
2956 struct rte_udp_hdr *udp = NULL;
2957 struct rte_vxlan_hdr *vxlan = NULL;
2958 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2959 struct rte_gre_hdr *gre = NULL;
2961 size_t temp_size = 0;
2964 return rte_flow_error_set(error, EINVAL,
2965 RTE_FLOW_ERROR_TYPE_ACTION,
2966 NULL, "invalid empty data");
2967 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2968 len = flow_dv_get_item_len(items->type);
2969 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2970 return rte_flow_error_set(error, EINVAL,
2971 RTE_FLOW_ERROR_TYPE_ACTION,
2972 (void *)items->type,
2973 "items total size is too big"
2974 " for encap action");
2975 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2976 switch (items->type) {
2977 case RTE_FLOW_ITEM_TYPE_ETH:
2978 eth = (struct rte_ether_hdr *)&buf[temp_size];
2980 case RTE_FLOW_ITEM_TYPE_VLAN:
2981 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2983 return rte_flow_error_set(error, EINVAL,
2984 RTE_FLOW_ERROR_TYPE_ACTION,
2985 (void *)items->type,
2986 "eth header not found");
2987 if (!eth->ether_type)
2988 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2990 case RTE_FLOW_ITEM_TYPE_IPV4:
2991 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2993 return rte_flow_error_set(error, EINVAL,
2994 RTE_FLOW_ERROR_TYPE_ACTION,
2995 (void *)items->type,
2996 "neither eth nor vlan"
2998 if (vlan && !vlan->eth_proto)
2999 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3000 else if (eth && !eth->ether_type)
3001 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3002 if (!ipv4->version_ihl)
3003 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3004 MLX5_ENCAP_IPV4_IHL_MIN;
3005 if (!ipv4->time_to_live)
3006 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3008 case RTE_FLOW_ITEM_TYPE_IPV6:
3009 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3011 return rte_flow_error_set(error, EINVAL,
3012 RTE_FLOW_ERROR_TYPE_ACTION,
3013 (void *)items->type,
3014 "neither eth nor vlan"
3016 if (vlan && !vlan->eth_proto)
3017 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3018 else if (eth && !eth->ether_type)
3019 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3020 if (!ipv6->vtc_flow)
3022 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3023 if (!ipv6->hop_limits)
3024 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3026 case RTE_FLOW_ITEM_TYPE_UDP:
3027 udp = (struct rte_udp_hdr *)&buf[temp_size];
3029 return rte_flow_error_set(error, EINVAL,
3030 RTE_FLOW_ERROR_TYPE_ACTION,
3031 (void *)items->type,
3032 "ip header not found");
3033 if (ipv4 && !ipv4->next_proto_id)
3034 ipv4->next_proto_id = IPPROTO_UDP;
3035 else if (ipv6 && !ipv6->proto)
3036 ipv6->proto = IPPROTO_UDP;
3038 case RTE_FLOW_ITEM_TYPE_VXLAN:
3039 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3041 return rte_flow_error_set(error, EINVAL,
3042 RTE_FLOW_ERROR_TYPE_ACTION,
3043 (void *)items->type,
3044 "udp header not found");
3046 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3047 if (!vxlan->vx_flags)
3049 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3051 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3052 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3054 return rte_flow_error_set(error, EINVAL,
3055 RTE_FLOW_ERROR_TYPE_ACTION,
3056 (void *)items->type,
3057 "udp header not found");
3058 if (!vxlan_gpe->proto)
3059 return rte_flow_error_set(error, EINVAL,
3060 RTE_FLOW_ERROR_TYPE_ACTION,
3061 (void *)items->type,
3062 "next protocol not found");
3065 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3066 if (!vxlan_gpe->vx_flags)
3067 vxlan_gpe->vx_flags =
3068 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3070 case RTE_FLOW_ITEM_TYPE_GRE:
3071 case RTE_FLOW_ITEM_TYPE_NVGRE:
3072 gre = (struct rte_gre_hdr *)&buf[temp_size];
3074 return rte_flow_error_set(error, EINVAL,
3075 RTE_FLOW_ERROR_TYPE_ACTION,
3076 (void *)items->type,
3077 "next protocol not found");
3079 return rte_flow_error_set(error, EINVAL,
3080 RTE_FLOW_ERROR_TYPE_ACTION,
3081 (void *)items->type,
3082 "ip header not found");
3083 if (ipv4 && !ipv4->next_proto_id)
3084 ipv4->next_proto_id = IPPROTO_GRE;
3085 else if (ipv6 && !ipv6->proto)
3086 ipv6->proto = IPPROTO_GRE;
3088 case RTE_FLOW_ITEM_TYPE_VOID:
3091 return rte_flow_error_set(error, EINVAL,
3092 RTE_FLOW_ERROR_TYPE_ACTION,
3093 (void *)items->type,
3094 "unsupported item type");
3104 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3106 struct rte_ether_hdr *eth = NULL;
3107 struct rte_vlan_hdr *vlan = NULL;
3108 struct rte_ipv6_hdr *ipv6 = NULL;
3109 struct rte_udp_hdr *udp = NULL;
3113 eth = (struct rte_ether_hdr *)data;
3114 next_hdr = (char *)(eth + 1);
3115 proto = RTE_BE16(eth->ether_type);
3118 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3119 vlan = (struct rte_vlan_hdr *)next_hdr;
3120 proto = RTE_BE16(vlan->eth_proto);
3121 next_hdr += sizeof(struct rte_vlan_hdr);
3124 /* HW calculates IPv4 csum. no need to proceed */
3125 if (proto == RTE_ETHER_TYPE_IPV4)
3128 /* non IPv4/IPv6 header. not supported */
3129 if (proto != RTE_ETHER_TYPE_IPV6) {
3130 return rte_flow_error_set(error, ENOTSUP,
3131 RTE_FLOW_ERROR_TYPE_ACTION,
3132 NULL, "Cannot offload non IPv4/IPv6");
3135 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3137 /* ignore non UDP */
3138 if (ipv6->proto != IPPROTO_UDP)
3141 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3142 udp->dgram_cksum = 0;
3148 * Convert L2 encap action to DV specification.
3151 * Pointer to rte_eth_dev structure.
3153 * Pointer to action structure.
3154 * @param[in, out] dev_flow
3155 * Pointer to the mlx5_flow.
3156 * @param[in] transfer
3157 * Mark if the flow is E-Switch flow.
3159 * Pointer to the error structure.
3162 * 0 on success, a negative errno value otherwise and rte_errno is set.
3165 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3166 const struct rte_flow_action *action,
3167 struct mlx5_flow *dev_flow,
3169 struct rte_flow_error *error)
3171 const struct rte_flow_item *encap_data;
3172 const struct rte_flow_action_raw_encap *raw_encap_data;
3173 struct mlx5_flow_dv_encap_decap_resource res = {
3175 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3176 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3177 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3180 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3182 (const struct rte_flow_action_raw_encap *)action->conf;
3183 res.size = raw_encap_data->size;
3184 memcpy(res.buf, raw_encap_data->data, res.size);
3186 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3188 ((const struct rte_flow_action_vxlan_encap *)
3189 action->conf)->definition;
3192 ((const struct rte_flow_action_nvgre_encap *)
3193 action->conf)->definition;
3194 if (flow_dv_convert_encap_data(encap_data, res.buf,
3198 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3200 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3201 return rte_flow_error_set(error, EINVAL,
3202 RTE_FLOW_ERROR_TYPE_ACTION,
3203 NULL, "can't create L2 encap action");
3208 * Convert L2 decap action to DV specification.
3211 * Pointer to rte_eth_dev structure.
3212 * @param[in, out] dev_flow
3213 * Pointer to the mlx5_flow.
3214 * @param[in] transfer
3215 * Mark if the flow is E-Switch flow.
3217 * Pointer to the error structure.
3220 * 0 on success, a negative errno value otherwise and rte_errno is set.
3223 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3224 struct mlx5_flow *dev_flow,
3226 struct rte_flow_error *error)
3228 struct mlx5_flow_dv_encap_decap_resource res = {
3231 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3232 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3233 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3236 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3237 return rte_flow_error_set(error, EINVAL,
3238 RTE_FLOW_ERROR_TYPE_ACTION,
3239 NULL, "can't create L2 decap action");
3244 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3247 * Pointer to rte_eth_dev structure.
3249 * Pointer to action structure.
3250 * @param[in, out] dev_flow
3251 * Pointer to the mlx5_flow.
3253 * Pointer to the flow attributes.
3255 * Pointer to the error structure.
3258 * 0 on success, a negative errno value otherwise and rte_errno is set.
3261 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3262 const struct rte_flow_action *action,
3263 struct mlx5_flow *dev_flow,
3264 const struct rte_flow_attr *attr,
3265 struct rte_flow_error *error)
3267 const struct rte_flow_action_raw_encap *encap_data;
3268 struct mlx5_flow_dv_encap_decap_resource res;
3270 memset(&res, 0, sizeof(res));
3271 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3272 res.size = encap_data->size;
3273 memcpy(res.buf, encap_data->data, res.size);
3274 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3275 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3276 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3278 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3280 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3281 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3282 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3283 return rte_flow_error_set(error, EINVAL,
3284 RTE_FLOW_ERROR_TYPE_ACTION,
3285 NULL, "can't create encap action");
3290 * Create action push VLAN.
3293 * Pointer to rte_eth_dev structure.
3295 * Pointer to the flow attributes.
3297 * Pointer to the vlan to push to the Ethernet header.
3298 * @param[in, out] dev_flow
3299 * Pointer to the mlx5_flow.
3301 * Pointer to the error structure.
3304 * 0 on success, a negative errno value otherwise and rte_errno is set.
3307 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3308 const struct rte_flow_attr *attr,
3309 const struct rte_vlan_hdr *vlan,
3310 struct mlx5_flow *dev_flow,
3311 struct rte_flow_error *error)
3313 struct mlx5_flow_dv_push_vlan_action_resource res;
3315 memset(&res, 0, sizeof(res));
3317 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3320 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3322 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3323 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3324 return flow_dv_push_vlan_action_resource_register
3325 (dev, &res, dev_flow, error);
3329 * Validate the modify-header actions.
3331 * @param[in] action_flags
3332 * Holds the actions detected until now.
3334 * Pointer to the modify action.
3336 * Pointer to error structure.
3339 * 0 on success, a negative errno value otherwise and rte_errno is set.
3342 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3343 const struct rte_flow_action *action,
3344 struct rte_flow_error *error)
3346 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3349 NULL, "action configuration not set");
3350 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3351 return rte_flow_error_set(error, EINVAL,
3352 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3353 "can't have encap action before"
3359 * Validate the modify-header MAC address actions.
3361 * @param[in] action_flags
3362 * Holds the actions detected until now.
3364 * Pointer to the modify action.
3365 * @param[in] item_flags
3366 * Holds the items detected.
3368 * Pointer to error structure.
3371 * 0 on success, a negative errno value otherwise and rte_errno is set.
3374 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3375 const struct rte_flow_action *action,
3376 const uint64_t item_flags,
3377 struct rte_flow_error *error)
3381 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3383 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3384 return rte_flow_error_set(error, EINVAL,
3385 RTE_FLOW_ERROR_TYPE_ACTION,
3387 "no L2 item in pattern");
3393 * Validate the modify-header IPv4 address actions.
3395 * @param[in] action_flags
3396 * Holds the actions detected until now.
3398 * Pointer to the modify action.
3399 * @param[in] item_flags
3400 * Holds the items detected.
3402 * Pointer to error structure.
3405 * 0 on success, a negative errno value otherwise and rte_errno is set.
3408 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3409 const struct rte_flow_action *action,
3410 const uint64_t item_flags,
3411 struct rte_flow_error *error)
3416 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3418 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3419 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3420 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3421 if (!(item_flags & layer))
3422 return rte_flow_error_set(error, EINVAL,
3423 RTE_FLOW_ERROR_TYPE_ACTION,
3425 "no ipv4 item in pattern");
3431 * Validate the modify-header IPv6 address actions.
3433 * @param[in] action_flags
3434 * Holds the actions detected until now.
3436 * Pointer to the modify action.
3437 * @param[in] item_flags
3438 * Holds the items detected.
3440 * Pointer to error structure.
3443 * 0 on success, a negative errno value otherwise and rte_errno is set.
3446 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3447 const struct rte_flow_action *action,
3448 const uint64_t item_flags,
3449 struct rte_flow_error *error)
3454 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3456 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3457 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3458 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3459 if (!(item_flags & layer))
3460 return rte_flow_error_set(error, EINVAL,
3461 RTE_FLOW_ERROR_TYPE_ACTION,
3463 "no ipv6 item in pattern");
3469 * Validate the modify-header TP actions.
3471 * @param[in] action_flags
3472 * Holds the actions detected until now.
3474 * Pointer to the modify action.
3475 * @param[in] item_flags
3476 * Holds the items detected.
3478 * Pointer to error structure.
3481 * 0 on success, a negative errno value otherwise and rte_errno is set.
3484 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3485 const struct rte_flow_action *action,
3486 const uint64_t item_flags,
3487 struct rte_flow_error *error)
3492 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3494 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495 MLX5_FLOW_LAYER_INNER_L4 :
3496 MLX5_FLOW_LAYER_OUTER_L4;
3497 if (!(item_flags & layer))
3498 return rte_flow_error_set(error, EINVAL,
3499 RTE_FLOW_ERROR_TYPE_ACTION,
3500 NULL, "no transport layer "
3507 * Validate the modify-header actions of increment/decrement
3508 * TCP Sequence-number.
3510 * @param[in] action_flags
3511 * Holds the actions detected until now.
3513 * Pointer to the modify action.
3514 * @param[in] item_flags
3515 * Holds the items detected.
3517 * Pointer to error structure.
3520 * 0 on success, a negative errno value otherwise and rte_errno is set.
3523 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3524 const struct rte_flow_action *action,
3525 const uint64_t item_flags,
3526 struct rte_flow_error *error)
3531 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3533 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3534 MLX5_FLOW_LAYER_INNER_L4_TCP :
3535 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3536 if (!(item_flags & layer))
3537 return rte_flow_error_set(error, EINVAL,
3538 RTE_FLOW_ERROR_TYPE_ACTION,
3539 NULL, "no TCP item in"
3541 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3542 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3543 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3544 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3545 return rte_flow_error_set(error, EINVAL,
3546 RTE_FLOW_ERROR_TYPE_ACTION,
3548 "cannot decrease and increase"
3549 " TCP sequence number"
3550 " at the same time");
3556 * Validate the modify-header actions of increment/decrement
3557 * TCP Acknowledgment number.
3559 * @param[in] action_flags
3560 * Holds the actions detected until now.
3562 * Pointer to the modify action.
3563 * @param[in] item_flags
3564 * Holds the items detected.
3566 * Pointer to error structure.
3569 * 0 on success, a negative errno value otherwise and rte_errno is set.
3572 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3573 const struct rte_flow_action *action,
3574 const uint64_t item_flags,
3575 struct rte_flow_error *error)
3580 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3582 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3583 MLX5_FLOW_LAYER_INNER_L4_TCP :
3584 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3585 if (!(item_flags & layer))
3586 return rte_flow_error_set(error, EINVAL,
3587 RTE_FLOW_ERROR_TYPE_ACTION,
3588 NULL, "no TCP item in"
3590 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3591 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3592 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3593 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3594 return rte_flow_error_set(error, EINVAL,
3595 RTE_FLOW_ERROR_TYPE_ACTION,
3597 "cannot decrease and increase"
3598 " TCP acknowledgment number"
3599 " at the same time");
3605 * Validate the modify-header TTL actions.
3607 * @param[in] action_flags
3608 * Holds the actions detected until now.
3610 * Pointer to the modify action.
3611 * @param[in] item_flags
3612 * Holds the items detected.
3614 * Pointer to error structure.
3617 * 0 on success, a negative errno value otherwise and rte_errno is set.
3620 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3621 const struct rte_flow_action *action,
3622 const uint64_t item_flags,
3623 struct rte_flow_error *error)
3628 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3630 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3631 MLX5_FLOW_LAYER_INNER_L3 :
3632 MLX5_FLOW_LAYER_OUTER_L3;
3633 if (!(item_flags & layer))
3634 return rte_flow_error_set(error, EINVAL,
3635 RTE_FLOW_ERROR_TYPE_ACTION,
3637 "no IP protocol in pattern");
3643 * Validate jump action.
3646 * Pointer to the jump action.
3647 * @param[in] action_flags
3648 * Holds the actions detected until now.
3649 * @param[in] attributes
3650 * Pointer to flow attributes
3651 * @param[in] external
3652 * Action belongs to flow rule created by request external to PMD.
3654 * Pointer to error structure.
3657 * 0 on success, a negative errno value otherwise and rte_errno is set.
3660 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3661 uint64_t action_flags,
3662 const struct rte_flow_attr *attributes,
3663 bool external, struct rte_flow_error *error)
3665 uint32_t target_group, table;
3668 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3669 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3670 return rte_flow_error_set(error, EINVAL,
3671 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3672 "can't have 2 fate actions in"
3674 if (action_flags & MLX5_FLOW_ACTION_METER)
3675 return rte_flow_error_set(error, ENOTSUP,
3676 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3677 "jump with meter not support");
3679 return rte_flow_error_set(error, EINVAL,
3680 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3681 NULL, "action configuration not set");
3683 ((const struct rte_flow_action_jump *)action->conf)->group;
3684 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3685 true, &table, error);
3688 if (attributes->group == target_group)
3689 return rte_flow_error_set(error, EINVAL,
3690 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3691 "target group must be other than"
3692 " the current flow group");
3697 * Validate the port_id action.
3700 * Pointer to rte_eth_dev structure.
3701 * @param[in] action_flags
3702 * Bit-fields that holds the actions detected until now.
3704 * Port_id RTE action structure.
3706 * Attributes of flow that includes this action.
3708 * Pointer to error structure.
3711 * 0 on success, a negative errno value otherwise and rte_errno is set.
3714 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3715 uint64_t action_flags,
3716 const struct rte_flow_action *action,
3717 const struct rte_flow_attr *attr,
3718 struct rte_flow_error *error)
3720 const struct rte_flow_action_port_id *port_id;
3721 struct mlx5_priv *act_priv;
3722 struct mlx5_priv *dev_priv;
3725 if (!attr->transfer)
3726 return rte_flow_error_set(error, ENOTSUP,
3727 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3729 "port id action is valid in transfer"
3731 if (!action || !action->conf)
3732 return rte_flow_error_set(error, ENOTSUP,
3733 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3735 "port id action parameters must be"
3737 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3738 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3739 return rte_flow_error_set(error, EINVAL,
3740 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3741 "can have only one fate actions in"
3743 dev_priv = mlx5_dev_to_eswitch_info(dev);
3745 return rte_flow_error_set(error, rte_errno,
3746 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3748 "failed to obtain E-Switch info");
3749 port_id = action->conf;
3750 port = port_id->original ? dev->data->port_id : port_id->id;
3751 act_priv = mlx5_port_to_eswitch_info(port, false);
3753 return rte_flow_error_set
3755 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3756 "failed to obtain E-Switch port id for port");
3757 if (act_priv->domain_id != dev_priv->domain_id)
3758 return rte_flow_error_set
3760 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3761 "port does not belong to"
3762 " E-Switch being configured");
3767 * Get the maximum number of modify header actions.
3770 * Pointer to rte_eth_dev structure.
3772 * Flags bits to check if root level.
3775 * Max number of modify header actions device can support.
3777 static inline unsigned int
3778 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3782 * There's no way to directly query the max capacity from FW.
3783 * The maximal value on root table should be assumed to be supported.
3785 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3786 return MLX5_MAX_MODIFY_NUM;
3788 return MLX5_ROOT_TBL_MODIFY_NUM;
3792 * Validate the meter action.
3795 * Pointer to rte_eth_dev structure.
3796 * @param[in] action_flags
3797 * Bit-fields that holds the actions detected until now.
3799 * Pointer to the meter action.
3801 * Attributes of flow that includes this action.
3803 * Pointer to error structure.
3806 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3809 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3810 uint64_t action_flags,
3811 const struct rte_flow_action *action,
3812 const struct rte_flow_attr *attr,
3813 struct rte_flow_error *error)
3815 struct mlx5_priv *priv = dev->data->dev_private;
3816 const struct rte_flow_action_meter *am = action->conf;
3817 struct mlx5_flow_meter *fm;
3820 return rte_flow_error_set(error, EINVAL,
3821 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3822 "meter action conf is NULL");
3824 if (action_flags & MLX5_FLOW_ACTION_METER)
3825 return rte_flow_error_set(error, ENOTSUP,
3826 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3827 "meter chaining not support");
3828 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3829 return rte_flow_error_set(error, ENOTSUP,
3830 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3831 "meter with jump not support");
3833 return rte_flow_error_set(error, ENOTSUP,
3834 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3836 "meter action not supported");
3837 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3839 return rte_flow_error_set(error, EINVAL,
3840 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3842 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3843 (!fm->ingress && !attr->ingress && attr->egress) ||
3844 (!fm->egress && !attr->egress && attr->ingress))))
3845 return rte_flow_error_set(error, EINVAL,
3846 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3847 "Flow attributes are either invalid "
3848 "or have a conflict with current "
3849 "meter attributes");
3854 * Validate the age action.
3856 * @param[in] action_flags
3857 * Holds the actions detected until now.
3859 * Pointer to the age action.
3861 * Pointer to the Ethernet device structure.
3863 * Pointer to error structure.
3866 * 0 on success, a negative errno value otherwise and rte_errno is set.
3869 flow_dv_validate_action_age(uint64_t action_flags,
3870 const struct rte_flow_action *action,
3871 struct rte_eth_dev *dev,
3872 struct rte_flow_error *error)
3874 struct mlx5_priv *priv = dev->data->dev_private;
3875 const struct rte_flow_action_age *age = action->conf;
3877 if (!priv->config.devx || priv->counter_fallback)
3878 return rte_flow_error_set(error, ENOTSUP,
3879 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3881 "age action not supported");
3882 if (!(action->conf))
3883 return rte_flow_error_set(error, EINVAL,
3884 RTE_FLOW_ERROR_TYPE_ACTION, action,
3885 "configuration cannot be null");
3886 if (age->timeout >= UINT16_MAX / 2 / 10)
3887 return rte_flow_error_set(error, ENOTSUP,
3888 RTE_FLOW_ERROR_TYPE_ACTION, action,
3889 "Max age time: 3275 seconds");
3890 if (action_flags & MLX5_FLOW_ACTION_AGE)
3891 return rte_flow_error_set(error, EINVAL,
3892 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3893 "Duplicate age ctions set");
3898 * Validate the modify-header IPv4 DSCP actions.
3900 * @param[in] action_flags
3901 * Holds the actions detected until now.
3903 * Pointer to the modify action.
3904 * @param[in] item_flags
3905 * Holds the items detected.
3907 * Pointer to error structure.
3910 * 0 on success, a negative errno value otherwise and rte_errno is set.
3913 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3914 const struct rte_flow_action *action,
3915 const uint64_t item_flags,
3916 struct rte_flow_error *error)
3920 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3922 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3923 return rte_flow_error_set(error, EINVAL,
3924 RTE_FLOW_ERROR_TYPE_ACTION,
3926 "no ipv4 item in pattern");
3932 * Validate the modify-header IPv6 DSCP actions.
3934 * @param[in] action_flags
3935 * Holds the actions detected until now.
3937 * Pointer to the modify action.
3938 * @param[in] item_flags
3939 * Holds the items detected.
3941 * Pointer to error structure.
3944 * 0 on success, a negative errno value otherwise and rte_errno is set.
3947 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3948 const struct rte_flow_action *action,
3949 const uint64_t item_flags,
3950 struct rte_flow_error *error)
3954 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3956 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3957 return rte_flow_error_set(error, EINVAL,
3958 RTE_FLOW_ERROR_TYPE_ACTION,
3960 "no ipv6 item in pattern");
3966 * Find existing modify-header resource or create and register a new one.
3968 * @param dev[in, out]
3969 * Pointer to rte_eth_dev structure.
3970 * @param[in, out] resource
3971 * Pointer to modify-header resource.
3972 * @parm[in, out] dev_flow
3973 * Pointer to the dev_flow.
3975 * pointer to error structure.
3978 * 0 on success otherwise -errno and errno is set.
3981 flow_dv_modify_hdr_resource_register
3982 (struct rte_eth_dev *dev,
3983 struct mlx5_flow_dv_modify_hdr_resource *resource,
3984 struct mlx5_flow *dev_flow,
3985 struct rte_flow_error *error)
3987 struct mlx5_priv *priv = dev->data->dev_private;
3988 struct mlx5_dev_ctx_shared *sh = priv->sh;
3989 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3990 struct mlx5dv_dr_domain *ns;
3991 uint32_t actions_len;
3994 resource->flags = dev_flow->dv.group ? 0 :
3995 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3996 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3998 return rte_flow_error_set(error, EOVERFLOW,
3999 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4000 "too many modify header items");
4001 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4002 ns = sh->fdb_domain;
4003 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4007 /* Lookup a matching resource from cache. */
4008 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4009 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4010 if (resource->ft_type == cache_resource->ft_type &&
4011 resource->actions_num == cache_resource->actions_num &&
4012 resource->flags == cache_resource->flags &&
4013 !memcmp((const void *)resource->actions,
4014 (const void *)cache_resource->actions,
4016 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4017 (void *)cache_resource,
4018 rte_atomic32_read(&cache_resource->refcnt));
4019 rte_atomic32_inc(&cache_resource->refcnt);
4020 dev_flow->handle->dvh.modify_hdr = cache_resource;
4024 /* Register new modify-header resource. */
4025 cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4026 sizeof(*cache_resource) + actions_len, 0,
4028 if (!cache_resource)
4029 return rte_flow_error_set(error, ENOMEM,
4030 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4031 "cannot allocate resource memory");
4032 *cache_resource = *resource;
4033 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4034 ret = mlx5_flow_os_create_flow_action_modify_header
4035 (sh->ctx, ns, cache_resource,
4036 actions_len, &cache_resource->action);
4038 mlx5_free(cache_resource);
4039 return rte_flow_error_set(error, ENOMEM,
4040 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4041 NULL, "cannot create action");
4043 rte_atomic32_init(&cache_resource->refcnt);
4044 rte_atomic32_inc(&cache_resource->refcnt);
4045 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4046 dev_flow->handle->dvh.modify_hdr = cache_resource;
4047 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4048 (void *)cache_resource,
4049 rte_atomic32_read(&cache_resource->refcnt));
4054 * Get DV flow counter by index.
4057 * Pointer to the Ethernet device structure.
4059 * mlx5 flow counter index in the container.
4061 * mlx5 flow counter pool in the container,
4064 * Pointer to the counter, NULL otherwise.
4066 static struct mlx5_flow_counter *
4067 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4069 struct mlx5_flow_counter_pool **ppool)
4071 struct mlx5_priv *priv = dev->data->dev_private;
4072 struct mlx5_pools_container *cont;
4073 struct mlx5_flow_counter_pool *pool;
4074 uint32_t batch = 0, age = 0;
4077 age = MLX_CNT_IS_AGE(idx);
4078 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4079 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4080 idx -= MLX5_CNT_BATCH_OFFSET;
4083 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4084 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4085 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4089 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4093 * Check the devx counter belongs to the pool.
4096 * Pointer to the counter pool.
4098 * The counter devx ID.
4101 * True if counter belongs to the pool, false otherwise.
4104 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4106 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4107 MLX5_COUNTERS_PER_POOL;
4109 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4115 * Get a pool by devx counter ID.
4118 * Pointer to the counter container.
4120 * The counter devx ID.
4123 * The counter pool pointer if exists, NULL otherwise,
4125 static struct mlx5_flow_counter_pool *
4126 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4130 /* Check last used pool. */
4131 if (cont->last_pool_idx != POOL_IDX_INVALID &&
4132 flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4133 return cont->pools[cont->last_pool_idx];
4134 /* ID out of range means no suitable pool in the container. */
4135 if (id > cont->max_id || id < cont->min_id)
4138 * Find the pool from the end of the container, since mostly counter
4139 * ID is sequence increasing, and the last pool should be the needed
4142 i = rte_atomic16_read(&cont->n_valid);
4144 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4146 if (flow_dv_is_counter_in_pool(pool, id))
4153 * Allocate a new memory for the counter values wrapped by all the needed
4157 * Pointer to the Ethernet device structure.
4159 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4162 * The new memory management pointer on success, otherwise NULL and rte_errno
4165 static struct mlx5_counter_stats_mem_mng *
4166 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4168 struct mlx5_priv *priv = dev->data->dev_private;
4169 struct mlx5_dev_ctx_shared *sh = priv->sh;
4170 struct mlx5_devx_mkey_attr mkey_attr;
4171 struct mlx5_counter_stats_mem_mng *mem_mng;
4172 volatile struct flow_counter_stats *raw_data;
4173 int size = (sizeof(struct flow_counter_stats) *
4174 MLX5_COUNTERS_PER_POOL +
4175 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4176 sizeof(struct mlx5_counter_stats_mem_mng);
4177 size_t pgsize = rte_mem_page_size();
4178 if (pgsize == (size_t)-1) {
4179 DRV_LOG(ERR, "Failed to get mem page size");
4183 uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4191 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4192 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4193 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4194 IBV_ACCESS_LOCAL_WRITE);
4195 if (!mem_mng->umem) {
4200 mkey_attr.addr = (uintptr_t)mem;
4201 mkey_attr.size = size;
4202 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4203 mkey_attr.pd = sh->pdn;
4204 mkey_attr.log_entity_size = 0;
4205 mkey_attr.pg_access = 0;
4206 mkey_attr.klm_array = NULL;
4207 mkey_attr.klm_num = 0;
4208 if (priv->config.hca_attr.relaxed_ordering_write &&
4209 priv->config.hca_attr.relaxed_ordering_read &&
4210 !haswell_broadwell_cpu)
4211 mkey_attr.relaxed_ordering = 1;
4212 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4214 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4219 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4220 raw_data = (volatile struct flow_counter_stats *)mem;
4221 for (i = 0; i < raws_n; ++i) {
4222 mem_mng->raws[i].mem_mng = mem_mng;
4223 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4225 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4230 * Resize a counter container.
4233 * Pointer to the Ethernet device structure.
4235 * Whether the pool is for counter that was allocated by batch command.
4237 * Whether the pool is for Aging counter.
4240 * 0 on success, otherwise negative errno value and rte_errno is set.
4243 flow_dv_container_resize(struct rte_eth_dev *dev,
4244 uint32_t batch, uint32_t age)
4246 struct mlx5_priv *priv = dev->data->dev_private;
4247 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4249 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4250 void *old_pools = cont->pools;
4251 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4252 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4253 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4260 memcpy(pools, old_pools, cont->n *
4261 sizeof(struct mlx5_flow_counter_pool *));
4263 * Fallback mode query the counter directly, no background query
4264 * resources are needed.
4266 if (!priv->counter_fallback) {
4269 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4270 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4275 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4276 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4278 MLX5_CNT_CONTAINER_RESIZE +
4281 rte_spinlock_lock(&cont->resize_sl);
4283 cont->mem_mng = mem_mng;
4284 cont->pools = pools;
4285 rte_spinlock_unlock(&cont->resize_sl);
4287 mlx5_free(old_pools);
4292 * Query a devx flow counter.
4295 * Pointer to the Ethernet device structure.
4297 * Index to the flow counter.
4299 * The statistics value of packets.
4301 * The statistics value of bytes.
4304 * 0 on success, otherwise a negative errno value and rte_errno is set.
4307 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4310 struct mlx5_priv *priv = dev->data->dev_private;
4311 struct mlx5_flow_counter_pool *pool = NULL;
4312 struct mlx5_flow_counter *cnt;
4313 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4316 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4318 if (counter < MLX5_CNT_BATCH_OFFSET) {
4319 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4320 if (priv->counter_fallback)
4321 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4322 0, pkts, bytes, 0, NULL, NULL, 0);
4325 rte_spinlock_lock(&pool->sl);
4327 * The single counters allocation may allocate smaller ID than the
4328 * current allocated in parallel to the host reading.
4329 * In this case the new counter values must be reported as 0.
4331 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4335 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4336 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4337 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4339 rte_spinlock_unlock(&pool->sl);
4344 * Create and initialize a new counter pool.
4347 * Pointer to the Ethernet device structure.
4349 * The devX counter handle.
4351 * Whether the pool is for counter that was allocated by batch command.
4353 * Whether the pool is for counter that was allocated for aging.
4354 * @param[in/out] cont_cur
4355 * Pointer to the container pointer, it will be update in pool resize.
4358 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4360 static struct mlx5_flow_counter_pool *
4361 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4362 uint32_t batch, uint32_t age)
4364 struct mlx5_priv *priv = dev->data->dev_private;
4365 struct mlx5_flow_counter_pool *pool;
4366 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4368 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4369 uint32_t size = sizeof(*pool);
4371 if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4373 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4374 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4375 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4376 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4381 pool->min_dcs = dcs;
4382 if (!priv->counter_fallback)
4383 pool->raw = cont->mem_mng->raws + n_valid %
4384 MLX5_CNT_CONTAINER_RESIZE;
4385 pool->raw_hw = NULL;
4387 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4388 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4389 pool->query_gen = 0;
4390 rte_spinlock_init(&pool->sl);
4391 TAILQ_INIT(&pool->counters[0]);
4392 TAILQ_INIT(&pool->counters[1]);
4393 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4394 pool->index = n_valid;
4395 cont->pools[n_valid] = pool;
4397 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4399 if (base < cont->min_id)
4400 cont->min_id = base;
4401 if (base > cont->max_id)
4402 cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4403 cont->last_pool_idx = pool->index;
4405 /* Pool initialization must be updated before host thread access. */
4407 rte_atomic16_add(&cont->n_valid, 1);
4412 * Update the minimum dcs-id for aged or no-aged counter pool.
4415 * Pointer to the Ethernet device structure.
4417 * Current counter pool.
4419 * Whether the pool is for counter that was allocated by batch command.
4421 * Whether the counter is for aging.
4424 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4425 struct mlx5_flow_counter_pool *pool,
4426 uint32_t batch, uint32_t age)
4428 struct mlx5_priv *priv = dev->data->dev_private;
4429 struct mlx5_flow_counter_pool *other;
4430 struct mlx5_pools_container *cont;
4432 cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4433 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4436 if (pool->min_dcs->id < other->min_dcs->id) {
4437 rte_atomic64_set(&other->a64_dcs,
4438 rte_atomic64_read(&pool->a64_dcs));
4440 rte_atomic64_set(&pool->a64_dcs,
4441 rte_atomic64_read(&other->a64_dcs));
4445 * Prepare a new counter and/or a new counter pool.
4448 * Pointer to the Ethernet device structure.
4449 * @param[out] cnt_free
4450 * Where to put the pointer of a new counter.
4452 * Whether the pool is for counter that was allocated by batch command.
4454 * Whether the pool is for counter that was allocated for aging.
4457 * The counter pool pointer and @p cnt_free is set on success,
4458 * NULL otherwise and rte_errno is set.
4460 static struct mlx5_flow_counter_pool *
4461 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4462 struct mlx5_flow_counter **cnt_free,
4463 uint32_t batch, uint32_t age)
4465 struct mlx5_priv *priv = dev->data->dev_private;
4466 struct mlx5_pools_container *cont;
4467 struct mlx5_flow_counter_pool *pool;
4468 struct mlx5_counters tmp_tq;
4469 struct mlx5_devx_obj *dcs = NULL;
4470 struct mlx5_flow_counter *cnt;
4473 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4475 /* bulk_bitmap must be 0 for single counter allocation. */
4476 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4479 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4481 pool = flow_dv_pool_create(dev, dcs, batch, age);
4483 mlx5_devx_cmd_destroy(dcs);
4486 } else if (dcs->id < pool->min_dcs->id) {
4487 rte_atomic64_set(&pool->a64_dcs,
4488 (int64_t)(uintptr_t)dcs);
4490 flow_dv_counter_update_min_dcs(dev,
4492 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4493 cnt = MLX5_POOL_GET_CNT(pool, i);
4495 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4499 /* bulk_bitmap is in 128 counters units. */
4500 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4501 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4503 rte_errno = ENODATA;
4506 pool = flow_dv_pool_create(dev, dcs, batch, age);
4508 mlx5_devx_cmd_destroy(dcs);
4511 TAILQ_INIT(&tmp_tq);
4512 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4513 cnt = MLX5_POOL_GET_CNT(pool, i);
4515 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4517 rte_spinlock_lock(&cont->csl);
4518 TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4519 rte_spinlock_unlock(&cont->csl);
4520 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4521 (*cnt_free)->pool = pool;
4526 * Search for existed shared counter.
4529 * Pointer to the Ethernet device structure.
4531 * The shared counter ID to search.
4533 * mlx5 flow counter pool in the container,
4536 * NULL if not existed, otherwise pointer to the shared extend counter.
4538 static struct mlx5_flow_counter_ext *
4539 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4540 struct mlx5_flow_counter_pool **ppool)
4542 struct mlx5_priv *priv = dev->data->dev_private;
4543 union mlx5_l3t_data data;
4546 if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4548 cnt_idx = data.dword;
4550 * Shared counters don't have age info. The counter extend is after
4551 * the counter datat structure.
4553 return (struct mlx5_flow_counter_ext *)
4554 ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4558 * Allocate a flow counter.
4561 * Pointer to the Ethernet device structure.
4563 * Indicate if this counter is shared with other flows.
4565 * Counter identifier.
4567 * Counter flow group.
4569 * Whether the counter was allocated for aging.
4572 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4575 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4576 uint16_t group, uint32_t age)
4578 struct mlx5_priv *priv = dev->data->dev_private;
4579 struct mlx5_flow_counter_pool *pool = NULL;
4580 struct mlx5_flow_counter *cnt_free = NULL;
4581 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4583 * Currently group 0 flow counter cannot be assigned to a flow if it is
4584 * not the first one in the batch counter allocation, so it is better
4585 * to allocate counters one by one for these flows in a separate
4587 * A counter can be shared between different groups so need to take
4588 * shared counters from the single container.
4590 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4591 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4595 if (!priv->config.devx) {
4596 rte_errno = ENOTSUP;
4600 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4602 if (cnt_ext->ref_cnt + 1 == 0) {
4607 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4608 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4613 /* Get free counters from container. */
4614 rte_spinlock_lock(&cont->csl);
4615 cnt_free = TAILQ_FIRST(&cont->counters);
4617 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4618 rte_spinlock_unlock(&cont->csl);
4619 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4622 pool = cnt_free->pool;
4624 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4625 /* Create a DV counter action only in the first time usage. */
4626 if (!cnt_free->action) {
4628 struct mlx5_devx_obj *dcs;
4632 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4633 dcs = pool->min_dcs;
4638 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4645 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4646 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4647 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4648 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4649 /* Update the counter reset values. */
4650 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4654 cnt_ext->shared = shared;
4655 cnt_ext->ref_cnt = 1;
4658 union mlx5_l3t_data data;
4660 data.dword = cnt_idx;
4661 if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4665 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4666 /* Start the asynchronous batch query by the host thread. */
4667 mlx5_set_query_alarm(priv->sh);
4671 cnt_free->pool = pool;
4672 rte_spinlock_lock(&cont->csl);
4673 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4674 rte_spinlock_unlock(&cont->csl);
4680 * Get age param from counter index.
4683 * Pointer to the Ethernet device structure.
4684 * @param[in] counter
4685 * Index to the counter handler.
4688 * The aging parameter specified for the counter index.
4690 static struct mlx5_age_param*
4691 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4694 struct mlx5_flow_counter *cnt;
4695 struct mlx5_flow_counter_pool *pool = NULL;
4697 flow_dv_counter_get_by_idx(dev, counter, &pool);
4698 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4699 cnt = MLX5_POOL_GET_CNT(pool, counter);
4700 return MLX5_CNT_TO_AGE(cnt);
4704 * Remove a flow counter from aged counter list.
4707 * Pointer to the Ethernet device structure.
4708 * @param[in] counter
4709 * Index to the counter handler.
4711 * Pointer to the counter handler.
4714 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4715 uint32_t counter, struct mlx5_flow_counter *cnt)
4717 struct mlx5_age_info *age_info;
4718 struct mlx5_age_param *age_param;
4719 struct mlx5_priv *priv = dev->data->dev_private;
4721 age_info = GET_PORT_AGE_INFO(priv);
4722 age_param = flow_dv_counter_idx_get_age(dev, counter);
4723 if (rte_atomic16_cmpset((volatile uint16_t *)
4725 AGE_CANDIDATE, AGE_FREE)
4728 * We need the lock even it is age timeout,
4729 * since counter may still in process.
4731 rte_spinlock_lock(&age_info->aged_sl);
4732 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4733 rte_spinlock_unlock(&age_info->aged_sl);
4735 rte_atomic16_set(&age_param->state, AGE_FREE);
4738 * Release a flow counter.
4741 * Pointer to the Ethernet device structure.
4742 * @param[in] counter
4743 * Index to the counter handler.
4746 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4748 struct mlx5_priv *priv = dev->data->dev_private;
4749 struct mlx5_flow_counter_pool *pool = NULL;
4750 struct mlx5_flow_counter *cnt;
4751 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4755 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4757 if (counter < MLX5_CNT_BATCH_OFFSET) {
4758 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4760 if (--cnt_ext->ref_cnt)
4762 if (cnt_ext->shared)
4763 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4767 if (IS_AGE_POOL(pool))
4768 flow_dv_counter_remove_from_age(dev, counter, cnt);
4771 * Put the counter back to list to be updated in none fallback mode.
4772 * Currently, we are using two list alternately, while one is in query,
4773 * add the freed counter to the other list based on the pool query_gen
4774 * value. After query finishes, add counter the list to the global
4775 * container counter list. The list changes while query starts. In
4776 * this case, lock will not be needed as query callback and release
4777 * function both operate with the different list.
4780 if (!priv->counter_fallback)
4781 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4783 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4784 (priv->sh, 0, 0))->counters),
4789 * Verify the @p attributes will be correctly understood by the NIC and store
4790 * them in the @p flow if everything is correct.
4793 * Pointer to dev struct.
4794 * @param[in] attributes
4795 * Pointer to flow attributes
4796 * @param[in] external
4797 * This flow rule is created by request external to PMD.
4799 * Pointer to error structure.
4802 * - 0 on success and non root table.
4803 * - 1 on success and root table.
4804 * - a negative errno value otherwise and rte_errno is set.
4807 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4808 const struct rte_flow_attr *attributes,
4809 bool external __rte_unused,
4810 struct rte_flow_error *error)
4812 struct mlx5_priv *priv = dev->data->dev_private;
4813 uint32_t priority_max = priv->config.flow_prio - 1;
4816 #ifndef HAVE_MLX5DV_DR
4817 if (attributes->group)
4818 return rte_flow_error_set(error, ENOTSUP,
4819 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4821 "groups are not supported");
4825 ret = mlx5_flow_group_to_table(attributes, external,
4826 attributes->group, !!priv->fdb_def_rule,
4831 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4833 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4834 attributes->priority >= priority_max)
4835 return rte_flow_error_set(error, ENOTSUP,
4836 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4838 "priority out of range");
4839 if (attributes->transfer) {
4840 if (!priv->config.dv_esw_en)
4841 return rte_flow_error_set
4843 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4844 "E-Switch dr is not supported");
4845 if (!(priv->representor || priv->master))
4846 return rte_flow_error_set
4847 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4848 NULL, "E-Switch configuration can only be"
4849 " done by a master or a representor device");
4850 if (attributes->egress)
4851 return rte_flow_error_set
4853 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4854 "egress is not supported");
4856 if (!(attributes->egress ^ attributes->ingress))
4857 return rte_flow_error_set(error, ENOTSUP,
4858 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4859 "must specify exactly one of "
4860 "ingress or egress");
4865 * Internal validation function. For validating both actions and items.
4868 * Pointer to the rte_eth_dev structure.
4870 * Pointer to the flow attributes.
4872 * Pointer to the list of items.
4873 * @param[in] actions
4874 * Pointer to the list of actions.
4875 * @param[in] external
4876 * This flow rule is created by request external to PMD.
4877 * @param[in] hairpin
4878 * Number of hairpin TX actions, 0 means classic flow.
4880 * Pointer to the error structure.
4883 * 0 on success, a negative errno value otherwise and rte_errno is set.
4886 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4887 const struct rte_flow_item items[],
4888 const struct rte_flow_action actions[],
4889 bool external, int hairpin, struct rte_flow_error *error)
4892 uint64_t action_flags = 0;
4893 uint64_t item_flags = 0;
4894 uint64_t last_item = 0;
4895 uint8_t next_protocol = 0xff;
4896 uint16_t ether_type = 0;
4898 uint8_t item_ipv6_proto = 0;
4899 const struct rte_flow_item *gre_item = NULL;
4900 const struct rte_flow_action_raw_decap *decap;
4901 const struct rte_flow_action_raw_encap *encap;
4902 const struct rte_flow_action_rss *rss;
4903 const struct rte_flow_item_tcp nic_tcp_mask = {
4906 .src_port = RTE_BE16(UINT16_MAX),
4907 .dst_port = RTE_BE16(UINT16_MAX),
4910 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4912 .src_addr = RTE_BE32(0xffffffff),
4913 .dst_addr = RTE_BE32(0xffffffff),
4914 .type_of_service = 0xff,
4915 .next_proto_id = 0xff,
4916 .time_to_live = 0xff,
4919 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4922 "\xff\xff\xff\xff\xff\xff\xff\xff"
4923 "\xff\xff\xff\xff\xff\xff\xff\xff",
4925 "\xff\xff\xff\xff\xff\xff\xff\xff"
4926 "\xff\xff\xff\xff\xff\xff\xff\xff",
4927 .vtc_flow = RTE_BE32(0xffffffff),
4932 const struct rte_flow_item_ecpri nic_ecpri_mask = {
4936 RTE_BE32(((const struct rte_ecpri_common_hdr) {
4940 .dummy[0] = 0xffffffff,
4943 struct mlx5_priv *priv = dev->data->dev_private;
4944 struct mlx5_dev_config *dev_conf = &priv->config;
4945 uint16_t queue_index = 0xFFFF;
4946 const struct rte_flow_item_vlan *vlan_m = NULL;
4947 int16_t rw_act_num = 0;
4952 ret = flow_dv_validate_attributes(dev, attr, external, error);
4955 is_root = (uint64_t)ret;
4956 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4957 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4958 int type = items->type;
4960 if (!mlx5_flow_os_item_supported(type))
4961 return rte_flow_error_set(error, ENOTSUP,
4962 RTE_FLOW_ERROR_TYPE_ITEM,
4963 NULL, "item not supported");
4965 case RTE_FLOW_ITEM_TYPE_VOID:
4967 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4968 ret = flow_dv_validate_item_port_id
4969 (dev, items, attr, item_flags, error);
4972 last_item = MLX5_FLOW_ITEM_PORT_ID;
4974 case RTE_FLOW_ITEM_TYPE_ETH:
4975 ret = mlx5_flow_validate_item_eth(items, item_flags,
4979 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4980 MLX5_FLOW_LAYER_OUTER_L2;
4981 if (items->mask != NULL && items->spec != NULL) {
4983 ((const struct rte_flow_item_eth *)
4986 ((const struct rte_flow_item_eth *)
4988 ether_type = rte_be_to_cpu_16(ether_type);
4993 case RTE_FLOW_ITEM_TYPE_VLAN:
4994 ret = flow_dv_validate_item_vlan(items, item_flags,
4998 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4999 MLX5_FLOW_LAYER_OUTER_VLAN;
5000 if (items->mask != NULL && items->spec != NULL) {
5002 ((const struct rte_flow_item_vlan *)
5003 items->spec)->inner_type;
5005 ((const struct rte_flow_item_vlan *)
5006 items->mask)->inner_type;
5007 ether_type = rte_be_to_cpu_16(ether_type);
5011 /* Store outer VLAN mask for of_push_vlan action. */
5013 vlan_m = items->mask;
5015 case RTE_FLOW_ITEM_TYPE_IPV4:
5016 mlx5_flow_tunnel_ip_check(items, next_protocol,
5017 &item_flags, &tunnel);
5018 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5025 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5026 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5027 if (items->mask != NULL &&
5028 ((const struct rte_flow_item_ipv4 *)
5029 items->mask)->hdr.next_proto_id) {
5031 ((const struct rte_flow_item_ipv4 *)
5032 (items->spec))->hdr.next_proto_id;
5034 ((const struct rte_flow_item_ipv4 *)
5035 (items->mask))->hdr.next_proto_id;
5037 /* Reset for inner layer. */
5038 next_protocol = 0xff;
5041 case RTE_FLOW_ITEM_TYPE_IPV6:
5042 mlx5_flow_tunnel_ip_check(items, next_protocol,
5043 &item_flags, &tunnel);
5044 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5051 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5052 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5053 if (items->mask != NULL &&
5054 ((const struct rte_flow_item_ipv6 *)
5055 items->mask)->hdr.proto) {
5057 ((const struct rte_flow_item_ipv6 *)
5058 items->spec)->hdr.proto;
5060 ((const struct rte_flow_item_ipv6 *)
5061 items->spec)->hdr.proto;
5063 ((const struct rte_flow_item_ipv6 *)
5064 items->mask)->hdr.proto;
5066 /* Reset for inner layer. */
5067 next_protocol = 0xff;
5070 case RTE_FLOW_ITEM_TYPE_TCP:
5071 ret = mlx5_flow_validate_item_tcp
5078 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5079 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5081 case RTE_FLOW_ITEM_TYPE_UDP:
5082 ret = mlx5_flow_validate_item_udp(items, item_flags,
5087 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5088 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5090 case RTE_FLOW_ITEM_TYPE_GRE:
5091 ret = mlx5_flow_validate_item_gre(items, item_flags,
5092 next_protocol, error);
5096 last_item = MLX5_FLOW_LAYER_GRE;
5098 case RTE_FLOW_ITEM_TYPE_NVGRE:
5099 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5104 last_item = MLX5_FLOW_LAYER_NVGRE;
5106 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5107 ret = mlx5_flow_validate_item_gre_key
5108 (items, item_flags, gre_item, error);
5111 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5113 case RTE_FLOW_ITEM_TYPE_VXLAN:
5114 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5118 last_item = MLX5_FLOW_LAYER_VXLAN;
5120 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5121 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5126 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5128 case RTE_FLOW_ITEM_TYPE_GENEVE:
5129 ret = mlx5_flow_validate_item_geneve(items,
5134 last_item = MLX5_FLOW_LAYER_GENEVE;
5136 case RTE_FLOW_ITEM_TYPE_MPLS:
5137 ret = mlx5_flow_validate_item_mpls(dev, items,
5142 last_item = MLX5_FLOW_LAYER_MPLS;
5145 case RTE_FLOW_ITEM_TYPE_MARK:
5146 ret = flow_dv_validate_item_mark(dev, items, attr,
5150 last_item = MLX5_FLOW_ITEM_MARK;
5152 case RTE_FLOW_ITEM_TYPE_META:
5153 ret = flow_dv_validate_item_meta(dev, items, attr,
5157 last_item = MLX5_FLOW_ITEM_METADATA;
5159 case RTE_FLOW_ITEM_TYPE_ICMP:
5160 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5165 last_item = MLX5_FLOW_LAYER_ICMP;
5167 case RTE_FLOW_ITEM_TYPE_ICMP6:
5168 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5173 item_ipv6_proto = IPPROTO_ICMPV6;
5174 last_item = MLX5_FLOW_LAYER_ICMP6;
5176 case RTE_FLOW_ITEM_TYPE_TAG:
5177 ret = flow_dv_validate_item_tag(dev, items,
5181 last_item = MLX5_FLOW_ITEM_TAG;
5183 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5184 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5186 case RTE_FLOW_ITEM_TYPE_GTP:
5187 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5191 last_item = MLX5_FLOW_LAYER_GTP;
5193 case RTE_FLOW_ITEM_TYPE_ECPRI:
5194 /* Capacity will be checked in the translate stage. */
5195 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5202 last_item = MLX5_FLOW_LAYER_ECPRI;
5205 return rte_flow_error_set(error, ENOTSUP,
5206 RTE_FLOW_ERROR_TYPE_ITEM,
5207 NULL, "item not supported");
5209 item_flags |= last_item;
5211 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5212 int type = actions->type;
5214 if (!mlx5_flow_os_action_supported(type))
5215 return rte_flow_error_set(error, ENOTSUP,
5216 RTE_FLOW_ERROR_TYPE_ACTION,
5218 "action not supported");
5219 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5220 return rte_flow_error_set(error, ENOTSUP,
5221 RTE_FLOW_ERROR_TYPE_ACTION,
5222 actions, "too many actions");
5224 case RTE_FLOW_ACTION_TYPE_VOID:
5226 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5227 ret = flow_dv_validate_action_port_id(dev,
5234 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5237 case RTE_FLOW_ACTION_TYPE_FLAG:
5238 ret = flow_dv_validate_action_flag(dev, action_flags,
5242 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5243 /* Count all modify-header actions as one. */
5244 if (!(action_flags &
5245 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5247 action_flags |= MLX5_FLOW_ACTION_FLAG |
5248 MLX5_FLOW_ACTION_MARK_EXT;
5250 action_flags |= MLX5_FLOW_ACTION_FLAG;
5253 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5255 case RTE_FLOW_ACTION_TYPE_MARK:
5256 ret = flow_dv_validate_action_mark(dev, actions,
5261 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5262 /* Count all modify-header actions as one. */
5263 if (!(action_flags &
5264 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5266 action_flags |= MLX5_FLOW_ACTION_MARK |
5267 MLX5_FLOW_ACTION_MARK_EXT;
5269 action_flags |= MLX5_FLOW_ACTION_MARK;
5272 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5274 case RTE_FLOW_ACTION_TYPE_SET_META:
5275 ret = flow_dv_validate_action_set_meta(dev, actions,
5280 /* Count all modify-header actions as one action. */
5281 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5283 action_flags |= MLX5_FLOW_ACTION_SET_META;
5284 rw_act_num += MLX5_ACT_NUM_SET_META;
5286 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5287 ret = flow_dv_validate_action_set_tag(dev, actions,
5292 /* Count all modify-header actions as one action. */
5293 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5295 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5296 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5298 case RTE_FLOW_ACTION_TYPE_DROP:
5299 ret = mlx5_flow_validate_action_drop(action_flags,
5303 action_flags |= MLX5_FLOW_ACTION_DROP;
5306 case RTE_FLOW_ACTION_TYPE_QUEUE:
5307 ret = mlx5_flow_validate_action_queue(actions,
5312 queue_index = ((const struct rte_flow_action_queue *)
5313 (actions->conf))->index;
5314 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5317 case RTE_FLOW_ACTION_TYPE_RSS:
5318 rss = actions->conf;
5319 ret = mlx5_flow_validate_action_rss(actions,
5325 if (rss != NULL && rss->queue_num)
5326 queue_index = rss->queue[0];
5327 action_flags |= MLX5_FLOW_ACTION_RSS;
5330 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5332 mlx5_flow_validate_action_default_miss(action_flags,
5336 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5339 case RTE_FLOW_ACTION_TYPE_COUNT:
5340 ret = flow_dv_validate_action_count(dev, error);
5343 action_flags |= MLX5_FLOW_ACTION_COUNT;
5346 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5347 if (flow_dv_validate_action_pop_vlan(dev,
5353 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5356 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5357 ret = flow_dv_validate_action_push_vlan(dev,
5364 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5367 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5368 ret = flow_dv_validate_action_set_vlan_pcp
5369 (action_flags, actions, error);
5372 /* Count PCP with push_vlan command. */
5373 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5375 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5376 ret = flow_dv_validate_action_set_vlan_vid
5377 (item_flags, action_flags,
5381 /* Count VID with push_vlan command. */
5382 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5383 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5385 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5386 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5387 ret = flow_dv_validate_action_l2_encap(dev,
5393 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5396 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5397 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5398 ret = flow_dv_validate_action_decap(dev, action_flags,
5402 action_flags |= MLX5_FLOW_ACTION_DECAP;
5405 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5406 ret = flow_dv_validate_action_raw_encap_decap
5407 (dev, NULL, actions->conf, attr, &action_flags,
5412 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5413 decap = actions->conf;
5414 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5416 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5420 encap = actions->conf;
5422 ret = flow_dv_validate_action_raw_encap_decap
5424 decap ? decap : &empty_decap, encap,
5425 attr, &action_flags, &actions_n,
5430 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5431 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5432 ret = flow_dv_validate_action_modify_mac(action_flags,
5438 /* Count all modify-header actions as one action. */
5439 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5441 action_flags |= actions->type ==
5442 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5443 MLX5_FLOW_ACTION_SET_MAC_SRC :
5444 MLX5_FLOW_ACTION_SET_MAC_DST;
5446 * Even if the source and destination MAC addresses have
5447 * overlap in the header with 4B alignment, the convert
5448 * function will handle them separately and 4 SW actions
5449 * will be created. And 2 actions will be added each
5450 * time no matter how many bytes of address will be set.
5452 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5454 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5455 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5456 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5462 /* Count all modify-header actions as one action. */
5463 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5465 action_flags |= actions->type ==
5466 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5467 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5468 MLX5_FLOW_ACTION_SET_IPV4_DST;
5469 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5471 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5472 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5473 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5479 if (item_ipv6_proto == IPPROTO_ICMPV6)
5480 return rte_flow_error_set(error, ENOTSUP,
5481 RTE_FLOW_ERROR_TYPE_ACTION,
5483 "Can't change header "
5484 "with ICMPv6 proto");
5485 /* Count all modify-header actions as one action. */
5486 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5488 action_flags |= actions->type ==
5489 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5490 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5491 MLX5_FLOW_ACTION_SET_IPV6_DST;
5492 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5494 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5495 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5496 ret = flow_dv_validate_action_modify_tp(action_flags,
5502 /* Count all modify-header actions as one action. */
5503 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5505 action_flags |= actions->type ==
5506 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5507 MLX5_FLOW_ACTION_SET_TP_SRC :
5508 MLX5_FLOW_ACTION_SET_TP_DST;
5509 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5511 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5512 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5513 ret = flow_dv_validate_action_modify_ttl(action_flags,
5519 /* Count all modify-header actions as one action. */
5520 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5522 action_flags |= actions->type ==
5523 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5524 MLX5_FLOW_ACTION_SET_TTL :
5525 MLX5_FLOW_ACTION_DEC_TTL;
5526 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5528 case RTE_FLOW_ACTION_TYPE_JUMP:
5529 ret = flow_dv_validate_action_jump(actions,
5536 action_flags |= MLX5_FLOW_ACTION_JUMP;
5538 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5539 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5540 ret = flow_dv_validate_action_modify_tcp_seq
5547 /* Count all modify-header actions as one action. */
5548 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5550 action_flags |= actions->type ==
5551 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5552 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5553 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5554 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5556 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5557 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5558 ret = flow_dv_validate_action_modify_tcp_ack
5565 /* Count all modify-header actions as one action. */
5566 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5568 action_flags |= actions->type ==
5569 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5570 MLX5_FLOW_ACTION_INC_TCP_ACK :
5571 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5572 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5574 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5576 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5577 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5578 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5580 case RTE_FLOW_ACTION_TYPE_METER:
5581 ret = mlx5_flow_validate_action_meter(dev,
5587 action_flags |= MLX5_FLOW_ACTION_METER;
5589 /* Meter action will add one more TAG action. */
5590 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5592 case RTE_FLOW_ACTION_TYPE_AGE:
5593 ret = flow_dv_validate_action_age(action_flags,
5598 action_flags |= MLX5_FLOW_ACTION_AGE;
5601 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5602 ret = flow_dv_validate_action_modify_ipv4_dscp
5609 /* Count all modify-header actions as one action. */
5610 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5612 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5613 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5615 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5616 ret = flow_dv_validate_action_modify_ipv6_dscp
5623 /* Count all modify-header actions as one action. */
5624 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5626 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5627 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5630 return rte_flow_error_set(error, ENOTSUP,
5631 RTE_FLOW_ERROR_TYPE_ACTION,
5633 "action not supported");
5637 * Validate the drop action mutual exclusion with other actions.
5638 * Drop action is mutually-exclusive with any other action, except for
5641 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5642 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5643 return rte_flow_error_set(error, EINVAL,
5644 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5645 "Drop action is mutually-exclusive "
5646 "with any other action, except for "
5648 /* Eswitch has few restrictions on using items and actions */
5649 if (attr->transfer) {
5650 if (!mlx5_flow_ext_mreg_supported(dev) &&
5651 action_flags & MLX5_FLOW_ACTION_FLAG)
5652 return rte_flow_error_set(error, ENOTSUP,
5653 RTE_FLOW_ERROR_TYPE_ACTION,
5655 "unsupported action FLAG");
5656 if (!mlx5_flow_ext_mreg_supported(dev) &&
5657 action_flags & MLX5_FLOW_ACTION_MARK)
5658 return rte_flow_error_set(error, ENOTSUP,
5659 RTE_FLOW_ERROR_TYPE_ACTION,
5661 "unsupported action MARK");
5662 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5663 return rte_flow_error_set(error, ENOTSUP,
5664 RTE_FLOW_ERROR_TYPE_ACTION,
5666 "unsupported action QUEUE");
5667 if (action_flags & MLX5_FLOW_ACTION_RSS)
5668 return rte_flow_error_set(error, ENOTSUP,
5669 RTE_FLOW_ERROR_TYPE_ACTION,
5671 "unsupported action RSS");
5672 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5673 return rte_flow_error_set(error, EINVAL,
5674 RTE_FLOW_ERROR_TYPE_ACTION,
5676 "no fate action is found");
5678 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5679 return rte_flow_error_set(error, EINVAL,
5680 RTE_FLOW_ERROR_TYPE_ACTION,
5682 "no fate action is found");
5684 /* Continue validation for Xcap actions.*/
5685 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5686 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5687 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5688 MLX5_FLOW_XCAP_ACTIONS)
5689 return rte_flow_error_set(error, ENOTSUP,
5690 RTE_FLOW_ERROR_TYPE_ACTION,
5691 NULL, "encap and decap "
5692 "combination aren't supported");
5693 if (!attr->transfer && attr->ingress && (action_flags &
5694 MLX5_FLOW_ACTION_ENCAP))
5695 return rte_flow_error_set(error, ENOTSUP,
5696 RTE_FLOW_ERROR_TYPE_ACTION,
5697 NULL, "encap is not supported"
5698 " for ingress traffic");
5700 /* Hairpin flow will add one more TAG action. */
5702 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5703 /* extra metadata enabled: one more TAG action will be add. */
5704 if (dev_conf->dv_flow_en &&
5705 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5706 mlx5_flow_ext_mreg_supported(dev))
5707 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5708 if ((uint32_t)rw_act_num >
5709 flow_dv_modify_hdr_action_max(dev, is_root)) {
5710 return rte_flow_error_set(error, ENOTSUP,
5711 RTE_FLOW_ERROR_TYPE_ACTION,
5712 NULL, "too many header modify"
5713 " actions to support");
5719 * Internal preparation function. Allocates the DV flow size,
5720 * this size is constant.
5723 * Pointer to the rte_eth_dev structure.
5725 * Pointer to the flow attributes.
5727 * Pointer to the list of items.
5728 * @param[in] actions
5729 * Pointer to the list of actions.
5731 * Pointer to the error structure.
5734 * Pointer to mlx5_flow object on success,
5735 * otherwise NULL and rte_errno is set.
5737 static struct mlx5_flow *
5738 flow_dv_prepare(struct rte_eth_dev *dev,
5739 const struct rte_flow_attr *attr __rte_unused,
5740 const struct rte_flow_item items[] __rte_unused,
5741 const struct rte_flow_action actions[] __rte_unused,
5742 struct rte_flow_error *error)
5744 uint32_t handle_idx = 0;
5745 struct mlx5_flow *dev_flow;
5746 struct mlx5_flow_handle *dev_handle;
5747 struct mlx5_priv *priv = dev->data->dev_private;
5749 /* In case of corrupting the memory. */
5750 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5751 rte_flow_error_set(error, ENOSPC,
5752 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5753 "not free temporary device flow");
5756 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5759 rte_flow_error_set(error, ENOMEM,
5760 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5761 "not enough memory to create flow handle");
5764 /* No multi-thread supporting. */
5765 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5766 dev_flow->handle = dev_handle;
5767 dev_flow->handle_idx = handle_idx;
5769 * In some old rdma-core releases, before continuing, a check of the
5770 * length of matching parameter will be done at first. It needs to use
5771 * the length without misc4 param. If the flow has misc4 support, then
5772 * the length needs to be adjusted accordingly. Each param member is
5773 * aligned with a 64B boundary naturally.
5775 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
5776 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
5778 * The matching value needs to be cleared to 0 before using. In the
5779 * past, it will be automatically cleared when using rte_*alloc
5780 * API. The time consumption will be almost the same as before.
5782 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5783 dev_flow->ingress = attr->ingress;
5784 dev_flow->dv.transfer = attr->transfer;
5788 #ifdef RTE_LIBRTE_MLX5_DEBUG
5790 * Sanity check for match mask and value. Similar to check_valid_spec() in
5791 * kernel driver. If unmasked bit is present in value, it returns failure.
5794 * pointer to match mask buffer.
5795 * @param match_value
5796 * pointer to match value buffer.
5799 * 0 if valid, -EINVAL otherwise.
5802 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5804 uint8_t *m = match_mask;
5805 uint8_t *v = match_value;
5808 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5811 "match_value differs from match_criteria"
5812 " %p[%u] != %p[%u]",
5813 match_value, i, match_mask, i);
5822 * Add match of ip_version.
5826 * @param[in] headers_v
5827 * Values header pointer.
5828 * @param[in] headers_m
5829 * Masks header pointer.
5830 * @param[in] ip_version
5831 * The IP version to set.
5834 flow_dv_set_match_ip_version(uint32_t group,
5840 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5842 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5844 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5845 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5846 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5850 * Add Ethernet item to matcher and to the value.
5852 * @param[in, out] matcher
5854 * @param[in, out] key
5855 * Flow matcher value.
5857 * Flow pattern to translate.
5859 * Item is inner pattern.
5862 flow_dv_translate_item_eth(void *matcher, void *key,
5863 const struct rte_flow_item *item, int inner,
5866 const struct rte_flow_item_eth *eth_m = item->mask;
5867 const struct rte_flow_item_eth *eth_v = item->spec;
5868 const struct rte_flow_item_eth nic_mask = {
5869 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5870 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5871 .type = RTE_BE16(0xffff),
5883 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5885 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5887 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5889 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5891 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5892 ð_m->dst, sizeof(eth_m->dst));
5893 /* The value must be in the range of the mask. */
5894 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5895 for (i = 0; i < sizeof(eth_m->dst); ++i)
5896 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5897 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5898 ð_m->src, sizeof(eth_m->src));
5899 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5900 /* The value must be in the range of the mask. */
5901 for (i = 0; i < sizeof(eth_m->dst); ++i)
5902 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5904 /* When ethertype is present set mask for tagged VLAN. */
5905 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5906 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5907 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5908 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5909 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5911 /* Return here to avoid setting match on ethertype. */
5916 * HW supports match on one Ethertype, the Ethertype following the last
5917 * VLAN tag of the packet (see PRM).
5918 * Set match on ethertype only if ETH header is not followed by VLAN.
5919 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5920 * ethertype, and use ip_version field instead.
5921 * eCPRI over Ether layer will use type value 0xAEFE.
5923 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5924 eth_m->type == 0xFFFF) {
5925 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5926 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5927 eth_m->type == 0xFFFF) {
5928 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5930 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5931 rte_be_to_cpu_16(eth_m->type));
5932 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5934 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5939 * Add VLAN item to matcher and to the value.
5941 * @param[in, out] dev_flow
5943 * @param[in, out] matcher
5945 * @param[in, out] key
5946 * Flow matcher value.
5948 * Flow pattern to translate.
5950 * Item is inner pattern.
5953 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5954 void *matcher, void *key,
5955 const struct rte_flow_item *item,
5956 int inner, uint32_t group)
5958 const struct rte_flow_item_vlan *vlan_m = item->mask;
5959 const struct rte_flow_item_vlan *vlan_v = item->spec;
5966 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5968 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5970 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5972 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5974 * This is workaround, masks are not supported,
5975 * and pre-validated.
5978 dev_flow->handle->vf_vlan.tag =
5979 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5982 * When VLAN item exists in flow, mark packet as tagged,
5983 * even if TCI is not specified.
5985 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5990 vlan_m = &rte_flow_item_vlan_mask;
5991 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5992 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5993 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5994 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5995 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5996 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5997 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5998 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6000 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6001 * ethertype, and use ip_version field instead.
6003 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6004 vlan_m->inner_type == 0xFFFF) {
6005 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6006 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6007 vlan_m->inner_type == 0xFFFF) {
6008 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6010 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6011 rte_be_to_cpu_16(vlan_m->inner_type));
6012 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6013 rte_be_to_cpu_16(vlan_m->inner_type &
6014 vlan_v->inner_type));
6019 * Add IPV4 item to matcher and to the value.
6021 * @param[in, out] matcher
6023 * @param[in, out] key
6024 * Flow matcher value.
6026 * Flow pattern to translate.
6027 * @param[in] item_flags
6028 * Bit-fields that holds the items detected until now.
6030 * Item is inner pattern.
6032 * The group to insert the rule.
6035 flow_dv_translate_item_ipv4(void *matcher, void *key,
6036 const struct rte_flow_item *item,
6037 const uint64_t item_flags,
6038 int inner, uint32_t group)
6040 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6041 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6042 const struct rte_flow_item_ipv4 nic_mask = {
6044 .src_addr = RTE_BE32(0xffffffff),
6045 .dst_addr = RTE_BE32(0xffffffff),
6046 .type_of_service = 0xff,
6047 .next_proto_id = 0xff,
6048 .time_to_live = 0xff,
6058 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6060 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6062 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6064 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6066 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6068 * On outer header (which must contains L2), or inner header with L2,
6069 * set cvlan_tag mask bit to mark this packet as untagged.
6070 * This should be done even if item->spec is empty.
6072 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6073 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6078 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6079 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6080 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6081 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6082 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6083 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6084 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6085 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6086 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6087 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6088 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6089 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6090 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6091 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6092 ipv4_m->hdr.type_of_service);
6093 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6094 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6095 ipv4_m->hdr.type_of_service >> 2);
6096 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6097 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6098 ipv4_m->hdr.next_proto_id);
6099 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6100 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6101 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6102 ipv4_m->hdr.time_to_live);
6103 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6104 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6108 * Add IPV6 item to matcher and to the value.
6110 * @param[in, out] matcher
6112 * @param[in, out] key
6113 * Flow matcher value.
6115 * Flow pattern to translate.
6116 * @param[in] item_flags
6117 * Bit-fields that holds the items detected until now.
6119 * Item is inner pattern.
6121 * The group to insert the rule.
6124 flow_dv_translate_item_ipv6(void *matcher, void *key,
6125 const struct rte_flow_item *item,
6126 const uint64_t item_flags,
6127 int inner, uint32_t group)
6129 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6130 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6131 const struct rte_flow_item_ipv6 nic_mask = {
6134 "\xff\xff\xff\xff\xff\xff\xff\xff"
6135 "\xff\xff\xff\xff\xff\xff\xff\xff",
6137 "\xff\xff\xff\xff\xff\xff\xff\xff"
6138 "\xff\xff\xff\xff\xff\xff\xff\xff",
6139 .vtc_flow = RTE_BE32(0xffffffff),
6146 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6147 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6156 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6158 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6160 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6162 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6164 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6166 * On outer header (which must contains L2), or inner header with L2,
6167 * set cvlan_tag mask bit to mark this packet as untagged.
6168 * This should be done even if item->spec is empty.
6170 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6176 size = sizeof(ipv6_m->hdr.dst_addr);
6177 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6178 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6179 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6180 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6181 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6182 for (i = 0; i < size; ++i)
6183 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6184 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6185 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6186 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6187 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6188 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6189 for (i = 0; i < size; ++i)
6190 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6192 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6193 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6194 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6195 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6196 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6197 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6200 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6202 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6205 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6207 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6211 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6213 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6214 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6217 ipv6_m->hdr.hop_limits);
6218 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6219 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6223 * Add TCP item to matcher and to the value.
6225 * @param[in, out] matcher
6227 * @param[in, out] key
6228 * Flow matcher value.
6230 * Flow pattern to translate.
6232 * Item is inner pattern.
6235 flow_dv_translate_item_tcp(void *matcher, void *key,
6236 const struct rte_flow_item *item,
6239 const struct rte_flow_item_tcp *tcp_m = item->mask;
6240 const struct rte_flow_item_tcp *tcp_v = item->spec;
6245 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6247 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6249 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6251 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6253 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6254 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6258 tcp_m = &rte_flow_item_tcp_mask;
6259 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6260 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6261 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6262 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6263 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6264 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6265 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6266 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6268 tcp_m->hdr.tcp_flags);
6269 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6270 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6274 * Add UDP item to matcher and to the value.
6276 * @param[in, out] matcher
6278 * @param[in, out] key
6279 * Flow matcher value.
6281 * Flow pattern to translate.
6283 * Item is inner pattern.
6286 flow_dv_translate_item_udp(void *matcher, void *key,
6287 const struct rte_flow_item *item,
6290 const struct rte_flow_item_udp *udp_m = item->mask;
6291 const struct rte_flow_item_udp *udp_v = item->spec;
6296 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6298 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6300 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6302 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6304 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6305 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6309 udp_m = &rte_flow_item_udp_mask;
6310 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6311 rte_be_to_cpu_16(udp_m->hdr.src_port));
6312 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6313 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6314 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6315 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6316 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6317 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6321 * Add GRE optional Key item to matcher and to the value.
6323 * @param[in, out] matcher
6325 * @param[in, out] key
6326 * Flow matcher value.
6328 * Flow pattern to translate.
6330 * Item is inner pattern.
6333 flow_dv_translate_item_gre_key(void *matcher, void *key,
6334 const struct rte_flow_item *item)
6336 const rte_be32_t *key_m = item->mask;
6337 const rte_be32_t *key_v = item->spec;
6338 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6339 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6340 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6342 /* GRE K bit must be on and should already be validated */
6343 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6344 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6348 key_m = &gre_key_default_mask;
6349 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6350 rte_be_to_cpu_32(*key_m) >> 8);
6351 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6352 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6353 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6354 rte_be_to_cpu_32(*key_m) & 0xFF);
6355 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6356 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6360 * Add GRE item to matcher and to the value.
6362 * @param[in, out] matcher
6364 * @param[in, out] key
6365 * Flow matcher value.
6367 * Flow pattern to translate.
6369 * Item is inner pattern.
6372 flow_dv_translate_item_gre(void *matcher, void *key,
6373 const struct rte_flow_item *item,
6376 const struct rte_flow_item_gre *gre_m = item->mask;
6377 const struct rte_flow_item_gre *gre_v = item->spec;
6380 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6381 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6388 uint16_t s_present:1;
6389 uint16_t k_present:1;
6390 uint16_t rsvd_bit1:1;
6391 uint16_t c_present:1;
6395 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6398 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6400 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6402 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6404 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6406 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6411 gre_m = &rte_flow_item_gre_mask;
6412 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6413 rte_be_to_cpu_16(gre_m->protocol));
6414 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6415 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6416 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6417 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6418 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6419 gre_crks_rsvd0_ver_m.c_present);
6420 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6421 gre_crks_rsvd0_ver_v.c_present &
6422 gre_crks_rsvd0_ver_m.c_present);
6423 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6424 gre_crks_rsvd0_ver_m.k_present);
6425 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6426 gre_crks_rsvd0_ver_v.k_present &
6427 gre_crks_rsvd0_ver_m.k_present);
6428 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6429 gre_crks_rsvd0_ver_m.s_present);
6430 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6431 gre_crks_rsvd0_ver_v.s_present &
6432 gre_crks_rsvd0_ver_m.s_present);
6436 * Add NVGRE item to matcher and to the value.
6438 * @param[in, out] matcher
6440 * @param[in, out] key
6441 * Flow matcher value.
6443 * Flow pattern to translate.
6445 * Item is inner pattern.
6448 flow_dv_translate_item_nvgre(void *matcher, void *key,
6449 const struct rte_flow_item *item,
6452 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6453 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6454 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6455 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6456 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6457 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6463 /* For NVGRE, GRE header fields must be set with defined values. */
6464 const struct rte_flow_item_gre gre_spec = {
6465 .c_rsvd0_ver = RTE_BE16(0x2000),
6466 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6468 const struct rte_flow_item_gre gre_mask = {
6469 .c_rsvd0_ver = RTE_BE16(0xB000),
6470 .protocol = RTE_BE16(UINT16_MAX),
6472 const struct rte_flow_item gre_item = {
6477 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6481 nvgre_m = &rte_flow_item_nvgre_mask;
6482 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6483 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6484 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6485 memcpy(gre_key_m, tni_flow_id_m, size);
6486 for (i = 0; i < size; ++i)
6487 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6491 * Add VXLAN item to matcher and to the value.
6493 * @param[in, out] matcher
6495 * @param[in, out] key
6496 * Flow matcher value.
6498 * Flow pattern to translate.
6500 * Item is inner pattern.
6503 flow_dv_translate_item_vxlan(void *matcher, void *key,
6504 const struct rte_flow_item *item,
6507 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6508 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6511 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6512 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6520 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6522 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6524 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6526 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6528 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6529 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6530 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6531 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6537 vxlan_m = &rte_flow_item_vxlan_mask;
6538 size = sizeof(vxlan_m->vni);
6539 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6540 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6541 memcpy(vni_m, vxlan_m->vni, size);
6542 for (i = 0; i < size; ++i)
6543 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6547 * Add VXLAN-GPE item to matcher and to the value.
6549 * @param[in, out] matcher
6551 * @param[in, out] key
6552 * Flow matcher value.
6554 * Flow pattern to translate.
6556 * Item is inner pattern.
6560 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6561 const struct rte_flow_item *item, int inner)
6563 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6564 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6568 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6570 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6576 uint8_t flags_m = 0xff;
6577 uint8_t flags_v = 0xc;
6580 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6582 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6584 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6586 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6588 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6589 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6590 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6591 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6592 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6597 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6598 size = sizeof(vxlan_m->vni);
6599 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6600 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6601 memcpy(vni_m, vxlan_m->vni, size);
6602 for (i = 0; i < size; ++i)
6603 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6604 if (vxlan_m->flags) {
6605 flags_m = vxlan_m->flags;
6606 flags_v = vxlan_v->flags;
6608 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6609 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6610 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6612 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6617 * Add Geneve item to matcher and to the value.
6619 * @param[in, out] matcher
6621 * @param[in, out] key
6622 * Flow matcher value.
6624 * Flow pattern to translate.
6626 * Item is inner pattern.
6630 flow_dv_translate_item_geneve(void *matcher, void *key,
6631 const struct rte_flow_item *item, int inner)
6633 const struct rte_flow_item_geneve *geneve_m = item->mask;
6634 const struct rte_flow_item_geneve *geneve_v = item->spec;
6637 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6638 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6647 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6649 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6651 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6653 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6655 dport = MLX5_UDP_PORT_GENEVE;
6656 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6657 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6663 geneve_m = &rte_flow_item_geneve_mask;
6664 size = sizeof(geneve_m->vni);
6665 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6666 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6667 memcpy(vni_m, geneve_m->vni, size);
6668 for (i = 0; i < size; ++i)
6669 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6670 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6671 rte_be_to_cpu_16(geneve_m->protocol));
6672 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6673 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6674 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6675 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6676 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6677 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6678 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6679 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6680 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6681 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6682 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6683 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6684 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6688 * Add MPLS item to matcher and to the value.
6690 * @param[in, out] matcher
6692 * @param[in, out] key
6693 * Flow matcher value.
6695 * Flow pattern to translate.
6696 * @param[in] prev_layer
6697 * The protocol layer indicated in previous item.
6699 * Item is inner pattern.
6702 flow_dv_translate_item_mpls(void *matcher, void *key,
6703 const struct rte_flow_item *item,
6704 uint64_t prev_layer,
6707 const uint32_t *in_mpls_m = item->mask;
6708 const uint32_t *in_mpls_v = item->spec;
6709 uint32_t *out_mpls_m = 0;
6710 uint32_t *out_mpls_v = 0;
6711 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6712 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6713 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6715 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6716 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6717 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6719 switch (prev_layer) {
6720 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6721 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6722 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6723 MLX5_UDP_PORT_MPLS);
6725 case MLX5_FLOW_LAYER_GRE:
6726 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6727 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6728 RTE_ETHER_TYPE_MPLS);
6731 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6739 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6740 switch (prev_layer) {
6741 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6743 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6744 outer_first_mpls_over_udp);
6746 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6747 outer_first_mpls_over_udp);
6749 case MLX5_FLOW_LAYER_GRE:
6751 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6752 outer_first_mpls_over_gre);
6754 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6755 outer_first_mpls_over_gre);
6758 /* Inner MPLS not over GRE is not supported. */
6761 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6765 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6771 if (out_mpls_m && out_mpls_v) {
6772 *out_mpls_m = *in_mpls_m;
6773 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6778 * Add metadata register item to matcher
6780 * @param[in, out] matcher
6782 * @param[in, out] key
6783 * Flow matcher value.
6784 * @param[in] reg_type
6785 * Type of device metadata register
6792 flow_dv_match_meta_reg(void *matcher, void *key,
6793 enum modify_reg reg_type,
6794 uint32_t data, uint32_t mask)
6797 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6799 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6805 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6806 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6809 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6810 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6814 * The metadata register C0 field might be divided into
6815 * source vport index and META item value, we should set
6816 * this field according to specified mask, not as whole one.
6818 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6820 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6821 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6824 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6827 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6828 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6831 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6832 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6835 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6836 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6839 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6840 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6843 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6844 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6847 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6848 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6851 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6852 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6861 * Add MARK item to matcher
6864 * The device to configure through.
6865 * @param[in, out] matcher
6867 * @param[in, out] key
6868 * Flow matcher value.
6870 * Flow pattern to translate.
6873 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6874 void *matcher, void *key,
6875 const struct rte_flow_item *item)
6877 struct mlx5_priv *priv = dev->data->dev_private;
6878 const struct rte_flow_item_mark *mark;
6882 mark = item->mask ? (const void *)item->mask :
6883 &rte_flow_item_mark_mask;
6884 mask = mark->id & priv->sh->dv_mark_mask;
6885 mark = (const void *)item->spec;
6887 value = mark->id & priv->sh->dv_mark_mask & mask;
6889 enum modify_reg reg;
6891 /* Get the metadata register index for the mark. */
6892 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6893 MLX5_ASSERT(reg > 0);
6894 if (reg == REG_C_0) {
6895 struct mlx5_priv *priv = dev->data->dev_private;
6896 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6897 uint32_t shl_c0 = rte_bsf32(msk_c0);
6903 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6908 * Add META item to matcher
6911 * The devich to configure through.
6912 * @param[in, out] matcher
6914 * @param[in, out] key
6915 * Flow matcher value.
6917 * Attributes of flow that includes this item.
6919 * Flow pattern to translate.
6922 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6923 void *matcher, void *key,
6924 const struct rte_flow_attr *attr,
6925 const struct rte_flow_item *item)
6927 const struct rte_flow_item_meta *meta_m;
6928 const struct rte_flow_item_meta *meta_v;
6930 meta_m = (const void *)item->mask;
6932 meta_m = &rte_flow_item_meta_mask;
6933 meta_v = (const void *)item->spec;
6936 uint32_t value = meta_v->data;
6937 uint32_t mask = meta_m->data;
6939 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6943 * In datapath code there is no endianness
6944 * coversions for perfromance reasons, all
6945 * pattern conversions are done in rte_flow.
6947 value = rte_cpu_to_be_32(value);
6948 mask = rte_cpu_to_be_32(mask);
6949 if (reg == REG_C_0) {
6950 struct mlx5_priv *priv = dev->data->dev_private;
6951 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6952 uint32_t shl_c0 = rte_bsf32(msk_c0);
6953 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6954 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6961 MLX5_ASSERT(msk_c0);
6962 MLX5_ASSERT(!(~msk_c0 & mask));
6964 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6969 * Add vport metadata Reg C0 item to matcher
6971 * @param[in, out] matcher
6973 * @param[in, out] key
6974 * Flow matcher value.
6976 * Flow pattern to translate.
6979 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6980 uint32_t value, uint32_t mask)
6982 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6986 * Add tag item to matcher
6989 * The devich to configure through.
6990 * @param[in, out] matcher
6992 * @param[in, out] key
6993 * Flow matcher value.
6995 * Flow pattern to translate.
6998 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6999 void *matcher, void *key,
7000 const struct rte_flow_item *item)
7002 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7003 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7004 uint32_t mask, value;
7007 value = tag_v->data;
7008 mask = tag_m ? tag_m->data : UINT32_MAX;
7009 if (tag_v->id == REG_C_0) {
7010 struct mlx5_priv *priv = dev->data->dev_private;
7011 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7012 uint32_t shl_c0 = rte_bsf32(msk_c0);
7018 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7022 * Add TAG item to matcher
7025 * The devich to configure through.
7026 * @param[in, out] matcher
7028 * @param[in, out] key
7029 * Flow matcher value.
7031 * Flow pattern to translate.
7034 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7035 void *matcher, void *key,
7036 const struct rte_flow_item *item)
7038 const struct rte_flow_item_tag *tag_v = item->spec;
7039 const struct rte_flow_item_tag *tag_m = item->mask;
7040 enum modify_reg reg;
7043 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7044 /* Get the metadata register index for the tag. */
7045 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7046 MLX5_ASSERT(reg > 0);
7047 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7051 * Add source vport match to the specified matcher.
7053 * @param[in, out] matcher
7055 * @param[in, out] key
7056 * Flow matcher value.
7058 * Source vport value to match
7063 flow_dv_translate_item_source_vport(void *matcher, void *key,
7064 int16_t port, uint16_t mask)
7066 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7067 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7069 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7070 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7074 * Translate port-id item to eswitch match on port-id.
7077 * The devich to configure through.
7078 * @param[in, out] matcher
7080 * @param[in, out] key
7081 * Flow matcher value.
7083 * Flow pattern to translate.
7086 * 0 on success, a negative errno value otherwise.
7089 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7090 void *key, const struct rte_flow_item *item)
7092 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7093 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7094 struct mlx5_priv *priv;
7097 mask = pid_m ? pid_m->id : 0xffff;
7098 id = pid_v ? pid_v->id : dev->data->port_id;
7099 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7102 /* Translate to vport field or to metadata, depending on mode. */
7103 if (priv->vport_meta_mask)
7104 flow_dv_translate_item_meta_vport(matcher, key,
7105 priv->vport_meta_tag,
7106 priv->vport_meta_mask);
7108 flow_dv_translate_item_source_vport(matcher, key,
7109 priv->vport_id, mask);
7114 * Add ICMP6 item to matcher and to the value.
7116 * @param[in, out] matcher
7118 * @param[in, out] key
7119 * Flow matcher value.
7121 * Flow pattern to translate.
7123 * Item is inner pattern.
7126 flow_dv_translate_item_icmp6(void *matcher, void *key,
7127 const struct rte_flow_item *item,
7130 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7131 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7134 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7136 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7138 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7140 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7142 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7144 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7146 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7147 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7151 icmp6_m = &rte_flow_item_icmp6_mask;
7153 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7154 * If only the protocol is specified, no need to match the frag.
7156 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7157 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7158 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7159 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7160 icmp6_v->type & icmp6_m->type);
7161 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7162 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7163 icmp6_v->code & icmp6_m->code);
7167 * Add ICMP item to matcher and to the value.
7169 * @param[in, out] matcher
7171 * @param[in, out] key
7172 * Flow matcher value.
7174 * Flow pattern to translate.
7176 * Item is inner pattern.
7179 flow_dv_translate_item_icmp(void *matcher, void *key,
7180 const struct rte_flow_item *item,
7183 const struct rte_flow_item_icmp *icmp_m = item->mask;
7184 const struct rte_flow_item_icmp *icmp_v = item->spec;
7187 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7189 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7191 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7193 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7195 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7197 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7199 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7200 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7204 icmp_m = &rte_flow_item_icmp_mask;
7206 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7207 * If only the protocol is specified, no need to match the frag.
7209 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7210 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7211 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7212 icmp_m->hdr.icmp_type);
7213 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7214 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7215 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7216 icmp_m->hdr.icmp_code);
7217 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7218 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7222 * Add GTP item to matcher and to the value.
7224 * @param[in, out] matcher
7226 * @param[in, out] key
7227 * Flow matcher value.
7229 * Flow pattern to translate.
7231 * Item is inner pattern.
7234 flow_dv_translate_item_gtp(void *matcher, void *key,
7235 const struct rte_flow_item *item, int inner)
7237 const struct rte_flow_item_gtp *gtp_m = item->mask;
7238 const struct rte_flow_item_gtp *gtp_v = item->spec;
7241 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7243 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7244 uint16_t dport = RTE_GTPU_UDP_PORT;
7247 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7249 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7251 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7253 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7255 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7256 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7257 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7262 gtp_m = &rte_flow_item_gtp_mask;
7263 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7264 gtp_m->v_pt_rsv_flags);
7265 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7266 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7267 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7268 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7269 gtp_v->msg_type & gtp_m->msg_type);
7270 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7271 rte_be_to_cpu_32(gtp_m->teid));
7272 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7273 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7277 * Add eCPRI item to matcher and to the value.
7280 * The devich to configure through.
7281 * @param[in, out] matcher
7283 * @param[in, out] key
7284 * Flow matcher value.
7286 * Flow pattern to translate.
7287 * @param[in] samples
7288 * Sample IDs to be used in the matching.
7291 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7292 void *key, const struct rte_flow_item *item)
7294 struct mlx5_priv *priv = dev->data->dev_private;
7295 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7296 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7297 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7299 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7307 ecpri_m = &rte_flow_item_ecpri_mask;
7309 * Maximal four DW samples are supported in a single matching now.
7310 * Two are used now for a eCPRI matching:
7311 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7312 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7315 if (!ecpri_m->hdr.common.u32)
7317 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7318 /* Need to take the whole DW as the mask to fill the entry. */
7319 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7320 prog_sample_field_value_0);
7321 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7322 prog_sample_field_value_0);
7323 /* Already big endian (network order) in the header. */
7324 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7325 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7326 /* Sample#0, used for matching type, offset 0. */
7327 MLX5_SET(fte_match_set_misc4, misc4_m,
7328 prog_sample_field_id_0, samples[0]);
7329 /* It makes no sense to set the sample ID in the mask field. */
7330 MLX5_SET(fte_match_set_misc4, misc4_v,
7331 prog_sample_field_id_0, samples[0]);
7333 * Checking if message body part needs to be matched.
7334 * Some wildcard rules only matching type field should be supported.
7336 if (ecpri_m->hdr.dummy[0]) {
7337 switch (ecpri_v->hdr.common.type) {
7338 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7339 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7340 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7341 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7342 prog_sample_field_value_1);
7343 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7344 prog_sample_field_value_1);
7345 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7346 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7347 /* Sample#1, to match message body, offset 4. */
7348 MLX5_SET(fte_match_set_misc4, misc4_m,
7349 prog_sample_field_id_1, samples[1]);
7350 MLX5_SET(fte_match_set_misc4, misc4_v,
7351 prog_sample_field_id_1, samples[1]);
7354 /* Others, do not match any sample ID. */
7360 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7362 #define HEADER_IS_ZERO(match_criteria, headers) \
7363 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7364 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7367 * Calculate flow matcher enable bitmap.
7369 * @param match_criteria
7370 * Pointer to flow matcher criteria.
7373 * Bitmap of enabled fields.
7376 flow_dv_matcher_enable(uint32_t *match_criteria)
7378 uint8_t match_criteria_enable;
7380 match_criteria_enable =
7381 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7382 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7383 match_criteria_enable |=
7384 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7385 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7386 match_criteria_enable |=
7387 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7388 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7389 match_criteria_enable |=
7390 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7391 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7392 match_criteria_enable |=
7393 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7394 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7395 match_criteria_enable |=
7396 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7397 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7398 return match_criteria_enable;
7405 * @param[in, out] dev
7406 * Pointer to rte_eth_dev structure.
7407 * @param[in] table_id
7410 * Direction of the table.
7411 * @param[in] transfer
7412 * E-Switch or NIC flow.
7414 * pointer to error structure.
7417 * Returns tables resource based on the index, NULL in case of failed.
7419 static struct mlx5_flow_tbl_resource *
7420 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7421 uint32_t table_id, uint8_t egress,
7423 struct rte_flow_error *error)
7425 struct mlx5_priv *priv = dev->data->dev_private;
7426 struct mlx5_dev_ctx_shared *sh = priv->sh;
7427 struct mlx5_flow_tbl_resource *tbl;
7428 union mlx5_flow_tbl_key table_key = {
7430 .table_id = table_id,
7432 .domain = !!transfer,
7433 .direction = !!egress,
7436 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7438 struct mlx5_flow_tbl_data_entry *tbl_data;
7444 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7446 tbl = &tbl_data->tbl;
7447 rte_atomic32_inc(&tbl->refcnt);
7450 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7452 rte_flow_error_set(error, ENOMEM,
7453 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7455 "cannot allocate flow table data entry");
7458 tbl_data->idx = idx;
7459 tbl = &tbl_data->tbl;
7460 pos = &tbl_data->entry;
7462 domain = sh->fdb_domain;
7464 domain = sh->tx_domain;
7466 domain = sh->rx_domain;
7467 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7469 rte_flow_error_set(error, ENOMEM,
7470 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7471 NULL, "cannot create flow table object");
7472 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7476 * No multi-threads now, but still better to initialize the reference
7477 * count before insert it into the hash list.
7479 rte_atomic32_init(&tbl->refcnt);
7480 /* Jump action reference count is initialized here. */
7481 rte_atomic32_init(&tbl_data->jump.refcnt);
7482 pos->key = table_key.v64;
7483 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7485 rte_flow_error_set(error, -ret,
7486 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7487 "cannot insert flow table data entry");
7488 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7489 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7491 rte_atomic32_inc(&tbl->refcnt);
7496 * Release a flow table.
7499 * Pointer to rte_eth_dev structure.
7501 * Table resource to be released.
7504 * Returns 0 if table was released, else return 1;
7507 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7508 struct mlx5_flow_tbl_resource *tbl)
7510 struct mlx5_priv *priv = dev->data->dev_private;
7511 struct mlx5_dev_ctx_shared *sh = priv->sh;
7512 struct mlx5_flow_tbl_data_entry *tbl_data =
7513 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7517 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7518 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7520 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7522 /* remove the entry from the hash list and free memory. */
7523 mlx5_hlist_remove(sh->flow_tbls, pos);
7524 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7532 * Register the flow matcher.
7534 * @param[in, out] dev
7535 * Pointer to rte_eth_dev structure.
7536 * @param[in, out] matcher
7537 * Pointer to flow matcher.
7538 * @param[in, out] key
7539 * Pointer to flow table key.
7540 * @parm[in, out] dev_flow
7541 * Pointer to the dev_flow.
7543 * pointer to error structure.
7546 * 0 on success otherwise -errno and errno is set.
7549 flow_dv_matcher_register(struct rte_eth_dev *dev,
7550 struct mlx5_flow_dv_matcher *matcher,
7551 union mlx5_flow_tbl_key *key,
7552 struct mlx5_flow *dev_flow,
7553 struct rte_flow_error *error)
7555 struct mlx5_priv *priv = dev->data->dev_private;
7556 struct mlx5_dev_ctx_shared *sh = priv->sh;
7557 struct mlx5_flow_dv_matcher *cache_matcher;
7558 struct mlx5dv_flow_matcher_attr dv_attr = {
7559 .type = IBV_FLOW_ATTR_NORMAL,
7560 .match_mask = (void *)&matcher->mask,
7562 struct mlx5_flow_tbl_resource *tbl;
7563 struct mlx5_flow_tbl_data_entry *tbl_data;
7566 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7567 key->domain, error);
7569 return -rte_errno; /* No need to refill the error info */
7570 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7571 /* Lookup from cache. */
7572 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7573 if (matcher->crc == cache_matcher->crc &&
7574 matcher->priority == cache_matcher->priority &&
7575 !memcmp((const void *)matcher->mask.buf,
7576 (const void *)cache_matcher->mask.buf,
7577 cache_matcher->mask.size)) {
7579 "%s group %u priority %hd use %s "
7580 "matcher %p: refcnt %d++",
7581 key->domain ? "FDB" : "NIC", key->table_id,
7582 cache_matcher->priority,
7583 key->direction ? "tx" : "rx",
7584 (void *)cache_matcher,
7585 rte_atomic32_read(&cache_matcher->refcnt));
7586 rte_atomic32_inc(&cache_matcher->refcnt);
7587 dev_flow->handle->dvh.matcher = cache_matcher;
7588 /* old matcher should not make the table ref++. */
7589 flow_dv_tbl_resource_release(dev, tbl);
7593 /* Register new matcher. */
7594 cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7596 if (!cache_matcher) {
7597 flow_dv_tbl_resource_release(dev, tbl);
7598 return rte_flow_error_set(error, ENOMEM,
7599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7600 "cannot allocate matcher memory");
7602 *cache_matcher = *matcher;
7603 dv_attr.match_criteria_enable =
7604 flow_dv_matcher_enable(cache_matcher->mask.buf);
7605 dv_attr.priority = matcher->priority;
7607 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7608 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7609 &cache_matcher->matcher_object);
7611 mlx5_free(cache_matcher);
7612 #ifdef HAVE_MLX5DV_DR
7613 flow_dv_tbl_resource_release(dev, tbl);
7615 return rte_flow_error_set(error, ENOMEM,
7616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7617 NULL, "cannot create matcher");
7619 /* Save the table information */
7620 cache_matcher->tbl = tbl;
7621 rte_atomic32_init(&cache_matcher->refcnt);
7622 /* only matcher ref++, table ref++ already done above in get API. */
7623 rte_atomic32_inc(&cache_matcher->refcnt);
7624 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7625 dev_flow->handle->dvh.matcher = cache_matcher;
7626 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7627 key->domain ? "FDB" : "NIC", key->table_id,
7628 cache_matcher->priority,
7629 key->direction ? "tx" : "rx", (void *)cache_matcher,
7630 rte_atomic32_read(&cache_matcher->refcnt));
7635 * Find existing tag resource or create and register a new one.
7637 * @param dev[in, out]
7638 * Pointer to rte_eth_dev structure.
7639 * @param[in, out] tag_be24
7640 * Tag value in big endian then R-shift 8.
7641 * @parm[in, out] dev_flow
7642 * Pointer to the dev_flow.
7644 * pointer to error structure.
7647 * 0 on success otherwise -errno and errno is set.
7650 flow_dv_tag_resource_register
7651 (struct rte_eth_dev *dev,
7653 struct mlx5_flow *dev_flow,
7654 struct rte_flow_error *error)
7656 struct mlx5_priv *priv = dev->data->dev_private;
7657 struct mlx5_dev_ctx_shared *sh = priv->sh;
7658 struct mlx5_flow_dv_tag_resource *cache_resource;
7659 struct mlx5_hlist_entry *entry;
7662 /* Lookup a matching resource from cache. */
7663 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7665 cache_resource = container_of
7666 (entry, struct mlx5_flow_dv_tag_resource, entry);
7667 rte_atomic32_inc(&cache_resource->refcnt);
7668 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7669 dev_flow->dv.tag_resource = cache_resource;
7670 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7671 (void *)cache_resource,
7672 rte_atomic32_read(&cache_resource->refcnt));
7675 /* Register new resource. */
7676 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7677 &dev_flow->handle->dvh.rix_tag);
7678 if (!cache_resource)
7679 return rte_flow_error_set(error, ENOMEM,
7680 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7681 "cannot allocate resource memory");
7682 cache_resource->entry.key = (uint64_t)tag_be24;
7683 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7684 &cache_resource->action);
7686 mlx5_free(cache_resource);
7687 return rte_flow_error_set(error, ENOMEM,
7688 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7689 NULL, "cannot create action");
7691 rte_atomic32_init(&cache_resource->refcnt);
7692 rte_atomic32_inc(&cache_resource->refcnt);
7693 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7694 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7695 mlx5_free(cache_resource);
7696 return rte_flow_error_set(error, EEXIST,
7697 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7698 NULL, "cannot insert tag");
7700 dev_flow->dv.tag_resource = cache_resource;
7701 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7702 (void *)cache_resource,
7703 rte_atomic32_read(&cache_resource->refcnt));
7711 * Pointer to Ethernet device.
7716 * 1 while a reference on it exists, 0 when freed.
7719 flow_dv_tag_release(struct rte_eth_dev *dev,
7722 struct mlx5_priv *priv = dev->data->dev_private;
7723 struct mlx5_dev_ctx_shared *sh = priv->sh;
7724 struct mlx5_flow_dv_tag_resource *tag;
7726 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7729 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7730 dev->data->port_id, (void *)tag,
7731 rte_atomic32_read(&tag->refcnt));
7732 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7733 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7734 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7735 DRV_LOG(DEBUG, "port %u tag %p: removed",
7736 dev->data->port_id, (void *)tag);
7737 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7744 * Translate port ID action to vport.
7747 * Pointer to rte_eth_dev structure.
7749 * Pointer to the port ID action.
7750 * @param[out] dst_port_id
7751 * The target port ID.
7753 * Pointer to the error structure.
7756 * 0 on success, a negative errno value otherwise and rte_errno is set.
7759 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7760 const struct rte_flow_action *action,
7761 uint32_t *dst_port_id,
7762 struct rte_flow_error *error)
7765 struct mlx5_priv *priv;
7766 const struct rte_flow_action_port_id *conf =
7767 (const struct rte_flow_action_port_id *)action->conf;
7769 port = conf->original ? dev->data->port_id : conf->id;
7770 priv = mlx5_port_to_eswitch_info(port, false);
7772 return rte_flow_error_set(error, -rte_errno,
7773 RTE_FLOW_ERROR_TYPE_ACTION,
7775 "No eswitch info was found for port");
7776 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7778 * This parameter is transferred to
7779 * mlx5dv_dr_action_create_dest_ib_port().
7781 *dst_port_id = priv->dev_port;
7784 * Legacy mode, no LAG configurations is supported.
7785 * This parameter is transferred to
7786 * mlx5dv_dr_action_create_dest_vport().
7788 *dst_port_id = priv->vport_id;
7794 * Create a counter with aging configuration.
7797 * Pointer to rte_eth_dev structure.
7799 * Pointer to the counter action configuration.
7801 * Pointer to the aging action configuration.
7804 * Index to flow counter on success, 0 otherwise.
7807 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7808 struct mlx5_flow *dev_flow,
7809 const struct rte_flow_action_count *count,
7810 const struct rte_flow_action_age *age)
7813 struct mlx5_age_param *age_param;
7815 counter = flow_dv_counter_alloc(dev,
7816 count ? count->shared : 0,
7817 count ? count->id : 0,
7818 dev_flow->dv.group, !!age);
7819 if (!counter || age == NULL)
7821 age_param = flow_dv_counter_idx_get_age(dev, counter);
7823 * The counter age accuracy may have a bit delay. Have 3/4
7824 * second bias on the timeount in order to let it age in time.
7826 age_param->context = age->context ? age->context :
7827 (void *)(uintptr_t)(dev_flow->flow_idx);
7829 * The counter age accuracy may have a bit delay. Have 3/4
7830 * second bias on the timeount in order to let it age in time.
7832 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7833 /* Set expire time in unit of 0.1 sec. */
7834 age_param->port_id = dev->data->port_id;
7835 age_param->expire = age_param->timeout +
7836 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7837 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7841 * Add Tx queue matcher
7844 * Pointer to the dev struct.
7845 * @param[in, out] matcher
7847 * @param[in, out] key
7848 * Flow matcher value.
7850 * Flow pattern to translate.
7852 * Item is inner pattern.
7855 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7856 void *matcher, void *key,
7857 const struct rte_flow_item *item)
7859 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7860 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7862 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7864 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7865 struct mlx5_txq_ctrl *txq;
7869 queue_m = (const void *)item->mask;
7872 queue_v = (const void *)item->spec;
7875 txq = mlx5_txq_get(dev, queue_v->queue);
7878 queue = txq->obj->sq->id;
7879 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7880 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7881 queue & queue_m->queue);
7882 mlx5_txq_release(dev, queue_v->queue);
7886 * Set the hash fields according to the @p flow information.
7888 * @param[in] dev_flow
7889 * Pointer to the mlx5_flow.
7890 * @param[in] rss_desc
7891 * Pointer to the mlx5_flow_rss_desc.
7894 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7895 struct mlx5_flow_rss_desc *rss_desc)
7897 uint64_t items = dev_flow->handle->layers;
7899 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7901 dev_flow->hash_fields = 0;
7902 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7903 if (rss_desc->level >= 2) {
7904 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7908 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7909 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7910 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7911 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7912 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7913 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7914 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7916 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7918 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7919 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7920 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7921 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7922 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7923 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7924 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7926 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7929 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7930 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7931 if (rss_types & ETH_RSS_UDP) {
7932 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7933 dev_flow->hash_fields |=
7934 IBV_RX_HASH_SRC_PORT_UDP;
7935 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7936 dev_flow->hash_fields |=
7937 IBV_RX_HASH_DST_PORT_UDP;
7939 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7941 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7942 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7943 if (rss_types & ETH_RSS_TCP) {
7944 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7945 dev_flow->hash_fields |=
7946 IBV_RX_HASH_SRC_PORT_TCP;
7947 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7948 dev_flow->hash_fields |=
7949 IBV_RX_HASH_DST_PORT_TCP;
7951 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7957 * Fill the flow with DV spec, lock free
7958 * (mutex should be acquired by caller).
7961 * Pointer to rte_eth_dev structure.
7962 * @param[in, out] dev_flow
7963 * Pointer to the sub flow.
7965 * Pointer to the flow attributes.
7967 * Pointer to the list of items.
7968 * @param[in] actions
7969 * Pointer to the list of actions.
7971 * Pointer to the error structure.
7974 * 0 on success, a negative errno value otherwise and rte_errno is set.
7977 __flow_dv_translate(struct rte_eth_dev *dev,
7978 struct mlx5_flow *dev_flow,
7979 const struct rte_flow_attr *attr,
7980 const struct rte_flow_item items[],
7981 const struct rte_flow_action actions[],
7982 struct rte_flow_error *error)
7984 struct mlx5_priv *priv = dev->data->dev_private;
7985 struct mlx5_dev_config *dev_conf = &priv->config;
7986 struct rte_flow *flow = dev_flow->flow;
7987 struct mlx5_flow_handle *handle = dev_flow->handle;
7988 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7990 [!!priv->flow_nested_idx];
7991 uint64_t item_flags = 0;
7992 uint64_t last_item = 0;
7993 uint64_t action_flags = 0;
7994 uint64_t priority = attr->priority;
7995 struct mlx5_flow_dv_matcher matcher = {
7997 .size = sizeof(matcher.mask.buf) -
7998 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8002 bool actions_end = false;
8004 struct mlx5_flow_dv_modify_hdr_resource res;
8005 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8006 sizeof(struct mlx5_modification_cmd) *
8007 (MLX5_MAX_MODIFY_NUM + 1)];
8009 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8010 const struct rte_flow_action_count *count = NULL;
8011 const struct rte_flow_action_age *age = NULL;
8012 union flow_dv_attr flow_attr = { .attr = 0 };
8014 union mlx5_flow_tbl_key tbl_key;
8015 uint32_t modify_action_position = UINT32_MAX;
8016 void *match_mask = matcher.mask.buf;
8017 void *match_value = dev_flow->dv.value.buf;
8018 uint8_t next_protocol = 0xff;
8019 struct rte_vlan_hdr vlan = { 0 };
8023 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8024 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8025 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8026 !!priv->fdb_def_rule, &table, error);
8029 dev_flow->dv.group = table;
8031 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8032 if (priority == MLX5_FLOW_PRIO_RSVD)
8033 priority = dev_conf->flow_prio - 1;
8034 /* number of actions must be set to 0 in case of dirty stack. */
8035 mhdr_res->actions_num = 0;
8036 for (; !actions_end ; actions++) {
8037 const struct rte_flow_action_queue *queue;
8038 const struct rte_flow_action_rss *rss;
8039 const struct rte_flow_action *action = actions;
8040 const uint8_t *rss_key;
8041 const struct rte_flow_action_jump *jump_data;
8042 const struct rte_flow_action_meter *mtr;
8043 struct mlx5_flow_tbl_resource *tbl;
8044 uint32_t port_id = 0;
8045 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8046 int action_type = actions->type;
8047 const struct rte_flow_action *found_action = NULL;
8048 struct mlx5_flow_meter *fm = NULL;
8050 if (!mlx5_flow_os_action_supported(action_type))
8051 return rte_flow_error_set(error, ENOTSUP,
8052 RTE_FLOW_ERROR_TYPE_ACTION,
8054 "action not supported");
8055 switch (action_type) {
8056 case RTE_FLOW_ACTION_TYPE_VOID:
8058 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8059 if (flow_dv_translate_action_port_id(dev, action,
8062 port_id_resource.port_id = port_id;
8063 MLX5_ASSERT(!handle->rix_port_id_action);
8064 if (flow_dv_port_id_action_resource_register
8065 (dev, &port_id_resource, dev_flow, error))
8067 dev_flow->dv.actions[actions_n++] =
8068 dev_flow->dv.port_id_action->action;
8069 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8070 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8072 case RTE_FLOW_ACTION_TYPE_FLAG:
8073 action_flags |= MLX5_FLOW_ACTION_FLAG;
8074 dev_flow->handle->mark = 1;
8075 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8076 struct rte_flow_action_mark mark = {
8077 .id = MLX5_FLOW_MARK_DEFAULT,
8080 if (flow_dv_convert_action_mark(dev, &mark,
8084 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8087 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8089 * Only one FLAG or MARK is supported per device flow
8090 * right now. So the pointer to the tag resource must be
8091 * zero before the register process.
8093 MLX5_ASSERT(!handle->dvh.rix_tag);
8094 if (flow_dv_tag_resource_register(dev, tag_be,
8097 MLX5_ASSERT(dev_flow->dv.tag_resource);
8098 dev_flow->dv.actions[actions_n++] =
8099 dev_flow->dv.tag_resource->action;
8101 case RTE_FLOW_ACTION_TYPE_MARK:
8102 action_flags |= MLX5_FLOW_ACTION_MARK;
8103 dev_flow->handle->mark = 1;
8104 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8105 const struct rte_flow_action_mark *mark =
8106 (const struct rte_flow_action_mark *)
8109 if (flow_dv_convert_action_mark(dev, mark,
8113 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8117 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8118 /* Legacy (non-extensive) MARK action. */
8119 tag_be = mlx5_flow_mark_set
8120 (((const struct rte_flow_action_mark *)
8121 (actions->conf))->id);
8122 MLX5_ASSERT(!handle->dvh.rix_tag);
8123 if (flow_dv_tag_resource_register(dev, tag_be,
8126 MLX5_ASSERT(dev_flow->dv.tag_resource);
8127 dev_flow->dv.actions[actions_n++] =
8128 dev_flow->dv.tag_resource->action;
8130 case RTE_FLOW_ACTION_TYPE_SET_META:
8131 if (flow_dv_convert_action_set_meta
8132 (dev, mhdr_res, attr,
8133 (const struct rte_flow_action_set_meta *)
8134 actions->conf, error))
8136 action_flags |= MLX5_FLOW_ACTION_SET_META;
8138 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8139 if (flow_dv_convert_action_set_tag
8141 (const struct rte_flow_action_set_tag *)
8142 actions->conf, error))
8144 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8146 case RTE_FLOW_ACTION_TYPE_DROP:
8147 action_flags |= MLX5_FLOW_ACTION_DROP;
8148 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8150 case RTE_FLOW_ACTION_TYPE_QUEUE:
8151 queue = actions->conf;
8152 rss_desc->queue_num = 1;
8153 rss_desc->queue[0] = queue->index;
8154 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8155 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8157 case RTE_FLOW_ACTION_TYPE_RSS:
8158 rss = actions->conf;
8159 memcpy(rss_desc->queue, rss->queue,
8160 rss->queue_num * sizeof(uint16_t));
8161 rss_desc->queue_num = rss->queue_num;
8162 /* NULL RSS key indicates default RSS key. */
8163 rss_key = !rss->key ? rss_hash_default_key : rss->key;
8164 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8166 * rss->level and rss.types should be set in advance
8167 * when expanding items for RSS.
8169 action_flags |= MLX5_FLOW_ACTION_RSS;
8170 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8172 case RTE_FLOW_ACTION_TYPE_AGE:
8173 case RTE_FLOW_ACTION_TYPE_COUNT:
8174 if (!dev_conf->devx) {
8175 return rte_flow_error_set
8177 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8179 "count action not supported");
8181 /* Save information first, will apply later. */
8182 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8183 count = action->conf;
8186 action_flags |= MLX5_FLOW_ACTION_COUNT;
8188 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8189 dev_flow->dv.actions[actions_n++] =
8190 priv->sh->pop_vlan_action;
8191 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8193 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8194 if (!(action_flags &
8195 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8196 flow_dev_get_vlan_info_from_items(items, &vlan);
8197 vlan.eth_proto = rte_be_to_cpu_16
8198 ((((const struct rte_flow_action_of_push_vlan *)
8199 actions->conf)->ethertype));
8200 found_action = mlx5_flow_find_action
8202 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8204 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8205 found_action = mlx5_flow_find_action
8207 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8209 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8210 if (flow_dv_create_action_push_vlan
8211 (dev, attr, &vlan, dev_flow, error))
8213 dev_flow->dv.actions[actions_n++] =
8214 dev_flow->dv.push_vlan_res->action;
8215 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8217 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8218 /* of_vlan_push action handled this action */
8219 MLX5_ASSERT(action_flags &
8220 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8222 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8223 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8225 flow_dev_get_vlan_info_from_items(items, &vlan);
8226 mlx5_update_vlan_vid_pcp(actions, &vlan);
8227 /* If no VLAN push - this is a modify header action */
8228 if (flow_dv_convert_action_modify_vlan_vid
8229 (mhdr_res, actions, error))
8231 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8233 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8234 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8235 if (flow_dv_create_action_l2_encap(dev, actions,
8240 dev_flow->dv.actions[actions_n++] =
8241 dev_flow->dv.encap_decap->action;
8242 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8244 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8245 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8246 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8250 dev_flow->dv.actions[actions_n++] =
8251 dev_flow->dv.encap_decap->action;
8252 action_flags |= MLX5_FLOW_ACTION_DECAP;
8254 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8255 /* Handle encap with preceding decap. */
8256 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8257 if (flow_dv_create_action_raw_encap
8258 (dev, actions, dev_flow, attr, error))
8260 dev_flow->dv.actions[actions_n++] =
8261 dev_flow->dv.encap_decap->action;
8263 /* Handle encap without preceding decap. */
8264 if (flow_dv_create_action_l2_encap
8265 (dev, actions, dev_flow, attr->transfer,
8268 dev_flow->dv.actions[actions_n++] =
8269 dev_flow->dv.encap_decap->action;
8271 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8273 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8274 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8276 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8277 if (flow_dv_create_action_l2_decap
8278 (dev, dev_flow, attr->transfer, error))
8280 dev_flow->dv.actions[actions_n++] =
8281 dev_flow->dv.encap_decap->action;
8283 /* If decap is followed by encap, handle it at encap. */
8284 action_flags |= MLX5_FLOW_ACTION_DECAP;
8286 case RTE_FLOW_ACTION_TYPE_JUMP:
8287 jump_data = action->conf;
8288 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8290 !!priv->fdb_def_rule,
8294 tbl = flow_dv_tbl_resource_get(dev, table,
8296 attr->transfer, error);
8298 return rte_flow_error_set
8300 RTE_FLOW_ERROR_TYPE_ACTION,
8302 "cannot create jump action.");
8303 if (flow_dv_jump_tbl_resource_register
8304 (dev, tbl, dev_flow, error)) {
8305 flow_dv_tbl_resource_release(dev, tbl);
8306 return rte_flow_error_set
8308 RTE_FLOW_ERROR_TYPE_ACTION,
8310 "cannot create jump action.");
8312 dev_flow->dv.actions[actions_n++] =
8313 dev_flow->dv.jump->action;
8314 action_flags |= MLX5_FLOW_ACTION_JUMP;
8315 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8317 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8318 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8319 if (flow_dv_convert_action_modify_mac
8320 (mhdr_res, actions, error))
8322 action_flags |= actions->type ==
8323 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8324 MLX5_FLOW_ACTION_SET_MAC_SRC :
8325 MLX5_FLOW_ACTION_SET_MAC_DST;
8327 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8328 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8329 if (flow_dv_convert_action_modify_ipv4
8330 (mhdr_res, actions, error))
8332 action_flags |= actions->type ==
8333 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8334 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8335 MLX5_FLOW_ACTION_SET_IPV4_DST;
8337 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8338 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8339 if (flow_dv_convert_action_modify_ipv6
8340 (mhdr_res, actions, error))
8342 action_flags |= actions->type ==
8343 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8344 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8345 MLX5_FLOW_ACTION_SET_IPV6_DST;
8347 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8348 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8349 if (flow_dv_convert_action_modify_tp
8350 (mhdr_res, actions, items,
8351 &flow_attr, dev_flow, !!(action_flags &
8352 MLX5_FLOW_ACTION_DECAP), error))
8354 action_flags |= actions->type ==
8355 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8356 MLX5_FLOW_ACTION_SET_TP_SRC :
8357 MLX5_FLOW_ACTION_SET_TP_DST;
8359 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8360 if (flow_dv_convert_action_modify_dec_ttl
8361 (mhdr_res, items, &flow_attr, dev_flow,
8363 MLX5_FLOW_ACTION_DECAP), error))
8365 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8367 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8368 if (flow_dv_convert_action_modify_ttl
8369 (mhdr_res, actions, items, &flow_attr,
8370 dev_flow, !!(action_flags &
8371 MLX5_FLOW_ACTION_DECAP), error))
8373 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8375 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8376 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8377 if (flow_dv_convert_action_modify_tcp_seq
8378 (mhdr_res, actions, error))
8380 action_flags |= actions->type ==
8381 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8382 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8383 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8386 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8387 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8388 if (flow_dv_convert_action_modify_tcp_ack
8389 (mhdr_res, actions, error))
8391 action_flags |= actions->type ==
8392 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8393 MLX5_FLOW_ACTION_INC_TCP_ACK :
8394 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8396 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8397 if (flow_dv_convert_action_set_reg
8398 (mhdr_res, actions, error))
8400 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8402 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8403 if (flow_dv_convert_action_copy_mreg
8404 (dev, mhdr_res, actions, error))
8406 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8408 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8409 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8410 dev_flow->handle->fate_action =
8411 MLX5_FLOW_FATE_DEFAULT_MISS;
8413 case RTE_FLOW_ACTION_TYPE_METER:
8414 mtr = actions->conf;
8416 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8419 return rte_flow_error_set(error,
8421 RTE_FLOW_ERROR_TYPE_ACTION,
8424 "or invalid parameters");
8425 flow->meter = fm->idx;
8427 /* Set the meter action. */
8429 fm = mlx5_ipool_get(priv->sh->ipool
8430 [MLX5_IPOOL_MTR], flow->meter);
8432 return rte_flow_error_set(error,
8434 RTE_FLOW_ERROR_TYPE_ACTION,
8437 "or invalid parameters");
8439 dev_flow->dv.actions[actions_n++] =
8440 fm->mfts->meter_action;
8441 action_flags |= MLX5_FLOW_ACTION_METER;
8443 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8444 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8447 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8449 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8450 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8453 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8455 case RTE_FLOW_ACTION_TYPE_END:
8457 if (mhdr_res->actions_num) {
8458 /* create modify action if needed. */
8459 if (flow_dv_modify_hdr_resource_register
8460 (dev, mhdr_res, dev_flow, error))
8462 dev_flow->dv.actions[modify_action_position] =
8463 handle->dvh.modify_hdr->action;
8465 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8467 flow_dv_translate_create_counter(dev,
8468 dev_flow, count, age);
8471 return rte_flow_error_set
8473 RTE_FLOW_ERROR_TYPE_ACTION,
8475 "cannot create counter"
8477 dev_flow->dv.actions[actions_n++] =
8478 (flow_dv_counter_get_by_idx(dev,
8479 flow->counter, NULL))->action;
8485 if (mhdr_res->actions_num &&
8486 modify_action_position == UINT32_MAX)
8487 modify_action_position = actions_n++;
8489 dev_flow->dv.actions_n = actions_n;
8490 dev_flow->act_flags = action_flags;
8491 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8492 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8493 int item_type = items->type;
8495 if (!mlx5_flow_os_item_supported(item_type))
8496 return rte_flow_error_set(error, ENOTSUP,
8497 RTE_FLOW_ERROR_TYPE_ITEM,
8498 NULL, "item not supported");
8499 switch (item_type) {
8500 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8501 flow_dv_translate_item_port_id(dev, match_mask,
8502 match_value, items);
8503 last_item = MLX5_FLOW_ITEM_PORT_ID;
8505 case RTE_FLOW_ITEM_TYPE_ETH:
8506 flow_dv_translate_item_eth(match_mask, match_value,
8508 dev_flow->dv.group);
8509 matcher.priority = action_flags &
8510 MLX5_FLOW_ACTION_DEFAULT_MISS &&
8511 !dev_flow->external ?
8512 MLX5_PRIORITY_MAP_L3 :
8513 MLX5_PRIORITY_MAP_L2;
8514 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8515 MLX5_FLOW_LAYER_OUTER_L2;
8517 case RTE_FLOW_ITEM_TYPE_VLAN:
8518 flow_dv_translate_item_vlan(dev_flow,
8519 match_mask, match_value,
8521 dev_flow->dv.group);
8522 matcher.priority = MLX5_PRIORITY_MAP_L2;
8523 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8524 MLX5_FLOW_LAYER_INNER_VLAN) :
8525 (MLX5_FLOW_LAYER_OUTER_L2 |
8526 MLX5_FLOW_LAYER_OUTER_VLAN);
8528 case RTE_FLOW_ITEM_TYPE_IPV4:
8529 mlx5_flow_tunnel_ip_check(items, next_protocol,
8530 &item_flags, &tunnel);
8531 flow_dv_translate_item_ipv4(match_mask, match_value,
8532 items, item_flags, tunnel,
8533 dev_flow->dv.group);
8534 matcher.priority = MLX5_PRIORITY_MAP_L3;
8535 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8536 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8537 if (items->mask != NULL &&
8538 ((const struct rte_flow_item_ipv4 *)
8539 items->mask)->hdr.next_proto_id) {
8541 ((const struct rte_flow_item_ipv4 *)
8542 (items->spec))->hdr.next_proto_id;
8544 ((const struct rte_flow_item_ipv4 *)
8545 (items->mask))->hdr.next_proto_id;
8547 /* Reset for inner layer. */
8548 next_protocol = 0xff;
8551 case RTE_FLOW_ITEM_TYPE_IPV6:
8552 mlx5_flow_tunnel_ip_check(items, next_protocol,
8553 &item_flags, &tunnel);
8554 flow_dv_translate_item_ipv6(match_mask, match_value,
8555 items, item_flags, tunnel,
8556 dev_flow->dv.group);
8557 matcher.priority = MLX5_PRIORITY_MAP_L3;
8558 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8559 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8560 if (items->mask != NULL &&
8561 ((const struct rte_flow_item_ipv6 *)
8562 items->mask)->hdr.proto) {
8564 ((const struct rte_flow_item_ipv6 *)
8565 items->spec)->hdr.proto;
8567 ((const struct rte_flow_item_ipv6 *)
8568 items->mask)->hdr.proto;
8570 /* Reset for inner layer. */
8571 next_protocol = 0xff;
8574 case RTE_FLOW_ITEM_TYPE_TCP:
8575 flow_dv_translate_item_tcp(match_mask, match_value,
8577 matcher.priority = MLX5_PRIORITY_MAP_L4;
8578 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8579 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8581 case RTE_FLOW_ITEM_TYPE_UDP:
8582 flow_dv_translate_item_udp(match_mask, match_value,
8584 matcher.priority = MLX5_PRIORITY_MAP_L4;
8585 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8586 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8588 case RTE_FLOW_ITEM_TYPE_GRE:
8589 flow_dv_translate_item_gre(match_mask, match_value,
8591 matcher.priority = rss_desc->level >= 2 ?
8592 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8593 last_item = MLX5_FLOW_LAYER_GRE;
8595 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8596 flow_dv_translate_item_gre_key(match_mask,
8597 match_value, items);
8598 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8600 case RTE_FLOW_ITEM_TYPE_NVGRE:
8601 flow_dv_translate_item_nvgre(match_mask, match_value,
8603 matcher.priority = rss_desc->level >= 2 ?
8604 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8605 last_item = MLX5_FLOW_LAYER_GRE;
8607 case RTE_FLOW_ITEM_TYPE_VXLAN:
8608 flow_dv_translate_item_vxlan(match_mask, match_value,
8610 matcher.priority = rss_desc->level >= 2 ?
8611 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8612 last_item = MLX5_FLOW_LAYER_VXLAN;
8614 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8615 flow_dv_translate_item_vxlan_gpe(match_mask,
8618 matcher.priority = rss_desc->level >= 2 ?
8619 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8620 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8622 case RTE_FLOW_ITEM_TYPE_GENEVE:
8623 flow_dv_translate_item_geneve(match_mask, match_value,
8625 matcher.priority = rss_desc->level >= 2 ?
8626 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8627 last_item = MLX5_FLOW_LAYER_GENEVE;
8629 case RTE_FLOW_ITEM_TYPE_MPLS:
8630 flow_dv_translate_item_mpls(match_mask, match_value,
8631 items, last_item, tunnel);
8632 matcher.priority = rss_desc->level >= 2 ?
8633 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8634 last_item = MLX5_FLOW_LAYER_MPLS;
8636 case RTE_FLOW_ITEM_TYPE_MARK:
8637 flow_dv_translate_item_mark(dev, match_mask,
8638 match_value, items);
8639 last_item = MLX5_FLOW_ITEM_MARK;
8641 case RTE_FLOW_ITEM_TYPE_META:
8642 flow_dv_translate_item_meta(dev, match_mask,
8643 match_value, attr, items);
8644 last_item = MLX5_FLOW_ITEM_METADATA;
8646 case RTE_FLOW_ITEM_TYPE_ICMP:
8647 flow_dv_translate_item_icmp(match_mask, match_value,
8649 last_item = MLX5_FLOW_LAYER_ICMP;
8651 case RTE_FLOW_ITEM_TYPE_ICMP6:
8652 flow_dv_translate_item_icmp6(match_mask, match_value,
8654 last_item = MLX5_FLOW_LAYER_ICMP6;
8656 case RTE_FLOW_ITEM_TYPE_TAG:
8657 flow_dv_translate_item_tag(dev, match_mask,
8658 match_value, items);
8659 last_item = MLX5_FLOW_ITEM_TAG;
8661 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8662 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8663 match_value, items);
8664 last_item = MLX5_FLOW_ITEM_TAG;
8666 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8667 flow_dv_translate_item_tx_queue(dev, match_mask,
8670 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8672 case RTE_FLOW_ITEM_TYPE_GTP:
8673 flow_dv_translate_item_gtp(match_mask, match_value,
8675 matcher.priority = rss_desc->level >= 2 ?
8676 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8677 last_item = MLX5_FLOW_LAYER_GTP;
8679 case RTE_FLOW_ITEM_TYPE_ECPRI:
8680 if (!mlx5_flex_parser_ecpri_exist(dev)) {
8681 /* Create it only the first time to be used. */
8682 ret = mlx5_flex_parser_ecpri_alloc(dev);
8684 return rte_flow_error_set
8686 RTE_FLOW_ERROR_TYPE_ITEM,
8688 "cannot create eCPRI parser");
8690 /* Adjust the length matcher and device flow value. */
8691 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
8692 dev_flow->dv.value.size =
8693 MLX5_ST_SZ_BYTES(fte_match_param);
8694 flow_dv_translate_item_ecpri(dev, match_mask,
8695 match_value, items);
8696 /* No other protocol should follow eCPRI layer. */
8697 last_item = MLX5_FLOW_LAYER_ECPRI;
8702 item_flags |= last_item;
8705 * When E-Switch mode is enabled, we have two cases where we need to
8706 * set the source port manually.
8707 * The first one, is in case of Nic steering rule, and the second is
8708 * E-Switch rule where no port_id item was found. In both cases
8709 * the source port is set according the current port in use.
8711 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8712 (priv->representor || priv->master)) {
8713 if (flow_dv_translate_item_port_id(dev, match_mask,
8717 #ifdef RTE_LIBRTE_MLX5_DEBUG
8718 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8719 dev_flow->dv.value.buf));
8722 * Layers may be already initialized from prefix flow if this dev_flow
8723 * is the suffix flow.
8725 handle->layers |= item_flags;
8726 if (action_flags & MLX5_FLOW_ACTION_RSS)
8727 flow_dv_hashfields_set(dev_flow, rss_desc);
8728 /* Register matcher. */
8729 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8731 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8733 /* reserved field no needs to be set to 0 here. */
8734 tbl_key.domain = attr->transfer;
8735 tbl_key.direction = attr->egress;
8736 tbl_key.table_id = dev_flow->dv.group;
8737 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8743 * Apply the flow to the NIC, lock free,
8744 * (mutex should be acquired by caller).
8747 * Pointer to the Ethernet device structure.
8748 * @param[in, out] flow
8749 * Pointer to flow structure.
8751 * Pointer to error structure.
8754 * 0 on success, a negative errno value otherwise and rte_errno is set.
8757 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8758 struct rte_flow_error *error)
8760 struct mlx5_flow_dv_workspace *dv;
8761 struct mlx5_flow_handle *dh;
8762 struct mlx5_flow_handle_dv *dv_h;
8763 struct mlx5_flow *dev_flow;
8764 struct mlx5_priv *priv = dev->data->dev_private;
8765 uint32_t handle_idx;
8770 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8771 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8773 dh = dev_flow->handle;
8776 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8778 dv->actions[n++] = priv->sh->esw_drop_action;
8780 struct mlx5_hrxq *drop_hrxq;
8781 drop_hrxq = mlx5_hrxq_drop_new(dev);
8785 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8787 "cannot get drop hash queue");
8791 * Drop queues will be released by the specify
8792 * mlx5_hrxq_drop_release() function. Assign
8793 * the special index to hrxq to mark the queue
8794 * has been allocated.
8796 dh->rix_hrxq = UINT32_MAX;
8797 dv->actions[n++] = drop_hrxq->action;
8799 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8800 struct mlx5_hrxq *hrxq;
8802 struct mlx5_flow_rss_desc *rss_desc =
8803 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8804 [!!priv->flow_nested_idx];
8806 MLX5_ASSERT(rss_desc->queue_num);
8807 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8808 MLX5_RSS_HASH_KEY_LEN,
8809 dev_flow->hash_fields,
8811 rss_desc->queue_num);
8813 hrxq_idx = mlx5_hrxq_new
8814 (dev, rss_desc->key,
8815 MLX5_RSS_HASH_KEY_LEN,
8816 dev_flow->hash_fields,
8818 rss_desc->queue_num,
8820 MLX5_FLOW_LAYER_TUNNEL));
8822 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8827 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8828 "cannot get hash queue");
8831 dh->rix_hrxq = hrxq_idx;
8832 dv->actions[n++] = hrxq->action;
8833 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8834 if (flow_dv_default_miss_resource_register
8838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8839 "cannot create default miss resource");
8840 goto error_default_miss;
8842 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
8843 dv->actions[n++] = priv->sh->default_miss.action;
8845 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8846 (void *)&dv->value, n,
8847 dv->actions, &dh->drv_flow);
8849 rte_flow_error_set(error, errno,
8850 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8852 "hardware refuses to create flow");
8855 if (priv->vmwa_context &&
8856 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8858 * The rule contains the VLAN pattern.
8859 * For VF we are going to create VLAN
8860 * interface to make hypervisor set correct
8861 * e-Switch vport context.
8863 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8868 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8869 flow_dv_default_miss_resource_release(dev);
8871 err = rte_errno; /* Save rte_errno before cleanup. */
8872 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8873 handle_idx, dh, next) {
8874 /* hrxq is union, don't clear it if the flag is not set. */
8876 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8877 mlx5_hrxq_drop_release(dev);
8879 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8880 mlx5_hrxq_release(dev, dh->rix_hrxq);
8884 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8885 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8887 rte_errno = err; /* Restore rte_errno. */
8892 * Release the flow matcher.
8895 * Pointer to Ethernet device.
8897 * Pointer to mlx5_flow_handle.
8900 * 1 while a reference on it exists, 0 when freed.
8903 flow_dv_matcher_release(struct rte_eth_dev *dev,
8904 struct mlx5_flow_handle *handle)
8906 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8908 MLX5_ASSERT(matcher->matcher_object);
8909 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8910 dev->data->port_id, (void *)matcher,
8911 rte_atomic32_read(&matcher->refcnt));
8912 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8913 claim_zero(mlx5_flow_os_destroy_flow_matcher
8914 (matcher->matcher_object));
8915 LIST_REMOVE(matcher, next);
8916 /* table ref-- in release interface. */
8917 flow_dv_tbl_resource_release(dev, matcher->tbl);
8919 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8920 dev->data->port_id, (void *)matcher);
8927 * Release an encap/decap resource.
8930 * Pointer to Ethernet device.
8932 * Pointer to mlx5_flow_handle.
8935 * 1 while a reference on it exists, 0 when freed.
8938 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8939 struct mlx5_flow_handle *handle)
8941 struct mlx5_priv *priv = dev->data->dev_private;
8942 uint32_t idx = handle->dvh.rix_encap_decap;
8943 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8945 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8947 if (!cache_resource)
8949 MLX5_ASSERT(cache_resource->action);
8950 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8951 (void *)cache_resource,
8952 rte_atomic32_read(&cache_resource->refcnt));
8953 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8954 claim_zero(mlx5_flow_os_destroy_flow_action
8955 (cache_resource->action));
8956 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8957 &priv->sh->encaps_decaps, idx,
8958 cache_resource, next);
8959 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8960 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8961 (void *)cache_resource);
8968 * Release an jump to table action resource.
8971 * Pointer to Ethernet device.
8973 * Pointer to mlx5_flow_handle.
8976 * 1 while a reference on it exists, 0 when freed.
8979 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8980 struct mlx5_flow_handle *handle)
8982 struct mlx5_priv *priv = dev->data->dev_private;
8983 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8984 struct mlx5_flow_tbl_data_entry *tbl_data;
8986 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8990 cache_resource = &tbl_data->jump;
8991 MLX5_ASSERT(cache_resource->action);
8992 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8993 (void *)cache_resource,
8994 rte_atomic32_read(&cache_resource->refcnt));
8995 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8996 claim_zero(mlx5_flow_os_destroy_flow_action
8997 (cache_resource->action));
8998 /* jump action memory free is inside the table release. */
8999 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
9000 DRV_LOG(DEBUG, "jump table resource %p: removed",
9001 (void *)cache_resource);
9008 * Release a default miss resource.
9011 * Pointer to Ethernet device.
9013 * 1 while a reference on it exists, 0 when freed.
9016 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9018 struct mlx5_priv *priv = dev->data->dev_private;
9019 struct mlx5_dev_ctx_shared *sh = priv->sh;
9020 struct mlx5_flow_default_miss_resource *cache_resource =
9023 MLX5_ASSERT(cache_resource->action);
9024 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9025 (void *)cache_resource->action,
9026 rte_atomic32_read(&cache_resource->refcnt));
9027 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9028 claim_zero(mlx5_glue->destroy_flow_action
9029 (cache_resource->action));
9030 DRV_LOG(DEBUG, "default miss resource %p: removed",
9031 (void *)cache_resource->action);
9038 * Release a modify-header resource.
9041 * Pointer to mlx5_flow_handle.
9044 * 1 while a reference on it exists, 0 when freed.
9047 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
9049 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9050 handle->dvh.modify_hdr;
9052 MLX5_ASSERT(cache_resource->action);
9053 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9054 (void *)cache_resource,
9055 rte_atomic32_read(&cache_resource->refcnt));
9056 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9057 claim_zero(mlx5_flow_os_destroy_flow_action
9058 (cache_resource->action));
9059 LIST_REMOVE(cache_resource, next);
9060 mlx5_free(cache_resource);
9061 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9062 (void *)cache_resource);
9069 * Release port ID action resource.
9072 * Pointer to Ethernet device.
9074 * Pointer to mlx5_flow_handle.
9077 * 1 while a reference on it exists, 0 when freed.
9080 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9081 struct mlx5_flow_handle *handle)
9083 struct mlx5_priv *priv = dev->data->dev_private;
9084 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9085 uint32_t idx = handle->rix_port_id_action;
9087 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9089 if (!cache_resource)
9091 MLX5_ASSERT(cache_resource->action);
9092 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9093 (void *)cache_resource,
9094 rte_atomic32_read(&cache_resource->refcnt));
9095 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9096 claim_zero(mlx5_flow_os_destroy_flow_action
9097 (cache_resource->action));
9098 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9099 &priv->sh->port_id_action_list, idx,
9100 cache_resource, next);
9101 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9102 DRV_LOG(DEBUG, "port id action resource %p: removed",
9103 (void *)cache_resource);
9110 * Release push vlan action resource.
9113 * Pointer to Ethernet device.
9115 * Pointer to mlx5_flow_handle.
9118 * 1 while a reference on it exists, 0 when freed.
9121 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9122 struct mlx5_flow_handle *handle)
9124 struct mlx5_priv *priv = dev->data->dev_private;
9125 uint32_t idx = handle->dvh.rix_push_vlan;
9126 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9128 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9130 if (!cache_resource)
9132 MLX5_ASSERT(cache_resource->action);
9133 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9134 (void *)cache_resource,
9135 rte_atomic32_read(&cache_resource->refcnt));
9136 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9137 claim_zero(mlx5_flow_os_destroy_flow_action
9138 (cache_resource->action));
9139 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9140 &priv->sh->push_vlan_action_list, idx,
9141 cache_resource, next);
9142 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9143 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9144 (void *)cache_resource);
9151 * Release the fate resource.
9154 * Pointer to Ethernet device.
9156 * Pointer to mlx5_flow_handle.
9159 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9160 struct mlx5_flow_handle *handle)
9162 if (!handle->rix_fate)
9164 switch (handle->fate_action) {
9165 case MLX5_FLOW_FATE_DROP:
9166 mlx5_hrxq_drop_release(dev);
9168 case MLX5_FLOW_FATE_QUEUE:
9169 mlx5_hrxq_release(dev, handle->rix_hrxq);
9171 case MLX5_FLOW_FATE_JUMP:
9172 flow_dv_jump_tbl_resource_release(dev, handle);
9174 case MLX5_FLOW_FATE_PORT_ID:
9175 flow_dv_port_id_action_resource_release(dev, handle);
9177 case MLX5_FLOW_FATE_DEFAULT_MISS:
9178 flow_dv_default_miss_resource_release(dev);
9181 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9184 handle->rix_fate = 0;
9188 * Remove the flow from the NIC but keeps it in memory.
9189 * Lock free, (mutex should be acquired by caller).
9192 * Pointer to Ethernet device.
9193 * @param[in, out] flow
9194 * Pointer to flow structure.
9197 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9199 struct mlx5_flow_handle *dh;
9200 uint32_t handle_idx;
9201 struct mlx5_priv *priv = dev->data->dev_private;
9205 handle_idx = flow->dev_handles;
9206 while (handle_idx) {
9207 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9212 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9213 dh->drv_flow = NULL;
9215 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9216 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9217 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9218 flow_dv_fate_resource_release(dev, dh);
9219 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9220 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9221 handle_idx = dh->next.next;
9226 * Remove the flow from the NIC and the memory.
9227 * Lock free, (mutex should be acquired by caller).
9230 * Pointer to the Ethernet device structure.
9231 * @param[in, out] flow
9232 * Pointer to flow structure.
9235 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9237 struct mlx5_flow_handle *dev_handle;
9238 struct mlx5_priv *priv = dev->data->dev_private;
9242 __flow_dv_remove(dev, flow);
9243 if (flow->counter) {
9244 flow_dv_counter_release(dev, flow->counter);
9248 struct mlx5_flow_meter *fm;
9250 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9253 mlx5_flow_meter_detach(fm);
9256 while (flow->dev_handles) {
9257 uint32_t tmp_idx = flow->dev_handles;
9259 dev_handle = mlx5_ipool_get(priv->sh->ipool
9260 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9263 flow->dev_handles = dev_handle->next.next;
9264 if (dev_handle->dvh.matcher)
9265 flow_dv_matcher_release(dev, dev_handle);
9266 if (dev_handle->dvh.rix_encap_decap)
9267 flow_dv_encap_decap_resource_release(dev, dev_handle);
9268 if (dev_handle->dvh.modify_hdr)
9269 flow_dv_modify_hdr_resource_release(dev_handle);
9270 if (dev_handle->dvh.rix_push_vlan)
9271 flow_dv_push_vlan_action_resource_release(dev,
9273 if (dev_handle->dvh.rix_tag)
9274 flow_dv_tag_release(dev,
9275 dev_handle->dvh.rix_tag);
9276 flow_dv_fate_resource_release(dev, dev_handle);
9277 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9283 * Query a dv flow rule for its statistics via devx.
9286 * Pointer to Ethernet device.
9288 * Pointer to the sub flow.
9290 * data retrieved by the query.
9292 * Perform verbose error reporting if not NULL.
9295 * 0 on success, a negative errno value otherwise and rte_errno is set.
9298 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9299 void *data, struct rte_flow_error *error)
9301 struct mlx5_priv *priv = dev->data->dev_private;
9302 struct rte_flow_query_count *qc = data;
9304 if (!priv->config.devx)
9305 return rte_flow_error_set(error, ENOTSUP,
9306 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9308 "counters are not supported");
9309 if (flow->counter) {
9310 uint64_t pkts, bytes;
9311 struct mlx5_flow_counter *cnt;
9313 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9315 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9319 return rte_flow_error_set(error, -err,
9320 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9321 NULL, "cannot read counters");
9324 qc->hits = pkts - cnt->hits;
9325 qc->bytes = bytes - cnt->bytes;
9332 return rte_flow_error_set(error, EINVAL,
9333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9335 "counters are not available");
9341 * @see rte_flow_query()
9345 flow_dv_query(struct rte_eth_dev *dev,
9346 struct rte_flow *flow __rte_unused,
9347 const struct rte_flow_action *actions __rte_unused,
9348 void *data __rte_unused,
9349 struct rte_flow_error *error __rte_unused)
9353 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9354 switch (actions->type) {
9355 case RTE_FLOW_ACTION_TYPE_VOID:
9357 case RTE_FLOW_ACTION_TYPE_COUNT:
9358 ret = flow_dv_query_count(dev, flow, data, error);
9361 return rte_flow_error_set(error, ENOTSUP,
9362 RTE_FLOW_ERROR_TYPE_ACTION,
9364 "action not supported");
9371 * Destroy the meter table set.
9372 * Lock free, (mutex should be acquired by caller).
9375 * Pointer to Ethernet device.
9377 * Pointer to the meter table set.
9383 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9384 struct mlx5_meter_domains_infos *tbl)
9386 struct mlx5_priv *priv = dev->data->dev_private;
9387 struct mlx5_meter_domains_infos *mtd =
9388 (struct mlx5_meter_domains_infos *)tbl;
9390 if (!mtd || !priv->config.dv_flow_en)
9392 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9393 claim_zero(mlx5_flow_os_destroy_flow
9394 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9395 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9396 claim_zero(mlx5_flow_os_destroy_flow
9397 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9398 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9399 claim_zero(mlx5_flow_os_destroy_flow
9400 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9401 if (mtd->egress.color_matcher)
9402 claim_zero(mlx5_flow_os_destroy_flow_matcher
9403 (mtd->egress.color_matcher));
9404 if (mtd->egress.any_matcher)
9405 claim_zero(mlx5_flow_os_destroy_flow_matcher
9406 (mtd->egress.any_matcher));
9407 if (mtd->egress.tbl)
9408 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9409 if (mtd->egress.sfx_tbl)
9410 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9411 if (mtd->ingress.color_matcher)
9412 claim_zero(mlx5_flow_os_destroy_flow_matcher
9413 (mtd->ingress.color_matcher));
9414 if (mtd->ingress.any_matcher)
9415 claim_zero(mlx5_flow_os_destroy_flow_matcher
9416 (mtd->ingress.any_matcher));
9417 if (mtd->ingress.tbl)
9418 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9419 if (mtd->ingress.sfx_tbl)
9420 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9421 if (mtd->transfer.color_matcher)
9422 claim_zero(mlx5_flow_os_destroy_flow_matcher
9423 (mtd->transfer.color_matcher));
9424 if (mtd->transfer.any_matcher)
9425 claim_zero(mlx5_flow_os_destroy_flow_matcher
9426 (mtd->transfer.any_matcher));
9427 if (mtd->transfer.tbl)
9428 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9429 if (mtd->transfer.sfx_tbl)
9430 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9432 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9437 /* Number of meter flow actions, count and jump or count and drop. */
9438 #define METER_ACTIONS 2
9441 * Create specify domain meter table and suffix table.
9444 * Pointer to Ethernet device.
9445 * @param[in,out] mtb
9446 * Pointer to DV meter table set.
9449 * @param[in] transfer
9451 * @param[in] color_reg_c_idx
9452 * Reg C index for color match.
9455 * 0 on success, -1 otherwise and rte_errno is set.
9458 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9459 struct mlx5_meter_domains_infos *mtb,
9460 uint8_t egress, uint8_t transfer,
9461 uint32_t color_reg_c_idx)
9463 struct mlx5_priv *priv = dev->data->dev_private;
9464 struct mlx5_dev_ctx_shared *sh = priv->sh;
9465 struct mlx5_flow_dv_match_params mask = {
9466 .size = sizeof(mask.buf),
9468 struct mlx5_flow_dv_match_params value = {
9469 .size = sizeof(value.buf),
9471 struct mlx5dv_flow_matcher_attr dv_attr = {
9472 .type = IBV_FLOW_ATTR_NORMAL,
9474 .match_criteria_enable = 0,
9475 .match_mask = (void *)&mask,
9477 void *actions[METER_ACTIONS];
9478 struct mlx5_meter_domain_info *dtb;
9479 struct rte_flow_error error;
9484 dtb = &mtb->transfer;
9488 dtb = &mtb->ingress;
9489 /* Create the meter table with METER level. */
9490 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9491 egress, transfer, &error);
9493 DRV_LOG(ERR, "Failed to create meter policer table.");
9496 /* Create the meter suffix table with SUFFIX level. */
9497 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9498 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9499 egress, transfer, &error);
9500 if (!dtb->sfx_tbl) {
9501 DRV_LOG(ERR, "Failed to create meter suffix table.");
9504 /* Create matchers, Any and Color. */
9505 dv_attr.priority = 3;
9506 dv_attr.match_criteria_enable = 0;
9507 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9510 DRV_LOG(ERR, "Failed to create meter"
9511 " policer default matcher.");
9514 dv_attr.priority = 0;
9515 dv_attr.match_criteria_enable =
9516 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9517 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9518 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9519 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9520 &dtb->color_matcher);
9522 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9525 if (mtb->count_actns[RTE_MTR_DROPPED])
9526 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9527 actions[i++] = mtb->drop_actn;
9528 /* Default rule: lowest priority, match any, actions: drop. */
9529 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9531 &dtb->policer_rules[RTE_MTR_DROPPED]);
9533 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9542 * Create the needed meter and suffix tables.
9543 * Lock free, (mutex should be acquired by caller).
9546 * Pointer to Ethernet device.
9548 * Pointer to the flow meter.
9551 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9553 static struct mlx5_meter_domains_infos *
9554 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9555 const struct mlx5_flow_meter *fm)
9557 struct mlx5_priv *priv = dev->data->dev_private;
9558 struct mlx5_meter_domains_infos *mtb;
9562 if (!priv->mtr_en) {
9563 rte_errno = ENOTSUP;
9566 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9568 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9571 /* Create meter count actions */
9572 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9573 struct mlx5_flow_counter *cnt;
9574 if (!fm->policer_stats.cnt[i])
9576 cnt = flow_dv_counter_get_by_idx(dev,
9577 fm->policer_stats.cnt[i], NULL);
9578 mtb->count_actns[i] = cnt->action;
9580 /* Create drop action. */
9581 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9583 DRV_LOG(ERR, "Failed to create drop action.");
9586 /* Egress meter table. */
9587 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9589 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9592 /* Ingress meter table. */
9593 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9595 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9598 /* FDB meter table. */
9599 if (priv->config.dv_esw_en) {
9600 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9601 priv->mtr_color_reg);
9603 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9609 flow_dv_destroy_mtr_tbl(dev, mtb);
9614 * Destroy domain policer rule.
9617 * Pointer to domain table.
9620 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9624 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9625 if (dt->policer_rules[i]) {
9626 claim_zero(mlx5_flow_os_destroy_flow
9627 (dt->policer_rules[i]));
9628 dt->policer_rules[i] = NULL;
9631 if (dt->jump_actn) {
9632 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9633 dt->jump_actn = NULL;
9638 * Destroy policer rules.
9641 * Pointer to Ethernet device.
9643 * Pointer to flow meter structure.
9645 * Pointer to flow attributes.
9651 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9652 const struct mlx5_flow_meter *fm,
9653 const struct rte_flow_attr *attr)
9655 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9660 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9662 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9664 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9669 * Create specify domain meter policer rule.
9672 * Pointer to flow meter structure.
9674 * Pointer to DV meter table set.
9675 * @param[in] mtr_reg_c
9676 * Color match REG_C.
9679 * 0 on success, -1 otherwise.
9682 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9683 struct mlx5_meter_domain_info *dtb,
9686 struct mlx5_flow_dv_match_params matcher = {
9687 .size = sizeof(matcher.buf),
9689 struct mlx5_flow_dv_match_params value = {
9690 .size = sizeof(value.buf),
9692 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9693 void *actions[METER_ACTIONS];
9697 /* Create jump action. */
9698 if (!dtb->jump_actn)
9699 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9700 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9702 DRV_LOG(ERR, "Failed to create policer jump action.");
9705 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9708 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9709 rte_col_2_mlx5_col(i), UINT8_MAX);
9710 if (mtb->count_actns[i])
9711 actions[j++] = mtb->count_actns[i];
9712 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9713 actions[j++] = mtb->drop_actn;
9715 actions[j++] = dtb->jump_actn;
9716 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9717 (void *)&value, j, actions,
9718 &dtb->policer_rules[i]);
9720 DRV_LOG(ERR, "Failed to create policer rule.");
9731 * Create policer rules.
9734 * Pointer to Ethernet device.
9736 * Pointer to flow meter structure.
9738 * Pointer to flow attributes.
9741 * 0 on success, -1 otherwise.
9744 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9745 struct mlx5_flow_meter *fm,
9746 const struct rte_flow_attr *attr)
9748 struct mlx5_priv *priv = dev->data->dev_private;
9749 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9753 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9754 priv->mtr_color_reg);
9756 DRV_LOG(ERR, "Failed to create egress policer.");
9760 if (attr->ingress) {
9761 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9762 priv->mtr_color_reg);
9764 DRV_LOG(ERR, "Failed to create ingress policer.");
9768 if (attr->transfer) {
9769 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9770 priv->mtr_color_reg);
9772 DRV_LOG(ERR, "Failed to create transfer policer.");
9778 flow_dv_destroy_policer_rules(dev, fm, attr);
9783 * Query a devx counter.
9786 * Pointer to the Ethernet device structure.
9788 * Index to the flow counter.
9790 * Set to clear the counter statistics.
9792 * The statistics value of packets.
9794 * The statistics value of bytes.
9797 * 0 on success, otherwise return -1.
9800 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9801 uint64_t *pkts, uint64_t *bytes)
9803 struct mlx5_priv *priv = dev->data->dev_private;
9804 struct mlx5_flow_counter *cnt;
9805 uint64_t inn_pkts, inn_bytes;
9808 if (!priv->config.devx)
9811 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9814 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9815 *pkts = inn_pkts - cnt->hits;
9816 *bytes = inn_bytes - cnt->bytes;
9818 cnt->hits = inn_pkts;
9819 cnt->bytes = inn_bytes;
9825 * Get aged-out flows.
9828 * Pointer to the Ethernet device structure.
9829 * @param[in] context
9830 * The address of an array of pointers to the aged-out flows contexts.
9831 * @param[in] nb_contexts
9832 * The length of context array pointers.
9834 * Perform verbose error reporting if not NULL. Initialized in case of
9838 * how many contexts get in success, otherwise negative errno value.
9839 * if nb_contexts is 0, return the amount of all aged contexts.
9840 * if nb_contexts is not 0 , return the amount of aged flows reported
9841 * in the context array.
9842 * @note: only stub for now
9845 flow_get_aged_flows(struct rte_eth_dev *dev,
9847 uint32_t nb_contexts,
9848 struct rte_flow_error *error)
9850 struct mlx5_priv *priv = dev->data->dev_private;
9851 struct mlx5_age_info *age_info;
9852 struct mlx5_age_param *age_param;
9853 struct mlx5_flow_counter *counter;
9856 if (nb_contexts && !context)
9857 return rte_flow_error_set(error, EINVAL,
9858 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9860 "Should assign at least one flow or"
9861 " context to get if nb_contexts != 0");
9862 age_info = GET_PORT_AGE_INFO(priv);
9863 rte_spinlock_lock(&age_info->aged_sl);
9864 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9867 age_param = MLX5_CNT_TO_AGE(counter);
9868 context[nb_flows - 1] = age_param->context;
9869 if (!(--nb_contexts))
9873 rte_spinlock_unlock(&age_info->aged_sl);
9874 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9879 * Mutex-protected thunk to lock-free __flow_dv_translate().
9882 flow_dv_translate(struct rte_eth_dev *dev,
9883 struct mlx5_flow *dev_flow,
9884 const struct rte_flow_attr *attr,
9885 const struct rte_flow_item items[],
9886 const struct rte_flow_action actions[],
9887 struct rte_flow_error *error)
9891 flow_dv_shared_lock(dev);
9892 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9893 flow_dv_shared_unlock(dev);
9898 * Mutex-protected thunk to lock-free __flow_dv_apply().
9901 flow_dv_apply(struct rte_eth_dev *dev,
9902 struct rte_flow *flow,
9903 struct rte_flow_error *error)
9907 flow_dv_shared_lock(dev);
9908 ret = __flow_dv_apply(dev, flow, error);
9909 flow_dv_shared_unlock(dev);
9914 * Mutex-protected thunk to lock-free __flow_dv_remove().
9917 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9919 flow_dv_shared_lock(dev);
9920 __flow_dv_remove(dev, flow);
9921 flow_dv_shared_unlock(dev);
9925 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9928 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9930 flow_dv_shared_lock(dev);
9931 __flow_dv_destroy(dev, flow);
9932 flow_dv_shared_unlock(dev);
9936 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9939 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9943 flow_dv_shared_lock(dev);
9944 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9945 flow_dv_shared_unlock(dev);
9950 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9953 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9955 flow_dv_shared_lock(dev);
9956 flow_dv_counter_release(dev, cnt);
9957 flow_dv_shared_unlock(dev);
9960 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9961 .validate = flow_dv_validate,
9962 .prepare = flow_dv_prepare,
9963 .translate = flow_dv_translate,
9964 .apply = flow_dv_apply,
9965 .remove = flow_dv_remove,
9966 .destroy = flow_dv_destroy,
9967 .query = flow_dv_query,
9968 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9969 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9970 .create_policer_rules = flow_dv_create_policer_rules,
9971 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9972 .counter_alloc = flow_dv_counter_allocate,
9973 .counter_free = flow_dv_counter_free,
9974 .counter_query = flow_dv_counter_query,
9975 .get_aged_flows = flow_get_aged_flows,
9978 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */