1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
92 * Initialize flow attributes structure according to flow items' types.
94 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
95 * mode. For tunnel mode, the items to be modified are the outermost ones.
98 * Pointer to item specification.
100 * Pointer to flow attributes structure.
101 * @param[in] dev_flow
102 * Pointer to the sub flow.
103 * @param[in] tunnel_decap
104 * Whether action is after tunnel decapsulation.
107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
108 struct mlx5_flow *dev_flow, bool tunnel_decap)
110 uint64_t layers = dev_flow->handle->layers;
113 * If layers is already initialized, it means this dev_flow is the
114 * suffix flow, the layers flags is set by the prefix flow. Need to
115 * use the layer flags from prefix flow as the suffix flow may not
116 * have the user defined items as the flow is split.
119 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
123 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
130 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
131 uint8_t next_protocol = 0xff;
132 switch (item->type) {
133 case RTE_FLOW_ITEM_TYPE_GRE:
134 case RTE_FLOW_ITEM_TYPE_NVGRE:
135 case RTE_FLOW_ITEM_TYPE_VXLAN:
136 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
137 case RTE_FLOW_ITEM_TYPE_GENEVE:
138 case RTE_FLOW_ITEM_TYPE_MPLS:
142 case RTE_FLOW_ITEM_TYPE_IPV4:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv4 *)
147 item->mask)->hdr.next_proto_id)
149 ((const struct rte_flow_item_ipv4 *)
150 (item->spec))->hdr.next_proto_id &
151 ((const struct rte_flow_item_ipv4 *)
152 (item->mask))->hdr.next_proto_id;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_IPV6:
160 if (item->mask != NULL &&
161 ((const struct rte_flow_item_ipv6 *)
162 item->mask)->hdr.proto)
164 ((const struct rte_flow_item_ipv6 *)
165 (item->spec))->hdr.proto &
166 ((const struct rte_flow_item_ipv6 *)
167 (item->mask))->hdr.proto;
168 if ((next_protocol == IPPROTO_IPIP ||
169 next_protocol == IPPROTO_IPV6) && tunnel_decap)
172 case RTE_FLOW_ITEM_TYPE_UDP:
176 case RTE_FLOW_ITEM_TYPE_TCP:
188 * Convert rte_mtr_color to mlx5 color.
197 rte_col_2_mlx5_col(enum rte_color rcol)
200 case RTE_COLOR_GREEN:
201 return MLX5_FLOW_COLOR_GREEN;
202 case RTE_COLOR_YELLOW:
203 return MLX5_FLOW_COLOR_YELLOW;
205 return MLX5_FLOW_COLOR_RED;
209 return MLX5_FLOW_COLOR_UNDEFINED;
212 struct field_modify_info {
213 uint32_t size; /* Size of field in protocol header, in bytes. */
214 uint32_t offset; /* Offset of field in protocol header, in bytes. */
215 enum mlx5_modification_field id;
218 struct field_modify_info modify_eth[] = {
219 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
220 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
221 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
222 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
226 struct field_modify_info modify_vlan_out_first_vid[] = {
227 /* Size in bits !!! */
228 {12, 0, MLX5_MODI_OUT_FIRST_VID},
232 struct field_modify_info modify_ipv4[] = {
233 {1, 1, MLX5_MODI_OUT_IP_DSCP},
234 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
235 {4, 12, MLX5_MODI_OUT_SIPV4},
236 {4, 16, MLX5_MODI_OUT_DIPV4},
240 struct field_modify_info modify_ipv6[] = {
241 {1, 0, MLX5_MODI_OUT_IP_DSCP},
242 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
243 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
244 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
245 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
246 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
247 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
248 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
249 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
250 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
254 struct field_modify_info modify_udp[] = {
255 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
256 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
260 struct field_modify_info modify_tcp[] = {
261 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
262 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
263 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
264 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
270 uint8_t next_protocol, uint64_t *item_flags,
273 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
274 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
275 if (next_protocol == IPPROTO_IPIP) {
276 *item_flags |= MLX5_FLOW_LAYER_IPIP;
279 if (next_protocol == IPPROTO_IPV6) {
280 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
285 /* Update VLAN's VID/PCP based on input rte_flow_action.
288 * Pointer to struct rte_flow_action.
290 * Pointer to struct rte_vlan_hdr.
293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
294 struct rte_vlan_hdr *vlan)
297 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
299 ((const struct rte_flow_action_of_set_vlan_pcp *)
300 action->conf)->vlan_pcp;
301 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
302 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
303 vlan->vlan_tci |= vlan_tci;
304 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
305 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
306 vlan->vlan_tci |= rte_be_to_cpu_16
307 (((const struct rte_flow_action_of_set_vlan_vid *)
308 action->conf)->vlan_vid);
313 * Fetch 1, 2, 3 or 4 byte field from the byte array
314 * and return as unsigned integer in host-endian format.
317 * Pointer to data array.
319 * Size of field to extract.
322 * converted field in host endian format.
324 static inline uint32_t
325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
334 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
337 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = (ret << 8) | *(data + sizeof(uint16_t));
341 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
352 * Convert modify-header action to DV specification.
354 * Data length of each action is determined by provided field description
355 * and the item mask. Data bit offset and width of each action is determined
356 * by provided item mask.
359 * Pointer to item specification.
361 * Pointer to field modification information.
362 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
363 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
366 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
367 * Negative offset value sets the same offset as source offset.
368 * size field is ignored, value is taken from source field.
369 * @param[in,out] resource
370 * Pointer to the modify-header resource.
372 * Type of modification.
374 * Pointer to the error structure.
377 * 0 on success, a negative errno value otherwise and rte_errno is set.
380 flow_dv_convert_modify_action(struct rte_flow_item *item,
381 struct field_modify_info *field,
382 struct field_modify_info *dcopy,
383 struct mlx5_flow_dv_modify_hdr_resource *resource,
384 uint32_t type, struct rte_flow_error *error)
386 uint32_t i = resource->actions_num;
387 struct mlx5_modification_cmd *actions = resource->actions;
390 * The item and mask are provided in big-endian format.
391 * The fields should be presented as in big-endian format either.
392 * Mask must be always present, it defines the actual field width.
394 MLX5_ASSERT(item->mask);
395 MLX5_ASSERT(field->size);
402 if (i >= MLX5_MAX_MODIFY_NUM)
403 return rte_flow_error_set(error, EINVAL,
404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
405 "too many items to modify");
406 /* Fetch variable byte size mask from the array. */
407 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
408 field->offset, field->size);
413 /* Deduce actual data width in bits from mask value. */
414 off_b = rte_bsf32(mask);
415 size_b = sizeof(uint32_t) * CHAR_BIT -
416 off_b - __builtin_clz(mask);
418 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
419 actions[i] = (struct mlx5_modification_cmd) {
425 /* Convert entire record to expected big-endian format. */
426 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
427 if (type == MLX5_MODIFICATION_TYPE_COPY) {
429 actions[i].dst_field = dcopy->id;
430 actions[i].dst_offset =
431 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
432 /* Convert entire record to big-endian format. */
433 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
435 MLX5_ASSERT(item->spec);
436 data = flow_dv_fetch_field((const uint8_t *)item->spec +
437 field->offset, field->size);
438 /* Shift out the trailing masked bits from data. */
439 data = (data & mask) >> off_b;
440 actions[i].data1 = rte_cpu_to_be_32(data);
444 } while (field->size);
445 if (resource->actions_num == i)
446 return rte_flow_error_set(error, EINVAL,
447 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
448 "invalid modification flow item");
449 resource->actions_num = i;
454 * Convert modify-header set IPv4 address action to DV specification.
456 * @param[in,out] resource
457 * Pointer to the modify-header resource.
459 * Pointer to action specification.
461 * Pointer to the error structure.
464 * 0 on success, a negative errno value otherwise and rte_errno is set.
467 flow_dv_convert_action_modify_ipv4
468 (struct mlx5_flow_dv_modify_hdr_resource *resource,
469 const struct rte_flow_action *action,
470 struct rte_flow_error *error)
472 const struct rte_flow_action_set_ipv4 *conf =
473 (const struct rte_flow_action_set_ipv4 *)(action->conf);
474 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
475 struct rte_flow_item_ipv4 ipv4;
476 struct rte_flow_item_ipv4 ipv4_mask;
478 memset(&ipv4, 0, sizeof(ipv4));
479 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
480 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
481 ipv4.hdr.src_addr = conf->ipv4_addr;
482 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
484 ipv4.hdr.dst_addr = conf->ipv4_addr;
485 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
488 item.mask = &ipv4_mask;
489 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
490 MLX5_MODIFICATION_TYPE_SET, error);
494 * Convert modify-header set IPv6 address action to DV specification.
496 * @param[in,out] resource
497 * Pointer to the modify-header resource.
499 * Pointer to action specification.
501 * Pointer to the error structure.
504 * 0 on success, a negative errno value otherwise and rte_errno is set.
507 flow_dv_convert_action_modify_ipv6
508 (struct mlx5_flow_dv_modify_hdr_resource *resource,
509 const struct rte_flow_action *action,
510 struct rte_flow_error *error)
512 const struct rte_flow_action_set_ipv6 *conf =
513 (const struct rte_flow_action_set_ipv6 *)(action->conf);
514 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
515 struct rte_flow_item_ipv6 ipv6;
516 struct rte_flow_item_ipv6 ipv6_mask;
518 memset(&ipv6, 0, sizeof(ipv6));
519 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
520 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
521 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
522 sizeof(ipv6.hdr.src_addr));
523 memcpy(&ipv6_mask.hdr.src_addr,
524 &rte_flow_item_ipv6_mask.hdr.src_addr,
525 sizeof(ipv6.hdr.src_addr));
527 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
528 sizeof(ipv6.hdr.dst_addr));
529 memcpy(&ipv6_mask.hdr.dst_addr,
530 &rte_flow_item_ipv6_mask.hdr.dst_addr,
531 sizeof(ipv6.hdr.dst_addr));
534 item.mask = &ipv6_mask;
535 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
536 MLX5_MODIFICATION_TYPE_SET, error);
540 * Convert modify-header set MAC address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_mac
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_mac *conf =
559 (const struct rte_flow_action_set_mac *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
561 struct rte_flow_item_eth eth;
562 struct rte_flow_item_eth eth_mask;
564 memset(ð, 0, sizeof(eth));
565 memset(ð_mask, 0, sizeof(eth_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
567 memcpy(ð.src.addr_bytes, &conf->mac_addr,
568 sizeof(eth.src.addr_bytes));
569 memcpy(ð_mask.src.addr_bytes,
570 &rte_flow_item_eth_mask.src.addr_bytes,
571 sizeof(eth_mask.src.addr_bytes));
573 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
574 sizeof(eth.dst.addr_bytes));
575 memcpy(ð_mask.dst.addr_bytes,
576 &rte_flow_item_eth_mask.dst.addr_bytes,
577 sizeof(eth_mask.dst.addr_bytes));
580 item.mask = ð_mask;
581 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
582 MLX5_MODIFICATION_TYPE_SET, error);
586 * Convert modify-header set VLAN VID action to DV specification.
588 * @param[in,out] resource
589 * Pointer to the modify-header resource.
591 * Pointer to action specification.
593 * Pointer to the error structure.
596 * 0 on success, a negative errno value otherwise and rte_errno is set.
599 flow_dv_convert_action_modify_vlan_vid
600 (struct mlx5_flow_dv_modify_hdr_resource *resource,
601 const struct rte_flow_action *action,
602 struct rte_flow_error *error)
604 const struct rte_flow_action_of_set_vlan_vid *conf =
605 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
606 int i = resource->actions_num;
607 struct mlx5_modification_cmd *actions = resource->actions;
608 struct field_modify_info *field = modify_vlan_out_first_vid;
610 if (i >= MLX5_MAX_MODIFY_NUM)
611 return rte_flow_error_set(error, EINVAL,
612 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
613 "too many items to modify");
614 actions[i] = (struct mlx5_modification_cmd) {
615 .action_type = MLX5_MODIFICATION_TYPE_SET,
617 .length = field->size,
618 .offset = field->offset,
620 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
621 actions[i].data1 = conf->vlan_vid;
622 actions[i].data1 = actions[i].data1 << 16;
623 resource->actions_num = ++i;
628 * Convert modify-header set TP action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
638 * @param[in] dev_flow
639 * Pointer to the sub flow.
640 * @param[in] tunnel_decap
641 * Whether action is after tunnel decapsulation.
643 * Pointer to the error structure.
646 * 0 on success, a negative errno value otherwise and rte_errno is set.
649 flow_dv_convert_action_modify_tp
650 (struct mlx5_flow_dv_modify_hdr_resource *resource,
651 const struct rte_flow_action *action,
652 const struct rte_flow_item *items,
653 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
654 bool tunnel_decap, struct rte_flow_error *error)
656 const struct rte_flow_action_set_tp *conf =
657 (const struct rte_flow_action_set_tp *)(action->conf);
658 struct rte_flow_item item;
659 struct rte_flow_item_udp udp;
660 struct rte_flow_item_udp udp_mask;
661 struct rte_flow_item_tcp tcp;
662 struct rte_flow_item_tcp tcp_mask;
663 struct field_modify_info *field;
666 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
668 memset(&udp, 0, sizeof(udp));
669 memset(&udp_mask, 0, sizeof(udp_mask));
670 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
671 udp.hdr.src_port = conf->port;
672 udp_mask.hdr.src_port =
673 rte_flow_item_udp_mask.hdr.src_port;
675 udp.hdr.dst_port = conf->port;
676 udp_mask.hdr.dst_port =
677 rte_flow_item_udp_mask.hdr.dst_port;
679 item.type = RTE_FLOW_ITEM_TYPE_UDP;
681 item.mask = &udp_mask;
684 MLX5_ASSERT(attr->tcp);
685 memset(&tcp, 0, sizeof(tcp));
686 memset(&tcp_mask, 0, sizeof(tcp_mask));
687 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
688 tcp.hdr.src_port = conf->port;
689 tcp_mask.hdr.src_port =
690 rte_flow_item_tcp_mask.hdr.src_port;
692 tcp.hdr.dst_port = conf->port;
693 tcp_mask.hdr.dst_port =
694 rte_flow_item_tcp_mask.hdr.dst_port;
696 item.type = RTE_FLOW_ITEM_TYPE_TCP;
698 item.mask = &tcp_mask;
701 return flow_dv_convert_modify_action(&item, field, NULL, resource,
702 MLX5_MODIFICATION_TYPE_SET, error);
706 * Convert modify-header set TTL action to DV specification.
708 * @param[in,out] resource
709 * Pointer to the modify-header resource.
711 * Pointer to action specification.
713 * Pointer to rte_flow_item objects list.
715 * Pointer to flow attributes structure.
716 * @param[in] dev_flow
717 * Pointer to the sub flow.
718 * @param[in] tunnel_decap
719 * Whether action is after tunnel decapsulation.
721 * Pointer to the error structure.
724 * 0 on success, a negative errno value otherwise and rte_errno is set.
727 flow_dv_convert_action_modify_ttl
728 (struct mlx5_flow_dv_modify_hdr_resource *resource,
729 const struct rte_flow_action *action,
730 const struct rte_flow_item *items,
731 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
732 bool tunnel_decap, struct rte_flow_error *error)
734 const struct rte_flow_action_set_ttl *conf =
735 (const struct rte_flow_action_set_ttl *)(action->conf);
736 struct rte_flow_item item;
737 struct rte_flow_item_ipv4 ipv4;
738 struct rte_flow_item_ipv4 ipv4_mask;
739 struct rte_flow_item_ipv6 ipv6;
740 struct rte_flow_item_ipv6 ipv6_mask;
741 struct field_modify_info *field;
744 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
746 memset(&ipv4, 0, sizeof(ipv4));
747 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
748 ipv4.hdr.time_to_live = conf->ttl_value;
749 ipv4_mask.hdr.time_to_live = 0xFF;
750 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
752 item.mask = &ipv4_mask;
755 MLX5_ASSERT(attr->ipv6);
756 memset(&ipv6, 0, sizeof(ipv6));
757 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
758 ipv6.hdr.hop_limits = conf->ttl_value;
759 ipv6_mask.hdr.hop_limits = 0xFF;
760 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
762 item.mask = &ipv6_mask;
765 return flow_dv_convert_modify_action(&item, field, NULL, resource,
766 MLX5_MODIFICATION_TYPE_SET, error);
770 * Convert modify-header decrement TTL action to DV specification.
772 * @param[in,out] resource
773 * Pointer to the modify-header resource.
775 * Pointer to action specification.
777 * Pointer to rte_flow_item objects list.
779 * Pointer to flow attributes structure.
780 * @param[in] dev_flow
781 * Pointer to the sub flow.
782 * @param[in] tunnel_decap
783 * Whether action is after tunnel decapsulation.
785 * Pointer to the error structure.
788 * 0 on success, a negative errno value otherwise and rte_errno is set.
791 flow_dv_convert_action_modify_dec_ttl
792 (struct mlx5_flow_dv_modify_hdr_resource *resource,
793 const struct rte_flow_item *items,
794 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
795 bool tunnel_decap, struct rte_flow_error *error)
797 struct rte_flow_item item;
798 struct rte_flow_item_ipv4 ipv4;
799 struct rte_flow_item_ipv4 ipv4_mask;
800 struct rte_flow_item_ipv6 ipv6;
801 struct rte_flow_item_ipv6 ipv6_mask;
802 struct field_modify_info *field;
805 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
807 memset(&ipv4, 0, sizeof(ipv4));
808 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
809 ipv4.hdr.time_to_live = 0xFF;
810 ipv4_mask.hdr.time_to_live = 0xFF;
811 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
813 item.mask = &ipv4_mask;
816 MLX5_ASSERT(attr->ipv6);
817 memset(&ipv6, 0, sizeof(ipv6));
818 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
819 ipv6.hdr.hop_limits = 0xFF;
820 ipv6_mask.hdr.hop_limits = 0xFF;
821 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
823 item.mask = &ipv6_mask;
826 return flow_dv_convert_modify_action(&item, field, NULL, resource,
827 MLX5_MODIFICATION_TYPE_ADD, error);
831 * Convert modify-header increment/decrement TCP Sequence number
832 * to DV specification.
834 * @param[in,out] resource
835 * Pointer to the modify-header resource.
837 * Pointer to action specification.
839 * Pointer to the error structure.
842 * 0 on success, a negative errno value otherwise and rte_errno is set.
845 flow_dv_convert_action_modify_tcp_seq
846 (struct mlx5_flow_dv_modify_hdr_resource *resource,
847 const struct rte_flow_action *action,
848 struct rte_flow_error *error)
850 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
851 uint64_t value = rte_be_to_cpu_32(*conf);
852 struct rte_flow_item item;
853 struct rte_flow_item_tcp tcp;
854 struct rte_flow_item_tcp tcp_mask;
856 memset(&tcp, 0, sizeof(tcp));
857 memset(&tcp_mask, 0, sizeof(tcp_mask));
858 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
860 * The HW has no decrement operation, only increment operation.
861 * To simulate decrement X from Y using increment operation
862 * we need to add UINT32_MAX X times to Y.
863 * Each adding of UINT32_MAX decrements Y by 1.
866 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
867 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
868 item.type = RTE_FLOW_ITEM_TYPE_TCP;
870 item.mask = &tcp_mask;
871 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
872 MLX5_MODIFICATION_TYPE_ADD, error);
876 * Convert modify-header increment/decrement TCP Acknowledgment number
877 * to DV specification.
879 * @param[in,out] resource
880 * Pointer to the modify-header resource.
882 * Pointer to action specification.
884 * Pointer to the error structure.
887 * 0 on success, a negative errno value otherwise and rte_errno is set.
890 flow_dv_convert_action_modify_tcp_ack
891 (struct mlx5_flow_dv_modify_hdr_resource *resource,
892 const struct rte_flow_action *action,
893 struct rte_flow_error *error)
895 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
896 uint64_t value = rte_be_to_cpu_32(*conf);
897 struct rte_flow_item item;
898 struct rte_flow_item_tcp tcp;
899 struct rte_flow_item_tcp tcp_mask;
901 memset(&tcp, 0, sizeof(tcp));
902 memset(&tcp_mask, 0, sizeof(tcp_mask));
903 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
905 * The HW has no decrement operation, only increment operation.
906 * To simulate decrement X from Y using increment operation
907 * we need to add UINT32_MAX X times to Y.
908 * Each adding of UINT32_MAX decrements Y by 1.
911 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
912 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
913 item.type = RTE_FLOW_ITEM_TYPE_TCP;
915 item.mask = &tcp_mask;
916 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
917 MLX5_MODIFICATION_TYPE_ADD, error);
920 static enum mlx5_modification_field reg_to_field[] = {
921 [REG_NON] = MLX5_MODI_OUT_NONE,
922 [REG_A] = MLX5_MODI_META_DATA_REG_A,
923 [REG_B] = MLX5_MODI_META_DATA_REG_B,
924 [REG_C_0] = MLX5_MODI_META_REG_C_0,
925 [REG_C_1] = MLX5_MODI_META_REG_C_1,
926 [REG_C_2] = MLX5_MODI_META_REG_C_2,
927 [REG_C_3] = MLX5_MODI_META_REG_C_3,
928 [REG_C_4] = MLX5_MODI_META_REG_C_4,
929 [REG_C_5] = MLX5_MODI_META_REG_C_5,
930 [REG_C_6] = MLX5_MODI_META_REG_C_6,
931 [REG_C_7] = MLX5_MODI_META_REG_C_7,
935 * Convert register set to DV specification.
937 * @param[in,out] resource
938 * Pointer to the modify-header resource.
940 * Pointer to action specification.
942 * Pointer to the error structure.
945 * 0 on success, a negative errno value otherwise and rte_errno is set.
948 flow_dv_convert_action_set_reg
949 (struct mlx5_flow_dv_modify_hdr_resource *resource,
950 const struct rte_flow_action *action,
951 struct rte_flow_error *error)
953 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
954 struct mlx5_modification_cmd *actions = resource->actions;
955 uint32_t i = resource->actions_num;
957 if (i >= MLX5_MAX_MODIFY_NUM)
958 return rte_flow_error_set(error, EINVAL,
959 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
960 "too many items to modify");
961 MLX5_ASSERT(conf->id != REG_NON);
962 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
963 actions[i] = (struct mlx5_modification_cmd) {
964 .action_type = MLX5_MODIFICATION_TYPE_SET,
965 .field = reg_to_field[conf->id],
967 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
968 actions[i].data1 = rte_cpu_to_be_32(conf->data);
970 resource->actions_num = i;
975 * Convert SET_TAG action to DV specification.
978 * Pointer to the rte_eth_dev structure.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_set_tag
991 (struct rte_eth_dev *dev,
992 struct mlx5_flow_dv_modify_hdr_resource *resource,
993 const struct rte_flow_action_set_tag *conf,
994 struct rte_flow_error *error)
996 rte_be32_t data = rte_cpu_to_be_32(conf->data);
997 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
998 struct rte_flow_item item = {
1002 struct field_modify_info reg_c_x[] = {
1005 enum mlx5_modification_field reg_type;
1008 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1011 MLX5_ASSERT(ret != REG_NON);
1012 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1013 reg_type = reg_to_field[ret];
1014 MLX5_ASSERT(reg_type > 0);
1015 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1016 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_SET, error);
1021 * Convert internal COPY_REG action to DV specification.
1024 * Pointer to the rte_eth_dev structure.
1025 * @param[in,out] res
1026 * Pointer to the modify-header resource.
1028 * Pointer to action specification.
1030 * Pointer to the error structure.
1033 * 0 on success, a negative errno value otherwise and rte_errno is set.
1036 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1037 struct mlx5_flow_dv_modify_hdr_resource *res,
1038 const struct rte_flow_action *action,
1039 struct rte_flow_error *error)
1041 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1042 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1043 struct rte_flow_item item = {
1047 struct field_modify_info reg_src[] = {
1048 {4, 0, reg_to_field[conf->src]},
1051 struct field_modify_info reg_dst = {
1053 .id = reg_to_field[conf->dst],
1055 /* Adjust reg_c[0] usage according to reported mask. */
1056 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1057 struct mlx5_priv *priv = dev->data->dev_private;
1058 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060 MLX5_ASSERT(reg_c0);
1061 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1062 if (conf->dst == REG_C_0) {
1063 /* Copy to reg_c[0], within mask only. */
1064 reg_dst.offset = rte_bsf32(reg_c0);
1066 * Mask is ignoring the enianness, because
1067 * there is no conversion in datapath.
1069 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1070 /* Copy from destination lower bits to reg_c[0]. */
1071 mask = reg_c0 >> reg_dst.offset;
1073 /* Copy from destination upper bits to reg_c[0]. */
1074 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1075 rte_fls_u32(reg_c0));
1078 mask = rte_cpu_to_be_32(reg_c0);
1079 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1080 /* Copy from reg_c[0] to destination lower bits. */
1083 /* Copy from reg_c[0] to destination upper bits. */
1084 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1085 (rte_fls_u32(reg_c0) -
1090 return flow_dv_convert_modify_action(&item,
1091 reg_src, ®_dst, res,
1092 MLX5_MODIFICATION_TYPE_COPY,
1097 * Convert MARK action to DV specification. This routine is used
1098 * in extensive metadata only and requires metadata register to be
1099 * handled. In legacy mode hardware tag resource is engaged.
1102 * Pointer to the rte_eth_dev structure.
1104 * Pointer to MARK action specification.
1105 * @param[in,out] resource
1106 * Pointer to the modify-header resource.
1108 * Pointer to the error structure.
1111 * 0 on success, a negative errno value otherwise and rte_errno is set.
1114 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1115 const struct rte_flow_action_mark *conf,
1116 struct mlx5_flow_dv_modify_hdr_resource *resource,
1117 struct rte_flow_error *error)
1119 struct mlx5_priv *priv = dev->data->dev_private;
1120 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1121 priv->sh->dv_mark_mask);
1122 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1123 struct rte_flow_item item = {
1127 struct field_modify_info reg_c_x[] = {
1133 return rte_flow_error_set(error, EINVAL,
1134 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1135 NULL, "zero mark action mask");
1136 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1139 MLX5_ASSERT(reg > 0);
1140 if (reg == REG_C_0) {
1141 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1142 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1145 mask = rte_cpu_to_be_32(mask) & msk_c0;
1146 mask = rte_cpu_to_be_32(mask << shl_c0);
1148 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1149 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1150 MLX5_MODIFICATION_TYPE_SET, error);
1154 * Get metadata register index for specified steering domain.
1157 * Pointer to the rte_eth_dev structure.
1159 * Attributes of flow to determine steering domain.
1161 * Pointer to the error structure.
1164 * positive index on success, a negative errno value otherwise
1165 * and rte_errno is set.
1167 static enum modify_reg
1168 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1169 const struct rte_flow_attr *attr,
1170 struct rte_flow_error *error)
1173 mlx5_flow_get_reg_id(dev, attr->transfer ?
1177 MLX5_METADATA_RX, 0, error);
1179 return rte_flow_error_set(error,
1180 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1181 NULL, "unavailable "
1182 "metadata register");
1187 * Convert SET_META action to DV specification.
1190 * Pointer to the rte_eth_dev structure.
1191 * @param[in,out] resource
1192 * Pointer to the modify-header resource.
1194 * Attributes of flow that includes this item.
1196 * Pointer to action specification.
1198 * Pointer to the error structure.
1201 * 0 on success, a negative errno value otherwise and rte_errno is set.
1204 flow_dv_convert_action_set_meta
1205 (struct rte_eth_dev *dev,
1206 struct mlx5_flow_dv_modify_hdr_resource *resource,
1207 const struct rte_flow_attr *attr,
1208 const struct rte_flow_action_set_meta *conf,
1209 struct rte_flow_error *error)
1211 uint32_t data = conf->data;
1212 uint32_t mask = conf->mask;
1213 struct rte_flow_item item = {
1217 struct field_modify_info reg_c_x[] = {
1220 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1224 MLX5_ASSERT(reg != REG_NON);
1226 * In datapath code there is no endianness
1227 * coversions for perfromance reasons, all
1228 * pattern conversions are done in rte_flow.
1230 if (reg == REG_C_0) {
1231 struct mlx5_priv *priv = dev->data->dev_private;
1232 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1235 MLX5_ASSERT(msk_c0);
1236 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1237 shl_c0 = rte_bsf32(msk_c0);
1239 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1243 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1246 /* The routine expects parameters in memory as big-endian ones. */
1247 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1248 MLX5_MODIFICATION_TYPE_SET, error);
1252 * Convert modify-header set IPv4 DSCP action to DV specification.
1254 * @param[in,out] resource
1255 * Pointer to the modify-header resource.
1257 * Pointer to action specification.
1259 * Pointer to the error structure.
1262 * 0 on success, a negative errno value otherwise and rte_errno is set.
1265 flow_dv_convert_action_modify_ipv4_dscp
1266 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1267 const struct rte_flow_action *action,
1268 struct rte_flow_error *error)
1270 const struct rte_flow_action_set_dscp *conf =
1271 (const struct rte_flow_action_set_dscp *)(action->conf);
1272 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1273 struct rte_flow_item_ipv4 ipv4;
1274 struct rte_flow_item_ipv4 ipv4_mask;
1276 memset(&ipv4, 0, sizeof(ipv4));
1277 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1278 ipv4.hdr.type_of_service = conf->dscp;
1279 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281 item.mask = &ipv4_mask;
1282 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1283 MLX5_MODIFICATION_TYPE_SET, error);
1287 * Convert modify-header set IPv6 DSCP action to DV specification.
1289 * @param[in,out] resource
1290 * Pointer to the modify-header resource.
1292 * Pointer to action specification.
1294 * Pointer to the error structure.
1297 * 0 on success, a negative errno value otherwise and rte_errno is set.
1300 flow_dv_convert_action_modify_ipv6_dscp
1301 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1302 const struct rte_flow_action *action,
1303 struct rte_flow_error *error)
1305 const struct rte_flow_action_set_dscp *conf =
1306 (const struct rte_flow_action_set_dscp *)(action->conf);
1307 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1308 struct rte_flow_item_ipv6 ipv6;
1309 struct rte_flow_item_ipv6 ipv6_mask;
1311 memset(&ipv6, 0, sizeof(ipv6));
1312 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1315 * rdma-core only accept the DSCP bits byte aligned start from
1316 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1317 * bits in IPv6 case as rdma-core requires byte aligned value.
1319 ipv6.hdr.vtc_flow = conf->dscp;
1320 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322 item.mask = &ipv6_mask;
1323 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1324 MLX5_MODIFICATION_TYPE_SET, error);
1328 * Validate MARK item.
1331 * Pointer to the rte_eth_dev structure.
1333 * Item specification.
1335 * Attributes of flow that includes this item.
1337 * Pointer to error structure.
1340 * 0 on success, a negative errno value otherwise and rte_errno is set.
1343 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1344 const struct rte_flow_item *item,
1345 const struct rte_flow_attr *attr __rte_unused,
1346 struct rte_flow_error *error)
1348 struct mlx5_priv *priv = dev->data->dev_private;
1349 struct mlx5_dev_config *config = &priv->config;
1350 const struct rte_flow_item_mark *spec = item->spec;
1351 const struct rte_flow_item_mark *mask = item->mask;
1352 const struct rte_flow_item_mark nic_mask = {
1353 .id = priv->sh->dv_mark_mask,
1357 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1358 return rte_flow_error_set(error, ENOTSUP,
1359 RTE_FLOW_ERROR_TYPE_ITEM, item,
1360 "extended metadata feature"
1362 if (!mlx5_flow_ext_mreg_supported(dev))
1363 return rte_flow_error_set(error, ENOTSUP,
1364 RTE_FLOW_ERROR_TYPE_ITEM, item,
1365 "extended metadata register"
1366 " isn't supported");
1368 return rte_flow_error_set(error, ENOTSUP,
1369 RTE_FLOW_ERROR_TYPE_ITEM, item,
1370 "extended metadata register"
1371 " isn't available");
1372 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1376 return rte_flow_error_set(error, EINVAL,
1377 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1379 "data cannot be empty");
1380 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1381 return rte_flow_error_set(error, EINVAL,
1382 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1384 "mark id exceeds the limit");
1388 return rte_flow_error_set(error, EINVAL,
1389 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1390 "mask cannot be zero");
1392 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1393 (const uint8_t *)&nic_mask,
1394 sizeof(struct rte_flow_item_mark),
1395 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1402 * Validate META item.
1405 * Pointer to the rte_eth_dev structure.
1407 * Item specification.
1409 * Attributes of flow that includes this item.
1411 * Pointer to error structure.
1414 * 0 on success, a negative errno value otherwise and rte_errno is set.
1417 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1418 const struct rte_flow_item *item,
1419 const struct rte_flow_attr *attr,
1420 struct rte_flow_error *error)
1422 struct mlx5_priv *priv = dev->data->dev_private;
1423 struct mlx5_dev_config *config = &priv->config;
1424 const struct rte_flow_item_meta *spec = item->spec;
1425 const struct rte_flow_item_meta *mask = item->mask;
1426 struct rte_flow_item_meta nic_mask = {
1433 return rte_flow_error_set(error, EINVAL,
1434 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1436 "data cannot be empty");
1437 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1438 if (!mlx5_flow_ext_mreg_supported(dev))
1439 return rte_flow_error_set(error, ENOTSUP,
1440 RTE_FLOW_ERROR_TYPE_ITEM, item,
1441 "extended metadata register"
1442 " isn't supported");
1443 reg = flow_dv_get_metadata_reg(dev, attr, error);
1447 return rte_flow_error_set(error, ENOTSUP,
1448 RTE_FLOW_ERROR_TYPE_ITEM, item,
1449 "unavalable extended metadata register");
1451 return rte_flow_error_set(error, ENOTSUP,
1452 RTE_FLOW_ERROR_TYPE_ITEM, item,
1456 nic_mask.data = priv->sh->dv_meta_mask;
1457 } else if (attr->transfer) {
1458 return rte_flow_error_set(error, ENOTSUP,
1459 RTE_FLOW_ERROR_TYPE_ITEM, item,
1460 "extended metadata feature "
1461 "should be enabled when "
1462 "meta item is requested "
1463 "with e-switch mode ");
1466 mask = &rte_flow_item_meta_mask;
1468 return rte_flow_error_set(error, EINVAL,
1469 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1470 "mask cannot be zero");
1472 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1473 (const uint8_t *)&nic_mask,
1474 sizeof(struct rte_flow_item_meta),
1475 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1480 * Validate TAG item.
1483 * Pointer to the rte_eth_dev structure.
1485 * Item specification.
1487 * Attributes of flow that includes this item.
1489 * Pointer to error structure.
1492 * 0 on success, a negative errno value otherwise and rte_errno is set.
1495 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1496 const struct rte_flow_item *item,
1497 const struct rte_flow_attr *attr __rte_unused,
1498 struct rte_flow_error *error)
1500 const struct rte_flow_item_tag *spec = item->spec;
1501 const struct rte_flow_item_tag *mask = item->mask;
1502 const struct rte_flow_item_tag nic_mask = {
1503 .data = RTE_BE32(UINT32_MAX),
1508 if (!mlx5_flow_ext_mreg_supported(dev))
1509 return rte_flow_error_set(error, ENOTSUP,
1510 RTE_FLOW_ERROR_TYPE_ITEM, item,
1511 "extensive metadata register"
1512 " isn't supported");
1514 return rte_flow_error_set(error, EINVAL,
1515 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1517 "data cannot be empty");
1519 mask = &rte_flow_item_tag_mask;
1521 return rte_flow_error_set(error, EINVAL,
1522 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1523 "mask cannot be zero");
1525 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526 (const uint8_t *)&nic_mask,
1527 sizeof(struct rte_flow_item_tag),
1528 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1531 if (mask->index != 0xff)
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534 "partial mask for tag index"
1535 " is not supported");
1536 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1539 MLX5_ASSERT(ret != REG_NON);
1544 * Validate vport item.
1547 * Pointer to the rte_eth_dev structure.
1549 * Item specification.
1551 * Attributes of flow that includes this item.
1552 * @param[in] item_flags
1553 * Bit-fields that holds the items detected until now.
1555 * Pointer to error structure.
1558 * 0 on success, a negative errno value otherwise and rte_errno is set.
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562 const struct rte_flow_item *item,
1563 const struct rte_flow_attr *attr,
1564 uint64_t item_flags,
1565 struct rte_flow_error *error)
1567 const struct rte_flow_item_port_id *spec = item->spec;
1568 const struct rte_flow_item_port_id *mask = item->mask;
1569 const struct rte_flow_item_port_id switch_mask = {
1572 struct mlx5_priv *esw_priv;
1573 struct mlx5_priv *dev_priv;
1576 if (!attr->transfer)
1577 return rte_flow_error_set(error, EINVAL,
1578 RTE_FLOW_ERROR_TYPE_ITEM,
1580 "match on port id is valid only"
1581 " when transfer flag is enabled");
1582 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583 return rte_flow_error_set(error, ENOTSUP,
1584 RTE_FLOW_ERROR_TYPE_ITEM, item,
1585 "multiple source ports are not"
1588 mask = &switch_mask;
1589 if (mask->id != 0xffffffff)
1590 return rte_flow_error_set(error, ENOTSUP,
1591 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1593 "no support for partial mask on"
1595 ret = mlx5_flow_item_acceptable
1596 (item, (const uint8_t *)mask,
1597 (const uint8_t *)&rte_flow_item_port_id_mask,
1598 sizeof(struct rte_flow_item_port_id),
1599 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1604 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1606 return rte_flow_error_set(error, rte_errno,
1607 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608 "failed to obtain E-Switch info for"
1610 dev_priv = mlx5_dev_to_eswitch_info(dev);
1612 return rte_flow_error_set(error, rte_errno,
1613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1615 "failed to obtain E-Switch info");
1616 if (esw_priv->domain_id != dev_priv->domain_id)
1617 return rte_flow_error_set(error, EINVAL,
1618 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619 "cannot match on a port from a"
1620 " different E-Switch");
1625 * Validate VLAN item.
1628 * Item specification.
1629 * @param[in] item_flags
1630 * Bit-fields that holds the items detected until now.
1632 * Ethernet device flow is being created on.
1634 * Pointer to error structure.
1637 * 0 on success, a negative errno value otherwise and rte_errno is set.
1640 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1641 uint64_t item_flags,
1642 struct rte_eth_dev *dev,
1643 struct rte_flow_error *error)
1645 const struct rte_flow_item_vlan *mask = item->mask;
1646 const struct rte_flow_item_vlan nic_mask = {
1647 .tci = RTE_BE16(UINT16_MAX),
1648 .inner_type = RTE_BE16(UINT16_MAX),
1651 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1653 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1654 MLX5_FLOW_LAYER_INNER_L4) :
1655 (MLX5_FLOW_LAYER_OUTER_L3 |
1656 MLX5_FLOW_LAYER_OUTER_L4);
1657 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1658 MLX5_FLOW_LAYER_OUTER_VLAN;
1660 if (item_flags & vlanm)
1661 return rte_flow_error_set(error, EINVAL,
1662 RTE_FLOW_ERROR_TYPE_ITEM, item,
1663 "multiple VLAN layers not supported");
1664 else if ((item_flags & l34m) != 0)
1665 return rte_flow_error_set(error, EINVAL,
1666 RTE_FLOW_ERROR_TYPE_ITEM, item,
1667 "VLAN cannot follow L3/L4 layer");
1669 mask = &rte_flow_item_vlan_mask;
1670 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1671 (const uint8_t *)&nic_mask,
1672 sizeof(struct rte_flow_item_vlan),
1673 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1676 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1677 struct mlx5_priv *priv = dev->data->dev_private;
1679 if (priv->vmwa_context) {
1681 * Non-NULL context means we have a virtual machine
1682 * and SR-IOV enabled, we have to create VLAN interface
1683 * to make hypervisor to setup E-Switch vport
1684 * context correctly. We avoid creating the multiple
1685 * VLAN interfaces, so we cannot support VLAN tag mask.
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ITEM,
1690 "VLAN tag mask is not"
1691 " supported in virtual"
1699 * GTP flags are contained in 1 byte of the format:
1700 * -------------------------------------------
1701 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1702 * |-----------------------------------------|
1703 * | value | Version | PT | Res | E | S | PN |
1704 * -------------------------------------------
1706 * Matching is supported only for GTP flags E, S, PN.
1708 #define MLX5_GTP_FLAGS_MASK 0x07
1711 * Validate GTP item.
1714 * Pointer to the rte_eth_dev structure.
1716 * Item specification.
1717 * @param[in] item_flags
1718 * Bit-fields that holds the items detected until now.
1720 * Pointer to error structure.
1723 * 0 on success, a negative errno value otherwise and rte_errno is set.
1726 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1727 const struct rte_flow_item *item,
1728 uint64_t item_flags,
1729 struct rte_flow_error *error)
1731 struct mlx5_priv *priv = dev->data->dev_private;
1732 const struct rte_flow_item_gtp *spec = item->spec;
1733 const struct rte_flow_item_gtp *mask = item->mask;
1734 const struct rte_flow_item_gtp nic_mask = {
1735 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1737 .teid = RTE_BE32(0xffffffff),
1740 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1741 return rte_flow_error_set(error, ENOTSUP,
1742 RTE_FLOW_ERROR_TYPE_ITEM, item,
1743 "GTP support is not enabled");
1744 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1745 return rte_flow_error_set(error, ENOTSUP,
1746 RTE_FLOW_ERROR_TYPE_ITEM, item,
1747 "multiple tunnel layers not"
1749 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1750 return rte_flow_error_set(error, EINVAL,
1751 RTE_FLOW_ERROR_TYPE_ITEM, item,
1752 "no outer UDP layer found");
1754 mask = &rte_flow_item_gtp_mask;
1755 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1756 return rte_flow_error_set(error, ENOTSUP,
1757 RTE_FLOW_ERROR_TYPE_ITEM, item,
1758 "Match is supported for GTP"
1760 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1761 (const uint8_t *)&nic_mask,
1762 sizeof(struct rte_flow_item_gtp),
1763 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1767 * Validate GTP PSC item.
1770 * Item specification.
1771 * @param[in] last_item
1772 * Previous validated item in the pattern items.
1773 * @param[in] gtp_item
1774 * Previous GTP item specification.
1776 * Pointer to flow attributes.
1778 * Pointer to error structure.
1781 * 0 on success, a negative errno value otherwise and rte_errno is set.
1784 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1786 const struct rte_flow_item *gtp_item,
1787 const struct rte_flow_attr *attr,
1788 struct rte_flow_error *error)
1790 const struct rte_flow_item_gtp *gtp_spec;
1791 const struct rte_flow_item_gtp *gtp_mask;
1792 const struct rte_flow_item_gtp_psc *spec;
1793 const struct rte_flow_item_gtp_psc *mask;
1794 const struct rte_flow_item_gtp_psc nic_mask = {
1799 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1800 return rte_flow_error_set
1801 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1802 "GTP PSC item must be preceded with GTP item");
1803 gtp_spec = gtp_item->spec;
1804 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1805 /* GTP spec and E flag is requested to match zero. */
1807 (gtp_mask->v_pt_rsv_flags &
1808 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1809 return rte_flow_error_set
1810 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1811 "GTP E flag must be 1 to match GTP PSC");
1812 /* Check the flow is not created in group zero. */
1813 if (!attr->transfer && !attr->group)
1814 return rte_flow_error_set
1815 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1816 "GTP PSC is not supported for group 0");
1817 /* GTP spec is here and E flag is requested to match zero. */
1821 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1822 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1823 return rte_flow_error_set
1824 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1825 "PDU type should be smaller than 16");
1826 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1827 (const uint8_t *)&nic_mask,
1828 sizeof(struct rte_flow_item_gtp_psc),
1829 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1833 * Validate IPV4 item.
1834 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1835 * add specific validation of fragment_offset field,
1838 * Item specification.
1839 * @param[in] item_flags
1840 * Bit-fields that holds the items detected until now.
1842 * Pointer to error structure.
1845 * 0 on success, a negative errno value otherwise and rte_errno is set.
1848 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1849 uint64_t item_flags,
1851 uint16_t ether_type,
1852 struct rte_flow_error *error)
1855 const struct rte_flow_item_ipv4 *spec = item->spec;
1856 const struct rte_flow_item_ipv4 *last = item->last;
1857 const struct rte_flow_item_ipv4 *mask = item->mask;
1858 rte_be16_t fragment_offset_spec = 0;
1859 rte_be16_t fragment_offset_last = 0;
1860 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1862 .src_addr = RTE_BE32(0xffffffff),
1863 .dst_addr = RTE_BE32(0xffffffff),
1864 .type_of_service = 0xff,
1865 .fragment_offset = RTE_BE16(0xffff),
1866 .next_proto_id = 0xff,
1867 .time_to_live = 0xff,
1871 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1872 ether_type, &nic_ipv4_mask,
1873 MLX5_ITEM_RANGE_ACCEPTED, error);
1877 fragment_offset_spec = spec->hdr.fragment_offset &
1878 mask->hdr.fragment_offset;
1879 if (!fragment_offset_spec)
1882 * spec and mask are valid, enforce using full mask to make sure the
1883 * complete value is used correctly.
1885 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1886 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1887 return rte_flow_error_set(error, EINVAL,
1888 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1889 item, "must use full mask for"
1890 " fragment_offset");
1892 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1893 * indicating this is 1st fragment of fragmented packet.
1894 * This is not yet supported in MLX5, return appropriate error message.
1896 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1897 return rte_flow_error_set(error, ENOTSUP,
1898 RTE_FLOW_ERROR_TYPE_ITEM, item,
1899 "match on first fragment not "
1901 if (fragment_offset_spec && !last)
1902 return rte_flow_error_set(error, ENOTSUP,
1903 RTE_FLOW_ERROR_TYPE_ITEM, item,
1904 "specified value not supported");
1905 /* spec and last are valid, validate the specified range. */
1906 fragment_offset_last = last->hdr.fragment_offset &
1907 mask->hdr.fragment_offset;
1909 * Match on fragment_offset spec 0x2001 and last 0x3fff
1910 * means MF is 1 and frag-offset is > 0.
1911 * This packet is fragment 2nd and onward, excluding last.
1912 * This is not yet supported in MLX5, return appropriate
1915 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1916 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1917 return rte_flow_error_set(error, ENOTSUP,
1918 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1919 last, "match on following "
1920 "fragments not supported");
1922 * Match on fragment_offset spec 0x0001 and last 0x1fff
1923 * means MF is 0 and frag-offset is > 0.
1924 * This packet is last fragment of fragmented packet.
1925 * This is not yet supported in MLX5, return appropriate
1928 if (fragment_offset_spec == RTE_BE16(1) &&
1929 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1930 return rte_flow_error_set(error, ENOTSUP,
1931 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1932 last, "match on last "
1933 "fragment not supported");
1935 * Match on fragment_offset spec 0x0001 and last 0x3fff
1936 * means MF and/or frag-offset is not 0.
1937 * This is a fragmented packet.
1938 * Other range values are invalid and rejected.
1940 if (!(fragment_offset_spec == RTE_BE16(1) &&
1941 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1944 "specified range not supported");
1949 * Validate IPV6 fragment extension item.
1952 * Item specification.
1953 * @param[in] item_flags
1954 * Bit-fields that holds the items detected until now.
1956 * Pointer to error structure.
1959 * 0 on success, a negative errno value otherwise and rte_errno is set.
1962 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1963 uint64_t item_flags,
1964 struct rte_flow_error *error)
1966 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1967 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1968 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1969 rte_be16_t frag_data_spec = 0;
1970 rte_be16_t frag_data_last = 0;
1971 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1972 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1973 MLX5_FLOW_LAYER_OUTER_L4;
1975 struct rte_flow_item_ipv6_frag_ext nic_mask = {
1977 .next_header = 0xff,
1978 .frag_data = RTE_BE16(0xffff),
1982 if (item_flags & l4m)
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ITEM, item,
1985 "ipv6 fragment extension item cannot "
1987 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1988 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1989 return rte_flow_error_set(error, EINVAL,
1990 RTE_FLOW_ERROR_TYPE_ITEM, item,
1991 "ipv6 fragment extension item must "
1992 "follow ipv6 item");
1994 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1995 if (!frag_data_spec)
1998 * spec and mask are valid, enforce using full mask to make sure the
1999 * complete value is used correctly.
2001 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2002 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2003 return rte_flow_error_set(error, EINVAL,
2004 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2005 item, "must use full mask for"
2008 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2009 * This is 1st fragment of fragmented packet.
2011 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2012 return rte_flow_error_set(error, ENOTSUP,
2013 RTE_FLOW_ERROR_TYPE_ITEM, item,
2014 "match on first fragment not "
2016 if (frag_data_spec && !last)
2017 return rte_flow_error_set(error, EINVAL,
2018 RTE_FLOW_ERROR_TYPE_ITEM, item,
2019 "specified value not supported");
2020 ret = mlx5_flow_item_acceptable
2021 (item, (const uint8_t *)mask,
2022 (const uint8_t *)&nic_mask,
2023 sizeof(struct rte_flow_item_ipv6_frag_ext),
2024 MLX5_ITEM_RANGE_ACCEPTED, error);
2027 /* spec and last are valid, validate the specified range. */
2028 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2030 * Match on frag_data spec 0x0009 and last 0xfff9
2031 * means M is 1 and frag-offset is > 0.
2032 * This packet is fragment 2nd and onward, excluding last.
2033 * This is not yet supported in MLX5, return appropriate
2036 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2037 RTE_IPV6_EHDR_MF_MASK) &&
2038 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2039 return rte_flow_error_set(error, ENOTSUP,
2040 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2041 last, "match on following "
2042 "fragments not supported");
2044 * Match on frag_data spec 0x0008 and last 0xfff8
2045 * means M is 0 and frag-offset is > 0.
2046 * This packet is last fragment of fragmented packet.
2047 * This is not yet supported in MLX5, return appropriate
2050 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2051 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2054 last, "match on last "
2055 "fragment not supported");
2056 /* Other range values are invalid and rejected. */
2057 return rte_flow_error_set(error, EINVAL,
2058 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2059 "specified range not supported");
2063 * Validate the pop VLAN action.
2066 * Pointer to the rte_eth_dev structure.
2067 * @param[in] action_flags
2068 * Holds the actions detected until now.
2070 * Pointer to the pop vlan action.
2071 * @param[in] item_flags
2072 * The items found in this flow rule.
2074 * Pointer to flow attributes.
2076 * Pointer to error structure.
2079 * 0 on success, a negative errno value otherwise and rte_errno is set.
2082 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2083 uint64_t action_flags,
2084 const struct rte_flow_action *action,
2085 uint64_t item_flags,
2086 const struct rte_flow_attr *attr,
2087 struct rte_flow_error *error)
2089 const struct mlx5_priv *priv = dev->data->dev_private;
2093 if (!priv->sh->pop_vlan_action)
2094 return rte_flow_error_set(error, ENOTSUP,
2095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2097 "pop vlan action is not supported");
2099 return rte_flow_error_set(error, ENOTSUP,
2100 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2102 "pop vlan action not supported for "
2104 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2105 return rte_flow_error_set(error, ENOTSUP,
2106 RTE_FLOW_ERROR_TYPE_ACTION, action,
2107 "no support for multiple VLAN "
2109 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2110 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2111 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2112 return rte_flow_error_set(error, ENOTSUP,
2113 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2115 "cannot pop vlan after decap without "
2116 "match on inner vlan in the flow");
2117 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2118 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2119 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2120 return rte_flow_error_set(error, ENOTSUP,
2121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2123 "cannot pop vlan without a "
2124 "match on (outer) vlan in the flow");
2125 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2126 return rte_flow_error_set(error, EINVAL,
2127 RTE_FLOW_ERROR_TYPE_ACTION, action,
2128 "wrong action order, port_id should "
2129 "be after pop VLAN action");
2130 if (!attr->transfer && priv->representor)
2131 return rte_flow_error_set(error, ENOTSUP,
2132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2133 "pop vlan action for VF representor "
2134 "not supported on NIC table");
2139 * Get VLAN default info from vlan match info.
2142 * the list of item specifications.
2144 * pointer VLAN info to fill to.
2147 * 0 on success, a negative errno value otherwise and rte_errno is set.
2150 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2151 struct rte_vlan_hdr *vlan)
2153 const struct rte_flow_item_vlan nic_mask = {
2154 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2155 MLX5DV_FLOW_VLAN_VID_MASK),
2156 .inner_type = RTE_BE16(0xffff),
2161 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2162 int type = items->type;
2164 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2165 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2168 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2169 const struct rte_flow_item_vlan *vlan_m = items->mask;
2170 const struct rte_flow_item_vlan *vlan_v = items->spec;
2172 /* If VLAN item in pattern doesn't contain data, return here. */
2177 /* Only full match values are accepted */
2178 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2179 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2180 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2182 rte_be_to_cpu_16(vlan_v->tci &
2183 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2185 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2186 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2187 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2189 rte_be_to_cpu_16(vlan_v->tci &
2190 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2192 if (vlan_m->inner_type == nic_mask.inner_type)
2193 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2194 vlan_m->inner_type);
2199 * Validate the push VLAN action.
2202 * Pointer to the rte_eth_dev structure.
2203 * @param[in] action_flags
2204 * Holds the actions detected until now.
2205 * @param[in] item_flags
2206 * The items found in this flow rule.
2208 * Pointer to the action structure.
2210 * Pointer to flow attributes
2212 * Pointer to error structure.
2215 * 0 on success, a negative errno value otherwise and rte_errno is set.
2218 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2219 uint64_t action_flags,
2220 const struct rte_flow_item_vlan *vlan_m,
2221 const struct rte_flow_action *action,
2222 const struct rte_flow_attr *attr,
2223 struct rte_flow_error *error)
2225 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2226 const struct mlx5_priv *priv = dev->data->dev_private;
2228 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2229 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2230 return rte_flow_error_set(error, EINVAL,
2231 RTE_FLOW_ERROR_TYPE_ACTION, action,
2232 "invalid vlan ethertype");
2233 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2234 return rte_flow_error_set(error, EINVAL,
2235 RTE_FLOW_ERROR_TYPE_ACTION, action,
2236 "wrong action order, port_id should "
2237 "be after push VLAN");
2238 if (!attr->transfer && priv->representor)
2239 return rte_flow_error_set(error, ENOTSUP,
2240 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2241 "push vlan action for VF representor "
2242 "not supported on NIC table");
2244 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2245 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2246 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2247 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2248 !(mlx5_flow_find_action
2249 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2250 return rte_flow_error_set(error, EINVAL,
2251 RTE_FLOW_ERROR_TYPE_ACTION, action,
2252 "not full match mask on VLAN PCP and "
2253 "there is no of_set_vlan_pcp action, "
2254 "push VLAN action cannot figure out "
2257 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2258 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2259 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2260 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2261 !(mlx5_flow_find_action
2262 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2263 return rte_flow_error_set(error, EINVAL,
2264 RTE_FLOW_ERROR_TYPE_ACTION, action,
2265 "not full match mask on VLAN VID and "
2266 "there is no of_set_vlan_vid action, "
2267 "push VLAN action cannot figure out "
2274 * Validate the set VLAN PCP.
2276 * @param[in] action_flags
2277 * Holds the actions detected until now.
2278 * @param[in] actions
2279 * Pointer to the list of actions remaining in the flow rule.
2281 * Pointer to error structure.
2284 * 0 on success, a negative errno value otherwise and rte_errno is set.
2287 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2288 const struct rte_flow_action actions[],
2289 struct rte_flow_error *error)
2291 const struct rte_flow_action *action = actions;
2292 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2294 if (conf->vlan_pcp > 7)
2295 return rte_flow_error_set(error, EINVAL,
2296 RTE_FLOW_ERROR_TYPE_ACTION, action,
2297 "VLAN PCP value is too big");
2298 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2299 return rte_flow_error_set(error, ENOTSUP,
2300 RTE_FLOW_ERROR_TYPE_ACTION, action,
2301 "set VLAN PCP action must follow "
2302 "the push VLAN action");
2303 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2304 return rte_flow_error_set(error, ENOTSUP,
2305 RTE_FLOW_ERROR_TYPE_ACTION, action,
2306 "Multiple VLAN PCP modification are "
2308 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2309 return rte_flow_error_set(error, EINVAL,
2310 RTE_FLOW_ERROR_TYPE_ACTION, action,
2311 "wrong action order, port_id should "
2312 "be after set VLAN PCP");
2317 * Validate the set VLAN VID.
2319 * @param[in] item_flags
2320 * Holds the items detected in this rule.
2321 * @param[in] action_flags
2322 * Holds the actions detected until now.
2323 * @param[in] actions
2324 * Pointer to the list of actions remaining in the flow rule.
2326 * Pointer to error structure.
2329 * 0 on success, a negative errno value otherwise and rte_errno is set.
2332 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2333 uint64_t action_flags,
2334 const struct rte_flow_action actions[],
2335 struct rte_flow_error *error)
2337 const struct rte_flow_action *action = actions;
2338 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2340 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2341 return rte_flow_error_set(error, EINVAL,
2342 RTE_FLOW_ERROR_TYPE_ACTION, action,
2343 "VLAN VID value is too big");
2344 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2345 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2346 return rte_flow_error_set(error, ENOTSUP,
2347 RTE_FLOW_ERROR_TYPE_ACTION, action,
2348 "set VLAN VID action must follow push"
2349 " VLAN action or match on VLAN item");
2350 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ACTION, action,
2353 "Multiple VLAN VID modifications are "
2355 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2356 return rte_flow_error_set(error, EINVAL,
2357 RTE_FLOW_ERROR_TYPE_ACTION, action,
2358 "wrong action order, port_id should "
2359 "be after set VLAN VID");
2364 * Validate the FLAG action.
2367 * Pointer to the rte_eth_dev structure.
2368 * @param[in] action_flags
2369 * Holds the actions detected until now.
2371 * Pointer to flow attributes
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2380 uint64_t action_flags,
2381 const struct rte_flow_attr *attr,
2382 struct rte_flow_error *error)
2384 struct mlx5_priv *priv = dev->data->dev_private;
2385 struct mlx5_dev_config *config = &priv->config;
2388 /* Fall back if no extended metadata register support. */
2389 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2390 return mlx5_flow_validate_action_flag(action_flags, attr,
2392 /* Extensive metadata mode requires registers. */
2393 if (!mlx5_flow_ext_mreg_supported(dev))
2394 return rte_flow_error_set(error, ENOTSUP,
2395 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2396 "no metadata registers "
2397 "to support flag action");
2398 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2399 return rte_flow_error_set(error, ENOTSUP,
2400 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2401 "extended metadata register"
2402 " isn't available");
2403 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2406 MLX5_ASSERT(ret > 0);
2407 if (action_flags & MLX5_FLOW_ACTION_MARK)
2408 return rte_flow_error_set(error, EINVAL,
2409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410 "can't mark and flag in same flow");
2411 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2412 return rte_flow_error_set(error, EINVAL,
2413 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2415 " actions in same flow");
2420 * Validate MARK action.
2423 * Pointer to the rte_eth_dev structure.
2425 * Pointer to action.
2426 * @param[in] action_flags
2427 * Holds the actions detected until now.
2429 * Pointer to flow attributes
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2438 const struct rte_flow_action *action,
2439 uint64_t action_flags,
2440 const struct rte_flow_attr *attr,
2441 struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 struct mlx5_dev_config *config = &priv->config;
2445 const struct rte_flow_action_mark *mark = action->conf;
2448 if (is_tunnel_offload_active(dev))
2449 return rte_flow_error_set(error, ENOTSUP,
2450 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2452 "if tunnel offload active");
2453 /* Fall back if no extended metadata register support. */
2454 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2455 return mlx5_flow_validate_action_mark(action, action_flags,
2457 /* Extensive metadata mode requires registers. */
2458 if (!mlx5_flow_ext_mreg_supported(dev))
2459 return rte_flow_error_set(error, ENOTSUP,
2460 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2461 "no metadata registers "
2462 "to support mark action");
2463 if (!priv->sh->dv_mark_mask)
2464 return rte_flow_error_set(error, ENOTSUP,
2465 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2466 "extended metadata register"
2467 " isn't available");
2468 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2471 MLX5_ASSERT(ret > 0);
2473 return rte_flow_error_set(error, EINVAL,
2474 RTE_FLOW_ERROR_TYPE_ACTION, action,
2475 "configuration cannot be null");
2476 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2477 return rte_flow_error_set(error, EINVAL,
2478 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2480 "mark id exceeds the limit");
2481 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2482 return rte_flow_error_set(error, EINVAL,
2483 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2484 "can't flag and mark in same flow");
2485 if (action_flags & MLX5_FLOW_ACTION_MARK)
2486 return rte_flow_error_set(error, EINVAL,
2487 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2488 "can't have 2 mark actions in same"
2494 * Validate SET_META action.
2497 * Pointer to the rte_eth_dev structure.
2499 * Pointer to the action structure.
2500 * @param[in] action_flags
2501 * Holds the actions detected until now.
2503 * Pointer to flow attributes
2505 * Pointer to error structure.
2508 * 0 on success, a negative errno value otherwise and rte_errno is set.
2511 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2512 const struct rte_flow_action *action,
2513 uint64_t action_flags __rte_unused,
2514 const struct rte_flow_attr *attr,
2515 struct rte_flow_error *error)
2517 const struct rte_flow_action_set_meta *conf;
2518 uint32_t nic_mask = UINT32_MAX;
2521 if (!mlx5_flow_ext_mreg_supported(dev))
2522 return rte_flow_error_set(error, ENOTSUP,
2523 RTE_FLOW_ERROR_TYPE_ACTION, action,
2524 "extended metadata register"
2525 " isn't supported");
2526 reg = flow_dv_get_metadata_reg(dev, attr, error);
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ACTION, action,
2532 "unavalable extended metadata register");
2533 if (reg != REG_A && reg != REG_B) {
2534 struct mlx5_priv *priv = dev->data->dev_private;
2536 nic_mask = priv->sh->dv_meta_mask;
2538 if (!(action->conf))
2539 return rte_flow_error_set(error, EINVAL,
2540 RTE_FLOW_ERROR_TYPE_ACTION, action,
2541 "configuration cannot be null");
2542 conf = (const struct rte_flow_action_set_meta *)action->conf;
2544 return rte_flow_error_set(error, EINVAL,
2545 RTE_FLOW_ERROR_TYPE_ACTION, action,
2546 "zero mask doesn't have any effect");
2547 if (conf->mask & ~nic_mask)
2548 return rte_flow_error_set(error, EINVAL,
2549 RTE_FLOW_ERROR_TYPE_ACTION, action,
2550 "meta data must be within reg C0");
2555 * Validate SET_TAG action.
2558 * Pointer to the rte_eth_dev structure.
2560 * Pointer to the action structure.
2561 * @param[in] action_flags
2562 * Holds the actions detected until now.
2564 * Pointer to flow attributes
2566 * Pointer to error structure.
2569 * 0 on success, a negative errno value otherwise and rte_errno is set.
2572 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2573 const struct rte_flow_action *action,
2574 uint64_t action_flags,
2575 const struct rte_flow_attr *attr,
2576 struct rte_flow_error *error)
2578 const struct rte_flow_action_set_tag *conf;
2579 const uint64_t terminal_action_flags =
2580 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2581 MLX5_FLOW_ACTION_RSS;
2584 if (!mlx5_flow_ext_mreg_supported(dev))
2585 return rte_flow_error_set(error, ENOTSUP,
2586 RTE_FLOW_ERROR_TYPE_ACTION, action,
2587 "extensive metadata register"
2588 " isn't supported");
2589 if (!(action->conf))
2590 return rte_flow_error_set(error, EINVAL,
2591 RTE_FLOW_ERROR_TYPE_ACTION, action,
2592 "configuration cannot be null");
2593 conf = (const struct rte_flow_action_set_tag *)action->conf;
2595 return rte_flow_error_set(error, EINVAL,
2596 RTE_FLOW_ERROR_TYPE_ACTION, action,
2597 "zero mask doesn't have any effect");
2598 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2601 if (!attr->transfer && attr->ingress &&
2602 (action_flags & terminal_action_flags))
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ACTION, action,
2605 "set_tag has no effect"
2606 " with terminal actions");
2611 * Validate count action.
2614 * Pointer to rte_eth_dev structure.
2616 * Pointer to error structure.
2619 * 0 on success, a negative errno value otherwise and rte_errno is set.
2622 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2623 struct rte_flow_error *error)
2625 struct mlx5_priv *priv = dev->data->dev_private;
2627 if (!priv->config.devx)
2629 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2633 return rte_flow_error_set
2635 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2637 "count action not supported");
2641 * Validate the L2 encap action.
2644 * Pointer to the rte_eth_dev structure.
2645 * @param[in] action_flags
2646 * Holds the actions detected until now.
2648 * Pointer to the action structure.
2650 * Pointer to flow attributes.
2652 * Pointer to error structure.
2655 * 0 on success, a negative errno value otherwise and rte_errno is set.
2658 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2659 uint64_t action_flags,
2660 const struct rte_flow_action *action,
2661 const struct rte_flow_attr *attr,
2662 struct rte_flow_error *error)
2664 const struct mlx5_priv *priv = dev->data->dev_private;
2666 if (!(action->conf))
2667 return rte_flow_error_set(error, EINVAL,
2668 RTE_FLOW_ERROR_TYPE_ACTION, action,
2669 "configuration cannot be null");
2670 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2671 return rte_flow_error_set(error, EINVAL,
2672 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2673 "can only have a single encap action "
2675 if (!attr->transfer && priv->representor)
2676 return rte_flow_error_set(error, ENOTSUP,
2677 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2678 "encap action for VF representor "
2679 "not supported on NIC table");
2684 * Validate a decap action.
2687 * Pointer to the rte_eth_dev structure.
2688 * @param[in] action_flags
2689 * Holds the actions detected until now.
2691 * Pointer to the action structure.
2692 * @param[in] item_flags
2693 * Holds the items detected.
2695 * Pointer to flow attributes
2697 * Pointer to error structure.
2700 * 0 on success, a negative errno value otherwise and rte_errno is set.
2703 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2704 uint64_t action_flags,
2705 const struct rte_flow_action *action,
2706 const uint64_t item_flags,
2707 const struct rte_flow_attr *attr,
2708 struct rte_flow_error *error)
2710 const struct mlx5_priv *priv = dev->data->dev_private;
2712 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2713 !priv->config.decap_en)
2714 return rte_flow_error_set(error, ENOTSUP,
2715 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2716 "decap is not enabled");
2717 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2718 return rte_flow_error_set(error, ENOTSUP,
2719 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2721 MLX5_FLOW_ACTION_DECAP ? "can only "
2722 "have a single decap action" : "decap "
2723 "after encap is not supported");
2724 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2725 return rte_flow_error_set(error, EINVAL,
2726 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2727 "can't have decap action after"
2730 return rte_flow_error_set(error, ENOTSUP,
2731 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2733 "decap action not supported for "
2735 if (!attr->transfer && priv->representor)
2736 return rte_flow_error_set(error, ENOTSUP,
2737 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2738 "decap action for VF representor "
2739 "not supported on NIC table");
2740 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2741 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2742 return rte_flow_error_set(error, ENOTSUP,
2743 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2744 "VXLAN item should be present for VXLAN decap");
2748 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2751 * Validate the raw encap and decap actions.
2754 * Pointer to the rte_eth_dev structure.
2756 * Pointer to the decap action.
2758 * Pointer to the encap action.
2760 * Pointer to flow attributes
2761 * @param[in/out] action_flags
2762 * Holds the actions detected until now.
2763 * @param[out] actions_n
2764 * pointer to the number of actions counter.
2766 * Pointer to the action structure.
2767 * @param[in] item_flags
2768 * Holds the items detected.
2770 * Pointer to error structure.
2773 * 0 on success, a negative errno value otherwise and rte_errno is set.
2776 flow_dv_validate_action_raw_encap_decap
2777 (struct rte_eth_dev *dev,
2778 const struct rte_flow_action_raw_decap *decap,
2779 const struct rte_flow_action_raw_encap *encap,
2780 const struct rte_flow_attr *attr, uint64_t *action_flags,
2781 int *actions_n, const struct rte_flow_action *action,
2782 uint64_t item_flags, struct rte_flow_error *error)
2784 const struct mlx5_priv *priv = dev->data->dev_private;
2787 if (encap && (!encap->size || !encap->data))
2788 return rte_flow_error_set(error, EINVAL,
2789 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2790 "raw encap data cannot be empty");
2791 if (decap && encap) {
2792 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2793 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2796 else if (encap->size <=
2797 MLX5_ENCAPSULATION_DECISION_SIZE &&
2799 MLX5_ENCAPSULATION_DECISION_SIZE)
2802 else if (encap->size >
2803 MLX5_ENCAPSULATION_DECISION_SIZE &&
2805 MLX5_ENCAPSULATION_DECISION_SIZE)
2806 /* 2 L2 actions: encap and decap. */
2809 return rte_flow_error_set(error,
2811 RTE_FLOW_ERROR_TYPE_ACTION,
2812 NULL, "unsupported too small "
2813 "raw decap and too small raw "
2814 "encap combination");
2817 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2818 item_flags, attr, error);
2821 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2825 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2826 return rte_flow_error_set(error, ENOTSUP,
2827 RTE_FLOW_ERROR_TYPE_ACTION,
2829 "small raw encap size");
2830 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2831 return rte_flow_error_set(error, EINVAL,
2832 RTE_FLOW_ERROR_TYPE_ACTION,
2834 "more than one encap action");
2835 if (!attr->transfer && priv->representor)
2836 return rte_flow_error_set
2838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2839 "encap action for VF representor "
2840 "not supported on NIC table");
2841 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2848 * Match encap_decap resource.
2851 * Pointer to the hash list.
2853 * Pointer to exist resource entry object.
2855 * Key of the new entry.
2857 * Pointer to new encap_decap resource.
2860 * 0 on matching, none-zero otherwise.
2863 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2864 struct mlx5_hlist_entry *entry,
2865 uint64_t key __rte_unused, void *cb_ctx)
2867 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2868 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2869 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2871 cache_resource = container_of(entry,
2872 struct mlx5_flow_dv_encap_decap_resource,
2874 if (resource->reformat_type == cache_resource->reformat_type &&
2875 resource->ft_type == cache_resource->ft_type &&
2876 resource->flags == cache_resource->flags &&
2877 resource->size == cache_resource->size &&
2878 !memcmp((const void *)resource->buf,
2879 (const void *)cache_resource->buf,
2886 * Allocate encap_decap resource.
2889 * Pointer to the hash list.
2891 * Pointer to exist resource entry object.
2893 * Pointer to new encap_decap resource.
2896 * 0 on matching, none-zero otherwise.
2898 struct mlx5_hlist_entry *
2899 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2900 uint64_t key __rte_unused,
2903 struct mlx5_dev_ctx_shared *sh = list->ctx;
2904 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2905 struct mlx5dv_dr_domain *domain;
2906 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2907 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2911 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2912 domain = sh->fdb_domain;
2913 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2914 domain = sh->rx_domain;
2916 domain = sh->tx_domain;
2917 /* Register new encap/decap resource. */
2918 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2920 if (!cache_resource) {
2921 rte_flow_error_set(ctx->error, ENOMEM,
2922 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2923 "cannot allocate resource memory");
2926 *cache_resource = *resource;
2927 cache_resource->idx = idx;
2928 ret = mlx5_flow_os_create_flow_action_packet_reformat
2929 (sh->ctx, domain, cache_resource,
2930 &cache_resource->action);
2932 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2933 rte_flow_error_set(ctx->error, ENOMEM,
2934 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2935 NULL, "cannot create action");
2939 return &cache_resource->entry;
2943 * Find existing encap/decap resource or create and register a new one.
2945 * @param[in, out] dev
2946 * Pointer to rte_eth_dev structure.
2947 * @param[in, out] resource
2948 * Pointer to encap/decap resource.
2949 * @parm[in, out] dev_flow
2950 * Pointer to the dev_flow.
2952 * pointer to error structure.
2955 * 0 on success otherwise -errno and errno is set.
2958 flow_dv_encap_decap_resource_register
2959 (struct rte_eth_dev *dev,
2960 struct mlx5_flow_dv_encap_decap_resource *resource,
2961 struct mlx5_flow *dev_flow,
2962 struct rte_flow_error *error)
2964 struct mlx5_priv *priv = dev->data->dev_private;
2965 struct mlx5_dev_ctx_shared *sh = priv->sh;
2966 struct mlx5_hlist_entry *entry;
2970 uint32_t refmt_type:8;
2972 * Header reformat actions can be shared between
2973 * non-root tables. One bit to indicate non-root
2977 uint32_t reserve:15;
2980 } encap_decap_key = {
2982 .ft_type = resource->ft_type,
2983 .refmt_type = resource->reformat_type,
2984 .is_root = !!dev_flow->dv.group,
2988 struct mlx5_flow_cb_ctx ctx = {
2994 resource->flags = dev_flow->dv.group ? 0 : 1;
2995 key64 = __rte_raw_cksum(&encap_decap_key.v32,
2996 sizeof(encap_decap_key.v32), 0);
2997 if (resource->reformat_type !=
2998 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3000 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3001 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3004 resource = container_of(entry, typeof(*resource), entry);
3005 dev_flow->dv.encap_decap = resource;
3006 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3011 * Find existing table jump resource or create and register a new one.
3013 * @param[in, out] dev
3014 * Pointer to rte_eth_dev structure.
3015 * @param[in, out] tbl
3016 * Pointer to flow table resource.
3017 * @parm[in, out] dev_flow
3018 * Pointer to the dev_flow.
3020 * pointer to error structure.
3023 * 0 on success otherwise -errno and errno is set.
3026 flow_dv_jump_tbl_resource_register
3027 (struct rte_eth_dev *dev __rte_unused,
3028 struct mlx5_flow_tbl_resource *tbl,
3029 struct mlx5_flow *dev_flow,
3030 struct rte_flow_error *error __rte_unused)
3032 struct mlx5_flow_tbl_data_entry *tbl_data =
3033 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3036 MLX5_ASSERT(tbl_data->jump.action);
3037 dev_flow->handle->rix_jump = tbl_data->idx;
3038 dev_flow->dv.jump = &tbl_data->jump;
3043 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3044 struct mlx5_cache_entry *entry, void *cb_ctx)
3046 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3047 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3048 struct mlx5_flow_dv_port_id_action_resource *res =
3049 container_of(entry, typeof(*res), entry);
3051 return ref->port_id != res->port_id;
3054 struct mlx5_cache_entry *
3055 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3056 struct mlx5_cache_entry *entry __rte_unused,
3059 struct mlx5_dev_ctx_shared *sh = list->ctx;
3060 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3061 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3062 struct mlx5_flow_dv_port_id_action_resource *cache;
3066 /* Register new port id action resource. */
3067 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3069 rte_flow_error_set(ctx->error, ENOMEM,
3070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3071 "cannot allocate port_id action cache memory");
3075 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3079 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3080 rte_flow_error_set(ctx->error, ENOMEM,
3081 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3082 "cannot create action");
3085 return &cache->entry;
3089 * Find existing table port ID resource or create and register a new one.
3091 * @param[in, out] dev
3092 * Pointer to rte_eth_dev structure.
3093 * @param[in, out] resource
3094 * Pointer to port ID action resource.
3095 * @parm[in, out] dev_flow
3096 * Pointer to the dev_flow.
3098 * pointer to error structure.
3101 * 0 on success otherwise -errno and errno is set.
3104 flow_dv_port_id_action_resource_register
3105 (struct rte_eth_dev *dev,
3106 struct mlx5_flow_dv_port_id_action_resource *resource,
3107 struct mlx5_flow *dev_flow,
3108 struct rte_flow_error *error)
3110 struct mlx5_priv *priv = dev->data->dev_private;
3111 struct mlx5_cache_entry *entry;
3112 struct mlx5_flow_dv_port_id_action_resource *cache;
3113 struct mlx5_flow_cb_ctx ctx = {
3118 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3121 cache = container_of(entry, typeof(*cache), entry);
3122 dev_flow->dv.port_id_action = cache;
3123 dev_flow->handle->rix_port_id_action = cache->idx;
3128 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3129 struct mlx5_cache_entry *entry, void *cb_ctx)
3131 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3132 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3133 struct mlx5_flow_dv_push_vlan_action_resource *res =
3134 container_of(entry, typeof(*res), entry);
3136 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3139 struct mlx5_cache_entry *
3140 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3141 struct mlx5_cache_entry *entry __rte_unused,
3144 struct mlx5_dev_ctx_shared *sh = list->ctx;
3145 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3146 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3147 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3148 struct mlx5dv_dr_domain *domain;
3152 /* Register new port id action resource. */
3153 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3155 rte_flow_error_set(ctx->error, ENOMEM,
3156 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3157 "cannot allocate push_vlan action cache memory");
3161 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3162 domain = sh->fdb_domain;
3163 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3164 domain = sh->rx_domain;
3166 domain = sh->tx_domain;
3167 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3170 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3171 rte_flow_error_set(ctx->error, ENOMEM,
3172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173 "cannot create push vlan action");
3176 return &cache->entry;
3180 * Find existing push vlan resource or create and register a new one.
3182 * @param [in, out] dev
3183 * Pointer to rte_eth_dev structure.
3184 * @param[in, out] resource
3185 * Pointer to port ID action resource.
3186 * @parm[in, out] dev_flow
3187 * Pointer to the dev_flow.
3189 * pointer to error structure.
3192 * 0 on success otherwise -errno and errno is set.
3195 flow_dv_push_vlan_action_resource_register
3196 (struct rte_eth_dev *dev,
3197 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3198 struct mlx5_flow *dev_flow,
3199 struct rte_flow_error *error)
3201 struct mlx5_priv *priv = dev->data->dev_private;
3202 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3203 struct mlx5_cache_entry *entry;
3204 struct mlx5_flow_cb_ctx ctx = {
3209 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3212 cache = container_of(entry, typeof(*cache), entry);
3214 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3215 dev_flow->dv.push_vlan_res = cache;
3220 * Get the size of specific rte_flow_item_type hdr size
3222 * @param[in] item_type
3223 * Tested rte_flow_item_type.
3226 * sizeof struct item_type, 0 if void or irrelevant.
3229 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3233 switch (item_type) {
3234 case RTE_FLOW_ITEM_TYPE_ETH:
3235 retval = sizeof(struct rte_ether_hdr);
3237 case RTE_FLOW_ITEM_TYPE_VLAN:
3238 retval = sizeof(struct rte_vlan_hdr);
3240 case RTE_FLOW_ITEM_TYPE_IPV4:
3241 retval = sizeof(struct rte_ipv4_hdr);
3243 case RTE_FLOW_ITEM_TYPE_IPV6:
3244 retval = sizeof(struct rte_ipv6_hdr);
3246 case RTE_FLOW_ITEM_TYPE_UDP:
3247 retval = sizeof(struct rte_udp_hdr);
3249 case RTE_FLOW_ITEM_TYPE_TCP:
3250 retval = sizeof(struct rte_tcp_hdr);
3252 case RTE_FLOW_ITEM_TYPE_VXLAN:
3253 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3254 retval = sizeof(struct rte_vxlan_hdr);
3256 case RTE_FLOW_ITEM_TYPE_GRE:
3257 case RTE_FLOW_ITEM_TYPE_NVGRE:
3258 retval = sizeof(struct rte_gre_hdr);
3260 case RTE_FLOW_ITEM_TYPE_MPLS:
3261 retval = sizeof(struct rte_mpls_hdr);
3263 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3271 #define MLX5_ENCAP_IPV4_VERSION 0x40
3272 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3273 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3274 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3275 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3276 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3277 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3280 * Convert the encap action data from list of rte_flow_item to raw buffer
3283 * Pointer to rte_flow_item objects list.
3285 * Pointer to the output buffer.
3287 * Pointer to the output buffer size.
3289 * Pointer to the error structure.
3292 * 0 on success, a negative errno value otherwise and rte_errno is set.
3295 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3296 size_t *size, struct rte_flow_error *error)
3298 struct rte_ether_hdr *eth = NULL;
3299 struct rte_vlan_hdr *vlan = NULL;
3300 struct rte_ipv4_hdr *ipv4 = NULL;
3301 struct rte_ipv6_hdr *ipv6 = NULL;
3302 struct rte_udp_hdr *udp = NULL;
3303 struct rte_vxlan_hdr *vxlan = NULL;
3304 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3305 struct rte_gre_hdr *gre = NULL;
3307 size_t temp_size = 0;
3310 return rte_flow_error_set(error, EINVAL,
3311 RTE_FLOW_ERROR_TYPE_ACTION,
3312 NULL, "invalid empty data");
3313 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3314 len = flow_dv_get_item_hdr_len(items->type);
3315 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION,
3318 (void *)items->type,
3319 "items total size is too big"
3320 " for encap action");
3321 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3322 switch (items->type) {
3323 case RTE_FLOW_ITEM_TYPE_ETH:
3324 eth = (struct rte_ether_hdr *)&buf[temp_size];
3326 case RTE_FLOW_ITEM_TYPE_VLAN:
3327 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3329 return rte_flow_error_set(error, EINVAL,
3330 RTE_FLOW_ERROR_TYPE_ACTION,
3331 (void *)items->type,
3332 "eth header not found");
3333 if (!eth->ether_type)
3334 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3336 case RTE_FLOW_ITEM_TYPE_IPV4:
3337 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3339 return rte_flow_error_set(error, EINVAL,
3340 RTE_FLOW_ERROR_TYPE_ACTION,
3341 (void *)items->type,
3342 "neither eth nor vlan"
3344 if (vlan && !vlan->eth_proto)
3345 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3346 else if (eth && !eth->ether_type)
3347 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3348 if (!ipv4->version_ihl)
3349 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3350 MLX5_ENCAP_IPV4_IHL_MIN;
3351 if (!ipv4->time_to_live)
3352 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3354 case RTE_FLOW_ITEM_TYPE_IPV6:
3355 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION,
3359 (void *)items->type,
3360 "neither eth nor vlan"
3362 if (vlan && !vlan->eth_proto)
3363 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3364 else if (eth && !eth->ether_type)
3365 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3366 if (!ipv6->vtc_flow)
3368 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3369 if (!ipv6->hop_limits)
3370 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3372 case RTE_FLOW_ITEM_TYPE_UDP:
3373 udp = (struct rte_udp_hdr *)&buf[temp_size];
3375 return rte_flow_error_set(error, EINVAL,
3376 RTE_FLOW_ERROR_TYPE_ACTION,
3377 (void *)items->type,
3378 "ip header not found");
3379 if (ipv4 && !ipv4->next_proto_id)
3380 ipv4->next_proto_id = IPPROTO_UDP;
3381 else if (ipv6 && !ipv6->proto)
3382 ipv6->proto = IPPROTO_UDP;
3384 case RTE_FLOW_ITEM_TYPE_VXLAN:
3385 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3387 return rte_flow_error_set(error, EINVAL,
3388 RTE_FLOW_ERROR_TYPE_ACTION,
3389 (void *)items->type,
3390 "udp header not found");
3392 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3393 if (!vxlan->vx_flags)
3395 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3397 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3398 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3400 return rte_flow_error_set(error, EINVAL,
3401 RTE_FLOW_ERROR_TYPE_ACTION,
3402 (void *)items->type,
3403 "udp header not found");
3404 if (!vxlan_gpe->proto)
3405 return rte_flow_error_set(error, EINVAL,
3406 RTE_FLOW_ERROR_TYPE_ACTION,
3407 (void *)items->type,
3408 "next protocol not found");
3411 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3412 if (!vxlan_gpe->vx_flags)
3413 vxlan_gpe->vx_flags =
3414 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3416 case RTE_FLOW_ITEM_TYPE_GRE:
3417 case RTE_FLOW_ITEM_TYPE_NVGRE:
3418 gre = (struct rte_gre_hdr *)&buf[temp_size];
3420 return rte_flow_error_set(error, EINVAL,
3421 RTE_FLOW_ERROR_TYPE_ACTION,
3422 (void *)items->type,
3423 "next protocol not found");
3425 return rte_flow_error_set(error, EINVAL,
3426 RTE_FLOW_ERROR_TYPE_ACTION,
3427 (void *)items->type,
3428 "ip header not found");
3429 if (ipv4 && !ipv4->next_proto_id)
3430 ipv4->next_proto_id = IPPROTO_GRE;
3431 else if (ipv6 && !ipv6->proto)
3432 ipv6->proto = IPPROTO_GRE;
3434 case RTE_FLOW_ITEM_TYPE_VOID:
3437 return rte_flow_error_set(error, EINVAL,
3438 RTE_FLOW_ERROR_TYPE_ACTION,
3439 (void *)items->type,
3440 "unsupported item type");
3450 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3452 struct rte_ether_hdr *eth = NULL;
3453 struct rte_vlan_hdr *vlan = NULL;
3454 struct rte_ipv6_hdr *ipv6 = NULL;
3455 struct rte_udp_hdr *udp = NULL;
3459 eth = (struct rte_ether_hdr *)data;
3460 next_hdr = (char *)(eth + 1);
3461 proto = RTE_BE16(eth->ether_type);
3464 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3465 vlan = (struct rte_vlan_hdr *)next_hdr;
3466 proto = RTE_BE16(vlan->eth_proto);
3467 next_hdr += sizeof(struct rte_vlan_hdr);
3470 /* HW calculates IPv4 csum. no need to proceed */
3471 if (proto == RTE_ETHER_TYPE_IPV4)
3474 /* non IPv4/IPv6 header. not supported */
3475 if (proto != RTE_ETHER_TYPE_IPV6) {
3476 return rte_flow_error_set(error, ENOTSUP,
3477 RTE_FLOW_ERROR_TYPE_ACTION,
3478 NULL, "Cannot offload non IPv4/IPv6");
3481 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3483 /* ignore non UDP */
3484 if (ipv6->proto != IPPROTO_UDP)
3487 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3488 udp->dgram_cksum = 0;
3494 * Convert L2 encap action to DV specification.
3497 * Pointer to rte_eth_dev structure.
3499 * Pointer to action structure.
3500 * @param[in, out] dev_flow
3501 * Pointer to the mlx5_flow.
3502 * @param[in] transfer
3503 * Mark if the flow is E-Switch flow.
3505 * Pointer to the error structure.
3508 * 0 on success, a negative errno value otherwise and rte_errno is set.
3511 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3512 const struct rte_flow_action *action,
3513 struct mlx5_flow *dev_flow,
3515 struct rte_flow_error *error)
3517 const struct rte_flow_item *encap_data;
3518 const struct rte_flow_action_raw_encap *raw_encap_data;
3519 struct mlx5_flow_dv_encap_decap_resource res = {
3521 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3522 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3523 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3526 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3528 (const struct rte_flow_action_raw_encap *)action->conf;
3529 res.size = raw_encap_data->size;
3530 memcpy(res.buf, raw_encap_data->data, res.size);
3532 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3534 ((const struct rte_flow_action_vxlan_encap *)
3535 action->conf)->definition;
3538 ((const struct rte_flow_action_nvgre_encap *)
3539 action->conf)->definition;
3540 if (flow_dv_convert_encap_data(encap_data, res.buf,
3544 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3546 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3547 return rte_flow_error_set(error, EINVAL,
3548 RTE_FLOW_ERROR_TYPE_ACTION,
3549 NULL, "can't create L2 encap action");
3554 * Convert L2 decap action to DV specification.
3557 * Pointer to rte_eth_dev structure.
3558 * @param[in, out] dev_flow
3559 * Pointer to the mlx5_flow.
3560 * @param[in] transfer
3561 * Mark if the flow is E-Switch flow.
3563 * Pointer to the error structure.
3566 * 0 on success, a negative errno value otherwise and rte_errno is set.
3569 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3570 struct mlx5_flow *dev_flow,
3572 struct rte_flow_error *error)
3574 struct mlx5_flow_dv_encap_decap_resource res = {
3577 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3578 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3579 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3582 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3583 return rte_flow_error_set(error, EINVAL,
3584 RTE_FLOW_ERROR_TYPE_ACTION,
3585 NULL, "can't create L2 decap action");
3590 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3593 * Pointer to rte_eth_dev structure.
3595 * Pointer to action structure.
3596 * @param[in, out] dev_flow
3597 * Pointer to the mlx5_flow.
3599 * Pointer to the flow attributes.
3601 * Pointer to the error structure.
3604 * 0 on success, a negative errno value otherwise and rte_errno is set.
3607 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3608 const struct rte_flow_action *action,
3609 struct mlx5_flow *dev_flow,
3610 const struct rte_flow_attr *attr,
3611 struct rte_flow_error *error)
3613 const struct rte_flow_action_raw_encap *encap_data;
3614 struct mlx5_flow_dv_encap_decap_resource res;
3616 memset(&res, 0, sizeof(res));
3617 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3618 res.size = encap_data->size;
3619 memcpy(res.buf, encap_data->data, res.size);
3620 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3621 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3622 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3624 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3626 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3627 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3628 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3629 return rte_flow_error_set(error, EINVAL,
3630 RTE_FLOW_ERROR_TYPE_ACTION,
3631 NULL, "can't create encap action");
3636 * Create action push VLAN.
3639 * Pointer to rte_eth_dev structure.
3641 * Pointer to the flow attributes.
3643 * Pointer to the vlan to push to the Ethernet header.
3644 * @param[in, out] dev_flow
3645 * Pointer to the mlx5_flow.
3647 * Pointer to the error structure.
3650 * 0 on success, a negative errno value otherwise and rte_errno is set.
3653 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3654 const struct rte_flow_attr *attr,
3655 const struct rte_vlan_hdr *vlan,
3656 struct mlx5_flow *dev_flow,
3657 struct rte_flow_error *error)
3659 struct mlx5_flow_dv_push_vlan_action_resource res;
3661 memset(&res, 0, sizeof(res));
3663 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3666 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3668 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3669 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3670 return flow_dv_push_vlan_action_resource_register
3671 (dev, &res, dev_flow, error);
3675 * Validate the modify-header actions.
3677 * @param[in] action_flags
3678 * Holds the actions detected until now.
3680 * Pointer to the modify action.
3682 * Pointer to error structure.
3685 * 0 on success, a negative errno value otherwise and rte_errno is set.
3688 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3689 const struct rte_flow_action *action,
3690 struct rte_flow_error *error)
3692 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3693 return rte_flow_error_set(error, EINVAL,
3694 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695 NULL, "action configuration not set");
3696 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3697 return rte_flow_error_set(error, EINVAL,
3698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699 "can't have encap action before"
3705 * Validate the modify-header MAC address actions.
3707 * @param[in] action_flags
3708 * Holds the actions detected until now.
3710 * Pointer to the modify action.
3711 * @param[in] item_flags
3712 * Holds the items detected.
3714 * Pointer to error structure.
3717 * 0 on success, a negative errno value otherwise and rte_errno is set.
3720 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3721 const struct rte_flow_action *action,
3722 const uint64_t item_flags,
3723 struct rte_flow_error *error)
3727 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3729 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3730 return rte_flow_error_set(error, EINVAL,
3731 RTE_FLOW_ERROR_TYPE_ACTION,
3733 "no L2 item in pattern");
3739 * Validate the modify-header IPv4 address actions.
3741 * @param[in] action_flags
3742 * Holds the actions detected until now.
3744 * Pointer to the modify action.
3745 * @param[in] item_flags
3746 * Holds the items detected.
3748 * Pointer to error structure.
3751 * 0 on success, a negative errno value otherwise and rte_errno is set.
3754 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3755 const struct rte_flow_action *action,
3756 const uint64_t item_flags,
3757 struct rte_flow_error *error)
3762 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3764 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3765 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3766 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3767 if (!(item_flags & layer))
3768 return rte_flow_error_set(error, EINVAL,
3769 RTE_FLOW_ERROR_TYPE_ACTION,
3771 "no ipv4 item in pattern");
3777 * Validate the modify-header IPv6 address actions.
3779 * @param[in] action_flags
3780 * Holds the actions detected until now.
3782 * Pointer to the modify action.
3783 * @param[in] item_flags
3784 * Holds the items detected.
3786 * Pointer to error structure.
3789 * 0 on success, a negative errno value otherwise and rte_errno is set.
3792 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3793 const struct rte_flow_action *action,
3794 const uint64_t item_flags,
3795 struct rte_flow_error *error)
3800 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3802 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3803 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3804 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3805 if (!(item_flags & layer))
3806 return rte_flow_error_set(error, EINVAL,
3807 RTE_FLOW_ERROR_TYPE_ACTION,
3809 "no ipv6 item in pattern");
3815 * Validate the modify-header TP actions.
3817 * @param[in] action_flags
3818 * Holds the actions detected until now.
3820 * Pointer to the modify action.
3821 * @param[in] item_flags
3822 * Holds the items detected.
3824 * Pointer to error structure.
3827 * 0 on success, a negative errno value otherwise and rte_errno is set.
3830 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3831 const struct rte_flow_action *action,
3832 const uint64_t item_flags,
3833 struct rte_flow_error *error)
3838 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3840 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3841 MLX5_FLOW_LAYER_INNER_L4 :
3842 MLX5_FLOW_LAYER_OUTER_L4;
3843 if (!(item_flags & layer))
3844 return rte_flow_error_set(error, EINVAL,
3845 RTE_FLOW_ERROR_TYPE_ACTION,
3846 NULL, "no transport layer "
3853 * Validate the modify-header actions of increment/decrement
3854 * TCP Sequence-number.
3856 * @param[in] action_flags
3857 * Holds the actions detected until now.
3859 * Pointer to the modify action.
3860 * @param[in] item_flags
3861 * Holds the items detected.
3863 * Pointer to error structure.
3866 * 0 on success, a negative errno value otherwise and rte_errno is set.
3869 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3870 const struct rte_flow_action *action,
3871 const uint64_t item_flags,
3872 struct rte_flow_error *error)
3877 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3879 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3880 MLX5_FLOW_LAYER_INNER_L4_TCP :
3881 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3882 if (!(item_flags & layer))
3883 return rte_flow_error_set(error, EINVAL,
3884 RTE_FLOW_ERROR_TYPE_ACTION,
3885 NULL, "no TCP item in"
3887 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3888 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3889 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3890 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3891 return rte_flow_error_set(error, EINVAL,
3892 RTE_FLOW_ERROR_TYPE_ACTION,
3894 "cannot decrease and increase"
3895 " TCP sequence number"
3896 " at the same time");
3902 * Validate the modify-header actions of increment/decrement
3903 * TCP Acknowledgment number.
3905 * @param[in] action_flags
3906 * Holds the actions detected until now.
3908 * Pointer to the modify action.
3909 * @param[in] item_flags
3910 * Holds the items detected.
3912 * Pointer to error structure.
3915 * 0 on success, a negative errno value otherwise and rte_errno is set.
3918 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3919 const struct rte_flow_action *action,
3920 const uint64_t item_flags,
3921 struct rte_flow_error *error)
3926 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3928 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3929 MLX5_FLOW_LAYER_INNER_L4_TCP :
3930 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3931 if (!(item_flags & layer))
3932 return rte_flow_error_set(error, EINVAL,
3933 RTE_FLOW_ERROR_TYPE_ACTION,
3934 NULL, "no TCP item in"
3936 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3937 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3938 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3939 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3940 return rte_flow_error_set(error, EINVAL,
3941 RTE_FLOW_ERROR_TYPE_ACTION,
3943 "cannot decrease and increase"
3944 " TCP acknowledgment number"
3945 " at the same time");
3951 * Validate the modify-header TTL actions.
3953 * @param[in] action_flags
3954 * Holds the actions detected until now.
3956 * Pointer to the modify action.
3957 * @param[in] item_flags
3958 * Holds the items detected.
3960 * Pointer to error structure.
3963 * 0 on success, a negative errno value otherwise and rte_errno is set.
3966 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3967 const struct rte_flow_action *action,
3968 const uint64_t item_flags,
3969 struct rte_flow_error *error)
3974 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3976 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3977 MLX5_FLOW_LAYER_INNER_L3 :
3978 MLX5_FLOW_LAYER_OUTER_L3;
3979 if (!(item_flags & layer))
3980 return rte_flow_error_set(error, EINVAL,
3981 RTE_FLOW_ERROR_TYPE_ACTION,
3983 "no IP protocol in pattern");
3989 * Validate jump action.
3992 * Pointer to the jump action.
3993 * @param[in] action_flags
3994 * Holds the actions detected until now.
3995 * @param[in] attributes
3996 * Pointer to flow attributes
3997 * @param[in] external
3998 * Action belongs to flow rule created by request external to PMD.
4000 * Pointer to error structure.
4003 * 0 on success, a negative errno value otherwise and rte_errno is set.
4006 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4007 const struct mlx5_flow_tunnel *tunnel,
4008 const struct rte_flow_action *action,
4009 uint64_t action_flags,
4010 const struct rte_flow_attr *attributes,
4011 bool external, struct rte_flow_error *error)
4013 uint32_t target_group, table;
4015 struct flow_grp_info grp_info = {
4016 .external = !!external,
4017 .transfer = !!attributes->transfer,
4021 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4022 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4023 return rte_flow_error_set(error, EINVAL,
4024 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4025 "can't have 2 fate actions in"
4027 if (action_flags & MLX5_FLOW_ACTION_METER)
4028 return rte_flow_error_set(error, ENOTSUP,
4029 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4030 "jump with meter not support");
4032 return rte_flow_error_set(error, EINVAL,
4033 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4034 NULL, "action configuration not set");
4036 ((const struct rte_flow_action_jump *)action->conf)->group;
4037 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4041 if (attributes->group == target_group &&
4042 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4043 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4044 return rte_flow_error_set(error, EINVAL,
4045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4046 "target group must be other than"
4047 " the current flow group");
4052 * Validate the port_id action.
4055 * Pointer to rte_eth_dev structure.
4056 * @param[in] action_flags
4057 * Bit-fields that holds the actions detected until now.
4059 * Port_id RTE action structure.
4061 * Attributes of flow that includes this action.
4063 * Pointer to error structure.
4066 * 0 on success, a negative errno value otherwise and rte_errno is set.
4069 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4070 uint64_t action_flags,
4071 const struct rte_flow_action *action,
4072 const struct rte_flow_attr *attr,
4073 struct rte_flow_error *error)
4075 const struct rte_flow_action_port_id *port_id;
4076 struct mlx5_priv *act_priv;
4077 struct mlx5_priv *dev_priv;
4080 if (!attr->transfer)
4081 return rte_flow_error_set(error, ENOTSUP,
4082 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4084 "port id action is valid in transfer"
4086 if (!action || !action->conf)
4087 return rte_flow_error_set(error, ENOTSUP,
4088 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4090 "port id action parameters must be"
4092 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4093 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4094 return rte_flow_error_set(error, EINVAL,
4095 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4096 "can have only one fate actions in"
4098 dev_priv = mlx5_dev_to_eswitch_info(dev);
4100 return rte_flow_error_set(error, rte_errno,
4101 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4103 "failed to obtain E-Switch info");
4104 port_id = action->conf;
4105 port = port_id->original ? dev->data->port_id : port_id->id;
4106 act_priv = mlx5_port_to_eswitch_info(port, false);
4108 return rte_flow_error_set
4110 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4111 "failed to obtain E-Switch port id for port");
4112 if (act_priv->domain_id != dev_priv->domain_id)
4113 return rte_flow_error_set
4115 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4116 "port does not belong to"
4117 " E-Switch being configured");
4122 * Get the maximum number of modify header actions.
4125 * Pointer to rte_eth_dev structure.
4127 * Flags bits to check if root level.
4130 * Max number of modify header actions device can support.
4132 static inline unsigned int
4133 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4137 * There's no way to directly query the max capacity from FW.
4138 * The maximal value on root table should be assumed to be supported.
4140 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4141 return MLX5_MAX_MODIFY_NUM;
4143 return MLX5_ROOT_TBL_MODIFY_NUM;
4147 * Validate the meter action.
4150 * Pointer to rte_eth_dev structure.
4151 * @param[in] action_flags
4152 * Bit-fields that holds the actions detected until now.
4154 * Pointer to the meter action.
4156 * Attributes of flow that includes this action.
4158 * Pointer to error structure.
4161 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4164 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4165 uint64_t action_flags,
4166 const struct rte_flow_action *action,
4167 const struct rte_flow_attr *attr,
4168 struct rte_flow_error *error)
4170 struct mlx5_priv *priv = dev->data->dev_private;
4171 const struct rte_flow_action_meter *am = action->conf;
4172 struct mlx5_flow_meter *fm;
4175 return rte_flow_error_set(error, EINVAL,
4176 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4177 "meter action conf is NULL");
4179 if (action_flags & MLX5_FLOW_ACTION_METER)
4180 return rte_flow_error_set(error, ENOTSUP,
4181 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182 "meter chaining not support");
4183 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4184 return rte_flow_error_set(error, ENOTSUP,
4185 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4186 "meter with jump not support");
4188 return rte_flow_error_set(error, ENOTSUP,
4189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4191 "meter action not supported");
4192 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4194 return rte_flow_error_set(error, EINVAL,
4195 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4197 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4198 (!fm->ingress && !attr->ingress && attr->egress) ||
4199 (!fm->egress && !attr->egress && attr->ingress))))
4200 return rte_flow_error_set(error, EINVAL,
4201 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4202 "Flow attributes are either invalid "
4203 "or have a conflict with current "
4204 "meter attributes");
4209 * Validate the age action.
4211 * @param[in] action_flags
4212 * Holds the actions detected until now.
4214 * Pointer to the age action.
4216 * Pointer to the Ethernet device structure.
4218 * Pointer to error structure.
4221 * 0 on success, a negative errno value otherwise and rte_errno is set.
4224 flow_dv_validate_action_age(uint64_t action_flags,
4225 const struct rte_flow_action *action,
4226 struct rte_eth_dev *dev,
4227 struct rte_flow_error *error)
4229 struct mlx5_priv *priv = dev->data->dev_private;
4230 const struct rte_flow_action_age *age = action->conf;
4232 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4233 !priv->sh->aso_age_mng))
4234 return rte_flow_error_set(error, ENOTSUP,
4235 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4237 "age action not supported");
4238 if (!(action->conf))
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION, action,
4241 "configuration cannot be null");
4242 if (!(age->timeout))
4243 return rte_flow_error_set(error, EINVAL,
4244 RTE_FLOW_ERROR_TYPE_ACTION, action,
4245 "invalid timeout value 0");
4246 if (action_flags & MLX5_FLOW_ACTION_AGE)
4247 return rte_flow_error_set(error, EINVAL,
4248 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4249 "duplicate age actions set");
4254 * Validate the modify-header IPv4 DSCP actions.
4256 * @param[in] action_flags
4257 * Holds the actions detected until now.
4259 * Pointer to the modify action.
4260 * @param[in] item_flags
4261 * Holds the items detected.
4263 * Pointer to error structure.
4266 * 0 on success, a negative errno value otherwise and rte_errno is set.
4269 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4270 const struct rte_flow_action *action,
4271 const uint64_t item_flags,
4272 struct rte_flow_error *error)
4276 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4278 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4279 return rte_flow_error_set(error, EINVAL,
4280 RTE_FLOW_ERROR_TYPE_ACTION,
4282 "no ipv4 item in pattern");
4288 * Validate the modify-header IPv6 DSCP actions.
4290 * @param[in] action_flags
4291 * Holds the actions detected until now.
4293 * Pointer to the modify action.
4294 * @param[in] item_flags
4295 * Holds the items detected.
4297 * Pointer to error structure.
4300 * 0 on success, a negative errno value otherwise and rte_errno is set.
4303 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4304 const struct rte_flow_action *action,
4305 const uint64_t item_flags,
4306 struct rte_flow_error *error)
4310 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4312 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4313 return rte_flow_error_set(error, EINVAL,
4314 RTE_FLOW_ERROR_TYPE_ACTION,
4316 "no ipv6 item in pattern");
4322 * Match modify-header resource.
4325 * Pointer to the hash list.
4327 * Pointer to exist resource entry object.
4329 * Key of the new entry.
4331 * Pointer to new modify-header resource.
4334 * 0 on matching, non-zero otherwise.
4337 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4338 struct mlx5_hlist_entry *entry,
4339 uint64_t key __rte_unused, void *cb_ctx)
4341 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4342 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4343 struct mlx5_flow_dv_modify_hdr_resource *resource =
4344 container_of(entry, typeof(*resource), entry);
4345 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4347 key_len += ref->actions_num * sizeof(ref->actions[0]);
4348 return ref->actions_num != resource->actions_num ||
4349 memcmp(&ref->ft_type, &resource->ft_type, key_len);
4352 struct mlx5_hlist_entry *
4353 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4356 struct mlx5_dev_ctx_shared *sh = list->ctx;
4357 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4358 struct mlx5dv_dr_domain *ns;
4359 struct mlx5_flow_dv_modify_hdr_resource *entry;
4360 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4362 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4363 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4365 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4368 rte_flow_error_set(ctx->error, ENOMEM,
4369 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4370 "cannot allocate resource memory");
4373 rte_memcpy(&entry->ft_type,
4374 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4375 key_len + data_len);
4376 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4377 ns = sh->fdb_domain;
4378 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4382 ret = mlx5_flow_os_create_flow_action_modify_header
4383 (sh->ctx, ns, entry,
4384 data_len, &entry->action);
4387 rte_flow_error_set(ctx->error, ENOMEM,
4388 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4389 NULL, "cannot create modification action");
4392 return &entry->entry;
4396 * Validate the sample action.
4398 * @param[in] action_flags
4399 * Holds the actions detected until now.
4401 * Pointer to the sample action.
4403 * Pointer to the Ethernet device structure.
4405 * Attributes of flow that includes this action.
4406 * @param[in] item_flags
4407 * Holds the items detected.
4409 * Pointer to the RSS action.
4410 * @param[out] sample_rss
4411 * Pointer to the RSS action in sample action list.
4413 * Pointer to error structure.
4416 * 0 on success, a negative errno value otherwise and rte_errno is set.
4419 flow_dv_validate_action_sample(uint64_t action_flags,
4420 const struct rte_flow_action *action,
4421 struct rte_eth_dev *dev,
4422 const struct rte_flow_attr *attr,
4423 uint64_t item_flags,
4424 const struct rte_flow_action_rss *rss,
4425 const struct rte_flow_action_rss **sample_rss,
4426 struct rte_flow_error *error)
4428 struct mlx5_priv *priv = dev->data->dev_private;
4429 struct mlx5_dev_config *dev_conf = &priv->config;
4430 const struct rte_flow_action_sample *sample = action->conf;
4431 const struct rte_flow_action *act;
4432 uint64_t sub_action_flags = 0;
4433 uint16_t queue_index = 0xFFFF;
4438 return rte_flow_error_set(error, EINVAL,
4439 RTE_FLOW_ERROR_TYPE_ACTION, action,
4440 "configuration cannot be NULL");
4441 if (sample->ratio == 0)
4442 return rte_flow_error_set(error, EINVAL,
4443 RTE_FLOW_ERROR_TYPE_ACTION, action,
4444 "ratio value starts from 1");
4445 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446 return rte_flow_error_set(error, ENOTSUP,
4447 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4449 "sample action not supported");
4450 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451 return rte_flow_error_set(error, EINVAL,
4452 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453 "Multiple sample actions not "
4455 if (action_flags & MLX5_FLOW_ACTION_METER)
4456 return rte_flow_error_set(error, EINVAL,
4457 RTE_FLOW_ERROR_TYPE_ACTION, action,
4458 "wrong action order, meter should "
4459 "be after sample action");
4460 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461 return rte_flow_error_set(error, EINVAL,
4462 RTE_FLOW_ERROR_TYPE_ACTION, action,
4463 "wrong action order, jump should "
4464 "be after sample action");
4465 act = sample->actions;
4466 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468 return rte_flow_error_set(error, ENOTSUP,
4469 RTE_FLOW_ERROR_TYPE_ACTION,
4470 act, "too many actions");
4471 switch (act->type) {
4472 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473 ret = mlx5_flow_validate_action_queue(act,
4479 queue_index = ((const struct rte_flow_action_queue *)
4480 (act->conf))->index;
4481 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4484 case RTE_FLOW_ACTION_TYPE_RSS:
4485 *sample_rss = act->conf;
4486 ret = mlx5_flow_validate_action_rss(act,
4493 if (rss && *sample_rss &&
4494 ((*sample_rss)->level != rss->level ||
4495 (*sample_rss)->types != rss->types))
4496 return rte_flow_error_set(error, ENOTSUP,
4497 RTE_FLOW_ERROR_TYPE_ACTION,
4499 "Can't use the different RSS types "
4500 "or level in the same flow");
4501 if (*sample_rss != NULL && (*sample_rss)->queue_num)
4502 queue_index = (*sample_rss)->queue[0];
4503 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
4506 case RTE_FLOW_ACTION_TYPE_MARK:
4507 ret = flow_dv_validate_action_mark(dev, act,
4512 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4513 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4514 MLX5_FLOW_ACTION_MARK_EXT;
4516 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4519 case RTE_FLOW_ACTION_TYPE_COUNT:
4520 ret = flow_dv_validate_action_count(dev, error);
4523 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4526 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4527 ret = flow_dv_validate_action_port_id(dev,
4534 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4537 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4538 ret = flow_dv_validate_action_raw_encap_decap
4539 (dev, NULL, act->conf, attr, &sub_action_flags,
4540 &actions_n, action, item_flags, error);
4546 return rte_flow_error_set(error, ENOTSUP,
4547 RTE_FLOW_ERROR_TYPE_ACTION,
4549 "Doesn't support optional "
4553 if (attr->ingress && !attr->transfer) {
4554 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
4555 MLX5_FLOW_ACTION_RSS)))
4556 return rte_flow_error_set(error, EINVAL,
4557 RTE_FLOW_ERROR_TYPE_ACTION,
4559 "Ingress must has a dest "
4560 "QUEUE for Sample");
4561 } else if (attr->egress && !attr->transfer) {
4562 return rte_flow_error_set(error, ENOTSUP,
4563 RTE_FLOW_ERROR_TYPE_ACTION,
4565 "Sample Only support Ingress "
4567 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4568 MLX5_ASSERT(attr->transfer);
4569 if (sample->ratio > 1)
4570 return rte_flow_error_set(error, ENOTSUP,
4571 RTE_FLOW_ERROR_TYPE_ACTION,
4573 "E-Switch doesn't support "
4574 "any optional action "
4576 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4577 return rte_flow_error_set(error, ENOTSUP,
4578 RTE_FLOW_ERROR_TYPE_ACTION,
4580 "unsupported action QUEUE");
4581 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
4582 return rte_flow_error_set(error, ENOTSUP,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "unsupported action QUEUE");
4586 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4587 return rte_flow_error_set(error, EINVAL,
4588 RTE_FLOW_ERROR_TYPE_ACTION,
4590 "E-Switch must has a dest "
4591 "port for mirroring");
4593 /* Continue validation for Xcap actions.*/
4594 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4595 (queue_index == 0xFFFF ||
4596 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4597 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4598 MLX5_FLOW_XCAP_ACTIONS)
4599 return rte_flow_error_set(error, ENOTSUP,
4600 RTE_FLOW_ERROR_TYPE_ACTION,
4601 NULL, "encap and decap "
4602 "combination aren't "
4604 if (!attr->transfer && attr->ingress && (sub_action_flags &
4605 MLX5_FLOW_ACTION_ENCAP))
4606 return rte_flow_error_set(error, ENOTSUP,
4607 RTE_FLOW_ERROR_TYPE_ACTION,
4608 NULL, "encap is not supported"
4609 " for ingress traffic");
4615 * Find existing modify-header resource or create and register a new one.
4617 * @param dev[in, out]
4618 * Pointer to rte_eth_dev structure.
4619 * @param[in, out] resource
4620 * Pointer to modify-header resource.
4621 * @parm[in, out] dev_flow
4622 * Pointer to the dev_flow.
4624 * pointer to error structure.
4627 * 0 on success otherwise -errno and errno is set.
4630 flow_dv_modify_hdr_resource_register
4631 (struct rte_eth_dev *dev,
4632 struct mlx5_flow_dv_modify_hdr_resource *resource,
4633 struct mlx5_flow *dev_flow,
4634 struct rte_flow_error *error)
4636 struct mlx5_priv *priv = dev->data->dev_private;
4637 struct mlx5_dev_ctx_shared *sh = priv->sh;
4638 uint32_t key_len = sizeof(*resource) -
4639 offsetof(typeof(*resource), ft_type) +
4640 resource->actions_num * sizeof(resource->actions[0]);
4641 struct mlx5_hlist_entry *entry;
4642 struct mlx5_flow_cb_ctx ctx = {
4648 resource->flags = dev_flow->dv.group ? 0 :
4649 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4650 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4652 return rte_flow_error_set(error, EOVERFLOW,
4653 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4654 "too many modify header items");
4655 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4656 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4659 resource = container_of(entry, typeof(*resource), entry);
4660 dev_flow->handle->dvh.modify_hdr = resource;
4665 * Get DV flow counter by index.
4668 * Pointer to the Ethernet device structure.
4670 * mlx5 flow counter index in the container.
4672 * mlx5 flow counter pool in the container,
4675 * Pointer to the counter, NULL otherwise.
4677 static struct mlx5_flow_counter *
4678 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4680 struct mlx5_flow_counter_pool **ppool)
4682 struct mlx5_priv *priv = dev->data->dev_private;
4683 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4684 struct mlx5_flow_counter_pool *pool;
4686 /* Decrease to original index and clear shared bit. */
4687 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4688 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4689 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4693 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4697 * Check the devx counter belongs to the pool.
4700 * Pointer to the counter pool.
4702 * The counter devx ID.
4705 * True if counter belongs to the pool, false otherwise.
4708 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4710 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4711 MLX5_COUNTERS_PER_POOL;
4713 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4719 * Get a pool by devx counter ID.
4722 * Pointer to the counter management.
4724 * The counter devx ID.
4727 * The counter pool pointer if exists, NULL otherwise,
4729 static struct mlx5_flow_counter_pool *
4730 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4733 struct mlx5_flow_counter_pool *pool = NULL;
4735 rte_spinlock_lock(&cmng->pool_update_sl);
4736 /* Check last used pool. */
4737 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4738 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4739 pool = cmng->pools[cmng->last_pool_idx];
4742 /* ID out of range means no suitable pool in the container. */
4743 if (id > cmng->max_id || id < cmng->min_id)
4746 * Find the pool from the end of the container, since mostly counter
4747 * ID is sequence increasing, and the last pool should be the needed
4752 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4754 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4760 rte_spinlock_unlock(&cmng->pool_update_sl);
4765 * Resize a counter container.
4768 * Pointer to the Ethernet device structure.
4771 * 0 on success, otherwise negative errno value and rte_errno is set.
4774 flow_dv_container_resize(struct rte_eth_dev *dev)
4776 struct mlx5_priv *priv = dev->data->dev_private;
4777 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4778 void *old_pools = cmng->pools;
4779 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4780 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4781 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4788 memcpy(pools, old_pools, cmng->n *
4789 sizeof(struct mlx5_flow_counter_pool *));
4791 cmng->pools = pools;
4793 mlx5_free(old_pools);
4798 * Query a devx flow counter.
4801 * Pointer to the Ethernet device structure.
4803 * Index to the flow counter.
4805 * The statistics value of packets.
4807 * The statistics value of bytes.
4810 * 0 on success, otherwise a negative errno value and rte_errno is set.
4813 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4816 struct mlx5_priv *priv = dev->data->dev_private;
4817 struct mlx5_flow_counter_pool *pool = NULL;
4818 struct mlx5_flow_counter *cnt;
4821 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4823 if (priv->sh->cmng.counter_fallback)
4824 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4825 0, pkts, bytes, 0, NULL, NULL, 0);
4826 rte_spinlock_lock(&pool->sl);
4831 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4832 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4833 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4835 rte_spinlock_unlock(&pool->sl);
4840 * Create and initialize a new counter pool.
4843 * Pointer to the Ethernet device structure.
4845 * The devX counter handle.
4847 * Whether the pool is for counter that was allocated for aging.
4848 * @param[in/out] cont_cur
4849 * Pointer to the container pointer, it will be update in pool resize.
4852 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4854 static struct mlx5_flow_counter_pool *
4855 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4858 struct mlx5_priv *priv = dev->data->dev_private;
4859 struct mlx5_flow_counter_pool *pool;
4860 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4861 bool fallback = priv->sh->cmng.counter_fallback;
4862 uint32_t size = sizeof(*pool);
4864 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4865 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4866 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4872 pool->is_aged = !!age;
4873 pool->query_gen = 0;
4874 pool->min_dcs = dcs;
4875 rte_spinlock_init(&pool->sl);
4876 rte_spinlock_init(&pool->csl);
4877 TAILQ_INIT(&pool->counters[0]);
4878 TAILQ_INIT(&pool->counters[1]);
4879 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4880 rte_spinlock_lock(&cmng->pool_update_sl);
4881 pool->index = cmng->n_valid;
4882 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4884 rte_spinlock_unlock(&cmng->pool_update_sl);
4887 cmng->pools[pool->index] = pool;
4889 if (unlikely(fallback)) {
4890 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4892 if (base < cmng->min_id)
4893 cmng->min_id = base;
4894 if (base > cmng->max_id)
4895 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4896 cmng->last_pool_idx = pool->index;
4898 rte_spinlock_unlock(&cmng->pool_update_sl);
4903 * Prepare a new counter and/or a new counter pool.
4906 * Pointer to the Ethernet device structure.
4907 * @param[out] cnt_free
4908 * Where to put the pointer of a new counter.
4910 * Whether the pool is for counter that was allocated for aging.
4913 * The counter pool pointer and @p cnt_free is set on success,
4914 * NULL otherwise and rte_errno is set.
4916 static struct mlx5_flow_counter_pool *
4917 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4918 struct mlx5_flow_counter **cnt_free,
4921 struct mlx5_priv *priv = dev->data->dev_private;
4922 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4923 struct mlx5_flow_counter_pool *pool;
4924 struct mlx5_counters tmp_tq;
4925 struct mlx5_devx_obj *dcs = NULL;
4926 struct mlx5_flow_counter *cnt;
4927 enum mlx5_counter_type cnt_type =
4928 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4929 bool fallback = priv->sh->cmng.counter_fallback;
4933 /* bulk_bitmap must be 0 for single counter allocation. */
4934 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4937 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4939 pool = flow_dv_pool_create(dev, dcs, age);
4941 mlx5_devx_cmd_destroy(dcs);
4945 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4946 cnt = MLX5_POOL_GET_CNT(pool, i);
4948 cnt->dcs_when_free = dcs;
4952 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4954 rte_errno = ENODATA;
4957 pool = flow_dv_pool_create(dev, dcs, age);
4959 mlx5_devx_cmd_destroy(dcs);
4962 TAILQ_INIT(&tmp_tq);
4963 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4964 cnt = MLX5_POOL_GET_CNT(pool, i);
4966 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4968 rte_spinlock_lock(&cmng->csl[cnt_type]);
4969 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4970 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4971 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4972 (*cnt_free)->pool = pool;
4977 * Allocate a flow counter.
4980 * Pointer to the Ethernet device structure.
4982 * Whether the counter was allocated for aging.
4985 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4988 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4990 struct mlx5_priv *priv = dev->data->dev_private;
4991 struct mlx5_flow_counter_pool *pool = NULL;
4992 struct mlx5_flow_counter *cnt_free = NULL;
4993 bool fallback = priv->sh->cmng.counter_fallback;
4994 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4995 enum mlx5_counter_type cnt_type =
4996 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4999 if (!priv->config.devx) {
5000 rte_errno = ENOTSUP;
5003 /* Get free counters from container. */
5004 rte_spinlock_lock(&cmng->csl[cnt_type]);
5005 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5007 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5008 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5009 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5011 pool = cnt_free->pool;
5013 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5014 /* Create a DV counter action only in the first time usage. */
5015 if (!cnt_free->action) {
5017 struct mlx5_devx_obj *dcs;
5021 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5022 dcs = pool->min_dcs;
5025 dcs = cnt_free->dcs_when_free;
5027 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5034 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5035 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5036 /* Update the counter reset values. */
5037 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5040 if (!fallback && !priv->sh->cmng.query_thread_on)
5041 /* Start the asynchronous batch query by the host thread. */
5042 mlx5_set_query_alarm(priv->sh);
5046 cnt_free->pool = pool;
5048 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5049 rte_spinlock_lock(&cmng->csl[cnt_type]);
5050 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5051 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5057 * Allocate a shared flow counter.
5060 * Pointer to the shared counter configuration.
5062 * Pointer to save the allocated counter index.
5065 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5069 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5071 struct mlx5_shared_counter_conf *conf = ctx;
5072 struct rte_eth_dev *dev = conf->dev;
5073 struct mlx5_flow_counter *cnt;
5075 data->dword = flow_dv_counter_alloc(dev, 0);
5076 data->dword |= MLX5_CNT_SHARED_OFFSET;
5077 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5078 cnt->shared_info.id = conf->id;
5083 * Get a shared flow counter.
5086 * Pointer to the Ethernet device structure.
5088 * Counter identifier.
5091 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5094 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5096 struct mlx5_priv *priv = dev->data->dev_private;
5097 struct mlx5_shared_counter_conf conf = {
5101 union mlx5_l3t_data data = {
5105 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5106 flow_dv_counter_alloc_shared_cb, &conf);
5111 * Get age param from counter index.
5114 * Pointer to the Ethernet device structure.
5115 * @param[in] counter
5116 * Index to the counter handler.
5119 * The aging parameter specified for the counter index.
5121 static struct mlx5_age_param*
5122 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5125 struct mlx5_flow_counter *cnt;
5126 struct mlx5_flow_counter_pool *pool = NULL;
5128 flow_dv_counter_get_by_idx(dev, counter, &pool);
5129 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5130 cnt = MLX5_POOL_GET_CNT(pool, counter);
5131 return MLX5_CNT_TO_AGE(cnt);
5135 * Remove a flow counter from aged counter list.
5138 * Pointer to the Ethernet device structure.
5139 * @param[in] counter
5140 * Index to the counter handler.
5142 * Pointer to the counter handler.
5145 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5146 uint32_t counter, struct mlx5_flow_counter *cnt)
5148 struct mlx5_age_info *age_info;
5149 struct mlx5_age_param *age_param;
5150 struct mlx5_priv *priv = dev->data->dev_private;
5151 uint16_t expected = AGE_CANDIDATE;
5153 age_info = GET_PORT_AGE_INFO(priv);
5154 age_param = flow_dv_counter_idx_get_age(dev, counter);
5155 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5156 AGE_FREE, false, __ATOMIC_RELAXED,
5157 __ATOMIC_RELAXED)) {
5159 * We need the lock even it is age timeout,
5160 * since counter may still in process.
5162 rte_spinlock_lock(&age_info->aged_sl);
5163 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5164 rte_spinlock_unlock(&age_info->aged_sl);
5165 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5170 * Release a flow counter.
5173 * Pointer to the Ethernet device structure.
5174 * @param[in] counter
5175 * Index to the counter handler.
5178 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5180 struct mlx5_priv *priv = dev->data->dev_private;
5181 struct mlx5_flow_counter_pool *pool = NULL;
5182 struct mlx5_flow_counter *cnt;
5183 enum mlx5_counter_type cnt_type;
5187 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5189 if (IS_SHARED_CNT(counter) &&
5190 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5193 flow_dv_counter_remove_from_age(dev, counter, cnt);
5196 * Put the counter back to list to be updated in none fallback mode.
5197 * Currently, we are using two list alternately, while one is in query,
5198 * add the freed counter to the other list based on the pool query_gen
5199 * value. After query finishes, add counter the list to the global
5200 * container counter list. The list changes while query starts. In
5201 * this case, lock will not be needed as query callback and release
5202 * function both operate with the different list.
5205 if (!priv->sh->cmng.counter_fallback) {
5206 rte_spinlock_lock(&pool->csl);
5207 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5208 rte_spinlock_unlock(&pool->csl);
5210 cnt->dcs_when_free = cnt->dcs_when_active;
5211 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5212 MLX5_COUNTER_TYPE_ORIGIN;
5213 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5214 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5216 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5221 * Verify the @p attributes will be correctly understood by the NIC and store
5222 * them in the @p flow if everything is correct.
5225 * Pointer to dev struct.
5226 * @param[in] attributes
5227 * Pointer to flow attributes
5228 * @param[in] external
5229 * This flow rule is created by request external to PMD.
5231 * Pointer to error structure.
5234 * - 0 on success and non root table.
5235 * - 1 on success and root table.
5236 * - a negative errno value otherwise and rte_errno is set.
5239 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5240 const struct mlx5_flow_tunnel *tunnel,
5241 const struct rte_flow_attr *attributes,
5242 const struct flow_grp_info *grp_info,
5243 struct rte_flow_error *error)
5245 struct mlx5_priv *priv = dev->data->dev_private;
5246 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5249 #ifndef HAVE_MLX5DV_DR
5250 RTE_SET_USED(tunnel);
5251 RTE_SET_USED(grp_info);
5252 if (attributes->group)
5253 return rte_flow_error_set(error, ENOTSUP,
5254 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5256 "groups are not supported");
5260 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5265 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5267 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5268 attributes->priority > lowest_priority)
5269 return rte_flow_error_set(error, ENOTSUP,
5270 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5272 "priority out of range");
5273 if (attributes->transfer) {
5274 if (!priv->config.dv_esw_en)
5275 return rte_flow_error_set
5277 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5278 "E-Switch dr is not supported");
5279 if (!(priv->representor || priv->master))
5280 return rte_flow_error_set
5281 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5282 NULL, "E-Switch configuration can only be"
5283 " done by a master or a representor device");
5284 if (attributes->egress)
5285 return rte_flow_error_set
5287 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5288 "egress is not supported");
5290 if (!(attributes->egress ^ attributes->ingress))
5291 return rte_flow_error_set(error, ENOTSUP,
5292 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5293 "must specify exactly one of "
5294 "ingress or egress");
5299 * Internal validation function. For validating both actions and items.
5302 * Pointer to the rte_eth_dev structure.
5304 * Pointer to the flow attributes.
5306 * Pointer to the list of items.
5307 * @param[in] actions
5308 * Pointer to the list of actions.
5309 * @param[in] external
5310 * This flow rule is created by request external to PMD.
5311 * @param[in] hairpin
5312 * Number of hairpin TX actions, 0 means classic flow.
5314 * Pointer to the error structure.
5317 * 0 on success, a negative errno value otherwise and rte_errno is set.
5320 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5321 const struct rte_flow_item items[],
5322 const struct rte_flow_action actions[],
5323 bool external, int hairpin, struct rte_flow_error *error)
5326 uint64_t action_flags = 0;
5327 uint64_t item_flags = 0;
5328 uint64_t last_item = 0;
5329 uint8_t next_protocol = 0xff;
5330 uint16_t ether_type = 0;
5332 uint8_t item_ipv6_proto = 0;
5333 const struct rte_flow_item *geneve_item = NULL;
5334 const struct rte_flow_item *gre_item = NULL;
5335 const struct rte_flow_item *gtp_item = NULL;
5336 const struct rte_flow_action_raw_decap *decap;
5337 const struct rte_flow_action_raw_encap *encap;
5338 const struct rte_flow_action_rss *rss = NULL;
5339 const struct rte_flow_action_rss *sample_rss = NULL;
5340 const struct rte_flow_item_tcp nic_tcp_mask = {
5343 .src_port = RTE_BE16(UINT16_MAX),
5344 .dst_port = RTE_BE16(UINT16_MAX),
5347 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5350 "\xff\xff\xff\xff\xff\xff\xff\xff"
5351 "\xff\xff\xff\xff\xff\xff\xff\xff",
5353 "\xff\xff\xff\xff\xff\xff\xff\xff"
5354 "\xff\xff\xff\xff\xff\xff\xff\xff",
5355 .vtc_flow = RTE_BE32(0xffffffff),
5361 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5365 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5369 .dummy[0] = 0xffffffff,
5372 struct mlx5_priv *priv = dev->data->dev_private;
5373 struct mlx5_dev_config *dev_conf = &priv->config;
5374 uint16_t queue_index = 0xFFFF;
5375 const struct rte_flow_item_vlan *vlan_m = NULL;
5376 int16_t rw_act_num = 0;
5378 const struct mlx5_flow_tunnel *tunnel;
5379 struct flow_grp_info grp_info = {
5380 .external = !!external,
5381 .transfer = !!attr->transfer,
5382 .fdb_def_rule = !!priv->fdb_def_rule,
5384 const struct rte_eth_hairpin_conf *conf;
5388 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5389 tunnel = flow_items_to_tunnel(items);
5390 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5391 MLX5_FLOW_ACTION_DECAP;
5392 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5393 tunnel = flow_actions_to_tunnel(actions);
5394 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5398 if (tunnel && priv->representor)
5399 return rte_flow_error_set(error, ENOTSUP,
5400 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5401 "decap not supported "
5402 "for VF representor");
5403 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5404 (dev, tunnel, attr, items, actions);
5405 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5408 is_root = (uint64_t)ret;
5409 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5410 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5411 int type = items->type;
5413 if (!mlx5_flow_os_item_supported(type))
5414 return rte_flow_error_set(error, ENOTSUP,
5415 RTE_FLOW_ERROR_TYPE_ITEM,
5416 NULL, "item not supported");
5418 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5419 if (items[0].type != (typeof(items[0].type))
5420 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5421 return rte_flow_error_set
5423 RTE_FLOW_ERROR_TYPE_ITEM,
5424 NULL, "MLX5 private items "
5425 "must be the first");
5427 case RTE_FLOW_ITEM_TYPE_VOID:
5429 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5430 ret = flow_dv_validate_item_port_id
5431 (dev, items, attr, item_flags, error);
5434 last_item = MLX5_FLOW_ITEM_PORT_ID;
5436 case RTE_FLOW_ITEM_TYPE_ETH:
5437 ret = mlx5_flow_validate_item_eth(items, item_flags,
5441 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5442 MLX5_FLOW_LAYER_OUTER_L2;
5443 if (items->mask != NULL && items->spec != NULL) {
5445 ((const struct rte_flow_item_eth *)
5448 ((const struct rte_flow_item_eth *)
5450 ether_type = rte_be_to_cpu_16(ether_type);
5455 case RTE_FLOW_ITEM_TYPE_VLAN:
5456 ret = flow_dv_validate_item_vlan(items, item_flags,
5460 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5461 MLX5_FLOW_LAYER_OUTER_VLAN;
5462 if (items->mask != NULL && items->spec != NULL) {
5464 ((const struct rte_flow_item_vlan *)
5465 items->spec)->inner_type;
5467 ((const struct rte_flow_item_vlan *)
5468 items->mask)->inner_type;
5469 ether_type = rte_be_to_cpu_16(ether_type);
5473 /* Store outer VLAN mask for of_push_vlan action. */
5475 vlan_m = items->mask;
5477 case RTE_FLOW_ITEM_TYPE_IPV4:
5478 mlx5_flow_tunnel_ip_check(items, next_protocol,
5479 &item_flags, &tunnel);
5480 ret = flow_dv_validate_item_ipv4(items, item_flags,
5481 last_item, ether_type,
5485 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5486 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5487 if (items->mask != NULL &&
5488 ((const struct rte_flow_item_ipv4 *)
5489 items->mask)->hdr.next_proto_id) {
5491 ((const struct rte_flow_item_ipv4 *)
5492 (items->spec))->hdr.next_proto_id;
5494 ((const struct rte_flow_item_ipv4 *)
5495 (items->mask))->hdr.next_proto_id;
5497 /* Reset for inner layer. */
5498 next_protocol = 0xff;
5501 case RTE_FLOW_ITEM_TYPE_IPV6:
5502 mlx5_flow_tunnel_ip_check(items, next_protocol,
5503 &item_flags, &tunnel);
5504 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5511 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5512 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5513 if (items->mask != NULL &&
5514 ((const struct rte_flow_item_ipv6 *)
5515 items->mask)->hdr.proto) {
5517 ((const struct rte_flow_item_ipv6 *)
5518 items->spec)->hdr.proto;
5520 ((const struct rte_flow_item_ipv6 *)
5521 items->spec)->hdr.proto;
5523 ((const struct rte_flow_item_ipv6 *)
5524 items->mask)->hdr.proto;
5526 /* Reset for inner layer. */
5527 next_protocol = 0xff;
5530 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5531 ret = flow_dv_validate_item_ipv6_frag_ext(items,
5536 last_item = tunnel ?
5537 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5538 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5539 if (items->mask != NULL &&
5540 ((const struct rte_flow_item_ipv6_frag_ext *)
5541 items->mask)->hdr.next_header) {
5543 ((const struct rte_flow_item_ipv6_frag_ext *)
5544 items->spec)->hdr.next_header;
5546 ((const struct rte_flow_item_ipv6_frag_ext *)
5547 items->mask)->hdr.next_header;
5549 /* Reset for inner layer. */
5550 next_protocol = 0xff;
5553 case RTE_FLOW_ITEM_TYPE_TCP:
5554 ret = mlx5_flow_validate_item_tcp
5561 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5562 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5564 case RTE_FLOW_ITEM_TYPE_UDP:
5565 ret = mlx5_flow_validate_item_udp(items, item_flags,
5570 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5571 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5573 case RTE_FLOW_ITEM_TYPE_GRE:
5574 ret = mlx5_flow_validate_item_gre(items, item_flags,
5575 next_protocol, error);
5579 last_item = MLX5_FLOW_LAYER_GRE;
5581 case RTE_FLOW_ITEM_TYPE_NVGRE:
5582 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5587 last_item = MLX5_FLOW_LAYER_NVGRE;
5589 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5590 ret = mlx5_flow_validate_item_gre_key
5591 (items, item_flags, gre_item, error);
5594 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5596 case RTE_FLOW_ITEM_TYPE_VXLAN:
5597 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5601 last_item = MLX5_FLOW_LAYER_VXLAN;
5603 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5604 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5609 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5611 case RTE_FLOW_ITEM_TYPE_GENEVE:
5612 ret = mlx5_flow_validate_item_geneve(items,
5617 geneve_item = items;
5618 last_item = MLX5_FLOW_LAYER_GENEVE;
5620 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5621 ret = mlx5_flow_validate_item_geneve_opt(items,
5628 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5630 case RTE_FLOW_ITEM_TYPE_MPLS:
5631 ret = mlx5_flow_validate_item_mpls(dev, items,
5636 last_item = MLX5_FLOW_LAYER_MPLS;
5639 case RTE_FLOW_ITEM_TYPE_MARK:
5640 ret = flow_dv_validate_item_mark(dev, items, attr,
5644 last_item = MLX5_FLOW_ITEM_MARK;
5646 case RTE_FLOW_ITEM_TYPE_META:
5647 ret = flow_dv_validate_item_meta(dev, items, attr,
5651 last_item = MLX5_FLOW_ITEM_METADATA;
5653 case RTE_FLOW_ITEM_TYPE_ICMP:
5654 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5659 last_item = MLX5_FLOW_LAYER_ICMP;
5661 case RTE_FLOW_ITEM_TYPE_ICMP6:
5662 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5667 item_ipv6_proto = IPPROTO_ICMPV6;
5668 last_item = MLX5_FLOW_LAYER_ICMP6;
5670 case RTE_FLOW_ITEM_TYPE_TAG:
5671 ret = flow_dv_validate_item_tag(dev, items,
5675 last_item = MLX5_FLOW_ITEM_TAG;
5677 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5678 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5680 case RTE_FLOW_ITEM_TYPE_GTP:
5681 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5686 last_item = MLX5_FLOW_LAYER_GTP;
5688 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5689 ret = flow_dv_validate_item_gtp_psc(items, last_item,
5694 last_item = MLX5_FLOW_LAYER_GTP_PSC;
5696 case RTE_FLOW_ITEM_TYPE_ECPRI:
5697 /* Capacity will be checked in the translate stage. */
5698 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5705 last_item = MLX5_FLOW_LAYER_ECPRI;
5708 return rte_flow_error_set(error, ENOTSUP,
5709 RTE_FLOW_ERROR_TYPE_ITEM,
5710 NULL, "item not supported");
5712 item_flags |= last_item;
5714 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5715 int type = actions->type;
5717 if (!mlx5_flow_os_action_supported(type))
5718 return rte_flow_error_set(error, ENOTSUP,
5719 RTE_FLOW_ERROR_TYPE_ACTION,
5721 "action not supported");
5722 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5723 return rte_flow_error_set(error, ENOTSUP,
5724 RTE_FLOW_ERROR_TYPE_ACTION,
5725 actions, "too many actions");
5727 case RTE_FLOW_ACTION_TYPE_VOID:
5729 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5730 ret = flow_dv_validate_action_port_id(dev,
5737 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5740 case RTE_FLOW_ACTION_TYPE_FLAG:
5741 ret = flow_dv_validate_action_flag(dev, action_flags,
5745 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5746 /* Count all modify-header actions as one. */
5747 if (!(action_flags &
5748 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5750 action_flags |= MLX5_FLOW_ACTION_FLAG |
5751 MLX5_FLOW_ACTION_MARK_EXT;
5753 action_flags |= MLX5_FLOW_ACTION_FLAG;
5756 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5758 case RTE_FLOW_ACTION_TYPE_MARK:
5759 ret = flow_dv_validate_action_mark(dev, actions,
5764 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5765 /* Count all modify-header actions as one. */
5766 if (!(action_flags &
5767 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5769 action_flags |= MLX5_FLOW_ACTION_MARK |
5770 MLX5_FLOW_ACTION_MARK_EXT;
5772 action_flags |= MLX5_FLOW_ACTION_MARK;
5775 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5777 case RTE_FLOW_ACTION_TYPE_SET_META:
5778 ret = flow_dv_validate_action_set_meta(dev, actions,
5783 /* Count all modify-header actions as one action. */
5784 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5786 action_flags |= MLX5_FLOW_ACTION_SET_META;
5787 rw_act_num += MLX5_ACT_NUM_SET_META;
5789 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5790 ret = flow_dv_validate_action_set_tag(dev, actions,
5795 /* Count all modify-header actions as one action. */
5796 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5798 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5799 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5801 case RTE_FLOW_ACTION_TYPE_DROP:
5802 ret = mlx5_flow_validate_action_drop(action_flags,
5806 action_flags |= MLX5_FLOW_ACTION_DROP;
5809 case RTE_FLOW_ACTION_TYPE_QUEUE:
5810 ret = mlx5_flow_validate_action_queue(actions,
5815 queue_index = ((const struct rte_flow_action_queue *)
5816 (actions->conf))->index;
5817 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5820 case RTE_FLOW_ACTION_TYPE_RSS:
5821 rss = actions->conf;
5822 ret = mlx5_flow_validate_action_rss(actions,
5828 if (rss && sample_rss &&
5829 (sample_rss->level != rss->level ||
5830 sample_rss->types != rss->types))
5831 return rte_flow_error_set(error, ENOTSUP,
5832 RTE_FLOW_ERROR_TYPE_ACTION,
5834 "Can't use the different RSS types "
5835 "or level in the same flow");
5836 if (rss != NULL && rss->queue_num)
5837 queue_index = rss->queue[0];
5838 action_flags |= MLX5_FLOW_ACTION_RSS;
5841 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5843 mlx5_flow_validate_action_default_miss(action_flags,
5847 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5850 case RTE_FLOW_ACTION_TYPE_COUNT:
5851 ret = flow_dv_validate_action_count(dev, error);
5854 action_flags |= MLX5_FLOW_ACTION_COUNT;
5857 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5858 if (flow_dv_validate_action_pop_vlan(dev,
5864 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5867 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5868 ret = flow_dv_validate_action_push_vlan(dev,
5875 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5878 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5879 ret = flow_dv_validate_action_set_vlan_pcp
5880 (action_flags, actions, error);
5883 /* Count PCP with push_vlan command. */
5884 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5886 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5887 ret = flow_dv_validate_action_set_vlan_vid
5888 (item_flags, action_flags,
5892 /* Count VID with push_vlan command. */
5893 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5894 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5896 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5897 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5898 ret = flow_dv_validate_action_l2_encap(dev,
5904 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5907 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5908 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5909 ret = flow_dv_validate_action_decap(dev, action_flags,
5910 actions, item_flags,
5914 action_flags |= MLX5_FLOW_ACTION_DECAP;
5917 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5918 ret = flow_dv_validate_action_raw_encap_decap
5919 (dev, NULL, actions->conf, attr, &action_flags,
5920 &actions_n, actions, item_flags, error);
5924 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5925 decap = actions->conf;
5926 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5928 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5932 encap = actions->conf;
5934 ret = flow_dv_validate_action_raw_encap_decap
5936 decap ? decap : &empty_decap, encap,
5937 attr, &action_flags, &actions_n,
5938 actions, item_flags, error);
5942 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5943 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5944 ret = flow_dv_validate_action_modify_mac(action_flags,
5950 /* Count all modify-header actions as one action. */
5951 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5953 action_flags |= actions->type ==
5954 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5955 MLX5_FLOW_ACTION_SET_MAC_SRC :
5956 MLX5_FLOW_ACTION_SET_MAC_DST;
5958 * Even if the source and destination MAC addresses have
5959 * overlap in the header with 4B alignment, the convert
5960 * function will handle them separately and 4 SW actions
5961 * will be created. And 2 actions will be added each
5962 * time no matter how many bytes of address will be set.
5964 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5966 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5967 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5968 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5974 /* Count all modify-header actions as one action. */
5975 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5977 action_flags |= actions->type ==
5978 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5979 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5980 MLX5_FLOW_ACTION_SET_IPV4_DST;
5981 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5983 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5984 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5985 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5991 if (item_ipv6_proto == IPPROTO_ICMPV6)
5992 return rte_flow_error_set(error, ENOTSUP,
5993 RTE_FLOW_ERROR_TYPE_ACTION,
5995 "Can't change header "
5996 "with ICMPv6 proto");
5997 /* Count all modify-header actions as one action. */
5998 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6000 action_flags |= actions->type ==
6001 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6002 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6003 MLX5_FLOW_ACTION_SET_IPV6_DST;
6004 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6006 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6007 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6008 ret = flow_dv_validate_action_modify_tp(action_flags,
6014 /* Count all modify-header actions as one action. */
6015 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6017 action_flags |= actions->type ==
6018 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6019 MLX5_FLOW_ACTION_SET_TP_SRC :
6020 MLX5_FLOW_ACTION_SET_TP_DST;
6021 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6023 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6024 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6025 ret = flow_dv_validate_action_modify_ttl(action_flags,
6031 /* Count all modify-header actions as one action. */
6032 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6034 action_flags |= actions->type ==
6035 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6036 MLX5_FLOW_ACTION_SET_TTL :
6037 MLX5_FLOW_ACTION_DEC_TTL;
6038 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6040 case RTE_FLOW_ACTION_TYPE_JUMP:
6041 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6048 action_flags |= MLX5_FLOW_ACTION_JUMP;
6050 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6051 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6052 ret = flow_dv_validate_action_modify_tcp_seq
6059 /* Count all modify-header actions as one action. */
6060 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6062 action_flags |= actions->type ==
6063 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6064 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6065 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6066 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6068 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6069 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6070 ret = flow_dv_validate_action_modify_tcp_ack
6077 /* Count all modify-header actions as one action. */
6078 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6080 action_flags |= actions->type ==
6081 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6082 MLX5_FLOW_ACTION_INC_TCP_ACK :
6083 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6084 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6086 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6088 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6089 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6090 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6092 case RTE_FLOW_ACTION_TYPE_METER:
6093 ret = mlx5_flow_validate_action_meter(dev,
6099 action_flags |= MLX5_FLOW_ACTION_METER;
6101 /* Meter action will add one more TAG action. */
6102 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6104 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6105 if (!attr->transfer && !attr->group)
6106 return rte_flow_error_set(error, ENOTSUP,
6107 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6109 "Shared ASO age action is not supported for group 0");
6110 action_flags |= MLX5_FLOW_ACTION_AGE;
6113 case RTE_FLOW_ACTION_TYPE_AGE:
6114 ret = flow_dv_validate_action_age(action_flags,
6119 action_flags |= MLX5_FLOW_ACTION_AGE;
6122 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6123 ret = flow_dv_validate_action_modify_ipv4_dscp
6130 /* Count all modify-header actions as one action. */
6131 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6133 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6134 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6136 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6137 ret = flow_dv_validate_action_modify_ipv6_dscp
6144 /* Count all modify-header actions as one action. */
6145 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6147 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6148 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6150 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6151 ret = flow_dv_validate_action_sample(action_flags,
6158 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6161 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6162 if (actions[0].type != (typeof(actions[0].type))
6163 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6164 return rte_flow_error_set
6166 RTE_FLOW_ERROR_TYPE_ACTION,
6167 NULL, "MLX5 private action "
6168 "must be the first");
6170 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6173 return rte_flow_error_set(error, ENOTSUP,
6174 RTE_FLOW_ERROR_TYPE_ACTION,
6176 "action not supported");
6180 * Validate actions in flow rules
6181 * - Explicit decap action is prohibited by the tunnel offload API.
6182 * - Drop action in tunnel steer rule is prohibited by the API.
6183 * - Application cannot use MARK action because it's value can mask
6184 * tunnel default miss nitification.
6185 * - JUMP in tunnel match rule has no support in current PMD
6187 * - TAG & META are reserved for future uses.
6189 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6190 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6191 MLX5_FLOW_ACTION_MARK |
6192 MLX5_FLOW_ACTION_SET_TAG |
6193 MLX5_FLOW_ACTION_SET_META |
6194 MLX5_FLOW_ACTION_DROP;
6196 if (action_flags & bad_actions_mask)
6197 return rte_flow_error_set
6199 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6200 "Invalid RTE action in tunnel "
6202 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6203 return rte_flow_error_set
6205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6206 "tunnel set decap rule must terminate "
6209 return rte_flow_error_set
6211 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6212 "tunnel flows for ingress traffic only");
6214 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6215 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6216 MLX5_FLOW_ACTION_MARK |
6217 MLX5_FLOW_ACTION_SET_TAG |
6218 MLX5_FLOW_ACTION_SET_META;
6220 if (action_flags & bad_actions_mask)
6221 return rte_flow_error_set
6223 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6224 "Invalid RTE action in tunnel "
6228 * Validate the drop action mutual exclusion with other actions.
6229 * Drop action is mutually-exclusive with any other action, except for
6231 * Drop action compatibility with tunnel offload was already validated.
6233 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
6234 MLX5_FLOW_ACTION_TUNNEL_MATCH));
6235 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6236 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6237 return rte_flow_error_set(error, EINVAL,
6238 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6239 "Drop action is mutually-exclusive "
6240 "with any other action, except for "
6242 /* Eswitch has few restrictions on using items and actions */
6243 if (attr->transfer) {
6244 if (!mlx5_flow_ext_mreg_supported(dev) &&
6245 action_flags & MLX5_FLOW_ACTION_FLAG)
6246 return rte_flow_error_set(error, ENOTSUP,
6247 RTE_FLOW_ERROR_TYPE_ACTION,
6249 "unsupported action FLAG");
6250 if (!mlx5_flow_ext_mreg_supported(dev) &&
6251 action_flags & MLX5_FLOW_ACTION_MARK)
6252 return rte_flow_error_set(error, ENOTSUP,
6253 RTE_FLOW_ERROR_TYPE_ACTION,
6255 "unsupported action MARK");
6256 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6257 return rte_flow_error_set(error, ENOTSUP,
6258 RTE_FLOW_ERROR_TYPE_ACTION,
6260 "unsupported action QUEUE");
6261 if (action_flags & MLX5_FLOW_ACTION_RSS)
6262 return rte_flow_error_set(error, ENOTSUP,
6263 RTE_FLOW_ERROR_TYPE_ACTION,
6265 "unsupported action RSS");
6266 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6267 return rte_flow_error_set(error, EINVAL,
6268 RTE_FLOW_ERROR_TYPE_ACTION,
6270 "no fate action is found");
6272 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6273 return rte_flow_error_set(error, EINVAL,
6274 RTE_FLOW_ERROR_TYPE_ACTION,
6276 "no fate action is found");
6279 * Continue validation for Xcap and VLAN actions.
6280 * If hairpin is working in explicit TX rule mode, there is no actions
6281 * splitting and the validation of hairpin ingress flow should be the
6282 * same as other standard flows.
6284 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6285 MLX5_FLOW_VLAN_ACTIONS)) &&
6286 (queue_index == 0xFFFF ||
6287 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6288 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6289 conf->tx_explicit != 0))) {
6290 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6291 MLX5_FLOW_XCAP_ACTIONS)
6292 return rte_flow_error_set(error, ENOTSUP,
6293 RTE_FLOW_ERROR_TYPE_ACTION,
6294 NULL, "encap and decap "
6295 "combination aren't supported");
6296 if (!attr->transfer && attr->ingress) {
6297 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6298 return rte_flow_error_set
6300 RTE_FLOW_ERROR_TYPE_ACTION,
6301 NULL, "encap is not supported"
6302 " for ingress traffic");
6303 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6304 return rte_flow_error_set
6306 RTE_FLOW_ERROR_TYPE_ACTION,
6307 NULL, "push VLAN action not "
6308 "supported for ingress");
6309 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6310 MLX5_FLOW_VLAN_ACTIONS)
6311 return rte_flow_error_set
6313 RTE_FLOW_ERROR_TYPE_ACTION,
6314 NULL, "no support for "
6315 "multiple VLAN actions");
6319 * Hairpin flow will add one more TAG action in TX implicit mode.
6320 * In TX explicit mode, there will be no hairpin flow ID.
6323 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6324 /* extra metadata enabled: one more TAG action will be add. */
6325 if (dev_conf->dv_flow_en &&
6326 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6327 mlx5_flow_ext_mreg_supported(dev))
6328 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6329 if ((uint32_t)rw_act_num >
6330 flow_dv_modify_hdr_action_max(dev, is_root)) {
6331 return rte_flow_error_set(error, ENOTSUP,
6332 RTE_FLOW_ERROR_TYPE_ACTION,
6333 NULL, "too many header modify"
6334 " actions to support");
6340 * Internal preparation function. Allocates the DV flow size,
6341 * this size is constant.
6344 * Pointer to the rte_eth_dev structure.
6346 * Pointer to the flow attributes.
6348 * Pointer to the list of items.
6349 * @param[in] actions
6350 * Pointer to the list of actions.
6352 * Pointer to the error structure.
6355 * Pointer to mlx5_flow object on success,
6356 * otherwise NULL and rte_errno is set.
6358 static struct mlx5_flow *
6359 flow_dv_prepare(struct rte_eth_dev *dev,
6360 const struct rte_flow_attr *attr __rte_unused,
6361 const struct rte_flow_item items[] __rte_unused,
6362 const struct rte_flow_action actions[] __rte_unused,
6363 struct rte_flow_error *error)
6365 uint32_t handle_idx = 0;
6366 struct mlx5_flow *dev_flow;
6367 struct mlx5_flow_handle *dev_handle;
6368 struct mlx5_priv *priv = dev->data->dev_private;
6369 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6372 /* In case of corrupting the memory. */
6373 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6374 rte_flow_error_set(error, ENOSPC,
6375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6376 "not free temporary device flow");
6379 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6382 rte_flow_error_set(error, ENOMEM,
6383 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6384 "not enough memory to create flow handle");
6387 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6388 dev_flow = &wks->flows[wks->flow_idx++];
6389 memset(dev_flow, 0, sizeof(*dev_flow));
6390 dev_flow->handle = dev_handle;
6391 dev_flow->handle_idx = handle_idx;
6393 * In some old rdma-core releases, before continuing, a check of the
6394 * length of matching parameter will be done at first. It needs to use
6395 * the length without misc4 param. If the flow has misc4 support, then
6396 * the length needs to be adjusted accordingly. Each param member is
6397 * aligned with a 64B boundary naturally.
6399 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6400 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6401 dev_flow->ingress = attr->ingress;
6402 dev_flow->dv.transfer = attr->transfer;
6406 #ifdef RTE_LIBRTE_MLX5_DEBUG
6408 * Sanity check for match mask and value. Similar to check_valid_spec() in
6409 * kernel driver. If unmasked bit is present in value, it returns failure.
6412 * pointer to match mask buffer.
6413 * @param match_value
6414 * pointer to match value buffer.
6417 * 0 if valid, -EINVAL otherwise.
6420 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6422 uint8_t *m = match_mask;
6423 uint8_t *v = match_value;
6426 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6429 "match_value differs from match_criteria"
6430 " %p[%u] != %p[%u]",
6431 match_value, i, match_mask, i);
6440 * Add match of ip_version.
6444 * @param[in] headers_v
6445 * Values header pointer.
6446 * @param[in] headers_m
6447 * Masks header pointer.
6448 * @param[in] ip_version
6449 * The IP version to set.
6452 flow_dv_set_match_ip_version(uint32_t group,
6458 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6460 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6462 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6463 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6464 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6468 * Add Ethernet item to matcher and to the value.
6470 * @param[in, out] matcher
6472 * @param[in, out] key
6473 * Flow matcher value.
6475 * Flow pattern to translate.
6477 * Item is inner pattern.
6480 flow_dv_translate_item_eth(void *matcher, void *key,
6481 const struct rte_flow_item *item, int inner,
6484 const struct rte_flow_item_eth *eth_m = item->mask;
6485 const struct rte_flow_item_eth *eth_v = item->spec;
6486 const struct rte_flow_item_eth nic_mask = {
6487 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6488 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6489 .type = RTE_BE16(0xffff),
6502 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6504 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6506 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6508 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6510 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6511 ð_m->dst, sizeof(eth_m->dst));
6512 /* The value must be in the range of the mask. */
6513 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6514 for (i = 0; i < sizeof(eth_m->dst); ++i)
6515 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6516 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6517 ð_m->src, sizeof(eth_m->src));
6518 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6519 /* The value must be in the range of the mask. */
6520 for (i = 0; i < sizeof(eth_m->dst); ++i)
6521 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6523 * HW supports match on one Ethertype, the Ethertype following the last
6524 * VLAN tag of the packet (see PRM).
6525 * Set match on ethertype only if ETH header is not followed by VLAN.
6526 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6527 * ethertype, and use ip_version field instead.
6528 * eCPRI over Ether layer will use type value 0xAEFE.
6530 if (eth_m->type == 0xFFFF) {
6531 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6532 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6533 switch (eth_v->type) {
6534 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6535 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6537 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6538 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6539 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6541 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6542 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6544 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6545 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6551 if (eth_m->has_vlan) {
6552 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6553 if (eth_v->has_vlan) {
6555 * Here, when also has_more_vlan field in VLAN item is
6556 * not set, only single-tagged packets will be matched.
6558 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6562 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6563 rte_be_to_cpu_16(eth_m->type));
6564 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6565 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6569 * Add VLAN item to matcher and to the value.
6571 * @param[in, out] dev_flow
6573 * @param[in, out] matcher
6575 * @param[in, out] key
6576 * Flow matcher value.
6578 * Flow pattern to translate.
6580 * Item is inner pattern.
6583 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6584 void *matcher, void *key,
6585 const struct rte_flow_item *item,
6586 int inner, uint32_t group)
6588 const struct rte_flow_item_vlan *vlan_m = item->mask;
6589 const struct rte_flow_item_vlan *vlan_v = item->spec;
6596 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6598 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6600 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6602 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6604 * This is workaround, masks are not supported,
6605 * and pre-validated.
6608 dev_flow->handle->vf_vlan.tag =
6609 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6612 * When VLAN item exists in flow, mark packet as tagged,
6613 * even if TCI is not specified.
6615 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6616 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6617 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6622 vlan_m = &rte_flow_item_vlan_mask;
6623 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6624 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6625 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6626 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6627 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6628 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6629 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6630 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6632 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6633 * ethertype, and use ip_version field instead.
6635 if (vlan_m->inner_type == 0xFFFF) {
6636 switch (vlan_v->inner_type) {
6637 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6638 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6639 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6640 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6642 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6643 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6645 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6646 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6652 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6653 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6654 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6655 /* Only one vlan_tag bit can be set. */
6656 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6659 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6660 rte_be_to_cpu_16(vlan_m->inner_type));
6661 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6662 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6666 * Add IPV4 item to matcher and to the value.
6668 * @param[in, out] matcher
6670 * @param[in, out] key
6671 * Flow matcher value.
6673 * Flow pattern to translate.
6675 * Item is inner pattern.
6677 * The group to insert the rule.
6680 flow_dv_translate_item_ipv4(void *matcher, void *key,
6681 const struct rte_flow_item *item,
6682 int inner, uint32_t group)
6684 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6685 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6686 const struct rte_flow_item_ipv4 nic_mask = {
6688 .src_addr = RTE_BE32(0xffffffff),
6689 .dst_addr = RTE_BE32(0xffffffff),
6690 .type_of_service = 0xff,
6691 .next_proto_id = 0xff,
6692 .time_to_live = 0xff,
6702 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6704 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6706 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6708 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6710 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6715 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6716 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6717 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6718 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6719 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6720 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6721 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6722 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6723 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6724 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6725 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6726 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6727 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6728 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6729 ipv4_m->hdr.type_of_service);
6730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6731 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6732 ipv4_m->hdr.type_of_service >> 2);
6733 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6734 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6735 ipv4_m->hdr.next_proto_id);
6736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6737 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6738 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6739 ipv4_m->hdr.time_to_live);
6740 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6741 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6742 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6743 !!(ipv4_m->hdr.fragment_offset));
6744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6745 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6749 * Add IPV6 item to matcher and to the value.
6751 * @param[in, out] matcher
6753 * @param[in, out] key
6754 * Flow matcher value.
6756 * Flow pattern to translate.
6758 * Item is inner pattern.
6760 * The group to insert the rule.
6763 flow_dv_translate_item_ipv6(void *matcher, void *key,
6764 const struct rte_flow_item *item,
6765 int inner, uint32_t group)
6767 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6768 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6769 const struct rte_flow_item_ipv6 nic_mask = {
6772 "\xff\xff\xff\xff\xff\xff\xff\xff"
6773 "\xff\xff\xff\xff\xff\xff\xff\xff",
6775 "\xff\xff\xff\xff\xff\xff\xff\xff"
6776 "\xff\xff\xff\xff\xff\xff\xff\xff",
6777 .vtc_flow = RTE_BE32(0xffffffff),
6784 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6785 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6794 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6796 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6798 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6800 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6802 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6807 size = sizeof(ipv6_m->hdr.dst_addr);
6808 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6809 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6810 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6811 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6812 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6813 for (i = 0; i < size; ++i)
6814 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6815 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6816 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6817 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6818 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6819 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6820 for (i = 0; i < size; ++i)
6821 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6823 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6824 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6825 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6826 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6827 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6828 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6831 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6833 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6836 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6838 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6842 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6844 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6845 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6847 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6848 ipv6_m->hdr.hop_limits);
6849 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6850 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6851 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6852 !!(ipv6_m->has_frag_ext));
6853 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6854 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6858 * Add IPV6 fragment extension item to matcher and to the value.
6860 * @param[in, out] matcher
6862 * @param[in, out] key
6863 * Flow matcher value.
6865 * Flow pattern to translate.
6867 * Item is inner pattern.
6870 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6871 const struct rte_flow_item *item,
6874 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6875 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6876 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6878 .next_header = 0xff,
6879 .frag_data = RTE_BE16(0xffff),
6886 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6888 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6890 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6892 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6894 /* IPv6 fragment extension item exists, so packet is IP fragment. */
6895 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6896 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6897 if (!ipv6_frag_ext_v)
6899 if (!ipv6_frag_ext_m)
6900 ipv6_frag_ext_m = &nic_mask;
6901 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6902 ipv6_frag_ext_m->hdr.next_header);
6903 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6904 ipv6_frag_ext_v->hdr.next_header &
6905 ipv6_frag_ext_m->hdr.next_header);
6909 * Add TCP item to matcher and to the value.
6911 * @param[in, out] matcher
6913 * @param[in, out] key
6914 * Flow matcher value.
6916 * Flow pattern to translate.
6918 * Item is inner pattern.
6921 flow_dv_translate_item_tcp(void *matcher, void *key,
6922 const struct rte_flow_item *item,
6925 const struct rte_flow_item_tcp *tcp_m = item->mask;
6926 const struct rte_flow_item_tcp *tcp_v = item->spec;
6931 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6933 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6935 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6937 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6939 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6940 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6944 tcp_m = &rte_flow_item_tcp_mask;
6945 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6946 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6947 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6948 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6949 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6950 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6951 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6952 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6953 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6954 tcp_m->hdr.tcp_flags);
6955 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6956 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6960 * Add UDP item to matcher and to the value.
6962 * @param[in, out] matcher
6964 * @param[in, out] key
6965 * Flow matcher value.
6967 * Flow pattern to translate.
6969 * Item is inner pattern.
6972 flow_dv_translate_item_udp(void *matcher, void *key,
6973 const struct rte_flow_item *item,
6976 const struct rte_flow_item_udp *udp_m = item->mask;
6977 const struct rte_flow_item_udp *udp_v = item->spec;
6982 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6984 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6986 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6988 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6990 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6991 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6995 udp_m = &rte_flow_item_udp_mask;
6996 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6997 rte_be_to_cpu_16(udp_m->hdr.src_port));
6998 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6999 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7000 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7001 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7002 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7003 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7007 * Add GRE optional Key item to matcher and to the value.
7009 * @param[in, out] matcher
7011 * @param[in, out] key
7012 * Flow matcher value.
7014 * Flow pattern to translate.
7016 * Item is inner pattern.
7019 flow_dv_translate_item_gre_key(void *matcher, void *key,
7020 const struct rte_flow_item *item)
7022 const rte_be32_t *key_m = item->mask;
7023 const rte_be32_t *key_v = item->spec;
7024 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7025 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7026 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7028 /* GRE K bit must be on and should already be validated */
7029 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7030 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7034 key_m = &gre_key_default_mask;
7035 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7036 rte_be_to_cpu_32(*key_m) >> 8);
7037 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7038 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7039 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7040 rte_be_to_cpu_32(*key_m) & 0xFF);
7041 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7042 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7046 * Add GRE item to matcher and to the value.
7048 * @param[in, out] matcher
7050 * @param[in, out] key
7051 * Flow matcher value.
7053 * Flow pattern to translate.
7055 * Item is inner pattern.
7058 flow_dv_translate_item_gre(void *matcher, void *key,
7059 const struct rte_flow_item *item,
7062 const struct rte_flow_item_gre *gre_m = item->mask;
7063 const struct rte_flow_item_gre *gre_v = item->spec;
7066 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7067 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7074 uint16_t s_present:1;
7075 uint16_t k_present:1;
7076 uint16_t rsvd_bit1:1;
7077 uint16_t c_present:1;
7081 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7084 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7086 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7088 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7090 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7092 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7093 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7097 gre_m = &rte_flow_item_gre_mask;
7098 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7099 rte_be_to_cpu_16(gre_m->protocol));
7100 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7101 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7102 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7103 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7104 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7105 gre_crks_rsvd0_ver_m.c_present);
7106 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7107 gre_crks_rsvd0_ver_v.c_present &
7108 gre_crks_rsvd0_ver_m.c_present);
7109 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7110 gre_crks_rsvd0_ver_m.k_present);
7111 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7112 gre_crks_rsvd0_ver_v.k_present &
7113 gre_crks_rsvd0_ver_m.k_present);
7114 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7115 gre_crks_rsvd0_ver_m.s_present);
7116 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7117 gre_crks_rsvd0_ver_v.s_present &
7118 gre_crks_rsvd0_ver_m.s_present);
7122 * Add NVGRE item to matcher and to the value.
7124 * @param[in, out] matcher
7126 * @param[in, out] key
7127 * Flow matcher value.
7129 * Flow pattern to translate.
7131 * Item is inner pattern.
7134 flow_dv_translate_item_nvgre(void *matcher, void *key,
7135 const struct rte_flow_item *item,
7138 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7139 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7140 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7141 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7142 const char *tni_flow_id_m;
7143 const char *tni_flow_id_v;
7149 /* For NVGRE, GRE header fields must be set with defined values. */
7150 const struct rte_flow_item_gre gre_spec = {
7151 .c_rsvd0_ver = RTE_BE16(0x2000),
7152 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7154 const struct rte_flow_item_gre gre_mask = {
7155 .c_rsvd0_ver = RTE_BE16(0xB000),
7156 .protocol = RTE_BE16(UINT16_MAX),
7158 const struct rte_flow_item gre_item = {
7163 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7167 nvgre_m = &rte_flow_item_nvgre_mask;
7168 tni_flow_id_m = (const char *)nvgre_m->tni;
7169 tni_flow_id_v = (const char *)nvgre_v->tni;
7170 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7171 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7172 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7173 memcpy(gre_key_m, tni_flow_id_m, size);
7174 for (i = 0; i < size; ++i)
7175 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7179 * Add VXLAN item to matcher and to the value.
7181 * @param[in, out] matcher
7183 * @param[in, out] key
7184 * Flow matcher value.
7186 * Flow pattern to translate.
7188 * Item is inner pattern.
7191 flow_dv_translate_item_vxlan(void *matcher, void *key,
7192 const struct rte_flow_item *item,
7195 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7196 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7199 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7200 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7208 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7210 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7212 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7214 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7216 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7217 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7218 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7219 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7220 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7225 vxlan_m = &rte_flow_item_vxlan_mask;
7226 size = sizeof(vxlan_m->vni);
7227 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7228 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7229 memcpy(vni_m, vxlan_m->vni, size);
7230 for (i = 0; i < size; ++i)
7231 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7235 * Add VXLAN-GPE item to matcher and to the value.
7237 * @param[in, out] matcher
7239 * @param[in, out] key
7240 * Flow matcher value.
7242 * Flow pattern to translate.
7244 * Item is inner pattern.
7248 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7249 const struct rte_flow_item *item, int inner)
7251 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7252 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7256 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7258 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7264 uint8_t flags_m = 0xff;
7265 uint8_t flags_v = 0xc;
7268 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7270 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7272 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7274 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7276 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7277 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7278 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7279 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7280 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7285 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7286 size = sizeof(vxlan_m->vni);
7287 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7288 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7289 memcpy(vni_m, vxlan_m->vni, size);
7290 for (i = 0; i < size; ++i)
7291 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7292 if (vxlan_m->flags) {
7293 flags_m = vxlan_m->flags;
7294 flags_v = vxlan_v->flags;
7296 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7297 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7298 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7300 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7305 * Add Geneve item to matcher and to the value.
7307 * @param[in, out] matcher
7309 * @param[in, out] key
7310 * Flow matcher value.
7312 * Flow pattern to translate.
7314 * Item is inner pattern.
7318 flow_dv_translate_item_geneve(void *matcher, void *key,
7319 const struct rte_flow_item *item, int inner)
7321 const struct rte_flow_item_geneve *geneve_m = item->mask;
7322 const struct rte_flow_item_geneve *geneve_v = item->spec;
7325 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7326 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7335 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7337 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7339 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7341 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7343 dport = MLX5_UDP_PORT_GENEVE;
7344 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7345 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7346 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7351 geneve_m = &rte_flow_item_geneve_mask;
7352 size = sizeof(geneve_m->vni);
7353 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7354 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7355 memcpy(vni_m, geneve_m->vni, size);
7356 for (i = 0; i < size; ++i)
7357 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7358 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7359 rte_be_to_cpu_16(geneve_m->protocol));
7360 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7361 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7362 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7363 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7364 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7365 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7366 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7367 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7368 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7369 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7370 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7371 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7372 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7376 * Create Geneve TLV option resource.
7378 * @param dev[in, out]
7379 * Pointer to rte_eth_dev structure.
7380 * @param[in, out] tag_be24
7381 * Tag value in big endian then R-shift 8.
7382 * @parm[in, out] dev_flow
7383 * Pointer to the dev_flow.
7385 * pointer to error structure.
7388 * 0 on success otherwise -errno and errno is set.
7392 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7393 const struct rte_flow_item *item,
7394 struct rte_flow_error *error)
7396 struct mlx5_priv *priv = dev->data->dev_private;
7397 struct mlx5_dev_ctx_shared *sh = priv->sh;
7398 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7399 sh->geneve_tlv_option_resource;
7400 struct mlx5_devx_obj *obj;
7401 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7406 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7407 if (geneve_opt_resource != NULL) {
7408 if (geneve_opt_resource->option_class ==
7409 geneve_opt_v->option_class &&
7410 geneve_opt_resource->option_type ==
7411 geneve_opt_v->option_type &&
7412 geneve_opt_resource->length ==
7413 geneve_opt_v->option_len) {
7414 /* We already have GENVE TLV option obj allocated. */
7415 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7418 ret = rte_flow_error_set(error, ENOMEM,
7419 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7420 "Only one GENEVE TLV option supported");
7424 /* Create a GENEVE TLV object and resource. */
7425 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7426 geneve_opt_v->option_class,
7427 geneve_opt_v->option_type,
7428 geneve_opt_v->option_len);
7430 ret = rte_flow_error_set(error, ENODATA,
7431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7432 "Failed to create GENEVE TLV Devx object");
7435 sh->geneve_tlv_option_resource =
7436 mlx5_malloc(MLX5_MEM_ZERO,
7437 sizeof(*geneve_opt_resource),
7439 if (!sh->geneve_tlv_option_resource) {
7440 claim_zero(mlx5_devx_cmd_destroy(obj));
7441 ret = rte_flow_error_set(error, ENOMEM,
7442 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7443 "GENEVE TLV object memory allocation failed");
7446 geneve_opt_resource = sh->geneve_tlv_option_resource;
7447 geneve_opt_resource->obj = obj;
7448 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7449 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7450 geneve_opt_resource->length = geneve_opt_v->option_len;
7451 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7455 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7460 * Add Geneve TLV option item to matcher.
7462 * @param[in, out] dev
7463 * Pointer to rte_eth_dev structure.
7464 * @param[in, out] matcher
7466 * @param[in, out] key
7467 * Flow matcher value.
7469 * Flow pattern to translate.
7471 * Pointer to error structure.
7474 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
7475 void *key, const struct rte_flow_item *item,
7476 struct rte_flow_error *error)
7478 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
7479 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7480 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7481 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7482 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7484 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7485 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
7491 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
7492 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
7495 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
7499 * Set the option length in GENEVE header if not requested.
7500 * The GENEVE TLV option length is expressed by the option length field
7501 * in the GENEVE header.
7502 * If the option length was not requested but the GENEVE TLV option item
7503 * is present we set the option length field implicitly.
7505 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
7506 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7507 MLX5_GENEVE_OPTLEN_MASK);
7508 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7509 geneve_opt_v->option_len + 1);
7512 if (geneve_opt_v->data) {
7513 memcpy(&opt_data_key, geneve_opt_v->data,
7514 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7515 sizeof(opt_data_key)));
7516 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7517 sizeof(opt_data_key));
7518 memcpy(&opt_data_mask, geneve_opt_m->data,
7519 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7520 sizeof(opt_data_mask)));
7521 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7522 sizeof(opt_data_mask));
7523 MLX5_SET(fte_match_set_misc3, misc3_m,
7524 geneve_tlv_option_0_data,
7525 rte_be_to_cpu_32(opt_data_mask));
7526 MLX5_SET(fte_match_set_misc3, misc3_v,
7527 geneve_tlv_option_0_data,
7528 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
7534 * Add MPLS item to matcher and to the value.
7536 * @param[in, out] matcher
7538 * @param[in, out] key
7539 * Flow matcher value.
7541 * Flow pattern to translate.
7542 * @param[in] prev_layer
7543 * The protocol layer indicated in previous item.
7545 * Item is inner pattern.
7548 flow_dv_translate_item_mpls(void *matcher, void *key,
7549 const struct rte_flow_item *item,
7550 uint64_t prev_layer,
7553 const uint32_t *in_mpls_m = item->mask;
7554 const uint32_t *in_mpls_v = item->spec;
7555 uint32_t *out_mpls_m = 0;
7556 uint32_t *out_mpls_v = 0;
7557 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7558 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7559 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7561 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7562 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7563 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7565 switch (prev_layer) {
7566 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7567 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7569 MLX5_UDP_PORT_MPLS);
7571 case MLX5_FLOW_LAYER_GRE:
7572 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7573 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7574 RTE_ETHER_TYPE_MPLS);
7577 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7578 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7585 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7586 switch (prev_layer) {
7587 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7589 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7590 outer_first_mpls_over_udp);
7592 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7593 outer_first_mpls_over_udp);
7595 case MLX5_FLOW_LAYER_GRE:
7597 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7598 outer_first_mpls_over_gre);
7600 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7601 outer_first_mpls_over_gre);
7604 /* Inner MPLS not over GRE is not supported. */
7607 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7611 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7617 if (out_mpls_m && out_mpls_v) {
7618 *out_mpls_m = *in_mpls_m;
7619 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7624 * Add metadata register item to matcher
7626 * @param[in, out] matcher
7628 * @param[in, out] key
7629 * Flow matcher value.
7630 * @param[in] reg_type
7631 * Type of device metadata register
7638 flow_dv_match_meta_reg(void *matcher, void *key,
7639 enum modify_reg reg_type,
7640 uint32_t data, uint32_t mask)
7643 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7645 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7651 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7652 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7655 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7656 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7660 * The metadata register C0 field might be divided into
7661 * source vport index and META item value, we should set
7662 * this field according to specified mask, not as whole one.
7664 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7666 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7667 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7670 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7673 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7674 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7677 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7678 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7681 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7682 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7685 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7686 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7689 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7690 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7693 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7694 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7697 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7698 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7707 * Add MARK item to matcher
7710 * The device to configure through.
7711 * @param[in, out] matcher
7713 * @param[in, out] key
7714 * Flow matcher value.
7716 * Flow pattern to translate.
7719 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7720 void *matcher, void *key,
7721 const struct rte_flow_item *item)
7723 struct mlx5_priv *priv = dev->data->dev_private;
7724 const struct rte_flow_item_mark *mark;
7728 mark = item->mask ? (const void *)item->mask :
7729 &rte_flow_item_mark_mask;
7730 mask = mark->id & priv->sh->dv_mark_mask;
7731 mark = (const void *)item->spec;
7733 value = mark->id & priv->sh->dv_mark_mask & mask;
7735 enum modify_reg reg;
7737 /* Get the metadata register index for the mark. */
7738 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7739 MLX5_ASSERT(reg > 0);
7740 if (reg == REG_C_0) {
7741 struct mlx5_priv *priv = dev->data->dev_private;
7742 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7743 uint32_t shl_c0 = rte_bsf32(msk_c0);
7749 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7754 * Add META item to matcher
7757 * The devich to configure through.
7758 * @param[in, out] matcher
7760 * @param[in, out] key
7761 * Flow matcher value.
7763 * Attributes of flow that includes this item.
7765 * Flow pattern to translate.
7768 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7769 void *matcher, void *key,
7770 const struct rte_flow_attr *attr,
7771 const struct rte_flow_item *item)
7773 const struct rte_flow_item_meta *meta_m;
7774 const struct rte_flow_item_meta *meta_v;
7776 meta_m = (const void *)item->mask;
7778 meta_m = &rte_flow_item_meta_mask;
7779 meta_v = (const void *)item->spec;
7782 uint32_t value = meta_v->data;
7783 uint32_t mask = meta_m->data;
7785 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7788 MLX5_ASSERT(reg != REG_NON);
7790 * In datapath code there is no endianness
7791 * coversions for perfromance reasons, all
7792 * pattern conversions are done in rte_flow.
7794 value = rte_cpu_to_be_32(value);
7795 mask = rte_cpu_to_be_32(mask);
7796 if (reg == REG_C_0) {
7797 struct mlx5_priv *priv = dev->data->dev_private;
7798 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7799 uint32_t shl_c0 = rte_bsf32(msk_c0);
7800 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7801 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7808 MLX5_ASSERT(msk_c0);
7809 MLX5_ASSERT(!(~msk_c0 & mask));
7811 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7816 * Add vport metadata Reg C0 item to matcher
7818 * @param[in, out] matcher
7820 * @param[in, out] key
7821 * Flow matcher value.
7823 * Flow pattern to translate.
7826 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7827 uint32_t value, uint32_t mask)
7829 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7833 * Add tag item to matcher
7836 * The devich to configure through.
7837 * @param[in, out] matcher
7839 * @param[in, out] key
7840 * Flow matcher value.
7842 * Flow pattern to translate.
7845 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7846 void *matcher, void *key,
7847 const struct rte_flow_item *item)
7849 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7850 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7851 uint32_t mask, value;
7854 value = tag_v->data;
7855 mask = tag_m ? tag_m->data : UINT32_MAX;
7856 if (tag_v->id == REG_C_0) {
7857 struct mlx5_priv *priv = dev->data->dev_private;
7858 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7859 uint32_t shl_c0 = rte_bsf32(msk_c0);
7865 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7869 * Add TAG item to matcher
7872 * The devich to configure through.
7873 * @param[in, out] matcher
7875 * @param[in, out] key
7876 * Flow matcher value.
7878 * Flow pattern to translate.
7881 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7882 void *matcher, void *key,
7883 const struct rte_flow_item *item)
7885 const struct rte_flow_item_tag *tag_v = item->spec;
7886 const struct rte_flow_item_tag *tag_m = item->mask;
7887 enum modify_reg reg;
7890 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7891 /* Get the metadata register index for the tag. */
7892 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7893 MLX5_ASSERT(reg > 0);
7894 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7898 * Add source vport match to the specified matcher.
7900 * @param[in, out] matcher
7902 * @param[in, out] key
7903 * Flow matcher value.
7905 * Source vport value to match
7910 flow_dv_translate_item_source_vport(void *matcher, void *key,
7911 int16_t port, uint16_t mask)
7913 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7914 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7916 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7917 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7921 * Translate port-id item to eswitch match on port-id.
7924 * The devich to configure through.
7925 * @param[in, out] matcher
7927 * @param[in, out] key
7928 * Flow matcher value.
7930 * Flow pattern to translate.
7935 * 0 on success, a negative errno value otherwise.
7938 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7939 void *key, const struct rte_flow_item *item,
7940 const struct rte_flow_attr *attr)
7942 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7943 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7944 struct mlx5_priv *priv;
7947 mask = pid_m ? pid_m->id : 0xffff;
7948 id = pid_v ? pid_v->id : dev->data->port_id;
7949 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7953 * Translate to vport field or to metadata, depending on mode.
7954 * Kernel can use either misc.source_port or half of C0 metadata
7957 if (priv->vport_meta_mask) {
7959 * Provide the hint for SW steering library
7960 * to insert the flow into ingress domain and
7961 * save the extra vport match.
7963 if (mask == 0xffff && priv->vport_id == 0xffff &&
7964 priv->pf_bond < 0 && attr->transfer)
7965 flow_dv_translate_item_source_vport
7966 (matcher, key, priv->vport_id, mask);
7968 flow_dv_translate_item_meta_vport
7970 priv->vport_meta_tag,
7971 priv->vport_meta_mask);
7973 flow_dv_translate_item_source_vport(matcher, key,
7974 priv->vport_id, mask);
7980 * Add ICMP6 item to matcher and to the value.
7982 * @param[in, out] matcher
7984 * @param[in, out] key
7985 * Flow matcher value.
7987 * Flow pattern to translate.
7989 * Item is inner pattern.
7992 flow_dv_translate_item_icmp6(void *matcher, void *key,
7993 const struct rte_flow_item *item,
7996 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7997 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8000 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8002 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8004 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8006 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8008 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8010 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8012 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8013 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8017 icmp6_m = &rte_flow_item_icmp6_mask;
8018 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8019 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8020 icmp6_v->type & icmp6_m->type);
8021 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8022 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8023 icmp6_v->code & icmp6_m->code);
8027 * Add ICMP item to matcher and to the value.
8029 * @param[in, out] matcher
8031 * @param[in, out] key
8032 * Flow matcher value.
8034 * Flow pattern to translate.
8036 * Item is inner pattern.
8039 flow_dv_translate_item_icmp(void *matcher, void *key,
8040 const struct rte_flow_item *item,
8043 const struct rte_flow_item_icmp *icmp_m = item->mask;
8044 const struct rte_flow_item_icmp *icmp_v = item->spec;
8045 uint32_t icmp_header_data_m = 0;
8046 uint32_t icmp_header_data_v = 0;
8049 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8051 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8053 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8055 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8059 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8066 icmp_m = &rte_flow_item_icmp_mask;
8067 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8068 icmp_m->hdr.icmp_type);
8069 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8070 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8071 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8072 icmp_m->hdr.icmp_code);
8073 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8074 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8075 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8076 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8077 if (icmp_header_data_m) {
8078 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8079 icmp_header_data_v |=
8080 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8081 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8082 icmp_header_data_m);
8083 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8084 icmp_header_data_v & icmp_header_data_m);
8089 * Add GTP item to matcher and to the value.
8091 * @param[in, out] matcher
8093 * @param[in, out] key
8094 * Flow matcher value.
8096 * Flow pattern to translate.
8098 * Item is inner pattern.
8101 flow_dv_translate_item_gtp(void *matcher, void *key,
8102 const struct rte_flow_item *item, int inner)
8104 const struct rte_flow_item_gtp *gtp_m = item->mask;
8105 const struct rte_flow_item_gtp *gtp_v = item->spec;
8108 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8110 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8111 uint16_t dport = RTE_GTPU_UDP_PORT;
8114 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8116 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8118 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8120 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8122 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8123 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8124 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8129 gtp_m = &rte_flow_item_gtp_mask;
8130 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8131 gtp_m->v_pt_rsv_flags);
8132 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8133 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8134 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8135 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8136 gtp_v->msg_type & gtp_m->msg_type);
8137 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8138 rte_be_to_cpu_32(gtp_m->teid));
8139 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8140 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8144 * Add GTP PSC item to matcher.
8146 * @param[in, out] matcher
8148 * @param[in, out] key
8149 * Flow matcher value.
8151 * Flow pattern to translate.
8154 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8155 const struct rte_flow_item *item)
8157 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8158 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8159 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8161 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8167 uint8_t next_ext_header_type;
8172 /* Always set E-flag match on one, regardless of GTP item settings. */
8173 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8174 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8175 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8176 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8177 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8178 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8179 /*Set next extension header type. */
8182 dw_2.next_ext_header_type = 0xff;
8183 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8184 rte_cpu_to_be_32(dw_2.w32));
8187 dw_2.next_ext_header_type = 0x85;
8188 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8189 rte_cpu_to_be_32(dw_2.w32));
8201 /*Set extension header PDU type and Qos. */
8203 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8205 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8206 dw_0.qfi = gtp_psc_m->qfi;
8207 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8208 rte_cpu_to_be_32(dw_0.w32));
8210 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8211 gtp_psc_m->pdu_type);
8212 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8213 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8214 rte_cpu_to_be_32(dw_0.w32));
8220 * Add eCPRI item to matcher and to the value.
8223 * The devich to configure through.
8224 * @param[in, out] matcher
8226 * @param[in, out] key
8227 * Flow matcher value.
8229 * Flow pattern to translate.
8230 * @param[in] samples
8231 * Sample IDs to be used in the matching.
8234 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8235 void *key, const struct rte_flow_item *item)
8237 struct mlx5_priv *priv = dev->data->dev_private;
8238 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8239 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8240 struct rte_ecpri_common_hdr common;
8241 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8243 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8251 ecpri_m = &rte_flow_item_ecpri_mask;
8253 * Maximal four DW samples are supported in a single matching now.
8254 * Two are used now for a eCPRI matching:
8255 * 1. Type: one byte, mask should be 0x00ff0000 in network order
8256 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8259 if (!ecpri_m->hdr.common.u32)
8261 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8262 /* Need to take the whole DW as the mask to fill the entry. */
8263 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8264 prog_sample_field_value_0);
8265 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8266 prog_sample_field_value_0);
8267 /* Already big endian (network order) in the header. */
8268 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8269 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8270 /* Sample#0, used for matching type, offset 0. */
8271 MLX5_SET(fte_match_set_misc4, misc4_m,
8272 prog_sample_field_id_0, samples[0]);
8273 /* It makes no sense to set the sample ID in the mask field. */
8274 MLX5_SET(fte_match_set_misc4, misc4_v,
8275 prog_sample_field_id_0, samples[0]);
8277 * Checking if message body part needs to be matched.
8278 * Some wildcard rules only matching type field should be supported.
8280 if (ecpri_m->hdr.dummy[0]) {
8281 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8282 switch (common.type) {
8283 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8284 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8285 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8286 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8287 prog_sample_field_value_1);
8288 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8289 prog_sample_field_value_1);
8290 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8291 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8292 ecpri_m->hdr.dummy[0];
8293 /* Sample#1, to match message body, offset 4. */
8294 MLX5_SET(fte_match_set_misc4, misc4_m,
8295 prog_sample_field_id_1, samples[1]);
8296 MLX5_SET(fte_match_set_misc4, misc4_v,
8297 prog_sample_field_id_1, samples[1]);
8300 /* Others, do not match any sample ID. */
8306 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8308 #define HEADER_IS_ZERO(match_criteria, headers) \
8309 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
8310 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8313 * Calculate flow matcher enable bitmap.
8315 * @param match_criteria
8316 * Pointer to flow matcher criteria.
8319 * Bitmap of enabled fields.
8322 flow_dv_matcher_enable(uint32_t *match_criteria)
8324 uint8_t match_criteria_enable;
8326 match_criteria_enable =
8327 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8328 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8329 match_criteria_enable |=
8330 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8331 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8332 match_criteria_enable |=
8333 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8334 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8335 match_criteria_enable |=
8336 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8337 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8338 match_criteria_enable |=
8339 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8340 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8341 match_criteria_enable |=
8342 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8343 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8344 return match_criteria_enable;
8347 struct mlx5_hlist_entry *
8348 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8350 struct mlx5_dev_ctx_shared *sh = list->ctx;
8351 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8352 struct rte_eth_dev *dev = ctx->dev;
8353 struct mlx5_flow_tbl_data_entry *tbl_data;
8354 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8355 struct rte_flow_error *error = ctx->error;
8356 union mlx5_flow_tbl_key key = { .v64 = key64 };
8357 struct mlx5_flow_tbl_resource *tbl;
8362 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8364 rte_flow_error_set(error, ENOMEM,
8365 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8367 "cannot allocate flow table data entry");
8370 tbl_data->idx = idx;
8371 tbl_data->tunnel = tt_prm->tunnel;
8372 tbl_data->group_id = tt_prm->group_id;
8373 tbl_data->external = !!tt_prm->external;
8374 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8375 tbl_data->is_egress = !!key.direction;
8376 tbl_data->is_transfer = !!key.domain;
8377 tbl_data->dummy = !!key.dummy;
8378 tbl_data->table_id = key.table_id;
8379 tbl = &tbl_data->tbl;
8381 return &tbl_data->entry;
8383 domain = sh->fdb_domain;
8384 else if (key.direction)
8385 domain = sh->tx_domain;
8387 domain = sh->rx_domain;
8388 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8390 rte_flow_error_set(error, ENOMEM,
8391 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8392 NULL, "cannot create flow table object");
8393 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8397 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8398 (tbl->obj, &tbl_data->jump.action);
8400 rte_flow_error_set(error, ENOMEM,
8401 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8403 "cannot create flow jump action");
8404 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8405 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8409 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8410 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8412 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8413 flow_dv_matcher_create_cb,
8414 flow_dv_matcher_match_cb,
8415 flow_dv_matcher_remove_cb);
8416 return &tbl_data->entry;
8420 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8421 struct mlx5_hlist_entry *entry, uint64_t key64,
8422 void *cb_ctx __rte_unused)
8424 struct mlx5_flow_tbl_data_entry *tbl_data =
8425 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8426 union mlx5_flow_tbl_key key = { .v64 = key64 };
8428 return tbl_data->table_id != key.table_id ||
8429 tbl_data->dummy != key.dummy ||
8430 tbl_data->is_transfer != key.domain ||
8431 tbl_data->is_egress != key.direction;
8437 * @param[in, out] dev
8438 * Pointer to rte_eth_dev structure.
8439 * @param[in] table_id
8442 * Direction of the table.
8443 * @param[in] transfer
8444 * E-Switch or NIC flow.
8446 * Dummy entry for dv API.
8448 * pointer to error structure.
8451 * Returns tables resource based on the index, NULL in case of failed.
8453 struct mlx5_flow_tbl_resource *
8454 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8455 uint32_t table_id, uint8_t egress,
8458 const struct mlx5_flow_tunnel *tunnel,
8459 uint32_t group_id, uint8_t dummy,
8460 struct rte_flow_error *error)
8462 struct mlx5_priv *priv = dev->data->dev_private;
8463 union mlx5_flow_tbl_key table_key = {
8465 .table_id = table_id,
8467 .domain = !!transfer,
8468 .direction = !!egress,
8471 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8473 .group_id = group_id,
8474 .external = external,
8476 struct mlx5_flow_cb_ctx ctx = {
8481 struct mlx5_hlist_entry *entry;
8482 struct mlx5_flow_tbl_data_entry *tbl_data;
8484 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8486 rte_flow_error_set(error, ENOMEM,
8487 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8488 "cannot get table");
8491 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8492 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8493 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8494 return &tbl_data->tbl;
8498 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8499 struct mlx5_hlist_entry *entry)
8501 struct mlx5_dev_ctx_shared *sh = list->ctx;
8502 struct mlx5_flow_tbl_data_entry *tbl_data =
8503 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8505 MLX5_ASSERT(entry && sh);
8506 if (tbl_data->jump.action)
8507 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8508 if (tbl_data->tbl.obj)
8509 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8510 if (tbl_data->tunnel_offload && tbl_data->external) {
8511 struct mlx5_hlist_entry *he;
8512 struct mlx5_hlist *tunnel_grp_hash;
8513 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8514 union tunnel_tbl_key tunnel_key = {
8515 .tunnel_id = tbl_data->tunnel ?
8516 tbl_data->tunnel->tunnel_id : 0,
8517 .group = tbl_data->group_id
8519 uint32_t table_id = tbl_data->table_id;
8521 tunnel_grp_hash = tbl_data->tunnel ?
8522 tbl_data->tunnel->groups :
8524 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8526 mlx5_hlist_unregister(tunnel_grp_hash, he);
8528 "Table_id %u tunnel %u group %u released.",
8531 tbl_data->tunnel->tunnel_id : 0,
8532 tbl_data->group_id);
8534 mlx5_cache_list_destroy(&tbl_data->matchers);
8535 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8539 * Release a flow table.
8542 * Pointer to device shared structure.
8544 * Table resource to be released.
8547 * Returns 0 if table was released, else return 1;
8550 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8551 struct mlx5_flow_tbl_resource *tbl)
8553 struct mlx5_flow_tbl_data_entry *tbl_data =
8554 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8558 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8562 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8563 struct mlx5_cache_entry *entry, void *cb_ctx)
8565 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8566 struct mlx5_flow_dv_matcher *ref = ctx->data;
8567 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8570 return cur->crc != ref->crc ||
8571 cur->priority != ref->priority ||
8572 memcmp((const void *)cur->mask.buf,
8573 (const void *)ref->mask.buf, ref->mask.size);
8576 struct mlx5_cache_entry *
8577 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8578 struct mlx5_cache_entry *entry __rte_unused,
8581 struct mlx5_dev_ctx_shared *sh = list->ctx;
8582 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8583 struct mlx5_flow_dv_matcher *ref = ctx->data;
8584 struct mlx5_flow_dv_matcher *cache;
8585 struct mlx5dv_flow_matcher_attr dv_attr = {
8586 .type = IBV_FLOW_ATTR_NORMAL,
8587 .match_mask = (void *)&ref->mask,
8589 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8593 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8595 rte_flow_error_set(ctx->error, ENOMEM,
8596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8597 "cannot create matcher");
8601 dv_attr.match_criteria_enable =
8602 flow_dv_matcher_enable(cache->mask.buf);
8603 dv_attr.priority = ref->priority;
8605 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8606 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8607 &cache->matcher_object);
8610 rte_flow_error_set(ctx->error, ENOMEM,
8611 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8612 "cannot create matcher");
8615 return &cache->entry;
8619 * Register the flow matcher.
8621 * @param[in, out] dev
8622 * Pointer to rte_eth_dev structure.
8623 * @param[in, out] matcher
8624 * Pointer to flow matcher.
8625 * @param[in, out] key
8626 * Pointer to flow table key.
8627 * @parm[in, out] dev_flow
8628 * Pointer to the dev_flow.
8630 * pointer to error structure.
8633 * 0 on success otherwise -errno and errno is set.
8636 flow_dv_matcher_register(struct rte_eth_dev *dev,
8637 struct mlx5_flow_dv_matcher *ref,
8638 union mlx5_flow_tbl_key *key,
8639 struct mlx5_flow *dev_flow,
8640 const struct mlx5_flow_tunnel *tunnel,
8642 struct rte_flow_error *error)
8644 struct mlx5_cache_entry *entry;
8645 struct mlx5_flow_dv_matcher *cache;
8646 struct mlx5_flow_tbl_resource *tbl;
8647 struct mlx5_flow_tbl_data_entry *tbl_data;
8648 struct mlx5_flow_cb_ctx ctx = {
8654 * tunnel offload API requires this registration for cases when
8655 * tunnel match rule was inserted before tunnel set rule.
8657 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8658 key->direction, key->domain,
8659 dev_flow->external, tunnel,
8660 group_id, 0, error);
8662 return -rte_errno; /* No need to refill the error info */
8663 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8665 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8667 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8668 return rte_flow_error_set(error, ENOMEM,
8669 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8670 "cannot allocate ref memory");
8672 cache = container_of(entry, typeof(*cache), entry);
8673 dev_flow->handle->dvh.matcher = cache;
8677 struct mlx5_hlist_entry *
8678 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8680 struct mlx5_dev_ctx_shared *sh = list->ctx;
8681 struct rte_flow_error *error = ctx;
8682 struct mlx5_flow_dv_tag_resource *entry;
8686 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8688 rte_flow_error_set(error, ENOMEM,
8689 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8690 "cannot allocate resource memory");
8694 entry->tag_id = key;
8695 ret = mlx5_flow_os_create_flow_action_tag(key,
8698 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8699 rte_flow_error_set(error, ENOMEM,
8700 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8701 NULL, "cannot create action");
8704 return &entry->entry;
8708 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8709 struct mlx5_hlist_entry *entry, uint64_t key,
8710 void *cb_ctx __rte_unused)
8712 struct mlx5_flow_dv_tag_resource *tag =
8713 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8715 return key != tag->tag_id;
8719 * Find existing tag resource or create and register a new one.
8721 * @param dev[in, out]
8722 * Pointer to rte_eth_dev structure.
8723 * @param[in, out] tag_be24
8724 * Tag value in big endian then R-shift 8.
8725 * @parm[in, out] dev_flow
8726 * Pointer to the dev_flow.
8728 * pointer to error structure.
8731 * 0 on success otherwise -errno and errno is set.
8734 flow_dv_tag_resource_register
8735 (struct rte_eth_dev *dev,
8737 struct mlx5_flow *dev_flow,
8738 struct rte_flow_error *error)
8740 struct mlx5_priv *priv = dev->data->dev_private;
8741 struct mlx5_flow_dv_tag_resource *cache_resource;
8742 struct mlx5_hlist_entry *entry;
8744 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8746 cache_resource = container_of
8747 (entry, struct mlx5_flow_dv_tag_resource, entry);
8748 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8749 dev_flow->dv.tag_resource = cache_resource;
8756 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8757 struct mlx5_hlist_entry *entry)
8759 struct mlx5_dev_ctx_shared *sh = list->ctx;
8760 struct mlx5_flow_dv_tag_resource *tag =
8761 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8763 MLX5_ASSERT(tag && sh && tag->action);
8764 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8765 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8766 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8773 * Pointer to Ethernet device.
8778 * 1 while a reference on it exists, 0 when freed.
8781 flow_dv_tag_release(struct rte_eth_dev *dev,
8784 struct mlx5_priv *priv = dev->data->dev_private;
8785 struct mlx5_flow_dv_tag_resource *tag;
8787 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8790 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8791 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8792 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8796 * Translate port ID action to vport.
8799 * Pointer to rte_eth_dev structure.
8801 * Pointer to the port ID action.
8802 * @param[out] dst_port_id
8803 * The target port ID.
8805 * Pointer to the error structure.
8808 * 0 on success, a negative errno value otherwise and rte_errno is set.
8811 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8812 const struct rte_flow_action *action,
8813 uint32_t *dst_port_id,
8814 struct rte_flow_error *error)
8817 struct mlx5_priv *priv;
8818 const struct rte_flow_action_port_id *conf =
8819 (const struct rte_flow_action_port_id *)action->conf;
8821 port = conf->original ? dev->data->port_id : conf->id;
8822 priv = mlx5_port_to_eswitch_info(port, false);
8824 return rte_flow_error_set(error, -rte_errno,
8825 RTE_FLOW_ERROR_TYPE_ACTION,
8827 "No eswitch info was found for port");
8828 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8830 * This parameter is transferred to
8831 * mlx5dv_dr_action_create_dest_ib_port().
8833 *dst_port_id = priv->dev_port;
8836 * Legacy mode, no LAG configurations is supported.
8837 * This parameter is transferred to
8838 * mlx5dv_dr_action_create_dest_vport().
8840 *dst_port_id = priv->vport_id;
8846 * Create a counter with aging configuration.
8849 * Pointer to rte_eth_dev structure.
8851 * Pointer to the counter action configuration.
8853 * Pointer to the aging action configuration.
8856 * Index to flow counter on success, 0 otherwise.
8859 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8860 struct mlx5_flow *dev_flow,
8861 const struct rte_flow_action_count *count,
8862 const struct rte_flow_action_age *age)
8865 struct mlx5_age_param *age_param;
8867 if (count && count->shared)
8868 counter = flow_dv_counter_get_shared(dev, count->id);
8870 counter = flow_dv_counter_alloc(dev, !!age);
8871 if (!counter || age == NULL)
8873 age_param = flow_dv_counter_idx_get_age(dev, counter);
8874 age_param->context = age->context ? age->context :
8875 (void *)(uintptr_t)(dev_flow->flow_idx);
8876 age_param->timeout = age->timeout;
8877 age_param->port_id = dev->data->port_id;
8878 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8879 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8884 * Add Tx queue matcher
8887 * Pointer to the dev struct.
8888 * @param[in, out] matcher
8890 * @param[in, out] key
8891 * Flow matcher value.
8893 * Flow pattern to translate.
8895 * Item is inner pattern.
8898 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8899 void *matcher, void *key,
8900 const struct rte_flow_item *item)
8902 const struct mlx5_rte_flow_item_tx_queue *queue_m;
8903 const struct mlx5_rte_flow_item_tx_queue *queue_v;
8905 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8907 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8908 struct mlx5_txq_ctrl *txq;
8912 queue_m = (const void *)item->mask;
8915 queue_v = (const void *)item->spec;
8918 txq = mlx5_txq_get(dev, queue_v->queue);
8921 queue = txq->obj->sq->id;
8922 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8923 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8924 queue & queue_m->queue);
8925 mlx5_txq_release(dev, queue_v->queue);
8929 * Set the hash fields according to the @p flow information.
8931 * @param[in] dev_flow
8932 * Pointer to the mlx5_flow.
8933 * @param[in] rss_desc
8934 * Pointer to the mlx5_flow_rss_desc.
8937 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8938 struct mlx5_flow_rss_desc *rss_desc)
8940 uint64_t items = dev_flow->handle->layers;
8942 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8944 dev_flow->hash_fields = 0;
8945 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8946 if (rss_desc->level >= 2) {
8947 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8951 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8952 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8953 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8954 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8955 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8956 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8957 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8959 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8961 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8962 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8963 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8964 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8965 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8966 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8967 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8969 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8972 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8973 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8974 if (rss_types & ETH_RSS_UDP) {
8975 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8976 dev_flow->hash_fields |=
8977 IBV_RX_HASH_SRC_PORT_UDP;
8978 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8979 dev_flow->hash_fields |=
8980 IBV_RX_HASH_DST_PORT_UDP;
8982 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8984 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8985 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8986 if (rss_types & ETH_RSS_TCP) {
8987 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8988 dev_flow->hash_fields |=
8989 IBV_RX_HASH_SRC_PORT_TCP;
8990 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8991 dev_flow->hash_fields |=
8992 IBV_RX_HASH_DST_PORT_TCP;
8994 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9000 * Prepare an Rx Hash queue.
9003 * Pointer to Ethernet device.
9004 * @param[in] dev_flow
9005 * Pointer to the mlx5_flow.
9006 * @param[in] rss_desc
9007 * Pointer to the mlx5_flow_rss_desc.
9008 * @param[out] hrxq_idx
9009 * Hash Rx queue index.
9012 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9014 static struct mlx5_hrxq *
9015 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9016 struct mlx5_flow *dev_flow,
9017 struct mlx5_flow_rss_desc *rss_desc,
9020 struct mlx5_priv *priv = dev->data->dev_private;
9021 struct mlx5_flow_handle *dh = dev_flow->handle;
9022 struct mlx5_hrxq *hrxq;
9024 MLX5_ASSERT(rss_desc->queue_num);
9025 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9026 rss_desc->hash_fields = dev_flow->hash_fields;
9027 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9028 rss_desc->shared_rss = 0;
9029 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9032 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9038 * Release sample sub action resource.
9040 * @param[in, out] dev
9041 * Pointer to rte_eth_dev structure.
9042 * @param[in] act_res
9043 * Pointer to sample sub action resource.
9046 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9047 struct mlx5_flow_sub_actions_idx *act_res)
9049 if (act_res->rix_hrxq) {
9050 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9051 act_res->rix_hrxq = 0;
9053 if (act_res->rix_encap_decap) {
9054 flow_dv_encap_decap_resource_release(dev,
9055 act_res->rix_encap_decap);
9056 act_res->rix_encap_decap = 0;
9058 if (act_res->rix_port_id_action) {
9059 flow_dv_port_id_action_resource_release(dev,
9060 act_res->rix_port_id_action);
9061 act_res->rix_port_id_action = 0;
9063 if (act_res->rix_tag) {
9064 flow_dv_tag_release(dev, act_res->rix_tag);
9065 act_res->rix_tag = 0;
9068 flow_dv_counter_free(dev, act_res->cnt);
9071 if (act_res->rix_jump) {
9072 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9073 act_res->rix_jump = 0;
9078 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9079 struct mlx5_cache_entry *entry, void *cb_ctx)
9081 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9082 struct rte_eth_dev *dev = ctx->dev;
9083 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9084 struct mlx5_flow_dv_sample_resource *cache_resource =
9085 container_of(entry, typeof(*cache_resource), entry);
9087 if (resource->ratio == cache_resource->ratio &&
9088 resource->ft_type == cache_resource->ft_type &&
9089 resource->ft_id == cache_resource->ft_id &&
9090 resource->set_action == cache_resource->set_action &&
9091 !memcmp((void *)&resource->sample_act,
9092 (void *)&cache_resource->sample_act,
9093 sizeof(struct mlx5_flow_sub_actions_list))) {
9095 * Existing sample action should release the prepared
9096 * sub-actions reference counter.
9098 flow_dv_sample_sub_actions_release(dev,
9099 &resource->sample_idx);
9105 struct mlx5_cache_entry *
9106 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9107 struct mlx5_cache_entry *entry __rte_unused,
9110 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9111 struct rte_eth_dev *dev = ctx->dev;
9112 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9113 void **sample_dv_actions = resource->sub_actions;
9114 struct mlx5_flow_dv_sample_resource *cache_resource;
9115 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9116 struct mlx5_priv *priv = dev->data->dev_private;
9117 struct mlx5_dev_ctx_shared *sh = priv->sh;
9118 struct mlx5_flow_tbl_resource *tbl;
9120 const uint32_t next_ft_step = 1;
9121 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9122 uint8_t is_egress = 0;
9123 uint8_t is_transfer = 0;
9124 struct rte_flow_error *error = ctx->error;
9126 /* Register new sample resource. */
9127 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9128 if (!cache_resource) {
9129 rte_flow_error_set(error, ENOMEM,
9130 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9132 "cannot allocate resource memory");
9135 *cache_resource = *resource;
9136 /* Create normal path table level */
9137 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9139 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9141 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9142 is_egress, is_transfer,
9143 true, NULL, 0, 0, error);
9145 rte_flow_error_set(error, ENOMEM,
9146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9148 "fail to create normal path table "
9152 cache_resource->normal_path_tbl = tbl;
9153 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9154 if (!sh->default_miss_action) {
9155 rte_flow_error_set(error, ENOMEM,
9156 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9158 "default miss action was not "
9162 sample_dv_actions[resource->sample_act.actions_num++] =
9163 sh->default_miss_action;
9165 /* Create a DR sample action */
9166 sampler_attr.sample_ratio = cache_resource->ratio;
9167 sampler_attr.default_next_table = tbl->obj;
9168 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9169 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9170 &sample_dv_actions[0];
9171 sampler_attr.action = cache_resource->set_action;
9172 if (mlx5_os_flow_dr_create_flow_action_sampler
9173 (&sampler_attr, &cache_resource->verbs_action)) {
9174 rte_flow_error_set(error, ENOMEM,
9175 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9176 NULL, "cannot create sample action");
9179 cache_resource->idx = idx;
9180 cache_resource->dev = dev;
9181 return &cache_resource->entry;
9183 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9184 flow_dv_sample_sub_actions_release(dev,
9185 &cache_resource->sample_idx);
9186 if (cache_resource->normal_path_tbl)
9187 flow_dv_tbl_resource_release(MLX5_SH(dev),
9188 cache_resource->normal_path_tbl);
9189 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9195 * Find existing sample resource or create and register a new one.
9197 * @param[in, out] dev
9198 * Pointer to rte_eth_dev structure.
9199 * @param[in] resource
9200 * Pointer to sample resource.
9201 * @parm[in, out] dev_flow
9202 * Pointer to the dev_flow.
9204 * pointer to error structure.
9207 * 0 on success otherwise -errno and errno is set.
9210 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9211 struct mlx5_flow_dv_sample_resource *resource,
9212 struct mlx5_flow *dev_flow,
9213 struct rte_flow_error *error)
9215 struct mlx5_flow_dv_sample_resource *cache_resource;
9216 struct mlx5_cache_entry *entry;
9217 struct mlx5_priv *priv = dev->data->dev_private;
9218 struct mlx5_flow_cb_ctx ctx = {
9224 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9227 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9228 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9229 dev_flow->dv.sample_res = cache_resource;
9234 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9235 struct mlx5_cache_entry *entry, void *cb_ctx)
9237 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9238 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9239 struct rte_eth_dev *dev = ctx->dev;
9240 struct mlx5_flow_dv_dest_array_resource *cache_resource =
9241 container_of(entry, typeof(*cache_resource), entry);
9244 if (resource->num_of_dest == cache_resource->num_of_dest &&
9245 resource->ft_type == cache_resource->ft_type &&
9246 !memcmp((void *)cache_resource->sample_act,
9247 (void *)resource->sample_act,
9248 (resource->num_of_dest *
9249 sizeof(struct mlx5_flow_sub_actions_list)))) {
9251 * Existing sample action should release the prepared
9252 * sub-actions reference counter.
9254 for (idx = 0; idx < resource->num_of_dest; idx++)
9255 flow_dv_sample_sub_actions_release(dev,
9256 &resource->sample_idx[idx]);
9262 struct mlx5_cache_entry *
9263 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9264 struct mlx5_cache_entry *entry __rte_unused,
9267 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9268 struct rte_eth_dev *dev = ctx->dev;
9269 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9270 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9271 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9272 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9273 struct mlx5_priv *priv = dev->data->dev_private;
9274 struct mlx5_dev_ctx_shared *sh = priv->sh;
9275 struct mlx5_flow_sub_actions_list *sample_act;
9276 struct mlx5dv_dr_domain *domain;
9277 uint32_t idx = 0, res_idx = 0;
9278 struct rte_flow_error *error = ctx->error;
9279 uint64_t action_flags;
9282 /* Register new destination array resource. */
9283 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9285 if (!cache_resource) {
9286 rte_flow_error_set(error, ENOMEM,
9287 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9289 "cannot allocate resource memory");
9292 *cache_resource = *resource;
9293 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9294 domain = sh->fdb_domain;
9295 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9296 domain = sh->rx_domain;
9298 domain = sh->tx_domain;
9299 for (idx = 0; idx < resource->num_of_dest; idx++) {
9300 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9301 mlx5_malloc(MLX5_MEM_ZERO,
9302 sizeof(struct mlx5dv_dr_action_dest_attr),
9304 if (!dest_attr[idx]) {
9305 rte_flow_error_set(error, ENOMEM,
9306 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9308 "cannot allocate resource memory");
9311 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9312 sample_act = &resource->sample_act[idx];
9313 action_flags = sample_act->action_flags;
9314 switch (action_flags) {
9315 case MLX5_FLOW_ACTION_QUEUE:
9316 dest_attr[idx]->dest = sample_act->dr_queue_action;
9318 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
9319 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9320 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9321 dest_attr[idx]->dest_reformat->reformat =
9322 sample_act->dr_encap_action;
9323 dest_attr[idx]->dest_reformat->dest =
9324 sample_act->dr_port_id_action;
9326 case MLX5_FLOW_ACTION_PORT_ID:
9327 dest_attr[idx]->dest = sample_act->dr_port_id_action;
9329 case MLX5_FLOW_ACTION_JUMP:
9330 dest_attr[idx]->dest = sample_act->dr_jump_action;
9333 rte_flow_error_set(error, EINVAL,
9334 RTE_FLOW_ERROR_TYPE_ACTION,
9336 "unsupported actions type");
9340 /* create a dest array actioin */
9341 ret = mlx5_os_flow_dr_create_flow_action_dest_array
9343 cache_resource->num_of_dest,
9345 &cache_resource->action);
9347 rte_flow_error_set(error, ENOMEM,
9348 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9350 "cannot create destination array action");
9353 cache_resource->idx = res_idx;
9354 cache_resource->dev = dev;
9355 for (idx = 0; idx < resource->num_of_dest; idx++)
9356 mlx5_free(dest_attr[idx]);
9357 return &cache_resource->entry;
9359 for (idx = 0; idx < resource->num_of_dest; idx++) {
9360 struct mlx5_flow_sub_actions_idx *act_res =
9361 &cache_resource->sample_idx[idx];
9362 if (act_res->rix_hrxq &&
9363 !mlx5_hrxq_release(dev,
9365 act_res->rix_hrxq = 0;
9366 if (act_res->rix_encap_decap &&
9367 !flow_dv_encap_decap_resource_release(dev,
9368 act_res->rix_encap_decap))
9369 act_res->rix_encap_decap = 0;
9370 if (act_res->rix_port_id_action &&
9371 !flow_dv_port_id_action_resource_release(dev,
9372 act_res->rix_port_id_action))
9373 act_res->rix_port_id_action = 0;
9374 if (act_res->rix_jump &&
9375 !flow_dv_jump_tbl_resource_release(dev,
9377 act_res->rix_jump = 0;
9379 mlx5_free(dest_attr[idx]);
9382 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9387 * Find existing destination array resource or create and register a new one.
9389 * @param[in, out] dev
9390 * Pointer to rte_eth_dev structure.
9391 * @param[in] resource
9392 * Pointer to destination array resource.
9393 * @parm[in, out] dev_flow
9394 * Pointer to the dev_flow.
9396 * pointer to error structure.
9399 * 0 on success otherwise -errno and errno is set.
9402 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9403 struct mlx5_flow_dv_dest_array_resource *resource,
9404 struct mlx5_flow *dev_flow,
9405 struct rte_flow_error *error)
9407 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9408 struct mlx5_priv *priv = dev->data->dev_private;
9409 struct mlx5_cache_entry *entry;
9410 struct mlx5_flow_cb_ctx ctx = {
9416 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9419 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9420 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9421 dev_flow->dv.dest_array_res = cache_resource;
9426 * Convert Sample action to DV specification.
9429 * Pointer to rte_eth_dev structure.
9431 * Pointer to sample action structure.
9432 * @param[in, out] dev_flow
9433 * Pointer to the mlx5_flow.
9435 * Pointer to the flow attributes.
9436 * @param[in, out] num_of_dest
9437 * Pointer to the num of destination.
9438 * @param[in, out] sample_actions
9439 * Pointer to sample actions list.
9440 * @param[in, out] res
9441 * Pointer to sample resource.
9443 * Pointer to the error structure.
9446 * 0 on success, a negative errno value otherwise and rte_errno is set.
9449 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9450 const struct rte_flow_action_sample *action,
9451 struct mlx5_flow *dev_flow,
9452 const struct rte_flow_attr *attr,
9453 uint32_t *num_of_dest,
9454 void **sample_actions,
9455 struct mlx5_flow_dv_sample_resource *res,
9456 struct rte_flow_error *error)
9458 struct mlx5_priv *priv = dev->data->dev_private;
9459 const struct rte_flow_action *sub_actions;
9460 struct mlx5_flow_sub_actions_list *sample_act;
9461 struct mlx5_flow_sub_actions_idx *sample_idx;
9462 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9463 struct mlx5_flow_rss_desc *rss_desc;
9464 uint64_t action_flags = 0;
9467 rss_desc = &wks->rss_desc;
9468 sample_act = &res->sample_act;
9469 sample_idx = &res->sample_idx;
9470 res->ratio = action->ratio;
9471 sub_actions = action->actions;
9472 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9473 int type = sub_actions->type;
9474 uint32_t pre_rix = 0;
9477 case RTE_FLOW_ACTION_TYPE_QUEUE:
9479 const struct rte_flow_action_queue *queue;
9480 struct mlx5_hrxq *hrxq;
9483 queue = sub_actions->conf;
9484 rss_desc->queue_num = 1;
9485 rss_desc->queue[0] = queue->index;
9486 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9487 rss_desc, &hrxq_idx);
9489 return rte_flow_error_set
9491 RTE_FLOW_ERROR_TYPE_ACTION,
9493 "cannot create fate queue");
9494 sample_act->dr_queue_action = hrxq->action;
9495 sample_idx->rix_hrxq = hrxq_idx;
9496 sample_actions[sample_act->actions_num++] =
9499 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9500 if (action_flags & MLX5_FLOW_ACTION_MARK)
9501 dev_flow->handle->rix_hrxq = hrxq_idx;
9502 dev_flow->handle->fate_action =
9503 MLX5_FLOW_FATE_QUEUE;
9506 case RTE_FLOW_ACTION_TYPE_RSS:
9508 struct mlx5_hrxq *hrxq;
9510 const struct rte_flow_action_rss *rss;
9511 const uint8_t *rss_key;
9513 rss = sub_actions->conf;
9514 memcpy(rss_desc->queue, rss->queue,
9515 rss->queue_num * sizeof(uint16_t));
9516 rss_desc->queue_num = rss->queue_num;
9517 /* NULL RSS key indicates default RSS key. */
9518 rss_key = !rss->key ? rss_hash_default_key : rss->key;
9519 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9521 * rss->level and rss.types should be set in advance
9522 * when expanding items for RSS.
9524 flow_dv_hashfields_set(dev_flow, rss_desc);
9525 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9526 rss_desc, &hrxq_idx);
9528 return rte_flow_error_set
9530 RTE_FLOW_ERROR_TYPE_ACTION,
9532 "cannot create fate queue");
9533 sample_act->dr_queue_action = hrxq->action;
9534 sample_idx->rix_hrxq = hrxq_idx;
9535 sample_actions[sample_act->actions_num++] =
9538 action_flags |= MLX5_FLOW_ACTION_RSS;
9539 if (action_flags & MLX5_FLOW_ACTION_MARK)
9540 dev_flow->handle->rix_hrxq = hrxq_idx;
9541 dev_flow->handle->fate_action =
9542 MLX5_FLOW_FATE_QUEUE;
9545 case RTE_FLOW_ACTION_TYPE_MARK:
9547 uint32_t tag_be = mlx5_flow_mark_set
9548 (((const struct rte_flow_action_mark *)
9549 (sub_actions->conf))->id);
9551 dev_flow->handle->mark = 1;
9552 pre_rix = dev_flow->handle->dvh.rix_tag;
9553 /* Save the mark resource before sample */
9554 pre_r = dev_flow->dv.tag_resource;
9555 if (flow_dv_tag_resource_register(dev, tag_be,
9558 MLX5_ASSERT(dev_flow->dv.tag_resource);
9559 sample_act->dr_tag_action =
9560 dev_flow->dv.tag_resource->action;
9561 sample_idx->rix_tag =
9562 dev_flow->handle->dvh.rix_tag;
9563 sample_actions[sample_act->actions_num++] =
9564 sample_act->dr_tag_action;
9565 /* Recover the mark resource after sample */
9566 dev_flow->dv.tag_resource = pre_r;
9567 dev_flow->handle->dvh.rix_tag = pre_rix;
9568 action_flags |= MLX5_FLOW_ACTION_MARK;
9571 case RTE_FLOW_ACTION_TYPE_COUNT:
9575 counter = flow_dv_translate_create_counter(dev,
9576 dev_flow, sub_actions->conf, 0);
9578 return rte_flow_error_set
9580 RTE_FLOW_ERROR_TYPE_ACTION,
9582 "cannot create counter"
9584 sample_idx->cnt = counter;
9585 sample_act->dr_cnt_action =
9586 (flow_dv_counter_get_by_idx(dev,
9587 counter, NULL))->action;
9588 sample_actions[sample_act->actions_num++] =
9589 sample_act->dr_cnt_action;
9590 action_flags |= MLX5_FLOW_ACTION_COUNT;
9593 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9595 struct mlx5_flow_dv_port_id_action_resource
9597 uint32_t port_id = 0;
9599 memset(&port_id_resource, 0, sizeof(port_id_resource));
9600 /* Save the port id resource before sample */
9601 pre_rix = dev_flow->handle->rix_port_id_action;
9602 pre_r = dev_flow->dv.port_id_action;
9603 if (flow_dv_translate_action_port_id(dev, sub_actions,
9606 port_id_resource.port_id = port_id;
9607 if (flow_dv_port_id_action_resource_register
9608 (dev, &port_id_resource, dev_flow, error))
9610 sample_act->dr_port_id_action =
9611 dev_flow->dv.port_id_action->action;
9612 sample_idx->rix_port_id_action =
9613 dev_flow->handle->rix_port_id_action;
9614 sample_actions[sample_act->actions_num++] =
9615 sample_act->dr_port_id_action;
9616 /* Recover the port id resource after sample */
9617 dev_flow->dv.port_id_action = pre_r;
9618 dev_flow->handle->rix_port_id_action = pre_rix;
9620 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9623 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9624 /* Save the encap resource before sample */
9625 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9626 pre_r = dev_flow->dv.encap_decap;
9627 if (flow_dv_create_action_l2_encap(dev, sub_actions,
9632 sample_act->dr_encap_action =
9633 dev_flow->dv.encap_decap->action;
9634 sample_idx->rix_encap_decap =
9635 dev_flow->handle->dvh.rix_encap_decap;
9636 sample_actions[sample_act->actions_num++] =
9637 sample_act->dr_encap_action;
9638 /* Recover the encap resource after sample */
9639 dev_flow->dv.encap_decap = pre_r;
9640 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9641 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9644 return rte_flow_error_set(error, EINVAL,
9645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9647 "Not support for sampler action");
9650 sample_act->action_flags = action_flags;
9651 res->ft_id = dev_flow->dv.group;
9652 if (attr->transfer) {
9654 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9655 uint64_t set_action;
9656 } action_ctx = { .set_action = 0 };
9658 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9659 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9660 MLX5_MODIFICATION_TYPE_SET);
9661 MLX5_SET(set_action_in, action_ctx.action_in, field,
9662 MLX5_MODI_META_REG_C_0);
9663 MLX5_SET(set_action_in, action_ctx.action_in, data,
9664 priv->vport_meta_tag);
9665 res->set_action = action_ctx.set_action;
9666 } else if (attr->ingress) {
9667 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9669 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9675 * Convert Sample action to DV specification.
9678 * Pointer to rte_eth_dev structure.
9679 * @param[in, out] dev_flow
9680 * Pointer to the mlx5_flow.
9681 * @param[in] num_of_dest
9682 * The num of destination.
9683 * @param[in, out] res
9684 * Pointer to sample resource.
9685 * @param[in, out] mdest_res
9686 * Pointer to destination array resource.
9687 * @param[in] sample_actions
9688 * Pointer to sample path actions list.
9689 * @param[in] action_flags
9690 * Holds the actions detected until now.
9692 * Pointer to the error structure.
9695 * 0 on success, a negative errno value otherwise and rte_errno is set.
9698 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9699 struct mlx5_flow *dev_flow,
9700 uint32_t num_of_dest,
9701 struct mlx5_flow_dv_sample_resource *res,
9702 struct mlx5_flow_dv_dest_array_resource *mdest_res,
9703 void **sample_actions,
9704 uint64_t action_flags,
9705 struct rte_flow_error *error)
9707 /* update normal path action resource into last index of array */
9708 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9709 struct mlx5_flow_sub_actions_list *sample_act =
9710 &mdest_res->sample_act[dest_index];
9711 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9712 struct mlx5_flow_rss_desc *rss_desc;
9713 uint32_t normal_idx = 0;
9714 struct mlx5_hrxq *hrxq;
9718 rss_desc = &wks->rss_desc;
9719 if (num_of_dest > 1) {
9720 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9721 /* Handle QP action for mirroring */
9722 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9723 rss_desc, &hrxq_idx);
9725 return rte_flow_error_set
9727 RTE_FLOW_ERROR_TYPE_ACTION,
9729 "cannot create rx queue");
9731 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9732 sample_act->dr_queue_action = hrxq->action;
9733 if (action_flags & MLX5_FLOW_ACTION_MARK)
9734 dev_flow->handle->rix_hrxq = hrxq_idx;
9735 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9737 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9739 mdest_res->sample_idx[dest_index].rix_encap_decap =
9740 dev_flow->handle->dvh.rix_encap_decap;
9741 sample_act->dr_encap_action =
9742 dev_flow->dv.encap_decap->action;
9744 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9746 mdest_res->sample_idx[dest_index].rix_port_id_action =
9747 dev_flow->handle->rix_port_id_action;
9748 sample_act->dr_port_id_action =
9749 dev_flow->dv.port_id_action->action;
9751 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
9753 mdest_res->sample_idx[dest_index].rix_jump =
9754 dev_flow->handle->rix_jump;
9755 sample_act->dr_jump_action =
9756 dev_flow->dv.jump->action;
9757 dev_flow->handle->rix_jump = 0;
9759 sample_act->actions_num = normal_idx;
9760 /* update sample action resource into first index of array */
9761 mdest_res->ft_type = res->ft_type;
9762 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9763 sizeof(struct mlx5_flow_sub_actions_idx));
9764 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9765 sizeof(struct mlx5_flow_sub_actions_list));
9766 mdest_res->num_of_dest = num_of_dest;
9767 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9769 return rte_flow_error_set(error, EINVAL,
9770 RTE_FLOW_ERROR_TYPE_ACTION,
9771 NULL, "can't create sample "
9774 res->sub_actions = sample_actions;
9775 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9776 return rte_flow_error_set(error, EINVAL,
9777 RTE_FLOW_ERROR_TYPE_ACTION,
9779 "can't create sample action");
9785 * Remove an ASO age action from age actions list.
9788 * Pointer to the Ethernet device structure.
9790 * Pointer to the aso age action handler.
9793 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9794 struct mlx5_aso_age_action *age)
9796 struct mlx5_age_info *age_info;
9797 struct mlx5_age_param *age_param = &age->age_params;
9798 struct mlx5_priv *priv = dev->data->dev_private;
9799 uint16_t expected = AGE_CANDIDATE;
9801 age_info = GET_PORT_AGE_INFO(priv);
9802 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9803 AGE_FREE, false, __ATOMIC_RELAXED,
9804 __ATOMIC_RELAXED)) {
9806 * We need the lock even it is age timeout,
9807 * since age action may still in process.
9809 rte_spinlock_lock(&age_info->aged_sl);
9810 LIST_REMOVE(age, next);
9811 rte_spinlock_unlock(&age_info->aged_sl);
9812 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9817 * Release an ASO age action.
9820 * Pointer to the Ethernet device structure.
9821 * @param[in] age_idx
9822 * Index of ASO age action to release.
9824 * True if the release operation is during flow destroy operation.
9825 * False if the release operation is during action destroy operation.
9828 * 0 when age action was removed, otherwise the number of references.
9831 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9833 struct mlx5_priv *priv = dev->data->dev_private;
9834 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9835 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9836 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9839 flow_dv_aso_age_remove_from_age(dev, age);
9840 rte_spinlock_lock(&mng->free_sl);
9841 LIST_INSERT_HEAD(&mng->free, age, next);
9842 rte_spinlock_unlock(&mng->free_sl);
9848 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9851 * Pointer to the Ethernet device structure.
9854 * 0 on success, otherwise negative errno value and rte_errno is set.
9857 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9859 struct mlx5_priv *priv = dev->data->dev_private;
9860 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9861 void *old_pools = mng->pools;
9862 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9863 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9864 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9871 memcpy(pools, old_pools,
9872 mng->n * sizeof(struct mlx5_flow_counter_pool *));
9873 mlx5_free(old_pools);
9875 /* First ASO flow hit allocation - starting ASO data-path. */
9876 int ret = mlx5_aso_queue_start(priv->sh);
9889 * Create and initialize a new ASO aging pool.
9892 * Pointer to the Ethernet device structure.
9893 * @param[out] age_free
9894 * Where to put the pointer of a new age action.
9897 * The age actions pool pointer and @p age_free is set on success,
9898 * NULL otherwise and rte_errno is set.
9900 static struct mlx5_aso_age_pool *
9901 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9902 struct mlx5_aso_age_action **age_free)
9904 struct mlx5_priv *priv = dev->data->dev_private;
9905 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9906 struct mlx5_aso_age_pool *pool = NULL;
9907 struct mlx5_devx_obj *obj = NULL;
9910 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9913 rte_errno = ENODATA;
9914 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9917 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9919 claim_zero(mlx5_devx_cmd_destroy(obj));
9923 pool->flow_hit_aso_obj = obj;
9924 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9925 rte_spinlock_lock(&mng->resize_sl);
9926 pool->index = mng->next;
9927 /* Resize pools array if there is no room for the new pool in it. */
9928 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9929 claim_zero(mlx5_devx_cmd_destroy(obj));
9931 rte_spinlock_unlock(&mng->resize_sl);
9934 mng->pools[pool->index] = pool;
9936 rte_spinlock_unlock(&mng->resize_sl);
9937 /* Assign the first action in the new pool, the rest go to free list. */
9938 *age_free = &pool->actions[0];
9939 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9940 pool->actions[i].offset = i;
9941 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9947 * Allocate a ASO aging bit.
9950 * Pointer to the Ethernet device structure.
9952 * Pointer to the error structure.
9955 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
9958 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9960 struct mlx5_priv *priv = dev->data->dev_private;
9961 const struct mlx5_aso_age_pool *pool;
9962 struct mlx5_aso_age_action *age_free = NULL;
9963 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9966 /* Try to get the next free age action bit. */
9967 rte_spinlock_lock(&mng->free_sl);
9968 age_free = LIST_FIRST(&mng->free);
9970 LIST_REMOVE(age_free, next);
9971 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9972 rte_spinlock_unlock(&mng->free_sl);
9973 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9974 NULL, "failed to create ASO age pool");
9975 return 0; /* 0 is an error. */
9977 rte_spinlock_unlock(&mng->free_sl);
9979 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9980 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9982 if (!age_free->dr_action) {
9983 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9987 rte_flow_error_set(error, rte_errno,
9988 RTE_FLOW_ERROR_TYPE_ACTION,
9989 NULL, "failed to get reg_c "
9990 "for ASO flow hit");
9991 return 0; /* 0 is an error. */
9993 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9994 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9995 (priv->sh->rx_domain,
9996 pool->flow_hit_aso_obj->obj, age_free->offset,
9997 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9999 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10000 if (!age_free->dr_action) {
10002 rte_spinlock_lock(&mng->free_sl);
10003 LIST_INSERT_HEAD(&mng->free, age_free, next);
10004 rte_spinlock_unlock(&mng->free_sl);
10005 rte_flow_error_set(error, rte_errno,
10006 RTE_FLOW_ERROR_TYPE_ACTION,
10007 NULL, "failed to create ASO "
10008 "flow hit action");
10009 return 0; /* 0 is an error. */
10012 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10013 return pool->index | ((age_free->offset + 1) << 16);
10017 * Create a age action using ASO mechanism.
10020 * Pointer to rte_eth_dev structure.
10022 * Pointer to the aging action configuration.
10023 * @param[out] error
10024 * Pointer to the error structure.
10027 * Index to flow counter on success, 0 otherwise.
10030 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10031 const struct rte_flow_action_age *age,
10032 struct rte_flow_error *error)
10034 uint32_t age_idx = 0;
10035 struct mlx5_aso_age_action *aso_age;
10037 age_idx = flow_dv_aso_age_alloc(dev, error);
10040 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10041 aso_age->age_params.context = age->context;
10042 aso_age->age_params.timeout = age->timeout;
10043 aso_age->age_params.port_id = dev->data->port_id;
10044 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10046 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10052 * Fill the flow with DV spec, lock free
10053 * (mutex should be acquired by caller).
10056 * Pointer to rte_eth_dev structure.
10057 * @param[in, out] dev_flow
10058 * Pointer to the sub flow.
10060 * Pointer to the flow attributes.
10062 * Pointer to the list of items.
10063 * @param[in] actions
10064 * Pointer to the list of actions.
10065 * @param[out] error
10066 * Pointer to the error structure.
10069 * 0 on success, a negative errno value otherwise and rte_errno is set.
10072 flow_dv_translate(struct rte_eth_dev *dev,
10073 struct mlx5_flow *dev_flow,
10074 const struct rte_flow_attr *attr,
10075 const struct rte_flow_item items[],
10076 const struct rte_flow_action actions[],
10077 struct rte_flow_error *error)
10079 struct mlx5_priv *priv = dev->data->dev_private;
10080 struct mlx5_dev_config *dev_conf = &priv->config;
10081 struct rte_flow *flow = dev_flow->flow;
10082 struct mlx5_flow_handle *handle = dev_flow->handle;
10083 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10084 struct mlx5_flow_rss_desc *rss_desc;
10085 uint64_t item_flags = 0;
10086 uint64_t last_item = 0;
10087 uint64_t action_flags = 0;
10088 struct mlx5_flow_dv_matcher matcher = {
10090 .size = sizeof(matcher.mask.buf) -
10091 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10095 bool actions_end = false;
10097 struct mlx5_flow_dv_modify_hdr_resource res;
10098 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10099 sizeof(struct mlx5_modification_cmd) *
10100 (MLX5_MAX_MODIFY_NUM + 1)];
10102 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10103 const struct rte_flow_action_count *count = NULL;
10104 const struct rte_flow_action_age *age = NULL;
10105 union flow_dv_attr flow_attr = { .attr = 0 };
10107 union mlx5_flow_tbl_key tbl_key;
10108 uint32_t modify_action_position = UINT32_MAX;
10109 void *match_mask = matcher.mask.buf;
10110 void *match_value = dev_flow->dv.value.buf;
10111 uint8_t next_protocol = 0xff;
10112 struct rte_vlan_hdr vlan = { 0 };
10113 struct mlx5_flow_dv_dest_array_resource mdest_res;
10114 struct mlx5_flow_dv_sample_resource sample_res;
10115 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10116 const struct rte_flow_action_sample *sample = NULL;
10117 struct mlx5_flow_sub_actions_list *sample_act;
10118 uint32_t sample_act_pos = UINT32_MAX;
10119 uint32_t num_of_dest = 0;
10120 int tmp_actions_n = 0;
10123 const struct mlx5_flow_tunnel *tunnel;
10124 struct flow_grp_info grp_info = {
10125 .external = !!dev_flow->external,
10126 .transfer = !!attr->transfer,
10127 .fdb_def_rule = !!priv->fdb_def_rule,
10128 .skip_scale = dev_flow->skip_scale &
10129 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10133 return rte_flow_error_set(error, ENOMEM,
10134 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10136 "failed to push flow workspace");
10137 rss_desc = &wks->rss_desc;
10138 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10139 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10140 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10141 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10142 /* update normal path action resource into last index of array */
10143 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10144 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10145 flow_items_to_tunnel(items) :
10146 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10147 flow_actions_to_tunnel(actions) :
10148 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10149 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10150 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10151 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10152 (dev, tunnel, attr, items, actions);
10153 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10157 dev_flow->dv.group = table;
10158 if (attr->transfer)
10159 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10160 /* number of actions must be set to 0 in case of dirty stack. */
10161 mhdr_res->actions_num = 0;
10162 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10164 * do not add decap action if match rule drops packet
10165 * HW rejects rules with decap & drop
10167 * if tunnel match rule was inserted before matching tunnel set
10168 * rule flow table used in the match rule must be registered.
10169 * current implementation handles that in the
10170 * flow_dv_match_register() at the function end.
10172 bool add_decap = true;
10173 const struct rte_flow_action *ptr = actions;
10175 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10176 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10182 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10186 dev_flow->dv.actions[actions_n++] =
10187 dev_flow->dv.encap_decap->action;
10188 action_flags |= MLX5_FLOW_ACTION_DECAP;
10191 for (; !actions_end ; actions++) {
10192 const struct rte_flow_action_queue *queue;
10193 const struct rte_flow_action_rss *rss;
10194 const struct rte_flow_action *action = actions;
10195 const uint8_t *rss_key;
10196 const struct rte_flow_action_meter *mtr;
10197 struct mlx5_flow_tbl_resource *tbl;
10198 struct mlx5_aso_age_action *age_act;
10199 uint32_t port_id = 0;
10200 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10201 int action_type = actions->type;
10202 const struct rte_flow_action *found_action = NULL;
10203 struct mlx5_flow_meter *fm = NULL;
10204 uint32_t jump_group = 0;
10206 if (!mlx5_flow_os_action_supported(action_type))
10207 return rte_flow_error_set(error, ENOTSUP,
10208 RTE_FLOW_ERROR_TYPE_ACTION,
10210 "action not supported");
10211 switch (action_type) {
10212 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10213 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10215 case RTE_FLOW_ACTION_TYPE_VOID:
10217 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10218 if (flow_dv_translate_action_port_id(dev, action,
10221 port_id_resource.port_id = port_id;
10222 MLX5_ASSERT(!handle->rix_port_id_action);
10223 if (flow_dv_port_id_action_resource_register
10224 (dev, &port_id_resource, dev_flow, error))
10226 dev_flow->dv.actions[actions_n++] =
10227 dev_flow->dv.port_id_action->action;
10228 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10229 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10230 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10233 case RTE_FLOW_ACTION_TYPE_FLAG:
10234 action_flags |= MLX5_FLOW_ACTION_FLAG;
10235 dev_flow->handle->mark = 1;
10236 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10237 struct rte_flow_action_mark mark = {
10238 .id = MLX5_FLOW_MARK_DEFAULT,
10241 if (flow_dv_convert_action_mark(dev, &mark,
10245 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10248 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10250 * Only one FLAG or MARK is supported per device flow
10251 * right now. So the pointer to the tag resource must be
10252 * zero before the register process.
10254 MLX5_ASSERT(!handle->dvh.rix_tag);
10255 if (flow_dv_tag_resource_register(dev, tag_be,
10258 MLX5_ASSERT(dev_flow->dv.tag_resource);
10259 dev_flow->dv.actions[actions_n++] =
10260 dev_flow->dv.tag_resource->action;
10262 case RTE_FLOW_ACTION_TYPE_MARK:
10263 action_flags |= MLX5_FLOW_ACTION_MARK;
10264 dev_flow->handle->mark = 1;
10265 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10266 const struct rte_flow_action_mark *mark =
10267 (const struct rte_flow_action_mark *)
10270 if (flow_dv_convert_action_mark(dev, mark,
10274 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10278 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10279 /* Legacy (non-extensive) MARK action. */
10280 tag_be = mlx5_flow_mark_set
10281 (((const struct rte_flow_action_mark *)
10282 (actions->conf))->id);
10283 MLX5_ASSERT(!handle->dvh.rix_tag);
10284 if (flow_dv_tag_resource_register(dev, tag_be,
10287 MLX5_ASSERT(dev_flow->dv.tag_resource);
10288 dev_flow->dv.actions[actions_n++] =
10289 dev_flow->dv.tag_resource->action;
10291 case RTE_FLOW_ACTION_TYPE_SET_META:
10292 if (flow_dv_convert_action_set_meta
10293 (dev, mhdr_res, attr,
10294 (const struct rte_flow_action_set_meta *)
10295 actions->conf, error))
10297 action_flags |= MLX5_FLOW_ACTION_SET_META;
10299 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10300 if (flow_dv_convert_action_set_tag
10302 (const struct rte_flow_action_set_tag *)
10303 actions->conf, error))
10305 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10307 case RTE_FLOW_ACTION_TYPE_DROP:
10308 action_flags |= MLX5_FLOW_ACTION_DROP;
10309 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10311 case RTE_FLOW_ACTION_TYPE_QUEUE:
10312 queue = actions->conf;
10313 rss_desc->queue_num = 1;
10314 rss_desc->queue[0] = queue->index;
10315 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10316 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10317 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10320 case RTE_FLOW_ACTION_TYPE_RSS:
10321 rss = actions->conf;
10322 memcpy(rss_desc->queue, rss->queue,
10323 rss->queue_num * sizeof(uint16_t));
10324 rss_desc->queue_num = rss->queue_num;
10325 /* NULL RSS key indicates default RSS key. */
10326 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10327 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10329 * rss->level and rss.types should be set in advance
10330 * when expanding items for RSS.
10332 action_flags |= MLX5_FLOW_ACTION_RSS;
10333 dev_flow->handle->fate_action = rss_desc->shared_rss ?
10334 MLX5_FLOW_FATE_SHARED_RSS :
10335 MLX5_FLOW_FATE_QUEUE;
10337 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10338 flow->age = (uint32_t)(uintptr_t)(action->conf);
10339 age_act = flow_aso_age_get_by_idx(dev, flow->age);
10340 __atomic_fetch_add(&age_act->refcnt, 1,
10342 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10343 action_flags |= MLX5_FLOW_ACTION_AGE;
10345 case RTE_FLOW_ACTION_TYPE_AGE:
10346 if (priv->sh->flow_hit_aso_en && attr->group) {
10348 * Create one shared age action, to be used
10349 * by all sub-flows.
10353 flow_dv_translate_create_aso_age
10354 (dev, action->conf,
10357 return rte_flow_error_set
10359 RTE_FLOW_ERROR_TYPE_ACTION,
10361 "can't create ASO age action");
10363 dev_flow->dv.actions[actions_n++] =
10364 (flow_aso_age_get_by_idx
10365 (dev, flow->age))->dr_action;
10366 action_flags |= MLX5_FLOW_ACTION_AGE;
10370 case RTE_FLOW_ACTION_TYPE_COUNT:
10371 if (!dev_conf->devx) {
10372 return rte_flow_error_set
10374 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10376 "count action not supported");
10378 /* Save information first, will apply later. */
10379 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10380 count = action->conf;
10382 age = action->conf;
10383 action_flags |= MLX5_FLOW_ACTION_COUNT;
10385 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10386 dev_flow->dv.actions[actions_n++] =
10387 priv->sh->pop_vlan_action;
10388 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10390 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10391 if (!(action_flags &
10392 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10393 flow_dev_get_vlan_info_from_items(items, &vlan);
10394 vlan.eth_proto = rte_be_to_cpu_16
10395 ((((const struct rte_flow_action_of_push_vlan *)
10396 actions->conf)->ethertype));
10397 found_action = mlx5_flow_find_action
10399 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10401 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10402 found_action = mlx5_flow_find_action
10404 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10406 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10407 if (flow_dv_create_action_push_vlan
10408 (dev, attr, &vlan, dev_flow, error))
10410 dev_flow->dv.actions[actions_n++] =
10411 dev_flow->dv.push_vlan_res->action;
10412 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10414 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10415 /* of_vlan_push action handled this action */
10416 MLX5_ASSERT(action_flags &
10417 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10419 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10420 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10422 flow_dev_get_vlan_info_from_items(items, &vlan);
10423 mlx5_update_vlan_vid_pcp(actions, &vlan);
10424 /* If no VLAN push - this is a modify header action */
10425 if (flow_dv_convert_action_modify_vlan_vid
10426 (mhdr_res, actions, error))
10428 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10430 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10431 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10432 if (flow_dv_create_action_l2_encap(dev, actions,
10437 dev_flow->dv.actions[actions_n++] =
10438 dev_flow->dv.encap_decap->action;
10439 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10440 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10441 sample_act->action_flags |=
10442 MLX5_FLOW_ACTION_ENCAP;
10444 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10445 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10446 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10450 dev_flow->dv.actions[actions_n++] =
10451 dev_flow->dv.encap_decap->action;
10452 action_flags |= MLX5_FLOW_ACTION_DECAP;
10454 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10455 /* Handle encap with preceding decap. */
10456 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10457 if (flow_dv_create_action_raw_encap
10458 (dev, actions, dev_flow, attr, error))
10460 dev_flow->dv.actions[actions_n++] =
10461 dev_flow->dv.encap_decap->action;
10463 /* Handle encap without preceding decap. */
10464 if (flow_dv_create_action_l2_encap
10465 (dev, actions, dev_flow, attr->transfer,
10468 dev_flow->dv.actions[actions_n++] =
10469 dev_flow->dv.encap_decap->action;
10471 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10472 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10473 sample_act->action_flags |=
10474 MLX5_FLOW_ACTION_ENCAP;
10476 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10477 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10479 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10480 if (flow_dv_create_action_l2_decap
10481 (dev, dev_flow, attr->transfer, error))
10483 dev_flow->dv.actions[actions_n++] =
10484 dev_flow->dv.encap_decap->action;
10486 /* If decap is followed by encap, handle it at encap. */
10487 action_flags |= MLX5_FLOW_ACTION_DECAP;
10489 case RTE_FLOW_ACTION_TYPE_JUMP:
10490 jump_group = ((const struct rte_flow_action_jump *)
10491 action->conf)->group;
10492 grp_info.std_tbl_fix = 0;
10493 if (dev_flow->skip_scale &
10494 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
10495 grp_info.skip_scale = 1;
10497 grp_info.skip_scale = 0;
10498 ret = mlx5_flow_group_to_table(dev, tunnel,
10504 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10506 !!dev_flow->external,
10507 tunnel, jump_group, 0,
10510 return rte_flow_error_set
10512 RTE_FLOW_ERROR_TYPE_ACTION,
10514 "cannot create jump action.");
10515 if (flow_dv_jump_tbl_resource_register
10516 (dev, tbl, dev_flow, error)) {
10517 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10518 return rte_flow_error_set
10520 RTE_FLOW_ERROR_TYPE_ACTION,
10522 "cannot create jump action.");
10524 dev_flow->dv.actions[actions_n++] =
10525 dev_flow->dv.jump->action;
10526 action_flags |= MLX5_FLOW_ACTION_JUMP;
10527 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10528 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
10531 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10532 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10533 if (flow_dv_convert_action_modify_mac
10534 (mhdr_res, actions, error))
10536 action_flags |= actions->type ==
10537 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10538 MLX5_FLOW_ACTION_SET_MAC_SRC :
10539 MLX5_FLOW_ACTION_SET_MAC_DST;
10541 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10542 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10543 if (flow_dv_convert_action_modify_ipv4
10544 (mhdr_res, actions, error))
10546 action_flags |= actions->type ==
10547 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10548 MLX5_FLOW_ACTION_SET_IPV4_SRC :
10549 MLX5_FLOW_ACTION_SET_IPV4_DST;
10551 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10552 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10553 if (flow_dv_convert_action_modify_ipv6
10554 (mhdr_res, actions, error))
10556 action_flags |= actions->type ==
10557 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10558 MLX5_FLOW_ACTION_SET_IPV6_SRC :
10559 MLX5_FLOW_ACTION_SET_IPV6_DST;
10561 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10562 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10563 if (flow_dv_convert_action_modify_tp
10564 (mhdr_res, actions, items,
10565 &flow_attr, dev_flow, !!(action_flags &
10566 MLX5_FLOW_ACTION_DECAP), error))
10568 action_flags |= actions->type ==
10569 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10570 MLX5_FLOW_ACTION_SET_TP_SRC :
10571 MLX5_FLOW_ACTION_SET_TP_DST;
10573 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10574 if (flow_dv_convert_action_modify_dec_ttl
10575 (mhdr_res, items, &flow_attr, dev_flow,
10577 MLX5_FLOW_ACTION_DECAP), error))
10579 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10581 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10582 if (flow_dv_convert_action_modify_ttl
10583 (mhdr_res, actions, items, &flow_attr,
10584 dev_flow, !!(action_flags &
10585 MLX5_FLOW_ACTION_DECAP), error))
10587 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10589 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10590 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10591 if (flow_dv_convert_action_modify_tcp_seq
10592 (mhdr_res, actions, error))
10594 action_flags |= actions->type ==
10595 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10596 MLX5_FLOW_ACTION_INC_TCP_SEQ :
10597 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10600 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10601 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10602 if (flow_dv_convert_action_modify_tcp_ack
10603 (mhdr_res, actions, error))
10605 action_flags |= actions->type ==
10606 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10607 MLX5_FLOW_ACTION_INC_TCP_ACK :
10608 MLX5_FLOW_ACTION_DEC_TCP_ACK;
10610 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10611 if (flow_dv_convert_action_set_reg
10612 (mhdr_res, actions, error))
10614 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10616 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10617 if (flow_dv_convert_action_copy_mreg
10618 (dev, mhdr_res, actions, error))
10620 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10622 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10623 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10624 dev_flow->handle->fate_action =
10625 MLX5_FLOW_FATE_DEFAULT_MISS;
10627 case RTE_FLOW_ACTION_TYPE_METER:
10628 mtr = actions->conf;
10629 if (!flow->meter) {
10630 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10633 return rte_flow_error_set(error,
10635 RTE_FLOW_ERROR_TYPE_ACTION,
10638 "or invalid parameters");
10639 flow->meter = fm->idx;
10641 /* Set the meter action. */
10643 fm = mlx5_ipool_get(priv->sh->ipool
10644 [MLX5_IPOOL_MTR], flow->meter);
10646 return rte_flow_error_set(error,
10648 RTE_FLOW_ERROR_TYPE_ACTION,
10651 "or invalid parameters");
10653 dev_flow->dv.actions[actions_n++] =
10654 fm->mfts->meter_action;
10655 action_flags |= MLX5_FLOW_ACTION_METER;
10657 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10658 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10661 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10663 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10664 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10667 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10669 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10670 sample_act_pos = actions_n;
10671 sample = (const struct rte_flow_action_sample *)
10674 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10675 /* put encap action into group if work with port id */
10676 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10677 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10678 sample_act->action_flags |=
10679 MLX5_FLOW_ACTION_ENCAP;
10681 case RTE_FLOW_ACTION_TYPE_END:
10682 actions_end = true;
10683 if (mhdr_res->actions_num) {
10684 /* create modify action if needed. */
10685 if (flow_dv_modify_hdr_resource_register
10686 (dev, mhdr_res, dev_flow, error))
10688 dev_flow->dv.actions[modify_action_position] =
10689 handle->dvh.modify_hdr->action;
10691 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10693 * Create one count action, to be used
10694 * by all sub-flows.
10696 if (!flow->counter) {
10698 flow_dv_translate_create_counter
10699 (dev, dev_flow, count,
10701 if (!flow->counter)
10702 return rte_flow_error_set
10704 RTE_FLOW_ERROR_TYPE_ACTION,
10705 NULL, "cannot create counter"
10708 dev_flow->dv.actions[actions_n] =
10709 (flow_dv_counter_get_by_idx(dev,
10710 flow->counter, NULL))->action;
10716 if (mhdr_res->actions_num &&
10717 modify_action_position == UINT32_MAX)
10718 modify_action_position = actions_n++;
10720 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10721 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10722 int item_type = items->type;
10724 if (!mlx5_flow_os_item_supported(item_type))
10725 return rte_flow_error_set(error, ENOTSUP,
10726 RTE_FLOW_ERROR_TYPE_ITEM,
10727 NULL, "item not supported");
10728 switch (item_type) {
10729 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10730 flow_dv_translate_item_port_id
10731 (dev, match_mask, match_value, items, attr);
10732 last_item = MLX5_FLOW_ITEM_PORT_ID;
10734 case RTE_FLOW_ITEM_TYPE_ETH:
10735 flow_dv_translate_item_eth(match_mask, match_value,
10737 dev_flow->dv.group);
10738 matcher.priority = action_flags &
10739 MLX5_FLOW_ACTION_DEFAULT_MISS &&
10740 !dev_flow->external ?
10741 MLX5_PRIORITY_MAP_L3 :
10742 MLX5_PRIORITY_MAP_L2;
10743 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10744 MLX5_FLOW_LAYER_OUTER_L2;
10746 case RTE_FLOW_ITEM_TYPE_VLAN:
10747 flow_dv_translate_item_vlan(dev_flow,
10748 match_mask, match_value,
10750 dev_flow->dv.group);
10751 matcher.priority = MLX5_PRIORITY_MAP_L2;
10752 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10753 MLX5_FLOW_LAYER_INNER_VLAN) :
10754 (MLX5_FLOW_LAYER_OUTER_L2 |
10755 MLX5_FLOW_LAYER_OUTER_VLAN);
10757 case RTE_FLOW_ITEM_TYPE_IPV4:
10758 mlx5_flow_tunnel_ip_check(items, next_protocol,
10759 &item_flags, &tunnel);
10760 flow_dv_translate_item_ipv4(match_mask, match_value,
10762 dev_flow->dv.group);
10763 matcher.priority = MLX5_PRIORITY_MAP_L3;
10764 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10765 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10766 if (items->mask != NULL &&
10767 ((const struct rte_flow_item_ipv4 *)
10768 items->mask)->hdr.next_proto_id) {
10770 ((const struct rte_flow_item_ipv4 *)
10771 (items->spec))->hdr.next_proto_id;
10773 ((const struct rte_flow_item_ipv4 *)
10774 (items->mask))->hdr.next_proto_id;
10776 /* Reset for inner layer. */
10777 next_protocol = 0xff;
10780 case RTE_FLOW_ITEM_TYPE_IPV6:
10781 mlx5_flow_tunnel_ip_check(items, next_protocol,
10782 &item_flags, &tunnel);
10783 flow_dv_translate_item_ipv6(match_mask, match_value,
10785 dev_flow->dv.group);
10786 matcher.priority = MLX5_PRIORITY_MAP_L3;
10787 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10788 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10789 if (items->mask != NULL &&
10790 ((const struct rte_flow_item_ipv6 *)
10791 items->mask)->hdr.proto) {
10793 ((const struct rte_flow_item_ipv6 *)
10794 items->spec)->hdr.proto;
10796 ((const struct rte_flow_item_ipv6 *)
10797 items->mask)->hdr.proto;
10799 /* Reset for inner layer. */
10800 next_protocol = 0xff;
10803 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10804 flow_dv_translate_item_ipv6_frag_ext(match_mask,
10807 last_item = tunnel ?
10808 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10809 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10810 if (items->mask != NULL &&
10811 ((const struct rte_flow_item_ipv6_frag_ext *)
10812 items->mask)->hdr.next_header) {
10814 ((const struct rte_flow_item_ipv6_frag_ext *)
10815 items->spec)->hdr.next_header;
10817 ((const struct rte_flow_item_ipv6_frag_ext *)
10818 items->mask)->hdr.next_header;
10820 /* Reset for inner layer. */
10821 next_protocol = 0xff;
10824 case RTE_FLOW_ITEM_TYPE_TCP:
10825 flow_dv_translate_item_tcp(match_mask, match_value,
10827 matcher.priority = MLX5_PRIORITY_MAP_L4;
10828 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10829 MLX5_FLOW_LAYER_OUTER_L4_TCP;
10831 case RTE_FLOW_ITEM_TYPE_UDP:
10832 flow_dv_translate_item_udp(match_mask, match_value,
10834 matcher.priority = MLX5_PRIORITY_MAP_L4;
10835 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10836 MLX5_FLOW_LAYER_OUTER_L4_UDP;
10838 case RTE_FLOW_ITEM_TYPE_GRE:
10839 flow_dv_translate_item_gre(match_mask, match_value,
10841 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10842 last_item = MLX5_FLOW_LAYER_GRE;
10844 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10845 flow_dv_translate_item_gre_key(match_mask,
10846 match_value, items);
10847 last_item = MLX5_FLOW_LAYER_GRE_KEY;
10849 case RTE_FLOW_ITEM_TYPE_NVGRE:
10850 flow_dv_translate_item_nvgre(match_mask, match_value,
10852 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10853 last_item = MLX5_FLOW_LAYER_GRE;
10855 case RTE_FLOW_ITEM_TYPE_VXLAN:
10856 flow_dv_translate_item_vxlan(match_mask, match_value,
10858 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10859 last_item = MLX5_FLOW_LAYER_VXLAN;
10861 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10862 flow_dv_translate_item_vxlan_gpe(match_mask,
10863 match_value, items,
10865 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10866 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10868 case RTE_FLOW_ITEM_TYPE_GENEVE:
10869 flow_dv_translate_item_geneve(match_mask, match_value,
10871 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10872 last_item = MLX5_FLOW_LAYER_GENEVE;
10874 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
10875 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
10879 return rte_flow_error_set(error, -ret,
10880 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10881 "cannot create GENEVE TLV option");
10882 flow->geneve_tlv_option = 1;
10883 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
10885 case RTE_FLOW_ITEM_TYPE_MPLS:
10886 flow_dv_translate_item_mpls(match_mask, match_value,
10887 items, last_item, tunnel);
10888 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10889 last_item = MLX5_FLOW_LAYER_MPLS;
10891 case RTE_FLOW_ITEM_TYPE_MARK:
10892 flow_dv_translate_item_mark(dev, match_mask,
10893 match_value, items);
10894 last_item = MLX5_FLOW_ITEM_MARK;
10896 case RTE_FLOW_ITEM_TYPE_META:
10897 flow_dv_translate_item_meta(dev, match_mask,
10898 match_value, attr, items);
10899 last_item = MLX5_FLOW_ITEM_METADATA;
10901 case RTE_FLOW_ITEM_TYPE_ICMP:
10902 flow_dv_translate_item_icmp(match_mask, match_value,
10904 last_item = MLX5_FLOW_LAYER_ICMP;
10906 case RTE_FLOW_ITEM_TYPE_ICMP6:
10907 flow_dv_translate_item_icmp6(match_mask, match_value,
10909 last_item = MLX5_FLOW_LAYER_ICMP6;
10911 case RTE_FLOW_ITEM_TYPE_TAG:
10912 flow_dv_translate_item_tag(dev, match_mask,
10913 match_value, items);
10914 last_item = MLX5_FLOW_ITEM_TAG;
10916 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10917 flow_dv_translate_mlx5_item_tag(dev, match_mask,
10918 match_value, items);
10919 last_item = MLX5_FLOW_ITEM_TAG;
10921 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10922 flow_dv_translate_item_tx_queue(dev, match_mask,
10925 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10927 case RTE_FLOW_ITEM_TYPE_GTP:
10928 flow_dv_translate_item_gtp(match_mask, match_value,
10930 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10931 last_item = MLX5_FLOW_LAYER_GTP;
10933 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10934 ret = flow_dv_translate_item_gtp_psc(match_mask,
10938 return rte_flow_error_set(error, -ret,
10939 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10940 "cannot create GTP PSC item");
10941 last_item = MLX5_FLOW_LAYER_GTP_PSC;
10943 case RTE_FLOW_ITEM_TYPE_ECPRI:
10944 if (!mlx5_flex_parser_ecpri_exist(dev)) {
10945 /* Create it only the first time to be used. */
10946 ret = mlx5_flex_parser_ecpri_alloc(dev);
10948 return rte_flow_error_set
10950 RTE_FLOW_ERROR_TYPE_ITEM,
10952 "cannot create eCPRI parser");
10954 /* Adjust the length matcher and device flow value. */
10955 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10956 dev_flow->dv.value.size =
10957 MLX5_ST_SZ_BYTES(fte_match_param);
10958 flow_dv_translate_item_ecpri(dev, match_mask,
10959 match_value, items);
10960 /* No other protocol should follow eCPRI layer. */
10961 last_item = MLX5_FLOW_LAYER_ECPRI;
10966 item_flags |= last_item;
10969 * When E-Switch mode is enabled, we have two cases where we need to
10970 * set the source port manually.
10971 * The first one, is in case of Nic steering rule, and the second is
10972 * E-Switch rule where no port_id item was found. In both cases
10973 * the source port is set according the current port in use.
10975 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10976 (priv->representor || priv->master)) {
10977 if (flow_dv_translate_item_port_id(dev, match_mask,
10978 match_value, NULL, attr))
10981 #ifdef RTE_LIBRTE_MLX5_DEBUG
10982 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10983 dev_flow->dv.value.buf));
10986 * Layers may be already initialized from prefix flow if this dev_flow
10987 * is the suffix flow.
10989 handle->layers |= item_flags;
10990 if (action_flags & MLX5_FLOW_ACTION_RSS)
10991 flow_dv_hashfields_set(dev_flow, rss_desc);
10992 /* If has RSS action in the sample action, the Sample/Mirror resource
10993 * should be registered after the hash filed be update.
10995 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10996 ret = flow_dv_translate_action_sample(dev,
11005 ret = flow_dv_create_action_sample(dev,
11014 return rte_flow_error_set
11016 RTE_FLOW_ERROR_TYPE_ACTION,
11018 "cannot create sample action");
11019 if (num_of_dest > 1) {
11020 dev_flow->dv.actions[sample_act_pos] =
11021 dev_flow->dv.dest_array_res->action;
11023 dev_flow->dv.actions[sample_act_pos] =
11024 dev_flow->dv.sample_res->verbs_action;
11028 * For multiple destination (sample action with ratio=1), the encap
11029 * action and port id action will be combined into group action.
11030 * So need remove the original these actions in the flow and only
11031 * use the sample action instead of.
11033 if (num_of_dest > 1 &&
11034 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11036 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11038 for (i = 0; i < actions_n; i++) {
11039 if ((sample_act->dr_encap_action &&
11040 sample_act->dr_encap_action ==
11041 dev_flow->dv.actions[i]) ||
11042 (sample_act->dr_port_id_action &&
11043 sample_act->dr_port_id_action ==
11044 dev_flow->dv.actions[i]) ||
11045 (sample_act->dr_jump_action &&
11046 sample_act->dr_jump_action ==
11047 dev_flow->dv.actions[i]))
11049 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11051 memcpy((void *)dev_flow->dv.actions,
11052 (void *)temp_actions,
11053 tmp_actions_n * sizeof(void *));
11054 actions_n = tmp_actions_n;
11056 dev_flow->dv.actions_n = actions_n;
11057 dev_flow->act_flags = action_flags;
11058 /* Register matcher. */
11059 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11060 matcher.mask.size);
11061 matcher.priority = mlx5_get_matcher_priority(dev, attr,
11063 /* reserved field no needs to be set to 0 here. */
11064 tbl_key.domain = attr->transfer;
11065 tbl_key.direction = attr->egress;
11066 tbl_key.table_id = dev_flow->dv.group;
11067 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11068 tunnel, attr->group, error))
11074 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11077 * @param[in, out] action
11078 * Shred RSS action holding hash RX queue objects.
11079 * @param[in] hash_fields
11080 * Defines combination of packet fields to participate in RX hash.
11081 * @param[in] tunnel
11083 * @param[in] hrxq_idx
11084 * Hash RX queue index to set.
11087 * 0 on success, otherwise negative errno value.
11090 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11091 const uint64_t hash_fields,
11095 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11097 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11098 case MLX5_RSS_HASH_IPV4:
11099 hrxqs[0] = hrxq_idx;
11101 case MLX5_RSS_HASH_IPV4_TCP:
11102 hrxqs[1] = hrxq_idx;
11104 case MLX5_RSS_HASH_IPV4_UDP:
11105 hrxqs[2] = hrxq_idx;
11107 case MLX5_RSS_HASH_IPV6:
11108 hrxqs[3] = hrxq_idx;
11110 case MLX5_RSS_HASH_IPV6_TCP:
11111 hrxqs[4] = hrxq_idx;
11113 case MLX5_RSS_HASH_IPV6_UDP:
11114 hrxqs[5] = hrxq_idx;
11116 case MLX5_RSS_HASH_NONE:
11117 hrxqs[6] = hrxq_idx;
11125 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11129 * Pointer to the Ethernet device structure.
11131 * Shared RSS action ID holding hash RX queue objects.
11132 * @param[in] hash_fields
11133 * Defines combination of packet fields to participate in RX hash.
11134 * @param[in] tunnel
11138 * Valid hash RX queue index, otherwise 0.
11141 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11142 const uint64_t hash_fields,
11145 struct mlx5_priv *priv = dev->data->dev_private;
11146 struct mlx5_shared_action_rss *shared_rss =
11147 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11148 const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11149 shared_rss->hrxq_tunnel;
11151 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11152 case MLX5_RSS_HASH_IPV4:
11154 case MLX5_RSS_HASH_IPV4_TCP:
11156 case MLX5_RSS_HASH_IPV4_UDP:
11158 case MLX5_RSS_HASH_IPV6:
11160 case MLX5_RSS_HASH_IPV6_TCP:
11162 case MLX5_RSS_HASH_IPV6_UDP:
11164 case MLX5_RSS_HASH_NONE:
11172 * Apply the flow to the NIC, lock free,
11173 * (mutex should be acquired by caller).
11176 * Pointer to the Ethernet device structure.
11177 * @param[in, out] flow
11178 * Pointer to flow structure.
11179 * @param[out] error
11180 * Pointer to error structure.
11183 * 0 on success, a negative errno value otherwise and rte_errno is set.
11186 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11187 struct rte_flow_error *error)
11189 struct mlx5_flow_dv_workspace *dv;
11190 struct mlx5_flow_handle *dh;
11191 struct mlx5_flow_handle_dv *dv_h;
11192 struct mlx5_flow *dev_flow;
11193 struct mlx5_priv *priv = dev->data->dev_private;
11194 uint32_t handle_idx;
11198 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11199 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11202 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11203 dev_flow = &wks->flows[idx];
11204 dv = &dev_flow->dv;
11205 dh = dev_flow->handle;
11208 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11209 if (dv->transfer) {
11210 dv->actions[n++] = priv->sh->esw_drop_action;
11212 MLX5_ASSERT(priv->drop_queue.hrxq);
11214 priv->drop_queue.hrxq->action;
11216 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11217 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11218 struct mlx5_hrxq *hrxq;
11221 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11226 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11227 "cannot get hash queue");
11230 dh->rix_hrxq = hrxq_idx;
11231 dv->actions[n++] = hrxq->action;
11232 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11233 struct mlx5_hrxq *hrxq = NULL;
11236 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11237 rss_desc->shared_rss,
11238 dev_flow->hash_fields,
11240 MLX5_FLOW_LAYER_TUNNEL));
11242 hrxq = mlx5_ipool_get
11243 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11248 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11249 "cannot get hash queue");
11252 dh->rix_srss = rss_desc->shared_rss;
11253 dv->actions[n++] = hrxq->action;
11254 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11255 if (!priv->sh->default_miss_action) {
11258 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11259 "default miss action not be created.");
11262 dv->actions[n++] = priv->sh->default_miss_action;
11264 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11265 (void *)&dv->value, n,
11266 dv->actions, &dh->drv_flow);
11268 rte_flow_error_set(error, errno,
11269 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11271 "hardware refuses to create flow");
11274 if (priv->vmwa_context &&
11275 dh->vf_vlan.tag && !dh->vf_vlan.created) {
11277 * The rule contains the VLAN pattern.
11278 * For VF we are going to create VLAN
11279 * interface to make hypervisor set correct
11280 * e-Switch vport context.
11282 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11287 err = rte_errno; /* Save rte_errno before cleanup. */
11288 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11289 handle_idx, dh, next) {
11290 /* hrxq is union, don't clear it if the flag is not set. */
11291 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11292 mlx5_hrxq_release(dev, dh->rix_hrxq);
11294 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11297 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11298 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11300 rte_errno = err; /* Restore rte_errno. */
11305 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11306 struct mlx5_cache_entry *entry)
11308 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11311 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11316 * Release the flow matcher.
11319 * Pointer to Ethernet device.
11321 * Index to port ID action resource.
11324 * 1 while a reference on it exists, 0 when freed.
11327 flow_dv_matcher_release(struct rte_eth_dev *dev,
11328 struct mlx5_flow_handle *handle)
11330 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11331 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11332 typeof(*tbl), tbl);
11335 MLX5_ASSERT(matcher->matcher_object);
11336 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11337 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11342 * Release encap_decap resource.
11345 * Pointer to the hash list.
11347 * Pointer to exist resource entry object.
11350 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11351 struct mlx5_hlist_entry *entry)
11353 struct mlx5_dev_ctx_shared *sh = list->ctx;
11354 struct mlx5_flow_dv_encap_decap_resource *res =
11355 container_of(entry, typeof(*res), entry);
11357 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11358 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11362 * Release an encap/decap resource.
11365 * Pointer to Ethernet device.
11366 * @param encap_decap_idx
11367 * Index of encap decap resource.
11370 * 1 while a reference on it exists, 0 when freed.
11373 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11374 uint32_t encap_decap_idx)
11376 struct mlx5_priv *priv = dev->data->dev_private;
11377 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11379 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11381 if (!cache_resource)
11383 MLX5_ASSERT(cache_resource->action);
11384 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11385 &cache_resource->entry);
11389 * Release an jump to table action resource.
11392 * Pointer to Ethernet device.
11394 * Index to the jump action resource.
11397 * 1 while a reference on it exists, 0 when freed.
11400 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11403 struct mlx5_priv *priv = dev->data->dev_private;
11404 struct mlx5_flow_tbl_data_entry *tbl_data;
11406 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11410 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11414 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11415 struct mlx5_hlist_entry *entry)
11417 struct mlx5_flow_dv_modify_hdr_resource *res =
11418 container_of(entry, typeof(*res), entry);
11420 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11425 * Release a modify-header resource.
11428 * Pointer to Ethernet device.
11430 * Pointer to mlx5_flow_handle.
11433 * 1 while a reference on it exists, 0 when freed.
11436 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11437 struct mlx5_flow_handle *handle)
11439 struct mlx5_priv *priv = dev->data->dev_private;
11440 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11442 MLX5_ASSERT(entry->action);
11443 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11447 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11448 struct mlx5_cache_entry *entry)
11450 struct mlx5_dev_ctx_shared *sh = list->ctx;
11451 struct mlx5_flow_dv_port_id_action_resource *cache =
11452 container_of(entry, typeof(*cache), entry);
11454 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11455 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11459 * Release port ID action resource.
11462 * Pointer to Ethernet device.
11464 * Pointer to mlx5_flow_handle.
11467 * 1 while a reference on it exists, 0 when freed.
11470 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11473 struct mlx5_priv *priv = dev->data->dev_private;
11474 struct mlx5_flow_dv_port_id_action_resource *cache;
11476 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11479 MLX5_ASSERT(cache->action);
11480 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11485 * Release shared RSS action resource.
11488 * Pointer to Ethernet device.
11490 * Shared RSS action index.
11493 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11495 struct mlx5_priv *priv = dev->data->dev_private;
11496 struct mlx5_shared_action_rss *shared_rss;
11498 shared_rss = mlx5_ipool_get
11499 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11500 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11504 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11505 struct mlx5_cache_entry *entry)
11507 struct mlx5_dev_ctx_shared *sh = list->ctx;
11508 struct mlx5_flow_dv_push_vlan_action_resource *cache =
11509 container_of(entry, typeof(*cache), entry);
11511 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11512 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11516 * Release push vlan action resource.
11519 * Pointer to Ethernet device.
11521 * Pointer to mlx5_flow_handle.
11524 * 1 while a reference on it exists, 0 when freed.
11527 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11528 struct mlx5_flow_handle *handle)
11530 struct mlx5_priv *priv = dev->data->dev_private;
11531 struct mlx5_flow_dv_push_vlan_action_resource *cache;
11532 uint32_t idx = handle->dvh.rix_push_vlan;
11534 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11537 MLX5_ASSERT(cache->action);
11538 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11543 * Release the fate resource.
11546 * Pointer to Ethernet device.
11548 * Pointer to mlx5_flow_handle.
11551 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11552 struct mlx5_flow_handle *handle)
11554 if (!handle->rix_fate)
11556 switch (handle->fate_action) {
11557 case MLX5_FLOW_FATE_QUEUE:
11558 mlx5_hrxq_release(dev, handle->rix_hrxq);
11560 case MLX5_FLOW_FATE_JUMP:
11561 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
11563 case MLX5_FLOW_FATE_PORT_ID:
11564 flow_dv_port_id_action_resource_release(dev,
11565 handle->rix_port_id_action);
11568 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11571 handle->rix_fate = 0;
11575 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11576 struct mlx5_cache_entry *entry)
11578 struct mlx5_flow_dv_sample_resource *cache_resource =
11579 container_of(entry, typeof(*cache_resource), entry);
11580 struct rte_eth_dev *dev = cache_resource->dev;
11581 struct mlx5_priv *priv = dev->data->dev_private;
11583 if (cache_resource->verbs_action)
11584 claim_zero(mlx5_flow_os_destroy_flow_action
11585 (cache_resource->verbs_action));
11586 if (cache_resource->normal_path_tbl)
11587 flow_dv_tbl_resource_release(MLX5_SH(dev),
11588 cache_resource->normal_path_tbl);
11589 flow_dv_sample_sub_actions_release(dev,
11590 &cache_resource->sample_idx);
11591 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11592 cache_resource->idx);
11593 DRV_LOG(DEBUG, "sample resource %p: removed",
11594 (void *)cache_resource);
11598 * Release an sample resource.
11601 * Pointer to Ethernet device.
11603 * Pointer to mlx5_flow_handle.
11606 * 1 while a reference on it exists, 0 when freed.
11609 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11610 struct mlx5_flow_handle *handle)
11612 struct mlx5_priv *priv = dev->data->dev_private;
11613 struct mlx5_flow_dv_sample_resource *cache_resource;
11615 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11616 handle->dvh.rix_sample);
11617 if (!cache_resource)
11619 MLX5_ASSERT(cache_resource->verbs_action);
11620 return mlx5_cache_unregister(&priv->sh->sample_action_list,
11621 &cache_resource->entry);
11625 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11626 struct mlx5_cache_entry *entry)
11628 struct mlx5_flow_dv_dest_array_resource *cache_resource =
11629 container_of(entry, typeof(*cache_resource), entry);
11630 struct rte_eth_dev *dev = cache_resource->dev;
11631 struct mlx5_priv *priv = dev->data->dev_private;
11634 MLX5_ASSERT(cache_resource->action);
11635 if (cache_resource->action)
11636 claim_zero(mlx5_flow_os_destroy_flow_action
11637 (cache_resource->action));
11638 for (; i < cache_resource->num_of_dest; i++)
11639 flow_dv_sample_sub_actions_release(dev,
11640 &cache_resource->sample_idx[i]);
11641 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11642 cache_resource->idx);
11643 DRV_LOG(DEBUG, "destination array resource %p: removed",
11644 (void *)cache_resource);
11648 * Release an destination array resource.
11651 * Pointer to Ethernet device.
11653 * Pointer to mlx5_flow_handle.
11656 * 1 while a reference on it exists, 0 when freed.
11659 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11660 struct mlx5_flow_handle *handle)
11662 struct mlx5_priv *priv = dev->data->dev_private;
11663 struct mlx5_flow_dv_dest_array_resource *cache;
11665 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11666 handle->dvh.rix_dest_array);
11669 MLX5_ASSERT(cache->action);
11670 return mlx5_cache_unregister(&priv->sh->dest_array_list,
11675 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11677 struct mlx5_priv *priv = dev->data->dev_private;
11678 struct mlx5_dev_ctx_shared *sh = priv->sh;
11679 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11680 sh->geneve_tlv_option_resource;
11681 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11682 if (geneve_opt_resource) {
11683 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11684 __ATOMIC_RELAXED))) {
11685 claim_zero(mlx5_devx_cmd_destroy
11686 (geneve_opt_resource->obj));
11687 mlx5_free(sh->geneve_tlv_option_resource);
11688 sh->geneve_tlv_option_resource = NULL;
11691 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11695 * Remove the flow from the NIC but keeps it in memory.
11696 * Lock free, (mutex should be acquired by caller).
11699 * Pointer to Ethernet device.
11700 * @param[in, out] flow
11701 * Pointer to flow structure.
11704 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11706 struct mlx5_flow_handle *dh;
11707 uint32_t handle_idx;
11708 struct mlx5_priv *priv = dev->data->dev_private;
11712 handle_idx = flow->dev_handles;
11713 while (handle_idx) {
11714 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11718 if (dh->drv_flow) {
11719 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11720 dh->drv_flow = NULL;
11722 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11723 flow_dv_fate_resource_release(dev, dh);
11724 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11725 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11726 handle_idx = dh->next.next;
11731 * Remove the flow from the NIC and the memory.
11732 * Lock free, (mutex should be acquired by caller).
11735 * Pointer to the Ethernet device structure.
11736 * @param[in, out] flow
11737 * Pointer to flow structure.
11740 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11742 struct mlx5_flow_handle *dev_handle;
11743 struct mlx5_priv *priv = dev->data->dev_private;
11748 flow_dv_remove(dev, flow);
11749 if (flow->counter) {
11750 flow_dv_counter_free(dev, flow->counter);
11754 struct mlx5_flow_meter *fm;
11756 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11759 mlx5_flow_meter_detach(fm);
11763 flow_dv_aso_age_release(dev, flow->age);
11764 if (flow->geneve_tlv_option) {
11765 flow_dv_geneve_tlv_option_resource_release(dev);
11766 flow->geneve_tlv_option = 0;
11768 while (flow->dev_handles) {
11769 uint32_t tmp_idx = flow->dev_handles;
11771 dev_handle = mlx5_ipool_get(priv->sh->ipool
11772 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11775 flow->dev_handles = dev_handle->next.next;
11776 if (dev_handle->dvh.matcher)
11777 flow_dv_matcher_release(dev, dev_handle);
11778 if (dev_handle->dvh.rix_sample)
11779 flow_dv_sample_resource_release(dev, dev_handle);
11780 if (dev_handle->dvh.rix_dest_array)
11781 flow_dv_dest_array_resource_release(dev, dev_handle);
11782 if (dev_handle->dvh.rix_encap_decap)
11783 flow_dv_encap_decap_resource_release(dev,
11784 dev_handle->dvh.rix_encap_decap);
11785 if (dev_handle->dvh.modify_hdr)
11786 flow_dv_modify_hdr_resource_release(dev, dev_handle);
11787 if (dev_handle->dvh.rix_push_vlan)
11788 flow_dv_push_vlan_action_resource_release(dev,
11790 if (dev_handle->dvh.rix_tag)
11791 flow_dv_tag_release(dev,
11792 dev_handle->dvh.rix_tag);
11793 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11794 flow_dv_fate_resource_release(dev, dev_handle);
11796 srss = dev_handle->rix_srss;
11797 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11801 flow_dv_shared_rss_action_release(dev, srss);
11805 * Release array of hash RX queue objects.
11809 * Pointer to the Ethernet device structure.
11810 * @param[in, out] hrxqs
11811 * Array of hash RX queue objects.
11814 * Total number of references to hash RX queue objects in *hrxqs* array
11815 * after this operation.
11818 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11819 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11824 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11825 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11835 * Release all hash RX queue objects representing shared RSS action.
11838 * Pointer to the Ethernet device structure.
11839 * @param[in, out] action
11840 * Shared RSS action to remove hash RX queue objects from.
11843 * Total number of references to hash RX queue objects stored in *action*
11844 * after this operation.
11845 * Expected to be 0 if no external references held.
11848 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11849 struct mlx5_shared_action_rss *action)
11851 return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11852 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11856 * Setup shared RSS action.
11857 * Prepare set of hash RX queue objects sufficient to handle all valid
11858 * hash_fields combinations (see enum ibv_rx_hash_fields).
11861 * Pointer to the Ethernet device structure.
11862 * @param[in] action_idx
11863 * Shared RSS action ipool index.
11864 * @param[in, out] action
11865 * Partially initialized shared RSS action.
11866 * @param[out] error
11867 * Perform verbose error reporting if not NULL. Initialized in case of
11871 * 0 on success, otherwise negative errno value.
11874 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11875 uint32_t action_idx,
11876 struct mlx5_shared_action_rss *action,
11877 struct rte_flow_error *error)
11879 struct mlx5_flow_rss_desc rss_desc = { 0 };
11883 if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11884 return rte_flow_error_set(error, rte_errno,
11885 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11886 "cannot setup indirection table");
11888 memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11889 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11890 rss_desc.const_q = action->origin.queue;
11891 rss_desc.queue_num = action->origin.queue_num;
11892 /* Set non-zero value to indicate a shared RSS. */
11893 rss_desc.shared_rss = action_idx;
11894 rss_desc.ind_tbl = action->ind_tbl;
11895 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11897 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11900 for (tunnel = 0; tunnel < 2; tunnel++) {
11901 rss_desc.tunnel = tunnel;
11902 rss_desc.hash_fields = hash_fields;
11903 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11908 "cannot get hash queue");
11909 goto error_hrxq_new;
11911 err = __flow_dv_action_rss_hrxq_set
11912 (action, hash_fields, tunnel, hrxq_idx);
11919 __flow_dv_action_rss_hrxqs_release(dev, action);
11920 if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11921 action->ind_tbl = NULL;
11927 * Create shared RSS action.
11930 * Pointer to the Ethernet device structure.
11932 * Shared action configuration.
11934 * RSS action specification used to create shared action.
11935 * @param[out] error
11936 * Perform verbose error reporting if not NULL. Initialized in case of
11940 * A valid shared action ID in case of success, 0 otherwise and
11941 * rte_errno is set.
11944 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11945 const struct rte_flow_shared_action_conf *conf,
11946 const struct rte_flow_action_rss *rss,
11947 struct rte_flow_error *error)
11949 struct mlx5_priv *priv = dev->data->dev_private;
11950 struct mlx5_shared_action_rss *shared_action = NULL;
11951 void *queue = NULL;
11952 struct rte_flow_action_rss *origin;
11953 const uint8_t *rss_key;
11954 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11957 RTE_SET_USED(conf);
11958 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11960 shared_action = mlx5_ipool_zmalloc
11961 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11962 if (!shared_action || !queue) {
11963 rte_flow_error_set(error, ENOMEM,
11964 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11965 "cannot allocate resource memory");
11966 goto error_rss_init;
11968 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11969 rte_flow_error_set(error, E2BIG,
11970 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11971 "rss action number out of range");
11972 goto error_rss_init;
11974 shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11975 sizeof(*shared_action->ind_tbl),
11977 if (!shared_action->ind_tbl) {
11978 rte_flow_error_set(error, ENOMEM,
11979 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11980 "cannot allocate resource memory");
11981 goto error_rss_init;
11983 memcpy(queue, rss->queue, queue_size);
11984 shared_action->ind_tbl->queues = queue;
11985 shared_action->ind_tbl->queues_n = rss->queue_num;
11986 origin = &shared_action->origin;
11987 origin->func = rss->func;
11988 origin->level = rss->level;
11989 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11990 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11991 /* NULL RSS key indicates default RSS key. */
11992 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11993 memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11994 origin->key = &shared_action->key[0];
11995 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11996 origin->queue = queue;
11997 origin->queue_num = rss->queue_num;
11998 if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11999 goto error_rss_init;
12000 rte_spinlock_init(&shared_action->action_rss_sl);
12001 __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
12002 rte_spinlock_lock(&priv->shared_act_sl);
12003 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12004 &priv->rss_shared_actions, idx, shared_action, next);
12005 rte_spinlock_unlock(&priv->shared_act_sl);
12008 if (shared_action) {
12009 if (shared_action->ind_tbl)
12010 mlx5_free(shared_action->ind_tbl);
12011 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12020 * Destroy the shared RSS action.
12021 * Release related hash RX queue objects.
12024 * Pointer to the Ethernet device structure.
12026 * The shared RSS action object ID to be removed.
12027 * @param[out] error
12028 * Perform verbose error reporting if not NULL. Initialized in case of
12032 * 0 on success, otherwise negative errno value.
12035 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12036 struct rte_flow_error *error)
12038 struct mlx5_priv *priv = dev->data->dev_private;
12039 struct mlx5_shared_action_rss *shared_rss =
12040 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12041 uint32_t old_refcnt = 1;
12043 uint16_t *queue = NULL;
12046 return rte_flow_error_set(error, EINVAL,
12047 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12048 "invalid shared action");
12049 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12051 return rte_flow_error_set(error, EBUSY,
12052 RTE_FLOW_ERROR_TYPE_ACTION,
12054 "shared rss hrxq has references");
12055 queue = shared_rss->ind_tbl->queues;
12056 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12058 return rte_flow_error_set(error, EBUSY,
12059 RTE_FLOW_ERROR_TYPE_ACTION,
12061 "shared rss indirection table has"
12063 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12064 0, 0, __ATOMIC_ACQUIRE,
12066 return rte_flow_error_set(error, EBUSY,
12067 RTE_FLOW_ERROR_TYPE_ACTION,
12069 "shared rss has references");
12071 rte_spinlock_lock(&priv->shared_act_sl);
12072 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12073 &priv->rss_shared_actions, idx, shared_rss, next);
12074 rte_spinlock_unlock(&priv->shared_act_sl);
12075 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12081 * Create shared action, lock free,
12082 * (mutex should be acquired by caller).
12083 * Dispatcher for action type specific call.
12086 * Pointer to the Ethernet device structure.
12088 * Shared action configuration.
12089 * @param[in] action
12090 * Action specification used to create shared action.
12091 * @param[out] error
12092 * Perform verbose error reporting if not NULL. Initialized in case of
12096 * A valid shared action handle in case of success, NULL otherwise and
12097 * rte_errno is set.
12099 static struct rte_flow_shared_action *
12100 flow_dv_action_create(struct rte_eth_dev *dev,
12101 const struct rte_flow_shared_action_conf *conf,
12102 const struct rte_flow_action *action,
12103 struct rte_flow_error *err)
12108 switch (action->type) {
12109 case RTE_FLOW_ACTION_TYPE_RSS:
12110 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12111 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12112 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12114 case RTE_FLOW_ACTION_TYPE_AGE:
12115 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12116 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12117 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12119 struct mlx5_aso_age_action *aso_age =
12120 flow_aso_age_get_by_idx(dev, ret);
12122 if (!aso_age->age_params.context)
12123 aso_age->age_params.context =
12124 (void *)(uintptr_t)idx;
12128 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12129 NULL, "action type not supported");
12132 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12136 * Destroy the shared action.
12137 * Release action related resources on the NIC and the memory.
12138 * Lock free, (mutex should be acquired by caller).
12139 * Dispatcher for action type specific call.
12142 * Pointer to the Ethernet device structure.
12143 * @param[in] action
12144 * The shared action object to be removed.
12145 * @param[out] error
12146 * Perform verbose error reporting if not NULL. Initialized in case of
12150 * 0 on success, otherwise negative errno value.
12153 flow_dv_action_destroy(struct rte_eth_dev *dev,
12154 struct rte_flow_shared_action *action,
12155 struct rte_flow_error *error)
12157 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12158 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12159 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12163 case MLX5_SHARED_ACTION_TYPE_RSS:
12164 return __flow_dv_action_rss_release(dev, idx, error);
12165 case MLX5_SHARED_ACTION_TYPE_AGE:
12166 ret = flow_dv_aso_age_release(dev, idx);
12169 * In this case, the last flow has a reference will
12170 * actually release the age action.
12172 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12173 " released with references %d.", idx, ret);
12176 return rte_flow_error_set(error, ENOTSUP,
12177 RTE_FLOW_ERROR_TYPE_ACTION,
12179 "action type not supported");
12184 * Updates in place shared RSS action configuration.
12187 * Pointer to the Ethernet device structure.
12189 * The shared RSS action object ID to be updated.
12190 * @param[in] action_conf
12191 * RSS action specification used to modify *shared_rss*.
12192 * @param[out] error
12193 * Perform verbose error reporting if not NULL. Initialized in case of
12197 * 0 on success, otherwise negative errno value.
12198 * @note: currently only support update of RSS queues.
12201 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12202 const struct rte_flow_action_rss *action_conf,
12203 struct rte_flow_error *error)
12205 struct mlx5_priv *priv = dev->data->dev_private;
12206 struct mlx5_shared_action_rss *shared_rss =
12207 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12209 void *queue = NULL;
12210 uint16_t *queue_old = NULL;
12211 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12214 return rte_flow_error_set(error, EINVAL,
12215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12216 "invalid shared action to update");
12217 queue = mlx5_malloc(MLX5_MEM_ZERO,
12218 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12221 return rte_flow_error_set(error, ENOMEM,
12222 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12224 "cannot allocate resource memory");
12225 memcpy(queue, action_conf->queue, queue_size);
12226 MLX5_ASSERT(shared_rss->ind_tbl);
12227 rte_spinlock_lock(&shared_rss->action_rss_sl);
12228 queue_old = shared_rss->ind_tbl->queues;
12229 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12230 queue, action_conf->queue_num, true);
12233 ret = rte_flow_error_set(error, rte_errno,
12234 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12235 "cannot update indirection table");
12237 mlx5_free(queue_old);
12238 shared_rss->origin.queue = queue;
12239 shared_rss->origin.queue_num = action_conf->queue_num;
12241 rte_spinlock_unlock(&shared_rss->action_rss_sl);
12246 * Updates in place shared action configuration, lock free,
12247 * (mutex should be acquired by caller).
12250 * Pointer to the Ethernet device structure.
12251 * @param[in] action
12252 * The shared action object to be updated.
12253 * @param[in] action_conf
12254 * Action specification used to modify *action*.
12255 * *action_conf* should be of type correlating with type of the *action*,
12256 * otherwise considered as invalid.
12257 * @param[out] error
12258 * Perform verbose error reporting if not NULL. Initialized in case of
12262 * 0 on success, otherwise negative errno value.
12265 flow_dv_action_update(struct rte_eth_dev *dev,
12266 struct rte_flow_shared_action *action,
12267 const void *action_conf,
12268 struct rte_flow_error *err)
12270 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12271 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12272 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12275 case MLX5_SHARED_ACTION_TYPE_RSS:
12276 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12278 return rte_flow_error_set(err, ENOTSUP,
12279 RTE_FLOW_ERROR_TYPE_ACTION,
12281 "action type update not supported");
12286 flow_dv_action_query(struct rte_eth_dev *dev,
12287 const struct rte_flow_shared_action *action, void *data,
12288 struct rte_flow_error *error)
12290 struct mlx5_age_param *age_param;
12291 struct rte_flow_query_age *resp;
12292 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12293 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12294 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12297 case MLX5_SHARED_ACTION_TYPE_AGE:
12298 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12300 resp->aged = __atomic_load_n(&age_param->state,
12301 __ATOMIC_RELAXED) == AGE_TMOUT ?
12303 resp->sec_since_last_hit_valid = !resp->aged;
12304 if (resp->sec_since_last_hit_valid)
12305 resp->sec_since_last_hit = __atomic_load_n
12306 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12309 return rte_flow_error_set(error, ENOTSUP,
12310 RTE_FLOW_ERROR_TYPE_ACTION,
12312 "action type query not supported");
12317 * Query a dv flow rule for its statistics via devx.
12320 * Pointer to Ethernet device.
12322 * Pointer to the sub flow.
12324 * data retrieved by the query.
12325 * @param[out] error
12326 * Perform verbose error reporting if not NULL.
12329 * 0 on success, a negative errno value otherwise and rte_errno is set.
12332 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12333 void *data, struct rte_flow_error *error)
12335 struct mlx5_priv *priv = dev->data->dev_private;
12336 struct rte_flow_query_count *qc = data;
12338 if (!priv->config.devx)
12339 return rte_flow_error_set(error, ENOTSUP,
12340 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12342 "counters are not supported");
12343 if (flow->counter) {
12344 uint64_t pkts, bytes;
12345 struct mlx5_flow_counter *cnt;
12347 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12349 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12353 return rte_flow_error_set(error, -err,
12354 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12355 NULL, "cannot read counters");
12358 qc->hits = pkts - cnt->hits;
12359 qc->bytes = bytes - cnt->bytes;
12362 cnt->bytes = bytes;
12366 return rte_flow_error_set(error, EINVAL,
12367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12369 "counters are not available");
12373 * Query a flow rule AGE action for aging information.
12376 * Pointer to Ethernet device.
12378 * Pointer to the sub flow.
12380 * data retrieved by the query.
12381 * @param[out] error
12382 * Perform verbose error reporting if not NULL.
12385 * 0 on success, a negative errno value otherwise and rte_errno is set.
12388 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12389 void *data, struct rte_flow_error *error)
12391 struct rte_flow_query_age *resp = data;
12392 struct mlx5_age_param *age_param;
12395 struct mlx5_aso_age_action *act =
12396 flow_aso_age_get_by_idx(dev, flow->age);
12398 age_param = &act->age_params;
12399 } else if (flow->counter) {
12400 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12402 if (!age_param || !age_param->timeout)
12403 return rte_flow_error_set
12405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12406 NULL, "cannot read age data");
12408 return rte_flow_error_set(error, EINVAL,
12409 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12410 NULL, "age data not available");
12412 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12414 resp->sec_since_last_hit_valid = !resp->aged;
12415 if (resp->sec_since_last_hit_valid)
12416 resp->sec_since_last_hit = __atomic_load_n
12417 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12424 * @see rte_flow_query()
12425 * @see rte_flow_ops
12428 flow_dv_query(struct rte_eth_dev *dev,
12429 struct rte_flow *flow __rte_unused,
12430 const struct rte_flow_action *actions __rte_unused,
12431 void *data __rte_unused,
12432 struct rte_flow_error *error __rte_unused)
12436 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12437 switch (actions->type) {
12438 case RTE_FLOW_ACTION_TYPE_VOID:
12440 case RTE_FLOW_ACTION_TYPE_COUNT:
12441 ret = flow_dv_query_count(dev, flow, data, error);
12443 case RTE_FLOW_ACTION_TYPE_AGE:
12444 ret = flow_dv_query_age(dev, flow, data, error);
12447 return rte_flow_error_set(error, ENOTSUP,
12448 RTE_FLOW_ERROR_TYPE_ACTION,
12450 "action not supported");
12457 * Destroy the meter table set.
12458 * Lock free, (mutex should be acquired by caller).
12461 * Pointer to Ethernet device.
12463 * Pointer to the meter table set.
12469 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12470 struct mlx5_meter_domains_infos *tbl)
12472 struct mlx5_priv *priv = dev->data->dev_private;
12473 struct mlx5_meter_domains_infos *mtd =
12474 (struct mlx5_meter_domains_infos *)tbl;
12476 if (!mtd || !priv->config.dv_flow_en)
12478 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12479 claim_zero(mlx5_flow_os_destroy_flow
12480 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12481 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12482 claim_zero(mlx5_flow_os_destroy_flow
12483 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12484 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12485 claim_zero(mlx5_flow_os_destroy_flow
12486 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12487 if (mtd->egress.color_matcher)
12488 claim_zero(mlx5_flow_os_destroy_flow_matcher
12489 (mtd->egress.color_matcher));
12490 if (mtd->egress.any_matcher)
12491 claim_zero(mlx5_flow_os_destroy_flow_matcher
12492 (mtd->egress.any_matcher));
12493 if (mtd->egress.tbl)
12494 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12495 if (mtd->egress.sfx_tbl)
12496 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12497 if (mtd->ingress.color_matcher)
12498 claim_zero(mlx5_flow_os_destroy_flow_matcher
12499 (mtd->ingress.color_matcher));
12500 if (mtd->ingress.any_matcher)
12501 claim_zero(mlx5_flow_os_destroy_flow_matcher
12502 (mtd->ingress.any_matcher));
12503 if (mtd->ingress.tbl)
12504 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12505 if (mtd->ingress.sfx_tbl)
12506 flow_dv_tbl_resource_release(MLX5_SH(dev),
12507 mtd->ingress.sfx_tbl);
12508 if (mtd->transfer.color_matcher)
12509 claim_zero(mlx5_flow_os_destroy_flow_matcher
12510 (mtd->transfer.color_matcher));
12511 if (mtd->transfer.any_matcher)
12512 claim_zero(mlx5_flow_os_destroy_flow_matcher
12513 (mtd->transfer.any_matcher));
12514 if (mtd->transfer.tbl)
12515 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12516 if (mtd->transfer.sfx_tbl)
12517 flow_dv_tbl_resource_release(MLX5_SH(dev),
12518 mtd->transfer.sfx_tbl);
12519 if (mtd->drop_actn)
12520 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12525 /* Number of meter flow actions, count and jump or count and drop. */
12526 #define METER_ACTIONS 2
12529 * Create specify domain meter table and suffix table.
12532 * Pointer to Ethernet device.
12533 * @param[in,out] mtb
12534 * Pointer to DV meter table set.
12535 * @param[in] egress
12537 * @param[in] transfer
12539 * @param[in] color_reg_c_idx
12540 * Reg C index for color match.
12543 * 0 on success, -1 otherwise and rte_errno is set.
12546 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12547 struct mlx5_meter_domains_infos *mtb,
12548 uint8_t egress, uint8_t transfer,
12549 uint32_t color_reg_c_idx)
12551 struct mlx5_priv *priv = dev->data->dev_private;
12552 struct mlx5_dev_ctx_shared *sh = priv->sh;
12553 struct mlx5_flow_dv_match_params mask = {
12554 .size = sizeof(mask.buf),
12556 struct mlx5_flow_dv_match_params value = {
12557 .size = sizeof(value.buf),
12559 struct mlx5dv_flow_matcher_attr dv_attr = {
12560 .type = IBV_FLOW_ATTR_NORMAL,
12562 .match_criteria_enable = 0,
12563 .match_mask = (void *)&mask,
12565 void *actions[METER_ACTIONS];
12566 struct mlx5_meter_domain_info *dtb;
12567 struct rte_flow_error error;
12572 dtb = &mtb->transfer;
12574 dtb = &mtb->egress;
12576 dtb = &mtb->ingress;
12577 /* Create the meter table with METER level. */
12578 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12579 egress, transfer, false, NULL, 0,
12582 DRV_LOG(ERR, "Failed to create meter policer table.");
12585 /* Create the meter suffix table with SUFFIX level. */
12586 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12587 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12588 egress, transfer, false, NULL, 0,
12590 if (!dtb->sfx_tbl) {
12591 DRV_LOG(ERR, "Failed to create meter suffix table.");
12594 /* Create matchers, Any and Color. */
12595 dv_attr.priority = 3;
12596 dv_attr.match_criteria_enable = 0;
12597 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12598 &dtb->any_matcher);
12600 DRV_LOG(ERR, "Failed to create meter"
12601 " policer default matcher.");
12604 dv_attr.priority = 0;
12605 dv_attr.match_criteria_enable =
12606 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12607 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12608 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12609 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12610 &dtb->color_matcher);
12612 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12615 if (mtb->count_actns[RTE_MTR_DROPPED])
12616 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12617 actions[i++] = mtb->drop_actn;
12618 /* Default rule: lowest priority, match any, actions: drop. */
12619 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12621 &dtb->policer_rules[RTE_MTR_DROPPED]);
12623 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12632 * Create the needed meter and suffix tables.
12633 * Lock free, (mutex should be acquired by caller).
12636 * Pointer to Ethernet device.
12638 * Pointer to the flow meter.
12641 * Pointer to table set on success, NULL otherwise and rte_errno is set.
12643 static struct mlx5_meter_domains_infos *
12644 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12645 const struct mlx5_flow_meter *fm)
12647 struct mlx5_priv *priv = dev->data->dev_private;
12648 struct mlx5_meter_domains_infos *mtb;
12652 if (!priv->mtr_en) {
12653 rte_errno = ENOTSUP;
12656 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12658 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12661 /* Create meter count actions */
12662 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12663 struct mlx5_flow_counter *cnt;
12664 if (!fm->policer_stats.cnt[i])
12666 cnt = flow_dv_counter_get_by_idx(dev,
12667 fm->policer_stats.cnt[i], NULL);
12668 mtb->count_actns[i] = cnt->action;
12670 /* Create drop action. */
12671 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12673 DRV_LOG(ERR, "Failed to create drop action.");
12676 /* Egress meter table. */
12677 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12679 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12682 /* Ingress meter table. */
12683 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12685 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12688 /* FDB meter table. */
12689 if (priv->config.dv_esw_en) {
12690 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12691 priv->mtr_color_reg);
12693 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12699 flow_dv_destroy_mtr_tbl(dev, mtb);
12704 * Destroy domain policer rule.
12707 * Pointer to domain table.
12710 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12714 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12715 if (dt->policer_rules[i]) {
12716 claim_zero(mlx5_flow_os_destroy_flow
12717 (dt->policer_rules[i]));
12718 dt->policer_rules[i] = NULL;
12721 if (dt->jump_actn) {
12722 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12723 dt->jump_actn = NULL;
12728 * Destroy policer rules.
12731 * Pointer to Ethernet device.
12733 * Pointer to flow meter structure.
12735 * Pointer to flow attributes.
12741 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12742 const struct mlx5_flow_meter *fm,
12743 const struct rte_flow_attr *attr)
12745 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12750 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12752 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12753 if (attr->transfer)
12754 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12759 * Create specify domain meter policer rule.
12762 * Pointer to flow meter structure.
12764 * Pointer to DV meter table set.
12765 * @param[in] mtr_reg_c
12766 * Color match REG_C.
12769 * 0 on success, -1 otherwise.
12772 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12773 struct mlx5_meter_domain_info *dtb,
12776 struct mlx5_flow_dv_match_params matcher = {
12777 .size = sizeof(matcher.buf),
12779 struct mlx5_flow_dv_match_params value = {
12780 .size = sizeof(value.buf),
12782 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12783 void *actions[METER_ACTIONS];
12787 /* Create jump action. */
12788 if (!dtb->jump_actn)
12789 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12790 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12792 DRV_LOG(ERR, "Failed to create policer jump action.");
12795 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12798 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12799 rte_col_2_mlx5_col(i), UINT8_MAX);
12800 if (mtb->count_actns[i])
12801 actions[j++] = mtb->count_actns[i];
12802 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12803 actions[j++] = mtb->drop_actn;
12805 actions[j++] = dtb->jump_actn;
12806 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12807 (void *)&value, j, actions,
12808 &dtb->policer_rules[i]);
12810 DRV_LOG(ERR, "Failed to create policer rule.");
12821 * Create policer rules.
12824 * Pointer to Ethernet device.
12826 * Pointer to flow meter structure.
12828 * Pointer to flow attributes.
12831 * 0 on success, -1 otherwise.
12834 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12835 struct mlx5_flow_meter *fm,
12836 const struct rte_flow_attr *attr)
12838 struct mlx5_priv *priv = dev->data->dev_private;
12839 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12842 if (attr->egress) {
12843 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12844 priv->mtr_color_reg);
12846 DRV_LOG(ERR, "Failed to create egress policer.");
12850 if (attr->ingress) {
12851 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12852 priv->mtr_color_reg);
12854 DRV_LOG(ERR, "Failed to create ingress policer.");
12858 if (attr->transfer) {
12859 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12860 priv->mtr_color_reg);
12862 DRV_LOG(ERR, "Failed to create transfer policer.");
12868 flow_dv_destroy_policer_rules(dev, fm, attr);
12873 * Validate the batch counter support in root table.
12875 * Create a simple flow with invalid counter and drop action on root table to
12876 * validate if batch counter with offset on root table is supported or not.
12879 * Pointer to rte_eth_dev structure.
12882 * 0 on success, a negative errno value otherwise and rte_errno is set.
12885 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12887 struct mlx5_priv *priv = dev->data->dev_private;
12888 struct mlx5_dev_ctx_shared *sh = priv->sh;
12889 struct mlx5_flow_dv_match_params mask = {
12890 .size = sizeof(mask.buf),
12892 struct mlx5_flow_dv_match_params value = {
12893 .size = sizeof(value.buf),
12895 struct mlx5dv_flow_matcher_attr dv_attr = {
12896 .type = IBV_FLOW_ATTR_NORMAL,
12898 .match_criteria_enable = 0,
12899 .match_mask = (void *)&mask,
12901 void *actions[2] = { 0 };
12902 struct mlx5_flow_tbl_resource *tbl = NULL;
12903 struct mlx5_devx_obj *dcs = NULL;
12904 void *matcher = NULL;
12908 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12911 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12914 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12918 actions[1] = priv->drop_queue.hrxq->action;
12919 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12920 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12924 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12928 * If batch counter with offset is not supported, the driver will not
12929 * validate the invalid offset value, flow create should success.
12930 * In this case, it means batch counter is not supported in root table.
12932 * Otherwise, if flow create is failed, counter offset is supported.
12935 DRV_LOG(INFO, "Batch counter is not supported in root "
12936 "table. Switch to fallback mode.");
12937 rte_errno = ENOTSUP;
12939 claim_zero(mlx5_flow_os_destroy_flow(flow));
12941 /* Check matcher to make sure validate fail at flow create. */
12942 if (!matcher || (matcher && errno != EINVAL))
12943 DRV_LOG(ERR, "Unexpected error in counter offset "
12944 "support detection");
12948 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12950 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12952 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12954 claim_zero(mlx5_devx_cmd_destroy(dcs));
12959 * Query a devx counter.
12962 * Pointer to the Ethernet device structure.
12964 * Index to the flow counter.
12966 * Set to clear the counter statistics.
12968 * The statistics value of packets.
12969 * @param[out] bytes
12970 * The statistics value of bytes.
12973 * 0 on success, otherwise return -1.
12976 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12977 uint64_t *pkts, uint64_t *bytes)
12979 struct mlx5_priv *priv = dev->data->dev_private;
12980 struct mlx5_flow_counter *cnt;
12981 uint64_t inn_pkts, inn_bytes;
12984 if (!priv->config.devx)
12987 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12990 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12991 *pkts = inn_pkts - cnt->hits;
12992 *bytes = inn_bytes - cnt->bytes;
12994 cnt->hits = inn_pkts;
12995 cnt->bytes = inn_bytes;
13001 * Get aged-out flows.
13004 * Pointer to the Ethernet device structure.
13005 * @param[in] context
13006 * The address of an array of pointers to the aged-out flows contexts.
13007 * @param[in] nb_contexts
13008 * The length of context array pointers.
13009 * @param[out] error
13010 * Perform verbose error reporting if not NULL. Initialized in case of
13014 * how many contexts get in success, otherwise negative errno value.
13015 * if nb_contexts is 0, return the amount of all aged contexts.
13016 * if nb_contexts is not 0 , return the amount of aged flows reported
13017 * in the context array.
13018 * @note: only stub for now
13021 flow_get_aged_flows(struct rte_eth_dev *dev,
13023 uint32_t nb_contexts,
13024 struct rte_flow_error *error)
13026 struct mlx5_priv *priv = dev->data->dev_private;
13027 struct mlx5_age_info *age_info;
13028 struct mlx5_age_param *age_param;
13029 struct mlx5_flow_counter *counter;
13030 struct mlx5_aso_age_action *act;
13033 if (nb_contexts && !context)
13034 return rte_flow_error_set(error, EINVAL,
13035 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13036 NULL, "empty context");
13037 age_info = GET_PORT_AGE_INFO(priv);
13038 rte_spinlock_lock(&age_info->aged_sl);
13039 LIST_FOREACH(act, &age_info->aged_aso, next) {
13042 context[nb_flows - 1] =
13043 act->age_params.context;
13044 if (!(--nb_contexts))
13048 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13051 age_param = MLX5_CNT_TO_AGE(counter);
13052 context[nb_flows - 1] = age_param->context;
13053 if (!(--nb_contexts))
13057 rte_spinlock_unlock(&age_info->aged_sl);
13058 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13063 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13066 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13068 return flow_dv_counter_alloc(dev, 0);
13072 * Validate shared action.
13073 * Dispatcher for action type specific validation.
13076 * Pointer to the Ethernet device structure.
13078 * Shared action configuration.
13079 * @param[in] action
13080 * The shared action object to validate.
13081 * @param[out] error
13082 * Perform verbose error reporting if not NULL. Initialized in case of
13086 * 0 on success, otherwise negative errno value.
13089 flow_dv_action_validate(struct rte_eth_dev *dev,
13090 const struct rte_flow_shared_action_conf *conf,
13091 const struct rte_flow_action *action,
13092 struct rte_flow_error *err)
13094 struct mlx5_priv *priv = dev->data->dev_private;
13096 RTE_SET_USED(conf);
13097 switch (action->type) {
13098 case RTE_FLOW_ACTION_TYPE_RSS:
13099 return mlx5_validate_action_rss(dev, action, err);
13100 case RTE_FLOW_ACTION_TYPE_AGE:
13101 if (!priv->sh->aso_age_mng)
13102 return rte_flow_error_set(err, ENOTSUP,
13103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13105 "shared age action not supported");
13106 return flow_dv_validate_action_age(0, action, dev, err);
13108 return rte_flow_error_set(err, ENOTSUP,
13109 RTE_FLOW_ERROR_TYPE_ACTION,
13111 "action type not supported");
13116 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13118 struct mlx5_priv *priv = dev->data->dev_private;
13121 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13122 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13127 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13128 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13132 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13133 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13140 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13141 .validate = flow_dv_validate,
13142 .prepare = flow_dv_prepare,
13143 .translate = flow_dv_translate,
13144 .apply = flow_dv_apply,
13145 .remove = flow_dv_remove,
13146 .destroy = flow_dv_destroy,
13147 .query = flow_dv_query,
13148 .create_mtr_tbls = flow_dv_create_mtr_tbl,
13149 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13150 .create_policer_rules = flow_dv_create_policer_rules,
13151 .destroy_policer_rules = flow_dv_destroy_policer_rules,
13152 .counter_alloc = flow_dv_counter_allocate,
13153 .counter_free = flow_dv_counter_free,
13154 .counter_query = flow_dv_counter_query,
13155 .get_aged_flows = flow_get_aged_flows,
13156 .action_validate = flow_dv_action_validate,
13157 .action_create = flow_dv_action_create,
13158 .action_destroy = flow_dv_action_destroy,
13159 .action_update = flow_dv_action_update,
13160 .action_query = flow_dv_action_query,
13161 .sync_domain = flow_dv_sync_domain,
13164 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */