1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 static inline uint16_t
97 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
99 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
100 return RTE_ETHER_TYPE_TEB;
101 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 return RTE_ETHER_TYPE_IPV4;
103 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 return RTE_ETHER_TYPE_IPV6;
105 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
106 return RTE_ETHER_TYPE_MPLS;
111 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
113 struct mlx5_priv *priv = dev->data->dev_private;
115 if (priv->pci_dev == NULL)
117 switch (priv->pci_dev->id.device_id) {
118 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
119 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
120 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
121 return (int16_t)0xfffe;
128 * Initialize flow attributes structure according to flow items' types.
130 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
131 * mode. For tunnel mode, the items to be modified are the outermost ones.
134 * Pointer to item specification.
136 * Pointer to flow attributes structure.
137 * @param[in] dev_flow
138 * Pointer to the sub flow.
139 * @param[in] tunnel_decap
140 * Whether action is after tunnel decapsulation.
143 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
144 struct mlx5_flow *dev_flow, bool tunnel_decap)
146 uint64_t layers = dev_flow->handle->layers;
149 * If layers is already initialized, it means this dev_flow is the
150 * suffix flow, the layers flags is set by the prefix flow. Need to
151 * use the layer flags from prefix flow as the suffix flow may not
152 * have the user defined items as the flow is split.
155 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
157 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
159 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
161 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
166 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
167 uint8_t next_protocol = 0xff;
168 switch (item->type) {
169 case RTE_FLOW_ITEM_TYPE_GRE:
170 case RTE_FLOW_ITEM_TYPE_NVGRE:
171 case RTE_FLOW_ITEM_TYPE_VXLAN:
172 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
173 case RTE_FLOW_ITEM_TYPE_GENEVE:
174 case RTE_FLOW_ITEM_TYPE_MPLS:
178 case RTE_FLOW_ITEM_TYPE_IPV4:
181 if (item->mask != NULL &&
182 ((const struct rte_flow_item_ipv4 *)
183 item->mask)->hdr.next_proto_id)
185 ((const struct rte_flow_item_ipv4 *)
186 (item->spec))->hdr.next_proto_id &
187 ((const struct rte_flow_item_ipv4 *)
188 (item->mask))->hdr.next_proto_id;
189 if ((next_protocol == IPPROTO_IPIP ||
190 next_protocol == IPPROTO_IPV6) && tunnel_decap)
193 case RTE_FLOW_ITEM_TYPE_IPV6:
196 if (item->mask != NULL &&
197 ((const struct rte_flow_item_ipv6 *)
198 item->mask)->hdr.proto)
200 ((const struct rte_flow_item_ipv6 *)
201 (item->spec))->hdr.proto &
202 ((const struct rte_flow_item_ipv6 *)
203 (item->mask))->hdr.proto;
204 if ((next_protocol == IPPROTO_IPIP ||
205 next_protocol == IPPROTO_IPV6) && tunnel_decap)
208 case RTE_FLOW_ITEM_TYPE_UDP:
212 case RTE_FLOW_ITEM_TYPE_TCP:
224 * Convert rte_mtr_color to mlx5 color.
233 rte_col_2_mlx5_col(enum rte_color rcol)
236 case RTE_COLOR_GREEN:
237 return MLX5_FLOW_COLOR_GREEN;
238 case RTE_COLOR_YELLOW:
239 return MLX5_FLOW_COLOR_YELLOW;
241 return MLX5_FLOW_COLOR_RED;
245 return MLX5_FLOW_COLOR_UNDEFINED;
248 struct field_modify_info {
249 uint32_t size; /* Size of field in protocol header, in bytes. */
250 uint32_t offset; /* Offset of field in protocol header, in bytes. */
251 enum mlx5_modification_field id;
254 struct field_modify_info modify_eth[] = {
255 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
256 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
257 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
258 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
262 struct field_modify_info modify_vlan_out_first_vid[] = {
263 /* Size in bits !!! */
264 {12, 0, MLX5_MODI_OUT_FIRST_VID},
268 struct field_modify_info modify_ipv4[] = {
269 {1, 1, MLX5_MODI_OUT_IP_DSCP},
270 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
271 {4, 12, MLX5_MODI_OUT_SIPV4},
272 {4, 16, MLX5_MODI_OUT_DIPV4},
276 struct field_modify_info modify_ipv6[] = {
277 {1, 0, MLX5_MODI_OUT_IP_DSCP},
278 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
279 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
280 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
281 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
282 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
283 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
284 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
285 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
286 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
290 struct field_modify_info modify_udp[] = {
291 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
292 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
296 struct field_modify_info modify_tcp[] = {
297 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
298 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
299 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
300 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
305 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
306 uint8_t next_protocol, uint64_t *item_flags,
309 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
310 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
311 if (next_protocol == IPPROTO_IPIP) {
312 *item_flags |= MLX5_FLOW_LAYER_IPIP;
315 if (next_protocol == IPPROTO_IPV6) {
316 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
321 static inline struct mlx5_hlist *
322 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
323 const char *name, uint32_t size, bool direct_key,
324 bool lcores_share, void *ctx,
325 mlx5_list_create_cb cb_create,
326 mlx5_list_match_cb cb_match,
327 mlx5_list_remove_cb cb_remove,
328 mlx5_list_clone_cb cb_clone,
329 mlx5_list_clone_free_cb cb_clone_free)
331 struct mlx5_hlist *hl;
332 struct mlx5_hlist *expected = NULL;
333 char s[MLX5_NAME_SIZE];
335 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
338 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
339 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
340 ctx, cb_create, cb_match, cb_remove, cb_clone,
343 DRV_LOG(ERR, "%s hash creation failed", name);
347 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
350 mlx5_hlist_destroy(hl);
351 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
356 /* Update VLAN's VID/PCP based on input rte_flow_action.
359 * Pointer to struct rte_flow_action.
361 * Pointer to struct rte_vlan_hdr.
364 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
365 struct rte_vlan_hdr *vlan)
368 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
370 ((const struct rte_flow_action_of_set_vlan_pcp *)
371 action->conf)->vlan_pcp;
372 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
373 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
374 vlan->vlan_tci |= vlan_tci;
375 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
376 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
377 vlan->vlan_tci |= rte_be_to_cpu_16
378 (((const struct rte_flow_action_of_set_vlan_vid *)
379 action->conf)->vlan_vid);
384 * Fetch 1, 2, 3 or 4 byte field from the byte array
385 * and return as unsigned integer in host-endian format.
388 * Pointer to data array.
390 * Size of field to extract.
393 * converted field in host endian format.
395 static inline uint32_t
396 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
405 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
408 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
409 ret = (ret << 8) | *(data + sizeof(uint16_t));
412 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
423 * Convert modify-header action to DV specification.
425 * Data length of each action is determined by provided field description
426 * and the item mask. Data bit offset and width of each action is determined
427 * by provided item mask.
430 * Pointer to item specification.
432 * Pointer to field modification information.
433 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
434 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
435 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
437 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
438 * Negative offset value sets the same offset as source offset.
439 * size field is ignored, value is taken from source field.
440 * @param[in,out] resource
441 * Pointer to the modify-header resource.
443 * Type of modification.
445 * Pointer to the error structure.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 flow_dv_convert_modify_action(struct rte_flow_item *item,
452 struct field_modify_info *field,
453 struct field_modify_info *dcopy,
454 struct mlx5_flow_dv_modify_hdr_resource *resource,
455 uint32_t type, struct rte_flow_error *error)
457 uint32_t i = resource->actions_num;
458 struct mlx5_modification_cmd *actions = resource->actions;
459 uint32_t carry_b = 0;
462 * The item and mask are provided in big-endian format.
463 * The fields should be presented as in big-endian format either.
464 * Mask must be always present, it defines the actual field width.
466 MLX5_ASSERT(item->mask);
467 MLX5_ASSERT(field->size);
473 bool next_field = true;
474 bool next_dcopy = true;
476 if (i >= MLX5_MAX_MODIFY_NUM)
477 return rte_flow_error_set(error, EINVAL,
478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
479 "too many items to modify");
480 /* Fetch variable byte size mask from the array. */
481 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
482 field->offset, field->size);
487 /* Deduce actual data width in bits from mask value. */
488 off_b = rte_bsf32(mask) + carry_b;
489 size_b = sizeof(uint32_t) * CHAR_BIT -
490 off_b - __builtin_clz(mask);
492 actions[i] = (struct mlx5_modification_cmd) {
496 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
499 if (type == MLX5_MODIFICATION_TYPE_COPY) {
501 actions[i].dst_field = dcopy->id;
502 actions[i].dst_offset =
503 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
504 /* Convert entire record to big-endian format. */
505 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
507 * Destination field overflow. Copy leftovers of
508 * a source field to the next destination field.
511 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
514 dcopy->size * CHAR_BIT - dcopy->offset;
515 carry_b = actions[i].length;
519 * Not enough bits in a source filed to fill a
520 * destination field. Switch to the next source.
522 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
523 (size_b == field->size * CHAR_BIT - off_b)) {
525 field->size * CHAR_BIT - off_b;
526 dcopy->offset += actions[i].length;
532 MLX5_ASSERT(item->spec);
533 data = flow_dv_fetch_field((const uint8_t *)item->spec +
534 field->offset, field->size);
535 /* Shift out the trailing masked bits from data. */
536 data = (data & mask) >> off_b;
537 actions[i].data1 = rte_cpu_to_be_32(data);
539 /* Convert entire record to expected big-endian format. */
540 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
544 } while (field->size);
545 if (resource->actions_num == i)
546 return rte_flow_error_set(error, EINVAL,
547 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
548 "invalid modification flow item");
549 resource->actions_num = i;
554 * Convert modify-header set IPv4 address action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to the error structure.
564 * 0 on success, a negative errno value otherwise and rte_errno is set.
567 flow_dv_convert_action_modify_ipv4
568 (struct mlx5_flow_dv_modify_hdr_resource *resource,
569 const struct rte_flow_action *action,
570 struct rte_flow_error *error)
572 const struct rte_flow_action_set_ipv4 *conf =
573 (const struct rte_flow_action_set_ipv4 *)(action->conf);
574 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
575 struct rte_flow_item_ipv4 ipv4;
576 struct rte_flow_item_ipv4 ipv4_mask;
578 memset(&ipv4, 0, sizeof(ipv4));
579 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
580 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
581 ipv4.hdr.src_addr = conf->ipv4_addr;
582 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
584 ipv4.hdr.dst_addr = conf->ipv4_addr;
585 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
588 item.mask = &ipv4_mask;
589 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
590 MLX5_MODIFICATION_TYPE_SET, error);
594 * Convert modify-header set IPv6 address action to DV specification.
596 * @param[in,out] resource
597 * Pointer to the modify-header resource.
599 * Pointer to action specification.
601 * Pointer to the error structure.
604 * 0 on success, a negative errno value otherwise and rte_errno is set.
607 flow_dv_convert_action_modify_ipv6
608 (struct mlx5_flow_dv_modify_hdr_resource *resource,
609 const struct rte_flow_action *action,
610 struct rte_flow_error *error)
612 const struct rte_flow_action_set_ipv6 *conf =
613 (const struct rte_flow_action_set_ipv6 *)(action->conf);
614 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
615 struct rte_flow_item_ipv6 ipv6;
616 struct rte_flow_item_ipv6 ipv6_mask;
618 memset(&ipv6, 0, sizeof(ipv6));
619 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
620 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
621 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
622 sizeof(ipv6.hdr.src_addr));
623 memcpy(&ipv6_mask.hdr.src_addr,
624 &rte_flow_item_ipv6_mask.hdr.src_addr,
625 sizeof(ipv6.hdr.src_addr));
627 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
628 sizeof(ipv6.hdr.dst_addr));
629 memcpy(&ipv6_mask.hdr.dst_addr,
630 &rte_flow_item_ipv6_mask.hdr.dst_addr,
631 sizeof(ipv6.hdr.dst_addr));
634 item.mask = &ipv6_mask;
635 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
636 MLX5_MODIFICATION_TYPE_SET, error);
640 * Convert modify-header set MAC address action to DV specification.
642 * @param[in,out] resource
643 * Pointer to the modify-header resource.
645 * Pointer to action specification.
647 * Pointer to the error structure.
650 * 0 on success, a negative errno value otherwise and rte_errno is set.
653 flow_dv_convert_action_modify_mac
654 (struct mlx5_flow_dv_modify_hdr_resource *resource,
655 const struct rte_flow_action *action,
656 struct rte_flow_error *error)
658 const struct rte_flow_action_set_mac *conf =
659 (const struct rte_flow_action_set_mac *)(action->conf);
660 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
661 struct rte_flow_item_eth eth;
662 struct rte_flow_item_eth eth_mask;
664 memset(ð, 0, sizeof(eth));
665 memset(ð_mask, 0, sizeof(eth_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
667 memcpy(ð.src.addr_bytes, &conf->mac_addr,
668 sizeof(eth.src.addr_bytes));
669 memcpy(ð_mask.src.addr_bytes,
670 &rte_flow_item_eth_mask.src.addr_bytes,
671 sizeof(eth_mask.src.addr_bytes));
673 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
674 sizeof(eth.dst.addr_bytes));
675 memcpy(ð_mask.dst.addr_bytes,
676 &rte_flow_item_eth_mask.dst.addr_bytes,
677 sizeof(eth_mask.dst.addr_bytes));
680 item.mask = ð_mask;
681 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
682 MLX5_MODIFICATION_TYPE_SET, error);
686 * Convert modify-header set VLAN VID action to DV specification.
688 * @param[in,out] resource
689 * Pointer to the modify-header resource.
691 * Pointer to action specification.
693 * Pointer to the error structure.
696 * 0 on success, a negative errno value otherwise and rte_errno is set.
699 flow_dv_convert_action_modify_vlan_vid
700 (struct mlx5_flow_dv_modify_hdr_resource *resource,
701 const struct rte_flow_action *action,
702 struct rte_flow_error *error)
704 const struct rte_flow_action_of_set_vlan_vid *conf =
705 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
706 int i = resource->actions_num;
707 struct mlx5_modification_cmd *actions = resource->actions;
708 struct field_modify_info *field = modify_vlan_out_first_vid;
710 if (i >= MLX5_MAX_MODIFY_NUM)
711 return rte_flow_error_set(error, EINVAL,
712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
713 "too many items to modify");
714 actions[i] = (struct mlx5_modification_cmd) {
715 .action_type = MLX5_MODIFICATION_TYPE_SET,
717 .length = field->size,
718 .offset = field->offset,
720 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
721 actions[i].data1 = conf->vlan_vid;
722 actions[i].data1 = actions[i].data1 << 16;
723 resource->actions_num = ++i;
728 * Convert modify-header set TP action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_tp
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_tp *conf =
757 (const struct rte_flow_action_set_tp *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_udp udp;
760 struct rte_flow_item_udp udp_mask;
761 struct rte_flow_item_tcp tcp;
762 struct rte_flow_item_tcp tcp_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&udp, 0, sizeof(udp));
769 memset(&udp_mask, 0, sizeof(udp_mask));
770 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
771 udp.hdr.src_port = conf->port;
772 udp_mask.hdr.src_port =
773 rte_flow_item_udp_mask.hdr.src_port;
775 udp.hdr.dst_port = conf->port;
776 udp_mask.hdr.dst_port =
777 rte_flow_item_udp_mask.hdr.dst_port;
779 item.type = RTE_FLOW_ITEM_TYPE_UDP;
781 item.mask = &udp_mask;
784 MLX5_ASSERT(attr->tcp);
785 memset(&tcp, 0, sizeof(tcp));
786 memset(&tcp_mask, 0, sizeof(tcp_mask));
787 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
788 tcp.hdr.src_port = conf->port;
789 tcp_mask.hdr.src_port =
790 rte_flow_item_tcp_mask.hdr.src_port;
792 tcp.hdr.dst_port = conf->port;
793 tcp_mask.hdr.dst_port =
794 rte_flow_item_tcp_mask.hdr.dst_port;
796 item.type = RTE_FLOW_ITEM_TYPE_TCP;
798 item.mask = &tcp_mask;
801 return flow_dv_convert_modify_action(&item, field, NULL, resource,
802 MLX5_MODIFICATION_TYPE_SET, error);
806 * Convert modify-header set TTL action to DV specification.
808 * @param[in,out] resource
809 * Pointer to the modify-header resource.
811 * Pointer to action specification.
813 * Pointer to rte_flow_item objects list.
815 * Pointer to flow attributes structure.
816 * @param[in] dev_flow
817 * Pointer to the sub flow.
818 * @param[in] tunnel_decap
819 * Whether action is after tunnel decapsulation.
821 * Pointer to the error structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 flow_dv_convert_action_modify_ttl
828 (struct mlx5_flow_dv_modify_hdr_resource *resource,
829 const struct rte_flow_action *action,
830 const struct rte_flow_item *items,
831 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
832 bool tunnel_decap, struct rte_flow_error *error)
834 const struct rte_flow_action_set_ttl *conf =
835 (const struct rte_flow_action_set_ttl *)(action->conf);
836 struct rte_flow_item item;
837 struct rte_flow_item_ipv4 ipv4;
838 struct rte_flow_item_ipv4 ipv4_mask;
839 struct rte_flow_item_ipv6 ipv6;
840 struct rte_flow_item_ipv6 ipv6_mask;
841 struct field_modify_info *field;
844 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
846 memset(&ipv4, 0, sizeof(ipv4));
847 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
848 ipv4.hdr.time_to_live = conf->ttl_value;
849 ipv4_mask.hdr.time_to_live = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
852 item.mask = &ipv4_mask;
855 MLX5_ASSERT(attr->ipv6);
856 memset(&ipv6, 0, sizeof(ipv6));
857 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
858 ipv6.hdr.hop_limits = conf->ttl_value;
859 ipv6_mask.hdr.hop_limits = 0xFF;
860 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
862 item.mask = &ipv6_mask;
865 return flow_dv_convert_modify_action(&item, field, NULL, resource,
866 MLX5_MODIFICATION_TYPE_SET, error);
870 * Convert modify-header decrement TTL action to DV specification.
872 * @param[in,out] resource
873 * Pointer to the modify-header resource.
875 * Pointer to action specification.
877 * Pointer to rte_flow_item objects list.
879 * Pointer to flow attributes structure.
880 * @param[in] dev_flow
881 * Pointer to the sub flow.
882 * @param[in] tunnel_decap
883 * Whether action is after tunnel decapsulation.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_dec_ttl
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_item *items,
894 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
895 bool tunnel_decap, struct rte_flow_error *error)
897 struct rte_flow_item item;
898 struct rte_flow_item_ipv4 ipv4;
899 struct rte_flow_item_ipv4 ipv4_mask;
900 struct rte_flow_item_ipv6 ipv6;
901 struct rte_flow_item_ipv6 ipv6_mask;
902 struct field_modify_info *field;
905 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
907 memset(&ipv4, 0, sizeof(ipv4));
908 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
909 ipv4.hdr.time_to_live = 0xFF;
910 ipv4_mask.hdr.time_to_live = 0xFF;
911 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
913 item.mask = &ipv4_mask;
916 MLX5_ASSERT(attr->ipv6);
917 memset(&ipv6, 0, sizeof(ipv6));
918 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
919 ipv6.hdr.hop_limits = 0xFF;
920 ipv6_mask.hdr.hop_limits = 0xFF;
921 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
923 item.mask = &ipv6_mask;
926 return flow_dv_convert_modify_action(&item, field, NULL, resource,
927 MLX5_MODIFICATION_TYPE_ADD, error);
931 * Convert modify-header increment/decrement TCP Sequence number
932 * to DV specification.
934 * @param[in,out] resource
935 * Pointer to the modify-header resource.
937 * Pointer to action specification.
939 * Pointer to the error structure.
942 * 0 on success, a negative errno value otherwise and rte_errno is set.
945 flow_dv_convert_action_modify_tcp_seq
946 (struct mlx5_flow_dv_modify_hdr_resource *resource,
947 const struct rte_flow_action *action,
948 struct rte_flow_error *error)
950 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
951 uint64_t value = rte_be_to_cpu_32(*conf);
952 struct rte_flow_item item;
953 struct rte_flow_item_tcp tcp;
954 struct rte_flow_item_tcp tcp_mask;
956 memset(&tcp, 0, sizeof(tcp));
957 memset(&tcp_mask, 0, sizeof(tcp_mask));
958 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
960 * The HW has no decrement operation, only increment operation.
961 * To simulate decrement X from Y using increment operation
962 * we need to add UINT32_MAX X times to Y.
963 * Each adding of UINT32_MAX decrements Y by 1.
966 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
967 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
968 item.type = RTE_FLOW_ITEM_TYPE_TCP;
970 item.mask = &tcp_mask;
971 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
972 MLX5_MODIFICATION_TYPE_ADD, error);
976 * Convert modify-header increment/decrement TCP Acknowledgment number
977 * to DV specification.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_modify_tcp_ack
991 (struct mlx5_flow_dv_modify_hdr_resource *resource,
992 const struct rte_flow_action *action,
993 struct rte_flow_error *error)
995 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
996 uint64_t value = rte_be_to_cpu_32(*conf);
997 struct rte_flow_item item;
998 struct rte_flow_item_tcp tcp;
999 struct rte_flow_item_tcp tcp_mask;
1001 memset(&tcp, 0, sizeof(tcp));
1002 memset(&tcp_mask, 0, sizeof(tcp_mask));
1003 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
1005 * The HW has no decrement operation, only increment operation.
1006 * To simulate decrement X from Y using increment operation
1007 * we need to add UINT32_MAX X times to Y.
1008 * Each adding of UINT32_MAX decrements Y by 1.
1010 value *= UINT32_MAX;
1011 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1012 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1013 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1015 item.mask = &tcp_mask;
1016 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_ADD, error);
1020 static enum mlx5_modification_field reg_to_field[] = {
1021 [REG_NON] = MLX5_MODI_OUT_NONE,
1022 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1023 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1024 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1025 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1026 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1027 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1028 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1029 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1030 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1031 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1035 * Convert register set to DV specification.
1037 * @param[in,out] resource
1038 * Pointer to the modify-header resource.
1040 * Pointer to action specification.
1042 * Pointer to the error structure.
1045 * 0 on success, a negative errno value otherwise and rte_errno is set.
1048 flow_dv_convert_action_set_reg
1049 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1050 const struct rte_flow_action *action,
1051 struct rte_flow_error *error)
1053 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1054 struct mlx5_modification_cmd *actions = resource->actions;
1055 uint32_t i = resource->actions_num;
1057 if (i >= MLX5_MAX_MODIFY_NUM)
1058 return rte_flow_error_set(error, EINVAL,
1059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1060 "too many items to modify");
1061 MLX5_ASSERT(conf->id != REG_NON);
1062 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1063 actions[i] = (struct mlx5_modification_cmd) {
1064 .action_type = MLX5_MODIFICATION_TYPE_SET,
1065 .field = reg_to_field[conf->id],
1066 .offset = conf->offset,
1067 .length = conf->length,
1069 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1070 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1072 resource->actions_num = i;
1077 * Convert SET_TAG action to DV specification.
1080 * Pointer to the rte_eth_dev structure.
1081 * @param[in,out] resource
1082 * Pointer to the modify-header resource.
1084 * Pointer to action specification.
1086 * Pointer to the error structure.
1089 * 0 on success, a negative errno value otherwise and rte_errno is set.
1092 flow_dv_convert_action_set_tag
1093 (struct rte_eth_dev *dev,
1094 struct mlx5_flow_dv_modify_hdr_resource *resource,
1095 const struct rte_flow_action_set_tag *conf,
1096 struct rte_flow_error *error)
1098 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1099 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1100 struct rte_flow_item item = {
1104 struct field_modify_info reg_c_x[] = {
1107 enum mlx5_modification_field reg_type;
1110 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1113 MLX5_ASSERT(ret != REG_NON);
1114 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1115 reg_type = reg_to_field[ret];
1116 MLX5_ASSERT(reg_type > 0);
1117 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1118 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1119 MLX5_MODIFICATION_TYPE_SET, error);
1123 * Convert internal COPY_REG action to DV specification.
1126 * Pointer to the rte_eth_dev structure.
1127 * @param[in,out] res
1128 * Pointer to the modify-header resource.
1130 * Pointer to action specification.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1139 struct mlx5_flow_dv_modify_hdr_resource *res,
1140 const struct rte_flow_action *action,
1141 struct rte_flow_error *error)
1143 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1144 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_src[] = {
1150 {4, 0, reg_to_field[conf->src]},
1153 struct field_modify_info reg_dst = {
1155 .id = reg_to_field[conf->dst],
1157 /* Adjust reg_c[0] usage according to reported mask. */
1158 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1159 struct mlx5_priv *priv = dev->data->dev_private;
1160 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1162 MLX5_ASSERT(reg_c0);
1163 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1164 if (conf->dst == REG_C_0) {
1165 /* Copy to reg_c[0], within mask only. */
1166 reg_dst.offset = rte_bsf32(reg_c0);
1167 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1170 mask = rte_cpu_to_be_32(reg_c0);
1173 return flow_dv_convert_modify_action(&item,
1174 reg_src, ®_dst, res,
1175 MLX5_MODIFICATION_TYPE_COPY,
1180 * Convert MARK action to DV specification. This routine is used
1181 * in extensive metadata only and requires metadata register to be
1182 * handled. In legacy mode hardware tag resource is engaged.
1185 * Pointer to the rte_eth_dev structure.
1187 * Pointer to MARK action specification.
1188 * @param[in,out] resource
1189 * Pointer to the modify-header resource.
1191 * Pointer to the error structure.
1194 * 0 on success, a negative errno value otherwise and rte_errno is set.
1197 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1198 const struct rte_flow_action_mark *conf,
1199 struct mlx5_flow_dv_modify_hdr_resource *resource,
1200 struct rte_flow_error *error)
1202 struct mlx5_priv *priv = dev->data->dev_private;
1203 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1204 priv->sh->dv_mark_mask);
1205 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1206 struct rte_flow_item item = {
1210 struct field_modify_info reg_c_x[] = {
1216 return rte_flow_error_set(error, EINVAL,
1217 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1218 NULL, "zero mark action mask");
1219 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1222 MLX5_ASSERT(reg > 0);
1223 if (reg == REG_C_0) {
1224 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1225 uint32_t shl_c0 = rte_bsf32(msk_c0);
1227 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1228 mask = rte_cpu_to_be_32(mask) & msk_c0;
1229 mask = rte_cpu_to_be_32(mask << shl_c0);
1231 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1232 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1233 MLX5_MODIFICATION_TYPE_SET, error);
1237 * Get metadata register index for specified steering domain.
1240 * Pointer to the rte_eth_dev structure.
1242 * Attributes of flow to determine steering domain.
1244 * Pointer to the error structure.
1247 * positive index on success, a negative errno value otherwise
1248 * and rte_errno is set.
1250 static enum modify_reg
1251 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1252 const struct rte_flow_attr *attr,
1253 struct rte_flow_error *error)
1256 mlx5_flow_get_reg_id(dev, attr->transfer ?
1260 MLX5_METADATA_RX, 0, error);
1262 return rte_flow_error_set(error,
1263 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1264 NULL, "unavailable "
1265 "metadata register");
1270 * Convert SET_META action to DV specification.
1273 * Pointer to the rte_eth_dev structure.
1274 * @param[in,out] resource
1275 * Pointer to the modify-header resource.
1277 * Attributes of flow that includes this item.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_set_meta
1288 (struct rte_eth_dev *dev,
1289 struct mlx5_flow_dv_modify_hdr_resource *resource,
1290 const struct rte_flow_attr *attr,
1291 const struct rte_flow_action_set_meta *conf,
1292 struct rte_flow_error *error)
1294 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1295 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1296 struct rte_flow_item item = {
1300 struct field_modify_info reg_c_x[] = {
1303 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1307 MLX5_ASSERT(reg != REG_NON);
1308 if (reg == REG_C_0) {
1309 struct mlx5_priv *priv = dev->data->dev_private;
1310 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1311 uint32_t shl_c0 = rte_bsf32(msk_c0);
1313 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1314 mask = rte_cpu_to_be_32(mask) & msk_c0;
1315 mask = rte_cpu_to_be_32(mask << shl_c0);
1317 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1318 /* The routine expects parameters in memory as big-endian ones. */
1319 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Convert modify-header set IPv4 DSCP action to DV specification.
1326 * @param[in,out] resource
1327 * Pointer to the modify-header resource.
1329 * Pointer to action specification.
1331 * Pointer to the error structure.
1334 * 0 on success, a negative errno value otherwise and rte_errno is set.
1337 flow_dv_convert_action_modify_ipv4_dscp
1338 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1339 const struct rte_flow_action *action,
1340 struct rte_flow_error *error)
1342 const struct rte_flow_action_set_dscp *conf =
1343 (const struct rte_flow_action_set_dscp *)(action->conf);
1344 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1345 struct rte_flow_item_ipv4 ipv4;
1346 struct rte_flow_item_ipv4 ipv4_mask;
1348 memset(&ipv4, 0, sizeof(ipv4));
1349 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1350 ipv4.hdr.type_of_service = conf->dscp;
1351 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1353 item.mask = &ipv4_mask;
1354 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1355 MLX5_MODIFICATION_TYPE_SET, error);
1359 * Convert modify-header set IPv6 DSCP action to DV specification.
1361 * @param[in,out] resource
1362 * Pointer to the modify-header resource.
1364 * Pointer to action specification.
1366 * Pointer to the error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_convert_action_modify_ipv6_dscp
1373 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1374 const struct rte_flow_action *action,
1375 struct rte_flow_error *error)
1377 const struct rte_flow_action_set_dscp *conf =
1378 (const struct rte_flow_action_set_dscp *)(action->conf);
1379 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1380 struct rte_flow_item_ipv6 ipv6;
1381 struct rte_flow_item_ipv6 ipv6_mask;
1383 memset(&ipv6, 0, sizeof(ipv6));
1384 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1386 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1387 * rdma-core only accept the DSCP bits byte aligned start from
1388 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1389 * bits in IPv6 case as rdma-core requires byte aligned value.
1391 ipv6.hdr.vtc_flow = conf->dscp;
1392 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1394 item.mask = &ipv6_mask;
1395 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1396 MLX5_MODIFICATION_TYPE_SET, error);
1400 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1401 enum rte_flow_field_id field, int inherit,
1402 const struct rte_flow_attr *attr,
1403 struct rte_flow_error *error)
1405 struct mlx5_priv *priv = dev->data->dev_private;
1408 case RTE_FLOW_FIELD_START:
1410 case RTE_FLOW_FIELD_MAC_DST:
1411 case RTE_FLOW_FIELD_MAC_SRC:
1413 case RTE_FLOW_FIELD_VLAN_TYPE:
1415 case RTE_FLOW_FIELD_VLAN_ID:
1417 case RTE_FLOW_FIELD_MAC_TYPE:
1419 case RTE_FLOW_FIELD_IPV4_DSCP:
1421 case RTE_FLOW_FIELD_IPV4_TTL:
1423 case RTE_FLOW_FIELD_IPV4_SRC:
1424 case RTE_FLOW_FIELD_IPV4_DST:
1426 case RTE_FLOW_FIELD_IPV6_DSCP:
1428 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1430 case RTE_FLOW_FIELD_IPV6_SRC:
1431 case RTE_FLOW_FIELD_IPV6_DST:
1433 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1434 case RTE_FLOW_FIELD_TCP_PORT_DST:
1436 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1437 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1439 case RTE_FLOW_FIELD_TCP_FLAGS:
1441 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1442 case RTE_FLOW_FIELD_UDP_PORT_DST:
1444 case RTE_FLOW_FIELD_VXLAN_VNI:
1445 case RTE_FLOW_FIELD_GENEVE_VNI:
1447 case RTE_FLOW_FIELD_GTP_TEID:
1448 case RTE_FLOW_FIELD_TAG:
1450 case RTE_FLOW_FIELD_MARK:
1451 return __builtin_popcount(priv->sh->dv_mark_mask);
1452 case RTE_FLOW_FIELD_META:
1453 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1454 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1455 case RTE_FLOW_FIELD_POINTER:
1456 case RTE_FLOW_FIELD_VALUE:
1457 return inherit < 0 ? 0 : inherit;
1465 mlx5_flow_field_id_to_modify_info
1466 (const struct rte_flow_action_modify_data *data,
1467 struct field_modify_info *info, uint32_t *mask,
1468 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1469 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1471 struct mlx5_priv *priv = dev->data->dev_private;
1475 switch (data->field) {
1476 case RTE_FLOW_FIELD_START:
1477 /* not supported yet */
1480 case RTE_FLOW_FIELD_MAC_DST:
1481 off = data->offset > 16 ? data->offset - 16 : 0;
1483 if (data->offset < 16) {
1484 info[idx] = (struct field_modify_info){2, 4,
1485 MLX5_MODI_OUT_DMAC_15_0};
1487 mask[1] = rte_cpu_to_be_16(0xffff >>
1491 mask[1] = RTE_BE16(0xffff);
1498 info[idx] = (struct field_modify_info){4, 0,
1499 MLX5_MODI_OUT_DMAC_47_16};
1500 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1501 (32 - width)) << off);
1503 if (data->offset < 16)
1504 info[idx++] = (struct field_modify_info){2, 4,
1505 MLX5_MODI_OUT_DMAC_15_0};
1506 info[idx] = (struct field_modify_info){4, 0,
1507 MLX5_MODI_OUT_DMAC_47_16};
1510 case RTE_FLOW_FIELD_MAC_SRC:
1511 off = data->offset > 16 ? data->offset - 16 : 0;
1513 if (data->offset < 16) {
1514 info[idx] = (struct field_modify_info){2, 4,
1515 MLX5_MODI_OUT_SMAC_15_0};
1517 mask[1] = rte_cpu_to_be_16(0xffff >>
1521 mask[1] = RTE_BE16(0xffff);
1528 info[idx] = (struct field_modify_info){4, 0,
1529 MLX5_MODI_OUT_SMAC_47_16};
1530 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1531 (32 - width)) << off);
1533 if (data->offset < 16)
1534 info[idx++] = (struct field_modify_info){2, 4,
1535 MLX5_MODI_OUT_SMAC_15_0};
1536 info[idx] = (struct field_modify_info){4, 0,
1537 MLX5_MODI_OUT_SMAC_47_16};
1540 case RTE_FLOW_FIELD_VLAN_TYPE:
1541 /* not supported yet */
1543 case RTE_FLOW_FIELD_VLAN_ID:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_FIRST_VID};
1547 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1549 case RTE_FLOW_FIELD_MAC_TYPE:
1550 info[idx] = (struct field_modify_info){2, 0,
1551 MLX5_MODI_OUT_ETHERTYPE};
1553 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1555 case RTE_FLOW_FIELD_IPV4_DSCP:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IP_DSCP};
1559 mask[idx] = 0x3f >> (6 - width);
1561 case RTE_FLOW_FIELD_IPV4_TTL:
1562 info[idx] = (struct field_modify_info){1, 0,
1563 MLX5_MODI_OUT_IPV4_TTL};
1565 mask[idx] = 0xff >> (8 - width);
1567 case RTE_FLOW_FIELD_IPV4_SRC:
1568 info[idx] = (struct field_modify_info){4, 0,
1569 MLX5_MODI_OUT_SIPV4};
1571 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574 case RTE_FLOW_FIELD_IPV4_DST:
1575 info[idx] = (struct field_modify_info){4, 0,
1576 MLX5_MODI_OUT_DIPV4};
1578 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1581 case RTE_FLOW_FIELD_IPV6_DSCP:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IP_DSCP};
1585 mask[idx] = 0x3f >> (6 - width);
1587 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1588 info[idx] = (struct field_modify_info){1, 0,
1589 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1591 mask[idx] = 0xff >> (8 - width);
1593 case RTE_FLOW_FIELD_IPV6_SRC:
1595 if (data->offset < 32) {
1596 info[idx] = (struct field_modify_info){4, 12,
1597 MLX5_MODI_OUT_SIPV6_31_0};
1600 rte_cpu_to_be_32(0xffffffff >>
1604 mask[3] = RTE_BE32(0xffffffff);
1611 if (data->offset < 64) {
1612 info[idx] = (struct field_modify_info){4, 8,
1613 MLX5_MODI_OUT_SIPV6_63_32};
1616 rte_cpu_to_be_32(0xffffffff >>
1620 mask[2] = RTE_BE32(0xffffffff);
1627 if (data->offset < 96) {
1628 info[idx] = (struct field_modify_info){4, 4,
1629 MLX5_MODI_OUT_SIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[1] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1645 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1647 if (data->offset < 32)
1648 info[idx++] = (struct field_modify_info){4, 12,
1649 MLX5_MODI_OUT_SIPV6_31_0};
1650 if (data->offset < 64)
1651 info[idx++] = (struct field_modify_info){4, 8,
1652 MLX5_MODI_OUT_SIPV6_63_32};
1653 if (data->offset < 96)
1654 info[idx++] = (struct field_modify_info){4, 4,
1655 MLX5_MODI_OUT_SIPV6_95_64};
1656 if (data->offset < 128)
1657 info[idx++] = (struct field_modify_info){4, 0,
1658 MLX5_MODI_OUT_SIPV6_127_96};
1661 case RTE_FLOW_FIELD_IPV6_DST:
1663 if (data->offset < 32) {
1664 info[idx] = (struct field_modify_info){4, 12,
1665 MLX5_MODI_OUT_DIPV6_31_0};
1668 rte_cpu_to_be_32(0xffffffff >>
1672 mask[3] = RTE_BE32(0xffffffff);
1679 if (data->offset < 64) {
1680 info[idx] = (struct field_modify_info){4, 8,
1681 MLX5_MODI_OUT_DIPV6_63_32};
1684 rte_cpu_to_be_32(0xffffffff >>
1688 mask[2] = RTE_BE32(0xffffffff);
1695 if (data->offset < 96) {
1696 info[idx] = (struct field_modify_info){4, 4,
1697 MLX5_MODI_OUT_DIPV6_95_64};
1700 rte_cpu_to_be_32(0xffffffff >>
1704 mask[1] = RTE_BE32(0xffffffff);
1711 info[idx] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1713 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1715 if (data->offset < 32)
1716 info[idx++] = (struct field_modify_info){4, 12,
1717 MLX5_MODI_OUT_DIPV6_31_0};
1718 if (data->offset < 64)
1719 info[idx++] = (struct field_modify_info){4, 8,
1720 MLX5_MODI_OUT_DIPV6_63_32};
1721 if (data->offset < 96)
1722 info[idx++] = (struct field_modify_info){4, 4,
1723 MLX5_MODI_OUT_DIPV6_95_64};
1724 if (data->offset < 128)
1725 info[idx++] = (struct field_modify_info){4, 0,
1726 MLX5_MODI_OUT_DIPV6_127_96};
1729 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_SPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_PORT_DST:
1736 info[idx] = (struct field_modify_info){2, 0,
1737 MLX5_MODI_OUT_TCP_DPORT};
1739 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1741 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1742 info[idx] = (struct field_modify_info){4, 0,
1743 MLX5_MODI_OUT_TCP_SEQ_NUM};
1745 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1748 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1749 info[idx] = (struct field_modify_info){4, 0,
1750 MLX5_MODI_OUT_TCP_ACK_NUM};
1752 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1755 case RTE_FLOW_FIELD_TCP_FLAGS:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_TCP_FLAGS};
1759 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_SPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_UDP_PORT_DST:
1768 info[idx] = (struct field_modify_info){2, 0,
1769 MLX5_MODI_OUT_UDP_DPORT};
1771 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1773 case RTE_FLOW_FIELD_VXLAN_VNI:
1774 /* not supported yet */
1776 case RTE_FLOW_FIELD_GENEVE_VNI:
1777 /* not supported yet*/
1779 case RTE_FLOW_FIELD_GTP_TEID:
1780 info[idx] = (struct field_modify_info){4, 0,
1781 MLX5_MODI_GTP_TEID};
1783 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1786 case RTE_FLOW_FIELD_TAG:
1788 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1789 data->level, error);
1792 MLX5_ASSERT(reg != REG_NON);
1793 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1794 info[idx] = (struct field_modify_info){4, 0,
1798 rte_cpu_to_be_32(0xffffffff >>
1802 case RTE_FLOW_FIELD_MARK:
1804 uint32_t mark_mask = priv->sh->dv_mark_mask;
1805 uint32_t mark_count = __builtin_popcount(mark_mask);
1806 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1810 MLX5_ASSERT(reg != REG_NON);
1811 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1812 info[idx] = (struct field_modify_info){4, 0,
1815 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1816 (mark_count - width)) & mark_mask);
1819 case RTE_FLOW_FIELD_META:
1821 uint32_t meta_mask = priv->sh->dv_meta_mask;
1822 uint32_t meta_count = __builtin_popcount(meta_mask);
1824 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1825 uint32_t shl_c0 = rte_bsf32(msk_c0);
1826 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1829 MLX5_ASSERT(reg != REG_NON);
1830 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1833 info[idx] = (struct field_modify_info){4, 0,
1836 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1837 (meta_count - width)) & meta_mask);
1840 case RTE_FLOW_FIELD_POINTER:
1841 case RTE_FLOW_FIELD_VALUE:
1849 * Convert modify_field action to DV specification.
1852 * Pointer to the rte_eth_dev structure.
1853 * @param[in,out] resource
1854 * Pointer to the modify-header resource.
1856 * Pointer to action specification.
1858 * Attributes of flow that includes this item.
1860 * Pointer to the error structure.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 flow_dv_convert_action_modify_field
1867 (struct rte_eth_dev *dev,
1868 struct mlx5_flow_dv_modify_hdr_resource *resource,
1869 const struct rte_flow_action *action,
1870 const struct rte_flow_attr *attr,
1871 struct rte_flow_error *error)
1873 const struct rte_flow_action_modify_field *conf =
1874 (const struct rte_flow_action_modify_field *)(action->conf);
1875 struct rte_flow_item item = {
1879 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1881 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1883 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1887 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1888 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1889 type = MLX5_MODIFICATION_TYPE_SET;
1890 /** For SET fill the destination field (field) first. */
1891 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1892 conf->width, &shift, dev,
1894 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1895 (void *)(uintptr_t)conf->src.pvalue :
1896 (void *)(uintptr_t)&conf->src.value;
1898 type = MLX5_MODIFICATION_TYPE_COPY;
1899 /** For COPY fill the destination field (dcopy) without mask. */
1900 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1901 conf->width, &shift, dev,
1903 /** Then construct the source field (field) with mask. */
1904 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1905 conf->width, &shift,
1909 return flow_dv_convert_modify_action(&item,
1910 field, dcopy, resource, type, error);
1914 * Validate MARK item.
1917 * Pointer to the rte_eth_dev structure.
1919 * Item specification.
1921 * Attributes of flow that includes this item.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1930 const struct rte_flow_item *item,
1931 const struct rte_flow_attr *attr __rte_unused,
1932 struct rte_flow_error *error)
1934 struct mlx5_priv *priv = dev->data->dev_private;
1935 struct mlx5_dev_config *config = &priv->config;
1936 const struct rte_flow_item_mark *spec = item->spec;
1937 const struct rte_flow_item_mark *mask = item->mask;
1938 const struct rte_flow_item_mark nic_mask = {
1939 .id = priv->sh->dv_mark_mask,
1943 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1944 return rte_flow_error_set(error, ENOTSUP,
1945 RTE_FLOW_ERROR_TYPE_ITEM, item,
1946 "extended metadata feature"
1948 if (!mlx5_flow_ext_mreg_supported(dev))
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ITEM, item,
1951 "extended metadata register"
1952 " isn't supported");
1954 return rte_flow_error_set(error, ENOTSUP,
1955 RTE_FLOW_ERROR_TYPE_ITEM, item,
1956 "extended metadata register"
1957 " isn't available");
1958 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965 "data cannot be empty");
1966 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1970 "mark id exceeds the limit");
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1976 "mask cannot be zero");
1978 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1979 (const uint8_t *)&nic_mask,
1980 sizeof(struct rte_flow_item_mark),
1981 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1988 * Validate META item.
1991 * Pointer to the rte_eth_dev structure.
1993 * Item specification.
1995 * Attributes of flow that includes this item.
1997 * Pointer to error structure.
2000 * 0 on success, a negative errno value otherwise and rte_errno is set.
2003 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2004 const struct rte_flow_item *item,
2005 const struct rte_flow_attr *attr,
2006 struct rte_flow_error *error)
2008 struct mlx5_priv *priv = dev->data->dev_private;
2009 struct mlx5_dev_config *config = &priv->config;
2010 const struct rte_flow_item_meta *spec = item->spec;
2011 const struct rte_flow_item_meta *mask = item->mask;
2012 struct rte_flow_item_meta nic_mask = {
2019 return rte_flow_error_set(error, EINVAL,
2020 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2022 "data cannot be empty");
2023 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2024 if (!mlx5_flow_ext_mreg_supported(dev))
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 "extended metadata register"
2028 " isn't supported");
2029 reg = flow_dv_get_metadata_reg(dev, attr, error);
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "unavalable extended metadata register");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 nic_mask.data = priv->sh->dv_meta_mask;
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "extended metadata feature "
2048 "should be enabled when "
2049 "meta item is requested "
2050 "with e-switch mode ");
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM, item,
2054 "match on metadata for ingress "
2055 "is not supported in legacy "
2059 mask = &rte_flow_item_meta_mask;
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2063 "mask cannot be zero");
2065 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2066 (const uint8_t *)&nic_mask,
2067 sizeof(struct rte_flow_item_meta),
2068 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2073 * Validate TAG item.
2076 * Pointer to the rte_eth_dev structure.
2078 * Item specification.
2080 * Attributes of flow that includes this item.
2082 * Pointer to error structure.
2085 * 0 on success, a negative errno value otherwise and rte_errno is set.
2088 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2089 const struct rte_flow_item *item,
2090 const struct rte_flow_attr *attr __rte_unused,
2091 struct rte_flow_error *error)
2093 const struct rte_flow_item_tag *spec = item->spec;
2094 const struct rte_flow_item_tag *mask = item->mask;
2095 const struct rte_flow_item_tag nic_mask = {
2096 .data = RTE_BE32(UINT32_MAX),
2101 if (!mlx5_flow_ext_mreg_supported(dev))
2102 return rte_flow_error_set(error, ENOTSUP,
2103 RTE_FLOW_ERROR_TYPE_ITEM, item,
2104 "extensive metadata register"
2105 " isn't supported");
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2110 "data cannot be empty");
2112 mask = &rte_flow_item_tag_mask;
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2116 "mask cannot be zero");
2118 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2119 (const uint8_t *)&nic_mask,
2120 sizeof(struct rte_flow_item_tag),
2121 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2124 if (mask->index != 0xff)
2125 return rte_flow_error_set(error, EINVAL,
2126 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2127 "partial mask for tag index"
2128 " is not supported");
2129 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2132 MLX5_ASSERT(ret != REG_NON);
2137 * Validate vport item.
2140 * Pointer to the rte_eth_dev structure.
2142 * Item specification.
2144 * Attributes of flow that includes this item.
2145 * @param[in] item_flags
2146 * Bit-fields that holds the items detected until now.
2148 * Pointer to error structure.
2151 * 0 on success, a negative errno value otherwise and rte_errno is set.
2154 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2155 const struct rte_flow_item *item,
2156 const struct rte_flow_attr *attr,
2157 uint64_t item_flags,
2158 struct rte_flow_error *error)
2160 const struct rte_flow_item_port_id *spec = item->spec;
2161 const struct rte_flow_item_port_id *mask = item->mask;
2162 const struct rte_flow_item_port_id switch_mask = {
2165 struct mlx5_priv *esw_priv;
2166 struct mlx5_priv *dev_priv;
2169 if (!attr->transfer)
2170 return rte_flow_error_set(error, EINVAL,
2171 RTE_FLOW_ERROR_TYPE_ITEM,
2173 "match on port id is valid only"
2174 " when transfer flag is enabled");
2175 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM, item,
2178 "multiple source ports are not"
2181 mask = &switch_mask;
2182 if (mask->id != 0xffffffff)
2183 return rte_flow_error_set(error, ENOTSUP,
2184 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2186 "no support for partial mask on"
2188 ret = mlx5_flow_item_acceptable
2189 (item, (const uint8_t *)mask,
2190 (const uint8_t *)&rte_flow_item_port_id_mask,
2191 sizeof(struct rte_flow_item_port_id),
2192 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2197 if (spec->id == MLX5_PORT_ESW_MGR)
2199 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2201 return rte_flow_error_set(error, rte_errno,
2202 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2203 "failed to obtain E-Switch info for"
2205 dev_priv = mlx5_dev_to_eswitch_info(dev);
2207 return rte_flow_error_set(error, rte_errno,
2208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2210 "failed to obtain E-Switch info");
2211 if (esw_priv->domain_id != dev_priv->domain_id)
2212 return rte_flow_error_set(error, EINVAL,
2213 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2214 "cannot match on a port from a"
2215 " different E-Switch");
2220 * Validate VLAN item.
2223 * Item specification.
2224 * @param[in] item_flags
2225 * Bit-fields that holds the items detected until now.
2227 * Ethernet device flow is being created on.
2229 * Pointer to error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2236 uint64_t item_flags,
2237 struct rte_eth_dev *dev,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_item_vlan *mask = item->mask;
2241 const struct rte_flow_item_vlan nic_mask = {
2242 .tci = RTE_BE16(UINT16_MAX),
2243 .inner_type = RTE_BE16(UINT16_MAX),
2246 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2248 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2249 MLX5_FLOW_LAYER_INNER_L4) :
2250 (MLX5_FLOW_LAYER_OUTER_L3 |
2251 MLX5_FLOW_LAYER_OUTER_L4);
2252 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2253 MLX5_FLOW_LAYER_OUTER_VLAN;
2255 if (item_flags & vlanm)
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ITEM, item,
2258 "multiple VLAN layers not supported");
2259 else if ((item_flags & l34m) != 0)
2260 return rte_flow_error_set(error, EINVAL,
2261 RTE_FLOW_ERROR_TYPE_ITEM, item,
2262 "VLAN cannot follow L3/L4 layer");
2264 mask = &rte_flow_item_vlan_mask;
2265 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2266 (const uint8_t *)&nic_mask,
2267 sizeof(struct rte_flow_item_vlan),
2268 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2271 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2272 struct mlx5_priv *priv = dev->data->dev_private;
2274 if (priv->vmwa_context) {
2276 * Non-NULL context means we have a virtual machine
2277 * and SR-IOV enabled, we have to create VLAN interface
2278 * to make hypervisor to setup E-Switch vport
2279 * context correctly. We avoid creating the multiple
2280 * VLAN interfaces, so we cannot support VLAN tag mask.
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ITEM,
2285 "VLAN tag mask is not"
2286 " supported in virtual"
2294 * GTP flags are contained in 1 byte of the format:
2295 * -------------------------------------------
2296 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2297 * |-----------------------------------------|
2298 * | value | Version | PT | Res | E | S | PN |
2299 * -------------------------------------------
2301 * Matching is supported only for GTP flags E, S, PN.
2303 #define MLX5_GTP_FLAGS_MASK 0x07
2306 * Validate GTP item.
2309 * Pointer to the rte_eth_dev structure.
2311 * Item specification.
2312 * @param[in] item_flags
2313 * Bit-fields that holds the items detected until now.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2322 const struct rte_flow_item *item,
2323 uint64_t item_flags,
2324 struct rte_flow_error *error)
2326 struct mlx5_priv *priv = dev->data->dev_private;
2327 const struct rte_flow_item_gtp *spec = item->spec;
2328 const struct rte_flow_item_gtp *mask = item->mask;
2329 const struct rte_flow_item_gtp nic_mask = {
2330 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2332 .teid = RTE_BE32(0xffffffff),
2335 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "GTP support is not enabled");
2339 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2340 return rte_flow_error_set(error, ENOTSUP,
2341 RTE_FLOW_ERROR_TYPE_ITEM, item,
2342 "multiple tunnel layers not"
2344 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2345 return rte_flow_error_set(error, EINVAL,
2346 RTE_FLOW_ERROR_TYPE_ITEM, item,
2347 "no outer UDP layer found");
2349 mask = &rte_flow_item_gtp_mask;
2350 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ITEM, item,
2353 "Match is supported for GTP"
2355 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2356 (const uint8_t *)&nic_mask,
2357 sizeof(struct rte_flow_item_gtp),
2358 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2362 * Validate GTP PSC item.
2365 * Item specification.
2366 * @param[in] last_item
2367 * Previous validated item in the pattern items.
2368 * @param[in] gtp_item
2369 * Previous GTP item specification.
2371 * Pointer to flow attributes.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2381 const struct rte_flow_item *gtp_item,
2382 const struct rte_flow_attr *attr,
2383 struct rte_flow_error *error)
2385 const struct rte_flow_item_gtp *gtp_spec;
2386 const struct rte_flow_item_gtp *gtp_mask;
2387 const struct rte_flow_item_gtp_psc *mask;
2388 const struct rte_flow_item_gtp_psc nic_mask = {
2393 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2394 return rte_flow_error_set
2395 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2396 "GTP PSC item must be preceded with GTP item");
2397 gtp_spec = gtp_item->spec;
2398 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2399 /* GTP spec and E flag is requested to match zero. */
2401 (gtp_mask->v_pt_rsv_flags &
2402 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2403 return rte_flow_error_set
2404 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2405 "GTP E flag must be 1 to match GTP PSC");
2406 /* Check the flow is not created in group zero. */
2407 if (!attr->transfer && !attr->group)
2408 return rte_flow_error_set
2409 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2410 "GTP PSC is not supported for group 0");
2411 /* GTP spec is here and E flag is requested to match zero. */
2414 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2415 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2416 (const uint8_t *)&nic_mask,
2417 sizeof(struct rte_flow_item_gtp_psc),
2418 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2422 * Validate IPV4 item.
2423 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2424 * add specific validation of fragment_offset field,
2427 * Item specification.
2428 * @param[in] item_flags
2429 * Bit-fields that holds the items detected until now.
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2438 const struct rte_flow_item *item,
2439 uint64_t item_flags, uint64_t last_item,
2440 uint16_t ether_type, struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 const struct rte_flow_item_ipv4 *spec = item->spec;
2445 const struct rte_flow_item_ipv4 *last = item->last;
2446 const struct rte_flow_item_ipv4 *mask = item->mask;
2447 rte_be16_t fragment_offset_spec = 0;
2448 rte_be16_t fragment_offset_last = 0;
2449 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2451 .src_addr = RTE_BE32(0xffffffff),
2452 .dst_addr = RTE_BE32(0xffffffff),
2453 .type_of_service = 0xff,
2454 .fragment_offset = RTE_BE16(0xffff),
2455 .next_proto_id = 0xff,
2456 .time_to_live = 0xff,
2460 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2461 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2462 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2463 priv->config.hca_attr.inner_ipv4_ihl;
2465 return rte_flow_error_set(error, ENOTSUP,
2466 RTE_FLOW_ERROR_TYPE_ITEM,
2468 "IPV4 ihl offload not supported");
2469 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2471 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2472 ether_type, &nic_ipv4_mask,
2473 MLX5_ITEM_RANGE_ACCEPTED, error);
2477 fragment_offset_spec = spec->hdr.fragment_offset &
2478 mask->hdr.fragment_offset;
2479 if (!fragment_offset_spec)
2482 * spec and mask are valid, enforce using full mask to make sure the
2483 * complete value is used correctly.
2485 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2486 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2487 return rte_flow_error_set(error, EINVAL,
2488 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2489 item, "must use full mask for"
2490 " fragment_offset");
2492 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2493 * indicating this is 1st fragment of fragmented packet.
2494 * This is not yet supported in MLX5, return appropriate error message.
2496 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2497 return rte_flow_error_set(error, ENOTSUP,
2498 RTE_FLOW_ERROR_TYPE_ITEM, item,
2499 "match on first fragment not "
2501 if (fragment_offset_spec && !last)
2502 return rte_flow_error_set(error, ENOTSUP,
2503 RTE_FLOW_ERROR_TYPE_ITEM, item,
2504 "specified value not supported");
2505 /* spec and last are valid, validate the specified range. */
2506 fragment_offset_last = last->hdr.fragment_offset &
2507 mask->hdr.fragment_offset;
2509 * Match on fragment_offset spec 0x2001 and last 0x3fff
2510 * means MF is 1 and frag-offset is > 0.
2511 * This packet is fragment 2nd and onward, excluding last.
2512 * This is not yet supported in MLX5, return appropriate
2515 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2516 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519 last, "match on following "
2520 "fragments not supported");
2522 * Match on fragment_offset spec 0x0001 and last 0x1fff
2523 * means MF is 0 and frag-offset is > 0.
2524 * This packet is last fragment of fragmented packet.
2525 * This is not yet supported in MLX5, return appropriate
2528 if (fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532 last, "match on last "
2533 "fragment not supported");
2535 * Match on fragment_offset spec 0x0001 and last 0x3fff
2536 * means MF and/or frag-offset is not 0.
2537 * This is a fragmented packet.
2538 * Other range values are invalid and rejected.
2540 if (!(fragment_offset_spec == RTE_BE16(1) &&
2541 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2542 return rte_flow_error_set(error, ENOTSUP,
2543 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2544 "specified range not supported");
2549 * Validate IPV6 fragment extension item.
2552 * Item specification.
2553 * @param[in] item_flags
2554 * Bit-fields that holds the items detected until now.
2556 * Pointer to error structure.
2559 * 0 on success, a negative errno value otherwise and rte_errno is set.
2562 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2563 uint64_t item_flags,
2564 struct rte_flow_error *error)
2566 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2567 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2568 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2569 rte_be16_t frag_data_spec = 0;
2570 rte_be16_t frag_data_last = 0;
2571 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2572 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2573 MLX5_FLOW_LAYER_OUTER_L4;
2575 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2577 .next_header = 0xff,
2578 .frag_data = RTE_BE16(0xffff),
2582 if (item_flags & l4m)
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item cannot "
2587 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2588 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM, item,
2591 "ipv6 fragment extension item must "
2592 "follow ipv6 item");
2594 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2595 if (!frag_data_spec)
2598 * spec and mask are valid, enforce using full mask to make sure the
2599 * complete value is used correctly.
2601 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2602 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2605 item, "must use full mask for"
2608 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2609 * This is 1st fragment of fragmented packet.
2611 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2612 return rte_flow_error_set(error, ENOTSUP,
2613 RTE_FLOW_ERROR_TYPE_ITEM, item,
2614 "match on first fragment not "
2616 if (frag_data_spec && !last)
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ITEM, item,
2619 "specified value not supported");
2620 ret = mlx5_flow_item_acceptable
2621 (item, (const uint8_t *)mask,
2622 (const uint8_t *)&nic_mask,
2623 sizeof(struct rte_flow_item_ipv6_frag_ext),
2624 MLX5_ITEM_RANGE_ACCEPTED, error);
2627 /* spec and last are valid, validate the specified range. */
2628 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2630 * Match on frag_data spec 0x0009 and last 0xfff9
2631 * means M is 1 and frag-offset is > 0.
2632 * This packet is fragment 2nd and onward, excluding last.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2637 RTE_IPV6_EHDR_MF_MASK) &&
2638 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2639 return rte_flow_error_set(error, ENOTSUP,
2640 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2641 last, "match on following "
2642 "fragments not supported");
2644 * Match on frag_data spec 0x0008 and last 0xfff8
2645 * means M is 0 and frag-offset is > 0.
2646 * This packet is last fragment of fragmented packet.
2647 * This is not yet supported in MLX5, return appropriate
2650 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2651 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2652 return rte_flow_error_set(error, ENOTSUP,
2653 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2654 last, "match on last "
2655 "fragment not supported");
2656 /* Other range values are invalid and rejected. */
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2659 "specified range not supported");
2663 * Validate ASO CT item.
2666 * Pointer to the rte_eth_dev structure.
2668 * Item specification.
2669 * @param[in] item_flags
2670 * Pointer to bit-fields that holds the items detected until now.
2672 * Pointer to error structure.
2675 * 0 on success, a negative errno value otherwise and rte_errno is set.
2678 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2679 const struct rte_flow_item *item,
2680 uint64_t *item_flags,
2681 struct rte_flow_error *error)
2683 const struct rte_flow_item_conntrack *spec = item->spec;
2684 const struct rte_flow_item_conntrack *mask = item->mask;
2688 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2691 "Only one CT is supported");
2693 mask = &rte_flow_item_conntrack_mask;
2694 flags = spec->flags & mask->flags;
2695 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2696 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2697 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2698 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2701 "Conflict status bits");
2702 /* State change also needs to be considered. */
2703 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2708 * Validate the pop VLAN action.
2711 * Pointer to the rte_eth_dev structure.
2712 * @param[in] action_flags
2713 * Holds the actions detected until now.
2715 * Pointer to the pop vlan action.
2716 * @param[in] item_flags
2717 * The items found in this flow rule.
2719 * Pointer to flow attributes.
2721 * Pointer to error structure.
2724 * 0 on success, a negative errno value otherwise and rte_errno is set.
2727 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2728 uint64_t action_flags,
2729 const struct rte_flow_action *action,
2730 uint64_t item_flags,
2731 const struct rte_flow_attr *attr,
2732 struct rte_flow_error *error)
2734 const struct mlx5_priv *priv = dev->data->dev_private;
2735 struct mlx5_dev_ctx_shared *sh = priv->sh;
2736 bool direction_error = false;
2738 if (!priv->sh->pop_vlan_action)
2739 return rte_flow_error_set(error, ENOTSUP,
2740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2742 "pop vlan action is not supported");
2743 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2744 if (attr->transfer) {
2745 bool fdb_tx = priv->representor_id != UINT16_MAX;
2746 bool is_cx5 = sh->steering_format_version ==
2747 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2749 if (fdb_tx && is_cx5)
2750 direction_error = true;
2751 } else if (attr->egress) {
2752 direction_error = true;
2754 if (direction_error)
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2758 "pop vlan action not supported for egress");
2759 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2760 return rte_flow_error_set(error, ENOTSUP,
2761 RTE_FLOW_ERROR_TYPE_ACTION, action,
2762 "no support for multiple VLAN "
2764 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2765 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2766 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2767 return rte_flow_error_set(error, ENOTSUP,
2768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2770 "cannot pop vlan after decap without "
2771 "match on inner vlan in the flow");
2772 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2773 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2774 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2775 return rte_flow_error_set(error, ENOTSUP,
2776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2778 "cannot pop vlan without a "
2779 "match on (outer) vlan in the flow");
2780 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION, action,
2783 "wrong action order, port_id should "
2784 "be after pop VLAN action");
2785 if (!attr->transfer && priv->representor)
2786 return rte_flow_error_set(error, ENOTSUP,
2787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2788 "pop vlan action for VF representor "
2789 "not supported on NIC table");
2794 * Get VLAN default info from vlan match info.
2797 * the list of item specifications.
2799 * pointer VLAN info to fill to.
2802 * 0 on success, a negative errno value otherwise and rte_errno is set.
2805 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2806 struct rte_vlan_hdr *vlan)
2808 const struct rte_flow_item_vlan nic_mask = {
2809 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2810 MLX5DV_FLOW_VLAN_VID_MASK),
2811 .inner_type = RTE_BE16(0xffff),
2816 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2817 int type = items->type;
2819 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2820 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2823 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2824 const struct rte_flow_item_vlan *vlan_m = items->mask;
2825 const struct rte_flow_item_vlan *vlan_v = items->spec;
2827 /* If VLAN item in pattern doesn't contain data, return here. */
2832 /* Only full match values are accepted */
2833 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2834 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2835 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2837 rte_be_to_cpu_16(vlan_v->tci &
2838 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2840 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2841 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2842 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2844 rte_be_to_cpu_16(vlan_v->tci &
2845 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2847 if (vlan_m->inner_type == nic_mask.inner_type)
2848 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2849 vlan_m->inner_type);
2854 * Validate the push VLAN action.
2857 * Pointer to the rte_eth_dev structure.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] item_flags
2861 * The items found in this flow rule.
2863 * Pointer to the action structure.
2865 * Pointer to flow attributes
2867 * Pointer to error structure.
2870 * 0 on success, a negative errno value otherwise and rte_errno is set.
2873 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2874 uint64_t action_flags,
2875 const struct rte_flow_item_vlan *vlan_m,
2876 const struct rte_flow_action *action,
2877 const struct rte_flow_attr *attr,
2878 struct rte_flow_error *error)
2880 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2881 const struct mlx5_priv *priv = dev->data->dev_private;
2882 struct mlx5_dev_ctx_shared *sh = priv->sh;
2883 bool direction_error = false;
2885 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2886 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, action,
2889 "invalid vlan ethertype");
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after push VLAN");
2895 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2896 if (attr->transfer) {
2897 bool fdb_tx = priv->representor_id != UINT16_MAX;
2898 bool is_cx5 = sh->steering_format_version ==
2899 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2901 if (!fdb_tx && is_cx5)
2902 direction_error = true;
2903 } else if (attr->ingress) {
2904 direction_error = true;
2906 if (direction_error)
2907 return rte_flow_error_set(error, ENOTSUP,
2908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2910 "push vlan action not supported for ingress");
2911 if (!attr->transfer && priv->representor)
2912 return rte_flow_error_set(error, ENOTSUP,
2913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914 "push vlan action for VF representor "
2915 "not supported on NIC table");
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2919 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2920 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2921 !(mlx5_flow_find_action
2922 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2923 return rte_flow_error_set(error, EINVAL,
2924 RTE_FLOW_ERROR_TYPE_ACTION, action,
2925 "not full match mask on VLAN PCP and "
2926 "there is no of_set_vlan_pcp action, "
2927 "push VLAN action cannot figure out "
2930 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2931 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2932 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2933 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2934 !(mlx5_flow_find_action
2935 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2936 return rte_flow_error_set(error, EINVAL,
2937 RTE_FLOW_ERROR_TYPE_ACTION, action,
2938 "not full match mask on VLAN VID and "
2939 "there is no of_set_vlan_vid action, "
2940 "push VLAN action cannot figure out "
2947 * Validate the set VLAN PCP.
2949 * @param[in] action_flags
2950 * Holds the actions detected until now.
2951 * @param[in] actions
2952 * Pointer to the list of actions remaining in the flow rule.
2954 * Pointer to error structure.
2957 * 0 on success, a negative errno value otherwise and rte_errno is set.
2960 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2961 const struct rte_flow_action actions[],
2962 struct rte_flow_error *error)
2964 const struct rte_flow_action *action = actions;
2965 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2967 if (conf->vlan_pcp > 7)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "VLAN PCP value is too big");
2971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2972 return rte_flow_error_set(error, ENOTSUP,
2973 RTE_FLOW_ERROR_TYPE_ACTION, action,
2974 "set VLAN PCP action must follow "
2975 "the push VLAN action");
2976 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2977 return rte_flow_error_set(error, ENOTSUP,
2978 RTE_FLOW_ERROR_TYPE_ACTION, action,
2979 "Multiple VLAN PCP modification are "
2981 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2982 return rte_flow_error_set(error, EINVAL,
2983 RTE_FLOW_ERROR_TYPE_ACTION, action,
2984 "wrong action order, port_id should "
2985 "be after set VLAN PCP");
2990 * Validate the set VLAN VID.
2992 * @param[in] item_flags
2993 * Holds the items detected in this rule.
2994 * @param[in] action_flags
2995 * Holds the actions detected until now.
2996 * @param[in] actions
2997 * Pointer to the list of actions remaining in the flow rule.
2999 * Pointer to error structure.
3002 * 0 on success, a negative errno value otherwise and rte_errno is set.
3005 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3006 uint64_t action_flags,
3007 const struct rte_flow_action actions[],
3008 struct rte_flow_error *error)
3010 const struct rte_flow_action *action = actions;
3011 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3013 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION, action,
3016 "VLAN VID value is too big");
3017 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3018 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3019 return rte_flow_error_set(error, ENOTSUP,
3020 RTE_FLOW_ERROR_TYPE_ACTION, action,
3021 "set VLAN VID action must follow push"
3022 " VLAN action or match on VLAN item");
3023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3024 return rte_flow_error_set(error, ENOTSUP,
3025 RTE_FLOW_ERROR_TYPE_ACTION, action,
3026 "Multiple VLAN VID modifications are "
3028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3029 return rte_flow_error_set(error, EINVAL,
3030 RTE_FLOW_ERROR_TYPE_ACTION, action,
3031 "wrong action order, port_id should "
3032 "be after set VLAN VID");
3037 * Validate the FLAG action.
3040 * Pointer to the rte_eth_dev structure.
3041 * @param[in] action_flags
3042 * Holds the actions detected until now.
3044 * Pointer to flow attributes
3046 * Pointer to error structure.
3049 * 0 on success, a negative errno value otherwise and rte_errno is set.
3052 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3053 uint64_t action_flags,
3054 const struct rte_flow_attr *attr,
3055 struct rte_flow_error *error)
3057 struct mlx5_priv *priv = dev->data->dev_private;
3058 struct mlx5_dev_config *config = &priv->config;
3061 /* Fall back if no extended metadata register support. */
3062 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3063 return mlx5_flow_validate_action_flag(action_flags, attr,
3065 /* Extensive metadata mode requires registers. */
3066 if (!mlx5_flow_ext_mreg_supported(dev))
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "no metadata registers "
3070 "to support flag action");
3071 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3072 return rte_flow_error_set(error, ENOTSUP,
3073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 "extended metadata register"
3075 " isn't available");
3076 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3079 MLX5_ASSERT(ret > 0);
3080 if (action_flags & MLX5_FLOW_ACTION_MARK)
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3083 "can't mark and flag in same flow");
3084 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3088 " actions in same flow");
3093 * Validate MARK action.
3096 * Pointer to the rte_eth_dev structure.
3098 * Pointer to action.
3099 * @param[in] action_flags
3100 * Holds the actions detected until now.
3102 * Pointer to flow attributes
3104 * Pointer to error structure.
3107 * 0 on success, a negative errno value otherwise and rte_errno is set.
3110 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3111 const struct rte_flow_action *action,
3112 uint64_t action_flags,
3113 const struct rte_flow_attr *attr,
3114 struct rte_flow_error *error)
3116 struct mlx5_priv *priv = dev->data->dev_private;
3117 struct mlx5_dev_config *config = &priv->config;
3118 const struct rte_flow_action_mark *mark = action->conf;
3121 if (is_tunnel_offload_active(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "if tunnel offload active");
3126 /* Fall back if no extended metadata register support. */
3127 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3128 return mlx5_flow_validate_action_mark(action, action_flags,
3130 /* Extensive metadata mode requires registers. */
3131 if (!mlx5_flow_ext_mreg_supported(dev))
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3134 "no metadata registers "
3135 "to support mark action");
3136 if (!priv->sh->dv_mark_mask)
3137 return rte_flow_error_set(error, ENOTSUP,
3138 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3139 "extended metadata register"
3140 " isn't available");
3141 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3144 MLX5_ASSERT(ret > 0);
3146 return rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION, action,
3148 "configuration cannot be null");
3149 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3150 return rte_flow_error_set(error, EINVAL,
3151 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3153 "mark id exceeds the limit");
3154 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "can't flag and mark in same flow");
3158 if (action_flags & MLX5_FLOW_ACTION_MARK)
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3161 "can't have 2 mark actions in same"
3167 * Validate SET_META action.
3170 * Pointer to the rte_eth_dev structure.
3172 * Pointer to the action structure.
3173 * @param[in] action_flags
3174 * Holds the actions detected until now.
3176 * Pointer to flow attributes
3178 * Pointer to error structure.
3181 * 0 on success, a negative errno value otherwise and rte_errno is set.
3184 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3185 const struct rte_flow_action *action,
3186 uint64_t action_flags __rte_unused,
3187 const struct rte_flow_attr *attr,
3188 struct rte_flow_error *error)
3190 struct mlx5_priv *priv = dev->data->dev_private;
3191 struct mlx5_dev_config *config = &priv->config;
3192 const struct rte_flow_action_set_meta *conf;
3193 uint32_t nic_mask = UINT32_MAX;
3196 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3197 !mlx5_flow_ext_mreg_supported(dev))
3198 return rte_flow_error_set(error, ENOTSUP,
3199 RTE_FLOW_ERROR_TYPE_ACTION, action,
3200 "extended metadata register"
3201 " isn't supported");
3202 reg = flow_dv_get_metadata_reg(dev, attr, error);
3206 return rte_flow_error_set(error, ENOTSUP,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "unavalable extended metadata register");
3209 if (reg != REG_A && reg != REG_B) {
3210 struct mlx5_priv *priv = dev->data->dev_private;
3212 nic_mask = priv->sh->dv_meta_mask;
3214 if (!(action->conf))
3215 return rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ACTION, action,
3217 "configuration cannot be null");
3218 conf = (const struct rte_flow_action_set_meta *)action->conf;
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION, action,
3222 "zero mask doesn't have any effect");
3223 if (conf->mask & ~nic_mask)
3224 return rte_flow_error_set(error, EINVAL,
3225 RTE_FLOW_ERROR_TYPE_ACTION, action,
3226 "meta data must be within reg C0");
3231 * Validate SET_TAG action.
3234 * Pointer to the rte_eth_dev structure.
3236 * Pointer to the action structure.
3237 * @param[in] action_flags
3238 * Holds the actions detected until now.
3240 * Pointer to flow attributes
3242 * Pointer to error structure.
3245 * 0 on success, a negative errno value otherwise and rte_errno is set.
3248 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3249 const struct rte_flow_action *action,
3250 uint64_t action_flags,
3251 const struct rte_flow_attr *attr,
3252 struct rte_flow_error *error)
3254 const struct rte_flow_action_set_tag *conf;
3255 const uint64_t terminal_action_flags =
3256 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3257 MLX5_FLOW_ACTION_RSS;
3260 if (!mlx5_flow_ext_mreg_supported(dev))
3261 return rte_flow_error_set(error, ENOTSUP,
3262 RTE_FLOW_ERROR_TYPE_ACTION, action,
3263 "extensive metadata register"
3264 " isn't supported");
3265 if (!(action->conf))
3266 return rte_flow_error_set(error, EINVAL,
3267 RTE_FLOW_ERROR_TYPE_ACTION, action,
3268 "configuration cannot be null");
3269 conf = (const struct rte_flow_action_set_tag *)action->conf;
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION, action,
3273 "zero mask doesn't have any effect");
3274 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3277 if (!attr->transfer && attr->ingress &&
3278 (action_flags & terminal_action_flags))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, action,
3281 "set_tag has no effect"
3282 " with terminal actions");
3287 * Validate count action.
3290 * Pointer to rte_eth_dev structure.
3292 * Indicator if action is shared.
3293 * @param[in] action_flags
3294 * Holds the actions detected until now.
3296 * Pointer to error structure.
3299 * 0 on success, a negative errno value otherwise and rte_errno is set.
3302 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3303 uint64_t action_flags,
3304 struct rte_flow_error *error)
3306 struct mlx5_priv *priv = dev->data->dev_private;
3308 if (!priv->sh->devx)
3310 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3313 "duplicate count actions set");
3314 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3315 !priv->sh->flow_hit_aso_en)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3318 "old age and shared count combination is not supported");
3319 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3323 return rte_flow_error_set
3325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3327 "count action not supported");
3331 * Validate the L2 encap action.
3334 * Pointer to the rte_eth_dev structure.
3335 * @param[in] action_flags
3336 * Holds the actions detected until now.
3338 * Pointer to the action structure.
3340 * Pointer to flow attributes.
3342 * Pointer to error structure.
3345 * 0 on success, a negative errno value otherwise and rte_errno is set.
3348 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3349 uint64_t action_flags,
3350 const struct rte_flow_action *action,
3351 const struct rte_flow_attr *attr,
3352 struct rte_flow_error *error)
3354 const struct mlx5_priv *priv = dev->data->dev_private;
3356 if (!(action->conf))
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION, action,
3359 "configuration cannot be null");
3360 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3363 "can only have a single encap action "
3365 if (!attr->transfer && priv->representor)
3366 return rte_flow_error_set(error, ENOTSUP,
3367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368 "encap action for VF representor "
3369 "not supported on NIC table");
3374 * Validate a decap action.
3377 * Pointer to the rte_eth_dev structure.
3378 * @param[in] action_flags
3379 * Holds the actions detected until now.
3381 * Pointer to the action structure.
3382 * @param[in] item_flags
3383 * Holds the items detected.
3385 * Pointer to flow attributes
3387 * Pointer to error structure.
3390 * 0 on success, a negative errno value otherwise and rte_errno is set.
3393 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3394 uint64_t action_flags,
3395 const struct rte_flow_action *action,
3396 const uint64_t item_flags,
3397 const struct rte_flow_attr *attr,
3398 struct rte_flow_error *error)
3400 const struct mlx5_priv *priv = dev->data->dev_private;
3402 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3403 !priv->config.decap_en)
3404 return rte_flow_error_set(error, ENOTSUP,
3405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3406 "decap is not enabled");
3407 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3411 MLX5_FLOW_ACTION_DECAP ? "can only "
3412 "have a single decap action" : "decap "
3413 "after encap is not supported");
3414 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3415 return rte_flow_error_set(error, EINVAL,
3416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3417 "can't have decap action after"
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3423 "decap action not supported for "
3425 if (!attr->transfer && priv->representor)
3426 return rte_flow_error_set(error, ENOTSUP,
3427 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3428 "decap action for VF representor "
3429 "not supported on NIC table");
3430 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3431 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3432 return rte_flow_error_set(error, ENOTSUP,
3433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3434 "VXLAN item should be present for VXLAN decap");
3438 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3441 * Validate the raw encap and decap actions.
3444 * Pointer to the rte_eth_dev structure.
3446 * Pointer to the decap action.
3448 * Pointer to the encap action.
3450 * Pointer to flow attributes
3451 * @param[in/out] action_flags
3452 * Holds the actions detected until now.
3453 * @param[out] actions_n
3454 * pointer to the number of actions counter.
3456 * Pointer to the action structure.
3457 * @param[in] item_flags
3458 * Holds the items detected.
3460 * Pointer to error structure.
3463 * 0 on success, a negative errno value otherwise and rte_errno is set.
3466 flow_dv_validate_action_raw_encap_decap
3467 (struct rte_eth_dev *dev,
3468 const struct rte_flow_action_raw_decap *decap,
3469 const struct rte_flow_action_raw_encap *encap,
3470 const struct rte_flow_attr *attr, uint64_t *action_flags,
3471 int *actions_n, const struct rte_flow_action *action,
3472 uint64_t item_flags, struct rte_flow_error *error)
3474 const struct mlx5_priv *priv = dev->data->dev_private;
3477 if (encap && (!encap->size || !encap->data))
3478 return rte_flow_error_set(error, EINVAL,
3479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3480 "raw encap data cannot be empty");
3481 if (decap && encap) {
3482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3486 else if (encap->size <=
3487 MLX5_ENCAPSULATION_DECISION_SIZE &&
3489 MLX5_ENCAPSULATION_DECISION_SIZE)
3492 else if (encap->size >
3493 MLX5_ENCAPSULATION_DECISION_SIZE &&
3495 MLX5_ENCAPSULATION_DECISION_SIZE)
3496 /* 2 L2 actions: encap and decap. */
3499 return rte_flow_error_set(error,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "unsupported too small "
3503 "raw decap and too small raw "
3504 "encap combination");
3507 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3508 item_flags, attr, error);
3511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3516 return rte_flow_error_set(error, ENOTSUP,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3519 "small raw encap size");
3520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3521 return rte_flow_error_set(error, EINVAL,
3522 RTE_FLOW_ERROR_TYPE_ACTION,
3524 "more than one encap action");
3525 if (!attr->transfer && priv->representor)
3526 return rte_flow_error_set
3528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3529 "encap action for VF representor "
3530 "not supported on NIC table");
3531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3538 * Validate the ASO CT action.
3541 * Pointer to the rte_eth_dev structure.
3542 * @param[in] action_flags
3543 * Holds the actions detected until now.
3544 * @param[in] item_flags
3545 * The items found in this flow rule.
3547 * Pointer to flow attributes.
3549 * Pointer to error structure.
3552 * 0 on success, a negative errno value otherwise and rte_errno is set.
3555 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3556 uint64_t action_flags,
3557 uint64_t item_flags,
3558 const struct rte_flow_attr *attr,
3559 struct rte_flow_error *error)
3563 if (attr->group == 0 && !attr->transfer)
3564 return rte_flow_error_set(error, ENOTSUP,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3567 "Only support non-root table");
3568 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3569 return rte_flow_error_set(error, ENOTSUP,
3570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3571 "CT cannot follow a fate action");
3572 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3573 (action_flags & MLX5_FLOW_ACTION_AGE))
3574 return rte_flow_error_set(error, EINVAL,
3575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3576 "Only one ASO action is supported");
3577 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3578 return rte_flow_error_set(error, EINVAL,
3579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3580 "Encap cannot exist before CT");
3581 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3584 "Not a outer TCP packet");
3589 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3590 struct mlx5_list_entry *entry, void *cb_ctx)
3592 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3593 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3594 struct mlx5_flow_dv_encap_decap_resource *resource;
3596 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3598 if (resource->reformat_type == ctx_resource->reformat_type &&
3599 resource->ft_type == ctx_resource->ft_type &&
3600 resource->flags == ctx_resource->flags &&
3601 resource->size == ctx_resource->size &&
3602 !memcmp((const void *)resource->buf,
3603 (const void *)ctx_resource->buf,
3609 struct mlx5_list_entry *
3610 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3612 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3613 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3614 struct mlx5dv_dr_domain *domain;
3615 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3616 struct mlx5_flow_dv_encap_decap_resource *resource;
3620 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621 domain = sh->fdb_domain;
3622 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3623 domain = sh->rx_domain;
3625 domain = sh->tx_domain;
3626 /* Register new encap/decap resource. */
3627 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3629 rte_flow_error_set(ctx->error, ENOMEM,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3631 "cannot allocate resource memory");
3634 *resource = *ctx_resource;
3635 resource->idx = idx;
3636 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3640 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3641 rte_flow_error_set(ctx->error, ENOMEM,
3642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3643 NULL, "cannot create action");
3647 return &resource->entry;
3650 struct mlx5_list_entry *
3651 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3654 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3655 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3656 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3659 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3661 if (!cache_resource) {
3662 rte_flow_error_set(ctx->error, ENOMEM,
3663 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3664 "cannot allocate resource memory");
3667 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3668 cache_resource->idx = idx;
3669 return &cache_resource->entry;
3673 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3675 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3676 struct mlx5_flow_dv_encap_decap_resource *res =
3677 container_of(entry, typeof(*res), entry);
3679 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3683 * Find existing encap/decap resource or create and register a new one.
3685 * @param[in, out] dev
3686 * Pointer to rte_eth_dev structure.
3687 * @param[in, out] resource
3688 * Pointer to encap/decap resource.
3689 * @parm[in, out] dev_flow
3690 * Pointer to the dev_flow.
3692 * pointer to error structure.
3695 * 0 on success otherwise -errno and errno is set.
3698 flow_dv_encap_decap_resource_register
3699 (struct rte_eth_dev *dev,
3700 struct mlx5_flow_dv_encap_decap_resource *resource,
3701 struct mlx5_flow *dev_flow,
3702 struct rte_flow_error *error)
3704 struct mlx5_priv *priv = dev->data->dev_private;
3705 struct mlx5_dev_ctx_shared *sh = priv->sh;
3706 struct mlx5_list_entry *entry;
3710 uint32_t refmt_type:8;
3712 * Header reformat actions can be shared between
3713 * non-root tables. One bit to indicate non-root
3717 uint32_t reserve:15;
3720 } encap_decap_key = {
3722 .ft_type = resource->ft_type,
3723 .refmt_type = resource->reformat_type,
3724 .is_root = !!dev_flow->dv.group,
3728 struct mlx5_flow_cb_ctx ctx = {
3732 struct mlx5_hlist *encaps_decaps;
3735 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3737 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3739 flow_dv_encap_decap_create_cb,
3740 flow_dv_encap_decap_match_cb,
3741 flow_dv_encap_decap_remove_cb,
3742 flow_dv_encap_decap_clone_cb,
3743 flow_dv_encap_decap_clone_free_cb);
3744 if (unlikely(!encaps_decaps))
3746 resource->flags = dev_flow->dv.group ? 0 : 1;
3747 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3748 sizeof(encap_decap_key.v32), 0);
3749 if (resource->reformat_type !=
3750 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3752 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3753 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3756 resource = container_of(entry, typeof(*resource), entry);
3757 dev_flow->dv.encap_decap = resource;
3758 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3763 * Find existing table jump resource or create and register a new one.
3765 * @param[in, out] dev
3766 * Pointer to rte_eth_dev structure.
3767 * @param[in, out] tbl
3768 * Pointer to flow table resource.
3769 * @parm[in, out] dev_flow
3770 * Pointer to the dev_flow.
3772 * pointer to error structure.
3775 * 0 on success otherwise -errno and errno is set.
3778 flow_dv_jump_tbl_resource_register
3779 (struct rte_eth_dev *dev __rte_unused,
3780 struct mlx5_flow_tbl_resource *tbl,
3781 struct mlx5_flow *dev_flow,
3782 struct rte_flow_error *error __rte_unused)
3784 struct mlx5_flow_tbl_data_entry *tbl_data =
3785 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3788 MLX5_ASSERT(tbl_data->jump.action);
3789 dev_flow->handle->rix_jump = tbl_data->idx;
3790 dev_flow->dv.jump = &tbl_data->jump;
3795 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3796 struct mlx5_list_entry *entry, void *cb_ctx)
3798 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3799 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3800 struct mlx5_flow_dv_port_id_action_resource *res =
3801 container_of(entry, typeof(*res), entry);
3803 return ref->port_id != res->port_id;
3806 struct mlx5_list_entry *
3807 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3809 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3810 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3811 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3812 struct mlx5_flow_dv_port_id_action_resource *resource;
3816 /* Register new port id action resource. */
3817 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3819 rte_flow_error_set(ctx->error, ENOMEM,
3820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3821 "cannot allocate port_id action memory");
3825 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3829 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3830 rte_flow_error_set(ctx->error, ENOMEM,
3831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3832 "cannot create action");
3835 resource->idx = idx;
3836 return &resource->entry;
3839 struct mlx5_list_entry *
3840 flow_dv_port_id_clone_cb(void *tool_ctx,
3841 struct mlx5_list_entry *entry __rte_unused,
3844 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3845 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3846 struct mlx5_flow_dv_port_id_action_resource *resource;
3849 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3851 rte_flow_error_set(ctx->error, ENOMEM,
3852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3853 "cannot allocate port_id action memory");
3856 memcpy(resource, entry, sizeof(*resource));
3857 resource->idx = idx;
3858 return &resource->entry;
3862 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3864 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3865 struct mlx5_flow_dv_port_id_action_resource *resource =
3866 container_of(entry, typeof(*resource), entry);
3868 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3872 * Find existing table port ID resource or create and register a new one.
3874 * @param[in, out] dev
3875 * Pointer to rte_eth_dev structure.
3876 * @param[in, out] ref
3877 * Pointer to port ID action resource reference.
3878 * @parm[in, out] dev_flow
3879 * Pointer to the dev_flow.
3881 * pointer to error structure.
3884 * 0 on success otherwise -errno and errno is set.
3887 flow_dv_port_id_action_resource_register
3888 (struct rte_eth_dev *dev,
3889 struct mlx5_flow_dv_port_id_action_resource *ref,
3890 struct mlx5_flow *dev_flow,
3891 struct rte_flow_error *error)
3893 struct mlx5_priv *priv = dev->data->dev_private;
3894 struct mlx5_list_entry *entry;
3895 struct mlx5_flow_dv_port_id_action_resource *resource;
3896 struct mlx5_flow_cb_ctx ctx = {
3901 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3904 resource = container_of(entry, typeof(*resource), entry);
3905 dev_flow->dv.port_id_action = resource;
3906 dev_flow->handle->rix_port_id_action = resource->idx;
3911 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3912 struct mlx5_list_entry *entry, void *cb_ctx)
3914 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3915 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3916 struct mlx5_flow_dv_push_vlan_action_resource *res =
3917 container_of(entry, typeof(*res), entry);
3919 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3922 struct mlx5_list_entry *
3923 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3925 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3926 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3927 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3928 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3929 struct mlx5dv_dr_domain *domain;
3933 /* Register new port id action resource. */
3934 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3936 rte_flow_error_set(ctx->error, ENOMEM,
3937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3938 "cannot allocate push_vlan action memory");
3942 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3943 domain = sh->fdb_domain;
3944 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3945 domain = sh->rx_domain;
3947 domain = sh->tx_domain;
3948 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3951 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3952 rte_flow_error_set(ctx->error, ENOMEM,
3953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3954 "cannot create push vlan action");
3957 resource->idx = idx;
3958 return &resource->entry;
3961 struct mlx5_list_entry *
3962 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3963 struct mlx5_list_entry *entry __rte_unused,
3966 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3967 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3968 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3971 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3973 rte_flow_error_set(ctx->error, ENOMEM,
3974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3975 "cannot allocate push_vlan action memory");
3978 memcpy(resource, entry, sizeof(*resource));
3979 resource->idx = idx;
3980 return &resource->entry;
3984 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3986 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3987 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3988 container_of(entry, typeof(*resource), entry);
3990 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3994 * Find existing push vlan resource or create and register a new one.
3996 * @param [in, out] dev
3997 * Pointer to rte_eth_dev structure.
3998 * @param[in, out] ref
3999 * Pointer to port ID action resource reference.
4000 * @parm[in, out] dev_flow
4001 * Pointer to the dev_flow.
4003 * pointer to error structure.
4006 * 0 on success otherwise -errno and errno is set.
4009 flow_dv_push_vlan_action_resource_register
4010 (struct rte_eth_dev *dev,
4011 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4012 struct mlx5_flow *dev_flow,
4013 struct rte_flow_error *error)
4015 struct mlx5_priv *priv = dev->data->dev_private;
4016 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4017 struct mlx5_list_entry *entry;
4018 struct mlx5_flow_cb_ctx ctx = {
4023 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4026 resource = container_of(entry, typeof(*resource), entry);
4028 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4029 dev_flow->dv.push_vlan_res = resource;
4034 * Get the size of specific rte_flow_item_type hdr size
4036 * @param[in] item_type
4037 * Tested rte_flow_item_type.
4040 * sizeof struct item_type, 0 if void or irrelevant.
4043 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4047 switch (item_type) {
4048 case RTE_FLOW_ITEM_TYPE_ETH:
4049 retval = sizeof(struct rte_ether_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VLAN:
4052 retval = sizeof(struct rte_vlan_hdr);
4054 case RTE_FLOW_ITEM_TYPE_IPV4:
4055 retval = sizeof(struct rte_ipv4_hdr);
4057 case RTE_FLOW_ITEM_TYPE_IPV6:
4058 retval = sizeof(struct rte_ipv6_hdr);
4060 case RTE_FLOW_ITEM_TYPE_UDP:
4061 retval = sizeof(struct rte_udp_hdr);
4063 case RTE_FLOW_ITEM_TYPE_TCP:
4064 retval = sizeof(struct rte_tcp_hdr);
4066 case RTE_FLOW_ITEM_TYPE_VXLAN:
4067 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4068 retval = sizeof(struct rte_vxlan_hdr);
4070 case RTE_FLOW_ITEM_TYPE_GRE:
4071 case RTE_FLOW_ITEM_TYPE_NVGRE:
4072 retval = sizeof(struct rte_gre_hdr);
4074 case RTE_FLOW_ITEM_TYPE_MPLS:
4075 retval = sizeof(struct rte_mpls_hdr);
4077 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4085 #define MLX5_ENCAP_IPV4_VERSION 0x40
4086 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4087 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4088 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4089 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4090 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4091 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4094 * Convert the encap action data from list of rte_flow_item to raw buffer
4097 * Pointer to rte_flow_item objects list.
4099 * Pointer to the output buffer.
4101 * Pointer to the output buffer size.
4103 * Pointer to the error structure.
4106 * 0 on success, a negative errno value otherwise and rte_errno is set.
4109 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4110 size_t *size, struct rte_flow_error *error)
4112 struct rte_ether_hdr *eth = NULL;
4113 struct rte_vlan_hdr *vlan = NULL;
4114 struct rte_ipv4_hdr *ipv4 = NULL;
4115 struct rte_ipv6_hdr *ipv6 = NULL;
4116 struct rte_udp_hdr *udp = NULL;
4117 struct rte_vxlan_hdr *vxlan = NULL;
4118 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4119 struct rte_gre_hdr *gre = NULL;
4121 size_t temp_size = 0;
4124 return rte_flow_error_set(error, EINVAL,
4125 RTE_FLOW_ERROR_TYPE_ACTION,
4126 NULL, "invalid empty data");
4127 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4128 len = flow_dv_get_item_hdr_len(items->type);
4129 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4130 return rte_flow_error_set(error, EINVAL,
4131 RTE_FLOW_ERROR_TYPE_ACTION,
4132 (void *)items->type,
4133 "items total size is too big"
4134 " for encap action");
4135 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4136 switch (items->type) {
4137 case RTE_FLOW_ITEM_TYPE_ETH:
4138 eth = (struct rte_ether_hdr *)&buf[temp_size];
4140 case RTE_FLOW_ITEM_TYPE_VLAN:
4141 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4143 return rte_flow_error_set(error, EINVAL,
4144 RTE_FLOW_ERROR_TYPE_ACTION,
4145 (void *)items->type,
4146 "eth header not found");
4147 if (!eth->ether_type)
4148 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4150 case RTE_FLOW_ITEM_TYPE_IPV4:
4151 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4153 return rte_flow_error_set(error, EINVAL,
4154 RTE_FLOW_ERROR_TYPE_ACTION,
4155 (void *)items->type,
4156 "neither eth nor vlan"
4158 if (vlan && !vlan->eth_proto)
4159 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4160 else if (eth && !eth->ether_type)
4161 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4162 if (!ipv4->version_ihl)
4163 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4164 MLX5_ENCAP_IPV4_IHL_MIN;
4165 if (!ipv4->time_to_live)
4166 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4168 case RTE_FLOW_ITEM_TYPE_IPV6:
4169 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4171 return rte_flow_error_set(error, EINVAL,
4172 RTE_FLOW_ERROR_TYPE_ACTION,
4173 (void *)items->type,
4174 "neither eth nor vlan"
4176 if (vlan && !vlan->eth_proto)
4177 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4178 else if (eth && !eth->ether_type)
4179 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4180 if (!ipv6->vtc_flow)
4182 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4183 if (!ipv6->hop_limits)
4184 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4186 case RTE_FLOW_ITEM_TYPE_UDP:
4187 udp = (struct rte_udp_hdr *)&buf[temp_size];
4189 return rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ACTION,
4191 (void *)items->type,
4192 "ip header not found");
4193 if (ipv4 && !ipv4->next_proto_id)
4194 ipv4->next_proto_id = IPPROTO_UDP;
4195 else if (ipv6 && !ipv6->proto)
4196 ipv6->proto = IPPROTO_UDP;
4198 case RTE_FLOW_ITEM_TYPE_VXLAN:
4199 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4201 return rte_flow_error_set(error, EINVAL,
4202 RTE_FLOW_ERROR_TYPE_ACTION,
4203 (void *)items->type,
4204 "udp header not found");
4206 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4207 if (!vxlan->vx_flags)
4209 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4211 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4212 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4214 return rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ACTION,
4216 (void *)items->type,
4217 "udp header not found");
4218 if (!vxlan_gpe->proto)
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4225 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4226 if (!vxlan_gpe->vx_flags)
4227 vxlan_gpe->vx_flags =
4228 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4230 case RTE_FLOW_ITEM_TYPE_GRE:
4231 case RTE_FLOW_ITEM_TYPE_NVGRE:
4232 gre = (struct rte_gre_hdr *)&buf[temp_size];
4234 return rte_flow_error_set(error, EINVAL,
4235 RTE_FLOW_ERROR_TYPE_ACTION,
4236 (void *)items->type,
4237 "next protocol not found");
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION,
4241 (void *)items->type,
4242 "ip header not found");
4243 if (ipv4 && !ipv4->next_proto_id)
4244 ipv4->next_proto_id = IPPROTO_GRE;
4245 else if (ipv6 && !ipv6->proto)
4246 ipv6->proto = IPPROTO_GRE;
4248 case RTE_FLOW_ITEM_TYPE_VOID:
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "unsupported item type");
4264 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4266 struct rte_ether_hdr *eth = NULL;
4267 struct rte_vlan_hdr *vlan = NULL;
4268 struct rte_ipv6_hdr *ipv6 = NULL;
4269 struct rte_udp_hdr *udp = NULL;
4273 eth = (struct rte_ether_hdr *)data;
4274 next_hdr = (char *)(eth + 1);
4275 proto = RTE_BE16(eth->ether_type);
4278 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4279 vlan = (struct rte_vlan_hdr *)next_hdr;
4280 proto = RTE_BE16(vlan->eth_proto);
4281 next_hdr += sizeof(struct rte_vlan_hdr);
4284 /* HW calculates IPv4 csum. no need to proceed */
4285 if (proto == RTE_ETHER_TYPE_IPV4)
4288 /* non IPv4/IPv6 header. not supported */
4289 if (proto != RTE_ETHER_TYPE_IPV6) {
4290 return rte_flow_error_set(error, ENOTSUP,
4291 RTE_FLOW_ERROR_TYPE_ACTION,
4292 NULL, "Cannot offload non IPv4/IPv6");
4295 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4297 /* ignore non UDP */
4298 if (ipv6->proto != IPPROTO_UDP)
4301 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4302 udp->dgram_cksum = 0;
4308 * Convert L2 encap action to DV specification.
4311 * Pointer to rte_eth_dev structure.
4313 * Pointer to action structure.
4314 * @param[in, out] dev_flow
4315 * Pointer to the mlx5_flow.
4316 * @param[in] transfer
4317 * Mark if the flow is E-Switch flow.
4319 * Pointer to the error structure.
4322 * 0 on success, a negative errno value otherwise and rte_errno is set.
4325 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4326 const struct rte_flow_action *action,
4327 struct mlx5_flow *dev_flow,
4329 struct rte_flow_error *error)
4331 const struct rte_flow_item *encap_data;
4332 const struct rte_flow_action_raw_encap *raw_encap_data;
4333 struct mlx5_flow_dv_encap_decap_resource res = {
4335 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4336 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4337 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4340 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4342 (const struct rte_flow_action_raw_encap *)action->conf;
4343 res.size = raw_encap_data->size;
4344 memcpy(res.buf, raw_encap_data->data, res.size);
4346 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4348 ((const struct rte_flow_action_vxlan_encap *)
4349 action->conf)->definition;
4352 ((const struct rte_flow_action_nvgre_encap *)
4353 action->conf)->definition;
4354 if (flow_dv_convert_encap_data(encap_data, res.buf,
4358 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4360 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4361 return rte_flow_error_set(error, EINVAL,
4362 RTE_FLOW_ERROR_TYPE_ACTION,
4363 NULL, "can't create L2 encap action");
4368 * Convert L2 decap action to DV specification.
4371 * Pointer to rte_eth_dev structure.
4372 * @param[in, out] dev_flow
4373 * Pointer to the mlx5_flow.
4374 * @param[in] transfer
4375 * Mark if the flow is E-Switch flow.
4377 * Pointer to the error structure.
4380 * 0 on success, a negative errno value otherwise and rte_errno is set.
4383 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4384 struct mlx5_flow *dev_flow,
4386 struct rte_flow_error *error)
4388 struct mlx5_flow_dv_encap_decap_resource res = {
4391 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4392 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4393 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4396 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4397 return rte_flow_error_set(error, EINVAL,
4398 RTE_FLOW_ERROR_TYPE_ACTION,
4399 NULL, "can't create L2 decap action");
4404 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4407 * Pointer to rte_eth_dev structure.
4409 * Pointer to action structure.
4410 * @param[in, out] dev_flow
4411 * Pointer to the mlx5_flow.
4413 * Pointer to the flow attributes.
4415 * Pointer to the error structure.
4418 * 0 on success, a negative errno value otherwise and rte_errno is set.
4421 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4422 const struct rte_flow_action *action,
4423 struct mlx5_flow *dev_flow,
4424 const struct rte_flow_attr *attr,
4425 struct rte_flow_error *error)
4427 const struct rte_flow_action_raw_encap *encap_data;
4428 struct mlx5_flow_dv_encap_decap_resource res;
4430 memset(&res, 0, sizeof(res));
4431 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4432 res.size = encap_data->size;
4433 memcpy(res.buf, encap_data->data, res.size);
4434 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4435 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4436 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4438 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4440 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4441 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4442 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4443 return rte_flow_error_set(error, EINVAL,
4444 RTE_FLOW_ERROR_TYPE_ACTION,
4445 NULL, "can't create encap action");
4450 * Create action push VLAN.
4453 * Pointer to rte_eth_dev structure.
4455 * Pointer to the flow attributes.
4457 * Pointer to the vlan to push to the Ethernet header.
4458 * @param[in, out] dev_flow
4459 * Pointer to the mlx5_flow.
4461 * Pointer to the error structure.
4464 * 0 on success, a negative errno value otherwise and rte_errno is set.
4467 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4468 const struct rte_flow_attr *attr,
4469 const struct rte_vlan_hdr *vlan,
4470 struct mlx5_flow *dev_flow,
4471 struct rte_flow_error *error)
4473 struct mlx5_flow_dv_push_vlan_action_resource res;
4475 memset(&res, 0, sizeof(res));
4477 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4480 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4482 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4483 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4484 return flow_dv_push_vlan_action_resource_register
4485 (dev, &res, dev_flow, error);
4489 * Validate the modify-header actions.
4491 * @param[in] action_flags
4492 * Holds the actions detected until now.
4494 * Pointer to the modify action.
4496 * Pointer to error structure.
4499 * 0 on success, a negative errno value otherwise and rte_errno is set.
4502 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4503 const struct rte_flow_action *action,
4504 struct rte_flow_error *error)
4506 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4507 return rte_flow_error_set(error, EINVAL,
4508 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4509 NULL, "action configuration not set");
4510 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4511 return rte_flow_error_set(error, EINVAL,
4512 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4513 "can't have encap action before"
4519 * Validate the modify-header MAC address actions.
4521 * @param[in] action_flags
4522 * Holds the actions detected until now.
4524 * Pointer to the modify action.
4525 * @param[in] item_flags
4526 * Holds the items detected.
4528 * Pointer to error structure.
4531 * 0 on success, a negative errno value otherwise and rte_errno is set.
4534 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4535 const struct rte_flow_action *action,
4536 const uint64_t item_flags,
4537 struct rte_flow_error *error)
4541 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4543 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4544 return rte_flow_error_set(error, EINVAL,
4545 RTE_FLOW_ERROR_TYPE_ACTION,
4547 "no L2 item in pattern");
4553 * Validate the modify-header IPv4 address actions.
4555 * @param[in] action_flags
4556 * Holds the actions detected until now.
4558 * Pointer to the modify action.
4559 * @param[in] item_flags
4560 * Holds the items detected.
4562 * Pointer to error structure.
4565 * 0 on success, a negative errno value otherwise and rte_errno is set.
4568 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4569 const struct rte_flow_action *action,
4570 const uint64_t item_flags,
4571 struct rte_flow_error *error)
4576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4579 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4580 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4581 if (!(item_flags & layer))
4582 return rte_flow_error_set(error, EINVAL,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "no ipv4 item in pattern");
4591 * Validate the modify-header IPv6 address actions.
4593 * @param[in] action_flags
4594 * Holds the actions detected until now.
4596 * Pointer to the modify action.
4597 * @param[in] item_flags
4598 * Holds the items detected.
4600 * Pointer to error structure.
4603 * 0 on success, a negative errno value otherwise and rte_errno is set.
4606 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4607 const struct rte_flow_action *action,
4608 const uint64_t item_flags,
4609 struct rte_flow_error *error)
4614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4616 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4617 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4618 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4619 if (!(item_flags & layer))
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "no ipv6 item in pattern");
4629 * Validate the modify-header TP actions.
4631 * @param[in] action_flags
4632 * Holds the actions detected until now.
4634 * Pointer to the modify action.
4635 * @param[in] item_flags
4636 * Holds the items detected.
4638 * Pointer to error structure.
4641 * 0 on success, a negative errno value otherwise and rte_errno is set.
4644 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4645 const struct rte_flow_action *action,
4646 const uint64_t item_flags,
4647 struct rte_flow_error *error)
4652 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4654 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4655 MLX5_FLOW_LAYER_INNER_L4 :
4656 MLX5_FLOW_LAYER_OUTER_L4;
4657 if (!(item_flags & layer))
4658 return rte_flow_error_set(error, EINVAL,
4659 RTE_FLOW_ERROR_TYPE_ACTION,
4660 NULL, "no transport layer "
4667 * Validate the modify-header actions of increment/decrement
4668 * TCP Sequence-number.
4670 * @param[in] action_flags
4671 * Holds the actions detected until now.
4673 * Pointer to the modify action.
4674 * @param[in] item_flags
4675 * Holds the items detected.
4677 * Pointer to error structure.
4680 * 0 on success, a negative errno value otherwise and rte_errno is set.
4683 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4684 const struct rte_flow_action *action,
4685 const uint64_t item_flags,
4686 struct rte_flow_error *error)
4691 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4693 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4694 MLX5_FLOW_LAYER_INNER_L4_TCP :
4695 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4696 if (!(item_flags & layer))
4697 return rte_flow_error_set(error, EINVAL,
4698 RTE_FLOW_ERROR_TYPE_ACTION,
4699 NULL, "no TCP item in"
4701 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4702 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4703 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4704 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4705 return rte_flow_error_set(error, EINVAL,
4706 RTE_FLOW_ERROR_TYPE_ACTION,
4708 "cannot decrease and increase"
4709 " TCP sequence number"
4710 " at the same time");
4716 * Validate the modify-header actions of increment/decrement
4717 * TCP Acknowledgment number.
4719 * @param[in] action_flags
4720 * Holds the actions detected until now.
4722 * Pointer to the modify action.
4723 * @param[in] item_flags
4724 * Holds the items detected.
4726 * Pointer to error structure.
4729 * 0 on success, a negative errno value otherwise and rte_errno is set.
4732 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4733 const struct rte_flow_action *action,
4734 const uint64_t item_flags,
4735 struct rte_flow_error *error)
4740 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4742 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4743 MLX5_FLOW_LAYER_INNER_L4_TCP :
4744 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4745 if (!(item_flags & layer))
4746 return rte_flow_error_set(error, EINVAL,
4747 RTE_FLOW_ERROR_TYPE_ACTION,
4748 NULL, "no TCP item in"
4750 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4751 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4752 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4753 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4754 return rte_flow_error_set(error, EINVAL,
4755 RTE_FLOW_ERROR_TYPE_ACTION,
4757 "cannot decrease and increase"
4758 " TCP acknowledgment number"
4759 " at the same time");
4765 * Validate the modify-header TTL actions.
4767 * @param[in] action_flags
4768 * Holds the actions detected until now.
4770 * Pointer to the modify action.
4771 * @param[in] item_flags
4772 * Holds the items detected.
4774 * Pointer to error structure.
4777 * 0 on success, a negative errno value otherwise and rte_errno is set.
4780 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4781 const struct rte_flow_action *action,
4782 const uint64_t item_flags,
4783 struct rte_flow_error *error)
4788 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4790 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4791 MLX5_FLOW_LAYER_INNER_L3 :
4792 MLX5_FLOW_LAYER_OUTER_L3;
4793 if (!(item_flags & layer))
4794 return rte_flow_error_set(error, EINVAL,
4795 RTE_FLOW_ERROR_TYPE_ACTION,
4797 "no IP protocol in pattern");
4803 * Validate the generic modify field actions.
4805 * Pointer to the rte_eth_dev structure.
4806 * @param[in] action_flags
4807 * Holds the actions detected until now.
4809 * Pointer to the modify action.
4811 * Pointer to the flow attributes.
4813 * Pointer to error structure.
4816 * Number of header fields to modify (0 or more) on success,
4817 * a negative errno value otherwise and rte_errno is set.
4820 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4821 const uint64_t action_flags,
4822 const struct rte_flow_action *action,
4823 const struct rte_flow_attr *attr,
4824 struct rte_flow_error *error)
4827 struct mlx5_priv *priv = dev->data->dev_private;
4828 struct mlx5_dev_config *config = &priv->config;
4829 const struct rte_flow_action_modify_field *action_modify_field =
4831 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4832 action_modify_field->dst.field,
4834 uint32_t src_width = mlx5_flow_item_field_width(dev,
4835 action_modify_field->src.field,
4836 dst_width, attr, error);
4838 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4842 if (action_modify_field->width == 0)
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "no bits are requested to be modified");
4846 else if (action_modify_field->width > dst_width ||
4847 action_modify_field->width > src_width)
4848 return rte_flow_error_set(error, EINVAL,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "cannot modify more bits than"
4851 " the width of a field");
4852 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4853 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4854 if ((action_modify_field->dst.offset +
4855 action_modify_field->width > dst_width) ||
4856 (action_modify_field->dst.offset % 32))
4857 return rte_flow_error_set(error, EINVAL,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "destination offset is too big"
4860 " or not aligned to 4 bytes");
4861 if (action_modify_field->dst.level &&
4862 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4863 return rte_flow_error_set(error, ENOTSUP,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "inner header fields modification"
4866 " is not supported");
4868 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4870 if (!attr->transfer && !attr->group)
4871 return rte_flow_error_set(error, ENOTSUP,
4872 RTE_FLOW_ERROR_TYPE_ACTION, action,
4873 "modify field action is not"
4874 " supported for group 0");
4875 if ((action_modify_field->src.offset +
4876 action_modify_field->width > src_width) ||
4877 (action_modify_field->src.offset % 32))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source offset is too big"
4881 " or not aligned to 4 bytes");
4882 if (action_modify_field->src.level &&
4883 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4884 return rte_flow_error_set(error, ENOTSUP,
4885 RTE_FLOW_ERROR_TYPE_ACTION, action,
4886 "inner header fields modification"
4887 " is not supported");
4889 if ((action_modify_field->dst.field ==
4890 action_modify_field->src.field) &&
4891 (action_modify_field->dst.level ==
4892 action_modify_field->src.level))
4893 return rte_flow_error_set(error, EINVAL,
4894 RTE_FLOW_ERROR_TYPE_ACTION, action,
4895 "source and destination fields"
4896 " cannot be the same");
4897 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4898 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4899 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4900 return rte_flow_error_set(error, EINVAL,
4901 RTE_FLOW_ERROR_TYPE_ACTION, action,
4902 "mark, immediate value or a pointer to it"
4903 " cannot be used as a destination");
4904 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4905 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4906 return rte_flow_error_set(error, ENOTSUP,
4907 RTE_FLOW_ERROR_TYPE_ACTION, action,
4908 "modifications of an arbitrary"
4909 " place in a packet is not supported");
4910 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4911 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION, action,
4914 "modifications of the 802.1Q Tag"
4915 " Identifier is not supported");
4916 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4917 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "modifications of the VXLAN Network"
4921 " Identifier is not supported");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4924 return rte_flow_error_set(error, ENOTSUP,
4925 RTE_FLOW_ERROR_TYPE_ACTION, action,
4926 "modifications of the GENEVE Network"
4927 " Identifier is not supported");
4928 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4929 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4930 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4931 !mlx5_flow_ext_mreg_supported(dev))
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify mark in legacy mode"
4935 " or without extensive registers");
4936 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4937 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4938 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4939 !mlx5_flow_ext_mreg_supported(dev))
4940 return rte_flow_error_set(error, ENOTSUP,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "cannot modify meta without"
4943 " extensive registers support");
4944 ret = flow_dv_get_metadata_reg(dev, attr, error);
4945 if (ret < 0 || ret == REG_NON)
4946 return rte_flow_error_set(error, ENOTSUP,
4947 RTE_FLOW_ERROR_TYPE_ACTION, action,
4948 "cannot modify meta without"
4949 " extensive registers available");
4951 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4952 return rte_flow_error_set(error, ENOTSUP,
4953 RTE_FLOW_ERROR_TYPE_ACTION, action,
4954 "add and sub operations"
4955 " are not supported");
4956 return (action_modify_field->width / 32) +
4957 !!(action_modify_field->width % 32);
4961 * Validate jump action.
4964 * Pointer to the jump action.
4965 * @param[in] action_flags
4966 * Holds the actions detected until now.
4967 * @param[in] attributes
4968 * Pointer to flow attributes
4969 * @param[in] external
4970 * Action belongs to flow rule created by request external to PMD.
4972 * Pointer to error structure.
4975 * 0 on success, a negative errno value otherwise and rte_errno is set.
4978 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4979 const struct mlx5_flow_tunnel *tunnel,
4980 const struct rte_flow_action *action,
4981 uint64_t action_flags,
4982 const struct rte_flow_attr *attributes,
4983 bool external, struct rte_flow_error *error)
4985 uint32_t target_group, table;
4987 struct flow_grp_info grp_info = {
4988 .external = !!external,
4989 .transfer = !!attributes->transfer,
4993 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4994 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4995 return rte_flow_error_set(error, EINVAL,
4996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4997 "can't have 2 fate actions in"
5000 return rte_flow_error_set(error, EINVAL,
5001 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5002 NULL, "action configuration not set");
5004 ((const struct rte_flow_action_jump *)action->conf)->group;
5005 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5009 if (attributes->group == target_group &&
5010 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5011 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "target group must be other than"
5015 " the current flow group");
5020 * Validate action PORT_ID / REPRESENTED_PORT.
5023 * Pointer to rte_eth_dev structure.
5024 * @param[in] action_flags
5025 * Bit-fields that holds the actions detected until now.
5027 * PORT_ID / REPRESENTED_PORT action structure.
5029 * Attributes of flow that includes this action.
5031 * Pointer to error structure.
5034 * 0 on success, a negative errno value otherwise and rte_errno is set.
5037 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5038 uint64_t action_flags,
5039 const struct rte_flow_action *action,
5040 const struct rte_flow_attr *attr,
5041 struct rte_flow_error *error)
5043 const struct rte_flow_action_port_id *port_id;
5044 const struct rte_flow_action_ethdev *ethdev;
5045 struct mlx5_priv *act_priv;
5046 struct mlx5_priv *dev_priv;
5049 if (!attr->transfer)
5050 return rte_flow_error_set(error, ENOTSUP,
5051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5053 "port action is valid in transfer"
5055 if (!action || !action->conf)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5059 "port action parameters must be"
5061 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5062 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5063 return rte_flow_error_set(error, EINVAL,
5064 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5065 "can have only one fate actions in"
5067 dev_priv = mlx5_dev_to_eswitch_info(dev);
5069 return rte_flow_error_set(error, rte_errno,
5070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5072 "failed to obtain E-Switch info");
5073 switch (action->type) {
5074 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5075 port_id = action->conf;
5076 port = port_id->original ? dev->data->port_id : port_id->id;
5078 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5079 ethdev = action->conf;
5080 port = ethdev->port_id;
5084 return rte_flow_error_set
5086 RTE_FLOW_ERROR_TYPE_ACTION, action,
5087 "unknown E-Switch action");
5089 act_priv = mlx5_port_to_eswitch_info(port, false);
5091 return rte_flow_error_set
5093 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5094 "failed to obtain E-Switch port id for port");
5095 if (act_priv->domain_id != dev_priv->domain_id)
5096 return rte_flow_error_set
5098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5099 "port does not belong to"
5100 " E-Switch being configured");
5105 * Get the maximum number of modify header actions.
5108 * Pointer to rte_eth_dev structure.
5110 * Whether action is on root table.
5113 * Max number of modify header actions device can support.
5115 static inline unsigned int
5116 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5120 * There's no way to directly query the max capacity from FW.
5121 * The maximal value on root table should be assumed to be supported.
5124 return MLX5_MAX_MODIFY_NUM;
5126 return MLX5_ROOT_TBL_MODIFY_NUM;
5130 * Validate the meter action.
5133 * Pointer to rte_eth_dev structure.
5134 * @param[in] action_flags
5135 * Bit-fields that holds the actions detected until now.
5136 * @param[in] item_flags
5137 * Holds the items detected.
5139 * Pointer to the meter action.
5141 * Attributes of flow that includes this action.
5142 * @param[in] port_id_item
5143 * Pointer to item indicating port id.
5145 * Pointer to error structure.
5148 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5151 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5152 uint64_t action_flags, uint64_t item_flags,
5153 const struct rte_flow_action *action,
5154 const struct rte_flow_attr *attr,
5155 const struct rte_flow_item *port_id_item,
5157 struct rte_flow_error *error)
5159 struct mlx5_priv *priv = dev->data->dev_private;
5160 const struct rte_flow_action_meter *am = action->conf;
5161 struct mlx5_flow_meter_info *fm;
5162 struct mlx5_flow_meter_policy *mtr_policy;
5163 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5166 return rte_flow_error_set(error, EINVAL,
5167 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5168 "meter action conf is NULL");
5170 if (action_flags & MLX5_FLOW_ACTION_METER)
5171 return rte_flow_error_set(error, ENOTSUP,
5172 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5173 "meter chaining not support");
5174 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5175 return rte_flow_error_set(error, ENOTSUP,
5176 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5177 "meter with jump not support");
5179 return rte_flow_error_set(error, ENOTSUP,
5180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5182 "meter action not supported");
5183 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5185 return rte_flow_error_set(error, EINVAL,
5186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5188 /* aso meter can always be shared by different domains */
5189 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5190 !(fm->transfer == attr->transfer ||
5191 (!fm->ingress && !attr->ingress && attr->egress) ||
5192 (!fm->egress && !attr->egress && attr->ingress)))
5193 return rte_flow_error_set(error, EINVAL,
5194 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5195 "Flow attributes domain are either invalid "
5196 "or have a domain conflict with current "
5197 "meter attributes");
5198 if (fm->def_policy) {
5199 if (!((attr->transfer &&
5200 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5202 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5204 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5205 return rte_flow_error_set(error, EINVAL,
5206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5207 "Flow attributes domain "
5208 "have a conflict with current "
5209 "meter domain attributes");
5212 mtr_policy = mlx5_flow_meter_policy_find(dev,
5213 fm->policy_id, NULL);
5215 return rte_flow_error_set(error, EINVAL,
5216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5217 "Invalid policy id for meter ");
5218 if (!((attr->transfer && mtr_policy->transfer) ||
5219 (attr->egress && mtr_policy->egress) ||
5220 (attr->ingress && mtr_policy->ingress)))
5221 return rte_flow_error_set(error, EINVAL,
5222 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5223 "Flow attributes domain "
5224 "have a conflict with current "
5225 "meter domain attributes");
5226 if (attr->transfer && mtr_policy->dev) {
5228 * When policy has fate action of port_id,
5229 * the flow should have the same src port as policy.
5231 struct mlx5_priv *policy_port_priv =
5232 mtr_policy->dev->data->dev_private;
5233 int32_t flow_src_port = priv->representor_id;
5236 const struct rte_flow_item_port_id *spec =
5238 struct mlx5_priv *port_priv =
5239 mlx5_port_to_eswitch_info(spec->id,
5242 return rte_flow_error_set(error,
5244 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5246 "Failed to get port info.");
5247 flow_src_port = port_priv->representor_id;
5249 if (flow_src_port != policy_port_priv->representor_id)
5250 return rte_flow_error_set(error,
5252 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5254 "Flow and meter policy "
5255 "have different src port.");
5256 } else if (mtr_policy->is_rss) {
5257 struct mlx5_meter_policy_action_container *acg =
5258 &mtr_policy->act_cnt[RTE_COLOR_GREEN];
5259 struct mlx5_meter_policy_action_container *acy =
5260 &mtr_policy->act_cnt[RTE_COLOR_YELLOW];
5261 const struct rte_flow_action *rss_act;
5264 MLX5_ASSERT(acg->fate_action ==
5265 MLX5_FLOW_FATE_SHARED_RSS ||
5267 MLX5_FLOW_FATE_SHARED_RSS);
5268 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5272 ret = mlx5_flow_validate_action_rss(rss_act,
5273 action_flags, dev, attr,
5278 *def_policy = false;
5284 * Validate the age action.
5286 * @param[in] action_flags
5287 * Holds the actions detected until now.
5289 * Pointer to the age action.
5291 * Pointer to the Ethernet device structure.
5293 * Pointer to error structure.
5296 * 0 on success, a negative errno value otherwise and rte_errno is set.
5299 flow_dv_validate_action_age(uint64_t action_flags,
5300 const struct rte_flow_action *action,
5301 struct rte_eth_dev *dev,
5302 struct rte_flow_error *error)
5304 struct mlx5_priv *priv = dev->data->dev_private;
5305 const struct rte_flow_action_age *age = action->conf;
5307 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5308 !priv->sh->aso_age_mng))
5309 return rte_flow_error_set(error, ENOTSUP,
5310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5312 "age action not supported");
5313 if (!(action->conf))
5314 return rte_flow_error_set(error, EINVAL,
5315 RTE_FLOW_ERROR_TYPE_ACTION, action,
5316 "configuration cannot be null");
5317 if (!(age->timeout))
5318 return rte_flow_error_set(error, EINVAL,
5319 RTE_FLOW_ERROR_TYPE_ACTION, action,
5320 "invalid timeout value 0");
5321 if (action_flags & MLX5_FLOW_ACTION_AGE)
5322 return rte_flow_error_set(error, EINVAL,
5323 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5324 "duplicate age actions set");
5329 * Validate the modify-header IPv4 DSCP actions.
5331 * @param[in] action_flags
5332 * Holds the actions detected until now.
5334 * Pointer to the modify action.
5335 * @param[in] item_flags
5336 * Holds the items detected.
5338 * Pointer to error structure.
5341 * 0 on success, a negative errno value otherwise and rte_errno is set.
5344 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5345 const struct rte_flow_action *action,
5346 const uint64_t item_flags,
5347 struct rte_flow_error *error)
5351 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5353 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5354 return rte_flow_error_set(error, EINVAL,
5355 RTE_FLOW_ERROR_TYPE_ACTION,
5357 "no ipv4 item in pattern");
5363 * Validate the modify-header IPv6 DSCP actions.
5365 * @param[in] action_flags
5366 * Holds the actions detected until now.
5368 * Pointer to the modify action.
5369 * @param[in] item_flags
5370 * Holds the items detected.
5372 * Pointer to error structure.
5375 * 0 on success, a negative errno value otherwise and rte_errno is set.
5378 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5379 const struct rte_flow_action *action,
5380 const uint64_t item_flags,
5381 struct rte_flow_error *error)
5385 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5387 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5388 return rte_flow_error_set(error, EINVAL,
5389 RTE_FLOW_ERROR_TYPE_ACTION,
5391 "no ipv6 item in pattern");
5397 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5398 struct mlx5_list_entry *entry, void *cb_ctx)
5400 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5401 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5402 struct mlx5_flow_dv_modify_hdr_resource *resource =
5403 container_of(entry, typeof(*resource), entry);
5404 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5406 key_len += ref->actions_num * sizeof(ref->actions[0]);
5407 return ref->actions_num != resource->actions_num ||
5408 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5411 static struct mlx5_indexed_pool *
5412 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5414 struct mlx5_indexed_pool *ipool = __atomic_load_n
5415 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5418 struct mlx5_indexed_pool *expected = NULL;
5419 struct mlx5_indexed_pool_config cfg =
5420 (struct mlx5_indexed_pool_config) {
5421 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5423 sizeof(struct mlx5_modification_cmd),
5428 .release_mem_en = !!sh->reclaim_mode,
5429 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5430 .malloc = mlx5_malloc,
5432 .type = "mlx5_modify_action_resource",
5435 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5436 ipool = mlx5_ipool_create(&cfg);
5439 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5440 &expected, ipool, false,
5442 __ATOMIC_SEQ_CST)) {
5443 mlx5_ipool_destroy(ipool);
5444 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5451 struct mlx5_list_entry *
5452 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5454 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5455 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5456 struct mlx5dv_dr_domain *ns;
5457 struct mlx5_flow_dv_modify_hdr_resource *entry;
5458 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5459 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5460 ref->actions_num - 1);
5462 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5463 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5466 if (unlikely(!ipool)) {
5467 rte_flow_error_set(ctx->error, ENOMEM,
5468 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5469 NULL, "cannot allocate modify ipool");
5472 entry = mlx5_ipool_zmalloc(ipool, &idx);
5474 rte_flow_error_set(ctx->error, ENOMEM,
5475 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5476 "cannot allocate resource memory");
5479 rte_memcpy(&entry->ft_type,
5480 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5481 key_len + data_len);
5482 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5483 ns = sh->fdb_domain;
5484 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5488 ret = mlx5_flow_os_create_flow_action_modify_header
5489 (sh->cdev->ctx, ns, entry,
5490 data_len, &entry->action);
5492 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5493 rte_flow_error_set(ctx->error, ENOMEM,
5494 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5495 NULL, "cannot create modification action");
5499 return &entry->entry;
5502 struct mlx5_list_entry *
5503 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5506 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5507 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5508 struct mlx5_flow_dv_modify_hdr_resource *entry;
5509 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5510 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5513 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5516 rte_flow_error_set(ctx->error, ENOMEM,
5517 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5518 "cannot allocate resource memory");
5521 memcpy(entry, oentry, sizeof(*entry) + data_len);
5523 return &entry->entry;
5527 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5529 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5530 struct mlx5_flow_dv_modify_hdr_resource *res =
5531 container_of(entry, typeof(*res), entry);
5533 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5537 * Validate the sample action.
5539 * @param[in, out] action_flags
5540 * Holds the actions detected until now.
5542 * Pointer to the sample action.
5544 * Pointer to the Ethernet device structure.
5546 * Attributes of flow that includes this action.
5547 * @param[in] item_flags
5548 * Holds the items detected.
5550 * Pointer to the RSS action.
5551 * @param[out] sample_rss
5552 * Pointer to the RSS action in sample action list.
5554 * Pointer to the COUNT action in sample action list.
5555 * @param[out] fdb_mirror_limit
5556 * Pointer to the FDB mirror limitation flag.
5558 * Pointer to error structure.
5561 * 0 on success, a negative errno value otherwise and rte_errno is set.
5564 flow_dv_validate_action_sample(uint64_t *action_flags,
5565 const struct rte_flow_action *action,
5566 struct rte_eth_dev *dev,
5567 const struct rte_flow_attr *attr,
5568 uint64_t item_flags,
5569 const struct rte_flow_action_rss *rss,
5570 const struct rte_flow_action_rss **sample_rss,
5571 const struct rte_flow_action_count **count,
5572 int *fdb_mirror_limit,
5573 struct rte_flow_error *error)
5575 struct mlx5_priv *priv = dev->data->dev_private;
5576 struct mlx5_dev_config *dev_conf = &priv->config;
5577 const struct rte_flow_action_sample *sample = action->conf;
5578 const struct rte_flow_action *act;
5579 uint64_t sub_action_flags = 0;
5580 uint16_t queue_index = 0xFFFF;
5585 return rte_flow_error_set(error, EINVAL,
5586 RTE_FLOW_ERROR_TYPE_ACTION, action,
5587 "configuration cannot be NULL");
5588 if (sample->ratio == 0)
5589 return rte_flow_error_set(error, EINVAL,
5590 RTE_FLOW_ERROR_TYPE_ACTION, action,
5591 "ratio value starts from 1");
5592 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5593 return rte_flow_error_set(error, ENOTSUP,
5594 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5596 "sample action not supported");
5597 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5598 return rte_flow_error_set(error, EINVAL,
5599 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5600 "Multiple sample actions not "
5602 if (*action_flags & MLX5_FLOW_ACTION_METER)
5603 return rte_flow_error_set(error, EINVAL,
5604 RTE_FLOW_ERROR_TYPE_ACTION, action,
5605 "wrong action order, meter should "
5606 "be after sample action");
5607 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5608 return rte_flow_error_set(error, EINVAL,
5609 RTE_FLOW_ERROR_TYPE_ACTION, action,
5610 "wrong action order, jump should "
5611 "be after sample action");
5612 if (*action_flags & MLX5_FLOW_ACTION_CT)
5613 return rte_flow_error_set(error, EINVAL,
5614 RTE_FLOW_ERROR_TYPE_ACTION, action,
5615 "Sample after CT not supported");
5616 act = sample->actions;
5617 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5618 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5619 return rte_flow_error_set(error, ENOTSUP,
5620 RTE_FLOW_ERROR_TYPE_ACTION,
5621 act, "too many actions");
5622 switch (act->type) {
5623 case RTE_FLOW_ACTION_TYPE_QUEUE:
5624 ret = mlx5_flow_validate_action_queue(act,
5630 queue_index = ((const struct rte_flow_action_queue *)
5631 (act->conf))->index;
5632 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5635 case RTE_FLOW_ACTION_TYPE_RSS:
5636 *sample_rss = act->conf;
5637 ret = mlx5_flow_validate_action_rss(act,
5644 if (rss && *sample_rss &&
5645 ((*sample_rss)->level != rss->level ||
5646 (*sample_rss)->types != rss->types))
5647 return rte_flow_error_set(error, ENOTSUP,
5648 RTE_FLOW_ERROR_TYPE_ACTION,
5650 "Can't use the different RSS types "
5651 "or level in the same flow");
5652 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5653 queue_index = (*sample_rss)->queue[0];
5654 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5657 case RTE_FLOW_ACTION_TYPE_MARK:
5658 ret = flow_dv_validate_action_mark(dev, act,
5663 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5664 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5665 MLX5_FLOW_ACTION_MARK_EXT;
5667 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5670 case RTE_FLOW_ACTION_TYPE_COUNT:
5671 ret = flow_dv_validate_action_count
5672 (dev, false, *action_flags | sub_action_flags,
5677 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5678 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5681 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5682 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5683 ret = flow_dv_validate_action_port_id(dev,
5690 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5693 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5694 ret = flow_dv_validate_action_raw_encap_decap
5695 (dev, NULL, act->conf, attr, &sub_action_flags,
5696 &actions_n, action, item_flags, error);
5701 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5702 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5703 ret = flow_dv_validate_action_l2_encap(dev,
5709 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5713 return rte_flow_error_set(error, ENOTSUP,
5714 RTE_FLOW_ERROR_TYPE_ACTION,
5716 "Doesn't support optional "
5720 if (attr->ingress && !attr->transfer) {
5721 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5722 MLX5_FLOW_ACTION_RSS)))
5723 return rte_flow_error_set(error, EINVAL,
5724 RTE_FLOW_ERROR_TYPE_ACTION,
5726 "Ingress must has a dest "
5727 "QUEUE for Sample");
5728 } else if (attr->egress && !attr->transfer) {
5729 return rte_flow_error_set(error, ENOTSUP,
5730 RTE_FLOW_ERROR_TYPE_ACTION,
5732 "Sample Only support Ingress "
5734 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5735 MLX5_ASSERT(attr->transfer);
5736 if (sample->ratio > 1)
5737 return rte_flow_error_set(error, ENOTSUP,
5738 RTE_FLOW_ERROR_TYPE_ACTION,
5740 "E-Switch doesn't support "
5741 "any optional action "
5743 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5744 return rte_flow_error_set(error, ENOTSUP,
5745 RTE_FLOW_ERROR_TYPE_ACTION,
5747 "unsupported action QUEUE");
5748 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5749 return rte_flow_error_set(error, ENOTSUP,
5750 RTE_FLOW_ERROR_TYPE_ACTION,
5752 "unsupported action QUEUE");
5753 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5754 return rte_flow_error_set(error, EINVAL,
5755 RTE_FLOW_ERROR_TYPE_ACTION,
5757 "E-Switch must has a dest "
5758 "port for mirroring");
5759 if (!priv->config.hca_attr.reg_c_preserve &&
5760 priv->representor_id != UINT16_MAX)
5761 *fdb_mirror_limit = 1;
5763 /* Continue validation for Xcap actions.*/
5764 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5765 (queue_index == 0xFFFF ||
5766 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5767 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5768 MLX5_FLOW_XCAP_ACTIONS)
5769 return rte_flow_error_set(error, ENOTSUP,
5770 RTE_FLOW_ERROR_TYPE_ACTION,
5771 NULL, "encap and decap "
5772 "combination aren't "
5774 if (!attr->transfer && attr->ingress && (sub_action_flags &
5775 MLX5_FLOW_ACTION_ENCAP))
5776 return rte_flow_error_set(error, ENOTSUP,
5777 RTE_FLOW_ERROR_TYPE_ACTION,
5778 NULL, "encap is not supported"
5779 " for ingress traffic");
5785 * Find existing modify-header resource or create and register a new one.
5787 * @param dev[in, out]
5788 * Pointer to rte_eth_dev structure.
5789 * @param[in, out] resource
5790 * Pointer to modify-header resource.
5791 * @parm[in, out] dev_flow
5792 * Pointer to the dev_flow.
5794 * pointer to error structure.
5797 * 0 on success otherwise -errno and errno is set.
5800 flow_dv_modify_hdr_resource_register
5801 (struct rte_eth_dev *dev,
5802 struct mlx5_flow_dv_modify_hdr_resource *resource,
5803 struct mlx5_flow *dev_flow,
5804 struct rte_flow_error *error)
5806 struct mlx5_priv *priv = dev->data->dev_private;
5807 struct mlx5_dev_ctx_shared *sh = priv->sh;
5808 uint32_t key_len = sizeof(*resource) -
5809 offsetof(typeof(*resource), ft_type) +
5810 resource->actions_num * sizeof(resource->actions[0]);
5811 struct mlx5_list_entry *entry;
5812 struct mlx5_flow_cb_ctx ctx = {
5816 struct mlx5_hlist *modify_cmds;
5819 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5821 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5823 flow_dv_modify_create_cb,
5824 flow_dv_modify_match_cb,
5825 flow_dv_modify_remove_cb,
5826 flow_dv_modify_clone_cb,
5827 flow_dv_modify_clone_free_cb);
5828 if (unlikely(!modify_cmds))
5830 resource->root = !dev_flow->dv.group;
5831 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5833 return rte_flow_error_set(error, EOVERFLOW,
5834 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5835 "too many modify header items");
5836 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5837 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5840 resource = container_of(entry, typeof(*resource), entry);
5841 dev_flow->handle->dvh.modify_hdr = resource;
5846 * Get DV flow counter by index.
5849 * Pointer to the Ethernet device structure.
5851 * mlx5 flow counter index in the container.
5853 * mlx5 flow counter pool in the container.
5856 * Pointer to the counter, NULL otherwise.
5858 static struct mlx5_flow_counter *
5859 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5861 struct mlx5_flow_counter_pool **ppool)
5863 struct mlx5_priv *priv = dev->data->dev_private;
5864 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5865 struct mlx5_flow_counter_pool *pool;
5867 /* Decrease to original index and clear shared bit. */
5868 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5869 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5870 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5874 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5878 * Check the devx counter belongs to the pool.
5881 * Pointer to the counter pool.
5883 * The counter devx ID.
5886 * True if counter belongs to the pool, false otherwise.
5889 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5891 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5892 MLX5_COUNTERS_PER_POOL;
5894 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5900 * Get a pool by devx counter ID.
5903 * Pointer to the counter management.
5905 * The counter devx ID.
5908 * The counter pool pointer if exists, NULL otherwise,
5910 static struct mlx5_flow_counter_pool *
5911 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5914 struct mlx5_flow_counter_pool *pool = NULL;
5916 rte_spinlock_lock(&cmng->pool_update_sl);
5917 /* Check last used pool. */
5918 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5919 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5920 pool = cmng->pools[cmng->last_pool_idx];
5923 /* ID out of range means no suitable pool in the container. */
5924 if (id > cmng->max_id || id < cmng->min_id)
5927 * Find the pool from the end of the container, since mostly counter
5928 * ID is sequence increasing, and the last pool should be the needed
5933 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5935 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5941 rte_spinlock_unlock(&cmng->pool_update_sl);
5946 * Resize a counter container.
5949 * Pointer to the Ethernet device structure.
5952 * 0 on success, otherwise negative errno value and rte_errno is set.
5955 flow_dv_container_resize(struct rte_eth_dev *dev)
5957 struct mlx5_priv *priv = dev->data->dev_private;
5958 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5959 void *old_pools = cmng->pools;
5960 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5961 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5962 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5969 memcpy(pools, old_pools, cmng->n *
5970 sizeof(struct mlx5_flow_counter_pool *));
5972 cmng->pools = pools;
5974 mlx5_free(old_pools);
5979 * Query a devx flow counter.
5982 * Pointer to the Ethernet device structure.
5983 * @param[in] counter
5984 * Index to the flow counter.
5986 * The statistics value of packets.
5988 * The statistics value of bytes.
5991 * 0 on success, otherwise a negative errno value and rte_errno is set.
5994 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5997 struct mlx5_priv *priv = dev->data->dev_private;
5998 struct mlx5_flow_counter_pool *pool = NULL;
5999 struct mlx5_flow_counter *cnt;
6002 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6004 if (priv->sh->cmng.counter_fallback)
6005 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6006 0, pkts, bytes, 0, NULL, NULL, 0);
6007 rte_spinlock_lock(&pool->sl);
6012 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6013 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6014 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6016 rte_spinlock_unlock(&pool->sl);
6021 * Create and initialize a new counter pool.
6024 * Pointer to the Ethernet device structure.
6026 * The devX counter handle.
6028 * Whether the pool is for counter that was allocated for aging.
6029 * @param[in/out] cont_cur
6030 * Pointer to the container pointer, it will be update in pool resize.
6033 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6035 static struct mlx5_flow_counter_pool *
6036 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6039 struct mlx5_priv *priv = dev->data->dev_private;
6040 struct mlx5_flow_counter_pool *pool;
6041 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6042 bool fallback = priv->sh->cmng.counter_fallback;
6043 uint32_t size = sizeof(*pool);
6045 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6046 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6047 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6053 pool->is_aged = !!age;
6054 pool->query_gen = 0;
6055 pool->min_dcs = dcs;
6056 rte_spinlock_init(&pool->sl);
6057 rte_spinlock_init(&pool->csl);
6058 TAILQ_INIT(&pool->counters[0]);
6059 TAILQ_INIT(&pool->counters[1]);
6060 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6061 rte_spinlock_lock(&cmng->pool_update_sl);
6062 pool->index = cmng->n_valid;
6063 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6065 rte_spinlock_unlock(&cmng->pool_update_sl);
6068 cmng->pools[pool->index] = pool;
6070 if (unlikely(fallback)) {
6071 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6073 if (base < cmng->min_id)
6074 cmng->min_id = base;
6075 if (base > cmng->max_id)
6076 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6077 cmng->last_pool_idx = pool->index;
6079 rte_spinlock_unlock(&cmng->pool_update_sl);
6084 * Prepare a new counter and/or a new counter pool.
6087 * Pointer to the Ethernet device structure.
6088 * @param[out] cnt_free
6089 * Where to put the pointer of a new counter.
6091 * Whether the pool is for counter that was allocated for aging.
6094 * The counter pool pointer and @p cnt_free is set on success,
6095 * NULL otherwise and rte_errno is set.
6097 static struct mlx5_flow_counter_pool *
6098 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6099 struct mlx5_flow_counter **cnt_free,
6102 struct mlx5_priv *priv = dev->data->dev_private;
6103 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6104 struct mlx5_flow_counter_pool *pool;
6105 struct mlx5_counters tmp_tq;
6106 struct mlx5_devx_obj *dcs = NULL;
6107 struct mlx5_flow_counter *cnt;
6108 enum mlx5_counter_type cnt_type =
6109 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6110 bool fallback = priv->sh->cmng.counter_fallback;
6114 /* bulk_bitmap must be 0 for single counter allocation. */
6115 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6118 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6120 pool = flow_dv_pool_create(dev, dcs, age);
6122 mlx5_devx_cmd_destroy(dcs);
6126 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6127 cnt = MLX5_POOL_GET_CNT(pool, i);
6129 cnt->dcs_when_free = dcs;
6133 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6135 rte_errno = ENODATA;
6138 pool = flow_dv_pool_create(dev, dcs, age);
6140 mlx5_devx_cmd_destroy(dcs);
6143 TAILQ_INIT(&tmp_tq);
6144 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6145 cnt = MLX5_POOL_GET_CNT(pool, i);
6147 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6149 rte_spinlock_lock(&cmng->csl[cnt_type]);
6150 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6151 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6152 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6153 (*cnt_free)->pool = pool;
6158 * Allocate a flow counter.
6161 * Pointer to the Ethernet device structure.
6163 * Whether the counter was allocated for aging.
6166 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6169 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6171 struct mlx5_priv *priv = dev->data->dev_private;
6172 struct mlx5_flow_counter_pool *pool = NULL;
6173 struct mlx5_flow_counter *cnt_free = NULL;
6174 bool fallback = priv->sh->cmng.counter_fallback;
6175 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6176 enum mlx5_counter_type cnt_type =
6177 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6180 if (!priv->sh->devx) {
6181 rte_errno = ENOTSUP;
6184 /* Get free counters from container. */
6185 rte_spinlock_lock(&cmng->csl[cnt_type]);
6186 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6188 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6189 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6190 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6192 pool = cnt_free->pool;
6194 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6195 /* Create a DV counter action only in the first time usage. */
6196 if (!cnt_free->action) {
6198 struct mlx5_devx_obj *dcs;
6202 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6203 dcs = pool->min_dcs;
6206 dcs = cnt_free->dcs_when_free;
6208 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6215 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6216 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6217 /* Update the counter reset values. */
6218 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6221 if (!fallback && !priv->sh->cmng.query_thread_on)
6222 /* Start the asynchronous batch query by the host thread. */
6223 mlx5_set_query_alarm(priv->sh);
6225 * When the count action isn't shared (by ID), shared_info field is
6226 * used for indirect action API's refcnt.
6227 * When the counter action is not shared neither by ID nor by indirect
6228 * action API, shared info must be 1.
6230 cnt_free->shared_info.refcnt = 1;
6234 cnt_free->pool = pool;
6236 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6237 rte_spinlock_lock(&cmng->csl[cnt_type]);
6238 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6239 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6245 * Get age param from counter index.
6248 * Pointer to the Ethernet device structure.
6249 * @param[in] counter
6250 * Index to the counter handler.
6253 * The aging parameter specified for the counter index.
6255 static struct mlx5_age_param*
6256 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6259 struct mlx5_flow_counter *cnt;
6260 struct mlx5_flow_counter_pool *pool = NULL;
6262 flow_dv_counter_get_by_idx(dev, counter, &pool);
6263 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6264 cnt = MLX5_POOL_GET_CNT(pool, counter);
6265 return MLX5_CNT_TO_AGE(cnt);
6269 * Remove a flow counter from aged counter list.
6272 * Pointer to the Ethernet device structure.
6273 * @param[in] counter
6274 * Index to the counter handler.
6276 * Pointer to the counter handler.
6279 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6280 uint32_t counter, struct mlx5_flow_counter *cnt)
6282 struct mlx5_age_info *age_info;
6283 struct mlx5_age_param *age_param;
6284 struct mlx5_priv *priv = dev->data->dev_private;
6285 uint16_t expected = AGE_CANDIDATE;
6287 age_info = GET_PORT_AGE_INFO(priv);
6288 age_param = flow_dv_counter_idx_get_age(dev, counter);
6289 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6290 AGE_FREE, false, __ATOMIC_RELAXED,
6291 __ATOMIC_RELAXED)) {
6293 * We need the lock even it is age timeout,
6294 * since counter may still in process.
6296 rte_spinlock_lock(&age_info->aged_sl);
6297 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6298 rte_spinlock_unlock(&age_info->aged_sl);
6299 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6304 * Release a flow counter.
6307 * Pointer to the Ethernet device structure.
6308 * @param[in] counter
6309 * Index to the counter handler.
6312 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6314 struct mlx5_priv *priv = dev->data->dev_private;
6315 struct mlx5_flow_counter_pool *pool = NULL;
6316 struct mlx5_flow_counter *cnt;
6317 enum mlx5_counter_type cnt_type;
6321 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6323 if (pool->is_aged) {
6324 flow_dv_counter_remove_from_age(dev, counter, cnt);
6327 * If the counter action is shared by indirect action API,
6328 * the atomic function reduces its references counter.
6329 * If after the reduction the action is still referenced, the
6330 * function returns here and does not release it.
6331 * When the counter action is not shared by
6332 * indirect action API, shared info is 1 before the reduction,
6333 * so this condition is failed and function doesn't return here.
6335 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6341 * Put the counter back to list to be updated in none fallback mode.
6342 * Currently, we are using two list alternately, while one is in query,
6343 * add the freed counter to the other list based on the pool query_gen
6344 * value. After query finishes, add counter the list to the global
6345 * container counter list. The list changes while query starts. In
6346 * this case, lock will not be needed as query callback and release
6347 * function both operate with the different list.
6349 if (!priv->sh->cmng.counter_fallback) {
6350 rte_spinlock_lock(&pool->csl);
6351 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6352 rte_spinlock_unlock(&pool->csl);
6354 cnt->dcs_when_free = cnt->dcs_when_active;
6355 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6356 MLX5_COUNTER_TYPE_ORIGIN;
6357 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6358 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6360 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6365 * Resize a meter id container.
6368 * Pointer to the Ethernet device structure.
6371 * 0 on success, otherwise negative errno value and rte_errno is set.
6374 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6376 struct mlx5_priv *priv = dev->data->dev_private;
6377 struct mlx5_aso_mtr_pools_mng *pools_mng =
6378 &priv->sh->mtrmng->pools_mng;
6379 void *old_pools = pools_mng->pools;
6380 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6381 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6382 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6389 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6394 memcpy(pools, old_pools, pools_mng->n *
6395 sizeof(struct mlx5_aso_mtr_pool *));
6396 pools_mng->n = resize;
6397 pools_mng->pools = pools;
6399 mlx5_free(old_pools);
6404 * Prepare a new meter and/or a new meter pool.
6407 * Pointer to the Ethernet device structure.
6408 * @param[out] mtr_free
6409 * Where to put the pointer of a new meter.g.
6412 * The meter pool pointer and @mtr_free is set on success,
6413 * NULL otherwise and rte_errno is set.
6415 static struct mlx5_aso_mtr_pool *
6416 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6418 struct mlx5_priv *priv = dev->data->dev_private;
6419 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6420 struct mlx5_aso_mtr_pool *pool = NULL;
6421 struct mlx5_devx_obj *dcs = NULL;
6423 uint32_t log_obj_size;
6425 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6426 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6427 priv->sh->cdev->pdn,
6430 rte_errno = ENODATA;
6433 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6436 claim_zero(mlx5_devx_cmd_destroy(dcs));
6439 pool->devx_obj = dcs;
6440 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6441 pool->index = pools_mng->n_valid;
6442 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6444 claim_zero(mlx5_devx_cmd_destroy(dcs));
6445 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6448 pools_mng->pools[pool->index] = pool;
6449 pools_mng->n_valid++;
6450 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6451 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6452 pool->mtrs[i].offset = i;
6453 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6455 pool->mtrs[0].offset = 0;
6456 *mtr_free = &pool->mtrs[0];
6461 * Release a flow meter into pool.
6464 * Pointer to the Ethernet device structure.
6465 * @param[in] mtr_idx
6466 * Index to aso flow meter.
6469 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6471 struct mlx5_priv *priv = dev->data->dev_private;
6472 struct mlx5_aso_mtr_pools_mng *pools_mng =
6473 &priv->sh->mtrmng->pools_mng;
6474 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6476 MLX5_ASSERT(aso_mtr);
6477 rte_spinlock_lock(&pools_mng->mtrsl);
6478 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6479 aso_mtr->state = ASO_METER_FREE;
6480 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6481 rte_spinlock_unlock(&pools_mng->mtrsl);
6485 * Allocate a aso flow meter.
6488 * Pointer to the Ethernet device structure.
6491 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6494 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6496 struct mlx5_priv *priv = dev->data->dev_private;
6497 struct mlx5_aso_mtr *mtr_free = NULL;
6498 struct mlx5_aso_mtr_pools_mng *pools_mng =
6499 &priv->sh->mtrmng->pools_mng;
6500 struct mlx5_aso_mtr_pool *pool;
6501 uint32_t mtr_idx = 0;
6503 if (!priv->sh->devx) {
6504 rte_errno = ENOTSUP;
6507 /* Allocate the flow meter memory. */
6508 /* Get free meters from management. */
6509 rte_spinlock_lock(&pools_mng->mtrsl);
6510 mtr_free = LIST_FIRST(&pools_mng->meters);
6512 LIST_REMOVE(mtr_free, next);
6513 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6514 rte_spinlock_unlock(&pools_mng->mtrsl);
6517 mtr_free->state = ASO_METER_WAIT;
6518 rte_spinlock_unlock(&pools_mng->mtrsl);
6519 pool = container_of(mtr_free,
6520 struct mlx5_aso_mtr_pool,
6521 mtrs[mtr_free->offset]);
6522 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6523 if (!mtr_free->fm.meter_action) {
6524 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6525 struct rte_flow_error error;
6528 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6529 mtr_free->fm.meter_action =
6530 mlx5_glue->dv_create_flow_action_aso
6531 (priv->sh->rx_domain,
6532 pool->devx_obj->obj,
6534 (1 << MLX5_FLOW_COLOR_GREEN),
6536 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6537 if (!mtr_free->fm.meter_action) {
6538 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6546 * Verify the @p attributes will be correctly understood by the NIC and store
6547 * them in the @p flow if everything is correct.
6550 * Pointer to dev struct.
6551 * @param[in] attributes
6552 * Pointer to flow attributes
6553 * @param[in] external
6554 * This flow rule is created by request external to PMD.
6556 * Pointer to error structure.
6559 * - 0 on success and non root table.
6560 * - 1 on success and root table.
6561 * - a negative errno value otherwise and rte_errno is set.
6564 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6565 const struct mlx5_flow_tunnel *tunnel,
6566 const struct rte_flow_attr *attributes,
6567 const struct flow_grp_info *grp_info,
6568 struct rte_flow_error *error)
6570 struct mlx5_priv *priv = dev->data->dev_private;
6571 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6574 #ifndef HAVE_MLX5DV_DR
6575 RTE_SET_USED(tunnel);
6576 RTE_SET_USED(grp_info);
6577 if (attributes->group)
6578 return rte_flow_error_set(error, ENOTSUP,
6579 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6581 "groups are not supported");
6585 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6590 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6592 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6593 attributes->priority > lowest_priority)
6594 return rte_flow_error_set(error, ENOTSUP,
6595 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6597 "priority out of range");
6598 if (attributes->transfer) {
6599 if (!priv->config.dv_esw_en)
6600 return rte_flow_error_set
6602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6603 "E-Switch dr is not supported");
6604 if (!(priv->representor || priv->master))
6605 return rte_flow_error_set
6606 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6607 NULL, "E-Switch configuration can only be"
6608 " done by a master or a representor device");
6609 if (attributes->egress)
6610 return rte_flow_error_set
6612 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6613 "egress is not supported");
6615 if (!(attributes->egress ^ attributes->ingress))
6616 return rte_flow_error_set(error, ENOTSUP,
6617 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6618 "must specify exactly one of "
6619 "ingress or egress");
6624 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6625 int64_t pattern_flags, uint64_t l3_flags,
6626 uint64_t l4_flags, uint64_t ip4_flag,
6627 struct rte_flow_error *error)
6629 if (mask->l3_ok && !(pattern_flags & l3_flags))
6630 return rte_flow_error_set(error, EINVAL,
6631 RTE_FLOW_ERROR_TYPE_ITEM,
6632 NULL, "missing L3 protocol");
6634 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6635 return rte_flow_error_set(error, EINVAL,
6636 RTE_FLOW_ERROR_TYPE_ITEM,
6637 NULL, "missing IPv4 protocol");
6639 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6640 return rte_flow_error_set(error, EINVAL,
6641 RTE_FLOW_ERROR_TYPE_ITEM,
6642 NULL, "missing L4 protocol");
6648 flow_dv_validate_item_integrity_post(const struct
6649 rte_flow_item *integrity_items[2],
6650 int64_t pattern_flags,
6651 struct rte_flow_error *error)
6653 const struct rte_flow_item_integrity *mask;
6656 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6657 mask = (typeof(mask))integrity_items[0]->mask;
6658 ret = validate_integrity_bits(mask, pattern_flags,
6659 MLX5_FLOW_LAYER_OUTER_L3,
6660 MLX5_FLOW_LAYER_OUTER_L4,
6661 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6666 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6667 mask = (typeof(mask))integrity_items[1]->mask;
6668 ret = validate_integrity_bits(mask, pattern_flags,
6669 MLX5_FLOW_LAYER_INNER_L3,
6670 MLX5_FLOW_LAYER_INNER_L4,
6671 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6680 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6681 const struct rte_flow_item *integrity_item,
6682 uint64_t pattern_flags, uint64_t *last_item,
6683 const struct rte_flow_item *integrity_items[2],
6684 struct rte_flow_error *error)
6686 struct mlx5_priv *priv = dev->data->dev_private;
6687 const struct rte_flow_item_integrity *mask = (typeof(mask))
6688 integrity_item->mask;
6689 const struct rte_flow_item_integrity *spec = (typeof(spec))
6690 integrity_item->spec;
6692 if (!priv->config.hca_attr.pkt_integrity_match)
6693 return rte_flow_error_set(error, ENOTSUP,
6694 RTE_FLOW_ERROR_TYPE_ITEM,
6696 "packet integrity integrity_item not supported");
6698 return rte_flow_error_set(error, ENOTSUP,
6699 RTE_FLOW_ERROR_TYPE_ITEM,
6701 "no spec for integrity item");
6703 mask = &rte_flow_item_integrity_mask;
6704 if (!mlx5_validate_integrity_item(mask))
6705 return rte_flow_error_set(error, ENOTSUP,
6706 RTE_FLOW_ERROR_TYPE_ITEM,
6708 "unsupported integrity filter");
6709 if (spec->level > 1) {
6710 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6711 return rte_flow_error_set
6713 RTE_FLOW_ERROR_TYPE_ITEM,
6714 NULL, "multiple inner integrity items not supported");
6715 integrity_items[1] = integrity_item;
6716 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6718 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6719 return rte_flow_error_set
6721 RTE_FLOW_ERROR_TYPE_ITEM,
6722 NULL, "multiple outer integrity items not supported");
6723 integrity_items[0] = integrity_item;
6724 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6730 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6731 const struct rte_flow_item *item,
6732 uint64_t item_flags,
6733 uint64_t *last_item,
6735 struct rte_flow_error *error)
6737 const struct rte_flow_item_flex *flow_spec = item->spec;
6738 const struct rte_flow_item_flex *flow_mask = item->mask;
6739 struct mlx5_flex_item *flex;
6742 return rte_flow_error_set(error, EINVAL,
6743 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6744 "flex flow item spec cannot be NULL");
6746 return rte_flow_error_set(error, EINVAL,
6747 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6748 "flex flow item mask cannot be NULL");
6750 return rte_flow_error_set(error, ENOTSUP,
6751 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6752 "flex flow item last not supported");
6753 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6754 return rte_flow_error_set(error, EINVAL,
6755 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6756 "invalid flex flow item handle");
6757 flex = (struct mlx5_flex_item *)flow_spec->handle;
6758 switch (flex->tunnel_mode) {
6759 case FLEX_TUNNEL_MODE_SINGLE:
6761 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6762 rte_flow_error_set(error, EINVAL,
6763 RTE_FLOW_ERROR_TYPE_ITEM,
6764 NULL, "multiple flex items not supported");
6766 case FLEX_TUNNEL_MODE_OUTER:
6768 rte_flow_error_set(error, EINVAL,
6769 RTE_FLOW_ERROR_TYPE_ITEM,
6770 NULL, "inner flex item was not configured");
6771 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6772 rte_flow_error_set(error, ENOTSUP,
6773 RTE_FLOW_ERROR_TYPE_ITEM,
6774 NULL, "multiple flex items not supported");
6776 case FLEX_TUNNEL_MODE_INNER:
6778 rte_flow_error_set(error, EINVAL,
6779 RTE_FLOW_ERROR_TYPE_ITEM,
6780 NULL, "outer flex item was not configured");
6781 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6782 rte_flow_error_set(error, EINVAL,
6783 RTE_FLOW_ERROR_TYPE_ITEM,
6784 NULL, "multiple flex items not supported");
6786 case FLEX_TUNNEL_MODE_MULTI:
6787 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6788 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6789 rte_flow_error_set(error, EINVAL,
6790 RTE_FLOW_ERROR_TYPE_ITEM,
6791 NULL, "multiple flex items not supported");
6794 case FLEX_TUNNEL_MODE_TUNNEL:
6795 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6796 rte_flow_error_set(error, EINVAL,
6797 RTE_FLOW_ERROR_TYPE_ITEM,
6798 NULL, "multiple flex tunnel items not supported");
6801 rte_flow_error_set(error, EINVAL,
6802 RTE_FLOW_ERROR_TYPE_ITEM,
6803 NULL, "invalid flex item configuration");
6805 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6806 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6807 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6812 * Internal validation function. For validating both actions and items.
6815 * Pointer to the rte_eth_dev structure.
6817 * Pointer to the flow attributes.
6819 * Pointer to the list of items.
6820 * @param[in] actions
6821 * Pointer to the list of actions.
6822 * @param[in] external
6823 * This flow rule is created by request external to PMD.
6824 * @param[in] hairpin
6825 * Number of hairpin TX actions, 0 means classic flow.
6827 * Pointer to the error structure.
6830 * 0 on success, a negative errno value otherwise and rte_errno is set.
6833 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6834 const struct rte_flow_item items[],
6835 const struct rte_flow_action actions[],
6836 bool external, int hairpin, struct rte_flow_error *error)
6839 uint64_t action_flags = 0;
6840 uint64_t item_flags = 0;
6841 uint64_t last_item = 0;
6842 uint8_t next_protocol = 0xff;
6843 uint16_t ether_type = 0;
6845 uint8_t item_ipv6_proto = 0;
6846 int fdb_mirror_limit = 0;
6847 int modify_after_mirror = 0;
6848 const struct rte_flow_item *geneve_item = NULL;
6849 const struct rte_flow_item *gre_item = NULL;
6850 const struct rte_flow_item *gtp_item = NULL;
6851 const struct rte_flow_action_raw_decap *decap;
6852 const struct rte_flow_action_raw_encap *encap;
6853 const struct rte_flow_action_rss *rss = NULL;
6854 const struct rte_flow_action_rss *sample_rss = NULL;
6855 const struct rte_flow_action_count *sample_count = NULL;
6856 const struct rte_flow_item_tcp nic_tcp_mask = {
6859 .src_port = RTE_BE16(UINT16_MAX),
6860 .dst_port = RTE_BE16(UINT16_MAX),
6863 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6866 "\xff\xff\xff\xff\xff\xff\xff\xff"
6867 "\xff\xff\xff\xff\xff\xff\xff\xff",
6869 "\xff\xff\xff\xff\xff\xff\xff\xff"
6870 "\xff\xff\xff\xff\xff\xff\xff\xff",
6871 .vtc_flow = RTE_BE32(0xffffffff),
6877 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6881 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6885 .dummy[0] = 0xffffffff,
6888 struct mlx5_priv *priv = dev->data->dev_private;
6889 struct mlx5_dev_config *dev_conf = &priv->config;
6890 uint16_t queue_index = 0xFFFF;
6891 const struct rte_flow_item_vlan *vlan_m = NULL;
6892 uint32_t rw_act_num = 0;
6894 const struct mlx5_flow_tunnel *tunnel;
6895 enum mlx5_tof_rule_type tof_rule_type;
6896 struct flow_grp_info grp_info = {
6897 .external = !!external,
6898 .transfer = !!attr->transfer,
6899 .fdb_def_rule = !!priv->fdb_def_rule,
6900 .std_tbl_fix = true,
6902 const struct rte_eth_hairpin_conf *conf;
6903 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6904 const struct rte_flow_item *port_id_item = NULL;
6905 bool def_policy = false;
6906 uint16_t udp_dport = 0;
6910 tunnel = is_tunnel_offload_active(dev) ?
6911 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6913 if (!priv->config.dv_flow_en)
6914 return rte_flow_error_set
6916 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6917 NULL, "tunnel offload requires DV flow interface");
6918 if (priv->representor)
6919 return rte_flow_error_set
6921 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6922 NULL, "decap not supported for VF representor");
6923 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6924 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6925 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6926 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6927 MLX5_FLOW_ACTION_DECAP;
6928 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6929 (dev, attr, tunnel, tof_rule_type);
6931 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6934 is_root = (uint64_t)ret;
6935 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6936 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6937 int type = items->type;
6939 if (!mlx5_flow_os_item_supported(type))
6940 return rte_flow_error_set(error, ENOTSUP,
6941 RTE_FLOW_ERROR_TYPE_ITEM,
6942 NULL, "item not supported");
6944 case RTE_FLOW_ITEM_TYPE_VOID:
6946 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6947 ret = flow_dv_validate_item_port_id
6948 (dev, items, attr, item_flags, error);
6951 last_item = MLX5_FLOW_ITEM_PORT_ID;
6952 port_id_item = items;
6954 case RTE_FLOW_ITEM_TYPE_ETH:
6955 ret = mlx5_flow_validate_item_eth(items, item_flags,
6959 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6960 MLX5_FLOW_LAYER_OUTER_L2;
6961 if (items->mask != NULL && items->spec != NULL) {
6963 ((const struct rte_flow_item_eth *)
6966 ((const struct rte_flow_item_eth *)
6968 ether_type = rte_be_to_cpu_16(ether_type);
6973 case RTE_FLOW_ITEM_TYPE_VLAN:
6974 ret = flow_dv_validate_item_vlan(items, item_flags,
6978 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6979 MLX5_FLOW_LAYER_OUTER_VLAN;
6980 if (items->mask != NULL && items->spec != NULL) {
6982 ((const struct rte_flow_item_vlan *)
6983 items->spec)->inner_type;
6985 ((const struct rte_flow_item_vlan *)
6986 items->mask)->inner_type;
6987 ether_type = rte_be_to_cpu_16(ether_type);
6991 /* Store outer VLAN mask for of_push_vlan action. */
6993 vlan_m = items->mask;
6995 case RTE_FLOW_ITEM_TYPE_IPV4:
6996 mlx5_flow_tunnel_ip_check(items, next_protocol,
6997 &item_flags, &tunnel);
6998 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6999 last_item, ether_type,
7003 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7004 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7005 if (items->mask != NULL &&
7006 ((const struct rte_flow_item_ipv4 *)
7007 items->mask)->hdr.next_proto_id) {
7009 ((const struct rte_flow_item_ipv4 *)
7010 (items->spec))->hdr.next_proto_id;
7012 ((const struct rte_flow_item_ipv4 *)
7013 (items->mask))->hdr.next_proto_id;
7015 /* Reset for inner layer. */
7016 next_protocol = 0xff;
7019 case RTE_FLOW_ITEM_TYPE_IPV6:
7020 mlx5_flow_tunnel_ip_check(items, next_protocol,
7021 &item_flags, &tunnel);
7022 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7029 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7030 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7031 if (items->mask != NULL &&
7032 ((const struct rte_flow_item_ipv6 *)
7033 items->mask)->hdr.proto) {
7035 ((const struct rte_flow_item_ipv6 *)
7036 items->spec)->hdr.proto;
7038 ((const struct rte_flow_item_ipv6 *)
7039 items->spec)->hdr.proto;
7041 ((const struct rte_flow_item_ipv6 *)
7042 items->mask)->hdr.proto;
7044 /* Reset for inner layer. */
7045 next_protocol = 0xff;
7048 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7049 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7054 last_item = tunnel ?
7055 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7056 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7057 if (items->mask != NULL &&
7058 ((const struct rte_flow_item_ipv6_frag_ext *)
7059 items->mask)->hdr.next_header) {
7061 ((const struct rte_flow_item_ipv6_frag_ext *)
7062 items->spec)->hdr.next_header;
7064 ((const struct rte_flow_item_ipv6_frag_ext *)
7065 items->mask)->hdr.next_header;
7067 /* Reset for inner layer. */
7068 next_protocol = 0xff;
7071 case RTE_FLOW_ITEM_TYPE_TCP:
7072 ret = mlx5_flow_validate_item_tcp
7079 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7080 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7082 case RTE_FLOW_ITEM_TYPE_UDP:
7083 ret = mlx5_flow_validate_item_udp(items, item_flags,
7086 const struct rte_flow_item_udp *spec = items->spec;
7087 const struct rte_flow_item_udp *mask = items->mask;
7089 mask = &rte_flow_item_udp_mask;
7091 udp_dport = rte_be_to_cpu_16
7092 (spec->hdr.dst_port &
7093 mask->hdr.dst_port);
7096 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7097 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7099 case RTE_FLOW_ITEM_TYPE_GRE:
7100 ret = mlx5_flow_validate_item_gre(items, item_flags,
7101 next_protocol, error);
7105 last_item = MLX5_FLOW_LAYER_GRE;
7107 case RTE_FLOW_ITEM_TYPE_NVGRE:
7108 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7113 last_item = MLX5_FLOW_LAYER_NVGRE;
7115 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7116 ret = mlx5_flow_validate_item_gre_key
7117 (items, item_flags, gre_item, error);
7120 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7122 case RTE_FLOW_ITEM_TYPE_VXLAN:
7123 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7128 last_item = MLX5_FLOW_LAYER_VXLAN;
7130 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7131 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7136 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7138 case RTE_FLOW_ITEM_TYPE_GENEVE:
7139 ret = mlx5_flow_validate_item_geneve(items,
7144 geneve_item = items;
7145 last_item = MLX5_FLOW_LAYER_GENEVE;
7147 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7148 ret = mlx5_flow_validate_item_geneve_opt(items,
7155 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7157 case RTE_FLOW_ITEM_TYPE_MPLS:
7158 ret = mlx5_flow_validate_item_mpls(dev, items,
7163 last_item = MLX5_FLOW_LAYER_MPLS;
7166 case RTE_FLOW_ITEM_TYPE_MARK:
7167 ret = flow_dv_validate_item_mark(dev, items, attr,
7171 last_item = MLX5_FLOW_ITEM_MARK;
7173 case RTE_FLOW_ITEM_TYPE_META:
7174 ret = flow_dv_validate_item_meta(dev, items, attr,
7178 last_item = MLX5_FLOW_ITEM_METADATA;
7180 case RTE_FLOW_ITEM_TYPE_ICMP:
7181 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7186 last_item = MLX5_FLOW_LAYER_ICMP;
7188 case RTE_FLOW_ITEM_TYPE_ICMP6:
7189 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7194 item_ipv6_proto = IPPROTO_ICMPV6;
7195 last_item = MLX5_FLOW_LAYER_ICMP6;
7197 case RTE_FLOW_ITEM_TYPE_TAG:
7198 ret = flow_dv_validate_item_tag(dev, items,
7202 last_item = MLX5_FLOW_ITEM_TAG;
7204 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7205 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7207 case RTE_FLOW_ITEM_TYPE_GTP:
7208 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7213 last_item = MLX5_FLOW_LAYER_GTP;
7215 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7216 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7221 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7223 case RTE_FLOW_ITEM_TYPE_ECPRI:
7224 /* Capacity will be checked in the translate stage. */
7225 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7232 last_item = MLX5_FLOW_LAYER_ECPRI;
7234 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7235 ret = flow_dv_validate_item_integrity(dev, items,
7243 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7244 ret = flow_dv_validate_item_aso_ct(dev, items,
7245 &item_flags, error);
7249 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7250 /* tunnel offload item was processed before
7251 * list it here as a supported type
7254 case RTE_FLOW_ITEM_TYPE_FLEX:
7255 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7257 tunnel != 0, error);
7262 return rte_flow_error_set(error, ENOTSUP,
7263 RTE_FLOW_ERROR_TYPE_ITEM,
7264 NULL, "item not supported");
7266 item_flags |= last_item;
7268 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7269 ret = flow_dv_validate_item_integrity_post(integrity_items,
7274 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7275 int type = actions->type;
7276 bool shared_count = false;
7278 if (!mlx5_flow_os_action_supported(type))
7279 return rte_flow_error_set(error, ENOTSUP,
7280 RTE_FLOW_ERROR_TYPE_ACTION,
7282 "action not supported");
7283 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7284 return rte_flow_error_set(error, ENOTSUP,
7285 RTE_FLOW_ERROR_TYPE_ACTION,
7286 actions, "too many actions");
7288 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7289 return rte_flow_error_set(error, ENOTSUP,
7290 RTE_FLOW_ERROR_TYPE_ACTION,
7291 NULL, "meter action with policy "
7292 "must be the last action");
7294 case RTE_FLOW_ACTION_TYPE_VOID:
7296 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7297 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7298 ret = flow_dv_validate_action_port_id(dev,
7305 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7308 case RTE_FLOW_ACTION_TYPE_FLAG:
7309 ret = flow_dv_validate_action_flag(dev, action_flags,
7313 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7314 /* Count all modify-header actions as one. */
7315 if (!(action_flags &
7316 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7318 action_flags |= MLX5_FLOW_ACTION_FLAG |
7319 MLX5_FLOW_ACTION_MARK_EXT;
7320 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7321 modify_after_mirror = 1;
7324 action_flags |= MLX5_FLOW_ACTION_FLAG;
7327 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7329 case RTE_FLOW_ACTION_TYPE_MARK:
7330 ret = flow_dv_validate_action_mark(dev, actions,
7335 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7336 /* Count all modify-header actions as one. */
7337 if (!(action_flags &
7338 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7340 action_flags |= MLX5_FLOW_ACTION_MARK |
7341 MLX5_FLOW_ACTION_MARK_EXT;
7342 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7343 modify_after_mirror = 1;
7345 action_flags |= MLX5_FLOW_ACTION_MARK;
7348 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7350 case RTE_FLOW_ACTION_TYPE_SET_META:
7351 ret = flow_dv_validate_action_set_meta(dev, actions,
7356 /* Count all modify-header actions as one action. */
7357 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7359 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7360 modify_after_mirror = 1;
7361 action_flags |= MLX5_FLOW_ACTION_SET_META;
7362 rw_act_num += MLX5_ACT_NUM_SET_META;
7364 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7365 ret = flow_dv_validate_action_set_tag(dev, actions,
7370 /* Count all modify-header actions as one action. */
7371 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7373 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7374 modify_after_mirror = 1;
7375 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7376 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7378 case RTE_FLOW_ACTION_TYPE_DROP:
7379 ret = mlx5_flow_validate_action_drop(action_flags,
7383 action_flags |= MLX5_FLOW_ACTION_DROP;
7386 case RTE_FLOW_ACTION_TYPE_QUEUE:
7387 ret = mlx5_flow_validate_action_queue(actions,
7392 queue_index = ((const struct rte_flow_action_queue *)
7393 (actions->conf))->index;
7394 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7397 case RTE_FLOW_ACTION_TYPE_RSS:
7398 rss = actions->conf;
7399 ret = mlx5_flow_validate_action_rss(actions,
7405 if (rss && sample_rss &&
7406 (sample_rss->level != rss->level ||
7407 sample_rss->types != rss->types))
7408 return rte_flow_error_set(error, ENOTSUP,
7409 RTE_FLOW_ERROR_TYPE_ACTION,
7411 "Can't use the different RSS types "
7412 "or level in the same flow");
7413 if (rss != NULL && rss->queue_num)
7414 queue_index = rss->queue[0];
7415 action_flags |= MLX5_FLOW_ACTION_RSS;
7418 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7420 mlx5_flow_validate_action_default_miss(action_flags,
7424 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7427 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7428 shared_count = true;
7430 case RTE_FLOW_ACTION_TYPE_COUNT:
7431 ret = flow_dv_validate_action_count(dev, shared_count,
7436 action_flags |= MLX5_FLOW_ACTION_COUNT;
7439 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7440 if (flow_dv_validate_action_pop_vlan(dev,
7446 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7447 modify_after_mirror = 1;
7448 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7451 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7452 ret = flow_dv_validate_action_push_vlan(dev,
7459 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7460 modify_after_mirror = 1;
7461 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7464 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7465 ret = flow_dv_validate_action_set_vlan_pcp
7466 (action_flags, actions, error);
7469 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7470 modify_after_mirror = 1;
7471 /* Count PCP with push_vlan command. */
7472 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7474 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7475 ret = flow_dv_validate_action_set_vlan_vid
7476 (item_flags, action_flags,
7480 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7481 modify_after_mirror = 1;
7482 /* Count VID with push_vlan command. */
7483 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7484 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7486 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7487 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7488 ret = flow_dv_validate_action_l2_encap(dev,
7494 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7497 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7498 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7499 ret = flow_dv_validate_action_decap(dev, action_flags,
7500 actions, item_flags,
7504 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7505 modify_after_mirror = 1;
7506 action_flags |= MLX5_FLOW_ACTION_DECAP;
7509 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7510 ret = flow_dv_validate_action_raw_encap_decap
7511 (dev, NULL, actions->conf, attr, &action_flags,
7512 &actions_n, actions, item_flags, error);
7516 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7517 decap = actions->conf;
7518 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7520 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7524 encap = actions->conf;
7526 ret = flow_dv_validate_action_raw_encap_decap
7528 decap ? decap : &empty_decap, encap,
7529 attr, &action_flags, &actions_n,
7530 actions, item_flags, error);
7533 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7534 (action_flags & MLX5_FLOW_ACTION_DECAP))
7535 modify_after_mirror = 1;
7537 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7538 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7539 ret = flow_dv_validate_action_modify_mac(action_flags,
7545 /* Count all modify-header actions as one action. */
7546 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7548 action_flags |= actions->type ==
7549 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7550 MLX5_FLOW_ACTION_SET_MAC_SRC :
7551 MLX5_FLOW_ACTION_SET_MAC_DST;
7552 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7553 modify_after_mirror = 1;
7555 * Even if the source and destination MAC addresses have
7556 * overlap in the header with 4B alignment, the convert
7557 * function will handle them separately and 4 SW actions
7558 * will be created. And 2 actions will be added each
7559 * time no matter how many bytes of address will be set.
7561 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7563 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7564 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7565 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7571 /* Count all modify-header actions as one action. */
7572 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7574 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7575 modify_after_mirror = 1;
7576 action_flags |= actions->type ==
7577 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7578 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7579 MLX5_FLOW_ACTION_SET_IPV4_DST;
7580 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7582 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7583 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7584 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7590 if (item_ipv6_proto == IPPROTO_ICMPV6)
7591 return rte_flow_error_set(error, ENOTSUP,
7592 RTE_FLOW_ERROR_TYPE_ACTION,
7594 "Can't change header "
7595 "with ICMPv6 proto");
7596 /* Count all modify-header actions as one action. */
7597 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7599 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7600 modify_after_mirror = 1;
7601 action_flags |= actions->type ==
7602 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7603 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7604 MLX5_FLOW_ACTION_SET_IPV6_DST;
7605 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7607 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7608 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7609 ret = flow_dv_validate_action_modify_tp(action_flags,
7615 /* Count all modify-header actions as one action. */
7616 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7618 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7619 modify_after_mirror = 1;
7620 action_flags |= actions->type ==
7621 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7622 MLX5_FLOW_ACTION_SET_TP_SRC :
7623 MLX5_FLOW_ACTION_SET_TP_DST;
7624 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7626 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7627 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7628 ret = flow_dv_validate_action_modify_ttl(action_flags,
7634 /* Count all modify-header actions as one action. */
7635 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7637 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7638 modify_after_mirror = 1;
7639 action_flags |= actions->type ==
7640 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7641 MLX5_FLOW_ACTION_SET_TTL :
7642 MLX5_FLOW_ACTION_DEC_TTL;
7643 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7645 case RTE_FLOW_ACTION_TYPE_JUMP:
7646 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7652 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7654 return rte_flow_error_set(error, EINVAL,
7655 RTE_FLOW_ERROR_TYPE_ACTION,
7657 "sample and jump action combination is not supported");
7659 action_flags |= MLX5_FLOW_ACTION_JUMP;
7661 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7662 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7663 ret = flow_dv_validate_action_modify_tcp_seq
7670 /* Count all modify-header actions as one action. */
7671 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7673 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7674 modify_after_mirror = 1;
7675 action_flags |= actions->type ==
7676 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7677 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7678 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7679 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7681 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7682 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7683 ret = flow_dv_validate_action_modify_tcp_ack
7690 /* Count all modify-header actions as one action. */
7691 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7693 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7694 modify_after_mirror = 1;
7695 action_flags |= actions->type ==
7696 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7697 MLX5_FLOW_ACTION_INC_TCP_ACK :
7698 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7699 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7701 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7703 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7704 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7705 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7707 case RTE_FLOW_ACTION_TYPE_METER:
7708 ret = mlx5_flow_validate_action_meter(dev,
7717 action_flags |= MLX5_FLOW_ACTION_METER;
7720 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7722 /* Meter action will add one more TAG action. */
7723 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7725 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7726 if (!attr->transfer && !attr->group)
7727 return rte_flow_error_set(error, ENOTSUP,
7728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7730 "Shared ASO age action is not supported for group 0");
7731 if (action_flags & MLX5_FLOW_ACTION_AGE)
7732 return rte_flow_error_set
7734 RTE_FLOW_ERROR_TYPE_ACTION,
7736 "duplicate age actions set");
7737 action_flags |= MLX5_FLOW_ACTION_AGE;
7740 case RTE_FLOW_ACTION_TYPE_AGE:
7741 ret = flow_dv_validate_action_age(action_flags,
7747 * Validate the regular AGE action (using counter)
7748 * mutual exclusion with share counter actions.
7750 if (!priv->sh->flow_hit_aso_en) {
7752 return rte_flow_error_set
7754 RTE_FLOW_ERROR_TYPE_ACTION,
7756 "old age and shared count combination is not supported");
7758 return rte_flow_error_set
7760 RTE_FLOW_ERROR_TYPE_ACTION,
7762 "old age action and count must be in the same sub flow");
7764 action_flags |= MLX5_FLOW_ACTION_AGE;
7767 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7768 ret = flow_dv_validate_action_modify_ipv4_dscp
7775 /* Count all modify-header actions as one action. */
7776 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7778 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7779 modify_after_mirror = 1;
7780 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7781 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7783 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7784 ret = flow_dv_validate_action_modify_ipv6_dscp
7791 /* Count all modify-header actions as one action. */
7792 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7794 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7795 modify_after_mirror = 1;
7796 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7797 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7799 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7800 ret = flow_dv_validate_action_sample(&action_flags,
7809 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7812 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7813 ret = flow_dv_validate_action_modify_field(dev,
7820 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7821 modify_after_mirror = 1;
7822 /* Count all modify-header actions as one action. */
7823 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7825 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7828 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7829 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7834 action_flags |= MLX5_FLOW_ACTION_CT;
7836 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7837 /* tunnel offload action was processed before
7838 * list it here as a supported type
7842 return rte_flow_error_set(error, ENOTSUP,
7843 RTE_FLOW_ERROR_TYPE_ACTION,
7845 "action not supported");
7849 * Validate actions in flow rules
7850 * - Explicit decap action is prohibited by the tunnel offload API.
7851 * - Drop action in tunnel steer rule is prohibited by the API.
7852 * - Application cannot use MARK action because it's value can mask
7853 * tunnel default miss nitification.
7854 * - JUMP in tunnel match rule has no support in current PMD
7856 * - TAG & META are reserved for future uses.
7858 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7859 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7860 MLX5_FLOW_ACTION_MARK |
7861 MLX5_FLOW_ACTION_SET_TAG |
7862 MLX5_FLOW_ACTION_SET_META |
7863 MLX5_FLOW_ACTION_DROP;
7865 if (action_flags & bad_actions_mask)
7866 return rte_flow_error_set
7868 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7869 "Invalid RTE action in tunnel "
7871 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7872 return rte_flow_error_set
7874 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7875 "tunnel set decap rule must terminate "
7878 return rte_flow_error_set
7880 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7881 "tunnel flows for ingress traffic only");
7883 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7884 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7885 MLX5_FLOW_ACTION_MARK |
7886 MLX5_FLOW_ACTION_SET_TAG |
7887 MLX5_FLOW_ACTION_SET_META;
7889 if (action_flags & bad_actions_mask)
7890 return rte_flow_error_set
7892 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7893 "Invalid RTE action in tunnel "
7897 * Validate the drop action mutual exclusion with other actions.
7898 * Drop action is mutually-exclusive with any other action, except for
7900 * Drop action compatibility with tunnel offload was already validated.
7902 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7903 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7904 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7905 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7906 return rte_flow_error_set(error, EINVAL,
7907 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7908 "Drop action is mutually-exclusive "
7909 "with any other action, except for "
7911 /* Eswitch has few restrictions on using items and actions */
7912 if (attr->transfer) {
7913 if (!mlx5_flow_ext_mreg_supported(dev) &&
7914 action_flags & MLX5_FLOW_ACTION_FLAG)
7915 return rte_flow_error_set(error, ENOTSUP,
7916 RTE_FLOW_ERROR_TYPE_ACTION,
7918 "unsupported action FLAG");
7919 if (!mlx5_flow_ext_mreg_supported(dev) &&
7920 action_flags & MLX5_FLOW_ACTION_MARK)
7921 return rte_flow_error_set(error, ENOTSUP,
7922 RTE_FLOW_ERROR_TYPE_ACTION,
7924 "unsupported action MARK");
7925 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7926 return rte_flow_error_set(error, ENOTSUP,
7927 RTE_FLOW_ERROR_TYPE_ACTION,
7929 "unsupported action QUEUE");
7930 if (action_flags & MLX5_FLOW_ACTION_RSS)
7931 return rte_flow_error_set(error, ENOTSUP,
7932 RTE_FLOW_ERROR_TYPE_ACTION,
7934 "unsupported action RSS");
7935 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7936 return rte_flow_error_set(error, EINVAL,
7937 RTE_FLOW_ERROR_TYPE_ACTION,
7939 "no fate action is found");
7941 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7942 return rte_flow_error_set(error, EINVAL,
7943 RTE_FLOW_ERROR_TYPE_ACTION,
7945 "no fate action is found");
7948 * Continue validation for Xcap and VLAN actions.
7949 * If hairpin is working in explicit TX rule mode, there is no actions
7950 * splitting and the validation of hairpin ingress flow should be the
7951 * same as other standard flows.
7953 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7954 MLX5_FLOW_VLAN_ACTIONS)) &&
7955 (queue_index == 0xFFFF ||
7956 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7957 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7958 conf->tx_explicit != 0))) {
7959 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7960 MLX5_FLOW_XCAP_ACTIONS)
7961 return rte_flow_error_set(error, ENOTSUP,
7962 RTE_FLOW_ERROR_TYPE_ACTION,
7963 NULL, "encap and decap "
7964 "combination aren't supported");
7965 if (!attr->transfer && attr->ingress) {
7966 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7967 return rte_flow_error_set
7969 RTE_FLOW_ERROR_TYPE_ACTION,
7970 NULL, "encap is not supported"
7971 " for ingress traffic");
7972 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7973 return rte_flow_error_set
7975 RTE_FLOW_ERROR_TYPE_ACTION,
7976 NULL, "push VLAN action not "
7977 "supported for ingress");
7978 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7979 MLX5_FLOW_VLAN_ACTIONS)
7980 return rte_flow_error_set
7982 RTE_FLOW_ERROR_TYPE_ACTION,
7983 NULL, "no support for "
7984 "multiple VLAN actions");
7987 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7988 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7989 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7991 return rte_flow_error_set
7993 RTE_FLOW_ERROR_TYPE_ACTION,
7994 NULL, "fate action not supported for "
7995 "meter with policy");
7997 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7998 return rte_flow_error_set
8000 RTE_FLOW_ERROR_TYPE_ACTION,
8001 NULL, "modify header action in egress "
8002 "cannot be done before meter action");
8003 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8004 return rte_flow_error_set
8006 RTE_FLOW_ERROR_TYPE_ACTION,
8007 NULL, "encap action in egress "
8008 "cannot be done before meter action");
8009 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8010 return rte_flow_error_set
8012 RTE_FLOW_ERROR_TYPE_ACTION,
8013 NULL, "push vlan action in egress "
8014 "cannot be done before meter action");
8018 * Hairpin flow will add one more TAG action in TX implicit mode.
8019 * In TX explicit mode, there will be no hairpin flow ID.
8022 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8023 /* extra metadata enabled: one more TAG action will be add. */
8024 if (dev_conf->dv_flow_en &&
8025 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8026 mlx5_flow_ext_mreg_supported(dev))
8027 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8029 flow_dv_modify_hdr_action_max(dev, is_root)) {
8030 return rte_flow_error_set(error, ENOTSUP,
8031 RTE_FLOW_ERROR_TYPE_ACTION,
8032 NULL, "too many header modify"
8033 " actions to support");
8035 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8036 if (fdb_mirror_limit && modify_after_mirror)
8037 return rte_flow_error_set(error, EINVAL,
8038 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8039 "sample before modify action is not supported");
8044 * Internal preparation function. Allocates the DV flow size,
8045 * this size is constant.
8048 * Pointer to the rte_eth_dev structure.
8050 * Pointer to the flow attributes.
8052 * Pointer to the list of items.
8053 * @param[in] actions
8054 * Pointer to the list of actions.
8056 * Pointer to the error structure.
8059 * Pointer to mlx5_flow object on success,
8060 * otherwise NULL and rte_errno is set.
8062 static struct mlx5_flow *
8063 flow_dv_prepare(struct rte_eth_dev *dev,
8064 const struct rte_flow_attr *attr __rte_unused,
8065 const struct rte_flow_item items[] __rte_unused,
8066 const struct rte_flow_action actions[] __rte_unused,
8067 struct rte_flow_error *error)
8069 uint32_t handle_idx = 0;
8070 struct mlx5_flow *dev_flow;
8071 struct mlx5_flow_handle *dev_handle;
8072 struct mlx5_priv *priv = dev->data->dev_private;
8073 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8076 wks->skip_matcher_reg = 0;
8078 wks->final_policy = NULL;
8079 /* In case of corrupting the memory. */
8080 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8081 rte_flow_error_set(error, ENOSPC,
8082 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8083 "not free temporary device flow");
8086 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8089 rte_flow_error_set(error, ENOMEM,
8090 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8091 "not enough memory to create flow handle");
8094 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8095 dev_flow = &wks->flows[wks->flow_idx++];
8096 memset(dev_flow, 0, sizeof(*dev_flow));
8097 dev_flow->handle = dev_handle;
8098 dev_flow->handle_idx = handle_idx;
8099 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8100 dev_flow->ingress = attr->ingress;
8101 dev_flow->dv.transfer = attr->transfer;
8105 #ifdef RTE_LIBRTE_MLX5_DEBUG
8107 * Sanity check for match mask and value. Similar to check_valid_spec() in
8108 * kernel driver. If unmasked bit is present in value, it returns failure.
8111 * pointer to match mask buffer.
8112 * @param match_value
8113 * pointer to match value buffer.
8116 * 0 if valid, -EINVAL otherwise.
8119 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8121 uint8_t *m = match_mask;
8122 uint8_t *v = match_value;
8125 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8128 "match_value differs from match_criteria"
8129 " %p[%u] != %p[%u]",
8130 match_value, i, match_mask, i);
8139 * Add match of ip_version.
8143 * @param[in] headers_v
8144 * Values header pointer.
8145 * @param[in] headers_m
8146 * Masks header pointer.
8147 * @param[in] ip_version
8148 * The IP version to set.
8151 flow_dv_set_match_ip_version(uint32_t group,
8157 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8159 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8161 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8162 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8163 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8167 * Add Ethernet item to matcher and to the value.
8169 * @param[in, out] matcher
8171 * @param[in, out] key
8172 * Flow matcher value.
8174 * Flow pattern to translate.
8176 * Item is inner pattern.
8179 flow_dv_translate_item_eth(void *matcher, void *key,
8180 const struct rte_flow_item *item, int inner,
8183 const struct rte_flow_item_eth *eth_m = item->mask;
8184 const struct rte_flow_item_eth *eth_v = item->spec;
8185 const struct rte_flow_item_eth nic_mask = {
8186 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8187 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8188 .type = RTE_BE16(0xffff),
8201 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8203 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8205 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8207 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8209 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8210 ð_m->dst, sizeof(eth_m->dst));
8211 /* The value must be in the range of the mask. */
8212 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8213 for (i = 0; i < sizeof(eth_m->dst); ++i)
8214 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8215 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8216 ð_m->src, sizeof(eth_m->src));
8217 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8218 /* The value must be in the range of the mask. */
8219 for (i = 0; i < sizeof(eth_m->dst); ++i)
8220 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8222 * HW supports match on one Ethertype, the Ethertype following the last
8223 * VLAN tag of the packet (see PRM).
8224 * Set match on ethertype only if ETH header is not followed by VLAN.
8225 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8226 * ethertype, and use ip_version field instead.
8227 * eCPRI over Ether layer will use type value 0xAEFE.
8229 if (eth_m->type == 0xFFFF) {
8230 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8231 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8232 switch (eth_v->type) {
8233 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8234 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8236 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8237 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8238 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8240 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8241 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8243 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8244 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8250 if (eth_m->has_vlan) {
8251 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8252 if (eth_v->has_vlan) {
8254 * Here, when also has_more_vlan field in VLAN item is
8255 * not set, only single-tagged packets will be matched.
8257 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8261 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8262 rte_be_to_cpu_16(eth_m->type));
8263 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8264 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8268 * Add VLAN item to matcher and to the value.
8270 * @param[in, out] dev_flow
8272 * @param[in, out] matcher
8274 * @param[in, out] key
8275 * Flow matcher value.
8277 * Flow pattern to translate.
8279 * Item is inner pattern.
8282 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8283 void *matcher, void *key,
8284 const struct rte_flow_item *item,
8285 int inner, uint32_t group)
8287 const struct rte_flow_item_vlan *vlan_m = item->mask;
8288 const struct rte_flow_item_vlan *vlan_v = item->spec;
8295 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8297 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8299 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8301 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8303 * This is workaround, masks are not supported,
8304 * and pre-validated.
8307 dev_flow->handle->vf_vlan.tag =
8308 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8311 * When VLAN item exists in flow, mark packet as tagged,
8312 * even if TCI is not specified.
8314 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8315 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8316 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8321 vlan_m = &rte_flow_item_vlan_mask;
8322 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8323 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8325 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8326 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8327 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8328 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8329 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8331 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8332 * ethertype, and use ip_version field instead.
8334 if (vlan_m->inner_type == 0xFFFF) {
8335 switch (vlan_v->inner_type) {
8336 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8337 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8338 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8339 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8341 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8342 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8344 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8345 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8351 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8352 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8353 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8354 /* Only one vlan_tag bit can be set. */
8355 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8358 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8359 rte_be_to_cpu_16(vlan_m->inner_type));
8360 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8361 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8365 * Add IPV4 item to matcher and to the value.
8367 * @param[in, out] matcher
8369 * @param[in, out] key
8370 * Flow matcher value.
8372 * Flow pattern to translate.
8374 * Item is inner pattern.
8376 * The group to insert the rule.
8379 flow_dv_translate_item_ipv4(void *matcher, void *key,
8380 const struct rte_flow_item *item,
8381 int inner, uint32_t group)
8383 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8384 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8385 const struct rte_flow_item_ipv4 nic_mask = {
8387 .src_addr = RTE_BE32(0xffffffff),
8388 .dst_addr = RTE_BE32(0xffffffff),
8389 .type_of_service = 0xff,
8390 .next_proto_id = 0xff,
8391 .time_to_live = 0xff,
8398 uint8_t tos, ihl_m, ihl_v;
8401 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8403 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8405 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8407 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8409 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8414 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8415 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8416 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8417 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8418 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8419 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8420 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8421 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8422 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8423 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8424 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8425 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8426 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8427 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8428 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8429 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8431 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8432 ipv4_m->hdr.type_of_service);
8433 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8434 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8435 ipv4_m->hdr.type_of_service >> 2);
8436 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8437 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8438 ipv4_m->hdr.next_proto_id);
8439 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8440 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8441 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8442 ipv4_m->hdr.time_to_live);
8443 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8444 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8445 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8446 !!(ipv4_m->hdr.fragment_offset));
8447 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8448 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8452 * Add IPV6 item to matcher and to the value.
8454 * @param[in, out] matcher
8456 * @param[in, out] key
8457 * Flow matcher value.
8459 * Flow pattern to translate.
8461 * Item is inner pattern.
8463 * The group to insert the rule.
8466 flow_dv_translate_item_ipv6(void *matcher, void *key,
8467 const struct rte_flow_item *item,
8468 int inner, uint32_t group)
8470 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8471 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8472 const struct rte_flow_item_ipv6 nic_mask = {
8475 "\xff\xff\xff\xff\xff\xff\xff\xff"
8476 "\xff\xff\xff\xff\xff\xff\xff\xff",
8478 "\xff\xff\xff\xff\xff\xff\xff\xff"
8479 "\xff\xff\xff\xff\xff\xff\xff\xff",
8480 .vtc_flow = RTE_BE32(0xffffffff),
8487 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8488 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8497 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8499 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8501 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8503 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8505 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8510 size = sizeof(ipv6_m->hdr.dst_addr);
8511 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8512 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8513 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8514 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8515 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8516 for (i = 0; i < size; ++i)
8517 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8518 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8519 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8520 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8521 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8522 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8523 for (i = 0; i < size; ++i)
8524 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8526 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8527 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8528 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8531 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8534 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8536 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8539 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8541 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8545 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8547 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8548 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8550 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8551 ipv6_m->hdr.hop_limits);
8552 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8553 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8554 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8555 !!(ipv6_m->has_frag_ext));
8556 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8557 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8561 * Add IPV6 fragment extension item to matcher and to the value.
8563 * @param[in, out] matcher
8565 * @param[in, out] key
8566 * Flow matcher value.
8568 * Flow pattern to translate.
8570 * Item is inner pattern.
8573 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8574 const struct rte_flow_item *item,
8577 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8578 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8579 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8581 .next_header = 0xff,
8582 .frag_data = RTE_BE16(0xffff),
8589 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8591 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8593 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8595 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8597 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8598 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8599 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8600 if (!ipv6_frag_ext_v)
8602 if (!ipv6_frag_ext_m)
8603 ipv6_frag_ext_m = &nic_mask;
8604 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8605 ipv6_frag_ext_m->hdr.next_header);
8606 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8607 ipv6_frag_ext_v->hdr.next_header &
8608 ipv6_frag_ext_m->hdr.next_header);
8612 * Add TCP item to matcher and to the value.
8614 * @param[in, out] matcher
8616 * @param[in, out] key
8617 * Flow matcher value.
8619 * Flow pattern to translate.
8621 * Item is inner pattern.
8624 flow_dv_translate_item_tcp(void *matcher, void *key,
8625 const struct rte_flow_item *item,
8628 const struct rte_flow_item_tcp *tcp_m = item->mask;
8629 const struct rte_flow_item_tcp *tcp_v = item->spec;
8634 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8636 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8638 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8640 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8642 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8643 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8647 tcp_m = &rte_flow_item_tcp_mask;
8648 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8649 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8650 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8651 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8652 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8653 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8654 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8655 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8656 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8657 tcp_m->hdr.tcp_flags);
8658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8659 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8663 * Add UDP item to matcher and to the value.
8665 * @param[in, out] matcher
8667 * @param[in, out] key
8668 * Flow matcher value.
8670 * Flow pattern to translate.
8672 * Item is inner pattern.
8675 flow_dv_translate_item_udp(void *matcher, void *key,
8676 const struct rte_flow_item *item,
8679 const struct rte_flow_item_udp *udp_m = item->mask;
8680 const struct rte_flow_item_udp *udp_v = item->spec;
8685 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8687 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8689 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8691 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8693 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8694 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8698 udp_m = &rte_flow_item_udp_mask;
8699 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8700 rte_be_to_cpu_16(udp_m->hdr.src_port));
8701 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8702 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8703 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8704 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8705 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8706 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8710 * Add GRE optional Key item to matcher and to the value.
8712 * @param[in, out] matcher
8714 * @param[in, out] key
8715 * Flow matcher value.
8717 * Flow pattern to translate.
8719 * Item is inner pattern.
8722 flow_dv_translate_item_gre_key(void *matcher, void *key,
8723 const struct rte_flow_item *item)
8725 const rte_be32_t *key_m = item->mask;
8726 const rte_be32_t *key_v = item->spec;
8727 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8728 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8729 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8731 /* GRE K bit must be on and should already be validated */
8732 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8733 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8737 key_m = &gre_key_default_mask;
8738 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8739 rte_be_to_cpu_32(*key_m) >> 8);
8740 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8741 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8742 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8743 rte_be_to_cpu_32(*key_m) & 0xFF);
8744 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8745 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8749 * Add GRE item to matcher and to the value.
8751 * @param[in, out] matcher
8753 * @param[in, out] key
8754 * Flow matcher value.
8756 * Flow pattern to translate.
8757 * @param[in] pattern_flags
8758 * Accumulated pattern flags.
8761 flow_dv_translate_item_gre(void *matcher, void *key,
8762 const struct rte_flow_item *item,
8763 uint64_t pattern_flags)
8765 static const struct rte_flow_item_gre empty_gre = {0,};
8766 const struct rte_flow_item_gre *gre_m = item->mask;
8767 const struct rte_flow_item_gre *gre_v = item->spec;
8768 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8769 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8770 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8771 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8778 uint16_t s_present:1;
8779 uint16_t k_present:1;
8780 uint16_t rsvd_bit1:1;
8781 uint16_t c_present:1;
8785 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8786 uint16_t protocol_m, protocol_v;
8788 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8789 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8795 gre_m = &rte_flow_item_gre_mask;
8797 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8798 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8799 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8800 gre_crks_rsvd0_ver_m.c_present);
8801 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8802 gre_crks_rsvd0_ver_v.c_present &
8803 gre_crks_rsvd0_ver_m.c_present);
8804 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8805 gre_crks_rsvd0_ver_m.k_present);
8806 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8807 gre_crks_rsvd0_ver_v.k_present &
8808 gre_crks_rsvd0_ver_m.k_present);
8809 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8810 gre_crks_rsvd0_ver_m.s_present);
8811 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8812 gre_crks_rsvd0_ver_v.s_present &
8813 gre_crks_rsvd0_ver_m.s_present);
8814 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8815 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8817 /* Force next protocol to prevent matchers duplication */
8818 protocol_m = 0xFFFF;
8819 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8821 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8822 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8823 protocol_m & protocol_v);
8827 * Add NVGRE item to matcher and to the value.
8829 * @param[in, out] matcher
8831 * @param[in, out] key
8832 * Flow matcher value.
8834 * Flow pattern to translate.
8835 * @param[in] pattern_flags
8836 * Accumulated pattern flags.
8839 flow_dv_translate_item_nvgre(void *matcher, void *key,
8840 const struct rte_flow_item *item,
8841 unsigned long pattern_flags)
8843 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8844 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8845 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8846 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8847 const char *tni_flow_id_m;
8848 const char *tni_flow_id_v;
8854 /* For NVGRE, GRE header fields must be set with defined values. */
8855 const struct rte_flow_item_gre gre_spec = {
8856 .c_rsvd0_ver = RTE_BE16(0x2000),
8857 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8859 const struct rte_flow_item_gre gre_mask = {
8860 .c_rsvd0_ver = RTE_BE16(0xB000),
8861 .protocol = RTE_BE16(UINT16_MAX),
8863 const struct rte_flow_item gre_item = {
8868 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
8872 nvgre_m = &rte_flow_item_nvgre_mask;
8873 tni_flow_id_m = (const char *)nvgre_m->tni;
8874 tni_flow_id_v = (const char *)nvgre_v->tni;
8875 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8876 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8877 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8878 memcpy(gre_key_m, tni_flow_id_m, size);
8879 for (i = 0; i < size; ++i)
8880 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8884 * Add VXLAN item to matcher and to the value.
8887 * Pointer to the Ethernet device structure.
8889 * Flow rule attributes.
8890 * @param[in, out] matcher
8892 * @param[in, out] key
8893 * Flow matcher value.
8895 * Flow pattern to translate.
8897 * Item is inner pattern.
8900 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8901 const struct rte_flow_attr *attr,
8902 void *matcher, void *key,
8903 const struct rte_flow_item *item,
8906 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8907 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8912 uint32_t *tunnel_header_v;
8913 uint32_t *tunnel_header_m;
8915 struct mlx5_priv *priv = dev->data->dev_private;
8916 const struct rte_flow_item_vxlan nic_mask = {
8917 .vni = "\xff\xff\xff",
8922 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8924 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8926 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8928 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8930 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8931 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8932 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8933 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8934 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8936 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8940 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8941 (attr->group && !priv->sh->misc5_cap))
8942 vxlan_m = &rte_flow_item_vxlan_mask;
8944 vxlan_m = &nic_mask;
8946 if ((priv->sh->steering_format_version ==
8947 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8948 dport != MLX5_UDP_PORT_VXLAN) ||
8949 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8950 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8957 misc_m = MLX5_ADDR_OF(fte_match_param,
8958 matcher, misc_parameters);
8959 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8960 size = sizeof(vxlan_m->vni);
8961 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8962 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8963 memcpy(vni_m, vxlan_m->vni, size);
8964 for (i = 0; i < size; ++i)
8965 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8968 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8969 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8970 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8973 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8976 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8977 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8978 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8979 if (*tunnel_header_v)
8980 *tunnel_header_m = vxlan_m->vni[0] |
8981 vxlan_m->vni[1] << 8 |
8982 vxlan_m->vni[2] << 16;
8984 *tunnel_header_m = 0x0;
8985 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8986 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8987 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8991 * Add VXLAN-GPE item to matcher and to the value.
8993 * @param[in, out] matcher
8995 * @param[in, out] key
8996 * Flow matcher value.
8998 * Flow pattern to translate.
9000 * Item is inner pattern.
9004 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9005 const struct rte_flow_item *item,
9006 const uint64_t pattern_flags)
9008 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9009 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9010 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9011 /* The item was validated to be on the outer side */
9012 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9013 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9015 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9017 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9019 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9021 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9022 int i, size = sizeof(vxlan_m->vni);
9023 uint8_t flags_m = 0xff;
9024 uint8_t flags_v = 0xc;
9025 uint8_t m_protocol, v_protocol;
9027 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9028 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9029 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9030 MLX5_UDP_PORT_VXLAN_GPE);
9033 vxlan_v = &dummy_vxlan_gpe_hdr;
9034 vxlan_m = &dummy_vxlan_gpe_hdr;
9037 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9039 memcpy(vni_m, vxlan_m->vni, size);
9040 for (i = 0; i < size; ++i)
9041 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9042 if (vxlan_m->flags) {
9043 flags_m = vxlan_m->flags;
9044 flags_v = vxlan_v->flags;
9046 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9047 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9048 m_protocol = vxlan_m->protocol;
9049 v_protocol = vxlan_v->protocol;
9052 /* Force next protocol to ensure next headers parsing. */
9053 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9054 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9055 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9056 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9057 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9058 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9060 MLX5_SET(fte_match_set_misc3, misc_m,
9061 outer_vxlan_gpe_next_protocol, m_protocol);
9062 MLX5_SET(fte_match_set_misc3, misc_v,
9063 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9067 * Add Geneve item to matcher and to the value.
9069 * @param[in, out] matcher
9071 * @param[in, out] key
9072 * Flow matcher value.
9074 * Flow pattern to translate.
9076 * Item is inner pattern.
9080 flow_dv_translate_item_geneve(void *matcher, void *key,
9081 const struct rte_flow_item *item,
9082 uint64_t pattern_flags)
9084 static const struct rte_flow_item_geneve empty_geneve = {0,};
9085 const struct rte_flow_item_geneve *geneve_m = item->mask;
9086 const struct rte_flow_item_geneve *geneve_v = item->spec;
9087 /* GENEVE flow item validation allows single tunnel item */
9088 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9089 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9090 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9091 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9094 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9095 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9096 size_t size = sizeof(geneve_m->vni), i;
9097 uint16_t protocol_m, protocol_v;
9099 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9100 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9101 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9102 MLX5_UDP_PORT_GENEVE);
9105 geneve_v = &empty_geneve;
9106 geneve_m = &empty_geneve;
9109 geneve_m = &rte_flow_item_geneve_mask;
9111 memcpy(vni_m, geneve_m->vni, size);
9112 for (i = 0; i < size; ++i)
9113 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9114 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9115 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9116 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9117 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9118 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9119 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9120 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9121 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9122 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9123 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9124 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9125 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9126 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9128 /* Force next protocol to prevent matchers duplication */
9129 protocol_m = 0xFFFF;
9130 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9132 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9133 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9134 protocol_m & protocol_v);
9138 * Create Geneve TLV option resource.
9140 * @param dev[in, out]
9141 * Pointer to rte_eth_dev structure.
9142 * @param[in, out] tag_be24
9143 * Tag value in big endian then R-shift 8.
9144 * @parm[in, out] dev_flow
9145 * Pointer to the dev_flow.
9147 * pointer to error structure.
9150 * 0 on success otherwise -errno and errno is set.
9154 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9155 const struct rte_flow_item *item,
9156 struct rte_flow_error *error)
9158 struct mlx5_priv *priv = dev->data->dev_private;
9159 struct mlx5_dev_ctx_shared *sh = priv->sh;
9160 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9161 sh->geneve_tlv_option_resource;
9162 struct mlx5_devx_obj *obj;
9163 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9168 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9169 if (geneve_opt_resource != NULL) {
9170 if (geneve_opt_resource->option_class ==
9171 geneve_opt_v->option_class &&
9172 geneve_opt_resource->option_type ==
9173 geneve_opt_v->option_type &&
9174 geneve_opt_resource->length ==
9175 geneve_opt_v->option_len) {
9176 /* We already have GENVE TLV option obj allocated. */
9177 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9180 ret = rte_flow_error_set(error, ENOMEM,
9181 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9182 "Only one GENEVE TLV option supported");
9186 /* Create a GENEVE TLV object and resource. */
9187 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9188 geneve_opt_v->option_class,
9189 geneve_opt_v->option_type,
9190 geneve_opt_v->option_len);
9192 ret = rte_flow_error_set(error, ENODATA,
9193 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9194 "Failed to create GENEVE TLV Devx object");
9197 sh->geneve_tlv_option_resource =
9198 mlx5_malloc(MLX5_MEM_ZERO,
9199 sizeof(*geneve_opt_resource),
9201 if (!sh->geneve_tlv_option_resource) {
9202 claim_zero(mlx5_devx_cmd_destroy(obj));
9203 ret = rte_flow_error_set(error, ENOMEM,
9204 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9205 "GENEVE TLV object memory allocation failed");
9208 geneve_opt_resource = sh->geneve_tlv_option_resource;
9209 geneve_opt_resource->obj = obj;
9210 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9211 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9212 geneve_opt_resource->length = geneve_opt_v->option_len;
9213 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9217 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9222 * Add Geneve TLV option item to matcher.
9224 * @param[in, out] dev
9225 * Pointer to rte_eth_dev structure.
9226 * @param[in, out] matcher
9228 * @param[in, out] key
9229 * Flow matcher value.
9231 * Flow pattern to translate.
9233 * Pointer to error structure.
9236 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9237 void *key, const struct rte_flow_item *item,
9238 struct rte_flow_error *error)
9240 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9241 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9242 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9243 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9244 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9246 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9247 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9253 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9254 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9257 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9261 * Set the option length in GENEVE header if not requested.
9262 * The GENEVE TLV option length is expressed by the option length field
9263 * in the GENEVE header.
9264 * If the option length was not requested but the GENEVE TLV option item
9265 * is present we set the option length field implicitly.
9267 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9268 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9269 MLX5_GENEVE_OPTLEN_MASK);
9270 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9271 geneve_opt_v->option_len + 1);
9273 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9274 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9276 if (geneve_opt_v->data) {
9277 memcpy(&opt_data_key, geneve_opt_v->data,
9278 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9279 sizeof(opt_data_key)));
9280 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9281 sizeof(opt_data_key));
9282 memcpy(&opt_data_mask, geneve_opt_m->data,
9283 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9284 sizeof(opt_data_mask)));
9285 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9286 sizeof(opt_data_mask));
9287 MLX5_SET(fte_match_set_misc3, misc3_m,
9288 geneve_tlv_option_0_data,
9289 rte_be_to_cpu_32(opt_data_mask));
9290 MLX5_SET(fte_match_set_misc3, misc3_v,
9291 geneve_tlv_option_0_data,
9292 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9298 * Add MPLS item to matcher and to the value.
9300 * @param[in, out] matcher
9302 * @param[in, out] key
9303 * Flow matcher value.
9305 * Flow pattern to translate.
9306 * @param[in] prev_layer
9307 * The protocol layer indicated in previous item.
9309 * Item is inner pattern.
9312 flow_dv_translate_item_mpls(void *matcher, void *key,
9313 const struct rte_flow_item *item,
9314 uint64_t prev_layer,
9317 const uint32_t *in_mpls_m = item->mask;
9318 const uint32_t *in_mpls_v = item->spec;
9319 uint32_t *out_mpls_m = 0;
9320 uint32_t *out_mpls_v = 0;
9321 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9322 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9323 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9325 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9326 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9327 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9329 switch (prev_layer) {
9330 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9331 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9332 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9333 MLX5_UDP_PORT_MPLS);
9335 case MLX5_FLOW_LAYER_GRE:
9337 case MLX5_FLOW_LAYER_GRE_KEY:
9338 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9339 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9340 RTE_ETHER_TYPE_MPLS);
9348 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9349 switch (prev_layer) {
9350 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9352 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9353 outer_first_mpls_over_udp);
9355 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9356 outer_first_mpls_over_udp);
9358 case MLX5_FLOW_LAYER_GRE:
9360 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9361 outer_first_mpls_over_gre);
9363 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9364 outer_first_mpls_over_gre);
9367 /* Inner MPLS not over GRE is not supported. */
9370 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9374 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9380 if (out_mpls_m && out_mpls_v) {
9381 *out_mpls_m = *in_mpls_m;
9382 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9387 * Add metadata register item to matcher
9389 * @param[in, out] matcher
9391 * @param[in, out] key
9392 * Flow matcher value.
9393 * @param[in] reg_type
9394 * Type of device metadata register
9401 flow_dv_match_meta_reg(void *matcher, void *key,
9402 enum modify_reg reg_type,
9403 uint32_t data, uint32_t mask)
9406 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9408 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9414 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9415 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9418 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9419 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9423 * The metadata register C0 field might be divided into
9424 * source vport index and META item value, we should set
9425 * this field according to specified mask, not as whole one.
9427 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9429 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9430 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9433 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9436 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9437 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9440 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9441 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9444 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9445 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9448 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9449 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9452 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9453 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9456 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9457 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9460 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9461 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9470 * Add MARK item to matcher
9473 * The device to configure through.
9474 * @param[in, out] matcher
9476 * @param[in, out] key
9477 * Flow matcher value.
9479 * Flow pattern to translate.
9482 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9483 void *matcher, void *key,
9484 const struct rte_flow_item *item)
9486 struct mlx5_priv *priv = dev->data->dev_private;
9487 const struct rte_flow_item_mark *mark;
9491 mark = item->mask ? (const void *)item->mask :
9492 &rte_flow_item_mark_mask;
9493 mask = mark->id & priv->sh->dv_mark_mask;
9494 mark = (const void *)item->spec;
9496 value = mark->id & priv->sh->dv_mark_mask & mask;
9498 enum modify_reg reg;
9500 /* Get the metadata register index for the mark. */
9501 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9502 MLX5_ASSERT(reg > 0);
9503 if (reg == REG_C_0) {
9504 struct mlx5_priv *priv = dev->data->dev_private;
9505 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9506 uint32_t shl_c0 = rte_bsf32(msk_c0);
9512 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9517 * Add META item to matcher
9520 * The devich to configure through.
9521 * @param[in, out] matcher
9523 * @param[in, out] key
9524 * Flow matcher value.
9526 * Attributes of flow that includes this item.
9528 * Flow pattern to translate.
9531 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9532 void *matcher, void *key,
9533 const struct rte_flow_attr *attr,
9534 const struct rte_flow_item *item)
9536 const struct rte_flow_item_meta *meta_m;
9537 const struct rte_flow_item_meta *meta_v;
9539 meta_m = (const void *)item->mask;
9541 meta_m = &rte_flow_item_meta_mask;
9542 meta_v = (const void *)item->spec;
9545 uint32_t value = meta_v->data;
9546 uint32_t mask = meta_m->data;
9548 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9551 MLX5_ASSERT(reg != REG_NON);
9552 if (reg == REG_C_0) {
9553 struct mlx5_priv *priv = dev->data->dev_private;
9554 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9555 uint32_t shl_c0 = rte_bsf32(msk_c0);
9561 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9566 * Add vport metadata Reg C0 item to matcher
9568 * @param[in, out] matcher
9570 * @param[in, out] key
9571 * Flow matcher value.
9573 * Flow pattern to translate.
9576 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9577 uint32_t value, uint32_t mask)
9579 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9583 * Add tag item to matcher
9586 * The devich to configure through.
9587 * @param[in, out] matcher
9589 * @param[in, out] key
9590 * Flow matcher value.
9592 * Flow pattern to translate.
9595 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9596 void *matcher, void *key,
9597 const struct rte_flow_item *item)
9599 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9600 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9601 uint32_t mask, value;
9604 value = tag_v->data;
9605 mask = tag_m ? tag_m->data : UINT32_MAX;
9606 if (tag_v->id == REG_C_0) {
9607 struct mlx5_priv *priv = dev->data->dev_private;
9608 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9609 uint32_t shl_c0 = rte_bsf32(msk_c0);
9615 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9619 * Add TAG item to matcher
9622 * The devich to configure through.
9623 * @param[in, out] matcher
9625 * @param[in, out] key
9626 * Flow matcher value.
9628 * Flow pattern to translate.
9631 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9632 void *matcher, void *key,
9633 const struct rte_flow_item *item)
9635 const struct rte_flow_item_tag *tag_v = item->spec;
9636 const struct rte_flow_item_tag *tag_m = item->mask;
9637 enum modify_reg reg;
9640 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9641 /* Get the metadata register index for the tag. */
9642 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9643 MLX5_ASSERT(reg > 0);
9644 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9648 * Add source vport match to the specified matcher.
9650 * @param[in, out] matcher
9652 * @param[in, out] key
9653 * Flow matcher value.
9655 * Source vport value to match
9660 flow_dv_translate_item_source_vport(void *matcher, void *key,
9661 int16_t port, uint16_t mask)
9663 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9664 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9666 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9667 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9671 * Translate port-id item to eswitch match on port-id.
9674 * The devich to configure through.
9675 * @param[in, out] matcher
9677 * @param[in, out] key
9678 * Flow matcher value.
9680 * Flow pattern to translate.
9685 * 0 on success, a negative errno value otherwise.
9688 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9689 void *key, const struct rte_flow_item *item,
9690 const struct rte_flow_attr *attr)
9692 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9693 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9694 struct mlx5_priv *priv;
9697 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9698 flow_dv_translate_item_source_vport(matcher, key,
9699 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9702 mask = pid_m ? pid_m->id : 0xffff;
9703 id = pid_v ? pid_v->id : dev->data->port_id;
9704 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9708 * Translate to vport field or to metadata, depending on mode.
9709 * Kernel can use either misc.source_port or half of C0 metadata
9712 if (priv->vport_meta_mask) {
9714 * Provide the hint for SW steering library
9715 * to insert the flow into ingress domain and
9716 * save the extra vport match.
9718 if (mask == 0xffff && priv->vport_id == 0xffff &&
9719 priv->pf_bond < 0 && attr->transfer)
9720 flow_dv_translate_item_source_vport
9721 (matcher, key, priv->vport_id, mask);
9723 * We should always set the vport metadata register,
9724 * otherwise the SW steering library can drop
9725 * the rule if wire vport metadata value is not zero,
9726 * it depends on kernel configuration.
9728 flow_dv_translate_item_meta_vport(matcher, key,
9729 priv->vport_meta_tag,
9730 priv->vport_meta_mask);
9732 flow_dv_translate_item_source_vport(matcher, key,
9733 priv->vport_id, mask);
9739 * Add ICMP6 item to matcher and to the value.
9741 * @param[in, out] matcher
9743 * @param[in, out] key
9744 * Flow matcher value.
9746 * Flow pattern to translate.
9748 * Item is inner pattern.
9751 flow_dv_translate_item_icmp6(void *matcher, void *key,
9752 const struct rte_flow_item *item,
9755 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9756 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9759 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9761 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9763 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9765 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9767 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9769 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9771 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9772 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9776 icmp6_m = &rte_flow_item_icmp6_mask;
9777 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9778 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9779 icmp6_v->type & icmp6_m->type);
9780 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9781 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9782 icmp6_v->code & icmp6_m->code);
9786 * Add ICMP item to matcher and to the value.
9788 * @param[in, out] matcher
9790 * @param[in, out] key
9791 * Flow matcher value.
9793 * Flow pattern to translate.
9795 * Item is inner pattern.
9798 flow_dv_translate_item_icmp(void *matcher, void *key,
9799 const struct rte_flow_item *item,
9802 const struct rte_flow_item_icmp *icmp_m = item->mask;
9803 const struct rte_flow_item_icmp *icmp_v = item->spec;
9804 uint32_t icmp_header_data_m = 0;
9805 uint32_t icmp_header_data_v = 0;
9808 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9810 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9812 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9814 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9816 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9818 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9820 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9821 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9825 icmp_m = &rte_flow_item_icmp_mask;
9826 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9827 icmp_m->hdr.icmp_type);
9828 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9829 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9830 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9831 icmp_m->hdr.icmp_code);
9832 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9833 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9834 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9835 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9836 if (icmp_header_data_m) {
9837 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9838 icmp_header_data_v |=
9839 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9840 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9841 icmp_header_data_m);
9842 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9843 icmp_header_data_v & icmp_header_data_m);
9848 * Add GTP item to matcher and to the value.
9850 * @param[in, out] matcher
9852 * @param[in, out] key
9853 * Flow matcher value.
9855 * Flow pattern to translate.
9857 * Item is inner pattern.
9860 flow_dv_translate_item_gtp(void *matcher, void *key,
9861 const struct rte_flow_item *item, int inner)
9863 const struct rte_flow_item_gtp *gtp_m = item->mask;
9864 const struct rte_flow_item_gtp *gtp_v = item->spec;
9867 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9869 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9870 uint16_t dport = RTE_GTPU_UDP_PORT;
9873 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9875 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9877 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9879 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9881 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9882 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9883 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9888 gtp_m = &rte_flow_item_gtp_mask;
9889 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9890 gtp_m->v_pt_rsv_flags);
9891 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9892 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9893 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9894 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9895 gtp_v->msg_type & gtp_m->msg_type);
9896 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9897 rte_be_to_cpu_32(gtp_m->teid));
9898 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9899 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9903 * Add GTP PSC item to matcher.
9905 * @param[in, out] matcher
9907 * @param[in, out] key
9908 * Flow matcher value.
9910 * Flow pattern to translate.
9913 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9914 const struct rte_flow_item *item)
9916 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9917 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9918 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9920 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9926 uint8_t next_ext_header_type;
9931 /* Always set E-flag match on one, regardless of GTP item settings. */
9932 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9933 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9934 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9935 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9936 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9937 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9938 /*Set next extension header type. */
9941 dw_2.next_ext_header_type = 0xff;
9942 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9943 rte_cpu_to_be_32(dw_2.w32));
9946 dw_2.next_ext_header_type = 0x85;
9947 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9948 rte_cpu_to_be_32(dw_2.w32));
9960 /*Set extension header PDU type and Qos. */
9962 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9964 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9965 dw_0.qfi = gtp_psc_m->hdr.qfi;
9966 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9967 rte_cpu_to_be_32(dw_0.w32));
9969 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9970 gtp_psc_m->hdr.type);
9971 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9972 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9973 rte_cpu_to_be_32(dw_0.w32));
9979 * Add eCPRI item to matcher and to the value.
9982 * The devich to configure through.
9983 * @param[in, out] matcher
9985 * @param[in, out] key
9986 * Flow matcher value.
9988 * Flow pattern to translate.
9989 * @param[in] last_item
9993 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9994 void *key, const struct rte_flow_item *item,
9997 struct mlx5_priv *priv = dev->data->dev_private;
9998 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9999 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10000 struct rte_ecpri_common_hdr common;
10001 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10002 misc_parameters_4);
10003 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10009 * In case of eCPRI over Ethernet, if EtherType is not specified,
10010 * match on eCPRI EtherType implicitly.
10012 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10013 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10015 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10016 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10017 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10018 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10019 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10020 *(uint16_t *)l2m = UINT16_MAX;
10021 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10027 ecpri_m = &rte_flow_item_ecpri_mask;
10029 * Maximal four DW samples are supported in a single matching now.
10030 * Two are used now for a eCPRI matching:
10031 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10032 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10035 if (!ecpri_m->hdr.common.u32)
10037 samples = priv->sh->ecpri_parser.ids;
10038 /* Need to take the whole DW as the mask to fill the entry. */
10039 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10040 prog_sample_field_value_0);
10041 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10042 prog_sample_field_value_0);
10043 /* Already big endian (network order) in the header. */
10044 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10045 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10046 /* Sample#0, used for matching type, offset 0. */
10047 MLX5_SET(fte_match_set_misc4, misc4_m,
10048 prog_sample_field_id_0, samples[0]);
10049 /* It makes no sense to set the sample ID in the mask field. */
10050 MLX5_SET(fte_match_set_misc4, misc4_v,
10051 prog_sample_field_id_0, samples[0]);
10053 * Checking if message body part needs to be matched.
10054 * Some wildcard rules only matching type field should be supported.
10056 if (ecpri_m->hdr.dummy[0]) {
10057 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10058 switch (common.type) {
10059 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10060 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10061 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10062 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10063 prog_sample_field_value_1);
10064 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10065 prog_sample_field_value_1);
10066 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10067 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10068 ecpri_m->hdr.dummy[0];
10069 /* Sample#1, to match message body, offset 4. */
10070 MLX5_SET(fte_match_set_misc4, misc4_m,
10071 prog_sample_field_id_1, samples[1]);
10072 MLX5_SET(fte_match_set_misc4, misc4_v,
10073 prog_sample_field_id_1, samples[1]);
10076 /* Others, do not match any sample ID. */
10083 * Add connection tracking status item to matcher
10086 * The devich to configure through.
10087 * @param[in, out] matcher
10089 * @param[in, out] key
10090 * Flow matcher value.
10092 * Flow pattern to translate.
10095 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10096 void *matcher, void *key,
10097 const struct rte_flow_item *item)
10099 uint32_t reg_value = 0;
10101 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10102 uint32_t reg_mask = 0;
10103 const struct rte_flow_item_conntrack *spec = item->spec;
10104 const struct rte_flow_item_conntrack *mask = item->mask;
10106 struct rte_flow_error error;
10109 mask = &rte_flow_item_conntrack_mask;
10110 if (!spec || !mask->flags)
10112 flags = spec->flags & mask->flags;
10113 /* The conflict should be checked in the validation. */
10114 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10115 reg_value |= MLX5_CT_SYNDROME_VALID;
10116 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10117 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10118 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10119 reg_value |= MLX5_CT_SYNDROME_INVALID;
10120 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10121 reg_value |= MLX5_CT_SYNDROME_TRAP;
10122 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10123 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10124 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10125 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10126 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10128 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10129 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10130 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10131 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10132 /* The REG_C_x value could be saved during startup. */
10133 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10134 if (reg_id == REG_NON)
10136 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10137 reg_value, reg_mask);
10141 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10142 const struct rte_flow_item *item,
10143 struct mlx5_flow *dev_flow, bool is_inner)
10145 const struct rte_flow_item_flex *spec =
10146 (const struct rte_flow_item_flex *)item->spec;
10147 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10149 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10152 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10153 /* Don't count both inner and outer flex items in one rule. */
10154 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10155 MLX5_ASSERT(false);
10156 dev_flow->handle->flex_item |= RTE_BIT32(index);
10158 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10161 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10163 #define HEADER_IS_ZERO(match_criteria, headers) \
10164 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10165 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10168 * Calculate flow matcher enable bitmap.
10170 * @param match_criteria
10171 * Pointer to flow matcher criteria.
10174 * Bitmap of enabled fields.
10177 flow_dv_matcher_enable(uint32_t *match_criteria)
10179 uint8_t match_criteria_enable;
10181 match_criteria_enable =
10182 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10183 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10184 match_criteria_enable |=
10185 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10186 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10187 match_criteria_enable |=
10188 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10189 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10190 match_criteria_enable |=
10191 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10192 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10193 match_criteria_enable |=
10194 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10195 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10196 match_criteria_enable |=
10197 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10198 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10199 match_criteria_enable |=
10200 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10201 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10202 return match_criteria_enable;
10206 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10209 * Check flow matching criteria first, subtract misc5/4 length if flow
10210 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10211 * misc5/4 are not supported, and matcher creation failure is expected
10212 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10213 * misc5 is right after misc4.
10215 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10216 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10217 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10218 if (!(match_criteria & (1 <<
10219 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10220 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10225 static struct mlx5_list_entry *
10226 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10227 struct mlx5_list_entry *entry, void *cb_ctx)
10229 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10230 struct mlx5_flow_dv_matcher *ref = ctx->data;
10231 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10232 typeof(*tbl), tbl);
10233 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10238 rte_flow_error_set(ctx->error, ENOMEM,
10239 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10240 "cannot create matcher");
10243 memcpy(resource, entry, sizeof(*resource));
10244 resource->tbl = &tbl->tbl;
10245 return &resource->entry;
10249 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10250 struct mlx5_list_entry *entry)
10255 struct mlx5_list_entry *
10256 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10258 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10259 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10260 struct rte_eth_dev *dev = ctx->dev;
10261 struct mlx5_flow_tbl_data_entry *tbl_data;
10262 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10263 struct rte_flow_error *error = ctx->error;
10264 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10265 struct mlx5_flow_tbl_resource *tbl;
10270 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10272 rte_flow_error_set(error, ENOMEM,
10273 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10275 "cannot allocate flow table data entry");
10278 tbl_data->idx = idx;
10279 tbl_data->tunnel = tt_prm->tunnel;
10280 tbl_data->group_id = tt_prm->group_id;
10281 tbl_data->external = !!tt_prm->external;
10282 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10283 tbl_data->is_egress = !!key.is_egress;
10284 tbl_data->is_transfer = !!key.is_fdb;
10285 tbl_data->dummy = !!key.dummy;
10286 tbl_data->level = key.level;
10287 tbl_data->id = key.id;
10288 tbl = &tbl_data->tbl;
10290 return &tbl_data->entry;
10292 domain = sh->fdb_domain;
10293 else if (key.is_egress)
10294 domain = sh->tx_domain;
10296 domain = sh->rx_domain;
10297 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10299 rte_flow_error_set(error, ENOMEM,
10300 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10301 NULL, "cannot create flow table object");
10302 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10305 if (key.level != 0) {
10306 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10307 (tbl->obj, &tbl_data->jump.action);
10309 rte_flow_error_set(error, ENOMEM,
10310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10312 "cannot create flow jump action");
10313 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10314 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10318 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10319 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10320 key.level, key.id);
10321 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10322 flow_dv_matcher_create_cb,
10323 flow_dv_matcher_match_cb,
10324 flow_dv_matcher_remove_cb,
10325 flow_dv_matcher_clone_cb,
10326 flow_dv_matcher_clone_free_cb);
10327 if (!tbl_data->matchers) {
10328 rte_flow_error_set(error, ENOMEM,
10329 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10331 "cannot create tbl matcher list");
10332 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10333 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10334 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10337 return &tbl_data->entry;
10341 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10344 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10345 struct mlx5_flow_tbl_data_entry *tbl_data =
10346 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10347 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10349 return tbl_data->level != key.level ||
10350 tbl_data->id != key.id ||
10351 tbl_data->dummy != key.dummy ||
10352 tbl_data->is_transfer != !!key.is_fdb ||
10353 tbl_data->is_egress != !!key.is_egress;
10356 struct mlx5_list_entry *
10357 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10360 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10361 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10362 struct mlx5_flow_tbl_data_entry *tbl_data;
10363 struct rte_flow_error *error = ctx->error;
10366 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10368 rte_flow_error_set(error, ENOMEM,
10369 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10371 "cannot allocate flow table data entry");
10374 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10375 tbl_data->idx = idx;
10376 return &tbl_data->entry;
10380 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10382 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10383 struct mlx5_flow_tbl_data_entry *tbl_data =
10384 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10386 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10390 * Get a flow table.
10392 * @param[in, out] dev
10393 * Pointer to rte_eth_dev structure.
10394 * @param[in] table_level
10395 * Table level to use.
10396 * @param[in] egress
10397 * Direction of the table.
10398 * @param[in] transfer
10399 * E-Switch or NIC flow.
10401 * Dummy entry for dv API.
10402 * @param[in] table_id
10404 * @param[out] error
10405 * pointer to error structure.
10408 * Returns tables resource based on the index, NULL in case of failed.
10410 struct mlx5_flow_tbl_resource *
10411 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10412 uint32_t table_level, uint8_t egress,
10415 const struct mlx5_flow_tunnel *tunnel,
10416 uint32_t group_id, uint8_t dummy,
10418 struct rte_flow_error *error)
10420 struct mlx5_priv *priv = dev->data->dev_private;
10421 union mlx5_flow_tbl_key table_key = {
10423 .level = table_level,
10427 .is_fdb = !!transfer,
10428 .is_egress = !!egress,
10431 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10433 .group_id = group_id,
10434 .external = external,
10436 struct mlx5_flow_cb_ctx ctx = {
10439 .data = &table_key.v64,
10442 struct mlx5_list_entry *entry;
10443 struct mlx5_flow_tbl_data_entry *tbl_data;
10445 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10447 rte_flow_error_set(error, ENOMEM,
10448 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10449 "cannot get table");
10452 DRV_LOG(DEBUG, "table_level %u table_id %u "
10453 "tunnel %u group %u registered.",
10454 table_level, table_id,
10455 tunnel ? tunnel->tunnel_id : 0, group_id);
10456 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10457 return &tbl_data->tbl;
10461 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10463 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10464 struct mlx5_flow_tbl_data_entry *tbl_data =
10465 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10467 MLX5_ASSERT(entry && sh);
10468 if (tbl_data->jump.action)
10469 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10470 if (tbl_data->tbl.obj)
10471 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10472 if (tbl_data->tunnel_offload && tbl_data->external) {
10473 struct mlx5_list_entry *he;
10474 struct mlx5_hlist *tunnel_grp_hash;
10475 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10476 union tunnel_tbl_key tunnel_key = {
10477 .tunnel_id = tbl_data->tunnel ?
10478 tbl_data->tunnel->tunnel_id : 0,
10479 .group = tbl_data->group_id
10481 uint32_t table_level = tbl_data->level;
10482 struct mlx5_flow_cb_ctx ctx = {
10483 .data = (void *)&tunnel_key.val,
10486 tunnel_grp_hash = tbl_data->tunnel ?
10487 tbl_data->tunnel->groups :
10489 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10491 mlx5_hlist_unregister(tunnel_grp_hash, he);
10493 "table_level %u id %u tunnel %u group %u released.",
10497 tbl_data->tunnel->tunnel_id : 0,
10498 tbl_data->group_id);
10500 mlx5_list_destroy(tbl_data->matchers);
10501 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10505 * Release a flow table.
10508 * Pointer to device shared structure.
10510 * Table resource to be released.
10513 * Returns 0 if table was released, else return 1;
10516 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10517 struct mlx5_flow_tbl_resource *tbl)
10519 struct mlx5_flow_tbl_data_entry *tbl_data =
10520 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10524 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10528 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10529 struct mlx5_list_entry *entry, void *cb_ctx)
10531 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10532 struct mlx5_flow_dv_matcher *ref = ctx->data;
10533 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10536 return cur->crc != ref->crc ||
10537 cur->priority != ref->priority ||
10538 memcmp((const void *)cur->mask.buf,
10539 (const void *)ref->mask.buf, ref->mask.size);
10542 struct mlx5_list_entry *
10543 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10545 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10546 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10547 struct mlx5_flow_dv_matcher *ref = ctx->data;
10548 struct mlx5_flow_dv_matcher *resource;
10549 struct mlx5dv_flow_matcher_attr dv_attr = {
10550 .type = IBV_FLOW_ATTR_NORMAL,
10551 .match_mask = (void *)&ref->mask,
10553 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10554 typeof(*tbl), tbl);
10557 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10560 rte_flow_error_set(ctx->error, ENOMEM,
10561 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10562 "cannot create matcher");
10566 dv_attr.match_criteria_enable =
10567 flow_dv_matcher_enable(resource->mask.buf);
10568 __flow_dv_adjust_buf_size(&ref->mask.size,
10569 dv_attr.match_criteria_enable);
10570 dv_attr.priority = ref->priority;
10571 if (tbl->is_egress)
10572 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10573 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10575 &resource->matcher_object);
10577 mlx5_free(resource);
10578 rte_flow_error_set(ctx->error, ENOMEM,
10579 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10580 "cannot create matcher");
10583 return &resource->entry;
10587 * Register the flow matcher.
10589 * @param[in, out] dev
10590 * Pointer to rte_eth_dev structure.
10591 * @param[in, out] matcher
10592 * Pointer to flow matcher.
10593 * @param[in, out] key
10594 * Pointer to flow table key.
10595 * @parm[in, out] dev_flow
10596 * Pointer to the dev_flow.
10597 * @param[out] error
10598 * pointer to error structure.
10601 * 0 on success otherwise -errno and errno is set.
10604 flow_dv_matcher_register(struct rte_eth_dev *dev,
10605 struct mlx5_flow_dv_matcher *ref,
10606 union mlx5_flow_tbl_key *key,
10607 struct mlx5_flow *dev_flow,
10608 const struct mlx5_flow_tunnel *tunnel,
10610 struct rte_flow_error *error)
10612 struct mlx5_list_entry *entry;
10613 struct mlx5_flow_dv_matcher *resource;
10614 struct mlx5_flow_tbl_resource *tbl;
10615 struct mlx5_flow_tbl_data_entry *tbl_data;
10616 struct mlx5_flow_cb_ctx ctx = {
10621 * tunnel offload API requires this registration for cases when
10622 * tunnel match rule was inserted before tunnel set rule.
10624 tbl = flow_dv_tbl_resource_get(dev, key->level,
10625 key->is_egress, key->is_fdb,
10626 dev_flow->external, tunnel,
10627 group_id, 0, key->id, error);
10629 return -rte_errno; /* No need to refill the error info */
10630 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10632 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10634 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10635 return rte_flow_error_set(error, ENOMEM,
10636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10637 "cannot allocate ref memory");
10639 resource = container_of(entry, typeof(*resource), entry);
10640 dev_flow->handle->dvh.matcher = resource;
10644 struct mlx5_list_entry *
10645 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10647 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10648 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10649 struct mlx5_flow_dv_tag_resource *entry;
10653 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10655 rte_flow_error_set(ctx->error, ENOMEM,
10656 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10657 "cannot allocate resource memory");
10661 entry->tag_id = *(uint32_t *)(ctx->data);
10662 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10665 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10666 rte_flow_error_set(ctx->error, ENOMEM,
10667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10668 NULL, "cannot create action");
10671 return &entry->entry;
10675 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10678 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10679 struct mlx5_flow_dv_tag_resource *tag =
10680 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10682 return *(uint32_t *)(ctx->data) != tag->tag_id;
10685 struct mlx5_list_entry *
10686 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10689 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10690 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10691 struct mlx5_flow_dv_tag_resource *entry;
10694 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10696 rte_flow_error_set(ctx->error, ENOMEM,
10697 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10698 "cannot allocate tag resource memory");
10701 memcpy(entry, oentry, sizeof(*entry));
10703 return &entry->entry;
10707 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10709 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10710 struct mlx5_flow_dv_tag_resource *tag =
10711 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10713 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10717 * Find existing tag resource or create and register a new one.
10719 * @param dev[in, out]
10720 * Pointer to rte_eth_dev structure.
10721 * @param[in, out] tag_be24
10722 * Tag value in big endian then R-shift 8.
10723 * @parm[in, out] dev_flow
10724 * Pointer to the dev_flow.
10725 * @param[out] error
10726 * pointer to error structure.
10729 * 0 on success otherwise -errno and errno is set.
10732 flow_dv_tag_resource_register
10733 (struct rte_eth_dev *dev,
10735 struct mlx5_flow *dev_flow,
10736 struct rte_flow_error *error)
10738 struct mlx5_priv *priv = dev->data->dev_private;
10739 struct mlx5_flow_dv_tag_resource *resource;
10740 struct mlx5_list_entry *entry;
10741 struct mlx5_flow_cb_ctx ctx = {
10745 struct mlx5_hlist *tag_table;
10747 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10749 MLX5_TAGS_HLIST_ARRAY_SIZE,
10750 false, false, priv->sh,
10751 flow_dv_tag_create_cb,
10752 flow_dv_tag_match_cb,
10753 flow_dv_tag_remove_cb,
10754 flow_dv_tag_clone_cb,
10755 flow_dv_tag_clone_free_cb);
10756 if (unlikely(!tag_table))
10758 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10760 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10762 dev_flow->handle->dvh.rix_tag = resource->idx;
10763 dev_flow->dv.tag_resource = resource;
10770 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10772 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10773 struct mlx5_flow_dv_tag_resource *tag =
10774 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10776 MLX5_ASSERT(tag && sh && tag->action);
10777 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10778 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10779 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10786 * Pointer to Ethernet device.
10791 * 1 while a reference on it exists, 0 when freed.
10794 flow_dv_tag_release(struct rte_eth_dev *dev,
10797 struct mlx5_priv *priv = dev->data->dev_private;
10798 struct mlx5_flow_dv_tag_resource *tag;
10800 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10803 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10804 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10805 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10809 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10812 * Pointer to rte_eth_dev structure.
10813 * @param[in] action
10814 * Pointer to action PORT_ID / REPRESENTED_PORT.
10815 * @param[out] dst_port_id
10816 * The target port ID.
10817 * @param[out] error
10818 * Pointer to the error structure.
10821 * 0 on success, a negative errno value otherwise and rte_errno is set.
10824 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10825 const struct rte_flow_action *action,
10826 uint32_t *dst_port_id,
10827 struct rte_flow_error *error)
10830 struct mlx5_priv *priv;
10832 switch (action->type) {
10833 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10834 const struct rte_flow_action_port_id *conf;
10836 conf = (const struct rte_flow_action_port_id *)action->conf;
10837 port = conf->original ? dev->data->port_id : conf->id;
10840 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10841 const struct rte_flow_action_ethdev *ethdev;
10843 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10844 port = ethdev->port_id;
10848 MLX5_ASSERT(false);
10849 return rte_flow_error_set(error, EINVAL,
10850 RTE_FLOW_ERROR_TYPE_ACTION, action,
10851 "unknown E-Switch action");
10854 priv = mlx5_port_to_eswitch_info(port, false);
10856 return rte_flow_error_set(error, -rte_errno,
10857 RTE_FLOW_ERROR_TYPE_ACTION,
10859 "No eswitch info was found for port");
10860 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10862 * This parameter is transferred to
10863 * mlx5dv_dr_action_create_dest_ib_port().
10865 *dst_port_id = priv->dev_port;
10868 * Legacy mode, no LAG configurations is supported.
10869 * This parameter is transferred to
10870 * mlx5dv_dr_action_create_dest_vport().
10872 *dst_port_id = priv->vport_id;
10878 * Create a counter with aging configuration.
10881 * Pointer to rte_eth_dev structure.
10882 * @param[in] dev_flow
10883 * Pointer to the mlx5_flow.
10884 * @param[out] count
10885 * Pointer to the counter action configuration.
10887 * Pointer to the aging action configuration.
10890 * Index to flow counter on success, 0 otherwise.
10893 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10894 struct mlx5_flow *dev_flow,
10895 const struct rte_flow_action_count *count
10897 const struct rte_flow_action_age *age)
10900 struct mlx5_age_param *age_param;
10902 counter = flow_dv_counter_alloc(dev, !!age);
10903 if (!counter || age == NULL)
10905 age_param = flow_dv_counter_idx_get_age(dev, counter);
10906 age_param->context = age->context ? age->context :
10907 (void *)(uintptr_t)(dev_flow->flow_idx);
10908 age_param->timeout = age->timeout;
10909 age_param->port_id = dev->data->port_id;
10910 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10911 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10916 * Add Tx queue matcher
10919 * Pointer to the dev struct.
10920 * @param[in, out] matcher
10922 * @param[in, out] key
10923 * Flow matcher value.
10925 * Flow pattern to translate.
10927 * Item is inner pattern.
10930 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10931 void *matcher, void *key,
10932 const struct rte_flow_item *item)
10934 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10935 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10937 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10939 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10940 struct mlx5_txq_ctrl *txq;
10941 uint32_t queue, mask;
10943 queue_m = (const void *)item->mask;
10944 queue_v = (const void *)item->spec;
10947 txq = mlx5_txq_get(dev, queue_v->queue);
10950 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10951 queue = txq->obj->sq->id;
10953 queue = txq->obj->sq_obj.sq->id;
10954 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10955 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10956 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10957 mlx5_txq_release(dev, queue_v->queue);
10961 * Set the hash fields according to the @p flow information.
10963 * @param[in] dev_flow
10964 * Pointer to the mlx5_flow.
10965 * @param[in] rss_desc
10966 * Pointer to the mlx5_flow_rss_desc.
10969 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10970 struct mlx5_flow_rss_desc *rss_desc)
10972 uint64_t items = dev_flow->handle->layers;
10974 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10976 dev_flow->hash_fields = 0;
10977 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10978 if (rss_desc->level >= 2)
10981 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10982 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10983 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10984 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10985 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10986 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10987 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10989 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10991 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10992 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10993 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10994 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10995 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10996 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10997 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10999 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
11002 if (dev_flow->hash_fields == 0)
11004 * There is no match between the RSS types and the
11005 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11008 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11009 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
11010 if (rss_types & RTE_ETH_RSS_UDP) {
11011 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11012 dev_flow->hash_fields |=
11013 IBV_RX_HASH_SRC_PORT_UDP;
11014 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11015 dev_flow->hash_fields |=
11016 IBV_RX_HASH_DST_PORT_UDP;
11018 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
11020 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11021 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
11022 if (rss_types & RTE_ETH_RSS_TCP) {
11023 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11024 dev_flow->hash_fields |=
11025 IBV_RX_HASH_SRC_PORT_TCP;
11026 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11027 dev_flow->hash_fields |=
11028 IBV_RX_HASH_DST_PORT_TCP;
11030 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11034 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11038 * Prepare an Rx Hash queue.
11041 * Pointer to Ethernet device.
11042 * @param[in] dev_flow
11043 * Pointer to the mlx5_flow.
11044 * @param[in] rss_desc
11045 * Pointer to the mlx5_flow_rss_desc.
11046 * @param[out] hrxq_idx
11047 * Hash Rx queue index.
11050 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11052 static struct mlx5_hrxq *
11053 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11054 struct mlx5_flow *dev_flow,
11055 struct mlx5_flow_rss_desc *rss_desc,
11056 uint32_t *hrxq_idx)
11058 struct mlx5_priv *priv = dev->data->dev_private;
11059 struct mlx5_flow_handle *dh = dev_flow->handle;
11060 struct mlx5_hrxq *hrxq;
11062 MLX5_ASSERT(rss_desc->queue_num);
11063 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11064 rss_desc->hash_fields = dev_flow->hash_fields;
11065 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11066 rss_desc->shared_rss = 0;
11067 if (rss_desc->hash_fields == 0)
11068 rss_desc->queue_num = 1;
11069 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11072 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11078 * Release sample sub action resource.
11080 * @param[in, out] dev
11081 * Pointer to rte_eth_dev structure.
11082 * @param[in] act_res
11083 * Pointer to sample sub action resource.
11086 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11087 struct mlx5_flow_sub_actions_idx *act_res)
11089 if (act_res->rix_hrxq) {
11090 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11091 act_res->rix_hrxq = 0;
11093 if (act_res->rix_encap_decap) {
11094 flow_dv_encap_decap_resource_release(dev,
11095 act_res->rix_encap_decap);
11096 act_res->rix_encap_decap = 0;
11098 if (act_res->rix_port_id_action) {
11099 flow_dv_port_id_action_resource_release(dev,
11100 act_res->rix_port_id_action);
11101 act_res->rix_port_id_action = 0;
11103 if (act_res->rix_tag) {
11104 flow_dv_tag_release(dev, act_res->rix_tag);
11105 act_res->rix_tag = 0;
11107 if (act_res->rix_jump) {
11108 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11109 act_res->rix_jump = 0;
11114 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11115 struct mlx5_list_entry *entry, void *cb_ctx)
11117 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11118 struct rte_eth_dev *dev = ctx->dev;
11119 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11120 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11124 if (ctx_resource->ratio == resource->ratio &&
11125 ctx_resource->ft_type == resource->ft_type &&
11126 ctx_resource->ft_id == resource->ft_id &&
11127 ctx_resource->set_action == resource->set_action &&
11128 !memcmp((void *)&ctx_resource->sample_act,
11129 (void *)&resource->sample_act,
11130 sizeof(struct mlx5_flow_sub_actions_list))) {
11132 * Existing sample action should release the prepared
11133 * sub-actions reference counter.
11135 flow_dv_sample_sub_actions_release(dev,
11136 &ctx_resource->sample_idx);
11142 struct mlx5_list_entry *
11143 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11145 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11146 struct rte_eth_dev *dev = ctx->dev;
11147 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11148 void **sample_dv_actions = ctx_resource->sub_actions;
11149 struct mlx5_flow_dv_sample_resource *resource;
11150 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11151 struct mlx5_priv *priv = dev->data->dev_private;
11152 struct mlx5_dev_ctx_shared *sh = priv->sh;
11153 struct mlx5_flow_tbl_resource *tbl;
11155 const uint32_t next_ft_step = 1;
11156 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11157 uint8_t is_egress = 0;
11158 uint8_t is_transfer = 0;
11159 struct rte_flow_error *error = ctx->error;
11161 /* Register new sample resource. */
11162 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11164 rte_flow_error_set(error, ENOMEM,
11165 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11167 "cannot allocate resource memory");
11170 *resource = *ctx_resource;
11171 /* Create normal path table level */
11172 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11174 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11176 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11177 is_egress, is_transfer,
11178 true, NULL, 0, 0, 0, error);
11180 rte_flow_error_set(error, ENOMEM,
11181 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11183 "fail to create normal path table "
11187 resource->normal_path_tbl = tbl;
11188 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11189 if (!sh->default_miss_action) {
11190 rte_flow_error_set(error, ENOMEM,
11191 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11193 "default miss action was not "
11197 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11198 sh->default_miss_action;
11200 /* Create a DR sample action */
11201 sampler_attr.sample_ratio = resource->ratio;
11202 sampler_attr.default_next_table = tbl->obj;
11203 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11204 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11205 &sample_dv_actions[0];
11206 sampler_attr.action = resource->set_action;
11207 if (mlx5_os_flow_dr_create_flow_action_sampler
11208 (&sampler_attr, &resource->verbs_action)) {
11209 rte_flow_error_set(error, ENOMEM,
11210 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11211 NULL, "cannot create sample action");
11214 resource->idx = idx;
11215 resource->dev = dev;
11216 return &resource->entry;
11218 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11219 flow_dv_sample_sub_actions_release(dev,
11220 &resource->sample_idx);
11221 if (resource->normal_path_tbl)
11222 flow_dv_tbl_resource_release(MLX5_SH(dev),
11223 resource->normal_path_tbl);
11224 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11229 struct mlx5_list_entry *
11230 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11231 struct mlx5_list_entry *entry __rte_unused,
11234 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11235 struct rte_eth_dev *dev = ctx->dev;
11236 struct mlx5_flow_dv_sample_resource *resource;
11237 struct mlx5_priv *priv = dev->data->dev_private;
11238 struct mlx5_dev_ctx_shared *sh = priv->sh;
11241 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11243 rte_flow_error_set(ctx->error, ENOMEM,
11244 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11246 "cannot allocate resource memory");
11249 memcpy(resource, entry, sizeof(*resource));
11250 resource->idx = idx;
11251 resource->dev = dev;
11252 return &resource->entry;
11256 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11257 struct mlx5_list_entry *entry)
11259 struct mlx5_flow_dv_sample_resource *resource =
11260 container_of(entry, typeof(*resource), entry);
11261 struct rte_eth_dev *dev = resource->dev;
11262 struct mlx5_priv *priv = dev->data->dev_private;
11264 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11268 * Find existing sample resource or create and register a new one.
11270 * @param[in, out] dev
11271 * Pointer to rte_eth_dev structure.
11273 * Pointer to sample resource reference.
11274 * @parm[in, out] dev_flow
11275 * Pointer to the dev_flow.
11276 * @param[out] error
11277 * pointer to error structure.
11280 * 0 on success otherwise -errno and errno is set.
11283 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11284 struct mlx5_flow_dv_sample_resource *ref,
11285 struct mlx5_flow *dev_flow,
11286 struct rte_flow_error *error)
11288 struct mlx5_flow_dv_sample_resource *resource;
11289 struct mlx5_list_entry *entry;
11290 struct mlx5_priv *priv = dev->data->dev_private;
11291 struct mlx5_flow_cb_ctx ctx = {
11297 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11300 resource = container_of(entry, typeof(*resource), entry);
11301 dev_flow->handle->dvh.rix_sample = resource->idx;
11302 dev_flow->dv.sample_res = resource;
11307 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11308 struct mlx5_list_entry *entry, void *cb_ctx)
11310 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11311 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11312 struct rte_eth_dev *dev = ctx->dev;
11313 struct mlx5_flow_dv_dest_array_resource *resource =
11314 container_of(entry, typeof(*resource), entry);
11317 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11318 ctx_resource->ft_type == resource->ft_type &&
11319 !memcmp((void *)resource->sample_act,
11320 (void *)ctx_resource->sample_act,
11321 (ctx_resource->num_of_dest *
11322 sizeof(struct mlx5_flow_sub_actions_list)))) {
11324 * Existing sample action should release the prepared
11325 * sub-actions reference counter.
11327 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11328 flow_dv_sample_sub_actions_release(dev,
11329 &ctx_resource->sample_idx[idx]);
11335 struct mlx5_list_entry *
11336 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11338 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11339 struct rte_eth_dev *dev = ctx->dev;
11340 struct mlx5_flow_dv_dest_array_resource *resource;
11341 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11342 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11343 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11344 struct mlx5_priv *priv = dev->data->dev_private;
11345 struct mlx5_dev_ctx_shared *sh = priv->sh;
11346 struct mlx5_flow_sub_actions_list *sample_act;
11347 struct mlx5dv_dr_domain *domain;
11348 uint32_t idx = 0, res_idx = 0;
11349 struct rte_flow_error *error = ctx->error;
11350 uint64_t action_flags;
11353 /* Register new destination array resource. */
11354 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11357 rte_flow_error_set(error, ENOMEM,
11358 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11360 "cannot allocate resource memory");
11363 *resource = *ctx_resource;
11364 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11365 domain = sh->fdb_domain;
11366 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11367 domain = sh->rx_domain;
11369 domain = sh->tx_domain;
11370 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11371 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11372 mlx5_malloc(MLX5_MEM_ZERO,
11373 sizeof(struct mlx5dv_dr_action_dest_attr),
11375 if (!dest_attr[idx]) {
11376 rte_flow_error_set(error, ENOMEM,
11377 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11379 "cannot allocate resource memory");
11382 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11383 sample_act = &ctx_resource->sample_act[idx];
11384 action_flags = sample_act->action_flags;
11385 switch (action_flags) {
11386 case MLX5_FLOW_ACTION_QUEUE:
11387 dest_attr[idx]->dest = sample_act->dr_queue_action;
11389 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11390 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11391 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11392 dest_attr[idx]->dest_reformat->reformat =
11393 sample_act->dr_encap_action;
11394 dest_attr[idx]->dest_reformat->dest =
11395 sample_act->dr_port_id_action;
11397 case MLX5_FLOW_ACTION_PORT_ID:
11398 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11400 case MLX5_FLOW_ACTION_JUMP:
11401 dest_attr[idx]->dest = sample_act->dr_jump_action;
11404 rte_flow_error_set(error, EINVAL,
11405 RTE_FLOW_ERROR_TYPE_ACTION,
11407 "unsupported actions type");
11411 /* create a dest array actioin */
11412 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11414 resource->num_of_dest,
11416 &resource->action);
11418 rte_flow_error_set(error, ENOMEM,
11419 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11421 "cannot create destination array action");
11424 resource->idx = res_idx;
11425 resource->dev = dev;
11426 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11427 mlx5_free(dest_attr[idx]);
11428 return &resource->entry;
11430 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11431 flow_dv_sample_sub_actions_release(dev,
11432 &resource->sample_idx[idx]);
11433 if (dest_attr[idx])
11434 mlx5_free(dest_attr[idx]);
11436 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11440 struct mlx5_list_entry *
11441 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11442 struct mlx5_list_entry *entry __rte_unused,
11445 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11446 struct rte_eth_dev *dev = ctx->dev;
11447 struct mlx5_flow_dv_dest_array_resource *resource;
11448 struct mlx5_priv *priv = dev->data->dev_private;
11449 struct mlx5_dev_ctx_shared *sh = priv->sh;
11450 uint32_t res_idx = 0;
11451 struct rte_flow_error *error = ctx->error;
11453 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11456 rte_flow_error_set(error, ENOMEM,
11457 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11459 "cannot allocate dest-array memory");
11462 memcpy(resource, entry, sizeof(*resource));
11463 resource->idx = res_idx;
11464 resource->dev = dev;
11465 return &resource->entry;
11469 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11470 struct mlx5_list_entry *entry)
11472 struct mlx5_flow_dv_dest_array_resource *resource =
11473 container_of(entry, typeof(*resource), entry);
11474 struct rte_eth_dev *dev = resource->dev;
11475 struct mlx5_priv *priv = dev->data->dev_private;
11477 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11481 * Find existing destination array resource or create and register a new one.
11483 * @param[in, out] dev
11484 * Pointer to rte_eth_dev structure.
11486 * Pointer to destination array resource reference.
11487 * @parm[in, out] dev_flow
11488 * Pointer to the dev_flow.
11489 * @param[out] error
11490 * pointer to error structure.
11493 * 0 on success otherwise -errno and errno is set.
11496 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11497 struct mlx5_flow_dv_dest_array_resource *ref,
11498 struct mlx5_flow *dev_flow,
11499 struct rte_flow_error *error)
11501 struct mlx5_flow_dv_dest_array_resource *resource;
11502 struct mlx5_priv *priv = dev->data->dev_private;
11503 struct mlx5_list_entry *entry;
11504 struct mlx5_flow_cb_ctx ctx = {
11510 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11513 resource = container_of(entry, typeof(*resource), entry);
11514 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11515 dev_flow->dv.dest_array_res = resource;
11520 * Convert Sample action to DV specification.
11523 * Pointer to rte_eth_dev structure.
11524 * @param[in] action
11525 * Pointer to sample action structure.
11526 * @param[in, out] dev_flow
11527 * Pointer to the mlx5_flow.
11529 * Pointer to the flow attributes.
11530 * @param[in, out] num_of_dest
11531 * Pointer to the num of destination.
11532 * @param[in, out] sample_actions
11533 * Pointer to sample actions list.
11534 * @param[in, out] res
11535 * Pointer to sample resource.
11536 * @param[out] error
11537 * Pointer to the error structure.
11540 * 0 on success, a negative errno value otherwise and rte_errno is set.
11543 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11544 const struct rte_flow_action_sample *action,
11545 struct mlx5_flow *dev_flow,
11546 const struct rte_flow_attr *attr,
11547 uint32_t *num_of_dest,
11548 void **sample_actions,
11549 struct mlx5_flow_dv_sample_resource *res,
11550 struct rte_flow_error *error)
11552 struct mlx5_priv *priv = dev->data->dev_private;
11553 const struct rte_flow_action *sub_actions;
11554 struct mlx5_flow_sub_actions_list *sample_act;
11555 struct mlx5_flow_sub_actions_idx *sample_idx;
11556 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11557 struct rte_flow *flow = dev_flow->flow;
11558 struct mlx5_flow_rss_desc *rss_desc;
11559 uint64_t action_flags = 0;
11562 rss_desc = &wks->rss_desc;
11563 sample_act = &res->sample_act;
11564 sample_idx = &res->sample_idx;
11565 res->ratio = action->ratio;
11566 sub_actions = action->actions;
11567 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11568 int type = sub_actions->type;
11569 uint32_t pre_rix = 0;
11572 case RTE_FLOW_ACTION_TYPE_QUEUE:
11574 const struct rte_flow_action_queue *queue;
11575 struct mlx5_hrxq *hrxq;
11578 queue = sub_actions->conf;
11579 rss_desc->queue_num = 1;
11580 rss_desc->queue[0] = queue->index;
11581 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11582 rss_desc, &hrxq_idx);
11584 return rte_flow_error_set
11586 RTE_FLOW_ERROR_TYPE_ACTION,
11588 "cannot create fate queue");
11589 sample_act->dr_queue_action = hrxq->action;
11590 sample_idx->rix_hrxq = hrxq_idx;
11591 sample_actions[sample_act->actions_num++] =
11594 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11595 if (action_flags & MLX5_FLOW_ACTION_MARK)
11596 dev_flow->handle->rix_hrxq = hrxq_idx;
11597 dev_flow->handle->fate_action =
11598 MLX5_FLOW_FATE_QUEUE;
11601 case RTE_FLOW_ACTION_TYPE_RSS:
11603 struct mlx5_hrxq *hrxq;
11605 const struct rte_flow_action_rss *rss;
11606 const uint8_t *rss_key;
11608 rss = sub_actions->conf;
11609 memcpy(rss_desc->queue, rss->queue,
11610 rss->queue_num * sizeof(uint16_t));
11611 rss_desc->queue_num = rss->queue_num;
11612 /* NULL RSS key indicates default RSS key. */
11613 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11614 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11616 * rss->level and rss.types should be set in advance
11617 * when expanding items for RSS.
11619 flow_dv_hashfields_set(dev_flow, rss_desc);
11620 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11621 rss_desc, &hrxq_idx);
11623 return rte_flow_error_set
11625 RTE_FLOW_ERROR_TYPE_ACTION,
11627 "cannot create fate queue");
11628 sample_act->dr_queue_action = hrxq->action;
11629 sample_idx->rix_hrxq = hrxq_idx;
11630 sample_actions[sample_act->actions_num++] =
11633 action_flags |= MLX5_FLOW_ACTION_RSS;
11634 if (action_flags & MLX5_FLOW_ACTION_MARK)
11635 dev_flow->handle->rix_hrxq = hrxq_idx;
11636 dev_flow->handle->fate_action =
11637 MLX5_FLOW_FATE_QUEUE;
11640 case RTE_FLOW_ACTION_TYPE_MARK:
11642 uint32_t tag_be = mlx5_flow_mark_set
11643 (((const struct rte_flow_action_mark *)
11644 (sub_actions->conf))->id);
11646 dev_flow->handle->mark = 1;
11647 pre_rix = dev_flow->handle->dvh.rix_tag;
11648 /* Save the mark resource before sample */
11649 pre_r = dev_flow->dv.tag_resource;
11650 if (flow_dv_tag_resource_register(dev, tag_be,
11653 MLX5_ASSERT(dev_flow->dv.tag_resource);
11654 sample_act->dr_tag_action =
11655 dev_flow->dv.tag_resource->action;
11656 sample_idx->rix_tag =
11657 dev_flow->handle->dvh.rix_tag;
11658 sample_actions[sample_act->actions_num++] =
11659 sample_act->dr_tag_action;
11660 /* Recover the mark resource after sample */
11661 dev_flow->dv.tag_resource = pre_r;
11662 dev_flow->handle->dvh.rix_tag = pre_rix;
11663 action_flags |= MLX5_FLOW_ACTION_MARK;
11666 case RTE_FLOW_ACTION_TYPE_COUNT:
11668 if (!flow->counter) {
11670 flow_dv_translate_create_counter(dev,
11671 dev_flow, sub_actions->conf,
11673 if (!flow->counter)
11674 return rte_flow_error_set
11676 RTE_FLOW_ERROR_TYPE_ACTION,
11678 "cannot create counter"
11681 sample_act->dr_cnt_action =
11682 (flow_dv_counter_get_by_idx(dev,
11683 flow->counter, NULL))->action;
11684 sample_actions[sample_act->actions_num++] =
11685 sample_act->dr_cnt_action;
11686 action_flags |= MLX5_FLOW_ACTION_COUNT;
11689 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11690 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11692 struct mlx5_flow_dv_port_id_action_resource
11694 uint32_t port_id = 0;
11696 memset(&port_id_resource, 0, sizeof(port_id_resource));
11697 /* Save the port id resource before sample */
11698 pre_rix = dev_flow->handle->rix_port_id_action;
11699 pre_r = dev_flow->dv.port_id_action;
11700 if (flow_dv_translate_action_port_id(dev, sub_actions,
11703 port_id_resource.port_id = port_id;
11704 if (flow_dv_port_id_action_resource_register
11705 (dev, &port_id_resource, dev_flow, error))
11707 sample_act->dr_port_id_action =
11708 dev_flow->dv.port_id_action->action;
11709 sample_idx->rix_port_id_action =
11710 dev_flow->handle->rix_port_id_action;
11711 sample_actions[sample_act->actions_num++] =
11712 sample_act->dr_port_id_action;
11713 /* Recover the port id resource after sample */
11714 dev_flow->dv.port_id_action = pre_r;
11715 dev_flow->handle->rix_port_id_action = pre_rix;
11717 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11720 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11721 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11722 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11723 /* Save the encap resource before sample */
11724 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11725 pre_r = dev_flow->dv.encap_decap;
11726 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11731 sample_act->dr_encap_action =
11732 dev_flow->dv.encap_decap->action;
11733 sample_idx->rix_encap_decap =
11734 dev_flow->handle->dvh.rix_encap_decap;
11735 sample_actions[sample_act->actions_num++] =
11736 sample_act->dr_encap_action;
11737 /* Recover the encap resource after sample */
11738 dev_flow->dv.encap_decap = pre_r;
11739 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11740 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11743 return rte_flow_error_set(error, EINVAL,
11744 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11746 "Not support for sampler action");
11749 sample_act->action_flags = action_flags;
11750 res->ft_id = dev_flow->dv.group;
11751 if (attr->transfer) {
11753 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11754 uint64_t set_action;
11755 } action_ctx = { .set_action = 0 };
11757 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11758 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11759 MLX5_MODIFICATION_TYPE_SET);
11760 MLX5_SET(set_action_in, action_ctx.action_in, field,
11761 MLX5_MODI_META_REG_C_0);
11762 MLX5_SET(set_action_in, action_ctx.action_in, data,
11763 priv->vport_meta_tag);
11764 res->set_action = action_ctx.set_action;
11765 } else if (attr->ingress) {
11766 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11768 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11774 * Convert Sample action to DV specification.
11777 * Pointer to rte_eth_dev structure.
11778 * @param[in, out] dev_flow
11779 * Pointer to the mlx5_flow.
11780 * @param[in] num_of_dest
11781 * The num of destination.
11782 * @param[in, out] res
11783 * Pointer to sample resource.
11784 * @param[in, out] mdest_res
11785 * Pointer to destination array resource.
11786 * @param[in] sample_actions
11787 * Pointer to sample path actions list.
11788 * @param[in] action_flags
11789 * Holds the actions detected until now.
11790 * @param[out] error
11791 * Pointer to the error structure.
11794 * 0 on success, a negative errno value otherwise and rte_errno is set.
11797 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11798 struct mlx5_flow *dev_flow,
11799 uint32_t num_of_dest,
11800 struct mlx5_flow_dv_sample_resource *res,
11801 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11802 void **sample_actions,
11803 uint64_t action_flags,
11804 struct rte_flow_error *error)
11806 /* update normal path action resource into last index of array */
11807 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11808 struct mlx5_flow_sub_actions_list *sample_act =
11809 &mdest_res->sample_act[dest_index];
11810 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11811 struct mlx5_flow_rss_desc *rss_desc;
11812 uint32_t normal_idx = 0;
11813 struct mlx5_hrxq *hrxq;
11817 rss_desc = &wks->rss_desc;
11818 if (num_of_dest > 1) {
11819 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11820 /* Handle QP action for mirroring */
11821 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11822 rss_desc, &hrxq_idx);
11824 return rte_flow_error_set
11826 RTE_FLOW_ERROR_TYPE_ACTION,
11828 "cannot create rx queue");
11830 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11831 sample_act->dr_queue_action = hrxq->action;
11832 if (action_flags & MLX5_FLOW_ACTION_MARK)
11833 dev_flow->handle->rix_hrxq = hrxq_idx;
11834 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11836 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11838 mdest_res->sample_idx[dest_index].rix_encap_decap =
11839 dev_flow->handle->dvh.rix_encap_decap;
11840 sample_act->dr_encap_action =
11841 dev_flow->dv.encap_decap->action;
11842 dev_flow->handle->dvh.rix_encap_decap = 0;
11844 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11846 mdest_res->sample_idx[dest_index].rix_port_id_action =
11847 dev_flow->handle->rix_port_id_action;
11848 sample_act->dr_port_id_action =
11849 dev_flow->dv.port_id_action->action;
11850 dev_flow->handle->rix_port_id_action = 0;
11852 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11854 mdest_res->sample_idx[dest_index].rix_jump =
11855 dev_flow->handle->rix_jump;
11856 sample_act->dr_jump_action =
11857 dev_flow->dv.jump->action;
11858 dev_flow->handle->rix_jump = 0;
11860 sample_act->actions_num = normal_idx;
11861 /* update sample action resource into first index of array */
11862 mdest_res->ft_type = res->ft_type;
11863 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11864 sizeof(struct mlx5_flow_sub_actions_idx));
11865 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11866 sizeof(struct mlx5_flow_sub_actions_list));
11867 mdest_res->num_of_dest = num_of_dest;
11868 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11870 return rte_flow_error_set(error, EINVAL,
11871 RTE_FLOW_ERROR_TYPE_ACTION,
11872 NULL, "can't create sample "
11875 res->sub_actions = sample_actions;
11876 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11877 return rte_flow_error_set(error, EINVAL,
11878 RTE_FLOW_ERROR_TYPE_ACTION,
11880 "can't create sample action");
11886 * Remove an ASO age action from age actions list.
11889 * Pointer to the Ethernet device structure.
11891 * Pointer to the aso age action handler.
11894 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11895 struct mlx5_aso_age_action *age)
11897 struct mlx5_age_info *age_info;
11898 struct mlx5_age_param *age_param = &age->age_params;
11899 struct mlx5_priv *priv = dev->data->dev_private;
11900 uint16_t expected = AGE_CANDIDATE;
11902 age_info = GET_PORT_AGE_INFO(priv);
11903 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11904 AGE_FREE, false, __ATOMIC_RELAXED,
11905 __ATOMIC_RELAXED)) {
11907 * We need the lock even it is age timeout,
11908 * since age action may still in process.
11910 rte_spinlock_lock(&age_info->aged_sl);
11911 LIST_REMOVE(age, next);
11912 rte_spinlock_unlock(&age_info->aged_sl);
11913 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11918 * Release an ASO age action.
11921 * Pointer to the Ethernet device structure.
11922 * @param[in] age_idx
11923 * Index of ASO age action to release.
11925 * True if the release operation is during flow destroy operation.
11926 * False if the release operation is during action destroy operation.
11929 * 0 when age action was removed, otherwise the number of references.
11932 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11934 struct mlx5_priv *priv = dev->data->dev_private;
11935 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11936 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11937 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11940 flow_dv_aso_age_remove_from_age(dev, age);
11941 rte_spinlock_lock(&mng->free_sl);
11942 LIST_INSERT_HEAD(&mng->free, age, next);
11943 rte_spinlock_unlock(&mng->free_sl);
11949 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11952 * Pointer to the Ethernet device structure.
11955 * 0 on success, otherwise negative errno value and rte_errno is set.
11958 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11960 struct mlx5_priv *priv = dev->data->dev_private;
11961 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11962 void *old_pools = mng->pools;
11963 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11964 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11965 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11968 rte_errno = ENOMEM;
11972 memcpy(pools, old_pools,
11973 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11974 mlx5_free(old_pools);
11976 /* First ASO flow hit allocation - starting ASO data-path. */
11977 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11985 mng->pools = pools;
11990 * Create and initialize a new ASO aging pool.
11993 * Pointer to the Ethernet device structure.
11994 * @param[out] age_free
11995 * Where to put the pointer of a new age action.
11998 * The age actions pool pointer and @p age_free is set on success,
11999 * NULL otherwise and rte_errno is set.
12001 static struct mlx5_aso_age_pool *
12002 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12003 struct mlx5_aso_age_action **age_free)
12005 struct mlx5_priv *priv = dev->data->dev_private;
12006 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12007 struct mlx5_aso_age_pool *pool = NULL;
12008 struct mlx5_devx_obj *obj = NULL;
12011 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12012 priv->sh->cdev->pdn);
12014 rte_errno = ENODATA;
12015 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12018 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12020 claim_zero(mlx5_devx_cmd_destroy(obj));
12021 rte_errno = ENOMEM;
12024 pool->flow_hit_aso_obj = obj;
12025 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12026 rte_rwlock_write_lock(&mng->resize_rwl);
12027 pool->index = mng->next;
12028 /* Resize pools array if there is no room for the new pool in it. */
12029 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12030 claim_zero(mlx5_devx_cmd_destroy(obj));
12032 rte_rwlock_write_unlock(&mng->resize_rwl);
12035 mng->pools[pool->index] = pool;
12037 rte_rwlock_write_unlock(&mng->resize_rwl);
12038 /* Assign the first action in the new pool, the rest go to free list. */
12039 *age_free = &pool->actions[0];
12040 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12041 pool->actions[i].offset = i;
12042 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12048 * Allocate a ASO aging bit.
12051 * Pointer to the Ethernet device structure.
12052 * @param[out] error
12053 * Pointer to the error structure.
12056 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12059 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12061 struct mlx5_priv *priv = dev->data->dev_private;
12062 const struct mlx5_aso_age_pool *pool;
12063 struct mlx5_aso_age_action *age_free = NULL;
12064 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12067 /* Try to get the next free age action bit. */
12068 rte_spinlock_lock(&mng->free_sl);
12069 age_free = LIST_FIRST(&mng->free);
12071 LIST_REMOVE(age_free, next);
12072 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12073 rte_spinlock_unlock(&mng->free_sl);
12074 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12075 NULL, "failed to create ASO age pool");
12076 return 0; /* 0 is an error. */
12078 rte_spinlock_unlock(&mng->free_sl);
12079 pool = container_of
12080 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12081 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12083 if (!age_free->dr_action) {
12084 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12088 rte_flow_error_set(error, rte_errno,
12089 RTE_FLOW_ERROR_TYPE_ACTION,
12090 NULL, "failed to get reg_c "
12091 "for ASO flow hit");
12092 return 0; /* 0 is an error. */
12094 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12095 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12096 (priv->sh->rx_domain,
12097 pool->flow_hit_aso_obj->obj, age_free->offset,
12098 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12099 (reg_c - REG_C_0));
12100 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12101 if (!age_free->dr_action) {
12103 rte_spinlock_lock(&mng->free_sl);
12104 LIST_INSERT_HEAD(&mng->free, age_free, next);
12105 rte_spinlock_unlock(&mng->free_sl);
12106 rte_flow_error_set(error, rte_errno,
12107 RTE_FLOW_ERROR_TYPE_ACTION,
12108 NULL, "failed to create ASO "
12109 "flow hit action");
12110 return 0; /* 0 is an error. */
12113 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12114 return pool->index | ((age_free->offset + 1) << 16);
12118 * Initialize flow ASO age parameters.
12121 * Pointer to rte_eth_dev structure.
12122 * @param[in] age_idx
12123 * Index of ASO age action.
12124 * @param[in] context
12125 * Pointer to flow counter age context.
12126 * @param[in] timeout
12127 * Aging timeout in seconds.
12131 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12136 struct mlx5_aso_age_action *aso_age;
12138 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12139 MLX5_ASSERT(aso_age);
12140 aso_age->age_params.context = context;
12141 aso_age->age_params.timeout = timeout;
12142 aso_age->age_params.port_id = dev->data->port_id;
12143 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12145 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12150 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12151 const struct rte_flow_item_integrity *value,
12152 void *headers_m, void *headers_v)
12155 /* RTE l4_ok filter aggregates hardware l4_ok and
12156 * l4_checksum_ok filters.
12157 * Positive RTE l4_ok match requires hardware match on both L4
12158 * hardware integrity bits.
12159 * For negative match, check hardware l4_checksum_ok bit only,
12160 * because hardware sets that bit to 0 for all packets
12163 if (value->l4_ok) {
12164 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12165 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12167 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12168 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12171 if (mask->l4_csum_ok) {
12172 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12173 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12174 value->l4_csum_ok);
12179 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12180 const struct rte_flow_item_integrity *value,
12181 void *headers_m, void *headers_v, bool is_ipv4)
12184 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12185 * ipv4_csum_ok filters.
12186 * Positive RTE l3_ok match requires hardware match on both L3
12187 * hardware integrity bits.
12188 * For negative match, check hardware l3_csum_ok bit only,
12189 * because hardware sets that bit to 0 for all packets
12193 if (value->l3_ok) {
12194 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12196 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12199 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12200 ipv4_checksum_ok, 1);
12201 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12202 ipv4_checksum_ok, !!value->l3_ok);
12204 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12205 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12209 if (mask->ipv4_csum_ok) {
12210 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12211 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12212 value->ipv4_csum_ok);
12217 set_integrity_bits(void *headers_m, void *headers_v,
12218 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12220 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12221 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12223 /* Integrity bits validation cleared spec pointer */
12224 MLX5_ASSERT(spec != NULL);
12226 mask = &rte_flow_item_integrity_mask;
12227 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12229 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12233 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12235 struct rte_flow_item *integrity_items[2],
12236 uint64_t pattern_flags)
12238 void *headers_m, *headers_v;
12241 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12242 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12244 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12245 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12247 set_integrity_bits(headers_m, headers_v,
12248 integrity_items[1], is_l3_ip4);
12250 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12251 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12253 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12254 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12256 set_integrity_bits(headers_m, headers_v,
12257 integrity_items[0], is_l3_ip4);
12262 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12263 const struct rte_flow_item *integrity_items[2],
12264 uint64_t *last_item)
12266 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12268 /* integrity bits validation cleared spec pointer */
12269 MLX5_ASSERT(spec != NULL);
12270 if (spec->level > 1) {
12271 integrity_items[1] = item;
12272 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12274 integrity_items[0] = item;
12275 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12280 * Prepares DV flow counter with aging configuration.
12281 * Gets it by index when exists, creates a new one when doesn't.
12284 * Pointer to rte_eth_dev structure.
12285 * @param[in] dev_flow
12286 * Pointer to the mlx5_flow.
12287 * @param[in, out] flow
12288 * Pointer to the sub flow.
12290 * Pointer to the counter action configuration.
12292 * Pointer to the aging action configuration.
12293 * @param[out] error
12294 * Pointer to the error structure.
12297 * Pointer to the counter, NULL otherwise.
12299 static struct mlx5_flow_counter *
12300 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12301 struct mlx5_flow *dev_flow,
12302 struct rte_flow *flow,
12303 const struct rte_flow_action_count *count,
12304 const struct rte_flow_action_age *age,
12305 struct rte_flow_error *error)
12307 if (!flow->counter) {
12308 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12310 if (!flow->counter) {
12311 rte_flow_error_set(error, rte_errno,
12312 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12313 "cannot create counter object.");
12317 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12321 * Release an ASO CT action by its own device.
12324 * Pointer to the Ethernet device structure.
12326 * Index of ASO CT action to release.
12329 * 0 when CT action was removed, otherwise the number of references.
12332 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12334 struct mlx5_priv *priv = dev->data->dev_private;
12335 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12337 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12338 enum mlx5_aso_ct_state state =
12339 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12341 /* Cannot release when CT is in the ASO SQ. */
12342 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12344 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12346 if (ct->dr_action_orig) {
12347 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12348 claim_zero(mlx5_glue->destroy_flow_action
12349 (ct->dr_action_orig));
12351 ct->dr_action_orig = NULL;
12353 if (ct->dr_action_rply) {
12354 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12355 claim_zero(mlx5_glue->destroy_flow_action
12356 (ct->dr_action_rply));
12358 ct->dr_action_rply = NULL;
12360 /* Clear the state to free, no need in 1st allocation. */
12361 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12362 rte_spinlock_lock(&mng->ct_sl);
12363 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12364 rte_spinlock_unlock(&mng->ct_sl);
12370 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12371 struct rte_flow_error *error)
12373 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12374 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12375 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12378 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12379 if (dev->data->dev_started != 1)
12380 return rte_flow_error_set(error, EAGAIN,
12381 RTE_FLOW_ERROR_TYPE_ACTION,
12383 "Indirect CT action cannot be destroyed when the port is stopped");
12384 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12386 return rte_flow_error_set(error, EAGAIN,
12387 RTE_FLOW_ERROR_TYPE_ACTION,
12389 "Current state prevents indirect CT action from being destroyed");
12394 * Resize the ASO CT pools array by 64 pools.
12397 * Pointer to the Ethernet device structure.
12400 * 0 on success, otherwise negative errno value and rte_errno is set.
12403 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12405 struct mlx5_priv *priv = dev->data->dev_private;
12406 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12407 void *old_pools = mng->pools;
12408 /* Magic number now, need a macro. */
12409 uint32_t resize = mng->n + 64;
12410 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12411 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12414 rte_errno = ENOMEM;
12417 rte_rwlock_write_lock(&mng->resize_rwl);
12418 /* ASO SQ/QP was already initialized in the startup. */
12420 /* Realloc could be an alternative choice. */
12421 rte_memcpy(pools, old_pools,
12422 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12423 mlx5_free(old_pools);
12426 mng->pools = pools;
12427 rte_rwlock_write_unlock(&mng->resize_rwl);
12432 * Create and initialize a new ASO CT pool.
12435 * Pointer to the Ethernet device structure.
12436 * @param[out] ct_free
12437 * Where to put the pointer of a new CT action.
12440 * The CT actions pool pointer and @p ct_free is set on success,
12441 * NULL otherwise and rte_errno is set.
12443 static struct mlx5_aso_ct_pool *
12444 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12445 struct mlx5_aso_ct_action **ct_free)
12447 struct mlx5_priv *priv = dev->data->dev_private;
12448 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12449 struct mlx5_aso_ct_pool *pool = NULL;
12450 struct mlx5_devx_obj *obj = NULL;
12452 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12454 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12455 priv->sh->cdev->pdn,
12458 rte_errno = ENODATA;
12459 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12462 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12464 rte_errno = ENOMEM;
12465 claim_zero(mlx5_devx_cmd_destroy(obj));
12468 pool->devx_obj = obj;
12469 pool->index = mng->next;
12470 /* Resize pools array if there is no room for the new pool in it. */
12471 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12472 claim_zero(mlx5_devx_cmd_destroy(obj));
12476 mng->pools[pool->index] = pool;
12478 /* Assign the first action in the new pool, the rest go to free list. */
12479 *ct_free = &pool->actions[0];
12480 /* Lock outside, the list operation is safe here. */
12481 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12482 /* refcnt is 0 when allocating the memory. */
12483 pool->actions[i].offset = i;
12484 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12490 * Allocate a ASO CT action from free list.
12493 * Pointer to the Ethernet device structure.
12494 * @param[out] error
12495 * Pointer to the error structure.
12498 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12501 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12503 struct mlx5_priv *priv = dev->data->dev_private;
12504 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12505 struct mlx5_aso_ct_action *ct = NULL;
12506 struct mlx5_aso_ct_pool *pool;
12511 if (!priv->sh->devx) {
12512 rte_errno = ENOTSUP;
12515 /* Get a free CT action, if no, a new pool will be created. */
12516 rte_spinlock_lock(&mng->ct_sl);
12517 ct = LIST_FIRST(&mng->free_cts);
12519 LIST_REMOVE(ct, next);
12520 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12521 rte_spinlock_unlock(&mng->ct_sl);
12522 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12523 NULL, "failed to create ASO CT pool");
12526 rte_spinlock_unlock(&mng->ct_sl);
12527 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12528 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12529 /* 0: inactive, 1: created, 2+: used by flows. */
12530 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12531 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12532 if (!ct->dr_action_orig) {
12533 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12534 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12535 (priv->sh->rx_domain, pool->devx_obj->obj,
12537 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12540 RTE_SET_USED(reg_c);
12542 if (!ct->dr_action_orig) {
12543 flow_dv_aso_ct_dev_release(dev, ct_idx);
12544 rte_flow_error_set(error, rte_errno,
12545 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12546 "failed to create ASO CT action");
12550 if (!ct->dr_action_rply) {
12551 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12552 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12553 (priv->sh->rx_domain, pool->devx_obj->obj,
12555 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12558 if (!ct->dr_action_rply) {
12559 flow_dv_aso_ct_dev_release(dev, ct_idx);
12560 rte_flow_error_set(error, rte_errno,
12561 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12562 "failed to create ASO CT action");
12570 * Create a conntrack object with context and actions by using ASO mechanism.
12573 * Pointer to rte_eth_dev structure.
12575 * Pointer to conntrack information profile.
12576 * @param[out] error
12577 * Pointer to the error structure.
12580 * Index to conntrack object on success, 0 otherwise.
12583 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12584 const struct rte_flow_action_conntrack *pro,
12585 struct rte_flow_error *error)
12587 struct mlx5_priv *priv = dev->data->dev_private;
12588 struct mlx5_dev_ctx_shared *sh = priv->sh;
12589 struct mlx5_aso_ct_action *ct;
12592 if (!sh->ct_aso_en)
12593 return rte_flow_error_set(error, ENOTSUP,
12594 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12595 "Connection is not supported");
12596 idx = flow_dv_aso_ct_alloc(dev, error);
12598 return rte_flow_error_set(error, rte_errno,
12599 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12600 "Failed to allocate CT object");
12601 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12602 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12603 return rte_flow_error_set(error, EBUSY,
12604 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12605 "Failed to update CT");
12606 ct->is_original = !!pro->is_original_dir;
12607 ct->peer = pro->peer_port;
12612 * Fill the flow with DV spec, lock free
12613 * (mutex should be acquired by caller).
12616 * Pointer to rte_eth_dev structure.
12617 * @param[in, out] dev_flow
12618 * Pointer to the sub flow.
12620 * Pointer to the flow attributes.
12622 * Pointer to the list of items.
12623 * @param[in] actions
12624 * Pointer to the list of actions.
12625 * @param[out] error
12626 * Pointer to the error structure.
12629 * 0 on success, a negative errno value otherwise and rte_errno is set.
12632 flow_dv_translate(struct rte_eth_dev *dev,
12633 struct mlx5_flow *dev_flow,
12634 const struct rte_flow_attr *attr,
12635 const struct rte_flow_item items[],
12636 const struct rte_flow_action actions[],
12637 struct rte_flow_error *error)
12639 struct mlx5_priv *priv = dev->data->dev_private;
12640 struct mlx5_dev_config *dev_conf = &priv->config;
12641 struct rte_flow *flow = dev_flow->flow;
12642 struct mlx5_flow_handle *handle = dev_flow->handle;
12643 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12644 struct mlx5_flow_rss_desc *rss_desc;
12645 uint64_t item_flags = 0;
12646 uint64_t last_item = 0;
12647 uint64_t action_flags = 0;
12648 struct mlx5_flow_dv_matcher matcher = {
12650 .size = sizeof(matcher.mask.buf),
12654 bool actions_end = false;
12656 struct mlx5_flow_dv_modify_hdr_resource res;
12657 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12658 sizeof(struct mlx5_modification_cmd) *
12659 (MLX5_MAX_MODIFY_NUM + 1)];
12661 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12662 const struct rte_flow_action_count *count = NULL;
12663 const struct rte_flow_action_age *non_shared_age = NULL;
12664 union flow_dv_attr flow_attr = { .attr = 0 };
12666 union mlx5_flow_tbl_key tbl_key;
12667 uint32_t modify_action_position = UINT32_MAX;
12668 void *match_mask = matcher.mask.buf;
12669 void *match_value = dev_flow->dv.value.buf;
12670 uint8_t next_protocol = 0xff;
12671 struct rte_vlan_hdr vlan = { 0 };
12672 struct mlx5_flow_dv_dest_array_resource mdest_res;
12673 struct mlx5_flow_dv_sample_resource sample_res;
12674 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12675 const struct rte_flow_action_sample *sample = NULL;
12676 struct mlx5_flow_sub_actions_list *sample_act;
12677 uint32_t sample_act_pos = UINT32_MAX;
12678 uint32_t age_act_pos = UINT32_MAX;
12679 uint32_t num_of_dest = 0;
12680 int tmp_actions_n = 0;
12683 const struct mlx5_flow_tunnel *tunnel = NULL;
12684 struct flow_grp_info grp_info = {
12685 .external = !!dev_flow->external,
12686 .transfer = !!attr->transfer,
12687 .fdb_def_rule = !!priv->fdb_def_rule,
12688 .skip_scale = dev_flow->skip_scale &
12689 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12690 .std_tbl_fix = true,
12692 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12693 const struct rte_flow_item *tunnel_item = NULL;
12696 return rte_flow_error_set(error, ENOMEM,
12697 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12699 "failed to push flow workspace");
12700 rss_desc = &wks->rss_desc;
12701 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12702 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12703 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12704 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12705 /* update normal path action resource into last index of array */
12706 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12707 if (is_tunnel_offload_active(dev)) {
12708 if (dev_flow->tunnel) {
12709 RTE_VERIFY(dev_flow->tof_type ==
12710 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12711 tunnel = dev_flow->tunnel;
12713 tunnel = mlx5_get_tof(items, actions,
12714 &dev_flow->tof_type);
12715 dev_flow->tunnel = tunnel;
12717 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12718 (dev, attr, tunnel, dev_flow->tof_type);
12720 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12721 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12722 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12726 dev_flow->dv.group = table;
12727 if (attr->transfer)
12728 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12729 /* number of actions must be set to 0 in case of dirty stack. */
12730 mhdr_res->actions_num = 0;
12731 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12733 * do not add decap action if match rule drops packet
12734 * HW rejects rules with decap & drop
12736 * if tunnel match rule was inserted before matching tunnel set
12737 * rule flow table used in the match rule must be registered.
12738 * current implementation handles that in the
12739 * flow_dv_match_register() at the function end.
12741 bool add_decap = true;
12742 const struct rte_flow_action *ptr = actions;
12744 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12745 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12751 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12755 dev_flow->dv.actions[actions_n++] =
12756 dev_flow->dv.encap_decap->action;
12757 action_flags |= MLX5_FLOW_ACTION_DECAP;
12760 for (; !actions_end ; actions++) {
12761 const struct rte_flow_action_queue *queue;
12762 const struct rte_flow_action_rss *rss;
12763 const struct rte_flow_action *action = actions;
12764 const uint8_t *rss_key;
12765 struct mlx5_flow_tbl_resource *tbl;
12766 struct mlx5_aso_age_action *age_act;
12767 struct mlx5_flow_counter *cnt_act;
12768 uint32_t port_id = 0;
12769 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12770 int action_type = actions->type;
12771 const struct rte_flow_action *found_action = NULL;
12772 uint32_t jump_group = 0;
12773 uint32_t owner_idx;
12774 struct mlx5_aso_ct_action *ct;
12776 if (!mlx5_flow_os_action_supported(action_type))
12777 return rte_flow_error_set(error, ENOTSUP,
12778 RTE_FLOW_ERROR_TYPE_ACTION,
12780 "action not supported");
12781 switch (action_type) {
12782 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12783 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12785 case RTE_FLOW_ACTION_TYPE_VOID:
12787 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12788 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12789 if (flow_dv_translate_action_port_id(dev, action,
12792 port_id_resource.port_id = port_id;
12793 MLX5_ASSERT(!handle->rix_port_id_action);
12794 if (flow_dv_port_id_action_resource_register
12795 (dev, &port_id_resource, dev_flow, error))
12797 dev_flow->dv.actions[actions_n++] =
12798 dev_flow->dv.port_id_action->action;
12799 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12800 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12801 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12804 case RTE_FLOW_ACTION_TYPE_FLAG:
12805 action_flags |= MLX5_FLOW_ACTION_FLAG;
12806 dev_flow->handle->mark = 1;
12807 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12808 struct rte_flow_action_mark mark = {
12809 .id = MLX5_FLOW_MARK_DEFAULT,
12812 if (flow_dv_convert_action_mark(dev, &mark,
12816 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12819 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12821 * Only one FLAG or MARK is supported per device flow
12822 * right now. So the pointer to the tag resource must be
12823 * zero before the register process.
12825 MLX5_ASSERT(!handle->dvh.rix_tag);
12826 if (flow_dv_tag_resource_register(dev, tag_be,
12829 MLX5_ASSERT(dev_flow->dv.tag_resource);
12830 dev_flow->dv.actions[actions_n++] =
12831 dev_flow->dv.tag_resource->action;
12833 case RTE_FLOW_ACTION_TYPE_MARK:
12834 action_flags |= MLX5_FLOW_ACTION_MARK;
12835 dev_flow->handle->mark = 1;
12836 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12837 const struct rte_flow_action_mark *mark =
12838 (const struct rte_flow_action_mark *)
12841 if (flow_dv_convert_action_mark(dev, mark,
12845 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12849 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12850 /* Legacy (non-extensive) MARK action. */
12851 tag_be = mlx5_flow_mark_set
12852 (((const struct rte_flow_action_mark *)
12853 (actions->conf))->id);
12854 MLX5_ASSERT(!handle->dvh.rix_tag);
12855 if (flow_dv_tag_resource_register(dev, tag_be,
12858 MLX5_ASSERT(dev_flow->dv.tag_resource);
12859 dev_flow->dv.actions[actions_n++] =
12860 dev_flow->dv.tag_resource->action;
12862 case RTE_FLOW_ACTION_TYPE_SET_META:
12863 if (flow_dv_convert_action_set_meta
12864 (dev, mhdr_res, attr,
12865 (const struct rte_flow_action_set_meta *)
12866 actions->conf, error))
12868 action_flags |= MLX5_FLOW_ACTION_SET_META;
12870 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12871 if (flow_dv_convert_action_set_tag
12873 (const struct rte_flow_action_set_tag *)
12874 actions->conf, error))
12876 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12878 case RTE_FLOW_ACTION_TYPE_DROP:
12879 action_flags |= MLX5_FLOW_ACTION_DROP;
12880 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12882 case RTE_FLOW_ACTION_TYPE_QUEUE:
12883 queue = actions->conf;
12884 rss_desc->queue_num = 1;
12885 rss_desc->queue[0] = queue->index;
12886 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12887 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12888 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12891 case RTE_FLOW_ACTION_TYPE_RSS:
12892 rss = actions->conf;
12893 memcpy(rss_desc->queue, rss->queue,
12894 rss->queue_num * sizeof(uint16_t));
12895 rss_desc->queue_num = rss->queue_num;
12896 /* NULL RSS key indicates default RSS key. */
12897 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12898 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12900 * rss->level and rss.types should be set in advance
12901 * when expanding items for RSS.
12903 action_flags |= MLX5_FLOW_ACTION_RSS;
12904 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12905 MLX5_FLOW_FATE_SHARED_RSS :
12906 MLX5_FLOW_FATE_QUEUE;
12908 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12909 owner_idx = (uint32_t)(uintptr_t)action->conf;
12910 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12911 if (flow->age == 0) {
12912 flow->age = owner_idx;
12913 __atomic_fetch_add(&age_act->refcnt, 1,
12916 age_act_pos = actions_n++;
12917 action_flags |= MLX5_FLOW_ACTION_AGE;
12919 case RTE_FLOW_ACTION_TYPE_AGE:
12920 non_shared_age = action->conf;
12921 age_act_pos = actions_n++;
12922 action_flags |= MLX5_FLOW_ACTION_AGE;
12924 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12925 owner_idx = (uint32_t)(uintptr_t)action->conf;
12926 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12928 MLX5_ASSERT(cnt_act != NULL);
12930 * When creating meter drop flow in drop table, the
12931 * counter should not overwrite the rte flow counter.
12933 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12934 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12935 dev_flow->dv.actions[actions_n++] =
12938 if (flow->counter == 0) {
12939 flow->counter = owner_idx;
12941 (&cnt_act->shared_info.refcnt,
12942 1, __ATOMIC_RELAXED);
12944 /* Save information first, will apply later. */
12945 action_flags |= MLX5_FLOW_ACTION_COUNT;
12948 case RTE_FLOW_ACTION_TYPE_COUNT:
12949 if (!priv->sh->devx) {
12950 return rte_flow_error_set
12952 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12954 "count action not supported");
12956 /* Save information first, will apply later. */
12957 count = action->conf;
12958 action_flags |= MLX5_FLOW_ACTION_COUNT;
12960 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12961 dev_flow->dv.actions[actions_n++] =
12962 priv->sh->pop_vlan_action;
12963 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12965 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12966 if (!(action_flags &
12967 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12968 flow_dev_get_vlan_info_from_items(items, &vlan);
12969 vlan.eth_proto = rte_be_to_cpu_16
12970 ((((const struct rte_flow_action_of_push_vlan *)
12971 actions->conf)->ethertype));
12972 found_action = mlx5_flow_find_action
12974 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12976 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12977 found_action = mlx5_flow_find_action
12979 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12981 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12982 if (flow_dv_create_action_push_vlan
12983 (dev, attr, &vlan, dev_flow, error))
12985 dev_flow->dv.actions[actions_n++] =
12986 dev_flow->dv.push_vlan_res->action;
12987 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12989 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12990 /* of_vlan_push action handled this action */
12991 MLX5_ASSERT(action_flags &
12992 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12994 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12995 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12997 flow_dev_get_vlan_info_from_items(items, &vlan);
12998 mlx5_update_vlan_vid_pcp(actions, &vlan);
12999 /* If no VLAN push - this is a modify header action */
13000 if (flow_dv_convert_action_modify_vlan_vid
13001 (mhdr_res, actions, error))
13003 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13005 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13006 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13007 if (flow_dv_create_action_l2_encap(dev, actions,
13012 dev_flow->dv.actions[actions_n++] =
13013 dev_flow->dv.encap_decap->action;
13014 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13015 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13016 sample_act->action_flags |=
13017 MLX5_FLOW_ACTION_ENCAP;
13019 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13020 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13021 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13025 dev_flow->dv.actions[actions_n++] =
13026 dev_flow->dv.encap_decap->action;
13027 action_flags |= MLX5_FLOW_ACTION_DECAP;
13029 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13030 /* Handle encap with preceding decap. */
13031 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13032 if (flow_dv_create_action_raw_encap
13033 (dev, actions, dev_flow, attr, error))
13035 dev_flow->dv.actions[actions_n++] =
13036 dev_flow->dv.encap_decap->action;
13038 /* Handle encap without preceding decap. */
13039 if (flow_dv_create_action_l2_encap
13040 (dev, actions, dev_flow, attr->transfer,
13043 dev_flow->dv.actions[actions_n++] =
13044 dev_flow->dv.encap_decap->action;
13046 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13047 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13048 sample_act->action_flags |=
13049 MLX5_FLOW_ACTION_ENCAP;
13051 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13052 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13054 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13055 if (flow_dv_create_action_l2_decap
13056 (dev, dev_flow, attr->transfer, error))
13058 dev_flow->dv.actions[actions_n++] =
13059 dev_flow->dv.encap_decap->action;
13061 /* If decap is followed by encap, handle it at encap. */
13062 action_flags |= MLX5_FLOW_ACTION_DECAP;
13064 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13065 dev_flow->dv.actions[actions_n++] =
13066 (void *)(uintptr_t)action->conf;
13067 action_flags |= MLX5_FLOW_ACTION_JUMP;
13069 case RTE_FLOW_ACTION_TYPE_JUMP:
13070 jump_group = ((const struct rte_flow_action_jump *)
13071 action->conf)->group;
13072 grp_info.std_tbl_fix = 0;
13073 if (dev_flow->skip_scale &
13074 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13075 grp_info.skip_scale = 1;
13077 grp_info.skip_scale = 0;
13078 ret = mlx5_flow_group_to_table(dev, tunnel,
13084 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13086 !!dev_flow->external,
13087 tunnel, jump_group, 0,
13090 return rte_flow_error_set
13092 RTE_FLOW_ERROR_TYPE_ACTION,
13094 "cannot create jump action.");
13095 if (flow_dv_jump_tbl_resource_register
13096 (dev, tbl, dev_flow, error)) {
13097 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13098 return rte_flow_error_set
13100 RTE_FLOW_ERROR_TYPE_ACTION,
13102 "cannot create jump action.");
13104 dev_flow->dv.actions[actions_n++] =
13105 dev_flow->dv.jump->action;
13106 action_flags |= MLX5_FLOW_ACTION_JUMP;
13107 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13108 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13111 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13112 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13113 if (flow_dv_convert_action_modify_mac
13114 (mhdr_res, actions, error))
13116 action_flags |= actions->type ==
13117 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13118 MLX5_FLOW_ACTION_SET_MAC_SRC :
13119 MLX5_FLOW_ACTION_SET_MAC_DST;
13121 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13122 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13123 if (flow_dv_convert_action_modify_ipv4
13124 (mhdr_res, actions, error))
13126 action_flags |= actions->type ==
13127 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13128 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13129 MLX5_FLOW_ACTION_SET_IPV4_DST;
13131 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13132 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13133 if (flow_dv_convert_action_modify_ipv6
13134 (mhdr_res, actions, error))
13136 action_flags |= actions->type ==
13137 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13138 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13139 MLX5_FLOW_ACTION_SET_IPV6_DST;
13141 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13142 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13143 if (flow_dv_convert_action_modify_tp
13144 (mhdr_res, actions, items,
13145 &flow_attr, dev_flow, !!(action_flags &
13146 MLX5_FLOW_ACTION_DECAP), error))
13148 action_flags |= actions->type ==
13149 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13150 MLX5_FLOW_ACTION_SET_TP_SRC :
13151 MLX5_FLOW_ACTION_SET_TP_DST;
13153 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13154 if (flow_dv_convert_action_modify_dec_ttl
13155 (mhdr_res, items, &flow_attr, dev_flow,
13157 MLX5_FLOW_ACTION_DECAP), error))
13159 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13161 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13162 if (flow_dv_convert_action_modify_ttl
13163 (mhdr_res, actions, items, &flow_attr,
13164 dev_flow, !!(action_flags &
13165 MLX5_FLOW_ACTION_DECAP), error))
13167 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13169 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13170 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13171 if (flow_dv_convert_action_modify_tcp_seq
13172 (mhdr_res, actions, error))
13174 action_flags |= actions->type ==
13175 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13176 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13177 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13180 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13181 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13182 if (flow_dv_convert_action_modify_tcp_ack
13183 (mhdr_res, actions, error))
13185 action_flags |= actions->type ==
13186 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13187 MLX5_FLOW_ACTION_INC_TCP_ACK :
13188 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13190 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13191 if (flow_dv_convert_action_set_reg
13192 (mhdr_res, actions, error))
13194 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13196 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13197 if (flow_dv_convert_action_copy_mreg
13198 (dev, mhdr_res, actions, error))
13200 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13202 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13203 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13204 dev_flow->handle->fate_action =
13205 MLX5_FLOW_FATE_DEFAULT_MISS;
13207 case RTE_FLOW_ACTION_TYPE_METER:
13209 return rte_flow_error_set(error, rte_errno,
13210 RTE_FLOW_ERROR_TYPE_ACTION,
13211 NULL, "Failed to get meter in flow.");
13212 /* Set the meter action. */
13213 dev_flow->dv.actions[actions_n++] =
13214 wks->fm->meter_action;
13215 action_flags |= MLX5_FLOW_ACTION_METER;
13217 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13218 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13221 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13223 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13224 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13227 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13229 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13230 sample_act_pos = actions_n;
13231 sample = (const struct rte_flow_action_sample *)
13234 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13235 /* put encap action into group if work with port id */
13236 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13237 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13238 sample_act->action_flags |=
13239 MLX5_FLOW_ACTION_ENCAP;
13241 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13242 if (flow_dv_convert_action_modify_field
13243 (dev, mhdr_res, actions, attr, error))
13245 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13247 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13248 owner_idx = (uint32_t)(uintptr_t)action->conf;
13249 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13251 return rte_flow_error_set(error, EINVAL,
13252 RTE_FLOW_ERROR_TYPE_ACTION,
13254 "Failed to get CT object.");
13255 if (mlx5_aso_ct_available(priv->sh, ct))
13256 return rte_flow_error_set(error, rte_errno,
13257 RTE_FLOW_ERROR_TYPE_ACTION,
13259 "CT is unavailable.");
13260 if (ct->is_original)
13261 dev_flow->dv.actions[actions_n] =
13262 ct->dr_action_orig;
13264 dev_flow->dv.actions[actions_n] =
13265 ct->dr_action_rply;
13266 if (flow->ct == 0) {
13267 flow->indirect_type =
13268 MLX5_INDIRECT_ACTION_TYPE_CT;
13269 flow->ct = owner_idx;
13270 __atomic_fetch_add(&ct->refcnt, 1,
13274 action_flags |= MLX5_FLOW_ACTION_CT;
13276 case RTE_FLOW_ACTION_TYPE_END:
13277 actions_end = true;
13278 if (mhdr_res->actions_num) {
13279 /* create modify action if needed. */
13280 if (flow_dv_modify_hdr_resource_register
13281 (dev, mhdr_res, dev_flow, error))
13283 dev_flow->dv.actions[modify_action_position] =
13284 handle->dvh.modify_hdr->action;
13287 * Handle AGE and COUNT action by single HW counter
13288 * when they are not shared.
13290 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13291 if ((non_shared_age && count) ||
13292 !(priv->sh->flow_hit_aso_en &&
13293 (attr->group || attr->transfer))) {
13294 /* Creates age by counters. */
13295 cnt_act = flow_dv_prepare_counter
13302 dev_flow->dv.actions[age_act_pos] =
13306 if (!flow->age && non_shared_age) {
13307 flow->age = flow_dv_aso_age_alloc
13311 flow_dv_aso_age_params_init
13313 non_shared_age->context ?
13314 non_shared_age->context :
13315 (void *)(uintptr_t)
13316 (dev_flow->flow_idx),
13317 non_shared_age->timeout);
13319 age_act = flow_aso_age_get_by_idx(dev,
13321 dev_flow->dv.actions[age_act_pos] =
13322 age_act->dr_action;
13324 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13326 * Create one count action, to be used
13327 * by all sub-flows.
13329 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13334 dev_flow->dv.actions[actions_n++] =
13340 if (mhdr_res->actions_num &&
13341 modify_action_position == UINT32_MAX)
13342 modify_action_position = actions_n++;
13344 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13345 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13346 int item_type = items->type;
13348 if (!mlx5_flow_os_item_supported(item_type))
13349 return rte_flow_error_set(error, ENOTSUP,
13350 RTE_FLOW_ERROR_TYPE_ITEM,
13351 NULL, "item not supported");
13352 switch (item_type) {
13353 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13354 flow_dv_translate_item_port_id
13355 (dev, match_mask, match_value, items, attr);
13356 last_item = MLX5_FLOW_ITEM_PORT_ID;
13358 case RTE_FLOW_ITEM_TYPE_ETH:
13359 flow_dv_translate_item_eth(match_mask, match_value,
13361 dev_flow->dv.group);
13362 matcher.priority = action_flags &
13363 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13364 !dev_flow->external ?
13365 MLX5_PRIORITY_MAP_L3 :
13366 MLX5_PRIORITY_MAP_L2;
13367 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13368 MLX5_FLOW_LAYER_OUTER_L2;
13370 case RTE_FLOW_ITEM_TYPE_VLAN:
13371 flow_dv_translate_item_vlan(dev_flow,
13372 match_mask, match_value,
13374 dev_flow->dv.group);
13375 matcher.priority = MLX5_PRIORITY_MAP_L2;
13376 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13377 MLX5_FLOW_LAYER_INNER_VLAN) :
13378 (MLX5_FLOW_LAYER_OUTER_L2 |
13379 MLX5_FLOW_LAYER_OUTER_VLAN);
13381 case RTE_FLOW_ITEM_TYPE_IPV4:
13382 mlx5_flow_tunnel_ip_check(items, next_protocol,
13383 &item_flags, &tunnel);
13384 flow_dv_translate_item_ipv4(match_mask, match_value,
13386 dev_flow->dv.group);
13387 matcher.priority = MLX5_PRIORITY_MAP_L3;
13388 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13389 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13390 if (items->mask != NULL &&
13391 ((const struct rte_flow_item_ipv4 *)
13392 items->mask)->hdr.next_proto_id) {
13394 ((const struct rte_flow_item_ipv4 *)
13395 (items->spec))->hdr.next_proto_id;
13397 ((const struct rte_flow_item_ipv4 *)
13398 (items->mask))->hdr.next_proto_id;
13400 /* Reset for inner layer. */
13401 next_protocol = 0xff;
13404 case RTE_FLOW_ITEM_TYPE_IPV6:
13405 mlx5_flow_tunnel_ip_check(items, next_protocol,
13406 &item_flags, &tunnel);
13407 flow_dv_translate_item_ipv6(match_mask, match_value,
13409 dev_flow->dv.group);
13410 matcher.priority = MLX5_PRIORITY_MAP_L3;
13411 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13412 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13413 if (items->mask != NULL &&
13414 ((const struct rte_flow_item_ipv6 *)
13415 items->mask)->hdr.proto) {
13417 ((const struct rte_flow_item_ipv6 *)
13418 items->spec)->hdr.proto;
13420 ((const struct rte_flow_item_ipv6 *)
13421 items->mask)->hdr.proto;
13423 /* Reset for inner layer. */
13424 next_protocol = 0xff;
13427 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13428 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13431 last_item = tunnel ?
13432 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13433 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13434 if (items->mask != NULL &&
13435 ((const struct rte_flow_item_ipv6_frag_ext *)
13436 items->mask)->hdr.next_header) {
13438 ((const struct rte_flow_item_ipv6_frag_ext *)
13439 items->spec)->hdr.next_header;
13441 ((const struct rte_flow_item_ipv6_frag_ext *)
13442 items->mask)->hdr.next_header;
13444 /* Reset for inner layer. */
13445 next_protocol = 0xff;
13448 case RTE_FLOW_ITEM_TYPE_TCP:
13449 flow_dv_translate_item_tcp(match_mask, match_value,
13451 matcher.priority = MLX5_PRIORITY_MAP_L4;
13452 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13453 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13455 case RTE_FLOW_ITEM_TYPE_UDP:
13456 flow_dv_translate_item_udp(match_mask, match_value,
13458 matcher.priority = MLX5_PRIORITY_MAP_L4;
13459 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13460 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13462 case RTE_FLOW_ITEM_TYPE_GRE:
13463 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13464 last_item = MLX5_FLOW_LAYER_GRE;
13465 tunnel_item = items;
13467 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13468 flow_dv_translate_item_gre_key(match_mask,
13469 match_value, items);
13470 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13472 case RTE_FLOW_ITEM_TYPE_NVGRE:
13473 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13474 last_item = MLX5_FLOW_LAYER_GRE;
13475 tunnel_item = items;
13477 case RTE_FLOW_ITEM_TYPE_VXLAN:
13478 flow_dv_translate_item_vxlan(dev, attr,
13479 match_mask, match_value,
13481 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13482 last_item = MLX5_FLOW_LAYER_VXLAN;
13484 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13485 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13486 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13487 tunnel_item = items;
13489 case RTE_FLOW_ITEM_TYPE_GENEVE:
13490 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13491 last_item = MLX5_FLOW_LAYER_GENEVE;
13492 tunnel_item = items;
13494 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13495 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13499 return rte_flow_error_set(error, -ret,
13500 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13501 "cannot create GENEVE TLV option");
13502 flow->geneve_tlv_option = 1;
13503 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13505 case RTE_FLOW_ITEM_TYPE_MPLS:
13506 flow_dv_translate_item_mpls(match_mask, match_value,
13507 items, last_item, tunnel);
13508 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13509 last_item = MLX5_FLOW_LAYER_MPLS;
13511 case RTE_FLOW_ITEM_TYPE_MARK:
13512 flow_dv_translate_item_mark(dev, match_mask,
13513 match_value, items);
13514 last_item = MLX5_FLOW_ITEM_MARK;
13516 case RTE_FLOW_ITEM_TYPE_META:
13517 flow_dv_translate_item_meta(dev, match_mask,
13518 match_value, attr, items);
13519 last_item = MLX5_FLOW_ITEM_METADATA;
13521 case RTE_FLOW_ITEM_TYPE_ICMP:
13522 flow_dv_translate_item_icmp(match_mask, match_value,
13524 last_item = MLX5_FLOW_LAYER_ICMP;
13526 case RTE_FLOW_ITEM_TYPE_ICMP6:
13527 flow_dv_translate_item_icmp6(match_mask, match_value,
13529 last_item = MLX5_FLOW_LAYER_ICMP6;
13531 case RTE_FLOW_ITEM_TYPE_TAG:
13532 flow_dv_translate_item_tag(dev, match_mask,
13533 match_value, items);
13534 last_item = MLX5_FLOW_ITEM_TAG;
13536 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13537 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13538 match_value, items);
13539 last_item = MLX5_FLOW_ITEM_TAG;
13541 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13542 flow_dv_translate_item_tx_queue(dev, match_mask,
13545 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13547 case RTE_FLOW_ITEM_TYPE_GTP:
13548 flow_dv_translate_item_gtp(match_mask, match_value,
13550 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13551 last_item = MLX5_FLOW_LAYER_GTP;
13553 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13554 ret = flow_dv_translate_item_gtp_psc(match_mask,
13558 return rte_flow_error_set(error, -ret,
13559 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13560 "cannot create GTP PSC item");
13561 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13563 case RTE_FLOW_ITEM_TYPE_ECPRI:
13564 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13565 /* Create it only the first time to be used. */
13566 ret = mlx5_flex_parser_ecpri_alloc(dev);
13568 return rte_flow_error_set
13570 RTE_FLOW_ERROR_TYPE_ITEM,
13572 "cannot create eCPRI parser");
13574 flow_dv_translate_item_ecpri(dev, match_mask,
13575 match_value, items,
13577 /* No other protocol should follow eCPRI layer. */
13578 last_item = MLX5_FLOW_LAYER_ECPRI;
13580 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13581 flow_dv_translate_item_integrity(items, integrity_items,
13584 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13585 flow_dv_translate_item_aso_ct(dev, match_mask,
13586 match_value, items);
13588 case RTE_FLOW_ITEM_TYPE_FLEX:
13589 flow_dv_translate_item_flex(dev, match_mask,
13590 match_value, items,
13591 dev_flow, tunnel != 0);
13592 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13593 MLX5_FLOW_ITEM_OUTER_FLEX;
13598 item_flags |= last_item;
13601 * When E-Switch mode is enabled, we have two cases where we need to
13602 * set the source port manually.
13603 * The first one, is in case of Nic steering rule, and the second is
13604 * E-Switch rule where no port_id item was found. In both cases
13605 * the source port is set according the current port in use.
13607 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13608 (priv->representor || priv->master)) {
13609 if (flow_dv_translate_item_port_id(dev, match_mask,
13610 match_value, NULL, attr))
13613 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13614 flow_dv_translate_item_integrity_post(match_mask, match_value,
13618 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13619 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13620 tunnel_item, item_flags);
13621 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13622 flow_dv_translate_item_geneve(match_mask, match_value,
13623 tunnel_item, item_flags);
13624 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13625 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13626 flow_dv_translate_item_gre(match_mask, match_value,
13627 tunnel_item, item_flags);
13628 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13629 flow_dv_translate_item_nvgre(match_mask, match_value,
13630 tunnel_item, item_flags);
13632 MLX5_ASSERT(false);
13634 #ifdef RTE_LIBRTE_MLX5_DEBUG
13635 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13636 dev_flow->dv.value.buf));
13639 * Layers may be already initialized from prefix flow if this dev_flow
13640 * is the suffix flow.
13642 handle->layers |= item_flags;
13643 if (action_flags & MLX5_FLOW_ACTION_RSS)
13644 flow_dv_hashfields_set(dev_flow, rss_desc);
13645 /* If has RSS action in the sample action, the Sample/Mirror resource
13646 * should be registered after the hash filed be update.
13648 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13649 ret = flow_dv_translate_action_sample(dev,
13658 ret = flow_dv_create_action_sample(dev,
13667 return rte_flow_error_set
13669 RTE_FLOW_ERROR_TYPE_ACTION,
13671 "cannot create sample action");
13672 if (num_of_dest > 1) {
13673 dev_flow->dv.actions[sample_act_pos] =
13674 dev_flow->dv.dest_array_res->action;
13676 dev_flow->dv.actions[sample_act_pos] =
13677 dev_flow->dv.sample_res->verbs_action;
13681 * For multiple destination (sample action with ratio=1), the encap
13682 * action and port id action will be combined into group action.
13683 * So need remove the original these actions in the flow and only
13684 * use the sample action instead of.
13686 if (num_of_dest > 1 &&
13687 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13689 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13691 for (i = 0; i < actions_n; i++) {
13692 if ((sample_act->dr_encap_action &&
13693 sample_act->dr_encap_action ==
13694 dev_flow->dv.actions[i]) ||
13695 (sample_act->dr_port_id_action &&
13696 sample_act->dr_port_id_action ==
13697 dev_flow->dv.actions[i]) ||
13698 (sample_act->dr_jump_action &&
13699 sample_act->dr_jump_action ==
13700 dev_flow->dv.actions[i]))
13702 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13704 memcpy((void *)dev_flow->dv.actions,
13705 (void *)temp_actions,
13706 tmp_actions_n * sizeof(void *));
13707 actions_n = tmp_actions_n;
13709 dev_flow->dv.actions_n = actions_n;
13710 dev_flow->act_flags = action_flags;
13711 if (wks->skip_matcher_reg)
13713 /* Register matcher. */
13714 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13715 matcher.mask.size);
13716 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13718 dev_flow->external);
13720 * When creating meter drop flow in drop table, using original
13721 * 5-tuple match, the matcher priority should be lower than
13724 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13725 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13726 matcher.priority <= MLX5_REG_BITS)
13727 matcher.priority += MLX5_REG_BITS;
13728 /* reserved field no needs to be set to 0 here. */
13729 tbl_key.is_fdb = attr->transfer;
13730 tbl_key.is_egress = attr->egress;
13731 tbl_key.level = dev_flow->dv.group;
13732 tbl_key.id = dev_flow->dv.table_id;
13733 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13734 tunnel, attr->group, error))
13740 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13743 * @param[in, out] action
13744 * Shred RSS action holding hash RX queue objects.
13745 * @param[in] hash_fields
13746 * Defines combination of packet fields to participate in RX hash.
13747 * @param[in] tunnel
13749 * @param[in] hrxq_idx
13750 * Hash RX queue index to set.
13753 * 0 on success, otherwise negative errno value.
13756 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13757 const uint64_t hash_fields,
13760 uint32_t *hrxqs = action->hrxq;
13762 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13763 case MLX5_RSS_HASH_IPV4:
13764 /* fall-through. */
13765 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13766 /* fall-through. */
13767 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13768 hrxqs[0] = hrxq_idx;
13770 case MLX5_RSS_HASH_IPV4_TCP:
13771 /* fall-through. */
13772 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13773 /* fall-through. */
13774 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13775 hrxqs[1] = hrxq_idx;
13777 case MLX5_RSS_HASH_IPV4_UDP:
13778 /* fall-through. */
13779 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13780 /* fall-through. */
13781 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13782 hrxqs[2] = hrxq_idx;
13784 case MLX5_RSS_HASH_IPV6:
13785 /* fall-through. */
13786 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13787 /* fall-through. */
13788 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13789 hrxqs[3] = hrxq_idx;
13791 case MLX5_RSS_HASH_IPV6_TCP:
13792 /* fall-through. */
13793 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13794 /* fall-through. */
13795 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13796 hrxqs[4] = hrxq_idx;
13798 case MLX5_RSS_HASH_IPV6_UDP:
13799 /* fall-through. */
13800 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13801 /* fall-through. */
13802 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13803 hrxqs[5] = hrxq_idx;
13805 case MLX5_RSS_HASH_NONE:
13806 hrxqs[6] = hrxq_idx;
13814 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13818 * Pointer to the Ethernet device structure.
13820 * Shared RSS action ID holding hash RX queue objects.
13821 * @param[in] hash_fields
13822 * Defines combination of packet fields to participate in RX hash.
13823 * @param[in] tunnel
13827 * Valid hash RX queue index, otherwise 0.
13830 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13831 const uint64_t hash_fields)
13833 struct mlx5_priv *priv = dev->data->dev_private;
13834 struct mlx5_shared_action_rss *shared_rss =
13835 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13836 const uint32_t *hrxqs = shared_rss->hrxq;
13838 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13839 case MLX5_RSS_HASH_IPV4:
13840 /* fall-through. */
13841 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13842 /* fall-through. */
13843 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13845 case MLX5_RSS_HASH_IPV4_TCP:
13846 /* fall-through. */
13847 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13848 /* fall-through. */
13849 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13851 case MLX5_RSS_HASH_IPV4_UDP:
13852 /* fall-through. */
13853 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13854 /* fall-through. */
13855 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13857 case MLX5_RSS_HASH_IPV6:
13858 /* fall-through. */
13859 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13860 /* fall-through. */
13861 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13863 case MLX5_RSS_HASH_IPV6_TCP:
13864 /* fall-through. */
13865 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13866 /* fall-through. */
13867 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13869 case MLX5_RSS_HASH_IPV6_UDP:
13870 /* fall-through. */
13871 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13872 /* fall-through. */
13873 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13875 case MLX5_RSS_HASH_NONE:
13884 * Apply the flow to the NIC, lock free,
13885 * (mutex should be acquired by caller).
13888 * Pointer to the Ethernet device structure.
13889 * @param[in, out] flow
13890 * Pointer to flow structure.
13891 * @param[out] error
13892 * Pointer to error structure.
13895 * 0 on success, a negative errno value otherwise and rte_errno is set.
13898 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13899 struct rte_flow_error *error)
13901 struct mlx5_flow_dv_workspace *dv;
13902 struct mlx5_flow_handle *dh;
13903 struct mlx5_flow_handle_dv *dv_h;
13904 struct mlx5_flow *dev_flow;
13905 struct mlx5_priv *priv = dev->data->dev_private;
13906 uint32_t handle_idx;
13910 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13911 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13915 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13916 dev_flow = &wks->flows[idx];
13917 dv = &dev_flow->dv;
13918 dh = dev_flow->handle;
13921 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13922 if (dv->transfer) {
13923 MLX5_ASSERT(priv->sh->dr_drop_action);
13924 dv->actions[n++] = priv->sh->dr_drop_action;
13926 #ifdef HAVE_MLX5DV_DR
13927 /* DR supports drop action placeholder. */
13928 MLX5_ASSERT(priv->sh->dr_drop_action);
13929 dv->actions[n++] = dv->group ?
13930 priv->sh->dr_drop_action :
13931 priv->root_drop_action;
13933 /* For DV we use the explicit drop queue. */
13934 MLX5_ASSERT(priv->drop_queue.hrxq);
13936 priv->drop_queue.hrxq->action;
13939 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13940 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13941 struct mlx5_hrxq *hrxq;
13944 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13949 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13950 "cannot get hash queue");
13953 dh->rix_hrxq = hrxq_idx;
13954 dv->actions[n++] = hrxq->action;
13955 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13956 struct mlx5_hrxq *hrxq = NULL;
13959 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13960 rss_desc->shared_rss,
13961 dev_flow->hash_fields);
13963 hrxq = mlx5_ipool_get
13964 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13969 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13970 "cannot get hash queue");
13973 dh->rix_srss = rss_desc->shared_rss;
13974 dv->actions[n++] = hrxq->action;
13975 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13976 if (!priv->sh->default_miss_action) {
13979 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13980 "default miss action not be created.");
13983 dv->actions[n++] = priv->sh->default_miss_action;
13985 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13986 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13987 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13988 (void *)&dv->value, n,
13989 dv->actions, &dh->drv_flow);
13993 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13995 (!priv->config.allow_duplicate_pattern &&
13997 "duplicating pattern is not allowed" :
13998 "hardware refuses to create flow");
14001 if (priv->vmwa_context &&
14002 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14004 * The rule contains the VLAN pattern.
14005 * For VF we are going to create VLAN
14006 * interface to make hypervisor set correct
14007 * e-Switch vport context.
14009 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14014 err = rte_errno; /* Save rte_errno before cleanup. */
14015 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14016 handle_idx, dh, next) {
14017 /* hrxq is union, don't clear it if the flag is not set. */
14018 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14019 mlx5_hrxq_release(dev, dh->rix_hrxq);
14021 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14024 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14025 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14027 rte_errno = err; /* Restore rte_errno. */
14032 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14033 struct mlx5_list_entry *entry)
14035 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14039 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14040 mlx5_free(resource);
14044 * Release the flow matcher.
14047 * Pointer to Ethernet device.
14049 * Index to port ID action resource.
14052 * 1 while a reference on it exists, 0 when freed.
14055 flow_dv_matcher_release(struct rte_eth_dev *dev,
14056 struct mlx5_flow_handle *handle)
14058 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14059 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14060 typeof(*tbl), tbl);
14063 MLX5_ASSERT(matcher->matcher_object);
14064 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14065 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14070 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14072 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14073 struct mlx5_flow_dv_encap_decap_resource *res =
14074 container_of(entry, typeof(*res), entry);
14076 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14077 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14081 * Release an encap/decap resource.
14084 * Pointer to Ethernet device.
14085 * @param encap_decap_idx
14086 * Index of encap decap resource.
14089 * 1 while a reference on it exists, 0 when freed.
14092 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14093 uint32_t encap_decap_idx)
14095 struct mlx5_priv *priv = dev->data->dev_private;
14096 struct mlx5_flow_dv_encap_decap_resource *resource;
14098 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14102 MLX5_ASSERT(resource->action);
14103 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14107 * Release an jump to table action resource.
14110 * Pointer to Ethernet device.
14112 * Index to the jump action resource.
14115 * 1 while a reference on it exists, 0 when freed.
14118 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14121 struct mlx5_priv *priv = dev->data->dev_private;
14122 struct mlx5_flow_tbl_data_entry *tbl_data;
14124 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14128 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14132 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14134 struct mlx5_flow_dv_modify_hdr_resource *res =
14135 container_of(entry, typeof(*res), entry);
14136 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14138 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14139 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14143 * Release a modify-header resource.
14146 * Pointer to Ethernet device.
14148 * Pointer to mlx5_flow_handle.
14151 * 1 while a reference on it exists, 0 when freed.
14154 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14155 struct mlx5_flow_handle *handle)
14157 struct mlx5_priv *priv = dev->data->dev_private;
14158 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14160 MLX5_ASSERT(entry->action);
14161 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14165 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14167 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14168 struct mlx5_flow_dv_port_id_action_resource *resource =
14169 container_of(entry, typeof(*resource), entry);
14171 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14172 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14176 * Release port ID action resource.
14179 * Pointer to Ethernet device.
14181 * Pointer to mlx5_flow_handle.
14184 * 1 while a reference on it exists, 0 when freed.
14187 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14190 struct mlx5_priv *priv = dev->data->dev_private;
14191 struct mlx5_flow_dv_port_id_action_resource *resource;
14193 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14196 MLX5_ASSERT(resource->action);
14197 return mlx5_list_unregister(priv->sh->port_id_action_list,
14202 * Release shared RSS action resource.
14205 * Pointer to Ethernet device.
14207 * Shared RSS action index.
14210 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14212 struct mlx5_priv *priv = dev->data->dev_private;
14213 struct mlx5_shared_action_rss *shared_rss;
14215 shared_rss = mlx5_ipool_get
14216 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14217 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14221 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14223 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14224 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14225 container_of(entry, typeof(*resource), entry);
14227 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14228 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14232 * Release push vlan action resource.
14235 * Pointer to Ethernet device.
14237 * Pointer to mlx5_flow_handle.
14240 * 1 while a reference on it exists, 0 when freed.
14243 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14244 struct mlx5_flow_handle *handle)
14246 struct mlx5_priv *priv = dev->data->dev_private;
14247 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14248 uint32_t idx = handle->dvh.rix_push_vlan;
14250 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14253 MLX5_ASSERT(resource->action);
14254 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14259 * Release the fate resource.
14262 * Pointer to Ethernet device.
14264 * Pointer to mlx5_flow_handle.
14267 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14268 struct mlx5_flow_handle *handle)
14270 if (!handle->rix_fate)
14272 switch (handle->fate_action) {
14273 case MLX5_FLOW_FATE_QUEUE:
14274 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14275 mlx5_hrxq_release(dev, handle->rix_hrxq);
14277 case MLX5_FLOW_FATE_JUMP:
14278 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14280 case MLX5_FLOW_FATE_PORT_ID:
14281 flow_dv_port_id_action_resource_release(dev,
14282 handle->rix_port_id_action);
14285 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14288 handle->rix_fate = 0;
14292 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14293 struct mlx5_list_entry *entry)
14295 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14298 struct rte_eth_dev *dev = resource->dev;
14299 struct mlx5_priv *priv = dev->data->dev_private;
14301 if (resource->verbs_action)
14302 claim_zero(mlx5_flow_os_destroy_flow_action
14303 (resource->verbs_action));
14304 if (resource->normal_path_tbl)
14305 flow_dv_tbl_resource_release(MLX5_SH(dev),
14306 resource->normal_path_tbl);
14307 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14308 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14309 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14313 * Release an sample resource.
14316 * Pointer to Ethernet device.
14318 * Pointer to mlx5_flow_handle.
14321 * 1 while a reference on it exists, 0 when freed.
14324 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14325 struct mlx5_flow_handle *handle)
14327 struct mlx5_priv *priv = dev->data->dev_private;
14328 struct mlx5_flow_dv_sample_resource *resource;
14330 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14331 handle->dvh.rix_sample);
14334 MLX5_ASSERT(resource->verbs_action);
14335 return mlx5_list_unregister(priv->sh->sample_action_list,
14340 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14341 struct mlx5_list_entry *entry)
14343 struct mlx5_flow_dv_dest_array_resource *resource =
14344 container_of(entry, typeof(*resource), entry);
14345 struct rte_eth_dev *dev = resource->dev;
14346 struct mlx5_priv *priv = dev->data->dev_private;
14349 MLX5_ASSERT(resource->action);
14350 if (resource->action)
14351 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14352 for (; i < resource->num_of_dest; i++)
14353 flow_dv_sample_sub_actions_release(dev,
14354 &resource->sample_idx[i]);
14355 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14356 DRV_LOG(DEBUG, "destination array resource %p: removed",
14361 * Release an destination array resource.
14364 * Pointer to Ethernet device.
14366 * Pointer to mlx5_flow_handle.
14369 * 1 while a reference on it exists, 0 when freed.
14372 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14373 struct mlx5_flow_handle *handle)
14375 struct mlx5_priv *priv = dev->data->dev_private;
14376 struct mlx5_flow_dv_dest_array_resource *resource;
14378 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14379 handle->dvh.rix_dest_array);
14382 MLX5_ASSERT(resource->action);
14383 return mlx5_list_unregister(priv->sh->dest_array_list,
14388 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14390 struct mlx5_priv *priv = dev->data->dev_private;
14391 struct mlx5_dev_ctx_shared *sh = priv->sh;
14392 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14393 sh->geneve_tlv_option_resource;
14394 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14395 if (geneve_opt_resource) {
14396 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14397 __ATOMIC_RELAXED))) {
14398 claim_zero(mlx5_devx_cmd_destroy
14399 (geneve_opt_resource->obj));
14400 mlx5_free(sh->geneve_tlv_option_resource);
14401 sh->geneve_tlv_option_resource = NULL;
14404 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14408 * Remove the flow from the NIC but keeps it in memory.
14409 * Lock free, (mutex should be acquired by caller).
14412 * Pointer to Ethernet device.
14413 * @param[in, out] flow
14414 * Pointer to flow structure.
14417 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14419 struct mlx5_flow_handle *dh;
14420 uint32_t handle_idx;
14421 struct mlx5_priv *priv = dev->data->dev_private;
14425 handle_idx = flow->dev_handles;
14426 while (handle_idx) {
14427 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14431 if (dh->drv_flow) {
14432 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14433 dh->drv_flow = NULL;
14435 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14436 flow_dv_fate_resource_release(dev, dh);
14437 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14438 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14439 handle_idx = dh->next.next;
14444 * Remove the flow from the NIC and the memory.
14445 * Lock free, (mutex should be acquired by caller).
14448 * Pointer to the Ethernet device structure.
14449 * @param[in, out] flow
14450 * Pointer to flow structure.
14453 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14455 struct mlx5_flow_handle *dev_handle;
14456 struct mlx5_priv *priv = dev->data->dev_private;
14457 struct mlx5_flow_meter_info *fm = NULL;
14462 flow_dv_remove(dev, flow);
14463 if (flow->counter) {
14464 flow_dv_counter_free(dev, flow->counter);
14468 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14470 mlx5_flow_meter_detach(priv, fm);
14473 /* Keep the current age handling by default. */
14474 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14475 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14476 else if (flow->age)
14477 flow_dv_aso_age_release(dev, flow->age);
14478 if (flow->geneve_tlv_option) {
14479 flow_dv_geneve_tlv_option_resource_release(dev);
14480 flow->geneve_tlv_option = 0;
14482 while (flow->dev_handles) {
14483 uint32_t tmp_idx = flow->dev_handles;
14485 dev_handle = mlx5_ipool_get(priv->sh->ipool
14486 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14489 flow->dev_handles = dev_handle->next.next;
14490 while (dev_handle->flex_item) {
14491 int index = rte_bsf32(dev_handle->flex_item);
14493 mlx5_flex_release_index(dev, index);
14494 dev_handle->flex_item &= ~RTE_BIT32(index);
14496 if (dev_handle->dvh.matcher)
14497 flow_dv_matcher_release(dev, dev_handle);
14498 if (dev_handle->dvh.rix_sample)
14499 flow_dv_sample_resource_release(dev, dev_handle);
14500 if (dev_handle->dvh.rix_dest_array)
14501 flow_dv_dest_array_resource_release(dev, dev_handle);
14502 if (dev_handle->dvh.rix_encap_decap)
14503 flow_dv_encap_decap_resource_release(dev,
14504 dev_handle->dvh.rix_encap_decap);
14505 if (dev_handle->dvh.modify_hdr)
14506 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14507 if (dev_handle->dvh.rix_push_vlan)
14508 flow_dv_push_vlan_action_resource_release(dev,
14510 if (dev_handle->dvh.rix_tag)
14511 flow_dv_tag_release(dev,
14512 dev_handle->dvh.rix_tag);
14513 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14514 flow_dv_fate_resource_release(dev, dev_handle);
14516 srss = dev_handle->rix_srss;
14517 if (fm && dev_handle->is_meter_flow_id &&
14518 dev_handle->split_flow_id)
14519 mlx5_ipool_free(fm->flow_ipool,
14520 dev_handle->split_flow_id);
14521 else if (dev_handle->split_flow_id &&
14522 !dev_handle->is_meter_flow_id)
14523 mlx5_ipool_free(priv->sh->ipool
14524 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14525 dev_handle->split_flow_id);
14526 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14530 flow_dv_shared_rss_action_release(dev, srss);
14534 * Release array of hash RX queue objects.
14538 * Pointer to the Ethernet device structure.
14539 * @param[in, out] hrxqs
14540 * Array of hash RX queue objects.
14543 * Total number of references to hash RX queue objects in *hrxqs* array
14544 * after this operation.
14547 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14548 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14553 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14554 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14564 * Release all hash RX queue objects representing shared RSS action.
14567 * Pointer to the Ethernet device structure.
14568 * @param[in, out] action
14569 * Shared RSS action to remove hash RX queue objects from.
14572 * Total number of references to hash RX queue objects stored in *action*
14573 * after this operation.
14574 * Expected to be 0 if no external references held.
14577 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14578 struct mlx5_shared_action_rss *shared_rss)
14580 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14584 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14587 * Only one hash value is available for one L3+L4 combination:
14589 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14590 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14591 * same slot in mlx5_rss_hash_fields.
14594 * Pointer to the shared action RSS conf.
14595 * @param[in, out] hash_field
14596 * hash_field variable needed to be adjusted.
14602 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14603 uint64_t *hash_field)
14605 uint64_t rss_types = rss->origin.types;
14607 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14608 case MLX5_RSS_HASH_IPV4:
14609 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14610 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14611 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14612 *hash_field |= IBV_RX_HASH_DST_IPV4;
14613 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14614 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14616 *hash_field |= MLX5_RSS_HASH_IPV4;
14619 case MLX5_RSS_HASH_IPV6:
14620 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14621 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14622 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14623 *hash_field |= IBV_RX_HASH_DST_IPV6;
14624 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14625 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14627 *hash_field |= MLX5_RSS_HASH_IPV6;
14630 case MLX5_RSS_HASH_IPV4_UDP:
14631 /* fall-through. */
14632 case MLX5_RSS_HASH_IPV6_UDP:
14633 if (rss_types & RTE_ETH_RSS_UDP) {
14634 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14635 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14636 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14637 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14638 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14640 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14643 case MLX5_RSS_HASH_IPV4_TCP:
14644 /* fall-through. */
14645 case MLX5_RSS_HASH_IPV6_TCP:
14646 if (rss_types & RTE_ETH_RSS_TCP) {
14647 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14648 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14649 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14650 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14651 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14653 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14662 * Setup shared RSS action.
14663 * Prepare set of hash RX queue objects sufficient to handle all valid
14664 * hash_fields combinations (see enum ibv_rx_hash_fields).
14667 * Pointer to the Ethernet device structure.
14668 * @param[in] action_idx
14669 * Shared RSS action ipool index.
14670 * @param[in, out] action
14671 * Partially initialized shared RSS action.
14672 * @param[out] error
14673 * Perform verbose error reporting if not NULL. Initialized in case of
14677 * 0 on success, otherwise negative errno value.
14680 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14681 uint32_t action_idx,
14682 struct mlx5_shared_action_rss *shared_rss,
14683 struct rte_flow_error *error)
14685 struct mlx5_flow_rss_desc rss_desc = { 0 };
14689 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14690 return rte_flow_error_set(error, rte_errno,
14691 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14692 "cannot setup indirection table");
14694 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14695 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14696 rss_desc.const_q = shared_rss->origin.queue;
14697 rss_desc.queue_num = shared_rss->origin.queue_num;
14698 /* Set non-zero value to indicate a shared RSS. */
14699 rss_desc.shared_rss = action_idx;
14700 rss_desc.ind_tbl = shared_rss->ind_tbl;
14701 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14703 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14706 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14707 if (shared_rss->origin.level > 1) {
14708 hash_fields |= IBV_RX_HASH_INNER;
14711 rss_desc.tunnel = tunnel;
14712 rss_desc.hash_fields = hash_fields;
14713 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14717 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14718 "cannot get hash queue");
14719 goto error_hrxq_new;
14721 err = __flow_dv_action_rss_hrxq_set
14722 (shared_rss, hash_fields, hrxq_idx);
14728 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14729 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14730 shared_rss->ind_tbl = NULL;
14736 * Create shared RSS action.
14739 * Pointer to the Ethernet device structure.
14741 * Shared action configuration.
14743 * RSS action specification used to create shared action.
14744 * @param[out] error
14745 * Perform verbose error reporting if not NULL. Initialized in case of
14749 * A valid shared action ID in case of success, 0 otherwise and
14750 * rte_errno is set.
14753 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14754 const struct rte_flow_indir_action_conf *conf,
14755 const struct rte_flow_action_rss *rss,
14756 struct rte_flow_error *error)
14758 struct mlx5_priv *priv = dev->data->dev_private;
14759 struct mlx5_shared_action_rss *shared_rss = NULL;
14760 void *queue = NULL;
14761 struct rte_flow_action_rss *origin;
14762 const uint8_t *rss_key;
14763 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14766 RTE_SET_USED(conf);
14767 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14769 shared_rss = mlx5_ipool_zmalloc
14770 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14771 if (!shared_rss || !queue) {
14772 rte_flow_error_set(error, ENOMEM,
14773 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14774 "cannot allocate resource memory");
14775 goto error_rss_init;
14777 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14778 rte_flow_error_set(error, E2BIG,
14779 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14780 "rss action number out of range");
14781 goto error_rss_init;
14783 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14784 sizeof(*shared_rss->ind_tbl),
14786 if (!shared_rss->ind_tbl) {
14787 rte_flow_error_set(error, ENOMEM,
14788 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14789 "cannot allocate resource memory");
14790 goto error_rss_init;
14792 memcpy(queue, rss->queue, queue_size);
14793 shared_rss->ind_tbl->queues = queue;
14794 shared_rss->ind_tbl->queues_n = rss->queue_num;
14795 origin = &shared_rss->origin;
14796 origin->func = rss->func;
14797 origin->level = rss->level;
14798 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14799 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14800 /* NULL RSS key indicates default RSS key. */
14801 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14802 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14803 origin->key = &shared_rss->key[0];
14804 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14805 origin->queue = queue;
14806 origin->queue_num = rss->queue_num;
14807 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14808 goto error_rss_init;
14809 rte_spinlock_init(&shared_rss->action_rss_sl);
14810 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14811 rte_spinlock_lock(&priv->shared_act_sl);
14812 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14813 &priv->rss_shared_actions, idx, shared_rss, next);
14814 rte_spinlock_unlock(&priv->shared_act_sl);
14818 if (shared_rss->ind_tbl)
14819 mlx5_free(shared_rss->ind_tbl);
14820 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14829 * Destroy the shared RSS action.
14830 * Release related hash RX queue objects.
14833 * Pointer to the Ethernet device structure.
14835 * The shared RSS action object ID to be removed.
14836 * @param[out] error
14837 * Perform verbose error reporting if not NULL. Initialized in case of
14841 * 0 on success, otherwise negative errno value.
14844 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14845 struct rte_flow_error *error)
14847 struct mlx5_priv *priv = dev->data->dev_private;
14848 struct mlx5_shared_action_rss *shared_rss =
14849 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14850 uint32_t old_refcnt = 1;
14852 uint16_t *queue = NULL;
14855 return rte_flow_error_set(error, EINVAL,
14856 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14857 "invalid shared action");
14858 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14859 0, 0, __ATOMIC_ACQUIRE,
14861 return rte_flow_error_set(error, EBUSY,
14862 RTE_FLOW_ERROR_TYPE_ACTION,
14864 "shared rss has references");
14865 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14867 return rte_flow_error_set(error, EBUSY,
14868 RTE_FLOW_ERROR_TYPE_ACTION,
14870 "shared rss hrxq has references");
14871 queue = shared_rss->ind_tbl->queues;
14872 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14874 return rte_flow_error_set(error, EBUSY,
14875 RTE_FLOW_ERROR_TYPE_ACTION,
14877 "shared rss indirection table has"
14880 rte_spinlock_lock(&priv->shared_act_sl);
14881 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14882 &priv->rss_shared_actions, idx, shared_rss, next);
14883 rte_spinlock_unlock(&priv->shared_act_sl);
14884 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14890 * Create indirect action, lock free,
14891 * (mutex should be acquired by caller).
14892 * Dispatcher for action type specific call.
14895 * Pointer to the Ethernet device structure.
14897 * Shared action configuration.
14898 * @param[in] action
14899 * Action specification used to create indirect action.
14900 * @param[out] error
14901 * Perform verbose error reporting if not NULL. Initialized in case of
14905 * A valid shared action handle in case of success, NULL otherwise and
14906 * rte_errno is set.
14908 static struct rte_flow_action_handle *
14909 flow_dv_action_create(struct rte_eth_dev *dev,
14910 const struct rte_flow_indir_action_conf *conf,
14911 const struct rte_flow_action *action,
14912 struct rte_flow_error *err)
14914 struct mlx5_priv *priv = dev->data->dev_private;
14915 uint32_t age_idx = 0;
14919 switch (action->type) {
14920 case RTE_FLOW_ACTION_TYPE_RSS:
14921 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14922 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14923 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14925 case RTE_FLOW_ACTION_TYPE_AGE:
14926 age_idx = flow_dv_aso_age_alloc(dev, err);
14931 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14932 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14933 flow_dv_aso_age_params_init(dev, age_idx,
14934 ((const struct rte_flow_action_age *)
14935 action->conf)->context ?
14936 ((const struct rte_flow_action_age *)
14937 action->conf)->context :
14938 (void *)(uintptr_t)idx,
14939 ((const struct rte_flow_action_age *)
14940 action->conf)->timeout);
14943 case RTE_FLOW_ACTION_TYPE_COUNT:
14944 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14945 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14946 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14948 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14949 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14951 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14954 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14955 NULL, "action type not supported");
14958 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14962 * Destroy the indirect action.
14963 * Release action related resources on the NIC and the memory.
14964 * Lock free, (mutex should be acquired by caller).
14965 * Dispatcher for action type specific call.
14968 * Pointer to the Ethernet device structure.
14969 * @param[in] handle
14970 * The indirect action object handle to be removed.
14971 * @param[out] error
14972 * Perform verbose error reporting if not NULL. Initialized in case of
14976 * 0 on success, otherwise negative errno value.
14979 flow_dv_action_destroy(struct rte_eth_dev *dev,
14980 struct rte_flow_action_handle *handle,
14981 struct rte_flow_error *error)
14983 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14984 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14985 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14986 struct mlx5_flow_counter *cnt;
14987 uint32_t no_flow_refcnt = 1;
14991 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14992 return __flow_dv_action_rss_release(dev, idx, error);
14993 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14994 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14995 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14996 &no_flow_refcnt, 1, false,
14999 return rte_flow_error_set(error, EBUSY,
15000 RTE_FLOW_ERROR_TYPE_ACTION,
15002 "Indirect count action has references");
15003 flow_dv_counter_free(dev, idx);
15005 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15006 ret = flow_dv_aso_age_release(dev, idx);
15009 * In this case, the last flow has a reference will
15010 * actually release the age action.
15012 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15013 " released with references %d.", idx, ret);
15015 case MLX5_INDIRECT_ACTION_TYPE_CT:
15016 ret = flow_dv_aso_ct_release(dev, idx, error);
15020 DRV_LOG(DEBUG, "Connection tracking object %u still "
15021 "has references %d.", idx, ret);
15024 return rte_flow_error_set(error, ENOTSUP,
15025 RTE_FLOW_ERROR_TYPE_ACTION,
15027 "action type not supported");
15032 * Updates in place shared RSS action configuration.
15035 * Pointer to the Ethernet device structure.
15037 * The shared RSS action object ID to be updated.
15038 * @param[in] action_conf
15039 * RSS action specification used to modify *shared_rss*.
15040 * @param[out] error
15041 * Perform verbose error reporting if not NULL. Initialized in case of
15045 * 0 on success, otherwise negative errno value.
15046 * @note: currently only support update of RSS queues.
15049 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15050 const struct rte_flow_action_rss *action_conf,
15051 struct rte_flow_error *error)
15053 struct mlx5_priv *priv = dev->data->dev_private;
15054 struct mlx5_shared_action_rss *shared_rss =
15055 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15057 void *queue = NULL;
15058 uint16_t *queue_old = NULL;
15059 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15062 return rte_flow_error_set(error, EINVAL,
15063 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15064 "invalid shared action to update");
15065 if (priv->obj_ops.ind_table_modify == NULL)
15066 return rte_flow_error_set(error, ENOTSUP,
15067 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15068 "cannot modify indirection table");
15069 queue = mlx5_malloc(MLX5_MEM_ZERO,
15070 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15073 return rte_flow_error_set(error, ENOMEM,
15074 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15076 "cannot allocate resource memory");
15077 memcpy(queue, action_conf->queue, queue_size);
15078 MLX5_ASSERT(shared_rss->ind_tbl);
15079 rte_spinlock_lock(&shared_rss->action_rss_sl);
15080 queue_old = shared_rss->ind_tbl->queues;
15081 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15082 queue, action_conf->queue_num, true);
15085 ret = rte_flow_error_set(error, rte_errno,
15086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15087 "cannot update indirection table");
15089 mlx5_free(queue_old);
15090 shared_rss->origin.queue = queue;
15091 shared_rss->origin.queue_num = action_conf->queue_num;
15093 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15098 * Updates in place conntrack context or direction.
15099 * Context update should be synchronized.
15102 * Pointer to the Ethernet device structure.
15104 * The conntrack object ID to be updated.
15105 * @param[in] update
15106 * Pointer to the structure of information to update.
15107 * @param[out] error
15108 * Perform verbose error reporting if not NULL. Initialized in case of
15112 * 0 on success, otherwise negative errno value.
15115 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15116 const struct rte_flow_modify_conntrack *update,
15117 struct rte_flow_error *error)
15119 struct mlx5_priv *priv = dev->data->dev_private;
15120 struct mlx5_aso_ct_action *ct;
15121 const struct rte_flow_action_conntrack *new_prf;
15123 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15126 if (PORT_ID(priv) != owner)
15127 return rte_flow_error_set(error, EACCES,
15128 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15130 "CT object owned by another port");
15131 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15132 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15134 return rte_flow_error_set(error, ENOMEM,
15135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15137 "CT object is inactive");
15138 new_prf = &update->new_ct;
15139 if (update->direction)
15140 ct->is_original = !!new_prf->is_original_dir;
15141 if (update->state) {
15142 /* Only validate the profile when it needs to be updated. */
15143 ret = mlx5_validate_action_ct(dev, new_prf, error);
15146 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15148 return rte_flow_error_set(error, EIO,
15149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15151 "Failed to send CT context update WQE");
15152 /* Block until ready or a failure. */
15153 ret = mlx5_aso_ct_available(priv->sh, ct);
15155 rte_flow_error_set(error, rte_errno,
15156 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15158 "Timeout to get the CT update");
15164 * Updates in place shared action configuration, lock free,
15165 * (mutex should be acquired by caller).
15168 * Pointer to the Ethernet device structure.
15169 * @param[in] handle
15170 * The indirect action object handle to be updated.
15171 * @param[in] update
15172 * Action specification used to modify the action pointed by *handle*.
15173 * *update* could be of same type with the action pointed by the *handle*
15174 * handle argument, or some other structures like a wrapper, depending on
15175 * the indirect action type.
15176 * @param[out] error
15177 * Perform verbose error reporting if not NULL. Initialized in case of
15181 * 0 on success, otherwise negative errno value.
15184 flow_dv_action_update(struct rte_eth_dev *dev,
15185 struct rte_flow_action_handle *handle,
15186 const void *update,
15187 struct rte_flow_error *err)
15189 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15190 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15191 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15192 const void *action_conf;
15195 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15196 action_conf = ((const struct rte_flow_action *)update)->conf;
15197 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15198 case MLX5_INDIRECT_ACTION_TYPE_CT:
15199 return __flow_dv_action_ct_update(dev, idx, update, err);
15201 return rte_flow_error_set(err, ENOTSUP,
15202 RTE_FLOW_ERROR_TYPE_ACTION,
15204 "action type update not supported");
15209 * Destroy the meter sub policy table rules.
15210 * Lock free, (mutex should be acquired by caller).
15213 * Pointer to Ethernet device.
15214 * @param[in] sub_policy
15215 * Pointer to meter sub policy table.
15218 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15219 struct mlx5_flow_meter_sub_policy *sub_policy)
15221 struct mlx5_priv *priv = dev->data->dev_private;
15222 struct mlx5_flow_tbl_data_entry *tbl;
15223 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15224 struct mlx5_flow_meter_info *next_fm;
15225 struct mlx5_sub_policy_color_rule *color_rule;
15229 for (i = 0; i < RTE_COLORS; i++) {
15231 if (i == RTE_COLOR_GREEN && policy &&
15232 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15233 next_fm = mlx5_flow_meter_find(priv,
15234 policy->act_cnt[i].next_mtr_id, NULL);
15235 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15237 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15238 tbl = container_of(color_rule->matcher->tbl,
15239 typeof(*tbl), tbl);
15240 mlx5_list_unregister(tbl->matchers,
15241 &color_rule->matcher->entry);
15242 TAILQ_REMOVE(&sub_policy->color_rules[i],
15243 color_rule, next_port);
15244 mlx5_free(color_rule);
15246 mlx5_flow_meter_detach(priv, next_fm);
15249 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15250 if (sub_policy->rix_hrxq[i]) {
15251 if (policy && !policy->is_hierarchy)
15252 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15253 sub_policy->rix_hrxq[i] = 0;
15255 if (sub_policy->jump_tbl[i]) {
15256 flow_dv_tbl_resource_release(MLX5_SH(dev),
15257 sub_policy->jump_tbl[i]);
15258 sub_policy->jump_tbl[i] = NULL;
15261 if (sub_policy->tbl_rsc) {
15262 flow_dv_tbl_resource_release(MLX5_SH(dev),
15263 sub_policy->tbl_rsc);
15264 sub_policy->tbl_rsc = NULL;
15269 * Destroy policy rules, lock free,
15270 * (mutex should be acquired by caller).
15271 * Dispatcher for action type specific call.
15274 * Pointer to the Ethernet device structure.
15275 * @param[in] mtr_policy
15276 * Meter policy struct.
15279 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15280 struct mlx5_flow_meter_policy *mtr_policy)
15283 struct mlx5_flow_meter_sub_policy *sub_policy;
15284 uint16_t sub_policy_num;
15286 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15287 sub_policy_num = (mtr_policy->sub_policy_num >>
15288 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15289 MLX5_MTR_SUB_POLICY_NUM_MASK;
15290 for (j = 0; j < sub_policy_num; j++) {
15291 sub_policy = mtr_policy->sub_policys[i][j];
15293 __flow_dv_destroy_sub_policy_rules(dev,
15300 * Destroy policy action, lock free,
15301 * (mutex should be acquired by caller).
15302 * Dispatcher for action type specific call.
15305 * Pointer to the Ethernet device structure.
15306 * @param[in] mtr_policy
15307 * Meter policy struct.
15310 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15311 struct mlx5_flow_meter_policy *mtr_policy)
15313 struct rte_flow_action *rss_action;
15314 struct mlx5_flow_handle dev_handle;
15317 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15318 if (mtr_policy->act_cnt[i].rix_mark) {
15319 flow_dv_tag_release(dev,
15320 mtr_policy->act_cnt[i].rix_mark);
15321 mtr_policy->act_cnt[i].rix_mark = 0;
15323 if (mtr_policy->act_cnt[i].modify_hdr) {
15324 dev_handle.dvh.modify_hdr =
15325 mtr_policy->act_cnt[i].modify_hdr;
15326 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15328 switch (mtr_policy->act_cnt[i].fate_action) {
15329 case MLX5_FLOW_FATE_SHARED_RSS:
15330 rss_action = mtr_policy->act_cnt[i].rss;
15331 mlx5_free(rss_action);
15333 case MLX5_FLOW_FATE_PORT_ID:
15334 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15335 flow_dv_port_id_action_resource_release(dev,
15336 mtr_policy->act_cnt[i].rix_port_id_action);
15337 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15340 case MLX5_FLOW_FATE_DROP:
15341 case MLX5_FLOW_FATE_JUMP:
15342 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15343 mtr_policy->act_cnt[i].dr_jump_action[j] =
15347 /*Queue action do nothing*/
15351 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15352 mtr_policy->dr_drop_action[j] = NULL;
15356 * Create policy action per domain, lock free,
15357 * (mutex should be acquired by caller).
15358 * Dispatcher for action type specific call.
15361 * Pointer to the Ethernet device structure.
15362 * @param[in] mtr_policy
15363 * Meter policy struct.
15364 * @param[in] action
15365 * Action specification used to create meter actions.
15366 * @param[out] error
15367 * Perform verbose error reporting if not NULL. Initialized in case of
15371 * 0 on success, otherwise negative errno value.
15374 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15375 struct mlx5_flow_meter_policy *mtr_policy,
15376 const struct rte_flow_action *actions[RTE_COLORS],
15377 enum mlx5_meter_domain domain,
15378 struct rte_mtr_error *error)
15380 struct mlx5_priv *priv = dev->data->dev_private;
15381 struct rte_flow_error flow_err;
15382 const struct rte_flow_action *act;
15383 uint64_t action_flags;
15384 struct mlx5_flow_handle dh;
15385 struct mlx5_flow dev_flow;
15386 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15388 uint8_t egress, transfer;
15389 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15391 struct mlx5_flow_dv_modify_hdr_resource res;
15392 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15393 sizeof(struct mlx5_modification_cmd) *
15394 (MLX5_MAX_MODIFY_NUM + 1)];
15396 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15398 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15399 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15400 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15401 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15402 memset(&port_id_action, 0,
15403 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15404 memset(mhdr_res, 0, sizeof(*mhdr_res));
15405 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15406 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15407 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15408 dev_flow.handle = &dh;
15409 dev_flow.dv.port_id_action = &port_id_action;
15410 dev_flow.external = true;
15411 for (i = 0; i < RTE_COLORS; i++) {
15412 if (i < MLX5_MTR_RTE_COLORS)
15413 act_cnt = &mtr_policy->act_cnt[i];
15414 /* Skip the color policy actions creation. */
15415 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15416 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15419 for (act = actions[i];
15420 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15421 switch (act->type) {
15422 case RTE_FLOW_ACTION_TYPE_MARK:
15424 uint32_t tag_be = mlx5_flow_mark_set
15425 (((const struct rte_flow_action_mark *)
15428 if (i >= MLX5_MTR_RTE_COLORS)
15429 return -rte_mtr_error_set(error,
15431 RTE_MTR_ERROR_TYPE_METER_POLICY,
15433 "cannot create policy "
15434 "mark action for this color");
15435 dev_flow.handle->mark = 1;
15436 if (flow_dv_tag_resource_register(dev, tag_be,
15437 &dev_flow, &flow_err))
15438 return -rte_mtr_error_set(error,
15440 RTE_MTR_ERROR_TYPE_METER_POLICY,
15442 "cannot setup policy mark action");
15443 MLX5_ASSERT(dev_flow.dv.tag_resource);
15444 act_cnt->rix_mark =
15445 dev_flow.handle->dvh.rix_tag;
15446 action_flags |= MLX5_FLOW_ACTION_MARK;
15449 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15450 if (i >= MLX5_MTR_RTE_COLORS)
15451 return -rte_mtr_error_set(error,
15453 RTE_MTR_ERROR_TYPE_METER_POLICY,
15455 "cannot create policy "
15456 "set tag action for this color");
15457 if (flow_dv_convert_action_set_tag
15459 (const struct rte_flow_action_set_tag *)
15460 act->conf, &flow_err))
15461 return -rte_mtr_error_set(error,
15463 RTE_MTR_ERROR_TYPE_METER_POLICY,
15464 NULL, "cannot convert policy "
15466 if (!mhdr_res->actions_num)
15467 return -rte_mtr_error_set(error,
15469 RTE_MTR_ERROR_TYPE_METER_POLICY,
15470 NULL, "cannot find policy "
15472 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15474 case RTE_FLOW_ACTION_TYPE_DROP:
15476 struct mlx5_flow_mtr_mng *mtrmng =
15478 struct mlx5_flow_tbl_data_entry *tbl_data;
15481 * Create the drop table with
15482 * METER DROP level.
15484 if (!mtrmng->drop_tbl[domain]) {
15485 mtrmng->drop_tbl[domain] =
15486 flow_dv_tbl_resource_get(dev,
15487 MLX5_FLOW_TABLE_LEVEL_METER,
15488 egress, transfer, false, NULL, 0,
15489 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15490 if (!mtrmng->drop_tbl[domain])
15491 return -rte_mtr_error_set
15493 RTE_MTR_ERROR_TYPE_METER_POLICY,
15495 "Failed to create meter drop table");
15497 tbl_data = container_of
15498 (mtrmng->drop_tbl[domain],
15499 struct mlx5_flow_tbl_data_entry, tbl);
15500 if (i < MLX5_MTR_RTE_COLORS) {
15501 act_cnt->dr_jump_action[domain] =
15502 tbl_data->jump.action;
15503 act_cnt->fate_action =
15504 MLX5_FLOW_FATE_DROP;
15506 if (i == RTE_COLOR_RED)
15507 mtr_policy->dr_drop_action[domain] =
15508 tbl_data->jump.action;
15509 action_flags |= MLX5_FLOW_ACTION_DROP;
15512 case RTE_FLOW_ACTION_TYPE_QUEUE:
15514 if (i >= MLX5_MTR_RTE_COLORS)
15515 return -rte_mtr_error_set(error,
15517 RTE_MTR_ERROR_TYPE_METER_POLICY,
15518 NULL, "cannot create policy "
15519 "fate queue for this color");
15521 ((const struct rte_flow_action_queue *)
15522 (act->conf))->index;
15523 act_cnt->fate_action =
15524 MLX5_FLOW_FATE_QUEUE;
15525 dev_flow.handle->fate_action =
15526 MLX5_FLOW_FATE_QUEUE;
15527 mtr_policy->is_queue = 1;
15528 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15531 case RTE_FLOW_ACTION_TYPE_RSS:
15535 if (i >= MLX5_MTR_RTE_COLORS)
15536 return -rte_mtr_error_set(error,
15538 RTE_MTR_ERROR_TYPE_METER_POLICY,
15540 "cannot create policy "
15541 "rss action for this color");
15543 * Save RSS conf into policy struct
15544 * for translate stage.
15546 rss_size = (int)rte_flow_conv
15547 (RTE_FLOW_CONV_OP_ACTION,
15548 NULL, 0, act, &flow_err);
15550 return -rte_mtr_error_set(error,
15552 RTE_MTR_ERROR_TYPE_METER_POLICY,
15553 NULL, "Get the wrong "
15554 "rss action struct size");
15555 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15556 rss_size, 0, SOCKET_ID_ANY);
15558 return -rte_mtr_error_set(error,
15560 RTE_MTR_ERROR_TYPE_METER_POLICY,
15562 "Fail to malloc rss action memory");
15563 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15564 act_cnt->rss, rss_size,
15567 return -rte_mtr_error_set(error,
15569 RTE_MTR_ERROR_TYPE_METER_POLICY,
15570 NULL, "Fail to save "
15571 "rss action into policy struct");
15572 act_cnt->fate_action =
15573 MLX5_FLOW_FATE_SHARED_RSS;
15574 action_flags |= MLX5_FLOW_ACTION_RSS;
15577 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15578 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15580 struct mlx5_flow_dv_port_id_action_resource
15582 uint32_t port_id = 0;
15584 if (i >= MLX5_MTR_RTE_COLORS)
15585 return -rte_mtr_error_set(error,
15587 RTE_MTR_ERROR_TYPE_METER_POLICY,
15588 NULL, "cannot create policy "
15589 "port action for this color");
15590 memset(&port_id_resource, 0,
15591 sizeof(port_id_resource));
15592 if (flow_dv_translate_action_port_id(dev, act,
15593 &port_id, &flow_err))
15594 return -rte_mtr_error_set(error,
15596 RTE_MTR_ERROR_TYPE_METER_POLICY,
15597 NULL, "cannot translate "
15598 "policy port action");
15599 port_id_resource.port_id = port_id;
15600 if (flow_dv_port_id_action_resource_register
15601 (dev, &port_id_resource,
15602 &dev_flow, &flow_err))
15603 return -rte_mtr_error_set(error,
15605 RTE_MTR_ERROR_TYPE_METER_POLICY,
15606 NULL, "cannot setup "
15607 "policy port action");
15608 act_cnt->rix_port_id_action =
15609 dev_flow.handle->rix_port_id_action;
15610 act_cnt->fate_action =
15611 MLX5_FLOW_FATE_PORT_ID;
15612 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15615 case RTE_FLOW_ACTION_TYPE_JUMP:
15617 uint32_t jump_group = 0;
15618 uint32_t table = 0;
15619 struct mlx5_flow_tbl_data_entry *tbl_data;
15620 struct flow_grp_info grp_info = {
15621 .external = !!dev_flow.external,
15622 .transfer = !!transfer,
15623 .fdb_def_rule = !!priv->fdb_def_rule,
15625 .skip_scale = dev_flow.skip_scale &
15626 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15628 struct mlx5_flow_meter_sub_policy *sub_policy =
15629 mtr_policy->sub_policys[domain][0];
15631 if (i >= MLX5_MTR_RTE_COLORS)
15632 return -rte_mtr_error_set(error,
15634 RTE_MTR_ERROR_TYPE_METER_POLICY,
15636 "cannot create policy "
15637 "jump action for this color");
15639 ((const struct rte_flow_action_jump *)
15641 if (mlx5_flow_group_to_table(dev, NULL,
15644 &grp_info, &flow_err))
15645 return -rte_mtr_error_set(error,
15647 RTE_MTR_ERROR_TYPE_METER_POLICY,
15648 NULL, "cannot setup "
15649 "policy jump action");
15650 sub_policy->jump_tbl[i] =
15651 flow_dv_tbl_resource_get(dev,
15654 !!dev_flow.external,
15655 NULL, jump_group, 0,
15658 (!sub_policy->jump_tbl[i])
15659 return -rte_mtr_error_set(error,
15661 RTE_MTR_ERROR_TYPE_METER_POLICY,
15662 NULL, "cannot create jump action.");
15663 tbl_data = container_of
15664 (sub_policy->jump_tbl[i],
15665 struct mlx5_flow_tbl_data_entry, tbl);
15666 act_cnt->dr_jump_action[domain] =
15667 tbl_data->jump.action;
15668 act_cnt->fate_action =
15669 MLX5_FLOW_FATE_JUMP;
15670 action_flags |= MLX5_FLOW_ACTION_JUMP;
15674 * No need to check meter hierarchy for Y or R colors
15675 * here since it is done in the validation stage.
15677 case RTE_FLOW_ACTION_TYPE_METER:
15679 const struct rte_flow_action_meter *mtr;
15680 struct mlx5_flow_meter_info *next_fm;
15681 struct mlx5_flow_meter_policy *next_policy;
15682 struct rte_flow_action tag_action;
15683 struct mlx5_rte_flow_action_set_tag set_tag;
15684 uint32_t next_mtr_idx = 0;
15687 next_fm = mlx5_flow_meter_find(priv,
15691 return -rte_mtr_error_set(error, EINVAL,
15692 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15693 "Fail to find next meter.");
15694 if (next_fm->def_policy)
15695 return -rte_mtr_error_set(error, EINVAL,
15696 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15697 "Hierarchy only supports termination meter.");
15698 next_policy = mlx5_flow_meter_policy_find(dev,
15699 next_fm->policy_id, NULL);
15700 MLX5_ASSERT(next_policy);
15701 if (next_fm->drop_cnt) {
15704 mlx5_flow_get_reg_id(dev,
15707 (struct rte_flow_error *)error);
15708 set_tag.offset = (priv->mtr_reg_share ?
15709 MLX5_MTR_COLOR_BITS : 0);
15710 set_tag.length = (priv->mtr_reg_share ?
15711 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15713 set_tag.data = next_mtr_idx;
15715 (enum rte_flow_action_type)
15716 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15717 tag_action.conf = &set_tag;
15718 if (flow_dv_convert_action_set_reg
15719 (mhdr_res, &tag_action,
15720 (struct rte_flow_error *)error))
15723 MLX5_FLOW_ACTION_SET_TAG;
15725 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15726 act_cnt->next_mtr_id = next_fm->meter_id;
15727 act_cnt->next_sub_policy = NULL;
15728 mtr_policy->is_hierarchy = 1;
15729 mtr_policy->dev = next_policy->dev;
15731 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15735 return -rte_mtr_error_set(error, ENOTSUP,
15736 RTE_MTR_ERROR_TYPE_METER_POLICY,
15737 NULL, "action type not supported");
15739 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15740 /* create modify action if needed. */
15741 dev_flow.dv.group = 1;
15742 if (flow_dv_modify_hdr_resource_register
15743 (dev, mhdr_res, &dev_flow, &flow_err))
15744 return -rte_mtr_error_set(error,
15746 RTE_MTR_ERROR_TYPE_METER_POLICY,
15747 NULL, "cannot register policy "
15749 act_cnt->modify_hdr =
15750 dev_flow.handle->dvh.modify_hdr;
15758 * Create policy action per domain, lock free,
15759 * (mutex should be acquired by caller).
15760 * Dispatcher for action type specific call.
15763 * Pointer to the Ethernet device structure.
15764 * @param[in] mtr_policy
15765 * Meter policy struct.
15766 * @param[in] action
15767 * Action specification used to create meter actions.
15768 * @param[out] error
15769 * Perform verbose error reporting if not NULL. Initialized in case of
15773 * 0 on success, otherwise negative errno value.
15776 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15777 struct mlx5_flow_meter_policy *mtr_policy,
15778 const struct rte_flow_action *actions[RTE_COLORS],
15779 struct rte_mtr_error *error)
15782 uint16_t sub_policy_num;
15784 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15785 sub_policy_num = (mtr_policy->sub_policy_num >>
15786 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15787 MLX5_MTR_SUB_POLICY_NUM_MASK;
15788 if (sub_policy_num) {
15789 ret = __flow_dv_create_domain_policy_acts(dev,
15790 mtr_policy, actions,
15791 (enum mlx5_meter_domain)i, error);
15792 /* Cleaning resource is done in the caller level. */
15801 * Query a DV flow rule for its statistics via DevX.
15804 * Pointer to Ethernet device.
15805 * @param[in] cnt_idx
15806 * Index to the flow counter.
15808 * Data retrieved by the query.
15809 * @param[out] error
15810 * Perform verbose error reporting if not NULL.
15813 * 0 on success, a negative errno value otherwise and rte_errno is set.
15816 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15817 struct rte_flow_error *error)
15819 struct mlx5_priv *priv = dev->data->dev_private;
15820 struct rte_flow_query_count *qc = data;
15822 if (!priv->sh->devx)
15823 return rte_flow_error_set(error, ENOTSUP,
15824 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15826 "counters are not supported");
15828 uint64_t pkts, bytes;
15829 struct mlx5_flow_counter *cnt;
15830 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15833 return rte_flow_error_set(error, -err,
15834 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15835 NULL, "cannot read counters");
15836 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15839 qc->hits = pkts - cnt->hits;
15840 qc->bytes = bytes - cnt->bytes;
15843 cnt->bytes = bytes;
15847 return rte_flow_error_set(error, EINVAL,
15848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15850 "counters are not available");
15855 * Query counter's action pointer for a DV flow rule via DevX.
15858 * Pointer to Ethernet device.
15859 * @param[in] cnt_idx
15860 * Index to the flow counter.
15861 * @param[out] action_ptr
15862 * Action pointer for counter.
15863 * @param[out] error
15864 * Perform verbose error reporting if not NULL.
15867 * 0 on success, a negative errno value otherwise and rte_errno is set.
15870 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15871 void **action_ptr, struct rte_flow_error *error)
15873 struct mlx5_priv *priv = dev->data->dev_private;
15875 if (!priv->sh->devx || !action_ptr)
15876 return rte_flow_error_set(error, ENOTSUP,
15877 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15879 "counters are not supported");
15882 struct mlx5_flow_counter *cnt = NULL;
15883 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15885 *action_ptr = cnt->action;
15889 return rte_flow_error_set(error, EINVAL,
15890 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15892 "counters are not available");
15896 flow_dv_action_query(struct rte_eth_dev *dev,
15897 const struct rte_flow_action_handle *handle, void *data,
15898 struct rte_flow_error *error)
15900 struct mlx5_age_param *age_param;
15901 struct rte_flow_query_age *resp;
15902 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15903 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15904 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15905 struct mlx5_priv *priv = dev->data->dev_private;
15906 struct mlx5_aso_ct_action *ct;
15911 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15912 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15914 resp->aged = __atomic_load_n(&age_param->state,
15915 __ATOMIC_RELAXED) == AGE_TMOUT ?
15917 resp->sec_since_last_hit_valid = !resp->aged;
15918 if (resp->sec_since_last_hit_valid)
15919 resp->sec_since_last_hit = __atomic_load_n
15920 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15922 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15923 return flow_dv_query_count(dev, idx, data, error);
15924 case MLX5_INDIRECT_ACTION_TYPE_CT:
15925 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15926 if (owner != PORT_ID(priv))
15927 return rte_flow_error_set(error, EACCES,
15928 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15930 "CT object owned by another port");
15931 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15932 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15935 return rte_flow_error_set(error, EFAULT,
15936 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15938 "CT object is inactive");
15939 ((struct rte_flow_action_conntrack *)data)->peer_port =
15941 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15943 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15944 return rte_flow_error_set(error, EIO,
15945 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15947 "Failed to query CT context");
15950 return rte_flow_error_set(error, ENOTSUP,
15951 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15952 "action type query not supported");
15957 * Query a flow rule AGE action for aging information.
15960 * Pointer to Ethernet device.
15962 * Pointer to the sub flow.
15964 * data retrieved by the query.
15965 * @param[out] error
15966 * Perform verbose error reporting if not NULL.
15969 * 0 on success, a negative errno value otherwise and rte_errno is set.
15972 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15973 void *data, struct rte_flow_error *error)
15975 struct rte_flow_query_age *resp = data;
15976 struct mlx5_age_param *age_param;
15979 struct mlx5_aso_age_action *act =
15980 flow_aso_age_get_by_idx(dev, flow->age);
15982 age_param = &act->age_params;
15983 } else if (flow->counter) {
15984 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15986 if (!age_param || !age_param->timeout)
15987 return rte_flow_error_set
15989 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15990 NULL, "cannot read age data");
15992 return rte_flow_error_set(error, EINVAL,
15993 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15994 NULL, "age data not available");
15996 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15998 resp->sec_since_last_hit_valid = !resp->aged;
15999 if (resp->sec_since_last_hit_valid)
16000 resp->sec_since_last_hit = __atomic_load_n
16001 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16008 * @see rte_flow_query()
16009 * @see rte_flow_ops
16012 flow_dv_query(struct rte_eth_dev *dev,
16013 struct rte_flow *flow __rte_unused,
16014 const struct rte_flow_action *actions __rte_unused,
16015 void *data __rte_unused,
16016 struct rte_flow_error *error __rte_unused)
16020 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16021 switch (actions->type) {
16022 case RTE_FLOW_ACTION_TYPE_VOID:
16024 case RTE_FLOW_ACTION_TYPE_COUNT:
16025 ret = flow_dv_query_count(dev, flow->counter, data,
16028 case RTE_FLOW_ACTION_TYPE_AGE:
16029 ret = flow_dv_query_age(dev, flow, data, error);
16032 return rte_flow_error_set(error, ENOTSUP,
16033 RTE_FLOW_ERROR_TYPE_ACTION,
16035 "action not supported");
16042 * Destroy the meter table set.
16043 * Lock free, (mutex should be acquired by caller).
16046 * Pointer to Ethernet device.
16048 * Meter information table.
16051 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16052 struct mlx5_flow_meter_info *fm)
16054 struct mlx5_priv *priv = dev->data->dev_private;
16057 if (!fm || !priv->config.dv_flow_en)
16059 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16060 if (fm->drop_rule[i]) {
16061 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16062 fm->drop_rule[i] = NULL;
16068 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16070 struct mlx5_priv *priv = dev->data->dev_private;
16071 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16072 struct mlx5_flow_tbl_data_entry *tbl;
16075 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16076 if (mtrmng->def_rule[i]) {
16077 claim_zero(mlx5_flow_os_destroy_flow
16078 (mtrmng->def_rule[i]));
16079 mtrmng->def_rule[i] = NULL;
16081 if (mtrmng->def_matcher[i]) {
16082 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16083 struct mlx5_flow_tbl_data_entry, tbl);
16084 mlx5_list_unregister(tbl->matchers,
16085 &mtrmng->def_matcher[i]->entry);
16086 mtrmng->def_matcher[i] = NULL;
16088 for (j = 0; j < MLX5_REG_BITS; j++) {
16089 if (mtrmng->drop_matcher[i][j]) {
16091 container_of(mtrmng->drop_matcher[i][j]->tbl,
16092 struct mlx5_flow_tbl_data_entry,
16094 mlx5_list_unregister(tbl->matchers,
16095 &mtrmng->drop_matcher[i][j]->entry);
16096 mtrmng->drop_matcher[i][j] = NULL;
16099 if (mtrmng->drop_tbl[i]) {
16100 flow_dv_tbl_resource_release(MLX5_SH(dev),
16101 mtrmng->drop_tbl[i]);
16102 mtrmng->drop_tbl[i] = NULL;
16107 /* Number of meter flow actions, count and jump or count and drop. */
16108 #define METER_ACTIONS 2
16111 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16112 enum mlx5_meter_domain domain)
16114 struct mlx5_priv *priv = dev->data->dev_private;
16115 struct mlx5_flow_meter_def_policy *def_policy =
16116 priv->sh->mtrmng->def_policy[domain];
16118 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16119 mlx5_free(def_policy);
16120 priv->sh->mtrmng->def_policy[domain] = NULL;
16124 * Destroy the default policy table set.
16127 * Pointer to Ethernet device.
16130 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16132 struct mlx5_priv *priv = dev->data->dev_private;
16135 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16136 if (priv->sh->mtrmng->def_policy[i])
16137 __flow_dv_destroy_domain_def_policy(dev,
16138 (enum mlx5_meter_domain)i);
16139 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16143 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16144 uint32_t color_reg_c_idx,
16145 enum rte_color color, void *matcher_object,
16146 int actions_n, void *actions,
16147 bool match_src_port, const struct rte_flow_item *item,
16148 void **rule, const struct rte_flow_attr *attr)
16151 struct mlx5_flow_dv_match_params value = {
16152 .size = sizeof(value.buf),
16154 struct mlx5_flow_dv_match_params matcher = {
16155 .size = sizeof(matcher.buf),
16157 struct mlx5_priv *priv = dev->data->dev_private;
16160 if (match_src_port && (priv->representor || priv->master)) {
16161 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16162 value.buf, item, attr)) {
16163 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16164 " value with port.", color);
16168 flow_dv_match_meta_reg(matcher.buf, value.buf,
16169 (enum modify_reg)color_reg_c_idx,
16170 rte_col_2_mlx5_col(color), UINT32_MAX);
16171 misc_mask = flow_dv_matcher_enable(value.buf);
16172 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16173 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16174 actions_n, actions, rule);
16176 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16183 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16184 uint32_t color_reg_c_idx,
16186 struct mlx5_flow_meter_sub_policy *sub_policy,
16187 const struct rte_flow_attr *attr,
16188 bool match_src_port,
16189 const struct rte_flow_item *item,
16190 struct mlx5_flow_dv_matcher **policy_matcher,
16191 struct rte_flow_error *error)
16193 struct mlx5_list_entry *entry;
16194 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16195 struct mlx5_flow_dv_matcher matcher = {
16197 .size = sizeof(matcher.mask.buf),
16201 struct mlx5_flow_dv_match_params value = {
16202 .size = sizeof(value.buf),
16204 struct mlx5_flow_cb_ctx ctx = {
16208 struct mlx5_flow_tbl_data_entry *tbl_data;
16209 struct mlx5_priv *priv = dev->data->dev_private;
16210 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16212 if (match_src_port && (priv->representor || priv->master)) {
16213 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16214 value.buf, item, attr)) {
16215 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16216 " with port.", priority);
16220 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16221 if (priority < RTE_COLOR_RED)
16222 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16223 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16224 matcher.priority = priority;
16225 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16226 matcher.mask.size);
16227 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16229 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16233 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16238 * Create the policy rules per domain.
16241 * Pointer to Ethernet device.
16242 * @param[in] sub_policy
16243 * Pointer to sub policy table..
16244 * @param[in] egress
16245 * Direction of the table.
16246 * @param[in] transfer
16247 * E-Switch or NIC flow.
16249 * Pointer to policy action list per color.
16252 * 0 on success, -1 otherwise.
16255 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16256 struct mlx5_flow_meter_sub_policy *sub_policy,
16257 uint8_t egress, uint8_t transfer, bool match_src_port,
16258 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16260 struct mlx5_priv *priv = dev->data->dev_private;
16261 struct rte_flow_error flow_err;
16262 uint32_t color_reg_c_idx;
16263 struct rte_flow_attr attr = {
16264 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16267 .egress = !!egress,
16268 .transfer = !!transfer,
16272 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16273 struct mlx5_sub_policy_color_rule *color_rule;
16275 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16279 /* Create policy table with POLICY level. */
16280 if (!sub_policy->tbl_rsc)
16281 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16282 MLX5_FLOW_TABLE_LEVEL_POLICY,
16283 egress, transfer, false, NULL, 0, 0,
16284 sub_policy->idx, &flow_err);
16285 if (!sub_policy->tbl_rsc) {
16287 "Failed to create meter sub policy table.");
16290 /* Prepare matchers. */
16291 color_reg_c_idx = ret;
16292 for (i = 0; i < RTE_COLORS; i++) {
16293 TAILQ_INIT(&sub_policy->color_rules[i]);
16294 if (!acts[i].actions_n)
16296 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16297 sizeof(struct mlx5_sub_policy_color_rule),
16300 DRV_LOG(ERR, "No memory to create color rule.");
16303 tmp_rules[i] = color_rule;
16304 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16305 color_rule, next_port);
16306 color_rule->src_port = priv->representor_id;
16309 /* Create matchers for colors. */
16310 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16311 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16312 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16313 &attr, svport_match, NULL,
16314 &color_rule->matcher, &flow_err)) {
16315 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16318 /* Create flow, matching color. */
16319 if (__flow_dv_create_policy_flow(dev,
16320 color_reg_c_idx, (enum rte_color)i,
16321 color_rule->matcher->matcher_object,
16322 acts[i].actions_n, acts[i].dv_actions,
16323 svport_match, NULL, &color_rule->rule,
16325 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16331 /* All the policy rules will be cleared. */
16333 color_rule = tmp_rules[i];
16335 if (color_rule->rule)
16336 mlx5_flow_os_destroy_flow(color_rule->rule);
16337 if (color_rule->matcher) {
16338 struct mlx5_flow_tbl_data_entry *tbl =
16339 container_of(color_rule->matcher->tbl,
16340 typeof(*tbl), tbl);
16341 mlx5_list_unregister(tbl->matchers,
16342 &color_rule->matcher->entry);
16344 TAILQ_REMOVE(&sub_policy->color_rules[i],
16345 color_rule, next_port);
16346 mlx5_free(color_rule);
16353 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16354 struct mlx5_flow_meter_policy *mtr_policy,
16355 struct mlx5_flow_meter_sub_policy *sub_policy,
16358 struct mlx5_priv *priv = dev->data->dev_private;
16359 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16360 struct mlx5_flow_dv_tag_resource *tag;
16361 struct mlx5_flow_dv_port_id_action_resource *port_action;
16362 struct mlx5_hrxq *hrxq;
16363 struct mlx5_flow_meter_info *next_fm = NULL;
16364 struct mlx5_flow_meter_policy *next_policy;
16365 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16366 struct mlx5_flow_tbl_data_entry *tbl_data;
16367 struct rte_flow_error error;
16368 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16369 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16370 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16371 bool match_src_port = false;
16374 /* If RSS or Queue, no previous actions / rules is created. */
16375 for (i = 0; i < RTE_COLORS; i++) {
16376 acts[i].actions_n = 0;
16377 if (i == RTE_COLOR_RED) {
16378 /* Only support drop on red. */
16379 acts[i].dv_actions[0] =
16380 mtr_policy->dr_drop_action[domain];
16381 acts[i].actions_n = 1;
16384 if (i == RTE_COLOR_GREEN &&
16385 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16386 struct rte_flow_attr attr = {
16387 .transfer = transfer
16390 next_fm = mlx5_flow_meter_find(priv,
16391 mtr_policy->act_cnt[i].next_mtr_id,
16395 "Failed to get next hierarchy meter.");
16398 if (mlx5_flow_meter_attach(priv, next_fm,
16400 DRV_LOG(ERR, "%s", error.message);
16404 /* Meter action must be the first for TX. */
16406 acts[i].dv_actions[acts[i].actions_n] =
16407 next_fm->meter_action;
16408 acts[i].actions_n++;
16411 if (mtr_policy->act_cnt[i].rix_mark) {
16412 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16413 mtr_policy->act_cnt[i].rix_mark);
16415 DRV_LOG(ERR, "Failed to find "
16416 "mark action for policy.");
16419 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16420 acts[i].actions_n++;
16422 if (mtr_policy->act_cnt[i].modify_hdr) {
16423 acts[i].dv_actions[acts[i].actions_n] =
16424 mtr_policy->act_cnt[i].modify_hdr->action;
16425 acts[i].actions_n++;
16427 if (mtr_policy->act_cnt[i].fate_action) {
16428 switch (mtr_policy->act_cnt[i].fate_action) {
16429 case MLX5_FLOW_FATE_PORT_ID:
16430 port_action = mlx5_ipool_get
16431 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16432 mtr_policy->act_cnt[i].rix_port_id_action);
16433 if (!port_action) {
16434 DRV_LOG(ERR, "Failed to find "
16435 "port action for policy.");
16438 acts[i].dv_actions[acts[i].actions_n] =
16439 port_action->action;
16440 acts[i].actions_n++;
16441 mtr_policy->dev = dev;
16442 match_src_port = true;
16444 case MLX5_FLOW_FATE_DROP:
16445 case MLX5_FLOW_FATE_JUMP:
16446 acts[i].dv_actions[acts[i].actions_n] =
16447 mtr_policy->act_cnt[i].dr_jump_action[domain];
16448 acts[i].actions_n++;
16450 case MLX5_FLOW_FATE_SHARED_RSS:
16451 case MLX5_FLOW_FATE_QUEUE:
16452 hrxq = mlx5_ipool_get
16453 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16454 sub_policy->rix_hrxq[i]);
16456 DRV_LOG(ERR, "Failed to find "
16457 "queue action for policy.");
16460 acts[i].dv_actions[acts[i].actions_n] =
16462 acts[i].actions_n++;
16464 case MLX5_FLOW_FATE_MTR:
16467 "No next hierarchy meter.");
16471 acts[i].dv_actions[acts[i].actions_n] =
16472 next_fm->meter_action;
16473 acts[i].actions_n++;
16475 if (mtr_policy->act_cnt[i].next_sub_policy) {
16477 mtr_policy->act_cnt[i].next_sub_policy;
16480 mlx5_flow_meter_policy_find(dev,
16481 next_fm->policy_id, NULL);
16482 MLX5_ASSERT(next_policy);
16484 next_policy->sub_policys[domain][0];
16487 container_of(next_sub_policy->tbl_rsc,
16488 struct mlx5_flow_tbl_data_entry, tbl);
16489 acts[i].dv_actions[acts[i].actions_n++] =
16490 tbl_data->jump.action;
16491 if (mtr_policy->act_cnt[i].modify_hdr)
16492 match_src_port = !!transfer;
16495 /*Queue action do nothing*/
16500 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16501 egress, transfer, match_src_port, acts)) {
16503 "Failed to create policy rules per domain.");
16509 mlx5_flow_meter_detach(priv, next_fm);
16514 * Create the policy rules.
16517 * Pointer to Ethernet device.
16518 * @param[in,out] mtr_policy
16519 * Pointer to meter policy table.
16522 * 0 on success, -1 otherwise.
16525 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16526 struct mlx5_flow_meter_policy *mtr_policy)
16529 uint16_t sub_policy_num;
16531 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16532 sub_policy_num = (mtr_policy->sub_policy_num >>
16533 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16534 MLX5_MTR_SUB_POLICY_NUM_MASK;
16535 if (!sub_policy_num)
16537 /* Prepare actions list and create policy rules. */
16538 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16539 mtr_policy->sub_policys[i][0], i)) {
16540 DRV_LOG(ERR, "Failed to create policy action "
16541 "list per domain.");
16549 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16551 struct mlx5_priv *priv = dev->data->dev_private;
16552 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16553 struct mlx5_flow_meter_def_policy *def_policy;
16554 struct mlx5_flow_tbl_resource *jump_tbl;
16555 struct mlx5_flow_tbl_data_entry *tbl_data;
16556 uint8_t egress, transfer;
16557 struct rte_flow_error error;
16558 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16561 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16562 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16563 def_policy = mtrmng->def_policy[domain];
16565 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16566 sizeof(struct mlx5_flow_meter_def_policy),
16567 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16569 DRV_LOG(ERR, "Failed to alloc default policy table.");
16570 goto def_policy_error;
16572 mtrmng->def_policy[domain] = def_policy;
16573 /* Create the meter suffix table with SUFFIX level. */
16574 jump_tbl = flow_dv_tbl_resource_get(dev,
16575 MLX5_FLOW_TABLE_LEVEL_METER,
16576 egress, transfer, false, NULL, 0,
16577 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16580 "Failed to create meter suffix table.");
16581 goto def_policy_error;
16583 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16584 tbl_data = container_of(jump_tbl,
16585 struct mlx5_flow_tbl_data_entry, tbl);
16586 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16587 tbl_data->jump.action;
16588 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16589 acts[RTE_COLOR_GREEN].actions_n = 1;
16591 * YELLOW has the same default policy as GREEN does.
16592 * G & Y share the same table and action. The 2nd time of table
16593 * resource getting is just to update the reference count for
16594 * the releasing stage.
16596 jump_tbl = flow_dv_tbl_resource_get(dev,
16597 MLX5_FLOW_TABLE_LEVEL_METER,
16598 egress, transfer, false, NULL, 0,
16599 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16602 "Failed to get meter suffix table.");
16603 goto def_policy_error;
16605 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16606 tbl_data = container_of(jump_tbl,
16607 struct mlx5_flow_tbl_data_entry, tbl);
16608 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16609 tbl_data->jump.action;
16610 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16611 acts[RTE_COLOR_YELLOW].actions_n = 1;
16612 /* Create jump action to the drop table. */
16613 if (!mtrmng->drop_tbl[domain]) {
16614 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16615 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16616 egress, transfer, false, NULL, 0,
16617 0, MLX5_MTR_TABLE_ID_DROP, &error);
16618 if (!mtrmng->drop_tbl[domain]) {
16619 DRV_LOG(ERR, "Failed to create meter "
16620 "drop table for default policy.");
16621 goto def_policy_error;
16624 /* all RED: unique Drop table for jump action. */
16625 tbl_data = container_of(mtrmng->drop_tbl[domain],
16626 struct mlx5_flow_tbl_data_entry, tbl);
16627 def_policy->dr_jump_action[RTE_COLOR_RED] =
16628 tbl_data->jump.action;
16629 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16630 acts[RTE_COLOR_RED].actions_n = 1;
16631 /* Create default policy rules. */
16632 ret = __flow_dv_create_domain_policy_rules(dev,
16633 &def_policy->sub_policy,
16634 egress, transfer, false, acts);
16636 DRV_LOG(ERR, "Failed to create default policy rules.");
16637 goto def_policy_error;
16642 __flow_dv_destroy_domain_def_policy(dev,
16643 (enum mlx5_meter_domain)domain);
16648 * Create the default policy table set.
16651 * Pointer to Ethernet device.
16653 * 0 on success, -1 otherwise.
16656 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16658 struct mlx5_priv *priv = dev->data->dev_private;
16661 /* Non-termination policy table. */
16662 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16663 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16665 if (__flow_dv_create_domain_def_policy(dev, i)) {
16666 DRV_LOG(ERR, "Failed to create default policy");
16667 /* Rollback the created default policies for others. */
16668 flow_dv_destroy_def_policy(dev);
16676 * Create the needed meter tables.
16677 * Lock free, (mutex should be acquired by caller).
16680 * Pointer to Ethernet device.
16682 * Meter information table.
16683 * @param[in] mtr_idx
16685 * @param[in] domain_bitmap
16688 * 0 on success, -1 otherwise.
16691 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16692 struct mlx5_flow_meter_info *fm,
16694 uint8_t domain_bitmap)
16696 struct mlx5_priv *priv = dev->data->dev_private;
16697 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16698 struct rte_flow_error error;
16699 struct mlx5_flow_tbl_data_entry *tbl_data;
16700 uint8_t egress, transfer;
16701 void *actions[METER_ACTIONS];
16702 int domain, ret, i;
16703 struct mlx5_flow_counter *cnt;
16704 struct mlx5_flow_dv_match_params value = {
16705 .size = sizeof(value.buf),
16707 struct mlx5_flow_dv_match_params matcher_para = {
16708 .size = sizeof(matcher_para.buf),
16710 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16712 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16713 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16714 struct mlx5_list_entry *entry;
16715 struct mlx5_flow_dv_matcher matcher = {
16717 .size = sizeof(matcher.mask.buf),
16720 struct mlx5_flow_dv_matcher *drop_matcher;
16721 struct mlx5_flow_cb_ctx ctx = {
16727 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16728 rte_errno = ENOTSUP;
16731 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16732 if (!(domain_bitmap & (1 << domain)) ||
16733 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16735 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16736 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16737 /* Create the drop table with METER DROP level. */
16738 if (!mtrmng->drop_tbl[domain]) {
16739 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16740 MLX5_FLOW_TABLE_LEVEL_METER,
16741 egress, transfer, false, NULL, 0,
16742 0, MLX5_MTR_TABLE_ID_DROP, &error);
16743 if (!mtrmng->drop_tbl[domain]) {
16744 DRV_LOG(ERR, "Failed to create meter drop table.");
16748 /* Create default matcher in drop table. */
16749 matcher.tbl = mtrmng->drop_tbl[domain],
16750 tbl_data = container_of(mtrmng->drop_tbl[domain],
16751 struct mlx5_flow_tbl_data_entry, tbl);
16752 if (!mtrmng->def_matcher[domain]) {
16753 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16754 (enum modify_reg)mtr_id_reg_c,
16756 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16757 matcher.crc = rte_raw_cksum
16758 ((const void *)matcher.mask.buf,
16759 matcher.mask.size);
16760 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16762 DRV_LOG(ERR, "Failed to register meter "
16763 "drop default matcher.");
16766 mtrmng->def_matcher[domain] = container_of(entry,
16767 struct mlx5_flow_dv_matcher, entry);
16769 /* Create default rule in drop table. */
16770 if (!mtrmng->def_rule[domain]) {
16772 actions[i++] = priv->sh->dr_drop_action;
16773 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16774 (enum modify_reg)mtr_id_reg_c, 0, 0);
16775 misc_mask = flow_dv_matcher_enable(value.buf);
16776 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16777 ret = mlx5_flow_os_create_flow
16778 (mtrmng->def_matcher[domain]->matcher_object,
16779 (void *)&value, i, actions,
16780 &mtrmng->def_rule[domain]);
16782 DRV_LOG(ERR, "Failed to create meter "
16783 "default drop rule for drop table.");
16789 MLX5_ASSERT(mtrmng->max_mtr_bits);
16790 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16791 /* Create matchers for Drop. */
16792 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16793 (enum modify_reg)mtr_id_reg_c, 0,
16794 (mtr_id_mask << mtr_id_offset));
16795 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16796 matcher.crc = rte_raw_cksum
16797 ((const void *)matcher.mask.buf,
16798 matcher.mask.size);
16799 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16802 "Failed to register meter drop matcher.");
16805 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16806 container_of(entry, struct mlx5_flow_dv_matcher,
16810 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16811 /* Create drop rule, matching meter_id only. */
16812 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16813 (enum modify_reg)mtr_id_reg_c,
16814 (mtr_idx << mtr_id_offset), UINT32_MAX);
16816 cnt = flow_dv_counter_get_by_idx(dev,
16817 fm->drop_cnt, NULL);
16818 actions[i++] = cnt->action;
16819 actions[i++] = priv->sh->dr_drop_action;
16820 misc_mask = flow_dv_matcher_enable(value.buf);
16821 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16822 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16823 (void *)&value, i, actions,
16824 &fm->drop_rule[domain]);
16826 DRV_LOG(ERR, "Failed to create meter "
16827 "drop rule for drop table.");
16833 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16834 if (fm->drop_rule[i]) {
16835 claim_zero(mlx5_flow_os_destroy_flow
16836 (fm->drop_rule[i]));
16837 fm->drop_rule[i] = NULL;
16843 static struct mlx5_flow_meter_sub_policy *
16844 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16845 struct mlx5_flow_meter_policy *mtr_policy,
16846 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16847 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16850 struct mlx5_priv *priv = dev->data->dev_private;
16851 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16852 uint32_t sub_policy_idx = 0;
16853 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16855 struct mlx5_hrxq *hrxq;
16856 struct mlx5_flow_handle dh;
16857 struct mlx5_meter_policy_action_container *act_cnt;
16858 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16859 uint16_t sub_policy_num;
16861 rte_spinlock_lock(&mtr_policy->sl);
16862 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16865 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16866 if (!hrxq_idx[i]) {
16867 rte_spinlock_unlock(&mtr_policy->sl);
16871 sub_policy_num = (mtr_policy->sub_policy_num >>
16872 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16873 MLX5_MTR_SUB_POLICY_NUM_MASK;
16874 for (j = 0; j < sub_policy_num; j++) {
16875 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16878 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16881 if (i >= MLX5_MTR_RTE_COLORS) {
16883 * Found the sub policy table with
16884 * the same queue per color.
16886 rte_spinlock_unlock(&mtr_policy->sl);
16887 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16888 mlx5_hrxq_release(dev, hrxq_idx[i]);
16890 return mtr_policy->sub_policys[domain][j];
16893 /* Create sub policy. */
16894 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16895 /* Reuse the first pre-allocated sub_policy. */
16896 sub_policy = mtr_policy->sub_policys[domain][0];
16897 sub_policy_idx = sub_policy->idx;
16899 sub_policy = mlx5_ipool_zmalloc
16900 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16903 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16904 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16905 mlx5_hrxq_release(dev, hrxq_idx[i]);
16906 goto rss_sub_policy_error;
16908 sub_policy->idx = sub_policy_idx;
16909 sub_policy->main_policy = mtr_policy;
16911 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16914 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16915 if (mtr_policy->is_hierarchy) {
16916 act_cnt = &mtr_policy->act_cnt[i];
16917 act_cnt->next_sub_policy = next_sub_policy;
16918 mlx5_hrxq_release(dev, hrxq_idx[i]);
16921 * Overwrite the last action from
16922 * RSS action to Queue action.
16924 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16927 DRV_LOG(ERR, "Failed to get policy hrxq");
16928 goto rss_sub_policy_error;
16930 act_cnt = &mtr_policy->act_cnt[i];
16931 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16932 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16933 if (act_cnt->rix_mark)
16935 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16936 dh.rix_hrxq = hrxq_idx[i];
16937 flow_drv_rxq_flags_set(dev, &dh);
16941 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16942 sub_policy, domain)) {
16943 DRV_LOG(ERR, "Failed to create policy "
16944 "rules for ingress domain.");
16945 goto rss_sub_policy_error;
16947 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16948 i = (mtr_policy->sub_policy_num >>
16949 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16950 MLX5_MTR_SUB_POLICY_NUM_MASK;
16951 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16952 DRV_LOG(ERR, "No free sub-policy slot.");
16953 goto rss_sub_policy_error;
16955 mtr_policy->sub_policys[domain][i] = sub_policy;
16957 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16958 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16959 mtr_policy->sub_policy_num |=
16960 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16961 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16963 rte_spinlock_unlock(&mtr_policy->sl);
16966 rss_sub_policy_error:
16968 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16969 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16970 i = (mtr_policy->sub_policy_num >>
16971 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16972 MLX5_MTR_SUB_POLICY_NUM_MASK;
16973 mtr_policy->sub_policys[domain][i] = NULL;
16974 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16978 rte_spinlock_unlock(&mtr_policy->sl);
16983 * Find the policy table for prefix table with RSS.
16986 * Pointer to Ethernet device.
16987 * @param[in] mtr_policy
16988 * Pointer to meter policy table.
16989 * @param[in] rss_desc
16990 * Pointer to rss_desc
16992 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16994 static struct mlx5_flow_meter_sub_policy *
16995 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16996 struct mlx5_flow_meter_policy *mtr_policy,
16997 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16999 struct mlx5_priv *priv = dev->data->dev_private;
17000 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17001 struct mlx5_flow_meter_info *next_fm;
17002 struct mlx5_flow_meter_policy *next_policy;
17003 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17004 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17005 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17006 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17007 bool reuse_sub_policy;
17012 /* Iterate hierarchy to get all policies in this hierarchy. */
17013 policies[i++] = mtr_policy;
17014 if (!mtr_policy->is_hierarchy)
17016 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17017 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17020 next_fm = mlx5_flow_meter_find(priv,
17021 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17023 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17027 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17029 MLX5_ASSERT(next_policy);
17030 mtr_policy = next_policy;
17034 * From last policy to the first one in hierarchy,
17035 * create / get the sub policy for each of them.
17037 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17041 &reuse_sub_policy);
17043 DRV_LOG(ERR, "Failed to get the sub policy.");
17046 if (!reuse_sub_policy)
17047 sub_policies[j++] = sub_policy;
17048 next_sub_policy = sub_policy;
17053 uint16_t sub_policy_num;
17055 sub_policy = sub_policies[--j];
17056 mtr_policy = sub_policy->main_policy;
17057 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17058 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17059 sub_policy_num = (mtr_policy->sub_policy_num >>
17060 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17061 MLX5_MTR_SUB_POLICY_NUM_MASK;
17062 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17065 mtr_policy->sub_policy_num &=
17066 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17067 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17068 mtr_policy->sub_policy_num |=
17069 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17070 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17071 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17079 * Create the sub policy tag rule for all meters in hierarchy.
17082 * Pointer to Ethernet device.
17084 * Meter information table.
17085 * @param[in] src_port
17086 * The src port this extra rule should use.
17088 * The src port match item.
17089 * @param[out] error
17090 * Perform verbose error reporting if not NULL.
17092 * 0 on success, a negative errno value otherwise and rte_errno is set.
17095 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17096 struct mlx5_flow_meter_info *fm,
17098 const struct rte_flow_item *item,
17099 struct rte_flow_error *error)
17101 struct mlx5_priv *priv = dev->data->dev_private;
17102 struct mlx5_flow_meter_policy *mtr_policy;
17103 struct mlx5_flow_meter_sub_policy *sub_policy;
17104 struct mlx5_flow_meter_info *next_fm = NULL;
17105 struct mlx5_flow_meter_policy *next_policy;
17106 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17107 struct mlx5_flow_tbl_data_entry *tbl_data;
17108 struct mlx5_sub_policy_color_rule *color_rule;
17109 struct mlx5_meter_policy_acts acts;
17110 uint32_t color_reg_c_idx;
17111 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17112 struct rte_flow_attr attr = {
17113 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17120 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17123 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17124 MLX5_ASSERT(mtr_policy);
17125 if (!mtr_policy->is_hierarchy)
17127 next_fm = mlx5_flow_meter_find(priv,
17128 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17130 return rte_flow_error_set(error, EINVAL,
17131 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17132 "Failed to find next meter in hierarchy.");
17134 if (!next_fm->drop_cnt)
17136 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17137 sub_policy = mtr_policy->sub_policys[domain][0];
17138 for (i = 0; i < RTE_COLORS; i++) {
17139 bool rule_exist = false;
17140 struct mlx5_meter_policy_action_container *act_cnt;
17142 if (i >= RTE_COLOR_YELLOW)
17144 TAILQ_FOREACH(color_rule,
17145 &sub_policy->color_rules[i], next_port)
17146 if (color_rule->src_port == src_port) {
17152 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17153 sizeof(struct mlx5_sub_policy_color_rule),
17156 return rte_flow_error_set(error, ENOMEM,
17157 RTE_FLOW_ERROR_TYPE_ACTION,
17158 NULL, "No memory to create tag color rule.");
17159 color_rule->src_port = src_port;
17161 next_policy = mlx5_flow_meter_policy_find(dev,
17162 next_fm->policy_id, NULL);
17163 MLX5_ASSERT(next_policy);
17164 next_sub_policy = next_policy->sub_policys[domain][0];
17165 tbl_data = container_of(next_sub_policy->tbl_rsc,
17166 struct mlx5_flow_tbl_data_entry, tbl);
17167 act_cnt = &mtr_policy->act_cnt[i];
17169 acts.dv_actions[0] = next_fm->meter_action;
17170 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17172 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17173 acts.dv_actions[1] = next_fm->meter_action;
17175 acts.dv_actions[2] = tbl_data->jump.action;
17176 acts.actions_n = 3;
17177 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17181 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17182 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17184 &color_rule->matcher, error)) {
17185 rte_flow_error_set(error, errno,
17186 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17187 "Failed to create hierarchy meter matcher.");
17190 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17192 color_rule->matcher->matcher_object,
17193 acts.actions_n, acts.dv_actions,
17195 &color_rule->rule, &attr)) {
17196 rte_flow_error_set(error, errno,
17197 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17198 "Failed to create hierarchy meter rule.");
17201 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17202 color_rule, next_port);
17206 * Recursive call to iterate all meters in hierarchy and
17207 * create needed rules.
17209 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17210 src_port, item, error);
17213 if (color_rule->rule)
17214 mlx5_flow_os_destroy_flow(color_rule->rule);
17215 if (color_rule->matcher) {
17216 struct mlx5_flow_tbl_data_entry *tbl =
17217 container_of(color_rule->matcher->tbl,
17218 typeof(*tbl), tbl);
17219 mlx5_list_unregister(tbl->matchers,
17220 &color_rule->matcher->entry);
17222 mlx5_free(color_rule);
17225 mlx5_flow_meter_detach(priv, next_fm);
17230 * Destroy the sub policy table with RX queue.
17233 * Pointer to Ethernet device.
17234 * @param[in] mtr_policy
17235 * Pointer to meter policy table.
17238 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17239 struct mlx5_flow_meter_policy *mtr_policy)
17241 struct mlx5_priv *priv = dev->data->dev_private;
17242 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17243 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17245 uint16_t sub_policy_num, new_policy_num;
17247 rte_spinlock_lock(&mtr_policy->sl);
17248 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17249 switch (mtr_policy->act_cnt[i].fate_action) {
17250 case MLX5_FLOW_FATE_SHARED_RSS:
17251 sub_policy_num = (mtr_policy->sub_policy_num >>
17252 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17253 MLX5_MTR_SUB_POLICY_NUM_MASK;
17254 new_policy_num = sub_policy_num;
17255 for (j = 0; j < sub_policy_num; j++) {
17257 mtr_policy->sub_policys[domain][j];
17259 __flow_dv_destroy_sub_policy_rules(dev,
17262 mtr_policy->sub_policys[domain][0]) {
17263 mtr_policy->sub_policys[domain][j] =
17266 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17272 if (new_policy_num != sub_policy_num) {
17273 mtr_policy->sub_policy_num &=
17274 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17275 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17276 mtr_policy->sub_policy_num |=
17278 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17279 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17282 case MLX5_FLOW_FATE_QUEUE:
17283 sub_policy = mtr_policy->sub_policys[domain][0];
17284 __flow_dv_destroy_sub_policy_rules(dev,
17288 /*Other actions without queue and do nothing*/
17292 rte_spinlock_unlock(&mtr_policy->sl);
17295 * Check whether the DR drop action is supported on the root table or not.
17297 * Create a simple flow with DR drop action on root table to validate
17298 * if DR drop action on root table is supported or not.
17301 * Pointer to rte_eth_dev structure.
17304 * 0 on success, a negative errno value otherwise and rte_errno is set.
17307 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17309 struct mlx5_priv *priv = dev->data->dev_private;
17310 struct mlx5_dev_ctx_shared *sh = priv->sh;
17311 struct mlx5_flow_dv_match_params mask = {
17312 .size = sizeof(mask.buf),
17314 struct mlx5_flow_dv_match_params value = {
17315 .size = sizeof(value.buf),
17317 struct mlx5dv_flow_matcher_attr dv_attr = {
17318 .type = IBV_FLOW_ATTR_NORMAL,
17320 .match_criteria_enable = 0,
17321 .match_mask = (void *)&mask,
17323 struct mlx5_flow_tbl_resource *tbl = NULL;
17324 void *matcher = NULL;
17328 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17332 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17333 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17334 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17335 tbl->obj, &matcher);
17338 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17339 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17340 &sh->dr_drop_action, &flow);
17343 * If DR drop action is not supported on root table, flow create will
17344 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17348 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17349 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17351 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17354 claim_zero(mlx5_flow_os_destroy_flow(flow));
17357 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17359 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17364 * Validate the batch counter support in root table.
17366 * Create a simple flow with invalid counter and drop action on root table to
17367 * validate if batch counter with offset on root table is supported or not.
17370 * Pointer to rte_eth_dev structure.
17373 * 0 on success, a negative errno value otherwise and rte_errno is set.
17376 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17378 struct mlx5_priv *priv = dev->data->dev_private;
17379 struct mlx5_dev_ctx_shared *sh = priv->sh;
17380 struct mlx5_flow_dv_match_params mask = {
17381 .size = sizeof(mask.buf),
17383 struct mlx5_flow_dv_match_params value = {
17384 .size = sizeof(value.buf),
17386 struct mlx5dv_flow_matcher_attr dv_attr = {
17387 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17389 .match_criteria_enable = 0,
17390 .match_mask = (void *)&mask,
17392 void *actions[2] = { 0 };
17393 struct mlx5_flow_tbl_resource *tbl = NULL;
17394 struct mlx5_devx_obj *dcs = NULL;
17395 void *matcher = NULL;
17399 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17403 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17406 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17410 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17411 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17412 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17413 tbl->obj, &matcher);
17416 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17417 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17421 * If batch counter with offset is not supported, the driver will not
17422 * validate the invalid offset value, flow create should success.
17423 * In this case, it means batch counter is not supported in root table.
17425 * Otherwise, if flow create is failed, counter offset is supported.
17428 DRV_LOG(INFO, "Batch counter is not supported in root "
17429 "table. Switch to fallback mode.");
17430 rte_errno = ENOTSUP;
17432 claim_zero(mlx5_flow_os_destroy_flow(flow));
17434 /* Check matcher to make sure validate fail at flow create. */
17435 if (!matcher || (matcher && errno != EINVAL))
17436 DRV_LOG(ERR, "Unexpected error in counter offset "
17437 "support detection");
17441 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17443 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17445 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17447 claim_zero(mlx5_devx_cmd_destroy(dcs));
17452 * Query a devx counter.
17455 * Pointer to the Ethernet device structure.
17457 * Index to the flow counter.
17459 * Set to clear the counter statistics.
17461 * The statistics value of packets.
17462 * @param[out] bytes
17463 * The statistics value of bytes.
17466 * 0 on success, otherwise return -1.
17469 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17470 uint64_t *pkts, uint64_t *bytes)
17472 struct mlx5_priv *priv = dev->data->dev_private;
17473 struct mlx5_flow_counter *cnt;
17474 uint64_t inn_pkts, inn_bytes;
17477 if (!priv->sh->devx)
17480 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17483 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17484 *pkts = inn_pkts - cnt->hits;
17485 *bytes = inn_bytes - cnt->bytes;
17487 cnt->hits = inn_pkts;
17488 cnt->bytes = inn_bytes;
17494 * Get aged-out flows.
17497 * Pointer to the Ethernet device structure.
17498 * @param[in] context
17499 * The address of an array of pointers to the aged-out flows contexts.
17500 * @param[in] nb_contexts
17501 * The length of context array pointers.
17502 * @param[out] error
17503 * Perform verbose error reporting if not NULL. Initialized in case of
17507 * how many contexts get in success, otherwise negative errno value.
17508 * if nb_contexts is 0, return the amount of all aged contexts.
17509 * if nb_contexts is not 0 , return the amount of aged flows reported
17510 * in the context array.
17511 * @note: only stub for now
17514 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17516 uint32_t nb_contexts,
17517 struct rte_flow_error *error)
17519 struct mlx5_priv *priv = dev->data->dev_private;
17520 struct mlx5_age_info *age_info;
17521 struct mlx5_age_param *age_param;
17522 struct mlx5_flow_counter *counter;
17523 struct mlx5_aso_age_action *act;
17526 if (nb_contexts && !context)
17527 return rte_flow_error_set(error, EINVAL,
17528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17529 NULL, "empty context");
17530 age_info = GET_PORT_AGE_INFO(priv);
17531 rte_spinlock_lock(&age_info->aged_sl);
17532 LIST_FOREACH(act, &age_info->aged_aso, next) {
17535 context[nb_flows - 1] =
17536 act->age_params.context;
17537 if (!(--nb_contexts))
17541 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17544 age_param = MLX5_CNT_TO_AGE(counter);
17545 context[nb_flows - 1] = age_param->context;
17546 if (!(--nb_contexts))
17550 rte_spinlock_unlock(&age_info->aged_sl);
17551 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17556 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17559 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17561 return flow_dv_counter_alloc(dev, 0);
17565 * Validate indirect action.
17566 * Dispatcher for action type specific validation.
17569 * Pointer to the Ethernet device structure.
17571 * Indirect action configuration.
17572 * @param[in] action
17573 * The indirect action object to validate.
17574 * @param[out] error
17575 * Perform verbose error reporting if not NULL. Initialized in case of
17579 * 0 on success, otherwise negative errno value.
17582 flow_dv_action_validate(struct rte_eth_dev *dev,
17583 const struct rte_flow_indir_action_conf *conf,
17584 const struct rte_flow_action *action,
17585 struct rte_flow_error *err)
17587 struct mlx5_priv *priv = dev->data->dev_private;
17589 RTE_SET_USED(conf);
17590 switch (action->type) {
17591 case RTE_FLOW_ACTION_TYPE_RSS:
17593 * priv->obj_ops is set according to driver capabilities.
17594 * When DevX capabilities are
17595 * sufficient, it is set to devx_obj_ops.
17596 * Otherwise, it is set to ibv_obj_ops.
17597 * ibv_obj_ops doesn't support ind_table_modify operation.
17598 * In this case the indirect RSS action can't be used.
17600 if (priv->obj_ops.ind_table_modify == NULL)
17601 return rte_flow_error_set
17603 RTE_FLOW_ERROR_TYPE_ACTION,
17605 "Indirect RSS action not supported");
17606 return mlx5_validate_action_rss(dev, action, err);
17607 case RTE_FLOW_ACTION_TYPE_AGE:
17608 if (!priv->sh->aso_age_mng)
17609 return rte_flow_error_set(err, ENOTSUP,
17610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17612 "Indirect age action not supported");
17613 return flow_dv_validate_action_age(0, action, dev, err);
17614 case RTE_FLOW_ACTION_TYPE_COUNT:
17615 return flow_dv_validate_action_count(dev, true, 0, err);
17616 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17617 if (!priv->sh->ct_aso_en)
17618 return rte_flow_error_set(err, ENOTSUP,
17619 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17620 "ASO CT is not supported");
17621 return mlx5_validate_action_ct(dev, action->conf, err);
17623 return rte_flow_error_set(err, ENOTSUP,
17624 RTE_FLOW_ERROR_TYPE_ACTION,
17626 "action type not supported");
17631 * Check if the RSS configurations for colors of a meter policy match
17632 * each other, except the queues.
17635 * Pointer to the first RSS flow action.
17637 * Pointer to the second RSS flow action.
17640 * 0 on match, 1 on conflict.
17643 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17644 const struct rte_flow_action_rss *r2)
17646 if (r1 == NULL || r2 == NULL)
17648 if (!(r1->level <= 1 && r2->level <= 1) &&
17649 !(r1->level > 1 && r2->level > 1))
17651 if (r1->types != r2->types &&
17652 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17653 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17655 if (r1->key || r2->key) {
17656 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17657 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17659 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17666 * Validate the meter hierarchy chain for meter policy.
17669 * Pointer to the Ethernet device structure.
17670 * @param[in] meter_id
17672 * @param[in] action_flags
17673 * Holds the actions detected until now.
17674 * @param[out] is_rss
17676 * @param[out] hierarchy_domain
17677 * The domain bitmap for hierarchy policy.
17678 * @param[out] error
17679 * Perform verbose error reporting if not NULL. Initialized in case of
17683 * 0 on success, otherwise negative errno value with error set.
17686 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17688 uint64_t action_flags,
17690 uint8_t *hierarchy_domain,
17691 struct rte_mtr_error *error)
17693 struct mlx5_priv *priv = dev->data->dev_private;
17694 struct mlx5_flow_meter_info *fm;
17695 struct mlx5_flow_meter_policy *policy;
17698 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17699 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17700 return -rte_mtr_error_set(error, EINVAL,
17701 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17703 "Multiple fate actions not supported.");
17704 *hierarchy_domain = 0;
17706 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17708 return -rte_mtr_error_set(error, EINVAL,
17709 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17710 "Meter not found in meter hierarchy.");
17711 if (fm->def_policy)
17712 return -rte_mtr_error_set(error, EINVAL,
17713 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17714 "Non termination meter not supported in hierarchy.");
17715 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17716 MLX5_ASSERT(policy);
17718 * Only inherit the supported domains of the first meter in
17720 * One meter supports at least one domain.
17722 if (!*hierarchy_domain) {
17723 if (policy->transfer)
17724 *hierarchy_domain |=
17725 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17726 if (policy->ingress)
17727 *hierarchy_domain |=
17728 MLX5_MTR_DOMAIN_INGRESS_BIT;
17729 if (policy->egress)
17730 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17732 if (!policy->is_hierarchy) {
17733 *is_rss = policy->is_rss;
17736 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17737 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17738 return -rte_mtr_error_set(error, EINVAL,
17739 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17740 "Exceed max hierarchy meter number.");
17746 * Validate meter policy actions.
17747 * Dispatcher for action type specific validation.
17750 * Pointer to the Ethernet device structure.
17751 * @param[in] action
17752 * The meter policy action object to validate.
17754 * Attributes of flow to determine steering domain.
17755 * @param[out] error
17756 * Perform verbose error reporting if not NULL. Initialized in case of
17760 * 0 on success, otherwise negative errno value.
17763 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17764 const struct rte_flow_action *actions[RTE_COLORS],
17765 struct rte_flow_attr *attr,
17767 uint8_t *domain_bitmap,
17768 uint8_t *policy_mode,
17769 struct rte_mtr_error *error)
17771 struct mlx5_priv *priv = dev->data->dev_private;
17772 struct mlx5_dev_config *dev_conf = &priv->config;
17773 const struct rte_flow_action *act;
17774 uint64_t action_flags[RTE_COLORS] = {0};
17777 struct rte_flow_error flow_err;
17778 uint8_t domain_color[RTE_COLORS] = {0};
17779 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17780 uint8_t hierarchy_domain = 0;
17781 const struct rte_flow_action_meter *mtr;
17782 bool def_green = false;
17783 bool def_yellow = false;
17784 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17786 if (!priv->config.dv_esw_en)
17787 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17788 *domain_bitmap = def_domain;
17789 /* Red color could only support DROP action. */
17790 if (!actions[RTE_COLOR_RED] ||
17791 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17792 return -rte_mtr_error_set(error, ENOTSUP,
17793 RTE_MTR_ERROR_TYPE_METER_POLICY,
17794 NULL, "Red color only supports drop action.");
17796 * Check default policy actions:
17797 * Green / Yellow: no action, Red: drop action
17798 * Either G or Y will trigger default policy actions to be created.
17800 if (!actions[RTE_COLOR_GREEN] ||
17801 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17803 if (!actions[RTE_COLOR_YELLOW] ||
17804 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17806 if (def_green && def_yellow) {
17807 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17809 } else if (!def_green && def_yellow) {
17810 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17811 } else if (def_green && !def_yellow) {
17812 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17814 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17816 /* Set to empty string in case of NULL pointer access by user. */
17817 flow_err.message = "";
17818 for (i = 0; i < RTE_COLORS; i++) {
17820 for (action_flags[i] = 0, actions_n = 0;
17821 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17823 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17824 return -rte_mtr_error_set(error, ENOTSUP,
17825 RTE_MTR_ERROR_TYPE_METER_POLICY,
17826 NULL, "too many actions");
17827 switch (act->type) {
17828 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17829 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17830 if (!priv->config.dv_esw_en)
17831 return -rte_mtr_error_set(error,
17833 RTE_MTR_ERROR_TYPE_METER_POLICY,
17834 NULL, "PORT action validate check"
17835 " fail for ESW disable");
17836 ret = flow_dv_validate_action_port_id(dev,
17838 act, attr, &flow_err);
17840 return -rte_mtr_error_set(error,
17842 RTE_MTR_ERROR_TYPE_METER_POLICY,
17843 NULL, flow_err.message ?
17845 "PORT action validate check fail");
17847 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17849 case RTE_FLOW_ACTION_TYPE_MARK:
17850 ret = flow_dv_validate_action_mark(dev, act,
17854 return -rte_mtr_error_set(error,
17856 RTE_MTR_ERROR_TYPE_METER_POLICY,
17857 NULL, flow_err.message ?
17859 "Mark action validate check fail");
17860 if (dev_conf->dv_xmeta_en !=
17861 MLX5_XMETA_MODE_LEGACY)
17862 return -rte_mtr_error_set(error,
17864 RTE_MTR_ERROR_TYPE_METER_POLICY,
17865 NULL, "Extend MARK action is "
17866 "not supported. Please try use "
17867 "default policy for meter.");
17868 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17871 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17872 ret = flow_dv_validate_action_set_tag(dev,
17873 act, action_flags[i],
17876 return -rte_mtr_error_set(error,
17878 RTE_MTR_ERROR_TYPE_METER_POLICY,
17879 NULL, flow_err.message ?
17881 "Set tag action validate check fail");
17882 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17885 case RTE_FLOW_ACTION_TYPE_DROP:
17886 ret = mlx5_flow_validate_action_drop
17887 (action_flags[i], attr, &flow_err);
17889 return -rte_mtr_error_set(error,
17891 RTE_MTR_ERROR_TYPE_METER_POLICY,
17892 NULL, flow_err.message ?
17894 "Drop action validate check fail");
17895 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17898 case RTE_FLOW_ACTION_TYPE_QUEUE:
17900 * Check whether extensive
17901 * metadata feature is engaged.
17903 if (dev_conf->dv_flow_en &&
17904 (dev_conf->dv_xmeta_en !=
17905 MLX5_XMETA_MODE_LEGACY) &&
17906 mlx5_flow_ext_mreg_supported(dev))
17907 return -rte_mtr_error_set(error,
17909 RTE_MTR_ERROR_TYPE_METER_POLICY,
17910 NULL, "Queue action with meta "
17911 "is not supported. Please try use "
17912 "default policy for meter.");
17913 ret = mlx5_flow_validate_action_queue(act,
17914 action_flags[i], dev,
17917 return -rte_mtr_error_set(error,
17919 RTE_MTR_ERROR_TYPE_METER_POLICY,
17920 NULL, flow_err.message ?
17922 "Queue action validate check fail");
17923 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17926 case RTE_FLOW_ACTION_TYPE_RSS:
17927 if (dev_conf->dv_flow_en &&
17928 (dev_conf->dv_xmeta_en !=
17929 MLX5_XMETA_MODE_LEGACY) &&
17930 mlx5_flow_ext_mreg_supported(dev))
17931 return -rte_mtr_error_set(error,
17933 RTE_MTR_ERROR_TYPE_METER_POLICY,
17934 NULL, "RSS action with meta "
17935 "is not supported. Please try use "
17936 "default policy for meter.");
17937 ret = mlx5_validate_action_rss(dev, act,
17940 return -rte_mtr_error_set(error,
17942 RTE_MTR_ERROR_TYPE_METER_POLICY,
17943 NULL, flow_err.message ?
17945 "RSS action validate check fail");
17946 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17948 /* Either G or Y will set the RSS. */
17949 rss_color[i] = act->conf;
17951 case RTE_FLOW_ACTION_TYPE_JUMP:
17952 ret = flow_dv_validate_action_jump(dev,
17953 NULL, act, action_flags[i],
17954 attr, true, &flow_err);
17956 return -rte_mtr_error_set(error,
17958 RTE_MTR_ERROR_TYPE_METER_POLICY,
17959 NULL, flow_err.message ?
17961 "Jump action validate check fail");
17963 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17966 * Only the last meter in the hierarchy will support
17967 * the YELLOW color steering. Then in the meter policy
17968 * actions list, there should be no other meter inside.
17970 case RTE_FLOW_ACTION_TYPE_METER:
17971 if (i != RTE_COLOR_GREEN)
17972 return -rte_mtr_error_set(error,
17974 RTE_MTR_ERROR_TYPE_METER_POLICY,
17976 "Meter hierarchy only supports GREEN color.");
17977 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17978 return -rte_mtr_error_set(error,
17980 RTE_MTR_ERROR_TYPE_METER_POLICY,
17982 "No yellow policy should be provided in meter hierarchy.");
17984 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17994 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17997 return -rte_mtr_error_set(error, ENOTSUP,
17998 RTE_MTR_ERROR_TYPE_METER_POLICY,
18000 "Doesn't support optional action");
18003 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18004 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18005 } else if ((action_flags[i] &
18006 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18007 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18009 * Only support MLX5_XMETA_MODE_LEGACY
18010 * so MARK action is only in ingress domain.
18012 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18014 domain_color[i] = def_domain;
18015 if (action_flags[i] &&
18016 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18018 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18020 if (action_flags[i] &
18021 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18022 domain_color[i] &= hierarchy_domain;
18024 * Non-termination actions only support NIC Tx domain.
18025 * The adjustion should be skipped when there is no
18026 * action or only END is provided. The default domains
18027 * bit-mask is set to find the MIN intersection.
18028 * The action flags checking should also be skipped.
18030 if ((def_green && i == RTE_COLOR_GREEN) ||
18031 (def_yellow && i == RTE_COLOR_YELLOW))
18034 * Validate the drop action mutual exclusion
18035 * with other actions. Drop action is mutually-exclusive
18036 * with any other action, except for Count action.
18038 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18039 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18040 return -rte_mtr_error_set(error, ENOTSUP,
18041 RTE_MTR_ERROR_TYPE_METER_POLICY,
18042 NULL, "Drop action is mutually-exclusive "
18043 "with any other action");
18045 /* Eswitch has few restrictions on using items and actions */
18046 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18047 if (!mlx5_flow_ext_mreg_supported(dev) &&
18048 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18049 return -rte_mtr_error_set(error, ENOTSUP,
18050 RTE_MTR_ERROR_TYPE_METER_POLICY,
18051 NULL, "unsupported action MARK");
18052 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18053 return -rte_mtr_error_set(error, ENOTSUP,
18054 RTE_MTR_ERROR_TYPE_METER_POLICY,
18055 NULL, "unsupported action QUEUE");
18056 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18057 return -rte_mtr_error_set(error, ENOTSUP,
18058 RTE_MTR_ERROR_TYPE_METER_POLICY,
18059 NULL, "unsupported action RSS");
18060 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18061 return -rte_mtr_error_set(error, ENOTSUP,
18062 RTE_MTR_ERROR_TYPE_METER_POLICY,
18063 NULL, "no fate action is found");
18065 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18066 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18067 if ((domain_color[i] &
18068 MLX5_MTR_DOMAIN_EGRESS_BIT))
18070 MLX5_MTR_DOMAIN_EGRESS_BIT;
18072 return -rte_mtr_error_set(error,
18074 RTE_MTR_ERROR_TYPE_METER_POLICY,
18076 "no fate action is found");
18080 /* If both colors have RSS, the attributes should be the same. */
18081 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18082 rss_color[RTE_COLOR_YELLOW]))
18083 return -rte_mtr_error_set(error, EINVAL,
18084 RTE_MTR_ERROR_TYPE_METER_POLICY,
18085 NULL, "policy RSS attr conflict");
18086 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18088 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18089 if (!def_green && !def_yellow &&
18090 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18091 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18092 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18093 return -rte_mtr_error_set(error, EINVAL,
18094 RTE_MTR_ERROR_TYPE_METER_POLICY,
18095 NULL, "policy domains conflict");
18097 * At least one color policy is listed in the actions, the domains
18098 * to be supported should be the intersection.
18100 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18101 domain_color[RTE_COLOR_YELLOW];
18106 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18108 struct mlx5_priv *priv = dev->data->dev_private;
18111 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18112 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18117 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18118 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18122 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18123 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18131 * Discover the number of available flow priorities
18132 * by trying to create a flow with the highest priority value
18133 * for each possible number.
18138 * List of possible number of available priorities.
18139 * @param[in] vprio_n
18140 * Size of @p vprio array.
18142 * On success, number of available flow priorities.
18143 * On failure, a negative errno-style code and rte_errno is set.
18146 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18147 const uint16_t *vprio, int vprio_n)
18149 struct mlx5_priv *priv = dev->data->dev_private;
18150 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18151 struct rte_flow_item_eth eth;
18152 struct rte_flow_item item = {
18153 .type = RTE_FLOW_ITEM_TYPE_ETH,
18157 struct mlx5_flow_dv_matcher matcher = {
18159 .size = sizeof(matcher.mask.buf),
18162 union mlx5_flow_tbl_key tbl_key;
18163 struct mlx5_flow flow;
18165 struct rte_flow_error error;
18167 int i, err, ret = -ENOTSUP;
18170 * Prepare a flow with a catch-all pattern and a drop action.
18171 * Use drop queue, because shared drop action may be unavailable.
18173 action = priv->drop_queue.hrxq->action;
18174 if (action == NULL) {
18175 DRV_LOG(ERR, "Priority discovery requires a drop action");
18176 rte_errno = ENOTSUP;
18179 memset(&flow, 0, sizeof(flow));
18180 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18181 if (flow.handle == NULL) {
18182 DRV_LOG(ERR, "Cannot create flow handle");
18183 rte_errno = ENOMEM;
18186 flow.ingress = true;
18187 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18188 flow.dv.actions[0] = action;
18189 flow.dv.actions_n = 1;
18190 memset(ð, 0, sizeof(eth));
18191 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18192 &item, /* inner */ false, /* group */ 0);
18193 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18194 for (i = 0; i < vprio_n; i++) {
18195 /* Configure the next proposed maximum priority. */
18196 matcher.priority = vprio[i] - 1;
18197 memset(&tbl_key, 0, sizeof(tbl_key));
18198 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18203 /* This action is pure SW and must always succeed. */
18204 DRV_LOG(ERR, "Cannot register matcher");
18208 /* Try to apply the flow to HW. */
18209 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18210 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18211 err = mlx5_flow_os_create_flow
18212 (flow.handle->dvh.matcher->matcher_object,
18213 (void *)&flow.dv.value, flow.dv.actions_n,
18214 flow.dv.actions, &flow.handle->drv_flow);
18216 claim_zero(mlx5_flow_os_destroy_flow
18217 (flow.handle->drv_flow));
18218 flow.handle->drv_flow = NULL;
18220 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18225 mlx5_ipool_free(pool, flow.handle_idx);
18226 /* Set rte_errno if no expected priority value matched. */
18232 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18233 .validate = flow_dv_validate,
18234 .prepare = flow_dv_prepare,
18235 .translate = flow_dv_translate,
18236 .apply = flow_dv_apply,
18237 .remove = flow_dv_remove,
18238 .destroy = flow_dv_destroy,
18239 .query = flow_dv_query,
18240 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18241 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18242 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18243 .create_meter = flow_dv_mtr_alloc,
18244 .free_meter = flow_dv_aso_mtr_release_to_pool,
18245 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18246 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18247 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18248 .create_policy_rules = flow_dv_create_policy_rules,
18249 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18250 .create_def_policy = flow_dv_create_def_policy,
18251 .destroy_def_policy = flow_dv_destroy_def_policy,
18252 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18253 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18254 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18255 .counter_alloc = flow_dv_counter_allocate,
18256 .counter_free = flow_dv_counter_free,
18257 .counter_query = flow_dv_counter_query,
18258 .get_aged_flows = flow_dv_get_aged_flows,
18259 .action_validate = flow_dv_action_validate,
18260 .action_create = flow_dv_action_create,
18261 .action_destroy = flow_dv_action_destroy,
18262 .action_update = flow_dv_action_update,
18263 .action_query = flow_dv_action_query,
18264 .sync_domain = flow_dv_sync_domain,
18265 .discover_priorities = flow_dv_discover_priorities,
18266 .item_create = flow_dv_item_create,
18267 .item_release = flow_dv_item_release,
18270 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */