drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 /**
  88  * Initialize flow attributes structure according to flow items' types.
  89  *
  90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  91  * mode. For tunnel mode, the items to be modified are the outermost ones.
  92  *
  93  * @param[in] item
  94  *   Pointer to item specification.
  95  * @param[out] attr
  96  *   Pointer to flow attributes structure.
  97  * @param[in] dev_flow
  98  *   Pointer to the sub flow.
  99  * @param[in] tunnel_decap
 100  *   Whether action is after tunnel decapsulation.
 101  */
 102 static void
 103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 105 {
 106         uint64_t layers = dev_flow->handle->layers;
 107
 108         /*
 109          * If layers is already initialized, it means this dev_flow is the
 110          * suffix flow, the layers flags is set by the prefix flow. Need to
 111          * use the layer flags from prefix flow as the suffix flow may not
 112          * have the user defined items as the flow is split.
 113          */
 114         if (layers) {
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 116                         attr->ipv4 = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 118                         attr->ipv6 = 1;
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 120                         attr->tcp = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 122                         attr->udp = 1;
 123                 attr->valid = 1;
 124                 return;
 125         }
 126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 127                 uint8_t next_protocol = 0xff;
 128                 switch (item->type) {
 129                 case RTE_FLOW_ITEM_TYPE_GRE:
 130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 134                 case RTE_FLOW_ITEM_TYPE_MPLS:
 135                         if (tunnel_decap)
 136                                 attr->attr = 0;
 137                         break;
 138                 case RTE_FLOW_ITEM_TYPE_IPV4:
 139                         if (!attr->ipv6)
 140                                 attr->ipv4 = 1;
 141                         if (item->mask != NULL &&
 142                             ((const struct rte_flow_item_ipv4 *)
 143                             item->mask)->hdr.next_proto_id)
 144                                 next_protocol =
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->spec))->hdr.next_proto_id &
 147                                     ((const struct rte_flow_item_ipv4 *)
 148                                       (item->mask))->hdr.next_proto_id;
 149                         if ((next_protocol == IPPROTO_IPIP ||
 150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 151                                 attr->attr = 0;
 152                         break;
 153                 case RTE_FLOW_ITEM_TYPE_IPV6:
 154                         if (!attr->ipv4)
 155                                 attr->ipv6 = 1;
 156                         if (item->mask != NULL &&
 157                             ((const struct rte_flow_item_ipv6 *)
 158                             item->mask)->hdr.proto)
 159                                 next_protocol =
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->spec))->hdr.proto &
 162                                     ((const struct rte_flow_item_ipv6 *)
 163                                       (item->mask))->hdr.proto;
 164                         if ((next_protocol == IPPROTO_IPIP ||
 165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 166                                 attr->attr = 0;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_UDP:
 169                         if (!attr->tcp)
 170                                 attr->udp = 1;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_TCP:
 173                         if (!attr->udp)
 174                                 attr->tcp = 1;
 175                         break;
 176                 default:
 177                         break;
 178                 }
 179         }
 180         attr->valid = 1;
 181 }
 182
 183 /**
 184  * Convert rte_mtr_color to mlx5 color.
 185  *
 186  * @param[in] rcol
 187  *   rte_mtr_color.
 188  *
 189  * @return
 190  *   mlx5 color.
 191  */
 192 static int
 193 rte_col_2_mlx5_col(enum rte_color rcol)
 194 {
 195         switch (rcol) {
 196         case RTE_COLOR_GREEN:
 197                 return MLX5_FLOW_COLOR_GREEN;
 198         case RTE_COLOR_YELLOW:
 199                 return MLX5_FLOW_COLOR_YELLOW;
 200         case RTE_COLOR_RED:
 201                 return MLX5_FLOW_COLOR_RED;
 202         default:
 203                 break;
 204         }
 205         return MLX5_FLOW_COLOR_UNDEFINED;
 206 }
 207
 208 struct field_modify_info {
 209         uint32_t size; /* Size of field in protocol header, in bytes. */
 210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 211         enum mlx5_modification_field id;
 212 };
 213
 214 struct field_modify_info modify_eth[] = {
 215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_vlan_out_first_vid[] = {
 223         /* Size in bits !!! */
 224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv4[] = {
 229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 231         {4, 12, MLX5_MODI_OUT_SIPV4},
 232         {4, 16, MLX5_MODI_OUT_DIPV4},
 233         {0, 0, 0},
 234 };
 235
 236 struct field_modify_info modify_ipv6[] = {
 237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_udp[] = {
 251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 253         {0, 0, 0},
 254 };
 255
 256 struct field_modify_info modify_tcp[] = {
 257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 261         {0, 0, 0},
 262 };
 263
 264 static void
 265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 266                           uint8_t next_protocol, uint64_t *item_flags,
 267                           int *tunnel)
 268 {
 269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 271         if (next_protocol == IPPROTO_IPIP) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 273                 *tunnel = 1;
 274         }
 275         if (next_protocol == IPPROTO_IPV6) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 277                 *tunnel = 1;
 278         }
 279 }
 280
 281 /* Update VLAN's VID/PCP based on input rte_flow_action.
 282  *
 283  * @param[in] action
 284  *   Pointer to struct rte_flow_action.
 285  * @param[out] vlan
 286  *   Pointer to struct rte_vlan_hdr.
 287  */
 288 static void
 289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 290                          struct rte_vlan_hdr *vlan)
 291 {
 292         uint16_t vlan_tci;
 293         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 294                 vlan_tci =
 295                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 296                                                action->conf)->vlan_pcp;
 297                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 298                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 299                 vlan->vlan_tci |= vlan_tci;
 300         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 301                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 302                 vlan->vlan_tci |= rte_be_to_cpu_16
 303                     (((const struct rte_flow_action_of_set_vlan_vid *)
 304                                              action->conf)->vlan_vid);
 305         }
 306 }
 307
 308 /**
 309  * Fetch 1, 2, 3 or 4 byte field from the byte array
 310  * and return as unsigned integer in host-endian format.
 311  *
 312  * @param[in] data
 313  *   Pointer to data array.
 314  * @param[in] size
 315  *   Size of field to extract.
 316  *
 317  * @return
 318  *   converted field in host endian format.
 319  */
 320 static inline uint32_t
 321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 322 {
 323         uint32_t ret;
 324
 325         switch (size) {
 326         case 1:
 327                 ret = *data;
 328                 break;
 329         case 2:
 330                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 331                 break;
 332         case 3:
 333                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 334                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 335                 break;
 336         case 4:
 337                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 338                 break;
 339         default:
 340                 MLX5_ASSERT(false);
 341                 ret = 0;
 342                 break;
 343         }
 344         return ret;
 345 }
 346
 347 /**
 348  * Convert modify-header action to DV specification.
 349  *
 350  * Data length of each action is determined by provided field description
 351  * and the item mask. Data bit offset and width of each action is determined
 352  * by provided item mask.
 353  *
 354  * @param[in] item
 355  *   Pointer to item specification.
 356  * @param[in] field
 357  *   Pointer to field modification information.
 358  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 359  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 360  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 361  * @param[in] dcopy
 362  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 363  *   Negative offset value sets the same offset as source offset.
 364  *   size field is ignored, value is taken from source field.
 365  * @param[in,out] resource
 366  *   Pointer to the modify-header resource.
 367  * @param[in] type
 368  *   Type of modification.
 369  * @param[out] error
 370  *   Pointer to the error structure.
 371  *
 372  * @return
 373  *   0 on success, a negative errno value otherwise and rte_errno is set.
 374  */
 375 static int
 376 flow_dv_convert_modify_action(struct rte_flow_item *item,
 377                               struct field_modify_info *field,
 378                               struct field_modify_info *dcopy,
 379                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 380                               uint32_t type, struct rte_flow_error *error)
 381 {
 382         uint32_t i = resource->actions_num;
 383         struct mlx5_modification_cmd *actions = resource->actions;
 384
 385         /*
 386          * The item and mask are provided in big-endian format.
 387          * The fields should be presented as in big-endian format either.
 388          * Mask must be always present, it defines the actual field width.
 389          */
 390         MLX5_ASSERT(item->mask);
 391         MLX5_ASSERT(field->size);
 392         do {
 393                 unsigned int size_b;
 394                 unsigned int off_b;
 395                 uint32_t mask;
 396                 uint32_t data;
 397
 398                 if (i >= MLX5_MAX_MODIFY_NUM)
 399                         return rte_flow_error_set(error, EINVAL,
 400                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 401                                  "too many items to modify");
 402                 /* Fetch variable byte size mask from the array. */
 403                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 404                                            field->offset, field->size);
 405                 if (!mask) {
 406                         ++field;
 407                         continue;
 408                 }
 409                 /* Deduce actual data width in bits from mask value. */
 410                 off_b = rte_bsf32(mask);
 411                 size_b = sizeof(uint32_t) * CHAR_BIT -
 412                          off_b - __builtin_clz(mask);
 413                 MLX5_ASSERT(size_b);
 414                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 415                 actions[i] = (struct mlx5_modification_cmd) {
 416                         .action_type = type,
 417                         .field = field->id,
 418                         .offset = off_b,
 419                         .length = size_b,
 420                 };
 421                 /* Convert entire record to expected big-endian format. */
 422                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 423                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 424                         MLX5_ASSERT(dcopy);
 425                         actions[i].dst_field = dcopy->id;
 426                         actions[i].dst_offset =
 427                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 428                         /* Convert entire record to big-endian format. */
 429                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 430                 } else {
 431                         MLX5_ASSERT(item->spec);
 432                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 433                                                    field->offset, field->size);
 434                         /* Shift out the trailing masked bits from data. */
 435                         data = (data & mask) >> off_b;
 436                         actions[i].data1 = rte_cpu_to_be_32(data);
 437                 }
 438                 ++i;
 439                 ++field;
 440         } while (field->size);
 441         if (resource->actions_num == i)
 442                 return rte_flow_error_set(error, EINVAL,
 443                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 444                                           "invalid modification flow item");
 445         resource->actions_num = i;
 446         return 0;
 447 }
 448
 449 /**
 450  * Convert modify-header set IPv4 address action to DV specification.
 451  *
 452  * @param[in,out] resource
 453  *   Pointer to the modify-header resource.
 454  * @param[in] action
 455  *   Pointer to action specification.
 456  * @param[out] error
 457  *   Pointer to the error structure.
 458  *
 459  * @return
 460  *   0 on success, a negative errno value otherwise and rte_errno is set.
 461  */
 462 static int
 463 flow_dv_convert_action_modify_ipv4
 464                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 465                          const struct rte_flow_action *action,
 466                          struct rte_flow_error *error)
 467 {
 468         const struct rte_flow_action_set_ipv4 *conf =
 469                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 470         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 471         struct rte_flow_item_ipv4 ipv4;
 472         struct rte_flow_item_ipv4 ipv4_mask;
 473
 474         memset(&ipv4, 0, sizeof(ipv4));
 475         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 476         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 477                 ipv4.hdr.src_addr = conf->ipv4_addr;
 478                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 479         } else {
 480                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 481                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 482         }
 483         item.spec = &ipv4;
 484         item.mask = &ipv4_mask;
 485         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 486                                              MLX5_MODIFICATION_TYPE_SET, error);
 487 }
 488
 489 /**
 490  * Convert modify-header set IPv6 address action to DV specification.
 491  *
 492  * @param[in,out] resource
 493  *   Pointer to the modify-header resource.
 494  * @param[in] action
 495  *   Pointer to action specification.
 496  * @param[out] error
 497  *   Pointer to the error structure.
 498  *
 499  * @return
 500  *   0 on success, a negative errno value otherwise and rte_errno is set.
 501  */
 502 static int
 503 flow_dv_convert_action_modify_ipv6
 504                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 505                          const struct rte_flow_action *action,
 506                          struct rte_flow_error *error)
 507 {
 508         const struct rte_flow_action_set_ipv6 *conf =
 509                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 510         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 511         struct rte_flow_item_ipv6 ipv6;
 512         struct rte_flow_item_ipv6 ipv6_mask;
 513
 514         memset(&ipv6, 0, sizeof(ipv6));
 515         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 516         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 517                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 518                        sizeof(ipv6.hdr.src_addr));
 519                 memcpy(&ipv6_mask.hdr.src_addr,
 520                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 521                        sizeof(ipv6.hdr.src_addr));
 522         } else {
 523                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.dst_addr));
 525                 memcpy(&ipv6_mask.hdr.dst_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 527                        sizeof(ipv6.hdr.dst_addr));
 528         }
 529         item.spec = &ipv6;
 530         item.mask = &ipv6_mask;
 531         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 532                                              MLX5_MODIFICATION_TYPE_SET, error);
 533 }
 534
 535 /**
 536  * Convert modify-header set MAC address action to DV specification.
 537  *
 538  * @param[in,out] resource
 539  *   Pointer to the modify-header resource.
 540  * @param[in] action
 541  *   Pointer to action specification.
 542  * @param[out] error
 543  *   Pointer to the error structure.
 544  *
 545  * @return
 546  *   0 on success, a negative errno value otherwise and rte_errno is set.
 547  */
 548 static int
 549 flow_dv_convert_action_modify_mac
 550                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 551                          const struct rte_flow_action *action,
 552                          struct rte_flow_error *error)
 553 {
 554         const struct rte_flow_action_set_mac *conf =
 555                 (const struct rte_flow_action_set_mac *)(action->conf);
 556         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 557         struct rte_flow_item_eth eth;
 558         struct rte_flow_item_eth eth_mask;
 559
 560         memset(&eth, 0, sizeof(eth));
 561         memset(&eth_mask, 0, sizeof(eth_mask));
 562         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 563                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 564                        sizeof(eth.src.addr_bytes));
 565                 memcpy(&eth_mask.src.addr_bytes,
 566                        &rte_flow_item_eth_mask.src.addr_bytes,
 567                        sizeof(eth_mask.src.addr_bytes));
 568         } else {
 569                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.dst.addr_bytes));
 571                 memcpy(&eth_mask.dst.addr_bytes,
 572                        &rte_flow_item_eth_mask.dst.addr_bytes,
 573                        sizeof(eth_mask.dst.addr_bytes));
 574         }
 575         item.spec = &eth;
 576         item.mask = &eth_mask;
 577         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 578                                              MLX5_MODIFICATION_TYPE_SET, error);
 579 }
 580
 581 /**
 582  * Convert modify-header set VLAN VID action to DV specification.
 583  *
 584  * @param[in,out] resource
 585  *   Pointer to the modify-header resource.
 586  * @param[in] action
 587  *   Pointer to action specification.
 588  * @param[out] error
 589  *   Pointer to the error structure.
 590  *
 591  * @return
 592  *   0 on success, a negative errno value otherwise and rte_errno is set.
 593  */
 594 static int
 595 flow_dv_convert_action_modify_vlan_vid
 596                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 597                          const struct rte_flow_action *action,
 598                          struct rte_flow_error *error)
 599 {
 600         const struct rte_flow_action_of_set_vlan_vid *conf =
 601                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 602         int i = resource->actions_num;
 603         struct mlx5_modification_cmd *actions = resource->actions;
 604         struct field_modify_info *field = modify_vlan_out_first_vid;
 605
 606         if (i >= MLX5_MAX_MODIFY_NUM)
 607                 return rte_flow_error_set(error, EINVAL,
 608                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 609                          "too many items to modify");
 610         actions[i] = (struct mlx5_modification_cmd) {
 611                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 612                 .field = field->id,
 613                 .length = field->size,
 614                 .offset = field->offset,
 615         };
 616         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 617         actions[i].data1 = conf->vlan_vid;
 618         actions[i].data1 = actions[i].data1 << 16;
 619         resource->actions_num = ++i;
 620         return 0;
 621 }
 622
 623 /**
 624  * Convert modify-header set TP action to DV specification.
 625  *
 626  * @param[in,out] resource
 627  *   Pointer to the modify-header resource.
 628  * @param[in] action
 629  *   Pointer to action specification.
 630  * @param[in] items
 631  *   Pointer to rte_flow_item objects list.
 632  * @param[in] attr
 633  *   Pointer to flow attributes structure.
 634  * @param[in] dev_flow
 635  *   Pointer to the sub flow.
 636  * @param[in] tunnel_decap
 637  *   Whether action is after tunnel decapsulation.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_tp
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 650                          bool tunnel_decap, struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_tp *conf =
 653                 (const struct rte_flow_action_set_tp *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_udp udp;
 656         struct rte_flow_item_udp udp_mask;
 657         struct rte_flow_item_tcp tcp;
 658         struct rte_flow_item_tcp tcp_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 663         if (attr->udp) {
 664                 memset(&udp, 0, sizeof(udp));
 665                 memset(&udp_mask, 0, sizeof(udp_mask));
 666                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 667                         udp.hdr.src_port = conf->port;
 668                         udp_mask.hdr.src_port =
 669                                         rte_flow_item_udp_mask.hdr.src_port;
 670                 } else {
 671                         udp.hdr.dst_port = conf->port;
 672                         udp_mask.hdr.dst_port =
 673                                         rte_flow_item_udp_mask.hdr.dst_port;
 674                 }
 675                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 676                 item.spec = &udp;
 677                 item.mask = &udp_mask;
 678                 field = modify_udp;
 679         } else {
 680                 MLX5_ASSERT(attr->tcp);
 681                 memset(&tcp, 0, sizeof(tcp));
 682                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 683                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 684                         tcp.hdr.src_port = conf->port;
 685                         tcp_mask.hdr.src_port =
 686                                         rte_flow_item_tcp_mask.hdr.src_port;
 687                 } else {
 688                         tcp.hdr.dst_port = conf->port;
 689                         tcp_mask.hdr.dst_port =
 690                                         rte_flow_item_tcp_mask.hdr.dst_port;
 691                 }
 692                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 693                 item.spec = &tcp;
 694                 item.mask = &tcp_mask;
 695                 field = modify_tcp;
 696         }
 697         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 698                                              MLX5_MODIFICATION_TYPE_SET, error);
 699 }
 700
 701 /**
 702  * Convert modify-header set TTL action to DV specification.
 703  *
 704  * @param[in,out] resource
 705  *   Pointer to the modify-header resource.
 706  * @param[in] action
 707  *   Pointer to action specification.
 708  * @param[in] items
 709  *   Pointer to rte_flow_item objects list.
 710  * @param[in] attr
 711  *   Pointer to flow attributes structure.
 712  * @param[in] dev_flow
 713  *   Pointer to the sub flow.
 714  * @param[in] tunnel_decap
 715  *   Whether action is after tunnel decapsulation.
 716  * @param[out] error
 717  *   Pointer to the error structure.
 718  *
 719  * @return
 720  *   0 on success, a negative errno value otherwise and rte_errno is set.
 721  */
 722 static int
 723 flow_dv_convert_action_modify_ttl
 724                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 725                          const struct rte_flow_action *action,
 726                          const struct rte_flow_item *items,
 727                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 728                          bool tunnel_decap, struct rte_flow_error *error)
 729 {
 730         const struct rte_flow_action_set_ttl *conf =
 731                 (const struct rte_flow_action_set_ttl *)(action->conf);
 732         struct rte_flow_item item;
 733         struct rte_flow_item_ipv4 ipv4;
 734         struct rte_flow_item_ipv4 ipv4_mask;
 735         struct rte_flow_item_ipv6 ipv6;
 736         struct rte_flow_item_ipv6 ipv6_mask;
 737         struct field_modify_info *field;
 738
 739         if (!attr->valid)
 740                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 741         if (attr->ipv4) {
 742                 memset(&ipv4, 0, sizeof(ipv4));
 743                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 744                 ipv4.hdr.time_to_live = conf->ttl_value;
 745                 ipv4_mask.hdr.time_to_live = 0xFF;
 746                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 747                 item.spec = &ipv4;
 748                 item.mask = &ipv4_mask;
 749                 field = modify_ipv4;
 750         } else {
 751                 MLX5_ASSERT(attr->ipv6);
 752                 memset(&ipv6, 0, sizeof(ipv6));
 753                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 754                 ipv6.hdr.hop_limits = conf->ttl_value;
 755                 ipv6_mask.hdr.hop_limits = 0xFF;
 756                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 757                 item.spec = &ipv6;
 758                 item.mask = &ipv6_mask;
 759                 field = modify_ipv6;
 760         }
 761         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 762                                              MLX5_MODIFICATION_TYPE_SET, error);
 763 }
 764
 765 /**
 766  * Convert modify-header decrement TTL action to DV specification.
 767  *
 768  * @param[in,out] resource
 769  *   Pointer to the modify-header resource.
 770  * @param[in] action
 771  *   Pointer to action specification.
 772  * @param[in] items
 773  *   Pointer to rte_flow_item objects list.
 774  * @param[in] attr
 775  *   Pointer to flow attributes structure.
 776  * @param[in] dev_flow
 777  *   Pointer to the sub flow.
 778  * @param[in] tunnel_decap
 779  *   Whether action is after tunnel decapsulation.
 780  * @param[out] error
 781  *   Pointer to the error structure.
 782  *
 783  * @return
 784  *   0 on success, a negative errno value otherwise and rte_errno is set.
 785  */
 786 static int
 787 flow_dv_convert_action_modify_dec_ttl
 788                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 789                          const struct rte_flow_item *items,
 790                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 791                          bool tunnel_decap, struct rte_flow_error *error)
 792 {
 793         struct rte_flow_item item;
 794         struct rte_flow_item_ipv4 ipv4;
 795         struct rte_flow_item_ipv4 ipv4_mask;
 796         struct rte_flow_item_ipv6 ipv6;
 797         struct rte_flow_item_ipv6 ipv6_mask;
 798         struct field_modify_info *field;
 799
 800         if (!attr->valid)
 801                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 802         if (attr->ipv4) {
 803                 memset(&ipv4, 0, sizeof(ipv4));
 804                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 805                 ipv4.hdr.time_to_live = 0xFF;
 806                 ipv4_mask.hdr.time_to_live = 0xFF;
 807                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 808                 item.spec = &ipv4;
 809                 item.mask = &ipv4_mask;
 810                 field = modify_ipv4;
 811         } else {
 812                 MLX5_ASSERT(attr->ipv6);
 813                 memset(&ipv6, 0, sizeof(ipv6));
 814                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 815                 ipv6.hdr.hop_limits = 0xFF;
 816                 ipv6_mask.hdr.hop_limits = 0xFF;
 817                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 818                 item.spec = &ipv6;
 819                 item.mask = &ipv6_mask;
 820                 field = modify_ipv6;
 821         }
 822         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 823                                              MLX5_MODIFICATION_TYPE_ADD, error);
 824 }
 825
 826 /**
 827  * Convert modify-header increment/decrement TCP Sequence number
 828  * to DV specification.
 829  *
 830  * @param[in,out] resource
 831  *   Pointer to the modify-header resource.
 832  * @param[in] action
 833  *   Pointer to action specification.
 834  * @param[out] error
 835  *   Pointer to the error structure.
 836  *
 837  * @return
 838  *   0 on success, a negative errno value otherwise and rte_errno is set.
 839  */
 840 static int
 841 flow_dv_convert_action_modify_tcp_seq
 842                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 843                          const struct rte_flow_action *action,
 844                          struct rte_flow_error *error)
 845 {
 846         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 847         uint64_t value = rte_be_to_cpu_32(*conf);
 848         struct rte_flow_item item;
 849         struct rte_flow_item_tcp tcp;
 850         struct rte_flow_item_tcp tcp_mask;
 851
 852         memset(&tcp, 0, sizeof(tcp));
 853         memset(&tcp_mask, 0, sizeof(tcp_mask));
 854         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 855                 /*
 856                  * The HW has no decrement operation, only increment operation.
 857                  * To simulate decrement X from Y using increment operation
 858                  * we need to add UINT32_MAX X times to Y.
 859                  * Each adding of UINT32_MAX decrements Y by 1.
 860                  */
 861                 value *= UINT32_MAX;
 862         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 863         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 864         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 865         item.spec = &tcp;
 866         item.mask = &tcp_mask;
 867         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 868                                              MLX5_MODIFICATION_TYPE_ADD, error);
 869 }
 870
 871 /**
 872  * Convert modify-header increment/decrement TCP Acknowledgment number
 873  * to DV specification.
 874  *
 875  * @param[in,out] resource
 876  *   Pointer to the modify-header resource.
 877  * @param[in] action
 878  *   Pointer to action specification.
 879  * @param[out] error
 880  *   Pointer to the error structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 static int
 886 flow_dv_convert_action_modify_tcp_ack
 887                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 888                          const struct rte_flow_action *action,
 889                          struct rte_flow_error *error)
 890 {
 891         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 892         uint64_t value = rte_be_to_cpu_32(*conf);
 893         struct rte_flow_item item;
 894         struct rte_flow_item_tcp tcp;
 895         struct rte_flow_item_tcp tcp_mask;
 896
 897         memset(&tcp, 0, sizeof(tcp));
 898         memset(&tcp_mask, 0, sizeof(tcp_mask));
 899         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 900                 /*
 901                  * The HW has no decrement operation, only increment operation.
 902                  * To simulate decrement X from Y using increment operation
 903                  * we need to add UINT32_MAX X times to Y.
 904                  * Each adding of UINT32_MAX decrements Y by 1.
 905                  */
 906                 value *= UINT32_MAX;
 907         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 908         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 909         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 910         item.spec = &tcp;
 911         item.mask = &tcp_mask;
 912         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 913                                              MLX5_MODIFICATION_TYPE_ADD, error);
 914 }
 915
 916 static enum mlx5_modification_field reg_to_field[] = {
 917         [REG_NON] = MLX5_MODI_OUT_NONE,
 918         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 919         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 920         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 921         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 922         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 923         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 924         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 925         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 926         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 927         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 928 };
 929
 930 /**
 931  * Convert register set to DV specification.
 932  *
 933  * @param[in,out] resource
 934  *   Pointer to the modify-header resource.
 935  * @param[in] action
 936  *   Pointer to action specification.
 937  * @param[out] error
 938  *   Pointer to the error structure.
 939  *
 940  * @return
 941  *   0 on success, a negative errno value otherwise and rte_errno is set.
 942  */
 943 static int
 944 flow_dv_convert_action_set_reg
 945                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 946                          const struct rte_flow_action *action,
 947                          struct rte_flow_error *error)
 948 {
 949         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 950         struct mlx5_modification_cmd *actions = resource->actions;
 951         uint32_t i = resource->actions_num;
 952
 953         if (i >= MLX5_MAX_MODIFY_NUM)
 954                 return rte_flow_error_set(error, EINVAL,
 955                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 956                                           "too many items to modify");
 957         MLX5_ASSERT(conf->id != REG_NON);
 958         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 959         actions[i] = (struct mlx5_modification_cmd) {
 960                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 961                 .field = reg_to_field[conf->id],
 962         };
 963         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 964         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 965         ++i;
 966         resource->actions_num = i;
 967         return 0;
 968 }
 969
 970 /**
 971  * Convert SET_TAG action to DV specification.
 972  *
 973  * @param[in] dev
 974  *   Pointer to the rte_eth_dev structure.
 975  * @param[in,out] resource
 976  *   Pointer to the modify-header resource.
 977  * @param[in] conf
 978  *   Pointer to action specification.
 979  * @param[out] error
 980  *   Pointer to the error structure.
 981  *
 982  * @return
 983  *   0 on success, a negative errno value otherwise and rte_errno is set.
 984  */
 985 static int
 986 flow_dv_convert_action_set_tag
 987                         (struct rte_eth_dev *dev,
 988                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 989                          const struct rte_flow_action_set_tag *conf,
 990                          struct rte_flow_error *error)
 991 {
 992         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 993         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 994         struct rte_flow_item item = {
 995                 .spec = &data,
 996                 .mask = &mask,
 997         };
 998         struct field_modify_info reg_c_x[] = {
 999                 [1] = {0, 0, 0},
1000         };
1001         enum mlx5_modification_field reg_type;
1002         int ret;
1003
1004         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1005         if (ret < 0)
1006                 return ret;
1007         MLX5_ASSERT(ret != REG_NON);
1008         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009         reg_type = reg_to_field[ret];
1010         MLX5_ASSERT(reg_type > 0);
1011         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013                                              MLX5_MODIFICATION_TYPE_SET, error);
1014 }
1015
1016 /**
1017  * Convert internal COPY_REG action to DV specification.
1018  *
1019  * @param[in] dev
1020  *   Pointer to the rte_eth_dev structure.
1021  * @param[in,out] res
1022  *   Pointer to the modify-header resource.
1023  * @param[in] action
1024  *   Pointer to action specification.
1025  * @param[out] error
1026  *   Pointer to the error structure.
1027  *
1028  * @return
1029  *   0 on success, a negative errno value otherwise and rte_errno is set.
1030  */
1031 static int
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1034                                  const struct rte_flow_action *action,
1035                                  struct rte_flow_error *error)
1036 {
1037         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039         struct rte_flow_item item = {
1040                 .spec = NULL,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_src[] = {
1044                 {4, 0, reg_to_field[conf->src]},
1045                 {0, 0, 0},
1046         };
1047         struct field_modify_info reg_dst = {
1048                 .offset = 0,
1049                 .id = reg_to_field[conf->dst],
1050         };
1051         /* Adjust reg_c[0] usage according to reported mask. */
1052         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053                 struct mlx5_priv *priv = dev->data->dev_private;
1054                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1055
1056                 MLX5_ASSERT(reg_c0);
1057                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058                 if (conf->dst == REG_C_0) {
1059                         /* Copy to reg_c[0], within mask only. */
1060                         reg_dst.offset = rte_bsf32(reg_c0);
1061                         /*
1062                          * Mask is ignoring the enianness, because
1063                          * there is no conversion in datapath.
1064                          */
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066                         /* Copy from destination lower bits to reg_c[0]. */
1067                         mask = reg_c0 >> reg_dst.offset;
1068 #else
1069                         /* Copy from destination upper bits to reg_c[0]. */
1070                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071                                           rte_fls_u32(reg_c0));
1072 #endif
1073                 } else {
1074                         mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076                         /* Copy from reg_c[0] to destination lower bits. */
1077                         reg_dst.offset = 0;
1078 #else
1079                         /* Copy from reg_c[0] to destination upper bits. */
1080                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081                                          (rte_fls_u32(reg_c0) -
1082                                           rte_bsf32(reg_c0));
1083 #endif
1084                 }
1085         }
1086         return flow_dv_convert_modify_action(&item,
1087                                              reg_src, &reg_dst, res,
1088                                              MLX5_MODIFICATION_TYPE_COPY,
1089                                              error);
1090 }
1091
1092 /**
1093  * Convert MARK action to DV specification. This routine is used
1094  * in extensive metadata only and requires metadata register to be
1095  * handled. In legacy mode hardware tag resource is engaged.
1096  *
1097  * @param[in] dev
1098  *   Pointer to the rte_eth_dev structure.
1099  * @param[in] conf
1100  *   Pointer to MARK action specification.
1101  * @param[in,out] resource
1102  *   Pointer to the modify-header resource.
1103  * @param[out] error
1104  *   Pointer to the error structure.
1105  *
1106  * @return
1107  *   0 on success, a negative errno value otherwise and rte_errno is set.
1108  */
1109 static int
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111                             const struct rte_flow_action_mark *conf,
1112                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1113                             struct rte_flow_error *error)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117                                            priv->sh->dv_mark_mask);
1118         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119         struct rte_flow_item item = {
1120                 .spec = &data,
1121                 .mask = &mask,
1122         };
1123         struct field_modify_info reg_c_x[] = {
1124                 [1] = {0, 0, 0},
1125         };
1126         int reg;
1127
1128         if (!mask)
1129                 return rte_flow_error_set(error, EINVAL,
1130                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131                                           NULL, "zero mark action mask");
1132         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1133         if (reg < 0)
1134                 return reg;
1135         MLX5_ASSERT(reg > 0);
1136         if (reg == REG_C_0) {
1137                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1139
1140                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142                 mask = rte_cpu_to_be_32(mask << shl_c0);
1143         }
1144         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146                                              MLX5_MODIFICATION_TYPE_SET, error);
1147 }
1148
1149 /**
1150  * Get metadata register index for specified steering domain.
1151  *
1152  * @param[in] dev
1153  *   Pointer to the rte_eth_dev structure.
1154  * @param[in] attr
1155  *   Attributes of flow to determine steering domain.
1156  * @param[out] error
1157  *   Pointer to the error structure.
1158  *
1159  * @return
1160  *   positive index on success, a negative errno value otherwise
1161  *   and rte_errno is set.
1162  */
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165                          const struct rte_flow_attr *attr,
1166                          struct rte_flow_error *error)
1167 {
1168         int reg =
1169                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1170                                           MLX5_METADATA_FDB :
1171                                             attr->egress ?
1172                                             MLX5_METADATA_TX :
1173                                             MLX5_METADATA_RX, 0, error);
1174         if (reg < 0)
1175                 return rte_flow_error_set(error,
1176                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177                                           NULL, "unavailable "
1178                                           "metadata register");
1179         return reg;
1180 }
1181
1182 /**
1183  * Convert SET_META action to DV specification.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in,out] resource
1188  *   Pointer to the modify-header resource.
1189  * @param[in] attr
1190  *   Attributes of flow that includes this item.
1191  * @param[in] conf
1192  *   Pointer to action specification.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   0 on success, a negative errno value otherwise and rte_errno is set.
1198  */
1199 static int
1200 flow_dv_convert_action_set_meta
1201                         (struct rte_eth_dev *dev,
1202                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1203                          const struct rte_flow_attr *attr,
1204                          const struct rte_flow_action_set_meta *conf,
1205                          struct rte_flow_error *error)
1206 {
1207         uint32_t data = conf->data;
1208         uint32_t mask = conf->mask;
1209         struct rte_flow_item item = {
1210                 .spec = &data,
1211                 .mask = &mask,
1212         };
1213         struct field_modify_info reg_c_x[] = {
1214                 [1] = {0, 0, 0},
1215         };
1216         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1217
1218         if (reg < 0)
1219                 return reg;
1220         MLX5_ASSERT(reg != REG_NON);
1221         /*
1222          * In datapath code there is no endianness
1223          * coversions for perfromance reasons, all
1224          * pattern conversions are done in rte_flow.
1225          */
1226         if (reg == REG_C_0) {
1227                 struct mlx5_priv *priv = dev->data->dev_private;
1228                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1229                 uint32_t shl_c0;
1230
1231                 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233                 shl_c0 = rte_bsf32(msk_c0);
1234 #else
1235                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1236 #endif
1237                 mask <<= shl_c0;
1238                 data <<= shl_c0;
1239                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1240         }
1241         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242         /* The routine expects parameters in memory as big-endian ones. */
1243         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244                                              MLX5_MODIFICATION_TYPE_SET, error);
1245 }
1246
1247 /**
1248  * Convert modify-header set IPv4 DSCP action to DV specification.
1249  *
1250  * @param[in,out] resource
1251  *   Pointer to the modify-header resource.
1252  * @param[in] action
1253  *   Pointer to action specification.
1254  * @param[out] error
1255  *   Pointer to the error structure.
1256  *
1257  * @return
1258  *   0 on success, a negative errno value otherwise and rte_errno is set.
1259  */
1260 static int
1261 flow_dv_convert_action_modify_ipv4_dscp
1262                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263                          const struct rte_flow_action *action,
1264                          struct rte_flow_error *error)
1265 {
1266         const struct rte_flow_action_set_dscp *conf =
1267                 (const struct rte_flow_action_set_dscp *)(action->conf);
1268         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269         struct rte_flow_item_ipv4 ipv4;
1270         struct rte_flow_item_ipv4 ipv4_mask;
1271
1272         memset(&ipv4, 0, sizeof(ipv4));
1273         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274         ipv4.hdr.type_of_service = conf->dscp;
1275         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1276         item.spec = &ipv4;
1277         item.mask = &ipv4_mask;
1278         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv6 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv6_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304         struct rte_flow_item_ipv6 ipv6;
1305         struct rte_flow_item_ipv6 ipv6_mask;
1306
1307         memset(&ipv6, 0, sizeof(ipv6));
1308         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1309         /*
1310          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311          * rdma-core only accept the DSCP bits byte aligned start from
1312          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313          * bits in IPv6 case as rdma-core requires byte aligned value.
1314          */
1315         ipv6.hdr.vtc_flow = conf->dscp;
1316         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1317         item.spec = &ipv6;
1318         item.mask = &ipv6_mask;
1319         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320                                              MLX5_MODIFICATION_TYPE_SET, error);
1321 }
1322
1323 /**
1324  * Validate MARK item.
1325  *
1326  * @param[in] dev
1327  *   Pointer to the rte_eth_dev structure.
1328  * @param[in] item
1329  *   Item specification.
1330  * @param[in] attr
1331  *   Attributes of flow that includes this item.
1332  * @param[out] error
1333  *   Pointer to error structure.
1334  *
1335  * @return
1336  *   0 on success, a negative errno value otherwise and rte_errno is set.
1337  */
1338 static int
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340                            const struct rte_flow_item *item,
1341                            const struct rte_flow_attr *attr __rte_unused,
1342                            struct rte_flow_error *error)
1343 {
1344         struct mlx5_priv *priv = dev->data->dev_private;
1345         struct mlx5_dev_config *config = &priv->config;
1346         const struct rte_flow_item_mark *spec = item->spec;
1347         const struct rte_flow_item_mark *mask = item->mask;
1348         const struct rte_flow_item_mark nic_mask = {
1349                 .id = priv->sh->dv_mark_mask,
1350         };
1351         int ret;
1352
1353         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354                 return rte_flow_error_set(error, ENOTSUP,
1355                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1356                                           "extended metadata feature"
1357                                           " isn't enabled");
1358         if (!mlx5_flow_ext_mreg_supported(dev))
1359                 return rte_flow_error_set(error, ENOTSUP,
1360                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1361                                           "extended metadata register"
1362                                           " isn't supported");
1363         if (!nic_mask.id)
1364                 return rte_flow_error_set(error, ENOTSUP,
1365                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1366                                           "extended metadata register"
1367                                           " isn't available");
1368         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1369         if (ret < 0)
1370                 return ret;
1371         if (!spec)
1372                 return rte_flow_error_set(error, EINVAL,
1373                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1374                                           item->spec,
1375                                           "data cannot be empty");
1376         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377                 return rte_flow_error_set(error, EINVAL,
1378                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1379                                           &spec->id,
1380                                           "mark id exceeds the limit");
1381         if (!mask)
1382                 mask = &nic_mask;
1383         if (!mask->id)
1384                 return rte_flow_error_set(error, EINVAL,
1385                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386                                         "mask cannot be zero");
1387
1388         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389                                         (const uint8_t *)&nic_mask,
1390                                         sizeof(struct rte_flow_item_mark),
1391                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1392         if (ret < 0)
1393                 return ret;
1394         return 0;
1395 }
1396
1397 /**
1398  * Validate META item.
1399  *
1400  * @param[in] dev
1401  *   Pointer to the rte_eth_dev structure.
1402  * @param[in] item
1403  *   Item specification.
1404  * @param[in] attr
1405  *   Attributes of flow that includes this item.
1406  * @param[out] error
1407  *   Pointer to error structure.
1408  *
1409  * @return
1410  *   0 on success, a negative errno value otherwise and rte_errno is set.
1411  */
1412 static int
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414                            const struct rte_flow_item *item,
1415                            const struct rte_flow_attr *attr,
1416                            struct rte_flow_error *error)
1417 {
1418         struct mlx5_priv *priv = dev->data->dev_private;
1419         struct mlx5_dev_config *config = &priv->config;
1420         const struct rte_flow_item_meta *spec = item->spec;
1421         const struct rte_flow_item_meta *mask = item->mask;
1422         struct rte_flow_item_meta nic_mask = {
1423                 .data = UINT32_MAX
1424         };
1425         int reg;
1426         int ret;
1427
1428         if (!spec)
1429                 return rte_flow_error_set(error, EINVAL,
1430                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1431                                           item->spec,
1432                                           "data cannot be empty");
1433         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434                 if (!mlx5_flow_ext_mreg_supported(dev))
1435                         return rte_flow_error_set(error, ENOTSUP,
1436                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1437                                           "extended metadata register"
1438                                           " isn't supported");
1439                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1440                 if (reg < 0)
1441                         return reg;
1442                 if (reg == REG_NON)
1443                         return rte_flow_error_set(error, ENOTSUP,
1444                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1445                                         "unavalable extended metadata register");
1446                 if (reg == REG_B)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                           "match on reg_b "
1450                                           "isn't supported");
1451                 if (reg != REG_A)
1452                         nic_mask.data = priv->sh->dv_meta_mask;
1453         } else if (attr->transfer) {
1454                 return rte_flow_error_set(error, ENOTSUP,
1455                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1456                                         "extended metadata feature "
1457                                         "should be enabled when "
1458                                         "meta item is requested "
1459                                         "with e-switch mode ");
1460         }
1461         if (!mask)
1462                 mask = &rte_flow_item_meta_mask;
1463         if (!mask->data)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466                                         "mask cannot be zero");
1467
1468         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469                                         (const uint8_t *)&nic_mask,
1470                                         sizeof(struct rte_flow_item_meta),
1471                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1472         return ret;
1473 }
1474
1475 /**
1476  * Validate TAG item.
1477  *
1478  * @param[in] dev
1479  *   Pointer to the rte_eth_dev structure.
1480  * @param[in] item
1481  *   Item specification.
1482  * @param[in] attr
1483  *   Attributes of flow that includes this item.
1484  * @param[out] error
1485  *   Pointer to error structure.
1486  *
1487  * @return
1488  *   0 on success, a negative errno value otherwise and rte_errno is set.
1489  */
1490 static int
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492                           const struct rte_flow_item *item,
1493                           const struct rte_flow_attr *attr __rte_unused,
1494                           struct rte_flow_error *error)
1495 {
1496         const struct rte_flow_item_tag *spec = item->spec;
1497         const struct rte_flow_item_tag *mask = item->mask;
1498         const struct rte_flow_item_tag nic_mask = {
1499                 .data = RTE_BE32(UINT32_MAX),
1500                 .index = 0xff,
1501         };
1502         int ret;
1503
1504         if (!mlx5_flow_ext_mreg_supported(dev))
1505                 return rte_flow_error_set(error, ENOTSUP,
1506                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1507                                           "extensive metadata register"
1508                                           " isn't supported");
1509         if (!spec)
1510                 return rte_flow_error_set(error, EINVAL,
1511                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1512                                           item->spec,
1513                                           "data cannot be empty");
1514         if (!mask)
1515                 mask = &rte_flow_item_tag_mask;
1516         if (!mask->data)
1517                 return rte_flow_error_set(error, EINVAL,
1518                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519                                         "mask cannot be zero");
1520
1521         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522                                         (const uint8_t *)&nic_mask,
1523                                         sizeof(struct rte_flow_item_tag),
1524                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1525         if (ret < 0)
1526                 return ret;
1527         if (mask->index != 0xff)
1528                 return rte_flow_error_set(error, EINVAL,
1529                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530                                           "partial mask for tag index"
1531                                           " is not supported");
1532         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1533         if (ret < 0)
1534                 return ret;
1535         MLX5_ASSERT(ret != REG_NON);
1536         return 0;
1537 }
1538
1539 /**
1540  * Validate vport item.
1541  *
1542  * @param[in] dev
1543  *   Pointer to the rte_eth_dev structure.
1544  * @param[in] item
1545  *   Item specification.
1546  * @param[in] attr
1547  *   Attributes of flow that includes this item.
1548  * @param[in] item_flags
1549  *   Bit-fields that holds the items detected until now.
1550  * @param[out] error
1551  *   Pointer to error structure.
1552  *
1553  * @return
1554  *   0 on success, a negative errno value otherwise and rte_errno is set.
1555  */
1556 static int
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558                               const struct rte_flow_item *item,
1559                               const struct rte_flow_attr *attr,
1560                               uint64_t item_flags,
1561                               struct rte_flow_error *error)
1562 {
1563         const struct rte_flow_item_port_id *spec = item->spec;
1564         const struct rte_flow_item_port_id *mask = item->mask;
1565         const struct rte_flow_item_port_id switch_mask = {
1566                         .id = 0xffffffff,
1567         };
1568         struct mlx5_priv *esw_priv;
1569         struct mlx5_priv *dev_priv;
1570         int ret;
1571
1572         if (!attr->transfer)
1573                 return rte_flow_error_set(error, EINVAL,
1574                                           RTE_FLOW_ERROR_TYPE_ITEM,
1575                                           NULL,
1576                                           "match on port id is valid only"
1577                                           " when transfer flag is enabled");
1578         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579                 return rte_flow_error_set(error, ENOTSUP,
1580                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1581                                           "multiple source ports are not"
1582                                           " supported");
1583         if (!mask)
1584                 mask = &switch_mask;
1585         if (mask->id != 0xffffffff)
1586                 return rte_flow_error_set(error, ENOTSUP,
1587                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1588                                            mask,
1589                                            "no support for partial mask on"
1590                                            " \"id\" field");
1591         ret = mlx5_flow_item_acceptable
1592                                 (item, (const uint8_t *)mask,
1593                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1594                                  sizeof(struct rte_flow_item_port_id),
1595                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1596         if (ret)
1597                 return ret;
1598         if (!spec)
1599                 return 0;
1600         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1601         if (!esw_priv)
1602                 return rte_flow_error_set(error, rte_errno,
1603                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604                                           "failed to obtain E-Switch info for"
1605                                           " port");
1606         dev_priv = mlx5_dev_to_eswitch_info(dev);
1607         if (!dev_priv)
1608                 return rte_flow_error_set(error, rte_errno,
1609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1610                                           NULL,
1611                                           "failed to obtain E-Switch info");
1612         if (esw_priv->domain_id != dev_priv->domain_id)
1613                 return rte_flow_error_set(error, EINVAL,
1614                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615                                           "cannot match on a port from a"
1616                                           " different E-Switch");
1617         return 0;
1618 }
1619
1620 /**
1621  * Validate VLAN item.
1622  *
1623  * @param[in] item
1624  *   Item specification.
1625  * @param[in] item_flags
1626  *   Bit-fields that holds the items detected until now.
1627  * @param[in] dev
1628  *   Ethernet device flow is being created on.
1629  * @param[out] error
1630  *   Pointer to error structure.
1631  *
1632  * @return
1633  *   0 on success, a negative errno value otherwise and rte_errno is set.
1634  */
1635 static int
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637                            uint64_t item_flags,
1638                            struct rte_eth_dev *dev,
1639                            struct rte_flow_error *error)
1640 {
1641         const struct rte_flow_item_vlan *mask = item->mask;
1642         const struct rte_flow_item_vlan nic_mask = {
1643                 .tci = RTE_BE16(UINT16_MAX),
1644                 .inner_type = RTE_BE16(UINT16_MAX),
1645                 .has_more_vlan = 1,
1646         };
1647         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1648         int ret;
1649         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650                                         MLX5_FLOW_LAYER_INNER_L4) :
1651                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1652                                         MLX5_FLOW_LAYER_OUTER_L4);
1653         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1655
1656         if (item_flags & vlanm)
1657                 return rte_flow_error_set(error, EINVAL,
1658                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1659                                           "multiple VLAN layers not supported");
1660         else if ((item_flags & l34m) != 0)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "VLAN cannot follow L3/L4 layer");
1664         if (!mask)
1665                 mask = &rte_flow_item_vlan_mask;
1666         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667                                         (const uint8_t *)&nic_mask,
1668                                         sizeof(struct rte_flow_item_vlan),
1669                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1670         if (ret)
1671                 return ret;
1672         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673                 struct mlx5_priv *priv = dev->data->dev_private;
1674
1675                 if (priv->vmwa_context) {
1676                         /*
1677                          * Non-NULL context means we have a virtual machine
1678                          * and SR-IOV enabled, we have to create VLAN interface
1679                          * to make hypervisor to setup E-Switch vport
1680                          * context correctly. We avoid creating the multiple
1681                          * VLAN interfaces, so we cannot support VLAN tag mask.
1682                          */
1683                         return rte_flow_error_set(error, EINVAL,
1684                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1685                                                   item,
1686                                                   "VLAN tag mask is not"
1687                                                   " supported in virtual"
1688                                                   " environment");
1689                 }
1690         }
1691         return 0;
1692 }
1693
1694 /*
1695  * GTP flags are contained in 1 byte of the format:
1696  * -------------------------------------------
1697  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1698  * |-----------------------------------------|
1699  * | value | Version | PT | Res | E | S | PN |
1700  * -------------------------------------------
1701  *
1702  * Matching is supported only for GTP flags E, S, PN.
1703  */
1704 #define MLX5_GTP_FLAGS_MASK     0x07
1705
1706 /**
1707  * Validate GTP item.
1708  *
1709  * @param[in] dev
1710  *   Pointer to the rte_eth_dev structure.
1711  * @param[in] item
1712  *   Item specification.
1713  * @param[in] item_flags
1714  *   Bit-fields that holds the items detected until now.
1715  * @param[out] error
1716  *   Pointer to error structure.
1717  *
1718  * @return
1719  *   0 on success, a negative errno value otherwise and rte_errno is set.
1720  */
1721 static int
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723                           const struct rte_flow_item *item,
1724                           uint64_t item_flags,
1725                           struct rte_flow_error *error)
1726 {
1727         struct mlx5_priv *priv = dev->data->dev_private;
1728         const struct rte_flow_item_gtp *spec = item->spec;
1729         const struct rte_flow_item_gtp *mask = item->mask;
1730         const struct rte_flow_item_gtp nic_mask = {
1731                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1732                 .msg_type = 0xff,
1733                 .teid = RTE_BE32(0xffffffff),
1734         };
1735
1736         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1739                                           "GTP support is not enabled");
1740         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "multiple tunnel layers not"
1744                                           " supported");
1745         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1748                                           "no outer UDP layer found");
1749         if (!mask)
1750                 mask = &rte_flow_item_gtp_mask;
1751         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752                 return rte_flow_error_set(error, ENOTSUP,
1753                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1754                                           "Match is supported for GTP"
1755                                           " flags only");
1756         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757                                          (const uint8_t *)&nic_mask,
1758                                          sizeof(struct rte_flow_item_gtp),
1759                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1760 }
1761
1762 /**
1763  * Validate IPV4 item.
1764  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1765  * add specific validation of fragment_offset field,
1766  *
1767  * @param[in] item
1768  *   Item specification.
1769  * @param[in] item_flags
1770  *   Bit-fields that holds the items detected until now.
1771  * @param[out] error
1772  *   Pointer to error structure.
1773  *
1774  * @return
1775  *   0 on success, a negative errno value otherwise and rte_errno is set.
1776  */
1777 static int
1778 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1779                            uint64_t item_flags,
1780                            uint64_t last_item,
1781                            uint16_t ether_type,
1782                            struct rte_flow_error *error)
1783 {
1784         int ret;
1785         const struct rte_flow_item_ipv4 *spec = item->spec;
1786         const struct rte_flow_item_ipv4 *last = item->last;
1787         const struct rte_flow_item_ipv4 *mask = item->mask;
1788         rte_be16_t fragment_offset_spec = 0;
1789         rte_be16_t fragment_offset_last = 0;
1790         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1791                 .hdr = {
1792                         .src_addr = RTE_BE32(0xffffffff),
1793                         .dst_addr = RTE_BE32(0xffffffff),
1794                         .type_of_service = 0xff,
1795                         .fragment_offset = RTE_BE16(0xffff),
1796                         .next_proto_id = 0xff,
1797                         .time_to_live = 0xff,
1798                 },
1799         };
1800
1801         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1802                                            ether_type, &nic_ipv4_mask,
1803                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1804         if (ret < 0)
1805                 return ret;
1806         if (spec && mask)
1807                 fragment_offset_spec = spec->hdr.fragment_offset &
1808                                        mask->hdr.fragment_offset;
1809         if (!fragment_offset_spec)
1810                 return 0;
1811         /*
1812          * spec and mask are valid, enforce using full mask to make sure the
1813          * complete value is used correctly.
1814          */
1815         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1816                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1817                 return rte_flow_error_set(error, EINVAL,
1818                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1819                                           item, "must use full mask for"
1820                                           " fragment_offset");
1821         /*
1822          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1823          * indicating this is 1st fragment of fragmented packet.
1824          * This is not yet supported in MLX5, return appropriate error message.
1825          */
1826         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1829                                           "match on first fragment not "
1830                                           "supported");
1831         if (fragment_offset_spec && !last)
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1834                                           "specified value not supported");
1835         /* spec and last are valid, validate the specified range. */
1836         fragment_offset_last = last->hdr.fragment_offset &
1837                                mask->hdr.fragment_offset;
1838         /*
1839          * Match on fragment_offset spec 0x2001 and last 0x3fff
1840          * means MF is 1 and frag-offset is > 0.
1841          * This packet is fragment 2nd and onward, excluding last.
1842          * This is not yet supported in MLX5, return appropriate
1843          * error message.
1844          */
1845         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1846             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1847                 return rte_flow_error_set(error, ENOTSUP,
1848                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1849                                           last, "match on following "
1850                                           "fragments not supported");
1851         /*
1852          * Match on fragment_offset spec 0x0001 and last 0x1fff
1853          * means MF is 0 and frag-offset is > 0.
1854          * This packet is last fragment of fragmented packet.
1855          * This is not yet supported in MLX5, return appropriate
1856          * error message.
1857          */
1858         if (fragment_offset_spec == RTE_BE16(1) &&
1859             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1860                 return rte_flow_error_set(error, ENOTSUP,
1861                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1862                                           last, "match on last "
1863                                           "fragment not supported");
1864         /*
1865          * Match on fragment_offset spec 0x0001 and last 0x3fff
1866          * means MF and/or frag-offset is not 0.
1867          * This is a fragmented packet.
1868          * Other range values are invalid and rejected.
1869          */
1870         if (!(fragment_offset_spec == RTE_BE16(1) &&
1871               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1872                 return rte_flow_error_set(error, ENOTSUP,
1873                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1874                                           "specified range not supported");
1875         return 0;
1876 }
1877
1878 /**
1879  * Validate IPV6 fragment extension item.
1880  *
1881  * @param[in] item
1882  *   Item specification.
1883  * @param[in] item_flags
1884  *   Bit-fields that holds the items detected until now.
1885  * @param[out] error
1886  *   Pointer to error structure.
1887  *
1888  * @return
1889  *   0 on success, a negative errno value otherwise and rte_errno is set.
1890  */
1891 static int
1892 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1893                                     uint64_t item_flags,
1894                                     struct rte_flow_error *error)
1895 {
1896         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1897         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1898         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1899         rte_be16_t frag_data_spec = 0;
1900         rte_be16_t frag_data_last = 0;
1901         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1902         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1903                                       MLX5_FLOW_LAYER_OUTER_L4;
1904         int ret = 0;
1905         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1906                 .hdr = {
1907                         .next_header = 0xff,
1908                         .frag_data = RTE_BE16(0xffff),
1909                 },
1910         };
1911
1912         if (item_flags & l4m)
1913                 return rte_flow_error_set(error, EINVAL,
1914                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1915                                           "ipv6 fragment extension item cannot "
1916                                           "follow L4 item.");
1917         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1918             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1919                 return rte_flow_error_set(error, EINVAL,
1920                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1921                                           "ipv6 fragment extension item must "
1922                                           "follow ipv6 item");
1923         if (spec && mask)
1924                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1925         if (!frag_data_spec)
1926                 return 0;
1927         /*
1928          * spec and mask are valid, enforce using full mask to make sure the
1929          * complete value is used correctly.
1930          */
1931         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1932                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1933                 return rte_flow_error_set(error, EINVAL,
1934                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1935                                           item, "must use full mask for"
1936                                           " frag_data");
1937         /*
1938          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1939          * This is 1st fragment of fragmented packet.
1940          */
1941         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1942                 return rte_flow_error_set(error, ENOTSUP,
1943                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1944                                           "match on first fragment not "
1945                                           "supported");
1946         if (frag_data_spec && !last)
1947                 return rte_flow_error_set(error, EINVAL,
1948                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1949                                           "specified value not supported");
1950         ret = mlx5_flow_item_acceptable
1951                                 (item, (const uint8_t *)mask,
1952                                  (const uint8_t *)&nic_mask,
1953                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1954                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1955         if (ret)
1956                 return ret;
1957         /* spec and last are valid, validate the specified range. */
1958         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1959         /*
1960          * Match on frag_data spec 0x0009 and last 0xfff9
1961          * means M is 1 and frag-offset is > 0.
1962          * This packet is fragment 2nd and onward, excluding last.
1963          * This is not yet supported in MLX5, return appropriate
1964          * error message.
1965          */
1966         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1967                                        RTE_IPV6_EHDR_MF_MASK) &&
1968             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1969                 return rte_flow_error_set(error, ENOTSUP,
1970                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1971                                           last, "match on following "
1972                                           "fragments not supported");
1973         /*
1974          * Match on frag_data spec 0x0008 and last 0xfff8
1975          * means M is 0 and frag-offset is > 0.
1976          * This packet is last fragment of fragmented packet.
1977          * This is not yet supported in MLX5, return appropriate
1978          * error message.
1979          */
1980         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
1981             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
1982                 return rte_flow_error_set(error, ENOTSUP,
1983                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1984                                           last, "match on last "
1985                                           "fragment not supported");
1986         /* Other range values are invalid and rejected. */
1987         return rte_flow_error_set(error, EINVAL,
1988                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1989                                   "specified range not supported");
1990 }
1991
1992 /**
1993  * Validate the pop VLAN action.
1994  *
1995  * @param[in] dev
1996  *   Pointer to the rte_eth_dev structure.
1997  * @param[in] action_flags
1998  *   Holds the actions detected until now.
1999  * @param[in] action
2000  *   Pointer to the pop vlan action.
2001  * @param[in] item_flags
2002  *   The items found in this flow rule.
2003  * @param[in] attr
2004  *   Pointer to flow attributes.
2005  * @param[out] error
2006  *   Pointer to error structure.
2007  *
2008  * @return
2009  *   0 on success, a negative errno value otherwise and rte_errno is set.
2010  */
2011 static int
2012 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2013                                  uint64_t action_flags,
2014                                  const struct rte_flow_action *action,
2015                                  uint64_t item_flags,
2016                                  const struct rte_flow_attr *attr,
2017                                  struct rte_flow_error *error)
2018 {
2019         const struct mlx5_priv *priv = dev->data->dev_private;
2020
2021         (void)action;
2022         (void)attr;
2023         if (!priv->sh->pop_vlan_action)
2024                 return rte_flow_error_set(error, ENOTSUP,
2025                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2026                                           NULL,
2027                                           "pop vlan action is not supported");
2028         if (attr->egress)
2029                 return rte_flow_error_set(error, ENOTSUP,
2030                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2031                                           NULL,
2032                                           "pop vlan action not supported for "
2033                                           "egress");
2034         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2035                 return rte_flow_error_set(error, ENOTSUP,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2037                                           "no support for multiple VLAN "
2038                                           "actions");
2039         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2040         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2041             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2042                 return rte_flow_error_set(error, ENOTSUP,
2043                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2044                                           NULL,
2045                                           "cannot pop vlan after decap without "
2046                                           "match on inner vlan in the flow");
2047         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2048         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2049             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2050                 return rte_flow_error_set(error, ENOTSUP,
2051                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2052                                           NULL,
2053                                           "cannot pop vlan without a "
2054                                           "match on (outer) vlan in the flow");
2055         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2056                 return rte_flow_error_set(error, EINVAL,
2057                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2058                                           "wrong action order, port_id should "
2059                                           "be after pop VLAN action");
2060         if (!attr->transfer && priv->representor)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2063                                           "pop vlan action for VF representor "
2064                                           "not supported on NIC table");
2065         return 0;
2066 }
2067
2068 /**
2069  * Get VLAN default info from vlan match info.
2070  *
2071  * @param[in] items
2072  *   the list of item specifications.
2073  * @param[out] vlan
2074  *   pointer VLAN info to fill to.
2075  *
2076  * @return
2077  *   0 on success, a negative errno value otherwise and rte_errno is set.
2078  */
2079 static void
2080 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2081                                   struct rte_vlan_hdr *vlan)
2082 {
2083         const struct rte_flow_item_vlan nic_mask = {
2084                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2085                                 MLX5DV_FLOW_VLAN_VID_MASK),
2086                 .inner_type = RTE_BE16(0xffff),
2087         };
2088
2089         if (items == NULL)
2090                 return;
2091         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2092                 int type = items->type;
2093
2094                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2095                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2096                         break;
2097         }
2098         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2099                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2100                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2101
2102                 /* If VLAN item in pattern doesn't contain data, return here. */
2103                 if (!vlan_v)
2104                         return;
2105                 if (!vlan_m)
2106                         vlan_m = &nic_mask;
2107                 /* Only full match values are accepted */
2108                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2109                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2110                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2111                         vlan->vlan_tci |=
2112                                 rte_be_to_cpu_16(vlan_v->tci &
2113                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2114                 }
2115                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2116                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2117                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2118                         vlan->vlan_tci |=
2119                                 rte_be_to_cpu_16(vlan_v->tci &
2120                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2121                 }
2122                 if (vlan_m->inner_type == nic_mask.inner_type)
2123                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2124                                                            vlan_m->inner_type);
2125         }
2126 }
2127
2128 /**
2129  * Validate the push VLAN action.
2130  *
2131  * @param[in] dev
2132  *   Pointer to the rte_eth_dev structure.
2133  * @param[in] action_flags
2134  *   Holds the actions detected until now.
2135  * @param[in] item_flags
2136  *   The items found in this flow rule.
2137  * @param[in] action
2138  *   Pointer to the action structure.
2139  * @param[in] attr
2140  *   Pointer to flow attributes
2141  * @param[out] error
2142  *   Pointer to error structure.
2143  *
2144  * @return
2145  *   0 on success, a negative errno value otherwise and rte_errno is set.
2146  */
2147 static int
2148 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2149                                   uint64_t action_flags,
2150                                   const struct rte_flow_item_vlan *vlan_m,
2151                                   const struct rte_flow_action *action,
2152                                   const struct rte_flow_attr *attr,
2153                                   struct rte_flow_error *error)
2154 {
2155         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2156         const struct mlx5_priv *priv = dev->data->dev_private;
2157
2158         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2159             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2160                 return rte_flow_error_set(error, EINVAL,
2161                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2162                                           "invalid vlan ethertype");
2163         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2164                 return rte_flow_error_set(error, EINVAL,
2165                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2166                                           "wrong action order, port_id should "
2167                                           "be after push VLAN");
2168         if (!attr->transfer && priv->representor)
2169                 return rte_flow_error_set(error, ENOTSUP,
2170                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2171                                           "push vlan action for VF representor "
2172                                           "not supported on NIC table");
2173         if (vlan_m &&
2174             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2175             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2176                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2177             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2178             !(mlx5_flow_find_action
2179                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2180                 return rte_flow_error_set(error, EINVAL,
2181                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2182                                           "not full match mask on VLAN PCP and "
2183                                           "there is no of_set_vlan_pcp action, "
2184                                           "push VLAN action cannot figure out "
2185                                           "PCP value");
2186         if (vlan_m &&
2187             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2188             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2189                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2190             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2191             !(mlx5_flow_find_action
2192                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2193                 return rte_flow_error_set(error, EINVAL,
2194                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2195                                           "not full match mask on VLAN VID and "
2196                                           "there is no of_set_vlan_vid action, "
2197                                           "push VLAN action cannot figure out "
2198                                           "VID value");
2199         (void)attr;
2200         return 0;
2201 }
2202
2203 /**
2204  * Validate the set VLAN PCP.
2205  *
2206  * @param[in] action_flags
2207  *   Holds the actions detected until now.
2208  * @param[in] actions
2209  *   Pointer to the list of actions remaining in the flow rule.
2210  * @param[out] error
2211  *   Pointer to error structure.
2212  *
2213  * @return
2214  *   0 on success, a negative errno value otherwise and rte_errno is set.
2215  */
2216 static int
2217 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2218                                      const struct rte_flow_action actions[],
2219                                      struct rte_flow_error *error)
2220 {
2221         const struct rte_flow_action *action = actions;
2222         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2223
2224         if (conf->vlan_pcp > 7)
2225                 return rte_flow_error_set(error, EINVAL,
2226                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2227                                           "VLAN PCP value is too big");
2228         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2229                 return rte_flow_error_set(error, ENOTSUP,
2230                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2231                                           "set VLAN PCP action must follow "
2232                                           "the push VLAN action");
2233         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2234                 return rte_flow_error_set(error, ENOTSUP,
2235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2236                                           "Multiple VLAN PCP modification are "
2237                                           "not supported");
2238         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2239                 return rte_flow_error_set(error, EINVAL,
2240                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2241                                           "wrong action order, port_id should "
2242                                           "be after set VLAN PCP");
2243         return 0;
2244 }
2245
2246 /**
2247  * Validate the set VLAN VID.
2248  *
2249  * @param[in] item_flags
2250  *   Holds the items detected in this rule.
2251  * @param[in] action_flags
2252  *   Holds the actions detected until now.
2253  * @param[in] actions
2254  *   Pointer to the list of actions remaining in the flow rule.
2255  * @param[out] error
2256  *   Pointer to error structure.
2257  *
2258  * @return
2259  *   0 on success, a negative errno value otherwise and rte_errno is set.
2260  */
2261 static int
2262 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2263                                      uint64_t action_flags,
2264                                      const struct rte_flow_action actions[],
2265                                      struct rte_flow_error *error)
2266 {
2267         const struct rte_flow_action *action = actions;
2268         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2269
2270         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2271                 return rte_flow_error_set(error, EINVAL,
2272                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2273                                           "VLAN VID value is too big");
2274         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2275             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2276                 return rte_flow_error_set(error, ENOTSUP,
2277                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2278                                           "set VLAN VID action must follow push"
2279                                           " VLAN action or match on VLAN item");
2280         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2281                 return rte_flow_error_set(error, ENOTSUP,
2282                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2283                                           "Multiple VLAN VID modifications are "
2284                                           "not supported");
2285         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2286                 return rte_flow_error_set(error, EINVAL,
2287                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2288                                           "wrong action order, port_id should "
2289                                           "be after set VLAN VID");
2290         return 0;
2291 }
2292
2293 /*
2294  * Validate the FLAG action.
2295  *
2296  * @param[in] dev
2297  *   Pointer to the rte_eth_dev structure.
2298  * @param[in] action_flags
2299  *   Holds the actions detected until now.
2300  * @param[in] attr
2301  *   Pointer to flow attributes
2302  * @param[out] error
2303  *   Pointer to error structure.
2304  *
2305  * @return
2306  *   0 on success, a negative errno value otherwise and rte_errno is set.
2307  */
2308 static int
2309 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2310                              uint64_t action_flags,
2311                              const struct rte_flow_attr *attr,
2312                              struct rte_flow_error *error)
2313 {
2314         struct mlx5_priv *priv = dev->data->dev_private;
2315         struct mlx5_dev_config *config = &priv->config;
2316         int ret;
2317
2318         /* Fall back if no extended metadata register support. */
2319         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2320                 return mlx5_flow_validate_action_flag(action_flags, attr,
2321                                                       error);
2322         /* Extensive metadata mode requires registers. */
2323         if (!mlx5_flow_ext_mreg_supported(dev))
2324                 return rte_flow_error_set(error, ENOTSUP,
2325                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2326                                           "no metadata registers "
2327                                           "to support flag action");
2328         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2329                 return rte_flow_error_set(error, ENOTSUP,
2330                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2331                                           "extended metadata register"
2332                                           " isn't available");
2333         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2334         if (ret < 0)
2335                 return ret;
2336         MLX5_ASSERT(ret > 0);
2337         if (action_flags & MLX5_FLOW_ACTION_MARK)
2338                 return rte_flow_error_set(error, EINVAL,
2339                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2340                                           "can't mark and flag in same flow");
2341         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2342                 return rte_flow_error_set(error, EINVAL,
2343                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2344                                           "can't have 2 flag"
2345                                           " actions in same flow");
2346         return 0;
2347 }
2348
2349 /**
2350  * Validate MARK action.
2351  *
2352  * @param[in] dev
2353  *   Pointer to the rte_eth_dev structure.
2354  * @param[in] action
2355  *   Pointer to action.
2356  * @param[in] action_flags
2357  *   Holds the actions detected until now.
2358  * @param[in] attr
2359  *   Pointer to flow attributes
2360  * @param[out] error
2361  *   Pointer to error structure.
2362  *
2363  * @return
2364  *   0 on success, a negative errno value otherwise and rte_errno is set.
2365  */
2366 static int
2367 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2368                              const struct rte_flow_action *action,
2369                              uint64_t action_flags,
2370                              const struct rte_flow_attr *attr,
2371                              struct rte_flow_error *error)
2372 {
2373         struct mlx5_priv *priv = dev->data->dev_private;
2374         struct mlx5_dev_config *config = &priv->config;
2375         const struct rte_flow_action_mark *mark = action->conf;
2376         int ret;
2377
2378         /* Fall back if no extended metadata register support. */
2379         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2380                 return mlx5_flow_validate_action_mark(action, action_flags,
2381                                                       attr, error);
2382         /* Extensive metadata mode requires registers. */
2383         if (!mlx5_flow_ext_mreg_supported(dev))
2384                 return rte_flow_error_set(error, ENOTSUP,
2385                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2386                                           "no metadata registers "
2387                                           "to support mark action");
2388         if (!priv->sh->dv_mark_mask)
2389                 return rte_flow_error_set(error, ENOTSUP,
2390                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391                                           "extended metadata register"
2392                                           " isn't available");
2393         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2394         if (ret < 0)
2395                 return ret;
2396         MLX5_ASSERT(ret > 0);
2397         if (!mark)
2398                 return rte_flow_error_set(error, EINVAL,
2399                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2400                                           "configuration cannot be null");
2401         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2402                 return rte_flow_error_set(error, EINVAL,
2403                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2404                                           &mark->id,
2405                                           "mark id exceeds the limit");
2406         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2407                 return rte_flow_error_set(error, EINVAL,
2408                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2409                                           "can't flag and mark in same flow");
2410         if (action_flags & MLX5_FLOW_ACTION_MARK)
2411                 return rte_flow_error_set(error, EINVAL,
2412                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2413                                           "can't have 2 mark actions in same"
2414                                           " flow");
2415         return 0;
2416 }
2417
2418 /**
2419  * Validate SET_META action.
2420  *
2421  * @param[in] dev
2422  *   Pointer to the rte_eth_dev structure.
2423  * @param[in] action
2424  *   Pointer to the action structure.
2425  * @param[in] action_flags
2426  *   Holds the actions detected until now.
2427  * @param[in] attr
2428  *   Pointer to flow attributes
2429  * @param[out] error
2430  *   Pointer to error structure.
2431  *
2432  * @return
2433  *   0 on success, a negative errno value otherwise and rte_errno is set.
2434  */
2435 static int
2436 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2437                                  const struct rte_flow_action *action,
2438                                  uint64_t action_flags __rte_unused,
2439                                  const struct rte_flow_attr *attr,
2440                                  struct rte_flow_error *error)
2441 {
2442         const struct rte_flow_action_set_meta *conf;
2443         uint32_t nic_mask = UINT32_MAX;
2444         int reg;
2445
2446         if (!mlx5_flow_ext_mreg_supported(dev))
2447                 return rte_flow_error_set(error, ENOTSUP,
2448                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2449                                           "extended metadata register"
2450                                           " isn't supported");
2451         reg = flow_dv_get_metadata_reg(dev, attr, error);
2452         if (reg < 0)
2453                 return reg;
2454         if (reg == REG_NON)
2455                 return rte_flow_error_set(error, ENOTSUP,
2456                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2457                                           "unavalable extended metadata register");
2458         if (reg != REG_A && reg != REG_B) {
2459                 struct mlx5_priv *priv = dev->data->dev_private;
2460
2461                 nic_mask = priv->sh->dv_meta_mask;
2462         }
2463         if (!(action->conf))
2464                 return rte_flow_error_set(error, EINVAL,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2466                                           "configuration cannot be null");
2467         conf = (const struct rte_flow_action_set_meta *)action->conf;
2468         if (!conf->mask)
2469                 return rte_flow_error_set(error, EINVAL,
2470                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2471                                           "zero mask doesn't have any effect");
2472         if (conf->mask & ~nic_mask)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2475                                           "meta data must be within reg C0");
2476         return 0;
2477 }
2478
2479 /**
2480  * Validate SET_TAG action.
2481  *
2482  * @param[in] dev
2483  *   Pointer to the rte_eth_dev structure.
2484  * @param[in] action
2485  *   Pointer to the action structure.
2486  * @param[in] action_flags
2487  *   Holds the actions detected until now.
2488  * @param[in] attr
2489  *   Pointer to flow attributes
2490  * @param[out] error
2491  *   Pointer to error structure.
2492  *
2493  * @return
2494  *   0 on success, a negative errno value otherwise and rte_errno is set.
2495  */
2496 static int
2497 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2498                                 const struct rte_flow_action *action,
2499                                 uint64_t action_flags,
2500                                 const struct rte_flow_attr *attr,
2501                                 struct rte_flow_error *error)
2502 {
2503         const struct rte_flow_action_set_tag *conf;
2504         const uint64_t terminal_action_flags =
2505                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2506                 MLX5_FLOW_ACTION_RSS;
2507         int ret;
2508
2509         if (!mlx5_flow_ext_mreg_supported(dev))
2510                 return rte_flow_error_set(error, ENOTSUP,
2511                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2512                                           "extensive metadata register"
2513                                           " isn't supported");
2514         if (!(action->conf))
2515                 return rte_flow_error_set(error, EINVAL,
2516                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2517                                           "configuration cannot be null");
2518         conf = (const struct rte_flow_action_set_tag *)action->conf;
2519         if (!conf->mask)
2520                 return rte_flow_error_set(error, EINVAL,
2521                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2522                                           "zero mask doesn't have any effect");
2523         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2524         if (ret < 0)
2525                 return ret;
2526         if (!attr->transfer && attr->ingress &&
2527             (action_flags & terminal_action_flags))
2528                 return rte_flow_error_set(error, EINVAL,
2529                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2530                                           "set_tag has no effect"
2531                                           " with terminal actions");
2532         return 0;
2533 }
2534
2535 /**
2536  * Validate count action.
2537  *
2538  * @param[in] dev
2539  *   Pointer to rte_eth_dev structure.
2540  * @param[out] error
2541  *   Pointer to error structure.
2542  *
2543  * @return
2544  *   0 on success, a negative errno value otherwise and rte_errno is set.
2545  */
2546 static int
2547 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2548                               struct rte_flow_error *error)
2549 {
2550         struct mlx5_priv *priv = dev->data->dev_private;
2551
2552         if (!priv->config.devx)
2553                 goto notsup_err;
2554 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2555         return 0;
2556 #endif
2557 notsup_err:
2558         return rte_flow_error_set
2559                       (error, ENOTSUP,
2560                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2561                        NULL,
2562                        "count action not supported");
2563 }
2564
2565 /**
2566  * Validate the L2 encap action.
2567  *
2568  * @param[in] dev
2569  *   Pointer to the rte_eth_dev structure.
2570  * @param[in] action_flags
2571  *   Holds the actions detected until now.
2572  * @param[in] action
2573  *   Pointer to the action structure.
2574  * @param[in] attr
2575  *   Pointer to flow attributes.
2576  * @param[out] error
2577  *   Pointer to error structure.
2578  *
2579  * @return
2580  *   0 on success, a negative errno value otherwise and rte_errno is set.
2581  */
2582 static int
2583 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2584                                  uint64_t action_flags,
2585                                  const struct rte_flow_action *action,
2586                                  const struct rte_flow_attr *attr,
2587                                  struct rte_flow_error *error)
2588 {
2589         const struct mlx5_priv *priv = dev->data->dev_private;
2590
2591         if (!(action->conf))
2592                 return rte_flow_error_set(error, EINVAL,
2593                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2594                                           "configuration cannot be null");
2595         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2596                 return rte_flow_error_set(error, EINVAL,
2597                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2598                                           "can only have a single encap action "
2599                                           "in a flow");
2600         if (!attr->transfer && priv->representor)
2601                 return rte_flow_error_set(error, ENOTSUP,
2602                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2603                                           "encap action for VF representor "
2604                                           "not supported on NIC table");
2605         return 0;
2606 }
2607
2608 /**
2609  * Validate a decap action.
2610  *
2611  * @param[in] dev
2612  *   Pointer to the rte_eth_dev structure.
2613  * @param[in] action_flags
2614  *   Holds the actions detected until now.
2615  * @param[in] attr
2616  *   Pointer to flow attributes
2617  * @param[out] error
2618  *   Pointer to error structure.
2619  *
2620  * @return
2621  *   0 on success, a negative errno value otherwise and rte_errno is set.
2622  */
2623 static int
2624 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2625                               uint64_t action_flags,
2626                               const struct rte_flow_attr *attr,
2627                               struct rte_flow_error *error)
2628 {
2629         const struct mlx5_priv *priv = dev->data->dev_private;
2630
2631         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2632             !priv->config.decap_en)
2633                 return rte_flow_error_set(error, ENOTSUP,
2634                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2635                                           "decap is not enabled");
2636         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2637                 return rte_flow_error_set(error, ENOTSUP,
2638                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2639                                           action_flags &
2640                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2641                                           "have a single decap action" : "decap "
2642                                           "after encap is not supported");
2643         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2644                 return rte_flow_error_set(error, EINVAL,
2645                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2646                                           "can't have decap action after"
2647                                           " modify action");
2648         if (attr->egress)
2649                 return rte_flow_error_set(error, ENOTSUP,
2650                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2651                                           NULL,
2652                                           "decap action not supported for "
2653                                           "egress");
2654         if (!attr->transfer && priv->representor)
2655                 return rte_flow_error_set(error, ENOTSUP,
2656                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2657                                           "decap action for VF representor "
2658                                           "not supported on NIC table");
2659         return 0;
2660 }
2661
2662 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2663
2664 /**
2665  * Validate the raw encap and decap actions.
2666  *
2667  * @param[in] dev
2668  *   Pointer to the rte_eth_dev structure.
2669  * @param[in] decap
2670  *   Pointer to the decap action.
2671  * @param[in] encap
2672  *   Pointer to the encap action.
2673  * @param[in] attr
2674  *   Pointer to flow attributes
2675  * @param[in/out] action_flags
2676  *   Holds the actions detected until now.
2677  * @param[out] actions_n
2678  *   pointer to the number of actions counter.
2679  * @param[out] error
2680  *   Pointer to error structure.
2681  *
2682  * @return
2683  *   0 on success, a negative errno value otherwise and rte_errno is set.
2684  */
2685 static int
2686 flow_dv_validate_action_raw_encap_decap
2687         (struct rte_eth_dev *dev,
2688          const struct rte_flow_action_raw_decap *decap,
2689          const struct rte_flow_action_raw_encap *encap,
2690          const struct rte_flow_attr *attr, uint64_t *action_flags,
2691          int *actions_n, struct rte_flow_error *error)
2692 {
2693         const struct mlx5_priv *priv = dev->data->dev_private;
2694         int ret;
2695
2696         if (encap && (!encap->size || !encap->data))
2697                 return rte_flow_error_set(error, EINVAL,
2698                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2699                                           "raw encap data cannot be empty");
2700         if (decap && encap) {
2701                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2702                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2703                         /* L3 encap. */
2704                         decap = NULL;
2705                 else if (encap->size <=
2706                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2707                            decap->size >
2708                            MLX5_ENCAPSULATION_DECISION_SIZE)
2709                         /* L3 decap. */
2710                         encap = NULL;
2711                 else if (encap->size >
2712                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2713                            decap->size >
2714                            MLX5_ENCAPSULATION_DECISION_SIZE)
2715                         /* 2 L2 actions: encap and decap. */
2716                         ;
2717                 else
2718                         return rte_flow_error_set(error,
2719                                 ENOTSUP,
2720                                 RTE_FLOW_ERROR_TYPE_ACTION,
2721                                 NULL, "unsupported too small "
2722                                 "raw decap and too small raw "
2723                                 "encap combination");
2724         }
2725         if (decap) {
2726                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2727                                                     error);
2728                 if (ret < 0)
2729                         return ret;
2730                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2731                 ++(*actions_n);
2732         }
2733         if (encap) {
2734                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2735                         return rte_flow_error_set(error, ENOTSUP,
2736                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2737                                                   NULL,
2738                                                   "small raw encap size");
2739                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2740                         return rte_flow_error_set(error, EINVAL,
2741                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2742                                                   NULL,
2743                                                   "more than one encap action");
2744                 if (!attr->transfer && priv->representor)
2745                         return rte_flow_error_set
2746                                         (error, ENOTSUP,
2747                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2748                                          "encap action for VF representor "
2749                                          "not supported on NIC table");
2750                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2751                 ++(*actions_n);
2752         }
2753         return 0;
2754 }
2755
2756 /**
2757  * Match encap_decap resource.
2758  *
2759  * @param list
2760  *   Pointer to the hash list.
2761  * @param entry
2762  *   Pointer to exist resource entry object.
2763  * @param key
2764  *   Key of the new entry.
2765  * @param ctx_cb
2766  *   Pointer to new encap_decap resource.
2767  *
2768  * @return
2769  *   0 on matching, none-zero otherwise.
2770  */
2771 int
2772 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2773                              struct mlx5_hlist_entry *entry,
2774                              uint64_t key __rte_unused, void *cb_ctx)
2775 {
2776         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2777         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2778         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2779
2780         cache_resource = container_of(entry,
2781                                       struct mlx5_flow_dv_encap_decap_resource,
2782                                       entry);
2783         if (resource->reformat_type == cache_resource->reformat_type &&
2784             resource->ft_type == cache_resource->ft_type &&
2785             resource->flags == cache_resource->flags &&
2786             resource->size == cache_resource->size &&
2787             !memcmp((const void *)resource->buf,
2788                     (const void *)cache_resource->buf,
2789                     resource->size))
2790                 return 0;
2791         return -1;
2792 }
2793
2794 /**
2795  * Allocate encap_decap resource.
2796  *
2797  * @param list
2798  *   Pointer to the hash list.
2799  * @param entry
2800  *   Pointer to exist resource entry object.
2801  * @param ctx_cb
2802  *   Pointer to new encap_decap resource.
2803  *
2804  * @return
2805  *   0 on matching, none-zero otherwise.
2806  */
2807 struct mlx5_hlist_entry *
2808 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2809                               uint64_t key __rte_unused,
2810                               void *cb_ctx)
2811 {
2812         struct mlx5_dev_ctx_shared *sh = list->ctx;
2813         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2814         struct mlx5dv_dr_domain *domain;
2815         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2816         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2817         uint32_t idx;
2818         int ret;
2819
2820         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2821                 domain = sh->fdb_domain;
2822         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2823                 domain = sh->rx_domain;
2824         else
2825                 domain = sh->tx_domain;
2826         /* Register new encap/decap resource. */
2827         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2828                                        &idx);
2829         if (!cache_resource) {
2830                 rte_flow_error_set(ctx->error, ENOMEM,
2831                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2832                                    "cannot allocate resource memory");
2833                 return NULL;
2834         }
2835         *cache_resource = *resource;
2836         cache_resource->idx = idx;
2837         ret = mlx5_flow_os_create_flow_action_packet_reformat
2838                                         (sh->ctx, domain, cache_resource,
2839                                          &cache_resource->action);
2840         if (ret) {
2841                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2842                 rte_flow_error_set(ctx->error, ENOMEM,
2843                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2844                                    NULL, "cannot create action");
2845                 return NULL;
2846         }
2847
2848         return &cache_resource->entry;
2849 }
2850
2851 /**
2852  * Find existing encap/decap resource or create and register a new one.
2853  *
2854  * @param[in, out] dev
2855  *   Pointer to rte_eth_dev structure.
2856  * @param[in, out] resource
2857  *   Pointer to encap/decap resource.
2858  * @parm[in, out] dev_flow
2859  *   Pointer to the dev_flow.
2860  * @param[out] error
2861  *   pointer to error structure.
2862  *
2863  * @return
2864  *   0 on success otherwise -errno and errno is set.
2865  */
2866 static int
2867 flow_dv_encap_decap_resource_register
2868                         (struct rte_eth_dev *dev,
2869                          struct mlx5_flow_dv_encap_decap_resource *resource,
2870                          struct mlx5_flow *dev_flow,
2871                          struct rte_flow_error *error)
2872 {
2873         struct mlx5_priv *priv = dev->data->dev_private;
2874         struct mlx5_dev_ctx_shared *sh = priv->sh;
2875         struct mlx5_hlist_entry *entry;
2876         union {
2877                 struct {
2878                         uint32_t ft_type:8;
2879                         uint32_t refmt_type:8;
2880                         /*
2881                          * Header reformat actions can be shared between
2882                          * non-root tables. One bit to indicate non-root
2883                          * table or not.
2884                          */
2885                         uint32_t is_root:1;
2886                         uint32_t reserve:15;
2887                 };
2888                 uint32_t v32;
2889         } encap_decap_key = {
2890                 {
2891                         .ft_type = resource->ft_type,
2892                         .refmt_type = resource->reformat_type,
2893                         .is_root = !!dev_flow->dv.group,
2894                         .reserve = 0,
2895                 }
2896         };
2897         struct mlx5_flow_cb_ctx ctx = {
2898                 .error = error,
2899                 .data = resource,
2900         };
2901         uint64_t key64;
2902
2903         resource->flags = dev_flow->dv.group ? 0 : 1;
2904         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2905                                  sizeof(encap_decap_key.v32), 0);
2906         if (resource->reformat_type !=
2907             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2908             resource->size)
2909                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2910         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2911         if (!entry)
2912                 return -rte_errno;
2913         resource = container_of(entry, typeof(*resource), entry);
2914         dev_flow->dv.encap_decap = resource;
2915         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2916         return 0;
2917 }
2918
2919 /**
2920  * Find existing table jump resource or create and register a new one.
2921  *
2922  * @param[in, out] dev
2923  *   Pointer to rte_eth_dev structure.
2924  * @param[in, out] tbl
2925  *   Pointer to flow table resource.
2926  * @parm[in, out] dev_flow
2927  *   Pointer to the dev_flow.
2928  * @param[out] error
2929  *   pointer to error structure.
2930  *
2931  * @return
2932  *   0 on success otherwise -errno and errno is set.
2933  */
2934 static int
2935 flow_dv_jump_tbl_resource_register
2936                         (struct rte_eth_dev *dev __rte_unused,
2937                          struct mlx5_flow_tbl_resource *tbl,
2938                          struct mlx5_flow *dev_flow,
2939                          struct rte_flow_error *error __rte_unused)
2940 {
2941         struct mlx5_flow_tbl_data_entry *tbl_data =
2942                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2943
2944         MLX5_ASSERT(tbl);
2945         MLX5_ASSERT(tbl_data->jump.action);
2946         dev_flow->handle->rix_jump = tbl_data->idx;
2947         dev_flow->dv.jump = &tbl_data->jump;
2948         return 0;
2949 }
2950
2951 int
2952 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
2953                          struct mlx5_cache_entry *entry, void *cb_ctx)
2954 {
2955         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2956         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2957         struct mlx5_flow_dv_port_id_action_resource *res =
2958                         container_of(entry, typeof(*res), entry);
2959
2960         return ref->port_id != res->port_id;
2961 }
2962
2963 struct mlx5_cache_entry *
2964 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
2965                           struct mlx5_cache_entry *entry __rte_unused,
2966                           void *cb_ctx)
2967 {
2968         struct mlx5_dev_ctx_shared *sh = list->ctx;
2969         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2970         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2971         struct mlx5_flow_dv_port_id_action_resource *cache;
2972         uint32_t idx;
2973         int ret;
2974
2975         /* Register new port id action resource. */
2976         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
2977         if (!cache) {
2978                 rte_flow_error_set(ctx->error, ENOMEM,
2979                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2980                                    "cannot allocate port_id action cache memory");
2981                 return NULL;
2982         }
2983         *cache = *ref;
2984         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
2985                                                         ref->port_id,
2986                                                         &cache->action);
2987         if (ret) {
2988                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
2989                 rte_flow_error_set(ctx->error, ENOMEM,
2990                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2991                                    "cannot create action");
2992                 return NULL;
2993         }
2994         return &cache->entry;
2995 }
2996
2997 /**
2998  * Find existing table port ID resource or create and register a new one.
2999  *
3000  * @param[in, out] dev
3001  *   Pointer to rte_eth_dev structure.
3002  * @param[in, out] resource
3003  *   Pointer to port ID action resource.
3004  * @parm[in, out] dev_flow
3005  *   Pointer to the dev_flow.
3006  * @param[out] error
3007  *   pointer to error structure.
3008  *
3009  * @return
3010  *   0 on success otherwise -errno and errno is set.
3011  */
3012 static int
3013 flow_dv_port_id_action_resource_register
3014                         (struct rte_eth_dev *dev,
3015                          struct mlx5_flow_dv_port_id_action_resource *resource,
3016                          struct mlx5_flow *dev_flow,
3017                          struct rte_flow_error *error)
3018 {
3019         struct mlx5_priv *priv = dev->data->dev_private;
3020         struct mlx5_cache_entry *entry;
3021         struct mlx5_flow_dv_port_id_action_resource *cache;
3022         struct mlx5_flow_cb_ctx ctx = {
3023                 .error = error,
3024                 .data = resource,
3025         };
3026
3027         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3028         if (!entry)
3029                 return -rte_errno;
3030         cache = container_of(entry, typeof(*cache), entry);
3031         dev_flow->dv.port_id_action = cache;
3032         dev_flow->handle->rix_port_id_action = cache->idx;
3033         return 0;
3034 }
3035
3036 int
3037 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3038                          struct mlx5_cache_entry *entry, void *cb_ctx)
3039 {
3040         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3041         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3042         struct mlx5_flow_dv_push_vlan_action_resource *res =
3043                         container_of(entry, typeof(*res), entry);
3044
3045         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3046 }
3047
3048 struct mlx5_cache_entry *
3049 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3050                           struct mlx5_cache_entry *entry __rte_unused,
3051                           void *cb_ctx)
3052 {
3053         struct mlx5_dev_ctx_shared *sh = list->ctx;
3054         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3055         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3056         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3057         struct mlx5dv_dr_domain *domain;
3058         uint32_t idx;
3059         int ret;
3060
3061         /* Register new port id action resource. */
3062         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3063         if (!cache) {
3064                 rte_flow_error_set(ctx->error, ENOMEM,
3065                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3066                                    "cannot allocate push_vlan action cache memory");
3067                 return NULL;
3068         }
3069         *cache = *ref;
3070         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3071                 domain = sh->fdb_domain;
3072         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3073                 domain = sh->rx_domain;
3074         else
3075                 domain = sh->tx_domain;
3076         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3077                                                         &cache->action);
3078         if (ret) {
3079                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3080                 rte_flow_error_set(ctx->error, ENOMEM,
3081                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3082                                    "cannot create push vlan action");
3083                 return NULL;
3084         }
3085         return &cache->entry;
3086 }
3087
3088 /**
3089  * Find existing push vlan resource or create and register a new one.
3090  *
3091  * @param [in, out] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in, out] resource
3094  *   Pointer to port ID action resource.
3095  * @parm[in, out] dev_flow
3096  *   Pointer to the dev_flow.
3097  * @param[out] error
3098  *   pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success otherwise -errno and errno is set.
3102  */
3103 static int
3104 flow_dv_push_vlan_action_resource_register
3105                        (struct rte_eth_dev *dev,
3106                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3107                         struct mlx5_flow *dev_flow,
3108                         struct rte_flow_error *error)
3109 {
3110         struct mlx5_priv *priv = dev->data->dev_private;
3111         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3112         struct mlx5_cache_entry *entry;
3113         struct mlx5_flow_cb_ctx ctx = {
3114                 .error = error,
3115                 .data = resource,
3116         };
3117
3118         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3119         if (!entry)
3120                 return -rte_errno;
3121         cache = container_of(entry, typeof(*cache), entry);
3122
3123         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3124         dev_flow->dv.push_vlan_res = cache;
3125         return 0;
3126 }
3127
3128 /**
3129  * Get the size of specific rte_flow_item_type hdr size
3130  *
3131  * @param[in] item_type
3132  *   Tested rte_flow_item_type.
3133  *
3134  * @return
3135  *   sizeof struct item_type, 0 if void or irrelevant.
3136  */
3137 static size_t
3138 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3139 {
3140         size_t retval;
3141
3142         switch (item_type) {
3143         case RTE_FLOW_ITEM_TYPE_ETH:
3144                 retval = sizeof(struct rte_ether_hdr);
3145                 break;
3146         case RTE_FLOW_ITEM_TYPE_VLAN:
3147                 retval = sizeof(struct rte_vlan_hdr);
3148                 break;
3149         case RTE_FLOW_ITEM_TYPE_IPV4:
3150                 retval = sizeof(struct rte_ipv4_hdr);
3151                 break;
3152         case RTE_FLOW_ITEM_TYPE_IPV6:
3153                 retval = sizeof(struct rte_ipv6_hdr);
3154                 break;
3155         case RTE_FLOW_ITEM_TYPE_UDP:
3156                 retval = sizeof(struct rte_udp_hdr);
3157                 break;
3158         case RTE_FLOW_ITEM_TYPE_TCP:
3159                 retval = sizeof(struct rte_tcp_hdr);
3160                 break;
3161         case RTE_FLOW_ITEM_TYPE_VXLAN:
3162         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3163                 retval = sizeof(struct rte_vxlan_hdr);
3164                 break;
3165         case RTE_FLOW_ITEM_TYPE_GRE:
3166         case RTE_FLOW_ITEM_TYPE_NVGRE:
3167                 retval = sizeof(struct rte_gre_hdr);
3168                 break;
3169         case RTE_FLOW_ITEM_TYPE_MPLS:
3170                 retval = sizeof(struct rte_mpls_hdr);
3171                 break;
3172         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3173         default:
3174                 retval = 0;
3175                 break;
3176         }
3177         return retval;
3178 }
3179
3180 #define MLX5_ENCAP_IPV4_VERSION         0x40
3181 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3182 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3183 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3184 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3185 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3186 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3187
3188 /**
3189  * Convert the encap action data from list of rte_flow_item to raw buffer
3190  *
3191  * @param[in] items
3192  *   Pointer to rte_flow_item objects list.
3193  * @param[out] buf
3194  *   Pointer to the output buffer.
3195  * @param[out] size
3196  *   Pointer to the output buffer size.
3197  * @param[out] error
3198  *   Pointer to the error structure.
3199  *
3200  * @return
3201  *   0 on success, a negative errno value otherwise and rte_errno is set.
3202  */
3203 static int
3204 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3205                            size_t *size, struct rte_flow_error *error)
3206 {
3207         struct rte_ether_hdr *eth = NULL;
3208         struct rte_vlan_hdr *vlan = NULL;
3209         struct rte_ipv4_hdr *ipv4 = NULL;
3210         struct rte_ipv6_hdr *ipv6 = NULL;
3211         struct rte_udp_hdr *udp = NULL;
3212         struct rte_vxlan_hdr *vxlan = NULL;
3213         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3214         struct rte_gre_hdr *gre = NULL;
3215         size_t len;
3216         size_t temp_size = 0;
3217
3218         if (!items)
3219                 return rte_flow_error_set(error, EINVAL,
3220                                           RTE_FLOW_ERROR_TYPE_ACTION,
3221                                           NULL, "invalid empty data");
3222         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3223                 len = flow_dv_get_item_hdr_len(items->type);
3224                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3225                         return rte_flow_error_set(error, EINVAL,
3226                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3227                                                   (void *)items->type,
3228                                                   "items total size is too big"
3229                                                   " for encap action");
3230                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3231                 switch (items->type) {
3232                 case RTE_FLOW_ITEM_TYPE_ETH:
3233                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3234                         break;
3235                 case RTE_FLOW_ITEM_TYPE_VLAN:
3236                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3237                         if (!eth)
3238                                 return rte_flow_error_set(error, EINVAL,
3239                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3240                                                 (void *)items->type,
3241                                                 "eth header not found");
3242                         if (!eth->ether_type)
3243                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3244                         break;
3245                 case RTE_FLOW_ITEM_TYPE_IPV4:
3246                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3247                         if (!vlan && !eth)
3248                                 return rte_flow_error_set(error, EINVAL,
3249                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3250                                                 (void *)items->type,
3251                                                 "neither eth nor vlan"
3252                                                 " header found");
3253                         if (vlan && !vlan->eth_proto)
3254                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3255                         else if (eth && !eth->ether_type)
3256                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3257                         if (!ipv4->version_ihl)
3258                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3259                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3260                         if (!ipv4->time_to_live)
3261                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3262                         break;
3263                 case RTE_FLOW_ITEM_TYPE_IPV6:
3264                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3265                         if (!vlan && !eth)
3266                                 return rte_flow_error_set(error, EINVAL,
3267                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3268                                                 (void *)items->type,
3269                                                 "neither eth nor vlan"
3270                                                 " header found");
3271                         if (vlan && !vlan->eth_proto)
3272                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3273                         else if (eth && !eth->ether_type)
3274                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3275                         if (!ipv6->vtc_flow)
3276                                 ipv6->vtc_flow =
3277                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3278                         if (!ipv6->hop_limits)
3279                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3280                         break;
3281                 case RTE_FLOW_ITEM_TYPE_UDP:
3282                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3283                         if (!ipv4 && !ipv6)
3284                                 return rte_flow_error_set(error, EINVAL,
3285                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3286                                                 (void *)items->type,
3287                                                 "ip header not found");
3288                         if (ipv4 && !ipv4->next_proto_id)
3289                                 ipv4->next_proto_id = IPPROTO_UDP;
3290                         else if (ipv6 && !ipv6->proto)
3291                                 ipv6->proto = IPPROTO_UDP;
3292                         break;
3293                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3294                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3295                         if (!udp)
3296                                 return rte_flow_error_set(error, EINVAL,
3297                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3298                                                 (void *)items->type,
3299                                                 "udp header not found");
3300                         if (!udp->dst_port)
3301                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3302                         if (!vxlan->vx_flags)
3303                                 vxlan->vx_flags =
3304                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3305                         break;
3306                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3307                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3308                         if (!udp)
3309                                 return rte_flow_error_set(error, EINVAL,
3310                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3311                                                 (void *)items->type,
3312                                                 "udp header not found");
3313                         if (!vxlan_gpe->proto)
3314                                 return rte_flow_error_set(error, EINVAL,
3315                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3316                                                 (void *)items->type,
3317                                                 "next protocol not found");
3318                         if (!udp->dst_port)
3319                                 udp->dst_port =
3320                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3321                         if (!vxlan_gpe->vx_flags)
3322                                 vxlan_gpe->vx_flags =
3323                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3324                         break;
3325                 case RTE_FLOW_ITEM_TYPE_GRE:
3326                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3327                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3328                         if (!gre->proto)
3329                                 return rte_flow_error_set(error, EINVAL,
3330                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3331                                                 (void *)items->type,
3332                                                 "next protocol not found");
3333                         if (!ipv4 && !ipv6)
3334                                 return rte_flow_error_set(error, EINVAL,
3335                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3336                                                 (void *)items->type,
3337                                                 "ip header not found");
3338                         if (ipv4 && !ipv4->next_proto_id)
3339                                 ipv4->next_proto_id = IPPROTO_GRE;
3340                         else if (ipv6 && !ipv6->proto)
3341                                 ipv6->proto = IPPROTO_GRE;
3342                         break;
3343                 case RTE_FLOW_ITEM_TYPE_VOID:
3344                         break;
3345                 default:
3346                         return rte_flow_error_set(error, EINVAL,
3347                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3348                                                   (void *)items->type,
3349                                                   "unsupported item type");
3350                         break;
3351                 }
3352                 temp_size += len;
3353         }
3354         *size = temp_size;
3355         return 0;
3356 }
3357
3358 static int
3359 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3360 {
3361         struct rte_ether_hdr *eth = NULL;
3362         struct rte_vlan_hdr *vlan = NULL;
3363         struct rte_ipv6_hdr *ipv6 = NULL;
3364         struct rte_udp_hdr *udp = NULL;
3365         char *next_hdr;
3366         uint16_t proto;
3367
3368         eth = (struct rte_ether_hdr *)data;
3369         next_hdr = (char *)(eth + 1);
3370         proto = RTE_BE16(eth->ether_type);
3371
3372         /* VLAN skipping */
3373         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3374                 vlan = (struct rte_vlan_hdr *)next_hdr;
3375                 proto = RTE_BE16(vlan->eth_proto);
3376                 next_hdr += sizeof(struct rte_vlan_hdr);
3377         }
3378
3379         /* HW calculates IPv4 csum. no need to proceed */
3380         if (proto == RTE_ETHER_TYPE_IPV4)
3381                 return 0;
3382
3383         /* non IPv4/IPv6 header. not supported */
3384         if (proto != RTE_ETHER_TYPE_IPV6) {
3385                 return rte_flow_error_set(error, ENOTSUP,
3386                                           RTE_FLOW_ERROR_TYPE_ACTION,
3387                                           NULL, "Cannot offload non IPv4/IPv6");
3388         }
3389
3390         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3391
3392         /* ignore non UDP */
3393         if (ipv6->proto != IPPROTO_UDP)
3394                 return 0;
3395
3396         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3397         udp->dgram_cksum = 0;
3398
3399         return 0;
3400 }
3401
3402 /**
3403  * Convert L2 encap action to DV specification.
3404  *
3405  * @param[in] dev
3406  *   Pointer to rte_eth_dev structure.
3407  * @param[in] action
3408  *   Pointer to action structure.
3409  * @param[in, out] dev_flow
3410  *   Pointer to the mlx5_flow.
3411  * @param[in] transfer
3412  *   Mark if the flow is E-Switch flow.
3413  * @param[out] error
3414  *   Pointer to the error structure.
3415  *
3416  * @return
3417  *   0 on success, a negative errno value otherwise and rte_errno is set.
3418  */
3419 static int
3420 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3421                                const struct rte_flow_action *action,
3422                                struct mlx5_flow *dev_flow,
3423                                uint8_t transfer,
3424                                struct rte_flow_error *error)
3425 {
3426         const struct rte_flow_item *encap_data;
3427         const struct rte_flow_action_raw_encap *raw_encap_data;
3428         struct mlx5_flow_dv_encap_decap_resource res = {
3429                 .reformat_type =
3430                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3431                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3432                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3433         };
3434
3435         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3436                 raw_encap_data =
3437                         (const struct rte_flow_action_raw_encap *)action->conf;
3438                 res.size = raw_encap_data->size;
3439                 memcpy(res.buf, raw_encap_data->data, res.size);
3440         } else {
3441                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3442                         encap_data =
3443                                 ((const struct rte_flow_action_vxlan_encap *)
3444                                                 action->conf)->definition;
3445                 else
3446                         encap_data =
3447                                 ((const struct rte_flow_action_nvgre_encap *)
3448                                                 action->conf)->definition;
3449                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3450                                                &res.size, error))
3451                         return -rte_errno;
3452         }
3453         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3454                 return -rte_errno;
3455         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3456                 return rte_flow_error_set(error, EINVAL,
3457                                           RTE_FLOW_ERROR_TYPE_ACTION,
3458                                           NULL, "can't create L2 encap action");
3459         return 0;
3460 }
3461
3462 /**
3463  * Convert L2 decap action to DV specification.
3464  *
3465  * @param[in] dev
3466  *   Pointer to rte_eth_dev structure.
3467  * @param[in, out] dev_flow
3468  *   Pointer to the mlx5_flow.
3469  * @param[in] transfer
3470  *   Mark if the flow is E-Switch flow.
3471  * @param[out] error
3472  *   Pointer to the error structure.
3473  *
3474  * @return
3475  *   0 on success, a negative errno value otherwise and rte_errno is set.
3476  */
3477 static int
3478 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3479                                struct mlx5_flow *dev_flow,
3480                                uint8_t transfer,
3481                                struct rte_flow_error *error)
3482 {
3483         struct mlx5_flow_dv_encap_decap_resource res = {
3484                 .size = 0,
3485                 .reformat_type =
3486                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3487                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3488                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3489         };
3490
3491         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3492                 return rte_flow_error_set(error, EINVAL,
3493                                           RTE_FLOW_ERROR_TYPE_ACTION,
3494                                           NULL, "can't create L2 decap action");
3495         return 0;
3496 }
3497
3498 /**
3499  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3500  *
3501  * @param[in] dev
3502  *   Pointer to rte_eth_dev structure.
3503  * @param[in] action
3504  *   Pointer to action structure.
3505  * @param[in, out] dev_flow
3506  *   Pointer to the mlx5_flow.
3507  * @param[in] attr
3508  *   Pointer to the flow attributes.
3509  * @param[out] error
3510  *   Pointer to the error structure.
3511  *
3512  * @return
3513  *   0 on success, a negative errno value otherwise and rte_errno is set.
3514  */
3515 static int
3516 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3517                                 const struct rte_flow_action *action,
3518                                 struct mlx5_flow *dev_flow,
3519                                 const struct rte_flow_attr *attr,
3520                                 struct rte_flow_error *error)
3521 {
3522         const struct rte_flow_action_raw_encap *encap_data;
3523         struct mlx5_flow_dv_encap_decap_resource res;
3524
3525         memset(&res, 0, sizeof(res));
3526         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3527         res.size = encap_data->size;
3528         memcpy(res.buf, encap_data->data, res.size);
3529         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3530                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3531                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3532         if (attr->transfer)
3533                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3534         else
3535                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3536                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3537         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3538                 return rte_flow_error_set(error, EINVAL,
3539                                           RTE_FLOW_ERROR_TYPE_ACTION,
3540                                           NULL, "can't create encap action");
3541         return 0;
3542 }
3543
3544 /**
3545  * Create action push VLAN.
3546  *
3547  * @param[in] dev
3548  *   Pointer to rte_eth_dev structure.
3549  * @param[in] attr
3550  *   Pointer to the flow attributes.
3551  * @param[in] vlan
3552  *   Pointer to the vlan to push to the Ethernet header.
3553  * @param[in, out] dev_flow
3554  *   Pointer to the mlx5_flow.
3555  * @param[out] error
3556  *   Pointer to the error structure.
3557  *
3558  * @return
3559  *   0 on success, a negative errno value otherwise and rte_errno is set.
3560  */
3561 static int
3562 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3563                                 const struct rte_flow_attr *attr,
3564                                 const struct rte_vlan_hdr *vlan,
3565                                 struct mlx5_flow *dev_flow,
3566                                 struct rte_flow_error *error)
3567 {
3568         struct mlx5_flow_dv_push_vlan_action_resource res;
3569
3570         memset(&res, 0, sizeof(res));
3571         res.vlan_tag =
3572                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3573                                  vlan->vlan_tci);
3574         if (attr->transfer)
3575                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3576         else
3577                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3578                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3579         return flow_dv_push_vlan_action_resource_register
3580                                             (dev, &res, dev_flow, error);
3581 }
3582
3583 static int fdb_mirror;
3584
3585 /**
3586  * Validate the modify-header actions.
3587  *
3588  * @param[in] action_flags
3589  *   Holds the actions detected until now.
3590  * @param[in] action
3591  *   Pointer to the modify action.
3592  * @param[out] error
3593  *   Pointer to error structure.
3594  *
3595  * @return
3596  *   0 on success, a negative errno value otherwise and rte_errno is set.
3597  */
3598 static int
3599 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3600                                    const struct rte_flow_action *action,
3601                                    struct rte_flow_error *error)
3602 {
3603         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3604                 return rte_flow_error_set(error, EINVAL,
3605                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3606                                           NULL, "action configuration not set");
3607         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3608                 return rte_flow_error_set(error, EINVAL,
3609                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3610                                           "can't have encap action before"
3611                                           " modify action");
3612         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3613                 return rte_flow_error_set(error, EINVAL,
3614                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3615                                           "can't support sample action before"
3616                                           " modify action for E-Switch"
3617                                           " mirroring");
3618         return 0;
3619 }
3620
3621 /**
3622  * Validate the modify-header MAC address actions.
3623  *
3624  * @param[in] action_flags
3625  *   Holds the actions detected until now.
3626  * @param[in] action
3627  *   Pointer to the modify action.
3628  * @param[in] item_flags
3629  *   Holds the items detected.
3630  * @param[out] error
3631  *   Pointer to error structure.
3632  *
3633  * @return
3634  *   0 on success, a negative errno value otherwise and rte_errno is set.
3635  */
3636 static int
3637 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3638                                    const struct rte_flow_action *action,
3639                                    const uint64_t item_flags,
3640                                    struct rte_flow_error *error)
3641 {
3642         int ret = 0;
3643
3644         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3645         if (!ret) {
3646                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3647                         return rte_flow_error_set(error, EINVAL,
3648                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3649                                                   NULL,
3650                                                   "no L2 item in pattern");
3651         }
3652         return ret;
3653 }
3654
3655 /**
3656  * Validate the modify-header IPv4 address actions.
3657  *
3658  * @param[in] action_flags
3659  *   Holds the actions detected until now.
3660  * @param[in] action
3661  *   Pointer to the modify action.
3662  * @param[in] item_flags
3663  *   Holds the items detected.
3664  * @param[out] error
3665  *   Pointer to error structure.
3666  *
3667  * @return
3668  *   0 on success, a negative errno value otherwise and rte_errno is set.
3669  */
3670 static int
3671 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3672                                     const struct rte_flow_action *action,
3673                                     const uint64_t item_flags,
3674                                     struct rte_flow_error *error)
3675 {
3676         int ret = 0;
3677         uint64_t layer;
3678
3679         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3680         if (!ret) {
3681                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3682                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3683                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3684                 if (!(item_flags & layer))
3685                         return rte_flow_error_set(error, EINVAL,
3686                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3687                                                   NULL,
3688                                                   "no ipv4 item in pattern");
3689         }
3690         return ret;
3691 }
3692
3693 /**
3694  * Validate the modify-header IPv6 address actions.
3695  *
3696  * @param[in] action_flags
3697  *   Holds the actions detected until now.
3698  * @param[in] action
3699  *   Pointer to the modify action.
3700  * @param[in] item_flags
3701  *   Holds the items detected.
3702  * @param[out] error
3703  *   Pointer to error structure.
3704  *
3705  * @return
3706  *   0 on success, a negative errno value otherwise and rte_errno is set.
3707  */
3708 static int
3709 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3710                                     const struct rte_flow_action *action,
3711                                     const uint64_t item_flags,
3712                                     struct rte_flow_error *error)
3713 {
3714         int ret = 0;
3715         uint64_t layer;
3716
3717         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3718         if (!ret) {
3719                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3720                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3721                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3722                 if (!(item_flags & layer))
3723                         return rte_flow_error_set(error, EINVAL,
3724                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3725                                                   NULL,
3726                                                   "no ipv6 item in pattern");
3727         }
3728         return ret;
3729 }
3730
3731 /**
3732  * Validate the modify-header TP actions.
3733  *
3734  * @param[in] action_flags
3735  *   Holds the actions detected until now.
3736  * @param[in] action
3737  *   Pointer to the modify action.
3738  * @param[in] item_flags
3739  *   Holds the items detected.
3740  * @param[out] error
3741  *   Pointer to error structure.
3742  *
3743  * @return
3744  *   0 on success, a negative errno value otherwise and rte_errno is set.
3745  */
3746 static int
3747 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3748                                   const struct rte_flow_action *action,
3749                                   const uint64_t item_flags,
3750                                   struct rte_flow_error *error)
3751 {
3752         int ret = 0;
3753         uint64_t layer;
3754
3755         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3756         if (!ret) {
3757                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3758                                  MLX5_FLOW_LAYER_INNER_L4 :
3759                                  MLX5_FLOW_LAYER_OUTER_L4;
3760                 if (!(item_flags & layer))
3761                         return rte_flow_error_set(error, EINVAL,
3762                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3763                                                   NULL, "no transport layer "
3764                                                   "in pattern");
3765         }
3766         return ret;
3767 }
3768
3769 /**
3770  * Validate the modify-header actions of increment/decrement
3771  * TCP Sequence-number.
3772  *
3773  * @param[in] action_flags
3774  *   Holds the actions detected until now.
3775  * @param[in] action
3776  *   Pointer to the modify action.
3777  * @param[in] item_flags
3778  *   Holds the items detected.
3779  * @param[out] error
3780  *   Pointer to error structure.
3781  *
3782  * @return
3783  *   0 on success, a negative errno value otherwise and rte_errno is set.
3784  */
3785 static int
3786 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3787                                        const struct rte_flow_action *action,
3788                                        const uint64_t item_flags,
3789                                        struct rte_flow_error *error)
3790 {
3791         int ret = 0;
3792         uint64_t layer;
3793
3794         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3795         if (!ret) {
3796                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3797                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3798                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3799                 if (!(item_flags & layer))
3800                         return rte_flow_error_set(error, EINVAL,
3801                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3802                                                   NULL, "no TCP item in"
3803                                                   " pattern");
3804                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3805                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3806                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3807                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3808                         return rte_flow_error_set(error, EINVAL,
3809                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3810                                                   NULL,
3811                                                   "cannot decrease and increase"
3812                                                   " TCP sequence number"
3813                                                   " at the same time");
3814         }
3815         return ret;
3816 }
3817
3818 /**
3819  * Validate the modify-header actions of increment/decrement
3820  * TCP Acknowledgment number.
3821  *
3822  * @param[in] action_flags
3823  *   Holds the actions detected until now.
3824  * @param[in] action
3825  *   Pointer to the modify action.
3826  * @param[in] item_flags
3827  *   Holds the items detected.
3828  * @param[out] error
3829  *   Pointer to error structure.
3830  *
3831  * @return
3832  *   0 on success, a negative errno value otherwise and rte_errno is set.
3833  */
3834 static int
3835 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3836                                        const struct rte_flow_action *action,
3837                                        const uint64_t item_flags,
3838                                        struct rte_flow_error *error)
3839 {
3840         int ret = 0;
3841         uint64_t layer;
3842
3843         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3844         if (!ret) {
3845                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3846                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3847                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3848                 if (!(item_flags & layer))
3849                         return rte_flow_error_set(error, EINVAL,
3850                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3851                                                   NULL, "no TCP item in"
3852                                                   " pattern");
3853                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3854                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3855                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3856                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3857                         return rte_flow_error_set(error, EINVAL,
3858                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3859                                                   NULL,
3860                                                   "cannot decrease and increase"
3861                                                   " TCP acknowledgment number"
3862                                                   " at the same time");
3863         }
3864         return ret;
3865 }
3866
3867 /**
3868  * Validate the modify-header TTL actions.
3869  *
3870  * @param[in] action_flags
3871  *   Holds the actions detected until now.
3872  * @param[in] action
3873  *   Pointer to the modify action.
3874  * @param[in] item_flags
3875  *   Holds the items detected.
3876  * @param[out] error
3877  *   Pointer to error structure.
3878  *
3879  * @return
3880  *   0 on success, a negative errno value otherwise and rte_errno is set.
3881  */
3882 static int
3883 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3884                                    const struct rte_flow_action *action,
3885                                    const uint64_t item_flags,
3886                                    struct rte_flow_error *error)
3887 {
3888         int ret = 0;
3889         uint64_t layer;
3890
3891         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3892         if (!ret) {
3893                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3894                                  MLX5_FLOW_LAYER_INNER_L3 :
3895                                  MLX5_FLOW_LAYER_OUTER_L3;
3896                 if (!(item_flags & layer))
3897                         return rte_flow_error_set(error, EINVAL,
3898                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3899                                                   NULL,
3900                                                   "no IP protocol in pattern");
3901         }
3902         return ret;
3903 }
3904
3905 /**
3906  * Validate jump action.
3907  *
3908  * @param[in] action
3909  *   Pointer to the jump action.
3910  * @param[in] action_flags
3911  *   Holds the actions detected until now.
3912  * @param[in] attributes
3913  *   Pointer to flow attributes
3914  * @param[in] external
3915  *   Action belongs to flow rule created by request external to PMD.
3916  * @param[out] error
3917  *   Pointer to error structure.
3918  *
3919  * @return
3920  *   0 on success, a negative errno value otherwise and rte_errno is set.
3921  */
3922 static int
3923 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3924                              const struct mlx5_flow_tunnel *tunnel,
3925                              const struct rte_flow_action *action,
3926                              uint64_t action_flags,
3927                              const struct rte_flow_attr *attributes,
3928                              bool external, struct rte_flow_error *error)
3929 {
3930         uint32_t target_group, table;
3931         int ret = 0;
3932         struct flow_grp_info grp_info = {
3933                 .external = !!external,
3934                 .transfer = !!attributes->transfer,
3935                 .fdb_def_rule = 1,
3936                 .std_tbl_fix = 0
3937         };
3938         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3939                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3940                 return rte_flow_error_set(error, EINVAL,
3941                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3942                                           "can't have 2 fate actions in"
3943                                           " same flow");
3944         if (action_flags & MLX5_FLOW_ACTION_METER)
3945                 return rte_flow_error_set(error, ENOTSUP,
3946                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3947                                           "jump with meter not support");
3948         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3949                 return rte_flow_error_set(error, EINVAL,
3950                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3951                                           "E-Switch mirroring can't support"
3952                                           " Sample action and jump action in"
3953                                           " same flow now");
3954         if (!action->conf)
3955                 return rte_flow_error_set(error, EINVAL,
3956                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3957                                           NULL, "action configuration not set");
3958         target_group =
3959                 ((const struct rte_flow_action_jump *)action->conf)->group;
3960         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3961                                        &grp_info, error);
3962         if (ret)
3963                 return ret;
3964         if (attributes->group == target_group &&
3965             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3966                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3967                 return rte_flow_error_set(error, EINVAL,
3968                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3969                                           "target group must be other than"
3970                                           " the current flow group");
3971         return 0;
3972 }
3973
3974 /*
3975  * Validate the port_id action.
3976  *
3977  * @param[in] dev
3978  *   Pointer to rte_eth_dev structure.
3979  * @param[in] action_flags
3980  *   Bit-fields that holds the actions detected until now.
3981  * @param[in] action
3982  *   Port_id RTE action structure.
3983  * @param[in] attr
3984  *   Attributes of flow that includes this action.
3985  * @param[out] error
3986  *   Pointer to error structure.
3987  *
3988  * @return
3989  *   0 on success, a negative errno value otherwise and rte_errno is set.
3990  */
3991 static int
3992 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3993                                 uint64_t action_flags,
3994                                 const struct rte_flow_action *action,
3995                                 const struct rte_flow_attr *attr,
3996                                 struct rte_flow_error *error)
3997 {
3998         const struct rte_flow_action_port_id *port_id;
3999         struct mlx5_priv *act_priv;
4000         struct mlx5_priv *dev_priv;
4001         uint16_t port;
4002
4003         if (!attr->transfer)
4004                 return rte_flow_error_set(error, ENOTSUP,
4005                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4006                                           NULL,
4007                                           "port id action is valid in transfer"
4008                                           " mode only");
4009         if (!action || !action->conf)
4010                 return rte_flow_error_set(error, ENOTSUP,
4011                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4012                                           NULL,
4013                                           "port id action parameters must be"
4014                                           " specified");
4015         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4016                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4017                 return rte_flow_error_set(error, EINVAL,
4018                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4019                                           "can have only one fate actions in"
4020                                           " a flow");
4021         dev_priv = mlx5_dev_to_eswitch_info(dev);
4022         if (!dev_priv)
4023                 return rte_flow_error_set(error, rte_errno,
4024                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4025                                           NULL,
4026                                           "failed to obtain E-Switch info");
4027         port_id = action->conf;
4028         port = port_id->original ? dev->data->port_id : port_id->id;
4029         act_priv = mlx5_port_to_eswitch_info(port, false);
4030         if (!act_priv)
4031                 return rte_flow_error_set
4032                                 (error, rte_errno,
4033                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4034                                  "failed to obtain E-Switch port id for port");
4035         if (act_priv->domain_id != dev_priv->domain_id)
4036                 return rte_flow_error_set
4037                                 (error, EINVAL,
4038                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4039                                  "port does not belong to"
4040                                  " E-Switch being configured");
4041         return 0;
4042 }
4043
4044 /**
4045  * Get the maximum number of modify header actions.
4046  *
4047  * @param dev
4048  *   Pointer to rte_eth_dev structure.
4049  * @param flags
4050  *   Flags bits to check if root level.
4051  *
4052  * @return
4053  *   Max number of modify header actions device can support.
4054  */
4055 static inline unsigned int
4056 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4057                               uint64_t flags)
4058 {
4059         /*
4060          * There's no way to directly query the max capacity from FW.
4061          * The maximal value on root table should be assumed to be supported.
4062          */
4063         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4064                 return MLX5_MAX_MODIFY_NUM;
4065         else
4066                 return MLX5_ROOT_TBL_MODIFY_NUM;
4067 }
4068
4069 /**
4070  * Validate the meter action.
4071  *
4072  * @param[in] dev
4073  *   Pointer to rte_eth_dev structure.
4074  * @param[in] action_flags
4075  *   Bit-fields that holds the actions detected until now.
4076  * @param[in] action
4077  *   Pointer to the meter action.
4078  * @param[in] attr
4079  *   Attributes of flow that includes this action.
4080  * @param[out] error
4081  *   Pointer to error structure.
4082  *
4083  * @return
4084  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4085  */
4086 static int
4087 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4088                                 uint64_t action_flags,
4089                                 const struct rte_flow_action *action,
4090                                 const struct rte_flow_attr *attr,
4091                                 struct rte_flow_error *error)
4092 {
4093         struct mlx5_priv *priv = dev->data->dev_private;
4094         const struct rte_flow_action_meter *am = action->conf;
4095         struct mlx5_flow_meter *fm;
4096
4097         if (!am)
4098                 return rte_flow_error_set(error, EINVAL,
4099                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4100                                           "meter action conf is NULL");
4101
4102         if (action_flags & MLX5_FLOW_ACTION_METER)
4103                 return rte_flow_error_set(error, ENOTSUP,
4104                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4105                                           "meter chaining not support");
4106         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4107                 return rte_flow_error_set(error, ENOTSUP,
4108                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4109                                           "meter with jump not support");
4110         if (!priv->mtr_en)
4111                 return rte_flow_error_set(error, ENOTSUP,
4112                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4113                                           NULL,
4114                                           "meter action not supported");
4115         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4116         if (!fm)
4117                 return rte_flow_error_set(error, EINVAL,
4118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4119                                           "Meter not found");
4120         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4121               (!fm->ingress && !attr->ingress && attr->egress) ||
4122               (!fm->egress && !attr->egress && attr->ingress))))
4123                 return rte_flow_error_set(error, EINVAL,
4124                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4125                                           "Flow attributes are either invalid "
4126                                           "or have a conflict with current "
4127                                           "meter attributes");
4128         return 0;
4129 }
4130
4131 /**
4132  * Validate the age action.
4133  *
4134  * @param[in] action_flags
4135  *   Holds the actions detected until now.
4136  * @param[in] action
4137  *   Pointer to the age action.
4138  * @param[in] dev
4139  *   Pointer to the Ethernet device structure.
4140  * @param[out] error
4141  *   Pointer to error structure.
4142  *
4143  * @return
4144  *   0 on success, a negative errno value otherwise and rte_errno is set.
4145  */
4146 static int
4147 flow_dv_validate_action_age(uint64_t action_flags,
4148                             const struct rte_flow_action *action,
4149                             struct rte_eth_dev *dev,
4150                             struct rte_flow_error *error)
4151 {
4152         struct mlx5_priv *priv = dev->data->dev_private;
4153         const struct rte_flow_action_age *age = action->conf;
4154
4155         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4156             !priv->sh->aso_age_mng))
4157                 return rte_flow_error_set(error, ENOTSUP,
4158                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4159                                           NULL,
4160                                           "age action not supported");
4161         if (!(action->conf))
4162                 return rte_flow_error_set(error, EINVAL,
4163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4164                                           "configuration cannot be null");
4165         if (!(age->timeout))
4166                 return rte_flow_error_set(error, EINVAL,
4167                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4168                                           "invalid timeout value 0");
4169         if (action_flags & MLX5_FLOW_ACTION_AGE)
4170                 return rte_flow_error_set(error, EINVAL,
4171                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4172                                           "duplicate age actions set");
4173         return 0;
4174 }
4175
4176 /**
4177  * Validate the modify-header IPv4 DSCP actions.
4178  *
4179  * @param[in] action_flags
4180  *   Holds the actions detected until now.
4181  * @param[in] action
4182  *   Pointer to the modify action.
4183  * @param[in] item_flags
4184  *   Holds the items detected.
4185  * @param[out] error
4186  *   Pointer to error structure.
4187  *
4188  * @return
4189  *   0 on success, a negative errno value otherwise and rte_errno is set.
4190  */
4191 static int
4192 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4193                                          const struct rte_flow_action *action,
4194                                          const uint64_t item_flags,
4195                                          struct rte_flow_error *error)
4196 {
4197         int ret = 0;
4198
4199         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4200         if (!ret) {
4201                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4202                         return rte_flow_error_set(error, EINVAL,
4203                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4204                                                   NULL,
4205                                                   "no ipv4 item in pattern");
4206         }
4207         return ret;
4208 }
4209
4210 /**
4211  * Validate the modify-header IPv6 DSCP actions.
4212  *
4213  * @param[in] action_flags
4214  *   Holds the actions detected until now.
4215  * @param[in] action
4216  *   Pointer to the modify action.
4217  * @param[in] item_flags
4218  *   Holds the items detected.
4219  * @param[out] error
4220  *   Pointer to error structure.
4221  *
4222  * @return
4223  *   0 on success, a negative errno value otherwise and rte_errno is set.
4224  */
4225 static int
4226 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4227                                          const struct rte_flow_action *action,
4228                                          const uint64_t item_flags,
4229                                          struct rte_flow_error *error)
4230 {
4231         int ret = 0;
4232
4233         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4234         if (!ret) {
4235                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4236                         return rte_flow_error_set(error, EINVAL,
4237                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4238                                                   NULL,
4239                                                   "no ipv6 item in pattern");
4240         }
4241         return ret;
4242 }
4243
4244 /**
4245  * Match modify-header resource.
4246  *
4247  * @param list
4248  *   Pointer to the hash list.
4249  * @param entry
4250  *   Pointer to exist resource entry object.
4251  * @param key
4252  *   Key of the new entry.
4253  * @param ctx
4254  *   Pointer to new modify-header resource.
4255  *
4256  * @return
4257  *   0 on matching, non-zero otherwise.
4258  */
4259 int
4260 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4261                         struct mlx5_hlist_entry *entry,
4262                         uint64_t key __rte_unused, void *cb_ctx)
4263 {
4264         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4265         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4266         struct mlx5_flow_dv_modify_hdr_resource *resource =
4267                         container_of(entry, typeof(*resource), entry);
4268         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4269
4270         key_len += ref->actions_num * sizeof(ref->actions[0]);
4271         return ref->actions_num != resource->actions_num ||
4272                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4273 }
4274
4275 struct mlx5_hlist_entry *
4276 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4277                          void *cb_ctx)
4278 {
4279         struct mlx5_dev_ctx_shared *sh = list->ctx;
4280         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4281         struct mlx5dv_dr_domain *ns;
4282         struct mlx5_flow_dv_modify_hdr_resource *entry;
4283         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4284         int ret;
4285         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4286         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4287
4288         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4289                             SOCKET_ID_ANY);
4290         if (!entry) {
4291                 rte_flow_error_set(ctx->error, ENOMEM,
4292                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4293                                    "cannot allocate resource memory");
4294                 return NULL;
4295         }
4296         rte_memcpy(&entry->ft_type,
4297                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4298                    key_len + data_len);
4299         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4300                 ns = sh->fdb_domain;
4301         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4302                 ns = sh->tx_domain;
4303         else
4304                 ns = sh->rx_domain;
4305         ret = mlx5_flow_os_create_flow_action_modify_header
4306                                         (sh->ctx, ns, entry,
4307                                          data_len, &entry->action);
4308         if (ret) {
4309                 mlx5_free(entry);
4310                 rte_flow_error_set(ctx->error, ENOMEM,
4311                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4312                                    NULL, "cannot create modification action");
4313                 return NULL;
4314         }
4315         return &entry->entry;
4316 }
4317
4318 /**
4319  * Validate the sample action.
4320  *
4321  * @param[in] action_flags
4322  *   Holds the actions detected until now.
4323  * @param[in] action
4324  *   Pointer to the sample action.
4325  * @param[in] dev
4326  *   Pointer to the Ethernet device structure.
4327  * @param[in] attr
4328  *   Attributes of flow that includes this action.
4329  * @param[out] error
4330  *   Pointer to error structure.
4331  *
4332  * @return
4333  *   0 on success, a negative errno value otherwise and rte_errno is set.
4334  */
4335 static int
4336 flow_dv_validate_action_sample(uint64_t action_flags,
4337                                const struct rte_flow_action *action,
4338                                struct rte_eth_dev *dev,
4339                                const struct rte_flow_attr *attr,
4340                                struct rte_flow_error *error)
4341 {
4342         struct mlx5_priv *priv = dev->data->dev_private;
4343         struct mlx5_dev_config *dev_conf = &priv->config;
4344         const struct rte_flow_action_sample *sample = action->conf;
4345         const struct rte_flow_action *act;
4346         uint64_t sub_action_flags = 0;
4347         uint16_t queue_index = 0xFFFF;
4348         int actions_n = 0;
4349         int ret;
4350         fdb_mirror = 0;
4351
4352         if (!sample)
4353                 return rte_flow_error_set(error, EINVAL,
4354                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4355                                           "configuration cannot be NULL");
4356         if (sample->ratio == 0)
4357                 return rte_flow_error_set(error, EINVAL,
4358                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4359                                           "ratio value starts from 1");
4360         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4361                 return rte_flow_error_set(error, ENOTSUP,
4362                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4363                                           NULL,
4364                                           "sample action not supported");
4365         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4366                 return rte_flow_error_set(error, EINVAL,
4367                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4368                                           "Multiple sample actions not "
4369                                           "supported");
4370         if (action_flags & MLX5_FLOW_ACTION_METER)
4371                 return rte_flow_error_set(error, EINVAL,
4372                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4373                                           "wrong action order, meter should "
4374                                           "be after sample action");
4375         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4376                 return rte_flow_error_set(error, EINVAL,
4377                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4378                                           "wrong action order, jump should "
4379                                           "be after sample action");
4380         act = sample->actions;
4381         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4382                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4383                         return rte_flow_error_set(error, ENOTSUP,
4384                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4385                                                   act, "too many actions");
4386                 switch (act->type) {
4387                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4388                         ret = mlx5_flow_validate_action_queue(act,
4389                                                               sub_action_flags,
4390                                                               dev,
4391                                                               attr, error);
4392                         if (ret < 0)
4393                                 return ret;
4394                         queue_index = ((const struct rte_flow_action_queue *)
4395                                                         (act->conf))->index;
4396                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4397                         ++actions_n;
4398                         break;
4399                 case RTE_FLOW_ACTION_TYPE_MARK:
4400                         ret = flow_dv_validate_action_mark(dev, act,
4401                                                            sub_action_flags,
4402                                                            attr, error);
4403                         if (ret < 0)
4404                                 return ret;
4405                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4406                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4407                                                 MLX5_FLOW_ACTION_MARK_EXT;
4408                         else
4409                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4410                         ++actions_n;
4411                         break;
4412                 case RTE_FLOW_ACTION_TYPE_COUNT:
4413                         ret = flow_dv_validate_action_count(dev, error);
4414                         if (ret < 0)
4415                                 return ret;
4416                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4417                         ++actions_n;
4418                         break;
4419                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4420                         ret = flow_dv_validate_action_port_id(dev,
4421                                                               sub_action_flags,
4422                                                               act,
4423                                                               attr,
4424                                                               error);
4425                         if (ret)
4426                                 return ret;
4427                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4428                         ++actions_n;
4429                         break;
4430                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4431                         ret = flow_dv_validate_action_raw_encap_decap
4432                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4433                                  &actions_n, error);
4434                         if (ret < 0)
4435                                 return ret;
4436                         ++actions_n;
4437                         break;
4438                 default:
4439                         return rte_flow_error_set(error, ENOTSUP,
4440                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4441                                                   NULL,
4442                                                   "Doesn't support optional "
4443                                                   "action");
4444                 }
4445         }
4446         if (attr->ingress && !attr->transfer) {
4447                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4448                         return rte_flow_error_set(error, EINVAL,
4449                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4450                                                   NULL,
4451                                                   "Ingress must has a dest "
4452                                                   "QUEUE for Sample");
4453         } else if (attr->egress && !attr->transfer) {
4454                 return rte_flow_error_set(error, ENOTSUP,
4455                                           RTE_FLOW_ERROR_TYPE_ACTION,
4456                                           NULL,
4457                                           "Sample Only support Ingress "
4458                                           "or E-Switch");
4459         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4460                 MLX5_ASSERT(attr->transfer);
4461                 if (sample->ratio > 1)
4462                         return rte_flow_error_set(error, ENOTSUP,
4463                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4464                                                   NULL,
4465                                                   "E-Switch doesn't support "
4466                                                   "any optional action "
4467                                                   "for sampling");
4468                 fdb_mirror = 1;
4469                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4470                         return rte_flow_error_set(error, ENOTSUP,
4471                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4472                                                   NULL,
4473                                                   "unsupported action QUEUE");
4474                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4475                         return rte_flow_error_set(error, EINVAL,
4476                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4477                                                   NULL,
4478                                                   "E-Switch must has a dest "
4479                                                   "port for mirroring");
4480         }
4481         /* Continue validation for Xcap actions.*/
4482         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4483             (queue_index == 0xFFFF ||
4484              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4485                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4486                      MLX5_FLOW_XCAP_ACTIONS)
4487                         return rte_flow_error_set(error, ENOTSUP,
4488                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4489                                                   NULL, "encap and decap "
4490                                                   "combination aren't "
4491                                                   "supported");
4492                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4493                                                         MLX5_FLOW_ACTION_ENCAP))
4494                         return rte_flow_error_set(error, ENOTSUP,
4495                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4496                                                   NULL, "encap is not supported"
4497                                                   " for ingress traffic");
4498         }
4499         return 0;
4500 }
4501
4502 /**
4503  * Find existing modify-header resource or create and register a new one.
4504  *
4505  * @param dev[in, out]
4506  *   Pointer to rte_eth_dev structure.
4507  * @param[in, out] resource
4508  *   Pointer to modify-header resource.
4509  * @parm[in, out] dev_flow
4510  *   Pointer to the dev_flow.
4511  * @param[out] error
4512  *   pointer to error structure.
4513  *
4514  * @return
4515  *   0 on success otherwise -errno and errno is set.
4516  */
4517 static int
4518 flow_dv_modify_hdr_resource_register
4519                         (struct rte_eth_dev *dev,
4520                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4521                          struct mlx5_flow *dev_flow,
4522                          struct rte_flow_error *error)
4523 {
4524         struct mlx5_priv *priv = dev->data->dev_private;
4525         struct mlx5_dev_ctx_shared *sh = priv->sh;
4526         uint32_t key_len = sizeof(*resource) -
4527                            offsetof(typeof(*resource), ft_type) +
4528                            resource->actions_num * sizeof(resource->actions[0]);
4529         struct mlx5_hlist_entry *entry;
4530         struct mlx5_flow_cb_ctx ctx = {
4531                 .error = error,
4532                 .data = resource,
4533         };
4534         uint64_t key64;
4535
4536         resource->flags = dev_flow->dv.group ? 0 :
4537                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4538         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4539                                     resource->flags))
4540                 return rte_flow_error_set(error, EOVERFLOW,
4541                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4542                                           "too many modify header items");
4543         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4544         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4545         if (!entry)
4546                 return -rte_errno;
4547         resource = container_of(entry, typeof(*resource), entry);
4548         dev_flow->handle->dvh.modify_hdr = resource;
4549         return 0;
4550 }
4551
4552 /**
4553  * Get DV flow counter by index.
4554  *
4555  * @param[in] dev
4556  *   Pointer to the Ethernet device structure.
4557  * @param[in] idx
4558  *   mlx5 flow counter index in the container.
4559  * @param[out] ppool
4560  *   mlx5 flow counter pool in the container,
4561  *
4562  * @return
4563  *   Pointer to the counter, NULL otherwise.
4564  */
4565 static struct mlx5_flow_counter *
4566 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4567                            uint32_t idx,
4568                            struct mlx5_flow_counter_pool **ppool)
4569 {
4570         struct mlx5_priv *priv = dev->data->dev_private;
4571         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4572         struct mlx5_flow_counter_pool *pool;
4573
4574         /* Decrease to original index and clear shared bit. */
4575         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4576         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4577         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4578         MLX5_ASSERT(pool);
4579         if (ppool)
4580                 *ppool = pool;
4581         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4582 }
4583
4584 /**
4585  * Check the devx counter belongs to the pool.
4586  *
4587  * @param[in] pool
4588  *   Pointer to the counter pool.
4589  * @param[in] id
4590  *   The counter devx ID.
4591  *
4592  * @return
4593  *   True if counter belongs to the pool, false otherwise.
4594  */
4595 static bool
4596 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4597 {
4598         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4599                    MLX5_COUNTERS_PER_POOL;
4600
4601         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4602                 return true;
4603         return false;
4604 }
4605
4606 /**
4607  * Get a pool by devx counter ID.
4608  *
4609  * @param[in] cmng
4610  *   Pointer to the counter management.
4611  * @param[in] id
4612  *   The counter devx ID.
4613  *
4614  * @return
4615  *   The counter pool pointer if exists, NULL otherwise,
4616  */
4617 static struct mlx5_flow_counter_pool *
4618 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4619 {
4620         uint32_t i;
4621         struct mlx5_flow_counter_pool *pool = NULL;
4622
4623         rte_spinlock_lock(&cmng->pool_update_sl);
4624         /* Check last used pool. */
4625         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4626             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4627                 pool = cmng->pools[cmng->last_pool_idx];
4628                 goto out;
4629         }
4630         /* ID out of range means no suitable pool in the container. */
4631         if (id > cmng->max_id || id < cmng->min_id)
4632                 goto out;
4633         /*
4634          * Find the pool from the end of the container, since mostly counter
4635          * ID is sequence increasing, and the last pool should be the needed
4636          * one.
4637          */
4638         i = cmng->n_valid;
4639         while (i--) {
4640                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4641
4642                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4643                         pool = pool_tmp;
4644                         break;
4645                 }
4646         }
4647 out:
4648         rte_spinlock_unlock(&cmng->pool_update_sl);
4649         return pool;
4650 }
4651
4652 /**
4653  * Resize a counter container.
4654  *
4655  * @param[in] dev
4656  *   Pointer to the Ethernet device structure.
4657  *
4658  * @return
4659  *   0 on success, otherwise negative errno value and rte_errno is set.
4660  */
4661 static int
4662 flow_dv_container_resize(struct rte_eth_dev *dev)
4663 {
4664         struct mlx5_priv *priv = dev->data->dev_private;
4665         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4666         void *old_pools = cmng->pools;
4667         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4668         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4669         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4670
4671         if (!pools) {
4672                 rte_errno = ENOMEM;
4673                 return -ENOMEM;
4674         }
4675         if (old_pools)
4676                 memcpy(pools, old_pools, cmng->n *
4677                                        sizeof(struct mlx5_flow_counter_pool *));
4678         cmng->n = resize;
4679         cmng->pools = pools;
4680         if (old_pools)
4681                 mlx5_free(old_pools);
4682         return 0;
4683 }
4684
4685 /**
4686  * Query a devx flow counter.
4687  *
4688  * @param[in] dev
4689  *   Pointer to the Ethernet device structure.
4690  * @param[in] cnt
4691  *   Index to the flow counter.
4692  * @param[out] pkts
4693  *   The statistics value of packets.
4694  * @param[out] bytes
4695  *   The statistics value of bytes.
4696  *
4697  * @return
4698  *   0 on success, otherwise a negative errno value and rte_errno is set.
4699  */
4700 static inline int
4701 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4702                      uint64_t *bytes)
4703 {
4704         struct mlx5_priv *priv = dev->data->dev_private;
4705         struct mlx5_flow_counter_pool *pool = NULL;
4706         struct mlx5_flow_counter *cnt;
4707         int offset;
4708
4709         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4710         MLX5_ASSERT(pool);
4711         if (priv->sh->cmng.counter_fallback)
4712                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4713                                         0, pkts, bytes, 0, NULL, NULL, 0);
4714         rte_spinlock_lock(&pool->sl);
4715         if (!pool->raw) {
4716                 *pkts = 0;
4717                 *bytes = 0;
4718         } else {
4719                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4720                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4721                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4722         }
4723         rte_spinlock_unlock(&pool->sl);
4724         return 0;
4725 }
4726
4727 /**
4728  * Create and initialize a new counter pool.
4729  *
4730  * @param[in] dev
4731  *   Pointer to the Ethernet device structure.
4732  * @param[out] dcs
4733  *   The devX counter handle.
4734  * @param[in] age
4735  *   Whether the pool is for counter that was allocated for aging.
4736  * @param[in/out] cont_cur
4737  *   Pointer to the container pointer, it will be update in pool resize.
4738  *
4739  * @return
4740  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4741  */
4742 static struct mlx5_flow_counter_pool *
4743 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4744                     uint32_t age)
4745 {
4746         struct mlx5_priv *priv = dev->data->dev_private;
4747         struct mlx5_flow_counter_pool *pool;
4748         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4749         bool fallback = priv->sh->cmng.counter_fallback;
4750         uint32_t size = sizeof(*pool);
4751
4752         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4753         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4754         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4755         if (!pool) {
4756                 rte_errno = ENOMEM;
4757                 return NULL;
4758         }
4759         pool->raw = NULL;
4760         pool->is_aged = !!age;
4761         pool->query_gen = 0;
4762         pool->min_dcs = dcs;
4763         rte_spinlock_init(&pool->sl);
4764         rte_spinlock_init(&pool->csl);
4765         TAILQ_INIT(&pool->counters[0]);
4766         TAILQ_INIT(&pool->counters[1]);
4767         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4768         rte_spinlock_lock(&cmng->pool_update_sl);
4769         pool->index = cmng->n_valid;
4770         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4771                 mlx5_free(pool);
4772                 rte_spinlock_unlock(&cmng->pool_update_sl);
4773                 return NULL;
4774         }
4775         cmng->pools[pool->index] = pool;
4776         cmng->n_valid++;
4777         if (unlikely(fallback)) {
4778                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4779
4780                 if (base < cmng->min_id)
4781                         cmng->min_id = base;
4782                 if (base > cmng->max_id)
4783                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4784                 cmng->last_pool_idx = pool->index;
4785         }
4786         rte_spinlock_unlock(&cmng->pool_update_sl);
4787         return pool;
4788 }
4789
4790 /**
4791  * Prepare a new counter and/or a new counter pool.
4792  *
4793  * @param[in] dev
4794  *   Pointer to the Ethernet device structure.
4795  * @param[out] cnt_free
4796  *   Where to put the pointer of a new counter.
4797  * @param[in] age
4798  *   Whether the pool is for counter that was allocated for aging.
4799  *
4800  * @return
4801  *   The counter pool pointer and @p cnt_free is set on success,
4802  *   NULL otherwise and rte_errno is set.
4803  */
4804 static struct mlx5_flow_counter_pool *
4805 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4806                              struct mlx5_flow_counter **cnt_free,
4807                              uint32_t age)
4808 {
4809         struct mlx5_priv *priv = dev->data->dev_private;
4810         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4811         struct mlx5_flow_counter_pool *pool;
4812         struct mlx5_counters tmp_tq;
4813         struct mlx5_devx_obj *dcs = NULL;
4814         struct mlx5_flow_counter *cnt;
4815         enum mlx5_counter_type cnt_type =
4816                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4817         bool fallback = priv->sh->cmng.counter_fallback;
4818         uint32_t i;
4819
4820         if (fallback) {
4821                 /* bulk_bitmap must be 0 for single counter allocation. */
4822                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4823                 if (!dcs)
4824                         return NULL;
4825                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4826                 if (!pool) {
4827                         pool = flow_dv_pool_create(dev, dcs, age);
4828                         if (!pool) {
4829                                 mlx5_devx_cmd_destroy(dcs);
4830                                 return NULL;
4831                         }
4832                 }
4833                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4834                 cnt = MLX5_POOL_GET_CNT(pool, i);
4835                 cnt->pool = pool;
4836                 cnt->dcs_when_free = dcs;
4837                 *cnt_free = cnt;
4838                 return pool;
4839         }
4840         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4841         if (!dcs) {
4842                 rte_errno = ENODATA;
4843                 return NULL;
4844         }
4845         pool = flow_dv_pool_create(dev, dcs, age);
4846         if (!pool) {
4847                 mlx5_devx_cmd_destroy(dcs);
4848                 return NULL;
4849         }
4850         TAILQ_INIT(&tmp_tq);
4851         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4852                 cnt = MLX5_POOL_GET_CNT(pool, i);
4853                 cnt->pool = pool;
4854                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4855         }
4856         rte_spinlock_lock(&cmng->csl[cnt_type]);
4857         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4858         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4859         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4860         (*cnt_free)->pool = pool;
4861         return pool;
4862 }
4863
4864 /**
4865  * Allocate a flow counter.
4866  *
4867  * @param[in] dev
4868  *   Pointer to the Ethernet device structure.
4869  * @param[in] age
4870  *   Whether the counter was allocated for aging.
4871  *
4872  * @return
4873  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4874  */
4875 static uint32_t
4876 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4877 {
4878         struct mlx5_priv *priv = dev->data->dev_private;
4879         struct mlx5_flow_counter_pool *pool = NULL;
4880         struct mlx5_flow_counter *cnt_free = NULL;
4881         bool fallback = priv->sh->cmng.counter_fallback;
4882         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4883         enum mlx5_counter_type cnt_type =
4884                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4885         uint32_t cnt_idx;
4886
4887         if (!priv->config.devx) {
4888                 rte_errno = ENOTSUP;
4889                 return 0;
4890         }
4891         /* Get free counters from container. */
4892         rte_spinlock_lock(&cmng->csl[cnt_type]);
4893         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4894         if (cnt_free)
4895                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4896         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4897         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4898                 goto err;
4899         pool = cnt_free->pool;
4900         if (fallback)
4901                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4902         /* Create a DV counter action only in the first time usage. */
4903         if (!cnt_free->action) {
4904                 uint16_t offset;
4905                 struct mlx5_devx_obj *dcs;
4906                 int ret;
4907
4908                 if (!fallback) {
4909                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4910                         dcs = pool->min_dcs;
4911                 } else {
4912                         offset = 0;
4913                         dcs = cnt_free->dcs_when_free;
4914                 }
4915                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4916                                                             &cnt_free->action);
4917                 if (ret) {
4918                         rte_errno = errno;
4919                         goto err;
4920                 }
4921         }
4922         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4923                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4924         /* Update the counter reset values. */
4925         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4926                                  &cnt_free->bytes))
4927                 goto err;
4928         if (!fallback && !priv->sh->cmng.query_thread_on)
4929                 /* Start the asynchronous batch query by the host thread. */
4930                 mlx5_set_query_alarm(priv->sh);
4931         return cnt_idx;
4932 err:
4933         if (cnt_free) {
4934                 cnt_free->pool = pool;
4935                 if (fallback)
4936                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4937                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4938                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4939                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4940         }
4941         return 0;
4942 }
4943
4944 /**
4945  * Allocate a shared flow counter.
4946  *
4947  * @param[in] ctx
4948  *   Pointer to the shared counter configuration.
4949  * @param[in] data
4950  *   Pointer to save the allocated counter index.
4951  *
4952  * @return
4953  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4954  */
4955
4956 static int32_t
4957 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4958 {
4959         struct mlx5_shared_counter_conf *conf = ctx;
4960         struct rte_eth_dev *dev = conf->dev;
4961         struct mlx5_flow_counter *cnt;
4962
4963         data->dword = flow_dv_counter_alloc(dev, 0);
4964         data->dword |= MLX5_CNT_SHARED_OFFSET;
4965         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4966         cnt->shared_info.id = conf->id;
4967         return 0;
4968 }
4969
4970 /**
4971  * Get a shared flow counter.
4972  *
4973  * @param[in] dev
4974  *   Pointer to the Ethernet device structure.
4975  * @param[in] id
4976  *   Counter identifier.
4977  *
4978  * @return
4979  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4980  */
4981 static uint32_t
4982 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
4983 {
4984         struct mlx5_priv *priv = dev->data->dev_private;
4985         struct mlx5_shared_counter_conf conf = {
4986                 .dev = dev,
4987                 .id = id,
4988         };
4989         union mlx5_l3t_data data = {
4990                 .dword = 0,
4991         };
4992
4993         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
4994                                flow_dv_counter_alloc_shared_cb, &conf);
4995         return data.dword;
4996 }
4997
4998 /**
4999  * Get age param from counter index.
5000  *
5001  * @param[in] dev
5002  *   Pointer to the Ethernet device structure.
5003  * @param[in] counter
5004  *   Index to the counter handler.
5005  *
5006  * @return
5007  *   The aging parameter specified for the counter index.
5008  */
5009 static struct mlx5_age_param*
5010 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5011                                 uint32_t counter)
5012 {
5013         struct mlx5_flow_counter *cnt;
5014         struct mlx5_flow_counter_pool *pool = NULL;
5015
5016         flow_dv_counter_get_by_idx(dev, counter, &pool);
5017         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5018         cnt = MLX5_POOL_GET_CNT(pool, counter);
5019         return MLX5_CNT_TO_AGE(cnt);
5020 }
5021
5022 /**
5023  * Remove a flow counter from aged counter list.
5024  *
5025  * @param[in] dev
5026  *   Pointer to the Ethernet device structure.
5027  * @param[in] counter
5028  *   Index to the counter handler.
5029  * @param[in] cnt
5030  *   Pointer to the counter handler.
5031  */
5032 static void
5033 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5034                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5035 {
5036         struct mlx5_age_info *age_info;
5037         struct mlx5_age_param *age_param;
5038         struct mlx5_priv *priv = dev->data->dev_private;
5039         uint16_t expected = AGE_CANDIDATE;
5040
5041         age_info = GET_PORT_AGE_INFO(priv);
5042         age_param = flow_dv_counter_idx_get_age(dev, counter);
5043         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5044                                          AGE_FREE, false, __ATOMIC_RELAXED,
5045                                          __ATOMIC_RELAXED)) {
5046                 /**
5047                  * We need the lock even it is age timeout,
5048                  * since counter may still in process.
5049                  */
5050                 rte_spinlock_lock(&age_info->aged_sl);
5051                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5052                 rte_spinlock_unlock(&age_info->aged_sl);
5053                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5054         }
5055 }
5056
5057 /**
5058  * Release a flow counter.
5059  *
5060  * @param[in] dev
5061  *   Pointer to the Ethernet device structure.
5062  * @param[in] counter
5063  *   Index to the counter handler.
5064  */
5065 static void
5066 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5067 {
5068         struct mlx5_priv *priv = dev->data->dev_private;
5069         struct mlx5_flow_counter_pool *pool = NULL;
5070         struct mlx5_flow_counter *cnt;
5071         enum mlx5_counter_type cnt_type;
5072
5073         if (!counter)
5074                 return;
5075         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5076         MLX5_ASSERT(pool);
5077         if (IS_SHARED_CNT(counter) &&
5078             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5079                 return;
5080         if (pool->is_aged)
5081                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5082         cnt->pool = pool;
5083         /*
5084          * Put the counter back to list to be updated in none fallback mode.
5085          * Currently, we are using two list alternately, while one is in query,
5086          * add the freed counter to the other list based on the pool query_gen
5087          * value. After query finishes, add counter the list to the global
5088          * container counter list. The list changes while query starts. In
5089          * this case, lock will not be needed as query callback and release
5090          * function both operate with the different list.
5091          *
5092          */
5093         if (!priv->sh->cmng.counter_fallback) {
5094                 rte_spinlock_lock(&pool->csl);
5095                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5096                 rte_spinlock_unlock(&pool->csl);
5097         } else {
5098                 cnt->dcs_when_free = cnt->dcs_when_active;
5099                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5100                                            MLX5_COUNTER_TYPE_ORIGIN;
5101                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5102                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5103                                   cnt, next);
5104                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5105         }
5106 }
5107
5108 /**
5109  * Verify the @p attributes will be correctly understood by the NIC and store
5110  * them in the @p flow if everything is correct.
5111  *
5112  * @param[in] dev
5113  *   Pointer to dev struct.
5114  * @param[in] attributes
5115  *   Pointer to flow attributes
5116  * @param[in] external
5117  *   This flow rule is created by request external to PMD.
5118  * @param[out] error
5119  *   Pointer to error structure.
5120  *
5121  * @return
5122  *   - 0 on success and non root table.
5123  *   - 1 on success and root table.
5124  *   - a negative errno value otherwise and rte_errno is set.
5125  */
5126 static int
5127 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5128                             const struct mlx5_flow_tunnel *tunnel,
5129                             const struct rte_flow_attr *attributes,
5130                             const struct flow_grp_info *grp_info,
5131                             struct rte_flow_error *error)
5132 {
5133         struct mlx5_priv *priv = dev->data->dev_private;
5134         uint32_t priority_max = priv->config.flow_prio - 1;
5135         int ret = 0;
5136
5137 #ifndef HAVE_MLX5DV_DR
5138         RTE_SET_USED(tunnel);
5139         RTE_SET_USED(grp_info);
5140         if (attributes->group)
5141                 return rte_flow_error_set(error, ENOTSUP,
5142                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5143                                           NULL,
5144                                           "groups are not supported");
5145 #else
5146         uint32_t table = 0;
5147
5148         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5149                                        grp_info, error);
5150         if (ret)
5151                 return ret;
5152         if (!table)
5153                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5154 #endif
5155         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5156             attributes->priority >= priority_max)
5157                 return rte_flow_error_set(error, ENOTSUP,
5158                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5159                                           NULL,
5160                                           "priority out of range");
5161         if (attributes->transfer) {
5162                 if (!priv->config.dv_esw_en)
5163                         return rte_flow_error_set
5164                                 (error, ENOTSUP,
5165                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5166                                  "E-Switch dr is not supported");
5167                 if (!(priv->representor || priv->master))
5168                         return rte_flow_error_set
5169                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5170                                  NULL, "E-Switch configuration can only be"
5171                                  " done by a master or a representor device");
5172                 if (attributes->egress)
5173                         return rte_flow_error_set
5174                                 (error, ENOTSUP,
5175                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5176                                  "egress is not supported");
5177         }
5178         if (!(attributes->egress ^ attributes->ingress))
5179                 return rte_flow_error_set(error, ENOTSUP,
5180                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5181                                           "must specify exactly one of "
5182                                           "ingress or egress");
5183         return ret;
5184 }
5185
5186 /**
5187  * Internal validation function. For validating both actions and items.
5188  *
5189  * @param[in] dev
5190  *   Pointer to the rte_eth_dev structure.
5191  * @param[in] attr
5192  *   Pointer to the flow attributes.
5193  * @param[in] items
5194  *   Pointer to the list of items.
5195  * @param[in] actions
5196  *   Pointer to the list of actions.
5197  * @param[in] external
5198  *   This flow rule is created by request external to PMD.
5199  * @param[in] hairpin
5200  *   Number of hairpin TX actions, 0 means classic flow.
5201  * @param[out] error
5202  *   Pointer to the error structure.
5203  *
5204  * @return
5205  *   0 on success, a negative errno value otherwise and rte_errno is set.
5206  */
5207 static int
5208 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5209                  const struct rte_flow_item items[],
5210                  const struct rte_flow_action actions[],
5211                  bool external, int hairpin, struct rte_flow_error *error)
5212 {
5213         int ret;
5214         uint64_t action_flags = 0;
5215         uint64_t item_flags = 0;
5216         uint64_t last_item = 0;
5217         uint8_t next_protocol = 0xff;
5218         uint16_t ether_type = 0;
5219         int actions_n = 0;
5220         uint8_t item_ipv6_proto = 0;
5221         const struct rte_flow_item *gre_item = NULL;
5222         const struct rte_flow_action_raw_decap *decap;
5223         const struct rte_flow_action_raw_encap *encap;
5224         const struct rte_flow_action_rss *rss;
5225         const struct rte_flow_item_tcp nic_tcp_mask = {
5226                 .hdr = {
5227                         .tcp_flags = 0xFF,
5228                         .src_port = RTE_BE16(UINT16_MAX),
5229                         .dst_port = RTE_BE16(UINT16_MAX),
5230                 }
5231         };
5232         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5233                 .hdr = {
5234                         .src_addr =
5235                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5236                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5237                         .dst_addr =
5238                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5239                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5240                         .vtc_flow = RTE_BE32(0xffffffff),
5241                         .proto = 0xff,
5242                         .hop_limits = 0xff,
5243                 },
5244                 .has_frag_ext = 1,
5245         };
5246         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5247                 .hdr = {
5248                         .common = {
5249                                 .u32 =
5250                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5251                                         .type = 0xFF,
5252                                         }).u32),
5253                         },
5254                         .dummy[0] = 0xffffffff,
5255                 },
5256         };
5257         struct mlx5_priv *priv = dev->data->dev_private;
5258         struct mlx5_dev_config *dev_conf = &priv->config;
5259         uint16_t queue_index = 0xFFFF;
5260         const struct rte_flow_item_vlan *vlan_m = NULL;
5261         int16_t rw_act_num = 0;
5262         uint64_t is_root;
5263         const struct mlx5_flow_tunnel *tunnel;
5264         struct flow_grp_info grp_info = {
5265                 .external = !!external,
5266                 .transfer = !!attr->transfer,
5267                 .fdb_def_rule = !!priv->fdb_def_rule,
5268         };
5269         const struct rte_eth_hairpin_conf *conf;
5270
5271         if (items == NULL)
5272                 return -1;
5273         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5274                 tunnel = flow_items_to_tunnel(items);
5275                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5276                                 MLX5_FLOW_ACTION_DECAP;
5277         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5278                 tunnel = flow_actions_to_tunnel(actions);
5279                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5280         } else {
5281                 tunnel = NULL;
5282         }
5283         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5284                                 (dev, tunnel, attr, items, actions);
5285         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5286         if (ret < 0)
5287                 return ret;
5288         is_root = (uint64_t)ret;
5289         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5290                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5291                 int type = items->type;
5292
5293                 if (!mlx5_flow_os_item_supported(type))
5294                         return rte_flow_error_set(error, ENOTSUP,
5295                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5296                                                   NULL, "item not supported");
5297                 switch (type) {
5298                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5299                         if (items[0].type != (typeof(items[0].type))
5300                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5301                                 return rte_flow_error_set
5302                                                 (error, EINVAL,
5303                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5304                                                 NULL, "MLX5 private items "
5305                                                 "must be the first");
5306                         break;
5307                 case RTE_FLOW_ITEM_TYPE_VOID:
5308                         break;
5309                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5310                         ret = flow_dv_validate_item_port_id
5311                                         (dev, items, attr, item_flags, error);
5312                         if (ret < 0)
5313                                 return ret;
5314                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5315                         break;
5316                 case RTE_FLOW_ITEM_TYPE_ETH:
5317                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5318                                                           true, error);
5319                         if (ret < 0)
5320                                 return ret;
5321                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5322                                              MLX5_FLOW_LAYER_OUTER_L2;
5323                         if (items->mask != NULL && items->spec != NULL) {
5324                                 ether_type =
5325                                         ((const struct rte_flow_item_eth *)
5326                                          items->spec)->type;
5327                                 ether_type &=
5328                                         ((const struct rte_flow_item_eth *)
5329                                          items->mask)->type;
5330                                 ether_type = rte_be_to_cpu_16(ether_type);
5331                         } else {
5332                                 ether_type = 0;
5333                         }
5334                         break;
5335                 case RTE_FLOW_ITEM_TYPE_VLAN:
5336                         ret = flow_dv_validate_item_vlan(items, item_flags,
5337                                                          dev, error);
5338                         if (ret < 0)
5339                                 return ret;
5340                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5341                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5342                         if (items->mask != NULL && items->spec != NULL) {
5343                                 ether_type =
5344                                         ((const struct rte_flow_item_vlan *)
5345                                          items->spec)->inner_type;
5346                                 ether_type &=
5347                                         ((const struct rte_flow_item_vlan *)
5348                                          items->mask)->inner_type;
5349                                 ether_type = rte_be_to_cpu_16(ether_type);
5350                         } else {
5351                                 ether_type = 0;
5352                         }
5353                         /* Store outer VLAN mask for of_push_vlan action. */
5354                         if (!tunnel)
5355                                 vlan_m = items->mask;
5356                         break;
5357                 case RTE_FLOW_ITEM_TYPE_IPV4:
5358                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5359                                                   &item_flags, &tunnel);
5360                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5361                                                          last_item, ether_type,
5362                                                          error);
5363                         if (ret < 0)
5364                                 return ret;
5365                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5366                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5367                         if (items->mask != NULL &&
5368                             ((const struct rte_flow_item_ipv4 *)
5369                              items->mask)->hdr.next_proto_id) {
5370                                 next_protocol =
5371                                         ((const struct rte_flow_item_ipv4 *)
5372                                          (items->spec))->hdr.next_proto_id;
5373                                 next_protocol &=
5374                                         ((const struct rte_flow_item_ipv4 *)
5375                                          (items->mask))->hdr.next_proto_id;
5376                         } else {
5377                                 /* Reset for inner layer. */
5378                                 next_protocol = 0xff;
5379                         }
5380                         break;
5381                 case RTE_FLOW_ITEM_TYPE_IPV6:
5382                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5383                                                   &item_flags, &tunnel);
5384                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5385                                                            last_item,
5386                                                            ether_type,
5387                                                            &nic_ipv6_mask,
5388                                                            error);
5389                         if (ret < 0)
5390                                 return ret;
5391                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5392                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5393                         if (items->mask != NULL &&
5394                             ((const struct rte_flow_item_ipv6 *)
5395                              items->mask)->hdr.proto) {
5396                                 item_ipv6_proto =
5397                                         ((const struct rte_flow_item_ipv6 *)
5398                                          items->spec)->hdr.proto;
5399                                 next_protocol =
5400                                         ((const struct rte_flow_item_ipv6 *)
5401                                          items->spec)->hdr.proto;
5402                                 next_protocol &=
5403                                         ((const struct rte_flow_item_ipv6 *)
5404                                          items->mask)->hdr.proto;
5405                         } else {
5406                                 /* Reset for inner layer. */
5407                                 next_protocol = 0xff;
5408                         }
5409                         break;
5410                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5411                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5412                                                                   item_flags,
5413                                                                   error);
5414                         if (ret < 0)
5415                                 return ret;
5416                         last_item = tunnel ?
5417                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5418                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5419                         if (items->mask != NULL &&
5420                             ((const struct rte_flow_item_ipv6_frag_ext *)
5421                              items->mask)->hdr.next_header) {
5422                                 next_protocol =
5423                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5424                                  items->spec)->hdr.next_header;
5425                                 next_protocol &=
5426                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5427                                  items->mask)->hdr.next_header;
5428                         } else {
5429                                 /* Reset for inner layer. */
5430                                 next_protocol = 0xff;
5431                         }
5432                         break;
5433                 case RTE_FLOW_ITEM_TYPE_TCP:
5434                         ret = mlx5_flow_validate_item_tcp
5435                                                 (items, item_flags,
5436                                                  next_protocol,
5437                                                  &nic_tcp_mask,
5438                                                  error);
5439                         if (ret < 0)
5440                                 return ret;
5441                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5442                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5443                         break;
5444                 case RTE_FLOW_ITEM_TYPE_UDP:
5445                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5446                                                           next_protocol,
5447                                                           error);
5448                         if (ret < 0)
5449                                 return ret;
5450                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5451                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5452                         break;
5453                 case RTE_FLOW_ITEM_TYPE_GRE:
5454                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5455                                                           next_protocol, error);
5456                         if (ret < 0)
5457                                 return ret;
5458                         gre_item = items;
5459                         last_item = MLX5_FLOW_LAYER_GRE;
5460                         break;
5461                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5462                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5463                                                             next_protocol,
5464                                                             error);
5465                         if (ret < 0)
5466                                 return ret;
5467                         last_item = MLX5_FLOW_LAYER_NVGRE;
5468                         break;
5469                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5470                         ret = mlx5_flow_validate_item_gre_key
5471                                 (items, item_flags, gre_item, error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5475                         break;
5476                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5477                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5478                                                             error);
5479                         if (ret < 0)
5480                                 return ret;
5481                         last_item = MLX5_FLOW_LAYER_VXLAN;
5482                         break;
5483                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5484                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5485                                                                 item_flags, dev,
5486                                                                 error);
5487                         if (ret < 0)
5488                                 return ret;
5489                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5490                         break;
5491                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5492                         ret = mlx5_flow_validate_item_geneve(items,
5493                                                              item_flags, dev,
5494                                                              error);
5495                         if (ret < 0)
5496                                 return ret;
5497                         last_item = MLX5_FLOW_LAYER_GENEVE;
5498                         break;
5499                 case RTE_FLOW_ITEM_TYPE_MPLS:
5500                         ret = mlx5_flow_validate_item_mpls(dev, items,
5501                                                            item_flags,
5502                                                            last_item, error);
5503                         if (ret < 0)
5504                                 return ret;
5505                         last_item = MLX5_FLOW_LAYER_MPLS;
5506                         break;
5507
5508                 case RTE_FLOW_ITEM_TYPE_MARK:
5509                         ret = flow_dv_validate_item_mark(dev, items, attr,
5510                                                          error);
5511                         if (ret < 0)
5512                                 return ret;
5513                         last_item = MLX5_FLOW_ITEM_MARK;
5514                         break;
5515                 case RTE_FLOW_ITEM_TYPE_META:
5516                         ret = flow_dv_validate_item_meta(dev, items, attr,
5517                                                          error);
5518                         if (ret < 0)
5519                                 return ret;
5520                         last_item = MLX5_FLOW_ITEM_METADATA;
5521                         break;
5522                 case RTE_FLOW_ITEM_TYPE_ICMP:
5523                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5524                                                            next_protocol,
5525                                                            error);
5526                         if (ret < 0)
5527                                 return ret;
5528                         last_item = MLX5_FLOW_LAYER_ICMP;
5529                         break;
5530                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5531                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5532                                                             next_protocol,
5533                                                             error);
5534                         if (ret < 0)
5535                                 return ret;
5536                         item_ipv6_proto = IPPROTO_ICMPV6;
5537                         last_item = MLX5_FLOW_LAYER_ICMP6;
5538                         break;
5539                 case RTE_FLOW_ITEM_TYPE_TAG:
5540                         ret = flow_dv_validate_item_tag(dev, items,
5541                                                         attr, error);
5542                         if (ret < 0)
5543                                 return ret;
5544                         last_item = MLX5_FLOW_ITEM_TAG;
5545                         break;
5546                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5547                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5548                         break;
5549                 case RTE_FLOW_ITEM_TYPE_GTP:
5550                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5551                                                         error);
5552                         if (ret < 0)
5553                                 return ret;
5554                         last_item = MLX5_FLOW_LAYER_GTP;
5555                         break;
5556                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5557                         /* Capacity will be checked in the translate stage. */
5558                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5559                                                             last_item,
5560                                                             ether_type,
5561                                                             &nic_ecpri_mask,
5562                                                             error);
5563                         if (ret < 0)
5564                                 return ret;
5565                         last_item = MLX5_FLOW_LAYER_ECPRI;
5566                         break;
5567                 default:
5568                         return rte_flow_error_set(error, ENOTSUP,
5569                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5570                                                   NULL, "item not supported");
5571                 }
5572                 item_flags |= last_item;
5573         }
5574         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5575                 int type = actions->type;
5576
5577                 if (!mlx5_flow_os_action_supported(type))
5578                         return rte_flow_error_set(error, ENOTSUP,
5579                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5580                                                   actions,
5581                                                   "action not supported");
5582                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5583                         return rte_flow_error_set(error, ENOTSUP,
5584                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5585                                                   actions, "too many actions");
5586                 switch (type) {
5587                 case RTE_FLOW_ACTION_TYPE_VOID:
5588                         break;
5589                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5590                         ret = flow_dv_validate_action_port_id(dev,
5591                                                               action_flags,
5592                                                               actions,
5593                                                               attr,
5594                                                               error);
5595                         if (ret)
5596                                 return ret;
5597                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5598                         ++actions_n;
5599                         break;
5600                 case RTE_FLOW_ACTION_TYPE_FLAG:
5601                         ret = flow_dv_validate_action_flag(dev, action_flags,
5602                                                            attr, error);
5603                         if (ret < 0)
5604                                 return ret;
5605                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5606                                 /* Count all modify-header actions as one. */
5607                                 if (!(action_flags &
5608                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5609                                         ++actions_n;
5610                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5611                                                 MLX5_FLOW_ACTION_MARK_EXT;
5612                         } else {
5613                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5614                                 ++actions_n;
5615                         }
5616                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5617                         break;
5618                 case RTE_FLOW_ACTION_TYPE_MARK:
5619                         ret = flow_dv_validate_action_mark(dev, actions,
5620                                                            action_flags,
5621                                                            attr, error);
5622                         if (ret < 0)
5623                                 return ret;
5624                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5625                                 /* Count all modify-header actions as one. */
5626                                 if (!(action_flags &
5627                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5628                                         ++actions_n;
5629                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5630                                                 MLX5_FLOW_ACTION_MARK_EXT;
5631                         } else {
5632                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5633                                 ++actions_n;
5634                         }
5635                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5636                         break;
5637                 case RTE_FLOW_ACTION_TYPE_SET_META:
5638                         ret = flow_dv_validate_action_set_meta(dev, actions,
5639                                                                action_flags,
5640                                                                attr, error);
5641                         if (ret < 0)
5642                                 return ret;
5643                         /* Count all modify-header actions as one action. */
5644                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5645                                 ++actions_n;
5646                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5647                         rw_act_num += MLX5_ACT_NUM_SET_META;
5648                         break;
5649                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5650                         ret = flow_dv_validate_action_set_tag(dev, actions,
5651                                                               action_flags,
5652                                                               attr, error);
5653                         if (ret < 0)
5654                                 return ret;
5655                         /* Count all modify-header actions as one action. */
5656                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5657                                 ++actions_n;
5658                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5659                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5660                         break;
5661                 case RTE_FLOW_ACTION_TYPE_DROP:
5662                         ret = mlx5_flow_validate_action_drop(action_flags,
5663                                                              attr, error);
5664                         if (ret < 0)
5665                                 return ret;
5666                         action_flags |= MLX5_FLOW_ACTION_DROP;
5667                         ++actions_n;
5668                         break;
5669                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5670                         ret = mlx5_flow_validate_action_queue(actions,
5671                                                               action_flags, dev,
5672                                                               attr, error);
5673                         if (ret < 0)
5674                                 return ret;
5675                         queue_index = ((const struct rte_flow_action_queue *)
5676                                                         (actions->conf))->index;
5677                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5678                         ++actions_n;
5679                         break;
5680                 case RTE_FLOW_ACTION_TYPE_RSS:
5681                         rss = actions->conf;
5682                         ret = mlx5_flow_validate_action_rss(actions,
5683                                                             action_flags, dev,
5684                                                             attr, item_flags,
5685                                                             error);
5686                         if (ret < 0)
5687                                 return ret;
5688                         if (rss != NULL && rss->queue_num)
5689                                 queue_index = rss->queue[0];
5690                         action_flags |= MLX5_FLOW_ACTION_RSS;
5691                         ++actions_n;
5692                         break;
5693                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5694                         ret =
5695                         mlx5_flow_validate_action_default_miss(action_flags,
5696                                         attr, error);
5697                         if (ret < 0)
5698                                 return ret;
5699                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5700                         ++actions_n;
5701                         break;
5702                 case RTE_FLOW_ACTION_TYPE_COUNT:
5703                         ret = flow_dv_validate_action_count(dev, error);
5704                         if (ret < 0)
5705                                 return ret;
5706                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5707                         ++actions_n;
5708                         break;
5709                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5710                         if (flow_dv_validate_action_pop_vlan(dev,
5711                                                              action_flags,
5712                                                              actions,
5713                                                              item_flags, attr,
5714                                                              error))
5715                                 return -rte_errno;
5716                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5717                         ++actions_n;
5718                         break;
5719                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5720                         ret = flow_dv_validate_action_push_vlan(dev,
5721                                                                 action_flags,
5722                                                                 vlan_m,
5723                                                                 actions, attr,
5724                                                                 error);
5725                         if (ret < 0)
5726                                 return ret;
5727                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5728                         ++actions_n;
5729                         break;
5730                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5731                         ret = flow_dv_validate_action_set_vlan_pcp
5732                                                 (action_flags, actions, error);
5733                         if (ret < 0)
5734                                 return ret;
5735                         /* Count PCP with push_vlan command. */
5736                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5737                         break;
5738                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5739                         ret = flow_dv_validate_action_set_vlan_vid
5740                                                 (item_flags, action_flags,
5741                                                  actions, error);
5742                         if (ret < 0)
5743                                 return ret;
5744                         /* Count VID with push_vlan command. */
5745                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5746                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5747                         break;
5748                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5749                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5750                         ret = flow_dv_validate_action_l2_encap(dev,
5751                                                                action_flags,
5752                                                                actions, attr,
5753                                                                error);
5754                         if (ret < 0)
5755                                 return ret;
5756                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5757                         ++actions_n;
5758                         break;
5759                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5760                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5761                         ret = flow_dv_validate_action_decap(dev, action_flags,
5762                                                             attr, error);
5763                         if (ret < 0)
5764                                 return ret;
5765                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5766                         ++actions_n;
5767                         break;
5768                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5769                         ret = flow_dv_validate_action_raw_encap_decap
5770                                 (dev, NULL, actions->conf, attr, &action_flags,
5771                                  &actions_n, error);
5772                         if (ret < 0)
5773                                 return ret;
5774                         break;
5775                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5776                         decap = actions->conf;
5777                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5778                                 ;
5779                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5780                                 encap = NULL;
5781                                 actions--;
5782                         } else {
5783                                 encap = actions->conf;
5784                         }
5785                         ret = flow_dv_validate_action_raw_encap_decap
5786                                            (dev,
5787                                             decap ? decap : &empty_decap, encap,
5788                                             attr, &action_flags, &actions_n,
5789                                             error);
5790                         if (ret < 0)
5791                                 return ret;
5792                         break;
5793                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5794                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5795                         ret = flow_dv_validate_action_modify_mac(action_flags,
5796                                                                  actions,
5797                                                                  item_flags,
5798                                                                  error);
5799                         if (ret < 0)
5800                                 return ret;
5801                         /* Count all modify-header actions as one action. */
5802                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5803                                 ++actions_n;
5804                         action_flags |= actions->type ==
5805                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5806                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5807                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5808                         /*
5809                          * Even if the source and destination MAC addresses have
5810                          * overlap in the header with 4B alignment, the convert
5811                          * function will handle them separately and 4 SW actions
5812                          * will be created. And 2 actions will be added each
5813                          * time no matter how many bytes of address will be set.
5814                          */
5815                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5816                         break;
5817                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5818                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5819                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5820                                                                   actions,
5821                                                                   item_flags,
5822                                                                   error);
5823                         if (ret < 0)
5824                                 return ret;
5825                         /* Count all modify-header actions as one action. */
5826                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5827                                 ++actions_n;
5828                         action_flags |= actions->type ==
5829                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5830                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5831                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5832                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5833                         break;
5834                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5835                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5836                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5837                                                                   actions,
5838                                                                   item_flags,
5839                                                                   error);
5840                         if (ret < 0)
5841                                 return ret;
5842                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5843                                 return rte_flow_error_set(error, ENOTSUP,
5844                                         RTE_FLOW_ERROR_TYPE_ACTION,
5845                                         actions,
5846                                         "Can't change header "
5847                                         "with ICMPv6 proto");
5848                         /* Count all modify-header actions as one action. */
5849                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5850                                 ++actions_n;
5851                         action_flags |= actions->type ==
5852                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5853                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5854                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5855                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5856                         break;
5857                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5858                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5859                         ret = flow_dv_validate_action_modify_tp(action_flags,
5860                                                                 actions,
5861                                                                 item_flags,
5862                                                                 error);
5863                         if (ret < 0)
5864                                 return ret;
5865                         /* Count all modify-header actions as one action. */
5866                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5867                                 ++actions_n;
5868                         action_flags |= actions->type ==
5869                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5870                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5871                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5872                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5873                         break;
5874                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5875                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5876                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5877                                                                  actions,
5878                                                                  item_flags,
5879                                                                  error);
5880                         if (ret < 0)
5881                                 return ret;
5882                         /* Count all modify-header actions as one action. */
5883                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5884                                 ++actions_n;
5885                         action_flags |= actions->type ==
5886                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5887                                                 MLX5_FLOW_ACTION_SET_TTL :
5888                                                 MLX5_FLOW_ACTION_DEC_TTL;
5889                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5890                         break;
5891                 case RTE_FLOW_ACTION_TYPE_JUMP:
5892                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5893                                                            action_flags,
5894                                                            attr, external,
5895                                                            error);
5896                         if (ret)
5897                                 return ret;
5898                         ++actions_n;
5899                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5900                         break;
5901                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5902                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5903                         ret = flow_dv_validate_action_modify_tcp_seq
5904                                                                 (action_flags,
5905                                                                  actions,
5906                                                                  item_flags,
5907                                                                  error);
5908                         if (ret < 0)
5909                                 return ret;
5910                         /* Count all modify-header actions as one action. */
5911                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5912                                 ++actions_n;
5913                         action_flags |= actions->type ==
5914                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5915                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5916                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5917                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5918                         break;
5919                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5920                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5921                         ret = flow_dv_validate_action_modify_tcp_ack
5922                                                                 (action_flags,
5923                                                                  actions,
5924                                                                  item_flags,
5925                                                                  error);
5926                         if (ret < 0)
5927                                 return ret;
5928                         /* Count all modify-header actions as one action. */
5929                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5930                                 ++actions_n;
5931                         action_flags |= actions->type ==
5932                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5933                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5934                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5935                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5936                         break;
5937                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5938                         break;
5939                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5940                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5941                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5942                         break;
5943                 case RTE_FLOW_ACTION_TYPE_METER:
5944                         ret = mlx5_flow_validate_action_meter(dev,
5945                                                               action_flags,
5946                                                               actions, attr,
5947                                                               error);
5948                         if (ret < 0)
5949                                 return ret;
5950                         action_flags |= MLX5_FLOW_ACTION_METER;
5951                         ++actions_n;
5952                         /* Meter action will add one more TAG action. */
5953                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5954                         break;
5955                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
5956                         if (!attr->transfer && !attr->group)
5957                                 return rte_flow_error_set(error, ENOTSUP,
5958                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5959                                                                            NULL,
5960                           "Shared ASO age action is not supported for group 0");
5961                         action_flags |= MLX5_FLOW_ACTION_AGE;
5962                         ++actions_n;
5963                         break;
5964                 case RTE_FLOW_ACTION_TYPE_AGE:
5965                         ret = flow_dv_validate_action_age(action_flags,
5966                                                           actions, dev,
5967                                                           error);
5968                         if (ret < 0)
5969                                 return ret;
5970                         action_flags |= MLX5_FLOW_ACTION_AGE;
5971                         ++actions_n;
5972                         break;
5973                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5974                         ret = flow_dv_validate_action_modify_ipv4_dscp
5975                                                          (action_flags,
5976                                                           actions,
5977                                                           item_flags,
5978                                                           error);
5979                         if (ret < 0)
5980                                 return ret;
5981                         /* Count all modify-header actions as one action. */
5982                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5983                                 ++actions_n;
5984                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5985                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5986                         break;
5987                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5988                         ret = flow_dv_validate_action_modify_ipv6_dscp
5989                                                                 (action_flags,
5990                                                                  actions,
5991                                                                  item_flags,
5992                                                                  error);
5993                         if (ret < 0)
5994                                 return ret;
5995                         /* Count all modify-header actions as one action. */
5996                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5997                                 ++actions_n;
5998                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5999                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6000                         break;
6001                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6002                         ret = flow_dv_validate_action_sample(action_flags,
6003                                                              actions, dev,
6004                                                              attr, error);
6005                         if (ret < 0)
6006                                 return ret;
6007                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6008                         ++actions_n;
6009                         break;
6010                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6011                         if (actions[0].type != (typeof(actions[0].type))
6012                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6013                                 return rte_flow_error_set
6014                                                 (error, EINVAL,
6015                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6016                                                 NULL, "MLX5 private action "
6017                                                 "must be the first");
6018
6019                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6020                         break;
6021                 default:
6022                         return rte_flow_error_set(error, ENOTSUP,
6023                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6024                                                   actions,
6025                                                   "action not supported");
6026                 }
6027         }
6028         /*
6029          * Validate actions in flow rules
6030          * - Explicit decap action is prohibited by the tunnel offload API.
6031          * - Drop action in tunnel steer rule is prohibited by the API.
6032          * - Application cannot use MARK action because it's value can mask
6033          *   tunnel default miss nitification.
6034          * - JUMP in tunnel match rule has no support in current PMD
6035          *   implementation.
6036          * - TAG & META are reserved for future uses.
6037          */
6038         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6039                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6040                                             MLX5_FLOW_ACTION_MARK     |
6041                                             MLX5_FLOW_ACTION_SET_TAG  |
6042                                             MLX5_FLOW_ACTION_SET_META |
6043                                             MLX5_FLOW_ACTION_DROP;
6044
6045                 if (action_flags & bad_actions_mask)
6046                         return rte_flow_error_set
6047                                         (error, EINVAL,
6048                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6049                                         "Invalid RTE action in tunnel "
6050                                         "set decap rule");
6051                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6052                         return rte_flow_error_set
6053                                         (error, EINVAL,
6054                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6055                                         "tunnel set decap rule must terminate "
6056                                         "with JUMP");
6057                 if (!attr->ingress)
6058                         return rte_flow_error_set
6059                                         (error, EINVAL,
6060                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6061                                         "tunnel flows for ingress traffic only");
6062         }
6063         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6064                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6065                                             MLX5_FLOW_ACTION_MARK    |
6066                                             MLX5_FLOW_ACTION_SET_TAG |
6067                                             MLX5_FLOW_ACTION_SET_META;
6068
6069                 if (action_flags & bad_actions_mask)
6070                         return rte_flow_error_set
6071                                         (error, EINVAL,
6072                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6073                                         "Invalid RTE action in tunnel "
6074                                         "set match rule");
6075         }
6076         /*
6077          * Validate the drop action mutual exclusion with other actions.
6078          * Drop action is mutually-exclusive with any other action, except for
6079          * Count action.
6080          */
6081         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6082             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6083                 return rte_flow_error_set(error, EINVAL,
6084                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6085                                           "Drop action is mutually-exclusive "
6086                                           "with any other action, except for "
6087                                           "Count action");
6088         /* Eswitch has few restrictions on using items and actions */
6089         if (attr->transfer) {
6090                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6091                     action_flags & MLX5_FLOW_ACTION_FLAG)
6092                         return rte_flow_error_set(error, ENOTSUP,
6093                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6094                                                   NULL,
6095                                                   "unsupported action FLAG");
6096                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6097                     action_flags & MLX5_FLOW_ACTION_MARK)
6098                         return rte_flow_error_set(error, ENOTSUP,
6099                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6100                                                   NULL,
6101                                                   "unsupported action MARK");
6102                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6103                         return rte_flow_error_set(error, ENOTSUP,
6104                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6105                                                   NULL,
6106                                                   "unsupported action QUEUE");
6107                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6108                         return rte_flow_error_set(error, ENOTSUP,
6109                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6110                                                   NULL,
6111                                                   "unsupported action RSS");
6112                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6113                         return rte_flow_error_set(error, EINVAL,
6114                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6115                                                   actions,
6116                                                   "no fate action is found");
6117         } else {
6118                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6119                         return rte_flow_error_set(error, EINVAL,
6120                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6121                                                   actions,
6122                                                   "no fate action is found");
6123         }
6124         /*
6125          * Continue validation for Xcap and VLAN actions.
6126          * If hairpin is working in explicit TX rule mode, there is no actions
6127          * splitting and the validation of hairpin ingress flow should be the
6128          * same as other standard flows.
6129          */
6130         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6131                              MLX5_FLOW_VLAN_ACTIONS)) &&
6132             (queue_index == 0xFFFF ||
6133              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6134              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6135              conf->tx_explicit != 0))) {
6136                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6137                     MLX5_FLOW_XCAP_ACTIONS)
6138                         return rte_flow_error_set(error, ENOTSUP,
6139                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6140                                                   NULL, "encap and decap "
6141                                                   "combination aren't supported");
6142                 if (!attr->transfer && attr->ingress) {
6143                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6144                                 return rte_flow_error_set
6145                                                 (error, ENOTSUP,
6146                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6147                                                  NULL, "encap is not supported"
6148                                                  " for ingress traffic");
6149                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6150                                 return rte_flow_error_set
6151                                                 (error, ENOTSUP,
6152                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6153                                                  NULL, "push VLAN action not "
6154                                                  "supported for ingress");
6155                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6156                                         MLX5_FLOW_VLAN_ACTIONS)
6157                                 return rte_flow_error_set
6158                                                 (error, ENOTSUP,
6159                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6160                                                  NULL, "no support for "
6161                                                  "multiple VLAN actions");
6162                 }
6163         }
6164         /*
6165          * Hairpin flow will add one more TAG action in TX implicit mode.
6166          * In TX explicit mode, there will be no hairpin flow ID.
6167          */
6168         if (hairpin > 0)
6169                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6170         /* extra metadata enabled: one more TAG action will be add. */
6171         if (dev_conf->dv_flow_en &&
6172             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6173             mlx5_flow_ext_mreg_supported(dev))
6174                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6175         if ((uint32_t)rw_act_num >
6176                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6177                 return rte_flow_error_set(error, ENOTSUP,
6178                                           RTE_FLOW_ERROR_TYPE_ACTION,
6179                                           NULL, "too many header modify"
6180                                           " actions to support");
6181         }
6182         return 0;
6183 }
6184
6185 /**
6186  * Internal preparation function. Allocates the DV flow size,
6187  * this size is constant.
6188  *
6189  * @param[in] dev
6190  *   Pointer to the rte_eth_dev structure.
6191  * @param[in] attr
6192  *   Pointer to the flow attributes.
6193  * @param[in] items
6194  *   Pointer to the list of items.
6195  * @param[in] actions
6196  *   Pointer to the list of actions.
6197  * @param[out] error
6198  *   Pointer to the error structure.
6199  *
6200  * @return
6201  *   Pointer to mlx5_flow object on success,
6202  *   otherwise NULL and rte_errno is set.
6203  */
6204 static struct mlx5_flow *
6205 flow_dv_prepare(struct rte_eth_dev *dev,
6206                 const struct rte_flow_attr *attr __rte_unused,
6207                 const struct rte_flow_item items[] __rte_unused,
6208                 const struct rte_flow_action actions[] __rte_unused,
6209                 struct rte_flow_error *error)
6210 {
6211         uint32_t handle_idx = 0;
6212         struct mlx5_flow *dev_flow;
6213         struct mlx5_flow_handle *dev_handle;
6214         struct mlx5_priv *priv = dev->data->dev_private;
6215         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6216
6217         MLX5_ASSERT(wks);
6218         /* In case of corrupting the memory. */
6219         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6220                 rte_flow_error_set(error, ENOSPC,
6221                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6222                                    "not free temporary device flow");
6223                 return NULL;
6224         }
6225         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6226                                    &handle_idx);
6227         if (!dev_handle) {
6228                 rte_flow_error_set(error, ENOMEM,
6229                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6230                                    "not enough memory to create flow handle");
6231                 return NULL;
6232         }
6233         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6234         dev_flow = &wks->flows[wks->flow_idx++];
6235         memset(dev_flow, 0, sizeof(*dev_flow));
6236         dev_flow->handle = dev_handle;
6237         dev_flow->handle_idx = handle_idx;
6238         /*
6239          * In some old rdma-core releases, before continuing, a check of the
6240          * length of matching parameter will be done at first. It needs to use
6241          * the length without misc4 param. If the flow has misc4 support, then
6242          * the length needs to be adjusted accordingly. Each param member is
6243          * aligned with a 64B boundary naturally.
6244          */
6245         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6246                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6247         dev_flow->ingress = attr->ingress;
6248         dev_flow->dv.transfer = attr->transfer;
6249         return dev_flow;
6250 }
6251
6252 #ifdef RTE_LIBRTE_MLX5_DEBUG
6253 /**
6254  * Sanity check for match mask and value. Similar to check_valid_spec() in
6255  * kernel driver. If unmasked bit is present in value, it returns failure.
6256  *
6257  * @param match_mask
6258  *   pointer to match mask buffer.
6259  * @param match_value
6260  *   pointer to match value buffer.
6261  *
6262  * @return
6263  *   0 if valid, -EINVAL otherwise.
6264  */
6265 static int
6266 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6267 {
6268         uint8_t *m = match_mask;
6269         uint8_t *v = match_value;
6270         unsigned int i;
6271
6272         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6273                 if (v[i] & ~m[i]) {
6274                         DRV_LOG(ERR,
6275                                 "match_value differs from match_criteria"
6276                                 " %p[%u] != %p[%u]",
6277                                 match_value, i, match_mask, i);
6278                         return -EINVAL;
6279                 }
6280         }
6281         return 0;
6282 }
6283 #endif
6284
6285 /**
6286  * Add match of ip_version.
6287  *
6288  * @param[in] group
6289  *   Flow group.
6290  * @param[in] headers_v
6291  *   Values header pointer.
6292  * @param[in] headers_m
6293  *   Masks header pointer.
6294  * @param[in] ip_version
6295  *   The IP version to set.
6296  */
6297 static inline void
6298 flow_dv_set_match_ip_version(uint32_t group,
6299                              void *headers_v,
6300                              void *headers_m,
6301                              uint8_t ip_version)
6302 {
6303         if (group == 0)
6304                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6305         else
6306                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6307                          ip_version);
6308         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6309         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6310         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6311 }
6312
6313 /**
6314  * Add Ethernet item to matcher and to the value.
6315  *
6316  * @param[in, out] matcher
6317  *   Flow matcher.
6318  * @param[in, out] key
6319  *   Flow matcher value.
6320  * @param[in] item
6321  *   Flow pattern to translate.
6322  * @param[in] inner
6323  *   Item is inner pattern.
6324  */
6325 static void
6326 flow_dv_translate_item_eth(void *matcher, void *key,
6327                            const struct rte_flow_item *item, int inner,
6328                            uint32_t group)
6329 {
6330         const struct rte_flow_item_eth *eth_m = item->mask;
6331         const struct rte_flow_item_eth *eth_v = item->spec;
6332         const struct rte_flow_item_eth nic_mask = {
6333                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6334                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6335                 .type = RTE_BE16(0xffff),
6336                 .has_vlan = 0,
6337         };
6338         void *hdrs_m;
6339         void *hdrs_v;
6340         char *l24_v;
6341         unsigned int i;
6342
6343         if (!eth_v)
6344                 return;
6345         if (!eth_m)
6346                 eth_m = &nic_mask;
6347         if (inner) {
6348                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6349                                          inner_headers);
6350                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6351         } else {
6352                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6353                                          outer_headers);
6354                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6355         }
6356         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6357                &eth_m->dst, sizeof(eth_m->dst));
6358         /* The value must be in the range of the mask. */
6359         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6360         for (i = 0; i < sizeof(eth_m->dst); ++i)
6361                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6362         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6363                &eth_m->src, sizeof(eth_m->src));
6364         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6365         /* The value must be in the range of the mask. */
6366         for (i = 0; i < sizeof(eth_m->dst); ++i)
6367                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6368         /*
6369          * HW supports match on one Ethertype, the Ethertype following the last
6370          * VLAN tag of the packet (see PRM).
6371          * Set match on ethertype only if ETH header is not followed by VLAN.
6372          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6373          * ethertype, and use ip_version field instead.
6374          * eCPRI over Ether layer will use type value 0xAEFE.
6375          */
6376         if (eth_m->type == 0xFFFF) {
6377                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6378                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6379                 switch (eth_v->type) {
6380                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6381                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6382                         return;
6383                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6384                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6385                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6386                         return;
6387                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6388                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6389                         return;
6390                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6391                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6392                         return;
6393                 default:
6394                         break;
6395                 }
6396         }
6397         if (eth_m->has_vlan) {
6398                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6399                 if (eth_v->has_vlan) {
6400                         /*
6401                          * Here, when also has_more_vlan field in VLAN item is
6402                          * not set, only single-tagged packets will be matched.
6403                          */
6404                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6405                         return;
6406                 }
6407         }
6408         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6409                  rte_be_to_cpu_16(eth_m->type));
6410         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6411         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6412 }
6413
6414 /**
6415  * Add VLAN item to matcher and to the value.
6416  *
6417  * @param[in, out] dev_flow
6418  *   Flow descriptor.
6419  * @param[in, out] matcher
6420  *   Flow matcher.
6421  * @param[in, out] key
6422  *   Flow matcher value.
6423  * @param[in] item
6424  *   Flow pattern to translate.
6425  * @param[in] inner
6426  *   Item is inner pattern.
6427  */
6428 static void
6429 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6430                             void *matcher, void *key,
6431                             const struct rte_flow_item *item,
6432                             int inner, uint32_t group)
6433 {
6434         const struct rte_flow_item_vlan *vlan_m = item->mask;
6435         const struct rte_flow_item_vlan *vlan_v = item->spec;
6436         void *hdrs_m;
6437         void *hdrs_v;
6438         uint16_t tci_m;
6439         uint16_t tci_v;
6440
6441         if (inner) {
6442                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6443                                          inner_headers);
6444                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6445         } else {
6446                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6447                                          outer_headers);
6448                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6449                 /*
6450                  * This is workaround, masks are not supported,
6451                  * and pre-validated.
6452                  */
6453                 if (vlan_v)
6454                         dev_flow->handle->vf_vlan.tag =
6455                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6456         }
6457         /*
6458          * When VLAN item exists in flow, mark packet as tagged,
6459          * even if TCI is not specified.
6460          */
6461         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6462                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6463                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6464         }
6465         if (!vlan_v)
6466                 return;
6467         if (!vlan_m)
6468                 vlan_m = &rte_flow_item_vlan_mask;
6469         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6470         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6471         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6472         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6473         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6474         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6475         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6476         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6477         /*
6478          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6479          * ethertype, and use ip_version field instead.
6480          */
6481         if (vlan_m->inner_type == 0xFFFF) {
6482                 switch (vlan_v->inner_type) {
6483                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6484                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6485                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6486                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6487                         return;
6488                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6489                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6490                         return;
6491                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6492                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6493                         return;
6494                 default:
6495                         break;
6496                 }
6497         }
6498         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6499                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6500                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6501                 /* Only one vlan_tag bit can be set. */
6502                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6503                 return;
6504         }
6505         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6506                  rte_be_to_cpu_16(vlan_m->inner_type));
6507         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6508                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6509 }
6510
6511 /**
6512  * Add IPV4 item to matcher and to the value.
6513  *
6514  * @param[in, out] matcher
6515  *   Flow matcher.
6516  * @param[in, out] key
6517  *   Flow matcher value.
6518  * @param[in] item
6519  *   Flow pattern to translate.
6520  * @param[in] inner
6521  *   Item is inner pattern.
6522  * @param[in] group
6523  *   The group to insert the rule.
6524  */
6525 static void
6526 flow_dv_translate_item_ipv4(void *matcher, void *key,
6527                             const struct rte_flow_item *item,
6528                             int inner, uint32_t group)
6529 {
6530         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6531         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6532         const struct rte_flow_item_ipv4 nic_mask = {
6533                 .hdr = {
6534                         .src_addr = RTE_BE32(0xffffffff),
6535                         .dst_addr = RTE_BE32(0xffffffff),
6536                         .type_of_service = 0xff,
6537                         .next_proto_id = 0xff,
6538                         .time_to_live = 0xff,
6539                 },
6540         };
6541         void *headers_m;
6542         void *headers_v;
6543         char *l24_m;
6544         char *l24_v;
6545         uint8_t tos;
6546
6547         if (inner) {
6548                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6549                                          inner_headers);
6550                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6551         } else {
6552                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6553                                          outer_headers);
6554                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6555         }
6556         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6557         if (!ipv4_v)
6558                 return;
6559         if (!ipv4_m)
6560                 ipv4_m = &nic_mask;
6561         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6562                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6563         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6564                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6565         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6566         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6567         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6568                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6569         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6570                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6571         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6572         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6573         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6574         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6575                  ipv4_m->hdr.type_of_service);
6576         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6577         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6578                  ipv4_m->hdr.type_of_service >> 2);
6579         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6580         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6581                  ipv4_m->hdr.next_proto_id);
6582         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6583                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6584         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6585                  ipv4_m->hdr.time_to_live);
6586         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6587                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6588         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6589                  !!(ipv4_m->hdr.fragment_offset));
6590         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6591                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6592 }
6593
6594 /**
6595  * Add IPV6 item to matcher and to the value.
6596  *
6597  * @param[in, out] matcher
6598  *   Flow matcher.
6599  * @param[in, out] key
6600  *   Flow matcher value.
6601  * @param[in] item
6602  *   Flow pattern to translate.
6603  * @param[in] inner
6604  *   Item is inner pattern.
6605  * @param[in] group
6606  *   The group to insert the rule.
6607  */
6608 static void
6609 flow_dv_translate_item_ipv6(void *matcher, void *key,
6610                             const struct rte_flow_item *item,
6611                             int inner, uint32_t group)
6612 {
6613         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6614         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6615         const struct rte_flow_item_ipv6 nic_mask = {
6616                 .hdr = {
6617                         .src_addr =
6618                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6619                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6620                         .dst_addr =
6621                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6622                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6623                         .vtc_flow = RTE_BE32(0xffffffff),
6624                         .proto = 0xff,
6625                         .hop_limits = 0xff,
6626                 },
6627         };
6628         void *headers_m;
6629         void *headers_v;
6630         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6631         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6632         char *l24_m;
6633         char *l24_v;
6634         uint32_t vtc_m;
6635         uint32_t vtc_v;
6636         int i;
6637         int size;
6638
6639         if (inner) {
6640                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6641                                          inner_headers);
6642                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6643         } else {
6644                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6645                                          outer_headers);
6646                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6647         }
6648         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6649         if (!ipv6_v)
6650                 return;
6651         if (!ipv6_m)
6652                 ipv6_m = &nic_mask;
6653         size = sizeof(ipv6_m->hdr.dst_addr);
6654         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6655                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6656         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6657                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6658         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6659         for (i = 0; i < size; ++i)
6660                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6661         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6662                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6663         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6664                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6665         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6666         for (i = 0; i < size; ++i)
6667                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6668         /* TOS. */
6669         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6670         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6671         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6672         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6673         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6674         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6675         /* Label. */
6676         if (inner) {
6677                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6678                          vtc_m);
6679                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6680                          vtc_v);
6681         } else {
6682                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6683                          vtc_m);
6684                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6685                          vtc_v);
6686         }
6687         /* Protocol. */
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6689                  ipv6_m->hdr.proto);
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6691                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6692         /* Hop limit. */
6693         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6694                  ipv6_m->hdr.hop_limits);
6695         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6696                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6697         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6698                  !!(ipv6_m->has_frag_ext));
6699         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6700                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6701 }
6702
6703 /**
6704  * Add IPV6 fragment extension item to matcher and to the value.
6705  *
6706  * @param[in, out] matcher
6707  *   Flow matcher.
6708  * @param[in, out] key
6709  *   Flow matcher value.
6710  * @param[in] item
6711  *   Flow pattern to translate.
6712  * @param[in] inner
6713  *   Item is inner pattern.
6714  */
6715 static void
6716 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6717                                      const struct rte_flow_item *item,
6718                                      int inner)
6719 {
6720         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6721         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6722         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6723                 .hdr = {
6724                         .next_header = 0xff,
6725                         .frag_data = RTE_BE16(0xffff),
6726                 },
6727         };
6728         void *headers_m;
6729         void *headers_v;
6730
6731         if (inner) {
6732                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6733                                          inner_headers);
6734                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6735         } else {
6736                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6737                                          outer_headers);
6738                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6739         }
6740         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6741         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6742         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6743         if (!ipv6_frag_ext_v)
6744                 return;
6745         if (!ipv6_frag_ext_m)
6746                 ipv6_frag_ext_m = &nic_mask;
6747         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6748                  ipv6_frag_ext_m->hdr.next_header);
6749         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6750                  ipv6_frag_ext_v->hdr.next_header &
6751                  ipv6_frag_ext_m->hdr.next_header);
6752 }
6753
6754 /**
6755  * Add TCP item to matcher and to the value.
6756  *
6757  * @param[in, out] matcher
6758  *   Flow matcher.
6759  * @param[in, out] key
6760  *   Flow matcher value.
6761  * @param[in] item
6762  *   Flow pattern to translate.
6763  * @param[in] inner
6764  *   Item is inner pattern.
6765  */
6766 static void
6767 flow_dv_translate_item_tcp(void *matcher, void *key,
6768                            const struct rte_flow_item *item,
6769                            int inner)
6770 {
6771         const struct rte_flow_item_tcp *tcp_m = item->mask;
6772         const struct rte_flow_item_tcp *tcp_v = item->spec;
6773         void *headers_m;
6774         void *headers_v;
6775
6776         if (inner) {
6777                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6778                                          inner_headers);
6779                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6780         } else {
6781                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6782                                          outer_headers);
6783                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6784         }
6785         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6786         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6787         if (!tcp_v)
6788                 return;
6789         if (!tcp_m)
6790                 tcp_m = &rte_flow_item_tcp_mask;
6791         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6792                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6793         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6794                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6795         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6796                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6797         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6798                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6799         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6800                  tcp_m->hdr.tcp_flags);
6801         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6802                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6803 }
6804
6805 /**
6806  * Add UDP item to matcher and to the value.
6807  *
6808  * @param[in, out] matcher
6809  *   Flow matcher.
6810  * @param[in, out] key
6811  *   Flow matcher value.
6812  * @param[in] item
6813  *   Flow pattern to translate.
6814  * @param[in] inner
6815  *   Item is inner pattern.
6816  */
6817 static void
6818 flow_dv_translate_item_udp(void *matcher, void *key,
6819                            const struct rte_flow_item *item,
6820                            int inner)
6821 {
6822         const struct rte_flow_item_udp *udp_m = item->mask;
6823         const struct rte_flow_item_udp *udp_v = item->spec;
6824         void *headers_m;
6825         void *headers_v;
6826
6827         if (inner) {
6828                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6829                                          inner_headers);
6830                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6831         } else {
6832                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6833                                          outer_headers);
6834                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6835         }
6836         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6837         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6838         if (!udp_v)
6839                 return;
6840         if (!udp_m)
6841                 udp_m = &rte_flow_item_udp_mask;
6842         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6843                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6845                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6846         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6847                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6848         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6849                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6850 }
6851
6852 /**
6853  * Add GRE optional Key item to matcher and to the value.
6854  *
6855  * @param[in, out] matcher
6856  *   Flow matcher.
6857  * @param[in, out] key
6858  *   Flow matcher value.
6859  * @param[in] item
6860  *   Flow pattern to translate.
6861  * @param[in] inner
6862  *   Item is inner pattern.
6863  */
6864 static void
6865 flow_dv_translate_item_gre_key(void *matcher, void *key,
6866                                    const struct rte_flow_item *item)
6867 {
6868         const rte_be32_t *key_m = item->mask;
6869         const rte_be32_t *key_v = item->spec;
6870         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6871         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6872         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6873
6874         /* GRE K bit must be on and should already be validated */
6875         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6876         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6877         if (!key_v)
6878                 return;
6879         if (!key_m)
6880                 key_m = &gre_key_default_mask;
6881         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6882                  rte_be_to_cpu_32(*key_m) >> 8);
6883         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6884                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6885         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6886                  rte_be_to_cpu_32(*key_m) & 0xFF);
6887         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6888                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6889 }
6890
6891 /**
6892  * Add GRE item to matcher and to the value.
6893  *
6894  * @param[in, out] matcher
6895  *   Flow matcher.
6896  * @param[in, out] key
6897  *   Flow matcher value.
6898  * @param[in] item
6899  *   Flow pattern to translate.
6900  * @param[in] inner
6901  *   Item is inner pattern.
6902  */
6903 static void
6904 flow_dv_translate_item_gre(void *matcher, void *key,
6905                            const struct rte_flow_item *item,
6906                            int inner)
6907 {
6908         const struct rte_flow_item_gre *gre_m = item->mask;
6909         const struct rte_flow_item_gre *gre_v = item->spec;
6910         void *headers_m;
6911         void *headers_v;
6912         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6913         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6914         struct {
6915                 union {
6916                         __extension__
6917                         struct {
6918                                 uint16_t version:3;
6919                                 uint16_t rsvd0:9;
6920                                 uint16_t s_present:1;
6921                                 uint16_t k_present:1;
6922                                 uint16_t rsvd_bit1:1;
6923                                 uint16_t c_present:1;
6924                         };
6925                         uint16_t value;
6926                 };
6927         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6928
6929         if (inner) {
6930                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6931                                          inner_headers);
6932                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6933         } else {
6934                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6935                                          outer_headers);
6936                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6937         }
6938         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6939         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6940         if (!gre_v)
6941                 return;
6942         if (!gre_m)
6943                 gre_m = &rte_flow_item_gre_mask;
6944         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6945                  rte_be_to_cpu_16(gre_m->protocol));
6946         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6947                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6948         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6949         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6950         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6951                  gre_crks_rsvd0_ver_m.c_present);
6952         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6953                  gre_crks_rsvd0_ver_v.c_present &
6954                  gre_crks_rsvd0_ver_m.c_present);
6955         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6956                  gre_crks_rsvd0_ver_m.k_present);
6957         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6958                  gre_crks_rsvd0_ver_v.k_present &
6959                  gre_crks_rsvd0_ver_m.k_present);
6960         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6961                  gre_crks_rsvd0_ver_m.s_present);
6962         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6963                  gre_crks_rsvd0_ver_v.s_present &
6964                  gre_crks_rsvd0_ver_m.s_present);
6965 }
6966
6967 /**
6968  * Add NVGRE item to matcher and to the value.
6969  *
6970  * @param[in, out] matcher
6971  *   Flow matcher.
6972  * @param[in, out] key
6973  *   Flow matcher value.
6974  * @param[in] item
6975  *   Flow pattern to translate.
6976  * @param[in] inner
6977  *   Item is inner pattern.
6978  */
6979 static void
6980 flow_dv_translate_item_nvgre(void *matcher, void *key,
6981                              const struct rte_flow_item *item,
6982                              int inner)
6983 {
6984         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6985         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6986         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6987         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6988         const char *tni_flow_id_m;
6989         const char *tni_flow_id_v;
6990         char *gre_key_m;
6991         char *gre_key_v;
6992         int size;
6993         int i;
6994
6995         /* For NVGRE, GRE header fields must be set with defined values. */
6996         const struct rte_flow_item_gre gre_spec = {
6997                 .c_rsvd0_ver = RTE_BE16(0x2000),
6998                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6999         };
7000         const struct rte_flow_item_gre gre_mask = {
7001                 .c_rsvd0_ver = RTE_BE16(0xB000),
7002                 .protocol = RTE_BE16(UINT16_MAX),
7003         };
7004         const struct rte_flow_item gre_item = {
7005                 .spec = &gre_spec,
7006                 .mask = &gre_mask,
7007                 .last = NULL,
7008         };
7009         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7010         if (!nvgre_v)
7011                 return;
7012         if (!nvgre_m)
7013                 nvgre_m = &rte_flow_item_nvgre_mask;
7014         tni_flow_id_m = (const char *)nvgre_m->tni;
7015         tni_flow_id_v = (const char *)nvgre_v->tni;
7016         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7017         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7018         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7019         memcpy(gre_key_m, tni_flow_id_m, size);
7020         for (i = 0; i < size; ++i)
7021                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7022 }
7023
7024 /**
7025  * Add VXLAN item to matcher and to the value.
7026  *
7027  * @param[in, out] matcher
7028  *   Flow matcher.
7029  * @param[in, out] key
7030  *   Flow matcher value.
7031  * @param[in] item
7032  *   Flow pattern to translate.
7033  * @param[in] inner
7034  *   Item is inner pattern.
7035  */
7036 static void
7037 flow_dv_translate_item_vxlan(void *matcher, void *key,
7038                              const struct rte_flow_item *item,
7039                              int inner)
7040 {
7041         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7042         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7043         void *headers_m;
7044         void *headers_v;
7045         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7046         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7047         char *vni_m;
7048         char *vni_v;
7049         uint16_t dport;
7050         int size;
7051         int i;
7052
7053         if (inner) {
7054                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7055                                          inner_headers);
7056                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7057         } else {
7058                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7059                                          outer_headers);
7060                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7061         }
7062         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7063                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7064         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7065                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7066                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7067         }
7068         if (!vxlan_v)
7069                 return;
7070         if (!vxlan_m)
7071                 vxlan_m = &rte_flow_item_vxlan_mask;
7072         size = sizeof(vxlan_m->vni);
7073         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7074         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7075         memcpy(vni_m, vxlan_m->vni, size);
7076         for (i = 0; i < size; ++i)
7077                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7078 }
7079
7080 /**
7081  * Add VXLAN-GPE item to matcher and to the value.
7082  *
7083  * @param[in, out] matcher
7084  *   Flow matcher.
7085  * @param[in, out] key
7086  *   Flow matcher value.
7087  * @param[in] item
7088  *   Flow pattern to translate.
7089  * @param[in] inner
7090  *   Item is inner pattern.
7091  */
7092
7093 static void
7094 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7095                                  const struct rte_flow_item *item, int inner)
7096 {
7097         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7098         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7099         void *headers_m;
7100         void *headers_v;
7101         void *misc_m =
7102                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7103         void *misc_v =
7104                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7105         char *vni_m;
7106         char *vni_v;
7107         uint16_t dport;
7108         int size;
7109         int i;
7110         uint8_t flags_m = 0xff;
7111         uint8_t flags_v = 0xc;
7112
7113         if (inner) {
7114                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7115                                          inner_headers);
7116                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7117         } else {
7118                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7119                                          outer_headers);
7120                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7121         }
7122         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7123                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7124         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7125                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7126                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7127         }
7128         if (!vxlan_v)
7129                 return;
7130         if (!vxlan_m)
7131                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7132         size = sizeof(vxlan_m->vni);
7133         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7134         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7135         memcpy(vni_m, vxlan_m->vni, size);
7136         for (i = 0; i < size; ++i)
7137                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7138         if (vxlan_m->flags) {
7139                 flags_m = vxlan_m->flags;
7140                 flags_v = vxlan_v->flags;
7141         }
7142         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7143         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7144         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7145                  vxlan_m->protocol);
7146         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7147                  vxlan_v->protocol);
7148 }
7149
7150 /**
7151  * Add Geneve item to matcher and to the value.
7152  *
7153  * @param[in, out] matcher
7154  *   Flow matcher.
7155  * @param[in, out] key
7156  *   Flow matcher value.
7157  * @param[in] item
7158  *   Flow pattern to translate.
7159  * @param[in] inner
7160  *   Item is inner pattern.
7161  */
7162
7163 static void
7164 flow_dv_translate_item_geneve(void *matcher, void *key,
7165                               const struct rte_flow_item *item, int inner)
7166 {
7167         const struct rte_flow_item_geneve *geneve_m = item->mask;
7168         const struct rte_flow_item_geneve *geneve_v = item->spec;
7169         void *headers_m;
7170         void *headers_v;
7171         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7172         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7173         uint16_t dport;
7174         uint16_t gbhdr_m;
7175         uint16_t gbhdr_v;
7176         char *vni_m;
7177         char *vni_v;
7178         size_t size, i;
7179
7180         if (inner) {
7181                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7182                                          inner_headers);
7183                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7184         } else {
7185                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7186                                          outer_headers);
7187                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7188         }
7189         dport = MLX5_UDP_PORT_GENEVE;
7190         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7191                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7192                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7193         }
7194         if (!geneve_v)
7195                 return;
7196         if (!geneve_m)
7197                 geneve_m = &rte_flow_item_geneve_mask;
7198         size = sizeof(geneve_m->vni);
7199         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7200         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7201         memcpy(vni_m, geneve_m->vni, size);
7202         for (i = 0; i < size; ++i)
7203                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7204         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7205                  rte_be_to_cpu_16(geneve_m->protocol));
7206         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7207                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7208         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7209         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7210         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7211                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7212         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7213                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7214         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7215                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7216         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7217                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7218                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7219 }
7220
7221 /**
7222  * Add MPLS item to matcher and to the value.
7223  *
7224  * @param[in, out] matcher
7225  *   Flow matcher.
7226  * @param[in, out] key
7227  *   Flow matcher value.
7228  * @param[in] item
7229  *   Flow pattern to translate.
7230  * @param[in] prev_layer
7231  *   The protocol layer indicated in previous item.
7232  * @param[in] inner
7233  *   Item is inner pattern.
7234  */
7235 static void
7236 flow_dv_translate_item_mpls(void *matcher, void *key,
7237                             const struct rte_flow_item *item,
7238                             uint64_t prev_layer,
7239                             int inner)
7240 {
7241         const uint32_t *in_mpls_m = item->mask;
7242         const uint32_t *in_mpls_v = item->spec;
7243         uint32_t *out_mpls_m = 0;
7244         uint32_t *out_mpls_v = 0;
7245         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7246         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7247         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7248                                      misc_parameters_2);
7249         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7250         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7251         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7252
7253         switch (prev_layer) {
7254         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7255                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7256                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7257                          MLX5_UDP_PORT_MPLS);
7258                 break;
7259         case MLX5_FLOW_LAYER_GRE:
7260                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7261                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7262                          RTE_ETHER_TYPE_MPLS);
7263                 break;
7264         default:
7265                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7266                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7267                          IPPROTO_MPLS);
7268                 break;
7269         }
7270         if (!in_mpls_v)
7271                 return;
7272         if (!in_mpls_m)
7273                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7274         switch (prev_layer) {
7275         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7276                 out_mpls_m =
7277                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7278                                                  outer_first_mpls_over_udp);
7279                 out_mpls_v =
7280                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7281                                                  outer_first_mpls_over_udp);
7282                 break;
7283         case MLX5_FLOW_LAYER_GRE:
7284                 out_mpls_m =
7285                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7286                                                  outer_first_mpls_over_gre);
7287                 out_mpls_v =
7288                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7289                                                  outer_first_mpls_over_gre);
7290                 break;
7291         default:
7292                 /* Inner MPLS not over GRE is not supported. */
7293                 if (!inner) {
7294                         out_mpls_m =
7295                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7296                                                          misc2_m,
7297                                                          outer_first_mpls);
7298                         out_mpls_v =
7299                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7300                                                          misc2_v,
7301                                                          outer_first_mpls);
7302                 }
7303                 break;
7304         }
7305         if (out_mpls_m && out_mpls_v) {
7306                 *out_mpls_m = *in_mpls_m;
7307                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7308         }
7309 }
7310
7311 /**
7312  * Add metadata register item to matcher
7313  *
7314  * @param[in, out] matcher
7315  *   Flow matcher.
7316  * @param[in, out] key
7317  *   Flow matcher value.
7318  * @param[in] reg_type
7319  *   Type of device metadata register
7320  * @param[in] value
7321  *   Register value
7322  * @param[in] mask
7323  *   Register mask
7324  */
7325 static void
7326 flow_dv_match_meta_reg(void *matcher, void *key,
7327                        enum modify_reg reg_type,
7328                        uint32_t data, uint32_t mask)
7329 {
7330         void *misc2_m =
7331                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7332         void *misc2_v =
7333                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7334         uint32_t temp;
7335
7336         data &= mask;
7337         switch (reg_type) {
7338         case REG_A:
7339                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7340                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7341                 break;
7342         case REG_B:
7343                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7344                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7345                 break;
7346         case REG_C_0:
7347                 /*
7348                  * The metadata register C0 field might be divided into
7349                  * source vport index and META item value, we should set
7350                  * this field according to specified mask, not as whole one.
7351                  */
7352                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7353                 temp |= mask;
7354                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7355                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7356                 temp &= ~mask;
7357                 temp |= data;
7358                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7359                 break;
7360         case REG_C_1:
7361                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7362                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7363                 break;
7364         case REG_C_2:
7365                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7366                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7367                 break;
7368         case REG_C_3:
7369                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7370                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7371                 break;
7372         case REG_C_4:
7373                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7374                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7375                 break;
7376         case REG_C_5:
7377                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7378                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7379                 break;
7380         case REG_C_6:
7381                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7382                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7383                 break;
7384         case REG_C_7:
7385                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7386                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7387                 break;
7388         default:
7389                 MLX5_ASSERT(false);
7390                 break;
7391         }
7392 }
7393
7394 /**
7395  * Add MARK item to matcher
7396  *
7397  * @param[in] dev
7398  *   The device to configure through.
7399  * @param[in, out] matcher
7400  *   Flow matcher.
7401  * @param[in, out] key
7402  *   Flow matcher value.
7403  * @param[in] item
7404  *   Flow pattern to translate.
7405  */
7406 static void
7407 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7408                             void *matcher, void *key,
7409                             const struct rte_flow_item *item)
7410 {
7411         struct mlx5_priv *priv = dev->data->dev_private;
7412         const struct rte_flow_item_mark *mark;
7413         uint32_t value;
7414         uint32_t mask;
7415
7416         mark = item->mask ? (const void *)item->mask :
7417                             &rte_flow_item_mark_mask;
7418         mask = mark->id & priv->sh->dv_mark_mask;
7419         mark = (const void *)item->spec;
7420         MLX5_ASSERT(mark);
7421         value = mark->id & priv->sh->dv_mark_mask & mask;
7422         if (mask) {
7423                 enum modify_reg reg;
7424
7425                 /* Get the metadata register index for the mark. */
7426                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7427                 MLX5_ASSERT(reg > 0);
7428                 if (reg == REG_C_0) {
7429                         struct mlx5_priv *priv = dev->data->dev_private;
7430                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7431                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7432
7433                         mask &= msk_c0;
7434                         mask <<= shl_c0;
7435                         value <<= shl_c0;
7436                 }
7437                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7438         }
7439 }
7440
7441 /**
7442  * Add META item to matcher
7443  *
7444  * @param[in] dev
7445  *   The devich to configure through.
7446  * @param[in, out] matcher
7447  *   Flow matcher.
7448  * @param[in, out] key
7449  *   Flow matcher value.
7450  * @param[in] attr
7451  *   Attributes of flow that includes this item.
7452  * @param[in] item
7453  *   Flow pattern to translate.
7454  */
7455 static void
7456 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7457                             void *matcher, void *key,
7458                             const struct rte_flow_attr *attr,
7459                             const struct rte_flow_item *item)
7460 {
7461         const struct rte_flow_item_meta *meta_m;
7462         const struct rte_flow_item_meta *meta_v;
7463
7464         meta_m = (const void *)item->mask;
7465         if (!meta_m)
7466                 meta_m = &rte_flow_item_meta_mask;
7467         meta_v = (const void *)item->spec;
7468         if (meta_v) {
7469                 int reg;
7470                 uint32_t value = meta_v->data;
7471                 uint32_t mask = meta_m->data;
7472
7473                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7474                 if (reg < 0)
7475                         return;
7476                 MLX5_ASSERT(reg != REG_NON);
7477                 /*
7478                  * In datapath code there is no endianness
7479                  * coversions for perfromance reasons, all
7480                  * pattern conversions are done in rte_flow.
7481                  */
7482                 value = rte_cpu_to_be_32(value);
7483                 mask = rte_cpu_to_be_32(mask);
7484                 if (reg == REG_C_0) {
7485                         struct mlx5_priv *priv = dev->data->dev_private;
7486                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7487                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7488 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7489                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7490
7491                         value >>= shr_c0;
7492                         mask >>= shr_c0;
7493 #endif
7494                         value <<= shl_c0;
7495                         mask <<= shl_c0;
7496                         MLX5_ASSERT(msk_c0);
7497                         MLX5_ASSERT(!(~msk_c0 & mask));
7498                 }
7499                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7500         }
7501 }
7502
7503 /**
7504  * Add vport metadata Reg C0 item to matcher
7505  *
7506  * @param[in, out] matcher
7507  *   Flow matcher.
7508  * @param[in, out] key
7509  *   Flow matcher value.
7510  * @param[in] reg
7511  *   Flow pattern to translate.
7512  */
7513 static void
7514 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7515                                   uint32_t value, uint32_t mask)
7516 {
7517         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7518 }
7519
7520 /**
7521  * Add tag item to matcher
7522  *
7523  * @param[in] dev
7524  *   The devich to configure through.
7525  * @param[in, out] matcher
7526  *   Flow matcher.
7527  * @param[in, out] key
7528  *   Flow matcher value.
7529  * @param[in] item
7530  *   Flow pattern to translate.
7531  */
7532 static void
7533 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7534                                 void *matcher, void *key,
7535                                 const struct rte_flow_item *item)
7536 {
7537         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7538         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7539         uint32_t mask, value;
7540
7541         MLX5_ASSERT(tag_v);
7542         value = tag_v->data;
7543         mask = tag_m ? tag_m->data : UINT32_MAX;
7544         if (tag_v->id == REG_C_0) {
7545                 struct mlx5_priv *priv = dev->data->dev_private;
7546                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7547                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7548
7549                 mask &= msk_c0;
7550                 mask <<= shl_c0;
7551                 value <<= shl_c0;
7552         }
7553         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7554 }
7555
7556 /**
7557  * Add TAG item to matcher
7558  *
7559  * @param[in] dev
7560  *   The devich to configure through.
7561  * @param[in, out] matcher
7562  *   Flow matcher.
7563  * @param[in, out] key
7564  *   Flow matcher value.
7565  * @param[in] item
7566  *   Flow pattern to translate.
7567  */
7568 static void
7569 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7570                            void *matcher, void *key,
7571                            const struct rte_flow_item *item)
7572 {
7573         const struct rte_flow_item_tag *tag_v = item->spec;
7574         const struct rte_flow_item_tag *tag_m = item->mask;
7575         enum modify_reg reg;
7576
7577         MLX5_ASSERT(tag_v);
7578         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7579         /* Get the metadata register index for the tag. */
7580         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7581         MLX5_ASSERT(reg > 0);
7582         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7583 }
7584
7585 /**
7586  * Add source vport match to the specified matcher.
7587  *
7588  * @param[in, out] matcher
7589  *   Flow matcher.
7590  * @param[in, out] key
7591  *   Flow matcher value.
7592  * @param[in] port
7593  *   Source vport value to match
7594  * @param[in] mask
7595  *   Mask
7596  */
7597 static void
7598 flow_dv_translate_item_source_vport(void *matcher, void *key,
7599                                     int16_t port, uint16_t mask)
7600 {
7601         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7602         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7603
7604         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7605         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7606 }
7607
7608 /**
7609  * Translate port-id item to eswitch match on  port-id.
7610  *
7611  * @param[in] dev
7612  *   The devich to configure through.
7613  * @param[in, out] matcher
7614  *   Flow matcher.
7615  * @param[in, out] key
7616  *   Flow matcher value.
7617  * @param[in] item
7618  *   Flow pattern to translate.
7619  * @param[in]
7620  *   Flow attributes.
7621  *
7622  * @return
7623  *   0 on success, a negative errno value otherwise.
7624  */
7625 static int
7626 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7627                                void *key, const struct rte_flow_item *item,
7628                                const struct rte_flow_attr *attr)
7629 {
7630         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7631         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7632         struct mlx5_priv *priv;
7633         uint16_t mask, id;
7634
7635         mask = pid_m ? pid_m->id : 0xffff;
7636         id = pid_v ? pid_v->id : dev->data->port_id;
7637         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7638         if (!priv)
7639                 return -rte_errno;
7640         /*
7641          * Translate to vport field or to metadata, depending on mode.
7642          * Kernel can use either misc.source_port or half of C0 metadata
7643          * register.
7644          */
7645         if (priv->vport_meta_mask) {
7646                 /*
7647                  * Provide the hint for SW steering library
7648                  * to insert the flow into ingress domain and
7649                  * save the extra vport match.
7650                  */
7651                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7652                     priv->pf_bond < 0 && attr->transfer)
7653                         flow_dv_translate_item_source_vport
7654                                 (matcher, key, priv->vport_id, mask);
7655                 else
7656                         flow_dv_translate_item_meta_vport
7657                                 (matcher, key,
7658                                  priv->vport_meta_tag,
7659                                  priv->vport_meta_mask);
7660         } else {
7661                 flow_dv_translate_item_source_vport(matcher, key,
7662                                                     priv->vport_id, mask);
7663         }
7664         return 0;
7665 }
7666
7667 /**
7668  * Add ICMP6 item to matcher and to the value.
7669  *
7670  * @param[in, out] matcher
7671  *   Flow matcher.
7672  * @param[in, out] key
7673  *   Flow matcher value.
7674  * @param[in] item
7675  *   Flow pattern to translate.
7676  * @param[in] inner
7677  *   Item is inner pattern.
7678  */
7679 static void
7680 flow_dv_translate_item_icmp6(void *matcher, void *key,
7681                               const struct rte_flow_item *item,
7682                               int inner)
7683 {
7684         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7685         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7686         void *headers_m;
7687         void *headers_v;
7688         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7689                                      misc_parameters_3);
7690         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7691         if (inner) {
7692                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7693                                          inner_headers);
7694                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7695         } else {
7696                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7697                                          outer_headers);
7698                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7699         }
7700         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7701         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7702         if (!icmp6_v)
7703                 return;
7704         if (!icmp6_m)
7705                 icmp6_m = &rte_flow_item_icmp6_mask;
7706         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7707         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7708                  icmp6_v->type & icmp6_m->type);
7709         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7710         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7711                  icmp6_v->code & icmp6_m->code);
7712 }
7713
7714 /**
7715  * Add ICMP item to matcher and to the value.
7716  *
7717  * @param[in, out] matcher
7718  *   Flow matcher.
7719  * @param[in, out] key
7720  *   Flow matcher value.
7721  * @param[in] item
7722  *   Flow pattern to translate.
7723  * @param[in] inner
7724  *   Item is inner pattern.
7725  */
7726 static void
7727 flow_dv_translate_item_icmp(void *matcher, void *key,
7728                             const struct rte_flow_item *item,
7729                             int inner)
7730 {
7731         const struct rte_flow_item_icmp *icmp_m = item->mask;
7732         const struct rte_flow_item_icmp *icmp_v = item->spec;
7733         uint32_t icmp_header_data_m = 0;
7734         uint32_t icmp_header_data_v = 0;
7735         void *headers_m;
7736         void *headers_v;
7737         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7738                                      misc_parameters_3);
7739         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7740         if (inner) {
7741                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7742                                          inner_headers);
7743                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7744         } else {
7745                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7746                                          outer_headers);
7747                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7748         }
7749         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7750         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7751         if (!icmp_v)
7752                 return;
7753         if (!icmp_m)
7754                 icmp_m = &rte_flow_item_icmp_mask;
7755         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7756                  icmp_m->hdr.icmp_type);
7757         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7758                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7759         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7760                  icmp_m->hdr.icmp_code);
7761         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7762                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7763         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7764         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7765         if (icmp_header_data_m) {
7766                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7767                 icmp_header_data_v |=
7768                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7769                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7770                          icmp_header_data_m);
7771                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7772                          icmp_header_data_v & icmp_header_data_m);
7773         }
7774 }
7775
7776 /**
7777  * Add GTP item to matcher and to the value.
7778  *
7779  * @param[in, out] matcher
7780  *   Flow matcher.
7781  * @param[in, out] key
7782  *   Flow matcher value.
7783  * @param[in] item
7784  *   Flow pattern to translate.
7785  * @param[in] inner
7786  *   Item is inner pattern.
7787  */
7788 static void
7789 flow_dv_translate_item_gtp(void *matcher, void *key,
7790                            const struct rte_flow_item *item, int inner)
7791 {
7792         const struct rte_flow_item_gtp *gtp_m = item->mask;
7793         const struct rte_flow_item_gtp *gtp_v = item->spec;
7794         void *headers_m;
7795         void *headers_v;
7796         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7797                                      misc_parameters_3);
7798         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7799         uint16_t dport = RTE_GTPU_UDP_PORT;
7800
7801         if (inner) {
7802                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7803                                          inner_headers);
7804                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7805         } else {
7806                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7807                                          outer_headers);
7808                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7809         }
7810         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7811                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7812                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7813         }
7814         if (!gtp_v)
7815                 return;
7816         if (!gtp_m)
7817                 gtp_m = &rte_flow_item_gtp_mask;
7818         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7819                  gtp_m->v_pt_rsv_flags);
7820         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7821                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7822         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7823         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7824                  gtp_v->msg_type & gtp_m->msg_type);
7825         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7826                  rte_be_to_cpu_32(gtp_m->teid));
7827         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7828                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7829 }
7830
7831 /**
7832  * Add eCPRI item to matcher and to the value.
7833  *
7834  * @param[in] dev
7835  *   The devich to configure through.
7836  * @param[in, out] matcher
7837  *   Flow matcher.
7838  * @param[in, out] key
7839  *   Flow matcher value.
7840  * @param[in] item
7841  *   Flow pattern to translate.
7842  * @param[in] samples
7843  *   Sample IDs to be used in the matching.
7844  */
7845 static void
7846 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7847                              void *key, const struct rte_flow_item *item)
7848 {
7849         struct mlx5_priv *priv = dev->data->dev_private;
7850         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7851         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7852         struct rte_ecpri_common_hdr common;
7853         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7854                                      misc_parameters_4);
7855         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7856         uint32_t *samples;
7857         void *dw_m;
7858         void *dw_v;
7859
7860         if (!ecpri_v)
7861                 return;
7862         if (!ecpri_m)
7863                 ecpri_m = &rte_flow_item_ecpri_mask;
7864         /*
7865          * Maximal four DW samples are supported in a single matching now.
7866          * Two are used now for a eCPRI matching:
7867          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7868          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7869          *    if any.
7870          */
7871         if (!ecpri_m->hdr.common.u32)
7872                 return;
7873         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7874         /* Need to take the whole DW as the mask to fill the entry. */
7875         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7876                             prog_sample_field_value_0);
7877         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7878                             prog_sample_field_value_0);
7879         /* Already big endian (network order) in the header. */
7880         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7881         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
7882         /* Sample#0, used for matching type, offset 0. */
7883         MLX5_SET(fte_match_set_misc4, misc4_m,
7884                  prog_sample_field_id_0, samples[0]);
7885         /* It makes no sense to set the sample ID in the mask field. */
7886         MLX5_SET(fte_match_set_misc4, misc4_v,
7887                  prog_sample_field_id_0, samples[0]);
7888         /*
7889          * Checking if message body part needs to be matched.
7890          * Some wildcard rules only matching type field should be supported.
7891          */
7892         if (ecpri_m->hdr.dummy[0]) {
7893                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
7894                 switch (common.type) {
7895                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7896                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7897                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7898                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7899                                             prog_sample_field_value_1);
7900                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7901                                             prog_sample_field_value_1);
7902                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7903                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
7904                                             ecpri_m->hdr.dummy[0];
7905                         /* Sample#1, to match message body, offset 4. */
7906                         MLX5_SET(fte_match_set_misc4, misc4_m,
7907                                  prog_sample_field_id_1, samples[1]);
7908                         MLX5_SET(fte_match_set_misc4, misc4_v,
7909                                  prog_sample_field_id_1, samples[1]);
7910                         break;
7911                 default:
7912                         /* Others, do not match any sample ID. */
7913                         break;
7914                 }
7915         }
7916 }
7917
7918 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7919
7920 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7921         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7922                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7923
7924 /**
7925  * Calculate flow matcher enable bitmap.
7926  *
7927  * @param match_criteria
7928  *   Pointer to flow matcher criteria.
7929  *
7930  * @return
7931  *   Bitmap of enabled fields.
7932  */
7933 static uint8_t
7934 flow_dv_matcher_enable(uint32_t *match_criteria)
7935 {
7936         uint8_t match_criteria_enable;
7937
7938         match_criteria_enable =
7939                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7940                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7941         match_criteria_enable |=
7942                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7943                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7944         match_criteria_enable |=
7945                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7946                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7947         match_criteria_enable |=
7948                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7949                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7950         match_criteria_enable |=
7951                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7952                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7953         match_criteria_enable |=
7954                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7955                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7956         return match_criteria_enable;
7957 }
7958
7959 struct mlx5_hlist_entry *
7960 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
7961 {
7962         struct mlx5_dev_ctx_shared *sh = list->ctx;
7963         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
7964         struct rte_eth_dev *dev = ctx->dev;
7965         struct mlx5_flow_tbl_data_entry *tbl_data;
7966         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
7967         struct rte_flow_error *error = ctx->error;
7968         union mlx5_flow_tbl_key key = { .v64 = key64 };
7969         struct mlx5_flow_tbl_resource *tbl;
7970         void *domain;
7971         uint32_t idx = 0;
7972         int ret;
7973
7974         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7975         if (!tbl_data) {
7976                 rte_flow_error_set(error, ENOMEM,
7977                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7978                                    NULL,
7979                                    "cannot allocate flow table data entry");
7980                 return NULL;
7981         }
7982         tbl_data->idx = idx;
7983         tbl_data->tunnel = tt_prm->tunnel;
7984         tbl_data->group_id = tt_prm->group_id;
7985         tbl_data->external = !!tt_prm->external;
7986         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
7987         tbl_data->is_egress = !!key.direction;
7988         tbl_data->is_transfer = !!key.domain;
7989         tbl_data->dummy = !!key.dummy;
7990         tbl_data->table_id = key.table_id;
7991         tbl = &tbl_data->tbl;
7992         if (key.dummy)
7993                 return &tbl_data->entry;
7994         if (key.domain)
7995                 domain = sh->fdb_domain;
7996         else if (key.direction)
7997                 domain = sh->tx_domain;
7998         else
7999                 domain = sh->rx_domain;
8000         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8001         if (ret) {
8002                 rte_flow_error_set(error, ENOMEM,
8003                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8004                                    NULL, "cannot create flow table object");
8005                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8006                 return NULL;
8007         }
8008         if (key.table_id) {
8009                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8010                                         (tbl->obj, &tbl_data->jump.action);
8011                 if (ret) {
8012                         rte_flow_error_set(error, ENOMEM,
8013                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8014                                            NULL,
8015                                            "cannot create flow jump action");
8016                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8017                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8018                         return NULL;
8019                 }
8020         }
8021         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8022               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8023               key.table_id);
8024         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8025                              flow_dv_matcher_create_cb,
8026                              flow_dv_matcher_match_cb,
8027                              flow_dv_matcher_remove_cb);
8028         return &tbl_data->entry;
8029 }
8030
8031 int
8032 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8033                      struct mlx5_hlist_entry *entry, uint64_t key64,
8034                      void *cb_ctx __rte_unused)
8035 {
8036         struct mlx5_flow_tbl_data_entry *tbl_data =
8037                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8038         union mlx5_flow_tbl_key key = { .v64 = key64 };
8039
8040         return tbl_data->table_id != key.table_id ||
8041                tbl_data->dummy != key.dummy ||
8042                tbl_data->is_transfer != key.domain ||
8043                tbl_data->is_egress != key.direction;
8044 }
8045
8046 /**
8047  * Get a flow table.
8048  *
8049  * @param[in, out] dev
8050  *   Pointer to rte_eth_dev structure.
8051  * @param[in] table_id
8052  *   Table id to use.
8053  * @param[in] egress
8054  *   Direction of the table.
8055  * @param[in] transfer
8056  *   E-Switch or NIC flow.
8057  * @param[in] dummy
8058  *   Dummy entry for dv API.
8059  * @param[out] error
8060  *   pointer to error structure.
8061  *
8062  * @return
8063  *   Returns tables resource based on the index, NULL in case of failed.
8064  */
8065 struct mlx5_flow_tbl_resource *
8066 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8067                          uint32_t table_id, uint8_t egress,
8068                          uint8_t transfer,
8069                          bool external,
8070                          const struct mlx5_flow_tunnel *tunnel,
8071                          uint32_t group_id, uint8_t dummy,
8072                          struct rte_flow_error *error)
8073 {
8074         struct mlx5_priv *priv = dev->data->dev_private;
8075         union mlx5_flow_tbl_key table_key = {
8076                 {
8077                         .table_id = table_id,
8078                         .dummy = dummy,
8079                         .domain = !!transfer,
8080                         .direction = !!egress,
8081                 }
8082         };
8083         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8084                 .tunnel = tunnel,
8085                 .group_id = group_id,
8086                 .external = external,
8087         };
8088         struct mlx5_flow_cb_ctx ctx = {
8089                 .dev = dev,
8090                 .error = error,
8091                 .data = &tt_prm,
8092         };
8093         struct mlx5_hlist_entry *entry;
8094         struct mlx5_flow_tbl_data_entry *tbl_data;
8095
8096         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8097         if (!entry) {
8098                 rte_flow_error_set(error, ENOMEM,
8099                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8100                                    "cannot get table");
8101                 return NULL;
8102         }
8103         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8104                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8105         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8106         return &tbl_data->tbl;
8107 }
8108
8109 void
8110 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8111                       struct mlx5_hlist_entry *entry)
8112 {
8113         struct mlx5_dev_ctx_shared *sh = list->ctx;
8114         struct mlx5_flow_tbl_data_entry *tbl_data =
8115                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8116
8117         MLX5_ASSERT(entry && sh);
8118         if (tbl_data->jump.action)
8119                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8120         if (tbl_data->tbl.obj)
8121                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8122         if (tbl_data->tunnel_offload && tbl_data->external) {
8123                 struct mlx5_hlist_entry *he;
8124                 struct mlx5_hlist *tunnel_grp_hash;
8125                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8126                 union tunnel_tbl_key tunnel_key = {
8127                         .tunnel_id = tbl_data->tunnel ?
8128                                         tbl_data->tunnel->tunnel_id : 0,
8129                         .group = tbl_data->group_id
8130                 };
8131                 uint32_t table_id = tbl_data->table_id;
8132
8133                 tunnel_grp_hash = tbl_data->tunnel ?
8134                                         tbl_data->tunnel->groups :
8135                                         thub->groups;
8136                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8137                 if (he)
8138                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8139                 DRV_LOG(DEBUG,
8140                         "Table_id %u tunnel %u group %u released.",
8141                         table_id,
8142                         tbl_data->tunnel ?
8143                         tbl_data->tunnel->tunnel_id : 0,
8144                         tbl_data->group_id);
8145         }
8146         mlx5_cache_list_destroy(&tbl_data->matchers);
8147         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8148 }
8149
8150 /**
8151  * Release a flow table.
8152  *
8153  * @param[in] sh
8154  *   Pointer to device shared structure.
8155  * @param[in] tbl
8156  *   Table resource to be released.
8157  *
8158  * @return
8159  *   Returns 0 if table was released, else return 1;
8160  */
8161 static int
8162 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8163                              struct mlx5_flow_tbl_resource *tbl)
8164 {
8165         struct mlx5_flow_tbl_data_entry *tbl_data =
8166                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8167
8168         if (!tbl)
8169                 return 0;
8170         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8171 }
8172
8173 int
8174 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8175                          struct mlx5_cache_entry *entry, void *cb_ctx)
8176 {
8177         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8178         struct mlx5_flow_dv_matcher *ref = ctx->data;
8179         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8180                                                         entry);
8181
8182         return cur->crc != ref->crc ||
8183                cur->priority != ref->priority ||
8184                memcmp((const void *)cur->mask.buf,
8185                       (const void *)ref->mask.buf, ref->mask.size);
8186 }
8187
8188 struct mlx5_cache_entry *
8189 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8190                           struct mlx5_cache_entry *entry __rte_unused,
8191                           void *cb_ctx)
8192 {
8193         struct mlx5_dev_ctx_shared *sh = list->ctx;
8194         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8195         struct mlx5_flow_dv_matcher *ref = ctx->data;
8196         struct mlx5_flow_dv_matcher *cache;
8197         struct mlx5dv_flow_matcher_attr dv_attr = {
8198                 .type = IBV_FLOW_ATTR_NORMAL,
8199                 .match_mask = (void *)&ref->mask,
8200         };
8201         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8202                                                             typeof(*tbl), tbl);
8203         int ret;
8204
8205         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8206         if (!cache) {
8207                 rte_flow_error_set(ctx->error, ENOMEM,
8208                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8209                                    "cannot create matcher");
8210                 return NULL;
8211         }
8212         *cache = *ref;
8213         dv_attr.match_criteria_enable =
8214                 flow_dv_matcher_enable(cache->mask.buf);
8215         dv_attr.priority = ref->priority;
8216         if (tbl->is_egress)
8217                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8218         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8219                                                &cache->matcher_object);
8220         if (ret) {
8221                 mlx5_free(cache);
8222                 rte_flow_error_set(ctx->error, ENOMEM,
8223                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8224                                    "cannot create matcher");
8225                 return NULL;
8226         }
8227         return &cache->entry;
8228 }
8229
8230 /**
8231  * Register the flow matcher.
8232  *
8233  * @param[in, out] dev
8234  *   Pointer to rte_eth_dev structure.
8235  * @param[in, out] matcher
8236  *   Pointer to flow matcher.
8237  * @param[in, out] key
8238  *   Pointer to flow table key.
8239  * @parm[in, out] dev_flow
8240  *   Pointer to the dev_flow.
8241  * @param[out] error
8242  *   pointer to error structure.
8243  *
8244  * @return
8245  *   0 on success otherwise -errno and errno is set.
8246  */
8247 static int
8248 flow_dv_matcher_register(struct rte_eth_dev *dev,
8249                          struct mlx5_flow_dv_matcher *ref,
8250                          union mlx5_flow_tbl_key *key,
8251                          struct mlx5_flow *dev_flow,
8252                          const struct mlx5_flow_tunnel *tunnel,
8253                          uint32_t group_id,
8254                          struct rte_flow_error *error)
8255 {
8256         struct mlx5_cache_entry *entry;
8257         struct mlx5_flow_dv_matcher *cache;
8258         struct mlx5_flow_tbl_resource *tbl;
8259         struct mlx5_flow_tbl_data_entry *tbl_data;
8260         struct mlx5_flow_cb_ctx ctx = {
8261                 .error = error,
8262                 .data = ref,
8263         };
8264
8265         /**
8266          * tunnel offload API requires this registration for cases when
8267          * tunnel match rule was inserted before tunnel set rule.
8268          */
8269         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8270                                        key->direction, key->domain,
8271                                        dev_flow->external, tunnel,
8272                                        group_id, 0, error);
8273         if (!tbl)
8274                 return -rte_errno;      /* No need to refill the error info */
8275         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8276         ref->tbl = tbl;
8277         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8278         if (!entry) {
8279                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8280                 return rte_flow_error_set(error, ENOMEM,
8281                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8282                                           "cannot allocate ref memory");
8283         }
8284         cache = container_of(entry, typeof(*cache), entry);
8285         dev_flow->handle->dvh.matcher = cache;
8286         return 0;
8287 }
8288
8289 struct mlx5_hlist_entry *
8290 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8291 {
8292         struct mlx5_dev_ctx_shared *sh = list->ctx;
8293         struct rte_flow_error *error = ctx;
8294         struct mlx5_flow_dv_tag_resource *entry;
8295         uint32_t idx = 0;
8296         int ret;
8297
8298         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8299         if (!entry) {
8300                 rte_flow_error_set(error, ENOMEM,
8301                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8302                                    "cannot allocate resource memory");
8303                 return NULL;
8304         }
8305         entry->idx = idx;
8306         entry->tag_id = key;
8307         ret = mlx5_flow_os_create_flow_action_tag(key,
8308                                                   &entry->action);
8309         if (ret) {
8310                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8311                 rte_flow_error_set(error, ENOMEM,
8312                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8313                                    NULL, "cannot create action");
8314                 return NULL;
8315         }
8316         return &entry->entry;
8317 }
8318
8319 int
8320 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8321                      struct mlx5_hlist_entry *entry, uint64_t key,
8322                      void *cb_ctx __rte_unused)
8323 {
8324         struct mlx5_flow_dv_tag_resource *tag =
8325                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8326
8327         return key != tag->tag_id;
8328 }
8329
8330 /**
8331  * Find existing tag resource or create and register a new one.
8332  *
8333  * @param dev[in, out]
8334  *   Pointer to rte_eth_dev structure.
8335  * @param[in, out] tag_be24
8336  *   Tag value in big endian then R-shift 8.
8337  * @parm[in, out] dev_flow
8338  *   Pointer to the dev_flow.
8339  * @param[out] error
8340  *   pointer to error structure.
8341  *
8342  * @return
8343  *   0 on success otherwise -errno and errno is set.
8344  */
8345 static int
8346 flow_dv_tag_resource_register
8347                         (struct rte_eth_dev *dev,
8348                          uint32_t tag_be24,
8349                          struct mlx5_flow *dev_flow,
8350                          struct rte_flow_error *error)
8351 {
8352         struct mlx5_priv *priv = dev->data->dev_private;
8353         struct mlx5_flow_dv_tag_resource *cache_resource;
8354         struct mlx5_hlist_entry *entry;
8355
8356         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8357         if (entry) {
8358                 cache_resource = container_of
8359                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8360                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8361                 dev_flow->dv.tag_resource = cache_resource;
8362                 return 0;
8363         }
8364         return -rte_errno;
8365 }
8366
8367 void
8368 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8369                       struct mlx5_hlist_entry *entry)
8370 {
8371         struct mlx5_dev_ctx_shared *sh = list->ctx;
8372         struct mlx5_flow_dv_tag_resource *tag =
8373                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8374
8375         MLX5_ASSERT(tag && sh && tag->action);
8376         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8377         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8378         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8379 }
8380
8381 /**
8382  * Release the tag.
8383  *
8384  * @param dev
8385  *   Pointer to Ethernet device.
8386  * @param tag_idx
8387  *   Tag index.
8388  *
8389  * @return
8390  *   1 while a reference on it exists, 0 when freed.
8391  */
8392 static int
8393 flow_dv_tag_release(struct rte_eth_dev *dev,
8394                     uint32_t tag_idx)
8395 {
8396         struct mlx5_priv *priv = dev->data->dev_private;
8397         struct mlx5_flow_dv_tag_resource *tag;
8398
8399         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8400         if (!tag)
8401                 return 0;
8402         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8403                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8404         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8405 }
8406
8407 /**
8408  * Translate port ID action to vport.
8409  *
8410  * @param[in] dev
8411  *   Pointer to rte_eth_dev structure.
8412  * @param[in] action
8413  *   Pointer to the port ID action.
8414  * @param[out] dst_port_id
8415  *   The target port ID.
8416  * @param[out] error
8417  *   Pointer to the error structure.
8418  *
8419  * @return
8420  *   0 on success, a negative errno value otherwise and rte_errno is set.
8421  */
8422 static int
8423 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8424                                  const struct rte_flow_action *action,
8425                                  uint32_t *dst_port_id,
8426                                  struct rte_flow_error *error)
8427 {
8428         uint32_t port;
8429         struct mlx5_priv *priv;
8430         const struct rte_flow_action_port_id *conf =
8431                         (const struct rte_flow_action_port_id *)action->conf;
8432
8433         port = conf->original ? dev->data->port_id : conf->id;
8434         priv = mlx5_port_to_eswitch_info(port, false);
8435         if (!priv)
8436                 return rte_flow_error_set(error, -rte_errno,
8437                                           RTE_FLOW_ERROR_TYPE_ACTION,
8438                                           NULL,
8439                                           "No eswitch info was found for port");
8440 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8441         /*
8442          * This parameter is transferred to
8443          * mlx5dv_dr_action_create_dest_ib_port().
8444          */
8445         *dst_port_id = priv->dev_port;
8446 #else
8447         /*
8448          * Legacy mode, no LAG configurations is supported.
8449          * This parameter is transferred to
8450          * mlx5dv_dr_action_create_dest_vport().
8451          */
8452         *dst_port_id = priv->vport_id;
8453 #endif
8454         return 0;
8455 }
8456
8457 /**
8458  * Create a counter with aging configuration.
8459  *
8460  * @param[in] dev
8461  *   Pointer to rte_eth_dev structure.
8462  * @param[out] count
8463  *   Pointer to the counter action configuration.
8464  * @param[in] age
8465  *   Pointer to the aging action configuration.
8466  *
8467  * @return
8468  *   Index to flow counter on success, 0 otherwise.
8469  */
8470 static uint32_t
8471 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8472                                 struct mlx5_flow *dev_flow,
8473                                 const struct rte_flow_action_count *count,
8474                                 const struct rte_flow_action_age *age)
8475 {
8476         uint32_t counter;
8477         struct mlx5_age_param *age_param;
8478
8479         if (count && count->shared)
8480                 counter = flow_dv_counter_get_shared(dev, count->id);
8481         else
8482                 counter = flow_dv_counter_alloc(dev, !!age);
8483         if (!counter || age == NULL)
8484                 return counter;
8485         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8486         age_param->context = age->context ? age->context :
8487                 (void *)(uintptr_t)(dev_flow->flow_idx);
8488         age_param->timeout = age->timeout;
8489         age_param->port_id = dev->data->port_id;
8490         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8491         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8492         return counter;
8493 }
8494
8495 /**
8496  * Add Tx queue matcher
8497  *
8498  * @param[in] dev
8499  *   Pointer to the dev struct.
8500  * @param[in, out] matcher
8501  *   Flow matcher.
8502  * @param[in, out] key
8503  *   Flow matcher value.
8504  * @param[in] item
8505  *   Flow pattern to translate.
8506  * @param[in] inner
8507  *   Item is inner pattern.
8508  */
8509 static void
8510 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8511                                 void *matcher, void *key,
8512                                 const struct rte_flow_item *item)
8513 {
8514         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8515         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8516         void *misc_m =
8517                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8518         void *misc_v =
8519                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8520         struct mlx5_txq_ctrl *txq;
8521         uint32_t queue;
8522
8523
8524         queue_m = (const void *)item->mask;
8525         if (!queue_m)
8526                 return;
8527         queue_v = (const void *)item->spec;
8528         if (!queue_v)
8529                 return;
8530         txq = mlx5_txq_get(dev, queue_v->queue);
8531         if (!txq)
8532                 return;
8533         queue = txq->obj->sq->id;
8534         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8535         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8536                  queue & queue_m->queue);
8537         mlx5_txq_release(dev, queue_v->queue);
8538 }
8539
8540 /**
8541  * Set the hash fields according to the @p flow information.
8542  *
8543  * @param[in] dev_flow
8544  *   Pointer to the mlx5_flow.
8545  * @param[in] rss_desc
8546  *   Pointer to the mlx5_flow_rss_desc.
8547  */
8548 static void
8549 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8550                        struct mlx5_flow_rss_desc *rss_desc)
8551 {
8552         uint64_t items = dev_flow->handle->layers;
8553         int rss_inner = 0;
8554         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8555
8556         dev_flow->hash_fields = 0;
8557 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8558         if (rss_desc->level >= 2) {
8559                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8560                 rss_inner = 1;
8561         }
8562 #endif
8563         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8564             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8565                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8566                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8567                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8568                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8569                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8570                         else
8571                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8572                 }
8573         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8574                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8575                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8576                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8577                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8578                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8579                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8580                         else
8581                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8582                 }
8583         }
8584         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8585             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8586                 if (rss_types & ETH_RSS_UDP) {
8587                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8588                                 dev_flow->hash_fields |=
8589                                                 IBV_RX_HASH_SRC_PORT_UDP;
8590                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8591                                 dev_flow->hash_fields |=
8592                                                 IBV_RX_HASH_DST_PORT_UDP;
8593                         else
8594                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8595                 }
8596         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8597                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8598                 if (rss_types & ETH_RSS_TCP) {
8599                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8600                                 dev_flow->hash_fields |=
8601                                                 IBV_RX_HASH_SRC_PORT_TCP;
8602                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8603                                 dev_flow->hash_fields |=
8604                                                 IBV_RX_HASH_DST_PORT_TCP;
8605                         else
8606                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8607                 }
8608         }
8609 }
8610
8611 /**
8612  * Prepare an Rx Hash queue.
8613  *
8614  * @param dev
8615  *   Pointer to Ethernet device.
8616  * @param[in] dev_flow
8617  *   Pointer to the mlx5_flow.
8618  * @param[in] rss_desc
8619  *   Pointer to the mlx5_flow_rss_desc.
8620  * @param[out] hrxq_idx
8621  *   Hash Rx queue index.
8622  *
8623  * @return
8624  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8625  */
8626 static struct mlx5_hrxq *
8627 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8628                      struct mlx5_flow *dev_flow,
8629                      struct mlx5_flow_rss_desc *rss_desc,
8630                      uint32_t *hrxq_idx)
8631 {
8632         struct mlx5_priv *priv = dev->data->dev_private;
8633         struct mlx5_flow_handle *dh = dev_flow->handle;
8634         struct mlx5_hrxq *hrxq;
8635
8636         MLX5_ASSERT(rss_desc->queue_num);
8637         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8638         rss_desc->hash_fields = dev_flow->hash_fields;
8639         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8640         rss_desc->shared_rss = 0;
8641         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8642         if (!*hrxq_idx)
8643                 return NULL;
8644         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8645                               *hrxq_idx);
8646         return hrxq;
8647 }
8648
8649 /**
8650  * Release sample sub action resource.
8651  *
8652  * @param[in, out] dev
8653  *   Pointer to rte_eth_dev structure.
8654  * @param[in] act_res
8655  *   Pointer to sample sub action resource.
8656  */
8657 static void
8658 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8659                                    struct mlx5_flow_sub_actions_idx *act_res)
8660 {
8661         if (act_res->rix_hrxq) {
8662                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8663                 act_res->rix_hrxq = 0;
8664         }
8665         if (act_res->rix_encap_decap) {
8666                 flow_dv_encap_decap_resource_release(dev,
8667                                                      act_res->rix_encap_decap);
8668                 act_res->rix_encap_decap = 0;
8669         }
8670         if (act_res->rix_port_id_action) {
8671                 flow_dv_port_id_action_resource_release(dev,
8672                                                 act_res->rix_port_id_action);
8673                 act_res->rix_port_id_action = 0;
8674         }
8675         if (act_res->rix_tag) {
8676                 flow_dv_tag_release(dev, act_res->rix_tag);
8677                 act_res->rix_tag = 0;
8678         }
8679         if (act_res->cnt) {
8680                 flow_dv_counter_free(dev, act_res->cnt);
8681                 act_res->cnt = 0;
8682         }
8683 }
8684
8685 int
8686 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8687                         struct mlx5_cache_entry *entry, void *cb_ctx)
8688 {
8689         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8690         struct rte_eth_dev *dev = ctx->dev;
8691         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8692         struct mlx5_flow_dv_sample_resource *cache_resource =
8693                         container_of(entry, typeof(*cache_resource), entry);
8694
8695         if (resource->ratio == cache_resource->ratio &&
8696             resource->ft_type == cache_resource->ft_type &&
8697             resource->ft_id == cache_resource->ft_id &&
8698             resource->set_action == cache_resource->set_action &&
8699             !memcmp((void *)&resource->sample_act,
8700                     (void *)&cache_resource->sample_act,
8701                     sizeof(struct mlx5_flow_sub_actions_list))) {
8702                 /*
8703                  * Existing sample action should release the prepared
8704                  * sub-actions reference counter.
8705                  */
8706                 flow_dv_sample_sub_actions_release(dev,
8707                                                 &resource->sample_idx);
8708                 return 0;
8709         }
8710         return 1;
8711 }
8712
8713 struct mlx5_cache_entry *
8714 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8715                          struct mlx5_cache_entry *entry __rte_unused,
8716                          void *cb_ctx)
8717 {
8718         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8719         struct rte_eth_dev *dev = ctx->dev;
8720         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8721         void **sample_dv_actions = resource->sub_actions;
8722         struct mlx5_flow_dv_sample_resource *cache_resource;
8723         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8724         struct mlx5_priv *priv = dev->data->dev_private;
8725         struct mlx5_dev_ctx_shared *sh = priv->sh;
8726         struct mlx5_flow_tbl_resource *tbl;
8727         uint32_t idx = 0;
8728         const uint32_t next_ft_step = 1;
8729         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8730         uint8_t is_egress = 0;
8731         uint8_t is_transfer = 0;
8732         struct rte_flow_error *error = ctx->error;
8733
8734         /* Register new sample resource. */
8735         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
8736         if (!cache_resource) {
8737                 rte_flow_error_set(error, ENOMEM,
8738                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8739                                           NULL,
8740                                           "cannot allocate resource memory");
8741                 return NULL;
8742         }
8743         *cache_resource = *resource;
8744         /* Create normal path table level */
8745         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8746                 is_transfer = 1;
8747         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
8748                 is_egress = 1;
8749         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8750                                         is_egress, is_transfer,
8751                                         true, NULL, 0, 0, error);
8752         if (!tbl) {
8753                 rte_flow_error_set(error, ENOMEM,
8754                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8755                                           NULL,
8756                                           "fail to create normal path table "
8757                                           "for sample");
8758                 goto error;
8759         }
8760         cache_resource->normal_path_tbl = tbl;
8761         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8762                 cache_resource->default_miss =
8763                                 mlx5_glue->dr_create_flow_action_default_miss();
8764                 if (!cache_resource->default_miss) {
8765                         rte_flow_error_set(error, ENOMEM,
8766                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8767                                                 NULL,
8768                                                 "cannot create default miss "
8769                                                 "action");
8770                         goto error;
8771                 }
8772                 sample_dv_actions[resource->sample_act.actions_num++] =
8773                                                 cache_resource->default_miss;
8774         }
8775         /* Create a DR sample action */
8776         sampler_attr.sample_ratio = cache_resource->ratio;
8777         sampler_attr.default_next_table = tbl->obj;
8778         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8779         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8780                                                         &sample_dv_actions[0];
8781         sampler_attr.action = cache_resource->set_action;
8782         cache_resource->verbs_action =
8783                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8784         if (!cache_resource->verbs_action) {
8785                 rte_flow_error_set(error, ENOMEM,
8786                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8787                                         NULL, "cannot create sample action");
8788                 goto error;
8789         }
8790         cache_resource->idx = idx;
8791         cache_resource->dev = dev;
8792         return &cache_resource->entry;
8793 error:
8794         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
8795             cache_resource->default_miss)
8796                 claim_zero(mlx5_glue->destroy_flow_action
8797                                 (cache_resource->default_miss));
8798         else
8799                 flow_dv_sample_sub_actions_release(dev,
8800                                                    &cache_resource->sample_idx);
8801         if (cache_resource->normal_path_tbl)
8802                 flow_dv_tbl_resource_release(MLX5_SH(dev),
8803                                 cache_resource->normal_path_tbl);
8804         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
8805         return NULL;
8806
8807 }
8808
8809 /**
8810  * Find existing sample resource or create and register a new one.
8811  *
8812  * @param[in, out] dev
8813  *   Pointer to rte_eth_dev structure.
8814  * @param[in] resource
8815  *   Pointer to sample resource.
8816  * @parm[in, out] dev_flow
8817  *   Pointer to the dev_flow.
8818  * @param[out] error
8819  *   pointer to error structure.
8820  *
8821  * @return
8822  *   0 on success otherwise -errno and errno is set.
8823  */
8824 static int
8825 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8826                          struct mlx5_flow_dv_sample_resource *resource,
8827                          struct mlx5_flow *dev_flow,
8828                          struct rte_flow_error *error)
8829 {
8830         struct mlx5_flow_dv_sample_resource *cache_resource;
8831         struct mlx5_cache_entry *entry;
8832         struct mlx5_priv *priv = dev->data->dev_private;
8833         struct mlx5_flow_cb_ctx ctx = {
8834                 .dev = dev,
8835                 .error = error,
8836                 .data = resource,
8837         };
8838
8839         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
8840         if (!entry)
8841                 return -rte_errno;
8842         cache_resource = container_of(entry, typeof(*cache_resource), entry);
8843         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
8844         dev_flow->dv.sample_res = cache_resource;
8845         return 0;
8846 }
8847
8848 int
8849 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
8850                             struct mlx5_cache_entry *entry, void *cb_ctx)
8851 {
8852         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8853         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8854         struct rte_eth_dev *dev = ctx->dev;
8855         struct mlx5_flow_dv_dest_array_resource *cache_resource =
8856                         container_of(entry, typeof(*cache_resource), entry);
8857         uint32_t idx = 0;
8858
8859         if (resource->num_of_dest == cache_resource->num_of_dest &&
8860             resource->ft_type == cache_resource->ft_type &&
8861             !memcmp((void *)cache_resource->sample_act,
8862                     (void *)resource->sample_act,
8863                    (resource->num_of_dest *
8864                    sizeof(struct mlx5_flow_sub_actions_list)))) {
8865                 /*
8866                  * Existing sample action should release the prepared
8867                  * sub-actions reference counter.
8868                  */
8869                 for (idx = 0; idx < resource->num_of_dest; idx++)
8870                         flow_dv_sample_sub_actions_release(dev,
8871                                         &resource->sample_idx[idx]);
8872                 return 0;
8873         }
8874         return 1;
8875 }
8876
8877 struct mlx5_cache_entry *
8878 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
8879                          struct mlx5_cache_entry *entry __rte_unused,
8880                          void *cb_ctx)
8881 {
8882         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8883         struct rte_eth_dev *dev = ctx->dev;
8884         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8885         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8886         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8887         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8888         struct mlx5_priv *priv = dev->data->dev_private;
8889         struct mlx5_dev_ctx_shared *sh = priv->sh;
8890         struct mlx5_flow_sub_actions_list *sample_act;
8891         struct mlx5dv_dr_domain *domain;
8892         uint32_t idx = 0, res_idx = 0;
8893         struct rte_flow_error *error = ctx->error;
8894
8895         /* Register new destination array resource. */
8896         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8897                                             &res_idx);
8898         if (!cache_resource) {
8899                 rte_flow_error_set(error, ENOMEM,
8900                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8901                                           NULL,
8902                                           "cannot allocate resource memory");
8903                 return NULL;
8904         }
8905         *cache_resource = *resource;
8906         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8907                 domain = sh->fdb_domain;
8908         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
8909                 domain = sh->rx_domain;
8910         else
8911                 domain = sh->tx_domain;
8912         for (idx = 0; idx < resource->num_of_dest; idx++) {
8913                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8914                                  mlx5_malloc(MLX5_MEM_ZERO,
8915                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8916                                  0, SOCKET_ID_ANY);
8917                 if (!dest_attr[idx]) {
8918                         rte_flow_error_set(error, ENOMEM,
8919                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8920                                            NULL,
8921                                            "cannot allocate resource memory");
8922                         goto error;
8923                 }
8924                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8925                 sample_act = &resource->sample_act[idx];
8926                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8927                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8928                 } else if (sample_act->action_flags ==
8929                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8930                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8931                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8932                         dest_attr[idx]->dest_reformat->reformat =
8933                                         sample_act->dr_encap_action;
8934                         dest_attr[idx]->dest_reformat->dest =
8935                                         sample_act->dr_port_id_action;
8936                 } else if (sample_act->action_flags ==
8937                            MLX5_FLOW_ACTION_PORT_ID) {
8938                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8939                 }
8940         }
8941         /* create a dest array actioin */
8942         cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8943                                                 (domain,
8944                                                  cache_resource->num_of_dest,
8945                                                  dest_attr);
8946         if (!cache_resource->action) {
8947                 rte_flow_error_set(error, ENOMEM,
8948                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8949                                    NULL,
8950                                    "cannot create destination array action");
8951                 goto error;
8952         }
8953         cache_resource->idx = res_idx;
8954         cache_resource->dev = dev;
8955         for (idx = 0; idx < resource->num_of_dest; idx++)
8956                 mlx5_free(dest_attr[idx]);
8957         return &cache_resource->entry;
8958 error:
8959         for (idx = 0; idx < resource->num_of_dest; idx++) {
8960                 struct mlx5_flow_sub_actions_idx *act_res =
8961                                         &cache_resource->sample_idx[idx];
8962                 if (act_res->rix_hrxq &&
8963                     !mlx5_hrxq_release(dev,
8964                                 act_res->rix_hrxq))
8965                         act_res->rix_hrxq = 0;
8966                 if (act_res->rix_encap_decap &&
8967                         !flow_dv_encap_decap_resource_release(dev,
8968                                 act_res->rix_encap_decap))
8969                         act_res->rix_encap_decap = 0;
8970                 if (act_res->rix_port_id_action &&
8971                         !flow_dv_port_id_action_resource_release(dev,
8972                                 act_res->rix_port_id_action))
8973                         act_res->rix_port_id_action = 0;
8974                 if (dest_attr[idx])
8975                         mlx5_free(dest_attr[idx]);
8976         }
8977
8978         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
8979         return NULL;
8980 }
8981
8982 /**
8983  * Find existing destination array resource or create and register a new one.
8984  *
8985  * @param[in, out] dev
8986  *   Pointer to rte_eth_dev structure.
8987  * @param[in] resource
8988  *   Pointer to destination array resource.
8989  * @parm[in, out] dev_flow
8990  *   Pointer to the dev_flow.
8991  * @param[out] error
8992  *   pointer to error structure.
8993  *
8994  * @return
8995  *   0 on success otherwise -errno and errno is set.
8996  */
8997 static int
8998 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8999                          struct mlx5_flow_dv_dest_array_resource *resource,
9000                          struct mlx5_flow *dev_flow,
9001                          struct rte_flow_error *error)
9002 {
9003         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9004         struct mlx5_priv *priv = dev->data->dev_private;
9005         struct mlx5_cache_entry *entry;
9006         struct mlx5_flow_cb_ctx ctx = {
9007                 .dev = dev,
9008                 .error = error,
9009                 .data = resource,
9010         };
9011
9012         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9013         if (!entry)
9014                 return -rte_errno;
9015         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9016         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9017         dev_flow->dv.dest_array_res = cache_resource;
9018         return 0;
9019 }
9020
9021 /**
9022  * Convert Sample action to DV specification.
9023  *
9024  * @param[in] dev
9025  *   Pointer to rte_eth_dev structure.
9026  * @param[in] action
9027  *   Pointer to action structure.
9028  * @param[in, out] dev_flow
9029  *   Pointer to the mlx5_flow.
9030  * @param[in] attr
9031  *   Pointer to the flow attributes.
9032  * @param[in, out] num_of_dest
9033  *   Pointer to the num of destination.
9034  * @param[in, out] sample_actions
9035  *   Pointer to sample actions list.
9036  * @param[in, out] res
9037  *   Pointer to sample resource.
9038  * @param[out] error
9039  *   Pointer to the error structure.
9040  *
9041  * @return
9042  *   0 on success, a negative errno value otherwise and rte_errno is set.
9043  */
9044 static int
9045 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9046                                 const struct rte_flow_action *action,
9047                                 struct mlx5_flow *dev_flow,
9048                                 const struct rte_flow_attr *attr,
9049                                 uint32_t *num_of_dest,
9050                                 void **sample_actions,
9051                                 struct mlx5_flow_dv_sample_resource *res,
9052                                 struct rte_flow_error *error)
9053 {
9054         struct mlx5_priv *priv = dev->data->dev_private;
9055         const struct rte_flow_action_sample *sample_action;
9056         const struct rte_flow_action *sub_actions;
9057         const struct rte_flow_action_queue *queue;
9058         struct mlx5_flow_sub_actions_list *sample_act;
9059         struct mlx5_flow_sub_actions_idx *sample_idx;
9060         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9061         struct mlx5_flow_rss_desc *rss_desc;
9062         uint64_t action_flags = 0;
9063
9064         MLX5_ASSERT(wks);
9065         rss_desc = &wks->rss_desc;
9066         sample_act = &res->sample_act;
9067         sample_idx = &res->sample_idx;
9068         sample_action = (const struct rte_flow_action_sample *)action->conf;
9069         res->ratio = sample_action->ratio;
9070         sub_actions = sample_action->actions;
9071         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9072                 int type = sub_actions->type;
9073                 uint32_t pre_rix = 0;
9074                 void *pre_r;
9075                 switch (type) {
9076                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9077                 {
9078                         struct mlx5_hrxq *hrxq;
9079                         uint32_t hrxq_idx;
9080
9081                         queue = sub_actions->conf;
9082                         rss_desc->queue_num = 1;
9083                         rss_desc->queue[0] = queue->index;
9084                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9085                                                     rss_desc, &hrxq_idx);
9086                         if (!hrxq)
9087                                 return rte_flow_error_set
9088                                         (error, rte_errno,
9089                                          RTE_FLOW_ERROR_TYPE_ACTION,
9090                                          NULL,
9091                                          "cannot create fate queue");
9092                         sample_act->dr_queue_action = hrxq->action;
9093                         sample_idx->rix_hrxq = hrxq_idx;
9094                         sample_actions[sample_act->actions_num++] =
9095                                                 hrxq->action;
9096                         (*num_of_dest)++;
9097                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9098                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9099                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9100                         dev_flow->handle->fate_action =
9101                                         MLX5_FLOW_FATE_QUEUE;
9102                         break;
9103                 }
9104                 case RTE_FLOW_ACTION_TYPE_MARK:
9105                 {
9106                         uint32_t tag_be = mlx5_flow_mark_set
9107                                 (((const struct rte_flow_action_mark *)
9108                                 (sub_actions->conf))->id);
9109
9110                         dev_flow->handle->mark = 1;
9111                         pre_rix = dev_flow->handle->dvh.rix_tag;
9112                         /* Save the mark resource before sample */
9113                         pre_r = dev_flow->dv.tag_resource;
9114                         if (flow_dv_tag_resource_register(dev, tag_be,
9115                                                   dev_flow, error))
9116                                 return -rte_errno;
9117                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9118                         sample_act->dr_tag_action =
9119                                 dev_flow->dv.tag_resource->action;
9120                         sample_idx->rix_tag =
9121                                 dev_flow->handle->dvh.rix_tag;
9122                         sample_actions[sample_act->actions_num++] =
9123                                                 sample_act->dr_tag_action;
9124                         /* Recover the mark resource after sample */
9125                         dev_flow->dv.tag_resource = pre_r;
9126                         dev_flow->handle->dvh.rix_tag = pre_rix;
9127                         action_flags |= MLX5_FLOW_ACTION_MARK;
9128                         break;
9129                 }
9130                 case RTE_FLOW_ACTION_TYPE_COUNT:
9131                 {
9132                         uint32_t counter;
9133
9134                         counter = flow_dv_translate_create_counter(dev,
9135                                         dev_flow, sub_actions->conf, 0);
9136                         if (!counter)
9137                                 return rte_flow_error_set
9138                                                 (error, rte_errno,
9139                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9140                                                  NULL,
9141                                                  "cannot create counter"
9142                                                  " object.");
9143                         sample_idx->cnt = counter;
9144                         sample_act->dr_cnt_action =
9145                                   (flow_dv_counter_get_by_idx(dev,
9146                                   counter, NULL))->action;
9147                         sample_actions[sample_act->actions_num++] =
9148                                                 sample_act->dr_cnt_action;
9149                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9150                         break;
9151                 }
9152                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9153                 {
9154                         struct mlx5_flow_dv_port_id_action_resource
9155                                         port_id_resource;
9156                         uint32_t port_id = 0;
9157
9158                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9159                         /* Save the port id resource before sample */
9160                         pre_rix = dev_flow->handle->rix_port_id_action;
9161                         pre_r = dev_flow->dv.port_id_action;
9162                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9163                                                              &port_id, error))
9164                                 return -rte_errno;
9165                         port_id_resource.port_id = port_id;
9166                         if (flow_dv_port_id_action_resource_register
9167                             (dev, &port_id_resource, dev_flow, error))
9168                                 return -rte_errno;
9169                         sample_act->dr_port_id_action =
9170                                 dev_flow->dv.port_id_action->action;
9171                         sample_idx->rix_port_id_action =
9172                                 dev_flow->handle->rix_port_id_action;
9173                         sample_actions[sample_act->actions_num++] =
9174                                                 sample_act->dr_port_id_action;
9175                         /* Recover the port id resource after sample */
9176                         dev_flow->dv.port_id_action = pre_r;
9177                         dev_flow->handle->rix_port_id_action = pre_rix;
9178                         (*num_of_dest)++;
9179                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9180                         break;
9181                 }
9182                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9183                         /* Save the encap resource before sample */
9184                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9185                         pre_r = dev_flow->dv.encap_decap;
9186                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9187                                                            dev_flow,
9188                                                            attr->transfer,
9189                                                            error))
9190                                 return -rte_errno;
9191                         sample_act->dr_encap_action =
9192                                 dev_flow->dv.encap_decap->action;
9193                         sample_idx->rix_encap_decap =
9194                                 dev_flow->handle->dvh.rix_encap_decap;
9195                         sample_actions[sample_act->actions_num++] =
9196                                                 sample_act->dr_encap_action;
9197                         /* Recover the encap resource after sample */
9198                         dev_flow->dv.encap_decap = pre_r;
9199                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9200                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9201                         break;
9202                 default:
9203                         return rte_flow_error_set(error, EINVAL,
9204                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9205                                 NULL,
9206                                 "Not support for sampler action");
9207                 }
9208         }
9209         sample_act->action_flags = action_flags;
9210         res->ft_id = dev_flow->dv.group;
9211         if (attr->transfer) {
9212                 union {
9213                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9214                         uint64_t set_action;
9215                 } action_ctx = { .set_action = 0 };
9216
9217                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9218                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9219                          MLX5_MODIFICATION_TYPE_SET);
9220                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9221                          MLX5_MODI_META_REG_C_0);
9222                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9223                          priv->vport_meta_tag);
9224                 res->set_action = action_ctx.set_action;
9225         } else if (attr->ingress) {
9226                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9227         } else {
9228                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9229         }
9230         return 0;
9231 }
9232
9233 /**
9234  * Convert Sample action to DV specification.
9235  *
9236  * @param[in] dev
9237  *   Pointer to rte_eth_dev structure.
9238  * @param[in, out] dev_flow
9239  *   Pointer to the mlx5_flow.
9240  * @param[in] num_of_dest
9241  *   The num of destination.
9242  * @param[in, out] res
9243  *   Pointer to sample resource.
9244  * @param[in, out] mdest_res
9245  *   Pointer to destination array resource.
9246  * @param[in] sample_actions
9247  *   Pointer to sample path actions list.
9248  * @param[in] action_flags
9249  *   Holds the actions detected until now.
9250  * @param[out] error
9251  *   Pointer to the error structure.
9252  *
9253  * @return
9254  *   0 on success, a negative errno value otherwise and rte_errno is set.
9255  */
9256 static int
9257 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9258                              struct mlx5_flow *dev_flow,
9259                              uint32_t num_of_dest,
9260                              struct mlx5_flow_dv_sample_resource *res,
9261                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9262                              void **sample_actions,
9263                              uint64_t action_flags,
9264                              struct rte_flow_error *error)
9265 {
9266         /* update normal path action resource into last index of array */
9267         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9268         struct mlx5_flow_sub_actions_list *sample_act =
9269                                         &mdest_res->sample_act[dest_index];
9270         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9271         struct mlx5_flow_rss_desc *rss_desc;
9272         uint32_t normal_idx = 0;
9273         struct mlx5_hrxq *hrxq;
9274         uint32_t hrxq_idx;
9275
9276         MLX5_ASSERT(wks);
9277         rss_desc = &wks->rss_desc;
9278         if (num_of_dest > 1) {
9279                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9280                         /* Handle QP action for mirroring */
9281                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9282                                                     rss_desc, &hrxq_idx);
9283                         if (!hrxq)
9284                                 return rte_flow_error_set
9285                                      (error, rte_errno,
9286                                       RTE_FLOW_ERROR_TYPE_ACTION,
9287                                       NULL,
9288                                       "cannot create rx queue");
9289                         normal_idx++;
9290                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9291                         sample_act->dr_queue_action = hrxq->action;
9292                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9293                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9294                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9295                 }
9296                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9297                         normal_idx++;
9298                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9299                                 dev_flow->handle->dvh.rix_encap_decap;
9300                         sample_act->dr_encap_action =
9301                                 dev_flow->dv.encap_decap->action;
9302                 }
9303                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9304                         normal_idx++;
9305                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9306                                 dev_flow->handle->rix_port_id_action;
9307                         sample_act->dr_port_id_action =
9308                                 dev_flow->dv.port_id_action->action;
9309                 }
9310                 sample_act->actions_num = normal_idx;
9311                 /* update sample action resource into first index of array */
9312                 mdest_res->ft_type = res->ft_type;
9313                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9314                                 sizeof(struct mlx5_flow_sub_actions_idx));
9315                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9316                                 sizeof(struct mlx5_flow_sub_actions_list));
9317                 mdest_res->num_of_dest = num_of_dest;
9318                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9319                                                          dev_flow, error))
9320                         return rte_flow_error_set(error, EINVAL,
9321                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9322                                                   NULL, "can't create sample "
9323                                                   "action");
9324         } else {
9325                 res->sub_actions = sample_actions;
9326                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9327                         return rte_flow_error_set(error, EINVAL,
9328                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9329                                                   NULL,
9330                                                   "can't create sample action");
9331         }
9332         return 0;
9333 }
9334
9335 /**
9336  * Remove an ASO age action from age actions list.
9337  *
9338  * @param[in] dev
9339  *   Pointer to the Ethernet device structure.
9340  * @param[in] age
9341  *   Pointer to the aso age action handler.
9342  */
9343 static void
9344 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9345                                 struct mlx5_aso_age_action *age)
9346 {
9347         struct mlx5_age_info *age_info;
9348         struct mlx5_age_param *age_param = &age->age_params;
9349         struct mlx5_priv *priv = dev->data->dev_private;
9350         uint16_t expected = AGE_CANDIDATE;
9351
9352         age_info = GET_PORT_AGE_INFO(priv);
9353         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9354                                          AGE_FREE, false, __ATOMIC_RELAXED,
9355                                          __ATOMIC_RELAXED)) {
9356                 /**
9357                  * We need the lock even it is age timeout,
9358                  * since age action may still in process.
9359                  */
9360                 rte_spinlock_lock(&age_info->aged_sl);
9361                 LIST_REMOVE(age, next);
9362                 rte_spinlock_unlock(&age_info->aged_sl);
9363                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9364         }
9365 }
9366
9367 /**
9368  * Release an ASO age action.
9369  *
9370  * @param[in] dev
9371  *   Pointer to the Ethernet device structure.
9372  * @param[in] age_idx
9373  *   Index of ASO age action to release.
9374  * @param[in] flow
9375  *   True if the release operation is during flow destroy operation.
9376  *   False if the release operation is during action destroy operation.
9377  *
9378  * @return
9379  *   0 when age action was removed, otherwise the number of references.
9380  */
9381 static int
9382 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9383 {
9384         struct mlx5_priv *priv = dev->data->dev_private;
9385         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9386         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9387         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9388
9389         if (!ret) {
9390                 flow_dv_aso_age_remove_from_age(dev, age);
9391                 rte_spinlock_lock(&mng->free_sl);
9392                 LIST_INSERT_HEAD(&mng->free, age, next);
9393                 rte_spinlock_unlock(&mng->free_sl);
9394         }
9395         return ret;
9396 }
9397
9398 /**
9399  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9400  *
9401  * @param[in] dev
9402  *   Pointer to the Ethernet device structure.
9403  *
9404  * @return
9405  *   0 on success, otherwise negative errno value and rte_errno is set.
9406  */
9407 static int
9408 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9409 {
9410         struct mlx5_priv *priv = dev->data->dev_private;
9411         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9412         void *old_pools = mng->pools;
9413         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9414         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9415         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9416
9417         if (!pools) {
9418                 rte_errno = ENOMEM;
9419                 return -ENOMEM;
9420         }
9421         if (old_pools) {
9422                 memcpy(pools, old_pools,
9423                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9424                 mlx5_free(old_pools);
9425         } else {
9426                 /* First ASO flow hit allocation - starting ASO data-path. */
9427                 int ret = mlx5_aso_queue_start(priv->sh);
9428
9429                 if (ret) {
9430                         mlx5_free(pools);
9431                         return ret;
9432                 }
9433         }
9434         mng->n = resize;
9435         mng->pools = pools;
9436         return 0;
9437 }
9438
9439 /**
9440  * Create and initialize a new ASO aging pool.
9441  *
9442  * @param[in] dev
9443  *   Pointer to the Ethernet device structure.
9444  * @param[out] age_free
9445  *   Where to put the pointer of a new age action.
9446  *
9447  * @return
9448  *   The age actions pool pointer and @p age_free is set on success,
9449  *   NULL otherwise and rte_errno is set.
9450  */
9451 static struct mlx5_aso_age_pool *
9452 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9453                         struct mlx5_aso_age_action **age_free)
9454 {
9455         struct mlx5_priv *priv = dev->data->dev_private;
9456         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9457         struct mlx5_aso_age_pool *pool = NULL;
9458         struct mlx5_devx_obj *obj = NULL;
9459         uint32_t i;
9460
9461         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9462                                                     priv->sh->pdn);
9463         if (!obj) {
9464                 rte_errno = ENODATA;
9465                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9466                 return NULL;
9467         }
9468         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9469         if (!pool) {
9470                 claim_zero(mlx5_devx_cmd_destroy(obj));
9471                 rte_errno = ENOMEM;
9472                 return NULL;
9473         }
9474         pool->flow_hit_aso_obj = obj;
9475         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9476         rte_spinlock_lock(&mng->resize_sl);
9477         pool->index = mng->next;
9478         /* Resize pools array if there is no room for the new pool in it. */
9479         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9480                 claim_zero(mlx5_devx_cmd_destroy(obj));
9481                 mlx5_free(pool);
9482                 rte_spinlock_unlock(&mng->resize_sl);
9483                 return NULL;
9484         }
9485         mng->pools[pool->index] = pool;
9486         mng->next++;
9487         rte_spinlock_unlock(&mng->resize_sl);
9488         /* Assign the first action in the new pool, the rest go to free list. */
9489         *age_free = &pool->actions[0];
9490         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9491                 pool->actions[i].offset = i;
9492                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9493         }
9494         return pool;
9495 }
9496
9497 /**
9498  * Allocate a ASO aging bit.
9499  *
9500  * @param[in] dev
9501  *   Pointer to the Ethernet device structure.
9502  * @param[out] error
9503  *   Pointer to the error structure.
9504  *
9505  * @return
9506  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9507  */
9508 static uint32_t
9509 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9510 {
9511         struct mlx5_priv *priv = dev->data->dev_private;
9512         const struct mlx5_aso_age_pool *pool;
9513         struct mlx5_aso_age_action *age_free = NULL;
9514         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9515
9516         MLX5_ASSERT(mng);
9517         /* Try to get the next free age action bit. */
9518         rte_spinlock_lock(&mng->free_sl);
9519         age_free = LIST_FIRST(&mng->free);
9520         if (age_free) {
9521                 LIST_REMOVE(age_free, next);
9522         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9523                 rte_spinlock_unlock(&mng->free_sl);
9524                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9525                                    NULL, "failed to create ASO age pool");
9526                 return 0; /* 0 is an error. */
9527         }
9528         rte_spinlock_unlock(&mng->free_sl);
9529         pool = container_of
9530           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9531                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9532                                                                        actions);
9533         if (!age_free->dr_action) {
9534                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9535                                                  error);
9536
9537                 if (reg_c < 0) {
9538                         rte_flow_error_set(error, rte_errno,
9539                                            RTE_FLOW_ERROR_TYPE_ACTION,
9540                                            NULL, "failed to get reg_c "
9541                                            "for ASO flow hit");
9542                         return 0; /* 0 is an error. */
9543                 }
9544 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9545                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9546                                 (priv->sh->rx_domain,
9547                                  pool->flow_hit_aso_obj->obj, age_free->offset,
9548                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9549                                  (reg_c - REG_C_0));
9550 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9551                 if (!age_free->dr_action) {
9552                         rte_errno = errno;
9553                         rte_spinlock_lock(&mng->free_sl);
9554                         LIST_INSERT_HEAD(&mng->free, age_free, next);
9555                         rte_spinlock_unlock(&mng->free_sl);
9556                         rte_flow_error_set(error, rte_errno,
9557                                            RTE_FLOW_ERROR_TYPE_ACTION,
9558                                            NULL, "failed to create ASO "
9559                                            "flow hit action");
9560                         return 0; /* 0 is an error. */
9561                 }
9562         }
9563         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9564         return pool->index | ((age_free->offset + 1) << 16);
9565 }
9566
9567 /**
9568  * Create a age action using ASO mechanism.
9569  *
9570  * @param[in] dev
9571  *   Pointer to rte_eth_dev structure.
9572  * @param[in] age
9573  *   Pointer to the aging action configuration.
9574  * @param[out] error
9575  *   Pointer to the error structure.
9576  *
9577  * @return
9578  *   Index to flow counter on success, 0 otherwise.
9579  */
9580 static uint32_t
9581 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9582                                  const struct rte_flow_action_age *age,
9583                                  struct rte_flow_error *error)
9584 {
9585         uint32_t age_idx = 0;
9586         struct mlx5_aso_age_action *aso_age;
9587
9588         age_idx = flow_dv_aso_age_alloc(dev, error);
9589         if (!age_idx)
9590                 return 0;
9591         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9592         aso_age->age_params.context = age->context;
9593         aso_age->age_params.timeout = age->timeout;
9594         aso_age->age_params.port_id = dev->data->port_id;
9595         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9596                          __ATOMIC_RELAXED);
9597         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9598                          __ATOMIC_RELAXED);
9599         return age_idx;
9600 }
9601
9602 /**
9603  * Fill the flow with DV spec, lock free
9604  * (mutex should be acquired by caller).
9605  *
9606  * @param[in] dev
9607  *   Pointer to rte_eth_dev structure.
9608  * @param[in, out] dev_flow
9609  *   Pointer to the sub flow.
9610  * @param[in] attr
9611  *   Pointer to the flow attributes.
9612  * @param[in] items
9613  *   Pointer to the list of items.
9614  * @param[in] actions
9615  *   Pointer to the list of actions.
9616  * @param[out] error
9617  *   Pointer to the error structure.
9618  *
9619  * @return
9620  *   0 on success, a negative errno value otherwise and rte_errno is set.
9621  */
9622 static int
9623 flow_dv_translate(struct rte_eth_dev *dev,
9624                   struct mlx5_flow *dev_flow,
9625                   const struct rte_flow_attr *attr,
9626                   const struct rte_flow_item items[],
9627                   const struct rte_flow_action actions[],
9628                   struct rte_flow_error *error)
9629 {
9630         struct mlx5_priv *priv = dev->data->dev_private;
9631         struct mlx5_dev_config *dev_conf = &priv->config;
9632         struct rte_flow *flow = dev_flow->flow;
9633         struct mlx5_flow_handle *handle = dev_flow->handle;
9634         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9635         struct mlx5_flow_rss_desc *rss_desc;
9636         uint64_t item_flags = 0;
9637         uint64_t last_item = 0;
9638         uint64_t action_flags = 0;
9639         uint64_t priority = attr->priority;
9640         struct mlx5_flow_dv_matcher matcher = {
9641                 .mask = {
9642                         .size = sizeof(matcher.mask.buf) -
9643                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9644                 },
9645         };
9646         int actions_n = 0;
9647         bool actions_end = false;
9648         union {
9649                 struct mlx5_flow_dv_modify_hdr_resource res;
9650                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9651                             sizeof(struct mlx5_modification_cmd) *
9652                             (MLX5_MAX_MODIFY_NUM + 1)];
9653         } mhdr_dummy;
9654         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9655         const struct rte_flow_action_count *count = NULL;
9656         const struct rte_flow_action_age *age = NULL;
9657         union flow_dv_attr flow_attr = { .attr = 0 };
9658         uint32_t tag_be;
9659         union mlx5_flow_tbl_key tbl_key;
9660         uint32_t modify_action_position = UINT32_MAX;
9661         void *match_mask = matcher.mask.buf;
9662         void *match_value = dev_flow->dv.value.buf;
9663         uint8_t next_protocol = 0xff;
9664         struct rte_vlan_hdr vlan = { 0 };
9665         struct mlx5_flow_dv_dest_array_resource mdest_res;
9666         struct mlx5_flow_dv_sample_resource sample_res;
9667         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9668         struct mlx5_flow_sub_actions_list *sample_act;
9669         uint32_t sample_act_pos = UINT32_MAX;
9670         uint32_t num_of_dest = 0;
9671         int tmp_actions_n = 0;
9672         uint32_t table;
9673         int ret = 0;
9674         const struct mlx5_flow_tunnel *tunnel;
9675         struct flow_grp_info grp_info = {
9676                 .external = !!dev_flow->external,
9677                 .transfer = !!attr->transfer,
9678                 .fdb_def_rule = !!priv->fdb_def_rule,
9679                 .skip_scale = !!dev_flow->skip_scale,
9680         };
9681
9682         if (!wks)
9683                 return rte_flow_error_set(error, ENOMEM,
9684                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9685                                           NULL,
9686                                           "failed to push flow workspace");
9687         rss_desc = &wks->rss_desc;
9688         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9689         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9690         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9691                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9692         /* update normal path action resource into last index of array */
9693         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9694         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9695                  flow_items_to_tunnel(items) :
9696                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9697                  flow_actions_to_tunnel(actions) :
9698                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9699         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9700                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9701         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9702                                 (dev, tunnel, attr, items, actions);
9703         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9704                                        &grp_info, error);
9705         if (ret)
9706                 return ret;
9707         dev_flow->dv.group = table;
9708         if (attr->transfer)
9709                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9710         if (priority == MLX5_FLOW_PRIO_RSVD)
9711                 priority = dev_conf->flow_prio - 1;
9712         /* number of actions must be set to 0 in case of dirty stack. */
9713         mhdr_res->actions_num = 0;
9714         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9715                 /*
9716                  * do not add decap action if match rule drops packet
9717                  * HW rejects rules with decap & drop
9718                  *
9719                  * if tunnel match rule was inserted before matching tunnel set
9720                  * rule flow table used in the match rule must be registered.
9721                  * current implementation handles that in the
9722                  * flow_dv_match_register() at the function end.
9723                  */
9724                 bool add_decap = true;
9725                 const struct rte_flow_action *ptr = actions;
9726
9727                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9728                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9729                                 add_decap = false;
9730                                 break;
9731                         }
9732                 }
9733                 if (add_decap) {
9734                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9735                                                            attr->transfer,
9736                                                            error))
9737                                 return -rte_errno;
9738                         dev_flow->dv.actions[actions_n++] =
9739                                         dev_flow->dv.encap_decap->action;
9740                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9741                 }
9742         }
9743         for (; !actions_end ; actions++) {
9744                 const struct rte_flow_action_queue *queue;
9745                 const struct rte_flow_action_rss *rss;
9746                 const struct rte_flow_action *action = actions;
9747                 const uint8_t *rss_key;
9748                 const struct rte_flow_action_meter *mtr;
9749                 struct mlx5_flow_tbl_resource *tbl;
9750                 struct mlx5_aso_age_action *age_act;
9751                 uint32_t port_id = 0;
9752                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9753                 int action_type = actions->type;
9754                 const struct rte_flow_action *found_action = NULL;
9755                 struct mlx5_flow_meter *fm = NULL;
9756                 uint32_t jump_group = 0;
9757
9758                 if (!mlx5_flow_os_action_supported(action_type))
9759                         return rte_flow_error_set(error, ENOTSUP,
9760                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9761                                                   actions,
9762                                                   "action not supported");
9763                 switch (action_type) {
9764                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9765                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9766                         break;
9767                 case RTE_FLOW_ACTION_TYPE_VOID:
9768                         break;
9769                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9770                         if (flow_dv_translate_action_port_id(dev, action,
9771                                                              &port_id, error))
9772                                 return -rte_errno;
9773                         port_id_resource.port_id = port_id;
9774                         MLX5_ASSERT(!handle->rix_port_id_action);
9775                         if (flow_dv_port_id_action_resource_register
9776                             (dev, &port_id_resource, dev_flow, error))
9777                                 return -rte_errno;
9778                         dev_flow->dv.actions[actions_n++] =
9779                                         dev_flow->dv.port_id_action->action;
9780                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9781                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9782                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9783                         num_of_dest++;
9784                         break;
9785                 case RTE_FLOW_ACTION_TYPE_FLAG:
9786                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9787                         dev_flow->handle->mark = 1;
9788                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9789                                 struct rte_flow_action_mark mark = {
9790                                         .id = MLX5_FLOW_MARK_DEFAULT,
9791                                 };
9792
9793                                 if (flow_dv_convert_action_mark(dev, &mark,
9794                                                                 mhdr_res,
9795                                                                 error))
9796                                         return -rte_errno;
9797                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9798                                 break;
9799                         }
9800                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9801                         /*
9802                          * Only one FLAG or MARK is supported per device flow
9803                          * right now. So the pointer to the tag resource must be
9804                          * zero before the register process.
9805                          */
9806                         MLX5_ASSERT(!handle->dvh.rix_tag);
9807                         if (flow_dv_tag_resource_register(dev, tag_be,
9808                                                           dev_flow, error))
9809                                 return -rte_errno;
9810                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9811                         dev_flow->dv.actions[actions_n++] =
9812                                         dev_flow->dv.tag_resource->action;
9813                         break;
9814                 case RTE_FLOW_ACTION_TYPE_MARK:
9815                         action_flags |= MLX5_FLOW_ACTION_MARK;
9816                         dev_flow->handle->mark = 1;
9817                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9818                                 const struct rte_flow_action_mark *mark =
9819                                         (const struct rte_flow_action_mark *)
9820                                                 actions->conf;
9821
9822                                 if (flow_dv_convert_action_mark(dev, mark,
9823                                                                 mhdr_res,
9824                                                                 error))
9825                                         return -rte_errno;
9826                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9827                                 break;
9828                         }
9829                         /* Fall-through */
9830                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9831                         /* Legacy (non-extensive) MARK action. */
9832                         tag_be = mlx5_flow_mark_set
9833                               (((const struct rte_flow_action_mark *)
9834                                (actions->conf))->id);
9835                         MLX5_ASSERT(!handle->dvh.rix_tag);
9836                         if (flow_dv_tag_resource_register(dev, tag_be,
9837                                                           dev_flow, error))
9838                                 return -rte_errno;
9839                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9840                         dev_flow->dv.actions[actions_n++] =
9841                                         dev_flow->dv.tag_resource->action;
9842                         break;
9843                 case RTE_FLOW_ACTION_TYPE_SET_META:
9844                         if (flow_dv_convert_action_set_meta
9845                                 (dev, mhdr_res, attr,
9846                                  (const struct rte_flow_action_set_meta *)
9847                                   actions->conf, error))
9848                                 return -rte_errno;
9849                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9850                         break;
9851                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9852                         if (flow_dv_convert_action_set_tag
9853                                 (dev, mhdr_res,
9854                                  (const struct rte_flow_action_set_tag *)
9855                                   actions->conf, error))
9856                                 return -rte_errno;
9857                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9858                         break;
9859                 case RTE_FLOW_ACTION_TYPE_DROP:
9860                         action_flags |= MLX5_FLOW_ACTION_DROP;
9861                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9862                         break;
9863                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9864                         queue = actions->conf;
9865                         rss_desc->queue_num = 1;
9866                         rss_desc->queue[0] = queue->index;
9867                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9868                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9869                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9870                         num_of_dest++;
9871                         break;
9872                 case RTE_FLOW_ACTION_TYPE_RSS:
9873                         rss = actions->conf;
9874                         memcpy(rss_desc->queue, rss->queue,
9875                                rss->queue_num * sizeof(uint16_t));
9876                         rss_desc->queue_num = rss->queue_num;
9877                         /* NULL RSS key indicates default RSS key. */
9878                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9879                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9880                         /*
9881                          * rss->level and rss.types should be set in advance
9882                          * when expanding items for RSS.
9883                          */
9884                         action_flags |= MLX5_FLOW_ACTION_RSS;
9885                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
9886                                 MLX5_FLOW_FATE_SHARED_RSS :
9887                                 MLX5_FLOW_FATE_QUEUE;
9888                         break;
9889                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
9890                         flow->age = (uint32_t)(uintptr_t)(action->conf);
9891                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
9892                         __atomic_fetch_add(&age_act->refcnt, 1,
9893                                            __ATOMIC_RELAXED);
9894                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
9895                         action_flags |= MLX5_FLOW_ACTION_AGE;
9896                         break;
9897                 case RTE_FLOW_ACTION_TYPE_AGE:
9898                         if (priv->sh->flow_hit_aso_en && attr->group) {
9899                                 flow->age = flow_dv_translate_create_aso_age
9900                                                 (dev, action->conf, error);
9901                                 if (!flow->age)
9902                                         return rte_flow_error_set
9903                                                 (error, rte_errno,
9904                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9905                                                  NULL,
9906                                                  "can't create ASO age action");
9907                                 dev_flow->dv.actions[actions_n++] =
9908                                           (flow_aso_age_get_by_idx
9909                                                 (dev, flow->age))->dr_action;
9910                                 action_flags |= MLX5_FLOW_ACTION_AGE;
9911                                 break;
9912                         }
9913                         /* Fall-through */
9914                 case RTE_FLOW_ACTION_TYPE_COUNT:
9915                         if (!dev_conf->devx) {
9916                                 return rte_flow_error_set
9917                                               (error, ENOTSUP,
9918                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9919                                                NULL,
9920                                                "count action not supported");
9921                         }
9922                         /* Save information first, will apply later. */
9923                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9924                                 count = action->conf;
9925                         else
9926                                 age = action->conf;
9927                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9928                         break;
9929                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9930                         dev_flow->dv.actions[actions_n++] =
9931                                                 priv->sh->pop_vlan_action;
9932                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9933                         break;
9934                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9935                         if (!(action_flags &
9936                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9937                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9938                         vlan.eth_proto = rte_be_to_cpu_16
9939                              ((((const struct rte_flow_action_of_push_vlan *)
9940                                                    actions->conf)->ethertype));
9941                         found_action = mlx5_flow_find_action
9942                                         (actions + 1,
9943                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9944                         if (found_action)
9945                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9946                         found_action = mlx5_flow_find_action
9947                                         (actions + 1,
9948                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9949                         if (found_action)
9950                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9951                         if (flow_dv_create_action_push_vlan
9952                                             (dev, attr, &vlan, dev_flow, error))
9953                                 return -rte_errno;
9954                         dev_flow->dv.actions[actions_n++] =
9955                                         dev_flow->dv.push_vlan_res->action;
9956                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9957                         break;
9958                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9959                         /* of_vlan_push action handled this action */
9960                         MLX5_ASSERT(action_flags &
9961                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9962                         break;
9963                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9964                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9965                                 break;
9966                         flow_dev_get_vlan_info_from_items(items, &vlan);
9967                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9968                         /* If no VLAN push - this is a modify header action */
9969                         if (flow_dv_convert_action_modify_vlan_vid
9970                                                 (mhdr_res, actions, error))
9971                                 return -rte_errno;
9972                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9973                         break;
9974                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9975                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9976                         if (flow_dv_create_action_l2_encap(dev, actions,
9977                                                            dev_flow,
9978                                                            attr->transfer,
9979                                                            error))
9980                                 return -rte_errno;
9981                         dev_flow->dv.actions[actions_n++] =
9982                                         dev_flow->dv.encap_decap->action;
9983                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9984                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9985                                 sample_act->action_flags |=
9986                                                         MLX5_FLOW_ACTION_ENCAP;
9987                         break;
9988                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9989                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9990                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9991                                                            attr->transfer,
9992                                                            error))
9993                                 return -rte_errno;
9994                         dev_flow->dv.actions[actions_n++] =
9995                                         dev_flow->dv.encap_decap->action;
9996                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9997                         break;
9998                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9999                         /* Handle encap with preceding decap. */
10000                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10001                                 if (flow_dv_create_action_raw_encap
10002                                         (dev, actions, dev_flow, attr, error))
10003                                         return -rte_errno;
10004                                 dev_flow->dv.actions[actions_n++] =
10005                                         dev_flow->dv.encap_decap->action;
10006                         } else {
10007                                 /* Handle encap without preceding decap. */
10008                                 if (flow_dv_create_action_l2_encap
10009                                     (dev, actions, dev_flow, attr->transfer,
10010                                      error))
10011                                         return -rte_errno;
10012                                 dev_flow->dv.actions[actions_n++] =
10013                                         dev_flow->dv.encap_decap->action;
10014                         }
10015                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10016                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10017                                 sample_act->action_flags |=
10018                                                         MLX5_FLOW_ACTION_ENCAP;
10019                         break;
10020                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10021                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10022                                 ;
10023                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10024                                 if (flow_dv_create_action_l2_decap
10025                                     (dev, dev_flow, attr->transfer, error))
10026                                         return -rte_errno;
10027                                 dev_flow->dv.actions[actions_n++] =
10028                                         dev_flow->dv.encap_decap->action;
10029                         }
10030                         /* If decap is followed by encap, handle it at encap. */
10031                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10032                         break;
10033                 case RTE_FLOW_ACTION_TYPE_JUMP:
10034                         jump_group = ((const struct rte_flow_action_jump *)
10035                                                         action->conf)->group;
10036                         grp_info.std_tbl_fix = 0;
10037                         grp_info.skip_scale = 0;
10038                         ret = mlx5_flow_group_to_table(dev, tunnel,
10039                                                        jump_group,
10040                                                        &table,
10041                                                        &grp_info, error);
10042                         if (ret)
10043                                 return ret;
10044                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10045                                                        attr->transfer,
10046                                                        !!dev_flow->external,
10047                                                        tunnel, jump_group, 0,
10048                                                        error);
10049                         if (!tbl)
10050                                 return rte_flow_error_set
10051                                                 (error, errno,
10052                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10053                                                  NULL,
10054                                                  "cannot create jump action.");
10055                         if (flow_dv_jump_tbl_resource_register
10056                             (dev, tbl, dev_flow, error)) {
10057                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10058                                 return rte_flow_error_set
10059                                                 (error, errno,
10060                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10061                                                  NULL,
10062                                                  "cannot create jump action.");
10063                         }
10064                         dev_flow->dv.actions[actions_n++] =
10065                                         dev_flow->dv.jump->action;
10066                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10067                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10068                         break;
10069                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10070                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10071                         if (flow_dv_convert_action_modify_mac
10072                                         (mhdr_res, actions, error))
10073                                 return -rte_errno;
10074                         action_flags |= actions->type ==
10075                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10076                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10077                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10078                         break;
10079                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10080                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10081                         if (flow_dv_convert_action_modify_ipv4
10082                                         (mhdr_res, actions, error))
10083                                 return -rte_errno;
10084                         action_flags |= actions->type ==
10085                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10086                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10087                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10088                         break;
10089                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10090                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10091                         if (flow_dv_convert_action_modify_ipv6
10092                                         (mhdr_res, actions, error))
10093                                 return -rte_errno;
10094                         action_flags |= actions->type ==
10095                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10096                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10097                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10098                         break;
10099                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10100                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10101                         if (flow_dv_convert_action_modify_tp
10102                                         (mhdr_res, actions, items,
10103                                          &flow_attr, dev_flow, !!(action_flags &
10104                                          MLX5_FLOW_ACTION_DECAP), error))
10105                                 return -rte_errno;
10106                         action_flags |= actions->type ==
10107                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10108                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10109                                         MLX5_FLOW_ACTION_SET_TP_DST;
10110                         break;
10111                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10112                         if (flow_dv_convert_action_modify_dec_ttl
10113                                         (mhdr_res, items, &flow_attr, dev_flow,
10114                                          !!(action_flags &
10115                                          MLX5_FLOW_ACTION_DECAP), error))
10116                                 return -rte_errno;
10117                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10118                         break;
10119                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10120                         if (flow_dv_convert_action_modify_ttl
10121                                         (mhdr_res, actions, items, &flow_attr,
10122                                          dev_flow, !!(action_flags &
10123                                          MLX5_FLOW_ACTION_DECAP), error))
10124                                 return -rte_errno;
10125                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10126                         break;
10127                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10128                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10129                         if (flow_dv_convert_action_modify_tcp_seq
10130                                         (mhdr_res, actions, error))
10131                                 return -rte_errno;
10132                         action_flags |= actions->type ==
10133                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10134                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10135                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10136                         break;
10137
10138                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10139                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10140                         if (flow_dv_convert_action_modify_tcp_ack
10141                                         (mhdr_res, actions, error))
10142                                 return -rte_errno;
10143                         action_flags |= actions->type ==
10144                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10145                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10146                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10147                         break;
10148                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10149                         if (flow_dv_convert_action_set_reg
10150                                         (mhdr_res, actions, error))
10151                                 return -rte_errno;
10152                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10153                         break;
10154                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10155                         if (flow_dv_convert_action_copy_mreg
10156                                         (dev, mhdr_res, actions, error))
10157                                 return -rte_errno;
10158                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10159                         break;
10160                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10161                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10162                         dev_flow->handle->fate_action =
10163                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10164                         break;
10165                 case RTE_FLOW_ACTION_TYPE_METER:
10166                         mtr = actions->conf;
10167                         if (!flow->meter) {
10168                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10169                                                             attr, error);
10170                                 if (!fm)
10171                                         return rte_flow_error_set(error,
10172                                                 rte_errno,
10173                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10174                                                 NULL,
10175                                                 "meter not found "
10176                                                 "or invalid parameters");
10177                                 flow->meter = fm->idx;
10178                         }
10179                         /* Set the meter action. */
10180                         if (!fm) {
10181                                 fm = mlx5_ipool_get(priv->sh->ipool
10182                                                 [MLX5_IPOOL_MTR], flow->meter);
10183                                 if (!fm)
10184                                         return rte_flow_error_set(error,
10185                                                 rte_errno,
10186                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10187                                                 NULL,
10188                                                 "meter not found "
10189                                                 "or invalid parameters");
10190                         }
10191                         dev_flow->dv.actions[actions_n++] =
10192                                 fm->mfts->meter_action;
10193                         action_flags |= MLX5_FLOW_ACTION_METER;
10194                         break;
10195                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10196                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10197                                                               actions, error))
10198                                 return -rte_errno;
10199                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10200                         break;
10201                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10202                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10203                                                               actions, error))
10204                                 return -rte_errno;
10205                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10206                         break;
10207                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10208                         sample_act_pos = actions_n;
10209                         ret = flow_dv_translate_action_sample(dev,
10210                                                               actions,
10211                                                               dev_flow, attr,
10212                                                               &num_of_dest,
10213                                                               sample_actions,
10214                                                               &sample_res,
10215                                                               error);
10216                         if (ret < 0)
10217                                 return ret;
10218                         actions_n++;
10219                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10220                         /* put encap action into group if work with port id */
10221                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10222                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10223                                 sample_act->action_flags |=
10224                                                         MLX5_FLOW_ACTION_ENCAP;
10225                         break;
10226                 case RTE_FLOW_ACTION_TYPE_END:
10227                         actions_end = true;
10228                         if (mhdr_res->actions_num) {
10229                                 /* create modify action if needed. */
10230                                 if (flow_dv_modify_hdr_resource_register
10231                                         (dev, mhdr_res, dev_flow, error))
10232                                         return -rte_errno;
10233                                 dev_flow->dv.actions[modify_action_position] =
10234                                         handle->dvh.modify_hdr->action;
10235                         }
10236                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10237                                 flow->counter =
10238                                         flow_dv_translate_create_counter(dev,
10239                                                 dev_flow, count, age);
10240
10241                                 if (!flow->counter)
10242                                         return rte_flow_error_set
10243                                                 (error, rte_errno,
10244                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10245                                                 NULL,
10246                                                 "cannot create counter"
10247                                                 " object.");
10248                                 dev_flow->dv.actions[actions_n] =
10249                                           (flow_dv_counter_get_by_idx(dev,
10250                                           flow->counter, NULL))->action;
10251                                 actions_n++;
10252                         }
10253                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10254                                 ret = flow_dv_create_action_sample(dev,
10255                                                           dev_flow,
10256                                                           num_of_dest,
10257                                                           &sample_res,
10258                                                           &mdest_res,
10259                                                           sample_actions,
10260                                                           action_flags,
10261                                                           error);
10262                                 if (ret < 0)
10263                                         return rte_flow_error_set
10264                                                 (error, rte_errno,
10265                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10266                                                 NULL,
10267                                                 "cannot create sample action");
10268                                 if (num_of_dest > 1) {
10269                                         dev_flow->dv.actions[sample_act_pos] =
10270                                         dev_flow->dv.dest_array_res->action;
10271                                 } else {
10272                                         dev_flow->dv.actions[sample_act_pos] =
10273                                         dev_flow->dv.sample_res->verbs_action;
10274                                 }
10275                         }
10276                         break;
10277                 default:
10278                         break;
10279                 }
10280                 if (mhdr_res->actions_num &&
10281                     modify_action_position == UINT32_MAX)
10282                         modify_action_position = actions_n++;
10283         }
10284         /*
10285          * For multiple destination (sample action with ratio=1), the encap
10286          * action and port id action will be combined into group action.
10287          * So need remove the original these actions in the flow and only
10288          * use the sample action instead of.
10289          */
10290         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10291                 int i;
10292                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10293
10294                 for (i = 0; i < actions_n; i++) {
10295                         if ((sample_act->dr_encap_action &&
10296                                 sample_act->dr_encap_action ==
10297                                 dev_flow->dv.actions[i]) ||
10298                                 (sample_act->dr_port_id_action &&
10299                                 sample_act->dr_port_id_action ==
10300                                 dev_flow->dv.actions[i]))
10301                                 continue;
10302                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10303                 }
10304                 memcpy((void *)dev_flow->dv.actions,
10305                                 (void *)temp_actions,
10306                                 tmp_actions_n * sizeof(void *));
10307                 actions_n = tmp_actions_n;
10308         }
10309         dev_flow->dv.actions_n = actions_n;
10310         dev_flow->act_flags = action_flags;
10311         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10312                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10313                 int item_type = items->type;
10314
10315                 if (!mlx5_flow_os_item_supported(item_type))
10316                         return rte_flow_error_set(error, ENOTSUP,
10317                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10318                                                   NULL, "item not supported");
10319                 switch (item_type) {
10320                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10321                         flow_dv_translate_item_port_id
10322                                 (dev, match_mask, match_value, items, attr);
10323                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10324                         break;
10325                 case RTE_FLOW_ITEM_TYPE_ETH:
10326                         flow_dv_translate_item_eth(match_mask, match_value,
10327                                                    items, tunnel,
10328                                                    dev_flow->dv.group);
10329                         matcher.priority = action_flags &
10330                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10331                                         !dev_flow->external ?
10332                                         MLX5_PRIORITY_MAP_L3 :
10333                                         MLX5_PRIORITY_MAP_L2;
10334                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10335                                              MLX5_FLOW_LAYER_OUTER_L2;
10336                         break;
10337                 case RTE_FLOW_ITEM_TYPE_VLAN:
10338                         flow_dv_translate_item_vlan(dev_flow,
10339                                                     match_mask, match_value,
10340                                                     items, tunnel,
10341                                                     dev_flow->dv.group);
10342                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10343                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10344                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10345                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10346                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10347                         break;
10348                 case RTE_FLOW_ITEM_TYPE_IPV4:
10349                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10350                                                   &item_flags, &tunnel);
10351                         flow_dv_translate_item_ipv4(match_mask, match_value,
10352                                                     items, tunnel,
10353                                                     dev_flow->dv.group);
10354                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10355                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10356                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10357                         if (items->mask != NULL &&
10358                             ((const struct rte_flow_item_ipv4 *)
10359                              items->mask)->hdr.next_proto_id) {
10360                                 next_protocol =
10361                                         ((const struct rte_flow_item_ipv4 *)
10362                                          (items->spec))->hdr.next_proto_id;
10363                                 next_protocol &=
10364                                         ((const struct rte_flow_item_ipv4 *)
10365                                          (items->mask))->hdr.next_proto_id;
10366                         } else {
10367                                 /* Reset for inner layer. */
10368                                 next_protocol = 0xff;
10369                         }
10370                         break;
10371                 case RTE_FLOW_ITEM_TYPE_IPV6:
10372                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10373                                                   &item_flags, &tunnel);
10374                         flow_dv_translate_item_ipv6(match_mask, match_value,
10375                                                     items, tunnel,
10376                                                     dev_flow->dv.group);
10377                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10378                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10379                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10380                         if (items->mask != NULL &&
10381                             ((const struct rte_flow_item_ipv6 *)
10382                              items->mask)->hdr.proto) {
10383                                 next_protocol =
10384                                         ((const struct rte_flow_item_ipv6 *)
10385                                          items->spec)->hdr.proto;
10386                                 next_protocol &=
10387                                         ((const struct rte_flow_item_ipv6 *)
10388                                          items->mask)->hdr.proto;
10389                         } else {
10390                                 /* Reset for inner layer. */
10391                                 next_protocol = 0xff;
10392                         }
10393                         break;
10394                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10395                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10396                                                              match_value,
10397                                                              items, tunnel);
10398                         last_item = tunnel ?
10399                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10400                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10401                         if (items->mask != NULL &&
10402                             ((const struct rte_flow_item_ipv6_frag_ext *)
10403                              items->mask)->hdr.next_header) {
10404                                 next_protocol =
10405                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10406                                  items->spec)->hdr.next_header;
10407                                 next_protocol &=
10408                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10409                                  items->mask)->hdr.next_header;
10410                         } else {
10411                                 /* Reset for inner layer. */
10412                                 next_protocol = 0xff;
10413                         }
10414                         break;
10415                 case RTE_FLOW_ITEM_TYPE_TCP:
10416                         flow_dv_translate_item_tcp(match_mask, match_value,
10417                                                    items, tunnel);
10418                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10419                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10420                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10421                         break;
10422                 case RTE_FLOW_ITEM_TYPE_UDP:
10423                         flow_dv_translate_item_udp(match_mask, match_value,
10424                                                    items, tunnel);
10425                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10426                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10427                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10428                         break;
10429                 case RTE_FLOW_ITEM_TYPE_GRE:
10430                         flow_dv_translate_item_gre(match_mask, match_value,
10431                                                    items, tunnel);
10432                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10433                         last_item = MLX5_FLOW_LAYER_GRE;
10434                         break;
10435                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10436                         flow_dv_translate_item_gre_key(match_mask,
10437                                                        match_value, items);
10438                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10439                         break;
10440                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10441                         flow_dv_translate_item_nvgre(match_mask, match_value,
10442                                                      items, tunnel);
10443                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10444                         last_item = MLX5_FLOW_LAYER_GRE;
10445                         break;
10446                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10447                         flow_dv_translate_item_vxlan(match_mask, match_value,
10448                                                      items, tunnel);
10449                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10450                         last_item = MLX5_FLOW_LAYER_VXLAN;
10451                         break;
10452                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10453                         flow_dv_translate_item_vxlan_gpe(match_mask,
10454                                                          match_value, items,
10455                                                          tunnel);
10456                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10457                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10458                         break;
10459                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10460                         flow_dv_translate_item_geneve(match_mask, match_value,
10461                                                       items, tunnel);
10462                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10463                         last_item = MLX5_FLOW_LAYER_GENEVE;
10464                         break;
10465                 case RTE_FLOW_ITEM_TYPE_MPLS:
10466                         flow_dv_translate_item_mpls(match_mask, match_value,
10467                                                     items, last_item, tunnel);
10468                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10469                         last_item = MLX5_FLOW_LAYER_MPLS;
10470                         break;
10471                 case RTE_FLOW_ITEM_TYPE_MARK:
10472                         flow_dv_translate_item_mark(dev, match_mask,
10473                                                     match_value, items);
10474                         last_item = MLX5_FLOW_ITEM_MARK;
10475                         break;
10476                 case RTE_FLOW_ITEM_TYPE_META:
10477                         flow_dv_translate_item_meta(dev, match_mask,
10478                                                     match_value, attr, items);
10479                         last_item = MLX5_FLOW_ITEM_METADATA;
10480                         break;
10481                 case RTE_FLOW_ITEM_TYPE_ICMP:
10482                         flow_dv_translate_item_icmp(match_mask, match_value,
10483                                                     items, tunnel);
10484                         last_item = MLX5_FLOW_LAYER_ICMP;
10485                         break;
10486                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10487                         flow_dv_translate_item_icmp6(match_mask, match_value,
10488                                                       items, tunnel);
10489                         last_item = MLX5_FLOW_LAYER_ICMP6;
10490                         break;
10491                 case RTE_FLOW_ITEM_TYPE_TAG:
10492                         flow_dv_translate_item_tag(dev, match_mask,
10493                                                    match_value, items);
10494                         last_item = MLX5_FLOW_ITEM_TAG;
10495                         break;
10496                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10497                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10498                                                         match_value, items);
10499                         last_item = MLX5_FLOW_ITEM_TAG;
10500                         break;
10501                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10502                         flow_dv_translate_item_tx_queue(dev, match_mask,
10503                                                         match_value,
10504                                                         items);
10505                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10506                         break;
10507                 case RTE_FLOW_ITEM_TYPE_GTP:
10508                         flow_dv_translate_item_gtp(match_mask, match_value,
10509                                                    items, tunnel);
10510                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10511                         last_item = MLX5_FLOW_LAYER_GTP;
10512                         break;
10513                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10514                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10515                                 /* Create it only the first time to be used. */
10516                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10517                                 if (ret)
10518                                         return rte_flow_error_set
10519                                                 (error, -ret,
10520                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10521                                                 NULL,
10522                                                 "cannot create eCPRI parser");
10523                         }
10524                         /* Adjust the length matcher and device flow value. */
10525                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10526                         dev_flow->dv.value.size =
10527                                         MLX5_ST_SZ_BYTES(fte_match_param);
10528                         flow_dv_translate_item_ecpri(dev, match_mask,
10529                                                      match_value, items);
10530                         /* No other protocol should follow eCPRI layer. */
10531                         last_item = MLX5_FLOW_LAYER_ECPRI;
10532                         break;
10533                 default:
10534                         break;
10535                 }
10536                 item_flags |= last_item;
10537         }
10538         /*
10539          * When E-Switch mode is enabled, we have two cases where we need to
10540          * set the source port manually.
10541          * The first one, is in case of Nic steering rule, and the second is
10542          * E-Switch rule where no port_id item was found. In both cases
10543          * the source port is set according the current port in use.
10544          */
10545         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10546             (priv->representor || priv->master)) {
10547                 if (flow_dv_translate_item_port_id(dev, match_mask,
10548                                                    match_value, NULL, attr))
10549                         return -rte_errno;
10550         }
10551 #ifdef RTE_LIBRTE_MLX5_DEBUG
10552         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10553                                               dev_flow->dv.value.buf));
10554 #endif
10555         /*
10556          * Layers may be already initialized from prefix flow if this dev_flow
10557          * is the suffix flow.
10558          */
10559         handle->layers |= item_flags;
10560         if (action_flags & MLX5_FLOW_ACTION_RSS)
10561                 flow_dv_hashfields_set(dev_flow, rss_desc);
10562         /* Register matcher. */
10563         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10564                                     matcher.mask.size);
10565         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10566                                                      matcher.priority);
10567         /* reserved field no needs to be set to 0 here. */
10568         tbl_key.domain = attr->transfer;
10569         tbl_key.direction = attr->egress;
10570         tbl_key.table_id = dev_flow->dv.group;
10571         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10572                                      tunnel, attr->group, error))
10573                 return -rte_errno;
10574         return 0;
10575 }
10576
10577 /**
10578  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10579  * and tunnel.
10580  *
10581  * @param[in, out] action
10582  *   Shred RSS action holding hash RX queue objects.
10583  * @param[in] hash_fields
10584  *   Defines combination of packet fields to participate in RX hash.
10585  * @param[in] tunnel
10586  *   Tunnel type
10587  * @param[in] hrxq_idx
10588  *   Hash RX queue index to set.
10589  *
10590  * @return
10591  *   0 on success, otherwise negative errno value.
10592  */
10593 static int
10594 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10595                               const uint64_t hash_fields,
10596                               const int tunnel,
10597                               uint32_t hrxq_idx)
10598 {
10599         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10600
10601         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10602         case MLX5_RSS_HASH_IPV4:
10603                 hrxqs[0] = hrxq_idx;
10604                 return 0;
10605         case MLX5_RSS_HASH_IPV4_TCP:
10606                 hrxqs[1] = hrxq_idx;
10607                 return 0;
10608         case MLX5_RSS_HASH_IPV4_UDP:
10609                 hrxqs[2] = hrxq_idx;
10610                 return 0;
10611         case MLX5_RSS_HASH_IPV6:
10612                 hrxqs[3] = hrxq_idx;
10613                 return 0;
10614         case MLX5_RSS_HASH_IPV6_TCP:
10615                 hrxqs[4] = hrxq_idx;
10616                 return 0;
10617         case MLX5_RSS_HASH_IPV6_UDP:
10618                 hrxqs[5] = hrxq_idx;
10619                 return 0;
10620         case MLX5_RSS_HASH_NONE:
10621                 hrxqs[6] = hrxq_idx;
10622                 return 0;
10623         default:
10624                 return -1;
10625         }
10626 }
10627
10628 /**
10629  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10630  * and tunnel.
10631  *
10632  * @param[in] dev
10633  *   Pointer to the Ethernet device structure.
10634  * @param[in] idx
10635  *   Shared RSS action ID holding hash RX queue objects.
10636  * @param[in] hash_fields
10637  *   Defines combination of packet fields to participate in RX hash.
10638  * @param[in] tunnel
10639  *   Tunnel type
10640  *
10641  * @return
10642  *   Valid hash RX queue index, otherwise 0.
10643  */
10644 static uint32_t
10645 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10646                                  const uint64_t hash_fields,
10647                                  const int tunnel)
10648 {
10649         struct mlx5_priv *priv = dev->data->dev_private;
10650         struct mlx5_shared_action_rss *shared_rss =
10651             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10652         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10653                                                         shared_rss->hrxq_tunnel;
10654
10655         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10656         case MLX5_RSS_HASH_IPV4:
10657                 return hrxqs[0];
10658         case MLX5_RSS_HASH_IPV4_TCP:
10659                 return hrxqs[1];
10660         case MLX5_RSS_HASH_IPV4_UDP:
10661                 return hrxqs[2];
10662         case MLX5_RSS_HASH_IPV6:
10663                 return hrxqs[3];
10664         case MLX5_RSS_HASH_IPV6_TCP:
10665                 return hrxqs[4];
10666         case MLX5_RSS_HASH_IPV6_UDP:
10667                 return hrxqs[5];
10668         case MLX5_RSS_HASH_NONE:
10669                 return hrxqs[6];
10670         default:
10671                 return 0;
10672         }
10673 }
10674
10675 /**
10676  * Retrieves hash RX queue suitable for the *flow*.
10677  * If shared action configured for *flow* suitable hash RX queue will be
10678  * retrieved from attached shared action.
10679  *
10680  * @param[in] dev
10681  *   Pointer to the Ethernet device structure.
10682  * @param[in] dev_flow
10683  *   Pointer to the sub flow.
10684  * @param[in] rss_desc
10685  *   Pointer to the RSS descriptor.
10686  * @param[out] hrxq
10687  *   Pointer to retrieved hash RX queue object.
10688  *
10689  * @return
10690  *   Valid hash RX queue index, otherwise 0 and rte_errno is set.
10691  */
10692 static uint32_t
10693 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow,
10694                        struct mlx5_flow_rss_desc *rss_desc,
10695                        struct mlx5_hrxq **hrxq)
10696 {
10697         struct mlx5_priv *priv = dev->data->dev_private;
10698         uint32_t hrxq_idx;
10699
10700         if (rss_desc->shared_rss) {
10701                 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10702                                 (dev, rss_desc->shared_rss,
10703                                  dev_flow->hash_fields,
10704                                  !!(dev_flow->handle->layers &
10705                                     MLX5_FLOW_LAYER_TUNNEL));
10706                 if (hrxq_idx)
10707                         *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10708                                                hrxq_idx);
10709         } else {
10710                 *hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
10711                                              &hrxq_idx);
10712         }
10713         return hrxq_idx;
10714 }
10715
10716 /**
10717  * Apply the flow to the NIC, lock free,
10718  * (mutex should be acquired by caller).
10719  *
10720  * @param[in] dev
10721  *   Pointer to the Ethernet device structure.
10722  * @param[in, out] flow
10723  *   Pointer to flow structure.
10724  * @param[out] error
10725  *   Pointer to error structure.
10726  *
10727  * @return
10728  *   0 on success, a negative errno value otherwise and rte_errno is set.
10729  */
10730 static int
10731 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10732               struct rte_flow_error *error)
10733 {
10734         struct mlx5_flow_dv_workspace *dv;
10735         struct mlx5_flow_handle *dh;
10736         struct mlx5_flow_handle_dv *dv_h;
10737         struct mlx5_flow *dev_flow;
10738         struct mlx5_priv *priv = dev->data->dev_private;
10739         uint32_t handle_idx;
10740         int n;
10741         int err;
10742         int idx;
10743         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10744         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10745
10746         MLX5_ASSERT(wks);
10747         if (rss_desc->shared_rss) {
10748                 dh = wks->flows[wks->flow_idx - 1].handle;
10749                 MLX5_ASSERT(dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS);
10750                 dh->rix_srss = rss_desc->shared_rss;
10751         }
10752         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10753                 dev_flow = &wks->flows[idx];
10754                 dv = &dev_flow->dv;
10755                 dh = dev_flow->handle;
10756                 dv_h = &dh->dvh;
10757                 n = dv->actions_n;
10758                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10759                         if (dv->transfer) {
10760                                 dv->actions[n++] = priv->sh->esw_drop_action;
10761                         } else {
10762                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10763                                 dv->actions[n++] =
10764                                                 priv->drop_queue.hrxq->action;
10765                         }
10766                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10767                            !dv_h->rix_sample && !dv_h->rix_dest_array) ||
10768                             (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS)) {
10769                         struct mlx5_hrxq *hrxq = NULL;
10770                         uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10771                                         (dev, dev_flow, rss_desc, &hrxq);
10772                         if (!hrxq) {
10773                                 rte_flow_error_set
10774                                         (error, rte_errno,
10775                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10776                                          "cannot get hash queue");
10777                                 goto error;
10778                         }
10779                         if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
10780                                 dh->rix_hrxq = hrxq_idx;
10781                         dv->actions[n++] = hrxq->action;
10782                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10783                         if (!priv->sh->default_miss_action) {
10784                                 rte_flow_error_set
10785                                         (error, rte_errno,
10786                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10787                                          "default miss action not be created.");
10788                                 goto error;
10789                         }
10790                         dv->actions[n++] = priv->sh->default_miss_action;
10791                 }
10792                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10793                                                (void *)&dv->value, n,
10794                                                dv->actions, &dh->drv_flow);
10795                 if (err) {
10796                         rte_flow_error_set(error, errno,
10797                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10798                                            NULL,
10799                                            "hardware refuses to create flow");
10800                         goto error;
10801                 }
10802                 if (priv->vmwa_context &&
10803                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10804                         /*
10805                          * The rule contains the VLAN pattern.
10806                          * For VF we are going to create VLAN
10807                          * interface to make hypervisor set correct
10808                          * e-Switch vport context.
10809                          */
10810                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10811                 }
10812         }
10813         return 0;
10814 error:
10815         err = rte_errno; /* Save rte_errno before cleanup. */
10816         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10817                        handle_idx, dh, next) {
10818                 /* hrxq is union, don't clear it if the flag is not set. */
10819                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10820                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10821                         dh->rix_hrxq = 0;
10822                 }
10823                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10824                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10825         }
10826         if (rss_desc->shared_rss)
10827                 wks->flows[wks->flow_idx - 1].handle->rix_srss = 0;
10828         rte_errno = err; /* Restore rte_errno. */
10829         return -rte_errno;
10830 }
10831
10832 void
10833 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
10834                           struct mlx5_cache_entry *entry)
10835 {
10836         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
10837                                                           entry);
10838
10839         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
10840         mlx5_free(cache);
10841 }
10842
10843 /**
10844  * Release the flow matcher.
10845  *
10846  * @param dev
10847  *   Pointer to Ethernet device.
10848  * @param handle
10849  *   Pointer to mlx5_flow_handle.
10850  *
10851  * @return
10852  *   1 while a reference on it exists, 0 when freed.
10853  */
10854 static int
10855 flow_dv_matcher_release(struct rte_eth_dev *dev,
10856                         struct mlx5_flow_handle *handle)
10857 {
10858         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10859         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
10860                                                             typeof(*tbl), tbl);
10861         int ret;
10862
10863         MLX5_ASSERT(matcher->matcher_object);
10864         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
10865         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
10866         return ret;
10867 }
10868
10869 /**
10870  * Release encap_decap resource.
10871  *
10872  * @param list
10873  *   Pointer to the hash list.
10874  * @param entry
10875  *   Pointer to exist resource entry object.
10876  */
10877 void
10878 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
10879                               struct mlx5_hlist_entry *entry)
10880 {
10881         struct mlx5_dev_ctx_shared *sh = list->ctx;
10882         struct mlx5_flow_dv_encap_decap_resource *res =
10883                 container_of(entry, typeof(*res), entry);
10884
10885         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10886         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
10887 }
10888
10889 /**
10890  * Release an encap/decap resource.
10891  *
10892  * @param dev
10893  *   Pointer to Ethernet device.
10894  * @param encap_decap_idx
10895  *   Index of encap decap resource.
10896  *
10897  * @return
10898  *   1 while a reference on it exists, 0 when freed.
10899  */
10900 static int
10901 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10902                                      uint32_t encap_decap_idx)
10903 {
10904         struct mlx5_priv *priv = dev->data->dev_private;
10905         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10906
10907         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10908                                         encap_decap_idx);
10909         if (!cache_resource)
10910                 return 0;
10911         MLX5_ASSERT(cache_resource->action);
10912         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
10913                                      &cache_resource->entry);
10914 }
10915
10916 /**
10917  * Release an jump to table action resource.
10918  *
10919  * @param dev
10920  *   Pointer to Ethernet device.
10921  * @param handle
10922  *   Pointer to mlx5_flow_handle.
10923  *
10924  * @return
10925  *   1 while a reference on it exists, 0 when freed.
10926  */
10927 static int
10928 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10929                                   struct mlx5_flow_handle *handle)
10930 {
10931         struct mlx5_priv *priv = dev->data->dev_private;
10932         struct mlx5_flow_tbl_data_entry *tbl_data;
10933
10934         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10935                              handle->rix_jump);
10936         if (!tbl_data)
10937                 return 0;
10938         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
10939 }
10940
10941 void
10942 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
10943                          struct mlx5_hlist_entry *entry)
10944 {
10945         struct mlx5_flow_dv_modify_hdr_resource *res =
10946                 container_of(entry, typeof(*res), entry);
10947
10948         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10949         mlx5_free(entry);
10950 }
10951
10952 /**
10953  * Release a modify-header resource.
10954  *
10955  * @param dev
10956  *   Pointer to Ethernet device.
10957  * @param handle
10958  *   Pointer to mlx5_flow_handle.
10959  *
10960  * @return
10961  *   1 while a reference on it exists, 0 when freed.
10962  */
10963 static int
10964 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10965                                     struct mlx5_flow_handle *handle)
10966 {
10967         struct mlx5_priv *priv = dev->data->dev_private;
10968         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
10969
10970         MLX5_ASSERT(entry->action);
10971         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
10972 }
10973
10974 void
10975 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
10976                           struct mlx5_cache_entry *entry)
10977 {
10978         struct mlx5_dev_ctx_shared *sh = list->ctx;
10979         struct mlx5_flow_dv_port_id_action_resource *cache =
10980                         container_of(entry, typeof(*cache), entry);
10981
10982         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
10983         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
10984 }
10985
10986 /**
10987  * Release port ID action resource.
10988  *
10989  * @param dev
10990  *   Pointer to Ethernet device.
10991  * @param handle
10992  *   Pointer to mlx5_flow_handle.
10993  *
10994  * @return
10995  *   1 while a reference on it exists, 0 when freed.
10996  */
10997 static int
10998 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10999                                         uint32_t port_id)
11000 {
11001         struct mlx5_priv *priv = dev->data->dev_private;
11002         struct mlx5_flow_dv_port_id_action_resource *cache;
11003
11004         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11005         if (!cache)
11006                 return 0;
11007         MLX5_ASSERT(cache->action);
11008         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11009                                      &cache->entry);
11010 }
11011
11012 /**
11013  * Release shared RSS action resource.
11014  *
11015  * @param dev
11016  *   Pointer to Ethernet device.
11017  * @param srss
11018  *   Shared RSS action index.
11019  */
11020 static void
11021 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11022 {
11023         struct mlx5_priv *priv = dev->data->dev_private;
11024         struct mlx5_shared_action_rss *shared_rss;
11025
11026         shared_rss = mlx5_ipool_get
11027                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11028         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11029 }
11030
11031 void
11032 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11033                             struct mlx5_cache_entry *entry)
11034 {
11035         struct mlx5_dev_ctx_shared *sh = list->ctx;
11036         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11037                         container_of(entry, typeof(*cache), entry);
11038
11039         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11040         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11041 }
11042
11043 /**
11044  * Release push vlan action resource.
11045  *
11046  * @param dev
11047  *   Pointer to Ethernet device.
11048  * @param handle
11049  *   Pointer to mlx5_flow_handle.
11050  *
11051  * @return
11052  *   1 while a reference on it exists, 0 when freed.
11053  */
11054 static int
11055 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11056                                           struct mlx5_flow_handle *handle)
11057 {
11058         struct mlx5_priv *priv = dev->data->dev_private;
11059         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11060         uint32_t idx = handle->dvh.rix_push_vlan;
11061
11062         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11063         if (!cache)
11064                 return 0;
11065         MLX5_ASSERT(cache->action);
11066         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11067                                      &cache->entry);
11068 }
11069
11070 /**
11071  * Release the fate resource.
11072  *
11073  * @param dev
11074  *   Pointer to Ethernet device.
11075  * @param handle
11076  *   Pointer to mlx5_flow_handle.
11077  */
11078 static void
11079 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11080                                struct mlx5_flow_handle *handle)
11081 {
11082         if (!handle->rix_fate)
11083                 return;
11084         switch (handle->fate_action) {
11085         case MLX5_FLOW_FATE_QUEUE:
11086                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11087                 break;
11088         case MLX5_FLOW_FATE_JUMP:
11089                 flow_dv_jump_tbl_resource_release(dev, handle);
11090                 break;
11091         case MLX5_FLOW_FATE_PORT_ID:
11092                 flow_dv_port_id_action_resource_release(dev,
11093                                 handle->rix_port_id_action);
11094                 break;
11095         case MLX5_FLOW_FATE_SHARED_RSS:
11096                 flow_dv_shared_rss_action_release(dev, handle->rix_srss);
11097                 break;
11098         default:
11099                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11100                 break;
11101         }
11102         handle->rix_fate = 0;
11103 }
11104
11105 void
11106 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11107                          struct mlx5_cache_entry *entry)
11108 {
11109         struct mlx5_flow_dv_sample_resource *cache_resource =
11110                         container_of(entry, typeof(*cache_resource), entry);
11111         struct rte_eth_dev *dev = cache_resource->dev;
11112         struct mlx5_priv *priv = dev->data->dev_private;
11113
11114         if (cache_resource->verbs_action)
11115                 claim_zero(mlx5_glue->destroy_flow_action
11116                                 (cache_resource->verbs_action));
11117         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11118                 if (cache_resource->default_miss)
11119                         claim_zero(mlx5_glue->destroy_flow_action
11120                           (cache_resource->default_miss));
11121         }
11122         if (cache_resource->normal_path_tbl)
11123                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11124                         cache_resource->normal_path_tbl);
11125         flow_dv_sample_sub_actions_release(dev,
11126                                 &cache_resource->sample_idx);
11127         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11128                         cache_resource->idx);
11129         DRV_LOG(DEBUG, "sample resource %p: removed",
11130                 (void *)cache_resource);
11131 }
11132
11133 /**
11134  * Release an sample resource.
11135  *
11136  * @param dev
11137  *   Pointer to Ethernet device.
11138  * @param handle
11139  *   Pointer to mlx5_flow_handle.
11140  *
11141  * @return
11142  *   1 while a reference on it exists, 0 when freed.
11143  */
11144 static int
11145 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11146                                      struct mlx5_flow_handle *handle)
11147 {
11148         struct mlx5_priv *priv = dev->data->dev_private;
11149         struct mlx5_flow_dv_sample_resource *cache_resource;
11150
11151         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11152                          handle->dvh.rix_sample);
11153         if (!cache_resource)
11154                 return 0;
11155         MLX5_ASSERT(cache_resource->verbs_action);
11156         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11157                                      &cache_resource->entry);
11158 }
11159
11160 void
11161 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11162                              struct mlx5_cache_entry *entry)
11163 {
11164         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11165                         container_of(entry, typeof(*cache_resource), entry);
11166         struct rte_eth_dev *dev = cache_resource->dev;
11167         struct mlx5_priv *priv = dev->data->dev_private;
11168         uint32_t i = 0;
11169
11170         MLX5_ASSERT(cache_resource->action);
11171         if (cache_resource->action)
11172                 claim_zero(mlx5_glue->destroy_flow_action
11173                                         (cache_resource->action));
11174         for (; i < cache_resource->num_of_dest; i++)
11175                 flow_dv_sample_sub_actions_release(dev,
11176                                 &cache_resource->sample_idx[i]);
11177         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11178                         cache_resource->idx);
11179         DRV_LOG(DEBUG, "destination array resource %p: removed",
11180                 (void *)cache_resource);
11181 }
11182
11183 /**
11184  * Release an destination array resource.
11185  *
11186  * @param dev
11187  *   Pointer to Ethernet device.
11188  * @param handle
11189  *   Pointer to mlx5_flow_handle.
11190  *
11191  * @return
11192  *   1 while a reference on it exists, 0 when freed.
11193  */
11194 static int
11195 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11196                                     struct mlx5_flow_handle *handle)
11197 {
11198         struct mlx5_priv *priv = dev->data->dev_private;
11199         struct mlx5_flow_dv_dest_array_resource *cache;
11200
11201         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11202                                handle->dvh.rix_dest_array);
11203         if (!cache)
11204                 return 0;
11205         MLX5_ASSERT(cache->action);
11206         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11207                                      &cache->entry);
11208 }
11209
11210 /**
11211  * Remove the flow from the NIC but keeps it in memory.
11212  * Lock free, (mutex should be acquired by caller).
11213  *
11214  * @param[in] dev
11215  *   Pointer to Ethernet device.
11216  * @param[in, out] flow
11217  *   Pointer to flow structure.
11218  */
11219 static void
11220 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11221 {
11222         struct mlx5_flow_handle *dh;
11223         uint32_t handle_idx;
11224         struct mlx5_priv *priv = dev->data->dev_private;
11225
11226         if (!flow)
11227                 return;
11228         handle_idx = flow->dev_handles;
11229         while (handle_idx) {
11230                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11231                                     handle_idx);
11232                 if (!dh)
11233                         return;
11234                 if (dh->drv_flow) {
11235                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11236                         dh->drv_flow = NULL;
11237                 }
11238                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11239                         flow_dv_fate_resource_release(dev, dh);
11240                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11241                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11242                 handle_idx = dh->next.next;
11243         }
11244 }
11245
11246 /**
11247  * Remove the flow from the NIC and the memory.
11248  * Lock free, (mutex should be acquired by caller).
11249  *
11250  * @param[in] dev
11251  *   Pointer to the Ethernet device structure.
11252  * @param[in, out] flow
11253  *   Pointer to flow structure.
11254  */
11255 static void
11256 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11257 {
11258         struct mlx5_flow_handle *dev_handle;
11259         struct mlx5_priv *priv = dev->data->dev_private;
11260
11261         if (!flow)
11262                 return;
11263         flow_dv_remove(dev, flow);
11264         if (flow->counter) {
11265                 flow_dv_counter_free(dev, flow->counter);
11266                 flow->counter = 0;
11267         }
11268         if (flow->meter) {
11269                 struct mlx5_flow_meter *fm;
11270
11271                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11272                                     flow->meter);
11273                 if (fm)
11274                         mlx5_flow_meter_detach(fm);
11275                 flow->meter = 0;
11276         }
11277         if (flow->age)
11278                 flow_dv_aso_age_release(dev, flow->age);
11279         while (flow->dev_handles) {
11280                 uint32_t tmp_idx = flow->dev_handles;
11281
11282                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11283                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11284                 if (!dev_handle)
11285                         return;
11286                 flow->dev_handles = dev_handle->next.next;
11287                 if (dev_handle->dvh.matcher)
11288                         flow_dv_matcher_release(dev, dev_handle);
11289                 if (dev_handle->dvh.rix_sample)
11290                         flow_dv_sample_resource_release(dev, dev_handle);
11291                 if (dev_handle->dvh.rix_dest_array)
11292                         flow_dv_dest_array_resource_release(dev, dev_handle);
11293                 if (dev_handle->dvh.rix_encap_decap)
11294                         flow_dv_encap_decap_resource_release(dev,
11295                                 dev_handle->dvh.rix_encap_decap);
11296                 if (dev_handle->dvh.modify_hdr)
11297                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11298                 if (dev_handle->dvh.rix_push_vlan)
11299                         flow_dv_push_vlan_action_resource_release(dev,
11300                                                                   dev_handle);
11301                 if (dev_handle->dvh.rix_tag)
11302                         flow_dv_tag_release(dev,
11303                                             dev_handle->dvh.rix_tag);
11304                 flow_dv_fate_resource_release(dev, dev_handle);
11305                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11306                            tmp_idx);
11307         }
11308 }
11309
11310 /**
11311  * Release array of hash RX queue objects.
11312  * Helper function.
11313  *
11314  * @param[in] dev
11315  *   Pointer to the Ethernet device structure.
11316  * @param[in, out] hrxqs
11317  *   Array of hash RX queue objects.
11318  *
11319  * @return
11320  *   Total number of references to hash RX queue objects in *hrxqs* array
11321  *   after this operation.
11322  */
11323 static int
11324 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11325                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11326 {
11327         size_t i;
11328         int remaining = 0;
11329
11330         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11331                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11332
11333                 if (!ret)
11334                         (*hrxqs)[i] = 0;
11335                 remaining += ret;
11336         }
11337         return remaining;
11338 }
11339
11340 /**
11341  * Release all hash RX queue objects representing shared RSS action.
11342  *
11343  * @param[in] dev
11344  *   Pointer to the Ethernet device structure.
11345  * @param[in, out] action
11346  *   Shared RSS action to remove hash RX queue objects from.
11347  *
11348  * @return
11349  *   Total number of references to hash RX queue objects stored in *action*
11350  *   after this operation.
11351  *   Expected to be 0 if no external references held.
11352  */
11353 static int
11354 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11355                                  struct mlx5_shared_action_rss *action)
11356 {
11357         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11358                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11359 }
11360
11361 /**
11362  * Setup shared RSS action.
11363  * Prepare set of hash RX queue objects sufficient to handle all valid
11364  * hash_fields combinations (see enum ibv_rx_hash_fields).
11365  *
11366  * @param[in] dev
11367  *   Pointer to the Ethernet device structure.
11368  * @param[in] action_idx
11369  *   Shared RSS action ipool index.
11370  * @param[in, out] action
11371  *   Partially initialized shared RSS action.
11372  * @param[out] error
11373  *   Perform verbose error reporting if not NULL. Initialized in case of
11374  *   error only.
11375  *
11376  * @return
11377  *   0 on success, otherwise negative errno value.
11378  */
11379 static int
11380 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11381                            uint32_t action_idx,
11382                            struct mlx5_shared_action_rss *action,
11383                            struct rte_flow_error *error)
11384 {
11385         struct mlx5_flow_rss_desc rss_desc = { 0 };
11386         size_t i;
11387         int err;
11388
11389         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11390                 return rte_flow_error_set(error, rte_errno,
11391                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11392                                           "cannot setup indirection table");
11393         }
11394         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11395         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11396         rss_desc.const_q = action->origin.queue;
11397         rss_desc.queue_num = action->origin.queue_num;
11398         /* Set non-zero value to indicate a shared RSS. */
11399         rss_desc.shared_rss = action_idx;
11400         rss_desc.ind_tbl = action->ind_tbl;
11401         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11402                 uint32_t hrxq_idx;
11403                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11404                 int tunnel;
11405
11406                 for (tunnel = 0; tunnel < 2; tunnel++) {
11407                         rss_desc.tunnel = tunnel;
11408                         rss_desc.hash_fields = hash_fields;
11409                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11410                         if (!hrxq_idx) {
11411                                 rte_flow_error_set
11412                                         (error, rte_errno,
11413                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11414                                          "cannot get hash queue");
11415                                 goto error_hrxq_new;
11416                         }
11417                         err = __flow_dv_action_rss_hrxq_set
11418                                 (action, hash_fields, tunnel, hrxq_idx);
11419                         MLX5_ASSERT(!err);
11420                 }
11421         }
11422         return 0;
11423 error_hrxq_new:
11424         err = rte_errno;
11425         __flow_dv_action_rss_hrxqs_release(dev, action);
11426         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11427                 action->ind_tbl = NULL;
11428         rte_errno = err;
11429         return -rte_errno;
11430 }
11431
11432 /**
11433  * Create shared RSS action.
11434  *
11435  * @param[in] dev
11436  *   Pointer to the Ethernet device structure.
11437  * @param[in] conf
11438  *   Shared action configuration.
11439  * @param[in] rss
11440  *   RSS action specification used to create shared action.
11441  * @param[out] error
11442  *   Perform verbose error reporting if not NULL. Initialized in case of
11443  *   error only.
11444  *
11445  * @return
11446  *   A valid shared action ID in case of success, 0 otherwise and
11447  *   rte_errno is set.
11448  */
11449 static uint32_t
11450 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11451                             const struct rte_flow_shared_action_conf *conf,
11452                             const struct rte_flow_action_rss *rss,
11453                             struct rte_flow_error *error)
11454 {
11455         struct mlx5_priv *priv = dev->data->dev_private;
11456         struct mlx5_shared_action_rss *shared_action = NULL;
11457         void *queue = NULL;
11458         struct rte_flow_action_rss *origin;
11459         const uint8_t *rss_key;
11460         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11461         uint32_t idx;
11462
11463         RTE_SET_USED(conf);
11464         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11465                             0, SOCKET_ID_ANY);
11466         shared_action = mlx5_ipool_zmalloc
11467                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11468         if (!shared_action || !queue) {
11469                 rte_flow_error_set(error, ENOMEM,
11470                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11471                                    "cannot allocate resource memory");
11472                 goto error_rss_init;
11473         }
11474         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11475                 rte_flow_error_set(error, E2BIG,
11476                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11477                                    "rss action number out of range");
11478                 goto error_rss_init;
11479         }
11480         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11481                                              sizeof(*shared_action->ind_tbl),
11482                                              0, SOCKET_ID_ANY);
11483         if (!shared_action->ind_tbl) {
11484                 rte_flow_error_set(error, ENOMEM,
11485                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11486                                    "cannot allocate resource memory");
11487                 goto error_rss_init;
11488         }
11489         memcpy(queue, rss->queue, queue_size);
11490         shared_action->ind_tbl->queues = queue;
11491         shared_action->ind_tbl->queues_n = rss->queue_num;
11492         origin = &shared_action->origin;
11493         origin->func = rss->func;
11494         origin->level = rss->level;
11495         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11496         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11497         /* NULL RSS key indicates default RSS key. */
11498         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11499         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11500         origin->key = &shared_action->key[0];
11501         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11502         origin->queue = queue;
11503         origin->queue_num = rss->queue_num;
11504         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11505                 goto error_rss_init;
11506         rte_spinlock_init(&shared_action->action_rss_sl);
11507         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11508         rte_spinlock_lock(&priv->shared_act_sl);
11509         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11510                      &priv->rss_shared_actions, idx, shared_action, next);
11511         rte_spinlock_unlock(&priv->shared_act_sl);
11512         return idx;
11513 error_rss_init:
11514         if (shared_action) {
11515                 if (shared_action->ind_tbl)
11516                         mlx5_free(shared_action->ind_tbl);
11517                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11518                                 idx);
11519         }
11520         if (queue)
11521                 mlx5_free(queue);
11522         return 0;
11523 }
11524
11525 /**
11526  * Destroy the shared RSS action.
11527  * Release related hash RX queue objects.
11528  *
11529  * @param[in] dev
11530  *   Pointer to the Ethernet device structure.
11531  * @param[in] idx
11532  *   The shared RSS action object ID to be removed.
11533  * @param[out] error
11534  *   Perform verbose error reporting if not NULL. Initialized in case of
11535  *   error only.
11536  *
11537  * @return
11538  *   0 on success, otherwise negative errno value.
11539  */
11540 static int
11541 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11542                              struct rte_flow_error *error)
11543 {
11544         struct mlx5_priv *priv = dev->data->dev_private;
11545         struct mlx5_shared_action_rss *shared_rss =
11546             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11547         uint32_t old_refcnt = 1;
11548         int remaining;
11549         uint16_t *queue = NULL;
11550
11551         if (!shared_rss)
11552                 return rte_flow_error_set(error, EINVAL,
11553                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11554                                           "invalid shared action");
11555         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11556         if (remaining)
11557                 return rte_flow_error_set(error, EBUSY,
11558                                           RTE_FLOW_ERROR_TYPE_ACTION,
11559                                           NULL,
11560                                           "shared rss hrxq has references");
11561         queue = shared_rss->ind_tbl->queues;
11562         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11563         if (remaining)
11564                 return rte_flow_error_set(error, EBUSY,
11565                                           RTE_FLOW_ERROR_TYPE_ACTION,
11566                                           NULL,
11567                                           "shared rss indirection table has"
11568                                           " references");
11569         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11570                                          0, 0, __ATOMIC_ACQUIRE,
11571                                          __ATOMIC_RELAXED))
11572                 return rte_flow_error_set(error, EBUSY,
11573                                           RTE_FLOW_ERROR_TYPE_ACTION,
11574                                           NULL,
11575                                           "shared rss has references");
11576         mlx5_free(queue);
11577         rte_spinlock_lock(&priv->shared_act_sl);
11578         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11579                      &priv->rss_shared_actions, idx, shared_rss, next);
11580         rte_spinlock_unlock(&priv->shared_act_sl);
11581         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11582                         idx);
11583         return 0;
11584 }
11585
11586 /**
11587  * Create shared action, lock free,
11588  * (mutex should be acquired by caller).
11589  * Dispatcher for action type specific call.
11590  *
11591  * @param[in] dev
11592  *   Pointer to the Ethernet device structure.
11593  * @param[in] conf
11594  *   Shared action configuration.
11595  * @param[in] action
11596  *   Action specification used to create shared action.
11597  * @param[out] error
11598  *   Perform verbose error reporting if not NULL. Initialized in case of
11599  *   error only.
11600  *
11601  * @return
11602  *   A valid shared action handle in case of success, NULL otherwise and
11603  *   rte_errno is set.
11604  */
11605 static struct rte_flow_shared_action *
11606 flow_dv_action_create(struct rte_eth_dev *dev,
11607                       const struct rte_flow_shared_action_conf *conf,
11608                       const struct rte_flow_action *action,
11609                       struct rte_flow_error *err)
11610 {
11611         uint32_t idx = 0;
11612         uint32_t ret = 0;
11613
11614         switch (action->type) {
11615         case RTE_FLOW_ACTION_TYPE_RSS:
11616                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11617                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11618                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11619                 break;
11620         case RTE_FLOW_ACTION_TYPE_AGE:
11621                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11622                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11623                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11624                 if (ret) {
11625                         struct mlx5_aso_age_action *aso_age =
11626                                               flow_aso_age_get_by_idx(dev, ret);
11627
11628                         if (!aso_age->age_params.context)
11629                                 aso_age->age_params.context =
11630                                                          (void *)(uintptr_t)idx;
11631                 }
11632                 break;
11633         default:
11634                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11635                                    NULL, "action type not supported");
11636                 break;
11637         }
11638         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11639 }
11640
11641 /**
11642  * Destroy the shared action.
11643  * Release action related resources on the NIC and the memory.
11644  * Lock free, (mutex should be acquired by caller).
11645  * Dispatcher for action type specific call.
11646  *
11647  * @param[in] dev
11648  *   Pointer to the Ethernet device structure.
11649  * @param[in] action
11650  *   The shared action object to be removed.
11651  * @param[out] error
11652  *   Perform verbose error reporting if not NULL. Initialized in case of
11653  *   error only.
11654  *
11655  * @return
11656  *   0 on success, otherwise negative errno value.
11657  */
11658 static int
11659 flow_dv_action_destroy(struct rte_eth_dev *dev,
11660                        struct rte_flow_shared_action *action,
11661                        struct rte_flow_error *error)
11662 {
11663         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11664         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11665         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11666         int ret;
11667
11668         switch (type) {
11669         case MLX5_SHARED_ACTION_TYPE_RSS:
11670                 return __flow_dv_action_rss_release(dev, idx, error);
11671         case MLX5_SHARED_ACTION_TYPE_AGE:
11672                 ret = flow_dv_aso_age_release(dev, idx);
11673                 if (ret)
11674                         /*
11675                          * In this case, the last flow has a reference will
11676                          * actually release the age action.
11677                          */
11678                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11679                                 " released with references %d.", idx, ret);
11680                 return 0;
11681         default:
11682                 return rte_flow_error_set(error, ENOTSUP,
11683                                           RTE_FLOW_ERROR_TYPE_ACTION,
11684                                           NULL,
11685                                           "action type not supported");
11686         }
11687 }
11688
11689 /**
11690  * Updates in place shared RSS action configuration.
11691  *
11692  * @param[in] dev
11693  *   Pointer to the Ethernet device structure.
11694  * @param[in] idx
11695  *   The shared RSS action object ID to be updated.
11696  * @param[in] action_conf
11697  *   RSS action specification used to modify *shared_rss*.
11698  * @param[out] error
11699  *   Perform verbose error reporting if not NULL. Initialized in case of
11700  *   error only.
11701  *
11702  * @return
11703  *   0 on success, otherwise negative errno value.
11704  * @note: currently only support update of RSS queues.
11705  */
11706 static int
11707 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11708                             const struct rte_flow_action_rss *action_conf,
11709                             struct rte_flow_error *error)
11710 {
11711         struct mlx5_priv *priv = dev->data->dev_private;
11712         struct mlx5_shared_action_rss *shared_rss =
11713             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11714         int ret = 0;
11715         void *queue = NULL;
11716         uint16_t *queue_old = NULL;
11717         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11718
11719         if (!shared_rss)
11720                 return rte_flow_error_set(error, EINVAL,
11721                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11722                                           "invalid shared action to update");
11723         queue = mlx5_malloc(MLX5_MEM_ZERO,
11724                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11725                             0, SOCKET_ID_ANY);
11726         if (!queue)
11727                 return rte_flow_error_set(error, ENOMEM,
11728                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11729                                           NULL,
11730                                           "cannot allocate resource memory");
11731         memcpy(queue, action_conf->queue, queue_size);
11732         MLX5_ASSERT(shared_rss->ind_tbl);
11733         rte_spinlock_lock(&shared_rss->action_rss_sl);
11734         queue_old = shared_rss->ind_tbl->queues;
11735         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
11736                                         queue, action_conf->queue_num, true);
11737         if (ret) {
11738                 mlx5_free(queue);
11739                 ret = rte_flow_error_set(error, rte_errno,
11740                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11741                                           "cannot update indirection table");
11742         } else {
11743                 mlx5_free(queue_old);
11744                 shared_rss->origin.queue = queue;
11745                 shared_rss->origin.queue_num = action_conf->queue_num;
11746         }
11747         rte_spinlock_unlock(&shared_rss->action_rss_sl);
11748         return ret;
11749 }
11750
11751 /**
11752  * Updates in place shared action configuration, lock free,
11753  * (mutex should be acquired by caller).
11754  *
11755  * @param[in] dev
11756  *   Pointer to the Ethernet device structure.
11757  * @param[in] action
11758  *   The shared action object to be updated.
11759  * @param[in] action_conf
11760  *   Action specification used to modify *action*.
11761  *   *action_conf* should be of type correlating with type of the *action*,
11762  *   otherwise considered as invalid.
11763  * @param[out] error
11764  *   Perform verbose error reporting if not NULL. Initialized in case of
11765  *   error only.
11766  *
11767  * @return
11768  *   0 on success, otherwise negative errno value.
11769  */
11770 static int
11771 flow_dv_action_update(struct rte_eth_dev *dev,
11772                         struct rte_flow_shared_action *action,
11773                         const void *action_conf,
11774                         struct rte_flow_error *err)
11775 {
11776         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11777         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11778         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11779
11780         switch (type) {
11781         case MLX5_SHARED_ACTION_TYPE_RSS:
11782                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
11783         default:
11784                 return rte_flow_error_set(err, ENOTSUP,
11785                                           RTE_FLOW_ERROR_TYPE_ACTION,
11786                                           NULL,
11787                                           "action type update not supported");
11788         }
11789 }
11790
11791 static int
11792 flow_dv_action_query(struct rte_eth_dev *dev,
11793                      const struct rte_flow_shared_action *action, void *data,
11794                      struct rte_flow_error *error)
11795 {
11796         struct mlx5_age_param *age_param;
11797         struct rte_flow_query_age *resp;
11798         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11799         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11800         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11801
11802         switch (type) {
11803         case MLX5_SHARED_ACTION_TYPE_AGE:
11804                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
11805                 resp = data;
11806                 resp->aged = __atomic_load_n(&age_param->state,
11807                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
11808                                                                           1 : 0;
11809                 resp->sec_since_last_hit_valid = !resp->aged;
11810                 if (resp->sec_since_last_hit_valid)
11811                         resp->sec_since_last_hit = __atomic_load_n
11812                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11813                 return 0;
11814         default:
11815                 return rte_flow_error_set(error, ENOTSUP,
11816                                           RTE_FLOW_ERROR_TYPE_ACTION,
11817                                           NULL,
11818                                           "action type query not supported");
11819         }
11820 }
11821
11822 /**
11823  * Query a dv flow  rule for its statistics via devx.
11824  *
11825  * @param[in] dev
11826  *   Pointer to Ethernet device.
11827  * @param[in] flow
11828  *   Pointer to the sub flow.
11829  * @param[out] data
11830  *   data retrieved by the query.
11831  * @param[out] error
11832  *   Perform verbose error reporting if not NULL.
11833  *
11834  * @return
11835  *   0 on success, a negative errno value otherwise and rte_errno is set.
11836  */
11837 static int
11838 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11839                     void *data, struct rte_flow_error *error)
11840 {
11841         struct mlx5_priv *priv = dev->data->dev_private;
11842         struct rte_flow_query_count *qc = data;
11843
11844         if (!priv->config.devx)
11845                 return rte_flow_error_set(error, ENOTSUP,
11846                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11847                                           NULL,
11848                                           "counters are not supported");
11849         if (flow->counter) {
11850                 uint64_t pkts, bytes;
11851                 struct mlx5_flow_counter *cnt;
11852
11853                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11854                                                  NULL);
11855                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11856                                                &bytes);
11857
11858                 if (err)
11859                         return rte_flow_error_set(error, -err,
11860                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11861                                         NULL, "cannot read counters");
11862                 qc->hits_set = 1;
11863                 qc->bytes_set = 1;
11864                 qc->hits = pkts - cnt->hits;
11865                 qc->bytes = bytes - cnt->bytes;
11866                 if (qc->reset) {
11867                         cnt->hits = pkts;
11868                         cnt->bytes = bytes;
11869                 }
11870                 return 0;
11871         }
11872         return rte_flow_error_set(error, EINVAL,
11873                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11874                                   NULL,
11875                                   "counters are not available");
11876 }
11877
11878 /**
11879  * Query a flow rule AGE action for aging information.
11880  *
11881  * @param[in] dev
11882  *   Pointer to Ethernet device.
11883  * @param[in] flow
11884  *   Pointer to the sub flow.
11885  * @param[out] data
11886  *   data retrieved by the query.
11887  * @param[out] error
11888  *   Perform verbose error reporting if not NULL.
11889  *
11890  * @return
11891  *   0 on success, a negative errno value otherwise and rte_errno is set.
11892  */
11893 static int
11894 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11895                   void *data, struct rte_flow_error *error)
11896 {
11897         struct rte_flow_query_age *resp = data;
11898         struct mlx5_age_param *age_param;
11899
11900         if (flow->age) {
11901                 struct mlx5_aso_age_action *act =
11902                                      flow_aso_age_get_by_idx(dev, flow->age);
11903
11904                 age_param = &act->age_params;
11905         } else if (flow->counter) {
11906                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
11907
11908                 if (!age_param || !age_param->timeout)
11909                         return rte_flow_error_set
11910                                         (error, EINVAL,
11911                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11912                                          NULL, "cannot read age data");
11913         } else {
11914                 return rte_flow_error_set(error, EINVAL,
11915                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11916                                           NULL, "age data not available");
11917         }
11918         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
11919                                      AGE_TMOUT ? 1 : 0;
11920         resp->sec_since_last_hit_valid = !resp->aged;
11921         if (resp->sec_since_last_hit_valid)
11922                 resp->sec_since_last_hit = __atomic_load_n
11923                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11924         return 0;
11925 }
11926
11927 /**
11928  * Query a flow.
11929  *
11930  * @see rte_flow_query()
11931  * @see rte_flow_ops
11932  */
11933 static int
11934 flow_dv_query(struct rte_eth_dev *dev,
11935               struct rte_flow *flow __rte_unused,
11936               const struct rte_flow_action *actions __rte_unused,
11937               void *data __rte_unused,
11938               struct rte_flow_error *error __rte_unused)
11939 {
11940         int ret = -EINVAL;
11941
11942         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11943                 switch (actions->type) {
11944                 case RTE_FLOW_ACTION_TYPE_VOID:
11945                         break;
11946                 case RTE_FLOW_ACTION_TYPE_COUNT:
11947                         ret = flow_dv_query_count(dev, flow, data, error);
11948                         break;
11949                 case RTE_FLOW_ACTION_TYPE_AGE:
11950                         ret = flow_dv_query_age(dev, flow, data, error);
11951                         break;
11952                 default:
11953                         return rte_flow_error_set(error, ENOTSUP,
11954                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11955                                                   actions,
11956                                                   "action not supported");
11957                 }
11958         }
11959         return ret;
11960 }
11961
11962 /**
11963  * Destroy the meter table set.
11964  * Lock free, (mutex should be acquired by caller).
11965  *
11966  * @param[in] dev
11967  *   Pointer to Ethernet device.
11968  * @param[in] tbl
11969  *   Pointer to the meter table set.
11970  *
11971  * @return
11972  *   Always 0.
11973  */
11974 static int
11975 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11976                         struct mlx5_meter_domains_infos *tbl)
11977 {
11978         struct mlx5_priv *priv = dev->data->dev_private;
11979         struct mlx5_meter_domains_infos *mtd =
11980                                 (struct mlx5_meter_domains_infos *)tbl;
11981
11982         if (!mtd || !priv->config.dv_flow_en)
11983                 return 0;
11984         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11985                 claim_zero(mlx5_flow_os_destroy_flow
11986                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11987         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11988                 claim_zero(mlx5_flow_os_destroy_flow
11989                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11990         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11991                 claim_zero(mlx5_flow_os_destroy_flow
11992                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11993         if (mtd->egress.color_matcher)
11994                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11995                            (mtd->egress.color_matcher));
11996         if (mtd->egress.any_matcher)
11997                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11998                            (mtd->egress.any_matcher));
11999         if (mtd->egress.tbl)
12000                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12001         if (mtd->egress.sfx_tbl)
12002                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12003         if (mtd->ingress.color_matcher)
12004                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12005                            (mtd->ingress.color_matcher));
12006         if (mtd->ingress.any_matcher)
12007                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12008                            (mtd->ingress.any_matcher));
12009         if (mtd->ingress.tbl)
12010                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12011         if (mtd->ingress.sfx_tbl)
12012                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12013                                              mtd->ingress.sfx_tbl);
12014         if (mtd->transfer.color_matcher)
12015                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12016                            (mtd->transfer.color_matcher));
12017         if (mtd->transfer.any_matcher)
12018                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12019                            (mtd->transfer.any_matcher));
12020         if (mtd->transfer.tbl)
12021                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12022         if (mtd->transfer.sfx_tbl)
12023                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12024                                              mtd->transfer.sfx_tbl);
12025         if (mtd->drop_actn)
12026                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12027         mlx5_free(mtd);
12028         return 0;
12029 }
12030
12031 /* Number of meter flow actions, count and jump or count and drop. */
12032 #define METER_ACTIONS 2
12033
12034 /**
12035  * Create specify domain meter table and suffix table.
12036  *
12037  * @param[in] dev
12038  *   Pointer to Ethernet device.
12039  * @param[in,out] mtb
12040  *   Pointer to DV meter table set.
12041  * @param[in] egress
12042  *   Table attribute.
12043  * @param[in] transfer
12044  *   Table attribute.
12045  * @param[in] color_reg_c_idx
12046  *   Reg C index for color match.
12047  *
12048  * @return
12049  *   0 on success, -1 otherwise and rte_errno is set.
12050  */
12051 static int
12052 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12053                            struct mlx5_meter_domains_infos *mtb,
12054                            uint8_t egress, uint8_t transfer,
12055                            uint32_t color_reg_c_idx)
12056 {
12057         struct mlx5_priv *priv = dev->data->dev_private;
12058         struct mlx5_dev_ctx_shared *sh = priv->sh;
12059         struct mlx5_flow_dv_match_params mask = {
12060                 .size = sizeof(mask.buf),
12061         };
12062         struct mlx5_flow_dv_match_params value = {
12063                 .size = sizeof(value.buf),
12064         };
12065         struct mlx5dv_flow_matcher_attr dv_attr = {
12066                 .type = IBV_FLOW_ATTR_NORMAL,
12067                 .priority = 0,
12068                 .match_criteria_enable = 0,
12069                 .match_mask = (void *)&mask,
12070         };
12071         void *actions[METER_ACTIONS];
12072         struct mlx5_meter_domain_info *dtb;
12073         struct rte_flow_error error;
12074         int i = 0;
12075         int ret;
12076
12077         if (transfer)
12078                 dtb = &mtb->transfer;
12079         else if (egress)
12080                 dtb = &mtb->egress;
12081         else
12082                 dtb = &mtb->ingress;
12083         /* Create the meter table with METER level. */
12084         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12085                                             egress, transfer, false, NULL, 0,
12086                                             0, &error);
12087         if (!dtb->tbl) {
12088                 DRV_LOG(ERR, "Failed to create meter policer table.");
12089                 return -1;
12090         }
12091         /* Create the meter suffix table with SUFFIX level. */
12092         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12093                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12094                                             egress, transfer, false, NULL, 0,
12095                                             0, &error);
12096         if (!dtb->sfx_tbl) {
12097                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12098                 return -1;
12099         }
12100         /* Create matchers, Any and Color. */
12101         dv_attr.priority = 3;
12102         dv_attr.match_criteria_enable = 0;
12103         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12104                                                &dtb->any_matcher);
12105         if (ret) {
12106                 DRV_LOG(ERR, "Failed to create meter"
12107                              " policer default matcher.");
12108                 goto error_exit;
12109         }
12110         dv_attr.priority = 0;
12111         dv_attr.match_criteria_enable =
12112                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12113         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12114                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12115         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12116                                                &dtb->color_matcher);
12117         if (ret) {
12118                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12119                 goto error_exit;
12120         }
12121         if (mtb->count_actns[RTE_MTR_DROPPED])
12122                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12123         actions[i++] = mtb->drop_actn;
12124         /* Default rule: lowest priority, match any, actions: drop. */
12125         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12126                                        actions,
12127                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12128         if (ret) {
12129                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12130                 goto error_exit;
12131         }
12132         return 0;
12133 error_exit:
12134         return -1;
12135 }
12136
12137 /**
12138  * Create the needed meter and suffix tables.
12139  * Lock free, (mutex should be acquired by caller).
12140  *
12141  * @param[in] dev
12142  *   Pointer to Ethernet device.
12143  * @param[in] fm
12144  *   Pointer to the flow meter.
12145  *
12146  * @return
12147  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12148  */
12149 static struct mlx5_meter_domains_infos *
12150 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12151                        const struct mlx5_flow_meter *fm)
12152 {
12153         struct mlx5_priv *priv = dev->data->dev_private;
12154         struct mlx5_meter_domains_infos *mtb;
12155         int ret;
12156         int i;
12157
12158         if (!priv->mtr_en) {
12159                 rte_errno = ENOTSUP;
12160                 return NULL;
12161         }
12162         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12163         if (!mtb) {
12164                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12165                 return NULL;
12166         }
12167         /* Create meter count actions */
12168         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12169                 struct mlx5_flow_counter *cnt;
12170                 if (!fm->policer_stats.cnt[i])
12171                         continue;
12172                 cnt = flow_dv_counter_get_by_idx(dev,
12173                       fm->policer_stats.cnt[i], NULL);
12174                 mtb->count_actns[i] = cnt->action;
12175         }
12176         /* Create drop action. */
12177         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12178         if (ret) {
12179                 DRV_LOG(ERR, "Failed to create drop action.");
12180                 goto error_exit;
12181         }
12182         /* Egress meter table. */
12183         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12184         if (ret) {
12185                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12186                 goto error_exit;
12187         }
12188         /* Ingress meter table. */
12189         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12190         if (ret) {
12191                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12192                 goto error_exit;
12193         }
12194         /* FDB meter table. */
12195         if (priv->config.dv_esw_en) {
12196                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12197                                                  priv->mtr_color_reg);
12198                 if (ret) {
12199                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12200                         goto error_exit;
12201                 }
12202         }
12203         return mtb;
12204 error_exit:
12205         flow_dv_destroy_mtr_tbl(dev, mtb);
12206         return NULL;
12207 }
12208
12209 /**
12210  * Destroy domain policer rule.
12211  *
12212  * @param[in] dt
12213  *   Pointer to domain table.
12214  */
12215 static void
12216 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12217 {
12218         int i;
12219
12220         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12221                 if (dt->policer_rules[i]) {
12222                         claim_zero(mlx5_flow_os_destroy_flow
12223                                    (dt->policer_rules[i]));
12224                         dt->policer_rules[i] = NULL;
12225                 }
12226         }
12227         if (dt->jump_actn) {
12228                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12229                 dt->jump_actn = NULL;
12230         }
12231 }
12232
12233 /**
12234  * Destroy policer rules.
12235  *
12236  * @param[in] dev
12237  *   Pointer to Ethernet device.
12238  * @param[in] fm
12239  *   Pointer to flow meter structure.
12240  * @param[in] attr
12241  *   Pointer to flow attributes.
12242  *
12243  * @return
12244  *   Always 0.
12245  */
12246 static int
12247 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12248                               const struct mlx5_flow_meter *fm,
12249                               const struct rte_flow_attr *attr)
12250 {
12251         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12252
12253         if (!mtb)
12254                 return 0;
12255         if (attr->egress)
12256                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12257         if (attr->ingress)
12258                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12259         if (attr->transfer)
12260                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12261         return 0;
12262 }
12263
12264 /**
12265  * Create specify domain meter policer rule.
12266  *
12267  * @param[in] fm
12268  *   Pointer to flow meter structure.
12269  * @param[in] mtb
12270  *   Pointer to DV meter table set.
12271  * @param[in] mtr_reg_c
12272  *   Color match REG_C.
12273  *
12274  * @return
12275  *   0 on success, -1 otherwise.
12276  */
12277 static int
12278 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12279                                     struct mlx5_meter_domain_info *dtb,
12280                                     uint8_t mtr_reg_c)
12281 {
12282         struct mlx5_flow_dv_match_params matcher = {
12283                 .size = sizeof(matcher.buf),
12284         };
12285         struct mlx5_flow_dv_match_params value = {
12286                 .size = sizeof(value.buf),
12287         };
12288         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12289         void *actions[METER_ACTIONS];
12290         int i;
12291         int ret = 0;
12292
12293         /* Create jump action. */
12294         if (!dtb->jump_actn)
12295                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12296                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12297         if (ret) {
12298                 DRV_LOG(ERR, "Failed to create policer jump action.");
12299                 goto error;
12300         }
12301         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12302                 int j = 0;
12303
12304                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12305                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12306                 if (mtb->count_actns[i])
12307                         actions[j++] = mtb->count_actns[i];
12308                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12309                         actions[j++] = mtb->drop_actn;
12310                 else
12311                         actions[j++] = dtb->jump_actn;
12312                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12313                                                (void *)&value, j, actions,
12314                                                &dtb->policer_rules[i]);
12315                 if (ret) {
12316                         DRV_LOG(ERR, "Failed to create policer rule.");
12317                         goto error;
12318                 }
12319         }
12320         return 0;
12321 error:
12322         rte_errno = errno;
12323         return -1;
12324 }
12325
12326 /**
12327  * Create policer rules.
12328  *
12329  * @param[in] dev
12330  *   Pointer to Ethernet device.
12331  * @param[in] fm
12332  *   Pointer to flow meter structure.
12333  * @param[in] attr
12334  *   Pointer to flow attributes.
12335  *
12336  * @return
12337  *   0 on success, -1 otherwise.
12338  */
12339 static int
12340 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12341                              struct mlx5_flow_meter *fm,
12342                              const struct rte_flow_attr *attr)
12343 {
12344         struct mlx5_priv *priv = dev->data->dev_private;
12345         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12346         int ret;
12347
12348         if (attr->egress) {
12349                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12350                                                 priv->mtr_color_reg);
12351                 if (ret) {
12352                         DRV_LOG(ERR, "Failed to create egress policer.");
12353                         goto error;
12354                 }
12355         }
12356         if (attr->ingress) {
12357                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12358                                                 priv->mtr_color_reg);
12359                 if (ret) {
12360                         DRV_LOG(ERR, "Failed to create ingress policer.");
12361                         goto error;
12362                 }
12363         }
12364         if (attr->transfer) {
12365                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12366                                                 priv->mtr_color_reg);
12367                 if (ret) {
12368                         DRV_LOG(ERR, "Failed to create transfer policer.");
12369                         goto error;
12370                 }
12371         }
12372         return 0;
12373 error:
12374         flow_dv_destroy_policer_rules(dev, fm, attr);
12375         return -1;
12376 }
12377
12378 /**
12379  * Validate the batch counter support in root table.
12380  *
12381  * Create a simple flow with invalid counter and drop action on root table to
12382  * validate if batch counter with offset on root table is supported or not.
12383  *
12384  * @param[in] dev
12385  *   Pointer to rte_eth_dev structure.
12386  *
12387  * @return
12388  *   0 on success, a negative errno value otherwise and rte_errno is set.
12389  */
12390 int
12391 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12392 {
12393         struct mlx5_priv *priv = dev->data->dev_private;
12394         struct mlx5_dev_ctx_shared *sh = priv->sh;
12395         struct mlx5_flow_dv_match_params mask = {
12396                 .size = sizeof(mask.buf),
12397         };
12398         struct mlx5_flow_dv_match_params value = {
12399                 .size = sizeof(value.buf),
12400         };
12401         struct mlx5dv_flow_matcher_attr dv_attr = {
12402                 .type = IBV_FLOW_ATTR_NORMAL,
12403                 .priority = 0,
12404                 .match_criteria_enable = 0,
12405                 .match_mask = (void *)&mask,
12406         };
12407         void *actions[2] = { 0 };
12408         struct mlx5_flow_tbl_resource *tbl = NULL;
12409         struct mlx5_devx_obj *dcs = NULL;
12410         void *matcher = NULL;
12411         void *flow = NULL;
12412         int ret = -1;
12413
12414         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12415         if (!tbl)
12416                 goto err;
12417         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12418         if (!dcs)
12419                 goto err;
12420         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12421                                                     &actions[0]);
12422         if (ret)
12423                 goto err;
12424         actions[1] = priv->drop_queue.hrxq->action;
12425         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12426         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12427                                                &matcher);
12428         if (ret)
12429                 goto err;
12430         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12431                                        actions, &flow);
12432 err:
12433         /*
12434          * If batch counter with offset is not supported, the driver will not
12435          * validate the invalid offset value, flow create should success.
12436          * In this case, it means batch counter is not supported in root table.
12437          *
12438          * Otherwise, if flow create is failed, counter offset is supported.
12439          */
12440         if (flow) {
12441                 DRV_LOG(INFO, "Batch counter is not supported in root "
12442                               "table. Switch to fallback mode.");
12443                 rte_errno = ENOTSUP;
12444                 ret = -rte_errno;
12445                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12446         } else {
12447                 /* Check matcher to make sure validate fail at flow create. */
12448                 if (!matcher || (matcher && errno != EINVAL))
12449                         DRV_LOG(ERR, "Unexpected error in counter offset "
12450                                      "support detection");
12451                 ret = 0;
12452         }
12453         if (actions[0])
12454                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12455         if (matcher)
12456                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12457         if (tbl)
12458                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12459         if (dcs)
12460                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12461         return ret;
12462 }
12463
12464 /**
12465  * Query a devx counter.
12466  *
12467  * @param[in] dev
12468  *   Pointer to the Ethernet device structure.
12469  * @param[in] cnt
12470  *   Index to the flow counter.
12471  * @param[in] clear
12472  *   Set to clear the counter statistics.
12473  * @param[out] pkts
12474  *   The statistics value of packets.
12475  * @param[out] bytes
12476  *   The statistics value of bytes.
12477  *
12478  * @return
12479  *   0 on success, otherwise return -1.
12480  */
12481 static int
12482 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12483                       uint64_t *pkts, uint64_t *bytes)
12484 {
12485         struct mlx5_priv *priv = dev->data->dev_private;
12486         struct mlx5_flow_counter *cnt;
12487         uint64_t inn_pkts, inn_bytes;
12488         int ret;
12489
12490         if (!priv->config.devx)
12491                 return -1;
12492
12493         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12494         if (ret)
12495                 return -1;
12496         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12497         *pkts = inn_pkts - cnt->hits;
12498         *bytes = inn_bytes - cnt->bytes;
12499         if (clear) {
12500                 cnt->hits = inn_pkts;
12501                 cnt->bytes = inn_bytes;
12502         }
12503         return 0;
12504 }
12505
12506 /**
12507  * Get aged-out flows.
12508  *
12509  * @param[in] dev
12510  *   Pointer to the Ethernet device structure.
12511  * @param[in] context
12512  *   The address of an array of pointers to the aged-out flows contexts.
12513  * @param[in] nb_contexts
12514  *   The length of context array pointers.
12515  * @param[out] error
12516  *   Perform verbose error reporting if not NULL. Initialized in case of
12517  *   error only.
12518  *
12519  * @return
12520  *   how many contexts get in success, otherwise negative errno value.
12521  *   if nb_contexts is 0, return the amount of all aged contexts.
12522  *   if nb_contexts is not 0 , return the amount of aged flows reported
12523  *   in the context array.
12524  * @note: only stub for now
12525  */
12526 static int
12527 flow_get_aged_flows(struct rte_eth_dev *dev,
12528                     void **context,
12529                     uint32_t nb_contexts,
12530                     struct rte_flow_error *error)
12531 {
12532         struct mlx5_priv *priv = dev->data->dev_private;
12533         struct mlx5_age_info *age_info;
12534         struct mlx5_age_param *age_param;
12535         struct mlx5_flow_counter *counter;
12536         struct mlx5_aso_age_action *act;
12537         int nb_flows = 0;
12538
12539         if (nb_contexts && !context)
12540                 return rte_flow_error_set(error, EINVAL,
12541                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12542                                           NULL, "empty context");
12543         age_info = GET_PORT_AGE_INFO(priv);
12544         rte_spinlock_lock(&age_info->aged_sl);
12545         LIST_FOREACH(act, &age_info->aged_aso, next) {
12546                 nb_flows++;
12547                 if (nb_contexts) {
12548                         context[nb_flows - 1] =
12549                                                 act->age_params.context;
12550                         if (!(--nb_contexts))
12551                                 break;
12552                 }
12553         }
12554         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12555                 nb_flows++;
12556                 if (nb_contexts) {
12557                         age_param = MLX5_CNT_TO_AGE(counter);
12558                         context[nb_flows - 1] = age_param->context;
12559                         if (!(--nb_contexts))
12560                                 break;
12561                 }
12562         }
12563         rte_spinlock_unlock(&age_info->aged_sl);
12564         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12565         return nb_flows;
12566 }
12567
12568 /*
12569  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12570  */
12571 static uint32_t
12572 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12573 {
12574         return flow_dv_counter_alloc(dev, 0);
12575 }
12576
12577 /**
12578  * Validate shared action.
12579  * Dispatcher for action type specific validation.
12580  *
12581  * @param[in] dev
12582  *   Pointer to the Ethernet device structure.
12583  * @param[in] conf
12584  *   Shared action configuration.
12585  * @param[in] action
12586  *   The shared action object to validate.
12587  * @param[out] error
12588  *   Perform verbose error reporting if not NULL. Initialized in case of
12589  *   error only.
12590  *
12591  * @return
12592  *   0 on success, otherwise negative errno value.
12593  */
12594 static int
12595 flow_dv_action_validate(struct rte_eth_dev *dev,
12596                         const struct rte_flow_shared_action_conf *conf,
12597                         const struct rte_flow_action *action,
12598                         struct rte_flow_error *err)
12599 {
12600         struct mlx5_priv *priv = dev->data->dev_private;
12601
12602         RTE_SET_USED(conf);
12603         switch (action->type) {
12604         case RTE_FLOW_ACTION_TYPE_RSS:
12605                 return mlx5_validate_action_rss(dev, action, err);
12606         case RTE_FLOW_ACTION_TYPE_AGE:
12607                 if (!priv->sh->aso_age_mng)
12608                         return rte_flow_error_set(err, ENOTSUP,
12609                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12610                                                 NULL,
12611                                              "shared age action not supported");
12612                 return flow_dv_validate_action_age(0, action, dev, err);
12613         default:
12614                 return rte_flow_error_set(err, ENOTSUP,
12615                                           RTE_FLOW_ERROR_TYPE_ACTION,
12616                                           NULL,
12617                                           "action type not supported");
12618         }
12619 }
12620
12621 static int
12622 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12623 {
12624         struct mlx5_priv *priv = dev->data->dev_private;
12625         int ret = 0;
12626
12627         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12628                 ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain,
12629                                                 flags);
12630                 if (ret != 0)
12631                         return ret;
12632         }
12633         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12634                 ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags);
12635                 if (ret != 0)
12636                         return ret;
12637         }
12638         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12639                 ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags);
12640                 if (ret != 0)
12641                         return ret;
12642         }
12643         return 0;
12644 }
12645
12646 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12647         .validate = flow_dv_validate,
12648         .prepare = flow_dv_prepare,
12649         .translate = flow_dv_translate,
12650         .apply = flow_dv_apply,
12651         .remove = flow_dv_remove,
12652         .destroy = flow_dv_destroy,
12653         .query = flow_dv_query,
12654         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12655         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12656         .create_policer_rules = flow_dv_create_policer_rules,
12657         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12658         .counter_alloc = flow_dv_counter_allocate,
12659         .counter_free = flow_dv_counter_free,
12660         .counter_query = flow_dv_counter_query,
12661         .get_aged_flows = flow_get_aged_flows,
12662         .action_validate = flow_dv_action_validate,
12663         .action_create = flow_dv_action_create,
12664         .action_destroy = flow_dv_action_destroy,
12665         .action_update = flow_dv_action_update,
12666         .action_query = flow_dv_action_query,
12667         .sync_domain = flow_dv_sync_domain,
12668 };
12669
12670 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12671