net/liquidio: fix jumbo frame flag condition for MTU set
[dpdk.git] / drivers / net / mlx5 / mlx5_flow_dv.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2018 Mellanox Technologies, Ltd
3  */
4
5 #include <sys/queue.h>
6 #include <stdalign.h>
7 #include <stdint.h>
8 #include <string.h>
9 #include <unistd.h>
10
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
14 #include <rte_flow.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_ip.h>
19 #include <rte_gre.h>
20 #include <rte_vxlan.h>
21 #include <rte_gtp.h>
22 #include <rte_eal_paging.h>
23 #include <rte_mpls.h>
24
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_prm.h>
28 #include <mlx5_malloc.h>
29
30 #include "mlx5_defs.h"
31 #include "mlx5.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
37
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
39
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
42 #endif
43
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
47 #endif
48 #endif
49
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
52 #endif
53
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
60
61 union flow_dv_attr {
62         struct {
63                 uint32_t valid:1;
64                 uint32_t ipv4:1;
65                 uint32_t ipv6:1;
66                 uint32_t tcp:1;
67                 uint32_t udp:1;
68                 uint32_t reserved:27;
69         };
70         uint32_t attr;
71 };
72
73 static int
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75                              struct mlx5_flow_tbl_resource *tbl);
76
77 static int
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79                                       uint32_t encap_decap_idx);
80
81 static int
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
83                                         uint32_t port_id);
84 static void
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
86
87 /**
88  * Initialize flow attributes structure according to flow items' types.
89  *
90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
91  * mode. For tunnel mode, the items to be modified are the outermost ones.
92  *
93  * @param[in] item
94  *   Pointer to item specification.
95  * @param[out] attr
96  *   Pointer to flow attributes structure.
97  * @param[in] dev_flow
98  *   Pointer to the sub flow.
99  * @param[in] tunnel_decap
100  *   Whether action is after tunnel decapsulation.
101  */
102 static void
103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
105 {
106         uint64_t layers = dev_flow->handle->layers;
107
108         /*
109          * If layers is already initialized, it means this dev_flow is the
110          * suffix flow, the layers flags is set by the prefix flow. Need to
111          * use the layer flags from prefix flow as the suffix flow may not
112          * have the user defined items as the flow is split.
113          */
114         if (layers) {
115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
116                         attr->ipv4 = 1;
117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
118                         attr->ipv6 = 1;
119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
120                         attr->tcp = 1;
121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
122                         attr->udp = 1;
123                 attr->valid = 1;
124                 return;
125         }
126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
127                 uint8_t next_protocol = 0xff;
128                 switch (item->type) {
129                 case RTE_FLOW_ITEM_TYPE_GRE:
130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
134                 case RTE_FLOW_ITEM_TYPE_MPLS:
135                         if (tunnel_decap)
136                                 attr->attr = 0;
137                         break;
138                 case RTE_FLOW_ITEM_TYPE_IPV4:
139                         if (!attr->ipv6)
140                                 attr->ipv4 = 1;
141                         if (item->mask != NULL &&
142                             ((const struct rte_flow_item_ipv4 *)
143                             item->mask)->hdr.next_proto_id)
144                                 next_protocol =
145                                     ((const struct rte_flow_item_ipv4 *)
146                                       (item->spec))->hdr.next_proto_id &
147                                     ((const struct rte_flow_item_ipv4 *)
148                                       (item->mask))->hdr.next_proto_id;
149                         if ((next_protocol == IPPROTO_IPIP ||
150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
151                                 attr->attr = 0;
152                         break;
153                 case RTE_FLOW_ITEM_TYPE_IPV6:
154                         if (!attr->ipv4)
155                                 attr->ipv6 = 1;
156                         if (item->mask != NULL &&
157                             ((const struct rte_flow_item_ipv6 *)
158                             item->mask)->hdr.proto)
159                                 next_protocol =
160                                     ((const struct rte_flow_item_ipv6 *)
161                                       (item->spec))->hdr.proto &
162                                     ((const struct rte_flow_item_ipv6 *)
163                                       (item->mask))->hdr.proto;
164                         if ((next_protocol == IPPROTO_IPIP ||
165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
166                                 attr->attr = 0;
167                         break;
168                 case RTE_FLOW_ITEM_TYPE_UDP:
169                         if (!attr->tcp)
170                                 attr->udp = 1;
171                         break;
172                 case RTE_FLOW_ITEM_TYPE_TCP:
173                         if (!attr->udp)
174                                 attr->tcp = 1;
175                         break;
176                 default:
177                         break;
178                 }
179         }
180         attr->valid = 1;
181 }
182
183 /**
184  * Convert rte_mtr_color to mlx5 color.
185  *
186  * @param[in] rcol
187  *   rte_mtr_color.
188  *
189  * @return
190  *   mlx5 color.
191  */
192 static int
193 rte_col_2_mlx5_col(enum rte_color rcol)
194 {
195         switch (rcol) {
196         case RTE_COLOR_GREEN:
197                 return MLX5_FLOW_COLOR_GREEN;
198         case RTE_COLOR_YELLOW:
199                 return MLX5_FLOW_COLOR_YELLOW;
200         case RTE_COLOR_RED:
201                 return MLX5_FLOW_COLOR_RED;
202         default:
203                 break;
204         }
205         return MLX5_FLOW_COLOR_UNDEFINED;
206 }
207
208 struct field_modify_info {
209         uint32_t size; /* Size of field in protocol header, in bytes. */
210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
211         enum mlx5_modification_field id;
212 };
213
214 struct field_modify_info modify_eth[] = {
215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
219         {0, 0, 0},
220 };
221
222 struct field_modify_info modify_vlan_out_first_vid[] = {
223         /* Size in bits !!! */
224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
225         {0, 0, 0},
226 };
227
228 struct field_modify_info modify_ipv4[] = {
229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
231         {4, 12, MLX5_MODI_OUT_SIPV4},
232         {4, 16, MLX5_MODI_OUT_DIPV4},
233         {0, 0, 0},
234 };
235
236 struct field_modify_info modify_ipv6[] = {
237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
247         {0, 0, 0},
248 };
249
250 struct field_modify_info modify_udp[] = {
251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
253         {0, 0, 0},
254 };
255
256 struct field_modify_info modify_tcp[] = {
257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
261         {0, 0, 0},
262 };
263
264 static void
265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
266                           uint8_t next_protocol, uint64_t *item_flags,
267                           int *tunnel)
268 {
269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
271         if (next_protocol == IPPROTO_IPIP) {
272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
273                 *tunnel = 1;
274         }
275         if (next_protocol == IPPROTO_IPV6) {
276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
277                 *tunnel = 1;
278         }
279 }
280
281 /* Update VLAN's VID/PCP based on input rte_flow_action.
282  *
283  * @param[in] action
284  *   Pointer to struct rte_flow_action.
285  * @param[out] vlan
286  *   Pointer to struct rte_vlan_hdr.
287  */
288 static void
289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
290                          struct rte_vlan_hdr *vlan)
291 {
292         uint16_t vlan_tci;
293         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
294                 vlan_tci =
295                     ((const struct rte_flow_action_of_set_vlan_pcp *)
296                                                action->conf)->vlan_pcp;
297                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
298                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
299                 vlan->vlan_tci |= vlan_tci;
300         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
301                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
302                 vlan->vlan_tci |= rte_be_to_cpu_16
303                     (((const struct rte_flow_action_of_set_vlan_vid *)
304                                              action->conf)->vlan_vid);
305         }
306 }
307
308 /**
309  * Fetch 1, 2, 3 or 4 byte field from the byte array
310  * and return as unsigned integer in host-endian format.
311  *
312  * @param[in] data
313  *   Pointer to data array.
314  * @param[in] size
315  *   Size of field to extract.
316  *
317  * @return
318  *   converted field in host endian format.
319  */
320 static inline uint32_t
321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
322 {
323         uint32_t ret;
324
325         switch (size) {
326         case 1:
327                 ret = *data;
328                 break;
329         case 2:
330                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
331                 break;
332         case 3:
333                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
334                 ret = (ret << 8) | *(data + sizeof(uint16_t));
335                 break;
336         case 4:
337                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
338                 break;
339         default:
340                 MLX5_ASSERT(false);
341                 ret = 0;
342                 break;
343         }
344         return ret;
345 }
346
347 /**
348  * Convert modify-header action to DV specification.
349  *
350  * Data length of each action is determined by provided field description
351  * and the item mask. Data bit offset and width of each action is determined
352  * by provided item mask.
353  *
354  * @param[in] item
355  *   Pointer to item specification.
356  * @param[in] field
357  *   Pointer to field modification information.
358  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
359  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
360  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
361  * @param[in] dcopy
362  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
363  *   Negative offset value sets the same offset as source offset.
364  *   size field is ignored, value is taken from source field.
365  * @param[in,out] resource
366  *   Pointer to the modify-header resource.
367  * @param[in] type
368  *   Type of modification.
369  * @param[out] error
370  *   Pointer to the error structure.
371  *
372  * @return
373  *   0 on success, a negative errno value otherwise and rte_errno is set.
374  */
375 static int
376 flow_dv_convert_modify_action(struct rte_flow_item *item,
377                               struct field_modify_info *field,
378                               struct field_modify_info *dcopy,
379                               struct mlx5_flow_dv_modify_hdr_resource *resource,
380                               uint32_t type, struct rte_flow_error *error)
381 {
382         uint32_t i = resource->actions_num;
383         struct mlx5_modification_cmd *actions = resource->actions;
384
385         /*
386          * The item and mask are provided in big-endian format.
387          * The fields should be presented as in big-endian format either.
388          * Mask must be always present, it defines the actual field width.
389          */
390         MLX5_ASSERT(item->mask);
391         MLX5_ASSERT(field->size);
392         do {
393                 unsigned int size_b;
394                 unsigned int off_b;
395                 uint32_t mask;
396                 uint32_t data;
397
398                 if (i >= MLX5_MAX_MODIFY_NUM)
399                         return rte_flow_error_set(error, EINVAL,
400                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
401                                  "too many items to modify");
402                 /* Fetch variable byte size mask from the array. */
403                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
404                                            field->offset, field->size);
405                 if (!mask) {
406                         ++field;
407                         continue;
408                 }
409                 /* Deduce actual data width in bits from mask value. */
410                 off_b = rte_bsf32(mask);
411                 size_b = sizeof(uint32_t) * CHAR_BIT -
412                          off_b - __builtin_clz(mask);
413                 MLX5_ASSERT(size_b);
414                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
415                 actions[i] = (struct mlx5_modification_cmd) {
416                         .action_type = type,
417                         .field = field->id,
418                         .offset = off_b,
419                         .length = size_b,
420                 };
421                 /* Convert entire record to expected big-endian format. */
422                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
423                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
424                         MLX5_ASSERT(dcopy);
425                         actions[i].dst_field = dcopy->id;
426                         actions[i].dst_offset =
427                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
428                         /* Convert entire record to big-endian format. */
429                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
430                 } else {
431                         MLX5_ASSERT(item->spec);
432                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
433                                                    field->offset, field->size);
434                         /* Shift out the trailing masked bits from data. */
435                         data = (data & mask) >> off_b;
436                         actions[i].data1 = rte_cpu_to_be_32(data);
437                 }
438                 ++i;
439                 ++field;
440         } while (field->size);
441         if (resource->actions_num == i)
442                 return rte_flow_error_set(error, EINVAL,
443                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
444                                           "invalid modification flow item");
445         resource->actions_num = i;
446         return 0;
447 }
448
449 /**
450  * Convert modify-header set IPv4 address action to DV specification.
451  *
452  * @param[in,out] resource
453  *   Pointer to the modify-header resource.
454  * @param[in] action
455  *   Pointer to action specification.
456  * @param[out] error
457  *   Pointer to the error structure.
458  *
459  * @return
460  *   0 on success, a negative errno value otherwise and rte_errno is set.
461  */
462 static int
463 flow_dv_convert_action_modify_ipv4
464                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
465                          const struct rte_flow_action *action,
466                          struct rte_flow_error *error)
467 {
468         const struct rte_flow_action_set_ipv4 *conf =
469                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
470         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
471         struct rte_flow_item_ipv4 ipv4;
472         struct rte_flow_item_ipv4 ipv4_mask;
473
474         memset(&ipv4, 0, sizeof(ipv4));
475         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
476         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
477                 ipv4.hdr.src_addr = conf->ipv4_addr;
478                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
479         } else {
480                 ipv4.hdr.dst_addr = conf->ipv4_addr;
481                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
482         }
483         item.spec = &ipv4;
484         item.mask = &ipv4_mask;
485         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
486                                              MLX5_MODIFICATION_TYPE_SET, error);
487 }
488
489 /**
490  * Convert modify-header set IPv6 address action to DV specification.
491  *
492  * @param[in,out] resource
493  *   Pointer to the modify-header resource.
494  * @param[in] action
495  *   Pointer to action specification.
496  * @param[out] error
497  *   Pointer to the error structure.
498  *
499  * @return
500  *   0 on success, a negative errno value otherwise and rte_errno is set.
501  */
502 static int
503 flow_dv_convert_action_modify_ipv6
504                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
505                          const struct rte_flow_action *action,
506                          struct rte_flow_error *error)
507 {
508         const struct rte_flow_action_set_ipv6 *conf =
509                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
510         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
511         struct rte_flow_item_ipv6 ipv6;
512         struct rte_flow_item_ipv6 ipv6_mask;
513
514         memset(&ipv6, 0, sizeof(ipv6));
515         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
516         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
517                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
518                        sizeof(ipv6.hdr.src_addr));
519                 memcpy(&ipv6_mask.hdr.src_addr,
520                        &rte_flow_item_ipv6_mask.hdr.src_addr,
521                        sizeof(ipv6.hdr.src_addr));
522         } else {
523                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
524                        sizeof(ipv6.hdr.dst_addr));
525                 memcpy(&ipv6_mask.hdr.dst_addr,
526                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
527                        sizeof(ipv6.hdr.dst_addr));
528         }
529         item.spec = &ipv6;
530         item.mask = &ipv6_mask;
531         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
532                                              MLX5_MODIFICATION_TYPE_SET, error);
533 }
534
535 /**
536  * Convert modify-header set MAC address action to DV specification.
537  *
538  * @param[in,out] resource
539  *   Pointer to the modify-header resource.
540  * @param[in] action
541  *   Pointer to action specification.
542  * @param[out] error
543  *   Pointer to the error structure.
544  *
545  * @return
546  *   0 on success, a negative errno value otherwise and rte_errno is set.
547  */
548 static int
549 flow_dv_convert_action_modify_mac
550                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
551                          const struct rte_flow_action *action,
552                          struct rte_flow_error *error)
553 {
554         const struct rte_flow_action_set_mac *conf =
555                 (const struct rte_flow_action_set_mac *)(action->conf);
556         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
557         struct rte_flow_item_eth eth;
558         struct rte_flow_item_eth eth_mask;
559
560         memset(&eth, 0, sizeof(eth));
561         memset(&eth_mask, 0, sizeof(eth_mask));
562         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
563                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
564                        sizeof(eth.src.addr_bytes));
565                 memcpy(&eth_mask.src.addr_bytes,
566                        &rte_flow_item_eth_mask.src.addr_bytes,
567                        sizeof(eth_mask.src.addr_bytes));
568         } else {
569                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
570                        sizeof(eth.dst.addr_bytes));
571                 memcpy(&eth_mask.dst.addr_bytes,
572                        &rte_flow_item_eth_mask.dst.addr_bytes,
573                        sizeof(eth_mask.dst.addr_bytes));
574         }
575         item.spec = &eth;
576         item.mask = &eth_mask;
577         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
578                                              MLX5_MODIFICATION_TYPE_SET, error);
579 }
580
581 /**
582  * Convert modify-header set VLAN VID action to DV specification.
583  *
584  * @param[in,out] resource
585  *   Pointer to the modify-header resource.
586  * @param[in] action
587  *   Pointer to action specification.
588  * @param[out] error
589  *   Pointer to the error structure.
590  *
591  * @return
592  *   0 on success, a negative errno value otherwise and rte_errno is set.
593  */
594 static int
595 flow_dv_convert_action_modify_vlan_vid
596                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
597                          const struct rte_flow_action *action,
598                          struct rte_flow_error *error)
599 {
600         const struct rte_flow_action_of_set_vlan_vid *conf =
601                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
602         int i = resource->actions_num;
603         struct mlx5_modification_cmd *actions = resource->actions;
604         struct field_modify_info *field = modify_vlan_out_first_vid;
605
606         if (i >= MLX5_MAX_MODIFY_NUM)
607                 return rte_flow_error_set(error, EINVAL,
608                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
609                          "too many items to modify");
610         actions[i] = (struct mlx5_modification_cmd) {
611                 .action_type = MLX5_MODIFICATION_TYPE_SET,
612                 .field = field->id,
613                 .length = field->size,
614                 .offset = field->offset,
615         };
616         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
617         actions[i].data1 = conf->vlan_vid;
618         actions[i].data1 = actions[i].data1 << 16;
619         resource->actions_num = ++i;
620         return 0;
621 }
622
623 /**
624  * Convert modify-header set TP action to DV specification.
625  *
626  * @param[in,out] resource
627  *   Pointer to the modify-header resource.
628  * @param[in] action
629  *   Pointer to action specification.
630  * @param[in] items
631  *   Pointer to rte_flow_item objects list.
632  * @param[in] attr
633  *   Pointer to flow attributes structure.
634  * @param[in] dev_flow
635  *   Pointer to the sub flow.
636  * @param[in] tunnel_decap
637  *   Whether action is after tunnel decapsulation.
638  * @param[out] error
639  *   Pointer to the error structure.
640  *
641  * @return
642  *   0 on success, a negative errno value otherwise and rte_errno is set.
643  */
644 static int
645 flow_dv_convert_action_modify_tp
646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
647                          const struct rte_flow_action *action,
648                          const struct rte_flow_item *items,
649                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
650                          bool tunnel_decap, struct rte_flow_error *error)
651 {
652         const struct rte_flow_action_set_tp *conf =
653                 (const struct rte_flow_action_set_tp *)(action->conf);
654         struct rte_flow_item item;
655         struct rte_flow_item_udp udp;
656         struct rte_flow_item_udp udp_mask;
657         struct rte_flow_item_tcp tcp;
658         struct rte_flow_item_tcp tcp_mask;
659         struct field_modify_info *field;
660
661         if (!attr->valid)
662                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
663         if (attr->udp) {
664                 memset(&udp, 0, sizeof(udp));
665                 memset(&udp_mask, 0, sizeof(udp_mask));
666                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
667                         udp.hdr.src_port = conf->port;
668                         udp_mask.hdr.src_port =
669                                         rte_flow_item_udp_mask.hdr.src_port;
670                 } else {
671                         udp.hdr.dst_port = conf->port;
672                         udp_mask.hdr.dst_port =
673                                         rte_flow_item_udp_mask.hdr.dst_port;
674                 }
675                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
676                 item.spec = &udp;
677                 item.mask = &udp_mask;
678                 field = modify_udp;
679         } else {
680                 MLX5_ASSERT(attr->tcp);
681                 memset(&tcp, 0, sizeof(tcp));
682                 memset(&tcp_mask, 0, sizeof(tcp_mask));
683                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
684                         tcp.hdr.src_port = conf->port;
685                         tcp_mask.hdr.src_port =
686                                         rte_flow_item_tcp_mask.hdr.src_port;
687                 } else {
688                         tcp.hdr.dst_port = conf->port;
689                         tcp_mask.hdr.dst_port =
690                                         rte_flow_item_tcp_mask.hdr.dst_port;
691                 }
692                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
693                 item.spec = &tcp;
694                 item.mask = &tcp_mask;
695                 field = modify_tcp;
696         }
697         return flow_dv_convert_modify_action(&item, field, NULL, resource,
698                                              MLX5_MODIFICATION_TYPE_SET, error);
699 }
700
701 /**
702  * Convert modify-header set TTL action to DV specification.
703  *
704  * @param[in,out] resource
705  *   Pointer to the modify-header resource.
706  * @param[in] action
707  *   Pointer to action specification.
708  * @param[in] items
709  *   Pointer to rte_flow_item objects list.
710  * @param[in] attr
711  *   Pointer to flow attributes structure.
712  * @param[in] dev_flow
713  *   Pointer to the sub flow.
714  * @param[in] tunnel_decap
715  *   Whether action is after tunnel decapsulation.
716  * @param[out] error
717  *   Pointer to the error structure.
718  *
719  * @return
720  *   0 on success, a negative errno value otherwise and rte_errno is set.
721  */
722 static int
723 flow_dv_convert_action_modify_ttl
724                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
725                          const struct rte_flow_action *action,
726                          const struct rte_flow_item *items,
727                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
728                          bool tunnel_decap, struct rte_flow_error *error)
729 {
730         const struct rte_flow_action_set_ttl *conf =
731                 (const struct rte_flow_action_set_ttl *)(action->conf);
732         struct rte_flow_item item;
733         struct rte_flow_item_ipv4 ipv4;
734         struct rte_flow_item_ipv4 ipv4_mask;
735         struct rte_flow_item_ipv6 ipv6;
736         struct rte_flow_item_ipv6 ipv6_mask;
737         struct field_modify_info *field;
738
739         if (!attr->valid)
740                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
741         if (attr->ipv4) {
742                 memset(&ipv4, 0, sizeof(ipv4));
743                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
744                 ipv4.hdr.time_to_live = conf->ttl_value;
745                 ipv4_mask.hdr.time_to_live = 0xFF;
746                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
747                 item.spec = &ipv4;
748                 item.mask = &ipv4_mask;
749                 field = modify_ipv4;
750         } else {
751                 MLX5_ASSERT(attr->ipv6);
752                 memset(&ipv6, 0, sizeof(ipv6));
753                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
754                 ipv6.hdr.hop_limits = conf->ttl_value;
755                 ipv6_mask.hdr.hop_limits = 0xFF;
756                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
757                 item.spec = &ipv6;
758                 item.mask = &ipv6_mask;
759                 field = modify_ipv6;
760         }
761         return flow_dv_convert_modify_action(&item, field, NULL, resource,
762                                              MLX5_MODIFICATION_TYPE_SET, error);
763 }
764
765 /**
766  * Convert modify-header decrement TTL action to DV specification.
767  *
768  * @param[in,out] resource
769  *   Pointer to the modify-header resource.
770  * @param[in] action
771  *   Pointer to action specification.
772  * @param[in] items
773  *   Pointer to rte_flow_item objects list.
774  * @param[in] attr
775  *   Pointer to flow attributes structure.
776  * @param[in] dev_flow
777  *   Pointer to the sub flow.
778  * @param[in] tunnel_decap
779  *   Whether action is after tunnel decapsulation.
780  * @param[out] error
781  *   Pointer to the error structure.
782  *
783  * @return
784  *   0 on success, a negative errno value otherwise and rte_errno is set.
785  */
786 static int
787 flow_dv_convert_action_modify_dec_ttl
788                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
789                          const struct rte_flow_item *items,
790                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
791                          bool tunnel_decap, struct rte_flow_error *error)
792 {
793         struct rte_flow_item item;
794         struct rte_flow_item_ipv4 ipv4;
795         struct rte_flow_item_ipv4 ipv4_mask;
796         struct rte_flow_item_ipv6 ipv6;
797         struct rte_flow_item_ipv6 ipv6_mask;
798         struct field_modify_info *field;
799
800         if (!attr->valid)
801                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
802         if (attr->ipv4) {
803                 memset(&ipv4, 0, sizeof(ipv4));
804                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
805                 ipv4.hdr.time_to_live = 0xFF;
806                 ipv4_mask.hdr.time_to_live = 0xFF;
807                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
808                 item.spec = &ipv4;
809                 item.mask = &ipv4_mask;
810                 field = modify_ipv4;
811         } else {
812                 MLX5_ASSERT(attr->ipv6);
813                 memset(&ipv6, 0, sizeof(ipv6));
814                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
815                 ipv6.hdr.hop_limits = 0xFF;
816                 ipv6_mask.hdr.hop_limits = 0xFF;
817                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
818                 item.spec = &ipv6;
819                 item.mask = &ipv6_mask;
820                 field = modify_ipv6;
821         }
822         return flow_dv_convert_modify_action(&item, field, NULL, resource,
823                                              MLX5_MODIFICATION_TYPE_ADD, error);
824 }
825
826 /**
827  * Convert modify-header increment/decrement TCP Sequence number
828  * to DV specification.
829  *
830  * @param[in,out] resource
831  *   Pointer to the modify-header resource.
832  * @param[in] action
833  *   Pointer to action specification.
834  * @param[out] error
835  *   Pointer to the error structure.
836  *
837  * @return
838  *   0 on success, a negative errno value otherwise and rte_errno is set.
839  */
840 static int
841 flow_dv_convert_action_modify_tcp_seq
842                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
843                          const struct rte_flow_action *action,
844                          struct rte_flow_error *error)
845 {
846         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
847         uint64_t value = rte_be_to_cpu_32(*conf);
848         struct rte_flow_item item;
849         struct rte_flow_item_tcp tcp;
850         struct rte_flow_item_tcp tcp_mask;
851
852         memset(&tcp, 0, sizeof(tcp));
853         memset(&tcp_mask, 0, sizeof(tcp_mask));
854         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
855                 /*
856                  * The HW has no decrement operation, only increment operation.
857                  * To simulate decrement X from Y using increment operation
858                  * we need to add UINT32_MAX X times to Y.
859                  * Each adding of UINT32_MAX decrements Y by 1.
860                  */
861                 value *= UINT32_MAX;
862         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
863         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
864         item.type = RTE_FLOW_ITEM_TYPE_TCP;
865         item.spec = &tcp;
866         item.mask = &tcp_mask;
867         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
868                                              MLX5_MODIFICATION_TYPE_ADD, error);
869 }
870
871 /**
872  * Convert modify-header increment/decrement TCP Acknowledgment number
873  * to DV specification.
874  *
875  * @param[in,out] resource
876  *   Pointer to the modify-header resource.
877  * @param[in] action
878  *   Pointer to action specification.
879  * @param[out] error
880  *   Pointer to the error structure.
881  *
882  * @return
883  *   0 on success, a negative errno value otherwise and rte_errno is set.
884  */
885 static int
886 flow_dv_convert_action_modify_tcp_ack
887                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
888                          const struct rte_flow_action *action,
889                          struct rte_flow_error *error)
890 {
891         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
892         uint64_t value = rte_be_to_cpu_32(*conf);
893         struct rte_flow_item item;
894         struct rte_flow_item_tcp tcp;
895         struct rte_flow_item_tcp tcp_mask;
896
897         memset(&tcp, 0, sizeof(tcp));
898         memset(&tcp_mask, 0, sizeof(tcp_mask));
899         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
900                 /*
901                  * The HW has no decrement operation, only increment operation.
902                  * To simulate decrement X from Y using increment operation
903                  * we need to add UINT32_MAX X times to Y.
904                  * Each adding of UINT32_MAX decrements Y by 1.
905                  */
906                 value *= UINT32_MAX;
907         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
908         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
909         item.type = RTE_FLOW_ITEM_TYPE_TCP;
910         item.spec = &tcp;
911         item.mask = &tcp_mask;
912         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
913                                              MLX5_MODIFICATION_TYPE_ADD, error);
914 }
915
916 static enum mlx5_modification_field reg_to_field[] = {
917         [REG_NON] = MLX5_MODI_OUT_NONE,
918         [REG_A] = MLX5_MODI_META_DATA_REG_A,
919         [REG_B] = MLX5_MODI_META_DATA_REG_B,
920         [REG_C_0] = MLX5_MODI_META_REG_C_0,
921         [REG_C_1] = MLX5_MODI_META_REG_C_1,
922         [REG_C_2] = MLX5_MODI_META_REG_C_2,
923         [REG_C_3] = MLX5_MODI_META_REG_C_3,
924         [REG_C_4] = MLX5_MODI_META_REG_C_4,
925         [REG_C_5] = MLX5_MODI_META_REG_C_5,
926         [REG_C_6] = MLX5_MODI_META_REG_C_6,
927         [REG_C_7] = MLX5_MODI_META_REG_C_7,
928 };
929
930 /**
931  * Convert register set to DV specification.
932  *
933  * @param[in,out] resource
934  *   Pointer to the modify-header resource.
935  * @param[in] action
936  *   Pointer to action specification.
937  * @param[out] error
938  *   Pointer to the error structure.
939  *
940  * @return
941  *   0 on success, a negative errno value otherwise and rte_errno is set.
942  */
943 static int
944 flow_dv_convert_action_set_reg
945                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
946                          const struct rte_flow_action *action,
947                          struct rte_flow_error *error)
948 {
949         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
950         struct mlx5_modification_cmd *actions = resource->actions;
951         uint32_t i = resource->actions_num;
952
953         if (i >= MLX5_MAX_MODIFY_NUM)
954                 return rte_flow_error_set(error, EINVAL,
955                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
956                                           "too many items to modify");
957         MLX5_ASSERT(conf->id != REG_NON);
958         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
959         actions[i] = (struct mlx5_modification_cmd) {
960                 .action_type = MLX5_MODIFICATION_TYPE_SET,
961                 .field = reg_to_field[conf->id],
962         };
963         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
964         actions[i].data1 = rte_cpu_to_be_32(conf->data);
965         ++i;
966         resource->actions_num = i;
967         return 0;
968 }
969
970 /**
971  * Convert SET_TAG action to DV specification.
972  *
973  * @param[in] dev
974  *   Pointer to the rte_eth_dev structure.
975  * @param[in,out] resource
976  *   Pointer to the modify-header resource.
977  * @param[in] conf
978  *   Pointer to action specification.
979  * @param[out] error
980  *   Pointer to the error structure.
981  *
982  * @return
983  *   0 on success, a negative errno value otherwise and rte_errno is set.
984  */
985 static int
986 flow_dv_convert_action_set_tag
987                         (struct rte_eth_dev *dev,
988                          struct mlx5_flow_dv_modify_hdr_resource *resource,
989                          const struct rte_flow_action_set_tag *conf,
990                          struct rte_flow_error *error)
991 {
992         rte_be32_t data = rte_cpu_to_be_32(conf->data);
993         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
994         struct rte_flow_item item = {
995                 .spec = &data,
996                 .mask = &mask,
997         };
998         struct field_modify_info reg_c_x[] = {
999                 [1] = {0, 0, 0},
1000         };
1001         enum mlx5_modification_field reg_type;
1002         int ret;
1003
1004         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1005         if (ret < 0)
1006                 return ret;
1007         MLX5_ASSERT(ret != REG_NON);
1008         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009         reg_type = reg_to_field[ret];
1010         MLX5_ASSERT(reg_type > 0);
1011         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013                                              MLX5_MODIFICATION_TYPE_SET, error);
1014 }
1015
1016 /**
1017  * Convert internal COPY_REG action to DV specification.
1018  *
1019  * @param[in] dev
1020  *   Pointer to the rte_eth_dev structure.
1021  * @param[in,out] res
1022  *   Pointer to the modify-header resource.
1023  * @param[in] action
1024  *   Pointer to action specification.
1025  * @param[out] error
1026  *   Pointer to the error structure.
1027  *
1028  * @return
1029  *   0 on success, a negative errno value otherwise and rte_errno is set.
1030  */
1031 static int
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1034                                  const struct rte_flow_action *action,
1035                                  struct rte_flow_error *error)
1036 {
1037         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039         struct rte_flow_item item = {
1040                 .spec = NULL,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_src[] = {
1044                 {4, 0, reg_to_field[conf->src]},
1045                 {0, 0, 0},
1046         };
1047         struct field_modify_info reg_dst = {
1048                 .offset = 0,
1049                 .id = reg_to_field[conf->dst],
1050         };
1051         /* Adjust reg_c[0] usage according to reported mask. */
1052         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053                 struct mlx5_priv *priv = dev->data->dev_private;
1054                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1055
1056                 MLX5_ASSERT(reg_c0);
1057                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058                 if (conf->dst == REG_C_0) {
1059                         /* Copy to reg_c[0], within mask only. */
1060                         reg_dst.offset = rte_bsf32(reg_c0);
1061                         /*
1062                          * Mask is ignoring the enianness, because
1063                          * there is no conversion in datapath.
1064                          */
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066                         /* Copy from destination lower bits to reg_c[0]. */
1067                         mask = reg_c0 >> reg_dst.offset;
1068 #else
1069                         /* Copy from destination upper bits to reg_c[0]. */
1070                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071                                           rte_fls_u32(reg_c0));
1072 #endif
1073                 } else {
1074                         mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076                         /* Copy from reg_c[0] to destination lower bits. */
1077                         reg_dst.offset = 0;
1078 #else
1079                         /* Copy from reg_c[0] to destination upper bits. */
1080                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081                                          (rte_fls_u32(reg_c0) -
1082                                           rte_bsf32(reg_c0));
1083 #endif
1084                 }
1085         }
1086         return flow_dv_convert_modify_action(&item,
1087                                              reg_src, &reg_dst, res,
1088                                              MLX5_MODIFICATION_TYPE_COPY,
1089                                              error);
1090 }
1091
1092 /**
1093  * Convert MARK action to DV specification. This routine is used
1094  * in extensive metadata only and requires metadata register to be
1095  * handled. In legacy mode hardware tag resource is engaged.
1096  *
1097  * @param[in] dev
1098  *   Pointer to the rte_eth_dev structure.
1099  * @param[in] conf
1100  *   Pointer to MARK action specification.
1101  * @param[in,out] resource
1102  *   Pointer to the modify-header resource.
1103  * @param[out] error
1104  *   Pointer to the error structure.
1105  *
1106  * @return
1107  *   0 on success, a negative errno value otherwise and rte_errno is set.
1108  */
1109 static int
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111                             const struct rte_flow_action_mark *conf,
1112                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1113                             struct rte_flow_error *error)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117                                            priv->sh->dv_mark_mask);
1118         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119         struct rte_flow_item item = {
1120                 .spec = &data,
1121                 .mask = &mask,
1122         };
1123         struct field_modify_info reg_c_x[] = {
1124                 [1] = {0, 0, 0},
1125         };
1126         int reg;
1127
1128         if (!mask)
1129                 return rte_flow_error_set(error, EINVAL,
1130                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131                                           NULL, "zero mark action mask");
1132         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1133         if (reg < 0)
1134                 return reg;
1135         MLX5_ASSERT(reg > 0);
1136         if (reg == REG_C_0) {
1137                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1139
1140                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142                 mask = rte_cpu_to_be_32(mask << shl_c0);
1143         }
1144         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146                                              MLX5_MODIFICATION_TYPE_SET, error);
1147 }
1148
1149 /**
1150  * Get metadata register index for specified steering domain.
1151  *
1152  * @param[in] dev
1153  *   Pointer to the rte_eth_dev structure.
1154  * @param[in] attr
1155  *   Attributes of flow to determine steering domain.
1156  * @param[out] error
1157  *   Pointer to the error structure.
1158  *
1159  * @return
1160  *   positive index on success, a negative errno value otherwise
1161  *   and rte_errno is set.
1162  */
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165                          const struct rte_flow_attr *attr,
1166                          struct rte_flow_error *error)
1167 {
1168         int reg =
1169                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1170                                           MLX5_METADATA_FDB :
1171                                             attr->egress ?
1172                                             MLX5_METADATA_TX :
1173                                             MLX5_METADATA_RX, 0, error);
1174         if (reg < 0)
1175                 return rte_flow_error_set(error,
1176                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177                                           NULL, "unavailable "
1178                                           "metadata register");
1179         return reg;
1180 }
1181
1182 /**
1183  * Convert SET_META action to DV specification.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in,out] resource
1188  *   Pointer to the modify-header resource.
1189  * @param[in] attr
1190  *   Attributes of flow that includes this item.
1191  * @param[in] conf
1192  *   Pointer to action specification.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   0 on success, a negative errno value otherwise and rte_errno is set.
1198  */
1199 static int
1200 flow_dv_convert_action_set_meta
1201                         (struct rte_eth_dev *dev,
1202                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1203                          const struct rte_flow_attr *attr,
1204                          const struct rte_flow_action_set_meta *conf,
1205                          struct rte_flow_error *error)
1206 {
1207         uint32_t data = conf->data;
1208         uint32_t mask = conf->mask;
1209         struct rte_flow_item item = {
1210                 .spec = &data,
1211                 .mask = &mask,
1212         };
1213         struct field_modify_info reg_c_x[] = {
1214                 [1] = {0, 0, 0},
1215         };
1216         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1217
1218         if (reg < 0)
1219                 return reg;
1220         MLX5_ASSERT(reg != REG_NON);
1221         /*
1222          * In datapath code there is no endianness
1223          * coversions for perfromance reasons, all
1224          * pattern conversions are done in rte_flow.
1225          */
1226         if (reg == REG_C_0) {
1227                 struct mlx5_priv *priv = dev->data->dev_private;
1228                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1229                 uint32_t shl_c0;
1230
1231                 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233                 shl_c0 = rte_bsf32(msk_c0);
1234 #else
1235                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1236 #endif
1237                 mask <<= shl_c0;
1238                 data <<= shl_c0;
1239                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1240         }
1241         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242         /* The routine expects parameters in memory as big-endian ones. */
1243         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244                                              MLX5_MODIFICATION_TYPE_SET, error);
1245 }
1246
1247 /**
1248  * Convert modify-header set IPv4 DSCP action to DV specification.
1249  *
1250  * @param[in,out] resource
1251  *   Pointer to the modify-header resource.
1252  * @param[in] action
1253  *   Pointer to action specification.
1254  * @param[out] error
1255  *   Pointer to the error structure.
1256  *
1257  * @return
1258  *   0 on success, a negative errno value otherwise and rte_errno is set.
1259  */
1260 static int
1261 flow_dv_convert_action_modify_ipv4_dscp
1262                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263                          const struct rte_flow_action *action,
1264                          struct rte_flow_error *error)
1265 {
1266         const struct rte_flow_action_set_dscp *conf =
1267                 (const struct rte_flow_action_set_dscp *)(action->conf);
1268         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269         struct rte_flow_item_ipv4 ipv4;
1270         struct rte_flow_item_ipv4 ipv4_mask;
1271
1272         memset(&ipv4, 0, sizeof(ipv4));
1273         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274         ipv4.hdr.type_of_service = conf->dscp;
1275         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1276         item.spec = &ipv4;
1277         item.mask = &ipv4_mask;
1278         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv6 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv6_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304         struct rte_flow_item_ipv6 ipv6;
1305         struct rte_flow_item_ipv6 ipv6_mask;
1306
1307         memset(&ipv6, 0, sizeof(ipv6));
1308         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1309         /*
1310          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311          * rdma-core only accept the DSCP bits byte aligned start from
1312          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313          * bits in IPv6 case as rdma-core requires byte aligned value.
1314          */
1315         ipv6.hdr.vtc_flow = conf->dscp;
1316         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1317         item.spec = &ipv6;
1318         item.mask = &ipv6_mask;
1319         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320                                              MLX5_MODIFICATION_TYPE_SET, error);
1321 }
1322
1323 /**
1324  * Validate MARK item.
1325  *
1326  * @param[in] dev
1327  *   Pointer to the rte_eth_dev structure.
1328  * @param[in] item
1329  *   Item specification.
1330  * @param[in] attr
1331  *   Attributes of flow that includes this item.
1332  * @param[out] error
1333  *   Pointer to error structure.
1334  *
1335  * @return
1336  *   0 on success, a negative errno value otherwise and rte_errno is set.
1337  */
1338 static int
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340                            const struct rte_flow_item *item,
1341                            const struct rte_flow_attr *attr __rte_unused,
1342                            struct rte_flow_error *error)
1343 {
1344         struct mlx5_priv *priv = dev->data->dev_private;
1345         struct mlx5_dev_config *config = &priv->config;
1346         const struct rte_flow_item_mark *spec = item->spec;
1347         const struct rte_flow_item_mark *mask = item->mask;
1348         const struct rte_flow_item_mark nic_mask = {
1349                 .id = priv->sh->dv_mark_mask,
1350         };
1351         int ret;
1352
1353         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354                 return rte_flow_error_set(error, ENOTSUP,
1355                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1356                                           "extended metadata feature"
1357                                           " isn't enabled");
1358         if (!mlx5_flow_ext_mreg_supported(dev))
1359                 return rte_flow_error_set(error, ENOTSUP,
1360                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1361                                           "extended metadata register"
1362                                           " isn't supported");
1363         if (!nic_mask.id)
1364                 return rte_flow_error_set(error, ENOTSUP,
1365                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1366                                           "extended metadata register"
1367                                           " isn't available");
1368         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1369         if (ret < 0)
1370                 return ret;
1371         if (!spec)
1372                 return rte_flow_error_set(error, EINVAL,
1373                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1374                                           item->spec,
1375                                           "data cannot be empty");
1376         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377                 return rte_flow_error_set(error, EINVAL,
1378                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1379                                           &spec->id,
1380                                           "mark id exceeds the limit");
1381         if (!mask)
1382                 mask = &nic_mask;
1383         if (!mask->id)
1384                 return rte_flow_error_set(error, EINVAL,
1385                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386                                         "mask cannot be zero");
1387
1388         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389                                         (const uint8_t *)&nic_mask,
1390                                         sizeof(struct rte_flow_item_mark),
1391                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1392         if (ret < 0)
1393                 return ret;
1394         return 0;
1395 }
1396
1397 /**
1398  * Validate META item.
1399  *
1400  * @param[in] dev
1401  *   Pointer to the rte_eth_dev structure.
1402  * @param[in] item
1403  *   Item specification.
1404  * @param[in] attr
1405  *   Attributes of flow that includes this item.
1406  * @param[out] error
1407  *   Pointer to error structure.
1408  *
1409  * @return
1410  *   0 on success, a negative errno value otherwise and rte_errno is set.
1411  */
1412 static int
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414                            const struct rte_flow_item *item,
1415                            const struct rte_flow_attr *attr,
1416                            struct rte_flow_error *error)
1417 {
1418         struct mlx5_priv *priv = dev->data->dev_private;
1419         struct mlx5_dev_config *config = &priv->config;
1420         const struct rte_flow_item_meta *spec = item->spec;
1421         const struct rte_flow_item_meta *mask = item->mask;
1422         struct rte_flow_item_meta nic_mask = {
1423                 .data = UINT32_MAX
1424         };
1425         int reg;
1426         int ret;
1427
1428         if (!spec)
1429                 return rte_flow_error_set(error, EINVAL,
1430                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1431                                           item->spec,
1432                                           "data cannot be empty");
1433         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434                 if (!mlx5_flow_ext_mreg_supported(dev))
1435                         return rte_flow_error_set(error, ENOTSUP,
1436                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1437                                           "extended metadata register"
1438                                           " isn't supported");
1439                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1440                 if (reg < 0)
1441                         return reg;
1442                 if (reg == REG_NON)
1443                         return rte_flow_error_set(error, ENOTSUP,
1444                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1445                                         "unavalable extended metadata register");
1446                 if (reg == REG_B)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                           "match on reg_b "
1450                                           "isn't supported");
1451                 if (reg != REG_A)
1452                         nic_mask.data = priv->sh->dv_meta_mask;
1453         } else if (attr->transfer) {
1454                 return rte_flow_error_set(error, ENOTSUP,
1455                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1456                                         "extended metadata feature "
1457                                         "should be enabled when "
1458                                         "meta item is requested "
1459                                         "with e-switch mode ");
1460         }
1461         if (!mask)
1462                 mask = &rte_flow_item_meta_mask;
1463         if (!mask->data)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466                                         "mask cannot be zero");
1467
1468         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469                                         (const uint8_t *)&nic_mask,
1470                                         sizeof(struct rte_flow_item_meta),
1471                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1472         return ret;
1473 }
1474
1475 /**
1476  * Validate TAG item.
1477  *
1478  * @param[in] dev
1479  *   Pointer to the rte_eth_dev structure.
1480  * @param[in] item
1481  *   Item specification.
1482  * @param[in] attr
1483  *   Attributes of flow that includes this item.
1484  * @param[out] error
1485  *   Pointer to error structure.
1486  *
1487  * @return
1488  *   0 on success, a negative errno value otherwise and rte_errno is set.
1489  */
1490 static int
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492                           const struct rte_flow_item *item,
1493                           const struct rte_flow_attr *attr __rte_unused,
1494                           struct rte_flow_error *error)
1495 {
1496         const struct rte_flow_item_tag *spec = item->spec;
1497         const struct rte_flow_item_tag *mask = item->mask;
1498         const struct rte_flow_item_tag nic_mask = {
1499                 .data = RTE_BE32(UINT32_MAX),
1500                 .index = 0xff,
1501         };
1502         int ret;
1503
1504         if (!mlx5_flow_ext_mreg_supported(dev))
1505                 return rte_flow_error_set(error, ENOTSUP,
1506                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1507                                           "extensive metadata register"
1508                                           " isn't supported");
1509         if (!spec)
1510                 return rte_flow_error_set(error, EINVAL,
1511                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1512                                           item->spec,
1513                                           "data cannot be empty");
1514         if (!mask)
1515                 mask = &rte_flow_item_tag_mask;
1516         if (!mask->data)
1517                 return rte_flow_error_set(error, EINVAL,
1518                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519                                         "mask cannot be zero");
1520
1521         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522                                         (const uint8_t *)&nic_mask,
1523                                         sizeof(struct rte_flow_item_tag),
1524                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1525         if (ret < 0)
1526                 return ret;
1527         if (mask->index != 0xff)
1528                 return rte_flow_error_set(error, EINVAL,
1529                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530                                           "partial mask for tag index"
1531                                           " is not supported");
1532         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1533         if (ret < 0)
1534                 return ret;
1535         MLX5_ASSERT(ret != REG_NON);
1536         return 0;
1537 }
1538
1539 /**
1540  * Validate vport item.
1541  *
1542  * @param[in] dev
1543  *   Pointer to the rte_eth_dev structure.
1544  * @param[in] item
1545  *   Item specification.
1546  * @param[in] attr
1547  *   Attributes of flow that includes this item.
1548  * @param[in] item_flags
1549  *   Bit-fields that holds the items detected until now.
1550  * @param[out] error
1551  *   Pointer to error structure.
1552  *
1553  * @return
1554  *   0 on success, a negative errno value otherwise and rte_errno is set.
1555  */
1556 static int
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558                               const struct rte_flow_item *item,
1559                               const struct rte_flow_attr *attr,
1560                               uint64_t item_flags,
1561                               struct rte_flow_error *error)
1562 {
1563         const struct rte_flow_item_port_id *spec = item->spec;
1564         const struct rte_flow_item_port_id *mask = item->mask;
1565         const struct rte_flow_item_port_id switch_mask = {
1566                         .id = 0xffffffff,
1567         };
1568         struct mlx5_priv *esw_priv;
1569         struct mlx5_priv *dev_priv;
1570         int ret;
1571
1572         if (!attr->transfer)
1573                 return rte_flow_error_set(error, EINVAL,
1574                                           RTE_FLOW_ERROR_TYPE_ITEM,
1575                                           NULL,
1576                                           "match on port id is valid only"
1577                                           " when transfer flag is enabled");
1578         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579                 return rte_flow_error_set(error, ENOTSUP,
1580                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1581                                           "multiple source ports are not"
1582                                           " supported");
1583         if (!mask)
1584                 mask = &switch_mask;
1585         if (mask->id != 0xffffffff)
1586                 return rte_flow_error_set(error, ENOTSUP,
1587                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1588                                            mask,
1589                                            "no support for partial mask on"
1590                                            " \"id\" field");
1591         ret = mlx5_flow_item_acceptable
1592                                 (item, (const uint8_t *)mask,
1593                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1594                                  sizeof(struct rte_flow_item_port_id),
1595                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1596         if (ret)
1597                 return ret;
1598         if (!spec)
1599                 return 0;
1600         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1601         if (!esw_priv)
1602                 return rte_flow_error_set(error, rte_errno,
1603                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604                                           "failed to obtain E-Switch info for"
1605                                           " port");
1606         dev_priv = mlx5_dev_to_eswitch_info(dev);
1607         if (!dev_priv)
1608                 return rte_flow_error_set(error, rte_errno,
1609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1610                                           NULL,
1611                                           "failed to obtain E-Switch info");
1612         if (esw_priv->domain_id != dev_priv->domain_id)
1613                 return rte_flow_error_set(error, EINVAL,
1614                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615                                           "cannot match on a port from a"
1616                                           " different E-Switch");
1617         return 0;
1618 }
1619
1620 /**
1621  * Validate VLAN item.
1622  *
1623  * @param[in] item
1624  *   Item specification.
1625  * @param[in] item_flags
1626  *   Bit-fields that holds the items detected until now.
1627  * @param[in] dev
1628  *   Ethernet device flow is being created on.
1629  * @param[out] error
1630  *   Pointer to error structure.
1631  *
1632  * @return
1633  *   0 on success, a negative errno value otherwise and rte_errno is set.
1634  */
1635 static int
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637                            uint64_t item_flags,
1638                            struct rte_eth_dev *dev,
1639                            struct rte_flow_error *error)
1640 {
1641         const struct rte_flow_item_vlan *mask = item->mask;
1642         const struct rte_flow_item_vlan nic_mask = {
1643                 .tci = RTE_BE16(UINT16_MAX),
1644                 .inner_type = RTE_BE16(UINT16_MAX),
1645                 .has_more_vlan = 1,
1646         };
1647         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1648         int ret;
1649         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650                                         MLX5_FLOW_LAYER_INNER_L4) :
1651                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1652                                         MLX5_FLOW_LAYER_OUTER_L4);
1653         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1655
1656         if (item_flags & vlanm)
1657                 return rte_flow_error_set(error, EINVAL,
1658                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1659                                           "multiple VLAN layers not supported");
1660         else if ((item_flags & l34m) != 0)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "VLAN cannot follow L3/L4 layer");
1664         if (!mask)
1665                 mask = &rte_flow_item_vlan_mask;
1666         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667                                         (const uint8_t *)&nic_mask,
1668                                         sizeof(struct rte_flow_item_vlan),
1669                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1670         if (ret)
1671                 return ret;
1672         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673                 struct mlx5_priv *priv = dev->data->dev_private;
1674
1675                 if (priv->vmwa_context) {
1676                         /*
1677                          * Non-NULL context means we have a virtual machine
1678                          * and SR-IOV enabled, we have to create VLAN interface
1679                          * to make hypervisor to setup E-Switch vport
1680                          * context correctly. We avoid creating the multiple
1681                          * VLAN interfaces, so we cannot support VLAN tag mask.
1682                          */
1683                         return rte_flow_error_set(error, EINVAL,
1684                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1685                                                   item,
1686                                                   "VLAN tag mask is not"
1687                                                   " supported in virtual"
1688                                                   " environment");
1689                 }
1690         }
1691         return 0;
1692 }
1693
1694 /*
1695  * GTP flags are contained in 1 byte of the format:
1696  * -------------------------------------------
1697  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1698  * |-----------------------------------------|
1699  * | value | Version | PT | Res | E | S | PN |
1700  * -------------------------------------------
1701  *
1702  * Matching is supported only for GTP flags E, S, PN.
1703  */
1704 #define MLX5_GTP_FLAGS_MASK     0x07
1705
1706 /**
1707  * Validate GTP item.
1708  *
1709  * @param[in] dev
1710  *   Pointer to the rte_eth_dev structure.
1711  * @param[in] item
1712  *   Item specification.
1713  * @param[in] item_flags
1714  *   Bit-fields that holds the items detected until now.
1715  * @param[out] error
1716  *   Pointer to error structure.
1717  *
1718  * @return
1719  *   0 on success, a negative errno value otherwise and rte_errno is set.
1720  */
1721 static int
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723                           const struct rte_flow_item *item,
1724                           uint64_t item_flags,
1725                           struct rte_flow_error *error)
1726 {
1727         struct mlx5_priv *priv = dev->data->dev_private;
1728         const struct rte_flow_item_gtp *spec = item->spec;
1729         const struct rte_flow_item_gtp *mask = item->mask;
1730         const struct rte_flow_item_gtp nic_mask = {
1731                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1732                 .msg_type = 0xff,
1733                 .teid = RTE_BE32(0xffffffff),
1734         };
1735
1736         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1739                                           "GTP support is not enabled");
1740         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "multiple tunnel layers not"
1744                                           " supported");
1745         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1748                                           "no outer UDP layer found");
1749         if (!mask)
1750                 mask = &rte_flow_item_gtp_mask;
1751         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752                 return rte_flow_error_set(error, ENOTSUP,
1753                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1754                                           "Match is supported for GTP"
1755                                           " flags only");
1756         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757                                          (const uint8_t *)&nic_mask,
1758                                          sizeof(struct rte_flow_item_gtp),
1759                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1760 }
1761
1762 /**
1763  * Validate GTP PSC item.
1764  *
1765  * @param[in] item
1766  *   Item specification.
1767  * @param[in] last_item
1768  *   Previous validated item in the pattern items.
1769  * @param[in] gtp_item
1770  *   Previous GTP item specification.
1771  * @param[in] attr
1772  *   Pointer to flow attributes.
1773  * @param[out] error
1774  *   Pointer to error structure.
1775  *
1776  * @return
1777  *   0 on success, a negative errno value otherwise and rte_errno is set.
1778  */
1779 static int
1780 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1781                               uint64_t last_item,
1782                               const struct rte_flow_item *gtp_item,
1783                               const struct rte_flow_attr *attr,
1784                               struct rte_flow_error *error)
1785 {
1786         const struct rte_flow_item_gtp *gtp_spec;
1787         const struct rte_flow_item_gtp *gtp_mask;
1788         const struct rte_flow_item_gtp_psc *spec;
1789         const struct rte_flow_item_gtp_psc *mask;
1790         const struct rte_flow_item_gtp_psc nic_mask = {
1791                 .pdu_type = 0xFF,
1792                 .qfi = 0xFF,
1793         };
1794
1795         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1796                 return rte_flow_error_set
1797                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1798                          "GTP PSC item must be preceded with GTP item");
1799         gtp_spec = gtp_item->spec;
1800         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1801         /* GTP spec and E flag is requested to match zero. */
1802         if (gtp_spec &&
1803                 (gtp_mask->v_pt_rsv_flags &
1804                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1805                 return rte_flow_error_set
1806                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1807                          "GTP E flag must be 1 to match GTP PSC");
1808         /* Check the flow is not created in group zero. */
1809         if (!attr->transfer && !attr->group)
1810                 return rte_flow_error_set
1811                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1812                          "GTP PSC is not supported for group 0");
1813         /* GTP spec is here and E flag is requested to match zero. */
1814         if (!item->spec)
1815                 return 0;
1816         spec = item->spec;
1817         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1818         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1819                 return rte_flow_error_set
1820                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1821                          "PDU type should be smaller than 16");
1822         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1823                                          (const uint8_t *)&nic_mask,
1824                                          sizeof(struct rte_flow_item_gtp_psc),
1825                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1826 }
1827
1828 /**
1829  * Validate IPV4 item.
1830  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1831  * add specific validation of fragment_offset field,
1832  *
1833  * @param[in] item
1834  *   Item specification.
1835  * @param[in] item_flags
1836  *   Bit-fields that holds the items detected until now.
1837  * @param[out] error
1838  *   Pointer to error structure.
1839  *
1840  * @return
1841  *   0 on success, a negative errno value otherwise and rte_errno is set.
1842  */
1843 static int
1844 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1845                            uint64_t item_flags,
1846                            uint64_t last_item,
1847                            uint16_t ether_type,
1848                            struct rte_flow_error *error)
1849 {
1850         int ret;
1851         const struct rte_flow_item_ipv4 *spec = item->spec;
1852         const struct rte_flow_item_ipv4 *last = item->last;
1853         const struct rte_flow_item_ipv4 *mask = item->mask;
1854         rte_be16_t fragment_offset_spec = 0;
1855         rte_be16_t fragment_offset_last = 0;
1856         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1857                 .hdr = {
1858                         .src_addr = RTE_BE32(0xffffffff),
1859                         .dst_addr = RTE_BE32(0xffffffff),
1860                         .type_of_service = 0xff,
1861                         .fragment_offset = RTE_BE16(0xffff),
1862                         .next_proto_id = 0xff,
1863                         .time_to_live = 0xff,
1864                 },
1865         };
1866
1867         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1868                                            ether_type, &nic_ipv4_mask,
1869                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1870         if (ret < 0)
1871                 return ret;
1872         if (spec && mask)
1873                 fragment_offset_spec = spec->hdr.fragment_offset &
1874                                        mask->hdr.fragment_offset;
1875         if (!fragment_offset_spec)
1876                 return 0;
1877         /*
1878          * spec and mask are valid, enforce using full mask to make sure the
1879          * complete value is used correctly.
1880          */
1881         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1882                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1883                 return rte_flow_error_set(error, EINVAL,
1884                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1885                                           item, "must use full mask for"
1886                                           " fragment_offset");
1887         /*
1888          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1889          * indicating this is 1st fragment of fragmented packet.
1890          * This is not yet supported in MLX5, return appropriate error message.
1891          */
1892         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1895                                           "match on first fragment not "
1896                                           "supported");
1897         if (fragment_offset_spec && !last)
1898                 return rte_flow_error_set(error, ENOTSUP,
1899                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1900                                           "specified value not supported");
1901         /* spec and last are valid, validate the specified range. */
1902         fragment_offset_last = last->hdr.fragment_offset &
1903                                mask->hdr.fragment_offset;
1904         /*
1905          * Match on fragment_offset spec 0x2001 and last 0x3fff
1906          * means MF is 1 and frag-offset is > 0.
1907          * This packet is fragment 2nd and onward, excluding last.
1908          * This is not yet supported in MLX5, return appropriate
1909          * error message.
1910          */
1911         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1912             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1913                 return rte_flow_error_set(error, ENOTSUP,
1914                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1915                                           last, "match on following "
1916                                           "fragments not supported");
1917         /*
1918          * Match on fragment_offset spec 0x0001 and last 0x1fff
1919          * means MF is 0 and frag-offset is > 0.
1920          * This packet is last fragment of fragmented packet.
1921          * This is not yet supported in MLX5, return appropriate
1922          * error message.
1923          */
1924         if (fragment_offset_spec == RTE_BE16(1) &&
1925             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1926                 return rte_flow_error_set(error, ENOTSUP,
1927                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1928                                           last, "match on last "
1929                                           "fragment not supported");
1930         /*
1931          * Match on fragment_offset spec 0x0001 and last 0x3fff
1932          * means MF and/or frag-offset is not 0.
1933          * This is a fragmented packet.
1934          * Other range values are invalid and rejected.
1935          */
1936         if (!(fragment_offset_spec == RTE_BE16(1) &&
1937               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1938                 return rte_flow_error_set(error, ENOTSUP,
1939                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1940                                           "specified range not supported");
1941         return 0;
1942 }
1943
1944 /**
1945  * Validate IPV6 fragment extension item.
1946  *
1947  * @param[in] item
1948  *   Item specification.
1949  * @param[in] item_flags
1950  *   Bit-fields that holds the items detected until now.
1951  * @param[out] error
1952  *   Pointer to error structure.
1953  *
1954  * @return
1955  *   0 on success, a negative errno value otherwise and rte_errno is set.
1956  */
1957 static int
1958 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1959                                     uint64_t item_flags,
1960                                     struct rte_flow_error *error)
1961 {
1962         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1963         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1964         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1965         rte_be16_t frag_data_spec = 0;
1966         rte_be16_t frag_data_last = 0;
1967         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1968         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1969                                       MLX5_FLOW_LAYER_OUTER_L4;
1970         int ret = 0;
1971         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1972                 .hdr = {
1973                         .next_header = 0xff,
1974                         .frag_data = RTE_BE16(0xffff),
1975                 },
1976         };
1977
1978         if (item_flags & l4m)
1979                 return rte_flow_error_set(error, EINVAL,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "ipv6 fragment extension item cannot "
1982                                           "follow L4 item.");
1983         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1984             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1985                 return rte_flow_error_set(error, EINVAL,
1986                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1987                                           "ipv6 fragment extension item must "
1988                                           "follow ipv6 item");
1989         if (spec && mask)
1990                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1991         if (!frag_data_spec)
1992                 return 0;
1993         /*
1994          * spec and mask are valid, enforce using full mask to make sure the
1995          * complete value is used correctly.
1996          */
1997         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1998                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1999                 return rte_flow_error_set(error, EINVAL,
2000                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2001                                           item, "must use full mask for"
2002                                           " frag_data");
2003         /*
2004          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2005          * This is 1st fragment of fragmented packet.
2006          */
2007         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2008                 return rte_flow_error_set(error, ENOTSUP,
2009                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2010                                           "match on first fragment not "
2011                                           "supported");
2012         if (frag_data_spec && !last)
2013                 return rte_flow_error_set(error, EINVAL,
2014                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2015                                           "specified value not supported");
2016         ret = mlx5_flow_item_acceptable
2017                                 (item, (const uint8_t *)mask,
2018                                  (const uint8_t *)&nic_mask,
2019                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2020                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2021         if (ret)
2022                 return ret;
2023         /* spec and last are valid, validate the specified range. */
2024         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2025         /*
2026          * Match on frag_data spec 0x0009 and last 0xfff9
2027          * means M is 1 and frag-offset is > 0.
2028          * This packet is fragment 2nd and onward, excluding last.
2029          * This is not yet supported in MLX5, return appropriate
2030          * error message.
2031          */
2032         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2033                                        RTE_IPV6_EHDR_MF_MASK) &&
2034             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2035                 return rte_flow_error_set(error, ENOTSUP,
2036                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2037                                           last, "match on following "
2038                                           "fragments not supported");
2039         /*
2040          * Match on frag_data spec 0x0008 and last 0xfff8
2041          * means M is 0 and frag-offset is > 0.
2042          * This packet is last fragment of fragmented packet.
2043          * This is not yet supported in MLX5, return appropriate
2044          * error message.
2045          */
2046         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2047             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2048                 return rte_flow_error_set(error, ENOTSUP,
2049                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2050                                           last, "match on last "
2051                                           "fragment not supported");
2052         /* Other range values are invalid and rejected. */
2053         return rte_flow_error_set(error, EINVAL,
2054                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2055                                   "specified range not supported");
2056 }
2057
2058 /**
2059  * Validate the pop VLAN action.
2060  *
2061  * @param[in] dev
2062  *   Pointer to the rte_eth_dev structure.
2063  * @param[in] action_flags
2064  *   Holds the actions detected until now.
2065  * @param[in] action
2066  *   Pointer to the pop vlan action.
2067  * @param[in] item_flags
2068  *   The items found in this flow rule.
2069  * @param[in] attr
2070  *   Pointer to flow attributes.
2071  * @param[out] error
2072  *   Pointer to error structure.
2073  *
2074  * @return
2075  *   0 on success, a negative errno value otherwise and rte_errno is set.
2076  */
2077 static int
2078 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2079                                  uint64_t action_flags,
2080                                  const struct rte_flow_action *action,
2081                                  uint64_t item_flags,
2082                                  const struct rte_flow_attr *attr,
2083                                  struct rte_flow_error *error)
2084 {
2085         const struct mlx5_priv *priv = dev->data->dev_private;
2086
2087         (void)action;
2088         (void)attr;
2089         if (!priv->sh->pop_vlan_action)
2090                 return rte_flow_error_set(error, ENOTSUP,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "pop vlan action is not supported");
2094         if (attr->egress)
2095                 return rte_flow_error_set(error, ENOTSUP,
2096                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2097                                           NULL,
2098                                           "pop vlan action not supported for "
2099                                           "egress");
2100         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2101                 return rte_flow_error_set(error, ENOTSUP,
2102                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2103                                           "no support for multiple VLAN "
2104                                           "actions");
2105         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2106         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2107             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2108                 return rte_flow_error_set(error, ENOTSUP,
2109                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2110                                           NULL,
2111                                           "cannot pop vlan after decap without "
2112                                           "match on inner vlan in the flow");
2113         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2114         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2115             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2116                 return rte_flow_error_set(error, ENOTSUP,
2117                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2118                                           NULL,
2119                                           "cannot pop vlan without a "
2120                                           "match on (outer) vlan in the flow");
2121         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2122                 return rte_flow_error_set(error, EINVAL,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2124                                           "wrong action order, port_id should "
2125                                           "be after pop VLAN action");
2126         if (!attr->transfer && priv->representor)
2127                 return rte_flow_error_set(error, ENOTSUP,
2128                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2129                                           "pop vlan action for VF representor "
2130                                           "not supported on NIC table");
2131         return 0;
2132 }
2133
2134 /**
2135  * Get VLAN default info from vlan match info.
2136  *
2137  * @param[in] items
2138  *   the list of item specifications.
2139  * @param[out] vlan
2140  *   pointer VLAN info to fill to.
2141  *
2142  * @return
2143  *   0 on success, a negative errno value otherwise and rte_errno is set.
2144  */
2145 static void
2146 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2147                                   struct rte_vlan_hdr *vlan)
2148 {
2149         const struct rte_flow_item_vlan nic_mask = {
2150                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2151                                 MLX5DV_FLOW_VLAN_VID_MASK),
2152                 .inner_type = RTE_BE16(0xffff),
2153         };
2154
2155         if (items == NULL)
2156                 return;
2157         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2158                 int type = items->type;
2159
2160                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2161                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2162                         break;
2163         }
2164         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2165                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2166                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2167
2168                 /* If VLAN item in pattern doesn't contain data, return here. */
2169                 if (!vlan_v)
2170                         return;
2171                 if (!vlan_m)
2172                         vlan_m = &nic_mask;
2173                 /* Only full match values are accepted */
2174                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2175                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2176                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2177                         vlan->vlan_tci |=
2178                                 rte_be_to_cpu_16(vlan_v->tci &
2179                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2180                 }
2181                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2182                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2183                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2184                         vlan->vlan_tci |=
2185                                 rte_be_to_cpu_16(vlan_v->tci &
2186                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2187                 }
2188                 if (vlan_m->inner_type == nic_mask.inner_type)
2189                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2190                                                            vlan_m->inner_type);
2191         }
2192 }
2193
2194 /**
2195  * Validate the push VLAN action.
2196  *
2197  * @param[in] dev
2198  *   Pointer to the rte_eth_dev structure.
2199  * @param[in] action_flags
2200  *   Holds the actions detected until now.
2201  * @param[in] item_flags
2202  *   The items found in this flow rule.
2203  * @param[in] action
2204  *   Pointer to the action structure.
2205  * @param[in] attr
2206  *   Pointer to flow attributes
2207  * @param[out] error
2208  *   Pointer to error structure.
2209  *
2210  * @return
2211  *   0 on success, a negative errno value otherwise and rte_errno is set.
2212  */
2213 static int
2214 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2215                                   uint64_t action_flags,
2216                                   const struct rte_flow_item_vlan *vlan_m,
2217                                   const struct rte_flow_action *action,
2218                                   const struct rte_flow_attr *attr,
2219                                   struct rte_flow_error *error)
2220 {
2221         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2222         const struct mlx5_priv *priv = dev->data->dev_private;
2223
2224         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2225             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2226                 return rte_flow_error_set(error, EINVAL,
2227                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2228                                           "invalid vlan ethertype");
2229         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2232                                           "wrong action order, port_id should "
2233                                           "be after push VLAN");
2234         if (!attr->transfer && priv->representor)
2235                 return rte_flow_error_set(error, ENOTSUP,
2236                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2237                                           "push vlan action for VF representor "
2238                                           "not supported on NIC table");
2239         if (vlan_m &&
2240             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2241             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2242                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2243             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2244             !(mlx5_flow_find_action
2245                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2246                 return rte_flow_error_set(error, EINVAL,
2247                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2248                                           "not full match mask on VLAN PCP and "
2249                                           "there is no of_set_vlan_pcp action, "
2250                                           "push VLAN action cannot figure out "
2251                                           "PCP value");
2252         if (vlan_m &&
2253             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2254             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2255                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2256             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2257             !(mlx5_flow_find_action
2258                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2259                 return rte_flow_error_set(error, EINVAL,
2260                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2261                                           "not full match mask on VLAN VID and "
2262                                           "there is no of_set_vlan_vid action, "
2263                                           "push VLAN action cannot figure out "
2264                                           "VID value");
2265         (void)attr;
2266         return 0;
2267 }
2268
2269 /**
2270  * Validate the set VLAN PCP.
2271  *
2272  * @param[in] action_flags
2273  *   Holds the actions detected until now.
2274  * @param[in] actions
2275  *   Pointer to the list of actions remaining in the flow rule.
2276  * @param[out] error
2277  *   Pointer to error structure.
2278  *
2279  * @return
2280  *   0 on success, a negative errno value otherwise and rte_errno is set.
2281  */
2282 static int
2283 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2284                                      const struct rte_flow_action actions[],
2285                                      struct rte_flow_error *error)
2286 {
2287         const struct rte_flow_action *action = actions;
2288         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2289
2290         if (conf->vlan_pcp > 7)
2291                 return rte_flow_error_set(error, EINVAL,
2292                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2293                                           "VLAN PCP value is too big");
2294         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2295                 return rte_flow_error_set(error, ENOTSUP,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "set VLAN PCP action must follow "
2298                                           "the push VLAN action");
2299         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2300                 return rte_flow_error_set(error, ENOTSUP,
2301                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2302                                           "Multiple VLAN PCP modification are "
2303                                           "not supported");
2304         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2305                 return rte_flow_error_set(error, EINVAL,
2306                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2307                                           "wrong action order, port_id should "
2308                                           "be after set VLAN PCP");
2309         return 0;
2310 }
2311
2312 /**
2313  * Validate the set VLAN VID.
2314  *
2315  * @param[in] item_flags
2316  *   Holds the items detected in this rule.
2317  * @param[in] action_flags
2318  *   Holds the actions detected until now.
2319  * @param[in] actions
2320  *   Pointer to the list of actions remaining in the flow rule.
2321  * @param[out] error
2322  *   Pointer to error structure.
2323  *
2324  * @return
2325  *   0 on success, a negative errno value otherwise and rte_errno is set.
2326  */
2327 static int
2328 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2329                                      uint64_t action_flags,
2330                                      const struct rte_flow_action actions[],
2331                                      struct rte_flow_error *error)
2332 {
2333         const struct rte_flow_action *action = actions;
2334         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2335
2336         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2337                 return rte_flow_error_set(error, EINVAL,
2338                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2339                                           "VLAN VID value is too big");
2340         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2341             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2342                 return rte_flow_error_set(error, ENOTSUP,
2343                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2344                                           "set VLAN VID action must follow push"
2345                                           " VLAN action or match on VLAN item");
2346         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2347                 return rte_flow_error_set(error, ENOTSUP,
2348                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2349                                           "Multiple VLAN VID modifications are "
2350                                           "not supported");
2351         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2352                 return rte_flow_error_set(error, EINVAL,
2353                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2354                                           "wrong action order, port_id should "
2355                                           "be after set VLAN VID");
2356         return 0;
2357 }
2358
2359 /*
2360  * Validate the FLAG action.
2361  *
2362  * @param[in] dev
2363  *   Pointer to the rte_eth_dev structure.
2364  * @param[in] action_flags
2365  *   Holds the actions detected until now.
2366  * @param[in] attr
2367  *   Pointer to flow attributes
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2376                              uint64_t action_flags,
2377                              const struct rte_flow_attr *attr,
2378                              struct rte_flow_error *error)
2379 {
2380         struct mlx5_priv *priv = dev->data->dev_private;
2381         struct mlx5_dev_config *config = &priv->config;
2382         int ret;
2383
2384         /* Fall back if no extended metadata register support. */
2385         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2386                 return mlx5_flow_validate_action_flag(action_flags, attr,
2387                                                       error);
2388         /* Extensive metadata mode requires registers. */
2389         if (!mlx5_flow_ext_mreg_supported(dev))
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2392                                           "no metadata registers "
2393                                           "to support flag action");
2394         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2397                                           "extended metadata register"
2398                                           " isn't available");
2399         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2400         if (ret < 0)
2401                 return ret;
2402         MLX5_ASSERT(ret > 0);
2403         if (action_flags & MLX5_FLOW_ACTION_MARK)
2404                 return rte_flow_error_set(error, EINVAL,
2405                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2406                                           "can't mark and flag in same flow");
2407         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2408                 return rte_flow_error_set(error, EINVAL,
2409                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410                                           "can't have 2 flag"
2411                                           " actions in same flow");
2412         return 0;
2413 }
2414
2415 /**
2416  * Validate MARK action.
2417  *
2418  * @param[in] dev
2419  *   Pointer to the rte_eth_dev structure.
2420  * @param[in] action
2421  *   Pointer to action.
2422  * @param[in] action_flags
2423  *   Holds the actions detected until now.
2424  * @param[in] attr
2425  *   Pointer to flow attributes
2426  * @param[out] error
2427  *   Pointer to error structure.
2428  *
2429  * @return
2430  *   0 on success, a negative errno value otherwise and rte_errno is set.
2431  */
2432 static int
2433 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2434                              const struct rte_flow_action *action,
2435                              uint64_t action_flags,
2436                              const struct rte_flow_attr *attr,
2437                              struct rte_flow_error *error)
2438 {
2439         struct mlx5_priv *priv = dev->data->dev_private;
2440         struct mlx5_dev_config *config = &priv->config;
2441         const struct rte_flow_action_mark *mark = action->conf;
2442         int ret;
2443
2444         /* Fall back if no extended metadata register support. */
2445         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2446                 return mlx5_flow_validate_action_mark(action, action_flags,
2447                                                       attr, error);
2448         /* Extensive metadata mode requires registers. */
2449         if (!mlx5_flow_ext_mreg_supported(dev))
2450                 return rte_flow_error_set(error, ENOTSUP,
2451                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2452                                           "no metadata registers "
2453                                           "to support mark action");
2454         if (!priv->sh->dv_mark_mask)
2455                 return rte_flow_error_set(error, ENOTSUP,
2456                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2457                                           "extended metadata register"
2458                                           " isn't available");
2459         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2460         if (ret < 0)
2461                 return ret;
2462         MLX5_ASSERT(ret > 0);
2463         if (!mark)
2464                 return rte_flow_error_set(error, EINVAL,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2466                                           "configuration cannot be null");
2467         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2468                 return rte_flow_error_set(error, EINVAL,
2469                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2470                                           &mark->id,
2471                                           "mark id exceeds the limit");
2472         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2475                                           "can't flag and mark in same flow");
2476         if (action_flags & MLX5_FLOW_ACTION_MARK)
2477                 return rte_flow_error_set(error, EINVAL,
2478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2479                                           "can't have 2 mark actions in same"
2480                                           " flow");
2481         return 0;
2482 }
2483
2484 /**
2485  * Validate SET_META action.
2486  *
2487  * @param[in] dev
2488  *   Pointer to the rte_eth_dev structure.
2489  * @param[in] action
2490  *   Pointer to the action structure.
2491  * @param[in] action_flags
2492  *   Holds the actions detected until now.
2493  * @param[in] attr
2494  *   Pointer to flow attributes
2495  * @param[out] error
2496  *   Pointer to error structure.
2497  *
2498  * @return
2499  *   0 on success, a negative errno value otherwise and rte_errno is set.
2500  */
2501 static int
2502 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2503                                  const struct rte_flow_action *action,
2504                                  uint64_t action_flags __rte_unused,
2505                                  const struct rte_flow_attr *attr,
2506                                  struct rte_flow_error *error)
2507 {
2508         const struct rte_flow_action_set_meta *conf;
2509         uint32_t nic_mask = UINT32_MAX;
2510         int reg;
2511
2512         if (!mlx5_flow_ext_mreg_supported(dev))
2513                 return rte_flow_error_set(error, ENOTSUP,
2514                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2515                                           "extended metadata register"
2516                                           " isn't supported");
2517         reg = flow_dv_get_metadata_reg(dev, attr, error);
2518         if (reg < 0)
2519                 return reg;
2520         if (reg == REG_NON)
2521                 return rte_flow_error_set(error, ENOTSUP,
2522                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2523                                           "unavalable extended metadata register");
2524         if (reg != REG_A && reg != REG_B) {
2525                 struct mlx5_priv *priv = dev->data->dev_private;
2526
2527                 nic_mask = priv->sh->dv_meta_mask;
2528         }
2529         if (!(action->conf))
2530                 return rte_flow_error_set(error, EINVAL,
2531                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2532                                           "configuration cannot be null");
2533         conf = (const struct rte_flow_action_set_meta *)action->conf;
2534         if (!conf->mask)
2535                 return rte_flow_error_set(error, EINVAL,
2536                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2537                                           "zero mask doesn't have any effect");
2538         if (conf->mask & ~nic_mask)
2539                 return rte_flow_error_set(error, EINVAL,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "meta data must be within reg C0");
2542         return 0;
2543 }
2544
2545 /**
2546  * Validate SET_TAG action.
2547  *
2548  * @param[in] dev
2549  *   Pointer to the rte_eth_dev structure.
2550  * @param[in] action
2551  *   Pointer to the action structure.
2552  * @param[in] action_flags
2553  *   Holds the actions detected until now.
2554  * @param[in] attr
2555  *   Pointer to flow attributes
2556  * @param[out] error
2557  *   Pointer to error structure.
2558  *
2559  * @return
2560  *   0 on success, a negative errno value otherwise and rte_errno is set.
2561  */
2562 static int
2563 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2564                                 const struct rte_flow_action *action,
2565                                 uint64_t action_flags,
2566                                 const struct rte_flow_attr *attr,
2567                                 struct rte_flow_error *error)
2568 {
2569         const struct rte_flow_action_set_tag *conf;
2570         const uint64_t terminal_action_flags =
2571                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2572                 MLX5_FLOW_ACTION_RSS;
2573         int ret;
2574
2575         if (!mlx5_flow_ext_mreg_supported(dev))
2576                 return rte_flow_error_set(error, ENOTSUP,
2577                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2578                                           "extensive metadata register"
2579                                           " isn't supported");
2580         if (!(action->conf))
2581                 return rte_flow_error_set(error, EINVAL,
2582                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2583                                           "configuration cannot be null");
2584         conf = (const struct rte_flow_action_set_tag *)action->conf;
2585         if (!conf->mask)
2586                 return rte_flow_error_set(error, EINVAL,
2587                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2588                                           "zero mask doesn't have any effect");
2589         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2590         if (ret < 0)
2591                 return ret;
2592         if (!attr->transfer && attr->ingress &&
2593             (action_flags & terminal_action_flags))
2594                 return rte_flow_error_set(error, EINVAL,
2595                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2596                                           "set_tag has no effect"
2597                                           " with terminal actions");
2598         return 0;
2599 }
2600
2601 /**
2602  * Validate count action.
2603  *
2604  * @param[in] dev
2605  *   Pointer to rte_eth_dev structure.
2606  * @param[out] error
2607  *   Pointer to error structure.
2608  *
2609  * @return
2610  *   0 on success, a negative errno value otherwise and rte_errno is set.
2611  */
2612 static int
2613 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2614                               struct rte_flow_error *error)
2615 {
2616         struct mlx5_priv *priv = dev->data->dev_private;
2617
2618         if (!priv->config.devx)
2619                 goto notsup_err;
2620 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2621         return 0;
2622 #endif
2623 notsup_err:
2624         return rte_flow_error_set
2625                       (error, ENOTSUP,
2626                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2627                        NULL,
2628                        "count action not supported");
2629 }
2630
2631 /**
2632  * Validate the L2 encap action.
2633  *
2634  * @param[in] dev
2635  *   Pointer to the rte_eth_dev structure.
2636  * @param[in] action_flags
2637  *   Holds the actions detected until now.
2638  * @param[in] action
2639  *   Pointer to the action structure.
2640  * @param[in] attr
2641  *   Pointer to flow attributes.
2642  * @param[out] error
2643  *   Pointer to error structure.
2644  *
2645  * @return
2646  *   0 on success, a negative errno value otherwise and rte_errno is set.
2647  */
2648 static int
2649 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2650                                  uint64_t action_flags,
2651                                  const struct rte_flow_action *action,
2652                                  const struct rte_flow_attr *attr,
2653                                  struct rte_flow_error *error)
2654 {
2655         const struct mlx5_priv *priv = dev->data->dev_private;
2656
2657         if (!(action->conf))
2658                 return rte_flow_error_set(error, EINVAL,
2659                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2660                                           "configuration cannot be null");
2661         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2662                 return rte_flow_error_set(error, EINVAL,
2663                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2664                                           "can only have a single encap action "
2665                                           "in a flow");
2666         if (!attr->transfer && priv->representor)
2667                 return rte_flow_error_set(error, ENOTSUP,
2668                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2669                                           "encap action for VF representor "
2670                                           "not supported on NIC table");
2671         return 0;
2672 }
2673
2674 /**
2675  * Validate a decap action.
2676  *
2677  * @param[in] dev
2678  *   Pointer to the rte_eth_dev structure.
2679  * @param[in] action_flags
2680  *   Holds the actions detected until now.
2681  * @param[in] action
2682  *   Pointer to the action structure.
2683  * @param[in] item_flags
2684  *   Holds the items detected.
2685  * @param[in] attr
2686  *   Pointer to flow attributes
2687  * @param[out] error
2688  *   Pointer to error structure.
2689  *
2690  * @return
2691  *   0 on success, a negative errno value otherwise and rte_errno is set.
2692  */
2693 static int
2694 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2695                               uint64_t action_flags,
2696                               const struct rte_flow_action *action,
2697                               const uint64_t item_flags,
2698                               const struct rte_flow_attr *attr,
2699                               struct rte_flow_error *error)
2700 {
2701         const struct mlx5_priv *priv = dev->data->dev_private;
2702
2703         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2704             !priv->config.decap_en)
2705                 return rte_flow_error_set(error, ENOTSUP,
2706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2707                                           "decap is not enabled");
2708         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2709                 return rte_flow_error_set(error, ENOTSUP,
2710                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711                                           action_flags &
2712                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2713                                           "have a single decap action" : "decap "
2714                                           "after encap is not supported");
2715         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2716                 return rte_flow_error_set(error, EINVAL,
2717                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2718                                           "can't have decap action after"
2719                                           " modify action");
2720         if (attr->egress)
2721                 return rte_flow_error_set(error, ENOTSUP,
2722                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2723                                           NULL,
2724                                           "decap action not supported for "
2725                                           "egress");
2726         if (!attr->transfer && priv->representor)
2727                 return rte_flow_error_set(error, ENOTSUP,
2728                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2729                                           "decap action for VF representor "
2730                                           "not supported on NIC table");
2731         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2732             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2733                 return rte_flow_error_set(error, ENOTSUP,
2734                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2735                                 "VXLAN item should be present for VXLAN decap");
2736         return 0;
2737 }
2738
2739 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2740
2741 /**
2742  * Validate the raw encap and decap actions.
2743  *
2744  * @param[in] dev
2745  *   Pointer to the rte_eth_dev structure.
2746  * @param[in] decap
2747  *   Pointer to the decap action.
2748  * @param[in] encap
2749  *   Pointer to the encap action.
2750  * @param[in] attr
2751  *   Pointer to flow attributes
2752  * @param[in/out] action_flags
2753  *   Holds the actions detected until now.
2754  * @param[out] actions_n
2755  *   pointer to the number of actions counter.
2756  * @param[in] action
2757  *   Pointer to the action structure.
2758  * @param[in] item_flags
2759  *   Holds the items detected.
2760  * @param[out] error
2761  *   Pointer to error structure.
2762  *
2763  * @return
2764  *   0 on success, a negative errno value otherwise and rte_errno is set.
2765  */
2766 static int
2767 flow_dv_validate_action_raw_encap_decap
2768         (struct rte_eth_dev *dev,
2769          const struct rte_flow_action_raw_decap *decap,
2770          const struct rte_flow_action_raw_encap *encap,
2771          const struct rte_flow_attr *attr, uint64_t *action_flags,
2772          int *actions_n, const struct rte_flow_action *action,
2773          uint64_t item_flags, struct rte_flow_error *error)
2774 {
2775         const struct mlx5_priv *priv = dev->data->dev_private;
2776         int ret;
2777
2778         if (encap && (!encap->size || !encap->data))
2779                 return rte_flow_error_set(error, EINVAL,
2780                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2781                                           "raw encap data cannot be empty");
2782         if (decap && encap) {
2783                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2784                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2785                         /* L3 encap. */
2786                         decap = NULL;
2787                 else if (encap->size <=
2788                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2789                            decap->size >
2790                            MLX5_ENCAPSULATION_DECISION_SIZE)
2791                         /* L3 decap. */
2792                         encap = NULL;
2793                 else if (encap->size >
2794                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2795                            decap->size >
2796                            MLX5_ENCAPSULATION_DECISION_SIZE)
2797                         /* 2 L2 actions: encap and decap. */
2798                         ;
2799                 else
2800                         return rte_flow_error_set(error,
2801                                 ENOTSUP,
2802                                 RTE_FLOW_ERROR_TYPE_ACTION,
2803                                 NULL, "unsupported too small "
2804                                 "raw decap and too small raw "
2805                                 "encap combination");
2806         }
2807         if (decap) {
2808                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2809                                                     item_flags, attr, error);
2810                 if (ret < 0)
2811                         return ret;
2812                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2813                 ++(*actions_n);
2814         }
2815         if (encap) {
2816                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2817                         return rte_flow_error_set(error, ENOTSUP,
2818                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2819                                                   NULL,
2820                                                   "small raw encap size");
2821                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2822                         return rte_flow_error_set(error, EINVAL,
2823                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2824                                                   NULL,
2825                                                   "more than one encap action");
2826                 if (!attr->transfer && priv->representor)
2827                         return rte_flow_error_set
2828                                         (error, ENOTSUP,
2829                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2830                                          "encap action for VF representor "
2831                                          "not supported on NIC table");
2832                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2833                 ++(*actions_n);
2834         }
2835         return 0;
2836 }
2837
2838 /**
2839  * Match encap_decap resource.
2840  *
2841  * @param list
2842  *   Pointer to the hash list.
2843  * @param entry
2844  *   Pointer to exist resource entry object.
2845  * @param key
2846  *   Key of the new entry.
2847  * @param ctx_cb
2848  *   Pointer to new encap_decap resource.
2849  *
2850  * @return
2851  *   0 on matching, none-zero otherwise.
2852  */
2853 int
2854 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2855                              struct mlx5_hlist_entry *entry,
2856                              uint64_t key __rte_unused, void *cb_ctx)
2857 {
2858         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2859         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2860         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2861
2862         cache_resource = container_of(entry,
2863                                       struct mlx5_flow_dv_encap_decap_resource,
2864                                       entry);
2865         if (resource->reformat_type == cache_resource->reformat_type &&
2866             resource->ft_type == cache_resource->ft_type &&
2867             resource->flags == cache_resource->flags &&
2868             resource->size == cache_resource->size &&
2869             !memcmp((const void *)resource->buf,
2870                     (const void *)cache_resource->buf,
2871                     resource->size))
2872                 return 0;
2873         return -1;
2874 }
2875
2876 /**
2877  * Allocate encap_decap resource.
2878  *
2879  * @param list
2880  *   Pointer to the hash list.
2881  * @param entry
2882  *   Pointer to exist resource entry object.
2883  * @param ctx_cb
2884  *   Pointer to new encap_decap resource.
2885  *
2886  * @return
2887  *   0 on matching, none-zero otherwise.
2888  */
2889 struct mlx5_hlist_entry *
2890 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2891                               uint64_t key __rte_unused,
2892                               void *cb_ctx)
2893 {
2894         struct mlx5_dev_ctx_shared *sh = list->ctx;
2895         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2896         struct mlx5dv_dr_domain *domain;
2897         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2898         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2899         uint32_t idx;
2900         int ret;
2901
2902         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2903                 domain = sh->fdb_domain;
2904         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2905                 domain = sh->rx_domain;
2906         else
2907                 domain = sh->tx_domain;
2908         /* Register new encap/decap resource. */
2909         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2910                                        &idx);
2911         if (!cache_resource) {
2912                 rte_flow_error_set(ctx->error, ENOMEM,
2913                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914                                    "cannot allocate resource memory");
2915                 return NULL;
2916         }
2917         *cache_resource = *resource;
2918         cache_resource->idx = idx;
2919         ret = mlx5_flow_os_create_flow_action_packet_reformat
2920                                         (sh->ctx, domain, cache_resource,
2921                                          &cache_resource->action);
2922         if (ret) {
2923                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2924                 rte_flow_error_set(ctx->error, ENOMEM,
2925                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2926                                    NULL, "cannot create action");
2927                 return NULL;
2928         }
2929
2930         return &cache_resource->entry;
2931 }
2932
2933 /**
2934  * Find existing encap/decap resource or create and register a new one.
2935  *
2936  * @param[in, out] dev
2937  *   Pointer to rte_eth_dev structure.
2938  * @param[in, out] resource
2939  *   Pointer to encap/decap resource.
2940  * @parm[in, out] dev_flow
2941  *   Pointer to the dev_flow.
2942  * @param[out] error
2943  *   pointer to error structure.
2944  *
2945  * @return
2946  *   0 on success otherwise -errno and errno is set.
2947  */
2948 static int
2949 flow_dv_encap_decap_resource_register
2950                         (struct rte_eth_dev *dev,
2951                          struct mlx5_flow_dv_encap_decap_resource *resource,
2952                          struct mlx5_flow *dev_flow,
2953                          struct rte_flow_error *error)
2954 {
2955         struct mlx5_priv *priv = dev->data->dev_private;
2956         struct mlx5_dev_ctx_shared *sh = priv->sh;
2957         struct mlx5_hlist_entry *entry;
2958         union {
2959                 struct {
2960                         uint32_t ft_type:8;
2961                         uint32_t refmt_type:8;
2962                         /*
2963                          * Header reformat actions can be shared between
2964                          * non-root tables. One bit to indicate non-root
2965                          * table or not.
2966                          */
2967                         uint32_t is_root:1;
2968                         uint32_t reserve:15;
2969                 };
2970                 uint32_t v32;
2971         } encap_decap_key = {
2972                 {
2973                         .ft_type = resource->ft_type,
2974                         .refmt_type = resource->reformat_type,
2975                         .is_root = !!dev_flow->dv.group,
2976                         .reserve = 0,
2977                 }
2978         };
2979         struct mlx5_flow_cb_ctx ctx = {
2980                 .error = error,
2981                 .data = resource,
2982         };
2983         uint64_t key64;
2984
2985         resource->flags = dev_flow->dv.group ? 0 : 1;
2986         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2987                                  sizeof(encap_decap_key.v32), 0);
2988         if (resource->reformat_type !=
2989             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2990             resource->size)
2991                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2992         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2993         if (!entry)
2994                 return -rte_errno;
2995         resource = container_of(entry, typeof(*resource), entry);
2996         dev_flow->dv.encap_decap = resource;
2997         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2998         return 0;
2999 }
3000
3001 /**
3002  * Find existing table jump resource or create and register a new one.
3003  *
3004  * @param[in, out] dev
3005  *   Pointer to rte_eth_dev structure.
3006  * @param[in, out] tbl
3007  *   Pointer to flow table resource.
3008  * @parm[in, out] dev_flow
3009  *   Pointer to the dev_flow.
3010  * @param[out] error
3011  *   pointer to error structure.
3012  *
3013  * @return
3014  *   0 on success otherwise -errno and errno is set.
3015  */
3016 static int
3017 flow_dv_jump_tbl_resource_register
3018                         (struct rte_eth_dev *dev __rte_unused,
3019                          struct mlx5_flow_tbl_resource *tbl,
3020                          struct mlx5_flow *dev_flow,
3021                          struct rte_flow_error *error __rte_unused)
3022 {
3023         struct mlx5_flow_tbl_data_entry *tbl_data =
3024                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3025
3026         MLX5_ASSERT(tbl);
3027         MLX5_ASSERT(tbl_data->jump.action);
3028         dev_flow->handle->rix_jump = tbl_data->idx;
3029         dev_flow->dv.jump = &tbl_data->jump;
3030         return 0;
3031 }
3032
3033 int
3034 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3035                          struct mlx5_cache_entry *entry, void *cb_ctx)
3036 {
3037         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3038         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3039         struct mlx5_flow_dv_port_id_action_resource *res =
3040                         container_of(entry, typeof(*res), entry);
3041
3042         return ref->port_id != res->port_id;
3043 }
3044
3045 struct mlx5_cache_entry *
3046 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3047                           struct mlx5_cache_entry *entry __rte_unused,
3048                           void *cb_ctx)
3049 {
3050         struct mlx5_dev_ctx_shared *sh = list->ctx;
3051         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3052         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3053         struct mlx5_flow_dv_port_id_action_resource *cache;
3054         uint32_t idx;
3055         int ret;
3056
3057         /* Register new port id action resource. */
3058         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3059         if (!cache) {
3060                 rte_flow_error_set(ctx->error, ENOMEM,
3061                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3062                                    "cannot allocate port_id action cache memory");
3063                 return NULL;
3064         }
3065         *cache = *ref;
3066         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3067                                                         ref->port_id,
3068                                                         &cache->action);
3069         if (ret) {
3070                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3071                 rte_flow_error_set(ctx->error, ENOMEM,
3072                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3073                                    "cannot create action");
3074                 return NULL;
3075         }
3076         return &cache->entry;
3077 }
3078
3079 /**
3080  * Find existing table port ID resource or create and register a new one.
3081  *
3082  * @param[in, out] dev
3083  *   Pointer to rte_eth_dev structure.
3084  * @param[in, out] resource
3085  *   Pointer to port ID action resource.
3086  * @parm[in, out] dev_flow
3087  *   Pointer to the dev_flow.
3088  * @param[out] error
3089  *   pointer to error structure.
3090  *
3091  * @return
3092  *   0 on success otherwise -errno and errno is set.
3093  */
3094 static int
3095 flow_dv_port_id_action_resource_register
3096                         (struct rte_eth_dev *dev,
3097                          struct mlx5_flow_dv_port_id_action_resource *resource,
3098                          struct mlx5_flow *dev_flow,
3099                          struct rte_flow_error *error)
3100 {
3101         struct mlx5_priv *priv = dev->data->dev_private;
3102         struct mlx5_cache_entry *entry;
3103         struct mlx5_flow_dv_port_id_action_resource *cache;
3104         struct mlx5_flow_cb_ctx ctx = {
3105                 .error = error,
3106                 .data = resource,
3107         };
3108
3109         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3110         if (!entry)
3111                 return -rte_errno;
3112         cache = container_of(entry, typeof(*cache), entry);
3113         dev_flow->dv.port_id_action = cache;
3114         dev_flow->handle->rix_port_id_action = cache->idx;
3115         return 0;
3116 }
3117
3118 int
3119 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3120                          struct mlx5_cache_entry *entry, void *cb_ctx)
3121 {
3122         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3123         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3124         struct mlx5_flow_dv_push_vlan_action_resource *res =
3125                         container_of(entry, typeof(*res), entry);
3126
3127         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3128 }
3129
3130 struct mlx5_cache_entry *
3131 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3132                           struct mlx5_cache_entry *entry __rte_unused,
3133                           void *cb_ctx)
3134 {
3135         struct mlx5_dev_ctx_shared *sh = list->ctx;
3136         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3137         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3138         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3139         struct mlx5dv_dr_domain *domain;
3140         uint32_t idx;
3141         int ret;
3142
3143         /* Register new port id action resource. */
3144         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3145         if (!cache) {
3146                 rte_flow_error_set(ctx->error, ENOMEM,
3147                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3148                                    "cannot allocate push_vlan action cache memory");
3149                 return NULL;
3150         }
3151         *cache = *ref;
3152         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3153                 domain = sh->fdb_domain;
3154         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3155                 domain = sh->rx_domain;
3156         else
3157                 domain = sh->tx_domain;
3158         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3159                                                         &cache->action);
3160         if (ret) {
3161                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3162                 rte_flow_error_set(ctx->error, ENOMEM,
3163                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3164                                    "cannot create push vlan action");
3165                 return NULL;
3166         }
3167         return &cache->entry;
3168 }
3169
3170 /**
3171  * Find existing push vlan resource or create and register a new one.
3172  *
3173  * @param [in, out] dev
3174  *   Pointer to rte_eth_dev structure.
3175  * @param[in, out] resource
3176  *   Pointer to port ID action resource.
3177  * @parm[in, out] dev_flow
3178  *   Pointer to the dev_flow.
3179  * @param[out] error
3180  *   pointer to error structure.
3181  *
3182  * @return
3183  *   0 on success otherwise -errno and errno is set.
3184  */
3185 static int
3186 flow_dv_push_vlan_action_resource_register
3187                        (struct rte_eth_dev *dev,
3188                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3189                         struct mlx5_flow *dev_flow,
3190                         struct rte_flow_error *error)
3191 {
3192         struct mlx5_priv *priv = dev->data->dev_private;
3193         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3194         struct mlx5_cache_entry *entry;
3195         struct mlx5_flow_cb_ctx ctx = {
3196                 .error = error,
3197                 .data = resource,
3198         };
3199
3200         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3201         if (!entry)
3202                 return -rte_errno;
3203         cache = container_of(entry, typeof(*cache), entry);
3204
3205         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3206         dev_flow->dv.push_vlan_res = cache;
3207         return 0;
3208 }
3209
3210 /**
3211  * Get the size of specific rte_flow_item_type hdr size
3212  *
3213  * @param[in] item_type
3214  *   Tested rte_flow_item_type.
3215  *
3216  * @return
3217  *   sizeof struct item_type, 0 if void or irrelevant.
3218  */
3219 static size_t
3220 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3221 {
3222         size_t retval;
3223
3224         switch (item_type) {
3225         case RTE_FLOW_ITEM_TYPE_ETH:
3226                 retval = sizeof(struct rte_ether_hdr);
3227                 break;
3228         case RTE_FLOW_ITEM_TYPE_VLAN:
3229                 retval = sizeof(struct rte_vlan_hdr);
3230                 break;
3231         case RTE_FLOW_ITEM_TYPE_IPV4:
3232                 retval = sizeof(struct rte_ipv4_hdr);
3233                 break;
3234         case RTE_FLOW_ITEM_TYPE_IPV6:
3235                 retval = sizeof(struct rte_ipv6_hdr);
3236                 break;
3237         case RTE_FLOW_ITEM_TYPE_UDP:
3238                 retval = sizeof(struct rte_udp_hdr);
3239                 break;
3240         case RTE_FLOW_ITEM_TYPE_TCP:
3241                 retval = sizeof(struct rte_tcp_hdr);
3242                 break;
3243         case RTE_FLOW_ITEM_TYPE_VXLAN:
3244         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3245                 retval = sizeof(struct rte_vxlan_hdr);
3246                 break;
3247         case RTE_FLOW_ITEM_TYPE_GRE:
3248         case RTE_FLOW_ITEM_TYPE_NVGRE:
3249                 retval = sizeof(struct rte_gre_hdr);
3250                 break;
3251         case RTE_FLOW_ITEM_TYPE_MPLS:
3252                 retval = sizeof(struct rte_mpls_hdr);
3253                 break;
3254         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3255         default:
3256                 retval = 0;
3257                 break;
3258         }
3259         return retval;
3260 }
3261
3262 #define MLX5_ENCAP_IPV4_VERSION         0x40
3263 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3264 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3265 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3266 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3267 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3268 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3269
3270 /**
3271  * Convert the encap action data from list of rte_flow_item to raw buffer
3272  *
3273  * @param[in] items
3274  *   Pointer to rte_flow_item objects list.
3275  * @param[out] buf
3276  *   Pointer to the output buffer.
3277  * @param[out] size
3278  *   Pointer to the output buffer size.
3279  * @param[out] error
3280  *   Pointer to the error structure.
3281  *
3282  * @return
3283  *   0 on success, a negative errno value otherwise and rte_errno is set.
3284  */
3285 static int
3286 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3287                            size_t *size, struct rte_flow_error *error)
3288 {
3289         struct rte_ether_hdr *eth = NULL;
3290         struct rte_vlan_hdr *vlan = NULL;
3291         struct rte_ipv4_hdr *ipv4 = NULL;
3292         struct rte_ipv6_hdr *ipv6 = NULL;
3293         struct rte_udp_hdr *udp = NULL;
3294         struct rte_vxlan_hdr *vxlan = NULL;
3295         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3296         struct rte_gre_hdr *gre = NULL;
3297         size_t len;
3298         size_t temp_size = 0;
3299
3300         if (!items)
3301                 return rte_flow_error_set(error, EINVAL,
3302                                           RTE_FLOW_ERROR_TYPE_ACTION,
3303                                           NULL, "invalid empty data");
3304         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3305                 len = flow_dv_get_item_hdr_len(items->type);
3306                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3307                         return rte_flow_error_set(error, EINVAL,
3308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3309                                                   (void *)items->type,
3310                                                   "items total size is too big"
3311                                                   " for encap action");
3312                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3313                 switch (items->type) {
3314                 case RTE_FLOW_ITEM_TYPE_ETH:
3315                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3316                         break;
3317                 case RTE_FLOW_ITEM_TYPE_VLAN:
3318                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3319                         if (!eth)
3320                                 return rte_flow_error_set(error, EINVAL,
3321                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3322                                                 (void *)items->type,
3323                                                 "eth header not found");
3324                         if (!eth->ether_type)
3325                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3326                         break;
3327                 case RTE_FLOW_ITEM_TYPE_IPV4:
3328                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3329                         if (!vlan && !eth)
3330                                 return rte_flow_error_set(error, EINVAL,
3331                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3332                                                 (void *)items->type,
3333                                                 "neither eth nor vlan"
3334                                                 " header found");
3335                         if (vlan && !vlan->eth_proto)
3336                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3337                         else if (eth && !eth->ether_type)
3338                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3339                         if (!ipv4->version_ihl)
3340                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3341                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3342                         if (!ipv4->time_to_live)
3343                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3344                         break;
3345                 case RTE_FLOW_ITEM_TYPE_IPV6:
3346                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3347                         if (!vlan && !eth)
3348                                 return rte_flow_error_set(error, EINVAL,
3349                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3350                                                 (void *)items->type,
3351                                                 "neither eth nor vlan"
3352                                                 " header found");
3353                         if (vlan && !vlan->eth_proto)
3354                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3355                         else if (eth && !eth->ether_type)
3356                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3357                         if (!ipv6->vtc_flow)
3358                                 ipv6->vtc_flow =
3359                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3360                         if (!ipv6->hop_limits)
3361                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3362                         break;
3363                 case RTE_FLOW_ITEM_TYPE_UDP:
3364                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3365                         if (!ipv4 && !ipv6)
3366                                 return rte_flow_error_set(error, EINVAL,
3367                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3368                                                 (void *)items->type,
3369                                                 "ip header not found");
3370                         if (ipv4 && !ipv4->next_proto_id)
3371                                 ipv4->next_proto_id = IPPROTO_UDP;
3372                         else if (ipv6 && !ipv6->proto)
3373                                 ipv6->proto = IPPROTO_UDP;
3374                         break;
3375                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3376                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3377                         if (!udp)
3378                                 return rte_flow_error_set(error, EINVAL,
3379                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3380                                                 (void *)items->type,
3381                                                 "udp header not found");
3382                         if (!udp->dst_port)
3383                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3384                         if (!vxlan->vx_flags)
3385                                 vxlan->vx_flags =
3386                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3387                         break;
3388                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3389                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3390                         if (!udp)
3391                                 return rte_flow_error_set(error, EINVAL,
3392                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3393                                                 (void *)items->type,
3394                                                 "udp header not found");
3395                         if (!vxlan_gpe->proto)
3396                                 return rte_flow_error_set(error, EINVAL,
3397                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3398                                                 (void *)items->type,
3399                                                 "next protocol not found");
3400                         if (!udp->dst_port)
3401                                 udp->dst_port =
3402                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3403                         if (!vxlan_gpe->vx_flags)
3404                                 vxlan_gpe->vx_flags =
3405                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3406                         break;
3407                 case RTE_FLOW_ITEM_TYPE_GRE:
3408                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3409                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3410                         if (!gre->proto)
3411                                 return rte_flow_error_set(error, EINVAL,
3412                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3413                                                 (void *)items->type,
3414                                                 "next protocol not found");
3415                         if (!ipv4 && !ipv6)
3416                                 return rte_flow_error_set(error, EINVAL,
3417                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3418                                                 (void *)items->type,
3419                                                 "ip header not found");
3420                         if (ipv4 && !ipv4->next_proto_id)
3421                                 ipv4->next_proto_id = IPPROTO_GRE;
3422                         else if (ipv6 && !ipv6->proto)
3423                                 ipv6->proto = IPPROTO_GRE;
3424                         break;
3425                 case RTE_FLOW_ITEM_TYPE_VOID:
3426                         break;
3427                 default:
3428                         return rte_flow_error_set(error, EINVAL,
3429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3430                                                   (void *)items->type,
3431                                                   "unsupported item type");
3432                         break;
3433                 }
3434                 temp_size += len;
3435         }
3436         *size = temp_size;
3437         return 0;
3438 }
3439
3440 static int
3441 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3442 {
3443         struct rte_ether_hdr *eth = NULL;
3444         struct rte_vlan_hdr *vlan = NULL;
3445         struct rte_ipv6_hdr *ipv6 = NULL;
3446         struct rte_udp_hdr *udp = NULL;
3447         char *next_hdr;
3448         uint16_t proto;
3449
3450         eth = (struct rte_ether_hdr *)data;
3451         next_hdr = (char *)(eth + 1);
3452         proto = RTE_BE16(eth->ether_type);
3453
3454         /* VLAN skipping */
3455         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3456                 vlan = (struct rte_vlan_hdr *)next_hdr;
3457                 proto = RTE_BE16(vlan->eth_proto);
3458                 next_hdr += sizeof(struct rte_vlan_hdr);
3459         }
3460
3461         /* HW calculates IPv4 csum. no need to proceed */
3462         if (proto == RTE_ETHER_TYPE_IPV4)
3463                 return 0;
3464
3465         /* non IPv4/IPv6 header. not supported */
3466         if (proto != RTE_ETHER_TYPE_IPV6) {
3467                 return rte_flow_error_set(error, ENOTSUP,
3468                                           RTE_FLOW_ERROR_TYPE_ACTION,
3469                                           NULL, "Cannot offload non IPv4/IPv6");
3470         }
3471
3472         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3473
3474         /* ignore non UDP */
3475         if (ipv6->proto != IPPROTO_UDP)
3476                 return 0;
3477
3478         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3479         udp->dgram_cksum = 0;
3480
3481         return 0;
3482 }
3483
3484 /**
3485  * Convert L2 encap action to DV specification.
3486  *
3487  * @param[in] dev
3488  *   Pointer to rte_eth_dev structure.
3489  * @param[in] action
3490  *   Pointer to action structure.
3491  * @param[in, out] dev_flow
3492  *   Pointer to the mlx5_flow.
3493  * @param[in] transfer
3494  *   Mark if the flow is E-Switch flow.
3495  * @param[out] error
3496  *   Pointer to the error structure.
3497  *
3498  * @return
3499  *   0 on success, a negative errno value otherwise and rte_errno is set.
3500  */
3501 static int
3502 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3503                                const struct rte_flow_action *action,
3504                                struct mlx5_flow *dev_flow,
3505                                uint8_t transfer,
3506                                struct rte_flow_error *error)
3507 {
3508         const struct rte_flow_item *encap_data;
3509         const struct rte_flow_action_raw_encap *raw_encap_data;
3510         struct mlx5_flow_dv_encap_decap_resource res = {
3511                 .reformat_type =
3512                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3513                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3514                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3515         };
3516
3517         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3518                 raw_encap_data =
3519                         (const struct rte_flow_action_raw_encap *)action->conf;
3520                 res.size = raw_encap_data->size;
3521                 memcpy(res.buf, raw_encap_data->data, res.size);
3522         } else {
3523                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3524                         encap_data =
3525                                 ((const struct rte_flow_action_vxlan_encap *)
3526                                                 action->conf)->definition;
3527                 else
3528                         encap_data =
3529                                 ((const struct rte_flow_action_nvgre_encap *)
3530                                                 action->conf)->definition;
3531                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3532                                                &res.size, error))
3533                         return -rte_errno;
3534         }
3535         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3536                 return -rte_errno;
3537         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3538                 return rte_flow_error_set(error, EINVAL,
3539                                           RTE_FLOW_ERROR_TYPE_ACTION,
3540                                           NULL, "can't create L2 encap action");
3541         return 0;
3542 }
3543
3544 /**
3545  * Convert L2 decap action to DV specification.
3546  *
3547  * @param[in] dev
3548  *   Pointer to rte_eth_dev structure.
3549  * @param[in, out] dev_flow
3550  *   Pointer to the mlx5_flow.
3551  * @param[in] transfer
3552  *   Mark if the flow is E-Switch flow.
3553  * @param[out] error
3554  *   Pointer to the error structure.
3555  *
3556  * @return
3557  *   0 on success, a negative errno value otherwise and rte_errno is set.
3558  */
3559 static int
3560 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3561                                struct mlx5_flow *dev_flow,
3562                                uint8_t transfer,
3563                                struct rte_flow_error *error)
3564 {
3565         struct mlx5_flow_dv_encap_decap_resource res = {
3566                 .size = 0,
3567                 .reformat_type =
3568                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3569                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3570                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3571         };
3572
3573         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3574                 return rte_flow_error_set(error, EINVAL,
3575                                           RTE_FLOW_ERROR_TYPE_ACTION,
3576                                           NULL, "can't create L2 decap action");
3577         return 0;
3578 }
3579
3580 /**
3581  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3582  *
3583  * @param[in] dev
3584  *   Pointer to rte_eth_dev structure.
3585  * @param[in] action
3586  *   Pointer to action structure.
3587  * @param[in, out] dev_flow
3588  *   Pointer to the mlx5_flow.
3589  * @param[in] attr
3590  *   Pointer to the flow attributes.
3591  * @param[out] error
3592  *   Pointer to the error structure.
3593  *
3594  * @return
3595  *   0 on success, a negative errno value otherwise and rte_errno is set.
3596  */
3597 static int
3598 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3599                                 const struct rte_flow_action *action,
3600                                 struct mlx5_flow *dev_flow,
3601                                 const struct rte_flow_attr *attr,
3602                                 struct rte_flow_error *error)
3603 {
3604         const struct rte_flow_action_raw_encap *encap_data;
3605         struct mlx5_flow_dv_encap_decap_resource res;
3606
3607         memset(&res, 0, sizeof(res));
3608         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3609         res.size = encap_data->size;
3610         memcpy(res.buf, encap_data->data, res.size);
3611         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3612                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3613                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3614         if (attr->transfer)
3615                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3616         else
3617                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3618                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3619         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3620                 return rte_flow_error_set(error, EINVAL,
3621                                           RTE_FLOW_ERROR_TYPE_ACTION,
3622                                           NULL, "can't create encap action");
3623         return 0;
3624 }
3625
3626 /**
3627  * Create action push VLAN.
3628  *
3629  * @param[in] dev
3630  *   Pointer to rte_eth_dev structure.
3631  * @param[in] attr
3632  *   Pointer to the flow attributes.
3633  * @param[in] vlan
3634  *   Pointer to the vlan to push to the Ethernet header.
3635  * @param[in, out] dev_flow
3636  *   Pointer to the mlx5_flow.
3637  * @param[out] error
3638  *   Pointer to the error structure.
3639  *
3640  * @return
3641  *   0 on success, a negative errno value otherwise and rte_errno is set.
3642  */
3643 static int
3644 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3645                                 const struct rte_flow_attr *attr,
3646                                 const struct rte_vlan_hdr *vlan,
3647                                 struct mlx5_flow *dev_flow,
3648                                 struct rte_flow_error *error)
3649 {
3650         struct mlx5_flow_dv_push_vlan_action_resource res;
3651
3652         memset(&res, 0, sizeof(res));
3653         res.vlan_tag =
3654                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3655                                  vlan->vlan_tci);
3656         if (attr->transfer)
3657                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3658         else
3659                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3660                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3661         return flow_dv_push_vlan_action_resource_register
3662                                             (dev, &res, dev_flow, error);
3663 }
3664
3665 static int fdb_mirror;
3666
3667 /**
3668  * Validate the modify-header actions.
3669  *
3670  * @param[in] action_flags
3671  *   Holds the actions detected until now.
3672  * @param[in] action
3673  *   Pointer to the modify action.
3674  * @param[out] error
3675  *   Pointer to error structure.
3676  *
3677  * @return
3678  *   0 on success, a negative errno value otherwise and rte_errno is set.
3679  */
3680 static int
3681 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3682                                    const struct rte_flow_action *action,
3683                                    struct rte_flow_error *error)
3684 {
3685         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3686                 return rte_flow_error_set(error, EINVAL,
3687                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3688                                           NULL, "action configuration not set");
3689         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3690                 return rte_flow_error_set(error, EINVAL,
3691                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3692                                           "can't have encap action before"
3693                                           " modify action");
3694         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3695                 return rte_flow_error_set(error, EINVAL,
3696                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697                                           "can't support sample action before"
3698                                           " modify action for E-Switch"
3699                                           " mirroring");
3700         return 0;
3701 }
3702
3703 /**
3704  * Validate the modify-header MAC address actions.
3705  *
3706  * @param[in] action_flags
3707  *   Holds the actions detected until now.
3708  * @param[in] action
3709  *   Pointer to the modify action.
3710  * @param[in] item_flags
3711  *   Holds the items detected.
3712  * @param[out] error
3713  *   Pointer to error structure.
3714  *
3715  * @return
3716  *   0 on success, a negative errno value otherwise and rte_errno is set.
3717  */
3718 static int
3719 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3720                                    const struct rte_flow_action *action,
3721                                    const uint64_t item_flags,
3722                                    struct rte_flow_error *error)
3723 {
3724         int ret = 0;
3725
3726         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3727         if (!ret) {
3728                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3729                         return rte_flow_error_set(error, EINVAL,
3730                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3731                                                   NULL,
3732                                                   "no L2 item in pattern");
3733         }
3734         return ret;
3735 }
3736
3737 /**
3738  * Validate the modify-header IPv4 address actions.
3739  *
3740  * @param[in] action_flags
3741  *   Holds the actions detected until now.
3742  * @param[in] action
3743  *   Pointer to the modify action.
3744  * @param[in] item_flags
3745  *   Holds the items detected.
3746  * @param[out] error
3747  *   Pointer to error structure.
3748  *
3749  * @return
3750  *   0 on success, a negative errno value otherwise and rte_errno is set.
3751  */
3752 static int
3753 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3754                                     const struct rte_flow_action *action,
3755                                     const uint64_t item_flags,
3756                                     struct rte_flow_error *error)
3757 {
3758         int ret = 0;
3759         uint64_t layer;
3760
3761         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3762         if (!ret) {
3763                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3764                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3765                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3766                 if (!(item_flags & layer))
3767                         return rte_flow_error_set(error, EINVAL,
3768                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3769                                                   NULL,
3770                                                   "no ipv4 item in pattern");
3771         }
3772         return ret;
3773 }
3774
3775 /**
3776  * Validate the modify-header IPv6 address actions.
3777  *
3778  * @param[in] action_flags
3779  *   Holds the actions detected until now.
3780  * @param[in] action
3781  *   Pointer to the modify action.
3782  * @param[in] item_flags
3783  *   Holds the items detected.
3784  * @param[out] error
3785  *   Pointer to error structure.
3786  *
3787  * @return
3788  *   0 on success, a negative errno value otherwise and rte_errno is set.
3789  */
3790 static int
3791 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3792                                     const struct rte_flow_action *action,
3793                                     const uint64_t item_flags,
3794                                     struct rte_flow_error *error)
3795 {
3796         int ret = 0;
3797         uint64_t layer;
3798
3799         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3800         if (!ret) {
3801                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3802                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3803                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3804                 if (!(item_flags & layer))
3805                         return rte_flow_error_set(error, EINVAL,
3806                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3807                                                   NULL,
3808                                                   "no ipv6 item in pattern");
3809         }
3810         return ret;
3811 }
3812
3813 /**
3814  * Validate the modify-header TP actions.
3815  *
3816  * @param[in] action_flags
3817  *   Holds the actions detected until now.
3818  * @param[in] action
3819  *   Pointer to the modify action.
3820  * @param[in] item_flags
3821  *   Holds the items detected.
3822  * @param[out] error
3823  *   Pointer to error structure.
3824  *
3825  * @return
3826  *   0 on success, a negative errno value otherwise and rte_errno is set.
3827  */
3828 static int
3829 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3830                                   const struct rte_flow_action *action,
3831                                   const uint64_t item_flags,
3832                                   struct rte_flow_error *error)
3833 {
3834         int ret = 0;
3835         uint64_t layer;
3836
3837         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3838         if (!ret) {
3839                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3840                                  MLX5_FLOW_LAYER_INNER_L4 :
3841                                  MLX5_FLOW_LAYER_OUTER_L4;
3842                 if (!(item_flags & layer))
3843                         return rte_flow_error_set(error, EINVAL,
3844                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3845                                                   NULL, "no transport layer "
3846                                                   "in pattern");
3847         }
3848         return ret;
3849 }
3850
3851 /**
3852  * Validate the modify-header actions of increment/decrement
3853  * TCP Sequence-number.
3854  *
3855  * @param[in] action_flags
3856  *   Holds the actions detected until now.
3857  * @param[in] action
3858  *   Pointer to the modify action.
3859  * @param[in] item_flags
3860  *   Holds the items detected.
3861  * @param[out] error
3862  *   Pointer to error structure.
3863  *
3864  * @return
3865  *   0 on success, a negative errno value otherwise and rte_errno is set.
3866  */
3867 static int
3868 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3869                                        const struct rte_flow_action *action,
3870                                        const uint64_t item_flags,
3871                                        struct rte_flow_error *error)
3872 {
3873         int ret = 0;
3874         uint64_t layer;
3875
3876         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3877         if (!ret) {
3878                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3879                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3880                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3881                 if (!(item_flags & layer))
3882                         return rte_flow_error_set(error, EINVAL,
3883                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3884                                                   NULL, "no TCP item in"
3885                                                   " pattern");
3886                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3887                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3888                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3889                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3890                         return rte_flow_error_set(error, EINVAL,
3891                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3892                                                   NULL,
3893                                                   "cannot decrease and increase"
3894                                                   " TCP sequence number"
3895                                                   " at the same time");
3896         }
3897         return ret;
3898 }
3899
3900 /**
3901  * Validate the modify-header actions of increment/decrement
3902  * TCP Acknowledgment number.
3903  *
3904  * @param[in] action_flags
3905  *   Holds the actions detected until now.
3906  * @param[in] action
3907  *   Pointer to the modify action.
3908  * @param[in] item_flags
3909  *   Holds the items detected.
3910  * @param[out] error
3911  *   Pointer to error structure.
3912  *
3913  * @return
3914  *   0 on success, a negative errno value otherwise and rte_errno is set.
3915  */
3916 static int
3917 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3918                                        const struct rte_flow_action *action,
3919                                        const uint64_t item_flags,
3920                                        struct rte_flow_error *error)
3921 {
3922         int ret = 0;
3923         uint64_t layer;
3924
3925         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3926         if (!ret) {
3927                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3928                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3929                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3930                 if (!(item_flags & layer))
3931                         return rte_flow_error_set(error, EINVAL,
3932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                   NULL, "no TCP item in"
3934                                                   " pattern");
3935                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3936                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3937                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3938                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3939                         return rte_flow_error_set(error, EINVAL,
3940                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3941                                                   NULL,
3942                                                   "cannot decrease and increase"
3943                                                   " TCP acknowledgment number"
3944                                                   " at the same time");
3945         }
3946         return ret;
3947 }
3948
3949 /**
3950  * Validate the modify-header TTL actions.
3951  *
3952  * @param[in] action_flags
3953  *   Holds the actions detected until now.
3954  * @param[in] action
3955  *   Pointer to the modify action.
3956  * @param[in] item_flags
3957  *   Holds the items detected.
3958  * @param[out] error
3959  *   Pointer to error structure.
3960  *
3961  * @return
3962  *   0 on success, a negative errno value otherwise and rte_errno is set.
3963  */
3964 static int
3965 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3966                                    const struct rte_flow_action *action,
3967                                    const uint64_t item_flags,
3968                                    struct rte_flow_error *error)
3969 {
3970         int ret = 0;
3971         uint64_t layer;
3972
3973         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3974         if (!ret) {
3975                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3976                                  MLX5_FLOW_LAYER_INNER_L3 :
3977                                  MLX5_FLOW_LAYER_OUTER_L3;
3978                 if (!(item_flags & layer))
3979                         return rte_flow_error_set(error, EINVAL,
3980                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3981                                                   NULL,
3982                                                   "no IP protocol in pattern");
3983         }
3984         return ret;
3985 }
3986
3987 /**
3988  * Validate jump action.
3989  *
3990  * @param[in] action
3991  *   Pointer to the jump action.
3992  * @param[in] action_flags
3993  *   Holds the actions detected until now.
3994  * @param[in] attributes
3995  *   Pointer to flow attributes
3996  * @param[in] external
3997  *   Action belongs to flow rule created by request external to PMD.
3998  * @param[out] error
3999  *   Pointer to error structure.
4000  *
4001  * @return
4002  *   0 on success, a negative errno value otherwise and rte_errno is set.
4003  */
4004 static int
4005 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4006                              const struct mlx5_flow_tunnel *tunnel,
4007                              const struct rte_flow_action *action,
4008                              uint64_t action_flags,
4009                              const struct rte_flow_attr *attributes,
4010                              bool external, struct rte_flow_error *error)
4011 {
4012         uint32_t target_group, table;
4013         int ret = 0;
4014         struct flow_grp_info grp_info = {
4015                 .external = !!external,
4016                 .transfer = !!attributes->transfer,
4017                 .fdb_def_rule = 1,
4018                 .std_tbl_fix = 0
4019         };
4020         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4021                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4022                 return rte_flow_error_set(error, EINVAL,
4023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4024                                           "can't have 2 fate actions in"
4025                                           " same flow");
4026         if (action_flags & MLX5_FLOW_ACTION_METER)
4027                 return rte_flow_error_set(error, ENOTSUP,
4028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4029                                           "jump with meter not support");
4030         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
4031                 return rte_flow_error_set(error, EINVAL,
4032                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4033                                           "E-Switch mirroring can't support"
4034                                           " Sample action and jump action in"
4035                                           " same flow now");
4036         if (!action->conf)
4037                 return rte_flow_error_set(error, EINVAL,
4038                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4039                                           NULL, "action configuration not set");
4040         target_group =
4041                 ((const struct rte_flow_action_jump *)action->conf)->group;
4042         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4043                                        &grp_info, error);
4044         if (ret)
4045                 return ret;
4046         if (attributes->group == target_group &&
4047             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4048                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4049                 return rte_flow_error_set(error, EINVAL,
4050                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4051                                           "target group must be other than"
4052                                           " the current flow group");
4053         return 0;
4054 }
4055
4056 /*
4057  * Validate the port_id action.
4058  *
4059  * @param[in] dev
4060  *   Pointer to rte_eth_dev structure.
4061  * @param[in] action_flags
4062  *   Bit-fields that holds the actions detected until now.
4063  * @param[in] action
4064  *   Port_id RTE action structure.
4065  * @param[in] attr
4066  *   Attributes of flow that includes this action.
4067  * @param[out] error
4068  *   Pointer to error structure.
4069  *
4070  * @return
4071  *   0 on success, a negative errno value otherwise and rte_errno is set.
4072  */
4073 static int
4074 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4075                                 uint64_t action_flags,
4076                                 const struct rte_flow_action *action,
4077                                 const struct rte_flow_attr *attr,
4078                                 struct rte_flow_error *error)
4079 {
4080         const struct rte_flow_action_port_id *port_id;
4081         struct mlx5_priv *act_priv;
4082         struct mlx5_priv *dev_priv;
4083         uint16_t port;
4084
4085         if (!attr->transfer)
4086                 return rte_flow_error_set(error, ENOTSUP,
4087                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4088                                           NULL,
4089                                           "port id action is valid in transfer"
4090                                           " mode only");
4091         if (!action || !action->conf)
4092                 return rte_flow_error_set(error, ENOTSUP,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4094                                           NULL,
4095                                           "port id action parameters must be"
4096                                           " specified");
4097         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4098                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4099                 return rte_flow_error_set(error, EINVAL,
4100                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4101                                           "can have only one fate actions in"
4102                                           " a flow");
4103         dev_priv = mlx5_dev_to_eswitch_info(dev);
4104         if (!dev_priv)
4105                 return rte_flow_error_set(error, rte_errno,
4106                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4107                                           NULL,
4108                                           "failed to obtain E-Switch info");
4109         port_id = action->conf;
4110         port = port_id->original ? dev->data->port_id : port_id->id;
4111         act_priv = mlx5_port_to_eswitch_info(port, false);
4112         if (!act_priv)
4113                 return rte_flow_error_set
4114                                 (error, rte_errno,
4115                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4116                                  "failed to obtain E-Switch port id for port");
4117         if (act_priv->domain_id != dev_priv->domain_id)
4118                 return rte_flow_error_set
4119                                 (error, EINVAL,
4120                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4121                                  "port does not belong to"
4122                                  " E-Switch being configured");
4123         return 0;
4124 }
4125
4126 /**
4127  * Get the maximum number of modify header actions.
4128  *
4129  * @param dev
4130  *   Pointer to rte_eth_dev structure.
4131  * @param flags
4132  *   Flags bits to check if root level.
4133  *
4134  * @return
4135  *   Max number of modify header actions device can support.
4136  */
4137 static inline unsigned int
4138 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4139                               uint64_t flags)
4140 {
4141         /*
4142          * There's no way to directly query the max capacity from FW.
4143          * The maximal value on root table should be assumed to be supported.
4144          */
4145         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4146                 return MLX5_MAX_MODIFY_NUM;
4147         else
4148                 return MLX5_ROOT_TBL_MODIFY_NUM;
4149 }
4150
4151 /**
4152  * Validate the meter action.
4153  *
4154  * @param[in] dev
4155  *   Pointer to rte_eth_dev structure.
4156  * @param[in] action_flags
4157  *   Bit-fields that holds the actions detected until now.
4158  * @param[in] action
4159  *   Pointer to the meter action.
4160  * @param[in] attr
4161  *   Attributes of flow that includes this action.
4162  * @param[out] error
4163  *   Pointer to error structure.
4164  *
4165  * @return
4166  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4167  */
4168 static int
4169 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4170                                 uint64_t action_flags,
4171                                 const struct rte_flow_action *action,
4172                                 const struct rte_flow_attr *attr,
4173                                 struct rte_flow_error *error)
4174 {
4175         struct mlx5_priv *priv = dev->data->dev_private;
4176         const struct rte_flow_action_meter *am = action->conf;
4177         struct mlx5_flow_meter *fm;
4178
4179         if (!am)
4180                 return rte_flow_error_set(error, EINVAL,
4181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182                                           "meter action conf is NULL");
4183
4184         if (action_flags & MLX5_FLOW_ACTION_METER)
4185                 return rte_flow_error_set(error, ENOTSUP,
4186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4187                                           "meter chaining not support");
4188         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4189                 return rte_flow_error_set(error, ENOTSUP,
4190                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4191                                           "meter with jump not support");
4192         if (!priv->mtr_en)
4193                 return rte_flow_error_set(error, ENOTSUP,
4194                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4195                                           NULL,
4196                                           "meter action not supported");
4197         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4198         if (!fm)
4199                 return rte_flow_error_set(error, EINVAL,
4200                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4201                                           "Meter not found");
4202         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4203               (!fm->ingress && !attr->ingress && attr->egress) ||
4204               (!fm->egress && !attr->egress && attr->ingress))))
4205                 return rte_flow_error_set(error, EINVAL,
4206                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4207                                           "Flow attributes are either invalid "
4208                                           "or have a conflict with current "
4209                                           "meter attributes");
4210         return 0;
4211 }
4212
4213 /**
4214  * Validate the age action.
4215  *
4216  * @param[in] action_flags
4217  *   Holds the actions detected until now.
4218  * @param[in] action
4219  *   Pointer to the age action.
4220  * @param[in] dev
4221  *   Pointer to the Ethernet device structure.
4222  * @param[out] error
4223  *   Pointer to error structure.
4224  *
4225  * @return
4226  *   0 on success, a negative errno value otherwise and rte_errno is set.
4227  */
4228 static int
4229 flow_dv_validate_action_age(uint64_t action_flags,
4230                             const struct rte_flow_action *action,
4231                             struct rte_eth_dev *dev,
4232                             struct rte_flow_error *error)
4233 {
4234         struct mlx5_priv *priv = dev->data->dev_private;
4235         const struct rte_flow_action_age *age = action->conf;
4236
4237         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4238             !priv->sh->aso_age_mng))
4239                 return rte_flow_error_set(error, ENOTSUP,
4240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4241                                           NULL,
4242                                           "age action not supported");
4243         if (!(action->conf))
4244                 return rte_flow_error_set(error, EINVAL,
4245                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4246                                           "configuration cannot be null");
4247         if (!(age->timeout))
4248                 return rte_flow_error_set(error, EINVAL,
4249                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4250                                           "invalid timeout value 0");
4251         if (action_flags & MLX5_FLOW_ACTION_AGE)
4252                 return rte_flow_error_set(error, EINVAL,
4253                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4254                                           "duplicate age actions set");
4255         return 0;
4256 }
4257
4258 /**
4259  * Validate the modify-header IPv4 DSCP actions.
4260  *
4261  * @param[in] action_flags
4262  *   Holds the actions detected until now.
4263  * @param[in] action
4264  *   Pointer to the modify action.
4265  * @param[in] item_flags
4266  *   Holds the items detected.
4267  * @param[out] error
4268  *   Pointer to error structure.
4269  *
4270  * @return
4271  *   0 on success, a negative errno value otherwise and rte_errno is set.
4272  */
4273 static int
4274 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4275                                          const struct rte_flow_action *action,
4276                                          const uint64_t item_flags,
4277                                          struct rte_flow_error *error)
4278 {
4279         int ret = 0;
4280
4281         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4282         if (!ret) {
4283                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4284                         return rte_flow_error_set(error, EINVAL,
4285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4286                                                   NULL,
4287                                                   "no ipv4 item in pattern");
4288         }
4289         return ret;
4290 }
4291
4292 /**
4293  * Validate the modify-header IPv6 DSCP actions.
4294  *
4295  * @param[in] action_flags
4296  *   Holds the actions detected until now.
4297  * @param[in] action
4298  *   Pointer to the modify action.
4299  * @param[in] item_flags
4300  *   Holds the items detected.
4301  * @param[out] error
4302  *   Pointer to error structure.
4303  *
4304  * @return
4305  *   0 on success, a negative errno value otherwise and rte_errno is set.
4306  */
4307 static int
4308 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4309                                          const struct rte_flow_action *action,
4310                                          const uint64_t item_flags,
4311                                          struct rte_flow_error *error)
4312 {
4313         int ret = 0;
4314
4315         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4316         if (!ret) {
4317                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4318                         return rte_flow_error_set(error, EINVAL,
4319                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4320                                                   NULL,
4321                                                   "no ipv6 item in pattern");
4322         }
4323         return ret;
4324 }
4325
4326 /**
4327  * Match modify-header resource.
4328  *
4329  * @param list
4330  *   Pointer to the hash list.
4331  * @param entry
4332  *   Pointer to exist resource entry object.
4333  * @param key
4334  *   Key of the new entry.
4335  * @param ctx
4336  *   Pointer to new modify-header resource.
4337  *
4338  * @return
4339  *   0 on matching, non-zero otherwise.
4340  */
4341 int
4342 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4343                         struct mlx5_hlist_entry *entry,
4344                         uint64_t key __rte_unused, void *cb_ctx)
4345 {
4346         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4347         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4348         struct mlx5_flow_dv_modify_hdr_resource *resource =
4349                         container_of(entry, typeof(*resource), entry);
4350         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4351
4352         key_len += ref->actions_num * sizeof(ref->actions[0]);
4353         return ref->actions_num != resource->actions_num ||
4354                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4355 }
4356
4357 struct mlx5_hlist_entry *
4358 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4359                          void *cb_ctx)
4360 {
4361         struct mlx5_dev_ctx_shared *sh = list->ctx;
4362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4363         struct mlx5dv_dr_domain *ns;
4364         struct mlx5_flow_dv_modify_hdr_resource *entry;
4365         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4366         int ret;
4367         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4368         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4369
4370         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4371                             SOCKET_ID_ANY);
4372         if (!entry) {
4373                 rte_flow_error_set(ctx->error, ENOMEM,
4374                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4375                                    "cannot allocate resource memory");
4376                 return NULL;
4377         }
4378         rte_memcpy(&entry->ft_type,
4379                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4380                    key_len + data_len);
4381         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4382                 ns = sh->fdb_domain;
4383         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4384                 ns = sh->tx_domain;
4385         else
4386                 ns = sh->rx_domain;
4387         ret = mlx5_flow_os_create_flow_action_modify_header
4388                                         (sh->ctx, ns, entry,
4389                                          data_len, &entry->action);
4390         if (ret) {
4391                 mlx5_free(entry);
4392                 rte_flow_error_set(ctx->error, ENOMEM,
4393                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4394                                    NULL, "cannot create modification action");
4395                 return NULL;
4396         }
4397         return &entry->entry;
4398 }
4399
4400 /**
4401  * Validate the sample action.
4402  *
4403  * @param[in] action_flags
4404  *   Holds the actions detected until now.
4405  * @param[in] action
4406  *   Pointer to the sample action.
4407  * @param[in] dev
4408  *   Pointer to the Ethernet device structure.
4409  * @param[in] attr
4410  *   Attributes of flow that includes this action.
4411  * @param[in] item_flags
4412  *   Holds the items detected.
4413  * @param[out] error
4414  *   Pointer to error structure.
4415  *
4416  * @return
4417  *   0 on success, a negative errno value otherwise and rte_errno is set.
4418  */
4419 static int
4420 flow_dv_validate_action_sample(uint64_t action_flags,
4421                                const struct rte_flow_action *action,
4422                                struct rte_eth_dev *dev,
4423                                const struct rte_flow_attr *attr,
4424                                const uint64_t item_flags,
4425                                struct rte_flow_error *error)
4426 {
4427         struct mlx5_priv *priv = dev->data->dev_private;
4428         struct mlx5_dev_config *dev_conf = &priv->config;
4429         const struct rte_flow_action_sample *sample = action->conf;
4430         const struct rte_flow_action *act;
4431         uint64_t sub_action_flags = 0;
4432         uint16_t queue_index = 0xFFFF;
4433         int actions_n = 0;
4434         int ret;
4435         fdb_mirror = 0;
4436
4437         if (!sample)
4438                 return rte_flow_error_set(error, EINVAL,
4439                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4440                                           "configuration cannot be NULL");
4441         if (sample->ratio == 0)
4442                 return rte_flow_error_set(error, EINVAL,
4443                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4444                                           "ratio value starts from 1");
4445         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446                 return rte_flow_error_set(error, ENOTSUP,
4447                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4448                                           NULL,
4449                                           "sample action not supported");
4450         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451                 return rte_flow_error_set(error, EINVAL,
4452                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453                                           "Multiple sample actions not "
4454                                           "supported");
4455         if (action_flags & MLX5_FLOW_ACTION_METER)
4456                 return rte_flow_error_set(error, EINVAL,
4457                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4458                                           "wrong action order, meter should "
4459                                           "be after sample action");
4460         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461                 return rte_flow_error_set(error, EINVAL,
4462                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4463                                           "wrong action order, jump should "
4464                                           "be after sample action");
4465         act = sample->actions;
4466         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468                         return rte_flow_error_set(error, ENOTSUP,
4469                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4470                                                   act, "too many actions");
4471                 switch (act->type) {
4472                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473                         ret = mlx5_flow_validate_action_queue(act,
4474                                                               sub_action_flags,
4475                                                               dev,
4476                                                               attr, error);
4477                         if (ret < 0)
4478                                 return ret;
4479                         queue_index = ((const struct rte_flow_action_queue *)
4480                                                         (act->conf))->index;
4481                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4482                         ++actions_n;
4483                         break;
4484                 case RTE_FLOW_ACTION_TYPE_MARK:
4485                         ret = flow_dv_validate_action_mark(dev, act,
4486                                                            sub_action_flags,
4487                                                            attr, error);
4488                         if (ret < 0)
4489                                 return ret;
4490                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4491                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4492                                                 MLX5_FLOW_ACTION_MARK_EXT;
4493                         else
4494                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4495                         ++actions_n;
4496                         break;
4497                 case RTE_FLOW_ACTION_TYPE_COUNT:
4498                         ret = flow_dv_validate_action_count(dev, error);
4499                         if (ret < 0)
4500                                 return ret;
4501                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4502                         ++actions_n;
4503                         break;
4504                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4505                         ret = flow_dv_validate_action_port_id(dev,
4506                                                               sub_action_flags,
4507                                                               act,
4508                                                               attr,
4509                                                               error);
4510                         if (ret)
4511                                 return ret;
4512                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4513                         ++actions_n;
4514                         break;
4515                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4516                         ret = flow_dv_validate_action_raw_encap_decap
4517                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4518                                  &actions_n, action, item_flags, error);
4519                         if (ret < 0)
4520                                 return ret;
4521                         ++actions_n;
4522                         break;
4523                 default:
4524                         return rte_flow_error_set(error, ENOTSUP,
4525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4526                                                   NULL,
4527                                                   "Doesn't support optional "
4528                                                   "action");
4529                 }
4530         }
4531         if (attr->ingress && !attr->transfer) {
4532                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4533                         return rte_flow_error_set(error, EINVAL,
4534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4535                                                   NULL,
4536                                                   "Ingress must has a dest "
4537                                                   "QUEUE for Sample");
4538         } else if (attr->egress && !attr->transfer) {
4539                 return rte_flow_error_set(error, ENOTSUP,
4540                                           RTE_FLOW_ERROR_TYPE_ACTION,
4541                                           NULL,
4542                                           "Sample Only support Ingress "
4543                                           "or E-Switch");
4544         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4545                 MLX5_ASSERT(attr->transfer);
4546                 if (sample->ratio > 1)
4547                         return rte_flow_error_set(error, ENOTSUP,
4548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4549                                                   NULL,
4550                                                   "E-Switch doesn't support "
4551                                                   "any optional action "
4552                                                   "for sampling");
4553                 fdb_mirror = 1;
4554                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4555                         return rte_flow_error_set(error, ENOTSUP,
4556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4557                                                   NULL,
4558                                                   "unsupported action QUEUE");
4559                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4560                         return rte_flow_error_set(error, EINVAL,
4561                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4562                                                   NULL,
4563                                                   "E-Switch must has a dest "
4564                                                   "port for mirroring");
4565         }
4566         /* Continue validation for Xcap actions.*/
4567         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4568             (queue_index == 0xFFFF ||
4569              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4570                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4571                      MLX5_FLOW_XCAP_ACTIONS)
4572                         return rte_flow_error_set(error, ENOTSUP,
4573                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4574                                                   NULL, "encap and decap "
4575                                                   "combination aren't "
4576                                                   "supported");
4577                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4578                                                         MLX5_FLOW_ACTION_ENCAP))
4579                         return rte_flow_error_set(error, ENOTSUP,
4580                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4581                                                   NULL, "encap is not supported"
4582                                                   " for ingress traffic");
4583         }
4584         return 0;
4585 }
4586
4587 /**
4588  * Find existing modify-header resource or create and register a new one.
4589  *
4590  * @param dev[in, out]
4591  *   Pointer to rte_eth_dev structure.
4592  * @param[in, out] resource
4593  *   Pointer to modify-header resource.
4594  * @parm[in, out] dev_flow
4595  *   Pointer to the dev_flow.
4596  * @param[out] error
4597  *   pointer to error structure.
4598  *
4599  * @return
4600  *   0 on success otherwise -errno and errno is set.
4601  */
4602 static int
4603 flow_dv_modify_hdr_resource_register
4604                         (struct rte_eth_dev *dev,
4605                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4606                          struct mlx5_flow *dev_flow,
4607                          struct rte_flow_error *error)
4608 {
4609         struct mlx5_priv *priv = dev->data->dev_private;
4610         struct mlx5_dev_ctx_shared *sh = priv->sh;
4611         uint32_t key_len = sizeof(*resource) -
4612                            offsetof(typeof(*resource), ft_type) +
4613                            resource->actions_num * sizeof(resource->actions[0]);
4614         struct mlx5_hlist_entry *entry;
4615         struct mlx5_flow_cb_ctx ctx = {
4616                 .error = error,
4617                 .data = resource,
4618         };
4619         uint64_t key64;
4620
4621         resource->flags = dev_flow->dv.group ? 0 :
4622                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4623         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4624                                     resource->flags))
4625                 return rte_flow_error_set(error, EOVERFLOW,
4626                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4627                                           "too many modify header items");
4628         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4629         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4630         if (!entry)
4631                 return -rte_errno;
4632         resource = container_of(entry, typeof(*resource), entry);
4633         dev_flow->handle->dvh.modify_hdr = resource;
4634         return 0;
4635 }
4636
4637 /**
4638  * Get DV flow counter by index.
4639  *
4640  * @param[in] dev
4641  *   Pointer to the Ethernet device structure.
4642  * @param[in] idx
4643  *   mlx5 flow counter index in the container.
4644  * @param[out] ppool
4645  *   mlx5 flow counter pool in the container,
4646  *
4647  * @return
4648  *   Pointer to the counter, NULL otherwise.
4649  */
4650 static struct mlx5_flow_counter *
4651 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4652                            uint32_t idx,
4653                            struct mlx5_flow_counter_pool **ppool)
4654 {
4655         struct mlx5_priv *priv = dev->data->dev_private;
4656         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4657         struct mlx5_flow_counter_pool *pool;
4658
4659         /* Decrease to original index and clear shared bit. */
4660         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4661         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4662         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4663         MLX5_ASSERT(pool);
4664         if (ppool)
4665                 *ppool = pool;
4666         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4667 }
4668
4669 /**
4670  * Check the devx counter belongs to the pool.
4671  *
4672  * @param[in] pool
4673  *   Pointer to the counter pool.
4674  * @param[in] id
4675  *   The counter devx ID.
4676  *
4677  * @return
4678  *   True if counter belongs to the pool, false otherwise.
4679  */
4680 static bool
4681 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4682 {
4683         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4684                    MLX5_COUNTERS_PER_POOL;
4685
4686         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4687                 return true;
4688         return false;
4689 }
4690
4691 /**
4692  * Get a pool by devx counter ID.
4693  *
4694  * @param[in] cmng
4695  *   Pointer to the counter management.
4696  * @param[in] id
4697  *   The counter devx ID.
4698  *
4699  * @return
4700  *   The counter pool pointer if exists, NULL otherwise,
4701  */
4702 static struct mlx5_flow_counter_pool *
4703 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4704 {
4705         uint32_t i;
4706         struct mlx5_flow_counter_pool *pool = NULL;
4707
4708         rte_spinlock_lock(&cmng->pool_update_sl);
4709         /* Check last used pool. */
4710         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4711             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4712                 pool = cmng->pools[cmng->last_pool_idx];
4713                 goto out;
4714         }
4715         /* ID out of range means no suitable pool in the container. */
4716         if (id > cmng->max_id || id < cmng->min_id)
4717                 goto out;
4718         /*
4719          * Find the pool from the end of the container, since mostly counter
4720          * ID is sequence increasing, and the last pool should be the needed
4721          * one.
4722          */
4723         i = cmng->n_valid;
4724         while (i--) {
4725                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4726
4727                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4728                         pool = pool_tmp;
4729                         break;
4730                 }
4731         }
4732 out:
4733         rte_spinlock_unlock(&cmng->pool_update_sl);
4734         return pool;
4735 }
4736
4737 /**
4738  * Resize a counter container.
4739  *
4740  * @param[in] dev
4741  *   Pointer to the Ethernet device structure.
4742  *
4743  * @return
4744  *   0 on success, otherwise negative errno value and rte_errno is set.
4745  */
4746 static int
4747 flow_dv_container_resize(struct rte_eth_dev *dev)
4748 {
4749         struct mlx5_priv *priv = dev->data->dev_private;
4750         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4751         void *old_pools = cmng->pools;
4752         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4753         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4754         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4755
4756         if (!pools) {
4757                 rte_errno = ENOMEM;
4758                 return -ENOMEM;
4759         }
4760         if (old_pools)
4761                 memcpy(pools, old_pools, cmng->n *
4762                                        sizeof(struct mlx5_flow_counter_pool *));
4763         cmng->n = resize;
4764         cmng->pools = pools;
4765         if (old_pools)
4766                 mlx5_free(old_pools);
4767         return 0;
4768 }
4769
4770 /**
4771  * Query a devx flow counter.
4772  *
4773  * @param[in] dev
4774  *   Pointer to the Ethernet device structure.
4775  * @param[in] cnt
4776  *   Index to the flow counter.
4777  * @param[out] pkts
4778  *   The statistics value of packets.
4779  * @param[out] bytes
4780  *   The statistics value of bytes.
4781  *
4782  * @return
4783  *   0 on success, otherwise a negative errno value and rte_errno is set.
4784  */
4785 static inline int
4786 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4787                      uint64_t *bytes)
4788 {
4789         struct mlx5_priv *priv = dev->data->dev_private;
4790         struct mlx5_flow_counter_pool *pool = NULL;
4791         struct mlx5_flow_counter *cnt;
4792         int offset;
4793
4794         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4795         MLX5_ASSERT(pool);
4796         if (priv->sh->cmng.counter_fallback)
4797                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4798                                         0, pkts, bytes, 0, NULL, NULL, 0);
4799         rte_spinlock_lock(&pool->sl);
4800         if (!pool->raw) {
4801                 *pkts = 0;
4802                 *bytes = 0;
4803         } else {
4804                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4805                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4806                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4807         }
4808         rte_spinlock_unlock(&pool->sl);
4809         return 0;
4810 }
4811
4812 /**
4813  * Create and initialize a new counter pool.
4814  *
4815  * @param[in] dev
4816  *   Pointer to the Ethernet device structure.
4817  * @param[out] dcs
4818  *   The devX counter handle.
4819  * @param[in] age
4820  *   Whether the pool is for counter that was allocated for aging.
4821  * @param[in/out] cont_cur
4822  *   Pointer to the container pointer, it will be update in pool resize.
4823  *
4824  * @return
4825  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4826  */
4827 static struct mlx5_flow_counter_pool *
4828 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4829                     uint32_t age)
4830 {
4831         struct mlx5_priv *priv = dev->data->dev_private;
4832         struct mlx5_flow_counter_pool *pool;
4833         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4834         bool fallback = priv->sh->cmng.counter_fallback;
4835         uint32_t size = sizeof(*pool);
4836
4837         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4838         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4839         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4840         if (!pool) {
4841                 rte_errno = ENOMEM;
4842                 return NULL;
4843         }
4844         pool->raw = NULL;
4845         pool->is_aged = !!age;
4846         pool->query_gen = 0;
4847         pool->min_dcs = dcs;
4848         rte_spinlock_init(&pool->sl);
4849         rte_spinlock_init(&pool->csl);
4850         TAILQ_INIT(&pool->counters[0]);
4851         TAILQ_INIT(&pool->counters[1]);
4852         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4853         rte_spinlock_lock(&cmng->pool_update_sl);
4854         pool->index = cmng->n_valid;
4855         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4856                 mlx5_free(pool);
4857                 rte_spinlock_unlock(&cmng->pool_update_sl);
4858                 return NULL;
4859         }
4860         cmng->pools[pool->index] = pool;
4861         cmng->n_valid++;
4862         if (unlikely(fallback)) {
4863                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4864
4865                 if (base < cmng->min_id)
4866                         cmng->min_id = base;
4867                 if (base > cmng->max_id)
4868                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4869                 cmng->last_pool_idx = pool->index;
4870         }
4871         rte_spinlock_unlock(&cmng->pool_update_sl);
4872         return pool;
4873 }
4874
4875 /**
4876  * Prepare a new counter and/or a new counter pool.
4877  *
4878  * @param[in] dev
4879  *   Pointer to the Ethernet device structure.
4880  * @param[out] cnt_free
4881  *   Where to put the pointer of a new counter.
4882  * @param[in] age
4883  *   Whether the pool is for counter that was allocated for aging.
4884  *
4885  * @return
4886  *   The counter pool pointer and @p cnt_free is set on success,
4887  *   NULL otherwise and rte_errno is set.
4888  */
4889 static struct mlx5_flow_counter_pool *
4890 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4891                              struct mlx5_flow_counter **cnt_free,
4892                              uint32_t age)
4893 {
4894         struct mlx5_priv *priv = dev->data->dev_private;
4895         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4896         struct mlx5_flow_counter_pool *pool;
4897         struct mlx5_counters tmp_tq;
4898         struct mlx5_devx_obj *dcs = NULL;
4899         struct mlx5_flow_counter *cnt;
4900         enum mlx5_counter_type cnt_type =
4901                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4902         bool fallback = priv->sh->cmng.counter_fallback;
4903         uint32_t i;
4904
4905         if (fallback) {
4906                 /* bulk_bitmap must be 0 for single counter allocation. */
4907                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4908                 if (!dcs)
4909                         return NULL;
4910                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4911                 if (!pool) {
4912                         pool = flow_dv_pool_create(dev, dcs, age);
4913                         if (!pool) {
4914                                 mlx5_devx_cmd_destroy(dcs);
4915                                 return NULL;
4916                         }
4917                 }
4918                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4919                 cnt = MLX5_POOL_GET_CNT(pool, i);
4920                 cnt->pool = pool;
4921                 cnt->dcs_when_free = dcs;
4922                 *cnt_free = cnt;
4923                 return pool;
4924         }
4925         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4926         if (!dcs) {
4927                 rte_errno = ENODATA;
4928                 return NULL;
4929         }
4930         pool = flow_dv_pool_create(dev, dcs, age);
4931         if (!pool) {
4932                 mlx5_devx_cmd_destroy(dcs);
4933                 return NULL;
4934         }
4935         TAILQ_INIT(&tmp_tq);
4936         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4937                 cnt = MLX5_POOL_GET_CNT(pool, i);
4938                 cnt->pool = pool;
4939                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4940         }
4941         rte_spinlock_lock(&cmng->csl[cnt_type]);
4942         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4943         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4944         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4945         (*cnt_free)->pool = pool;
4946         return pool;
4947 }
4948
4949 /**
4950  * Allocate a flow counter.
4951  *
4952  * @param[in] dev
4953  *   Pointer to the Ethernet device structure.
4954  * @param[in] age
4955  *   Whether the counter was allocated for aging.
4956  *
4957  * @return
4958  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4959  */
4960 static uint32_t
4961 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4962 {
4963         struct mlx5_priv *priv = dev->data->dev_private;
4964         struct mlx5_flow_counter_pool *pool = NULL;
4965         struct mlx5_flow_counter *cnt_free = NULL;
4966         bool fallback = priv->sh->cmng.counter_fallback;
4967         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4968         enum mlx5_counter_type cnt_type =
4969                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4970         uint32_t cnt_idx;
4971
4972         if (!priv->config.devx) {
4973                 rte_errno = ENOTSUP;
4974                 return 0;
4975         }
4976         /* Get free counters from container. */
4977         rte_spinlock_lock(&cmng->csl[cnt_type]);
4978         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4979         if (cnt_free)
4980                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4981         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4982         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4983                 goto err;
4984         pool = cnt_free->pool;
4985         if (fallback)
4986                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4987         /* Create a DV counter action only in the first time usage. */
4988         if (!cnt_free->action) {
4989                 uint16_t offset;
4990                 struct mlx5_devx_obj *dcs;
4991                 int ret;
4992
4993                 if (!fallback) {
4994                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4995                         dcs = pool->min_dcs;
4996                 } else {
4997                         offset = 0;
4998                         dcs = cnt_free->dcs_when_free;
4999                 }
5000                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5001                                                             &cnt_free->action);
5002                 if (ret) {
5003                         rte_errno = errno;
5004                         goto err;
5005                 }
5006         }
5007         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5008                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5009         /* Update the counter reset values. */
5010         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5011                                  &cnt_free->bytes))
5012                 goto err;
5013         if (!fallback && !priv->sh->cmng.query_thread_on)
5014                 /* Start the asynchronous batch query by the host thread. */
5015                 mlx5_set_query_alarm(priv->sh);
5016         return cnt_idx;
5017 err:
5018         if (cnt_free) {
5019                 cnt_free->pool = pool;
5020                 if (fallback)
5021                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5022                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5023                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5024                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5025         }
5026         return 0;
5027 }
5028
5029 /**
5030  * Allocate a shared flow counter.
5031  *
5032  * @param[in] ctx
5033  *   Pointer to the shared counter configuration.
5034  * @param[in] data
5035  *   Pointer to save the allocated counter index.
5036  *
5037  * @return
5038  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5039  */
5040
5041 static int32_t
5042 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5043 {
5044         struct mlx5_shared_counter_conf *conf = ctx;
5045         struct rte_eth_dev *dev = conf->dev;
5046         struct mlx5_flow_counter *cnt;
5047
5048         data->dword = flow_dv_counter_alloc(dev, 0);
5049         data->dword |= MLX5_CNT_SHARED_OFFSET;
5050         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5051         cnt->shared_info.id = conf->id;
5052         return 0;
5053 }
5054
5055 /**
5056  * Get a shared flow counter.
5057  *
5058  * @param[in] dev
5059  *   Pointer to the Ethernet device structure.
5060  * @param[in] id
5061  *   Counter identifier.
5062  *
5063  * @return
5064  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5065  */
5066 static uint32_t
5067 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5068 {
5069         struct mlx5_priv *priv = dev->data->dev_private;
5070         struct mlx5_shared_counter_conf conf = {
5071                 .dev = dev,
5072                 .id = id,
5073         };
5074         union mlx5_l3t_data data = {
5075                 .dword = 0,
5076         };
5077
5078         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5079                                flow_dv_counter_alloc_shared_cb, &conf);
5080         return data.dword;
5081 }
5082
5083 /**
5084  * Get age param from counter index.
5085  *
5086  * @param[in] dev
5087  *   Pointer to the Ethernet device structure.
5088  * @param[in] counter
5089  *   Index to the counter handler.
5090  *
5091  * @return
5092  *   The aging parameter specified for the counter index.
5093  */
5094 static struct mlx5_age_param*
5095 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5096                                 uint32_t counter)
5097 {
5098         struct mlx5_flow_counter *cnt;
5099         struct mlx5_flow_counter_pool *pool = NULL;
5100
5101         flow_dv_counter_get_by_idx(dev, counter, &pool);
5102         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5103         cnt = MLX5_POOL_GET_CNT(pool, counter);
5104         return MLX5_CNT_TO_AGE(cnt);
5105 }
5106
5107 /**
5108  * Remove a flow counter from aged counter list.
5109  *
5110  * @param[in] dev
5111  *   Pointer to the Ethernet device structure.
5112  * @param[in] counter
5113  *   Index to the counter handler.
5114  * @param[in] cnt
5115  *   Pointer to the counter handler.
5116  */
5117 static void
5118 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5119                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5120 {
5121         struct mlx5_age_info *age_info;
5122         struct mlx5_age_param *age_param;
5123         struct mlx5_priv *priv = dev->data->dev_private;
5124         uint16_t expected = AGE_CANDIDATE;
5125
5126         age_info = GET_PORT_AGE_INFO(priv);
5127         age_param = flow_dv_counter_idx_get_age(dev, counter);
5128         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5129                                          AGE_FREE, false, __ATOMIC_RELAXED,
5130                                          __ATOMIC_RELAXED)) {
5131                 /**
5132                  * We need the lock even it is age timeout,
5133                  * since counter may still in process.
5134                  */
5135                 rte_spinlock_lock(&age_info->aged_sl);
5136                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5137                 rte_spinlock_unlock(&age_info->aged_sl);
5138                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5139         }
5140 }
5141
5142 /**
5143  * Release a flow counter.
5144  *
5145  * @param[in] dev
5146  *   Pointer to the Ethernet device structure.
5147  * @param[in] counter
5148  *   Index to the counter handler.
5149  */
5150 static void
5151 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5152 {
5153         struct mlx5_priv *priv = dev->data->dev_private;
5154         struct mlx5_flow_counter_pool *pool = NULL;
5155         struct mlx5_flow_counter *cnt;
5156         enum mlx5_counter_type cnt_type;
5157
5158         if (!counter)
5159                 return;
5160         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5161         MLX5_ASSERT(pool);
5162         if (IS_SHARED_CNT(counter) &&
5163             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5164                 return;
5165         if (pool->is_aged)
5166                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5167         cnt->pool = pool;
5168         /*
5169          * Put the counter back to list to be updated in none fallback mode.
5170          * Currently, we are using two list alternately, while one is in query,
5171          * add the freed counter to the other list based on the pool query_gen
5172          * value. After query finishes, add counter the list to the global
5173          * container counter list. The list changes while query starts. In
5174          * this case, lock will not be needed as query callback and release
5175          * function both operate with the different list.
5176          *
5177          */
5178         if (!priv->sh->cmng.counter_fallback) {
5179                 rte_spinlock_lock(&pool->csl);
5180                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5181                 rte_spinlock_unlock(&pool->csl);
5182         } else {
5183                 cnt->dcs_when_free = cnt->dcs_when_active;
5184                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5185                                            MLX5_COUNTER_TYPE_ORIGIN;
5186                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5187                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5188                                   cnt, next);
5189                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5190         }
5191 }
5192
5193 /**
5194  * Verify the @p attributes will be correctly understood by the NIC and store
5195  * them in the @p flow if everything is correct.
5196  *
5197  * @param[in] dev
5198  *   Pointer to dev struct.
5199  * @param[in] attributes
5200  *   Pointer to flow attributes
5201  * @param[in] external
5202  *   This flow rule is created by request external to PMD.
5203  * @param[out] error
5204  *   Pointer to error structure.
5205  *
5206  * @return
5207  *   - 0 on success and non root table.
5208  *   - 1 on success and root table.
5209  *   - a negative errno value otherwise and rte_errno is set.
5210  */
5211 static int
5212 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5213                             const struct mlx5_flow_tunnel *tunnel,
5214                             const struct rte_flow_attr *attributes,
5215                             const struct flow_grp_info *grp_info,
5216                             struct rte_flow_error *error)
5217 {
5218         struct mlx5_priv *priv = dev->data->dev_private;
5219         uint32_t priority_max = priv->config.flow_prio - 1;
5220         int ret = 0;
5221
5222 #ifndef HAVE_MLX5DV_DR
5223         RTE_SET_USED(tunnel);
5224         RTE_SET_USED(grp_info);
5225         if (attributes->group)
5226                 return rte_flow_error_set(error, ENOTSUP,
5227                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5228                                           NULL,
5229                                           "groups are not supported");
5230 #else
5231         uint32_t table = 0;
5232
5233         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5234                                        grp_info, error);
5235         if (ret)
5236                 return ret;
5237         if (!table)
5238                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5239 #endif
5240         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5241             attributes->priority >= priority_max)
5242                 return rte_flow_error_set(error, ENOTSUP,
5243                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5244                                           NULL,
5245                                           "priority out of range");
5246         if (attributes->transfer) {
5247                 if (!priv->config.dv_esw_en)
5248                         return rte_flow_error_set
5249                                 (error, ENOTSUP,
5250                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5251                                  "E-Switch dr is not supported");
5252                 if (!(priv->representor || priv->master))
5253                         return rte_flow_error_set
5254                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5255                                  NULL, "E-Switch configuration can only be"
5256                                  " done by a master or a representor device");
5257                 if (attributes->egress)
5258                         return rte_flow_error_set
5259                                 (error, ENOTSUP,
5260                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5261                                  "egress is not supported");
5262         }
5263         if (!(attributes->egress ^ attributes->ingress))
5264                 return rte_flow_error_set(error, ENOTSUP,
5265                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5266                                           "must specify exactly one of "
5267                                           "ingress or egress");
5268         return ret;
5269 }
5270
5271 /**
5272  * Internal validation function. For validating both actions and items.
5273  *
5274  * @param[in] dev
5275  *   Pointer to the rte_eth_dev structure.
5276  * @param[in] attr
5277  *   Pointer to the flow attributes.
5278  * @param[in] items
5279  *   Pointer to the list of items.
5280  * @param[in] actions
5281  *   Pointer to the list of actions.
5282  * @param[in] external
5283  *   This flow rule is created by request external to PMD.
5284  * @param[in] hairpin
5285  *   Number of hairpin TX actions, 0 means classic flow.
5286  * @param[out] error
5287  *   Pointer to the error structure.
5288  *
5289  * @return
5290  *   0 on success, a negative errno value otherwise and rte_errno is set.
5291  */
5292 static int
5293 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5294                  const struct rte_flow_item items[],
5295                  const struct rte_flow_action actions[],
5296                  bool external, int hairpin, struct rte_flow_error *error)
5297 {
5298         int ret;
5299         uint64_t action_flags = 0;
5300         uint64_t item_flags = 0;
5301         uint64_t last_item = 0;
5302         uint8_t next_protocol = 0xff;
5303         uint16_t ether_type = 0;
5304         int actions_n = 0;
5305         uint8_t item_ipv6_proto = 0;
5306         const struct rte_flow_item *gre_item = NULL;
5307         const struct rte_flow_item *gtp_item = NULL;
5308         const struct rte_flow_action_raw_decap *decap;
5309         const struct rte_flow_action_raw_encap *encap;
5310         const struct rte_flow_action_rss *rss;
5311         const struct rte_flow_item_tcp nic_tcp_mask = {
5312                 .hdr = {
5313                         .tcp_flags = 0xFF,
5314                         .src_port = RTE_BE16(UINT16_MAX),
5315                         .dst_port = RTE_BE16(UINT16_MAX),
5316                 }
5317         };
5318         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5319                 .hdr = {
5320                         .src_addr =
5321                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5322                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5323                         .dst_addr =
5324                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5325                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5326                         .vtc_flow = RTE_BE32(0xffffffff),
5327                         .proto = 0xff,
5328                         .hop_limits = 0xff,
5329                 },
5330                 .has_frag_ext = 1,
5331         };
5332         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5333                 .hdr = {
5334                         .common = {
5335                                 .u32 =
5336                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5337                                         .type = 0xFF,
5338                                         }).u32),
5339                         },
5340                         .dummy[0] = 0xffffffff,
5341                 },
5342         };
5343         struct mlx5_priv *priv = dev->data->dev_private;
5344         struct mlx5_dev_config *dev_conf = &priv->config;
5345         uint16_t queue_index = 0xFFFF;
5346         const struct rte_flow_item_vlan *vlan_m = NULL;
5347         int16_t rw_act_num = 0;
5348         uint64_t is_root;
5349         const struct mlx5_flow_tunnel *tunnel;
5350         struct flow_grp_info grp_info = {
5351                 .external = !!external,
5352                 .transfer = !!attr->transfer,
5353                 .fdb_def_rule = !!priv->fdb_def_rule,
5354         };
5355         const struct rte_eth_hairpin_conf *conf;
5356
5357         if (items == NULL)
5358                 return -1;
5359         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5360                 tunnel = flow_items_to_tunnel(items);
5361                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5362                                 MLX5_FLOW_ACTION_DECAP;
5363         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5364                 tunnel = flow_actions_to_tunnel(actions);
5365                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5366         } else {
5367                 tunnel = NULL;
5368         }
5369         if (tunnel && priv->representor)
5370                 return rte_flow_error_set(error, ENOTSUP,
5371                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5372                                           "decap not supported "
5373                                           "for VF representor");
5374         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5375                                 (dev, tunnel, attr, items, actions);
5376         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5377         if (ret < 0)
5378                 return ret;
5379         is_root = (uint64_t)ret;
5380         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5381                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5382                 int type = items->type;
5383
5384                 if (!mlx5_flow_os_item_supported(type))
5385                         return rte_flow_error_set(error, ENOTSUP,
5386                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5387                                                   NULL, "item not supported");
5388                 switch (type) {
5389                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5390                         if (items[0].type != (typeof(items[0].type))
5391                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5392                                 return rte_flow_error_set
5393                                                 (error, EINVAL,
5394                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5395                                                 NULL, "MLX5 private items "
5396                                                 "must be the first");
5397                         break;
5398                 case RTE_FLOW_ITEM_TYPE_VOID:
5399                         break;
5400                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5401                         ret = flow_dv_validate_item_port_id
5402                                         (dev, items, attr, item_flags, error);
5403                         if (ret < 0)
5404                                 return ret;
5405                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5406                         break;
5407                 case RTE_FLOW_ITEM_TYPE_ETH:
5408                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5409                                                           true, error);
5410                         if (ret < 0)
5411                                 return ret;
5412                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5413                                              MLX5_FLOW_LAYER_OUTER_L2;
5414                         if (items->mask != NULL && items->spec != NULL) {
5415                                 ether_type =
5416                                         ((const struct rte_flow_item_eth *)
5417                                          items->spec)->type;
5418                                 ether_type &=
5419                                         ((const struct rte_flow_item_eth *)
5420                                          items->mask)->type;
5421                                 ether_type = rte_be_to_cpu_16(ether_type);
5422                         } else {
5423                                 ether_type = 0;
5424                         }
5425                         break;
5426                 case RTE_FLOW_ITEM_TYPE_VLAN:
5427                         ret = flow_dv_validate_item_vlan(items, item_flags,
5428                                                          dev, error);
5429                         if (ret < 0)
5430                                 return ret;
5431                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5432                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5433                         if (items->mask != NULL && items->spec != NULL) {
5434                                 ether_type =
5435                                         ((const struct rte_flow_item_vlan *)
5436                                          items->spec)->inner_type;
5437                                 ether_type &=
5438                                         ((const struct rte_flow_item_vlan *)
5439                                          items->mask)->inner_type;
5440                                 ether_type = rte_be_to_cpu_16(ether_type);
5441                         } else {
5442                                 ether_type = 0;
5443                         }
5444                         /* Store outer VLAN mask for of_push_vlan action. */
5445                         if (!tunnel)
5446                                 vlan_m = items->mask;
5447                         break;
5448                 case RTE_FLOW_ITEM_TYPE_IPV4:
5449                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5450                                                   &item_flags, &tunnel);
5451                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5452                                                          last_item, ether_type,
5453                                                          error);
5454                         if (ret < 0)
5455                                 return ret;
5456                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5457                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5458                         if (items->mask != NULL &&
5459                             ((const struct rte_flow_item_ipv4 *)
5460                              items->mask)->hdr.next_proto_id) {
5461                                 next_protocol =
5462                                         ((const struct rte_flow_item_ipv4 *)
5463                                          (items->spec))->hdr.next_proto_id;
5464                                 next_protocol &=
5465                                         ((const struct rte_flow_item_ipv4 *)
5466                                          (items->mask))->hdr.next_proto_id;
5467                         } else {
5468                                 /* Reset for inner layer. */
5469                                 next_protocol = 0xff;
5470                         }
5471                         break;
5472                 case RTE_FLOW_ITEM_TYPE_IPV6:
5473                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5474                                                   &item_flags, &tunnel);
5475                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5476                                                            last_item,
5477                                                            ether_type,
5478                                                            &nic_ipv6_mask,
5479                                                            error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5483                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5484                         if (items->mask != NULL &&
5485                             ((const struct rte_flow_item_ipv6 *)
5486                              items->mask)->hdr.proto) {
5487                                 item_ipv6_proto =
5488                                         ((const struct rte_flow_item_ipv6 *)
5489                                          items->spec)->hdr.proto;
5490                                 next_protocol =
5491                                         ((const struct rte_flow_item_ipv6 *)
5492                                          items->spec)->hdr.proto;
5493                                 next_protocol &=
5494                                         ((const struct rte_flow_item_ipv6 *)
5495                                          items->mask)->hdr.proto;
5496                         } else {
5497                                 /* Reset for inner layer. */
5498                                 next_protocol = 0xff;
5499                         }
5500                         break;
5501                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5502                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5503                                                                   item_flags,
5504                                                                   error);
5505                         if (ret < 0)
5506                                 return ret;
5507                         last_item = tunnel ?
5508                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5509                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5510                         if (items->mask != NULL &&
5511                             ((const struct rte_flow_item_ipv6_frag_ext *)
5512                              items->mask)->hdr.next_header) {
5513                                 next_protocol =
5514                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5515                                  items->spec)->hdr.next_header;
5516                                 next_protocol &=
5517                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5518                                  items->mask)->hdr.next_header;
5519                         } else {
5520                                 /* Reset for inner layer. */
5521                                 next_protocol = 0xff;
5522                         }
5523                         break;
5524                 case RTE_FLOW_ITEM_TYPE_TCP:
5525                         ret = mlx5_flow_validate_item_tcp
5526                                                 (items, item_flags,
5527                                                  next_protocol,
5528                                                  &nic_tcp_mask,
5529                                                  error);
5530                         if (ret < 0)
5531                                 return ret;
5532                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5533                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5534                         break;
5535                 case RTE_FLOW_ITEM_TYPE_UDP:
5536                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5537                                                           next_protocol,
5538                                                           error);
5539                         if (ret < 0)
5540                                 return ret;
5541                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5542                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5543                         break;
5544                 case RTE_FLOW_ITEM_TYPE_GRE:
5545                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5546                                                           next_protocol, error);
5547                         if (ret < 0)
5548                                 return ret;
5549                         gre_item = items;
5550                         last_item = MLX5_FLOW_LAYER_GRE;
5551                         break;
5552                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5553                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5554                                                             next_protocol,
5555                                                             error);
5556                         if (ret < 0)
5557                                 return ret;
5558                         last_item = MLX5_FLOW_LAYER_NVGRE;
5559                         break;
5560                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5561                         ret = mlx5_flow_validate_item_gre_key
5562                                 (items, item_flags, gre_item, error);
5563                         if (ret < 0)
5564                                 return ret;
5565                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5566                         break;
5567                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5568                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5569                                                             error);
5570                         if (ret < 0)
5571                                 return ret;
5572                         last_item = MLX5_FLOW_LAYER_VXLAN;
5573                         break;
5574                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5575                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5576                                                                 item_flags, dev,
5577                                                                 error);
5578                         if (ret < 0)
5579                                 return ret;
5580                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5581                         break;
5582                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5583                         ret = mlx5_flow_validate_item_geneve(items,
5584                                                              item_flags, dev,
5585                                                              error);
5586                         if (ret < 0)
5587                                 return ret;
5588                         last_item = MLX5_FLOW_LAYER_GENEVE;
5589                         break;
5590                 case RTE_FLOW_ITEM_TYPE_MPLS:
5591                         ret = mlx5_flow_validate_item_mpls(dev, items,
5592                                                            item_flags,
5593                                                            last_item, error);
5594                         if (ret < 0)
5595                                 return ret;
5596                         last_item = MLX5_FLOW_LAYER_MPLS;
5597                         break;
5598
5599                 case RTE_FLOW_ITEM_TYPE_MARK:
5600                         ret = flow_dv_validate_item_mark(dev, items, attr,
5601                                                          error);
5602                         if (ret < 0)
5603                                 return ret;
5604                         last_item = MLX5_FLOW_ITEM_MARK;
5605                         break;
5606                 case RTE_FLOW_ITEM_TYPE_META:
5607                         ret = flow_dv_validate_item_meta(dev, items, attr,
5608                                                          error);
5609                         if (ret < 0)
5610                                 return ret;
5611                         last_item = MLX5_FLOW_ITEM_METADATA;
5612                         break;
5613                 case RTE_FLOW_ITEM_TYPE_ICMP:
5614                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5615                                                            next_protocol,
5616                                                            error);
5617                         if (ret < 0)
5618                                 return ret;
5619                         last_item = MLX5_FLOW_LAYER_ICMP;
5620                         break;
5621                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5622                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5623                                                             next_protocol,
5624                                                             error);
5625                         if (ret < 0)
5626                                 return ret;
5627                         item_ipv6_proto = IPPROTO_ICMPV6;
5628                         last_item = MLX5_FLOW_LAYER_ICMP6;
5629                         break;
5630                 case RTE_FLOW_ITEM_TYPE_TAG:
5631                         ret = flow_dv_validate_item_tag(dev, items,
5632                                                         attr, error);
5633                         if (ret < 0)
5634                                 return ret;
5635                         last_item = MLX5_FLOW_ITEM_TAG;
5636                         break;
5637                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5638                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5639                         break;
5640                 case RTE_FLOW_ITEM_TYPE_GTP:
5641                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5642                                                         error);
5643                         if (ret < 0)
5644                                 return ret;
5645                         gtp_item = items;
5646                         last_item = MLX5_FLOW_LAYER_GTP;
5647                         break;
5648                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5649                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
5650                                                             gtp_item, attr,
5651                                                             error);
5652                         if (ret < 0)
5653                                 return ret;
5654                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
5655                         break;
5656                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5657                         /* Capacity will be checked in the translate stage. */
5658                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5659                                                             last_item,
5660                                                             ether_type,
5661                                                             &nic_ecpri_mask,
5662                                                             error);
5663                         if (ret < 0)
5664                                 return ret;
5665                         last_item = MLX5_FLOW_LAYER_ECPRI;
5666                         break;
5667                 default:
5668                         return rte_flow_error_set(error, ENOTSUP,
5669                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5670                                                   NULL, "item not supported");
5671                 }
5672                 item_flags |= last_item;
5673         }
5674         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5675                 int type = actions->type;
5676
5677                 if (!mlx5_flow_os_action_supported(type))
5678                         return rte_flow_error_set(error, ENOTSUP,
5679                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5680                                                   actions,
5681                                                   "action not supported");
5682                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5683                         return rte_flow_error_set(error, ENOTSUP,
5684                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5685                                                   actions, "too many actions");
5686                 switch (type) {
5687                 case RTE_FLOW_ACTION_TYPE_VOID:
5688                         break;
5689                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5690                         ret = flow_dv_validate_action_port_id(dev,
5691                                                               action_flags,
5692                                                               actions,
5693                                                               attr,
5694                                                               error);
5695                         if (ret)
5696                                 return ret;
5697                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5698                         ++actions_n;
5699                         break;
5700                 case RTE_FLOW_ACTION_TYPE_FLAG:
5701                         ret = flow_dv_validate_action_flag(dev, action_flags,
5702                                                            attr, error);
5703                         if (ret < 0)
5704                                 return ret;
5705                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5706                                 /* Count all modify-header actions as one. */
5707                                 if (!(action_flags &
5708                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5709                                         ++actions_n;
5710                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5711                                                 MLX5_FLOW_ACTION_MARK_EXT;
5712                         } else {
5713                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5714                                 ++actions_n;
5715                         }
5716                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5717                         break;
5718                 case RTE_FLOW_ACTION_TYPE_MARK:
5719                         ret = flow_dv_validate_action_mark(dev, actions,
5720                                                            action_flags,
5721                                                            attr, error);
5722                         if (ret < 0)
5723                                 return ret;
5724                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5725                                 /* Count all modify-header actions as one. */
5726                                 if (!(action_flags &
5727                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5728                                         ++actions_n;
5729                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5730                                                 MLX5_FLOW_ACTION_MARK_EXT;
5731                         } else {
5732                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5733                                 ++actions_n;
5734                         }
5735                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5736                         break;
5737                 case RTE_FLOW_ACTION_TYPE_SET_META:
5738                         ret = flow_dv_validate_action_set_meta(dev, actions,
5739                                                                action_flags,
5740                                                                attr, error);
5741                         if (ret < 0)
5742                                 return ret;
5743                         /* Count all modify-header actions as one action. */
5744                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5745                                 ++actions_n;
5746                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5747                         rw_act_num += MLX5_ACT_NUM_SET_META;
5748                         break;
5749                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5750                         ret = flow_dv_validate_action_set_tag(dev, actions,
5751                                                               action_flags,
5752                                                               attr, error);
5753                         if (ret < 0)
5754                                 return ret;
5755                         /* Count all modify-header actions as one action. */
5756                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5757                                 ++actions_n;
5758                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5759                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5760                         break;
5761                 case RTE_FLOW_ACTION_TYPE_DROP:
5762                         ret = mlx5_flow_validate_action_drop(action_flags,
5763                                                              attr, error);
5764                         if (ret < 0)
5765                                 return ret;
5766                         action_flags |= MLX5_FLOW_ACTION_DROP;
5767                         ++actions_n;
5768                         break;
5769                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5770                         ret = mlx5_flow_validate_action_queue(actions,
5771                                                               action_flags, dev,
5772                                                               attr, error);
5773                         if (ret < 0)
5774                                 return ret;
5775                         queue_index = ((const struct rte_flow_action_queue *)
5776                                                         (actions->conf))->index;
5777                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5778                         ++actions_n;
5779                         break;
5780                 case RTE_FLOW_ACTION_TYPE_RSS:
5781                         rss = actions->conf;
5782                         ret = mlx5_flow_validate_action_rss(actions,
5783                                                             action_flags, dev,
5784                                                             attr, item_flags,
5785                                                             error);
5786                         if (ret < 0)
5787                                 return ret;
5788                         if (rss != NULL && rss->queue_num)
5789                                 queue_index = rss->queue[0];
5790                         action_flags |= MLX5_FLOW_ACTION_RSS;
5791                         ++actions_n;
5792                         break;
5793                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5794                         ret =
5795                         mlx5_flow_validate_action_default_miss(action_flags,
5796                                         attr, error);
5797                         if (ret < 0)
5798                                 return ret;
5799                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5800                         ++actions_n;
5801                         break;
5802                 case RTE_FLOW_ACTION_TYPE_COUNT:
5803                         ret = flow_dv_validate_action_count(dev, error);
5804                         if (ret < 0)
5805                                 return ret;
5806                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5807                         ++actions_n;
5808                         break;
5809                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5810                         if (flow_dv_validate_action_pop_vlan(dev,
5811                                                              action_flags,
5812                                                              actions,
5813                                                              item_flags, attr,
5814                                                              error))
5815                                 return -rte_errno;
5816                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5817                         ++actions_n;
5818                         break;
5819                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5820                         ret = flow_dv_validate_action_push_vlan(dev,
5821                                                                 action_flags,
5822                                                                 vlan_m,
5823                                                                 actions, attr,
5824                                                                 error);
5825                         if (ret < 0)
5826                                 return ret;
5827                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5828                         ++actions_n;
5829                         break;
5830                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5831                         ret = flow_dv_validate_action_set_vlan_pcp
5832                                                 (action_flags, actions, error);
5833                         if (ret < 0)
5834                                 return ret;
5835                         /* Count PCP with push_vlan command. */
5836                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5837                         break;
5838                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5839                         ret = flow_dv_validate_action_set_vlan_vid
5840                                                 (item_flags, action_flags,
5841                                                  actions, error);
5842                         if (ret < 0)
5843                                 return ret;
5844                         /* Count VID with push_vlan command. */
5845                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5846                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5847                         break;
5848                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5849                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5850                         ret = flow_dv_validate_action_l2_encap(dev,
5851                                                                action_flags,
5852                                                                actions, attr,
5853                                                                error);
5854                         if (ret < 0)
5855                                 return ret;
5856                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5857                         ++actions_n;
5858                         break;
5859                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5860                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5861                         ret = flow_dv_validate_action_decap(dev, action_flags,
5862                                                             actions, item_flags,
5863                                                             attr, error);
5864                         if (ret < 0)
5865                                 return ret;
5866                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5867                         ++actions_n;
5868                         break;
5869                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5870                         ret = flow_dv_validate_action_raw_encap_decap
5871                                 (dev, NULL, actions->conf, attr, &action_flags,
5872                                  &actions_n, actions, item_flags, error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         break;
5876                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5877                         decap = actions->conf;
5878                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5879                                 ;
5880                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5881                                 encap = NULL;
5882                                 actions--;
5883                         } else {
5884                                 encap = actions->conf;
5885                         }
5886                         ret = flow_dv_validate_action_raw_encap_decap
5887                                            (dev,
5888                                             decap ? decap : &empty_decap, encap,
5889                                             attr, &action_flags, &actions_n,
5890                                             actions, item_flags, error);
5891                         if (ret < 0)
5892                                 return ret;
5893                         break;
5894                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5895                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5896                         ret = flow_dv_validate_action_modify_mac(action_flags,
5897                                                                  actions,
5898                                                                  item_flags,
5899                                                                  error);
5900                         if (ret < 0)
5901                                 return ret;
5902                         /* Count all modify-header actions as one action. */
5903                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5904                                 ++actions_n;
5905                         action_flags |= actions->type ==
5906                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5907                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5908                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5909                         /*
5910                          * Even if the source and destination MAC addresses have
5911                          * overlap in the header with 4B alignment, the convert
5912                          * function will handle them separately and 4 SW actions
5913                          * will be created. And 2 actions will be added each
5914                          * time no matter how many bytes of address will be set.
5915                          */
5916                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5917                         break;
5918                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5919                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5920                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5921                                                                   actions,
5922                                                                   item_flags,
5923                                                                   error);
5924                         if (ret < 0)
5925                                 return ret;
5926                         /* Count all modify-header actions as one action. */
5927                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5928                                 ++actions_n;
5929                         action_flags |= actions->type ==
5930                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5931                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5932                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5933                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5934                         break;
5935                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5936                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5937                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5938                                                                   actions,
5939                                                                   item_flags,
5940                                                                   error);
5941                         if (ret < 0)
5942                                 return ret;
5943                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5944                                 return rte_flow_error_set(error, ENOTSUP,
5945                                         RTE_FLOW_ERROR_TYPE_ACTION,
5946                                         actions,
5947                                         "Can't change header "
5948                                         "with ICMPv6 proto");
5949                         /* Count all modify-header actions as one action. */
5950                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5951                                 ++actions_n;
5952                         action_flags |= actions->type ==
5953                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5954                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5955                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5956                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5957                         break;
5958                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5959                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5960                         ret = flow_dv_validate_action_modify_tp(action_flags,
5961                                                                 actions,
5962                                                                 item_flags,
5963                                                                 error);
5964                         if (ret < 0)
5965                                 return ret;
5966                         /* Count all modify-header actions as one action. */
5967                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5968                                 ++actions_n;
5969                         action_flags |= actions->type ==
5970                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5971                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5972                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5973                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5974                         break;
5975                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5976                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5977                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5978                                                                  actions,
5979                                                                  item_flags,
5980                                                                  error);
5981                         if (ret < 0)
5982                                 return ret;
5983                         /* Count all modify-header actions as one action. */
5984                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5985                                 ++actions_n;
5986                         action_flags |= actions->type ==
5987                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5988                                                 MLX5_FLOW_ACTION_SET_TTL :
5989                                                 MLX5_FLOW_ACTION_DEC_TTL;
5990                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5991                         break;
5992                 case RTE_FLOW_ACTION_TYPE_JUMP:
5993                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5994                                                            action_flags,
5995                                                            attr, external,
5996                                                            error);
5997                         if (ret)
5998                                 return ret;
5999                         ++actions_n;
6000                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6001                         break;
6002                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6003                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6004                         ret = flow_dv_validate_action_modify_tcp_seq
6005                                                                 (action_flags,
6006                                                                  actions,
6007                                                                  item_flags,
6008                                                                  error);
6009                         if (ret < 0)
6010                                 return ret;
6011                         /* Count all modify-header actions as one action. */
6012                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6013                                 ++actions_n;
6014                         action_flags |= actions->type ==
6015                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6016                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6017                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6018                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6019                         break;
6020                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6021                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6022                         ret = flow_dv_validate_action_modify_tcp_ack
6023                                                                 (action_flags,
6024                                                                  actions,
6025                                                                  item_flags,
6026                                                                  error);
6027                         if (ret < 0)
6028                                 return ret;
6029                         /* Count all modify-header actions as one action. */
6030                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6031                                 ++actions_n;
6032                         action_flags |= actions->type ==
6033                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6034                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6035                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6036                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6037                         break;
6038                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6039                         break;
6040                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6041                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6042                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6043                         break;
6044                 case RTE_FLOW_ACTION_TYPE_METER:
6045                         ret = mlx5_flow_validate_action_meter(dev,
6046                                                               action_flags,
6047                                                               actions, attr,
6048                                                               error);
6049                         if (ret < 0)
6050                                 return ret;
6051                         action_flags |= MLX5_FLOW_ACTION_METER;
6052                         ++actions_n;
6053                         /* Meter action will add one more TAG action. */
6054                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6055                         break;
6056                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6057                         if (!attr->transfer && !attr->group)
6058                                 return rte_flow_error_set(error, ENOTSUP,
6059                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6060                                                                            NULL,
6061                           "Shared ASO age action is not supported for group 0");
6062                         action_flags |= MLX5_FLOW_ACTION_AGE;
6063                         ++actions_n;
6064                         break;
6065                 case RTE_FLOW_ACTION_TYPE_AGE:
6066                         ret = flow_dv_validate_action_age(action_flags,
6067                                                           actions, dev,
6068                                                           error);
6069                         if (ret < 0)
6070                                 return ret;
6071                         action_flags |= MLX5_FLOW_ACTION_AGE;
6072                         ++actions_n;
6073                         break;
6074                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6075                         ret = flow_dv_validate_action_modify_ipv4_dscp
6076                                                          (action_flags,
6077                                                           actions,
6078                                                           item_flags,
6079                                                           error);
6080                         if (ret < 0)
6081                                 return ret;
6082                         /* Count all modify-header actions as one action. */
6083                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6084                                 ++actions_n;
6085                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6086                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6087                         break;
6088                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6089                         ret = flow_dv_validate_action_modify_ipv6_dscp
6090                                                                 (action_flags,
6091                                                                  actions,
6092                                                                  item_flags,
6093                                                                  error);
6094                         if (ret < 0)
6095                                 return ret;
6096                         /* Count all modify-header actions as one action. */
6097                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6098                                 ++actions_n;
6099                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6100                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6101                         break;
6102                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6103                         ret = flow_dv_validate_action_sample(action_flags,
6104                                                              actions, dev,
6105                                                              attr, item_flags,
6106                                                              error);
6107                         if (ret < 0)
6108                                 return ret;
6109                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6110                         ++actions_n;
6111                         break;
6112                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6113                         if (actions[0].type != (typeof(actions[0].type))
6114                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6115                                 return rte_flow_error_set
6116                                                 (error, EINVAL,
6117                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6118                                                 NULL, "MLX5 private action "
6119                                                 "must be the first");
6120
6121                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6122                         break;
6123                 default:
6124                         return rte_flow_error_set(error, ENOTSUP,
6125                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6126                                                   actions,
6127                                                   "action not supported");
6128                 }
6129         }
6130         /*
6131          * Validate actions in flow rules
6132          * - Explicit decap action is prohibited by the tunnel offload API.
6133          * - Drop action in tunnel steer rule is prohibited by the API.
6134          * - Application cannot use MARK action because it's value can mask
6135          *   tunnel default miss nitification.
6136          * - JUMP in tunnel match rule has no support in current PMD
6137          *   implementation.
6138          * - TAG & META are reserved for future uses.
6139          */
6140         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6141                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6142                                             MLX5_FLOW_ACTION_MARK     |
6143                                             MLX5_FLOW_ACTION_SET_TAG  |
6144                                             MLX5_FLOW_ACTION_SET_META |
6145                                             MLX5_FLOW_ACTION_DROP;
6146
6147                 if (action_flags & bad_actions_mask)
6148                         return rte_flow_error_set
6149                                         (error, EINVAL,
6150                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6151                                         "Invalid RTE action in tunnel "
6152                                         "set decap rule");
6153                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6154                         return rte_flow_error_set
6155                                         (error, EINVAL,
6156                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6157                                         "tunnel set decap rule must terminate "
6158                                         "with JUMP");
6159                 if (!attr->ingress)
6160                         return rte_flow_error_set
6161                                         (error, EINVAL,
6162                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6163                                         "tunnel flows for ingress traffic only");
6164         }
6165         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6166                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6167                                             MLX5_FLOW_ACTION_MARK    |
6168                                             MLX5_FLOW_ACTION_SET_TAG |
6169                                             MLX5_FLOW_ACTION_SET_META;
6170
6171                 if (action_flags & bad_actions_mask)
6172                         return rte_flow_error_set
6173                                         (error, EINVAL,
6174                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6175                                         "Invalid RTE action in tunnel "
6176                                         "set match rule");
6177         }
6178         /*
6179          * Validate the drop action mutual exclusion with other actions.
6180          * Drop action is mutually-exclusive with any other action, except for
6181          * Count action.
6182          */
6183         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6184             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6185                 return rte_flow_error_set(error, EINVAL,
6186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6187                                           "Drop action is mutually-exclusive "
6188                                           "with any other action, except for "
6189                                           "Count action");
6190         /* Eswitch has few restrictions on using items and actions */
6191         if (attr->transfer) {
6192                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6193                     action_flags & MLX5_FLOW_ACTION_FLAG)
6194                         return rte_flow_error_set(error, ENOTSUP,
6195                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6196                                                   NULL,
6197                                                   "unsupported action FLAG");
6198                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6199                     action_flags & MLX5_FLOW_ACTION_MARK)
6200                         return rte_flow_error_set(error, ENOTSUP,
6201                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6202                                                   NULL,
6203                                                   "unsupported action MARK");
6204                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6205                         return rte_flow_error_set(error, ENOTSUP,
6206                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6207                                                   NULL,
6208                                                   "unsupported action QUEUE");
6209                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6210                         return rte_flow_error_set(error, ENOTSUP,
6211                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6212                                                   NULL,
6213                                                   "unsupported action RSS");
6214                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6215                         return rte_flow_error_set(error, EINVAL,
6216                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6217                                                   actions,
6218                                                   "no fate action is found");
6219         } else {
6220                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6221                         return rte_flow_error_set(error, EINVAL,
6222                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6223                                                   actions,
6224                                                   "no fate action is found");
6225         }
6226         /*
6227          * Continue validation for Xcap and VLAN actions.
6228          * If hairpin is working in explicit TX rule mode, there is no actions
6229          * splitting and the validation of hairpin ingress flow should be the
6230          * same as other standard flows.
6231          */
6232         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6233                              MLX5_FLOW_VLAN_ACTIONS)) &&
6234             (queue_index == 0xFFFF ||
6235              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6236              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6237              conf->tx_explicit != 0))) {
6238                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6239                     MLX5_FLOW_XCAP_ACTIONS)
6240                         return rte_flow_error_set(error, ENOTSUP,
6241                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6242                                                   NULL, "encap and decap "
6243                                                   "combination aren't supported");
6244                 if (!attr->transfer && attr->ingress) {
6245                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6246                                 return rte_flow_error_set
6247                                                 (error, ENOTSUP,
6248                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6249                                                  NULL, "encap is not supported"
6250                                                  " for ingress traffic");
6251                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6252                                 return rte_flow_error_set
6253                                                 (error, ENOTSUP,
6254                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6255                                                  NULL, "push VLAN action not "
6256                                                  "supported for ingress");
6257                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6258                                         MLX5_FLOW_VLAN_ACTIONS)
6259                                 return rte_flow_error_set
6260                                                 (error, ENOTSUP,
6261                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6262                                                  NULL, "no support for "
6263                                                  "multiple VLAN actions");
6264                 }
6265         }
6266         /*
6267          * Hairpin flow will add one more TAG action in TX implicit mode.
6268          * In TX explicit mode, there will be no hairpin flow ID.
6269          */
6270         if (hairpin > 0)
6271                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6272         /* extra metadata enabled: one more TAG action will be add. */
6273         if (dev_conf->dv_flow_en &&
6274             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6275             mlx5_flow_ext_mreg_supported(dev))
6276                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6277         if ((uint32_t)rw_act_num >
6278                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6279                 return rte_flow_error_set(error, ENOTSUP,
6280                                           RTE_FLOW_ERROR_TYPE_ACTION,
6281                                           NULL, "too many header modify"
6282                                           " actions to support");
6283         }
6284         return 0;
6285 }
6286
6287 /**
6288  * Internal preparation function. Allocates the DV flow size,
6289  * this size is constant.
6290  *
6291  * @param[in] dev
6292  *   Pointer to the rte_eth_dev structure.
6293  * @param[in] attr
6294  *   Pointer to the flow attributes.
6295  * @param[in] items
6296  *   Pointer to the list of items.
6297  * @param[in] actions
6298  *   Pointer to the list of actions.
6299  * @param[out] error
6300  *   Pointer to the error structure.
6301  *
6302  * @return
6303  *   Pointer to mlx5_flow object on success,
6304  *   otherwise NULL and rte_errno is set.
6305  */
6306 static struct mlx5_flow *
6307 flow_dv_prepare(struct rte_eth_dev *dev,
6308                 const struct rte_flow_attr *attr __rte_unused,
6309                 const struct rte_flow_item items[] __rte_unused,
6310                 const struct rte_flow_action actions[] __rte_unused,
6311                 struct rte_flow_error *error)
6312 {
6313         uint32_t handle_idx = 0;
6314         struct mlx5_flow *dev_flow;
6315         struct mlx5_flow_handle *dev_handle;
6316         struct mlx5_priv *priv = dev->data->dev_private;
6317         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6318
6319         MLX5_ASSERT(wks);
6320         /* In case of corrupting the memory. */
6321         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6322                 rte_flow_error_set(error, ENOSPC,
6323                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6324                                    "not free temporary device flow");
6325                 return NULL;
6326         }
6327         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6328                                    &handle_idx);
6329         if (!dev_handle) {
6330                 rte_flow_error_set(error, ENOMEM,
6331                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6332                                    "not enough memory to create flow handle");
6333                 return NULL;
6334         }
6335         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6336         dev_flow = &wks->flows[wks->flow_idx++];
6337         memset(dev_flow, 0, sizeof(*dev_flow));
6338         dev_flow->handle = dev_handle;
6339         dev_flow->handle_idx = handle_idx;
6340         /*
6341          * In some old rdma-core releases, before continuing, a check of the
6342          * length of matching parameter will be done at first. It needs to use
6343          * the length without misc4 param. If the flow has misc4 support, then
6344          * the length needs to be adjusted accordingly. Each param member is
6345          * aligned with a 64B boundary naturally.
6346          */
6347         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6348                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6349         dev_flow->ingress = attr->ingress;
6350         dev_flow->dv.transfer = attr->transfer;
6351         return dev_flow;
6352 }
6353
6354 #ifdef RTE_LIBRTE_MLX5_DEBUG
6355 /**
6356  * Sanity check for match mask and value. Similar to check_valid_spec() in
6357  * kernel driver. If unmasked bit is present in value, it returns failure.
6358  *
6359  * @param match_mask
6360  *   pointer to match mask buffer.
6361  * @param match_value
6362  *   pointer to match value buffer.
6363  *
6364  * @return
6365  *   0 if valid, -EINVAL otherwise.
6366  */
6367 static int
6368 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6369 {
6370         uint8_t *m = match_mask;
6371         uint8_t *v = match_value;
6372         unsigned int i;
6373
6374         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6375                 if (v[i] & ~m[i]) {
6376                         DRV_LOG(ERR,
6377                                 "match_value differs from match_criteria"
6378                                 " %p[%u] != %p[%u]",
6379                                 match_value, i, match_mask, i);
6380                         return -EINVAL;
6381                 }
6382         }
6383         return 0;
6384 }
6385 #endif
6386
6387 /**
6388  * Add match of ip_version.
6389  *
6390  * @param[in] group
6391  *   Flow group.
6392  * @param[in] headers_v
6393  *   Values header pointer.
6394  * @param[in] headers_m
6395  *   Masks header pointer.
6396  * @param[in] ip_version
6397  *   The IP version to set.
6398  */
6399 static inline void
6400 flow_dv_set_match_ip_version(uint32_t group,
6401                              void *headers_v,
6402                              void *headers_m,
6403                              uint8_t ip_version)
6404 {
6405         if (group == 0)
6406                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6407         else
6408                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6409                          ip_version);
6410         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6411         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6412         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6413 }
6414
6415 /**
6416  * Add Ethernet item to matcher and to the value.
6417  *
6418  * @param[in, out] matcher
6419  *   Flow matcher.
6420  * @param[in, out] key
6421  *   Flow matcher value.
6422  * @param[in] item
6423  *   Flow pattern to translate.
6424  * @param[in] inner
6425  *   Item is inner pattern.
6426  */
6427 static void
6428 flow_dv_translate_item_eth(void *matcher, void *key,
6429                            const struct rte_flow_item *item, int inner,
6430                            uint32_t group)
6431 {
6432         const struct rte_flow_item_eth *eth_m = item->mask;
6433         const struct rte_flow_item_eth *eth_v = item->spec;
6434         const struct rte_flow_item_eth nic_mask = {
6435                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6436                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6437                 .type = RTE_BE16(0xffff),
6438                 .has_vlan = 0,
6439         };
6440         void *hdrs_m;
6441         void *hdrs_v;
6442         char *l24_v;
6443         unsigned int i;
6444
6445         if (!eth_v)
6446                 return;
6447         if (!eth_m)
6448                 eth_m = &nic_mask;
6449         if (inner) {
6450                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6451                                          inner_headers);
6452                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6453         } else {
6454                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6455                                          outer_headers);
6456                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6457         }
6458         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6459                &eth_m->dst, sizeof(eth_m->dst));
6460         /* The value must be in the range of the mask. */
6461         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6462         for (i = 0; i < sizeof(eth_m->dst); ++i)
6463                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6464         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6465                &eth_m->src, sizeof(eth_m->src));
6466         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6467         /* The value must be in the range of the mask. */
6468         for (i = 0; i < sizeof(eth_m->dst); ++i)
6469                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6470         /*
6471          * HW supports match on one Ethertype, the Ethertype following the last
6472          * VLAN tag of the packet (see PRM).
6473          * Set match on ethertype only if ETH header is not followed by VLAN.
6474          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6475          * ethertype, and use ip_version field instead.
6476          * eCPRI over Ether layer will use type value 0xAEFE.
6477          */
6478         if (eth_m->type == 0xFFFF) {
6479                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6480                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6481                 switch (eth_v->type) {
6482                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6483                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6484                         return;
6485                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6486                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6487                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6488                         return;
6489                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6490                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6491                         return;
6492                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6493                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6494                         return;
6495                 default:
6496                         break;
6497                 }
6498         }
6499         if (eth_m->has_vlan) {
6500                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6501                 if (eth_v->has_vlan) {
6502                         /*
6503                          * Here, when also has_more_vlan field in VLAN item is
6504                          * not set, only single-tagged packets will be matched.
6505                          */
6506                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6507                         return;
6508                 }
6509         }
6510         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6511                  rte_be_to_cpu_16(eth_m->type));
6512         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6513         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6514 }
6515
6516 /**
6517  * Add VLAN item to matcher and to the value.
6518  *
6519  * @param[in, out] dev_flow
6520  *   Flow descriptor.
6521  * @param[in, out] matcher
6522  *   Flow matcher.
6523  * @param[in, out] key
6524  *   Flow matcher value.
6525  * @param[in] item
6526  *   Flow pattern to translate.
6527  * @param[in] inner
6528  *   Item is inner pattern.
6529  */
6530 static void
6531 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6532                             void *matcher, void *key,
6533                             const struct rte_flow_item *item,
6534                             int inner, uint32_t group)
6535 {
6536         const struct rte_flow_item_vlan *vlan_m = item->mask;
6537         const struct rte_flow_item_vlan *vlan_v = item->spec;
6538         void *hdrs_m;
6539         void *hdrs_v;
6540         uint16_t tci_m;
6541         uint16_t tci_v;
6542
6543         if (inner) {
6544                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6545                                          inner_headers);
6546                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6547         } else {
6548                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6549                                          outer_headers);
6550                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6551                 /*
6552                  * This is workaround, masks are not supported,
6553                  * and pre-validated.
6554                  */
6555                 if (vlan_v)
6556                         dev_flow->handle->vf_vlan.tag =
6557                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6558         }
6559         /*
6560          * When VLAN item exists in flow, mark packet as tagged,
6561          * even if TCI is not specified.
6562          */
6563         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6564                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6565                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6566         }
6567         if (!vlan_v)
6568                 return;
6569         if (!vlan_m)
6570                 vlan_m = &rte_flow_item_vlan_mask;
6571         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6572         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6573         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6574         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6575         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6576         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6577         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6578         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6579         /*
6580          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6581          * ethertype, and use ip_version field instead.
6582          */
6583         if (vlan_m->inner_type == 0xFFFF) {
6584                 switch (vlan_v->inner_type) {
6585                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6586                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6587                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6588                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6589                         return;
6590                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6591                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6592                         return;
6593                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6594                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6595                         return;
6596                 default:
6597                         break;
6598                 }
6599         }
6600         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6601                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6602                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6603                 /* Only one vlan_tag bit can be set. */
6604                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6605                 return;
6606         }
6607         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6608                  rte_be_to_cpu_16(vlan_m->inner_type));
6609         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6610                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6611 }
6612
6613 /**
6614  * Add IPV4 item to matcher and to the value.
6615  *
6616  * @param[in, out] matcher
6617  *   Flow matcher.
6618  * @param[in, out] key
6619  *   Flow matcher value.
6620  * @param[in] item
6621  *   Flow pattern to translate.
6622  * @param[in] inner
6623  *   Item is inner pattern.
6624  * @param[in] group
6625  *   The group to insert the rule.
6626  */
6627 static void
6628 flow_dv_translate_item_ipv4(void *matcher, void *key,
6629                             const struct rte_flow_item *item,
6630                             int inner, uint32_t group)
6631 {
6632         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6633         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6634         const struct rte_flow_item_ipv4 nic_mask = {
6635                 .hdr = {
6636                         .src_addr = RTE_BE32(0xffffffff),
6637                         .dst_addr = RTE_BE32(0xffffffff),
6638                         .type_of_service = 0xff,
6639                         .next_proto_id = 0xff,
6640                         .time_to_live = 0xff,
6641                 },
6642         };
6643         void *headers_m;
6644         void *headers_v;
6645         char *l24_m;
6646         char *l24_v;
6647         uint8_t tos;
6648
6649         if (inner) {
6650                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6651                                          inner_headers);
6652                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6653         } else {
6654                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6655                                          outer_headers);
6656                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6657         }
6658         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6659         if (!ipv4_v)
6660                 return;
6661         if (!ipv4_m)
6662                 ipv4_m = &nic_mask;
6663         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6664                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6665         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6666                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6667         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6668         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6669         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6670                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6671         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6672                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6673         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6674         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6675         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6676         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6677                  ipv4_m->hdr.type_of_service);
6678         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6679         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6680                  ipv4_m->hdr.type_of_service >> 2);
6681         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6682         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6683                  ipv4_m->hdr.next_proto_id);
6684         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6685                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6686         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6687                  ipv4_m->hdr.time_to_live);
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6689                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6691                  !!(ipv4_m->hdr.fragment_offset));
6692         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6693                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6694 }
6695
6696 /**
6697  * Add IPV6 item to matcher and to the value.
6698  *
6699  * @param[in, out] matcher
6700  *   Flow matcher.
6701  * @param[in, out] key
6702  *   Flow matcher value.
6703  * @param[in] item
6704  *   Flow pattern to translate.
6705  * @param[in] inner
6706  *   Item is inner pattern.
6707  * @param[in] group
6708  *   The group to insert the rule.
6709  */
6710 static void
6711 flow_dv_translate_item_ipv6(void *matcher, void *key,
6712                             const struct rte_flow_item *item,
6713                             int inner, uint32_t group)
6714 {
6715         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6716         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6717         const struct rte_flow_item_ipv6 nic_mask = {
6718                 .hdr = {
6719                         .src_addr =
6720                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6721                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6722                         .dst_addr =
6723                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6724                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6725                         .vtc_flow = RTE_BE32(0xffffffff),
6726                         .proto = 0xff,
6727                         .hop_limits = 0xff,
6728                 },
6729         };
6730         void *headers_m;
6731         void *headers_v;
6732         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6733         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6734         char *l24_m;
6735         char *l24_v;
6736         uint32_t vtc_m;
6737         uint32_t vtc_v;
6738         int i;
6739         int size;
6740
6741         if (inner) {
6742                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6743                                          inner_headers);
6744                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6745         } else {
6746                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6747                                          outer_headers);
6748                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6749         }
6750         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6751         if (!ipv6_v)
6752                 return;
6753         if (!ipv6_m)
6754                 ipv6_m = &nic_mask;
6755         size = sizeof(ipv6_m->hdr.dst_addr);
6756         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6757                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6758         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6759                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6760         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6761         for (i = 0; i < size; ++i)
6762                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6763         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6764                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6765         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6766                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6767         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6768         for (i = 0; i < size; ++i)
6769                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6770         /* TOS. */
6771         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6772         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6773         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6774         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6775         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6776         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6777         /* Label. */
6778         if (inner) {
6779                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6780                          vtc_m);
6781                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6782                          vtc_v);
6783         } else {
6784                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6785                          vtc_m);
6786                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6787                          vtc_v);
6788         }
6789         /* Protocol. */
6790         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6791                  ipv6_m->hdr.proto);
6792         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6793                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6794         /* Hop limit. */
6795         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6796                  ipv6_m->hdr.hop_limits);
6797         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6798                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6799         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6800                  !!(ipv6_m->has_frag_ext));
6801         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6802                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6803 }
6804
6805 /**
6806  * Add IPV6 fragment extension item to matcher and to the value.
6807  *
6808  * @param[in, out] matcher
6809  *   Flow matcher.
6810  * @param[in, out] key
6811  *   Flow matcher value.
6812  * @param[in] item
6813  *   Flow pattern to translate.
6814  * @param[in] inner
6815  *   Item is inner pattern.
6816  */
6817 static void
6818 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6819                                      const struct rte_flow_item *item,
6820                                      int inner)
6821 {
6822         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6823         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6824         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6825                 .hdr = {
6826                         .next_header = 0xff,
6827                         .frag_data = RTE_BE16(0xffff),
6828                 },
6829         };
6830         void *headers_m;
6831         void *headers_v;
6832
6833         if (inner) {
6834                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6835                                          inner_headers);
6836                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6837         } else {
6838                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6839                                          outer_headers);
6840                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6841         }
6842         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6843         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6845         if (!ipv6_frag_ext_v)
6846                 return;
6847         if (!ipv6_frag_ext_m)
6848                 ipv6_frag_ext_m = &nic_mask;
6849         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6850                  ipv6_frag_ext_m->hdr.next_header);
6851         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6852                  ipv6_frag_ext_v->hdr.next_header &
6853                  ipv6_frag_ext_m->hdr.next_header);
6854 }
6855
6856 /**
6857  * Add TCP item to matcher and to the value.
6858  *
6859  * @param[in, out] matcher
6860  *   Flow matcher.
6861  * @param[in, out] key
6862  *   Flow matcher value.
6863  * @param[in] item
6864  *   Flow pattern to translate.
6865  * @param[in] inner
6866  *   Item is inner pattern.
6867  */
6868 static void
6869 flow_dv_translate_item_tcp(void *matcher, void *key,
6870                            const struct rte_flow_item *item,
6871                            int inner)
6872 {
6873         const struct rte_flow_item_tcp *tcp_m = item->mask;
6874         const struct rte_flow_item_tcp *tcp_v = item->spec;
6875         void *headers_m;
6876         void *headers_v;
6877
6878         if (inner) {
6879                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6880                                          inner_headers);
6881                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6882         } else {
6883                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6884                                          outer_headers);
6885                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6886         }
6887         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6888         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6889         if (!tcp_v)
6890                 return;
6891         if (!tcp_m)
6892                 tcp_m = &rte_flow_item_tcp_mask;
6893         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6894                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6895         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6896                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6897         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6898                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6899         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6900                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6901         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6902                  tcp_m->hdr.tcp_flags);
6903         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6904                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6905 }
6906
6907 /**
6908  * Add UDP item to matcher and to the value.
6909  *
6910  * @param[in, out] matcher
6911  *   Flow matcher.
6912  * @param[in, out] key
6913  *   Flow matcher value.
6914  * @param[in] item
6915  *   Flow pattern to translate.
6916  * @param[in] inner
6917  *   Item is inner pattern.
6918  */
6919 static void
6920 flow_dv_translate_item_udp(void *matcher, void *key,
6921                            const struct rte_flow_item *item,
6922                            int inner)
6923 {
6924         const struct rte_flow_item_udp *udp_m = item->mask;
6925         const struct rte_flow_item_udp *udp_v = item->spec;
6926         void *headers_m;
6927         void *headers_v;
6928
6929         if (inner) {
6930                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6931                                          inner_headers);
6932                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6933         } else {
6934                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6935                                          outer_headers);
6936                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6937         }
6938         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6939         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6940         if (!udp_v)
6941                 return;
6942         if (!udp_m)
6943                 udp_m = &rte_flow_item_udp_mask;
6944         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6945                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6946         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6947                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6948         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6949                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6950         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6951                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6952 }
6953
6954 /**
6955  * Add GRE optional Key item to matcher and to the value.
6956  *
6957  * @param[in, out] matcher
6958  *   Flow matcher.
6959  * @param[in, out] key
6960  *   Flow matcher value.
6961  * @param[in] item
6962  *   Flow pattern to translate.
6963  * @param[in] inner
6964  *   Item is inner pattern.
6965  */
6966 static void
6967 flow_dv_translate_item_gre_key(void *matcher, void *key,
6968                                    const struct rte_flow_item *item)
6969 {
6970         const rte_be32_t *key_m = item->mask;
6971         const rte_be32_t *key_v = item->spec;
6972         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6973         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6974         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6975
6976         /* GRE K bit must be on and should already be validated */
6977         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6978         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6979         if (!key_v)
6980                 return;
6981         if (!key_m)
6982                 key_m = &gre_key_default_mask;
6983         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6984                  rte_be_to_cpu_32(*key_m) >> 8);
6985         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6986                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6987         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6988                  rte_be_to_cpu_32(*key_m) & 0xFF);
6989         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6990                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6991 }
6992
6993 /**
6994  * Add GRE item to matcher and to the value.
6995  *
6996  * @param[in, out] matcher
6997  *   Flow matcher.
6998  * @param[in, out] key
6999  *   Flow matcher value.
7000  * @param[in] item
7001  *   Flow pattern to translate.
7002  * @param[in] inner
7003  *   Item is inner pattern.
7004  */
7005 static void
7006 flow_dv_translate_item_gre(void *matcher, void *key,
7007                            const struct rte_flow_item *item,
7008                            int inner)
7009 {
7010         const struct rte_flow_item_gre *gre_m = item->mask;
7011         const struct rte_flow_item_gre *gre_v = item->spec;
7012         void *headers_m;
7013         void *headers_v;
7014         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7015         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7016         struct {
7017                 union {
7018                         __extension__
7019                         struct {
7020                                 uint16_t version:3;
7021                                 uint16_t rsvd0:9;
7022                                 uint16_t s_present:1;
7023                                 uint16_t k_present:1;
7024                                 uint16_t rsvd_bit1:1;
7025                                 uint16_t c_present:1;
7026                         };
7027                         uint16_t value;
7028                 };
7029         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7030
7031         if (inner) {
7032                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7033                                          inner_headers);
7034                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7035         } else {
7036                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7037                                          outer_headers);
7038                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7039         }
7040         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7041         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7042         if (!gre_v)
7043                 return;
7044         if (!gre_m)
7045                 gre_m = &rte_flow_item_gre_mask;
7046         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7047                  rte_be_to_cpu_16(gre_m->protocol));
7048         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7049                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7050         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7051         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7052         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7053                  gre_crks_rsvd0_ver_m.c_present);
7054         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7055                  gre_crks_rsvd0_ver_v.c_present &
7056                  gre_crks_rsvd0_ver_m.c_present);
7057         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7058                  gre_crks_rsvd0_ver_m.k_present);
7059         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7060                  gre_crks_rsvd0_ver_v.k_present &
7061                  gre_crks_rsvd0_ver_m.k_present);
7062         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7063                  gre_crks_rsvd0_ver_m.s_present);
7064         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7065                  gre_crks_rsvd0_ver_v.s_present &
7066                  gre_crks_rsvd0_ver_m.s_present);
7067 }
7068
7069 /**
7070  * Add NVGRE item to matcher and to the value.
7071  *
7072  * @param[in, out] matcher
7073  *   Flow matcher.
7074  * @param[in, out] key
7075  *   Flow matcher value.
7076  * @param[in] item
7077  *   Flow pattern to translate.
7078  * @param[in] inner
7079  *   Item is inner pattern.
7080  */
7081 static void
7082 flow_dv_translate_item_nvgre(void *matcher, void *key,
7083                              const struct rte_flow_item *item,
7084                              int inner)
7085 {
7086         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7087         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7088         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7089         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7090         const char *tni_flow_id_m;
7091         const char *tni_flow_id_v;
7092         char *gre_key_m;
7093         char *gre_key_v;
7094         int size;
7095         int i;
7096
7097         /* For NVGRE, GRE header fields must be set with defined values. */
7098         const struct rte_flow_item_gre gre_spec = {
7099                 .c_rsvd0_ver = RTE_BE16(0x2000),
7100                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7101         };
7102         const struct rte_flow_item_gre gre_mask = {
7103                 .c_rsvd0_ver = RTE_BE16(0xB000),
7104                 .protocol = RTE_BE16(UINT16_MAX),
7105         };
7106         const struct rte_flow_item gre_item = {
7107                 .spec = &gre_spec,
7108                 .mask = &gre_mask,
7109                 .last = NULL,
7110         };
7111         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7112         if (!nvgre_v)
7113                 return;
7114         if (!nvgre_m)
7115                 nvgre_m = &rte_flow_item_nvgre_mask;
7116         tni_flow_id_m = (const char *)nvgre_m->tni;
7117         tni_flow_id_v = (const char *)nvgre_v->tni;
7118         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7119         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7120         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7121         memcpy(gre_key_m, tni_flow_id_m, size);
7122         for (i = 0; i < size; ++i)
7123                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7124 }
7125
7126 /**
7127  * Add VXLAN item to matcher and to the value.
7128  *
7129  * @param[in, out] matcher
7130  *   Flow matcher.
7131  * @param[in, out] key
7132  *   Flow matcher value.
7133  * @param[in] item
7134  *   Flow pattern to translate.
7135  * @param[in] inner
7136  *   Item is inner pattern.
7137  */
7138 static void
7139 flow_dv_translate_item_vxlan(void *matcher, void *key,
7140                              const struct rte_flow_item *item,
7141                              int inner)
7142 {
7143         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7144         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7145         void *headers_m;
7146         void *headers_v;
7147         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7148         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7149         char *vni_m;
7150         char *vni_v;
7151         uint16_t dport;
7152         int size;
7153         int i;
7154
7155         if (inner) {
7156                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7157                                          inner_headers);
7158                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7159         } else {
7160                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7161                                          outer_headers);
7162                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7163         }
7164         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7165                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7166         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7167                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7168                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7169         }
7170         if (!vxlan_v)
7171                 return;
7172         if (!vxlan_m)
7173                 vxlan_m = &rte_flow_item_vxlan_mask;
7174         size = sizeof(vxlan_m->vni);
7175         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7176         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7177         memcpy(vni_m, vxlan_m->vni, size);
7178         for (i = 0; i < size; ++i)
7179                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7180 }
7181
7182 /**
7183  * Add VXLAN-GPE item to matcher and to the value.
7184  *
7185  * @param[in, out] matcher
7186  *   Flow matcher.
7187  * @param[in, out] key
7188  *   Flow matcher value.
7189  * @param[in] item
7190  *   Flow pattern to translate.
7191  * @param[in] inner
7192  *   Item is inner pattern.
7193  */
7194
7195 static void
7196 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7197                                  const struct rte_flow_item *item, int inner)
7198 {
7199         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7200         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7201         void *headers_m;
7202         void *headers_v;
7203         void *misc_m =
7204                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7205         void *misc_v =
7206                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7207         char *vni_m;
7208         char *vni_v;
7209         uint16_t dport;
7210         int size;
7211         int i;
7212         uint8_t flags_m = 0xff;
7213         uint8_t flags_v = 0xc;
7214
7215         if (inner) {
7216                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7217                                          inner_headers);
7218                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7219         } else {
7220                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7221                                          outer_headers);
7222                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7223         }
7224         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7225                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7226         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7227                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7228                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7229         }
7230         if (!vxlan_v)
7231                 return;
7232         if (!vxlan_m)
7233                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7234         size = sizeof(vxlan_m->vni);
7235         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7236         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7237         memcpy(vni_m, vxlan_m->vni, size);
7238         for (i = 0; i < size; ++i)
7239                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7240         if (vxlan_m->flags) {
7241                 flags_m = vxlan_m->flags;
7242                 flags_v = vxlan_v->flags;
7243         }
7244         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7245         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7246         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7247                  vxlan_m->protocol);
7248         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7249                  vxlan_v->protocol);
7250 }
7251
7252 /**
7253  * Add Geneve item to matcher and to the value.
7254  *
7255  * @param[in, out] matcher
7256  *   Flow matcher.
7257  * @param[in, out] key
7258  *   Flow matcher value.
7259  * @param[in] item
7260  *   Flow pattern to translate.
7261  * @param[in] inner
7262  *   Item is inner pattern.
7263  */
7264
7265 static void
7266 flow_dv_translate_item_geneve(void *matcher, void *key,
7267                               const struct rte_flow_item *item, int inner)
7268 {
7269         const struct rte_flow_item_geneve *geneve_m = item->mask;
7270         const struct rte_flow_item_geneve *geneve_v = item->spec;
7271         void *headers_m;
7272         void *headers_v;
7273         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7274         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7275         uint16_t dport;
7276         uint16_t gbhdr_m;
7277         uint16_t gbhdr_v;
7278         char *vni_m;
7279         char *vni_v;
7280         size_t size, i;
7281
7282         if (inner) {
7283                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7284                                          inner_headers);
7285                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7286         } else {
7287                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7288                                          outer_headers);
7289                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7290         }
7291         dport = MLX5_UDP_PORT_GENEVE;
7292         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7293                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7294                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7295         }
7296         if (!geneve_v)
7297                 return;
7298         if (!geneve_m)
7299                 geneve_m = &rte_flow_item_geneve_mask;
7300         size = sizeof(geneve_m->vni);
7301         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7302         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7303         memcpy(vni_m, geneve_m->vni, size);
7304         for (i = 0; i < size; ++i)
7305                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7306         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7307                  rte_be_to_cpu_16(geneve_m->protocol));
7308         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7309                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7310         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7311         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7312         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7313                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7314         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7315                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7316         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7317                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7318         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7319                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7320                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7321 }
7322
7323 /**
7324  * Add MPLS item to matcher and to the value.
7325  *
7326  * @param[in, out] matcher
7327  *   Flow matcher.
7328  * @param[in, out] key
7329  *   Flow matcher value.
7330  * @param[in] item
7331  *   Flow pattern to translate.
7332  * @param[in] prev_layer
7333  *   The protocol layer indicated in previous item.
7334  * @param[in] inner
7335  *   Item is inner pattern.
7336  */
7337 static void
7338 flow_dv_translate_item_mpls(void *matcher, void *key,
7339                             const struct rte_flow_item *item,
7340                             uint64_t prev_layer,
7341                             int inner)
7342 {
7343         const uint32_t *in_mpls_m = item->mask;
7344         const uint32_t *in_mpls_v = item->spec;
7345         uint32_t *out_mpls_m = 0;
7346         uint32_t *out_mpls_v = 0;
7347         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7348         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7349         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7350                                      misc_parameters_2);
7351         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7352         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7353         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7354
7355         switch (prev_layer) {
7356         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7357                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7358                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7359                          MLX5_UDP_PORT_MPLS);
7360                 break;
7361         case MLX5_FLOW_LAYER_GRE:
7362                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7363                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7364                          RTE_ETHER_TYPE_MPLS);
7365                 break;
7366         default:
7367                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7368                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7369                          IPPROTO_MPLS);
7370                 break;
7371         }
7372         if (!in_mpls_v)
7373                 return;
7374         if (!in_mpls_m)
7375                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7376         switch (prev_layer) {
7377         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7378                 out_mpls_m =
7379                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7380                                                  outer_first_mpls_over_udp);
7381                 out_mpls_v =
7382                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7383                                                  outer_first_mpls_over_udp);
7384                 break;
7385         case MLX5_FLOW_LAYER_GRE:
7386                 out_mpls_m =
7387                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7388                                                  outer_first_mpls_over_gre);
7389                 out_mpls_v =
7390                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7391                                                  outer_first_mpls_over_gre);
7392                 break;
7393         default:
7394                 /* Inner MPLS not over GRE is not supported. */
7395                 if (!inner) {
7396                         out_mpls_m =
7397                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7398                                                          misc2_m,
7399                                                          outer_first_mpls);
7400                         out_mpls_v =
7401                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7402                                                          misc2_v,
7403                                                          outer_first_mpls);
7404                 }
7405                 break;
7406         }
7407         if (out_mpls_m && out_mpls_v) {
7408                 *out_mpls_m = *in_mpls_m;
7409                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7410         }
7411 }
7412
7413 /**
7414  * Add metadata register item to matcher
7415  *
7416  * @param[in, out] matcher
7417  *   Flow matcher.
7418  * @param[in, out] key
7419  *   Flow matcher value.
7420  * @param[in] reg_type
7421  *   Type of device metadata register
7422  * @param[in] value
7423  *   Register value
7424  * @param[in] mask
7425  *   Register mask
7426  */
7427 static void
7428 flow_dv_match_meta_reg(void *matcher, void *key,
7429                        enum modify_reg reg_type,
7430                        uint32_t data, uint32_t mask)
7431 {
7432         void *misc2_m =
7433                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7434         void *misc2_v =
7435                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7436         uint32_t temp;
7437
7438         data &= mask;
7439         switch (reg_type) {
7440         case REG_A:
7441                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7442                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7443                 break;
7444         case REG_B:
7445                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7446                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7447                 break;
7448         case REG_C_0:
7449                 /*
7450                  * The metadata register C0 field might be divided into
7451                  * source vport index and META item value, we should set
7452                  * this field according to specified mask, not as whole one.
7453                  */
7454                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7455                 temp |= mask;
7456                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7457                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7458                 temp &= ~mask;
7459                 temp |= data;
7460                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7461                 break;
7462         case REG_C_1:
7463                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7464                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7465                 break;
7466         case REG_C_2:
7467                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7468                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7469                 break;
7470         case REG_C_3:
7471                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7472                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7473                 break;
7474         case REG_C_4:
7475                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7476                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7477                 break;
7478         case REG_C_5:
7479                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7480                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7481                 break;
7482         case REG_C_6:
7483                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7484                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7485                 break;
7486         case REG_C_7:
7487                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7488                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7489                 break;
7490         default:
7491                 MLX5_ASSERT(false);
7492                 break;
7493         }
7494 }
7495
7496 /**
7497  * Add MARK item to matcher
7498  *
7499  * @param[in] dev
7500  *   The device to configure through.
7501  * @param[in, out] matcher
7502  *   Flow matcher.
7503  * @param[in, out] key
7504  *   Flow matcher value.
7505  * @param[in] item
7506  *   Flow pattern to translate.
7507  */
7508 static void
7509 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7510                             void *matcher, void *key,
7511                             const struct rte_flow_item *item)
7512 {
7513         struct mlx5_priv *priv = dev->data->dev_private;
7514         const struct rte_flow_item_mark *mark;
7515         uint32_t value;
7516         uint32_t mask;
7517
7518         mark = item->mask ? (const void *)item->mask :
7519                             &rte_flow_item_mark_mask;
7520         mask = mark->id & priv->sh->dv_mark_mask;
7521         mark = (const void *)item->spec;
7522         MLX5_ASSERT(mark);
7523         value = mark->id & priv->sh->dv_mark_mask & mask;
7524         if (mask) {
7525                 enum modify_reg reg;
7526
7527                 /* Get the metadata register index for the mark. */
7528                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7529                 MLX5_ASSERT(reg > 0);
7530                 if (reg == REG_C_0) {
7531                         struct mlx5_priv *priv = dev->data->dev_private;
7532                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7533                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7534
7535                         mask &= msk_c0;
7536                         mask <<= shl_c0;
7537                         value <<= shl_c0;
7538                 }
7539                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7540         }
7541 }
7542
7543 /**
7544  * Add META item to matcher
7545  *
7546  * @param[in] dev
7547  *   The devich to configure through.
7548  * @param[in, out] matcher
7549  *   Flow matcher.
7550  * @param[in, out] key
7551  *   Flow matcher value.
7552  * @param[in] attr
7553  *   Attributes of flow that includes this item.
7554  * @param[in] item
7555  *   Flow pattern to translate.
7556  */
7557 static void
7558 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7559                             void *matcher, void *key,
7560                             const struct rte_flow_attr *attr,
7561                             const struct rte_flow_item *item)
7562 {
7563         const struct rte_flow_item_meta *meta_m;
7564         const struct rte_flow_item_meta *meta_v;
7565
7566         meta_m = (const void *)item->mask;
7567         if (!meta_m)
7568                 meta_m = &rte_flow_item_meta_mask;
7569         meta_v = (const void *)item->spec;
7570         if (meta_v) {
7571                 int reg;
7572                 uint32_t value = meta_v->data;
7573                 uint32_t mask = meta_m->data;
7574
7575                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7576                 if (reg < 0)
7577                         return;
7578                 MLX5_ASSERT(reg != REG_NON);
7579                 /*
7580                  * In datapath code there is no endianness
7581                  * coversions for perfromance reasons, all
7582                  * pattern conversions are done in rte_flow.
7583                  */
7584                 value = rte_cpu_to_be_32(value);
7585                 mask = rte_cpu_to_be_32(mask);
7586                 if (reg == REG_C_0) {
7587                         struct mlx5_priv *priv = dev->data->dev_private;
7588                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7589                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7590 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7591                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7592
7593                         value >>= shr_c0;
7594                         mask >>= shr_c0;
7595 #endif
7596                         value <<= shl_c0;
7597                         mask <<= shl_c0;
7598                         MLX5_ASSERT(msk_c0);
7599                         MLX5_ASSERT(!(~msk_c0 & mask));
7600                 }
7601                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7602         }
7603 }
7604
7605 /**
7606  * Add vport metadata Reg C0 item to matcher
7607  *
7608  * @param[in, out] matcher
7609  *   Flow matcher.
7610  * @param[in, out] key
7611  *   Flow matcher value.
7612  * @param[in] reg
7613  *   Flow pattern to translate.
7614  */
7615 static void
7616 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7617                                   uint32_t value, uint32_t mask)
7618 {
7619         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7620 }
7621
7622 /**
7623  * Add tag item to matcher
7624  *
7625  * @param[in] dev
7626  *   The devich to configure through.
7627  * @param[in, out] matcher
7628  *   Flow matcher.
7629  * @param[in, out] key
7630  *   Flow matcher value.
7631  * @param[in] item
7632  *   Flow pattern to translate.
7633  */
7634 static void
7635 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7636                                 void *matcher, void *key,
7637                                 const struct rte_flow_item *item)
7638 {
7639         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7640         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7641         uint32_t mask, value;
7642
7643         MLX5_ASSERT(tag_v);
7644         value = tag_v->data;
7645         mask = tag_m ? tag_m->data : UINT32_MAX;
7646         if (tag_v->id == REG_C_0) {
7647                 struct mlx5_priv *priv = dev->data->dev_private;
7648                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7649                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7650
7651                 mask &= msk_c0;
7652                 mask <<= shl_c0;
7653                 value <<= shl_c0;
7654         }
7655         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7656 }
7657
7658 /**
7659  * Add TAG item to matcher
7660  *
7661  * @param[in] dev
7662  *   The devich to configure through.
7663  * @param[in, out] matcher
7664  *   Flow matcher.
7665  * @param[in, out] key
7666  *   Flow matcher value.
7667  * @param[in] item
7668  *   Flow pattern to translate.
7669  */
7670 static void
7671 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7672                            void *matcher, void *key,
7673                            const struct rte_flow_item *item)
7674 {
7675         const struct rte_flow_item_tag *tag_v = item->spec;
7676         const struct rte_flow_item_tag *tag_m = item->mask;
7677         enum modify_reg reg;
7678
7679         MLX5_ASSERT(tag_v);
7680         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7681         /* Get the metadata register index for the tag. */
7682         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7683         MLX5_ASSERT(reg > 0);
7684         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7685 }
7686
7687 /**
7688  * Add source vport match to the specified matcher.
7689  *
7690  * @param[in, out] matcher
7691  *   Flow matcher.
7692  * @param[in, out] key
7693  *   Flow matcher value.
7694  * @param[in] port
7695  *   Source vport value to match
7696  * @param[in] mask
7697  *   Mask
7698  */
7699 static void
7700 flow_dv_translate_item_source_vport(void *matcher, void *key,
7701                                     int16_t port, uint16_t mask)
7702 {
7703         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7704         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7705
7706         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7707         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7708 }
7709
7710 /**
7711  * Translate port-id item to eswitch match on  port-id.
7712  *
7713  * @param[in] dev
7714  *   The devich to configure through.
7715  * @param[in, out] matcher
7716  *   Flow matcher.
7717  * @param[in, out] key
7718  *   Flow matcher value.
7719  * @param[in] item
7720  *   Flow pattern to translate.
7721  * @param[in]
7722  *   Flow attributes.
7723  *
7724  * @return
7725  *   0 on success, a negative errno value otherwise.
7726  */
7727 static int
7728 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7729                                void *key, const struct rte_flow_item *item,
7730                                const struct rte_flow_attr *attr)
7731 {
7732         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7733         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7734         struct mlx5_priv *priv;
7735         uint16_t mask, id;
7736
7737         mask = pid_m ? pid_m->id : 0xffff;
7738         id = pid_v ? pid_v->id : dev->data->port_id;
7739         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7740         if (!priv)
7741                 return -rte_errno;
7742         /*
7743          * Translate to vport field or to metadata, depending on mode.
7744          * Kernel can use either misc.source_port or half of C0 metadata
7745          * register.
7746          */
7747         if (priv->vport_meta_mask) {
7748                 /*
7749                  * Provide the hint for SW steering library
7750                  * to insert the flow into ingress domain and
7751                  * save the extra vport match.
7752                  */
7753                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7754                     priv->pf_bond < 0 && attr->transfer)
7755                         flow_dv_translate_item_source_vport
7756                                 (matcher, key, priv->vport_id, mask);
7757                 else
7758                         flow_dv_translate_item_meta_vport
7759                                 (matcher, key,
7760                                  priv->vport_meta_tag,
7761                                  priv->vport_meta_mask);
7762         } else {
7763                 flow_dv_translate_item_source_vport(matcher, key,
7764                                                     priv->vport_id, mask);
7765         }
7766         return 0;
7767 }
7768
7769 /**
7770  * Add ICMP6 item to matcher and to the value.
7771  *
7772  * @param[in, out] matcher
7773  *   Flow matcher.
7774  * @param[in, out] key
7775  *   Flow matcher value.
7776  * @param[in] item
7777  *   Flow pattern to translate.
7778  * @param[in] inner
7779  *   Item is inner pattern.
7780  */
7781 static void
7782 flow_dv_translate_item_icmp6(void *matcher, void *key,
7783                               const struct rte_flow_item *item,
7784                               int inner)
7785 {
7786         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7787         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7788         void *headers_m;
7789         void *headers_v;
7790         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7791                                      misc_parameters_3);
7792         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7793         if (inner) {
7794                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7795                                          inner_headers);
7796                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7797         } else {
7798                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7799                                          outer_headers);
7800                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7801         }
7802         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7803         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7804         if (!icmp6_v)
7805                 return;
7806         if (!icmp6_m)
7807                 icmp6_m = &rte_flow_item_icmp6_mask;
7808         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7809         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7810                  icmp6_v->type & icmp6_m->type);
7811         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7812         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7813                  icmp6_v->code & icmp6_m->code);
7814 }
7815
7816 /**
7817  * Add ICMP item to matcher and to the value.
7818  *
7819  * @param[in, out] matcher
7820  *   Flow matcher.
7821  * @param[in, out] key
7822  *   Flow matcher value.
7823  * @param[in] item
7824  *   Flow pattern to translate.
7825  * @param[in] inner
7826  *   Item is inner pattern.
7827  */
7828 static void
7829 flow_dv_translate_item_icmp(void *matcher, void *key,
7830                             const struct rte_flow_item *item,
7831                             int inner)
7832 {
7833         const struct rte_flow_item_icmp *icmp_m = item->mask;
7834         const struct rte_flow_item_icmp *icmp_v = item->spec;
7835         uint32_t icmp_header_data_m = 0;
7836         uint32_t icmp_header_data_v = 0;
7837         void *headers_m;
7838         void *headers_v;
7839         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7840                                      misc_parameters_3);
7841         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7842         if (inner) {
7843                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7844                                          inner_headers);
7845                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7846         } else {
7847                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7848                                          outer_headers);
7849                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7850         }
7851         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7852         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7853         if (!icmp_v)
7854                 return;
7855         if (!icmp_m)
7856                 icmp_m = &rte_flow_item_icmp_mask;
7857         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7858                  icmp_m->hdr.icmp_type);
7859         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7860                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7861         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7862                  icmp_m->hdr.icmp_code);
7863         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7864                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7865         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7866         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7867         if (icmp_header_data_m) {
7868                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7869                 icmp_header_data_v |=
7870                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7871                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7872                          icmp_header_data_m);
7873                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7874                          icmp_header_data_v & icmp_header_data_m);
7875         }
7876 }
7877
7878 /**
7879  * Add GTP item to matcher and to the value.
7880  *
7881  * @param[in, out] matcher
7882  *   Flow matcher.
7883  * @param[in, out] key
7884  *   Flow matcher value.
7885  * @param[in] item
7886  *   Flow pattern to translate.
7887  * @param[in] inner
7888  *   Item is inner pattern.
7889  */
7890 static void
7891 flow_dv_translate_item_gtp(void *matcher, void *key,
7892                            const struct rte_flow_item *item, int inner)
7893 {
7894         const struct rte_flow_item_gtp *gtp_m = item->mask;
7895         const struct rte_flow_item_gtp *gtp_v = item->spec;
7896         void *headers_m;
7897         void *headers_v;
7898         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7899                                      misc_parameters_3);
7900         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7901         uint16_t dport = RTE_GTPU_UDP_PORT;
7902
7903         if (inner) {
7904                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7905                                          inner_headers);
7906                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7907         } else {
7908                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7909                                          outer_headers);
7910                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7911         }
7912         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7913                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7914                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7915         }
7916         if (!gtp_v)
7917                 return;
7918         if (!gtp_m)
7919                 gtp_m = &rte_flow_item_gtp_mask;
7920         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7921                  gtp_m->v_pt_rsv_flags);
7922         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7923                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7924         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7925         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7926                  gtp_v->msg_type & gtp_m->msg_type);
7927         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7928                  rte_be_to_cpu_32(gtp_m->teid));
7929         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7930                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7931 }
7932
7933 /**
7934  * Add GTP PSC item to matcher.
7935  *
7936  * @param[in, out] matcher
7937  *   Flow matcher.
7938  * @param[in, out] key
7939  *   Flow matcher value.
7940  * @param[in] item
7941  *   Flow pattern to translate.
7942  */
7943 static int
7944 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
7945                                const struct rte_flow_item *item)
7946 {
7947         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
7948         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
7949         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7950                         misc_parameters_3);
7951         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7952         union {
7953                 uint32_t w32;
7954                 struct {
7955                         uint16_t seq_num;
7956                         uint8_t npdu_num;
7957                         uint8_t next_ext_header_type;
7958                 };
7959         } dw_2;
7960         uint8_t gtp_flags;
7961
7962         /* Always set E-flag match on one, regardless of GTP item settings. */
7963         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
7964         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
7965         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
7966         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
7967         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
7968         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
7969         /*Set next extension header type. */
7970         dw_2.seq_num = 0;
7971         dw_2.npdu_num = 0;
7972         dw_2.next_ext_header_type = 0xff;
7973         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
7974                  rte_cpu_to_be_32(dw_2.w32));
7975         dw_2.seq_num = 0;
7976         dw_2.npdu_num = 0;
7977         dw_2.next_ext_header_type = 0x85;
7978         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
7979                  rte_cpu_to_be_32(dw_2.w32));
7980         if (gtp_psc_v) {
7981                 union {
7982                         uint32_t w32;
7983                         struct {
7984                                 uint8_t len;
7985                                 uint8_t type_flags;
7986                                 uint8_t qfi;
7987                                 uint8_t reserved;
7988                         };
7989                 } dw_0;
7990
7991                 /*Set extension header PDU type and Qos. */
7992                 if (!gtp_psc_m)
7993                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
7994                 dw_0.w32 = 0;
7995                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
7996                 dw_0.qfi = gtp_psc_m->qfi;
7997                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
7998                          rte_cpu_to_be_32(dw_0.w32));
7999                 dw_0.w32 = 0;
8000                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8001                                                         gtp_psc_m->pdu_type);
8002                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8003                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8004                          rte_cpu_to_be_32(dw_0.w32));
8005         }
8006         return 0;
8007 }
8008
8009 /**
8010  * Add eCPRI item to matcher and to the value.
8011  *
8012  * @param[in] dev
8013  *   The devich to configure through.
8014  * @param[in, out] matcher
8015  *   Flow matcher.
8016  * @param[in, out] key
8017  *   Flow matcher value.
8018  * @param[in] item
8019  *   Flow pattern to translate.
8020  * @param[in] samples
8021  *   Sample IDs to be used in the matching.
8022  */
8023 static void
8024 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8025                              void *key, const struct rte_flow_item *item)
8026 {
8027         struct mlx5_priv *priv = dev->data->dev_private;
8028         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8029         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8030         struct rte_ecpri_common_hdr common;
8031         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8032                                      misc_parameters_4);
8033         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8034         uint32_t *samples;
8035         void *dw_m;
8036         void *dw_v;
8037
8038         if (!ecpri_v)
8039                 return;
8040         if (!ecpri_m)
8041                 ecpri_m = &rte_flow_item_ecpri_mask;
8042         /*
8043          * Maximal four DW samples are supported in a single matching now.
8044          * Two are used now for a eCPRI matching:
8045          * 1. Type: one byte, mask should be 0x00ff0000 in network order
8046          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8047          *    if any.
8048          */
8049         if (!ecpri_m->hdr.common.u32)
8050                 return;
8051         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8052         /* Need to take the whole DW as the mask to fill the entry. */
8053         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8054                             prog_sample_field_value_0);
8055         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8056                             prog_sample_field_value_0);
8057         /* Already big endian (network order) in the header. */
8058         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8059         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8060         /* Sample#0, used for matching type, offset 0. */
8061         MLX5_SET(fte_match_set_misc4, misc4_m,
8062                  prog_sample_field_id_0, samples[0]);
8063         /* It makes no sense to set the sample ID in the mask field. */
8064         MLX5_SET(fte_match_set_misc4, misc4_v,
8065                  prog_sample_field_id_0, samples[0]);
8066         /*
8067          * Checking if message body part needs to be matched.
8068          * Some wildcard rules only matching type field should be supported.
8069          */
8070         if (ecpri_m->hdr.dummy[0]) {
8071                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8072                 switch (common.type) {
8073                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8074                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8075                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8076                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8077                                             prog_sample_field_value_1);
8078                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8079                                             prog_sample_field_value_1);
8080                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8081                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8082                                             ecpri_m->hdr.dummy[0];
8083                         /* Sample#1, to match message body, offset 4. */
8084                         MLX5_SET(fte_match_set_misc4, misc4_m,
8085                                  prog_sample_field_id_1, samples[1]);
8086                         MLX5_SET(fte_match_set_misc4, misc4_v,
8087                                  prog_sample_field_id_1, samples[1]);
8088                         break;
8089                 default:
8090                         /* Others, do not match any sample ID. */
8091                         break;
8092                 }
8093         }
8094 }
8095
8096 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8097
8098 #define HEADER_IS_ZERO(match_criteria, headers)                              \
8099         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
8100                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8101
8102 /**
8103  * Calculate flow matcher enable bitmap.
8104  *
8105  * @param match_criteria
8106  *   Pointer to flow matcher criteria.
8107  *
8108  * @return
8109  *   Bitmap of enabled fields.
8110  */
8111 static uint8_t
8112 flow_dv_matcher_enable(uint32_t *match_criteria)
8113 {
8114         uint8_t match_criteria_enable;
8115
8116         match_criteria_enable =
8117                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8118                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8119         match_criteria_enable |=
8120                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8121                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8122         match_criteria_enable |=
8123                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8124                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8125         match_criteria_enable |=
8126                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8127                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8128         match_criteria_enable |=
8129                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8130                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8131         match_criteria_enable |=
8132                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8133                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8134         return match_criteria_enable;
8135 }
8136
8137 struct mlx5_hlist_entry *
8138 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8139 {
8140         struct mlx5_dev_ctx_shared *sh = list->ctx;
8141         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8142         struct rte_eth_dev *dev = ctx->dev;
8143         struct mlx5_flow_tbl_data_entry *tbl_data;
8144         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8145         struct rte_flow_error *error = ctx->error;
8146         union mlx5_flow_tbl_key key = { .v64 = key64 };
8147         struct mlx5_flow_tbl_resource *tbl;
8148         void *domain;
8149         uint32_t idx = 0;
8150         int ret;
8151
8152         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8153         if (!tbl_data) {
8154                 rte_flow_error_set(error, ENOMEM,
8155                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8156                                    NULL,
8157                                    "cannot allocate flow table data entry");
8158                 return NULL;
8159         }
8160         tbl_data->idx = idx;
8161         tbl_data->tunnel = tt_prm->tunnel;
8162         tbl_data->group_id = tt_prm->group_id;
8163         tbl_data->external = !!tt_prm->external;
8164         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8165         tbl_data->is_egress = !!key.direction;
8166         tbl_data->is_transfer = !!key.domain;
8167         tbl_data->dummy = !!key.dummy;
8168         tbl_data->table_id = key.table_id;
8169         tbl = &tbl_data->tbl;
8170         if (key.dummy)
8171                 return &tbl_data->entry;
8172         if (key.domain)
8173                 domain = sh->fdb_domain;
8174         else if (key.direction)
8175                 domain = sh->tx_domain;
8176         else
8177                 domain = sh->rx_domain;
8178         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8179         if (ret) {
8180                 rte_flow_error_set(error, ENOMEM,
8181                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8182                                    NULL, "cannot create flow table object");
8183                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8184                 return NULL;
8185         }
8186         if (key.table_id) {
8187                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8188                                         (tbl->obj, &tbl_data->jump.action);
8189                 if (ret) {
8190                         rte_flow_error_set(error, ENOMEM,
8191                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8192                                            NULL,
8193                                            "cannot create flow jump action");
8194                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8195                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8196                         return NULL;
8197                 }
8198         }
8199         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8200               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8201               key.table_id);
8202         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8203                              flow_dv_matcher_create_cb,
8204                              flow_dv_matcher_match_cb,
8205                              flow_dv_matcher_remove_cb);
8206         return &tbl_data->entry;
8207 }
8208
8209 int
8210 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8211                      struct mlx5_hlist_entry *entry, uint64_t key64,
8212                      void *cb_ctx __rte_unused)
8213 {
8214         struct mlx5_flow_tbl_data_entry *tbl_data =
8215                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8216         union mlx5_flow_tbl_key key = { .v64 = key64 };
8217
8218         return tbl_data->table_id != key.table_id ||
8219                tbl_data->dummy != key.dummy ||
8220                tbl_data->is_transfer != key.domain ||
8221                tbl_data->is_egress != key.direction;
8222 }
8223
8224 /**
8225  * Get a flow table.
8226  *
8227  * @param[in, out] dev
8228  *   Pointer to rte_eth_dev structure.
8229  * @param[in] table_id
8230  *   Table id to use.
8231  * @param[in] egress
8232  *   Direction of the table.
8233  * @param[in] transfer
8234  *   E-Switch or NIC flow.
8235  * @param[in] dummy
8236  *   Dummy entry for dv API.
8237  * @param[out] error
8238  *   pointer to error structure.
8239  *
8240  * @return
8241  *   Returns tables resource based on the index, NULL in case of failed.
8242  */
8243 struct mlx5_flow_tbl_resource *
8244 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8245                          uint32_t table_id, uint8_t egress,
8246                          uint8_t transfer,
8247                          bool external,
8248                          const struct mlx5_flow_tunnel *tunnel,
8249                          uint32_t group_id, uint8_t dummy,
8250                          struct rte_flow_error *error)
8251 {
8252         struct mlx5_priv *priv = dev->data->dev_private;
8253         union mlx5_flow_tbl_key table_key = {
8254                 {
8255                         .table_id = table_id,
8256                         .dummy = dummy,
8257                         .domain = !!transfer,
8258                         .direction = !!egress,
8259                 }
8260         };
8261         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8262                 .tunnel = tunnel,
8263                 .group_id = group_id,
8264                 .external = external,
8265         };
8266         struct mlx5_flow_cb_ctx ctx = {
8267                 .dev = dev,
8268                 .error = error,
8269                 .data = &tt_prm,
8270         };
8271         struct mlx5_hlist_entry *entry;
8272         struct mlx5_flow_tbl_data_entry *tbl_data;
8273
8274         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8275         if (!entry) {
8276                 rte_flow_error_set(error, ENOMEM,
8277                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8278                                    "cannot get table");
8279                 return NULL;
8280         }
8281         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8282                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8283         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8284         return &tbl_data->tbl;
8285 }
8286
8287 void
8288 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8289                       struct mlx5_hlist_entry *entry)
8290 {
8291         struct mlx5_dev_ctx_shared *sh = list->ctx;
8292         struct mlx5_flow_tbl_data_entry *tbl_data =
8293                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8294
8295         MLX5_ASSERT(entry && sh);
8296         if (tbl_data->jump.action)
8297                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8298         if (tbl_data->tbl.obj)
8299                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8300         if (tbl_data->tunnel_offload && tbl_data->external) {
8301                 struct mlx5_hlist_entry *he;
8302                 struct mlx5_hlist *tunnel_grp_hash;
8303                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8304                 union tunnel_tbl_key tunnel_key = {
8305                         .tunnel_id = tbl_data->tunnel ?
8306                                         tbl_data->tunnel->tunnel_id : 0,
8307                         .group = tbl_data->group_id
8308                 };
8309                 uint32_t table_id = tbl_data->table_id;
8310
8311                 tunnel_grp_hash = tbl_data->tunnel ?
8312                                         tbl_data->tunnel->groups :
8313                                         thub->groups;
8314                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8315                 if (he)
8316                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8317                 DRV_LOG(DEBUG,
8318                         "Table_id %u tunnel %u group %u released.",
8319                         table_id,
8320                         tbl_data->tunnel ?
8321                         tbl_data->tunnel->tunnel_id : 0,
8322                         tbl_data->group_id);
8323         }
8324         mlx5_cache_list_destroy(&tbl_data->matchers);
8325         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8326 }
8327
8328 /**
8329  * Release a flow table.
8330  *
8331  * @param[in] sh
8332  *   Pointer to device shared structure.
8333  * @param[in] tbl
8334  *   Table resource to be released.
8335  *
8336  * @return
8337  *   Returns 0 if table was released, else return 1;
8338  */
8339 static int
8340 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8341                              struct mlx5_flow_tbl_resource *tbl)
8342 {
8343         struct mlx5_flow_tbl_data_entry *tbl_data =
8344                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8345
8346         if (!tbl)
8347                 return 0;
8348         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8349 }
8350
8351 int
8352 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8353                          struct mlx5_cache_entry *entry, void *cb_ctx)
8354 {
8355         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8356         struct mlx5_flow_dv_matcher *ref = ctx->data;
8357         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8358                                                         entry);
8359
8360         return cur->crc != ref->crc ||
8361                cur->priority != ref->priority ||
8362                memcmp((const void *)cur->mask.buf,
8363                       (const void *)ref->mask.buf, ref->mask.size);
8364 }
8365
8366 struct mlx5_cache_entry *
8367 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8368                           struct mlx5_cache_entry *entry __rte_unused,
8369                           void *cb_ctx)
8370 {
8371         struct mlx5_dev_ctx_shared *sh = list->ctx;
8372         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8373         struct mlx5_flow_dv_matcher *ref = ctx->data;
8374         struct mlx5_flow_dv_matcher *cache;
8375         struct mlx5dv_flow_matcher_attr dv_attr = {
8376                 .type = IBV_FLOW_ATTR_NORMAL,
8377                 .match_mask = (void *)&ref->mask,
8378         };
8379         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8380                                                             typeof(*tbl), tbl);
8381         int ret;
8382
8383         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8384         if (!cache) {
8385                 rte_flow_error_set(ctx->error, ENOMEM,
8386                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8387                                    "cannot create matcher");
8388                 return NULL;
8389         }
8390         *cache = *ref;
8391         dv_attr.match_criteria_enable =
8392                 flow_dv_matcher_enable(cache->mask.buf);
8393         dv_attr.priority = ref->priority;
8394         if (tbl->is_egress)
8395                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8396         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8397                                                &cache->matcher_object);
8398         if (ret) {
8399                 mlx5_free(cache);
8400                 rte_flow_error_set(ctx->error, ENOMEM,
8401                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8402                                    "cannot create matcher");
8403                 return NULL;
8404         }
8405         return &cache->entry;
8406 }
8407
8408 /**
8409  * Register the flow matcher.
8410  *
8411  * @param[in, out] dev
8412  *   Pointer to rte_eth_dev structure.
8413  * @param[in, out] matcher
8414  *   Pointer to flow matcher.
8415  * @param[in, out] key
8416  *   Pointer to flow table key.
8417  * @parm[in, out] dev_flow
8418  *   Pointer to the dev_flow.
8419  * @param[out] error
8420  *   pointer to error structure.
8421  *
8422  * @return
8423  *   0 on success otherwise -errno and errno is set.
8424  */
8425 static int
8426 flow_dv_matcher_register(struct rte_eth_dev *dev,
8427                          struct mlx5_flow_dv_matcher *ref,
8428                          union mlx5_flow_tbl_key *key,
8429                          struct mlx5_flow *dev_flow,
8430                          const struct mlx5_flow_tunnel *tunnel,
8431                          uint32_t group_id,
8432                          struct rte_flow_error *error)
8433 {
8434         struct mlx5_cache_entry *entry;
8435         struct mlx5_flow_dv_matcher *cache;
8436         struct mlx5_flow_tbl_resource *tbl;
8437         struct mlx5_flow_tbl_data_entry *tbl_data;
8438         struct mlx5_flow_cb_ctx ctx = {
8439                 .error = error,
8440                 .data = ref,
8441         };
8442
8443         /**
8444          * tunnel offload API requires this registration for cases when
8445          * tunnel match rule was inserted before tunnel set rule.
8446          */
8447         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8448                                        key->direction, key->domain,
8449                                        dev_flow->external, tunnel,
8450                                        group_id, 0, error);
8451         if (!tbl)
8452                 return -rte_errno;      /* No need to refill the error info */
8453         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8454         ref->tbl = tbl;
8455         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8456         if (!entry) {
8457                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8458                 return rte_flow_error_set(error, ENOMEM,
8459                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8460                                           "cannot allocate ref memory");
8461         }
8462         cache = container_of(entry, typeof(*cache), entry);
8463         dev_flow->handle->dvh.matcher = cache;
8464         return 0;
8465 }
8466
8467 struct mlx5_hlist_entry *
8468 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8469 {
8470         struct mlx5_dev_ctx_shared *sh = list->ctx;
8471         struct rte_flow_error *error = ctx;
8472         struct mlx5_flow_dv_tag_resource *entry;
8473         uint32_t idx = 0;
8474         int ret;
8475
8476         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8477         if (!entry) {
8478                 rte_flow_error_set(error, ENOMEM,
8479                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8480                                    "cannot allocate resource memory");
8481                 return NULL;
8482         }
8483         entry->idx = idx;
8484         entry->tag_id = key;
8485         ret = mlx5_flow_os_create_flow_action_tag(key,
8486                                                   &entry->action);
8487         if (ret) {
8488                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8489                 rte_flow_error_set(error, ENOMEM,
8490                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8491                                    NULL, "cannot create action");
8492                 return NULL;
8493         }
8494         return &entry->entry;
8495 }
8496
8497 int
8498 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8499                      struct mlx5_hlist_entry *entry, uint64_t key,
8500                      void *cb_ctx __rte_unused)
8501 {
8502         struct mlx5_flow_dv_tag_resource *tag =
8503                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8504
8505         return key != tag->tag_id;
8506 }
8507
8508 /**
8509  * Find existing tag resource or create and register a new one.
8510  *
8511  * @param dev[in, out]
8512  *   Pointer to rte_eth_dev structure.
8513  * @param[in, out] tag_be24
8514  *   Tag value in big endian then R-shift 8.
8515  * @parm[in, out] dev_flow
8516  *   Pointer to the dev_flow.
8517  * @param[out] error
8518  *   pointer to error structure.
8519  *
8520  * @return
8521  *   0 on success otherwise -errno and errno is set.
8522  */
8523 static int
8524 flow_dv_tag_resource_register
8525                         (struct rte_eth_dev *dev,
8526                          uint32_t tag_be24,
8527                          struct mlx5_flow *dev_flow,
8528                          struct rte_flow_error *error)
8529 {
8530         struct mlx5_priv *priv = dev->data->dev_private;
8531         struct mlx5_flow_dv_tag_resource *cache_resource;
8532         struct mlx5_hlist_entry *entry;
8533
8534         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8535         if (entry) {
8536                 cache_resource = container_of
8537                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8538                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8539                 dev_flow->dv.tag_resource = cache_resource;
8540                 return 0;
8541         }
8542         return -rte_errno;
8543 }
8544
8545 void
8546 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8547                       struct mlx5_hlist_entry *entry)
8548 {
8549         struct mlx5_dev_ctx_shared *sh = list->ctx;
8550         struct mlx5_flow_dv_tag_resource *tag =
8551                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8552
8553         MLX5_ASSERT(tag && sh && tag->action);
8554         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8555         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8556         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8557 }
8558
8559 /**
8560  * Release the tag.
8561  *
8562  * @param dev
8563  *   Pointer to Ethernet device.
8564  * @param tag_idx
8565  *   Tag index.
8566  *
8567  * @return
8568  *   1 while a reference on it exists, 0 when freed.
8569  */
8570 static int
8571 flow_dv_tag_release(struct rte_eth_dev *dev,
8572                     uint32_t tag_idx)
8573 {
8574         struct mlx5_priv *priv = dev->data->dev_private;
8575         struct mlx5_flow_dv_tag_resource *tag;
8576
8577         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8578         if (!tag)
8579                 return 0;
8580         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8581                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8582         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8583 }
8584
8585 /**
8586  * Translate port ID action to vport.
8587  *
8588  * @param[in] dev
8589  *   Pointer to rte_eth_dev structure.
8590  * @param[in] action
8591  *   Pointer to the port ID action.
8592  * @param[out] dst_port_id
8593  *   The target port ID.
8594  * @param[out] error
8595  *   Pointer to the error structure.
8596  *
8597  * @return
8598  *   0 on success, a negative errno value otherwise and rte_errno is set.
8599  */
8600 static int
8601 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8602                                  const struct rte_flow_action *action,
8603                                  uint32_t *dst_port_id,
8604                                  struct rte_flow_error *error)
8605 {
8606         uint32_t port;
8607         struct mlx5_priv *priv;
8608         const struct rte_flow_action_port_id *conf =
8609                         (const struct rte_flow_action_port_id *)action->conf;
8610
8611         port = conf->original ? dev->data->port_id : conf->id;
8612         priv = mlx5_port_to_eswitch_info(port, false);
8613         if (!priv)
8614                 return rte_flow_error_set(error, -rte_errno,
8615                                           RTE_FLOW_ERROR_TYPE_ACTION,
8616                                           NULL,
8617                                           "No eswitch info was found for port");
8618 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8619         /*
8620          * This parameter is transferred to
8621          * mlx5dv_dr_action_create_dest_ib_port().
8622          */
8623         *dst_port_id = priv->dev_port;
8624 #else
8625         /*
8626          * Legacy mode, no LAG configurations is supported.
8627          * This parameter is transferred to
8628          * mlx5dv_dr_action_create_dest_vport().
8629          */
8630         *dst_port_id = priv->vport_id;
8631 #endif
8632         return 0;
8633 }
8634
8635 /**
8636  * Create a counter with aging configuration.
8637  *
8638  * @param[in] dev
8639  *   Pointer to rte_eth_dev structure.
8640  * @param[out] count
8641  *   Pointer to the counter action configuration.
8642  * @param[in] age
8643  *   Pointer to the aging action configuration.
8644  *
8645  * @return
8646  *   Index to flow counter on success, 0 otherwise.
8647  */
8648 static uint32_t
8649 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8650                                 struct mlx5_flow *dev_flow,
8651                                 const struct rte_flow_action_count *count,
8652                                 const struct rte_flow_action_age *age)
8653 {
8654         uint32_t counter;
8655         struct mlx5_age_param *age_param;
8656
8657         if (count && count->shared)
8658                 counter = flow_dv_counter_get_shared(dev, count->id);
8659         else
8660                 counter = flow_dv_counter_alloc(dev, !!age);
8661         if (!counter || age == NULL)
8662                 return counter;
8663         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8664         age_param->context = age->context ? age->context :
8665                 (void *)(uintptr_t)(dev_flow->flow_idx);
8666         age_param->timeout = age->timeout;
8667         age_param->port_id = dev->data->port_id;
8668         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8669         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8670         return counter;
8671 }
8672
8673 /**
8674  * Add Tx queue matcher
8675  *
8676  * @param[in] dev
8677  *   Pointer to the dev struct.
8678  * @param[in, out] matcher
8679  *   Flow matcher.
8680  * @param[in, out] key
8681  *   Flow matcher value.
8682  * @param[in] item
8683  *   Flow pattern to translate.
8684  * @param[in] inner
8685  *   Item is inner pattern.
8686  */
8687 static void
8688 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8689                                 void *matcher, void *key,
8690                                 const struct rte_flow_item *item)
8691 {
8692         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8693         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8694         void *misc_m =
8695                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8696         void *misc_v =
8697                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8698         struct mlx5_txq_ctrl *txq;
8699         uint32_t queue;
8700
8701
8702         queue_m = (const void *)item->mask;
8703         if (!queue_m)
8704                 return;
8705         queue_v = (const void *)item->spec;
8706         if (!queue_v)
8707                 return;
8708         txq = mlx5_txq_get(dev, queue_v->queue);
8709         if (!txq)
8710                 return;
8711         queue = txq->obj->sq->id;
8712         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8713         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8714                  queue & queue_m->queue);
8715         mlx5_txq_release(dev, queue_v->queue);
8716 }
8717
8718 /**
8719  * Set the hash fields according to the @p flow information.
8720  *
8721  * @param[in] dev_flow
8722  *   Pointer to the mlx5_flow.
8723  * @param[in] rss_desc
8724  *   Pointer to the mlx5_flow_rss_desc.
8725  */
8726 static void
8727 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8728                        struct mlx5_flow_rss_desc *rss_desc)
8729 {
8730         uint64_t items = dev_flow->handle->layers;
8731         int rss_inner = 0;
8732         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8733
8734         dev_flow->hash_fields = 0;
8735 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8736         if (rss_desc->level >= 2) {
8737                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8738                 rss_inner = 1;
8739         }
8740 #endif
8741         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8742             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8743                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8744                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8745                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8746                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8747                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8748                         else
8749                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8750                 }
8751         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8752                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8753                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8754                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8755                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8756                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8757                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8758                         else
8759                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8760                 }
8761         }
8762         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8763             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8764                 if (rss_types & ETH_RSS_UDP) {
8765                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8766                                 dev_flow->hash_fields |=
8767                                                 IBV_RX_HASH_SRC_PORT_UDP;
8768                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8769                                 dev_flow->hash_fields |=
8770                                                 IBV_RX_HASH_DST_PORT_UDP;
8771                         else
8772                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8773                 }
8774         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8775                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8776                 if (rss_types & ETH_RSS_TCP) {
8777                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8778                                 dev_flow->hash_fields |=
8779                                                 IBV_RX_HASH_SRC_PORT_TCP;
8780                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8781                                 dev_flow->hash_fields |=
8782                                                 IBV_RX_HASH_DST_PORT_TCP;
8783                         else
8784                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8785                 }
8786         }
8787 }
8788
8789 /**
8790  * Prepare an Rx Hash queue.
8791  *
8792  * @param dev
8793  *   Pointer to Ethernet device.
8794  * @param[in] dev_flow
8795  *   Pointer to the mlx5_flow.
8796  * @param[in] rss_desc
8797  *   Pointer to the mlx5_flow_rss_desc.
8798  * @param[out] hrxq_idx
8799  *   Hash Rx queue index.
8800  *
8801  * @return
8802  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8803  */
8804 static struct mlx5_hrxq *
8805 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8806                      struct mlx5_flow *dev_flow,
8807                      struct mlx5_flow_rss_desc *rss_desc,
8808                      uint32_t *hrxq_idx)
8809 {
8810         struct mlx5_priv *priv = dev->data->dev_private;
8811         struct mlx5_flow_handle *dh = dev_flow->handle;
8812         struct mlx5_hrxq *hrxq;
8813
8814         MLX5_ASSERT(rss_desc->queue_num);
8815         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8816         rss_desc->hash_fields = dev_flow->hash_fields;
8817         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8818         rss_desc->shared_rss = 0;
8819         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8820         if (!*hrxq_idx)
8821                 return NULL;
8822         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8823                               *hrxq_idx);
8824         return hrxq;
8825 }
8826
8827 /**
8828  * Release sample sub action resource.
8829  *
8830  * @param[in, out] dev
8831  *   Pointer to rte_eth_dev structure.
8832  * @param[in] act_res
8833  *   Pointer to sample sub action resource.
8834  */
8835 static void
8836 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8837                                    struct mlx5_flow_sub_actions_idx *act_res)
8838 {
8839         if (act_res->rix_hrxq) {
8840                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8841                 act_res->rix_hrxq = 0;
8842         }
8843         if (act_res->rix_encap_decap) {
8844                 flow_dv_encap_decap_resource_release(dev,
8845                                                      act_res->rix_encap_decap);
8846                 act_res->rix_encap_decap = 0;
8847         }
8848         if (act_res->rix_port_id_action) {
8849                 flow_dv_port_id_action_resource_release(dev,
8850                                                 act_res->rix_port_id_action);
8851                 act_res->rix_port_id_action = 0;
8852         }
8853         if (act_res->rix_tag) {
8854                 flow_dv_tag_release(dev, act_res->rix_tag);
8855                 act_res->rix_tag = 0;
8856         }
8857         if (act_res->cnt) {
8858                 flow_dv_counter_free(dev, act_res->cnt);
8859                 act_res->cnt = 0;
8860         }
8861 }
8862
8863 int
8864 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8865                         struct mlx5_cache_entry *entry, void *cb_ctx)
8866 {
8867         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8868         struct rte_eth_dev *dev = ctx->dev;
8869         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8870         struct mlx5_flow_dv_sample_resource *cache_resource =
8871                         container_of(entry, typeof(*cache_resource), entry);
8872
8873         if (resource->ratio == cache_resource->ratio &&
8874             resource->ft_type == cache_resource->ft_type &&
8875             resource->ft_id == cache_resource->ft_id &&
8876             resource->set_action == cache_resource->set_action &&
8877             !memcmp((void *)&resource->sample_act,
8878                     (void *)&cache_resource->sample_act,
8879                     sizeof(struct mlx5_flow_sub_actions_list))) {
8880                 /*
8881                  * Existing sample action should release the prepared
8882                  * sub-actions reference counter.
8883                  */
8884                 flow_dv_sample_sub_actions_release(dev,
8885                                                 &resource->sample_idx);
8886                 return 0;
8887         }
8888         return 1;
8889 }
8890
8891 struct mlx5_cache_entry *
8892 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8893                          struct mlx5_cache_entry *entry __rte_unused,
8894                          void *cb_ctx)
8895 {
8896         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8897         struct rte_eth_dev *dev = ctx->dev;
8898         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8899         void **sample_dv_actions = resource->sub_actions;
8900         struct mlx5_flow_dv_sample_resource *cache_resource;
8901         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8902         struct mlx5_priv *priv = dev->data->dev_private;
8903         struct mlx5_dev_ctx_shared *sh = priv->sh;
8904         struct mlx5_flow_tbl_resource *tbl;
8905         uint32_t idx = 0;
8906         const uint32_t next_ft_step = 1;
8907         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8908         uint8_t is_egress = 0;
8909         uint8_t is_transfer = 0;
8910         struct rte_flow_error *error = ctx->error;
8911
8912         /* Register new sample resource. */
8913         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
8914         if (!cache_resource) {
8915                 rte_flow_error_set(error, ENOMEM,
8916                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8917                                           NULL,
8918                                           "cannot allocate resource memory");
8919                 return NULL;
8920         }
8921         *cache_resource = *resource;
8922         /* Create normal path table level */
8923         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8924                 is_transfer = 1;
8925         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
8926                 is_egress = 1;
8927         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8928                                         is_egress, is_transfer,
8929                                         true, NULL, 0, 0, error);
8930         if (!tbl) {
8931                 rte_flow_error_set(error, ENOMEM,
8932                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8933                                           NULL,
8934                                           "fail to create normal path table "
8935                                           "for sample");
8936                 goto error;
8937         }
8938         int ret;
8939
8940         cache_resource->normal_path_tbl = tbl;
8941         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8942                 ret = mlx5_flow_os_create_flow_action_default_miss
8943                         (&cache_resource->default_miss);
8944                 if (!ret) {
8945                         rte_flow_error_set(error, ENOMEM,
8946                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8947                                                 NULL,
8948                                                 "cannot create default miss "
8949                                                 "action");
8950                         goto error;
8951                 }
8952                 sample_dv_actions[resource->sample_act.actions_num++] =
8953                                                 cache_resource->default_miss;
8954         }
8955         /* Create a DR sample action */
8956         sampler_attr.sample_ratio = cache_resource->ratio;
8957         sampler_attr.default_next_table = tbl->obj;
8958         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8959         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8960                                                         &sample_dv_actions[0];
8961         sampler_attr.action = cache_resource->set_action;
8962         if (mlx5_os_flow_dr_create_flow_action_sampler
8963                         (&sampler_attr, &cache_resource->verbs_action)) {
8964                 rte_flow_error_set(error, ENOMEM,
8965                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8966                                         NULL, "cannot create sample action");
8967                 goto error;
8968         }
8969         cache_resource->idx = idx;
8970         cache_resource->dev = dev;
8971         return &cache_resource->entry;
8972 error:
8973         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
8974             cache_resource->default_miss)
8975                 claim_zero(mlx5_flow_os_destroy_flow_action
8976                                 (cache_resource->default_miss));
8977         else
8978                 flow_dv_sample_sub_actions_release(dev,
8979                                                    &cache_resource->sample_idx);
8980         if (cache_resource->normal_path_tbl)
8981                 flow_dv_tbl_resource_release(MLX5_SH(dev),
8982                                 cache_resource->normal_path_tbl);
8983         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
8984         return NULL;
8985
8986 }
8987
8988 /**
8989  * Find existing sample resource or create and register a new one.
8990  *
8991  * @param[in, out] dev
8992  *   Pointer to rte_eth_dev structure.
8993  * @param[in] resource
8994  *   Pointer to sample resource.
8995  * @parm[in, out] dev_flow
8996  *   Pointer to the dev_flow.
8997  * @param[out] error
8998  *   pointer to error structure.
8999  *
9000  * @return
9001  *   0 on success otherwise -errno and errno is set.
9002  */
9003 static int
9004 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9005                          struct mlx5_flow_dv_sample_resource *resource,
9006                          struct mlx5_flow *dev_flow,
9007                          struct rte_flow_error *error)
9008 {
9009         struct mlx5_flow_dv_sample_resource *cache_resource;
9010         struct mlx5_cache_entry *entry;
9011         struct mlx5_priv *priv = dev->data->dev_private;
9012         struct mlx5_flow_cb_ctx ctx = {
9013                 .dev = dev,
9014                 .error = error,
9015                 .data = resource,
9016         };
9017
9018         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9019         if (!entry)
9020                 return -rte_errno;
9021         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9022         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9023         dev_flow->dv.sample_res = cache_resource;
9024         return 0;
9025 }
9026
9027 int
9028 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9029                             struct mlx5_cache_entry *entry, void *cb_ctx)
9030 {
9031         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9032         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9033         struct rte_eth_dev *dev = ctx->dev;
9034         struct mlx5_flow_dv_dest_array_resource *cache_resource =
9035                         container_of(entry, typeof(*cache_resource), entry);
9036         uint32_t idx = 0;
9037
9038         if (resource->num_of_dest == cache_resource->num_of_dest &&
9039             resource->ft_type == cache_resource->ft_type &&
9040             !memcmp((void *)cache_resource->sample_act,
9041                     (void *)resource->sample_act,
9042                    (resource->num_of_dest *
9043                    sizeof(struct mlx5_flow_sub_actions_list)))) {
9044                 /*
9045                  * Existing sample action should release the prepared
9046                  * sub-actions reference counter.
9047                  */
9048                 for (idx = 0; idx < resource->num_of_dest; idx++)
9049                         flow_dv_sample_sub_actions_release(dev,
9050                                         &resource->sample_idx[idx]);
9051                 return 0;
9052         }
9053         return 1;
9054 }
9055
9056 struct mlx5_cache_entry *
9057 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9058                          struct mlx5_cache_entry *entry __rte_unused,
9059                          void *cb_ctx)
9060 {
9061         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9062         struct rte_eth_dev *dev = ctx->dev;
9063         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9064         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9065         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9066         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9067         struct mlx5_priv *priv = dev->data->dev_private;
9068         struct mlx5_dev_ctx_shared *sh = priv->sh;
9069         struct mlx5_flow_sub_actions_list *sample_act;
9070         struct mlx5dv_dr_domain *domain;
9071         uint32_t idx = 0, res_idx = 0;
9072         struct rte_flow_error *error = ctx->error;
9073         int ret;
9074
9075         /* Register new destination array resource. */
9076         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9077                                             &res_idx);
9078         if (!cache_resource) {
9079                 rte_flow_error_set(error, ENOMEM,
9080                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9081                                           NULL,
9082                                           "cannot allocate resource memory");
9083                 return NULL;
9084         }
9085         *cache_resource = *resource;
9086         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9087                 domain = sh->fdb_domain;
9088         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9089                 domain = sh->rx_domain;
9090         else
9091                 domain = sh->tx_domain;
9092         for (idx = 0; idx < resource->num_of_dest; idx++) {
9093                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9094                                  mlx5_malloc(MLX5_MEM_ZERO,
9095                                  sizeof(struct mlx5dv_dr_action_dest_attr),
9096                                  0, SOCKET_ID_ANY);
9097                 if (!dest_attr[idx]) {
9098                         rte_flow_error_set(error, ENOMEM,
9099                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9100                                            NULL,
9101                                            "cannot allocate resource memory");
9102                         goto error;
9103                 }
9104                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9105                 sample_act = &resource->sample_act[idx];
9106                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
9107                         dest_attr[idx]->dest = sample_act->dr_queue_action;
9108                 } else if (sample_act->action_flags ==
9109                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
9110                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9111                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9112                         dest_attr[idx]->dest_reformat->reformat =
9113                                         sample_act->dr_encap_action;
9114                         dest_attr[idx]->dest_reformat->dest =
9115                                         sample_act->dr_port_id_action;
9116                 } else if (sample_act->action_flags ==
9117                            MLX5_FLOW_ACTION_PORT_ID) {
9118                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
9119                 }
9120         }
9121         /* create a dest array actioin */
9122         ret = mlx5_os_flow_dr_create_flow_action_dest_array
9123                                                 (domain,
9124                                                  cache_resource->num_of_dest,
9125                                                  dest_attr,
9126                                                  &cache_resource->action);
9127         if (ret) {
9128                 rte_flow_error_set(error, ENOMEM,
9129                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9130                                    NULL,
9131                                    "cannot create destination array action");
9132                 goto error;
9133         }
9134         cache_resource->idx = res_idx;
9135         cache_resource->dev = dev;
9136         for (idx = 0; idx < resource->num_of_dest; idx++)
9137                 mlx5_free(dest_attr[idx]);
9138         return &cache_resource->entry;
9139 error:
9140         for (idx = 0; idx < resource->num_of_dest; idx++) {
9141                 struct mlx5_flow_sub_actions_idx *act_res =
9142                                         &cache_resource->sample_idx[idx];
9143                 if (act_res->rix_hrxq &&
9144                     !mlx5_hrxq_release(dev,
9145                                 act_res->rix_hrxq))
9146                         act_res->rix_hrxq = 0;
9147                 if (act_res->rix_encap_decap &&
9148                         !flow_dv_encap_decap_resource_release(dev,
9149                                 act_res->rix_encap_decap))
9150                         act_res->rix_encap_decap = 0;
9151                 if (act_res->rix_port_id_action &&
9152                         !flow_dv_port_id_action_resource_release(dev,
9153                                 act_res->rix_port_id_action))
9154                         act_res->rix_port_id_action = 0;
9155                 if (dest_attr[idx])
9156                         mlx5_free(dest_attr[idx]);
9157         }
9158
9159         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9160         return NULL;
9161 }
9162
9163 /**
9164  * Find existing destination array resource or create and register a new one.
9165  *
9166  * @param[in, out] dev
9167  *   Pointer to rte_eth_dev structure.
9168  * @param[in] resource
9169  *   Pointer to destination array resource.
9170  * @parm[in, out] dev_flow
9171  *   Pointer to the dev_flow.
9172  * @param[out] error
9173  *   pointer to error structure.
9174  *
9175  * @return
9176  *   0 on success otherwise -errno and errno is set.
9177  */
9178 static int
9179 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9180                          struct mlx5_flow_dv_dest_array_resource *resource,
9181                          struct mlx5_flow *dev_flow,
9182                          struct rte_flow_error *error)
9183 {
9184         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9185         struct mlx5_priv *priv = dev->data->dev_private;
9186         struct mlx5_cache_entry *entry;
9187         struct mlx5_flow_cb_ctx ctx = {
9188                 .dev = dev,
9189                 .error = error,
9190                 .data = resource,
9191         };
9192
9193         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9194         if (!entry)
9195                 return -rte_errno;
9196         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9197         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9198         dev_flow->dv.dest_array_res = cache_resource;
9199         return 0;
9200 }
9201
9202 /**
9203  * Convert Sample action to DV specification.
9204  *
9205  * @param[in] dev
9206  *   Pointer to rte_eth_dev structure.
9207  * @param[in] action
9208  *   Pointer to action structure.
9209  * @param[in, out] dev_flow
9210  *   Pointer to the mlx5_flow.
9211  * @param[in] attr
9212  *   Pointer to the flow attributes.
9213  * @param[in, out] num_of_dest
9214  *   Pointer to the num of destination.
9215  * @param[in, out] sample_actions
9216  *   Pointer to sample actions list.
9217  * @param[in, out] res
9218  *   Pointer to sample resource.
9219  * @param[out] error
9220  *   Pointer to the error structure.
9221  *
9222  * @return
9223  *   0 on success, a negative errno value otherwise and rte_errno is set.
9224  */
9225 static int
9226 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9227                                 const struct rte_flow_action *action,
9228                                 struct mlx5_flow *dev_flow,
9229                                 const struct rte_flow_attr *attr,
9230                                 uint32_t *num_of_dest,
9231                                 void **sample_actions,
9232                                 struct mlx5_flow_dv_sample_resource *res,
9233                                 struct rte_flow_error *error)
9234 {
9235         struct mlx5_priv *priv = dev->data->dev_private;
9236         const struct rte_flow_action_sample *sample_action;
9237         const struct rte_flow_action *sub_actions;
9238         const struct rte_flow_action_queue *queue;
9239         struct mlx5_flow_sub_actions_list *sample_act;
9240         struct mlx5_flow_sub_actions_idx *sample_idx;
9241         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9242         struct mlx5_flow_rss_desc *rss_desc;
9243         uint64_t action_flags = 0;
9244
9245         MLX5_ASSERT(wks);
9246         rss_desc = &wks->rss_desc;
9247         sample_act = &res->sample_act;
9248         sample_idx = &res->sample_idx;
9249         sample_action = (const struct rte_flow_action_sample *)action->conf;
9250         res->ratio = sample_action->ratio;
9251         sub_actions = sample_action->actions;
9252         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9253                 int type = sub_actions->type;
9254                 uint32_t pre_rix = 0;
9255                 void *pre_r;
9256                 switch (type) {
9257                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9258                 {
9259                         struct mlx5_hrxq *hrxq;
9260                         uint32_t hrxq_idx;
9261
9262                         queue = sub_actions->conf;
9263                         rss_desc->queue_num = 1;
9264                         rss_desc->queue[0] = queue->index;
9265                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9266                                                     rss_desc, &hrxq_idx);
9267                         if (!hrxq)
9268                                 return rte_flow_error_set
9269                                         (error, rte_errno,
9270                                          RTE_FLOW_ERROR_TYPE_ACTION,
9271                                          NULL,
9272                                          "cannot create fate queue");
9273                         sample_act->dr_queue_action = hrxq->action;
9274                         sample_idx->rix_hrxq = hrxq_idx;
9275                         sample_actions[sample_act->actions_num++] =
9276                                                 hrxq->action;
9277                         (*num_of_dest)++;
9278                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9279                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9280                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9281                         dev_flow->handle->fate_action =
9282                                         MLX5_FLOW_FATE_QUEUE;
9283                         break;
9284                 }
9285                 case RTE_FLOW_ACTION_TYPE_MARK:
9286                 {
9287                         uint32_t tag_be = mlx5_flow_mark_set
9288                                 (((const struct rte_flow_action_mark *)
9289                                 (sub_actions->conf))->id);
9290
9291                         dev_flow->handle->mark = 1;
9292                         pre_rix = dev_flow->handle->dvh.rix_tag;
9293                         /* Save the mark resource before sample */
9294                         pre_r = dev_flow->dv.tag_resource;
9295                         if (flow_dv_tag_resource_register(dev, tag_be,
9296                                                   dev_flow, error))
9297                                 return -rte_errno;
9298                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9299                         sample_act->dr_tag_action =
9300                                 dev_flow->dv.tag_resource->action;
9301                         sample_idx->rix_tag =
9302                                 dev_flow->handle->dvh.rix_tag;
9303                         sample_actions[sample_act->actions_num++] =
9304                                                 sample_act->dr_tag_action;
9305                         /* Recover the mark resource after sample */
9306                         dev_flow->dv.tag_resource = pre_r;
9307                         dev_flow->handle->dvh.rix_tag = pre_rix;
9308                         action_flags |= MLX5_FLOW_ACTION_MARK;
9309                         break;
9310                 }
9311                 case RTE_FLOW_ACTION_TYPE_COUNT:
9312                 {
9313                         uint32_t counter;
9314
9315                         counter = flow_dv_translate_create_counter(dev,
9316                                         dev_flow, sub_actions->conf, 0);
9317                         if (!counter)
9318                                 return rte_flow_error_set
9319                                                 (error, rte_errno,
9320                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9321                                                  NULL,
9322                                                  "cannot create counter"
9323                                                  " object.");
9324                         sample_idx->cnt = counter;
9325                         sample_act->dr_cnt_action =
9326                                   (flow_dv_counter_get_by_idx(dev,
9327                                   counter, NULL))->action;
9328                         sample_actions[sample_act->actions_num++] =
9329                                                 sample_act->dr_cnt_action;
9330                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9331                         break;
9332                 }
9333                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9334                 {
9335                         struct mlx5_flow_dv_port_id_action_resource
9336                                         port_id_resource;
9337                         uint32_t port_id = 0;
9338
9339                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9340                         /* Save the port id resource before sample */
9341                         pre_rix = dev_flow->handle->rix_port_id_action;
9342                         pre_r = dev_flow->dv.port_id_action;
9343                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9344                                                              &port_id, error))
9345                                 return -rte_errno;
9346                         port_id_resource.port_id = port_id;
9347                         if (flow_dv_port_id_action_resource_register
9348                             (dev, &port_id_resource, dev_flow, error))
9349                                 return -rte_errno;
9350                         sample_act->dr_port_id_action =
9351                                 dev_flow->dv.port_id_action->action;
9352                         sample_idx->rix_port_id_action =
9353                                 dev_flow->handle->rix_port_id_action;
9354                         sample_actions[sample_act->actions_num++] =
9355                                                 sample_act->dr_port_id_action;
9356                         /* Recover the port id resource after sample */
9357                         dev_flow->dv.port_id_action = pre_r;
9358                         dev_flow->handle->rix_port_id_action = pre_rix;
9359                         (*num_of_dest)++;
9360                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9361                         break;
9362                 }
9363                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9364                         /* Save the encap resource before sample */
9365                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9366                         pre_r = dev_flow->dv.encap_decap;
9367                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9368                                                            dev_flow,
9369                                                            attr->transfer,
9370                                                            error))
9371                                 return -rte_errno;
9372                         sample_act->dr_encap_action =
9373                                 dev_flow->dv.encap_decap->action;
9374                         sample_idx->rix_encap_decap =
9375                                 dev_flow->handle->dvh.rix_encap_decap;
9376                         sample_actions[sample_act->actions_num++] =
9377                                                 sample_act->dr_encap_action;
9378                         /* Recover the encap resource after sample */
9379                         dev_flow->dv.encap_decap = pre_r;
9380                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9381                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9382                         break;
9383                 default:
9384                         return rte_flow_error_set(error, EINVAL,
9385                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9386                                 NULL,
9387                                 "Not support for sampler action");
9388                 }
9389         }
9390         sample_act->action_flags = action_flags;
9391         res->ft_id = dev_flow->dv.group;
9392         if (attr->transfer) {
9393                 union {
9394                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9395                         uint64_t set_action;
9396                 } action_ctx = { .set_action = 0 };
9397
9398                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9399                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9400                          MLX5_MODIFICATION_TYPE_SET);
9401                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9402                          MLX5_MODI_META_REG_C_0);
9403                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9404                          priv->vport_meta_tag);
9405                 res->set_action = action_ctx.set_action;
9406         } else if (attr->ingress) {
9407                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9408         } else {
9409                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9410         }
9411         return 0;
9412 }
9413
9414 /**
9415  * Convert Sample action to DV specification.
9416  *
9417  * @param[in] dev
9418  *   Pointer to rte_eth_dev structure.
9419  * @param[in, out] dev_flow
9420  *   Pointer to the mlx5_flow.
9421  * @param[in] num_of_dest
9422  *   The num of destination.
9423  * @param[in, out] res
9424  *   Pointer to sample resource.
9425  * @param[in, out] mdest_res
9426  *   Pointer to destination array resource.
9427  * @param[in] sample_actions
9428  *   Pointer to sample path actions list.
9429  * @param[in] action_flags
9430  *   Holds the actions detected until now.
9431  * @param[out] error
9432  *   Pointer to the error structure.
9433  *
9434  * @return
9435  *   0 on success, a negative errno value otherwise and rte_errno is set.
9436  */
9437 static int
9438 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9439                              struct mlx5_flow *dev_flow,
9440                              uint32_t num_of_dest,
9441                              struct mlx5_flow_dv_sample_resource *res,
9442                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9443                              void **sample_actions,
9444                              uint64_t action_flags,
9445                              struct rte_flow_error *error)
9446 {
9447         /* update normal path action resource into last index of array */
9448         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9449         struct mlx5_flow_sub_actions_list *sample_act =
9450                                         &mdest_res->sample_act[dest_index];
9451         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9452         struct mlx5_flow_rss_desc *rss_desc;
9453         uint32_t normal_idx = 0;
9454         struct mlx5_hrxq *hrxq;
9455         uint32_t hrxq_idx;
9456
9457         MLX5_ASSERT(wks);
9458         rss_desc = &wks->rss_desc;
9459         if (num_of_dest > 1) {
9460                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9461                         /* Handle QP action for mirroring */
9462                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9463                                                     rss_desc, &hrxq_idx);
9464                         if (!hrxq)
9465                                 return rte_flow_error_set
9466                                      (error, rte_errno,
9467                                       RTE_FLOW_ERROR_TYPE_ACTION,
9468                                       NULL,
9469                                       "cannot create rx queue");
9470                         normal_idx++;
9471                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9472                         sample_act->dr_queue_action = hrxq->action;
9473                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9474                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9475                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9476                 }
9477                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9478                         normal_idx++;
9479                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9480                                 dev_flow->handle->dvh.rix_encap_decap;
9481                         sample_act->dr_encap_action =
9482                                 dev_flow->dv.encap_decap->action;
9483                 }
9484                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9485                         normal_idx++;
9486                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9487                                 dev_flow->handle->rix_port_id_action;
9488                         sample_act->dr_port_id_action =
9489                                 dev_flow->dv.port_id_action->action;
9490                 }
9491                 sample_act->actions_num = normal_idx;
9492                 /* update sample action resource into first index of array */
9493                 mdest_res->ft_type = res->ft_type;
9494                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9495                                 sizeof(struct mlx5_flow_sub_actions_idx));
9496                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9497                                 sizeof(struct mlx5_flow_sub_actions_list));
9498                 mdest_res->num_of_dest = num_of_dest;
9499                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9500                                                          dev_flow, error))
9501                         return rte_flow_error_set(error, EINVAL,
9502                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9503                                                   NULL, "can't create sample "
9504                                                   "action");
9505         } else {
9506                 res->sub_actions = sample_actions;
9507                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9508                         return rte_flow_error_set(error, EINVAL,
9509                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9510                                                   NULL,
9511                                                   "can't create sample action");
9512         }
9513         return 0;
9514 }
9515
9516 /**
9517  * Remove an ASO age action from age actions list.
9518  *
9519  * @param[in] dev
9520  *   Pointer to the Ethernet device structure.
9521  * @param[in] age
9522  *   Pointer to the aso age action handler.
9523  */
9524 static void
9525 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9526                                 struct mlx5_aso_age_action *age)
9527 {
9528         struct mlx5_age_info *age_info;
9529         struct mlx5_age_param *age_param = &age->age_params;
9530         struct mlx5_priv *priv = dev->data->dev_private;
9531         uint16_t expected = AGE_CANDIDATE;
9532
9533         age_info = GET_PORT_AGE_INFO(priv);
9534         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9535                                          AGE_FREE, false, __ATOMIC_RELAXED,
9536                                          __ATOMIC_RELAXED)) {
9537                 /**
9538                  * We need the lock even it is age timeout,
9539                  * since age action may still in process.
9540                  */
9541                 rte_spinlock_lock(&age_info->aged_sl);
9542                 LIST_REMOVE(age, next);
9543                 rte_spinlock_unlock(&age_info->aged_sl);
9544                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9545         }
9546 }
9547
9548 /**
9549  * Release an ASO age action.
9550  *
9551  * @param[in] dev
9552  *   Pointer to the Ethernet device structure.
9553  * @param[in] age_idx
9554  *   Index of ASO age action to release.
9555  * @param[in] flow
9556  *   True if the release operation is during flow destroy operation.
9557  *   False if the release operation is during action destroy operation.
9558  *
9559  * @return
9560  *   0 when age action was removed, otherwise the number of references.
9561  */
9562 static int
9563 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9564 {
9565         struct mlx5_priv *priv = dev->data->dev_private;
9566         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9567         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9568         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9569
9570         if (!ret) {
9571                 flow_dv_aso_age_remove_from_age(dev, age);
9572                 rte_spinlock_lock(&mng->free_sl);
9573                 LIST_INSERT_HEAD(&mng->free, age, next);
9574                 rte_spinlock_unlock(&mng->free_sl);
9575         }
9576         return ret;
9577 }
9578
9579 /**
9580  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9581  *
9582  * @param[in] dev
9583  *   Pointer to the Ethernet device structure.
9584  *
9585  * @return
9586  *   0 on success, otherwise negative errno value and rte_errno is set.
9587  */
9588 static int
9589 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9590 {
9591         struct mlx5_priv *priv = dev->data->dev_private;
9592         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9593         void *old_pools = mng->pools;
9594         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9595         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9596         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9597
9598         if (!pools) {
9599                 rte_errno = ENOMEM;
9600                 return -ENOMEM;
9601         }
9602         if (old_pools) {
9603                 memcpy(pools, old_pools,
9604                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9605                 mlx5_free(old_pools);
9606         } else {
9607                 /* First ASO flow hit allocation - starting ASO data-path. */
9608                 int ret = mlx5_aso_queue_start(priv->sh);
9609
9610                 if (ret) {
9611                         mlx5_free(pools);
9612                         return ret;
9613                 }
9614         }
9615         mng->n = resize;
9616         mng->pools = pools;
9617         return 0;
9618 }
9619
9620 /**
9621  * Create and initialize a new ASO aging pool.
9622  *
9623  * @param[in] dev
9624  *   Pointer to the Ethernet device structure.
9625  * @param[out] age_free
9626  *   Where to put the pointer of a new age action.
9627  *
9628  * @return
9629  *   The age actions pool pointer and @p age_free is set on success,
9630  *   NULL otherwise and rte_errno is set.
9631  */
9632 static struct mlx5_aso_age_pool *
9633 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9634                         struct mlx5_aso_age_action **age_free)
9635 {
9636         struct mlx5_priv *priv = dev->data->dev_private;
9637         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9638         struct mlx5_aso_age_pool *pool = NULL;
9639         struct mlx5_devx_obj *obj = NULL;
9640         uint32_t i;
9641
9642         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9643                                                     priv->sh->pdn);
9644         if (!obj) {
9645                 rte_errno = ENODATA;
9646                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9647                 return NULL;
9648         }
9649         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9650         if (!pool) {
9651                 claim_zero(mlx5_devx_cmd_destroy(obj));
9652                 rte_errno = ENOMEM;
9653                 return NULL;
9654         }
9655         pool->flow_hit_aso_obj = obj;
9656         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9657         rte_spinlock_lock(&mng->resize_sl);
9658         pool->index = mng->next;
9659         /* Resize pools array if there is no room for the new pool in it. */
9660         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9661                 claim_zero(mlx5_devx_cmd_destroy(obj));
9662                 mlx5_free(pool);
9663                 rte_spinlock_unlock(&mng->resize_sl);
9664                 return NULL;
9665         }
9666         mng->pools[pool->index] = pool;
9667         mng->next++;
9668         rte_spinlock_unlock(&mng->resize_sl);
9669         /* Assign the first action in the new pool, the rest go to free list. */
9670         *age_free = &pool->actions[0];
9671         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9672                 pool->actions[i].offset = i;
9673                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9674         }
9675         return pool;
9676 }
9677
9678 /**
9679  * Allocate a ASO aging bit.
9680  *
9681  * @param[in] dev
9682  *   Pointer to the Ethernet device structure.
9683  * @param[out] error
9684  *   Pointer to the error structure.
9685  *
9686  * @return
9687  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9688  */
9689 static uint32_t
9690 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9691 {
9692         struct mlx5_priv *priv = dev->data->dev_private;
9693         const struct mlx5_aso_age_pool *pool;
9694         struct mlx5_aso_age_action *age_free = NULL;
9695         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9696
9697         MLX5_ASSERT(mng);
9698         /* Try to get the next free age action bit. */
9699         rte_spinlock_lock(&mng->free_sl);
9700         age_free = LIST_FIRST(&mng->free);
9701         if (age_free) {
9702                 LIST_REMOVE(age_free, next);
9703         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9704                 rte_spinlock_unlock(&mng->free_sl);
9705                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9706                                    NULL, "failed to create ASO age pool");
9707                 return 0; /* 0 is an error. */
9708         }
9709         rte_spinlock_unlock(&mng->free_sl);
9710         pool = container_of
9711           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9712                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9713                                                                        actions);
9714         if (!age_free->dr_action) {
9715                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9716                                                  error);
9717
9718                 if (reg_c < 0) {
9719                         rte_flow_error_set(error, rte_errno,
9720                                            RTE_FLOW_ERROR_TYPE_ACTION,
9721                                            NULL, "failed to get reg_c "
9722                                            "for ASO flow hit");
9723                         return 0; /* 0 is an error. */
9724                 }
9725 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9726                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9727                                 (priv->sh->rx_domain,
9728                                  pool->flow_hit_aso_obj->obj, age_free->offset,
9729                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9730                                  (reg_c - REG_C_0));
9731 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9732                 if (!age_free->dr_action) {
9733                         rte_errno = errno;
9734                         rte_spinlock_lock(&mng->free_sl);
9735                         LIST_INSERT_HEAD(&mng->free, age_free, next);
9736                         rte_spinlock_unlock(&mng->free_sl);
9737                         rte_flow_error_set(error, rte_errno,
9738                                            RTE_FLOW_ERROR_TYPE_ACTION,
9739                                            NULL, "failed to create ASO "
9740                                            "flow hit action");
9741                         return 0; /* 0 is an error. */
9742                 }
9743         }
9744         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9745         return pool->index | ((age_free->offset + 1) << 16);
9746 }
9747
9748 /**
9749  * Create a age action using ASO mechanism.
9750  *
9751  * @param[in] dev
9752  *   Pointer to rte_eth_dev structure.
9753  * @param[in] age
9754  *   Pointer to the aging action configuration.
9755  * @param[out] error
9756  *   Pointer to the error structure.
9757  *
9758  * @return
9759  *   Index to flow counter on success, 0 otherwise.
9760  */
9761 static uint32_t
9762 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9763                                  const struct rte_flow_action_age *age,
9764                                  struct rte_flow_error *error)
9765 {
9766         uint32_t age_idx = 0;
9767         struct mlx5_aso_age_action *aso_age;
9768
9769         age_idx = flow_dv_aso_age_alloc(dev, error);
9770         if (!age_idx)
9771                 return 0;
9772         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9773         aso_age->age_params.context = age->context;
9774         aso_age->age_params.timeout = age->timeout;
9775         aso_age->age_params.port_id = dev->data->port_id;
9776         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9777                          __ATOMIC_RELAXED);
9778         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9779                          __ATOMIC_RELAXED);
9780         return age_idx;
9781 }
9782
9783 /**
9784  * Fill the flow with DV spec, lock free
9785  * (mutex should be acquired by caller).
9786  *
9787  * @param[in] dev
9788  *   Pointer to rte_eth_dev structure.
9789  * @param[in, out] dev_flow
9790  *   Pointer to the sub flow.
9791  * @param[in] attr
9792  *   Pointer to the flow attributes.
9793  * @param[in] items
9794  *   Pointer to the list of items.
9795  * @param[in] actions
9796  *   Pointer to the list of actions.
9797  * @param[out] error
9798  *   Pointer to the error structure.
9799  *
9800  * @return
9801  *   0 on success, a negative errno value otherwise and rte_errno is set.
9802  */
9803 static int
9804 flow_dv_translate(struct rte_eth_dev *dev,
9805                   struct mlx5_flow *dev_flow,
9806                   const struct rte_flow_attr *attr,
9807                   const struct rte_flow_item items[],
9808                   const struct rte_flow_action actions[],
9809                   struct rte_flow_error *error)
9810 {
9811         struct mlx5_priv *priv = dev->data->dev_private;
9812         struct mlx5_dev_config *dev_conf = &priv->config;
9813         struct rte_flow *flow = dev_flow->flow;
9814         struct mlx5_flow_handle *handle = dev_flow->handle;
9815         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9816         struct mlx5_flow_rss_desc *rss_desc;
9817         uint64_t item_flags = 0;
9818         uint64_t last_item = 0;
9819         uint64_t action_flags = 0;
9820         uint64_t priority = attr->priority;
9821         struct mlx5_flow_dv_matcher matcher = {
9822                 .mask = {
9823                         .size = sizeof(matcher.mask.buf) -
9824                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9825                 },
9826         };
9827         int actions_n = 0;
9828         bool actions_end = false;
9829         union {
9830                 struct mlx5_flow_dv_modify_hdr_resource res;
9831                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9832                             sizeof(struct mlx5_modification_cmd) *
9833                             (MLX5_MAX_MODIFY_NUM + 1)];
9834         } mhdr_dummy;
9835         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9836         const struct rte_flow_action_count *count = NULL;
9837         const struct rte_flow_action_age *age = NULL;
9838         union flow_dv_attr flow_attr = { .attr = 0 };
9839         uint32_t tag_be;
9840         union mlx5_flow_tbl_key tbl_key;
9841         uint32_t modify_action_position = UINT32_MAX;
9842         void *match_mask = matcher.mask.buf;
9843         void *match_value = dev_flow->dv.value.buf;
9844         uint8_t next_protocol = 0xff;
9845         struct rte_vlan_hdr vlan = { 0 };
9846         struct mlx5_flow_dv_dest_array_resource mdest_res;
9847         struct mlx5_flow_dv_sample_resource sample_res;
9848         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9849         struct mlx5_flow_sub_actions_list *sample_act;
9850         uint32_t sample_act_pos = UINT32_MAX;
9851         uint32_t num_of_dest = 0;
9852         int tmp_actions_n = 0;
9853         uint32_t table;
9854         int ret = 0;
9855         const struct mlx5_flow_tunnel *tunnel;
9856         struct flow_grp_info grp_info = {
9857                 .external = !!dev_flow->external,
9858                 .transfer = !!attr->transfer,
9859                 .fdb_def_rule = !!priv->fdb_def_rule,
9860                 .skip_scale = !!dev_flow->skip_scale,
9861         };
9862
9863         if (!wks)
9864                 return rte_flow_error_set(error, ENOMEM,
9865                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9866                                           NULL,
9867                                           "failed to push flow workspace");
9868         rss_desc = &wks->rss_desc;
9869         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9870         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9871         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9872                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9873         /* update normal path action resource into last index of array */
9874         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9875         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9876                  flow_items_to_tunnel(items) :
9877                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9878                  flow_actions_to_tunnel(actions) :
9879                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9880         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9881                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9882         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9883                                 (dev, tunnel, attr, items, actions);
9884         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9885                                        &grp_info, error);
9886         if (ret)
9887                 return ret;
9888         dev_flow->dv.group = table;
9889         if (attr->transfer)
9890                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9891         if (priority == MLX5_FLOW_PRIO_RSVD)
9892                 priority = dev_conf->flow_prio - 1;
9893         /* number of actions must be set to 0 in case of dirty stack. */
9894         mhdr_res->actions_num = 0;
9895         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9896                 /*
9897                  * do not add decap action if match rule drops packet
9898                  * HW rejects rules with decap & drop
9899                  *
9900                  * if tunnel match rule was inserted before matching tunnel set
9901                  * rule flow table used in the match rule must be registered.
9902                  * current implementation handles that in the
9903                  * flow_dv_match_register() at the function end.
9904                  */
9905                 bool add_decap = true;
9906                 const struct rte_flow_action *ptr = actions;
9907
9908                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9909                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9910                                 add_decap = false;
9911                                 break;
9912                         }
9913                 }
9914                 if (add_decap) {
9915                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9916                                                            attr->transfer,
9917                                                            error))
9918                                 return -rte_errno;
9919                         dev_flow->dv.actions[actions_n++] =
9920                                         dev_flow->dv.encap_decap->action;
9921                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9922                 }
9923         }
9924         for (; !actions_end ; actions++) {
9925                 const struct rte_flow_action_queue *queue;
9926                 const struct rte_flow_action_rss *rss;
9927                 const struct rte_flow_action *action = actions;
9928                 const uint8_t *rss_key;
9929                 const struct rte_flow_action_meter *mtr;
9930                 struct mlx5_flow_tbl_resource *tbl;
9931                 struct mlx5_aso_age_action *age_act;
9932                 uint32_t port_id = 0;
9933                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9934                 int action_type = actions->type;
9935                 const struct rte_flow_action *found_action = NULL;
9936                 struct mlx5_flow_meter *fm = NULL;
9937                 uint32_t jump_group = 0;
9938
9939                 if (!mlx5_flow_os_action_supported(action_type))
9940                         return rte_flow_error_set(error, ENOTSUP,
9941                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9942                                                   actions,
9943                                                   "action not supported");
9944                 switch (action_type) {
9945                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9946                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9947                         break;
9948                 case RTE_FLOW_ACTION_TYPE_VOID:
9949                         break;
9950                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9951                         if (flow_dv_translate_action_port_id(dev, action,
9952                                                              &port_id, error))
9953                                 return -rte_errno;
9954                         port_id_resource.port_id = port_id;
9955                         MLX5_ASSERT(!handle->rix_port_id_action);
9956                         if (flow_dv_port_id_action_resource_register
9957                             (dev, &port_id_resource, dev_flow, error))
9958                                 return -rte_errno;
9959                         dev_flow->dv.actions[actions_n++] =
9960                                         dev_flow->dv.port_id_action->action;
9961                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9962                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9963                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9964                         num_of_dest++;
9965                         break;
9966                 case RTE_FLOW_ACTION_TYPE_FLAG:
9967                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9968                         dev_flow->handle->mark = 1;
9969                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9970                                 struct rte_flow_action_mark mark = {
9971                                         .id = MLX5_FLOW_MARK_DEFAULT,
9972                                 };
9973
9974                                 if (flow_dv_convert_action_mark(dev, &mark,
9975                                                                 mhdr_res,
9976                                                                 error))
9977                                         return -rte_errno;
9978                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9979                                 break;
9980                         }
9981                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9982                         /*
9983                          * Only one FLAG or MARK is supported per device flow
9984                          * right now. So the pointer to the tag resource must be
9985                          * zero before the register process.
9986                          */
9987                         MLX5_ASSERT(!handle->dvh.rix_tag);
9988                         if (flow_dv_tag_resource_register(dev, tag_be,
9989                                                           dev_flow, error))
9990                                 return -rte_errno;
9991                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9992                         dev_flow->dv.actions[actions_n++] =
9993                                         dev_flow->dv.tag_resource->action;
9994                         break;
9995                 case RTE_FLOW_ACTION_TYPE_MARK:
9996                         action_flags |= MLX5_FLOW_ACTION_MARK;
9997                         dev_flow->handle->mark = 1;
9998                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9999                                 const struct rte_flow_action_mark *mark =
10000                                         (const struct rte_flow_action_mark *)
10001                                                 actions->conf;
10002
10003                                 if (flow_dv_convert_action_mark(dev, mark,
10004                                                                 mhdr_res,
10005                                                                 error))
10006                                         return -rte_errno;
10007                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10008                                 break;
10009                         }
10010                         /* Fall-through */
10011                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10012                         /* Legacy (non-extensive) MARK action. */
10013                         tag_be = mlx5_flow_mark_set
10014                               (((const struct rte_flow_action_mark *)
10015                                (actions->conf))->id);
10016                         MLX5_ASSERT(!handle->dvh.rix_tag);
10017                         if (flow_dv_tag_resource_register(dev, tag_be,
10018                                                           dev_flow, error))
10019                                 return -rte_errno;
10020                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10021                         dev_flow->dv.actions[actions_n++] =
10022                                         dev_flow->dv.tag_resource->action;
10023                         break;
10024                 case RTE_FLOW_ACTION_TYPE_SET_META:
10025                         if (flow_dv_convert_action_set_meta
10026                                 (dev, mhdr_res, attr,
10027                                  (const struct rte_flow_action_set_meta *)
10028                                   actions->conf, error))
10029                                 return -rte_errno;
10030                         action_flags |= MLX5_FLOW_ACTION_SET_META;
10031                         break;
10032                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10033                         if (flow_dv_convert_action_set_tag
10034                                 (dev, mhdr_res,
10035                                  (const struct rte_flow_action_set_tag *)
10036                                   actions->conf, error))
10037                                 return -rte_errno;
10038                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10039                         break;
10040                 case RTE_FLOW_ACTION_TYPE_DROP:
10041                         action_flags |= MLX5_FLOW_ACTION_DROP;
10042                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10043                         break;
10044                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10045                         queue = actions->conf;
10046                         rss_desc->queue_num = 1;
10047                         rss_desc->queue[0] = queue->index;
10048                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10049                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10050                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10051                         num_of_dest++;
10052                         break;
10053                 case RTE_FLOW_ACTION_TYPE_RSS:
10054                         rss = actions->conf;
10055                         memcpy(rss_desc->queue, rss->queue,
10056                                rss->queue_num * sizeof(uint16_t));
10057                         rss_desc->queue_num = rss->queue_num;
10058                         /* NULL RSS key indicates default RSS key. */
10059                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10060                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10061                         /*
10062                          * rss->level and rss.types should be set in advance
10063                          * when expanding items for RSS.
10064                          */
10065                         action_flags |= MLX5_FLOW_ACTION_RSS;
10066                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
10067                                 MLX5_FLOW_FATE_SHARED_RSS :
10068                                 MLX5_FLOW_FATE_QUEUE;
10069                         break;
10070                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10071                         flow->age = (uint32_t)(uintptr_t)(action->conf);
10072                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
10073                         __atomic_fetch_add(&age_act->refcnt, 1,
10074                                            __ATOMIC_RELAXED);
10075                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10076                         action_flags |= MLX5_FLOW_ACTION_AGE;
10077                         break;
10078                 case RTE_FLOW_ACTION_TYPE_AGE:
10079                         if (priv->sh->flow_hit_aso_en && attr->group) {
10080                                 flow->age = flow_dv_translate_create_aso_age
10081                                                 (dev, action->conf, error);
10082                                 if (!flow->age)
10083                                         return rte_flow_error_set
10084                                                 (error, rte_errno,
10085                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10086                                                  NULL,
10087                                                  "can't create ASO age action");
10088                                 dev_flow->dv.actions[actions_n++] =
10089                                           (flow_aso_age_get_by_idx
10090                                                 (dev, flow->age))->dr_action;
10091                                 action_flags |= MLX5_FLOW_ACTION_AGE;
10092                                 break;
10093                         }
10094                         /* Fall-through */
10095                 case RTE_FLOW_ACTION_TYPE_COUNT:
10096                         if (!dev_conf->devx) {
10097                                 return rte_flow_error_set
10098                                               (error, ENOTSUP,
10099                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10100                                                NULL,
10101                                                "count action not supported");
10102                         }
10103                         /* Save information first, will apply later. */
10104                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10105                                 count = action->conf;
10106                         else
10107                                 age = action->conf;
10108                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10109                         break;
10110                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10111                         dev_flow->dv.actions[actions_n++] =
10112                                                 priv->sh->pop_vlan_action;
10113                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10114                         break;
10115                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10116                         if (!(action_flags &
10117                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10118                                 flow_dev_get_vlan_info_from_items(items, &vlan);
10119                         vlan.eth_proto = rte_be_to_cpu_16
10120                              ((((const struct rte_flow_action_of_push_vlan *)
10121                                                    actions->conf)->ethertype));
10122                         found_action = mlx5_flow_find_action
10123                                         (actions + 1,
10124                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10125                         if (found_action)
10126                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10127                         found_action = mlx5_flow_find_action
10128                                         (actions + 1,
10129                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10130                         if (found_action)
10131                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10132                         if (flow_dv_create_action_push_vlan
10133                                             (dev, attr, &vlan, dev_flow, error))
10134                                 return -rte_errno;
10135                         dev_flow->dv.actions[actions_n++] =
10136                                         dev_flow->dv.push_vlan_res->action;
10137                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10138                         break;
10139                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10140                         /* of_vlan_push action handled this action */
10141                         MLX5_ASSERT(action_flags &
10142                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10143                         break;
10144                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10145                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10146                                 break;
10147                         flow_dev_get_vlan_info_from_items(items, &vlan);
10148                         mlx5_update_vlan_vid_pcp(actions, &vlan);
10149                         /* If no VLAN push - this is a modify header action */
10150                         if (flow_dv_convert_action_modify_vlan_vid
10151                                                 (mhdr_res, actions, error))
10152                                 return -rte_errno;
10153                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10154                         break;
10155                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10156                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10157                         if (flow_dv_create_action_l2_encap(dev, actions,
10158                                                            dev_flow,
10159                                                            attr->transfer,
10160                                                            error))
10161                                 return -rte_errno;
10162                         dev_flow->dv.actions[actions_n++] =
10163                                         dev_flow->dv.encap_decap->action;
10164                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10165                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10166                                 sample_act->action_flags |=
10167                                                         MLX5_FLOW_ACTION_ENCAP;
10168                         break;
10169                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10170                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10171                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10172                                                            attr->transfer,
10173                                                            error))
10174                                 return -rte_errno;
10175                         dev_flow->dv.actions[actions_n++] =
10176                                         dev_flow->dv.encap_decap->action;
10177                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10178                         break;
10179                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10180                         /* Handle encap with preceding decap. */
10181                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10182                                 if (flow_dv_create_action_raw_encap
10183                                         (dev, actions, dev_flow, attr, error))
10184                                         return -rte_errno;
10185                                 dev_flow->dv.actions[actions_n++] =
10186                                         dev_flow->dv.encap_decap->action;
10187                         } else {
10188                                 /* Handle encap without preceding decap. */
10189                                 if (flow_dv_create_action_l2_encap
10190                                     (dev, actions, dev_flow, attr->transfer,
10191                                      error))
10192                                         return -rte_errno;
10193                                 dev_flow->dv.actions[actions_n++] =
10194                                         dev_flow->dv.encap_decap->action;
10195                         }
10196                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10197                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10198                                 sample_act->action_flags |=
10199                                                         MLX5_FLOW_ACTION_ENCAP;
10200                         break;
10201                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10202                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10203                                 ;
10204                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10205                                 if (flow_dv_create_action_l2_decap
10206                                     (dev, dev_flow, attr->transfer, error))
10207                                         return -rte_errno;
10208                                 dev_flow->dv.actions[actions_n++] =
10209                                         dev_flow->dv.encap_decap->action;
10210                         }
10211                         /* If decap is followed by encap, handle it at encap. */
10212                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10213                         break;
10214                 case RTE_FLOW_ACTION_TYPE_JUMP:
10215                         jump_group = ((const struct rte_flow_action_jump *)
10216                                                         action->conf)->group;
10217                         grp_info.std_tbl_fix = 0;
10218                         grp_info.skip_scale = 0;
10219                         ret = mlx5_flow_group_to_table(dev, tunnel,
10220                                                        jump_group,
10221                                                        &table,
10222                                                        &grp_info, error);
10223                         if (ret)
10224                                 return ret;
10225                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10226                                                        attr->transfer,
10227                                                        !!dev_flow->external,
10228                                                        tunnel, jump_group, 0,
10229                                                        error);
10230                         if (!tbl)
10231                                 return rte_flow_error_set
10232                                                 (error, errno,
10233                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10234                                                  NULL,
10235                                                  "cannot create jump action.");
10236                         if (flow_dv_jump_tbl_resource_register
10237                             (dev, tbl, dev_flow, error)) {
10238                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10239                                 return rte_flow_error_set
10240                                                 (error, errno,
10241                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10242                                                  NULL,
10243                                                  "cannot create jump action.");
10244                         }
10245                         dev_flow->dv.actions[actions_n++] =
10246                                         dev_flow->dv.jump->action;
10247                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10248                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10249                         break;
10250                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10251                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10252                         if (flow_dv_convert_action_modify_mac
10253                                         (mhdr_res, actions, error))
10254                                 return -rte_errno;
10255                         action_flags |= actions->type ==
10256                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10257                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10258                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10259                         break;
10260                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10261                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10262                         if (flow_dv_convert_action_modify_ipv4
10263                                         (mhdr_res, actions, error))
10264                                 return -rte_errno;
10265                         action_flags |= actions->type ==
10266                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10267                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10268                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10269                         break;
10270                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10271                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10272                         if (flow_dv_convert_action_modify_ipv6
10273                                         (mhdr_res, actions, error))
10274                                 return -rte_errno;
10275                         action_flags |= actions->type ==
10276                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10277                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10278                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10279                         break;
10280                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10281                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10282                         if (flow_dv_convert_action_modify_tp
10283                                         (mhdr_res, actions, items,
10284                                          &flow_attr, dev_flow, !!(action_flags &
10285                                          MLX5_FLOW_ACTION_DECAP), error))
10286                                 return -rte_errno;
10287                         action_flags |= actions->type ==
10288                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10289                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10290                                         MLX5_FLOW_ACTION_SET_TP_DST;
10291                         break;
10292                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10293                         if (flow_dv_convert_action_modify_dec_ttl
10294                                         (mhdr_res, items, &flow_attr, dev_flow,
10295                                          !!(action_flags &
10296                                          MLX5_FLOW_ACTION_DECAP), error))
10297                                 return -rte_errno;
10298                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10299                         break;
10300                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10301                         if (flow_dv_convert_action_modify_ttl
10302                                         (mhdr_res, actions, items, &flow_attr,
10303                                          dev_flow, !!(action_flags &
10304                                          MLX5_FLOW_ACTION_DECAP), error))
10305                                 return -rte_errno;
10306                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10307                         break;
10308                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10309                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10310                         if (flow_dv_convert_action_modify_tcp_seq
10311                                         (mhdr_res, actions, error))
10312                                 return -rte_errno;
10313                         action_flags |= actions->type ==
10314                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10315                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10316                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10317                         break;
10318
10319                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10320                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10321                         if (flow_dv_convert_action_modify_tcp_ack
10322                                         (mhdr_res, actions, error))
10323                                 return -rte_errno;
10324                         action_flags |= actions->type ==
10325                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10326                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10327                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10328                         break;
10329                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10330                         if (flow_dv_convert_action_set_reg
10331                                         (mhdr_res, actions, error))
10332                                 return -rte_errno;
10333                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10334                         break;
10335                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10336                         if (flow_dv_convert_action_copy_mreg
10337                                         (dev, mhdr_res, actions, error))
10338                                 return -rte_errno;
10339                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10340                         break;
10341                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10342                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10343                         dev_flow->handle->fate_action =
10344                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10345                         break;
10346                 case RTE_FLOW_ACTION_TYPE_METER:
10347                         mtr = actions->conf;
10348                         if (!flow->meter) {
10349                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10350                                                             attr, error);
10351                                 if (!fm)
10352                                         return rte_flow_error_set(error,
10353                                                 rte_errno,
10354                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10355                                                 NULL,
10356                                                 "meter not found "
10357                                                 "or invalid parameters");
10358                                 flow->meter = fm->idx;
10359                         }
10360                         /* Set the meter action. */
10361                         if (!fm) {
10362                                 fm = mlx5_ipool_get(priv->sh->ipool
10363                                                 [MLX5_IPOOL_MTR], flow->meter);
10364                                 if (!fm)
10365                                         return rte_flow_error_set(error,
10366                                                 rte_errno,
10367                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10368                                                 NULL,
10369                                                 "meter not found "
10370                                                 "or invalid parameters");
10371                         }
10372                         dev_flow->dv.actions[actions_n++] =
10373                                 fm->mfts->meter_action;
10374                         action_flags |= MLX5_FLOW_ACTION_METER;
10375                         break;
10376                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10377                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10378                                                               actions, error))
10379                                 return -rte_errno;
10380                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10381                         break;
10382                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10383                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10384                                                               actions, error))
10385                                 return -rte_errno;
10386                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10387                         break;
10388                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10389                         sample_act_pos = actions_n;
10390                         ret = flow_dv_translate_action_sample(dev,
10391                                                               actions,
10392                                                               dev_flow, attr,
10393                                                               &num_of_dest,
10394                                                               sample_actions,
10395                                                               &sample_res,
10396                                                               error);
10397                         if (ret < 0)
10398                                 return ret;
10399                         actions_n++;
10400                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10401                         /* put encap action into group if work with port id */
10402                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10403                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10404                                 sample_act->action_flags |=
10405                                                         MLX5_FLOW_ACTION_ENCAP;
10406                         break;
10407                 case RTE_FLOW_ACTION_TYPE_END:
10408                         actions_end = true;
10409                         if (mhdr_res->actions_num) {
10410                                 /* create modify action if needed. */
10411                                 if (flow_dv_modify_hdr_resource_register
10412                                         (dev, mhdr_res, dev_flow, error))
10413                                         return -rte_errno;
10414                                 dev_flow->dv.actions[modify_action_position] =
10415                                         handle->dvh.modify_hdr->action;
10416                         }
10417                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10418                                 flow->counter =
10419                                         flow_dv_translate_create_counter(dev,
10420                                                 dev_flow, count, age);
10421
10422                                 if (!flow->counter)
10423                                         return rte_flow_error_set
10424                                                 (error, rte_errno,
10425                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10426                                                 NULL,
10427                                                 "cannot create counter"
10428                                                 " object.");
10429                                 dev_flow->dv.actions[actions_n] =
10430                                           (flow_dv_counter_get_by_idx(dev,
10431                                           flow->counter, NULL))->action;
10432                                 actions_n++;
10433                         }
10434                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10435                                 ret = flow_dv_create_action_sample(dev,
10436                                                           dev_flow,
10437                                                           num_of_dest,
10438                                                           &sample_res,
10439                                                           &mdest_res,
10440                                                           sample_actions,
10441                                                           action_flags,
10442                                                           error);
10443                                 if (ret < 0)
10444                                         return rte_flow_error_set
10445                                                 (error, rte_errno,
10446                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10447                                                 NULL,
10448                                                 "cannot create sample action");
10449                                 if (num_of_dest > 1) {
10450                                         dev_flow->dv.actions[sample_act_pos] =
10451                                         dev_flow->dv.dest_array_res->action;
10452                                 } else {
10453                                         dev_flow->dv.actions[sample_act_pos] =
10454                                         dev_flow->dv.sample_res->verbs_action;
10455                                 }
10456                         }
10457                         break;
10458                 default:
10459                         break;
10460                 }
10461                 if (mhdr_res->actions_num &&
10462                     modify_action_position == UINT32_MAX)
10463                         modify_action_position = actions_n++;
10464         }
10465         /*
10466          * For multiple destination (sample action with ratio=1), the encap
10467          * action and port id action will be combined into group action.
10468          * So need remove the original these actions in the flow and only
10469          * use the sample action instead of.
10470          */
10471         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10472                 int i;
10473                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10474
10475                 for (i = 0; i < actions_n; i++) {
10476                         if ((sample_act->dr_encap_action &&
10477                                 sample_act->dr_encap_action ==
10478                                 dev_flow->dv.actions[i]) ||
10479                                 (sample_act->dr_port_id_action &&
10480                                 sample_act->dr_port_id_action ==
10481                                 dev_flow->dv.actions[i]))
10482                                 continue;
10483                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10484                 }
10485                 memcpy((void *)dev_flow->dv.actions,
10486                                 (void *)temp_actions,
10487                                 tmp_actions_n * sizeof(void *));
10488                 actions_n = tmp_actions_n;
10489         }
10490         dev_flow->dv.actions_n = actions_n;
10491         dev_flow->act_flags = action_flags;
10492         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10493                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10494                 int item_type = items->type;
10495
10496                 if (!mlx5_flow_os_item_supported(item_type))
10497                         return rte_flow_error_set(error, ENOTSUP,
10498                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10499                                                   NULL, "item not supported");
10500                 switch (item_type) {
10501                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10502                         flow_dv_translate_item_port_id
10503                                 (dev, match_mask, match_value, items, attr);
10504                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10505                         break;
10506                 case RTE_FLOW_ITEM_TYPE_ETH:
10507                         flow_dv_translate_item_eth(match_mask, match_value,
10508                                                    items, tunnel,
10509                                                    dev_flow->dv.group);
10510                         matcher.priority = action_flags &
10511                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10512                                         !dev_flow->external ?
10513                                         MLX5_PRIORITY_MAP_L3 :
10514                                         MLX5_PRIORITY_MAP_L2;
10515                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10516                                              MLX5_FLOW_LAYER_OUTER_L2;
10517                         break;
10518                 case RTE_FLOW_ITEM_TYPE_VLAN:
10519                         flow_dv_translate_item_vlan(dev_flow,
10520                                                     match_mask, match_value,
10521                                                     items, tunnel,
10522                                                     dev_flow->dv.group);
10523                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10524                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10525                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10526                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10527                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10528                         break;
10529                 case RTE_FLOW_ITEM_TYPE_IPV4:
10530                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10531                                                   &item_flags, &tunnel);
10532                         flow_dv_translate_item_ipv4(match_mask, match_value,
10533                                                     items, tunnel,
10534                                                     dev_flow->dv.group);
10535                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10536                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10537                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10538                         if (items->mask != NULL &&
10539                             ((const struct rte_flow_item_ipv4 *)
10540                              items->mask)->hdr.next_proto_id) {
10541                                 next_protocol =
10542                                         ((const struct rte_flow_item_ipv4 *)
10543                                          (items->spec))->hdr.next_proto_id;
10544                                 next_protocol &=
10545                                         ((const struct rte_flow_item_ipv4 *)
10546                                          (items->mask))->hdr.next_proto_id;
10547                         } else {
10548                                 /* Reset for inner layer. */
10549                                 next_protocol = 0xff;
10550                         }
10551                         break;
10552                 case RTE_FLOW_ITEM_TYPE_IPV6:
10553                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10554                                                   &item_flags, &tunnel);
10555                         flow_dv_translate_item_ipv6(match_mask, match_value,
10556                                                     items, tunnel,
10557                                                     dev_flow->dv.group);
10558                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10559                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10560                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10561                         if (items->mask != NULL &&
10562                             ((const struct rte_flow_item_ipv6 *)
10563                              items->mask)->hdr.proto) {
10564                                 next_protocol =
10565                                         ((const struct rte_flow_item_ipv6 *)
10566                                          items->spec)->hdr.proto;
10567                                 next_protocol &=
10568                                         ((const struct rte_flow_item_ipv6 *)
10569                                          items->mask)->hdr.proto;
10570                         } else {
10571                                 /* Reset for inner layer. */
10572                                 next_protocol = 0xff;
10573                         }
10574                         break;
10575                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10576                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10577                                                              match_value,
10578                                                              items, tunnel);
10579                         last_item = tunnel ?
10580                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10581                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10582                         if (items->mask != NULL &&
10583                             ((const struct rte_flow_item_ipv6_frag_ext *)
10584                              items->mask)->hdr.next_header) {
10585                                 next_protocol =
10586                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10587                                  items->spec)->hdr.next_header;
10588                                 next_protocol &=
10589                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10590                                  items->mask)->hdr.next_header;
10591                         } else {
10592                                 /* Reset for inner layer. */
10593                                 next_protocol = 0xff;
10594                         }
10595                         break;
10596                 case RTE_FLOW_ITEM_TYPE_TCP:
10597                         flow_dv_translate_item_tcp(match_mask, match_value,
10598                                                    items, tunnel);
10599                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10600                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10601                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10602                         break;
10603                 case RTE_FLOW_ITEM_TYPE_UDP:
10604                         flow_dv_translate_item_udp(match_mask, match_value,
10605                                                    items, tunnel);
10606                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10607                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10608                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10609                         break;
10610                 case RTE_FLOW_ITEM_TYPE_GRE:
10611                         flow_dv_translate_item_gre(match_mask, match_value,
10612                                                    items, tunnel);
10613                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10614                         last_item = MLX5_FLOW_LAYER_GRE;
10615                         break;
10616                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10617                         flow_dv_translate_item_gre_key(match_mask,
10618                                                        match_value, items);
10619                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10620                         break;
10621                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10622                         flow_dv_translate_item_nvgre(match_mask, match_value,
10623                                                      items, tunnel);
10624                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10625                         last_item = MLX5_FLOW_LAYER_GRE;
10626                         break;
10627                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10628                         flow_dv_translate_item_vxlan(match_mask, match_value,
10629                                                      items, tunnel);
10630                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10631                         last_item = MLX5_FLOW_LAYER_VXLAN;
10632                         break;
10633                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10634                         flow_dv_translate_item_vxlan_gpe(match_mask,
10635                                                          match_value, items,
10636                                                          tunnel);
10637                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10638                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10639                         break;
10640                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10641                         flow_dv_translate_item_geneve(match_mask, match_value,
10642                                                       items, tunnel);
10643                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10644                         last_item = MLX5_FLOW_LAYER_GENEVE;
10645                         break;
10646                 case RTE_FLOW_ITEM_TYPE_MPLS:
10647                         flow_dv_translate_item_mpls(match_mask, match_value,
10648                                                     items, last_item, tunnel);
10649                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10650                         last_item = MLX5_FLOW_LAYER_MPLS;
10651                         break;
10652                 case RTE_FLOW_ITEM_TYPE_MARK:
10653                         flow_dv_translate_item_mark(dev, match_mask,
10654                                                     match_value, items);
10655                         last_item = MLX5_FLOW_ITEM_MARK;
10656                         break;
10657                 case RTE_FLOW_ITEM_TYPE_META:
10658                         flow_dv_translate_item_meta(dev, match_mask,
10659                                                     match_value, attr, items);
10660                         last_item = MLX5_FLOW_ITEM_METADATA;
10661                         break;
10662                 case RTE_FLOW_ITEM_TYPE_ICMP:
10663                         flow_dv_translate_item_icmp(match_mask, match_value,
10664                                                     items, tunnel);
10665                         last_item = MLX5_FLOW_LAYER_ICMP;
10666                         break;
10667                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10668                         flow_dv_translate_item_icmp6(match_mask, match_value,
10669                                                       items, tunnel);
10670                         last_item = MLX5_FLOW_LAYER_ICMP6;
10671                         break;
10672                 case RTE_FLOW_ITEM_TYPE_TAG:
10673                         flow_dv_translate_item_tag(dev, match_mask,
10674                                                    match_value, items);
10675                         last_item = MLX5_FLOW_ITEM_TAG;
10676                         break;
10677                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10678                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10679                                                         match_value, items);
10680                         last_item = MLX5_FLOW_ITEM_TAG;
10681                         break;
10682                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10683                         flow_dv_translate_item_tx_queue(dev, match_mask,
10684                                                         match_value,
10685                                                         items);
10686                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10687                         break;
10688                 case RTE_FLOW_ITEM_TYPE_GTP:
10689                         flow_dv_translate_item_gtp(match_mask, match_value,
10690                                                    items, tunnel);
10691                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10692                         last_item = MLX5_FLOW_LAYER_GTP;
10693                         break;
10694                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10695                         ret = flow_dv_translate_item_gtp_psc(match_mask,
10696                                                           match_value,
10697                                                           items);
10698                         if (ret)
10699                                 return rte_flow_error_set(error, -ret,
10700                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10701                                         "cannot create GTP PSC item");
10702                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
10703                         break;
10704                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10705                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10706                                 /* Create it only the first time to be used. */
10707                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10708                                 if (ret)
10709                                         return rte_flow_error_set
10710                                                 (error, -ret,
10711                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10712                                                 NULL,
10713                                                 "cannot create eCPRI parser");
10714                         }
10715                         /* Adjust the length matcher and device flow value. */
10716                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10717                         dev_flow->dv.value.size =
10718                                         MLX5_ST_SZ_BYTES(fte_match_param);
10719                         flow_dv_translate_item_ecpri(dev, match_mask,
10720                                                      match_value, items);
10721                         /* No other protocol should follow eCPRI layer. */
10722                         last_item = MLX5_FLOW_LAYER_ECPRI;
10723                         break;
10724                 default:
10725                         break;
10726                 }
10727                 item_flags |= last_item;
10728         }
10729         /*
10730          * When E-Switch mode is enabled, we have two cases where we need to
10731          * set the source port manually.
10732          * The first one, is in case of Nic steering rule, and the second is
10733          * E-Switch rule where no port_id item was found. In both cases
10734          * the source port is set according the current port in use.
10735          */
10736         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10737             (priv->representor || priv->master)) {
10738                 if (flow_dv_translate_item_port_id(dev, match_mask,
10739                                                    match_value, NULL, attr))
10740                         return -rte_errno;
10741         }
10742 #ifdef RTE_LIBRTE_MLX5_DEBUG
10743         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10744                                               dev_flow->dv.value.buf));
10745 #endif
10746         /*
10747          * Layers may be already initialized from prefix flow if this dev_flow
10748          * is the suffix flow.
10749          */
10750         handle->layers |= item_flags;
10751         if (action_flags & MLX5_FLOW_ACTION_RSS)
10752                 flow_dv_hashfields_set(dev_flow, rss_desc);
10753         /* Register matcher. */
10754         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10755                                     matcher.mask.size);
10756         matcher.priority = mlx5_os_flow_adjust_priority(dev,
10757                                                         priority,
10758                                                         matcher.priority);
10759         /* reserved field no needs to be set to 0 here. */
10760         tbl_key.domain = attr->transfer;
10761         tbl_key.direction = attr->egress;
10762         tbl_key.table_id = dev_flow->dv.group;
10763         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10764                                      tunnel, attr->group, error))
10765                 return -rte_errno;
10766         return 0;
10767 }
10768
10769 /**
10770  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10771  * and tunnel.
10772  *
10773  * @param[in, out] action
10774  *   Shred RSS action holding hash RX queue objects.
10775  * @param[in] hash_fields
10776  *   Defines combination of packet fields to participate in RX hash.
10777  * @param[in] tunnel
10778  *   Tunnel type
10779  * @param[in] hrxq_idx
10780  *   Hash RX queue index to set.
10781  *
10782  * @return
10783  *   0 on success, otherwise negative errno value.
10784  */
10785 static int
10786 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10787                               const uint64_t hash_fields,
10788                               const int tunnel,
10789                               uint32_t hrxq_idx)
10790 {
10791         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10792
10793         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10794         case MLX5_RSS_HASH_IPV4:
10795                 hrxqs[0] = hrxq_idx;
10796                 return 0;
10797         case MLX5_RSS_HASH_IPV4_TCP:
10798                 hrxqs[1] = hrxq_idx;
10799                 return 0;
10800         case MLX5_RSS_HASH_IPV4_UDP:
10801                 hrxqs[2] = hrxq_idx;
10802                 return 0;
10803         case MLX5_RSS_HASH_IPV6:
10804                 hrxqs[3] = hrxq_idx;
10805                 return 0;
10806         case MLX5_RSS_HASH_IPV6_TCP:
10807                 hrxqs[4] = hrxq_idx;
10808                 return 0;
10809         case MLX5_RSS_HASH_IPV6_UDP:
10810                 hrxqs[5] = hrxq_idx;
10811                 return 0;
10812         case MLX5_RSS_HASH_NONE:
10813                 hrxqs[6] = hrxq_idx;
10814                 return 0;
10815         default:
10816                 return -1;
10817         }
10818 }
10819
10820 /**
10821  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10822  * and tunnel.
10823  *
10824  * @param[in] dev
10825  *   Pointer to the Ethernet device structure.
10826  * @param[in] idx
10827  *   Shared RSS action ID holding hash RX queue objects.
10828  * @param[in] hash_fields
10829  *   Defines combination of packet fields to participate in RX hash.
10830  * @param[in] tunnel
10831  *   Tunnel type
10832  *
10833  * @return
10834  *   Valid hash RX queue index, otherwise 0.
10835  */
10836 static uint32_t
10837 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10838                                  const uint64_t hash_fields,
10839                                  const int tunnel)
10840 {
10841         struct mlx5_priv *priv = dev->data->dev_private;
10842         struct mlx5_shared_action_rss *shared_rss =
10843             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10844         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10845                                                         shared_rss->hrxq_tunnel;
10846
10847         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10848         case MLX5_RSS_HASH_IPV4:
10849                 return hrxqs[0];
10850         case MLX5_RSS_HASH_IPV4_TCP:
10851                 return hrxqs[1];
10852         case MLX5_RSS_HASH_IPV4_UDP:
10853                 return hrxqs[2];
10854         case MLX5_RSS_HASH_IPV6:
10855                 return hrxqs[3];
10856         case MLX5_RSS_HASH_IPV6_TCP:
10857                 return hrxqs[4];
10858         case MLX5_RSS_HASH_IPV6_UDP:
10859                 return hrxqs[5];
10860         case MLX5_RSS_HASH_NONE:
10861                 return hrxqs[6];
10862         default:
10863                 return 0;
10864         }
10865 }
10866
10867 /**
10868  * Apply the flow to the NIC, lock free,
10869  * (mutex should be acquired by caller).
10870  *
10871  * @param[in] dev
10872  *   Pointer to the Ethernet device structure.
10873  * @param[in, out] flow
10874  *   Pointer to flow structure.
10875  * @param[out] error
10876  *   Pointer to error structure.
10877  *
10878  * @return
10879  *   0 on success, a negative errno value otherwise and rte_errno is set.
10880  */
10881 static int
10882 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10883               struct rte_flow_error *error)
10884 {
10885         struct mlx5_flow_dv_workspace *dv;
10886         struct mlx5_flow_handle *dh;
10887         struct mlx5_flow_handle_dv *dv_h;
10888         struct mlx5_flow *dev_flow;
10889         struct mlx5_priv *priv = dev->data->dev_private;
10890         uint32_t handle_idx;
10891         int n;
10892         int err;
10893         int idx;
10894         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10895         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10896
10897         MLX5_ASSERT(wks);
10898         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10899                 dev_flow = &wks->flows[idx];
10900                 dv = &dev_flow->dv;
10901                 dh = dev_flow->handle;
10902                 dv_h = &dh->dvh;
10903                 n = dv->actions_n;
10904                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10905                         if (dv->transfer) {
10906                                 dv->actions[n++] = priv->sh->esw_drop_action;
10907                         } else {
10908                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10909                                 dv->actions[n++] =
10910                                                 priv->drop_queue.hrxq->action;
10911                         }
10912                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10913                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
10914                         struct mlx5_hrxq *hrxq;
10915                         uint32_t hrxq_idx;
10916
10917                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
10918                                                     &hrxq_idx);
10919                         if (!hrxq) {
10920                                 rte_flow_error_set
10921                                         (error, rte_errno,
10922                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10923                                          "cannot get hash queue");
10924                                 goto error;
10925                         }
10926                         dh->rix_hrxq = hrxq_idx;
10927                         dv->actions[n++] = hrxq->action;
10928                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
10929                         struct mlx5_hrxq *hrxq = NULL;
10930                         uint32_t hrxq_idx;
10931
10932                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
10933                                                 rss_desc->shared_rss,
10934                                                 dev_flow->hash_fields,
10935                                                 !!(dh->layers &
10936                                                 MLX5_FLOW_LAYER_TUNNEL));
10937                         if (hrxq_idx)
10938                                 hrxq = mlx5_ipool_get
10939                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
10940                                          hrxq_idx);
10941                         if (!hrxq) {
10942                                 rte_flow_error_set
10943                                         (error, rte_errno,
10944                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10945                                          "cannot get hash queue");
10946                                 goto error;
10947                         }
10948                         dh->rix_srss = rss_desc->shared_rss;
10949                         dv->actions[n++] = hrxq->action;
10950                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10951                         if (!priv->sh->default_miss_action) {
10952                                 rte_flow_error_set
10953                                         (error, rte_errno,
10954                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10955                                          "default miss action not be created.");
10956                                 goto error;
10957                         }
10958                         dv->actions[n++] = priv->sh->default_miss_action;
10959                 }
10960                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10961                                                (void *)&dv->value, n,
10962                                                dv->actions, &dh->drv_flow);
10963                 if (err) {
10964                         rte_flow_error_set(error, errno,
10965                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10966                                            NULL,
10967                                            "hardware refuses to create flow");
10968                         goto error;
10969                 }
10970                 if (priv->vmwa_context &&
10971                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10972                         /*
10973                          * The rule contains the VLAN pattern.
10974                          * For VF we are going to create VLAN
10975                          * interface to make hypervisor set correct
10976                          * e-Switch vport context.
10977                          */
10978                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10979                 }
10980         }
10981         return 0;
10982 error:
10983         err = rte_errno; /* Save rte_errno before cleanup. */
10984         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10985                        handle_idx, dh, next) {
10986                 /* hrxq is union, don't clear it if the flag is not set. */
10987                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10988                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10989                         dh->rix_hrxq = 0;
10990                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
10991                         dh->rix_srss = 0;
10992                 }
10993                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10994                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10995         }
10996         rte_errno = err; /* Restore rte_errno. */
10997         return -rte_errno;
10998 }
10999
11000 void
11001 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11002                           struct mlx5_cache_entry *entry)
11003 {
11004         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11005                                                           entry);
11006
11007         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11008         mlx5_free(cache);
11009 }
11010
11011 /**
11012  * Release the flow matcher.
11013  *
11014  * @param dev
11015  *   Pointer to Ethernet device.
11016  * @param handle
11017  *   Pointer to mlx5_flow_handle.
11018  *
11019  * @return
11020  *   1 while a reference on it exists, 0 when freed.
11021  */
11022 static int
11023 flow_dv_matcher_release(struct rte_eth_dev *dev,
11024                         struct mlx5_flow_handle *handle)
11025 {
11026         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11027         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11028                                                             typeof(*tbl), tbl);
11029         int ret;
11030
11031         MLX5_ASSERT(matcher->matcher_object);
11032         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11033         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11034         return ret;
11035 }
11036
11037 /**
11038  * Release encap_decap resource.
11039  *
11040  * @param list
11041  *   Pointer to the hash list.
11042  * @param entry
11043  *   Pointer to exist resource entry object.
11044  */
11045 void
11046 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11047                               struct mlx5_hlist_entry *entry)
11048 {
11049         struct mlx5_dev_ctx_shared *sh = list->ctx;
11050         struct mlx5_flow_dv_encap_decap_resource *res =
11051                 container_of(entry, typeof(*res), entry);
11052
11053         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11054         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11055 }
11056
11057 /**
11058  * Release an encap/decap resource.
11059  *
11060  * @param dev
11061  *   Pointer to Ethernet device.
11062  * @param encap_decap_idx
11063  *   Index of encap decap resource.
11064  *
11065  * @return
11066  *   1 while a reference on it exists, 0 when freed.
11067  */
11068 static int
11069 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11070                                      uint32_t encap_decap_idx)
11071 {
11072         struct mlx5_priv *priv = dev->data->dev_private;
11073         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11074
11075         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11076                                         encap_decap_idx);
11077         if (!cache_resource)
11078                 return 0;
11079         MLX5_ASSERT(cache_resource->action);
11080         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11081                                      &cache_resource->entry);
11082 }
11083
11084 /**
11085  * Release an jump to table action resource.
11086  *
11087  * @param dev
11088  *   Pointer to Ethernet device.
11089  * @param handle
11090  *   Pointer to mlx5_flow_handle.
11091  *
11092  * @return
11093  *   1 while a reference on it exists, 0 when freed.
11094  */
11095 static int
11096 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11097                                   struct mlx5_flow_handle *handle)
11098 {
11099         struct mlx5_priv *priv = dev->data->dev_private;
11100         struct mlx5_flow_tbl_data_entry *tbl_data;
11101
11102         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11103                              handle->rix_jump);
11104         if (!tbl_data)
11105                 return 0;
11106         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11107 }
11108
11109 void
11110 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11111                          struct mlx5_hlist_entry *entry)
11112 {
11113         struct mlx5_flow_dv_modify_hdr_resource *res =
11114                 container_of(entry, typeof(*res), entry);
11115
11116         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11117         mlx5_free(entry);
11118 }
11119
11120 /**
11121  * Release a modify-header resource.
11122  *
11123  * @param dev
11124  *   Pointer to Ethernet device.
11125  * @param handle
11126  *   Pointer to mlx5_flow_handle.
11127  *
11128  * @return
11129  *   1 while a reference on it exists, 0 when freed.
11130  */
11131 static int
11132 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11133                                     struct mlx5_flow_handle *handle)
11134 {
11135         struct mlx5_priv *priv = dev->data->dev_private;
11136         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11137
11138         MLX5_ASSERT(entry->action);
11139         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11140 }
11141
11142 void
11143 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11144                           struct mlx5_cache_entry *entry)
11145 {
11146         struct mlx5_dev_ctx_shared *sh = list->ctx;
11147         struct mlx5_flow_dv_port_id_action_resource *cache =
11148                         container_of(entry, typeof(*cache), entry);
11149
11150         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11151         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11152 }
11153
11154 /**
11155  * Release port ID action resource.
11156  *
11157  * @param dev
11158  *   Pointer to Ethernet device.
11159  * @param handle
11160  *   Pointer to mlx5_flow_handle.
11161  *
11162  * @return
11163  *   1 while a reference on it exists, 0 when freed.
11164  */
11165 static int
11166 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11167                                         uint32_t port_id)
11168 {
11169         struct mlx5_priv *priv = dev->data->dev_private;
11170         struct mlx5_flow_dv_port_id_action_resource *cache;
11171
11172         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11173         if (!cache)
11174                 return 0;
11175         MLX5_ASSERT(cache->action);
11176         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11177                                      &cache->entry);
11178 }
11179
11180 /**
11181  * Release shared RSS action resource.
11182  *
11183  * @param dev
11184  *   Pointer to Ethernet device.
11185  * @param srss
11186  *   Shared RSS action index.
11187  */
11188 static void
11189 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11190 {
11191         struct mlx5_priv *priv = dev->data->dev_private;
11192         struct mlx5_shared_action_rss *shared_rss;
11193
11194         shared_rss = mlx5_ipool_get
11195                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11196         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11197 }
11198
11199 void
11200 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11201                             struct mlx5_cache_entry *entry)
11202 {
11203         struct mlx5_dev_ctx_shared *sh = list->ctx;
11204         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11205                         container_of(entry, typeof(*cache), entry);
11206
11207         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11208         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11209 }
11210
11211 /**
11212  * Release push vlan action resource.
11213  *
11214  * @param dev
11215  *   Pointer to Ethernet device.
11216  * @param handle
11217  *   Pointer to mlx5_flow_handle.
11218  *
11219  * @return
11220  *   1 while a reference on it exists, 0 when freed.
11221  */
11222 static int
11223 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11224                                           struct mlx5_flow_handle *handle)
11225 {
11226         struct mlx5_priv *priv = dev->data->dev_private;
11227         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11228         uint32_t idx = handle->dvh.rix_push_vlan;
11229
11230         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11231         if (!cache)
11232                 return 0;
11233         MLX5_ASSERT(cache->action);
11234         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11235                                      &cache->entry);
11236 }
11237
11238 /**
11239  * Release the fate resource.
11240  *
11241  * @param dev
11242  *   Pointer to Ethernet device.
11243  * @param handle
11244  *   Pointer to mlx5_flow_handle.
11245  */
11246 static void
11247 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11248                                struct mlx5_flow_handle *handle)
11249 {
11250         if (!handle->rix_fate)
11251                 return;
11252         switch (handle->fate_action) {
11253         case MLX5_FLOW_FATE_QUEUE:
11254                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11255                 break;
11256         case MLX5_FLOW_FATE_JUMP:
11257                 flow_dv_jump_tbl_resource_release(dev, handle);
11258                 break;
11259         case MLX5_FLOW_FATE_PORT_ID:
11260                 flow_dv_port_id_action_resource_release(dev,
11261                                 handle->rix_port_id_action);
11262                 break;
11263         default:
11264                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11265                 break;
11266         }
11267         handle->rix_fate = 0;
11268 }
11269
11270 void
11271 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11272                          struct mlx5_cache_entry *entry)
11273 {
11274         struct mlx5_flow_dv_sample_resource *cache_resource =
11275                         container_of(entry, typeof(*cache_resource), entry);
11276         struct rte_eth_dev *dev = cache_resource->dev;
11277         struct mlx5_priv *priv = dev->data->dev_private;
11278
11279         if (cache_resource->verbs_action)
11280                 claim_zero(mlx5_flow_os_destroy_flow_action
11281                                 (cache_resource->verbs_action));
11282         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11283                 if (cache_resource->default_miss)
11284                         claim_zero(mlx5_flow_os_destroy_flow_action
11285                           (cache_resource->default_miss));
11286         }
11287         if (cache_resource->normal_path_tbl)
11288                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11289                         cache_resource->normal_path_tbl);
11290         flow_dv_sample_sub_actions_release(dev,
11291                                 &cache_resource->sample_idx);
11292         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11293                         cache_resource->idx);
11294         DRV_LOG(DEBUG, "sample resource %p: removed",
11295                 (void *)cache_resource);
11296 }
11297
11298 /**
11299  * Release an sample resource.
11300  *
11301  * @param dev
11302  *   Pointer to Ethernet device.
11303  * @param handle
11304  *   Pointer to mlx5_flow_handle.
11305  *
11306  * @return
11307  *   1 while a reference on it exists, 0 when freed.
11308  */
11309 static int
11310 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11311                                      struct mlx5_flow_handle *handle)
11312 {
11313         struct mlx5_priv *priv = dev->data->dev_private;
11314         struct mlx5_flow_dv_sample_resource *cache_resource;
11315
11316         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11317                          handle->dvh.rix_sample);
11318         if (!cache_resource)
11319                 return 0;
11320         MLX5_ASSERT(cache_resource->verbs_action);
11321         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11322                                      &cache_resource->entry);
11323 }
11324
11325 void
11326 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11327                              struct mlx5_cache_entry *entry)
11328 {
11329         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11330                         container_of(entry, typeof(*cache_resource), entry);
11331         struct rte_eth_dev *dev = cache_resource->dev;
11332         struct mlx5_priv *priv = dev->data->dev_private;
11333         uint32_t i = 0;
11334
11335         MLX5_ASSERT(cache_resource->action);
11336         if (cache_resource->action)
11337                 claim_zero(mlx5_flow_os_destroy_flow_action
11338                                         (cache_resource->action));
11339         for (; i < cache_resource->num_of_dest; i++)
11340                 flow_dv_sample_sub_actions_release(dev,
11341                                 &cache_resource->sample_idx[i]);
11342         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11343                         cache_resource->idx);
11344         DRV_LOG(DEBUG, "destination array resource %p: removed",
11345                 (void *)cache_resource);
11346 }
11347
11348 /**
11349  * Release an destination array resource.
11350  *
11351  * @param dev
11352  *   Pointer to Ethernet device.
11353  * @param handle
11354  *   Pointer to mlx5_flow_handle.
11355  *
11356  * @return
11357  *   1 while a reference on it exists, 0 when freed.
11358  */
11359 static int
11360 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11361                                     struct mlx5_flow_handle *handle)
11362 {
11363         struct mlx5_priv *priv = dev->data->dev_private;
11364         struct mlx5_flow_dv_dest_array_resource *cache;
11365
11366         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11367                                handle->dvh.rix_dest_array);
11368         if (!cache)
11369                 return 0;
11370         MLX5_ASSERT(cache->action);
11371         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11372                                      &cache->entry);
11373 }
11374
11375 /**
11376  * Remove the flow from the NIC but keeps it in memory.
11377  * Lock free, (mutex should be acquired by caller).
11378  *
11379  * @param[in] dev
11380  *   Pointer to Ethernet device.
11381  * @param[in, out] flow
11382  *   Pointer to flow structure.
11383  */
11384 static void
11385 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11386 {
11387         struct mlx5_flow_handle *dh;
11388         uint32_t handle_idx;
11389         struct mlx5_priv *priv = dev->data->dev_private;
11390
11391         if (!flow)
11392                 return;
11393         handle_idx = flow->dev_handles;
11394         while (handle_idx) {
11395                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11396                                     handle_idx);
11397                 if (!dh)
11398                         return;
11399                 if (dh->drv_flow) {
11400                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11401                         dh->drv_flow = NULL;
11402                 }
11403                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11404                         flow_dv_fate_resource_release(dev, dh);
11405                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11406                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11407                 handle_idx = dh->next.next;
11408         }
11409 }
11410
11411 /**
11412  * Remove the flow from the NIC and the memory.
11413  * Lock free, (mutex should be acquired by caller).
11414  *
11415  * @param[in] dev
11416  *   Pointer to the Ethernet device structure.
11417  * @param[in, out] flow
11418  *   Pointer to flow structure.
11419  */
11420 static void
11421 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11422 {
11423         struct mlx5_flow_handle *dev_handle;
11424         struct mlx5_priv *priv = dev->data->dev_private;
11425         uint32_t srss = 0;
11426
11427         if (!flow)
11428                 return;
11429         flow_dv_remove(dev, flow);
11430         if (flow->counter) {
11431                 flow_dv_counter_free(dev, flow->counter);
11432                 flow->counter = 0;
11433         }
11434         if (flow->meter) {
11435                 struct mlx5_flow_meter *fm;
11436
11437                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11438                                     flow->meter);
11439                 if (fm)
11440                         mlx5_flow_meter_detach(fm);
11441                 flow->meter = 0;
11442         }
11443         if (flow->age)
11444                 flow_dv_aso_age_release(dev, flow->age);
11445         while (flow->dev_handles) {
11446                 uint32_t tmp_idx = flow->dev_handles;
11447
11448                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11449                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11450                 if (!dev_handle)
11451                         return;
11452                 flow->dev_handles = dev_handle->next.next;
11453                 if (dev_handle->dvh.matcher)
11454                         flow_dv_matcher_release(dev, dev_handle);
11455                 if (dev_handle->dvh.rix_sample)
11456                         flow_dv_sample_resource_release(dev, dev_handle);
11457                 if (dev_handle->dvh.rix_dest_array)
11458                         flow_dv_dest_array_resource_release(dev, dev_handle);
11459                 if (dev_handle->dvh.rix_encap_decap)
11460                         flow_dv_encap_decap_resource_release(dev,
11461                                 dev_handle->dvh.rix_encap_decap);
11462                 if (dev_handle->dvh.modify_hdr)
11463                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11464                 if (dev_handle->dvh.rix_push_vlan)
11465                         flow_dv_push_vlan_action_resource_release(dev,
11466                                                                   dev_handle);
11467                 if (dev_handle->dvh.rix_tag)
11468                         flow_dv_tag_release(dev,
11469                                             dev_handle->dvh.rix_tag);
11470                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11471                         flow_dv_fate_resource_release(dev, dev_handle);
11472                 else if (!srss)
11473                         srss = dev_handle->rix_srss;
11474                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11475                            tmp_idx);
11476         }
11477         if (srss)
11478                 flow_dv_shared_rss_action_release(dev, srss);
11479 }
11480
11481 /**
11482  * Release array of hash RX queue objects.
11483  * Helper function.
11484  *
11485  * @param[in] dev
11486  *   Pointer to the Ethernet device structure.
11487  * @param[in, out] hrxqs
11488  *   Array of hash RX queue objects.
11489  *
11490  * @return
11491  *   Total number of references to hash RX queue objects in *hrxqs* array
11492  *   after this operation.
11493  */
11494 static int
11495 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11496                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11497 {
11498         size_t i;
11499         int remaining = 0;
11500
11501         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11502                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11503
11504                 if (!ret)
11505                         (*hrxqs)[i] = 0;
11506                 remaining += ret;
11507         }
11508         return remaining;
11509 }
11510
11511 /**
11512  * Release all hash RX queue objects representing shared RSS action.
11513  *
11514  * @param[in] dev
11515  *   Pointer to the Ethernet device structure.
11516  * @param[in, out] action
11517  *   Shared RSS action to remove hash RX queue objects from.
11518  *
11519  * @return
11520  *   Total number of references to hash RX queue objects stored in *action*
11521  *   after this operation.
11522  *   Expected to be 0 if no external references held.
11523  */
11524 static int
11525 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11526                                  struct mlx5_shared_action_rss *action)
11527 {
11528         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11529                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11530 }
11531
11532 /**
11533  * Setup shared RSS action.
11534  * Prepare set of hash RX queue objects sufficient to handle all valid
11535  * hash_fields combinations (see enum ibv_rx_hash_fields).
11536  *
11537  * @param[in] dev
11538  *   Pointer to the Ethernet device structure.
11539  * @param[in] action_idx
11540  *   Shared RSS action ipool index.
11541  * @param[in, out] action
11542  *   Partially initialized shared RSS action.
11543  * @param[out] error
11544  *   Perform verbose error reporting if not NULL. Initialized in case of
11545  *   error only.
11546  *
11547  * @return
11548  *   0 on success, otherwise negative errno value.
11549  */
11550 static int
11551 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11552                            uint32_t action_idx,
11553                            struct mlx5_shared_action_rss *action,
11554                            struct rte_flow_error *error)
11555 {
11556         struct mlx5_flow_rss_desc rss_desc = { 0 };
11557         size_t i;
11558         int err;
11559
11560         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11561                 return rte_flow_error_set(error, rte_errno,
11562                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11563                                           "cannot setup indirection table");
11564         }
11565         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11566         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11567         rss_desc.const_q = action->origin.queue;
11568         rss_desc.queue_num = action->origin.queue_num;
11569         /* Set non-zero value to indicate a shared RSS. */
11570         rss_desc.shared_rss = action_idx;
11571         rss_desc.ind_tbl = action->ind_tbl;
11572         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11573                 uint32_t hrxq_idx;
11574                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11575                 int tunnel;
11576
11577                 for (tunnel = 0; tunnel < 2; tunnel++) {
11578                         rss_desc.tunnel = tunnel;
11579                         rss_desc.hash_fields = hash_fields;
11580                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11581                         if (!hrxq_idx) {
11582                                 rte_flow_error_set
11583                                         (error, rte_errno,
11584                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11585                                          "cannot get hash queue");
11586                                 goto error_hrxq_new;
11587                         }
11588                         err = __flow_dv_action_rss_hrxq_set
11589                                 (action, hash_fields, tunnel, hrxq_idx);
11590                         MLX5_ASSERT(!err);
11591                 }
11592         }
11593         return 0;
11594 error_hrxq_new:
11595         err = rte_errno;
11596         __flow_dv_action_rss_hrxqs_release(dev, action);
11597         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11598                 action->ind_tbl = NULL;
11599         rte_errno = err;
11600         return -rte_errno;
11601 }
11602
11603 /**
11604  * Create shared RSS action.
11605  *
11606  * @param[in] dev
11607  *   Pointer to the Ethernet device structure.
11608  * @param[in] conf
11609  *   Shared action configuration.
11610  * @param[in] rss
11611  *   RSS action specification used to create shared action.
11612  * @param[out] error
11613  *   Perform verbose error reporting if not NULL. Initialized in case of
11614  *   error only.
11615  *
11616  * @return
11617  *   A valid shared action ID in case of success, 0 otherwise and
11618  *   rte_errno is set.
11619  */
11620 static uint32_t
11621 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11622                             const struct rte_flow_shared_action_conf *conf,
11623                             const struct rte_flow_action_rss *rss,
11624                             struct rte_flow_error *error)
11625 {
11626         struct mlx5_priv *priv = dev->data->dev_private;
11627         struct mlx5_shared_action_rss *shared_action = NULL;
11628         void *queue = NULL;
11629         struct rte_flow_action_rss *origin;
11630         const uint8_t *rss_key;
11631         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11632         uint32_t idx;
11633
11634         RTE_SET_USED(conf);
11635         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11636                             0, SOCKET_ID_ANY);
11637         shared_action = mlx5_ipool_zmalloc
11638                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11639         if (!shared_action || !queue) {
11640                 rte_flow_error_set(error, ENOMEM,
11641                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11642                                    "cannot allocate resource memory");
11643                 goto error_rss_init;
11644         }
11645         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11646                 rte_flow_error_set(error, E2BIG,
11647                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11648                                    "rss action number out of range");
11649                 goto error_rss_init;
11650         }
11651         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11652                                              sizeof(*shared_action->ind_tbl),
11653                                              0, SOCKET_ID_ANY);
11654         if (!shared_action->ind_tbl) {
11655                 rte_flow_error_set(error, ENOMEM,
11656                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11657                                    "cannot allocate resource memory");
11658                 goto error_rss_init;
11659         }
11660         memcpy(queue, rss->queue, queue_size);
11661         shared_action->ind_tbl->queues = queue;
11662         shared_action->ind_tbl->queues_n = rss->queue_num;
11663         origin = &shared_action->origin;
11664         origin->func = rss->func;
11665         origin->level = rss->level;
11666         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11667         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11668         /* NULL RSS key indicates default RSS key. */
11669         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11670         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11671         origin->key = &shared_action->key[0];
11672         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11673         origin->queue = queue;
11674         origin->queue_num = rss->queue_num;
11675         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11676                 goto error_rss_init;
11677         rte_spinlock_init(&shared_action->action_rss_sl);
11678         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11679         rte_spinlock_lock(&priv->shared_act_sl);
11680         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11681                      &priv->rss_shared_actions, idx, shared_action, next);
11682         rte_spinlock_unlock(&priv->shared_act_sl);
11683         return idx;
11684 error_rss_init:
11685         if (shared_action) {
11686                 if (shared_action->ind_tbl)
11687                         mlx5_free(shared_action->ind_tbl);
11688                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11689                                 idx);
11690         }
11691         if (queue)
11692                 mlx5_free(queue);
11693         return 0;
11694 }
11695
11696 /**
11697  * Destroy the shared RSS action.
11698  * Release related hash RX queue objects.
11699  *
11700  * @param[in] dev
11701  *   Pointer to the Ethernet device structure.
11702  * @param[in] idx
11703  *   The shared RSS action object ID to be removed.
11704  * @param[out] error
11705  *   Perform verbose error reporting if not NULL. Initialized in case of
11706  *   error only.
11707  *
11708  * @return
11709  *   0 on success, otherwise negative errno value.
11710  */
11711 static int
11712 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11713                              struct rte_flow_error *error)
11714 {
11715         struct mlx5_priv *priv = dev->data->dev_private;
11716         struct mlx5_shared_action_rss *shared_rss =
11717             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11718         uint32_t old_refcnt = 1;
11719         int remaining;
11720         uint16_t *queue = NULL;
11721
11722         if (!shared_rss)
11723                 return rte_flow_error_set(error, EINVAL,
11724                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11725                                           "invalid shared action");
11726         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11727         if (remaining)
11728                 return rte_flow_error_set(error, EBUSY,
11729                                           RTE_FLOW_ERROR_TYPE_ACTION,
11730                                           NULL,
11731                                           "shared rss hrxq has references");
11732         queue = shared_rss->ind_tbl->queues;
11733         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11734         if (remaining)
11735                 return rte_flow_error_set(error, EBUSY,
11736                                           RTE_FLOW_ERROR_TYPE_ACTION,
11737                                           NULL,
11738                                           "shared rss indirection table has"
11739                                           " references");
11740         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11741                                          0, 0, __ATOMIC_ACQUIRE,
11742                                          __ATOMIC_RELAXED))
11743                 return rte_flow_error_set(error, EBUSY,
11744                                           RTE_FLOW_ERROR_TYPE_ACTION,
11745                                           NULL,
11746                                           "shared rss has references");
11747         mlx5_free(queue);
11748         rte_spinlock_lock(&priv->shared_act_sl);
11749         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11750                      &priv->rss_shared_actions, idx, shared_rss, next);
11751         rte_spinlock_unlock(&priv->shared_act_sl);
11752         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11753                         idx);
11754         return 0;
11755 }
11756
11757 /**
11758  * Create shared action, lock free,
11759  * (mutex should be acquired by caller).
11760  * Dispatcher for action type specific call.
11761  *
11762  * @param[in] dev
11763  *   Pointer to the Ethernet device structure.
11764  * @param[in] conf
11765  *   Shared action configuration.
11766  * @param[in] action
11767  *   Action specification used to create shared action.
11768  * @param[out] error
11769  *   Perform verbose error reporting if not NULL. Initialized in case of
11770  *   error only.
11771  *
11772  * @return
11773  *   A valid shared action handle in case of success, NULL otherwise and
11774  *   rte_errno is set.
11775  */
11776 static struct rte_flow_shared_action *
11777 flow_dv_action_create(struct rte_eth_dev *dev,
11778                       const struct rte_flow_shared_action_conf *conf,
11779                       const struct rte_flow_action *action,
11780                       struct rte_flow_error *err)
11781 {
11782         uint32_t idx = 0;
11783         uint32_t ret = 0;
11784
11785         switch (action->type) {
11786         case RTE_FLOW_ACTION_TYPE_RSS:
11787                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11788                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11789                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11790                 break;
11791         case RTE_FLOW_ACTION_TYPE_AGE:
11792                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11793                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11794                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11795                 if (ret) {
11796                         struct mlx5_aso_age_action *aso_age =
11797                                               flow_aso_age_get_by_idx(dev, ret);
11798
11799                         if (!aso_age->age_params.context)
11800                                 aso_age->age_params.context =
11801                                                          (void *)(uintptr_t)idx;
11802                 }
11803                 break;
11804         default:
11805                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11806                                    NULL, "action type not supported");
11807                 break;
11808         }
11809         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11810 }
11811
11812 /**
11813  * Destroy the shared action.
11814  * Release action related resources on the NIC and the memory.
11815  * Lock free, (mutex should be acquired by caller).
11816  * Dispatcher for action type specific call.
11817  *
11818  * @param[in] dev
11819  *   Pointer to the Ethernet device structure.
11820  * @param[in] action
11821  *   The shared action object to be removed.
11822  * @param[out] error
11823  *   Perform verbose error reporting if not NULL. Initialized in case of
11824  *   error only.
11825  *
11826  * @return
11827  *   0 on success, otherwise negative errno value.
11828  */
11829 static int
11830 flow_dv_action_destroy(struct rte_eth_dev *dev,
11831                        struct rte_flow_shared_action *action,
11832                        struct rte_flow_error *error)
11833 {
11834         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11835         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11836         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11837         int ret;
11838
11839         switch (type) {
11840         case MLX5_SHARED_ACTION_TYPE_RSS:
11841                 return __flow_dv_action_rss_release(dev, idx, error);
11842         case MLX5_SHARED_ACTION_TYPE_AGE:
11843                 ret = flow_dv_aso_age_release(dev, idx);
11844                 if (ret)
11845                         /*
11846                          * In this case, the last flow has a reference will
11847                          * actually release the age action.
11848                          */
11849                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11850                                 " released with references %d.", idx, ret);
11851                 return 0;
11852         default:
11853                 return rte_flow_error_set(error, ENOTSUP,
11854                                           RTE_FLOW_ERROR_TYPE_ACTION,
11855                                           NULL,
11856                                           "action type not supported");
11857         }
11858 }
11859
11860 /**
11861  * Updates in place shared RSS action configuration.
11862  *
11863  * @param[in] dev
11864  *   Pointer to the Ethernet device structure.
11865  * @param[in] idx
11866  *   The shared RSS action object ID to be updated.
11867  * @param[in] action_conf
11868  *   RSS action specification used to modify *shared_rss*.
11869  * @param[out] error
11870  *   Perform verbose error reporting if not NULL. Initialized in case of
11871  *   error only.
11872  *
11873  * @return
11874  *   0 on success, otherwise negative errno value.
11875  * @note: currently only support update of RSS queues.
11876  */
11877 static int
11878 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11879                             const struct rte_flow_action_rss *action_conf,
11880                             struct rte_flow_error *error)
11881 {
11882         struct mlx5_priv *priv = dev->data->dev_private;
11883         struct mlx5_shared_action_rss *shared_rss =
11884             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11885         int ret = 0;
11886         void *queue = NULL;
11887         uint16_t *queue_old = NULL;
11888         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11889
11890         if (!shared_rss)
11891                 return rte_flow_error_set(error, EINVAL,
11892                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11893                                           "invalid shared action to update");
11894         queue = mlx5_malloc(MLX5_MEM_ZERO,
11895                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11896                             0, SOCKET_ID_ANY);
11897         if (!queue)
11898                 return rte_flow_error_set(error, ENOMEM,
11899                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11900                                           NULL,
11901                                           "cannot allocate resource memory");
11902         memcpy(queue, action_conf->queue, queue_size);
11903         MLX5_ASSERT(shared_rss->ind_tbl);
11904         rte_spinlock_lock(&shared_rss->action_rss_sl);
11905         queue_old = shared_rss->ind_tbl->queues;
11906         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
11907                                         queue, action_conf->queue_num, true);
11908         if (ret) {
11909                 mlx5_free(queue);
11910                 ret = rte_flow_error_set(error, rte_errno,
11911                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11912                                           "cannot update indirection table");
11913         } else {
11914                 mlx5_free(queue_old);
11915                 shared_rss->origin.queue = queue;
11916                 shared_rss->origin.queue_num = action_conf->queue_num;
11917         }
11918         rte_spinlock_unlock(&shared_rss->action_rss_sl);
11919         return ret;
11920 }
11921
11922 /**
11923  * Updates in place shared action configuration, lock free,
11924  * (mutex should be acquired by caller).
11925  *
11926  * @param[in] dev
11927  *   Pointer to the Ethernet device structure.
11928  * @param[in] action
11929  *   The shared action object to be updated.
11930  * @param[in] action_conf
11931  *   Action specification used to modify *action*.
11932  *   *action_conf* should be of type correlating with type of the *action*,
11933  *   otherwise considered as invalid.
11934  * @param[out] error
11935  *   Perform verbose error reporting if not NULL. Initialized in case of
11936  *   error only.
11937  *
11938  * @return
11939  *   0 on success, otherwise negative errno value.
11940  */
11941 static int
11942 flow_dv_action_update(struct rte_eth_dev *dev,
11943                         struct rte_flow_shared_action *action,
11944                         const void *action_conf,
11945                         struct rte_flow_error *err)
11946 {
11947         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11948         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11949         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11950
11951         switch (type) {
11952         case MLX5_SHARED_ACTION_TYPE_RSS:
11953                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
11954         default:
11955                 return rte_flow_error_set(err, ENOTSUP,
11956                                           RTE_FLOW_ERROR_TYPE_ACTION,
11957                                           NULL,
11958                                           "action type update not supported");
11959         }
11960 }
11961
11962 static int
11963 flow_dv_action_query(struct rte_eth_dev *dev,
11964                      const struct rte_flow_shared_action *action, void *data,
11965                      struct rte_flow_error *error)
11966 {
11967         struct mlx5_age_param *age_param;
11968         struct rte_flow_query_age *resp;
11969         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11970         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11971         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11972
11973         switch (type) {
11974         case MLX5_SHARED_ACTION_TYPE_AGE:
11975                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
11976                 resp = data;
11977                 resp->aged = __atomic_load_n(&age_param->state,
11978                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
11979                                                                           1 : 0;
11980                 resp->sec_since_last_hit_valid = !resp->aged;
11981                 if (resp->sec_since_last_hit_valid)
11982                         resp->sec_since_last_hit = __atomic_load_n
11983                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11984                 return 0;
11985         default:
11986                 return rte_flow_error_set(error, ENOTSUP,
11987                                           RTE_FLOW_ERROR_TYPE_ACTION,
11988                                           NULL,
11989                                           "action type query not supported");
11990         }
11991 }
11992
11993 /**
11994  * Query a dv flow  rule for its statistics via devx.
11995  *
11996  * @param[in] dev
11997  *   Pointer to Ethernet device.
11998  * @param[in] flow
11999  *   Pointer to the sub flow.
12000  * @param[out] data
12001  *   data retrieved by the query.
12002  * @param[out] error
12003  *   Perform verbose error reporting if not NULL.
12004  *
12005  * @return
12006  *   0 on success, a negative errno value otherwise and rte_errno is set.
12007  */
12008 static int
12009 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12010                     void *data, struct rte_flow_error *error)
12011 {
12012         struct mlx5_priv *priv = dev->data->dev_private;
12013         struct rte_flow_query_count *qc = data;
12014
12015         if (!priv->config.devx)
12016                 return rte_flow_error_set(error, ENOTSUP,
12017                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12018                                           NULL,
12019                                           "counters are not supported");
12020         if (flow->counter) {
12021                 uint64_t pkts, bytes;
12022                 struct mlx5_flow_counter *cnt;
12023
12024                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12025                                                  NULL);
12026                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12027                                                &bytes);
12028
12029                 if (err)
12030                         return rte_flow_error_set(error, -err,
12031                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12032                                         NULL, "cannot read counters");
12033                 qc->hits_set = 1;
12034                 qc->bytes_set = 1;
12035                 qc->hits = pkts - cnt->hits;
12036                 qc->bytes = bytes - cnt->bytes;
12037                 if (qc->reset) {
12038                         cnt->hits = pkts;
12039                         cnt->bytes = bytes;
12040                 }
12041                 return 0;
12042         }
12043         return rte_flow_error_set(error, EINVAL,
12044                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12045                                   NULL,
12046                                   "counters are not available");
12047 }
12048
12049 /**
12050  * Query a flow rule AGE action for aging information.
12051  *
12052  * @param[in] dev
12053  *   Pointer to Ethernet device.
12054  * @param[in] flow
12055  *   Pointer to the sub flow.
12056  * @param[out] data
12057  *   data retrieved by the query.
12058  * @param[out] error
12059  *   Perform verbose error reporting if not NULL.
12060  *
12061  * @return
12062  *   0 on success, a negative errno value otherwise and rte_errno is set.
12063  */
12064 static int
12065 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12066                   void *data, struct rte_flow_error *error)
12067 {
12068         struct rte_flow_query_age *resp = data;
12069         struct mlx5_age_param *age_param;
12070
12071         if (flow->age) {
12072                 struct mlx5_aso_age_action *act =
12073                                      flow_aso_age_get_by_idx(dev, flow->age);
12074
12075                 age_param = &act->age_params;
12076         } else if (flow->counter) {
12077                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12078
12079                 if (!age_param || !age_param->timeout)
12080                         return rte_flow_error_set
12081                                         (error, EINVAL,
12082                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12083                                          NULL, "cannot read age data");
12084         } else {
12085                 return rte_flow_error_set(error, EINVAL,
12086                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12087                                           NULL, "age data not available");
12088         }
12089         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12090                                      AGE_TMOUT ? 1 : 0;
12091         resp->sec_since_last_hit_valid = !resp->aged;
12092         if (resp->sec_since_last_hit_valid)
12093                 resp->sec_since_last_hit = __atomic_load_n
12094                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12095         return 0;
12096 }
12097
12098 /**
12099  * Query a flow.
12100  *
12101  * @see rte_flow_query()
12102  * @see rte_flow_ops
12103  */
12104 static int
12105 flow_dv_query(struct rte_eth_dev *dev,
12106               struct rte_flow *flow __rte_unused,
12107               const struct rte_flow_action *actions __rte_unused,
12108               void *data __rte_unused,
12109               struct rte_flow_error *error __rte_unused)
12110 {
12111         int ret = -EINVAL;
12112
12113         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12114                 switch (actions->type) {
12115                 case RTE_FLOW_ACTION_TYPE_VOID:
12116                         break;
12117                 case RTE_FLOW_ACTION_TYPE_COUNT:
12118                         ret = flow_dv_query_count(dev, flow, data, error);
12119                         break;
12120                 case RTE_FLOW_ACTION_TYPE_AGE:
12121                         ret = flow_dv_query_age(dev, flow, data, error);
12122                         break;
12123                 default:
12124                         return rte_flow_error_set(error, ENOTSUP,
12125                                                   RTE_FLOW_ERROR_TYPE_ACTION,
12126                                                   actions,
12127                                                   "action not supported");
12128                 }
12129         }
12130         return ret;
12131 }
12132
12133 /**
12134  * Destroy the meter table set.
12135  * Lock free, (mutex should be acquired by caller).
12136  *
12137  * @param[in] dev
12138  *   Pointer to Ethernet device.
12139  * @param[in] tbl
12140  *   Pointer to the meter table set.
12141  *
12142  * @return
12143  *   Always 0.
12144  */
12145 static int
12146 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12147                         struct mlx5_meter_domains_infos *tbl)
12148 {
12149         struct mlx5_priv *priv = dev->data->dev_private;
12150         struct mlx5_meter_domains_infos *mtd =
12151                                 (struct mlx5_meter_domains_infos *)tbl;
12152
12153         if (!mtd || !priv->config.dv_flow_en)
12154                 return 0;
12155         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12156                 claim_zero(mlx5_flow_os_destroy_flow
12157                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12158         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12159                 claim_zero(mlx5_flow_os_destroy_flow
12160                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12161         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12162                 claim_zero(mlx5_flow_os_destroy_flow
12163                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12164         if (mtd->egress.color_matcher)
12165                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12166                            (mtd->egress.color_matcher));
12167         if (mtd->egress.any_matcher)
12168                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12169                            (mtd->egress.any_matcher));
12170         if (mtd->egress.tbl)
12171                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12172         if (mtd->egress.sfx_tbl)
12173                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12174         if (mtd->ingress.color_matcher)
12175                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12176                            (mtd->ingress.color_matcher));
12177         if (mtd->ingress.any_matcher)
12178                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12179                            (mtd->ingress.any_matcher));
12180         if (mtd->ingress.tbl)
12181                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12182         if (mtd->ingress.sfx_tbl)
12183                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12184                                              mtd->ingress.sfx_tbl);
12185         if (mtd->transfer.color_matcher)
12186                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12187                            (mtd->transfer.color_matcher));
12188         if (mtd->transfer.any_matcher)
12189                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12190                            (mtd->transfer.any_matcher));
12191         if (mtd->transfer.tbl)
12192                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12193         if (mtd->transfer.sfx_tbl)
12194                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12195                                              mtd->transfer.sfx_tbl);
12196         if (mtd->drop_actn)
12197                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12198         mlx5_free(mtd);
12199         return 0;
12200 }
12201
12202 /* Number of meter flow actions, count and jump or count and drop. */
12203 #define METER_ACTIONS 2
12204
12205 /**
12206  * Create specify domain meter table and suffix table.
12207  *
12208  * @param[in] dev
12209  *   Pointer to Ethernet device.
12210  * @param[in,out] mtb
12211  *   Pointer to DV meter table set.
12212  * @param[in] egress
12213  *   Table attribute.
12214  * @param[in] transfer
12215  *   Table attribute.
12216  * @param[in] color_reg_c_idx
12217  *   Reg C index for color match.
12218  *
12219  * @return
12220  *   0 on success, -1 otherwise and rte_errno is set.
12221  */
12222 static int
12223 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12224                            struct mlx5_meter_domains_infos *mtb,
12225                            uint8_t egress, uint8_t transfer,
12226                            uint32_t color_reg_c_idx)
12227 {
12228         struct mlx5_priv *priv = dev->data->dev_private;
12229         struct mlx5_dev_ctx_shared *sh = priv->sh;
12230         struct mlx5_flow_dv_match_params mask = {
12231                 .size = sizeof(mask.buf),
12232         };
12233         struct mlx5_flow_dv_match_params value = {
12234                 .size = sizeof(value.buf),
12235         };
12236         struct mlx5dv_flow_matcher_attr dv_attr = {
12237                 .type = IBV_FLOW_ATTR_NORMAL,
12238                 .priority = 0,
12239                 .match_criteria_enable = 0,
12240                 .match_mask = (void *)&mask,
12241         };
12242         void *actions[METER_ACTIONS];
12243         struct mlx5_meter_domain_info *dtb;
12244         struct rte_flow_error error;
12245         int i = 0;
12246         int ret;
12247
12248         if (transfer)
12249                 dtb = &mtb->transfer;
12250         else if (egress)
12251                 dtb = &mtb->egress;
12252         else
12253                 dtb = &mtb->ingress;
12254         /* Create the meter table with METER level. */
12255         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12256                                             egress, transfer, false, NULL, 0,
12257                                             0, &error);
12258         if (!dtb->tbl) {
12259                 DRV_LOG(ERR, "Failed to create meter policer table.");
12260                 return -1;
12261         }
12262         /* Create the meter suffix table with SUFFIX level. */
12263         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12264                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12265                                             egress, transfer, false, NULL, 0,
12266                                             0, &error);
12267         if (!dtb->sfx_tbl) {
12268                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12269                 return -1;
12270         }
12271         /* Create matchers, Any and Color. */
12272         dv_attr.priority = 3;
12273         dv_attr.match_criteria_enable = 0;
12274         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12275                                                &dtb->any_matcher);
12276         if (ret) {
12277                 DRV_LOG(ERR, "Failed to create meter"
12278                              " policer default matcher.");
12279                 goto error_exit;
12280         }
12281         dv_attr.priority = 0;
12282         dv_attr.match_criteria_enable =
12283                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12284         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12285                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12286         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12287                                                &dtb->color_matcher);
12288         if (ret) {
12289                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12290                 goto error_exit;
12291         }
12292         if (mtb->count_actns[RTE_MTR_DROPPED])
12293                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12294         actions[i++] = mtb->drop_actn;
12295         /* Default rule: lowest priority, match any, actions: drop. */
12296         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12297                                        actions,
12298                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12299         if (ret) {
12300                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12301                 goto error_exit;
12302         }
12303         return 0;
12304 error_exit:
12305         return -1;
12306 }
12307
12308 /**
12309  * Create the needed meter and suffix tables.
12310  * Lock free, (mutex should be acquired by caller).
12311  *
12312  * @param[in] dev
12313  *   Pointer to Ethernet device.
12314  * @param[in] fm
12315  *   Pointer to the flow meter.
12316  *
12317  * @return
12318  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12319  */
12320 static struct mlx5_meter_domains_infos *
12321 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12322                        const struct mlx5_flow_meter *fm)
12323 {
12324         struct mlx5_priv *priv = dev->data->dev_private;
12325         struct mlx5_meter_domains_infos *mtb;
12326         int ret;
12327         int i;
12328
12329         if (!priv->mtr_en) {
12330                 rte_errno = ENOTSUP;
12331                 return NULL;
12332         }
12333         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12334         if (!mtb) {
12335                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12336                 return NULL;
12337         }
12338         /* Create meter count actions */
12339         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12340                 struct mlx5_flow_counter *cnt;
12341                 if (!fm->policer_stats.cnt[i])
12342                         continue;
12343                 cnt = flow_dv_counter_get_by_idx(dev,
12344                       fm->policer_stats.cnt[i], NULL);
12345                 mtb->count_actns[i] = cnt->action;
12346         }
12347         /* Create drop action. */
12348         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12349         if (ret) {
12350                 DRV_LOG(ERR, "Failed to create drop action.");
12351                 goto error_exit;
12352         }
12353         /* Egress meter table. */
12354         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12355         if (ret) {
12356                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12357                 goto error_exit;
12358         }
12359         /* Ingress meter table. */
12360         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12361         if (ret) {
12362                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12363                 goto error_exit;
12364         }
12365         /* FDB meter table. */
12366         if (priv->config.dv_esw_en) {
12367                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12368                                                  priv->mtr_color_reg);
12369                 if (ret) {
12370                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12371                         goto error_exit;
12372                 }
12373         }
12374         return mtb;
12375 error_exit:
12376         flow_dv_destroy_mtr_tbl(dev, mtb);
12377         return NULL;
12378 }
12379
12380 /**
12381  * Destroy domain policer rule.
12382  *
12383  * @param[in] dt
12384  *   Pointer to domain table.
12385  */
12386 static void
12387 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12388 {
12389         int i;
12390
12391         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12392                 if (dt->policer_rules[i]) {
12393                         claim_zero(mlx5_flow_os_destroy_flow
12394                                    (dt->policer_rules[i]));
12395                         dt->policer_rules[i] = NULL;
12396                 }
12397         }
12398         if (dt->jump_actn) {
12399                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12400                 dt->jump_actn = NULL;
12401         }
12402 }
12403
12404 /**
12405  * Destroy policer rules.
12406  *
12407  * @param[in] dev
12408  *   Pointer to Ethernet device.
12409  * @param[in] fm
12410  *   Pointer to flow meter structure.
12411  * @param[in] attr
12412  *   Pointer to flow attributes.
12413  *
12414  * @return
12415  *   Always 0.
12416  */
12417 static int
12418 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12419                               const struct mlx5_flow_meter *fm,
12420                               const struct rte_flow_attr *attr)
12421 {
12422         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12423
12424         if (!mtb)
12425                 return 0;
12426         if (attr->egress)
12427                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12428         if (attr->ingress)
12429                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12430         if (attr->transfer)
12431                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12432         return 0;
12433 }
12434
12435 /**
12436  * Create specify domain meter policer rule.
12437  *
12438  * @param[in] fm
12439  *   Pointer to flow meter structure.
12440  * @param[in] mtb
12441  *   Pointer to DV meter table set.
12442  * @param[in] mtr_reg_c
12443  *   Color match REG_C.
12444  *
12445  * @return
12446  *   0 on success, -1 otherwise.
12447  */
12448 static int
12449 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12450                                     struct mlx5_meter_domain_info *dtb,
12451                                     uint8_t mtr_reg_c)
12452 {
12453         struct mlx5_flow_dv_match_params matcher = {
12454                 .size = sizeof(matcher.buf),
12455         };
12456         struct mlx5_flow_dv_match_params value = {
12457                 .size = sizeof(value.buf),
12458         };
12459         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12460         void *actions[METER_ACTIONS];
12461         int i;
12462         int ret = 0;
12463
12464         /* Create jump action. */
12465         if (!dtb->jump_actn)
12466                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12467                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12468         if (ret) {
12469                 DRV_LOG(ERR, "Failed to create policer jump action.");
12470                 goto error;
12471         }
12472         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12473                 int j = 0;
12474
12475                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12476                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12477                 if (mtb->count_actns[i])
12478                         actions[j++] = mtb->count_actns[i];
12479                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12480                         actions[j++] = mtb->drop_actn;
12481                 else
12482                         actions[j++] = dtb->jump_actn;
12483                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12484                                                (void *)&value, j, actions,
12485                                                &dtb->policer_rules[i]);
12486                 if (ret) {
12487                         DRV_LOG(ERR, "Failed to create policer rule.");
12488                         goto error;
12489                 }
12490         }
12491         return 0;
12492 error:
12493         rte_errno = errno;
12494         return -1;
12495 }
12496
12497 /**
12498  * Create policer rules.
12499  *
12500  * @param[in] dev
12501  *   Pointer to Ethernet device.
12502  * @param[in] fm
12503  *   Pointer to flow meter structure.
12504  * @param[in] attr
12505  *   Pointer to flow attributes.
12506  *
12507  * @return
12508  *   0 on success, -1 otherwise.
12509  */
12510 static int
12511 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12512                              struct mlx5_flow_meter *fm,
12513                              const struct rte_flow_attr *attr)
12514 {
12515         struct mlx5_priv *priv = dev->data->dev_private;
12516         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12517         int ret;
12518
12519         if (attr->egress) {
12520                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12521                                                 priv->mtr_color_reg);
12522                 if (ret) {
12523                         DRV_LOG(ERR, "Failed to create egress policer.");
12524                         goto error;
12525                 }
12526         }
12527         if (attr->ingress) {
12528                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12529                                                 priv->mtr_color_reg);
12530                 if (ret) {
12531                         DRV_LOG(ERR, "Failed to create ingress policer.");
12532                         goto error;
12533                 }
12534         }
12535         if (attr->transfer) {
12536                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12537                                                 priv->mtr_color_reg);
12538                 if (ret) {
12539                         DRV_LOG(ERR, "Failed to create transfer policer.");
12540                         goto error;
12541                 }
12542         }
12543         return 0;
12544 error:
12545         flow_dv_destroy_policer_rules(dev, fm, attr);
12546         return -1;
12547 }
12548
12549 /**
12550  * Validate the batch counter support in root table.
12551  *
12552  * Create a simple flow with invalid counter and drop action on root table to
12553  * validate if batch counter with offset on root table is supported or not.
12554  *
12555  * @param[in] dev
12556  *   Pointer to rte_eth_dev structure.
12557  *
12558  * @return
12559  *   0 on success, a negative errno value otherwise and rte_errno is set.
12560  */
12561 int
12562 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12563 {
12564         struct mlx5_priv *priv = dev->data->dev_private;
12565         struct mlx5_dev_ctx_shared *sh = priv->sh;
12566         struct mlx5_flow_dv_match_params mask = {
12567                 .size = sizeof(mask.buf),
12568         };
12569         struct mlx5_flow_dv_match_params value = {
12570                 .size = sizeof(value.buf),
12571         };
12572         struct mlx5dv_flow_matcher_attr dv_attr = {
12573                 .type = IBV_FLOW_ATTR_NORMAL,
12574                 .priority = 0,
12575                 .match_criteria_enable = 0,
12576                 .match_mask = (void *)&mask,
12577         };
12578         void *actions[2] = { 0 };
12579         struct mlx5_flow_tbl_resource *tbl = NULL;
12580         struct mlx5_devx_obj *dcs = NULL;
12581         void *matcher = NULL;
12582         void *flow = NULL;
12583         int ret = -1;
12584
12585         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12586         if (!tbl)
12587                 goto err;
12588         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12589         if (!dcs)
12590                 goto err;
12591         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12592                                                     &actions[0]);
12593         if (ret)
12594                 goto err;
12595         actions[1] = priv->drop_queue.hrxq->action;
12596         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12597         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12598                                                &matcher);
12599         if (ret)
12600                 goto err;
12601         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12602                                        actions, &flow);
12603 err:
12604         /*
12605          * If batch counter with offset is not supported, the driver will not
12606          * validate the invalid offset value, flow create should success.
12607          * In this case, it means batch counter is not supported in root table.
12608          *
12609          * Otherwise, if flow create is failed, counter offset is supported.
12610          */
12611         if (flow) {
12612                 DRV_LOG(INFO, "Batch counter is not supported in root "
12613                               "table. Switch to fallback mode.");
12614                 rte_errno = ENOTSUP;
12615                 ret = -rte_errno;
12616                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12617         } else {
12618                 /* Check matcher to make sure validate fail at flow create. */
12619                 if (!matcher || (matcher && errno != EINVAL))
12620                         DRV_LOG(ERR, "Unexpected error in counter offset "
12621                                      "support detection");
12622                 ret = 0;
12623         }
12624         if (actions[0])
12625                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12626         if (matcher)
12627                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12628         if (tbl)
12629                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12630         if (dcs)
12631                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12632         return ret;
12633 }
12634
12635 /**
12636  * Query a devx counter.
12637  *
12638  * @param[in] dev
12639  *   Pointer to the Ethernet device structure.
12640  * @param[in] cnt
12641  *   Index to the flow counter.
12642  * @param[in] clear
12643  *   Set to clear the counter statistics.
12644  * @param[out] pkts
12645  *   The statistics value of packets.
12646  * @param[out] bytes
12647  *   The statistics value of bytes.
12648  *
12649  * @return
12650  *   0 on success, otherwise return -1.
12651  */
12652 static int
12653 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12654                       uint64_t *pkts, uint64_t *bytes)
12655 {
12656         struct mlx5_priv *priv = dev->data->dev_private;
12657         struct mlx5_flow_counter *cnt;
12658         uint64_t inn_pkts, inn_bytes;
12659         int ret;
12660
12661         if (!priv->config.devx)
12662                 return -1;
12663
12664         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12665         if (ret)
12666                 return -1;
12667         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12668         *pkts = inn_pkts - cnt->hits;
12669         *bytes = inn_bytes - cnt->bytes;
12670         if (clear) {
12671                 cnt->hits = inn_pkts;
12672                 cnt->bytes = inn_bytes;
12673         }
12674         return 0;
12675 }
12676
12677 /**
12678  * Get aged-out flows.
12679  *
12680  * @param[in] dev
12681  *   Pointer to the Ethernet device structure.
12682  * @param[in] context
12683  *   The address of an array of pointers to the aged-out flows contexts.
12684  * @param[in] nb_contexts
12685  *   The length of context array pointers.
12686  * @param[out] error
12687  *   Perform verbose error reporting if not NULL. Initialized in case of
12688  *   error only.
12689  *
12690  * @return
12691  *   how many contexts get in success, otherwise negative errno value.
12692  *   if nb_contexts is 0, return the amount of all aged contexts.
12693  *   if nb_contexts is not 0 , return the amount of aged flows reported
12694  *   in the context array.
12695  * @note: only stub for now
12696  */
12697 static int
12698 flow_get_aged_flows(struct rte_eth_dev *dev,
12699                     void **context,
12700                     uint32_t nb_contexts,
12701                     struct rte_flow_error *error)
12702 {
12703         struct mlx5_priv *priv = dev->data->dev_private;
12704         struct mlx5_age_info *age_info;
12705         struct mlx5_age_param *age_param;
12706         struct mlx5_flow_counter *counter;
12707         struct mlx5_aso_age_action *act;
12708         int nb_flows = 0;
12709
12710         if (nb_contexts && !context)
12711                 return rte_flow_error_set(error, EINVAL,
12712                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12713                                           NULL, "empty context");
12714         age_info = GET_PORT_AGE_INFO(priv);
12715         rte_spinlock_lock(&age_info->aged_sl);
12716         LIST_FOREACH(act, &age_info->aged_aso, next) {
12717                 nb_flows++;
12718                 if (nb_contexts) {
12719                         context[nb_flows - 1] =
12720                                                 act->age_params.context;
12721                         if (!(--nb_contexts))
12722                                 break;
12723                 }
12724         }
12725         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12726                 nb_flows++;
12727                 if (nb_contexts) {
12728                         age_param = MLX5_CNT_TO_AGE(counter);
12729                         context[nb_flows - 1] = age_param->context;
12730                         if (!(--nb_contexts))
12731                                 break;
12732                 }
12733         }
12734         rte_spinlock_unlock(&age_info->aged_sl);
12735         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12736         return nb_flows;
12737 }
12738
12739 /*
12740  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12741  */
12742 static uint32_t
12743 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12744 {
12745         return flow_dv_counter_alloc(dev, 0);
12746 }
12747
12748 /**
12749  * Validate shared action.
12750  * Dispatcher for action type specific validation.
12751  *
12752  * @param[in] dev
12753  *   Pointer to the Ethernet device structure.
12754  * @param[in] conf
12755  *   Shared action configuration.
12756  * @param[in] action
12757  *   The shared action object to validate.
12758  * @param[out] error
12759  *   Perform verbose error reporting if not NULL. Initialized in case of
12760  *   error only.
12761  *
12762  * @return
12763  *   0 on success, otherwise negative errno value.
12764  */
12765 static int
12766 flow_dv_action_validate(struct rte_eth_dev *dev,
12767                         const struct rte_flow_shared_action_conf *conf,
12768                         const struct rte_flow_action *action,
12769                         struct rte_flow_error *err)
12770 {
12771         struct mlx5_priv *priv = dev->data->dev_private;
12772
12773         RTE_SET_USED(conf);
12774         switch (action->type) {
12775         case RTE_FLOW_ACTION_TYPE_RSS:
12776                 return mlx5_validate_action_rss(dev, action, err);
12777         case RTE_FLOW_ACTION_TYPE_AGE:
12778                 if (!priv->sh->aso_age_mng)
12779                         return rte_flow_error_set(err, ENOTSUP,
12780                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12781                                                 NULL,
12782                                              "shared age action not supported");
12783                 return flow_dv_validate_action_age(0, action, dev, err);
12784         default:
12785                 return rte_flow_error_set(err, ENOTSUP,
12786                                           RTE_FLOW_ERROR_TYPE_ACTION,
12787                                           NULL,
12788                                           "action type not supported");
12789         }
12790 }
12791
12792 static int
12793 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12794 {
12795         struct mlx5_priv *priv = dev->data->dev_private;
12796         int ret = 0;
12797
12798         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12799                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
12800                                                 flags);
12801                 if (ret != 0)
12802                         return ret;
12803         }
12804         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12805                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
12806                 if (ret != 0)
12807                         return ret;
12808         }
12809         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12810                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
12811                 if (ret != 0)
12812                         return ret;
12813         }
12814         return 0;
12815 }
12816
12817 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12818         .validate = flow_dv_validate,
12819         .prepare = flow_dv_prepare,
12820         .translate = flow_dv_translate,
12821         .apply = flow_dv_apply,
12822         .remove = flow_dv_remove,
12823         .destroy = flow_dv_destroy,
12824         .query = flow_dv_query,
12825         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12826         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12827         .create_policer_rules = flow_dv_create_policer_rules,
12828         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12829         .counter_alloc = flow_dv_counter_allocate,
12830         .counter_free = flow_dv_counter_free,
12831         .counter_query = flow_dv_counter_query,
12832         .get_aged_flows = flow_get_aged_flows,
12833         .action_validate = flow_dv_action_validate,
12834         .action_create = flow_dv_action_create,
12835         .action_destroy = flow_dv_action_destroy,
12836         .action_update = flow_dv_action_update,
12837         .action_query = flow_dv_action_query,
12838         .sync_domain = flow_dv_sync_domain,
12839 };
12840
12841 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12842