drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 /**
  88  * Initialize flow attributes structure according to flow items' types.
  89  *
  90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  91  * mode. For tunnel mode, the items to be modified are the outermost ones.
  92  *
  93  * @param[in] item
  94  *   Pointer to item specification.
  95  * @param[out] attr
  96  *   Pointer to flow attributes structure.
  97  * @param[in] dev_flow
  98  *   Pointer to the sub flow.
  99  * @param[in] tunnel_decap
 100  *   Whether action is after tunnel decapsulation.
 101  */
 102 static void
 103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 105 {
 106         uint64_t layers = dev_flow->handle->layers;
 107
 108         /*
 109          * If layers is already initialized, it means this dev_flow is the
 110          * suffix flow, the layers flags is set by the prefix flow. Need to
 111          * use the layer flags from prefix flow as the suffix flow may not
 112          * have the user defined items as the flow is split.
 113          */
 114         if (layers) {
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 116                         attr->ipv4 = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 118                         attr->ipv6 = 1;
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 120                         attr->tcp = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 122                         attr->udp = 1;
 123                 attr->valid = 1;
 124                 return;
 125         }
 126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 127                 uint8_t next_protocol = 0xff;
 128                 switch (item->type) {
 129                 case RTE_FLOW_ITEM_TYPE_GRE:
 130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 134                 case RTE_FLOW_ITEM_TYPE_MPLS:
 135                         if (tunnel_decap)
 136                                 attr->attr = 0;
 137                         break;
 138                 case RTE_FLOW_ITEM_TYPE_IPV4:
 139                         if (!attr->ipv6)
 140                                 attr->ipv4 = 1;
 141                         if (item->mask != NULL &&
 142                             ((const struct rte_flow_item_ipv4 *)
 143                             item->mask)->hdr.next_proto_id)
 144                                 next_protocol =
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->spec))->hdr.next_proto_id &
 147                                     ((const struct rte_flow_item_ipv4 *)
 148                                       (item->mask))->hdr.next_proto_id;
 149                         if ((next_protocol == IPPROTO_IPIP ||
 150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 151                                 attr->attr = 0;
 152                         break;
 153                 case RTE_FLOW_ITEM_TYPE_IPV6:
 154                         if (!attr->ipv4)
 155                                 attr->ipv6 = 1;
 156                         if (item->mask != NULL &&
 157                             ((const struct rte_flow_item_ipv6 *)
 158                             item->mask)->hdr.proto)
 159                                 next_protocol =
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->spec))->hdr.proto &
 162                                     ((const struct rte_flow_item_ipv6 *)
 163                                       (item->mask))->hdr.proto;
 164                         if ((next_protocol == IPPROTO_IPIP ||
 165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 166                                 attr->attr = 0;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_UDP:
 169                         if (!attr->tcp)
 170                                 attr->udp = 1;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_TCP:
 173                         if (!attr->udp)
 174                                 attr->tcp = 1;
 175                         break;
 176                 default:
 177                         break;
 178                 }
 179         }
 180         attr->valid = 1;
 181 }
 182
 183 /**
 184  * Convert rte_mtr_color to mlx5 color.
 185  *
 186  * @param[in] rcol
 187  *   rte_mtr_color.
 188  *
 189  * @return
 190  *   mlx5 color.
 191  */
 192 static int
 193 rte_col_2_mlx5_col(enum rte_color rcol)
 194 {
 195         switch (rcol) {
 196         case RTE_COLOR_GREEN:
 197                 return MLX5_FLOW_COLOR_GREEN;
 198         case RTE_COLOR_YELLOW:
 199                 return MLX5_FLOW_COLOR_YELLOW;
 200         case RTE_COLOR_RED:
 201                 return MLX5_FLOW_COLOR_RED;
 202         default:
 203                 break;
 204         }
 205         return MLX5_FLOW_COLOR_UNDEFINED;
 206 }
 207
 208 struct field_modify_info {
 209         uint32_t size; /* Size of field in protocol header, in bytes. */
 210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 211         enum mlx5_modification_field id;
 212 };
 213
 214 struct field_modify_info modify_eth[] = {
 215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_vlan_out_first_vid[] = {
 223         /* Size in bits !!! */
 224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv4[] = {
 229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 231         {4, 12, MLX5_MODI_OUT_SIPV4},
 232         {4, 16, MLX5_MODI_OUT_DIPV4},
 233         {0, 0, 0},
 234 };
 235
 236 struct field_modify_info modify_ipv6[] = {
 237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_udp[] = {
 251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 253         {0, 0, 0},
 254 };
 255
 256 struct field_modify_info modify_tcp[] = {
 257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 261         {0, 0, 0},
 262 };
 263
 264 static void
 265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 266                           uint8_t next_protocol, uint64_t *item_flags,
 267                           int *tunnel)
 268 {
 269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 271         if (next_protocol == IPPROTO_IPIP) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 273                 *tunnel = 1;
 274         }
 275         if (next_protocol == IPPROTO_IPV6) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 277                 *tunnel = 1;
 278         }
 279 }
 280
 281 /* Update VLAN's VID/PCP based on input rte_flow_action.
 282  *
 283  * @param[in] action
 284  *   Pointer to struct rte_flow_action.
 285  * @param[out] vlan
 286  *   Pointer to struct rte_vlan_hdr.
 287  */
 288 static void
 289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 290                          struct rte_vlan_hdr *vlan)
 291 {
 292         uint16_t vlan_tci;
 293         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 294                 vlan_tci =
 295                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 296                                                action->conf)->vlan_pcp;
 297                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 298                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 299                 vlan->vlan_tci |= vlan_tci;
 300         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 301                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 302                 vlan->vlan_tci |= rte_be_to_cpu_16
 303                     (((const struct rte_flow_action_of_set_vlan_vid *)
 304                                              action->conf)->vlan_vid);
 305         }
 306 }
 307
 308 /**
 309  * Fetch 1, 2, 3 or 4 byte field from the byte array
 310  * and return as unsigned integer in host-endian format.
 311  *
 312  * @param[in] data
 313  *   Pointer to data array.
 314  * @param[in] size
 315  *   Size of field to extract.
 316  *
 317  * @return
 318  *   converted field in host endian format.
 319  */
 320 static inline uint32_t
 321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 322 {
 323         uint32_t ret;
 324
 325         switch (size) {
 326         case 1:
 327                 ret = *data;
 328                 break;
 329         case 2:
 330                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 331                 break;
 332         case 3:
 333                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 334                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 335                 break;
 336         case 4:
 337                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 338                 break;
 339         default:
 340                 MLX5_ASSERT(false);
 341                 ret = 0;
 342                 break;
 343         }
 344         return ret;
 345 }
 346
 347 /**
 348  * Convert modify-header action to DV specification.
 349  *
 350  * Data length of each action is determined by provided field description
 351  * and the item mask. Data bit offset and width of each action is determined
 352  * by provided item mask.
 353  *
 354  * @param[in] item
 355  *   Pointer to item specification.
 356  * @param[in] field
 357  *   Pointer to field modification information.
 358  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 359  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 360  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 361  * @param[in] dcopy
 362  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 363  *   Negative offset value sets the same offset as source offset.
 364  *   size field is ignored, value is taken from source field.
 365  * @param[in,out] resource
 366  *   Pointer to the modify-header resource.
 367  * @param[in] type
 368  *   Type of modification.
 369  * @param[out] error
 370  *   Pointer to the error structure.
 371  *
 372  * @return
 373  *   0 on success, a negative errno value otherwise and rte_errno is set.
 374  */
 375 static int
 376 flow_dv_convert_modify_action(struct rte_flow_item *item,
 377                               struct field_modify_info *field,
 378                               struct field_modify_info *dcopy,
 379                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 380                               uint32_t type, struct rte_flow_error *error)
 381 {
 382         uint32_t i = resource->actions_num;
 383         struct mlx5_modification_cmd *actions = resource->actions;
 384
 385         /*
 386          * The item and mask are provided in big-endian format.
 387          * The fields should be presented as in big-endian format either.
 388          * Mask must be always present, it defines the actual field width.
 389          */
 390         MLX5_ASSERT(item->mask);
 391         MLX5_ASSERT(field->size);
 392         do {
 393                 unsigned int size_b;
 394                 unsigned int off_b;
 395                 uint32_t mask;
 396                 uint32_t data;
 397
 398                 if (i >= MLX5_MAX_MODIFY_NUM)
 399                         return rte_flow_error_set(error, EINVAL,
 400                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 401                                  "too many items to modify");
 402                 /* Fetch variable byte size mask from the array. */
 403                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 404                                            field->offset, field->size);
 405                 if (!mask) {
 406                         ++field;
 407                         continue;
 408                 }
 409                 /* Deduce actual data width in bits from mask value. */
 410                 off_b = rte_bsf32(mask);
 411                 size_b = sizeof(uint32_t) * CHAR_BIT -
 412                          off_b - __builtin_clz(mask);
 413                 MLX5_ASSERT(size_b);
 414                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 415                 actions[i] = (struct mlx5_modification_cmd) {
 416                         .action_type = type,
 417                         .field = field->id,
 418                         .offset = off_b,
 419                         .length = size_b,
 420                 };
 421                 /* Convert entire record to expected big-endian format. */
 422                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 423                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 424                         MLX5_ASSERT(dcopy);
 425                         actions[i].dst_field = dcopy->id;
 426                         actions[i].dst_offset =
 427                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 428                         /* Convert entire record to big-endian format. */
 429                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 430                 } else {
 431                         MLX5_ASSERT(item->spec);
 432                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 433                                                    field->offset, field->size);
 434                         /* Shift out the trailing masked bits from data. */
 435                         data = (data & mask) >> off_b;
 436                         actions[i].data1 = rte_cpu_to_be_32(data);
 437                 }
 438                 ++i;
 439                 ++field;
 440         } while (field->size);
 441         if (resource->actions_num == i)
 442                 return rte_flow_error_set(error, EINVAL,
 443                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 444                                           "invalid modification flow item");
 445         resource->actions_num = i;
 446         return 0;
 447 }
 448
 449 /**
 450  * Convert modify-header set IPv4 address action to DV specification.
 451  *
 452  * @param[in,out] resource
 453  *   Pointer to the modify-header resource.
 454  * @param[in] action
 455  *   Pointer to action specification.
 456  * @param[out] error
 457  *   Pointer to the error structure.
 458  *
 459  * @return
 460  *   0 on success, a negative errno value otherwise and rte_errno is set.
 461  */
 462 static int
 463 flow_dv_convert_action_modify_ipv4
 464                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 465                          const struct rte_flow_action *action,
 466                          struct rte_flow_error *error)
 467 {
 468         const struct rte_flow_action_set_ipv4 *conf =
 469                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 470         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 471         struct rte_flow_item_ipv4 ipv4;
 472         struct rte_flow_item_ipv4 ipv4_mask;
 473
 474         memset(&ipv4, 0, sizeof(ipv4));
 475         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 476         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 477                 ipv4.hdr.src_addr = conf->ipv4_addr;
 478                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 479         } else {
 480                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 481                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 482         }
 483         item.spec = &ipv4;
 484         item.mask = &ipv4_mask;
 485         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 486                                              MLX5_MODIFICATION_TYPE_SET, error);
 487 }
 488
 489 /**
 490  * Convert modify-header set IPv6 address action to DV specification.
 491  *
 492  * @param[in,out] resource
 493  *   Pointer to the modify-header resource.
 494  * @param[in] action
 495  *   Pointer to action specification.
 496  * @param[out] error
 497  *   Pointer to the error structure.
 498  *
 499  * @return
 500  *   0 on success, a negative errno value otherwise and rte_errno is set.
 501  */
 502 static int
 503 flow_dv_convert_action_modify_ipv6
 504                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 505                          const struct rte_flow_action *action,
 506                          struct rte_flow_error *error)
 507 {
 508         const struct rte_flow_action_set_ipv6 *conf =
 509                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 510         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 511         struct rte_flow_item_ipv6 ipv6;
 512         struct rte_flow_item_ipv6 ipv6_mask;
 513
 514         memset(&ipv6, 0, sizeof(ipv6));
 515         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 516         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 517                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 518                        sizeof(ipv6.hdr.src_addr));
 519                 memcpy(&ipv6_mask.hdr.src_addr,
 520                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 521                        sizeof(ipv6.hdr.src_addr));
 522         } else {
 523                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.dst_addr));
 525                 memcpy(&ipv6_mask.hdr.dst_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 527                        sizeof(ipv6.hdr.dst_addr));
 528         }
 529         item.spec = &ipv6;
 530         item.mask = &ipv6_mask;
 531         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 532                                              MLX5_MODIFICATION_TYPE_SET, error);
 533 }
 534
 535 /**
 536  * Convert modify-header set MAC address action to DV specification.
 537  *
 538  * @param[in,out] resource
 539  *   Pointer to the modify-header resource.
 540  * @param[in] action
 541  *   Pointer to action specification.
 542  * @param[out] error
 543  *   Pointer to the error structure.
 544  *
 545  * @return
 546  *   0 on success, a negative errno value otherwise and rte_errno is set.
 547  */
 548 static int
 549 flow_dv_convert_action_modify_mac
 550                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 551                          const struct rte_flow_action *action,
 552                          struct rte_flow_error *error)
 553 {
 554         const struct rte_flow_action_set_mac *conf =
 555                 (const struct rte_flow_action_set_mac *)(action->conf);
 556         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 557         struct rte_flow_item_eth eth;
 558         struct rte_flow_item_eth eth_mask;
 559
 560         memset(&eth, 0, sizeof(eth));
 561         memset(&eth_mask, 0, sizeof(eth_mask));
 562         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 563                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 564                        sizeof(eth.src.addr_bytes));
 565                 memcpy(&eth_mask.src.addr_bytes,
 566                        &rte_flow_item_eth_mask.src.addr_bytes,
 567                        sizeof(eth_mask.src.addr_bytes));
 568         } else {
 569                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.dst.addr_bytes));
 571                 memcpy(&eth_mask.dst.addr_bytes,
 572                        &rte_flow_item_eth_mask.dst.addr_bytes,
 573                        sizeof(eth_mask.dst.addr_bytes));
 574         }
 575         item.spec = &eth;
 576         item.mask = &eth_mask;
 577         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 578                                              MLX5_MODIFICATION_TYPE_SET, error);
 579 }
 580
 581 /**
 582  * Convert modify-header set VLAN VID action to DV specification.
 583  *
 584  * @param[in,out] resource
 585  *   Pointer to the modify-header resource.
 586  * @param[in] action
 587  *   Pointer to action specification.
 588  * @param[out] error
 589  *   Pointer to the error structure.
 590  *
 591  * @return
 592  *   0 on success, a negative errno value otherwise and rte_errno is set.
 593  */
 594 static int
 595 flow_dv_convert_action_modify_vlan_vid
 596                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 597                          const struct rte_flow_action *action,
 598                          struct rte_flow_error *error)
 599 {
 600         const struct rte_flow_action_of_set_vlan_vid *conf =
 601                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 602         int i = resource->actions_num;
 603         struct mlx5_modification_cmd *actions = resource->actions;
 604         struct field_modify_info *field = modify_vlan_out_first_vid;
 605
 606         if (i >= MLX5_MAX_MODIFY_NUM)
 607                 return rte_flow_error_set(error, EINVAL,
 608                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 609                          "too many items to modify");
 610         actions[i] = (struct mlx5_modification_cmd) {
 611                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 612                 .field = field->id,
 613                 .length = field->size,
 614                 .offset = field->offset,
 615         };
 616         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 617         actions[i].data1 = conf->vlan_vid;
 618         actions[i].data1 = actions[i].data1 << 16;
 619         resource->actions_num = ++i;
 620         return 0;
 621 }
 622
 623 /**
 624  * Convert modify-header set TP action to DV specification.
 625  *
 626  * @param[in,out] resource
 627  *   Pointer to the modify-header resource.
 628  * @param[in] action
 629  *   Pointer to action specification.
 630  * @param[in] items
 631  *   Pointer to rte_flow_item objects list.
 632  * @param[in] attr
 633  *   Pointer to flow attributes structure.
 634  * @param[in] dev_flow
 635  *   Pointer to the sub flow.
 636  * @param[in] tunnel_decap
 637  *   Whether action is after tunnel decapsulation.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_tp
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 650                          bool tunnel_decap, struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_tp *conf =
 653                 (const struct rte_flow_action_set_tp *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_udp udp;
 656         struct rte_flow_item_udp udp_mask;
 657         struct rte_flow_item_tcp tcp;
 658         struct rte_flow_item_tcp tcp_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 663         if (attr->udp) {
 664                 memset(&udp, 0, sizeof(udp));
 665                 memset(&udp_mask, 0, sizeof(udp_mask));
 666                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 667                         udp.hdr.src_port = conf->port;
 668                         udp_mask.hdr.src_port =
 669                                         rte_flow_item_udp_mask.hdr.src_port;
 670                 } else {
 671                         udp.hdr.dst_port = conf->port;
 672                         udp_mask.hdr.dst_port =
 673                                         rte_flow_item_udp_mask.hdr.dst_port;
 674                 }
 675                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 676                 item.spec = &udp;
 677                 item.mask = &udp_mask;
 678                 field = modify_udp;
 679         } else {
 680                 MLX5_ASSERT(attr->tcp);
 681                 memset(&tcp, 0, sizeof(tcp));
 682                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 683                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 684                         tcp.hdr.src_port = conf->port;
 685                         tcp_mask.hdr.src_port =
 686                                         rte_flow_item_tcp_mask.hdr.src_port;
 687                 } else {
 688                         tcp.hdr.dst_port = conf->port;
 689                         tcp_mask.hdr.dst_port =
 690                                         rte_flow_item_tcp_mask.hdr.dst_port;
 691                 }
 692                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 693                 item.spec = &tcp;
 694                 item.mask = &tcp_mask;
 695                 field = modify_tcp;
 696         }
 697         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 698                                              MLX5_MODIFICATION_TYPE_SET, error);
 699 }
 700
 701 /**
 702  * Convert modify-header set TTL action to DV specification.
 703  *
 704  * @param[in,out] resource
 705  *   Pointer to the modify-header resource.
 706  * @param[in] action
 707  *   Pointer to action specification.
 708  * @param[in] items
 709  *   Pointer to rte_flow_item objects list.
 710  * @param[in] attr
 711  *   Pointer to flow attributes structure.
 712  * @param[in] dev_flow
 713  *   Pointer to the sub flow.
 714  * @param[in] tunnel_decap
 715  *   Whether action is after tunnel decapsulation.
 716  * @param[out] error
 717  *   Pointer to the error structure.
 718  *
 719  * @return
 720  *   0 on success, a negative errno value otherwise and rte_errno is set.
 721  */
 722 static int
 723 flow_dv_convert_action_modify_ttl
 724                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 725                          const struct rte_flow_action *action,
 726                          const struct rte_flow_item *items,
 727                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 728                          bool tunnel_decap, struct rte_flow_error *error)
 729 {
 730         const struct rte_flow_action_set_ttl *conf =
 731                 (const struct rte_flow_action_set_ttl *)(action->conf);
 732         struct rte_flow_item item;
 733         struct rte_flow_item_ipv4 ipv4;
 734         struct rte_flow_item_ipv4 ipv4_mask;
 735         struct rte_flow_item_ipv6 ipv6;
 736         struct rte_flow_item_ipv6 ipv6_mask;
 737         struct field_modify_info *field;
 738
 739         if (!attr->valid)
 740                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 741         if (attr->ipv4) {
 742                 memset(&ipv4, 0, sizeof(ipv4));
 743                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 744                 ipv4.hdr.time_to_live = conf->ttl_value;
 745                 ipv4_mask.hdr.time_to_live = 0xFF;
 746                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 747                 item.spec = &ipv4;
 748                 item.mask = &ipv4_mask;
 749                 field = modify_ipv4;
 750         } else {
 751                 MLX5_ASSERT(attr->ipv6);
 752                 memset(&ipv6, 0, sizeof(ipv6));
 753                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 754                 ipv6.hdr.hop_limits = conf->ttl_value;
 755                 ipv6_mask.hdr.hop_limits = 0xFF;
 756                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 757                 item.spec = &ipv6;
 758                 item.mask = &ipv6_mask;
 759                 field = modify_ipv6;
 760         }
 761         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 762                                              MLX5_MODIFICATION_TYPE_SET, error);
 763 }
 764
 765 /**
 766  * Convert modify-header decrement TTL action to DV specification.
 767  *
 768  * @param[in,out] resource
 769  *   Pointer to the modify-header resource.
 770  * @param[in] action
 771  *   Pointer to action specification.
 772  * @param[in] items
 773  *   Pointer to rte_flow_item objects list.
 774  * @param[in] attr
 775  *   Pointer to flow attributes structure.
 776  * @param[in] dev_flow
 777  *   Pointer to the sub flow.
 778  * @param[in] tunnel_decap
 779  *   Whether action is after tunnel decapsulation.
 780  * @param[out] error
 781  *   Pointer to the error structure.
 782  *
 783  * @return
 784  *   0 on success, a negative errno value otherwise and rte_errno is set.
 785  */
 786 static int
 787 flow_dv_convert_action_modify_dec_ttl
 788                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 789                          const struct rte_flow_item *items,
 790                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 791                          bool tunnel_decap, struct rte_flow_error *error)
 792 {
 793         struct rte_flow_item item;
 794         struct rte_flow_item_ipv4 ipv4;
 795         struct rte_flow_item_ipv4 ipv4_mask;
 796         struct rte_flow_item_ipv6 ipv6;
 797         struct rte_flow_item_ipv6 ipv6_mask;
 798         struct field_modify_info *field;
 799
 800         if (!attr->valid)
 801                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 802         if (attr->ipv4) {
 803                 memset(&ipv4, 0, sizeof(ipv4));
 804                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 805                 ipv4.hdr.time_to_live = 0xFF;
 806                 ipv4_mask.hdr.time_to_live = 0xFF;
 807                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 808                 item.spec = &ipv4;
 809                 item.mask = &ipv4_mask;
 810                 field = modify_ipv4;
 811         } else {
 812                 MLX5_ASSERT(attr->ipv6);
 813                 memset(&ipv6, 0, sizeof(ipv6));
 814                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 815                 ipv6.hdr.hop_limits = 0xFF;
 816                 ipv6_mask.hdr.hop_limits = 0xFF;
 817                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 818                 item.spec = &ipv6;
 819                 item.mask = &ipv6_mask;
 820                 field = modify_ipv6;
 821         }
 822         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 823                                              MLX5_MODIFICATION_TYPE_ADD, error);
 824 }
 825
 826 /**
 827  * Convert modify-header increment/decrement TCP Sequence number
 828  * to DV specification.
 829  *
 830  * @param[in,out] resource
 831  *   Pointer to the modify-header resource.
 832  * @param[in] action
 833  *   Pointer to action specification.
 834  * @param[out] error
 835  *   Pointer to the error structure.
 836  *
 837  * @return
 838  *   0 on success, a negative errno value otherwise and rte_errno is set.
 839  */
 840 static int
 841 flow_dv_convert_action_modify_tcp_seq
 842                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 843                          const struct rte_flow_action *action,
 844                          struct rte_flow_error *error)
 845 {
 846         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 847         uint64_t value = rte_be_to_cpu_32(*conf);
 848         struct rte_flow_item item;
 849         struct rte_flow_item_tcp tcp;
 850         struct rte_flow_item_tcp tcp_mask;
 851
 852         memset(&tcp, 0, sizeof(tcp));
 853         memset(&tcp_mask, 0, sizeof(tcp_mask));
 854         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 855                 /*
 856                  * The HW has no decrement operation, only increment operation.
 857                  * To simulate decrement X from Y using increment operation
 858                  * we need to add UINT32_MAX X times to Y.
 859                  * Each adding of UINT32_MAX decrements Y by 1.
 860                  */
 861                 value *= UINT32_MAX;
 862         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 863         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 864         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 865         item.spec = &tcp;
 866         item.mask = &tcp_mask;
 867         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 868                                              MLX5_MODIFICATION_TYPE_ADD, error);
 869 }
 870
 871 /**
 872  * Convert modify-header increment/decrement TCP Acknowledgment number
 873  * to DV specification.
 874  *
 875  * @param[in,out] resource
 876  *   Pointer to the modify-header resource.
 877  * @param[in] action
 878  *   Pointer to action specification.
 879  * @param[out] error
 880  *   Pointer to the error structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 static int
 886 flow_dv_convert_action_modify_tcp_ack
 887                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 888                          const struct rte_flow_action *action,
 889                          struct rte_flow_error *error)
 890 {
 891         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 892         uint64_t value = rte_be_to_cpu_32(*conf);
 893         struct rte_flow_item item;
 894         struct rte_flow_item_tcp tcp;
 895         struct rte_flow_item_tcp tcp_mask;
 896
 897         memset(&tcp, 0, sizeof(tcp));
 898         memset(&tcp_mask, 0, sizeof(tcp_mask));
 899         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 900                 /*
 901                  * The HW has no decrement operation, only increment operation.
 902                  * To simulate decrement X from Y using increment operation
 903                  * we need to add UINT32_MAX X times to Y.
 904                  * Each adding of UINT32_MAX decrements Y by 1.
 905                  */
 906                 value *= UINT32_MAX;
 907         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 908         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 909         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 910         item.spec = &tcp;
 911         item.mask = &tcp_mask;
 912         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 913                                              MLX5_MODIFICATION_TYPE_ADD, error);
 914 }
 915
 916 static enum mlx5_modification_field reg_to_field[] = {
 917         [REG_NON] = MLX5_MODI_OUT_NONE,
 918         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 919         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 920         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 921         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 922         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 923         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 924         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 925         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 926         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 927         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 928 };
 929
 930 /**
 931  * Convert register set to DV specification.
 932  *
 933  * @param[in,out] resource
 934  *   Pointer to the modify-header resource.
 935  * @param[in] action
 936  *   Pointer to action specification.
 937  * @param[out] error
 938  *   Pointer to the error structure.
 939  *
 940  * @return
 941  *   0 on success, a negative errno value otherwise and rte_errno is set.
 942  */
 943 static int
 944 flow_dv_convert_action_set_reg
 945                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 946                          const struct rte_flow_action *action,
 947                          struct rte_flow_error *error)
 948 {
 949         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 950         struct mlx5_modification_cmd *actions = resource->actions;
 951         uint32_t i = resource->actions_num;
 952
 953         if (i >= MLX5_MAX_MODIFY_NUM)
 954                 return rte_flow_error_set(error, EINVAL,
 955                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 956                                           "too many items to modify");
 957         MLX5_ASSERT(conf->id != REG_NON);
 958         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 959         actions[i] = (struct mlx5_modification_cmd) {
 960                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 961                 .field = reg_to_field[conf->id],
 962         };
 963         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 964         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 965         ++i;
 966         resource->actions_num = i;
 967         return 0;
 968 }
 969
 970 /**
 971  * Convert SET_TAG action to DV specification.
 972  *
 973  * @param[in] dev
 974  *   Pointer to the rte_eth_dev structure.
 975  * @param[in,out] resource
 976  *   Pointer to the modify-header resource.
 977  * @param[in] conf
 978  *   Pointer to action specification.
 979  * @param[out] error
 980  *   Pointer to the error structure.
 981  *
 982  * @return
 983  *   0 on success, a negative errno value otherwise and rte_errno is set.
 984  */
 985 static int
 986 flow_dv_convert_action_set_tag
 987                         (struct rte_eth_dev *dev,
 988                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 989                          const struct rte_flow_action_set_tag *conf,
 990                          struct rte_flow_error *error)
 991 {
 992         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 993         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 994         struct rte_flow_item item = {
 995                 .spec = &data,
 996                 .mask = &mask,
 997         };
 998         struct field_modify_info reg_c_x[] = {
 999                 [1] = {0, 0, 0},
1000         };
1001         enum mlx5_modification_field reg_type;
1002         int ret;
1003
1004         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1005         if (ret < 0)
1006                 return ret;
1007         MLX5_ASSERT(ret != REG_NON);
1008         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009         reg_type = reg_to_field[ret];
1010         MLX5_ASSERT(reg_type > 0);
1011         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013                                              MLX5_MODIFICATION_TYPE_SET, error);
1014 }
1015
1016 /**
1017  * Convert internal COPY_REG action to DV specification.
1018  *
1019  * @param[in] dev
1020  *   Pointer to the rte_eth_dev structure.
1021  * @param[in,out] res
1022  *   Pointer to the modify-header resource.
1023  * @param[in] action
1024  *   Pointer to action specification.
1025  * @param[out] error
1026  *   Pointer to the error structure.
1027  *
1028  * @return
1029  *   0 on success, a negative errno value otherwise and rte_errno is set.
1030  */
1031 static int
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1034                                  const struct rte_flow_action *action,
1035                                  struct rte_flow_error *error)
1036 {
1037         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039         struct rte_flow_item item = {
1040                 .spec = NULL,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_src[] = {
1044                 {4, 0, reg_to_field[conf->src]},
1045                 {0, 0, 0},
1046         };
1047         struct field_modify_info reg_dst = {
1048                 .offset = 0,
1049                 .id = reg_to_field[conf->dst],
1050         };
1051         /* Adjust reg_c[0] usage according to reported mask. */
1052         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053                 struct mlx5_priv *priv = dev->data->dev_private;
1054                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1055
1056                 MLX5_ASSERT(reg_c0);
1057                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058                 if (conf->dst == REG_C_0) {
1059                         /* Copy to reg_c[0], within mask only. */
1060                         reg_dst.offset = rte_bsf32(reg_c0);
1061                         /*
1062                          * Mask is ignoring the enianness, because
1063                          * there is no conversion in datapath.
1064                          */
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066                         /* Copy from destination lower bits to reg_c[0]. */
1067                         mask = reg_c0 >> reg_dst.offset;
1068 #else
1069                         /* Copy from destination upper bits to reg_c[0]. */
1070                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071                                           rte_fls_u32(reg_c0));
1072 #endif
1073                 } else {
1074                         mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076                         /* Copy from reg_c[0] to destination lower bits. */
1077                         reg_dst.offset = 0;
1078 #else
1079                         /* Copy from reg_c[0] to destination upper bits. */
1080                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081                                          (rte_fls_u32(reg_c0) -
1082                                           rte_bsf32(reg_c0));
1083 #endif
1084                 }
1085         }
1086         return flow_dv_convert_modify_action(&item,
1087                                              reg_src, &reg_dst, res,
1088                                              MLX5_MODIFICATION_TYPE_COPY,
1089                                              error);
1090 }
1091
1092 /**
1093  * Convert MARK action to DV specification. This routine is used
1094  * in extensive metadata only and requires metadata register to be
1095  * handled. In legacy mode hardware tag resource is engaged.
1096  *
1097  * @param[in] dev
1098  *   Pointer to the rte_eth_dev structure.
1099  * @param[in] conf
1100  *   Pointer to MARK action specification.
1101  * @param[in,out] resource
1102  *   Pointer to the modify-header resource.
1103  * @param[out] error
1104  *   Pointer to the error structure.
1105  *
1106  * @return
1107  *   0 on success, a negative errno value otherwise and rte_errno is set.
1108  */
1109 static int
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111                             const struct rte_flow_action_mark *conf,
1112                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1113                             struct rte_flow_error *error)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117                                            priv->sh->dv_mark_mask);
1118         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119         struct rte_flow_item item = {
1120                 .spec = &data,
1121                 .mask = &mask,
1122         };
1123         struct field_modify_info reg_c_x[] = {
1124                 [1] = {0, 0, 0},
1125         };
1126         int reg;
1127
1128         if (!mask)
1129                 return rte_flow_error_set(error, EINVAL,
1130                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131                                           NULL, "zero mark action mask");
1132         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1133         if (reg < 0)
1134                 return reg;
1135         MLX5_ASSERT(reg > 0);
1136         if (reg == REG_C_0) {
1137                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1139
1140                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142                 mask = rte_cpu_to_be_32(mask << shl_c0);
1143         }
1144         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146                                              MLX5_MODIFICATION_TYPE_SET, error);
1147 }
1148
1149 /**
1150  * Get metadata register index for specified steering domain.
1151  *
1152  * @param[in] dev
1153  *   Pointer to the rte_eth_dev structure.
1154  * @param[in] attr
1155  *   Attributes of flow to determine steering domain.
1156  * @param[out] error
1157  *   Pointer to the error structure.
1158  *
1159  * @return
1160  *   positive index on success, a negative errno value otherwise
1161  *   and rte_errno is set.
1162  */
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165                          const struct rte_flow_attr *attr,
1166                          struct rte_flow_error *error)
1167 {
1168         int reg =
1169                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1170                                           MLX5_METADATA_FDB :
1171                                             attr->egress ?
1172                                             MLX5_METADATA_TX :
1173                                             MLX5_METADATA_RX, 0, error);
1174         if (reg < 0)
1175                 return rte_flow_error_set(error,
1176                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177                                           NULL, "unavailable "
1178                                           "metadata register");
1179         return reg;
1180 }
1181
1182 /**
1183  * Convert SET_META action to DV specification.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in,out] resource
1188  *   Pointer to the modify-header resource.
1189  * @param[in] attr
1190  *   Attributes of flow that includes this item.
1191  * @param[in] conf
1192  *   Pointer to action specification.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   0 on success, a negative errno value otherwise and rte_errno is set.
1198  */
1199 static int
1200 flow_dv_convert_action_set_meta
1201                         (struct rte_eth_dev *dev,
1202                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1203                          const struct rte_flow_attr *attr,
1204                          const struct rte_flow_action_set_meta *conf,
1205                          struct rte_flow_error *error)
1206 {
1207         uint32_t data = conf->data;
1208         uint32_t mask = conf->mask;
1209         struct rte_flow_item item = {
1210                 .spec = &data,
1211                 .mask = &mask,
1212         };
1213         struct field_modify_info reg_c_x[] = {
1214                 [1] = {0, 0, 0},
1215         };
1216         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1217
1218         if (reg < 0)
1219                 return reg;
1220         MLX5_ASSERT(reg != REG_NON);
1221         /*
1222          * In datapath code there is no endianness
1223          * coversions for perfromance reasons, all
1224          * pattern conversions are done in rte_flow.
1225          */
1226         if (reg == REG_C_0) {
1227                 struct mlx5_priv *priv = dev->data->dev_private;
1228                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1229                 uint32_t shl_c0;
1230
1231                 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233                 shl_c0 = rte_bsf32(msk_c0);
1234 #else
1235                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1236 #endif
1237                 mask <<= shl_c0;
1238                 data <<= shl_c0;
1239                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1240         }
1241         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242         /* The routine expects parameters in memory as big-endian ones. */
1243         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244                                              MLX5_MODIFICATION_TYPE_SET, error);
1245 }
1246
1247 /**
1248  * Convert modify-header set IPv4 DSCP action to DV specification.
1249  *
1250  * @param[in,out] resource
1251  *   Pointer to the modify-header resource.
1252  * @param[in] action
1253  *   Pointer to action specification.
1254  * @param[out] error
1255  *   Pointer to the error structure.
1256  *
1257  * @return
1258  *   0 on success, a negative errno value otherwise and rte_errno is set.
1259  */
1260 static int
1261 flow_dv_convert_action_modify_ipv4_dscp
1262                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263                          const struct rte_flow_action *action,
1264                          struct rte_flow_error *error)
1265 {
1266         const struct rte_flow_action_set_dscp *conf =
1267                 (const struct rte_flow_action_set_dscp *)(action->conf);
1268         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269         struct rte_flow_item_ipv4 ipv4;
1270         struct rte_flow_item_ipv4 ipv4_mask;
1271
1272         memset(&ipv4, 0, sizeof(ipv4));
1273         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274         ipv4.hdr.type_of_service = conf->dscp;
1275         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1276         item.spec = &ipv4;
1277         item.mask = &ipv4_mask;
1278         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv6 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv6_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304         struct rte_flow_item_ipv6 ipv6;
1305         struct rte_flow_item_ipv6 ipv6_mask;
1306
1307         memset(&ipv6, 0, sizeof(ipv6));
1308         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1309         /*
1310          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311          * rdma-core only accept the DSCP bits byte aligned start from
1312          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313          * bits in IPv6 case as rdma-core requires byte aligned value.
1314          */
1315         ipv6.hdr.vtc_flow = conf->dscp;
1316         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1317         item.spec = &ipv6;
1318         item.mask = &ipv6_mask;
1319         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320                                              MLX5_MODIFICATION_TYPE_SET, error);
1321 }
1322
1323 /**
1324  * Validate MARK item.
1325  *
1326  * @param[in] dev
1327  *   Pointer to the rte_eth_dev structure.
1328  * @param[in] item
1329  *   Item specification.
1330  * @param[in] attr
1331  *   Attributes of flow that includes this item.
1332  * @param[out] error
1333  *   Pointer to error structure.
1334  *
1335  * @return
1336  *   0 on success, a negative errno value otherwise and rte_errno is set.
1337  */
1338 static int
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340                            const struct rte_flow_item *item,
1341                            const struct rte_flow_attr *attr __rte_unused,
1342                            struct rte_flow_error *error)
1343 {
1344         struct mlx5_priv *priv = dev->data->dev_private;
1345         struct mlx5_dev_config *config = &priv->config;
1346         const struct rte_flow_item_mark *spec = item->spec;
1347         const struct rte_flow_item_mark *mask = item->mask;
1348         const struct rte_flow_item_mark nic_mask = {
1349                 .id = priv->sh->dv_mark_mask,
1350         };
1351         int ret;
1352
1353         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354                 return rte_flow_error_set(error, ENOTSUP,
1355                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1356                                           "extended metadata feature"
1357                                           " isn't enabled");
1358         if (!mlx5_flow_ext_mreg_supported(dev))
1359                 return rte_flow_error_set(error, ENOTSUP,
1360                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1361                                           "extended metadata register"
1362                                           " isn't supported");
1363         if (!nic_mask.id)
1364                 return rte_flow_error_set(error, ENOTSUP,
1365                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1366                                           "extended metadata register"
1367                                           " isn't available");
1368         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1369         if (ret < 0)
1370                 return ret;
1371         if (!spec)
1372                 return rte_flow_error_set(error, EINVAL,
1373                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1374                                           item->spec,
1375                                           "data cannot be empty");
1376         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377                 return rte_flow_error_set(error, EINVAL,
1378                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1379                                           &spec->id,
1380                                           "mark id exceeds the limit");
1381         if (!mask)
1382                 mask = &nic_mask;
1383         if (!mask->id)
1384                 return rte_flow_error_set(error, EINVAL,
1385                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386                                         "mask cannot be zero");
1387
1388         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389                                         (const uint8_t *)&nic_mask,
1390                                         sizeof(struct rte_flow_item_mark),
1391                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1392         if (ret < 0)
1393                 return ret;
1394         return 0;
1395 }
1396
1397 /**
1398  * Validate META item.
1399  *
1400  * @param[in] dev
1401  *   Pointer to the rte_eth_dev structure.
1402  * @param[in] item
1403  *   Item specification.
1404  * @param[in] attr
1405  *   Attributes of flow that includes this item.
1406  * @param[out] error
1407  *   Pointer to error structure.
1408  *
1409  * @return
1410  *   0 on success, a negative errno value otherwise and rte_errno is set.
1411  */
1412 static int
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414                            const struct rte_flow_item *item,
1415                            const struct rte_flow_attr *attr,
1416                            struct rte_flow_error *error)
1417 {
1418         struct mlx5_priv *priv = dev->data->dev_private;
1419         struct mlx5_dev_config *config = &priv->config;
1420         const struct rte_flow_item_meta *spec = item->spec;
1421         const struct rte_flow_item_meta *mask = item->mask;
1422         struct rte_flow_item_meta nic_mask = {
1423                 .data = UINT32_MAX
1424         };
1425         int reg;
1426         int ret;
1427
1428         if (!spec)
1429                 return rte_flow_error_set(error, EINVAL,
1430                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1431                                           item->spec,
1432                                           "data cannot be empty");
1433         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434                 if (!mlx5_flow_ext_mreg_supported(dev))
1435                         return rte_flow_error_set(error, ENOTSUP,
1436                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1437                                           "extended metadata register"
1438                                           " isn't supported");
1439                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1440                 if (reg < 0)
1441                         return reg;
1442                 if (reg == REG_NON)
1443                         return rte_flow_error_set(error, ENOTSUP,
1444                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1445                                         "unavalable extended metadata register");
1446                 if (reg == REG_B)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                           "match on reg_b "
1450                                           "isn't supported");
1451                 if (reg != REG_A)
1452                         nic_mask.data = priv->sh->dv_meta_mask;
1453         } else if (attr->transfer) {
1454                 return rte_flow_error_set(error, ENOTSUP,
1455                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1456                                         "extended metadata feature "
1457                                         "should be enabled when "
1458                                         "meta item is requested "
1459                                         "with e-switch mode ");
1460         }
1461         if (!mask)
1462                 mask = &rte_flow_item_meta_mask;
1463         if (!mask->data)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466                                         "mask cannot be zero");
1467
1468         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469                                         (const uint8_t *)&nic_mask,
1470                                         sizeof(struct rte_flow_item_meta),
1471                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1472         return ret;
1473 }
1474
1475 /**
1476  * Validate TAG item.
1477  *
1478  * @param[in] dev
1479  *   Pointer to the rte_eth_dev structure.
1480  * @param[in] item
1481  *   Item specification.
1482  * @param[in] attr
1483  *   Attributes of flow that includes this item.
1484  * @param[out] error
1485  *   Pointer to error structure.
1486  *
1487  * @return
1488  *   0 on success, a negative errno value otherwise and rte_errno is set.
1489  */
1490 static int
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492                           const struct rte_flow_item *item,
1493                           const struct rte_flow_attr *attr __rte_unused,
1494                           struct rte_flow_error *error)
1495 {
1496         const struct rte_flow_item_tag *spec = item->spec;
1497         const struct rte_flow_item_tag *mask = item->mask;
1498         const struct rte_flow_item_tag nic_mask = {
1499                 .data = RTE_BE32(UINT32_MAX),
1500                 .index = 0xff,
1501         };
1502         int ret;
1503
1504         if (!mlx5_flow_ext_mreg_supported(dev))
1505                 return rte_flow_error_set(error, ENOTSUP,
1506                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1507                                           "extensive metadata register"
1508                                           " isn't supported");
1509         if (!spec)
1510                 return rte_flow_error_set(error, EINVAL,
1511                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1512                                           item->spec,
1513                                           "data cannot be empty");
1514         if (!mask)
1515                 mask = &rte_flow_item_tag_mask;
1516         if (!mask->data)
1517                 return rte_flow_error_set(error, EINVAL,
1518                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519                                         "mask cannot be zero");
1520
1521         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522                                         (const uint8_t *)&nic_mask,
1523                                         sizeof(struct rte_flow_item_tag),
1524                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1525         if (ret < 0)
1526                 return ret;
1527         if (mask->index != 0xff)
1528                 return rte_flow_error_set(error, EINVAL,
1529                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530                                           "partial mask for tag index"
1531                                           " is not supported");
1532         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1533         if (ret < 0)
1534                 return ret;
1535         MLX5_ASSERT(ret != REG_NON);
1536         return 0;
1537 }
1538
1539 /**
1540  * Validate vport item.
1541  *
1542  * @param[in] dev
1543  *   Pointer to the rte_eth_dev structure.
1544  * @param[in] item
1545  *   Item specification.
1546  * @param[in] attr
1547  *   Attributes of flow that includes this item.
1548  * @param[in] item_flags
1549  *   Bit-fields that holds the items detected until now.
1550  * @param[out] error
1551  *   Pointer to error structure.
1552  *
1553  * @return
1554  *   0 on success, a negative errno value otherwise and rte_errno is set.
1555  */
1556 static int
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558                               const struct rte_flow_item *item,
1559                               const struct rte_flow_attr *attr,
1560                               uint64_t item_flags,
1561                               struct rte_flow_error *error)
1562 {
1563         const struct rte_flow_item_port_id *spec = item->spec;
1564         const struct rte_flow_item_port_id *mask = item->mask;
1565         const struct rte_flow_item_port_id switch_mask = {
1566                         .id = 0xffffffff,
1567         };
1568         struct mlx5_priv *esw_priv;
1569         struct mlx5_priv *dev_priv;
1570         int ret;
1571
1572         if (!attr->transfer)
1573                 return rte_flow_error_set(error, EINVAL,
1574                                           RTE_FLOW_ERROR_TYPE_ITEM,
1575                                           NULL,
1576                                           "match on port id is valid only"
1577                                           " when transfer flag is enabled");
1578         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579                 return rte_flow_error_set(error, ENOTSUP,
1580                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1581                                           "multiple source ports are not"
1582                                           " supported");
1583         if (!mask)
1584                 mask = &switch_mask;
1585         if (mask->id != 0xffffffff)
1586                 return rte_flow_error_set(error, ENOTSUP,
1587                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1588                                            mask,
1589                                            "no support for partial mask on"
1590                                            " \"id\" field");
1591         ret = mlx5_flow_item_acceptable
1592                                 (item, (const uint8_t *)mask,
1593                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1594                                  sizeof(struct rte_flow_item_port_id),
1595                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1596         if (ret)
1597                 return ret;
1598         if (!spec)
1599                 return 0;
1600         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1601         if (!esw_priv)
1602                 return rte_flow_error_set(error, rte_errno,
1603                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604                                           "failed to obtain E-Switch info for"
1605                                           " port");
1606         dev_priv = mlx5_dev_to_eswitch_info(dev);
1607         if (!dev_priv)
1608                 return rte_flow_error_set(error, rte_errno,
1609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1610                                           NULL,
1611                                           "failed to obtain E-Switch info");
1612         if (esw_priv->domain_id != dev_priv->domain_id)
1613                 return rte_flow_error_set(error, EINVAL,
1614                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615                                           "cannot match on a port from a"
1616                                           " different E-Switch");
1617         return 0;
1618 }
1619
1620 /**
1621  * Validate VLAN item.
1622  *
1623  * @param[in] item
1624  *   Item specification.
1625  * @param[in] item_flags
1626  *   Bit-fields that holds the items detected until now.
1627  * @param[in] dev
1628  *   Ethernet device flow is being created on.
1629  * @param[out] error
1630  *   Pointer to error structure.
1631  *
1632  * @return
1633  *   0 on success, a negative errno value otherwise and rte_errno is set.
1634  */
1635 static int
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637                            uint64_t item_flags,
1638                            struct rte_eth_dev *dev,
1639                            struct rte_flow_error *error)
1640 {
1641         const struct rte_flow_item_vlan *mask = item->mask;
1642         const struct rte_flow_item_vlan nic_mask = {
1643                 .tci = RTE_BE16(UINT16_MAX),
1644                 .inner_type = RTE_BE16(UINT16_MAX),
1645                 .has_more_vlan = 1,
1646         };
1647         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1648         int ret;
1649         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650                                         MLX5_FLOW_LAYER_INNER_L4) :
1651                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1652                                         MLX5_FLOW_LAYER_OUTER_L4);
1653         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1655
1656         if (item_flags & vlanm)
1657                 return rte_flow_error_set(error, EINVAL,
1658                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1659                                           "multiple VLAN layers not supported");
1660         else if ((item_flags & l34m) != 0)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "VLAN cannot follow L3/L4 layer");
1664         if (!mask)
1665                 mask = &rte_flow_item_vlan_mask;
1666         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667                                         (const uint8_t *)&nic_mask,
1668                                         sizeof(struct rte_flow_item_vlan),
1669                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1670         if (ret)
1671                 return ret;
1672         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673                 struct mlx5_priv *priv = dev->data->dev_private;
1674
1675                 if (priv->vmwa_context) {
1676                         /*
1677                          * Non-NULL context means we have a virtual machine
1678                          * and SR-IOV enabled, we have to create VLAN interface
1679                          * to make hypervisor to setup E-Switch vport
1680                          * context correctly. We avoid creating the multiple
1681                          * VLAN interfaces, so we cannot support VLAN tag mask.
1682                          */
1683                         return rte_flow_error_set(error, EINVAL,
1684                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1685                                                   item,
1686                                                   "VLAN tag mask is not"
1687                                                   " supported in virtual"
1688                                                   " environment");
1689                 }
1690         }
1691         return 0;
1692 }
1693
1694 /*
1695  * GTP flags are contained in 1 byte of the format:
1696  * -------------------------------------------
1697  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1698  * |-----------------------------------------|
1699  * | value | Version | PT | Res | E | S | PN |
1700  * -------------------------------------------
1701  *
1702  * Matching is supported only for GTP flags E, S, PN.
1703  */
1704 #define MLX5_GTP_FLAGS_MASK     0x07
1705
1706 /**
1707  * Validate GTP item.
1708  *
1709  * @param[in] dev
1710  *   Pointer to the rte_eth_dev structure.
1711  * @param[in] item
1712  *   Item specification.
1713  * @param[in] item_flags
1714  *   Bit-fields that holds the items detected until now.
1715  * @param[out] error
1716  *   Pointer to error structure.
1717  *
1718  * @return
1719  *   0 on success, a negative errno value otherwise and rte_errno is set.
1720  */
1721 static int
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723                           const struct rte_flow_item *item,
1724                           uint64_t item_flags,
1725                           struct rte_flow_error *error)
1726 {
1727         struct mlx5_priv *priv = dev->data->dev_private;
1728         const struct rte_flow_item_gtp *spec = item->spec;
1729         const struct rte_flow_item_gtp *mask = item->mask;
1730         const struct rte_flow_item_gtp nic_mask = {
1731                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1732                 .msg_type = 0xff,
1733                 .teid = RTE_BE32(0xffffffff),
1734         };
1735
1736         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1739                                           "GTP support is not enabled");
1740         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "multiple tunnel layers not"
1744                                           " supported");
1745         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1748                                           "no outer UDP layer found");
1749         if (!mask)
1750                 mask = &rte_flow_item_gtp_mask;
1751         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752                 return rte_flow_error_set(error, ENOTSUP,
1753                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1754                                           "Match is supported for GTP"
1755                                           " flags only");
1756         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757                                          (const uint8_t *)&nic_mask,
1758                                          sizeof(struct rte_flow_item_gtp),
1759                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1760 }
1761
1762 /**
1763  * Validate GTP PSC item.
1764  *
1765  * @param[in] item
1766  *   Item specification.
1767  * @param[in] last_item
1768  *   Previous validated item in the pattern items.
1769  * @param[in] gtp_item
1770  *   Previous GTP item specification.
1771  * @param[in] attr
1772  *   Pointer to flow attributes.
1773  * @param[out] error
1774  *   Pointer to error structure.
1775  *
1776  * @return
1777  *   0 on success, a negative errno value otherwise and rte_errno is set.
1778  */
1779 static int
1780 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1781                               uint64_t last_item,
1782                               const struct rte_flow_item *gtp_item,
1783                               const struct rte_flow_attr *attr,
1784                               struct rte_flow_error *error)
1785 {
1786         const struct rte_flow_item_gtp *gtp_spec;
1787         const struct rte_flow_item_gtp *gtp_mask;
1788         const struct rte_flow_item_gtp_psc *spec;
1789         const struct rte_flow_item_gtp_psc *mask;
1790         const struct rte_flow_item_gtp_psc nic_mask = {
1791                 .pdu_type = 0xFF,
1792                 .qfi = 0xFF,
1793         };
1794
1795         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1796                 return rte_flow_error_set
1797                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1798                          "GTP PSC item must be preceded with GTP item");
1799         gtp_spec = gtp_item->spec;
1800         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1801         /* GTP spec and E flag is requested to match zero. */
1802         if (gtp_spec &&
1803                 (gtp_mask->v_pt_rsv_flags &
1804                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1805                 return rte_flow_error_set
1806                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1807                          "GTP E flag must be 1 to match GTP PSC");
1808         /* Check the flow is not created in group zero. */
1809         if (!attr->transfer && !attr->group)
1810                 return rte_flow_error_set
1811                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1812                          "GTP PSC is not supported for group 0");
1813         /* GTP spec is here and E flag is requested to match zero. */
1814         if (!item->spec)
1815                 return 0;
1816         spec = item->spec;
1817         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1818         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1819                 return rte_flow_error_set
1820                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1821                          "PDU type should be smaller than 16");
1822         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1823                                          (const uint8_t *)&nic_mask,
1824                                          sizeof(struct rte_flow_item_gtp_psc),
1825                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1826 }
1827
1828 /**
1829  * Validate IPV4 item.
1830  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1831  * add specific validation of fragment_offset field,
1832  *
1833  * @param[in] item
1834  *   Item specification.
1835  * @param[in] item_flags
1836  *   Bit-fields that holds the items detected until now.
1837  * @param[out] error
1838  *   Pointer to error structure.
1839  *
1840  * @return
1841  *   0 on success, a negative errno value otherwise and rte_errno is set.
1842  */
1843 static int
1844 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1845                            uint64_t item_flags,
1846                            uint64_t last_item,
1847                            uint16_t ether_type,
1848                            struct rte_flow_error *error)
1849 {
1850         int ret;
1851         const struct rte_flow_item_ipv4 *spec = item->spec;
1852         const struct rte_flow_item_ipv4 *last = item->last;
1853         const struct rte_flow_item_ipv4 *mask = item->mask;
1854         rte_be16_t fragment_offset_spec = 0;
1855         rte_be16_t fragment_offset_last = 0;
1856         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1857                 .hdr = {
1858                         .src_addr = RTE_BE32(0xffffffff),
1859                         .dst_addr = RTE_BE32(0xffffffff),
1860                         .type_of_service = 0xff,
1861                         .fragment_offset = RTE_BE16(0xffff),
1862                         .next_proto_id = 0xff,
1863                         .time_to_live = 0xff,
1864                 },
1865         };
1866
1867         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1868                                            ether_type, &nic_ipv4_mask,
1869                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1870         if (ret < 0)
1871                 return ret;
1872         if (spec && mask)
1873                 fragment_offset_spec = spec->hdr.fragment_offset &
1874                                        mask->hdr.fragment_offset;
1875         if (!fragment_offset_spec)
1876                 return 0;
1877         /*
1878          * spec and mask are valid, enforce using full mask to make sure the
1879          * complete value is used correctly.
1880          */
1881         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1882                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1883                 return rte_flow_error_set(error, EINVAL,
1884                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1885                                           item, "must use full mask for"
1886                                           " fragment_offset");
1887         /*
1888          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1889          * indicating this is 1st fragment of fragmented packet.
1890          * This is not yet supported in MLX5, return appropriate error message.
1891          */
1892         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1895                                           "match on first fragment not "
1896                                           "supported");
1897         if (fragment_offset_spec && !last)
1898                 return rte_flow_error_set(error, ENOTSUP,
1899                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1900                                           "specified value not supported");
1901         /* spec and last are valid, validate the specified range. */
1902         fragment_offset_last = last->hdr.fragment_offset &
1903                                mask->hdr.fragment_offset;
1904         /*
1905          * Match on fragment_offset spec 0x2001 and last 0x3fff
1906          * means MF is 1 and frag-offset is > 0.
1907          * This packet is fragment 2nd and onward, excluding last.
1908          * This is not yet supported in MLX5, return appropriate
1909          * error message.
1910          */
1911         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1912             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1913                 return rte_flow_error_set(error, ENOTSUP,
1914                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1915                                           last, "match on following "
1916                                           "fragments not supported");
1917         /*
1918          * Match on fragment_offset spec 0x0001 and last 0x1fff
1919          * means MF is 0 and frag-offset is > 0.
1920          * This packet is last fragment of fragmented packet.
1921          * This is not yet supported in MLX5, return appropriate
1922          * error message.
1923          */
1924         if (fragment_offset_spec == RTE_BE16(1) &&
1925             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1926                 return rte_flow_error_set(error, ENOTSUP,
1927                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1928                                           last, "match on last "
1929                                           "fragment not supported");
1930         /*
1931          * Match on fragment_offset spec 0x0001 and last 0x3fff
1932          * means MF and/or frag-offset is not 0.
1933          * This is a fragmented packet.
1934          * Other range values are invalid and rejected.
1935          */
1936         if (!(fragment_offset_spec == RTE_BE16(1) &&
1937               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1938                 return rte_flow_error_set(error, ENOTSUP,
1939                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1940                                           "specified range not supported");
1941         return 0;
1942 }
1943
1944 /**
1945  * Validate IPV6 fragment extension item.
1946  *
1947  * @param[in] item
1948  *   Item specification.
1949  * @param[in] item_flags
1950  *   Bit-fields that holds the items detected until now.
1951  * @param[out] error
1952  *   Pointer to error structure.
1953  *
1954  * @return
1955  *   0 on success, a negative errno value otherwise and rte_errno is set.
1956  */
1957 static int
1958 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1959                                     uint64_t item_flags,
1960                                     struct rte_flow_error *error)
1961 {
1962         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1963         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1964         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1965         rte_be16_t frag_data_spec = 0;
1966         rte_be16_t frag_data_last = 0;
1967         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1968         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1969                                       MLX5_FLOW_LAYER_OUTER_L4;
1970         int ret = 0;
1971         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1972                 .hdr = {
1973                         .next_header = 0xff,
1974                         .frag_data = RTE_BE16(0xffff),
1975                 },
1976         };
1977
1978         if (item_flags & l4m)
1979                 return rte_flow_error_set(error, EINVAL,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "ipv6 fragment extension item cannot "
1982                                           "follow L4 item.");
1983         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1984             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1985                 return rte_flow_error_set(error, EINVAL,
1986                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1987                                           "ipv6 fragment extension item must "
1988                                           "follow ipv6 item");
1989         if (spec && mask)
1990                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1991         if (!frag_data_spec)
1992                 return 0;
1993         /*
1994          * spec and mask are valid, enforce using full mask to make sure the
1995          * complete value is used correctly.
1996          */
1997         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1998                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1999                 return rte_flow_error_set(error, EINVAL,
2000                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2001                                           item, "must use full mask for"
2002                                           " frag_data");
2003         /*
2004          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2005          * This is 1st fragment of fragmented packet.
2006          */
2007         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2008                 return rte_flow_error_set(error, ENOTSUP,
2009                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2010                                           "match on first fragment not "
2011                                           "supported");
2012         if (frag_data_spec && !last)
2013                 return rte_flow_error_set(error, EINVAL,
2014                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2015                                           "specified value not supported");
2016         ret = mlx5_flow_item_acceptable
2017                                 (item, (const uint8_t *)mask,
2018                                  (const uint8_t *)&nic_mask,
2019                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2020                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2021         if (ret)
2022                 return ret;
2023         /* spec and last are valid, validate the specified range. */
2024         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2025         /*
2026          * Match on frag_data spec 0x0009 and last 0xfff9
2027          * means M is 1 and frag-offset is > 0.
2028          * This packet is fragment 2nd and onward, excluding last.
2029          * This is not yet supported in MLX5, return appropriate
2030          * error message.
2031          */
2032         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2033                                        RTE_IPV6_EHDR_MF_MASK) &&
2034             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2035                 return rte_flow_error_set(error, ENOTSUP,
2036                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2037                                           last, "match on following "
2038                                           "fragments not supported");
2039         /*
2040          * Match on frag_data spec 0x0008 and last 0xfff8
2041          * means M is 0 and frag-offset is > 0.
2042          * This packet is last fragment of fragmented packet.
2043          * This is not yet supported in MLX5, return appropriate
2044          * error message.
2045          */
2046         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2047             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2048                 return rte_flow_error_set(error, ENOTSUP,
2049                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2050                                           last, "match on last "
2051                                           "fragment not supported");
2052         /* Other range values are invalid and rejected. */
2053         return rte_flow_error_set(error, EINVAL,
2054                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2055                                   "specified range not supported");
2056 }
2057
2058 /**
2059  * Validate the pop VLAN action.
2060  *
2061  * @param[in] dev
2062  *   Pointer to the rte_eth_dev structure.
2063  * @param[in] action_flags
2064  *   Holds the actions detected until now.
2065  * @param[in] action
2066  *   Pointer to the pop vlan action.
2067  * @param[in] item_flags
2068  *   The items found in this flow rule.
2069  * @param[in] attr
2070  *   Pointer to flow attributes.
2071  * @param[out] error
2072  *   Pointer to error structure.
2073  *
2074  * @return
2075  *   0 on success, a negative errno value otherwise and rte_errno is set.
2076  */
2077 static int
2078 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2079                                  uint64_t action_flags,
2080                                  const struct rte_flow_action *action,
2081                                  uint64_t item_flags,
2082                                  const struct rte_flow_attr *attr,
2083                                  struct rte_flow_error *error)
2084 {
2085         const struct mlx5_priv *priv = dev->data->dev_private;
2086
2087         (void)action;
2088         (void)attr;
2089         if (!priv->sh->pop_vlan_action)
2090                 return rte_flow_error_set(error, ENOTSUP,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "pop vlan action is not supported");
2094         if (attr->egress)
2095                 return rte_flow_error_set(error, ENOTSUP,
2096                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2097                                           NULL,
2098                                           "pop vlan action not supported for "
2099                                           "egress");
2100         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2101                 return rte_flow_error_set(error, ENOTSUP,
2102                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2103                                           "no support for multiple VLAN "
2104                                           "actions");
2105         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2106         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2107             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2108                 return rte_flow_error_set(error, ENOTSUP,
2109                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2110                                           NULL,
2111                                           "cannot pop vlan after decap without "
2112                                           "match on inner vlan in the flow");
2113         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2114         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2115             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2116                 return rte_flow_error_set(error, ENOTSUP,
2117                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2118                                           NULL,
2119                                           "cannot pop vlan without a "
2120                                           "match on (outer) vlan in the flow");
2121         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2122                 return rte_flow_error_set(error, EINVAL,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2124                                           "wrong action order, port_id should "
2125                                           "be after pop VLAN action");
2126         if (!attr->transfer && priv->representor)
2127                 return rte_flow_error_set(error, ENOTSUP,
2128                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2129                                           "pop vlan action for VF representor "
2130                                           "not supported on NIC table");
2131         return 0;
2132 }
2133
2134 /**
2135  * Get VLAN default info from vlan match info.
2136  *
2137  * @param[in] items
2138  *   the list of item specifications.
2139  * @param[out] vlan
2140  *   pointer VLAN info to fill to.
2141  *
2142  * @return
2143  *   0 on success, a negative errno value otherwise and rte_errno is set.
2144  */
2145 static void
2146 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2147                                   struct rte_vlan_hdr *vlan)
2148 {
2149         const struct rte_flow_item_vlan nic_mask = {
2150                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2151                                 MLX5DV_FLOW_VLAN_VID_MASK),
2152                 .inner_type = RTE_BE16(0xffff),
2153         };
2154
2155         if (items == NULL)
2156                 return;
2157         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2158                 int type = items->type;
2159
2160                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2161                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2162                         break;
2163         }
2164         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2165                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2166                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2167
2168                 /* If VLAN item in pattern doesn't contain data, return here. */
2169                 if (!vlan_v)
2170                         return;
2171                 if (!vlan_m)
2172                         vlan_m = &nic_mask;
2173                 /* Only full match values are accepted */
2174                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2175                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2176                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2177                         vlan->vlan_tci |=
2178                                 rte_be_to_cpu_16(vlan_v->tci &
2179                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2180                 }
2181                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2182                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2183                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2184                         vlan->vlan_tci |=
2185                                 rte_be_to_cpu_16(vlan_v->tci &
2186                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2187                 }
2188                 if (vlan_m->inner_type == nic_mask.inner_type)
2189                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2190                                                            vlan_m->inner_type);
2191         }
2192 }
2193
2194 /**
2195  * Validate the push VLAN action.
2196  *
2197  * @param[in] dev
2198  *   Pointer to the rte_eth_dev structure.
2199  * @param[in] action_flags
2200  *   Holds the actions detected until now.
2201  * @param[in] item_flags
2202  *   The items found in this flow rule.
2203  * @param[in] action
2204  *   Pointer to the action structure.
2205  * @param[in] attr
2206  *   Pointer to flow attributes
2207  * @param[out] error
2208  *   Pointer to error structure.
2209  *
2210  * @return
2211  *   0 on success, a negative errno value otherwise and rte_errno is set.
2212  */
2213 static int
2214 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2215                                   uint64_t action_flags,
2216                                   const struct rte_flow_item_vlan *vlan_m,
2217                                   const struct rte_flow_action *action,
2218                                   const struct rte_flow_attr *attr,
2219                                   struct rte_flow_error *error)
2220 {
2221         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2222         const struct mlx5_priv *priv = dev->data->dev_private;
2223
2224         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2225             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2226                 return rte_flow_error_set(error, EINVAL,
2227                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2228                                           "invalid vlan ethertype");
2229         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2232                                           "wrong action order, port_id should "
2233                                           "be after push VLAN");
2234         if (!attr->transfer && priv->representor)
2235                 return rte_flow_error_set(error, ENOTSUP,
2236                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2237                                           "push vlan action for VF representor "
2238                                           "not supported on NIC table");
2239         if (vlan_m &&
2240             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2241             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2242                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2243             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2244             !(mlx5_flow_find_action
2245                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2246                 return rte_flow_error_set(error, EINVAL,
2247                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2248                                           "not full match mask on VLAN PCP and "
2249                                           "there is no of_set_vlan_pcp action, "
2250                                           "push VLAN action cannot figure out "
2251                                           "PCP value");
2252         if (vlan_m &&
2253             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2254             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2255                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2256             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2257             !(mlx5_flow_find_action
2258                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2259                 return rte_flow_error_set(error, EINVAL,
2260                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2261                                           "not full match mask on VLAN VID and "
2262                                           "there is no of_set_vlan_vid action, "
2263                                           "push VLAN action cannot figure out "
2264                                           "VID value");
2265         (void)attr;
2266         return 0;
2267 }
2268
2269 /**
2270  * Validate the set VLAN PCP.
2271  *
2272  * @param[in] action_flags
2273  *   Holds the actions detected until now.
2274  * @param[in] actions
2275  *   Pointer to the list of actions remaining in the flow rule.
2276  * @param[out] error
2277  *   Pointer to error structure.
2278  *
2279  * @return
2280  *   0 on success, a negative errno value otherwise and rte_errno is set.
2281  */
2282 static int
2283 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2284                                      const struct rte_flow_action actions[],
2285                                      struct rte_flow_error *error)
2286 {
2287         const struct rte_flow_action *action = actions;
2288         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2289
2290         if (conf->vlan_pcp > 7)
2291                 return rte_flow_error_set(error, EINVAL,
2292                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2293                                           "VLAN PCP value is too big");
2294         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2295                 return rte_flow_error_set(error, ENOTSUP,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "set VLAN PCP action must follow "
2298                                           "the push VLAN action");
2299         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2300                 return rte_flow_error_set(error, ENOTSUP,
2301                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2302                                           "Multiple VLAN PCP modification are "
2303                                           "not supported");
2304         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2305                 return rte_flow_error_set(error, EINVAL,
2306                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2307                                           "wrong action order, port_id should "
2308                                           "be after set VLAN PCP");
2309         return 0;
2310 }
2311
2312 /**
2313  * Validate the set VLAN VID.
2314  *
2315  * @param[in] item_flags
2316  *   Holds the items detected in this rule.
2317  * @param[in] action_flags
2318  *   Holds the actions detected until now.
2319  * @param[in] actions
2320  *   Pointer to the list of actions remaining in the flow rule.
2321  * @param[out] error
2322  *   Pointer to error structure.
2323  *
2324  * @return
2325  *   0 on success, a negative errno value otherwise and rte_errno is set.
2326  */
2327 static int
2328 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2329                                      uint64_t action_flags,
2330                                      const struct rte_flow_action actions[],
2331                                      struct rte_flow_error *error)
2332 {
2333         const struct rte_flow_action *action = actions;
2334         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2335
2336         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2337                 return rte_flow_error_set(error, EINVAL,
2338                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2339                                           "VLAN VID value is too big");
2340         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2341             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2342                 return rte_flow_error_set(error, ENOTSUP,
2343                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2344                                           "set VLAN VID action must follow push"
2345                                           " VLAN action or match on VLAN item");
2346         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2347                 return rte_flow_error_set(error, ENOTSUP,
2348                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2349                                           "Multiple VLAN VID modifications are "
2350                                           "not supported");
2351         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2352                 return rte_flow_error_set(error, EINVAL,
2353                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2354                                           "wrong action order, port_id should "
2355                                           "be after set VLAN VID");
2356         return 0;
2357 }
2358
2359 /*
2360  * Validate the FLAG action.
2361  *
2362  * @param[in] dev
2363  *   Pointer to the rte_eth_dev structure.
2364  * @param[in] action_flags
2365  *   Holds the actions detected until now.
2366  * @param[in] attr
2367  *   Pointer to flow attributes
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2376                              uint64_t action_flags,
2377                              const struct rte_flow_attr *attr,
2378                              struct rte_flow_error *error)
2379 {
2380         struct mlx5_priv *priv = dev->data->dev_private;
2381         struct mlx5_dev_config *config = &priv->config;
2382         int ret;
2383
2384         /* Fall back if no extended metadata register support. */
2385         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2386                 return mlx5_flow_validate_action_flag(action_flags, attr,
2387                                                       error);
2388         /* Extensive metadata mode requires registers. */
2389         if (!mlx5_flow_ext_mreg_supported(dev))
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2392                                           "no metadata registers "
2393                                           "to support flag action");
2394         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2397                                           "extended metadata register"
2398                                           " isn't available");
2399         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2400         if (ret < 0)
2401                 return ret;
2402         MLX5_ASSERT(ret > 0);
2403         if (action_flags & MLX5_FLOW_ACTION_MARK)
2404                 return rte_flow_error_set(error, EINVAL,
2405                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2406                                           "can't mark and flag in same flow");
2407         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2408                 return rte_flow_error_set(error, EINVAL,
2409                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410                                           "can't have 2 flag"
2411                                           " actions in same flow");
2412         return 0;
2413 }
2414
2415 /**
2416  * Validate MARK action.
2417  *
2418  * @param[in] dev
2419  *   Pointer to the rte_eth_dev structure.
2420  * @param[in] action
2421  *   Pointer to action.
2422  * @param[in] action_flags
2423  *   Holds the actions detected until now.
2424  * @param[in] attr
2425  *   Pointer to flow attributes
2426  * @param[out] error
2427  *   Pointer to error structure.
2428  *
2429  * @return
2430  *   0 on success, a negative errno value otherwise and rte_errno is set.
2431  */
2432 static int
2433 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2434                              const struct rte_flow_action *action,
2435                              uint64_t action_flags,
2436                              const struct rte_flow_attr *attr,
2437                              struct rte_flow_error *error)
2438 {
2439         struct mlx5_priv *priv = dev->data->dev_private;
2440         struct mlx5_dev_config *config = &priv->config;
2441         const struct rte_flow_action_mark *mark = action->conf;
2442         int ret;
2443
2444         /* Fall back if no extended metadata register support. */
2445         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2446                 return mlx5_flow_validate_action_mark(action, action_flags,
2447                                                       attr, error);
2448         /* Extensive metadata mode requires registers. */
2449         if (!mlx5_flow_ext_mreg_supported(dev))
2450                 return rte_flow_error_set(error, ENOTSUP,
2451                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2452                                           "no metadata registers "
2453                                           "to support mark action");
2454         if (!priv->sh->dv_mark_mask)
2455                 return rte_flow_error_set(error, ENOTSUP,
2456                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2457                                           "extended metadata register"
2458                                           " isn't available");
2459         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2460         if (ret < 0)
2461                 return ret;
2462         MLX5_ASSERT(ret > 0);
2463         if (!mark)
2464                 return rte_flow_error_set(error, EINVAL,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2466                                           "configuration cannot be null");
2467         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2468                 return rte_flow_error_set(error, EINVAL,
2469                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2470                                           &mark->id,
2471                                           "mark id exceeds the limit");
2472         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2475                                           "can't flag and mark in same flow");
2476         if (action_flags & MLX5_FLOW_ACTION_MARK)
2477                 return rte_flow_error_set(error, EINVAL,
2478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2479                                           "can't have 2 mark actions in same"
2480                                           " flow");
2481         return 0;
2482 }
2483
2484 /**
2485  * Validate SET_META action.
2486  *
2487  * @param[in] dev
2488  *   Pointer to the rte_eth_dev structure.
2489  * @param[in] action
2490  *   Pointer to the action structure.
2491  * @param[in] action_flags
2492  *   Holds the actions detected until now.
2493  * @param[in] attr
2494  *   Pointer to flow attributes
2495  * @param[out] error
2496  *   Pointer to error structure.
2497  *
2498  * @return
2499  *   0 on success, a negative errno value otherwise and rte_errno is set.
2500  */
2501 static int
2502 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2503                                  const struct rte_flow_action *action,
2504                                  uint64_t action_flags __rte_unused,
2505                                  const struct rte_flow_attr *attr,
2506                                  struct rte_flow_error *error)
2507 {
2508         const struct rte_flow_action_set_meta *conf;
2509         uint32_t nic_mask = UINT32_MAX;
2510         int reg;
2511
2512         if (!mlx5_flow_ext_mreg_supported(dev))
2513                 return rte_flow_error_set(error, ENOTSUP,
2514                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2515                                           "extended metadata register"
2516                                           " isn't supported");
2517         reg = flow_dv_get_metadata_reg(dev, attr, error);
2518         if (reg < 0)
2519                 return reg;
2520         if (reg == REG_NON)
2521                 return rte_flow_error_set(error, ENOTSUP,
2522                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2523                                           "unavalable extended metadata register");
2524         if (reg != REG_A && reg != REG_B) {
2525                 struct mlx5_priv *priv = dev->data->dev_private;
2526
2527                 nic_mask = priv->sh->dv_meta_mask;
2528         }
2529         if (!(action->conf))
2530                 return rte_flow_error_set(error, EINVAL,
2531                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2532                                           "configuration cannot be null");
2533         conf = (const struct rte_flow_action_set_meta *)action->conf;
2534         if (!conf->mask)
2535                 return rte_flow_error_set(error, EINVAL,
2536                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2537                                           "zero mask doesn't have any effect");
2538         if (conf->mask & ~nic_mask)
2539                 return rte_flow_error_set(error, EINVAL,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "meta data must be within reg C0");
2542         return 0;
2543 }
2544
2545 /**
2546  * Validate SET_TAG action.
2547  *
2548  * @param[in] dev
2549  *   Pointer to the rte_eth_dev structure.
2550  * @param[in] action
2551  *   Pointer to the action structure.
2552  * @param[in] action_flags
2553  *   Holds the actions detected until now.
2554  * @param[in] attr
2555  *   Pointer to flow attributes
2556  * @param[out] error
2557  *   Pointer to error structure.
2558  *
2559  * @return
2560  *   0 on success, a negative errno value otherwise and rte_errno is set.
2561  */
2562 static int
2563 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2564                                 const struct rte_flow_action *action,
2565                                 uint64_t action_flags,
2566                                 const struct rte_flow_attr *attr,
2567                                 struct rte_flow_error *error)
2568 {
2569         const struct rte_flow_action_set_tag *conf;
2570         const uint64_t terminal_action_flags =
2571                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2572                 MLX5_FLOW_ACTION_RSS;
2573         int ret;
2574
2575         if (!mlx5_flow_ext_mreg_supported(dev))
2576                 return rte_flow_error_set(error, ENOTSUP,
2577                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2578                                           "extensive metadata register"
2579                                           " isn't supported");
2580         if (!(action->conf))
2581                 return rte_flow_error_set(error, EINVAL,
2582                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2583                                           "configuration cannot be null");
2584         conf = (const struct rte_flow_action_set_tag *)action->conf;
2585         if (!conf->mask)
2586                 return rte_flow_error_set(error, EINVAL,
2587                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2588                                           "zero mask doesn't have any effect");
2589         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2590         if (ret < 0)
2591                 return ret;
2592         if (!attr->transfer && attr->ingress &&
2593             (action_flags & terminal_action_flags))
2594                 return rte_flow_error_set(error, EINVAL,
2595                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2596                                           "set_tag has no effect"
2597                                           " with terminal actions");
2598         return 0;
2599 }
2600
2601 /**
2602  * Validate count action.
2603  *
2604  * @param[in] dev
2605  *   Pointer to rte_eth_dev structure.
2606  * @param[out] error
2607  *   Pointer to error structure.
2608  *
2609  * @return
2610  *   0 on success, a negative errno value otherwise and rte_errno is set.
2611  */
2612 static int
2613 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2614                               struct rte_flow_error *error)
2615 {
2616         struct mlx5_priv *priv = dev->data->dev_private;
2617
2618         if (!priv->config.devx)
2619                 goto notsup_err;
2620 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2621         return 0;
2622 #endif
2623 notsup_err:
2624         return rte_flow_error_set
2625                       (error, ENOTSUP,
2626                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2627                        NULL,
2628                        "count action not supported");
2629 }
2630
2631 /**
2632  * Validate the L2 encap action.
2633  *
2634  * @param[in] dev
2635  *   Pointer to the rte_eth_dev structure.
2636  * @param[in] action_flags
2637  *   Holds the actions detected until now.
2638  * @param[in] action
2639  *   Pointer to the action structure.
2640  * @param[in] attr
2641  *   Pointer to flow attributes.
2642  * @param[out] error
2643  *   Pointer to error structure.
2644  *
2645  * @return
2646  *   0 on success, a negative errno value otherwise and rte_errno is set.
2647  */
2648 static int
2649 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2650                                  uint64_t action_flags,
2651                                  const struct rte_flow_action *action,
2652                                  const struct rte_flow_attr *attr,
2653                                  struct rte_flow_error *error)
2654 {
2655         const struct mlx5_priv *priv = dev->data->dev_private;
2656
2657         if (!(action->conf))
2658                 return rte_flow_error_set(error, EINVAL,
2659                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2660                                           "configuration cannot be null");
2661         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2662                 return rte_flow_error_set(error, EINVAL,
2663                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2664                                           "can only have a single encap action "
2665                                           "in a flow");
2666         if (!attr->transfer && priv->representor)
2667                 return rte_flow_error_set(error, ENOTSUP,
2668                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2669                                           "encap action for VF representor "
2670                                           "not supported on NIC table");
2671         return 0;
2672 }
2673
2674 /**
2675  * Validate a decap action.
2676  *
2677  * @param[in] dev
2678  *   Pointer to the rte_eth_dev structure.
2679  * @param[in] action_flags
2680  *   Holds the actions detected until now.
2681  * @param[in] action
2682  *   Pointer to the action structure.
2683  * @param[in] item_flags
2684  *   Holds the items detected.
2685  * @param[in] attr
2686  *   Pointer to flow attributes
2687  * @param[out] error
2688  *   Pointer to error structure.
2689  *
2690  * @return
2691  *   0 on success, a negative errno value otherwise and rte_errno is set.
2692  */
2693 static int
2694 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2695                               uint64_t action_flags,
2696                               const struct rte_flow_action *action,
2697                               const uint64_t item_flags,
2698                               const struct rte_flow_attr *attr,
2699                               struct rte_flow_error *error)
2700 {
2701         const struct mlx5_priv *priv = dev->data->dev_private;
2702
2703         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2704             !priv->config.decap_en)
2705                 return rte_flow_error_set(error, ENOTSUP,
2706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2707                                           "decap is not enabled");
2708         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2709                 return rte_flow_error_set(error, ENOTSUP,
2710                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711                                           action_flags &
2712                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2713                                           "have a single decap action" : "decap "
2714                                           "after encap is not supported");
2715         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2716                 return rte_flow_error_set(error, EINVAL,
2717                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2718                                           "can't have decap action after"
2719                                           " modify action");
2720         if (attr->egress)
2721                 return rte_flow_error_set(error, ENOTSUP,
2722                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2723                                           NULL,
2724                                           "decap action not supported for "
2725                                           "egress");
2726         if (!attr->transfer && priv->representor)
2727                 return rte_flow_error_set(error, ENOTSUP,
2728                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2729                                           "decap action for VF representor "
2730                                           "not supported on NIC table");
2731         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2732             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2733                 return rte_flow_error_set(error, ENOTSUP,
2734                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2735                                 "VXLAN item should be present for VXLAN decap");
2736         return 0;
2737 }
2738
2739 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2740
2741 /**
2742  * Validate the raw encap and decap actions.
2743  *
2744  * @param[in] dev
2745  *   Pointer to the rte_eth_dev structure.
2746  * @param[in] decap
2747  *   Pointer to the decap action.
2748  * @param[in] encap
2749  *   Pointer to the encap action.
2750  * @param[in] attr
2751  *   Pointer to flow attributes
2752  * @param[in/out] action_flags
2753  *   Holds the actions detected until now.
2754  * @param[out] actions_n
2755  *   pointer to the number of actions counter.
2756  * @param[in] action
2757  *   Pointer to the action structure.
2758  * @param[in] item_flags
2759  *   Holds the items detected.
2760  * @param[out] error
2761  *   Pointer to error structure.
2762  *
2763  * @return
2764  *   0 on success, a negative errno value otherwise and rte_errno is set.
2765  */
2766 static int
2767 flow_dv_validate_action_raw_encap_decap
2768         (struct rte_eth_dev *dev,
2769          const struct rte_flow_action_raw_decap *decap,
2770          const struct rte_flow_action_raw_encap *encap,
2771          const struct rte_flow_attr *attr, uint64_t *action_flags,
2772          int *actions_n, const struct rte_flow_action *action,
2773          uint64_t item_flags, struct rte_flow_error *error)
2774 {
2775         const struct mlx5_priv *priv = dev->data->dev_private;
2776         int ret;
2777
2778         if (encap && (!encap->size || !encap->data))
2779                 return rte_flow_error_set(error, EINVAL,
2780                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2781                                           "raw encap data cannot be empty");
2782         if (decap && encap) {
2783                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2784                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2785                         /* L3 encap. */
2786                         decap = NULL;
2787                 else if (encap->size <=
2788                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2789                            decap->size >
2790                            MLX5_ENCAPSULATION_DECISION_SIZE)
2791                         /* L3 decap. */
2792                         encap = NULL;
2793                 else if (encap->size >
2794                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2795                            decap->size >
2796                            MLX5_ENCAPSULATION_DECISION_SIZE)
2797                         /* 2 L2 actions: encap and decap. */
2798                         ;
2799                 else
2800                         return rte_flow_error_set(error,
2801                                 ENOTSUP,
2802                                 RTE_FLOW_ERROR_TYPE_ACTION,
2803                                 NULL, "unsupported too small "
2804                                 "raw decap and too small raw "
2805                                 "encap combination");
2806         }
2807         if (decap) {
2808                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2809                                                     item_flags, attr, error);
2810                 if (ret < 0)
2811                         return ret;
2812                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2813                 ++(*actions_n);
2814         }
2815         if (encap) {
2816                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2817                         return rte_flow_error_set(error, ENOTSUP,
2818                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2819                                                   NULL,
2820                                                   "small raw encap size");
2821                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2822                         return rte_flow_error_set(error, EINVAL,
2823                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2824                                                   NULL,
2825                                                   "more than one encap action");
2826                 if (!attr->transfer && priv->representor)
2827                         return rte_flow_error_set
2828                                         (error, ENOTSUP,
2829                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2830                                          "encap action for VF representor "
2831                                          "not supported on NIC table");
2832                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2833                 ++(*actions_n);
2834         }
2835         return 0;
2836 }
2837
2838 /**
2839  * Match encap_decap resource.
2840  *
2841  * @param list
2842  *   Pointer to the hash list.
2843  * @param entry
2844  *   Pointer to exist resource entry object.
2845  * @param key
2846  *   Key of the new entry.
2847  * @param ctx_cb
2848  *   Pointer to new encap_decap resource.
2849  *
2850  * @return
2851  *   0 on matching, none-zero otherwise.
2852  */
2853 int
2854 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2855                              struct mlx5_hlist_entry *entry,
2856                              uint64_t key __rte_unused, void *cb_ctx)
2857 {
2858         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2859         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2860         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2861
2862         cache_resource = container_of(entry,
2863                                       struct mlx5_flow_dv_encap_decap_resource,
2864                                       entry);
2865         if (resource->reformat_type == cache_resource->reformat_type &&
2866             resource->ft_type == cache_resource->ft_type &&
2867             resource->flags == cache_resource->flags &&
2868             resource->size == cache_resource->size &&
2869             !memcmp((const void *)resource->buf,
2870                     (const void *)cache_resource->buf,
2871                     resource->size))
2872                 return 0;
2873         return -1;
2874 }
2875
2876 /**
2877  * Allocate encap_decap resource.
2878  *
2879  * @param list
2880  *   Pointer to the hash list.
2881  * @param entry
2882  *   Pointer to exist resource entry object.
2883  * @param ctx_cb
2884  *   Pointer to new encap_decap resource.
2885  *
2886  * @return
2887  *   0 on matching, none-zero otherwise.
2888  */
2889 struct mlx5_hlist_entry *
2890 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2891                               uint64_t key __rte_unused,
2892                               void *cb_ctx)
2893 {
2894         struct mlx5_dev_ctx_shared *sh = list->ctx;
2895         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2896         struct mlx5dv_dr_domain *domain;
2897         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2898         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2899         uint32_t idx;
2900         int ret;
2901
2902         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2903                 domain = sh->fdb_domain;
2904         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2905                 domain = sh->rx_domain;
2906         else
2907                 domain = sh->tx_domain;
2908         /* Register new encap/decap resource. */
2909         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2910                                        &idx);
2911         if (!cache_resource) {
2912                 rte_flow_error_set(ctx->error, ENOMEM,
2913                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914                                    "cannot allocate resource memory");
2915                 return NULL;
2916         }
2917         *cache_resource = *resource;
2918         cache_resource->idx = idx;
2919         ret = mlx5_flow_os_create_flow_action_packet_reformat
2920                                         (sh->ctx, domain, cache_resource,
2921                                          &cache_resource->action);
2922         if (ret) {
2923                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2924                 rte_flow_error_set(ctx->error, ENOMEM,
2925                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2926                                    NULL, "cannot create action");
2927                 return NULL;
2928         }
2929
2930         return &cache_resource->entry;
2931 }
2932
2933 /**
2934  * Find existing encap/decap resource or create and register a new one.
2935  *
2936  * @param[in, out] dev
2937  *   Pointer to rte_eth_dev structure.
2938  * @param[in, out] resource
2939  *   Pointer to encap/decap resource.
2940  * @parm[in, out] dev_flow
2941  *   Pointer to the dev_flow.
2942  * @param[out] error
2943  *   pointer to error structure.
2944  *
2945  * @return
2946  *   0 on success otherwise -errno and errno is set.
2947  */
2948 static int
2949 flow_dv_encap_decap_resource_register
2950                         (struct rte_eth_dev *dev,
2951                          struct mlx5_flow_dv_encap_decap_resource *resource,
2952                          struct mlx5_flow *dev_flow,
2953                          struct rte_flow_error *error)
2954 {
2955         struct mlx5_priv *priv = dev->data->dev_private;
2956         struct mlx5_dev_ctx_shared *sh = priv->sh;
2957         struct mlx5_hlist_entry *entry;
2958         union {
2959                 struct {
2960                         uint32_t ft_type:8;
2961                         uint32_t refmt_type:8;
2962                         /*
2963                          * Header reformat actions can be shared between
2964                          * non-root tables. One bit to indicate non-root
2965                          * table or not.
2966                          */
2967                         uint32_t is_root:1;
2968                         uint32_t reserve:15;
2969                 };
2970                 uint32_t v32;
2971         } encap_decap_key = {
2972                 {
2973                         .ft_type = resource->ft_type,
2974                         .refmt_type = resource->reformat_type,
2975                         .is_root = !!dev_flow->dv.group,
2976                         .reserve = 0,
2977                 }
2978         };
2979         struct mlx5_flow_cb_ctx ctx = {
2980                 .error = error,
2981                 .data = resource,
2982         };
2983         uint64_t key64;
2984
2985         resource->flags = dev_flow->dv.group ? 0 : 1;
2986         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2987                                  sizeof(encap_decap_key.v32), 0);
2988         if (resource->reformat_type !=
2989             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2990             resource->size)
2991                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2992         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2993         if (!entry)
2994                 return -rte_errno;
2995         resource = container_of(entry, typeof(*resource), entry);
2996         dev_flow->dv.encap_decap = resource;
2997         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2998         return 0;
2999 }
3000
3001 /**
3002  * Find existing table jump resource or create and register a new one.
3003  *
3004  * @param[in, out] dev
3005  *   Pointer to rte_eth_dev structure.
3006  * @param[in, out] tbl
3007  *   Pointer to flow table resource.
3008  * @parm[in, out] dev_flow
3009  *   Pointer to the dev_flow.
3010  * @param[out] error
3011  *   pointer to error structure.
3012  *
3013  * @return
3014  *   0 on success otherwise -errno and errno is set.
3015  */
3016 static int
3017 flow_dv_jump_tbl_resource_register
3018                         (struct rte_eth_dev *dev __rte_unused,
3019                          struct mlx5_flow_tbl_resource *tbl,
3020                          struct mlx5_flow *dev_flow,
3021                          struct rte_flow_error *error __rte_unused)
3022 {
3023         struct mlx5_flow_tbl_data_entry *tbl_data =
3024                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3025
3026         MLX5_ASSERT(tbl);
3027         MLX5_ASSERT(tbl_data->jump.action);
3028         dev_flow->handle->rix_jump = tbl_data->idx;
3029         dev_flow->dv.jump = &tbl_data->jump;
3030         return 0;
3031 }
3032
3033 int
3034 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3035                          struct mlx5_cache_entry *entry, void *cb_ctx)
3036 {
3037         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3038         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3039         struct mlx5_flow_dv_port_id_action_resource *res =
3040                         container_of(entry, typeof(*res), entry);
3041
3042         return ref->port_id != res->port_id;
3043 }
3044
3045 struct mlx5_cache_entry *
3046 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3047                           struct mlx5_cache_entry *entry __rte_unused,
3048                           void *cb_ctx)
3049 {
3050         struct mlx5_dev_ctx_shared *sh = list->ctx;
3051         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3052         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3053         struct mlx5_flow_dv_port_id_action_resource *cache;
3054         uint32_t idx;
3055         int ret;
3056
3057         /* Register new port id action resource. */
3058         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3059         if (!cache) {
3060                 rte_flow_error_set(ctx->error, ENOMEM,
3061                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3062                                    "cannot allocate port_id action cache memory");
3063                 return NULL;
3064         }
3065         *cache = *ref;
3066         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3067                                                         ref->port_id,
3068                                                         &cache->action);
3069         if (ret) {
3070                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3071                 rte_flow_error_set(ctx->error, ENOMEM,
3072                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3073                                    "cannot create action");
3074                 return NULL;
3075         }
3076         return &cache->entry;
3077 }
3078
3079 /**
3080  * Find existing table port ID resource or create and register a new one.
3081  *
3082  * @param[in, out] dev
3083  *   Pointer to rte_eth_dev structure.
3084  * @param[in, out] resource
3085  *   Pointer to port ID action resource.
3086  * @parm[in, out] dev_flow
3087  *   Pointer to the dev_flow.
3088  * @param[out] error
3089  *   pointer to error structure.
3090  *
3091  * @return
3092  *   0 on success otherwise -errno and errno is set.
3093  */
3094 static int
3095 flow_dv_port_id_action_resource_register
3096                         (struct rte_eth_dev *dev,
3097                          struct mlx5_flow_dv_port_id_action_resource *resource,
3098                          struct mlx5_flow *dev_flow,
3099                          struct rte_flow_error *error)
3100 {
3101         struct mlx5_priv *priv = dev->data->dev_private;
3102         struct mlx5_cache_entry *entry;
3103         struct mlx5_flow_dv_port_id_action_resource *cache;
3104         struct mlx5_flow_cb_ctx ctx = {
3105                 .error = error,
3106                 .data = resource,
3107         };
3108
3109         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3110         if (!entry)
3111                 return -rte_errno;
3112         cache = container_of(entry, typeof(*cache), entry);
3113         dev_flow->dv.port_id_action = cache;
3114         dev_flow->handle->rix_port_id_action = cache->idx;
3115         return 0;
3116 }
3117
3118 int
3119 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3120                          struct mlx5_cache_entry *entry, void *cb_ctx)
3121 {
3122         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3123         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3124         struct mlx5_flow_dv_push_vlan_action_resource *res =
3125                         container_of(entry, typeof(*res), entry);
3126
3127         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3128 }
3129
3130 struct mlx5_cache_entry *
3131 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3132                           struct mlx5_cache_entry *entry __rte_unused,
3133                           void *cb_ctx)
3134 {
3135         struct mlx5_dev_ctx_shared *sh = list->ctx;
3136         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3137         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3138         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3139         struct mlx5dv_dr_domain *domain;
3140         uint32_t idx;
3141         int ret;
3142
3143         /* Register new port id action resource. */
3144         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3145         if (!cache) {
3146                 rte_flow_error_set(ctx->error, ENOMEM,
3147                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3148                                    "cannot allocate push_vlan action cache memory");
3149                 return NULL;
3150         }
3151         *cache = *ref;
3152         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3153                 domain = sh->fdb_domain;
3154         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3155                 domain = sh->rx_domain;
3156         else
3157                 domain = sh->tx_domain;
3158         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3159                                                         &cache->action);
3160         if (ret) {
3161                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3162                 rte_flow_error_set(ctx->error, ENOMEM,
3163                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3164                                    "cannot create push vlan action");
3165                 return NULL;
3166         }
3167         return &cache->entry;
3168 }
3169
3170 /**
3171  * Find existing push vlan resource or create and register a new one.
3172  *
3173  * @param [in, out] dev
3174  *   Pointer to rte_eth_dev structure.
3175  * @param[in, out] resource
3176  *   Pointer to port ID action resource.
3177  * @parm[in, out] dev_flow
3178  *   Pointer to the dev_flow.
3179  * @param[out] error
3180  *   pointer to error structure.
3181  *
3182  * @return
3183  *   0 on success otherwise -errno and errno is set.
3184  */
3185 static int
3186 flow_dv_push_vlan_action_resource_register
3187                        (struct rte_eth_dev *dev,
3188                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3189                         struct mlx5_flow *dev_flow,
3190                         struct rte_flow_error *error)
3191 {
3192         struct mlx5_priv *priv = dev->data->dev_private;
3193         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3194         struct mlx5_cache_entry *entry;
3195         struct mlx5_flow_cb_ctx ctx = {
3196                 .error = error,
3197                 .data = resource,
3198         };
3199
3200         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3201         if (!entry)
3202                 return -rte_errno;
3203         cache = container_of(entry, typeof(*cache), entry);
3204
3205         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3206         dev_flow->dv.push_vlan_res = cache;
3207         return 0;
3208 }
3209
3210 /**
3211  * Get the size of specific rte_flow_item_type hdr size
3212  *
3213  * @param[in] item_type
3214  *   Tested rte_flow_item_type.
3215  *
3216  * @return
3217  *   sizeof struct item_type, 0 if void or irrelevant.
3218  */
3219 static size_t
3220 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3221 {
3222         size_t retval;
3223
3224         switch (item_type) {
3225         case RTE_FLOW_ITEM_TYPE_ETH:
3226                 retval = sizeof(struct rte_ether_hdr);
3227                 break;
3228         case RTE_FLOW_ITEM_TYPE_VLAN:
3229                 retval = sizeof(struct rte_vlan_hdr);
3230                 break;
3231         case RTE_FLOW_ITEM_TYPE_IPV4:
3232                 retval = sizeof(struct rte_ipv4_hdr);
3233                 break;
3234         case RTE_FLOW_ITEM_TYPE_IPV6:
3235                 retval = sizeof(struct rte_ipv6_hdr);
3236                 break;
3237         case RTE_FLOW_ITEM_TYPE_UDP:
3238                 retval = sizeof(struct rte_udp_hdr);
3239                 break;
3240         case RTE_FLOW_ITEM_TYPE_TCP:
3241                 retval = sizeof(struct rte_tcp_hdr);
3242                 break;
3243         case RTE_FLOW_ITEM_TYPE_VXLAN:
3244         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3245                 retval = sizeof(struct rte_vxlan_hdr);
3246                 break;
3247         case RTE_FLOW_ITEM_TYPE_GRE:
3248         case RTE_FLOW_ITEM_TYPE_NVGRE:
3249                 retval = sizeof(struct rte_gre_hdr);
3250                 break;
3251         case RTE_FLOW_ITEM_TYPE_MPLS:
3252                 retval = sizeof(struct rte_mpls_hdr);
3253                 break;
3254         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3255         default:
3256                 retval = 0;
3257                 break;
3258         }
3259         return retval;
3260 }
3261
3262 #define MLX5_ENCAP_IPV4_VERSION         0x40
3263 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3264 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3265 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3266 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3267 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3268 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3269
3270 /**
3271  * Convert the encap action data from list of rte_flow_item to raw buffer
3272  *
3273  * @param[in] items
3274  *   Pointer to rte_flow_item objects list.
3275  * @param[out] buf
3276  *   Pointer to the output buffer.
3277  * @param[out] size
3278  *   Pointer to the output buffer size.
3279  * @param[out] error
3280  *   Pointer to the error structure.
3281  *
3282  * @return
3283  *   0 on success, a negative errno value otherwise and rte_errno is set.
3284  */
3285 static int
3286 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3287                            size_t *size, struct rte_flow_error *error)
3288 {
3289         struct rte_ether_hdr *eth = NULL;
3290         struct rte_vlan_hdr *vlan = NULL;
3291         struct rte_ipv4_hdr *ipv4 = NULL;
3292         struct rte_ipv6_hdr *ipv6 = NULL;
3293         struct rte_udp_hdr *udp = NULL;
3294         struct rte_vxlan_hdr *vxlan = NULL;
3295         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3296         struct rte_gre_hdr *gre = NULL;
3297         size_t len;
3298         size_t temp_size = 0;
3299
3300         if (!items)
3301                 return rte_flow_error_set(error, EINVAL,
3302                                           RTE_FLOW_ERROR_TYPE_ACTION,
3303                                           NULL, "invalid empty data");
3304         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3305                 len = flow_dv_get_item_hdr_len(items->type);
3306                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3307                         return rte_flow_error_set(error, EINVAL,
3308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3309                                                   (void *)items->type,
3310                                                   "items total size is too big"
3311                                                   " for encap action");
3312                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3313                 switch (items->type) {
3314                 case RTE_FLOW_ITEM_TYPE_ETH:
3315                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3316                         break;
3317                 case RTE_FLOW_ITEM_TYPE_VLAN:
3318                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3319                         if (!eth)
3320                                 return rte_flow_error_set(error, EINVAL,
3321                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3322                                                 (void *)items->type,
3323                                                 "eth header not found");
3324                         if (!eth->ether_type)
3325                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3326                         break;
3327                 case RTE_FLOW_ITEM_TYPE_IPV4:
3328                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3329                         if (!vlan && !eth)
3330                                 return rte_flow_error_set(error, EINVAL,
3331                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3332                                                 (void *)items->type,
3333                                                 "neither eth nor vlan"
3334                                                 " header found");
3335                         if (vlan && !vlan->eth_proto)
3336                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3337                         else if (eth && !eth->ether_type)
3338                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3339                         if (!ipv4->version_ihl)
3340                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3341                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3342                         if (!ipv4->time_to_live)
3343                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3344                         break;
3345                 case RTE_FLOW_ITEM_TYPE_IPV6:
3346                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3347                         if (!vlan && !eth)
3348                                 return rte_flow_error_set(error, EINVAL,
3349                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3350                                                 (void *)items->type,
3351                                                 "neither eth nor vlan"
3352                                                 " header found");
3353                         if (vlan && !vlan->eth_proto)
3354                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3355                         else if (eth && !eth->ether_type)
3356                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3357                         if (!ipv6->vtc_flow)
3358                                 ipv6->vtc_flow =
3359                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3360                         if (!ipv6->hop_limits)
3361                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3362                         break;
3363                 case RTE_FLOW_ITEM_TYPE_UDP:
3364                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3365                         if (!ipv4 && !ipv6)
3366                                 return rte_flow_error_set(error, EINVAL,
3367                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3368                                                 (void *)items->type,
3369                                                 "ip header not found");
3370                         if (ipv4 && !ipv4->next_proto_id)
3371                                 ipv4->next_proto_id = IPPROTO_UDP;
3372                         else if (ipv6 && !ipv6->proto)
3373                                 ipv6->proto = IPPROTO_UDP;
3374                         break;
3375                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3376                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3377                         if (!udp)
3378                                 return rte_flow_error_set(error, EINVAL,
3379                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3380                                                 (void *)items->type,
3381                                                 "udp header not found");
3382                         if (!udp->dst_port)
3383                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3384                         if (!vxlan->vx_flags)
3385                                 vxlan->vx_flags =
3386                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3387                         break;
3388                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3389                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3390                         if (!udp)
3391                                 return rte_flow_error_set(error, EINVAL,
3392                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3393                                                 (void *)items->type,
3394                                                 "udp header not found");
3395                         if (!vxlan_gpe->proto)
3396                                 return rte_flow_error_set(error, EINVAL,
3397                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3398                                                 (void *)items->type,
3399                                                 "next protocol not found");
3400                         if (!udp->dst_port)
3401                                 udp->dst_port =
3402                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3403                         if (!vxlan_gpe->vx_flags)
3404                                 vxlan_gpe->vx_flags =
3405                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3406                         break;
3407                 case RTE_FLOW_ITEM_TYPE_GRE:
3408                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3409                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3410                         if (!gre->proto)
3411                                 return rte_flow_error_set(error, EINVAL,
3412                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3413                                                 (void *)items->type,
3414                                                 "next protocol not found");
3415                         if (!ipv4 && !ipv6)
3416                                 return rte_flow_error_set(error, EINVAL,
3417                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3418                                                 (void *)items->type,
3419                                                 "ip header not found");
3420                         if (ipv4 && !ipv4->next_proto_id)
3421                                 ipv4->next_proto_id = IPPROTO_GRE;
3422                         else if (ipv6 && !ipv6->proto)
3423                                 ipv6->proto = IPPROTO_GRE;
3424                         break;
3425                 case RTE_FLOW_ITEM_TYPE_VOID:
3426                         break;
3427                 default:
3428                         return rte_flow_error_set(error, EINVAL,
3429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3430                                                   (void *)items->type,
3431                                                   "unsupported item type");
3432                         break;
3433                 }
3434                 temp_size += len;
3435         }
3436         *size = temp_size;
3437         return 0;
3438 }
3439
3440 static int
3441 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3442 {
3443         struct rte_ether_hdr *eth = NULL;
3444         struct rte_vlan_hdr *vlan = NULL;
3445         struct rte_ipv6_hdr *ipv6 = NULL;
3446         struct rte_udp_hdr *udp = NULL;
3447         char *next_hdr;
3448         uint16_t proto;
3449
3450         eth = (struct rte_ether_hdr *)data;
3451         next_hdr = (char *)(eth + 1);
3452         proto = RTE_BE16(eth->ether_type);
3453
3454         /* VLAN skipping */
3455         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3456                 vlan = (struct rte_vlan_hdr *)next_hdr;
3457                 proto = RTE_BE16(vlan->eth_proto);
3458                 next_hdr += sizeof(struct rte_vlan_hdr);
3459         }
3460
3461         /* HW calculates IPv4 csum. no need to proceed */
3462         if (proto == RTE_ETHER_TYPE_IPV4)
3463                 return 0;
3464
3465         /* non IPv4/IPv6 header. not supported */
3466         if (proto != RTE_ETHER_TYPE_IPV6) {
3467                 return rte_flow_error_set(error, ENOTSUP,
3468                                           RTE_FLOW_ERROR_TYPE_ACTION,
3469                                           NULL, "Cannot offload non IPv4/IPv6");
3470         }
3471
3472         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3473
3474         /* ignore non UDP */
3475         if (ipv6->proto != IPPROTO_UDP)
3476                 return 0;
3477
3478         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3479         udp->dgram_cksum = 0;
3480
3481         return 0;
3482 }
3483
3484 /**
3485  * Convert L2 encap action to DV specification.
3486  *
3487  * @param[in] dev
3488  *   Pointer to rte_eth_dev structure.
3489  * @param[in] action
3490  *   Pointer to action structure.
3491  * @param[in, out] dev_flow
3492  *   Pointer to the mlx5_flow.
3493  * @param[in] transfer
3494  *   Mark if the flow is E-Switch flow.
3495  * @param[out] error
3496  *   Pointer to the error structure.
3497  *
3498  * @return
3499  *   0 on success, a negative errno value otherwise and rte_errno is set.
3500  */
3501 static int
3502 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3503                                const struct rte_flow_action *action,
3504                                struct mlx5_flow *dev_flow,
3505                                uint8_t transfer,
3506                                struct rte_flow_error *error)
3507 {
3508         const struct rte_flow_item *encap_data;
3509         const struct rte_flow_action_raw_encap *raw_encap_data;
3510         struct mlx5_flow_dv_encap_decap_resource res = {
3511                 .reformat_type =
3512                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3513                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3514                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3515         };
3516
3517         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3518                 raw_encap_data =
3519                         (const struct rte_flow_action_raw_encap *)action->conf;
3520                 res.size = raw_encap_data->size;
3521                 memcpy(res.buf, raw_encap_data->data, res.size);
3522         } else {
3523                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3524                         encap_data =
3525                                 ((const struct rte_flow_action_vxlan_encap *)
3526                                                 action->conf)->definition;
3527                 else
3528                         encap_data =
3529                                 ((const struct rte_flow_action_nvgre_encap *)
3530                                                 action->conf)->definition;
3531                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3532                                                &res.size, error))
3533                         return -rte_errno;
3534         }
3535         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3536                 return -rte_errno;
3537         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3538                 return rte_flow_error_set(error, EINVAL,
3539                                           RTE_FLOW_ERROR_TYPE_ACTION,
3540                                           NULL, "can't create L2 encap action");
3541         return 0;
3542 }
3543
3544 /**
3545  * Convert L2 decap action to DV specification.
3546  *
3547  * @param[in] dev
3548  *   Pointer to rte_eth_dev structure.
3549  * @param[in, out] dev_flow
3550  *   Pointer to the mlx5_flow.
3551  * @param[in] transfer
3552  *   Mark if the flow is E-Switch flow.
3553  * @param[out] error
3554  *   Pointer to the error structure.
3555  *
3556  * @return
3557  *   0 on success, a negative errno value otherwise and rte_errno is set.
3558  */
3559 static int
3560 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3561                                struct mlx5_flow *dev_flow,
3562                                uint8_t transfer,
3563                                struct rte_flow_error *error)
3564 {
3565         struct mlx5_flow_dv_encap_decap_resource res = {
3566                 .size = 0,
3567                 .reformat_type =
3568                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3569                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3570                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3571         };
3572
3573         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3574                 return rte_flow_error_set(error, EINVAL,
3575                                           RTE_FLOW_ERROR_TYPE_ACTION,
3576                                           NULL, "can't create L2 decap action");
3577         return 0;
3578 }
3579
3580 /**
3581  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3582  *
3583  * @param[in] dev
3584  *   Pointer to rte_eth_dev structure.
3585  * @param[in] action
3586  *   Pointer to action structure.
3587  * @param[in, out] dev_flow
3588  *   Pointer to the mlx5_flow.
3589  * @param[in] attr
3590  *   Pointer to the flow attributes.
3591  * @param[out] error
3592  *   Pointer to the error structure.
3593  *
3594  * @return
3595  *   0 on success, a negative errno value otherwise and rte_errno is set.
3596  */
3597 static int
3598 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3599                                 const struct rte_flow_action *action,
3600                                 struct mlx5_flow *dev_flow,
3601                                 const struct rte_flow_attr *attr,
3602                                 struct rte_flow_error *error)
3603 {
3604         const struct rte_flow_action_raw_encap *encap_data;
3605         struct mlx5_flow_dv_encap_decap_resource res;
3606
3607         memset(&res, 0, sizeof(res));
3608         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3609         res.size = encap_data->size;
3610         memcpy(res.buf, encap_data->data, res.size);
3611         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3612                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3613                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3614         if (attr->transfer)
3615                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3616         else
3617                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3618                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3619         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3620                 return rte_flow_error_set(error, EINVAL,
3621                                           RTE_FLOW_ERROR_TYPE_ACTION,
3622                                           NULL, "can't create encap action");
3623         return 0;
3624 }
3625
3626 /**
3627  * Create action push VLAN.
3628  *
3629  * @param[in] dev
3630  *   Pointer to rte_eth_dev structure.
3631  * @param[in] attr
3632  *   Pointer to the flow attributes.
3633  * @param[in] vlan
3634  *   Pointer to the vlan to push to the Ethernet header.
3635  * @param[in, out] dev_flow
3636  *   Pointer to the mlx5_flow.
3637  * @param[out] error
3638  *   Pointer to the error structure.
3639  *
3640  * @return
3641  *   0 on success, a negative errno value otherwise and rte_errno is set.
3642  */
3643 static int
3644 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3645                                 const struct rte_flow_attr *attr,
3646                                 const struct rte_vlan_hdr *vlan,
3647                                 struct mlx5_flow *dev_flow,
3648                                 struct rte_flow_error *error)
3649 {
3650         struct mlx5_flow_dv_push_vlan_action_resource res;
3651
3652         memset(&res, 0, sizeof(res));
3653         res.vlan_tag =
3654                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3655                                  vlan->vlan_tci);
3656         if (attr->transfer)
3657                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3658         else
3659                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3660                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3661         return flow_dv_push_vlan_action_resource_register
3662                                             (dev, &res, dev_flow, error);
3663 }
3664
3665 static int fdb_mirror;
3666
3667 /**
3668  * Validate the modify-header actions.
3669  *
3670  * @param[in] action_flags
3671  *   Holds the actions detected until now.
3672  * @param[in] action
3673  *   Pointer to the modify action.
3674  * @param[out] error
3675  *   Pointer to error structure.
3676  *
3677  * @return
3678  *   0 on success, a negative errno value otherwise and rte_errno is set.
3679  */
3680 static int
3681 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3682                                    const struct rte_flow_action *action,
3683                                    struct rte_flow_error *error)
3684 {
3685         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3686                 return rte_flow_error_set(error, EINVAL,
3687                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3688                                           NULL, "action configuration not set");
3689         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3690                 return rte_flow_error_set(error, EINVAL,
3691                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3692                                           "can't have encap action before"
3693                                           " modify action");
3694         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3695                 return rte_flow_error_set(error, EINVAL,
3696                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697                                           "can't support sample action before"
3698                                           " modify action for E-Switch"
3699                                           " mirroring");
3700         return 0;
3701 }
3702
3703 /**
3704  * Validate the modify-header MAC address actions.
3705  *
3706  * @param[in] action_flags
3707  *   Holds the actions detected until now.
3708  * @param[in] action
3709  *   Pointer to the modify action.
3710  * @param[in] item_flags
3711  *   Holds the items detected.
3712  * @param[out] error
3713  *   Pointer to error structure.
3714  *
3715  * @return
3716  *   0 on success, a negative errno value otherwise and rte_errno is set.
3717  */
3718 static int
3719 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3720                                    const struct rte_flow_action *action,
3721                                    const uint64_t item_flags,
3722                                    struct rte_flow_error *error)
3723 {
3724         int ret = 0;
3725
3726         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3727         if (!ret) {
3728                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3729                         return rte_flow_error_set(error, EINVAL,
3730                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3731                                                   NULL,
3732                                                   "no L2 item in pattern");
3733         }
3734         return ret;
3735 }
3736
3737 /**
3738  * Validate the modify-header IPv4 address actions.
3739  *
3740  * @param[in] action_flags
3741  *   Holds the actions detected until now.
3742  * @param[in] action
3743  *   Pointer to the modify action.
3744  * @param[in] item_flags
3745  *   Holds the items detected.
3746  * @param[out] error
3747  *   Pointer to error structure.
3748  *
3749  * @return
3750  *   0 on success, a negative errno value otherwise and rte_errno is set.
3751  */
3752 static int
3753 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3754                                     const struct rte_flow_action *action,
3755                                     const uint64_t item_flags,
3756                                     struct rte_flow_error *error)
3757 {
3758         int ret = 0;
3759         uint64_t layer;
3760
3761         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3762         if (!ret) {
3763                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3764                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3765                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3766                 if (!(item_flags & layer))
3767                         return rte_flow_error_set(error, EINVAL,
3768                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3769                                                   NULL,
3770                                                   "no ipv4 item in pattern");
3771         }
3772         return ret;
3773 }
3774
3775 /**
3776  * Validate the modify-header IPv6 address actions.
3777  *
3778  * @param[in] action_flags
3779  *   Holds the actions detected until now.
3780  * @param[in] action
3781  *   Pointer to the modify action.
3782  * @param[in] item_flags
3783  *   Holds the items detected.
3784  * @param[out] error
3785  *   Pointer to error structure.
3786  *
3787  * @return
3788  *   0 on success, a negative errno value otherwise and rte_errno is set.
3789  */
3790 static int
3791 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3792                                     const struct rte_flow_action *action,
3793                                     const uint64_t item_flags,
3794                                     struct rte_flow_error *error)
3795 {
3796         int ret = 0;
3797         uint64_t layer;
3798
3799         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3800         if (!ret) {
3801                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3802                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3803                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3804                 if (!(item_flags & layer))
3805                         return rte_flow_error_set(error, EINVAL,
3806                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3807                                                   NULL,
3808                                                   "no ipv6 item in pattern");
3809         }
3810         return ret;
3811 }
3812
3813 /**
3814  * Validate the modify-header TP actions.
3815  *
3816  * @param[in] action_flags
3817  *   Holds the actions detected until now.
3818  * @param[in] action
3819  *   Pointer to the modify action.
3820  * @param[in] item_flags
3821  *   Holds the items detected.
3822  * @param[out] error
3823  *   Pointer to error structure.
3824  *
3825  * @return
3826  *   0 on success, a negative errno value otherwise and rte_errno is set.
3827  */
3828 static int
3829 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3830                                   const struct rte_flow_action *action,
3831                                   const uint64_t item_flags,
3832                                   struct rte_flow_error *error)
3833 {
3834         int ret = 0;
3835         uint64_t layer;
3836
3837         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3838         if (!ret) {
3839                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3840                                  MLX5_FLOW_LAYER_INNER_L4 :
3841                                  MLX5_FLOW_LAYER_OUTER_L4;
3842                 if (!(item_flags & layer))
3843                         return rte_flow_error_set(error, EINVAL,
3844                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3845                                                   NULL, "no transport layer "
3846                                                   "in pattern");
3847         }
3848         return ret;
3849 }
3850
3851 /**
3852  * Validate the modify-header actions of increment/decrement
3853  * TCP Sequence-number.
3854  *
3855  * @param[in] action_flags
3856  *   Holds the actions detected until now.
3857  * @param[in] action
3858  *   Pointer to the modify action.
3859  * @param[in] item_flags
3860  *   Holds the items detected.
3861  * @param[out] error
3862  *   Pointer to error structure.
3863  *
3864  * @return
3865  *   0 on success, a negative errno value otherwise and rte_errno is set.
3866  */
3867 static int
3868 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3869                                        const struct rte_flow_action *action,
3870                                        const uint64_t item_flags,
3871                                        struct rte_flow_error *error)
3872 {
3873         int ret = 0;
3874         uint64_t layer;
3875
3876         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3877         if (!ret) {
3878                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3879                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3880                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3881                 if (!(item_flags & layer))
3882                         return rte_flow_error_set(error, EINVAL,
3883                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3884                                                   NULL, "no TCP item in"
3885                                                   " pattern");
3886                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3887                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3888                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3889                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3890                         return rte_flow_error_set(error, EINVAL,
3891                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3892                                                   NULL,
3893                                                   "cannot decrease and increase"
3894                                                   " TCP sequence number"
3895                                                   " at the same time");
3896         }
3897         return ret;
3898 }
3899
3900 /**
3901  * Validate the modify-header actions of increment/decrement
3902  * TCP Acknowledgment number.
3903  *
3904  * @param[in] action_flags
3905  *   Holds the actions detected until now.
3906  * @param[in] action
3907  *   Pointer to the modify action.
3908  * @param[in] item_flags
3909  *   Holds the items detected.
3910  * @param[out] error
3911  *   Pointer to error structure.
3912  *
3913  * @return
3914  *   0 on success, a negative errno value otherwise and rte_errno is set.
3915  */
3916 static int
3917 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3918                                        const struct rte_flow_action *action,
3919                                        const uint64_t item_flags,
3920                                        struct rte_flow_error *error)
3921 {
3922         int ret = 0;
3923         uint64_t layer;
3924
3925         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3926         if (!ret) {
3927                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3928                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3929                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3930                 if (!(item_flags & layer))
3931                         return rte_flow_error_set(error, EINVAL,
3932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                   NULL, "no TCP item in"
3934                                                   " pattern");
3935                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3936                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3937                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3938                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3939                         return rte_flow_error_set(error, EINVAL,
3940                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3941                                                   NULL,
3942                                                   "cannot decrease and increase"
3943                                                   " TCP acknowledgment number"
3944                                                   " at the same time");
3945         }
3946         return ret;
3947 }
3948
3949 /**
3950  * Validate the modify-header TTL actions.
3951  *
3952  * @param[in] action_flags
3953  *   Holds the actions detected until now.
3954  * @param[in] action
3955  *   Pointer to the modify action.
3956  * @param[in] item_flags
3957  *   Holds the items detected.
3958  * @param[out] error
3959  *   Pointer to error structure.
3960  *
3961  * @return
3962  *   0 on success, a negative errno value otherwise and rte_errno is set.
3963  */
3964 static int
3965 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3966                                    const struct rte_flow_action *action,
3967                                    const uint64_t item_flags,
3968                                    struct rte_flow_error *error)
3969 {
3970         int ret = 0;
3971         uint64_t layer;
3972
3973         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3974         if (!ret) {
3975                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3976                                  MLX5_FLOW_LAYER_INNER_L3 :
3977                                  MLX5_FLOW_LAYER_OUTER_L3;
3978                 if (!(item_flags & layer))
3979                         return rte_flow_error_set(error, EINVAL,
3980                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3981                                                   NULL,
3982                                                   "no IP protocol in pattern");
3983         }
3984         return ret;
3985 }
3986
3987 /**
3988  * Validate jump action.
3989  *
3990  * @param[in] action
3991  *   Pointer to the jump action.
3992  * @param[in] action_flags
3993  *   Holds the actions detected until now.
3994  * @param[in] attributes
3995  *   Pointer to flow attributes
3996  * @param[in] external
3997  *   Action belongs to flow rule created by request external to PMD.
3998  * @param[out] error
3999  *   Pointer to error structure.
4000  *
4001  * @return
4002  *   0 on success, a negative errno value otherwise and rte_errno is set.
4003  */
4004 static int
4005 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4006                              const struct mlx5_flow_tunnel *tunnel,
4007                              const struct rte_flow_action *action,
4008                              uint64_t action_flags,
4009                              const struct rte_flow_attr *attributes,
4010                              bool external, struct rte_flow_error *error)
4011 {
4012         uint32_t target_group, table;
4013         int ret = 0;
4014         struct flow_grp_info grp_info = {
4015                 .external = !!external,
4016                 .transfer = !!attributes->transfer,
4017                 .fdb_def_rule = 1,
4018                 .std_tbl_fix = 0
4019         };
4020         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4021                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4022                 return rte_flow_error_set(error, EINVAL,
4023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4024                                           "can't have 2 fate actions in"
4025                                           " same flow");
4026         if (action_flags & MLX5_FLOW_ACTION_METER)
4027                 return rte_flow_error_set(error, ENOTSUP,
4028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4029                                           "jump with meter not support");
4030         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
4031                 return rte_flow_error_set(error, EINVAL,
4032                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4033                                           "E-Switch mirroring can't support"
4034                                           " Sample action and jump action in"
4035                                           " same flow now");
4036         if (!action->conf)
4037                 return rte_flow_error_set(error, EINVAL,
4038                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4039                                           NULL, "action configuration not set");
4040         target_group =
4041                 ((const struct rte_flow_action_jump *)action->conf)->group;
4042         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4043                                        &grp_info, error);
4044         if (ret)
4045                 return ret;
4046         if (attributes->group == target_group &&
4047             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4048                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4049                 return rte_flow_error_set(error, EINVAL,
4050                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4051                                           "target group must be other than"
4052                                           " the current flow group");
4053         return 0;
4054 }
4055
4056 /*
4057  * Validate the port_id action.
4058  *
4059  * @param[in] dev
4060  *   Pointer to rte_eth_dev structure.
4061  * @param[in] action_flags
4062  *   Bit-fields that holds the actions detected until now.
4063  * @param[in] action
4064  *   Port_id RTE action structure.
4065  * @param[in] attr
4066  *   Attributes of flow that includes this action.
4067  * @param[out] error
4068  *   Pointer to error structure.
4069  *
4070  * @return
4071  *   0 on success, a negative errno value otherwise and rte_errno is set.
4072  */
4073 static int
4074 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4075                                 uint64_t action_flags,
4076                                 const struct rte_flow_action *action,
4077                                 const struct rte_flow_attr *attr,
4078                                 struct rte_flow_error *error)
4079 {
4080         const struct rte_flow_action_port_id *port_id;
4081         struct mlx5_priv *act_priv;
4082         struct mlx5_priv *dev_priv;
4083         uint16_t port;
4084
4085         if (!attr->transfer)
4086                 return rte_flow_error_set(error, ENOTSUP,
4087                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4088                                           NULL,
4089                                           "port id action is valid in transfer"
4090                                           " mode only");
4091         if (!action || !action->conf)
4092                 return rte_flow_error_set(error, ENOTSUP,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4094                                           NULL,
4095                                           "port id action parameters must be"
4096                                           " specified");
4097         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4098                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4099                 return rte_flow_error_set(error, EINVAL,
4100                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4101                                           "can have only one fate actions in"
4102                                           " a flow");
4103         dev_priv = mlx5_dev_to_eswitch_info(dev);
4104         if (!dev_priv)
4105                 return rte_flow_error_set(error, rte_errno,
4106                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4107                                           NULL,
4108                                           "failed to obtain E-Switch info");
4109         port_id = action->conf;
4110         port = port_id->original ? dev->data->port_id : port_id->id;
4111         act_priv = mlx5_port_to_eswitch_info(port, false);
4112         if (!act_priv)
4113                 return rte_flow_error_set
4114                                 (error, rte_errno,
4115                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4116                                  "failed to obtain E-Switch port id for port");
4117         if (act_priv->domain_id != dev_priv->domain_id)
4118                 return rte_flow_error_set
4119                                 (error, EINVAL,
4120                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4121                                  "port does not belong to"
4122                                  " E-Switch being configured");
4123         return 0;
4124 }
4125
4126 /**
4127  * Get the maximum number of modify header actions.
4128  *
4129  * @param dev
4130  *   Pointer to rte_eth_dev structure.
4131  * @param flags
4132  *   Flags bits to check if root level.
4133  *
4134  * @return
4135  *   Max number of modify header actions device can support.
4136  */
4137 static inline unsigned int
4138 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4139                               uint64_t flags)
4140 {
4141         /*
4142          * There's no way to directly query the max capacity from FW.
4143          * The maximal value on root table should be assumed to be supported.
4144          */
4145         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4146                 return MLX5_MAX_MODIFY_NUM;
4147         else
4148                 return MLX5_ROOT_TBL_MODIFY_NUM;
4149 }
4150
4151 /**
4152  * Validate the meter action.
4153  *
4154  * @param[in] dev
4155  *   Pointer to rte_eth_dev structure.
4156  * @param[in] action_flags
4157  *   Bit-fields that holds the actions detected until now.
4158  * @param[in] action
4159  *   Pointer to the meter action.
4160  * @param[in] attr
4161  *   Attributes of flow that includes this action.
4162  * @param[out] error
4163  *   Pointer to error structure.
4164  *
4165  * @return
4166  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4167  */
4168 static int
4169 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4170                                 uint64_t action_flags,
4171                                 const struct rte_flow_action *action,
4172                                 const struct rte_flow_attr *attr,
4173                                 struct rte_flow_error *error)
4174 {
4175         struct mlx5_priv *priv = dev->data->dev_private;
4176         const struct rte_flow_action_meter *am = action->conf;
4177         struct mlx5_flow_meter *fm;
4178
4179         if (!am)
4180                 return rte_flow_error_set(error, EINVAL,
4181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182                                           "meter action conf is NULL");
4183
4184         if (action_flags & MLX5_FLOW_ACTION_METER)
4185                 return rte_flow_error_set(error, ENOTSUP,
4186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4187                                           "meter chaining not support");
4188         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4189                 return rte_flow_error_set(error, ENOTSUP,
4190                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4191                                           "meter with jump not support");
4192         if (!priv->mtr_en)
4193                 return rte_flow_error_set(error, ENOTSUP,
4194                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4195                                           NULL,
4196                                           "meter action not supported");
4197         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4198         if (!fm)
4199                 return rte_flow_error_set(error, EINVAL,
4200                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4201                                           "Meter not found");
4202         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4203               (!fm->ingress && !attr->ingress && attr->egress) ||
4204               (!fm->egress && !attr->egress && attr->ingress))))
4205                 return rte_flow_error_set(error, EINVAL,
4206                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4207                                           "Flow attributes are either invalid "
4208                                           "or have a conflict with current "
4209                                           "meter attributes");
4210         return 0;
4211 }
4212
4213 /**
4214  * Validate the age action.
4215  *
4216  * @param[in] action_flags
4217  *   Holds the actions detected until now.
4218  * @param[in] action
4219  *   Pointer to the age action.
4220  * @param[in] dev
4221  *   Pointer to the Ethernet device structure.
4222  * @param[out] error
4223  *   Pointer to error structure.
4224  *
4225  * @return
4226  *   0 on success, a negative errno value otherwise and rte_errno is set.
4227  */
4228 static int
4229 flow_dv_validate_action_age(uint64_t action_flags,
4230                             const struct rte_flow_action *action,
4231                             struct rte_eth_dev *dev,
4232                             struct rte_flow_error *error)
4233 {
4234         struct mlx5_priv *priv = dev->data->dev_private;
4235         const struct rte_flow_action_age *age = action->conf;
4236
4237         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4238             !priv->sh->aso_age_mng))
4239                 return rte_flow_error_set(error, ENOTSUP,
4240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4241                                           NULL,
4242                                           "age action not supported");
4243         if (!(action->conf))
4244                 return rte_flow_error_set(error, EINVAL,
4245                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4246                                           "configuration cannot be null");
4247         if (!(age->timeout))
4248                 return rte_flow_error_set(error, EINVAL,
4249                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4250                                           "invalid timeout value 0");
4251         if (action_flags & MLX5_FLOW_ACTION_AGE)
4252                 return rte_flow_error_set(error, EINVAL,
4253                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4254                                           "duplicate age actions set");
4255         return 0;
4256 }
4257
4258 /**
4259  * Validate the modify-header IPv4 DSCP actions.
4260  *
4261  * @param[in] action_flags
4262  *   Holds the actions detected until now.
4263  * @param[in] action
4264  *   Pointer to the modify action.
4265  * @param[in] item_flags
4266  *   Holds the items detected.
4267  * @param[out] error
4268  *   Pointer to error structure.
4269  *
4270  * @return
4271  *   0 on success, a negative errno value otherwise and rte_errno is set.
4272  */
4273 static int
4274 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4275                                          const struct rte_flow_action *action,
4276                                          const uint64_t item_flags,
4277                                          struct rte_flow_error *error)
4278 {
4279         int ret = 0;
4280
4281         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4282         if (!ret) {
4283                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4284                         return rte_flow_error_set(error, EINVAL,
4285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4286                                                   NULL,
4287                                                   "no ipv4 item in pattern");
4288         }
4289         return ret;
4290 }
4291
4292 /**
4293  * Validate the modify-header IPv6 DSCP actions.
4294  *
4295  * @param[in] action_flags
4296  *   Holds the actions detected until now.
4297  * @param[in] action
4298  *   Pointer to the modify action.
4299  * @param[in] item_flags
4300  *   Holds the items detected.
4301  * @param[out] error
4302  *   Pointer to error structure.
4303  *
4304  * @return
4305  *   0 on success, a negative errno value otherwise and rte_errno is set.
4306  */
4307 static int
4308 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4309                                          const struct rte_flow_action *action,
4310                                          const uint64_t item_flags,
4311                                          struct rte_flow_error *error)
4312 {
4313         int ret = 0;
4314
4315         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4316         if (!ret) {
4317                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4318                         return rte_flow_error_set(error, EINVAL,
4319                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4320                                                   NULL,
4321                                                   "no ipv6 item in pattern");
4322         }
4323         return ret;
4324 }
4325
4326 /**
4327  * Match modify-header resource.
4328  *
4329  * @param list
4330  *   Pointer to the hash list.
4331  * @param entry
4332  *   Pointer to exist resource entry object.
4333  * @param key
4334  *   Key of the new entry.
4335  * @param ctx
4336  *   Pointer to new modify-header resource.
4337  *
4338  * @return
4339  *   0 on matching, non-zero otherwise.
4340  */
4341 int
4342 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4343                         struct mlx5_hlist_entry *entry,
4344                         uint64_t key __rte_unused, void *cb_ctx)
4345 {
4346         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4347         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4348         struct mlx5_flow_dv_modify_hdr_resource *resource =
4349                         container_of(entry, typeof(*resource), entry);
4350         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4351
4352         key_len += ref->actions_num * sizeof(ref->actions[0]);
4353         return ref->actions_num != resource->actions_num ||
4354                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4355 }
4356
4357 struct mlx5_hlist_entry *
4358 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4359                          void *cb_ctx)
4360 {
4361         struct mlx5_dev_ctx_shared *sh = list->ctx;
4362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4363         struct mlx5dv_dr_domain *ns;
4364         struct mlx5_flow_dv_modify_hdr_resource *entry;
4365         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4366         int ret;
4367         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4368         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4369
4370         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4371                             SOCKET_ID_ANY);
4372         if (!entry) {
4373                 rte_flow_error_set(ctx->error, ENOMEM,
4374                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4375                                    "cannot allocate resource memory");
4376                 return NULL;
4377         }
4378         rte_memcpy(&entry->ft_type,
4379                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4380                    key_len + data_len);
4381         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4382                 ns = sh->fdb_domain;
4383         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4384                 ns = sh->tx_domain;
4385         else
4386                 ns = sh->rx_domain;
4387         ret = mlx5_flow_os_create_flow_action_modify_header
4388                                         (sh->ctx, ns, entry,
4389                                          data_len, &entry->action);
4390         if (ret) {
4391                 mlx5_free(entry);
4392                 rte_flow_error_set(ctx->error, ENOMEM,
4393                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4394                                    NULL, "cannot create modification action");
4395                 return NULL;
4396         }
4397         return &entry->entry;
4398 }
4399
4400 /**
4401  * Validate the sample action.
4402  *
4403  * @param[in] action_flags
4404  *   Holds the actions detected until now.
4405  * @param[in] action
4406  *   Pointer to the sample action.
4407  * @param[in] dev
4408  *   Pointer to the Ethernet device structure.
4409  * @param[in] attr
4410  *   Attributes of flow that includes this action.
4411  * @param[in] item_flags
4412  *   Holds the items detected.
4413  * @param[out] error
4414  *   Pointer to error structure.
4415  *
4416  * @return
4417  *   0 on success, a negative errno value otherwise and rte_errno is set.
4418  */
4419 static int
4420 flow_dv_validate_action_sample(uint64_t action_flags,
4421                                const struct rte_flow_action *action,
4422                                struct rte_eth_dev *dev,
4423                                const struct rte_flow_attr *attr,
4424                                const uint64_t item_flags,
4425                                struct rte_flow_error *error)
4426 {
4427         struct mlx5_priv *priv = dev->data->dev_private;
4428         struct mlx5_dev_config *dev_conf = &priv->config;
4429         const struct rte_flow_action_sample *sample = action->conf;
4430         const struct rte_flow_action *act;
4431         uint64_t sub_action_flags = 0;
4432         uint16_t queue_index = 0xFFFF;
4433         int actions_n = 0;
4434         int ret;
4435         fdb_mirror = 0;
4436
4437         if (!sample)
4438                 return rte_flow_error_set(error, EINVAL,
4439                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4440                                           "configuration cannot be NULL");
4441         if (sample->ratio == 0)
4442                 return rte_flow_error_set(error, EINVAL,
4443                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4444                                           "ratio value starts from 1");
4445         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446                 return rte_flow_error_set(error, ENOTSUP,
4447                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4448                                           NULL,
4449                                           "sample action not supported");
4450         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451                 return rte_flow_error_set(error, EINVAL,
4452                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453                                           "Multiple sample actions not "
4454                                           "supported");
4455         if (action_flags & MLX5_FLOW_ACTION_METER)
4456                 return rte_flow_error_set(error, EINVAL,
4457                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4458                                           "wrong action order, meter should "
4459                                           "be after sample action");
4460         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461                 return rte_flow_error_set(error, EINVAL,
4462                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4463                                           "wrong action order, jump should "
4464                                           "be after sample action");
4465         act = sample->actions;
4466         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468                         return rte_flow_error_set(error, ENOTSUP,
4469                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4470                                                   act, "too many actions");
4471                 switch (act->type) {
4472                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473                         ret = mlx5_flow_validate_action_queue(act,
4474                                                               sub_action_flags,
4475                                                               dev,
4476                                                               attr, error);
4477                         if (ret < 0)
4478                                 return ret;
4479                         queue_index = ((const struct rte_flow_action_queue *)
4480                                                         (act->conf))->index;
4481                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4482                         ++actions_n;
4483                         break;
4484                 case RTE_FLOW_ACTION_TYPE_MARK:
4485                         ret = flow_dv_validate_action_mark(dev, act,
4486                                                            sub_action_flags,
4487                                                            attr, error);
4488                         if (ret < 0)
4489                                 return ret;
4490                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4491                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4492                                                 MLX5_FLOW_ACTION_MARK_EXT;
4493                         else
4494                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4495                         ++actions_n;
4496                         break;
4497                 case RTE_FLOW_ACTION_TYPE_COUNT:
4498                         ret = flow_dv_validate_action_count(dev, error);
4499                         if (ret < 0)
4500                                 return ret;
4501                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4502                         ++actions_n;
4503                         break;
4504                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4505                         ret = flow_dv_validate_action_port_id(dev,
4506                                                               sub_action_flags,
4507                                                               act,
4508                                                               attr,
4509                                                               error);
4510                         if (ret)
4511                                 return ret;
4512                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4513                         ++actions_n;
4514                         break;
4515                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4516                         ret = flow_dv_validate_action_raw_encap_decap
4517                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4518                                  &actions_n, action, item_flags, error);
4519                         if (ret < 0)
4520                                 return ret;
4521                         ++actions_n;
4522                         break;
4523                 default:
4524                         return rte_flow_error_set(error, ENOTSUP,
4525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4526                                                   NULL,
4527                                                   "Doesn't support optional "
4528                                                   "action");
4529                 }
4530         }
4531         if (attr->ingress && !attr->transfer) {
4532                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4533                         return rte_flow_error_set(error, EINVAL,
4534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4535                                                   NULL,
4536                                                   "Ingress must has a dest "
4537                                                   "QUEUE for Sample");
4538         } else if (attr->egress && !attr->transfer) {
4539                 return rte_flow_error_set(error, ENOTSUP,
4540                                           RTE_FLOW_ERROR_TYPE_ACTION,
4541                                           NULL,
4542                                           "Sample Only support Ingress "
4543                                           "or E-Switch");
4544         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4545                 MLX5_ASSERT(attr->transfer);
4546                 if (sample->ratio > 1)
4547                         return rte_flow_error_set(error, ENOTSUP,
4548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4549                                                   NULL,
4550                                                   "E-Switch doesn't support "
4551                                                   "any optional action "
4552                                                   "for sampling");
4553                 fdb_mirror = 1;
4554                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4555                         return rte_flow_error_set(error, ENOTSUP,
4556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4557                                                   NULL,
4558                                                   "unsupported action QUEUE");
4559                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4560                         return rte_flow_error_set(error, EINVAL,
4561                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4562                                                   NULL,
4563                                                   "E-Switch must has a dest "
4564                                                   "port for mirroring");
4565         }
4566         /* Continue validation for Xcap actions.*/
4567         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4568             (queue_index == 0xFFFF ||
4569              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4570                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4571                      MLX5_FLOW_XCAP_ACTIONS)
4572                         return rte_flow_error_set(error, ENOTSUP,
4573                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4574                                                   NULL, "encap and decap "
4575                                                   "combination aren't "
4576                                                   "supported");
4577                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4578                                                         MLX5_FLOW_ACTION_ENCAP))
4579                         return rte_flow_error_set(error, ENOTSUP,
4580                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4581                                                   NULL, "encap is not supported"
4582                                                   " for ingress traffic");
4583         }
4584         return 0;
4585 }
4586
4587 /**
4588  * Find existing modify-header resource or create and register a new one.
4589  *
4590  * @param dev[in, out]
4591  *   Pointer to rte_eth_dev structure.
4592  * @param[in, out] resource
4593  *   Pointer to modify-header resource.
4594  * @parm[in, out] dev_flow
4595  *   Pointer to the dev_flow.
4596  * @param[out] error
4597  *   pointer to error structure.
4598  *
4599  * @return
4600  *   0 on success otherwise -errno and errno is set.
4601  */
4602 static int
4603 flow_dv_modify_hdr_resource_register
4604                         (struct rte_eth_dev *dev,
4605                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4606                          struct mlx5_flow *dev_flow,
4607                          struct rte_flow_error *error)
4608 {
4609         struct mlx5_priv *priv = dev->data->dev_private;
4610         struct mlx5_dev_ctx_shared *sh = priv->sh;
4611         uint32_t key_len = sizeof(*resource) -
4612                            offsetof(typeof(*resource), ft_type) +
4613                            resource->actions_num * sizeof(resource->actions[0]);
4614         struct mlx5_hlist_entry *entry;
4615         struct mlx5_flow_cb_ctx ctx = {
4616                 .error = error,
4617                 .data = resource,
4618         };
4619         uint64_t key64;
4620
4621         resource->flags = dev_flow->dv.group ? 0 :
4622                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4623         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4624                                     resource->flags))
4625                 return rte_flow_error_set(error, EOVERFLOW,
4626                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4627                                           "too many modify header items");
4628         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4629         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4630         if (!entry)
4631                 return -rte_errno;
4632         resource = container_of(entry, typeof(*resource), entry);
4633         dev_flow->handle->dvh.modify_hdr = resource;
4634         return 0;
4635 }
4636
4637 /**
4638  * Get DV flow counter by index.
4639  *
4640  * @param[in] dev
4641  *   Pointer to the Ethernet device structure.
4642  * @param[in] idx
4643  *   mlx5 flow counter index in the container.
4644  * @param[out] ppool
4645  *   mlx5 flow counter pool in the container,
4646  *
4647  * @return
4648  *   Pointer to the counter, NULL otherwise.
4649  */
4650 static struct mlx5_flow_counter *
4651 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4652                            uint32_t idx,
4653                            struct mlx5_flow_counter_pool **ppool)
4654 {
4655         struct mlx5_priv *priv = dev->data->dev_private;
4656         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4657         struct mlx5_flow_counter_pool *pool;
4658
4659         /* Decrease to original index and clear shared bit. */
4660         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4661         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4662         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4663         MLX5_ASSERT(pool);
4664         if (ppool)
4665                 *ppool = pool;
4666         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4667 }
4668
4669 /**
4670  * Check the devx counter belongs to the pool.
4671  *
4672  * @param[in] pool
4673  *   Pointer to the counter pool.
4674  * @param[in] id
4675  *   The counter devx ID.
4676  *
4677  * @return
4678  *   True if counter belongs to the pool, false otherwise.
4679  */
4680 static bool
4681 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4682 {
4683         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4684                    MLX5_COUNTERS_PER_POOL;
4685
4686         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4687                 return true;
4688         return false;
4689 }
4690
4691 /**
4692  * Get a pool by devx counter ID.
4693  *
4694  * @param[in] cmng
4695  *   Pointer to the counter management.
4696  * @param[in] id
4697  *   The counter devx ID.
4698  *
4699  * @return
4700  *   The counter pool pointer if exists, NULL otherwise,
4701  */
4702 static struct mlx5_flow_counter_pool *
4703 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4704 {
4705         uint32_t i;
4706         struct mlx5_flow_counter_pool *pool = NULL;
4707
4708         rte_spinlock_lock(&cmng->pool_update_sl);
4709         /* Check last used pool. */
4710         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4711             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4712                 pool = cmng->pools[cmng->last_pool_idx];
4713                 goto out;
4714         }
4715         /* ID out of range means no suitable pool in the container. */
4716         if (id > cmng->max_id || id < cmng->min_id)
4717                 goto out;
4718         /*
4719          * Find the pool from the end of the container, since mostly counter
4720          * ID is sequence increasing, and the last pool should be the needed
4721          * one.
4722          */
4723         i = cmng->n_valid;
4724         while (i--) {
4725                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4726
4727                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4728                         pool = pool_tmp;
4729                         break;
4730                 }
4731         }
4732 out:
4733         rte_spinlock_unlock(&cmng->pool_update_sl);
4734         return pool;
4735 }
4736
4737 /**
4738  * Resize a counter container.
4739  *
4740  * @param[in] dev
4741  *   Pointer to the Ethernet device structure.
4742  *
4743  * @return
4744  *   0 on success, otherwise negative errno value and rte_errno is set.
4745  */
4746 static int
4747 flow_dv_container_resize(struct rte_eth_dev *dev)
4748 {
4749         struct mlx5_priv *priv = dev->data->dev_private;
4750         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4751         void *old_pools = cmng->pools;
4752         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4753         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4754         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4755
4756         if (!pools) {
4757                 rte_errno = ENOMEM;
4758                 return -ENOMEM;
4759         }
4760         if (old_pools)
4761                 memcpy(pools, old_pools, cmng->n *
4762                                        sizeof(struct mlx5_flow_counter_pool *));
4763         cmng->n = resize;
4764         cmng->pools = pools;
4765         if (old_pools)
4766                 mlx5_free(old_pools);
4767         return 0;
4768 }
4769
4770 /**
4771  * Query a devx flow counter.
4772  *
4773  * @param[in] dev
4774  *   Pointer to the Ethernet device structure.
4775  * @param[in] cnt
4776  *   Index to the flow counter.
4777  * @param[out] pkts
4778  *   The statistics value of packets.
4779  * @param[out] bytes
4780  *   The statistics value of bytes.
4781  *
4782  * @return
4783  *   0 on success, otherwise a negative errno value and rte_errno is set.
4784  */
4785 static inline int
4786 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4787                      uint64_t *bytes)
4788 {
4789         struct mlx5_priv *priv = dev->data->dev_private;
4790         struct mlx5_flow_counter_pool *pool = NULL;
4791         struct mlx5_flow_counter *cnt;
4792         int offset;
4793
4794         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4795         MLX5_ASSERT(pool);
4796         if (priv->sh->cmng.counter_fallback)
4797                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4798                                         0, pkts, bytes, 0, NULL, NULL, 0);
4799         rte_spinlock_lock(&pool->sl);
4800         if (!pool->raw) {
4801                 *pkts = 0;
4802                 *bytes = 0;
4803         } else {
4804                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4805                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4806                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4807         }
4808         rte_spinlock_unlock(&pool->sl);
4809         return 0;
4810 }
4811
4812 /**
4813  * Create and initialize a new counter pool.
4814  *
4815  * @param[in] dev
4816  *   Pointer to the Ethernet device structure.
4817  * @param[out] dcs
4818  *   The devX counter handle.
4819  * @param[in] age
4820  *   Whether the pool is for counter that was allocated for aging.
4821  * @param[in/out] cont_cur
4822  *   Pointer to the container pointer, it will be update in pool resize.
4823  *
4824  * @return
4825  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4826  */
4827 static struct mlx5_flow_counter_pool *
4828 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4829                     uint32_t age)
4830 {
4831         struct mlx5_priv *priv = dev->data->dev_private;
4832         struct mlx5_flow_counter_pool *pool;
4833         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4834         bool fallback = priv->sh->cmng.counter_fallback;
4835         uint32_t size = sizeof(*pool);
4836
4837         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4838         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4839         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4840         if (!pool) {
4841                 rte_errno = ENOMEM;
4842                 return NULL;
4843         }
4844         pool->raw = NULL;
4845         pool->is_aged = !!age;
4846         pool->query_gen = 0;
4847         pool->min_dcs = dcs;
4848         rte_spinlock_init(&pool->sl);
4849         rte_spinlock_init(&pool->csl);
4850         TAILQ_INIT(&pool->counters[0]);
4851         TAILQ_INIT(&pool->counters[1]);
4852         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4853         rte_spinlock_lock(&cmng->pool_update_sl);
4854         pool->index = cmng->n_valid;
4855         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4856                 mlx5_free(pool);
4857                 rte_spinlock_unlock(&cmng->pool_update_sl);
4858                 return NULL;
4859         }
4860         cmng->pools[pool->index] = pool;
4861         cmng->n_valid++;
4862         if (unlikely(fallback)) {
4863                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4864
4865                 if (base < cmng->min_id)
4866                         cmng->min_id = base;
4867                 if (base > cmng->max_id)
4868                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4869                 cmng->last_pool_idx = pool->index;
4870         }
4871         rte_spinlock_unlock(&cmng->pool_update_sl);
4872         return pool;
4873 }
4874
4875 /**
4876  * Prepare a new counter and/or a new counter pool.
4877  *
4878  * @param[in] dev
4879  *   Pointer to the Ethernet device structure.
4880  * @param[out] cnt_free
4881  *   Where to put the pointer of a new counter.
4882  * @param[in] age
4883  *   Whether the pool is for counter that was allocated for aging.
4884  *
4885  * @return
4886  *   The counter pool pointer and @p cnt_free is set on success,
4887  *   NULL otherwise and rte_errno is set.
4888  */
4889 static struct mlx5_flow_counter_pool *
4890 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4891                              struct mlx5_flow_counter **cnt_free,
4892                              uint32_t age)
4893 {
4894         struct mlx5_priv *priv = dev->data->dev_private;
4895         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4896         struct mlx5_flow_counter_pool *pool;
4897         struct mlx5_counters tmp_tq;
4898         struct mlx5_devx_obj *dcs = NULL;
4899         struct mlx5_flow_counter *cnt;
4900         enum mlx5_counter_type cnt_type =
4901                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4902         bool fallback = priv->sh->cmng.counter_fallback;
4903         uint32_t i;
4904
4905         if (fallback) {
4906                 /* bulk_bitmap must be 0 for single counter allocation. */
4907                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4908                 if (!dcs)
4909                         return NULL;
4910                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4911                 if (!pool) {
4912                         pool = flow_dv_pool_create(dev, dcs, age);
4913                         if (!pool) {
4914                                 mlx5_devx_cmd_destroy(dcs);
4915                                 return NULL;
4916                         }
4917                 }
4918                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4919                 cnt = MLX5_POOL_GET_CNT(pool, i);
4920                 cnt->pool = pool;
4921                 cnt->dcs_when_free = dcs;
4922                 *cnt_free = cnt;
4923                 return pool;
4924         }
4925         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4926         if (!dcs) {
4927                 rte_errno = ENODATA;
4928                 return NULL;
4929         }
4930         pool = flow_dv_pool_create(dev, dcs, age);
4931         if (!pool) {
4932                 mlx5_devx_cmd_destroy(dcs);
4933                 return NULL;
4934         }
4935         TAILQ_INIT(&tmp_tq);
4936         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4937                 cnt = MLX5_POOL_GET_CNT(pool, i);
4938                 cnt->pool = pool;
4939                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4940         }
4941         rte_spinlock_lock(&cmng->csl[cnt_type]);
4942         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4943         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4944         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4945         (*cnt_free)->pool = pool;
4946         return pool;
4947 }
4948
4949 /**
4950  * Allocate a flow counter.
4951  *
4952  * @param[in] dev
4953  *   Pointer to the Ethernet device structure.
4954  * @param[in] age
4955  *   Whether the counter was allocated for aging.
4956  *
4957  * @return
4958  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4959  */
4960 static uint32_t
4961 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4962 {
4963         struct mlx5_priv *priv = dev->data->dev_private;
4964         struct mlx5_flow_counter_pool *pool = NULL;
4965         struct mlx5_flow_counter *cnt_free = NULL;
4966         bool fallback = priv->sh->cmng.counter_fallback;
4967         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4968         enum mlx5_counter_type cnt_type =
4969                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4970         uint32_t cnt_idx;
4971
4972         if (!priv->config.devx) {
4973                 rte_errno = ENOTSUP;
4974                 return 0;
4975         }
4976         /* Get free counters from container. */
4977         rte_spinlock_lock(&cmng->csl[cnt_type]);
4978         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4979         if (cnt_free)
4980                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4981         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4982         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4983                 goto err;
4984         pool = cnt_free->pool;
4985         if (fallback)
4986                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4987         /* Create a DV counter action only in the first time usage. */
4988         if (!cnt_free->action) {
4989                 uint16_t offset;
4990                 struct mlx5_devx_obj *dcs;
4991                 int ret;
4992
4993                 if (!fallback) {
4994                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4995                         dcs = pool->min_dcs;
4996                 } else {
4997                         offset = 0;
4998                         dcs = cnt_free->dcs_when_free;
4999                 }
5000                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5001                                                             &cnt_free->action);
5002                 if (ret) {
5003                         rte_errno = errno;
5004                         goto err;
5005                 }
5006         }
5007         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5008                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5009         /* Update the counter reset values. */
5010         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5011                                  &cnt_free->bytes))
5012                 goto err;
5013         if (!fallback && !priv->sh->cmng.query_thread_on)
5014                 /* Start the asynchronous batch query by the host thread. */
5015                 mlx5_set_query_alarm(priv->sh);
5016         return cnt_idx;
5017 err:
5018         if (cnt_free) {
5019                 cnt_free->pool = pool;
5020                 if (fallback)
5021                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5022                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5023                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5024                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5025         }
5026         return 0;
5027 }
5028
5029 /**
5030  * Allocate a shared flow counter.
5031  *
5032  * @param[in] ctx
5033  *   Pointer to the shared counter configuration.
5034  * @param[in] data
5035  *   Pointer to save the allocated counter index.
5036  *
5037  * @return
5038  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5039  */
5040
5041 static int32_t
5042 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5043 {
5044         struct mlx5_shared_counter_conf *conf = ctx;
5045         struct rte_eth_dev *dev = conf->dev;
5046         struct mlx5_flow_counter *cnt;
5047
5048         data->dword = flow_dv_counter_alloc(dev, 0);
5049         data->dword |= MLX5_CNT_SHARED_OFFSET;
5050         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5051         cnt->shared_info.id = conf->id;
5052         return 0;
5053 }
5054
5055 /**
5056  * Get a shared flow counter.
5057  *
5058  * @param[in] dev
5059  *   Pointer to the Ethernet device structure.
5060  * @param[in] id
5061  *   Counter identifier.
5062  *
5063  * @return
5064  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5065  */
5066 static uint32_t
5067 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5068 {
5069         struct mlx5_priv *priv = dev->data->dev_private;
5070         struct mlx5_shared_counter_conf conf = {
5071                 .dev = dev,
5072                 .id = id,
5073         };
5074         union mlx5_l3t_data data = {
5075                 .dword = 0,
5076         };
5077
5078         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5079                                flow_dv_counter_alloc_shared_cb, &conf);
5080         return data.dword;
5081 }
5082
5083 /**
5084  * Get age param from counter index.
5085  *
5086  * @param[in] dev
5087  *   Pointer to the Ethernet device structure.
5088  * @param[in] counter
5089  *   Index to the counter handler.
5090  *
5091  * @return
5092  *   The aging parameter specified for the counter index.
5093  */
5094 static struct mlx5_age_param*
5095 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5096                                 uint32_t counter)
5097 {
5098         struct mlx5_flow_counter *cnt;
5099         struct mlx5_flow_counter_pool *pool = NULL;
5100
5101         flow_dv_counter_get_by_idx(dev, counter, &pool);
5102         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5103         cnt = MLX5_POOL_GET_CNT(pool, counter);
5104         return MLX5_CNT_TO_AGE(cnt);
5105 }
5106
5107 /**
5108  * Remove a flow counter from aged counter list.
5109  *
5110  * @param[in] dev
5111  *   Pointer to the Ethernet device structure.
5112  * @param[in] counter
5113  *   Index to the counter handler.
5114  * @param[in] cnt
5115  *   Pointer to the counter handler.
5116  */
5117 static void
5118 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5119                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5120 {
5121         struct mlx5_age_info *age_info;
5122         struct mlx5_age_param *age_param;
5123         struct mlx5_priv *priv = dev->data->dev_private;
5124         uint16_t expected = AGE_CANDIDATE;
5125
5126         age_info = GET_PORT_AGE_INFO(priv);
5127         age_param = flow_dv_counter_idx_get_age(dev, counter);
5128         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5129                                          AGE_FREE, false, __ATOMIC_RELAXED,
5130                                          __ATOMIC_RELAXED)) {
5131                 /**
5132                  * We need the lock even it is age timeout,
5133                  * since counter may still in process.
5134                  */
5135                 rte_spinlock_lock(&age_info->aged_sl);
5136                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5137                 rte_spinlock_unlock(&age_info->aged_sl);
5138                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5139         }
5140 }
5141
5142 /**
5143  * Release a flow counter.
5144  *
5145  * @param[in] dev
5146  *   Pointer to the Ethernet device structure.
5147  * @param[in] counter
5148  *   Index to the counter handler.
5149  */
5150 static void
5151 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5152 {
5153         struct mlx5_priv *priv = dev->data->dev_private;
5154         struct mlx5_flow_counter_pool *pool = NULL;
5155         struct mlx5_flow_counter *cnt;
5156         enum mlx5_counter_type cnt_type;
5157
5158         if (!counter)
5159                 return;
5160         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5161         MLX5_ASSERT(pool);
5162         if (IS_SHARED_CNT(counter) &&
5163             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5164                 return;
5165         if (pool->is_aged)
5166                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5167         cnt->pool = pool;
5168         /*
5169          * Put the counter back to list to be updated in none fallback mode.
5170          * Currently, we are using two list alternately, while one is in query,
5171          * add the freed counter to the other list based on the pool query_gen
5172          * value. After query finishes, add counter the list to the global
5173          * container counter list. The list changes while query starts. In
5174          * this case, lock will not be needed as query callback and release
5175          * function both operate with the different list.
5176          *
5177          */
5178         if (!priv->sh->cmng.counter_fallback) {
5179                 rte_spinlock_lock(&pool->csl);
5180                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5181                 rte_spinlock_unlock(&pool->csl);
5182         } else {
5183                 cnt->dcs_when_free = cnt->dcs_when_active;
5184                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5185                                            MLX5_COUNTER_TYPE_ORIGIN;
5186                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5187                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5188                                   cnt, next);
5189                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5190         }
5191 }
5192
5193 /**
5194  * Verify the @p attributes will be correctly understood by the NIC and store
5195  * them in the @p flow if everything is correct.
5196  *
5197  * @param[in] dev
5198  *   Pointer to dev struct.
5199  * @param[in] attributes
5200  *   Pointer to flow attributes
5201  * @param[in] external
5202  *   This flow rule is created by request external to PMD.
5203  * @param[out] error
5204  *   Pointer to error structure.
5205  *
5206  * @return
5207  *   - 0 on success and non root table.
5208  *   - 1 on success and root table.
5209  *   - a negative errno value otherwise and rte_errno is set.
5210  */
5211 static int
5212 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5213                             const struct mlx5_flow_tunnel *tunnel,
5214                             const struct rte_flow_attr *attributes,
5215                             const struct flow_grp_info *grp_info,
5216                             struct rte_flow_error *error)
5217 {
5218         struct mlx5_priv *priv = dev->data->dev_private;
5219         uint32_t priority_max = priv->config.flow_prio - 1;
5220         int ret = 0;
5221
5222 #ifndef HAVE_MLX5DV_DR
5223         RTE_SET_USED(tunnel);
5224         RTE_SET_USED(grp_info);
5225         if (attributes->group)
5226                 return rte_flow_error_set(error, ENOTSUP,
5227                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5228                                           NULL,
5229                                           "groups are not supported");
5230 #else
5231         uint32_t table = 0;
5232
5233         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5234                                        grp_info, error);
5235         if (ret)
5236                 return ret;
5237         if (!table)
5238                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5239 #endif
5240         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5241             attributes->priority >= priority_max)
5242                 return rte_flow_error_set(error, ENOTSUP,
5243                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5244                                           NULL,
5245                                           "priority out of range");
5246         if (attributes->transfer) {
5247                 if (!priv->config.dv_esw_en)
5248                         return rte_flow_error_set
5249                                 (error, ENOTSUP,
5250                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5251                                  "E-Switch dr is not supported");
5252                 if (!(priv->representor || priv->master))
5253                         return rte_flow_error_set
5254                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5255                                  NULL, "E-Switch configuration can only be"
5256                                  " done by a master or a representor device");
5257                 if (attributes->egress)
5258                         return rte_flow_error_set
5259                                 (error, ENOTSUP,
5260                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5261                                  "egress is not supported");
5262         }
5263         if (!(attributes->egress ^ attributes->ingress))
5264                 return rte_flow_error_set(error, ENOTSUP,
5265                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5266                                           "must specify exactly one of "
5267                                           "ingress or egress");
5268         return ret;
5269 }
5270
5271 /**
5272  * Internal validation function. For validating both actions and items.
5273  *
5274  * @param[in] dev
5275  *   Pointer to the rte_eth_dev structure.
5276  * @param[in] attr
5277  *   Pointer to the flow attributes.
5278  * @param[in] items
5279  *   Pointer to the list of items.
5280  * @param[in] actions
5281  *   Pointer to the list of actions.
5282  * @param[in] external
5283  *   This flow rule is created by request external to PMD.
5284  * @param[in] hairpin
5285  *   Number of hairpin TX actions, 0 means classic flow.
5286  * @param[out] error
5287  *   Pointer to the error structure.
5288  *
5289  * @return
5290  *   0 on success, a negative errno value otherwise and rte_errno is set.
5291  */
5292 static int
5293 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5294                  const struct rte_flow_item items[],
5295                  const struct rte_flow_action actions[],
5296                  bool external, int hairpin, struct rte_flow_error *error)
5297 {
5298         int ret;
5299         uint64_t action_flags = 0;
5300         uint64_t item_flags = 0;
5301         uint64_t last_item = 0;
5302         uint8_t next_protocol = 0xff;
5303         uint16_t ether_type = 0;
5304         int actions_n = 0;
5305         uint8_t item_ipv6_proto = 0;
5306         const struct rte_flow_item *geneve_item = NULL;
5307         const struct rte_flow_item *gre_item = NULL;
5308         const struct rte_flow_item *gtp_item = NULL;
5309         const struct rte_flow_action_raw_decap *decap;
5310         const struct rte_flow_action_raw_encap *encap;
5311         const struct rte_flow_action_rss *rss;
5312         const struct rte_flow_item_tcp nic_tcp_mask = {
5313                 .hdr = {
5314                         .tcp_flags = 0xFF,
5315                         .src_port = RTE_BE16(UINT16_MAX),
5316                         .dst_port = RTE_BE16(UINT16_MAX),
5317                 }
5318         };
5319         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5320                 .hdr = {
5321                         .src_addr =
5322                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5323                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5324                         .dst_addr =
5325                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5326                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5327                         .vtc_flow = RTE_BE32(0xffffffff),
5328                         .proto = 0xff,
5329                         .hop_limits = 0xff,
5330                 },
5331                 .has_frag_ext = 1,
5332         };
5333         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5334                 .hdr = {
5335                         .common = {
5336                                 .u32 =
5337                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5338                                         .type = 0xFF,
5339                                         }).u32),
5340                         },
5341                         .dummy[0] = 0xffffffff,
5342                 },
5343         };
5344         struct mlx5_priv *priv = dev->data->dev_private;
5345         struct mlx5_dev_config *dev_conf = &priv->config;
5346         uint16_t queue_index = 0xFFFF;
5347         const struct rte_flow_item_vlan *vlan_m = NULL;
5348         int16_t rw_act_num = 0;
5349         uint64_t is_root;
5350         const struct mlx5_flow_tunnel *tunnel;
5351         struct flow_grp_info grp_info = {
5352                 .external = !!external,
5353                 .transfer = !!attr->transfer,
5354                 .fdb_def_rule = !!priv->fdb_def_rule,
5355         };
5356         const struct rte_eth_hairpin_conf *conf;
5357
5358         if (items == NULL)
5359                 return -1;
5360         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5361                 tunnel = flow_items_to_tunnel(items);
5362                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5363                                 MLX5_FLOW_ACTION_DECAP;
5364         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5365                 tunnel = flow_actions_to_tunnel(actions);
5366                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5367         } else {
5368                 tunnel = NULL;
5369         }
5370         if (tunnel && priv->representor)
5371                 return rte_flow_error_set(error, ENOTSUP,
5372                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5373                                           "decap not supported "
5374                                           "for VF representor");
5375         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5376                                 (dev, tunnel, attr, items, actions);
5377         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5378         if (ret < 0)
5379                 return ret;
5380         is_root = (uint64_t)ret;
5381         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5382                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5383                 int type = items->type;
5384
5385                 if (!mlx5_flow_os_item_supported(type))
5386                         return rte_flow_error_set(error, ENOTSUP,
5387                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5388                                                   NULL, "item not supported");
5389                 switch (type) {
5390                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5391                         if (items[0].type != (typeof(items[0].type))
5392                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5393                                 return rte_flow_error_set
5394                                                 (error, EINVAL,
5395                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5396                                                 NULL, "MLX5 private items "
5397                                                 "must be the first");
5398                         break;
5399                 case RTE_FLOW_ITEM_TYPE_VOID:
5400                         break;
5401                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5402                         ret = flow_dv_validate_item_port_id
5403                                         (dev, items, attr, item_flags, error);
5404                         if (ret < 0)
5405                                 return ret;
5406                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5407                         break;
5408                 case RTE_FLOW_ITEM_TYPE_ETH:
5409                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5410                                                           true, error);
5411                         if (ret < 0)
5412                                 return ret;
5413                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5414                                              MLX5_FLOW_LAYER_OUTER_L2;
5415                         if (items->mask != NULL && items->spec != NULL) {
5416                                 ether_type =
5417                                         ((const struct rte_flow_item_eth *)
5418                                          items->spec)->type;
5419                                 ether_type &=
5420                                         ((const struct rte_flow_item_eth *)
5421                                          items->mask)->type;
5422                                 ether_type = rte_be_to_cpu_16(ether_type);
5423                         } else {
5424                                 ether_type = 0;
5425                         }
5426                         break;
5427                 case RTE_FLOW_ITEM_TYPE_VLAN:
5428                         ret = flow_dv_validate_item_vlan(items, item_flags,
5429                                                          dev, error);
5430                         if (ret < 0)
5431                                 return ret;
5432                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5433                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5434                         if (items->mask != NULL && items->spec != NULL) {
5435                                 ether_type =
5436                                         ((const struct rte_flow_item_vlan *)
5437                                          items->spec)->inner_type;
5438                                 ether_type &=
5439                                         ((const struct rte_flow_item_vlan *)
5440                                          items->mask)->inner_type;
5441                                 ether_type = rte_be_to_cpu_16(ether_type);
5442                         } else {
5443                                 ether_type = 0;
5444                         }
5445                         /* Store outer VLAN mask for of_push_vlan action. */
5446                         if (!tunnel)
5447                                 vlan_m = items->mask;
5448                         break;
5449                 case RTE_FLOW_ITEM_TYPE_IPV4:
5450                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5451                                                   &item_flags, &tunnel);
5452                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5453                                                          last_item, ether_type,
5454                                                          error);
5455                         if (ret < 0)
5456                                 return ret;
5457                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5458                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5459                         if (items->mask != NULL &&
5460                             ((const struct rte_flow_item_ipv4 *)
5461                              items->mask)->hdr.next_proto_id) {
5462                                 next_protocol =
5463                                         ((const struct rte_flow_item_ipv4 *)
5464                                          (items->spec))->hdr.next_proto_id;
5465                                 next_protocol &=
5466                                         ((const struct rte_flow_item_ipv4 *)
5467                                          (items->mask))->hdr.next_proto_id;
5468                         } else {
5469                                 /* Reset for inner layer. */
5470                                 next_protocol = 0xff;
5471                         }
5472                         break;
5473                 case RTE_FLOW_ITEM_TYPE_IPV6:
5474                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5475                                                   &item_flags, &tunnel);
5476                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5477                                                            last_item,
5478                                                            ether_type,
5479                                                            &nic_ipv6_mask,
5480                                                            error);
5481                         if (ret < 0)
5482                                 return ret;
5483                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5484                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5485                         if (items->mask != NULL &&
5486                             ((const struct rte_flow_item_ipv6 *)
5487                              items->mask)->hdr.proto) {
5488                                 item_ipv6_proto =
5489                                         ((const struct rte_flow_item_ipv6 *)
5490                                          items->spec)->hdr.proto;
5491                                 next_protocol =
5492                                         ((const struct rte_flow_item_ipv6 *)
5493                                          items->spec)->hdr.proto;
5494                                 next_protocol &=
5495                                         ((const struct rte_flow_item_ipv6 *)
5496                                          items->mask)->hdr.proto;
5497                         } else {
5498                                 /* Reset for inner layer. */
5499                                 next_protocol = 0xff;
5500                         }
5501                         break;
5502                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5503                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5504                                                                   item_flags,
5505                                                                   error);
5506                         if (ret < 0)
5507                                 return ret;
5508                         last_item = tunnel ?
5509                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5510                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5511                         if (items->mask != NULL &&
5512                             ((const struct rte_flow_item_ipv6_frag_ext *)
5513                              items->mask)->hdr.next_header) {
5514                                 next_protocol =
5515                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5516                                  items->spec)->hdr.next_header;
5517                                 next_protocol &=
5518                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5519                                  items->mask)->hdr.next_header;
5520                         } else {
5521                                 /* Reset for inner layer. */
5522                                 next_protocol = 0xff;
5523                         }
5524                         break;
5525                 case RTE_FLOW_ITEM_TYPE_TCP:
5526                         ret = mlx5_flow_validate_item_tcp
5527                                                 (items, item_flags,
5528                                                  next_protocol,
5529                                                  &nic_tcp_mask,
5530                                                  error);
5531                         if (ret < 0)
5532                                 return ret;
5533                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5534                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5535                         break;
5536                 case RTE_FLOW_ITEM_TYPE_UDP:
5537                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5538                                                           next_protocol,
5539                                                           error);
5540                         if (ret < 0)
5541                                 return ret;
5542                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5543                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5544                         break;
5545                 case RTE_FLOW_ITEM_TYPE_GRE:
5546                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5547                                                           next_protocol, error);
5548                         if (ret < 0)
5549                                 return ret;
5550                         gre_item = items;
5551                         last_item = MLX5_FLOW_LAYER_GRE;
5552                         break;
5553                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5554                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5555                                                             next_protocol,
5556                                                             error);
5557                         if (ret < 0)
5558                                 return ret;
5559                         last_item = MLX5_FLOW_LAYER_NVGRE;
5560                         break;
5561                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5562                         ret = mlx5_flow_validate_item_gre_key
5563                                 (items, item_flags, gre_item, error);
5564                         if (ret < 0)
5565                                 return ret;
5566                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5567                         break;
5568                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5569                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5570                                                             error);
5571                         if (ret < 0)
5572                                 return ret;
5573                         last_item = MLX5_FLOW_LAYER_VXLAN;
5574                         break;
5575                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5576                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5577                                                                 item_flags, dev,
5578                                                                 error);
5579                         if (ret < 0)
5580                                 return ret;
5581                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5582                         break;
5583                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5584                         ret = mlx5_flow_validate_item_geneve(items,
5585                                                              item_flags, dev,
5586                                                              error);
5587                         if (ret < 0)
5588                                 return ret;
5589                         geneve_item = items;
5590                         last_item = MLX5_FLOW_LAYER_GENEVE;
5591                         break;
5592                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5593                         ret = mlx5_flow_validate_item_geneve_opt(items,
5594                                                                  last_item,
5595                                                                  geneve_item,
5596                                                                  dev,
5597                                                                  error);
5598                         if (ret < 0)
5599                                 return ret;
5600                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5601                         break;
5602                 case RTE_FLOW_ITEM_TYPE_MPLS:
5603                         ret = mlx5_flow_validate_item_mpls(dev, items,
5604                                                            item_flags,
5605                                                            last_item, error);
5606                         if (ret < 0)
5607                                 return ret;
5608                         last_item = MLX5_FLOW_LAYER_MPLS;
5609                         break;
5610
5611                 case RTE_FLOW_ITEM_TYPE_MARK:
5612                         ret = flow_dv_validate_item_mark(dev, items, attr,
5613                                                          error);
5614                         if (ret < 0)
5615                                 return ret;
5616                         last_item = MLX5_FLOW_ITEM_MARK;
5617                         break;
5618                 case RTE_FLOW_ITEM_TYPE_META:
5619                         ret = flow_dv_validate_item_meta(dev, items, attr,
5620                                                          error);
5621                         if (ret < 0)
5622                                 return ret;
5623                         last_item = MLX5_FLOW_ITEM_METADATA;
5624                         break;
5625                 case RTE_FLOW_ITEM_TYPE_ICMP:
5626                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5627                                                            next_protocol,
5628                                                            error);
5629                         if (ret < 0)
5630                                 return ret;
5631                         last_item = MLX5_FLOW_LAYER_ICMP;
5632                         break;
5633                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5634                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5635                                                             next_protocol,
5636                                                             error);
5637                         if (ret < 0)
5638                                 return ret;
5639                         item_ipv6_proto = IPPROTO_ICMPV6;
5640                         last_item = MLX5_FLOW_LAYER_ICMP6;
5641                         break;
5642                 case RTE_FLOW_ITEM_TYPE_TAG:
5643                         ret = flow_dv_validate_item_tag(dev, items,
5644                                                         attr, error);
5645                         if (ret < 0)
5646                                 return ret;
5647                         last_item = MLX5_FLOW_ITEM_TAG;
5648                         break;
5649                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5650                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5651                         break;
5652                 case RTE_FLOW_ITEM_TYPE_GTP:
5653                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5654                                                         error);
5655                         if (ret < 0)
5656                                 return ret;
5657                         gtp_item = items;
5658                         last_item = MLX5_FLOW_LAYER_GTP;
5659                         break;
5660                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5661                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
5662                                                             gtp_item, attr,
5663                                                             error);
5664                         if (ret < 0)
5665                                 return ret;
5666                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
5667                         break;
5668                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5669                         /* Capacity will be checked in the translate stage. */
5670                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5671                                                             last_item,
5672                                                             ether_type,
5673                                                             &nic_ecpri_mask,
5674                                                             error);
5675                         if (ret < 0)
5676                                 return ret;
5677                         last_item = MLX5_FLOW_LAYER_ECPRI;
5678                         break;
5679                 default:
5680                         return rte_flow_error_set(error, ENOTSUP,
5681                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5682                                                   NULL, "item not supported");
5683                 }
5684                 item_flags |= last_item;
5685         }
5686         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5687                 int type = actions->type;
5688
5689                 if (!mlx5_flow_os_action_supported(type))
5690                         return rte_flow_error_set(error, ENOTSUP,
5691                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5692                                                   actions,
5693                                                   "action not supported");
5694                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5695                         return rte_flow_error_set(error, ENOTSUP,
5696                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5697                                                   actions, "too many actions");
5698                 switch (type) {
5699                 case RTE_FLOW_ACTION_TYPE_VOID:
5700                         break;
5701                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5702                         ret = flow_dv_validate_action_port_id(dev,
5703                                                               action_flags,
5704                                                               actions,
5705                                                               attr,
5706                                                               error);
5707                         if (ret)
5708                                 return ret;
5709                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5710                         ++actions_n;
5711                         break;
5712                 case RTE_FLOW_ACTION_TYPE_FLAG:
5713                         ret = flow_dv_validate_action_flag(dev, action_flags,
5714                                                            attr, error);
5715                         if (ret < 0)
5716                                 return ret;
5717                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5718                                 /* Count all modify-header actions as one. */
5719                                 if (!(action_flags &
5720                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5721                                         ++actions_n;
5722                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5723                                                 MLX5_FLOW_ACTION_MARK_EXT;
5724                         } else {
5725                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5726                                 ++actions_n;
5727                         }
5728                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5729                         break;
5730                 case RTE_FLOW_ACTION_TYPE_MARK:
5731                         ret = flow_dv_validate_action_mark(dev, actions,
5732                                                            action_flags,
5733                                                            attr, error);
5734                         if (ret < 0)
5735                                 return ret;
5736                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5737                                 /* Count all modify-header actions as one. */
5738                                 if (!(action_flags &
5739                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5740                                         ++actions_n;
5741                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5742                                                 MLX5_FLOW_ACTION_MARK_EXT;
5743                         } else {
5744                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5745                                 ++actions_n;
5746                         }
5747                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5748                         break;
5749                 case RTE_FLOW_ACTION_TYPE_SET_META:
5750                         ret = flow_dv_validate_action_set_meta(dev, actions,
5751                                                                action_flags,
5752                                                                attr, error);
5753                         if (ret < 0)
5754                                 return ret;
5755                         /* Count all modify-header actions as one action. */
5756                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5757                                 ++actions_n;
5758                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5759                         rw_act_num += MLX5_ACT_NUM_SET_META;
5760                         break;
5761                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5762                         ret = flow_dv_validate_action_set_tag(dev, actions,
5763                                                               action_flags,
5764                                                               attr, error);
5765                         if (ret < 0)
5766                                 return ret;
5767                         /* Count all modify-header actions as one action. */
5768                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5769                                 ++actions_n;
5770                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5771                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5772                         break;
5773                 case RTE_FLOW_ACTION_TYPE_DROP:
5774                         ret = mlx5_flow_validate_action_drop(action_flags,
5775                                                              attr, error);
5776                         if (ret < 0)
5777                                 return ret;
5778                         action_flags |= MLX5_FLOW_ACTION_DROP;
5779                         ++actions_n;
5780                         break;
5781                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5782                         ret = mlx5_flow_validate_action_queue(actions,
5783                                                               action_flags, dev,
5784                                                               attr, error);
5785                         if (ret < 0)
5786                                 return ret;
5787                         queue_index = ((const struct rte_flow_action_queue *)
5788                                                         (actions->conf))->index;
5789                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5790                         ++actions_n;
5791                         break;
5792                 case RTE_FLOW_ACTION_TYPE_RSS:
5793                         rss = actions->conf;
5794                         ret = mlx5_flow_validate_action_rss(actions,
5795                                                             action_flags, dev,
5796                                                             attr, item_flags,
5797                                                             error);
5798                         if (ret < 0)
5799                                 return ret;
5800                         if (rss != NULL && rss->queue_num)
5801                                 queue_index = rss->queue[0];
5802                         action_flags |= MLX5_FLOW_ACTION_RSS;
5803                         ++actions_n;
5804                         break;
5805                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5806                         ret =
5807                         mlx5_flow_validate_action_default_miss(action_flags,
5808                                         attr, error);
5809                         if (ret < 0)
5810                                 return ret;
5811                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5812                         ++actions_n;
5813                         break;
5814                 case RTE_FLOW_ACTION_TYPE_COUNT:
5815                         ret = flow_dv_validate_action_count(dev, error);
5816                         if (ret < 0)
5817                                 return ret;
5818                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5819                         ++actions_n;
5820                         break;
5821                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5822                         if (flow_dv_validate_action_pop_vlan(dev,
5823                                                              action_flags,
5824                                                              actions,
5825                                                              item_flags, attr,
5826                                                              error))
5827                                 return -rte_errno;
5828                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5829                         ++actions_n;
5830                         break;
5831                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5832                         ret = flow_dv_validate_action_push_vlan(dev,
5833                                                                 action_flags,
5834                                                                 vlan_m,
5835                                                                 actions, attr,
5836                                                                 error);
5837                         if (ret < 0)
5838                                 return ret;
5839                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5840                         ++actions_n;
5841                         break;
5842                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5843                         ret = flow_dv_validate_action_set_vlan_pcp
5844                                                 (action_flags, actions, error);
5845                         if (ret < 0)
5846                                 return ret;
5847                         /* Count PCP with push_vlan command. */
5848                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5851                         ret = flow_dv_validate_action_set_vlan_vid
5852                                                 (item_flags, action_flags,
5853                                                  actions, error);
5854                         if (ret < 0)
5855                                 return ret;
5856                         /* Count VID with push_vlan command. */
5857                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5858                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5859                         break;
5860                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5861                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5862                         ret = flow_dv_validate_action_l2_encap(dev,
5863                                                                action_flags,
5864                                                                actions, attr,
5865                                                                error);
5866                         if (ret < 0)
5867                                 return ret;
5868                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5869                         ++actions_n;
5870                         break;
5871                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5872                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5873                         ret = flow_dv_validate_action_decap(dev, action_flags,
5874                                                             actions, item_flags,
5875                                                             attr, error);
5876                         if (ret < 0)
5877                                 return ret;
5878                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5879                         ++actions_n;
5880                         break;
5881                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5882                         ret = flow_dv_validate_action_raw_encap_decap
5883                                 (dev, NULL, actions->conf, attr, &action_flags,
5884                                  &actions_n, actions, item_flags, error);
5885                         if (ret < 0)
5886                                 return ret;
5887                         break;
5888                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5889                         decap = actions->conf;
5890                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5891                                 ;
5892                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5893                                 encap = NULL;
5894                                 actions--;
5895                         } else {
5896                                 encap = actions->conf;
5897                         }
5898                         ret = flow_dv_validate_action_raw_encap_decap
5899                                            (dev,
5900                                             decap ? decap : &empty_decap, encap,
5901                                             attr, &action_flags, &actions_n,
5902                                             actions, item_flags, error);
5903                         if (ret < 0)
5904                                 return ret;
5905                         break;
5906                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5907                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5908                         ret = flow_dv_validate_action_modify_mac(action_flags,
5909                                                                  actions,
5910                                                                  item_flags,
5911                                                                  error);
5912                         if (ret < 0)
5913                                 return ret;
5914                         /* Count all modify-header actions as one action. */
5915                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5916                                 ++actions_n;
5917                         action_flags |= actions->type ==
5918                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5919                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5920                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5921                         /*
5922                          * Even if the source and destination MAC addresses have
5923                          * overlap in the header with 4B alignment, the convert
5924                          * function will handle them separately and 4 SW actions
5925                          * will be created. And 2 actions will be added each
5926                          * time no matter how many bytes of address will be set.
5927                          */
5928                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5929                         break;
5930                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5931                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5932                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5933                                                                   actions,
5934                                                                   item_flags,
5935                                                                   error);
5936                         if (ret < 0)
5937                                 return ret;
5938                         /* Count all modify-header actions as one action. */
5939                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5940                                 ++actions_n;
5941                         action_flags |= actions->type ==
5942                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5943                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5944                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5945                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5946                         break;
5947                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5948                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5949                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5950                                                                   actions,
5951                                                                   item_flags,
5952                                                                   error);
5953                         if (ret < 0)
5954                                 return ret;
5955                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5956                                 return rte_flow_error_set(error, ENOTSUP,
5957                                         RTE_FLOW_ERROR_TYPE_ACTION,
5958                                         actions,
5959                                         "Can't change header "
5960                                         "with ICMPv6 proto");
5961                         /* Count all modify-header actions as one action. */
5962                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5963                                 ++actions_n;
5964                         action_flags |= actions->type ==
5965                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5966                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5967                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5968                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5969                         break;
5970                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5971                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5972                         ret = flow_dv_validate_action_modify_tp(action_flags,
5973                                                                 actions,
5974                                                                 item_flags,
5975                                                                 error);
5976                         if (ret < 0)
5977                                 return ret;
5978                         /* Count all modify-header actions as one action. */
5979                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5980                                 ++actions_n;
5981                         action_flags |= actions->type ==
5982                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5983                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5984                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5985                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5986                         break;
5987                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5988                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5989                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5990                                                                  actions,
5991                                                                  item_flags,
5992                                                                  error);
5993                         if (ret < 0)
5994                                 return ret;
5995                         /* Count all modify-header actions as one action. */
5996                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5997                                 ++actions_n;
5998                         action_flags |= actions->type ==
5999                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6000                                                 MLX5_FLOW_ACTION_SET_TTL :
6001                                                 MLX5_FLOW_ACTION_DEC_TTL;
6002                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6003                         break;
6004                 case RTE_FLOW_ACTION_TYPE_JUMP:
6005                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6006                                                            action_flags,
6007                                                            attr, external,
6008                                                            error);
6009                         if (ret)
6010                                 return ret;
6011                         ++actions_n;
6012                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6013                         break;
6014                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6015                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6016                         ret = flow_dv_validate_action_modify_tcp_seq
6017                                                                 (action_flags,
6018                                                                  actions,
6019                                                                  item_flags,
6020                                                                  error);
6021                         if (ret < 0)
6022                                 return ret;
6023                         /* Count all modify-header actions as one action. */
6024                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6025                                 ++actions_n;
6026                         action_flags |= actions->type ==
6027                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6028                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6029                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6030                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6031                         break;
6032                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6033                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6034                         ret = flow_dv_validate_action_modify_tcp_ack
6035                                                                 (action_flags,
6036                                                                  actions,
6037                                                                  item_flags,
6038                                                                  error);
6039                         if (ret < 0)
6040                                 return ret;
6041                         /* Count all modify-header actions as one action. */
6042                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6043                                 ++actions_n;
6044                         action_flags |= actions->type ==
6045                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6046                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6047                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6048                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6049                         break;
6050                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6051                         break;
6052                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6053                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6054                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6055                         break;
6056                 case RTE_FLOW_ACTION_TYPE_METER:
6057                         ret = mlx5_flow_validate_action_meter(dev,
6058                                                               action_flags,
6059                                                               actions, attr,
6060                                                               error);
6061                         if (ret < 0)
6062                                 return ret;
6063                         action_flags |= MLX5_FLOW_ACTION_METER;
6064                         ++actions_n;
6065                         /* Meter action will add one more TAG action. */
6066                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6067                         break;
6068                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6069                         if (!attr->transfer && !attr->group)
6070                                 return rte_flow_error_set(error, ENOTSUP,
6071                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6072                                                                            NULL,
6073                           "Shared ASO age action is not supported for group 0");
6074                         action_flags |= MLX5_FLOW_ACTION_AGE;
6075                         ++actions_n;
6076                         break;
6077                 case RTE_FLOW_ACTION_TYPE_AGE:
6078                         ret = flow_dv_validate_action_age(action_flags,
6079                                                           actions, dev,
6080                                                           error);
6081                         if (ret < 0)
6082                                 return ret;
6083                         action_flags |= MLX5_FLOW_ACTION_AGE;
6084                         ++actions_n;
6085                         break;
6086                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6087                         ret = flow_dv_validate_action_modify_ipv4_dscp
6088                                                          (action_flags,
6089                                                           actions,
6090                                                           item_flags,
6091                                                           error);
6092                         if (ret < 0)
6093                                 return ret;
6094                         /* Count all modify-header actions as one action. */
6095                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6096                                 ++actions_n;
6097                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6098                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6099                         break;
6100                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6101                         ret = flow_dv_validate_action_modify_ipv6_dscp
6102                                                                 (action_flags,
6103                                                                  actions,
6104                                                                  item_flags,
6105                                                                  error);
6106                         if (ret < 0)
6107                                 return ret;
6108                         /* Count all modify-header actions as one action. */
6109                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6110                                 ++actions_n;
6111                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6112                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6113                         break;
6114                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6115                         ret = flow_dv_validate_action_sample(action_flags,
6116                                                              actions, dev,
6117                                                              attr, item_flags,
6118                                                              error);
6119                         if (ret < 0)
6120                                 return ret;
6121                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6122                         ++actions_n;
6123                         break;
6124                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6125                         if (actions[0].type != (typeof(actions[0].type))
6126                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6127                                 return rte_flow_error_set
6128                                                 (error, EINVAL,
6129                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6130                                                 NULL, "MLX5 private action "
6131                                                 "must be the first");
6132
6133                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6134                         break;
6135                 default:
6136                         return rte_flow_error_set(error, ENOTSUP,
6137                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6138                                                   actions,
6139                                                   "action not supported");
6140                 }
6141         }
6142         /*
6143          * Validate actions in flow rules
6144          * - Explicit decap action is prohibited by the tunnel offload API.
6145          * - Drop action in tunnel steer rule is prohibited by the API.
6146          * - Application cannot use MARK action because it's value can mask
6147          *   tunnel default miss nitification.
6148          * - JUMP in tunnel match rule has no support in current PMD
6149          *   implementation.
6150          * - TAG & META are reserved for future uses.
6151          */
6152         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6153                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6154                                             MLX5_FLOW_ACTION_MARK     |
6155                                             MLX5_FLOW_ACTION_SET_TAG  |
6156                                             MLX5_FLOW_ACTION_SET_META |
6157                                             MLX5_FLOW_ACTION_DROP;
6158
6159                 if (action_flags & bad_actions_mask)
6160                         return rte_flow_error_set
6161                                         (error, EINVAL,
6162                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6163                                         "Invalid RTE action in tunnel "
6164                                         "set decap rule");
6165                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6166                         return rte_flow_error_set
6167                                         (error, EINVAL,
6168                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6169                                         "tunnel set decap rule must terminate "
6170                                         "with JUMP");
6171                 if (!attr->ingress)
6172                         return rte_flow_error_set
6173                                         (error, EINVAL,
6174                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6175                                         "tunnel flows for ingress traffic only");
6176         }
6177         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6178                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6179                                             MLX5_FLOW_ACTION_MARK    |
6180                                             MLX5_FLOW_ACTION_SET_TAG |
6181                                             MLX5_FLOW_ACTION_SET_META;
6182
6183                 if (action_flags & bad_actions_mask)
6184                         return rte_flow_error_set
6185                                         (error, EINVAL,
6186                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6187                                         "Invalid RTE action in tunnel "
6188                                         "set match rule");
6189         }
6190         /*
6191          * Validate the drop action mutual exclusion with other actions.
6192          * Drop action is mutually-exclusive with any other action, except for
6193          * Count action.
6194          */
6195         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6196             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6197                 return rte_flow_error_set(error, EINVAL,
6198                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6199                                           "Drop action is mutually-exclusive "
6200                                           "with any other action, except for "
6201                                           "Count action");
6202         /* Eswitch has few restrictions on using items and actions */
6203         if (attr->transfer) {
6204                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6205                     action_flags & MLX5_FLOW_ACTION_FLAG)
6206                         return rte_flow_error_set(error, ENOTSUP,
6207                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6208                                                   NULL,
6209                                                   "unsupported action FLAG");
6210                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6211                     action_flags & MLX5_FLOW_ACTION_MARK)
6212                         return rte_flow_error_set(error, ENOTSUP,
6213                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6214                                                   NULL,
6215                                                   "unsupported action MARK");
6216                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6217                         return rte_flow_error_set(error, ENOTSUP,
6218                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6219                                                   NULL,
6220                                                   "unsupported action QUEUE");
6221                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6222                         return rte_flow_error_set(error, ENOTSUP,
6223                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6224                                                   NULL,
6225                                                   "unsupported action RSS");
6226                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6227                         return rte_flow_error_set(error, EINVAL,
6228                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6229                                                   actions,
6230                                                   "no fate action is found");
6231         } else {
6232                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6233                         return rte_flow_error_set(error, EINVAL,
6234                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6235                                                   actions,
6236                                                   "no fate action is found");
6237         }
6238         /*
6239          * Continue validation for Xcap and VLAN actions.
6240          * If hairpin is working in explicit TX rule mode, there is no actions
6241          * splitting and the validation of hairpin ingress flow should be the
6242          * same as other standard flows.
6243          */
6244         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6245                              MLX5_FLOW_VLAN_ACTIONS)) &&
6246             (queue_index == 0xFFFF ||
6247              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6248              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6249              conf->tx_explicit != 0))) {
6250                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6251                     MLX5_FLOW_XCAP_ACTIONS)
6252                         return rte_flow_error_set(error, ENOTSUP,
6253                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6254                                                   NULL, "encap and decap "
6255                                                   "combination aren't supported");
6256                 if (!attr->transfer && attr->ingress) {
6257                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6258                                 return rte_flow_error_set
6259                                                 (error, ENOTSUP,
6260                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6261                                                  NULL, "encap is not supported"
6262                                                  " for ingress traffic");
6263                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6264                                 return rte_flow_error_set
6265                                                 (error, ENOTSUP,
6266                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6267                                                  NULL, "push VLAN action not "
6268                                                  "supported for ingress");
6269                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6270                                         MLX5_FLOW_VLAN_ACTIONS)
6271                                 return rte_flow_error_set
6272                                                 (error, ENOTSUP,
6273                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6274                                                  NULL, "no support for "
6275                                                  "multiple VLAN actions");
6276                 }
6277         }
6278         /*
6279          * Hairpin flow will add one more TAG action in TX implicit mode.
6280          * In TX explicit mode, there will be no hairpin flow ID.
6281          */
6282         if (hairpin > 0)
6283                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6284         /* extra metadata enabled: one more TAG action will be add. */
6285         if (dev_conf->dv_flow_en &&
6286             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6287             mlx5_flow_ext_mreg_supported(dev))
6288                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6289         if ((uint32_t)rw_act_num >
6290                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6291                 return rte_flow_error_set(error, ENOTSUP,
6292                                           RTE_FLOW_ERROR_TYPE_ACTION,
6293                                           NULL, "too many header modify"
6294                                           " actions to support");
6295         }
6296         return 0;
6297 }
6298
6299 /**
6300  * Internal preparation function. Allocates the DV flow size,
6301  * this size is constant.
6302  *
6303  * @param[in] dev
6304  *   Pointer to the rte_eth_dev structure.
6305  * @param[in] attr
6306  *   Pointer to the flow attributes.
6307  * @param[in] items
6308  *   Pointer to the list of items.
6309  * @param[in] actions
6310  *   Pointer to the list of actions.
6311  * @param[out] error
6312  *   Pointer to the error structure.
6313  *
6314  * @return
6315  *   Pointer to mlx5_flow object on success,
6316  *   otherwise NULL and rte_errno is set.
6317  */
6318 static struct mlx5_flow *
6319 flow_dv_prepare(struct rte_eth_dev *dev,
6320                 const struct rte_flow_attr *attr __rte_unused,
6321                 const struct rte_flow_item items[] __rte_unused,
6322                 const struct rte_flow_action actions[] __rte_unused,
6323                 struct rte_flow_error *error)
6324 {
6325         uint32_t handle_idx = 0;
6326         struct mlx5_flow *dev_flow;
6327         struct mlx5_flow_handle *dev_handle;
6328         struct mlx5_priv *priv = dev->data->dev_private;
6329         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6330
6331         MLX5_ASSERT(wks);
6332         /* In case of corrupting the memory. */
6333         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6334                 rte_flow_error_set(error, ENOSPC,
6335                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6336                                    "not free temporary device flow");
6337                 return NULL;
6338         }
6339         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6340                                    &handle_idx);
6341         if (!dev_handle) {
6342                 rte_flow_error_set(error, ENOMEM,
6343                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6344                                    "not enough memory to create flow handle");
6345                 return NULL;
6346         }
6347         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6348         dev_flow = &wks->flows[wks->flow_idx++];
6349         memset(dev_flow, 0, sizeof(*dev_flow));
6350         dev_flow->handle = dev_handle;
6351         dev_flow->handle_idx = handle_idx;
6352         /*
6353          * In some old rdma-core releases, before continuing, a check of the
6354          * length of matching parameter will be done at first. It needs to use
6355          * the length without misc4 param. If the flow has misc4 support, then
6356          * the length needs to be adjusted accordingly. Each param member is
6357          * aligned with a 64B boundary naturally.
6358          */
6359         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6360                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6361         dev_flow->ingress = attr->ingress;
6362         dev_flow->dv.transfer = attr->transfer;
6363         return dev_flow;
6364 }
6365
6366 #ifdef RTE_LIBRTE_MLX5_DEBUG
6367 /**
6368  * Sanity check for match mask and value. Similar to check_valid_spec() in
6369  * kernel driver. If unmasked bit is present in value, it returns failure.
6370  *
6371  * @param match_mask
6372  *   pointer to match mask buffer.
6373  * @param match_value
6374  *   pointer to match value buffer.
6375  *
6376  * @return
6377  *   0 if valid, -EINVAL otherwise.
6378  */
6379 static int
6380 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6381 {
6382         uint8_t *m = match_mask;
6383         uint8_t *v = match_value;
6384         unsigned int i;
6385
6386         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6387                 if (v[i] & ~m[i]) {
6388                         DRV_LOG(ERR,
6389                                 "match_value differs from match_criteria"
6390                                 " %p[%u] != %p[%u]",
6391                                 match_value, i, match_mask, i);
6392                         return -EINVAL;
6393                 }
6394         }
6395         return 0;
6396 }
6397 #endif
6398
6399 /**
6400  * Add match of ip_version.
6401  *
6402  * @param[in] group
6403  *   Flow group.
6404  * @param[in] headers_v
6405  *   Values header pointer.
6406  * @param[in] headers_m
6407  *   Masks header pointer.
6408  * @param[in] ip_version
6409  *   The IP version to set.
6410  */
6411 static inline void
6412 flow_dv_set_match_ip_version(uint32_t group,
6413                              void *headers_v,
6414                              void *headers_m,
6415                              uint8_t ip_version)
6416 {
6417         if (group == 0)
6418                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6419         else
6420                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6421                          ip_version);
6422         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6423         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6424         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6425 }
6426
6427 /**
6428  * Add Ethernet item to matcher and to the value.
6429  *
6430  * @param[in, out] matcher
6431  *   Flow matcher.
6432  * @param[in, out] key
6433  *   Flow matcher value.
6434  * @param[in] item
6435  *   Flow pattern to translate.
6436  * @param[in] inner
6437  *   Item is inner pattern.
6438  */
6439 static void
6440 flow_dv_translate_item_eth(void *matcher, void *key,
6441                            const struct rte_flow_item *item, int inner,
6442                            uint32_t group)
6443 {
6444         const struct rte_flow_item_eth *eth_m = item->mask;
6445         const struct rte_flow_item_eth *eth_v = item->spec;
6446         const struct rte_flow_item_eth nic_mask = {
6447                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6448                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6449                 .type = RTE_BE16(0xffff),
6450                 .has_vlan = 0,
6451         };
6452         void *hdrs_m;
6453         void *hdrs_v;
6454         char *l24_v;
6455         unsigned int i;
6456
6457         if (!eth_v)
6458                 return;
6459         if (!eth_m)
6460                 eth_m = &nic_mask;
6461         if (inner) {
6462                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6463                                          inner_headers);
6464                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6465         } else {
6466                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6467                                          outer_headers);
6468                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6469         }
6470         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6471                &eth_m->dst, sizeof(eth_m->dst));
6472         /* The value must be in the range of the mask. */
6473         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6474         for (i = 0; i < sizeof(eth_m->dst); ++i)
6475                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6476         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6477                &eth_m->src, sizeof(eth_m->src));
6478         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6479         /* The value must be in the range of the mask. */
6480         for (i = 0; i < sizeof(eth_m->dst); ++i)
6481                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6482         /*
6483          * HW supports match on one Ethertype, the Ethertype following the last
6484          * VLAN tag of the packet (see PRM).
6485          * Set match on ethertype only if ETH header is not followed by VLAN.
6486          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6487          * ethertype, and use ip_version field instead.
6488          * eCPRI over Ether layer will use type value 0xAEFE.
6489          */
6490         if (eth_m->type == 0xFFFF) {
6491                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6492                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6493                 switch (eth_v->type) {
6494                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6495                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6496                         return;
6497                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6498                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6499                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6500                         return;
6501                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6502                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6503                         return;
6504                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6505                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6506                         return;
6507                 default:
6508                         break;
6509                 }
6510         }
6511         if (eth_m->has_vlan) {
6512                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6513                 if (eth_v->has_vlan) {
6514                         /*
6515                          * Here, when also has_more_vlan field in VLAN item is
6516                          * not set, only single-tagged packets will be matched.
6517                          */
6518                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6519                         return;
6520                 }
6521         }
6522         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6523                  rte_be_to_cpu_16(eth_m->type));
6524         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6525         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6526 }
6527
6528 /**
6529  * Add VLAN item to matcher and to the value.
6530  *
6531  * @param[in, out] dev_flow
6532  *   Flow descriptor.
6533  * @param[in, out] matcher
6534  *   Flow matcher.
6535  * @param[in, out] key
6536  *   Flow matcher value.
6537  * @param[in] item
6538  *   Flow pattern to translate.
6539  * @param[in] inner
6540  *   Item is inner pattern.
6541  */
6542 static void
6543 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6544                             void *matcher, void *key,
6545                             const struct rte_flow_item *item,
6546                             int inner, uint32_t group)
6547 {
6548         const struct rte_flow_item_vlan *vlan_m = item->mask;
6549         const struct rte_flow_item_vlan *vlan_v = item->spec;
6550         void *hdrs_m;
6551         void *hdrs_v;
6552         uint16_t tci_m;
6553         uint16_t tci_v;
6554
6555         if (inner) {
6556                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6557                                          inner_headers);
6558                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6559         } else {
6560                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6561                                          outer_headers);
6562                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6563                 /*
6564                  * This is workaround, masks are not supported,
6565                  * and pre-validated.
6566                  */
6567                 if (vlan_v)
6568                         dev_flow->handle->vf_vlan.tag =
6569                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6570         }
6571         /*
6572          * When VLAN item exists in flow, mark packet as tagged,
6573          * even if TCI is not specified.
6574          */
6575         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6576                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6577                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6578         }
6579         if (!vlan_v)
6580                 return;
6581         if (!vlan_m)
6582                 vlan_m = &rte_flow_item_vlan_mask;
6583         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6584         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6585         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6586         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6587         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6588         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6589         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6590         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6591         /*
6592          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6593          * ethertype, and use ip_version field instead.
6594          */
6595         if (vlan_m->inner_type == 0xFFFF) {
6596                 switch (vlan_v->inner_type) {
6597                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6598                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6599                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6600                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6601                         return;
6602                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6603                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6604                         return;
6605                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6606                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6607                         return;
6608                 default:
6609                         break;
6610                 }
6611         }
6612         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6613                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6614                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6615                 /* Only one vlan_tag bit can be set. */
6616                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6617                 return;
6618         }
6619         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6620                  rte_be_to_cpu_16(vlan_m->inner_type));
6621         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6622                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6623 }
6624
6625 /**
6626  * Add IPV4 item to matcher and to the value.
6627  *
6628  * @param[in, out] matcher
6629  *   Flow matcher.
6630  * @param[in, out] key
6631  *   Flow matcher value.
6632  * @param[in] item
6633  *   Flow pattern to translate.
6634  * @param[in] inner
6635  *   Item is inner pattern.
6636  * @param[in] group
6637  *   The group to insert the rule.
6638  */
6639 static void
6640 flow_dv_translate_item_ipv4(void *matcher, void *key,
6641                             const struct rte_flow_item *item,
6642                             int inner, uint32_t group)
6643 {
6644         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6645         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6646         const struct rte_flow_item_ipv4 nic_mask = {
6647                 .hdr = {
6648                         .src_addr = RTE_BE32(0xffffffff),
6649                         .dst_addr = RTE_BE32(0xffffffff),
6650                         .type_of_service = 0xff,
6651                         .next_proto_id = 0xff,
6652                         .time_to_live = 0xff,
6653                 },
6654         };
6655         void *headers_m;
6656         void *headers_v;
6657         char *l24_m;
6658         char *l24_v;
6659         uint8_t tos;
6660
6661         if (inner) {
6662                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6663                                          inner_headers);
6664                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6665         } else {
6666                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6667                                          outer_headers);
6668                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6669         }
6670         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6671         if (!ipv4_v)
6672                 return;
6673         if (!ipv4_m)
6674                 ipv4_m = &nic_mask;
6675         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6676                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6677         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6678                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6679         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6680         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6681         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6682                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6683         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6684                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6685         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6686         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6687         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6689                  ipv4_m->hdr.type_of_service);
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6691         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6692                  ipv4_m->hdr.type_of_service >> 2);
6693         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6694         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6695                  ipv4_m->hdr.next_proto_id);
6696         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6697                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6698         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6699                  ipv4_m->hdr.time_to_live);
6700         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6701                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6702         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6703                  !!(ipv4_m->hdr.fragment_offset));
6704         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6705                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6706 }
6707
6708 /**
6709  * Add IPV6 item to matcher and to the value.
6710  *
6711  * @param[in, out] matcher
6712  *   Flow matcher.
6713  * @param[in, out] key
6714  *   Flow matcher value.
6715  * @param[in] item
6716  *   Flow pattern to translate.
6717  * @param[in] inner
6718  *   Item is inner pattern.
6719  * @param[in] group
6720  *   The group to insert the rule.
6721  */
6722 static void
6723 flow_dv_translate_item_ipv6(void *matcher, void *key,
6724                             const struct rte_flow_item *item,
6725                             int inner, uint32_t group)
6726 {
6727         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6728         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6729         const struct rte_flow_item_ipv6 nic_mask = {
6730                 .hdr = {
6731                         .src_addr =
6732                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6733                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6734                         .dst_addr =
6735                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6736                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6737                         .vtc_flow = RTE_BE32(0xffffffff),
6738                         .proto = 0xff,
6739                         .hop_limits = 0xff,
6740                 },
6741         };
6742         void *headers_m;
6743         void *headers_v;
6744         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6745         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6746         char *l24_m;
6747         char *l24_v;
6748         uint32_t vtc_m;
6749         uint32_t vtc_v;
6750         int i;
6751         int size;
6752
6753         if (inner) {
6754                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6755                                          inner_headers);
6756                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6757         } else {
6758                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6759                                          outer_headers);
6760                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6761         }
6762         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6763         if (!ipv6_v)
6764                 return;
6765         if (!ipv6_m)
6766                 ipv6_m = &nic_mask;
6767         size = sizeof(ipv6_m->hdr.dst_addr);
6768         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6769                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6770         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6771                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6772         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6773         for (i = 0; i < size; ++i)
6774                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6775         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6776                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6777         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6778                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6779         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6780         for (i = 0; i < size; ++i)
6781                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6782         /* TOS. */
6783         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6784         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6785         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6786         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6787         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6788         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6789         /* Label. */
6790         if (inner) {
6791                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6792                          vtc_m);
6793                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6794                          vtc_v);
6795         } else {
6796                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6797                          vtc_m);
6798                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6799                          vtc_v);
6800         }
6801         /* Protocol. */
6802         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6803                  ipv6_m->hdr.proto);
6804         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6805                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6806         /* Hop limit. */
6807         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6808                  ipv6_m->hdr.hop_limits);
6809         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6810                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6811         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6812                  !!(ipv6_m->has_frag_ext));
6813         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6814                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6815 }
6816
6817 /**
6818  * Add IPV6 fragment extension item to matcher and to the value.
6819  *
6820  * @param[in, out] matcher
6821  *   Flow matcher.
6822  * @param[in, out] key
6823  *   Flow matcher value.
6824  * @param[in] item
6825  *   Flow pattern to translate.
6826  * @param[in] inner
6827  *   Item is inner pattern.
6828  */
6829 static void
6830 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6831                                      const struct rte_flow_item *item,
6832                                      int inner)
6833 {
6834         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6835         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6836         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6837                 .hdr = {
6838                         .next_header = 0xff,
6839                         .frag_data = RTE_BE16(0xffff),
6840                 },
6841         };
6842         void *headers_m;
6843         void *headers_v;
6844
6845         if (inner) {
6846                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6847                                          inner_headers);
6848                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6849         } else {
6850                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6851                                          outer_headers);
6852                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6853         }
6854         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6855         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6856         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6857         if (!ipv6_frag_ext_v)
6858                 return;
6859         if (!ipv6_frag_ext_m)
6860                 ipv6_frag_ext_m = &nic_mask;
6861         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6862                  ipv6_frag_ext_m->hdr.next_header);
6863         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6864                  ipv6_frag_ext_v->hdr.next_header &
6865                  ipv6_frag_ext_m->hdr.next_header);
6866 }
6867
6868 /**
6869  * Add TCP item to matcher and to the value.
6870  *
6871  * @param[in, out] matcher
6872  *   Flow matcher.
6873  * @param[in, out] key
6874  *   Flow matcher value.
6875  * @param[in] item
6876  *   Flow pattern to translate.
6877  * @param[in] inner
6878  *   Item is inner pattern.
6879  */
6880 static void
6881 flow_dv_translate_item_tcp(void *matcher, void *key,
6882                            const struct rte_flow_item *item,
6883                            int inner)
6884 {
6885         const struct rte_flow_item_tcp *tcp_m = item->mask;
6886         const struct rte_flow_item_tcp *tcp_v = item->spec;
6887         void *headers_m;
6888         void *headers_v;
6889
6890         if (inner) {
6891                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6892                                          inner_headers);
6893                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6894         } else {
6895                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6896                                          outer_headers);
6897                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6898         }
6899         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6900         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6901         if (!tcp_v)
6902                 return;
6903         if (!tcp_m)
6904                 tcp_m = &rte_flow_item_tcp_mask;
6905         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6906                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6907         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6908                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6909         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6910                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6911         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6912                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6913         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6914                  tcp_m->hdr.tcp_flags);
6915         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6916                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6917 }
6918
6919 /**
6920  * Add UDP item to matcher and to the value.
6921  *
6922  * @param[in, out] matcher
6923  *   Flow matcher.
6924  * @param[in, out] key
6925  *   Flow matcher value.
6926  * @param[in] item
6927  *   Flow pattern to translate.
6928  * @param[in] inner
6929  *   Item is inner pattern.
6930  */
6931 static void
6932 flow_dv_translate_item_udp(void *matcher, void *key,
6933                            const struct rte_flow_item *item,
6934                            int inner)
6935 {
6936         const struct rte_flow_item_udp *udp_m = item->mask;
6937         const struct rte_flow_item_udp *udp_v = item->spec;
6938         void *headers_m;
6939         void *headers_v;
6940
6941         if (inner) {
6942                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6943                                          inner_headers);
6944                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6945         } else {
6946                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6947                                          outer_headers);
6948                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6949         }
6950         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6951         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6952         if (!udp_v)
6953                 return;
6954         if (!udp_m)
6955                 udp_m = &rte_flow_item_udp_mask;
6956         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6957                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6958         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6959                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6960         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6961                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6962         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6963                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6964 }
6965
6966 /**
6967  * Add GRE optional Key item to matcher and to the value.
6968  *
6969  * @param[in, out] matcher
6970  *   Flow matcher.
6971  * @param[in, out] key
6972  *   Flow matcher value.
6973  * @param[in] item
6974  *   Flow pattern to translate.
6975  * @param[in] inner
6976  *   Item is inner pattern.
6977  */
6978 static void
6979 flow_dv_translate_item_gre_key(void *matcher, void *key,
6980                                    const struct rte_flow_item *item)
6981 {
6982         const rte_be32_t *key_m = item->mask;
6983         const rte_be32_t *key_v = item->spec;
6984         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6985         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6986         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6987
6988         /* GRE K bit must be on and should already be validated */
6989         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6990         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6991         if (!key_v)
6992                 return;
6993         if (!key_m)
6994                 key_m = &gre_key_default_mask;
6995         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6996                  rte_be_to_cpu_32(*key_m) >> 8);
6997         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6998                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6999         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7000                  rte_be_to_cpu_32(*key_m) & 0xFF);
7001         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7002                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7003 }
7004
7005 /**
7006  * Add GRE item to matcher and to the value.
7007  *
7008  * @param[in, out] matcher
7009  *   Flow matcher.
7010  * @param[in, out] key
7011  *   Flow matcher value.
7012  * @param[in] item
7013  *   Flow pattern to translate.
7014  * @param[in] inner
7015  *   Item is inner pattern.
7016  */
7017 static void
7018 flow_dv_translate_item_gre(void *matcher, void *key,
7019                            const struct rte_flow_item *item,
7020                            int inner)
7021 {
7022         const struct rte_flow_item_gre *gre_m = item->mask;
7023         const struct rte_flow_item_gre *gre_v = item->spec;
7024         void *headers_m;
7025         void *headers_v;
7026         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7027         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7028         struct {
7029                 union {
7030                         __extension__
7031                         struct {
7032                                 uint16_t version:3;
7033                                 uint16_t rsvd0:9;
7034                                 uint16_t s_present:1;
7035                                 uint16_t k_present:1;
7036                                 uint16_t rsvd_bit1:1;
7037                                 uint16_t c_present:1;
7038                         };
7039                         uint16_t value;
7040                 };
7041         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7042
7043         if (inner) {
7044                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7045                                          inner_headers);
7046                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7047         } else {
7048                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7049                                          outer_headers);
7050                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7051         }
7052         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7053         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7054         if (!gre_v)
7055                 return;
7056         if (!gre_m)
7057                 gre_m = &rte_flow_item_gre_mask;
7058         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7059                  rte_be_to_cpu_16(gre_m->protocol));
7060         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7061                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7062         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7063         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7064         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7065                  gre_crks_rsvd0_ver_m.c_present);
7066         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7067                  gre_crks_rsvd0_ver_v.c_present &
7068                  gre_crks_rsvd0_ver_m.c_present);
7069         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7070                  gre_crks_rsvd0_ver_m.k_present);
7071         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7072                  gre_crks_rsvd0_ver_v.k_present &
7073                  gre_crks_rsvd0_ver_m.k_present);
7074         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7075                  gre_crks_rsvd0_ver_m.s_present);
7076         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7077                  gre_crks_rsvd0_ver_v.s_present &
7078                  gre_crks_rsvd0_ver_m.s_present);
7079 }
7080
7081 /**
7082  * Add NVGRE item to matcher and to the value.
7083  *
7084  * @param[in, out] matcher
7085  *   Flow matcher.
7086  * @param[in, out] key
7087  *   Flow matcher value.
7088  * @param[in] item
7089  *   Flow pattern to translate.
7090  * @param[in] inner
7091  *   Item is inner pattern.
7092  */
7093 static void
7094 flow_dv_translate_item_nvgre(void *matcher, void *key,
7095                              const struct rte_flow_item *item,
7096                              int inner)
7097 {
7098         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7099         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7100         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7101         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7102         const char *tni_flow_id_m;
7103         const char *tni_flow_id_v;
7104         char *gre_key_m;
7105         char *gre_key_v;
7106         int size;
7107         int i;
7108
7109         /* For NVGRE, GRE header fields must be set with defined values. */
7110         const struct rte_flow_item_gre gre_spec = {
7111                 .c_rsvd0_ver = RTE_BE16(0x2000),
7112                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7113         };
7114         const struct rte_flow_item_gre gre_mask = {
7115                 .c_rsvd0_ver = RTE_BE16(0xB000),
7116                 .protocol = RTE_BE16(UINT16_MAX),
7117         };
7118         const struct rte_flow_item gre_item = {
7119                 .spec = &gre_spec,
7120                 .mask = &gre_mask,
7121                 .last = NULL,
7122         };
7123         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7124         if (!nvgre_v)
7125                 return;
7126         if (!nvgre_m)
7127                 nvgre_m = &rte_flow_item_nvgre_mask;
7128         tni_flow_id_m = (const char *)nvgre_m->tni;
7129         tni_flow_id_v = (const char *)nvgre_v->tni;
7130         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7131         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7132         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7133         memcpy(gre_key_m, tni_flow_id_m, size);
7134         for (i = 0; i < size; ++i)
7135                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7136 }
7137
7138 /**
7139  * Add VXLAN item to matcher and to the value.
7140  *
7141  * @param[in, out] matcher
7142  *   Flow matcher.
7143  * @param[in, out] key
7144  *   Flow matcher value.
7145  * @param[in] item
7146  *   Flow pattern to translate.
7147  * @param[in] inner
7148  *   Item is inner pattern.
7149  */
7150 static void
7151 flow_dv_translate_item_vxlan(void *matcher, void *key,
7152                              const struct rte_flow_item *item,
7153                              int inner)
7154 {
7155         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7156         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7157         void *headers_m;
7158         void *headers_v;
7159         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7160         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7161         char *vni_m;
7162         char *vni_v;
7163         uint16_t dport;
7164         int size;
7165         int i;
7166
7167         if (inner) {
7168                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7169                                          inner_headers);
7170                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7171         } else {
7172                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7173                                          outer_headers);
7174                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7175         }
7176         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7177                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7178         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7179                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7180                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7181         }
7182         if (!vxlan_v)
7183                 return;
7184         if (!vxlan_m)
7185                 vxlan_m = &rte_flow_item_vxlan_mask;
7186         size = sizeof(vxlan_m->vni);
7187         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7188         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7189         memcpy(vni_m, vxlan_m->vni, size);
7190         for (i = 0; i < size; ++i)
7191                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7192 }
7193
7194 /**
7195  * Add VXLAN-GPE item to matcher and to the value.
7196  *
7197  * @param[in, out] matcher
7198  *   Flow matcher.
7199  * @param[in, out] key
7200  *   Flow matcher value.
7201  * @param[in] item
7202  *   Flow pattern to translate.
7203  * @param[in] inner
7204  *   Item is inner pattern.
7205  */
7206
7207 static void
7208 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7209                                  const struct rte_flow_item *item, int inner)
7210 {
7211         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7212         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7213         void *headers_m;
7214         void *headers_v;
7215         void *misc_m =
7216                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7217         void *misc_v =
7218                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7219         char *vni_m;
7220         char *vni_v;
7221         uint16_t dport;
7222         int size;
7223         int i;
7224         uint8_t flags_m = 0xff;
7225         uint8_t flags_v = 0xc;
7226
7227         if (inner) {
7228                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7229                                          inner_headers);
7230                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7231         } else {
7232                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7233                                          outer_headers);
7234                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7235         }
7236         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7237                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7238         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7239                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7240                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7241         }
7242         if (!vxlan_v)
7243                 return;
7244         if (!vxlan_m)
7245                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7246         size = sizeof(vxlan_m->vni);
7247         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7248         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7249         memcpy(vni_m, vxlan_m->vni, size);
7250         for (i = 0; i < size; ++i)
7251                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7252         if (vxlan_m->flags) {
7253                 flags_m = vxlan_m->flags;
7254                 flags_v = vxlan_v->flags;
7255         }
7256         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7257         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7258         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7259                  vxlan_m->protocol);
7260         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7261                  vxlan_v->protocol);
7262 }
7263
7264 /**
7265  * Add Geneve item to matcher and to the value.
7266  *
7267  * @param[in, out] matcher
7268  *   Flow matcher.
7269  * @param[in, out] key
7270  *   Flow matcher value.
7271  * @param[in] item
7272  *   Flow pattern to translate.
7273  * @param[in] inner
7274  *   Item is inner pattern.
7275  */
7276
7277 static void
7278 flow_dv_translate_item_geneve(void *matcher, void *key,
7279                               const struct rte_flow_item *item, int inner)
7280 {
7281         const struct rte_flow_item_geneve *geneve_m = item->mask;
7282         const struct rte_flow_item_geneve *geneve_v = item->spec;
7283         void *headers_m;
7284         void *headers_v;
7285         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7286         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7287         uint16_t dport;
7288         uint16_t gbhdr_m;
7289         uint16_t gbhdr_v;
7290         char *vni_m;
7291         char *vni_v;
7292         size_t size, i;
7293
7294         if (inner) {
7295                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7296                                          inner_headers);
7297                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7298         } else {
7299                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7300                                          outer_headers);
7301                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7302         }
7303         dport = MLX5_UDP_PORT_GENEVE;
7304         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7305                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7306                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7307         }
7308         if (!geneve_v)
7309                 return;
7310         if (!geneve_m)
7311                 geneve_m = &rte_flow_item_geneve_mask;
7312         size = sizeof(geneve_m->vni);
7313         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7314         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7315         memcpy(vni_m, geneve_m->vni, size);
7316         for (i = 0; i < size; ++i)
7317                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7318         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7319                  rte_be_to_cpu_16(geneve_m->protocol));
7320         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7321                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7322         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7323         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7324         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7325                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7326         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7327                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7328         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7329                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7330         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7331                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7332                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7333 }
7334
7335 /**
7336  * Create Geneve TLV option resource.
7337  *
7338  * @param dev[in, out]
7339  *   Pointer to rte_eth_dev structure.
7340  * @param[in, out] tag_be24
7341  *   Tag value in big endian then R-shift 8.
7342  * @parm[in, out] dev_flow
7343  *   Pointer to the dev_flow.
7344  * @param[out] error
7345  *   pointer to error structure.
7346  *
7347  * @return
7348  *   0 on success otherwise -errno and errno is set.
7349  */
7350
7351 int
7352 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7353                                              const struct rte_flow_item *item,
7354                                              struct rte_flow_error *error)
7355 {
7356         struct mlx5_priv *priv = dev->data->dev_private;
7357         struct mlx5_dev_ctx_shared *sh = priv->sh;
7358         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7359                         sh->geneve_tlv_option_resource;
7360         struct mlx5_devx_obj *obj;
7361         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7362         int ret = 0;
7363
7364         if (!geneve_opt_v)
7365                 return -1;
7366         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7367         if (geneve_opt_resource != NULL) {
7368                 if (geneve_opt_resource->option_class ==
7369                         geneve_opt_v->option_class &&
7370                         geneve_opt_resource->option_type ==
7371                         geneve_opt_v->option_type &&
7372                         geneve_opt_resource->length ==
7373                         geneve_opt_v->option_len) {
7374                         /* We already have GENVE TLV option obj allocated. */
7375                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7376                                            __ATOMIC_RELAXED);
7377                 } else {
7378                         ret = rte_flow_error_set(error, ENOMEM,
7379                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7380                                 "Only one GENEVE TLV option supported");
7381                         goto exit;
7382                 }
7383         } else {
7384                 /* Create a GENEVE TLV object and resource. */
7385                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7386                                 geneve_opt_v->option_class,
7387                                 geneve_opt_v->option_type,
7388                                 geneve_opt_v->option_len);
7389                 if (!obj) {
7390                         ret = rte_flow_error_set(error, ENODATA,
7391                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7392                                 "Failed to create GENEVE TLV Devx object");
7393                         goto exit;
7394                 }
7395                 sh->geneve_tlv_option_resource =
7396                                 mlx5_malloc(MLX5_MEM_ZERO,
7397                                                 sizeof(*geneve_opt_resource),
7398                                                 0, SOCKET_ID_ANY);
7399                 if (!sh->geneve_tlv_option_resource) {
7400                         claim_zero(mlx5_devx_cmd_destroy(obj));
7401                         ret = rte_flow_error_set(error, ENOMEM,
7402                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7403                                 "GENEVE TLV object memory allocation failed");
7404                         goto exit;
7405                 }
7406                 geneve_opt_resource = sh->geneve_tlv_option_resource;
7407                 geneve_opt_resource->obj = obj;
7408                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7409                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7410                 geneve_opt_resource->length = geneve_opt_v->option_len;
7411                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7412                                 __ATOMIC_RELAXED);
7413         }
7414 exit:
7415         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7416         return ret;
7417 }
7418
7419 /**
7420  * Add MPLS item to matcher and to the value.
7421  *
7422  * @param[in, out] matcher
7423  *   Flow matcher.
7424  * @param[in, out] key
7425  *   Flow matcher value.
7426  * @param[in] item
7427  *   Flow pattern to translate.
7428  * @param[in] prev_layer
7429  *   The protocol layer indicated in previous item.
7430  * @param[in] inner
7431  *   Item is inner pattern.
7432  */
7433 static void
7434 flow_dv_translate_item_mpls(void *matcher, void *key,
7435                             const struct rte_flow_item *item,
7436                             uint64_t prev_layer,
7437                             int inner)
7438 {
7439         const uint32_t *in_mpls_m = item->mask;
7440         const uint32_t *in_mpls_v = item->spec;
7441         uint32_t *out_mpls_m = 0;
7442         uint32_t *out_mpls_v = 0;
7443         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7444         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7445         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7446                                      misc_parameters_2);
7447         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7448         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7449         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7450
7451         switch (prev_layer) {
7452         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7453                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7454                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7455                          MLX5_UDP_PORT_MPLS);
7456                 break;
7457         case MLX5_FLOW_LAYER_GRE:
7458                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7459                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7460                          RTE_ETHER_TYPE_MPLS);
7461                 break;
7462         default:
7463                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7464                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7465                          IPPROTO_MPLS);
7466                 break;
7467         }
7468         if (!in_mpls_v)
7469                 return;
7470         if (!in_mpls_m)
7471                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7472         switch (prev_layer) {
7473         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7474                 out_mpls_m =
7475                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7476                                                  outer_first_mpls_over_udp);
7477                 out_mpls_v =
7478                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7479                                                  outer_first_mpls_over_udp);
7480                 break;
7481         case MLX5_FLOW_LAYER_GRE:
7482                 out_mpls_m =
7483                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7484                                                  outer_first_mpls_over_gre);
7485                 out_mpls_v =
7486                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7487                                                  outer_first_mpls_over_gre);
7488                 break;
7489         default:
7490                 /* Inner MPLS not over GRE is not supported. */
7491                 if (!inner) {
7492                         out_mpls_m =
7493                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7494                                                          misc2_m,
7495                                                          outer_first_mpls);
7496                         out_mpls_v =
7497                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7498                                                          misc2_v,
7499                                                          outer_first_mpls);
7500                 }
7501                 break;
7502         }
7503         if (out_mpls_m && out_mpls_v) {
7504                 *out_mpls_m = *in_mpls_m;
7505                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7506         }
7507 }
7508
7509 /**
7510  * Add metadata register item to matcher
7511  *
7512  * @param[in, out] matcher
7513  *   Flow matcher.
7514  * @param[in, out] key
7515  *   Flow matcher value.
7516  * @param[in] reg_type
7517  *   Type of device metadata register
7518  * @param[in] value
7519  *   Register value
7520  * @param[in] mask
7521  *   Register mask
7522  */
7523 static void
7524 flow_dv_match_meta_reg(void *matcher, void *key,
7525                        enum modify_reg reg_type,
7526                        uint32_t data, uint32_t mask)
7527 {
7528         void *misc2_m =
7529                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7530         void *misc2_v =
7531                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7532         uint32_t temp;
7533
7534         data &= mask;
7535         switch (reg_type) {
7536         case REG_A:
7537                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7538                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7539                 break;
7540         case REG_B:
7541                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7542                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7543                 break;
7544         case REG_C_0:
7545                 /*
7546                  * The metadata register C0 field might be divided into
7547                  * source vport index and META item value, we should set
7548                  * this field according to specified mask, not as whole one.
7549                  */
7550                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7551                 temp |= mask;
7552                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7553                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7554                 temp &= ~mask;
7555                 temp |= data;
7556                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7557                 break;
7558         case REG_C_1:
7559                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7560                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7561                 break;
7562         case REG_C_2:
7563                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7564                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7565                 break;
7566         case REG_C_3:
7567                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7568                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7569                 break;
7570         case REG_C_4:
7571                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7572                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7573                 break;
7574         case REG_C_5:
7575                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7576                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7577                 break;
7578         case REG_C_6:
7579                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7580                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7581                 break;
7582         case REG_C_7:
7583                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7584                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7585                 break;
7586         default:
7587                 MLX5_ASSERT(false);
7588                 break;
7589         }
7590 }
7591
7592 /**
7593  * Add MARK item to matcher
7594  *
7595  * @param[in] dev
7596  *   The device to configure through.
7597  * @param[in, out] matcher
7598  *   Flow matcher.
7599  * @param[in, out] key
7600  *   Flow matcher value.
7601  * @param[in] item
7602  *   Flow pattern to translate.
7603  */
7604 static void
7605 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7606                             void *matcher, void *key,
7607                             const struct rte_flow_item *item)
7608 {
7609         struct mlx5_priv *priv = dev->data->dev_private;
7610         const struct rte_flow_item_mark *mark;
7611         uint32_t value;
7612         uint32_t mask;
7613
7614         mark = item->mask ? (const void *)item->mask :
7615                             &rte_flow_item_mark_mask;
7616         mask = mark->id & priv->sh->dv_mark_mask;
7617         mark = (const void *)item->spec;
7618         MLX5_ASSERT(mark);
7619         value = mark->id & priv->sh->dv_mark_mask & mask;
7620         if (mask) {
7621                 enum modify_reg reg;
7622
7623                 /* Get the metadata register index for the mark. */
7624                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7625                 MLX5_ASSERT(reg > 0);
7626                 if (reg == REG_C_0) {
7627                         struct mlx5_priv *priv = dev->data->dev_private;
7628                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7629                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7630
7631                         mask &= msk_c0;
7632                         mask <<= shl_c0;
7633                         value <<= shl_c0;
7634                 }
7635                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7636         }
7637 }
7638
7639 /**
7640  * Add META item to matcher
7641  *
7642  * @param[in] dev
7643  *   The devich to configure through.
7644  * @param[in, out] matcher
7645  *   Flow matcher.
7646  * @param[in, out] key
7647  *   Flow matcher value.
7648  * @param[in] attr
7649  *   Attributes of flow that includes this item.
7650  * @param[in] item
7651  *   Flow pattern to translate.
7652  */
7653 static void
7654 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7655                             void *matcher, void *key,
7656                             const struct rte_flow_attr *attr,
7657                             const struct rte_flow_item *item)
7658 {
7659         const struct rte_flow_item_meta *meta_m;
7660         const struct rte_flow_item_meta *meta_v;
7661
7662         meta_m = (const void *)item->mask;
7663         if (!meta_m)
7664                 meta_m = &rte_flow_item_meta_mask;
7665         meta_v = (const void *)item->spec;
7666         if (meta_v) {
7667                 int reg;
7668                 uint32_t value = meta_v->data;
7669                 uint32_t mask = meta_m->data;
7670
7671                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7672                 if (reg < 0)
7673                         return;
7674                 MLX5_ASSERT(reg != REG_NON);
7675                 /*
7676                  * In datapath code there is no endianness
7677                  * coversions for perfromance reasons, all
7678                  * pattern conversions are done in rte_flow.
7679                  */
7680                 value = rte_cpu_to_be_32(value);
7681                 mask = rte_cpu_to_be_32(mask);
7682                 if (reg == REG_C_0) {
7683                         struct mlx5_priv *priv = dev->data->dev_private;
7684                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7685                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7686 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7687                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7688
7689                         value >>= shr_c0;
7690                         mask >>= shr_c0;
7691 #endif
7692                         value <<= shl_c0;
7693                         mask <<= shl_c0;
7694                         MLX5_ASSERT(msk_c0);
7695                         MLX5_ASSERT(!(~msk_c0 & mask));
7696                 }
7697                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7698         }
7699 }
7700
7701 /**
7702  * Add vport metadata Reg C0 item to matcher
7703  *
7704  * @param[in, out] matcher
7705  *   Flow matcher.
7706  * @param[in, out] key
7707  *   Flow matcher value.
7708  * @param[in] reg
7709  *   Flow pattern to translate.
7710  */
7711 static void
7712 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7713                                   uint32_t value, uint32_t mask)
7714 {
7715         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7716 }
7717
7718 /**
7719  * Add tag item to matcher
7720  *
7721  * @param[in] dev
7722  *   The devich to configure through.
7723  * @param[in, out] matcher
7724  *   Flow matcher.
7725  * @param[in, out] key
7726  *   Flow matcher value.
7727  * @param[in] item
7728  *   Flow pattern to translate.
7729  */
7730 static void
7731 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7732                                 void *matcher, void *key,
7733                                 const struct rte_flow_item *item)
7734 {
7735         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7736         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7737         uint32_t mask, value;
7738
7739         MLX5_ASSERT(tag_v);
7740         value = tag_v->data;
7741         mask = tag_m ? tag_m->data : UINT32_MAX;
7742         if (tag_v->id == REG_C_0) {
7743                 struct mlx5_priv *priv = dev->data->dev_private;
7744                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7745                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7746
7747                 mask &= msk_c0;
7748                 mask <<= shl_c0;
7749                 value <<= shl_c0;
7750         }
7751         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7752 }
7753
7754 /**
7755  * Add TAG item to matcher
7756  *
7757  * @param[in] dev
7758  *   The devich to configure through.
7759  * @param[in, out] matcher
7760  *   Flow matcher.
7761  * @param[in, out] key
7762  *   Flow matcher value.
7763  * @param[in] item
7764  *   Flow pattern to translate.
7765  */
7766 static void
7767 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7768                            void *matcher, void *key,
7769                            const struct rte_flow_item *item)
7770 {
7771         const struct rte_flow_item_tag *tag_v = item->spec;
7772         const struct rte_flow_item_tag *tag_m = item->mask;
7773         enum modify_reg reg;
7774
7775         MLX5_ASSERT(tag_v);
7776         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7777         /* Get the metadata register index for the tag. */
7778         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7779         MLX5_ASSERT(reg > 0);
7780         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7781 }
7782
7783 /**
7784  * Add source vport match to the specified matcher.
7785  *
7786  * @param[in, out] matcher
7787  *   Flow matcher.
7788  * @param[in, out] key
7789  *   Flow matcher value.
7790  * @param[in] port
7791  *   Source vport value to match
7792  * @param[in] mask
7793  *   Mask
7794  */
7795 static void
7796 flow_dv_translate_item_source_vport(void *matcher, void *key,
7797                                     int16_t port, uint16_t mask)
7798 {
7799         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7800         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7801
7802         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7803         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7804 }
7805
7806 /**
7807  * Translate port-id item to eswitch match on  port-id.
7808  *
7809  * @param[in] dev
7810  *   The devich to configure through.
7811  * @param[in, out] matcher
7812  *   Flow matcher.
7813  * @param[in, out] key
7814  *   Flow matcher value.
7815  * @param[in] item
7816  *   Flow pattern to translate.
7817  * @param[in]
7818  *   Flow attributes.
7819  *
7820  * @return
7821  *   0 on success, a negative errno value otherwise.
7822  */
7823 static int
7824 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7825                                void *key, const struct rte_flow_item *item,
7826                                const struct rte_flow_attr *attr)
7827 {
7828         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7829         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7830         struct mlx5_priv *priv;
7831         uint16_t mask, id;
7832
7833         mask = pid_m ? pid_m->id : 0xffff;
7834         id = pid_v ? pid_v->id : dev->data->port_id;
7835         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7836         if (!priv)
7837                 return -rte_errno;
7838         /*
7839          * Translate to vport field or to metadata, depending on mode.
7840          * Kernel can use either misc.source_port or half of C0 metadata
7841          * register.
7842          */
7843         if (priv->vport_meta_mask) {
7844                 /*
7845                  * Provide the hint for SW steering library
7846                  * to insert the flow into ingress domain and
7847                  * save the extra vport match.
7848                  */
7849                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7850                     priv->pf_bond < 0 && attr->transfer)
7851                         flow_dv_translate_item_source_vport
7852                                 (matcher, key, priv->vport_id, mask);
7853                 else
7854                         flow_dv_translate_item_meta_vport
7855                                 (matcher, key,
7856                                  priv->vport_meta_tag,
7857                                  priv->vport_meta_mask);
7858         } else {
7859                 flow_dv_translate_item_source_vport(matcher, key,
7860                                                     priv->vport_id, mask);
7861         }
7862         return 0;
7863 }
7864
7865 /**
7866  * Add ICMP6 item to matcher and to the value.
7867  *
7868  * @param[in, out] matcher
7869  *   Flow matcher.
7870  * @param[in, out] key
7871  *   Flow matcher value.
7872  * @param[in] item
7873  *   Flow pattern to translate.
7874  * @param[in] inner
7875  *   Item is inner pattern.
7876  */
7877 static void
7878 flow_dv_translate_item_icmp6(void *matcher, void *key,
7879                               const struct rte_flow_item *item,
7880                               int inner)
7881 {
7882         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7883         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7884         void *headers_m;
7885         void *headers_v;
7886         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7887                                      misc_parameters_3);
7888         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7889         if (inner) {
7890                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7891                                          inner_headers);
7892                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7893         } else {
7894                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7895                                          outer_headers);
7896                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7897         }
7898         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7899         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7900         if (!icmp6_v)
7901                 return;
7902         if (!icmp6_m)
7903                 icmp6_m = &rte_flow_item_icmp6_mask;
7904         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7905         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7906                  icmp6_v->type & icmp6_m->type);
7907         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7908         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7909                  icmp6_v->code & icmp6_m->code);
7910 }
7911
7912 /**
7913  * Add ICMP item to matcher and to the value.
7914  *
7915  * @param[in, out] matcher
7916  *   Flow matcher.
7917  * @param[in, out] key
7918  *   Flow matcher value.
7919  * @param[in] item
7920  *   Flow pattern to translate.
7921  * @param[in] inner
7922  *   Item is inner pattern.
7923  */
7924 static void
7925 flow_dv_translate_item_icmp(void *matcher, void *key,
7926                             const struct rte_flow_item *item,
7927                             int inner)
7928 {
7929         const struct rte_flow_item_icmp *icmp_m = item->mask;
7930         const struct rte_flow_item_icmp *icmp_v = item->spec;
7931         uint32_t icmp_header_data_m = 0;
7932         uint32_t icmp_header_data_v = 0;
7933         void *headers_m;
7934         void *headers_v;
7935         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7936                                      misc_parameters_3);
7937         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7938         if (inner) {
7939                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7940                                          inner_headers);
7941                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7942         } else {
7943                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7944                                          outer_headers);
7945                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7946         }
7947         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7948         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7949         if (!icmp_v)
7950                 return;
7951         if (!icmp_m)
7952                 icmp_m = &rte_flow_item_icmp_mask;
7953         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7954                  icmp_m->hdr.icmp_type);
7955         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7956                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7957         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7958                  icmp_m->hdr.icmp_code);
7959         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7960                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7961         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7962         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7963         if (icmp_header_data_m) {
7964                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7965                 icmp_header_data_v |=
7966                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7967                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7968                          icmp_header_data_m);
7969                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7970                          icmp_header_data_v & icmp_header_data_m);
7971         }
7972 }
7973
7974 /**
7975  * Add GTP item to matcher and to the value.
7976  *
7977  * @param[in, out] matcher
7978  *   Flow matcher.
7979  * @param[in, out] key
7980  *   Flow matcher value.
7981  * @param[in] item
7982  *   Flow pattern to translate.
7983  * @param[in] inner
7984  *   Item is inner pattern.
7985  */
7986 static void
7987 flow_dv_translate_item_gtp(void *matcher, void *key,
7988                            const struct rte_flow_item *item, int inner)
7989 {
7990         const struct rte_flow_item_gtp *gtp_m = item->mask;
7991         const struct rte_flow_item_gtp *gtp_v = item->spec;
7992         void *headers_m;
7993         void *headers_v;
7994         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7995                                      misc_parameters_3);
7996         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7997         uint16_t dport = RTE_GTPU_UDP_PORT;
7998
7999         if (inner) {
8000                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8001                                          inner_headers);
8002                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8003         } else {
8004                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8005                                          outer_headers);
8006                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8007         }
8008         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8009                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8010                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8011         }
8012         if (!gtp_v)
8013                 return;
8014         if (!gtp_m)
8015                 gtp_m = &rte_flow_item_gtp_mask;
8016         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8017                  gtp_m->v_pt_rsv_flags);
8018         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8019                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8020         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8021         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8022                  gtp_v->msg_type & gtp_m->msg_type);
8023         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8024                  rte_be_to_cpu_32(gtp_m->teid));
8025         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8026                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8027 }
8028
8029 /**
8030  * Add GTP PSC item to matcher.
8031  *
8032  * @param[in, out] matcher
8033  *   Flow matcher.
8034  * @param[in, out] key
8035  *   Flow matcher value.
8036  * @param[in] item
8037  *   Flow pattern to translate.
8038  */
8039 static int
8040 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8041                                const struct rte_flow_item *item)
8042 {
8043         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8044         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8045         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8046                         misc_parameters_3);
8047         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8048         union {
8049                 uint32_t w32;
8050                 struct {
8051                         uint16_t seq_num;
8052                         uint8_t npdu_num;
8053                         uint8_t next_ext_header_type;
8054                 };
8055         } dw_2;
8056         uint8_t gtp_flags;
8057
8058         /* Always set E-flag match on one, regardless of GTP item settings. */
8059         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8060         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8061         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8062         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8063         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8064         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8065         /*Set next extension header type. */
8066         dw_2.seq_num = 0;
8067         dw_2.npdu_num = 0;
8068         dw_2.next_ext_header_type = 0xff;
8069         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8070                  rte_cpu_to_be_32(dw_2.w32));
8071         dw_2.seq_num = 0;
8072         dw_2.npdu_num = 0;
8073         dw_2.next_ext_header_type = 0x85;
8074         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8075                  rte_cpu_to_be_32(dw_2.w32));
8076         if (gtp_psc_v) {
8077                 union {
8078                         uint32_t w32;
8079                         struct {
8080                                 uint8_t len;
8081                                 uint8_t type_flags;
8082                                 uint8_t qfi;
8083                                 uint8_t reserved;
8084                         };
8085                 } dw_0;
8086
8087                 /*Set extension header PDU type and Qos. */
8088                 if (!gtp_psc_m)
8089                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8090                 dw_0.w32 = 0;
8091                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8092                 dw_0.qfi = gtp_psc_m->qfi;
8093                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8094                          rte_cpu_to_be_32(dw_0.w32));
8095                 dw_0.w32 = 0;
8096                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8097                                                         gtp_psc_m->pdu_type);
8098                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8099                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8100                          rte_cpu_to_be_32(dw_0.w32));
8101         }
8102         return 0;
8103 }
8104
8105 /**
8106  * Add eCPRI item to matcher and to the value.
8107  *
8108  * @param[in] dev
8109  *   The devich to configure through.
8110  * @param[in, out] matcher
8111  *   Flow matcher.
8112  * @param[in, out] key
8113  *   Flow matcher value.
8114  * @param[in] item
8115  *   Flow pattern to translate.
8116  * @param[in] samples
8117  *   Sample IDs to be used in the matching.
8118  */
8119 static void
8120 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8121                              void *key, const struct rte_flow_item *item)
8122 {
8123         struct mlx5_priv *priv = dev->data->dev_private;
8124         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8125         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8126         struct rte_ecpri_common_hdr common;
8127         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8128                                      misc_parameters_4);
8129         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8130         uint32_t *samples;
8131         void *dw_m;
8132         void *dw_v;
8133
8134         if (!ecpri_v)
8135                 return;
8136         if (!ecpri_m)
8137                 ecpri_m = &rte_flow_item_ecpri_mask;
8138         /*
8139          * Maximal four DW samples are supported in a single matching now.
8140          * Two are used now for a eCPRI matching:
8141          * 1. Type: one byte, mask should be 0x00ff0000 in network order
8142          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8143          *    if any.
8144          */
8145         if (!ecpri_m->hdr.common.u32)
8146                 return;
8147         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8148         /* Need to take the whole DW as the mask to fill the entry. */
8149         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8150                             prog_sample_field_value_0);
8151         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8152                             prog_sample_field_value_0);
8153         /* Already big endian (network order) in the header. */
8154         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8155         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8156         /* Sample#0, used for matching type, offset 0. */
8157         MLX5_SET(fte_match_set_misc4, misc4_m,
8158                  prog_sample_field_id_0, samples[0]);
8159         /* It makes no sense to set the sample ID in the mask field. */
8160         MLX5_SET(fte_match_set_misc4, misc4_v,
8161                  prog_sample_field_id_0, samples[0]);
8162         /*
8163          * Checking if message body part needs to be matched.
8164          * Some wildcard rules only matching type field should be supported.
8165          */
8166         if (ecpri_m->hdr.dummy[0]) {
8167                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8168                 switch (common.type) {
8169                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8170                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8171                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8172                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8173                                             prog_sample_field_value_1);
8174                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8175                                             prog_sample_field_value_1);
8176                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8177                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8178                                             ecpri_m->hdr.dummy[0];
8179                         /* Sample#1, to match message body, offset 4. */
8180                         MLX5_SET(fte_match_set_misc4, misc4_m,
8181                                  prog_sample_field_id_1, samples[1]);
8182                         MLX5_SET(fte_match_set_misc4, misc4_v,
8183                                  prog_sample_field_id_1, samples[1]);
8184                         break;
8185                 default:
8186                         /* Others, do not match any sample ID. */
8187                         break;
8188                 }
8189         }
8190 }
8191
8192 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8193
8194 #define HEADER_IS_ZERO(match_criteria, headers)                              \
8195         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
8196                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8197
8198 /**
8199  * Calculate flow matcher enable bitmap.
8200  *
8201  * @param match_criteria
8202  *   Pointer to flow matcher criteria.
8203  *
8204  * @return
8205  *   Bitmap of enabled fields.
8206  */
8207 static uint8_t
8208 flow_dv_matcher_enable(uint32_t *match_criteria)
8209 {
8210         uint8_t match_criteria_enable;
8211
8212         match_criteria_enable =
8213                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8214                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8215         match_criteria_enable |=
8216                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8217                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8218         match_criteria_enable |=
8219                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8220                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8221         match_criteria_enable |=
8222                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8223                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8224         match_criteria_enable |=
8225                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8226                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8227         match_criteria_enable |=
8228                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8229                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8230         return match_criteria_enable;
8231 }
8232
8233 struct mlx5_hlist_entry *
8234 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8235 {
8236         struct mlx5_dev_ctx_shared *sh = list->ctx;
8237         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8238         struct rte_eth_dev *dev = ctx->dev;
8239         struct mlx5_flow_tbl_data_entry *tbl_data;
8240         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8241         struct rte_flow_error *error = ctx->error;
8242         union mlx5_flow_tbl_key key = { .v64 = key64 };
8243         struct mlx5_flow_tbl_resource *tbl;
8244         void *domain;
8245         uint32_t idx = 0;
8246         int ret;
8247
8248         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8249         if (!tbl_data) {
8250                 rte_flow_error_set(error, ENOMEM,
8251                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8252                                    NULL,
8253                                    "cannot allocate flow table data entry");
8254                 return NULL;
8255         }
8256         tbl_data->idx = idx;
8257         tbl_data->tunnel = tt_prm->tunnel;
8258         tbl_data->group_id = tt_prm->group_id;
8259         tbl_data->external = !!tt_prm->external;
8260         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8261         tbl_data->is_egress = !!key.direction;
8262         tbl_data->is_transfer = !!key.domain;
8263         tbl_data->dummy = !!key.dummy;
8264         tbl_data->table_id = key.table_id;
8265         tbl = &tbl_data->tbl;
8266         if (key.dummy)
8267                 return &tbl_data->entry;
8268         if (key.domain)
8269                 domain = sh->fdb_domain;
8270         else if (key.direction)
8271                 domain = sh->tx_domain;
8272         else
8273                 domain = sh->rx_domain;
8274         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8275         if (ret) {
8276                 rte_flow_error_set(error, ENOMEM,
8277                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8278                                    NULL, "cannot create flow table object");
8279                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8280                 return NULL;
8281         }
8282         if (key.table_id) {
8283                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8284                                         (tbl->obj, &tbl_data->jump.action);
8285                 if (ret) {
8286                         rte_flow_error_set(error, ENOMEM,
8287                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8288                                            NULL,
8289                                            "cannot create flow jump action");
8290                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8291                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8292                         return NULL;
8293                 }
8294         }
8295         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8296               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8297               key.table_id);
8298         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8299                              flow_dv_matcher_create_cb,
8300                              flow_dv_matcher_match_cb,
8301                              flow_dv_matcher_remove_cb);
8302         return &tbl_data->entry;
8303 }
8304
8305 int
8306 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8307                      struct mlx5_hlist_entry *entry, uint64_t key64,
8308                      void *cb_ctx __rte_unused)
8309 {
8310         struct mlx5_flow_tbl_data_entry *tbl_data =
8311                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8312         union mlx5_flow_tbl_key key = { .v64 = key64 };
8313
8314         return tbl_data->table_id != key.table_id ||
8315                tbl_data->dummy != key.dummy ||
8316                tbl_data->is_transfer != key.domain ||
8317                tbl_data->is_egress != key.direction;
8318 }
8319
8320 /**
8321  * Get a flow table.
8322  *
8323  * @param[in, out] dev
8324  *   Pointer to rte_eth_dev structure.
8325  * @param[in] table_id
8326  *   Table id to use.
8327  * @param[in] egress
8328  *   Direction of the table.
8329  * @param[in] transfer
8330  *   E-Switch or NIC flow.
8331  * @param[in] dummy
8332  *   Dummy entry for dv API.
8333  * @param[out] error
8334  *   pointer to error structure.
8335  *
8336  * @return
8337  *   Returns tables resource based on the index, NULL in case of failed.
8338  */
8339 struct mlx5_flow_tbl_resource *
8340 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8341                          uint32_t table_id, uint8_t egress,
8342                          uint8_t transfer,
8343                          bool external,
8344                          const struct mlx5_flow_tunnel *tunnel,
8345                          uint32_t group_id, uint8_t dummy,
8346                          struct rte_flow_error *error)
8347 {
8348         struct mlx5_priv *priv = dev->data->dev_private;
8349         union mlx5_flow_tbl_key table_key = {
8350                 {
8351                         .table_id = table_id,
8352                         .dummy = dummy,
8353                         .domain = !!transfer,
8354                         .direction = !!egress,
8355                 }
8356         };
8357         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8358                 .tunnel = tunnel,
8359                 .group_id = group_id,
8360                 .external = external,
8361         };
8362         struct mlx5_flow_cb_ctx ctx = {
8363                 .dev = dev,
8364                 .error = error,
8365                 .data = &tt_prm,
8366         };
8367         struct mlx5_hlist_entry *entry;
8368         struct mlx5_flow_tbl_data_entry *tbl_data;
8369
8370         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8371         if (!entry) {
8372                 rte_flow_error_set(error, ENOMEM,
8373                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8374                                    "cannot get table");
8375                 return NULL;
8376         }
8377         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8378                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8379         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8380         return &tbl_data->tbl;
8381 }
8382
8383 void
8384 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8385                       struct mlx5_hlist_entry *entry)
8386 {
8387         struct mlx5_dev_ctx_shared *sh = list->ctx;
8388         struct mlx5_flow_tbl_data_entry *tbl_data =
8389                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8390
8391         MLX5_ASSERT(entry && sh);
8392         if (tbl_data->jump.action)
8393                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8394         if (tbl_data->tbl.obj)
8395                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8396         if (tbl_data->tunnel_offload && tbl_data->external) {
8397                 struct mlx5_hlist_entry *he;
8398                 struct mlx5_hlist *tunnel_grp_hash;
8399                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8400                 union tunnel_tbl_key tunnel_key = {
8401                         .tunnel_id = tbl_data->tunnel ?
8402                                         tbl_data->tunnel->tunnel_id : 0,
8403                         .group = tbl_data->group_id
8404                 };
8405                 uint32_t table_id = tbl_data->table_id;
8406
8407                 tunnel_grp_hash = tbl_data->tunnel ?
8408                                         tbl_data->tunnel->groups :
8409                                         thub->groups;
8410                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8411                 if (he)
8412                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8413                 DRV_LOG(DEBUG,
8414                         "Table_id %u tunnel %u group %u released.",
8415                         table_id,
8416                         tbl_data->tunnel ?
8417                         tbl_data->tunnel->tunnel_id : 0,
8418                         tbl_data->group_id);
8419         }
8420         mlx5_cache_list_destroy(&tbl_data->matchers);
8421         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8422 }
8423
8424 /**
8425  * Release a flow table.
8426  *
8427  * @param[in] sh
8428  *   Pointer to device shared structure.
8429  * @param[in] tbl
8430  *   Table resource to be released.
8431  *
8432  * @return
8433  *   Returns 0 if table was released, else return 1;
8434  */
8435 static int
8436 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8437                              struct mlx5_flow_tbl_resource *tbl)
8438 {
8439         struct mlx5_flow_tbl_data_entry *tbl_data =
8440                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8441
8442         if (!tbl)
8443                 return 0;
8444         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8445 }
8446
8447 int
8448 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8449                          struct mlx5_cache_entry *entry, void *cb_ctx)
8450 {
8451         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8452         struct mlx5_flow_dv_matcher *ref = ctx->data;
8453         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8454                                                         entry);
8455
8456         return cur->crc != ref->crc ||
8457                cur->priority != ref->priority ||
8458                memcmp((const void *)cur->mask.buf,
8459                       (const void *)ref->mask.buf, ref->mask.size);
8460 }
8461
8462 struct mlx5_cache_entry *
8463 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8464                           struct mlx5_cache_entry *entry __rte_unused,
8465                           void *cb_ctx)
8466 {
8467         struct mlx5_dev_ctx_shared *sh = list->ctx;
8468         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8469         struct mlx5_flow_dv_matcher *ref = ctx->data;
8470         struct mlx5_flow_dv_matcher *cache;
8471         struct mlx5dv_flow_matcher_attr dv_attr = {
8472                 .type = IBV_FLOW_ATTR_NORMAL,
8473                 .match_mask = (void *)&ref->mask,
8474         };
8475         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8476                                                             typeof(*tbl), tbl);
8477         int ret;
8478
8479         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8480         if (!cache) {
8481                 rte_flow_error_set(ctx->error, ENOMEM,
8482                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8483                                    "cannot create matcher");
8484                 return NULL;
8485         }
8486         *cache = *ref;
8487         dv_attr.match_criteria_enable =
8488                 flow_dv_matcher_enable(cache->mask.buf);
8489         dv_attr.priority = ref->priority;
8490         if (tbl->is_egress)
8491                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8492         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8493                                                &cache->matcher_object);
8494         if (ret) {
8495                 mlx5_free(cache);
8496                 rte_flow_error_set(ctx->error, ENOMEM,
8497                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8498                                    "cannot create matcher");
8499                 return NULL;
8500         }
8501         return &cache->entry;
8502 }
8503
8504 /**
8505  * Register the flow matcher.
8506  *
8507  * @param[in, out] dev
8508  *   Pointer to rte_eth_dev structure.
8509  * @param[in, out] matcher
8510  *   Pointer to flow matcher.
8511  * @param[in, out] key
8512  *   Pointer to flow table key.
8513  * @parm[in, out] dev_flow
8514  *   Pointer to the dev_flow.
8515  * @param[out] error
8516  *   pointer to error structure.
8517  *
8518  * @return
8519  *   0 on success otherwise -errno and errno is set.
8520  */
8521 static int
8522 flow_dv_matcher_register(struct rte_eth_dev *dev,
8523                          struct mlx5_flow_dv_matcher *ref,
8524                          union mlx5_flow_tbl_key *key,
8525                          struct mlx5_flow *dev_flow,
8526                          const struct mlx5_flow_tunnel *tunnel,
8527                          uint32_t group_id,
8528                          struct rte_flow_error *error)
8529 {
8530         struct mlx5_cache_entry *entry;
8531         struct mlx5_flow_dv_matcher *cache;
8532         struct mlx5_flow_tbl_resource *tbl;
8533         struct mlx5_flow_tbl_data_entry *tbl_data;
8534         struct mlx5_flow_cb_ctx ctx = {
8535                 .error = error,
8536                 .data = ref,
8537         };
8538
8539         /**
8540          * tunnel offload API requires this registration for cases when
8541          * tunnel match rule was inserted before tunnel set rule.
8542          */
8543         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8544                                        key->direction, key->domain,
8545                                        dev_flow->external, tunnel,
8546                                        group_id, 0, error);
8547         if (!tbl)
8548                 return -rte_errno;      /* No need to refill the error info */
8549         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8550         ref->tbl = tbl;
8551         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8552         if (!entry) {
8553                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8554                 return rte_flow_error_set(error, ENOMEM,
8555                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8556                                           "cannot allocate ref memory");
8557         }
8558         cache = container_of(entry, typeof(*cache), entry);
8559         dev_flow->handle->dvh.matcher = cache;
8560         return 0;
8561 }
8562
8563 struct mlx5_hlist_entry *
8564 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8565 {
8566         struct mlx5_dev_ctx_shared *sh = list->ctx;
8567         struct rte_flow_error *error = ctx;
8568         struct mlx5_flow_dv_tag_resource *entry;
8569         uint32_t idx = 0;
8570         int ret;
8571
8572         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8573         if (!entry) {
8574                 rte_flow_error_set(error, ENOMEM,
8575                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8576                                    "cannot allocate resource memory");
8577                 return NULL;
8578         }
8579         entry->idx = idx;
8580         entry->tag_id = key;
8581         ret = mlx5_flow_os_create_flow_action_tag(key,
8582                                                   &entry->action);
8583         if (ret) {
8584                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8585                 rte_flow_error_set(error, ENOMEM,
8586                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8587                                    NULL, "cannot create action");
8588                 return NULL;
8589         }
8590         return &entry->entry;
8591 }
8592
8593 int
8594 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8595                      struct mlx5_hlist_entry *entry, uint64_t key,
8596                      void *cb_ctx __rte_unused)
8597 {
8598         struct mlx5_flow_dv_tag_resource *tag =
8599                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8600
8601         return key != tag->tag_id;
8602 }
8603
8604 /**
8605  * Find existing tag resource or create and register a new one.
8606  *
8607  * @param dev[in, out]
8608  *   Pointer to rte_eth_dev structure.
8609  * @param[in, out] tag_be24
8610  *   Tag value in big endian then R-shift 8.
8611  * @parm[in, out] dev_flow
8612  *   Pointer to the dev_flow.
8613  * @param[out] error
8614  *   pointer to error structure.
8615  *
8616  * @return
8617  *   0 on success otherwise -errno and errno is set.
8618  */
8619 static int
8620 flow_dv_tag_resource_register
8621                         (struct rte_eth_dev *dev,
8622                          uint32_t tag_be24,
8623                          struct mlx5_flow *dev_flow,
8624                          struct rte_flow_error *error)
8625 {
8626         struct mlx5_priv *priv = dev->data->dev_private;
8627         struct mlx5_flow_dv_tag_resource *cache_resource;
8628         struct mlx5_hlist_entry *entry;
8629
8630         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8631         if (entry) {
8632                 cache_resource = container_of
8633                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8634                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8635                 dev_flow->dv.tag_resource = cache_resource;
8636                 return 0;
8637         }
8638         return -rte_errno;
8639 }
8640
8641 void
8642 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8643                       struct mlx5_hlist_entry *entry)
8644 {
8645         struct mlx5_dev_ctx_shared *sh = list->ctx;
8646         struct mlx5_flow_dv_tag_resource *tag =
8647                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8648
8649         MLX5_ASSERT(tag && sh && tag->action);
8650         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8651         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8652         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8653 }
8654
8655 /**
8656  * Release the tag.
8657  *
8658  * @param dev
8659  *   Pointer to Ethernet device.
8660  * @param tag_idx
8661  *   Tag index.
8662  *
8663  * @return
8664  *   1 while a reference on it exists, 0 when freed.
8665  */
8666 static int
8667 flow_dv_tag_release(struct rte_eth_dev *dev,
8668                     uint32_t tag_idx)
8669 {
8670         struct mlx5_priv *priv = dev->data->dev_private;
8671         struct mlx5_flow_dv_tag_resource *tag;
8672
8673         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8674         if (!tag)
8675                 return 0;
8676         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8677                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8678         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8679 }
8680
8681 /**
8682  * Translate port ID action to vport.
8683  *
8684  * @param[in] dev
8685  *   Pointer to rte_eth_dev structure.
8686  * @param[in] action
8687  *   Pointer to the port ID action.
8688  * @param[out] dst_port_id
8689  *   The target port ID.
8690  * @param[out] error
8691  *   Pointer to the error structure.
8692  *
8693  * @return
8694  *   0 on success, a negative errno value otherwise and rte_errno is set.
8695  */
8696 static int
8697 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8698                                  const struct rte_flow_action *action,
8699                                  uint32_t *dst_port_id,
8700                                  struct rte_flow_error *error)
8701 {
8702         uint32_t port;
8703         struct mlx5_priv *priv;
8704         const struct rte_flow_action_port_id *conf =
8705                         (const struct rte_flow_action_port_id *)action->conf;
8706
8707         port = conf->original ? dev->data->port_id : conf->id;
8708         priv = mlx5_port_to_eswitch_info(port, false);
8709         if (!priv)
8710                 return rte_flow_error_set(error, -rte_errno,
8711                                           RTE_FLOW_ERROR_TYPE_ACTION,
8712                                           NULL,
8713                                           "No eswitch info was found for port");
8714 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8715         /*
8716          * This parameter is transferred to
8717          * mlx5dv_dr_action_create_dest_ib_port().
8718          */
8719         *dst_port_id = priv->dev_port;
8720 #else
8721         /*
8722          * Legacy mode, no LAG configurations is supported.
8723          * This parameter is transferred to
8724          * mlx5dv_dr_action_create_dest_vport().
8725          */
8726         *dst_port_id = priv->vport_id;
8727 #endif
8728         return 0;
8729 }
8730
8731 /**
8732  * Create a counter with aging configuration.
8733  *
8734  * @param[in] dev
8735  *   Pointer to rte_eth_dev structure.
8736  * @param[out] count
8737  *   Pointer to the counter action configuration.
8738  * @param[in] age
8739  *   Pointer to the aging action configuration.
8740  *
8741  * @return
8742  *   Index to flow counter on success, 0 otherwise.
8743  */
8744 static uint32_t
8745 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8746                                 struct mlx5_flow *dev_flow,
8747                                 const struct rte_flow_action_count *count,
8748                                 const struct rte_flow_action_age *age)
8749 {
8750         uint32_t counter;
8751         struct mlx5_age_param *age_param;
8752
8753         if (count && count->shared)
8754                 counter = flow_dv_counter_get_shared(dev, count->id);
8755         else
8756                 counter = flow_dv_counter_alloc(dev, !!age);
8757         if (!counter || age == NULL)
8758                 return counter;
8759         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8760         age_param->context = age->context ? age->context :
8761                 (void *)(uintptr_t)(dev_flow->flow_idx);
8762         age_param->timeout = age->timeout;
8763         age_param->port_id = dev->data->port_id;
8764         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8765         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8766         return counter;
8767 }
8768
8769 /**
8770  * Add Tx queue matcher
8771  *
8772  * @param[in] dev
8773  *   Pointer to the dev struct.
8774  * @param[in, out] matcher
8775  *   Flow matcher.
8776  * @param[in, out] key
8777  *   Flow matcher value.
8778  * @param[in] item
8779  *   Flow pattern to translate.
8780  * @param[in] inner
8781  *   Item is inner pattern.
8782  */
8783 static void
8784 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8785                                 void *matcher, void *key,
8786                                 const struct rte_flow_item *item)
8787 {
8788         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8789         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8790         void *misc_m =
8791                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8792         void *misc_v =
8793                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8794         struct mlx5_txq_ctrl *txq;
8795         uint32_t queue;
8796
8797
8798         queue_m = (const void *)item->mask;
8799         if (!queue_m)
8800                 return;
8801         queue_v = (const void *)item->spec;
8802         if (!queue_v)
8803                 return;
8804         txq = mlx5_txq_get(dev, queue_v->queue);
8805         if (!txq)
8806                 return;
8807         queue = txq->obj->sq->id;
8808         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8809         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8810                  queue & queue_m->queue);
8811         mlx5_txq_release(dev, queue_v->queue);
8812 }
8813
8814 /**
8815  * Set the hash fields according to the @p flow information.
8816  *
8817  * @param[in] dev_flow
8818  *   Pointer to the mlx5_flow.
8819  * @param[in] rss_desc
8820  *   Pointer to the mlx5_flow_rss_desc.
8821  */
8822 static void
8823 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8824                        struct mlx5_flow_rss_desc *rss_desc)
8825 {
8826         uint64_t items = dev_flow->handle->layers;
8827         int rss_inner = 0;
8828         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8829
8830         dev_flow->hash_fields = 0;
8831 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8832         if (rss_desc->level >= 2) {
8833                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8834                 rss_inner = 1;
8835         }
8836 #endif
8837         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8838             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8839                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8840                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8841                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8842                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8843                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8844                         else
8845                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8846                 }
8847         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8848                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8849                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8850                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8851                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8852                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8853                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8854                         else
8855                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8856                 }
8857         }
8858         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8859             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8860                 if (rss_types & ETH_RSS_UDP) {
8861                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8862                                 dev_flow->hash_fields |=
8863                                                 IBV_RX_HASH_SRC_PORT_UDP;
8864                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8865                                 dev_flow->hash_fields |=
8866                                                 IBV_RX_HASH_DST_PORT_UDP;
8867                         else
8868                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8869                 }
8870         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8871                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8872                 if (rss_types & ETH_RSS_TCP) {
8873                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8874                                 dev_flow->hash_fields |=
8875                                                 IBV_RX_HASH_SRC_PORT_TCP;
8876                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8877                                 dev_flow->hash_fields |=
8878                                                 IBV_RX_HASH_DST_PORT_TCP;
8879                         else
8880                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8881                 }
8882         }
8883 }
8884
8885 /**
8886  * Prepare an Rx Hash queue.
8887  *
8888  * @param dev
8889  *   Pointer to Ethernet device.
8890  * @param[in] dev_flow
8891  *   Pointer to the mlx5_flow.
8892  * @param[in] rss_desc
8893  *   Pointer to the mlx5_flow_rss_desc.
8894  * @param[out] hrxq_idx
8895  *   Hash Rx queue index.
8896  *
8897  * @return
8898  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8899  */
8900 static struct mlx5_hrxq *
8901 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8902                      struct mlx5_flow *dev_flow,
8903                      struct mlx5_flow_rss_desc *rss_desc,
8904                      uint32_t *hrxq_idx)
8905 {
8906         struct mlx5_priv *priv = dev->data->dev_private;
8907         struct mlx5_flow_handle *dh = dev_flow->handle;
8908         struct mlx5_hrxq *hrxq;
8909
8910         MLX5_ASSERT(rss_desc->queue_num);
8911         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8912         rss_desc->hash_fields = dev_flow->hash_fields;
8913         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8914         rss_desc->shared_rss = 0;
8915         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8916         if (!*hrxq_idx)
8917                 return NULL;
8918         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8919                               *hrxq_idx);
8920         return hrxq;
8921 }
8922
8923 /**
8924  * Release sample sub action resource.
8925  *
8926  * @param[in, out] dev
8927  *   Pointer to rte_eth_dev structure.
8928  * @param[in] act_res
8929  *   Pointer to sample sub action resource.
8930  */
8931 static void
8932 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8933                                    struct mlx5_flow_sub_actions_idx *act_res)
8934 {
8935         if (act_res->rix_hrxq) {
8936                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8937                 act_res->rix_hrxq = 0;
8938         }
8939         if (act_res->rix_encap_decap) {
8940                 flow_dv_encap_decap_resource_release(dev,
8941                                                      act_res->rix_encap_decap);
8942                 act_res->rix_encap_decap = 0;
8943         }
8944         if (act_res->rix_port_id_action) {
8945                 flow_dv_port_id_action_resource_release(dev,
8946                                                 act_res->rix_port_id_action);
8947                 act_res->rix_port_id_action = 0;
8948         }
8949         if (act_res->rix_tag) {
8950                 flow_dv_tag_release(dev, act_res->rix_tag);
8951                 act_res->rix_tag = 0;
8952         }
8953         if (act_res->cnt) {
8954                 flow_dv_counter_free(dev, act_res->cnt);
8955                 act_res->cnt = 0;
8956         }
8957 }
8958
8959 int
8960 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8961                         struct mlx5_cache_entry *entry, void *cb_ctx)
8962 {
8963         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8964         struct rte_eth_dev *dev = ctx->dev;
8965         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8966         struct mlx5_flow_dv_sample_resource *cache_resource =
8967                         container_of(entry, typeof(*cache_resource), entry);
8968
8969         if (resource->ratio == cache_resource->ratio &&
8970             resource->ft_type == cache_resource->ft_type &&
8971             resource->ft_id == cache_resource->ft_id &&
8972             resource->set_action == cache_resource->set_action &&
8973             !memcmp((void *)&resource->sample_act,
8974                     (void *)&cache_resource->sample_act,
8975                     sizeof(struct mlx5_flow_sub_actions_list))) {
8976                 /*
8977                  * Existing sample action should release the prepared
8978                  * sub-actions reference counter.
8979                  */
8980                 flow_dv_sample_sub_actions_release(dev,
8981                                                 &resource->sample_idx);
8982                 return 0;
8983         }
8984         return 1;
8985 }
8986
8987 struct mlx5_cache_entry *
8988 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8989                          struct mlx5_cache_entry *entry __rte_unused,
8990                          void *cb_ctx)
8991 {
8992         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8993         struct rte_eth_dev *dev = ctx->dev;
8994         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8995         void **sample_dv_actions = resource->sub_actions;
8996         struct mlx5_flow_dv_sample_resource *cache_resource;
8997         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8998         struct mlx5_priv *priv = dev->data->dev_private;
8999         struct mlx5_dev_ctx_shared *sh = priv->sh;
9000         struct mlx5_flow_tbl_resource *tbl;
9001         uint32_t idx = 0;
9002         const uint32_t next_ft_step = 1;
9003         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9004         uint8_t is_egress = 0;
9005         uint8_t is_transfer = 0;
9006         struct rte_flow_error *error = ctx->error;
9007
9008         /* Register new sample resource. */
9009         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9010         if (!cache_resource) {
9011                 rte_flow_error_set(error, ENOMEM,
9012                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9013                                           NULL,
9014                                           "cannot allocate resource memory");
9015                 return NULL;
9016         }
9017         *cache_resource = *resource;
9018         /* Create normal path table level */
9019         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9020                 is_transfer = 1;
9021         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9022                 is_egress = 1;
9023         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9024                                         is_egress, is_transfer,
9025                                         true, NULL, 0, 0, error);
9026         if (!tbl) {
9027                 rte_flow_error_set(error, ENOMEM,
9028                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9029                                           NULL,
9030                                           "fail to create normal path table "
9031                                           "for sample");
9032                 goto error;
9033         }
9034         int ret;
9035
9036         cache_resource->normal_path_tbl = tbl;
9037         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9038                 ret = mlx5_flow_os_create_flow_action_default_miss
9039                         (&cache_resource->default_miss);
9040                 if (!ret) {
9041                         rte_flow_error_set(error, ENOMEM,
9042                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9043                                                 NULL,
9044                                                 "cannot create default miss "
9045                                                 "action");
9046                         goto error;
9047                 }
9048                 sample_dv_actions[resource->sample_act.actions_num++] =
9049                                                 cache_resource->default_miss;
9050         }
9051         /* Create a DR sample action */
9052         sampler_attr.sample_ratio = cache_resource->ratio;
9053         sampler_attr.default_next_table = tbl->obj;
9054         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9055         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9056                                                         &sample_dv_actions[0];
9057         sampler_attr.action = cache_resource->set_action;
9058         if (mlx5_os_flow_dr_create_flow_action_sampler
9059                         (&sampler_attr, &cache_resource->verbs_action)) {
9060                 rte_flow_error_set(error, ENOMEM,
9061                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9062                                         NULL, "cannot create sample action");
9063                 goto error;
9064         }
9065         cache_resource->idx = idx;
9066         cache_resource->dev = dev;
9067         return &cache_resource->entry;
9068 error:
9069         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9070             cache_resource->default_miss)
9071                 claim_zero(mlx5_flow_os_destroy_flow_action
9072                                 (cache_resource->default_miss));
9073         else
9074                 flow_dv_sample_sub_actions_release(dev,
9075                                                    &cache_resource->sample_idx);
9076         if (cache_resource->normal_path_tbl)
9077                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9078                                 cache_resource->normal_path_tbl);
9079         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9080         return NULL;
9081
9082 }
9083
9084 /**
9085  * Find existing sample resource or create and register a new one.
9086  *
9087  * @param[in, out] dev
9088  *   Pointer to rte_eth_dev structure.
9089  * @param[in] resource
9090  *   Pointer to sample resource.
9091  * @parm[in, out] dev_flow
9092  *   Pointer to the dev_flow.
9093  * @param[out] error
9094  *   pointer to error structure.
9095  *
9096  * @return
9097  *   0 on success otherwise -errno and errno is set.
9098  */
9099 static int
9100 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9101                          struct mlx5_flow_dv_sample_resource *resource,
9102                          struct mlx5_flow *dev_flow,
9103                          struct rte_flow_error *error)
9104 {
9105         struct mlx5_flow_dv_sample_resource *cache_resource;
9106         struct mlx5_cache_entry *entry;
9107         struct mlx5_priv *priv = dev->data->dev_private;
9108         struct mlx5_flow_cb_ctx ctx = {
9109                 .dev = dev,
9110                 .error = error,
9111                 .data = resource,
9112         };
9113
9114         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9115         if (!entry)
9116                 return -rte_errno;
9117         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9118         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9119         dev_flow->dv.sample_res = cache_resource;
9120         return 0;
9121 }
9122
9123 int
9124 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9125                             struct mlx5_cache_entry *entry, void *cb_ctx)
9126 {
9127         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9128         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9129         struct rte_eth_dev *dev = ctx->dev;
9130         struct mlx5_flow_dv_dest_array_resource *cache_resource =
9131                         container_of(entry, typeof(*cache_resource), entry);
9132         uint32_t idx = 0;
9133
9134         if (resource->num_of_dest == cache_resource->num_of_dest &&
9135             resource->ft_type == cache_resource->ft_type &&
9136             !memcmp((void *)cache_resource->sample_act,
9137                     (void *)resource->sample_act,
9138                    (resource->num_of_dest *
9139                    sizeof(struct mlx5_flow_sub_actions_list)))) {
9140                 /*
9141                  * Existing sample action should release the prepared
9142                  * sub-actions reference counter.
9143                  */
9144                 for (idx = 0; idx < resource->num_of_dest; idx++)
9145                         flow_dv_sample_sub_actions_release(dev,
9146                                         &resource->sample_idx[idx]);
9147                 return 0;
9148         }
9149         return 1;
9150 }
9151
9152 struct mlx5_cache_entry *
9153 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9154                          struct mlx5_cache_entry *entry __rte_unused,
9155                          void *cb_ctx)
9156 {
9157         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9158         struct rte_eth_dev *dev = ctx->dev;
9159         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9160         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9161         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9162         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9163         struct mlx5_priv *priv = dev->data->dev_private;
9164         struct mlx5_dev_ctx_shared *sh = priv->sh;
9165         struct mlx5_flow_sub_actions_list *sample_act;
9166         struct mlx5dv_dr_domain *domain;
9167         uint32_t idx = 0, res_idx = 0;
9168         struct rte_flow_error *error = ctx->error;
9169         int ret;
9170
9171         /* Register new destination array resource. */
9172         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9173                                             &res_idx);
9174         if (!cache_resource) {
9175                 rte_flow_error_set(error, ENOMEM,
9176                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9177                                           NULL,
9178                                           "cannot allocate resource memory");
9179                 return NULL;
9180         }
9181         *cache_resource = *resource;
9182         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9183                 domain = sh->fdb_domain;
9184         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9185                 domain = sh->rx_domain;
9186         else
9187                 domain = sh->tx_domain;
9188         for (idx = 0; idx < resource->num_of_dest; idx++) {
9189                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9190                                  mlx5_malloc(MLX5_MEM_ZERO,
9191                                  sizeof(struct mlx5dv_dr_action_dest_attr),
9192                                  0, SOCKET_ID_ANY);
9193                 if (!dest_attr[idx]) {
9194                         rte_flow_error_set(error, ENOMEM,
9195                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9196                                            NULL,
9197                                            "cannot allocate resource memory");
9198                         goto error;
9199                 }
9200                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9201                 sample_act = &resource->sample_act[idx];
9202                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
9203                         dest_attr[idx]->dest = sample_act->dr_queue_action;
9204                 } else if (sample_act->action_flags ==
9205                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
9206                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9207                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9208                         dest_attr[idx]->dest_reformat->reformat =
9209                                         sample_act->dr_encap_action;
9210                         dest_attr[idx]->dest_reformat->dest =
9211                                         sample_act->dr_port_id_action;
9212                 } else if (sample_act->action_flags ==
9213                            MLX5_FLOW_ACTION_PORT_ID) {
9214                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
9215                 }
9216         }
9217         /* create a dest array actioin */
9218         ret = mlx5_os_flow_dr_create_flow_action_dest_array
9219                                                 (domain,
9220                                                  cache_resource->num_of_dest,
9221                                                  dest_attr,
9222                                                  &cache_resource->action);
9223         if (ret) {
9224                 rte_flow_error_set(error, ENOMEM,
9225                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9226                                    NULL,
9227                                    "cannot create destination array action");
9228                 goto error;
9229         }
9230         cache_resource->idx = res_idx;
9231         cache_resource->dev = dev;
9232         for (idx = 0; idx < resource->num_of_dest; idx++)
9233                 mlx5_free(dest_attr[idx]);
9234         return &cache_resource->entry;
9235 error:
9236         for (idx = 0; idx < resource->num_of_dest; idx++) {
9237                 struct mlx5_flow_sub_actions_idx *act_res =
9238                                         &cache_resource->sample_idx[idx];
9239                 if (act_res->rix_hrxq &&
9240                     !mlx5_hrxq_release(dev,
9241                                 act_res->rix_hrxq))
9242                         act_res->rix_hrxq = 0;
9243                 if (act_res->rix_encap_decap &&
9244                         !flow_dv_encap_decap_resource_release(dev,
9245                                 act_res->rix_encap_decap))
9246                         act_res->rix_encap_decap = 0;
9247                 if (act_res->rix_port_id_action &&
9248                         !flow_dv_port_id_action_resource_release(dev,
9249                                 act_res->rix_port_id_action))
9250                         act_res->rix_port_id_action = 0;
9251                 if (dest_attr[idx])
9252                         mlx5_free(dest_attr[idx]);
9253         }
9254
9255         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9256         return NULL;
9257 }
9258
9259 /**
9260  * Find existing destination array resource or create and register a new one.
9261  *
9262  * @param[in, out] dev
9263  *   Pointer to rte_eth_dev structure.
9264  * @param[in] resource
9265  *   Pointer to destination array resource.
9266  * @parm[in, out] dev_flow
9267  *   Pointer to the dev_flow.
9268  * @param[out] error
9269  *   pointer to error structure.
9270  *
9271  * @return
9272  *   0 on success otherwise -errno and errno is set.
9273  */
9274 static int
9275 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9276                          struct mlx5_flow_dv_dest_array_resource *resource,
9277                          struct mlx5_flow *dev_flow,
9278                          struct rte_flow_error *error)
9279 {
9280         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9281         struct mlx5_priv *priv = dev->data->dev_private;
9282         struct mlx5_cache_entry *entry;
9283         struct mlx5_flow_cb_ctx ctx = {
9284                 .dev = dev,
9285                 .error = error,
9286                 .data = resource,
9287         };
9288
9289         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9290         if (!entry)
9291                 return -rte_errno;
9292         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9293         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9294         dev_flow->dv.dest_array_res = cache_resource;
9295         return 0;
9296 }
9297
9298 /**
9299  * Convert Sample action to DV specification.
9300  *
9301  * @param[in] dev
9302  *   Pointer to rte_eth_dev structure.
9303  * @param[in] action
9304  *   Pointer to action structure.
9305  * @param[in, out] dev_flow
9306  *   Pointer to the mlx5_flow.
9307  * @param[in] attr
9308  *   Pointer to the flow attributes.
9309  * @param[in, out] num_of_dest
9310  *   Pointer to the num of destination.
9311  * @param[in, out] sample_actions
9312  *   Pointer to sample actions list.
9313  * @param[in, out] res
9314  *   Pointer to sample resource.
9315  * @param[out] error
9316  *   Pointer to the error structure.
9317  *
9318  * @return
9319  *   0 on success, a negative errno value otherwise and rte_errno is set.
9320  */
9321 static int
9322 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9323                                 const struct rte_flow_action *action,
9324                                 struct mlx5_flow *dev_flow,
9325                                 const struct rte_flow_attr *attr,
9326                                 uint32_t *num_of_dest,
9327                                 void **sample_actions,
9328                                 struct mlx5_flow_dv_sample_resource *res,
9329                                 struct rte_flow_error *error)
9330 {
9331         struct mlx5_priv *priv = dev->data->dev_private;
9332         const struct rte_flow_action_sample *sample_action;
9333         const struct rte_flow_action *sub_actions;
9334         const struct rte_flow_action_queue *queue;
9335         struct mlx5_flow_sub_actions_list *sample_act;
9336         struct mlx5_flow_sub_actions_idx *sample_idx;
9337         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9338         struct mlx5_flow_rss_desc *rss_desc;
9339         uint64_t action_flags = 0;
9340
9341         MLX5_ASSERT(wks);
9342         rss_desc = &wks->rss_desc;
9343         sample_act = &res->sample_act;
9344         sample_idx = &res->sample_idx;
9345         sample_action = (const struct rte_flow_action_sample *)action->conf;
9346         res->ratio = sample_action->ratio;
9347         sub_actions = sample_action->actions;
9348         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9349                 int type = sub_actions->type;
9350                 uint32_t pre_rix = 0;
9351                 void *pre_r;
9352                 switch (type) {
9353                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9354                 {
9355                         struct mlx5_hrxq *hrxq;
9356                         uint32_t hrxq_idx;
9357
9358                         queue = sub_actions->conf;
9359                         rss_desc->queue_num = 1;
9360                         rss_desc->queue[0] = queue->index;
9361                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9362                                                     rss_desc, &hrxq_idx);
9363                         if (!hrxq)
9364                                 return rte_flow_error_set
9365                                         (error, rte_errno,
9366                                          RTE_FLOW_ERROR_TYPE_ACTION,
9367                                          NULL,
9368                                          "cannot create fate queue");
9369                         sample_act->dr_queue_action = hrxq->action;
9370                         sample_idx->rix_hrxq = hrxq_idx;
9371                         sample_actions[sample_act->actions_num++] =
9372                                                 hrxq->action;
9373                         (*num_of_dest)++;
9374                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9375                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9376                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9377                         dev_flow->handle->fate_action =
9378                                         MLX5_FLOW_FATE_QUEUE;
9379                         break;
9380                 }
9381                 case RTE_FLOW_ACTION_TYPE_MARK:
9382                 {
9383                         uint32_t tag_be = mlx5_flow_mark_set
9384                                 (((const struct rte_flow_action_mark *)
9385                                 (sub_actions->conf))->id);
9386
9387                         dev_flow->handle->mark = 1;
9388                         pre_rix = dev_flow->handle->dvh.rix_tag;
9389                         /* Save the mark resource before sample */
9390                         pre_r = dev_flow->dv.tag_resource;
9391                         if (flow_dv_tag_resource_register(dev, tag_be,
9392                                                   dev_flow, error))
9393                                 return -rte_errno;
9394                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9395                         sample_act->dr_tag_action =
9396                                 dev_flow->dv.tag_resource->action;
9397                         sample_idx->rix_tag =
9398                                 dev_flow->handle->dvh.rix_tag;
9399                         sample_actions[sample_act->actions_num++] =
9400                                                 sample_act->dr_tag_action;
9401                         /* Recover the mark resource after sample */
9402                         dev_flow->dv.tag_resource = pre_r;
9403                         dev_flow->handle->dvh.rix_tag = pre_rix;
9404                         action_flags |= MLX5_FLOW_ACTION_MARK;
9405                         break;
9406                 }
9407                 case RTE_FLOW_ACTION_TYPE_COUNT:
9408                 {
9409                         uint32_t counter;
9410
9411                         counter = flow_dv_translate_create_counter(dev,
9412                                         dev_flow, sub_actions->conf, 0);
9413                         if (!counter)
9414                                 return rte_flow_error_set
9415                                                 (error, rte_errno,
9416                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9417                                                  NULL,
9418                                                  "cannot create counter"
9419                                                  " object.");
9420                         sample_idx->cnt = counter;
9421                         sample_act->dr_cnt_action =
9422                                   (flow_dv_counter_get_by_idx(dev,
9423                                   counter, NULL))->action;
9424                         sample_actions[sample_act->actions_num++] =
9425                                                 sample_act->dr_cnt_action;
9426                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9427                         break;
9428                 }
9429                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9430                 {
9431                         struct mlx5_flow_dv_port_id_action_resource
9432                                         port_id_resource;
9433                         uint32_t port_id = 0;
9434
9435                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9436                         /* Save the port id resource before sample */
9437                         pre_rix = dev_flow->handle->rix_port_id_action;
9438                         pre_r = dev_flow->dv.port_id_action;
9439                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9440                                                              &port_id, error))
9441                                 return -rte_errno;
9442                         port_id_resource.port_id = port_id;
9443                         if (flow_dv_port_id_action_resource_register
9444                             (dev, &port_id_resource, dev_flow, error))
9445                                 return -rte_errno;
9446                         sample_act->dr_port_id_action =
9447                                 dev_flow->dv.port_id_action->action;
9448                         sample_idx->rix_port_id_action =
9449                                 dev_flow->handle->rix_port_id_action;
9450                         sample_actions[sample_act->actions_num++] =
9451                                                 sample_act->dr_port_id_action;
9452                         /* Recover the port id resource after sample */
9453                         dev_flow->dv.port_id_action = pre_r;
9454                         dev_flow->handle->rix_port_id_action = pre_rix;
9455                         (*num_of_dest)++;
9456                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9457                         break;
9458                 }
9459                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9460                         /* Save the encap resource before sample */
9461                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9462                         pre_r = dev_flow->dv.encap_decap;
9463                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9464                                                            dev_flow,
9465                                                            attr->transfer,
9466                                                            error))
9467                                 return -rte_errno;
9468                         sample_act->dr_encap_action =
9469                                 dev_flow->dv.encap_decap->action;
9470                         sample_idx->rix_encap_decap =
9471                                 dev_flow->handle->dvh.rix_encap_decap;
9472                         sample_actions[sample_act->actions_num++] =
9473                                                 sample_act->dr_encap_action;
9474                         /* Recover the encap resource after sample */
9475                         dev_flow->dv.encap_decap = pre_r;
9476                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9477                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9478                         break;
9479                 default:
9480                         return rte_flow_error_set(error, EINVAL,
9481                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9482                                 NULL,
9483                                 "Not support for sampler action");
9484                 }
9485         }
9486         sample_act->action_flags = action_flags;
9487         res->ft_id = dev_flow->dv.group;
9488         if (attr->transfer) {
9489                 union {
9490                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9491                         uint64_t set_action;
9492                 } action_ctx = { .set_action = 0 };
9493
9494                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9495                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9496                          MLX5_MODIFICATION_TYPE_SET);
9497                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9498                          MLX5_MODI_META_REG_C_0);
9499                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9500                          priv->vport_meta_tag);
9501                 res->set_action = action_ctx.set_action;
9502         } else if (attr->ingress) {
9503                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9504         } else {
9505                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9506         }
9507         return 0;
9508 }
9509
9510 /**
9511  * Convert Sample action to DV specification.
9512  *
9513  * @param[in] dev
9514  *   Pointer to rte_eth_dev structure.
9515  * @param[in, out] dev_flow
9516  *   Pointer to the mlx5_flow.
9517  * @param[in] num_of_dest
9518  *   The num of destination.
9519  * @param[in, out] res
9520  *   Pointer to sample resource.
9521  * @param[in, out] mdest_res
9522  *   Pointer to destination array resource.
9523  * @param[in] sample_actions
9524  *   Pointer to sample path actions list.
9525  * @param[in] action_flags
9526  *   Holds the actions detected until now.
9527  * @param[out] error
9528  *   Pointer to the error structure.
9529  *
9530  * @return
9531  *   0 on success, a negative errno value otherwise and rte_errno is set.
9532  */
9533 static int
9534 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9535                              struct mlx5_flow *dev_flow,
9536                              uint32_t num_of_dest,
9537                              struct mlx5_flow_dv_sample_resource *res,
9538                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9539                              void **sample_actions,
9540                              uint64_t action_flags,
9541                              struct rte_flow_error *error)
9542 {
9543         /* update normal path action resource into last index of array */
9544         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9545         struct mlx5_flow_sub_actions_list *sample_act =
9546                                         &mdest_res->sample_act[dest_index];
9547         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9548         struct mlx5_flow_rss_desc *rss_desc;
9549         uint32_t normal_idx = 0;
9550         struct mlx5_hrxq *hrxq;
9551         uint32_t hrxq_idx;
9552
9553         MLX5_ASSERT(wks);
9554         rss_desc = &wks->rss_desc;
9555         if (num_of_dest > 1) {
9556                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9557                         /* Handle QP action for mirroring */
9558                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9559                                                     rss_desc, &hrxq_idx);
9560                         if (!hrxq)
9561                                 return rte_flow_error_set
9562                                      (error, rte_errno,
9563                                       RTE_FLOW_ERROR_TYPE_ACTION,
9564                                       NULL,
9565                                       "cannot create rx queue");
9566                         normal_idx++;
9567                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9568                         sample_act->dr_queue_action = hrxq->action;
9569                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9570                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9571                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9572                 }
9573                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9574                         normal_idx++;
9575                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9576                                 dev_flow->handle->dvh.rix_encap_decap;
9577                         sample_act->dr_encap_action =
9578                                 dev_flow->dv.encap_decap->action;
9579                 }
9580                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9581                         normal_idx++;
9582                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9583                                 dev_flow->handle->rix_port_id_action;
9584                         sample_act->dr_port_id_action =
9585                                 dev_flow->dv.port_id_action->action;
9586                 }
9587                 sample_act->actions_num = normal_idx;
9588                 /* update sample action resource into first index of array */
9589                 mdest_res->ft_type = res->ft_type;
9590                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9591                                 sizeof(struct mlx5_flow_sub_actions_idx));
9592                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9593                                 sizeof(struct mlx5_flow_sub_actions_list));
9594                 mdest_res->num_of_dest = num_of_dest;
9595                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9596                                                          dev_flow, error))
9597                         return rte_flow_error_set(error, EINVAL,
9598                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9599                                                   NULL, "can't create sample "
9600                                                   "action");
9601         } else {
9602                 res->sub_actions = sample_actions;
9603                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9604                         return rte_flow_error_set(error, EINVAL,
9605                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9606                                                   NULL,
9607                                                   "can't create sample action");
9608         }
9609         return 0;
9610 }
9611
9612 /**
9613  * Remove an ASO age action from age actions list.
9614  *
9615  * @param[in] dev
9616  *   Pointer to the Ethernet device structure.
9617  * @param[in] age
9618  *   Pointer to the aso age action handler.
9619  */
9620 static void
9621 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9622                                 struct mlx5_aso_age_action *age)
9623 {
9624         struct mlx5_age_info *age_info;
9625         struct mlx5_age_param *age_param = &age->age_params;
9626         struct mlx5_priv *priv = dev->data->dev_private;
9627         uint16_t expected = AGE_CANDIDATE;
9628
9629         age_info = GET_PORT_AGE_INFO(priv);
9630         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9631                                          AGE_FREE, false, __ATOMIC_RELAXED,
9632                                          __ATOMIC_RELAXED)) {
9633                 /**
9634                  * We need the lock even it is age timeout,
9635                  * since age action may still in process.
9636                  */
9637                 rte_spinlock_lock(&age_info->aged_sl);
9638                 LIST_REMOVE(age, next);
9639                 rte_spinlock_unlock(&age_info->aged_sl);
9640                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9641         }
9642 }
9643
9644 /**
9645  * Release an ASO age action.
9646  *
9647  * @param[in] dev
9648  *   Pointer to the Ethernet device structure.
9649  * @param[in] age_idx
9650  *   Index of ASO age action to release.
9651  * @param[in] flow
9652  *   True if the release operation is during flow destroy operation.
9653  *   False if the release operation is during action destroy operation.
9654  *
9655  * @return
9656  *   0 when age action was removed, otherwise the number of references.
9657  */
9658 static int
9659 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9660 {
9661         struct mlx5_priv *priv = dev->data->dev_private;
9662         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9663         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9664         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9665
9666         if (!ret) {
9667                 flow_dv_aso_age_remove_from_age(dev, age);
9668                 rte_spinlock_lock(&mng->free_sl);
9669                 LIST_INSERT_HEAD(&mng->free, age, next);
9670                 rte_spinlock_unlock(&mng->free_sl);
9671         }
9672         return ret;
9673 }
9674
9675 /**
9676  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9677  *
9678  * @param[in] dev
9679  *   Pointer to the Ethernet device structure.
9680  *
9681  * @return
9682  *   0 on success, otherwise negative errno value and rte_errno is set.
9683  */
9684 static int
9685 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9686 {
9687         struct mlx5_priv *priv = dev->data->dev_private;
9688         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9689         void *old_pools = mng->pools;
9690         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9691         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9692         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9693
9694         if (!pools) {
9695                 rte_errno = ENOMEM;
9696                 return -ENOMEM;
9697         }
9698         if (old_pools) {
9699                 memcpy(pools, old_pools,
9700                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9701                 mlx5_free(old_pools);
9702         } else {
9703                 /* First ASO flow hit allocation - starting ASO data-path. */
9704                 int ret = mlx5_aso_queue_start(priv->sh);
9705
9706                 if (ret) {
9707                         mlx5_free(pools);
9708                         return ret;
9709                 }
9710         }
9711         mng->n = resize;
9712         mng->pools = pools;
9713         return 0;
9714 }
9715
9716 /**
9717  * Create and initialize a new ASO aging pool.
9718  *
9719  * @param[in] dev
9720  *   Pointer to the Ethernet device structure.
9721  * @param[out] age_free
9722  *   Where to put the pointer of a new age action.
9723  *
9724  * @return
9725  *   The age actions pool pointer and @p age_free is set on success,
9726  *   NULL otherwise and rte_errno is set.
9727  */
9728 static struct mlx5_aso_age_pool *
9729 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9730                         struct mlx5_aso_age_action **age_free)
9731 {
9732         struct mlx5_priv *priv = dev->data->dev_private;
9733         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9734         struct mlx5_aso_age_pool *pool = NULL;
9735         struct mlx5_devx_obj *obj = NULL;
9736         uint32_t i;
9737
9738         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9739                                                     priv->sh->pdn);
9740         if (!obj) {
9741                 rte_errno = ENODATA;
9742                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9743                 return NULL;
9744         }
9745         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9746         if (!pool) {
9747                 claim_zero(mlx5_devx_cmd_destroy(obj));
9748                 rte_errno = ENOMEM;
9749                 return NULL;
9750         }
9751         pool->flow_hit_aso_obj = obj;
9752         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9753         rte_spinlock_lock(&mng->resize_sl);
9754         pool->index = mng->next;
9755         /* Resize pools array if there is no room for the new pool in it. */
9756         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9757                 claim_zero(mlx5_devx_cmd_destroy(obj));
9758                 mlx5_free(pool);
9759                 rte_spinlock_unlock(&mng->resize_sl);
9760                 return NULL;
9761         }
9762         mng->pools[pool->index] = pool;
9763         mng->next++;
9764         rte_spinlock_unlock(&mng->resize_sl);
9765         /* Assign the first action in the new pool, the rest go to free list. */
9766         *age_free = &pool->actions[0];
9767         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9768                 pool->actions[i].offset = i;
9769                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9770         }
9771         return pool;
9772 }
9773
9774 /**
9775  * Allocate a ASO aging bit.
9776  *
9777  * @param[in] dev
9778  *   Pointer to the Ethernet device structure.
9779  * @param[out] error
9780  *   Pointer to the error structure.
9781  *
9782  * @return
9783  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9784  */
9785 static uint32_t
9786 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9787 {
9788         struct mlx5_priv *priv = dev->data->dev_private;
9789         const struct mlx5_aso_age_pool *pool;
9790         struct mlx5_aso_age_action *age_free = NULL;
9791         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9792
9793         MLX5_ASSERT(mng);
9794         /* Try to get the next free age action bit. */
9795         rte_spinlock_lock(&mng->free_sl);
9796         age_free = LIST_FIRST(&mng->free);
9797         if (age_free) {
9798                 LIST_REMOVE(age_free, next);
9799         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9800                 rte_spinlock_unlock(&mng->free_sl);
9801                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9802                                    NULL, "failed to create ASO age pool");
9803                 return 0; /* 0 is an error. */
9804         }
9805         rte_spinlock_unlock(&mng->free_sl);
9806         pool = container_of
9807           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9808                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9809                                                                        actions);
9810         if (!age_free->dr_action) {
9811                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9812                                                  error);
9813
9814                 if (reg_c < 0) {
9815                         rte_flow_error_set(error, rte_errno,
9816                                            RTE_FLOW_ERROR_TYPE_ACTION,
9817                                            NULL, "failed to get reg_c "
9818                                            "for ASO flow hit");
9819                         return 0; /* 0 is an error. */
9820                 }
9821 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9822                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9823                                 (priv->sh->rx_domain,
9824                                  pool->flow_hit_aso_obj->obj, age_free->offset,
9825                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9826                                  (reg_c - REG_C_0));
9827 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9828                 if (!age_free->dr_action) {
9829                         rte_errno = errno;
9830                         rte_spinlock_lock(&mng->free_sl);
9831                         LIST_INSERT_HEAD(&mng->free, age_free, next);
9832                         rte_spinlock_unlock(&mng->free_sl);
9833                         rte_flow_error_set(error, rte_errno,
9834                                            RTE_FLOW_ERROR_TYPE_ACTION,
9835                                            NULL, "failed to create ASO "
9836                                            "flow hit action");
9837                         return 0; /* 0 is an error. */
9838                 }
9839         }
9840         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9841         return pool->index | ((age_free->offset + 1) << 16);
9842 }
9843
9844 /**
9845  * Create a age action using ASO mechanism.
9846  *
9847  * @param[in] dev
9848  *   Pointer to rte_eth_dev structure.
9849  * @param[in] age
9850  *   Pointer to the aging action configuration.
9851  * @param[out] error
9852  *   Pointer to the error structure.
9853  *
9854  * @return
9855  *   Index to flow counter on success, 0 otherwise.
9856  */
9857 static uint32_t
9858 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9859                                  const struct rte_flow_action_age *age,
9860                                  struct rte_flow_error *error)
9861 {
9862         uint32_t age_idx = 0;
9863         struct mlx5_aso_age_action *aso_age;
9864
9865         age_idx = flow_dv_aso_age_alloc(dev, error);
9866         if (!age_idx)
9867                 return 0;
9868         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9869         aso_age->age_params.context = age->context;
9870         aso_age->age_params.timeout = age->timeout;
9871         aso_age->age_params.port_id = dev->data->port_id;
9872         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9873                          __ATOMIC_RELAXED);
9874         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9875                          __ATOMIC_RELAXED);
9876         return age_idx;
9877 }
9878
9879 /**
9880  * Fill the flow with DV spec, lock free
9881  * (mutex should be acquired by caller).
9882  *
9883  * @param[in] dev
9884  *   Pointer to rte_eth_dev structure.
9885  * @param[in, out] dev_flow
9886  *   Pointer to the sub flow.
9887  * @param[in] attr
9888  *   Pointer to the flow attributes.
9889  * @param[in] items
9890  *   Pointer to the list of items.
9891  * @param[in] actions
9892  *   Pointer to the list of actions.
9893  * @param[out] error
9894  *   Pointer to the error structure.
9895  *
9896  * @return
9897  *   0 on success, a negative errno value otherwise and rte_errno is set.
9898  */
9899 static int
9900 flow_dv_translate(struct rte_eth_dev *dev,
9901                   struct mlx5_flow *dev_flow,
9902                   const struct rte_flow_attr *attr,
9903                   const struct rte_flow_item items[],
9904                   const struct rte_flow_action actions[],
9905                   struct rte_flow_error *error)
9906 {
9907         struct mlx5_priv *priv = dev->data->dev_private;
9908         struct mlx5_dev_config *dev_conf = &priv->config;
9909         struct rte_flow *flow = dev_flow->flow;
9910         struct mlx5_flow_handle *handle = dev_flow->handle;
9911         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9912         struct mlx5_flow_rss_desc *rss_desc;
9913         uint64_t item_flags = 0;
9914         uint64_t last_item = 0;
9915         uint64_t action_flags = 0;
9916         uint64_t priority = attr->priority;
9917         struct mlx5_flow_dv_matcher matcher = {
9918                 .mask = {
9919                         .size = sizeof(matcher.mask.buf) -
9920                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9921                 },
9922         };
9923         int actions_n = 0;
9924         bool actions_end = false;
9925         union {
9926                 struct mlx5_flow_dv_modify_hdr_resource res;
9927                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9928                             sizeof(struct mlx5_modification_cmd) *
9929                             (MLX5_MAX_MODIFY_NUM + 1)];
9930         } mhdr_dummy;
9931         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9932         const struct rte_flow_action_count *count = NULL;
9933         const struct rte_flow_action_age *age = NULL;
9934         union flow_dv_attr flow_attr = { .attr = 0 };
9935         uint32_t tag_be;
9936         union mlx5_flow_tbl_key tbl_key;
9937         uint32_t modify_action_position = UINT32_MAX;
9938         void *match_mask = matcher.mask.buf;
9939         void *match_value = dev_flow->dv.value.buf;
9940         uint8_t next_protocol = 0xff;
9941         struct rte_vlan_hdr vlan = { 0 };
9942         struct mlx5_flow_dv_dest_array_resource mdest_res;
9943         struct mlx5_flow_dv_sample_resource sample_res;
9944         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9945         struct mlx5_flow_sub_actions_list *sample_act;
9946         uint32_t sample_act_pos = UINT32_MAX;
9947         uint32_t num_of_dest = 0;
9948         int tmp_actions_n = 0;
9949         uint32_t table;
9950         int ret = 0;
9951         const struct mlx5_flow_tunnel *tunnel;
9952         struct flow_grp_info grp_info = {
9953                 .external = !!dev_flow->external,
9954                 .transfer = !!attr->transfer,
9955                 .fdb_def_rule = !!priv->fdb_def_rule,
9956                 .skip_scale = !!dev_flow->skip_scale,
9957         };
9958
9959         if (!wks)
9960                 return rte_flow_error_set(error, ENOMEM,
9961                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9962                                           NULL,
9963                                           "failed to push flow workspace");
9964         rss_desc = &wks->rss_desc;
9965         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9966         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9967         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9968                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9969         /* update normal path action resource into last index of array */
9970         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9971         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9972                  flow_items_to_tunnel(items) :
9973                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9974                  flow_actions_to_tunnel(actions) :
9975                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9976         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9977                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9978         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9979                                 (dev, tunnel, attr, items, actions);
9980         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9981                                        &grp_info, error);
9982         if (ret)
9983                 return ret;
9984         dev_flow->dv.group = table;
9985         if (attr->transfer)
9986                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9987         if (priority == MLX5_FLOW_PRIO_RSVD)
9988                 priority = dev_conf->flow_prio - 1;
9989         /* number of actions must be set to 0 in case of dirty stack. */
9990         mhdr_res->actions_num = 0;
9991         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9992                 /*
9993                  * do not add decap action if match rule drops packet
9994                  * HW rejects rules with decap & drop
9995                  *
9996                  * if tunnel match rule was inserted before matching tunnel set
9997                  * rule flow table used in the match rule must be registered.
9998                  * current implementation handles that in the
9999                  * flow_dv_match_register() at the function end.
10000                  */
10001                 bool add_decap = true;
10002                 const struct rte_flow_action *ptr = actions;
10003
10004                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10005                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10006                                 add_decap = false;
10007                                 break;
10008                         }
10009                 }
10010                 if (add_decap) {
10011                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10012                                                            attr->transfer,
10013                                                            error))
10014                                 return -rte_errno;
10015                         dev_flow->dv.actions[actions_n++] =
10016                                         dev_flow->dv.encap_decap->action;
10017                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10018                 }
10019         }
10020         for (; !actions_end ; actions++) {
10021                 const struct rte_flow_action_queue *queue;
10022                 const struct rte_flow_action_rss *rss;
10023                 const struct rte_flow_action *action = actions;
10024                 const uint8_t *rss_key;
10025                 const struct rte_flow_action_meter *mtr;
10026                 struct mlx5_flow_tbl_resource *tbl;
10027                 struct mlx5_aso_age_action *age_act;
10028                 uint32_t port_id = 0;
10029                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10030                 int action_type = actions->type;
10031                 const struct rte_flow_action *found_action = NULL;
10032                 struct mlx5_flow_meter *fm = NULL;
10033                 uint32_t jump_group = 0;
10034
10035                 if (!mlx5_flow_os_action_supported(action_type))
10036                         return rte_flow_error_set(error, ENOTSUP,
10037                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10038                                                   actions,
10039                                                   "action not supported");
10040                 switch (action_type) {
10041                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10042                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10043                         break;
10044                 case RTE_FLOW_ACTION_TYPE_VOID:
10045                         break;
10046                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10047                         if (flow_dv_translate_action_port_id(dev, action,
10048                                                              &port_id, error))
10049                                 return -rte_errno;
10050                         port_id_resource.port_id = port_id;
10051                         MLX5_ASSERT(!handle->rix_port_id_action);
10052                         if (flow_dv_port_id_action_resource_register
10053                             (dev, &port_id_resource, dev_flow, error))
10054                                 return -rte_errno;
10055                         dev_flow->dv.actions[actions_n++] =
10056                                         dev_flow->dv.port_id_action->action;
10057                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10058                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10059                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10060                         num_of_dest++;
10061                         break;
10062                 case RTE_FLOW_ACTION_TYPE_FLAG:
10063                         action_flags |= MLX5_FLOW_ACTION_FLAG;
10064                         dev_flow->handle->mark = 1;
10065                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10066                                 struct rte_flow_action_mark mark = {
10067                                         .id = MLX5_FLOW_MARK_DEFAULT,
10068                                 };
10069
10070                                 if (flow_dv_convert_action_mark(dev, &mark,
10071                                                                 mhdr_res,
10072                                                                 error))
10073                                         return -rte_errno;
10074                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10075                                 break;
10076                         }
10077                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10078                         /*
10079                          * Only one FLAG or MARK is supported per device flow
10080                          * right now. So the pointer to the tag resource must be
10081                          * zero before the register process.
10082                          */
10083                         MLX5_ASSERT(!handle->dvh.rix_tag);
10084                         if (flow_dv_tag_resource_register(dev, tag_be,
10085                                                           dev_flow, error))
10086                                 return -rte_errno;
10087                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10088                         dev_flow->dv.actions[actions_n++] =
10089                                         dev_flow->dv.tag_resource->action;
10090                         break;
10091                 case RTE_FLOW_ACTION_TYPE_MARK:
10092                         action_flags |= MLX5_FLOW_ACTION_MARK;
10093                         dev_flow->handle->mark = 1;
10094                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10095                                 const struct rte_flow_action_mark *mark =
10096                                         (const struct rte_flow_action_mark *)
10097                                                 actions->conf;
10098
10099                                 if (flow_dv_convert_action_mark(dev, mark,
10100                                                                 mhdr_res,
10101                                                                 error))
10102                                         return -rte_errno;
10103                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10104                                 break;
10105                         }
10106                         /* Fall-through */
10107                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10108                         /* Legacy (non-extensive) MARK action. */
10109                         tag_be = mlx5_flow_mark_set
10110                               (((const struct rte_flow_action_mark *)
10111                                (actions->conf))->id);
10112                         MLX5_ASSERT(!handle->dvh.rix_tag);
10113                         if (flow_dv_tag_resource_register(dev, tag_be,
10114                                                           dev_flow, error))
10115                                 return -rte_errno;
10116                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10117                         dev_flow->dv.actions[actions_n++] =
10118                                         dev_flow->dv.tag_resource->action;
10119                         break;
10120                 case RTE_FLOW_ACTION_TYPE_SET_META:
10121                         if (flow_dv_convert_action_set_meta
10122                                 (dev, mhdr_res, attr,
10123                                  (const struct rte_flow_action_set_meta *)
10124                                   actions->conf, error))
10125                                 return -rte_errno;
10126                         action_flags |= MLX5_FLOW_ACTION_SET_META;
10127                         break;
10128                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10129                         if (flow_dv_convert_action_set_tag
10130                                 (dev, mhdr_res,
10131                                  (const struct rte_flow_action_set_tag *)
10132                                   actions->conf, error))
10133                                 return -rte_errno;
10134                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10135                         break;
10136                 case RTE_FLOW_ACTION_TYPE_DROP:
10137                         action_flags |= MLX5_FLOW_ACTION_DROP;
10138                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10139                         break;
10140                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10141                         queue = actions->conf;
10142                         rss_desc->queue_num = 1;
10143                         rss_desc->queue[0] = queue->index;
10144                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10145                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10146                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10147                         num_of_dest++;
10148                         break;
10149                 case RTE_FLOW_ACTION_TYPE_RSS:
10150                         rss = actions->conf;
10151                         memcpy(rss_desc->queue, rss->queue,
10152                                rss->queue_num * sizeof(uint16_t));
10153                         rss_desc->queue_num = rss->queue_num;
10154                         /* NULL RSS key indicates default RSS key. */
10155                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10156                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10157                         /*
10158                          * rss->level and rss.types should be set in advance
10159                          * when expanding items for RSS.
10160                          */
10161                         action_flags |= MLX5_FLOW_ACTION_RSS;
10162                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
10163                                 MLX5_FLOW_FATE_SHARED_RSS :
10164                                 MLX5_FLOW_FATE_QUEUE;
10165                         break;
10166                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10167                         flow->age = (uint32_t)(uintptr_t)(action->conf);
10168                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
10169                         __atomic_fetch_add(&age_act->refcnt, 1,
10170                                            __ATOMIC_RELAXED);
10171                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10172                         action_flags |= MLX5_FLOW_ACTION_AGE;
10173                         break;
10174                 case RTE_FLOW_ACTION_TYPE_AGE:
10175                         if (priv->sh->flow_hit_aso_en && attr->group) {
10176                                 flow->age = flow_dv_translate_create_aso_age
10177                                                 (dev, action->conf, error);
10178                                 if (!flow->age)
10179                                         return rte_flow_error_set
10180                                                 (error, rte_errno,
10181                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10182                                                  NULL,
10183                                                  "can't create ASO age action");
10184                                 dev_flow->dv.actions[actions_n++] =
10185                                           (flow_aso_age_get_by_idx
10186                                                 (dev, flow->age))->dr_action;
10187                                 action_flags |= MLX5_FLOW_ACTION_AGE;
10188                                 break;
10189                         }
10190                         /* Fall-through */
10191                 case RTE_FLOW_ACTION_TYPE_COUNT:
10192                         if (!dev_conf->devx) {
10193                                 return rte_flow_error_set
10194                                               (error, ENOTSUP,
10195                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10196                                                NULL,
10197                                                "count action not supported");
10198                         }
10199                         /* Save information first, will apply later. */
10200                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10201                                 count = action->conf;
10202                         else
10203                                 age = action->conf;
10204                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10205                         break;
10206                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10207                         dev_flow->dv.actions[actions_n++] =
10208                                                 priv->sh->pop_vlan_action;
10209                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10210                         break;
10211                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10212                         if (!(action_flags &
10213                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10214                                 flow_dev_get_vlan_info_from_items(items, &vlan);
10215                         vlan.eth_proto = rte_be_to_cpu_16
10216                              ((((const struct rte_flow_action_of_push_vlan *)
10217                                                    actions->conf)->ethertype));
10218                         found_action = mlx5_flow_find_action
10219                                         (actions + 1,
10220                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10221                         if (found_action)
10222                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10223                         found_action = mlx5_flow_find_action
10224                                         (actions + 1,
10225                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10226                         if (found_action)
10227                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10228                         if (flow_dv_create_action_push_vlan
10229                                             (dev, attr, &vlan, dev_flow, error))
10230                                 return -rte_errno;
10231                         dev_flow->dv.actions[actions_n++] =
10232                                         dev_flow->dv.push_vlan_res->action;
10233                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10234                         break;
10235                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10236                         /* of_vlan_push action handled this action */
10237                         MLX5_ASSERT(action_flags &
10238                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10239                         break;
10240                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10241                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10242                                 break;
10243                         flow_dev_get_vlan_info_from_items(items, &vlan);
10244                         mlx5_update_vlan_vid_pcp(actions, &vlan);
10245                         /* If no VLAN push - this is a modify header action */
10246                         if (flow_dv_convert_action_modify_vlan_vid
10247                                                 (mhdr_res, actions, error))
10248                                 return -rte_errno;
10249                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10250                         break;
10251                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10252                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10253                         if (flow_dv_create_action_l2_encap(dev, actions,
10254                                                            dev_flow,
10255                                                            attr->transfer,
10256                                                            error))
10257                                 return -rte_errno;
10258                         dev_flow->dv.actions[actions_n++] =
10259                                         dev_flow->dv.encap_decap->action;
10260                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10261                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10262                                 sample_act->action_flags |=
10263                                                         MLX5_FLOW_ACTION_ENCAP;
10264                         break;
10265                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10266                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10267                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10268                                                            attr->transfer,
10269                                                            error))
10270                                 return -rte_errno;
10271                         dev_flow->dv.actions[actions_n++] =
10272                                         dev_flow->dv.encap_decap->action;
10273                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10274                         break;
10275                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10276                         /* Handle encap with preceding decap. */
10277                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10278                                 if (flow_dv_create_action_raw_encap
10279                                         (dev, actions, dev_flow, attr, error))
10280                                         return -rte_errno;
10281                                 dev_flow->dv.actions[actions_n++] =
10282                                         dev_flow->dv.encap_decap->action;
10283                         } else {
10284                                 /* Handle encap without preceding decap. */
10285                                 if (flow_dv_create_action_l2_encap
10286                                     (dev, actions, dev_flow, attr->transfer,
10287                                      error))
10288                                         return -rte_errno;
10289                                 dev_flow->dv.actions[actions_n++] =
10290                                         dev_flow->dv.encap_decap->action;
10291                         }
10292                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10293                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10294                                 sample_act->action_flags |=
10295                                                         MLX5_FLOW_ACTION_ENCAP;
10296                         break;
10297                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10298                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10299                                 ;
10300                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10301                                 if (flow_dv_create_action_l2_decap
10302                                     (dev, dev_flow, attr->transfer, error))
10303                                         return -rte_errno;
10304                                 dev_flow->dv.actions[actions_n++] =
10305                                         dev_flow->dv.encap_decap->action;
10306                         }
10307                         /* If decap is followed by encap, handle it at encap. */
10308                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10309                         break;
10310                 case RTE_FLOW_ACTION_TYPE_JUMP:
10311                         jump_group = ((const struct rte_flow_action_jump *)
10312                                                         action->conf)->group;
10313                         grp_info.std_tbl_fix = 0;
10314                         grp_info.skip_scale = 0;
10315                         ret = mlx5_flow_group_to_table(dev, tunnel,
10316                                                        jump_group,
10317                                                        &table,
10318                                                        &grp_info, error);
10319                         if (ret)
10320                                 return ret;
10321                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10322                                                        attr->transfer,
10323                                                        !!dev_flow->external,
10324                                                        tunnel, jump_group, 0,
10325                                                        error);
10326                         if (!tbl)
10327                                 return rte_flow_error_set
10328                                                 (error, errno,
10329                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10330                                                  NULL,
10331                                                  "cannot create jump action.");
10332                         if (flow_dv_jump_tbl_resource_register
10333                             (dev, tbl, dev_flow, error)) {
10334                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10335                                 return rte_flow_error_set
10336                                                 (error, errno,
10337                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10338                                                  NULL,
10339                                                  "cannot create jump action.");
10340                         }
10341                         dev_flow->dv.actions[actions_n++] =
10342                                         dev_flow->dv.jump->action;
10343                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10344                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10345                         break;
10346                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10347                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10348                         if (flow_dv_convert_action_modify_mac
10349                                         (mhdr_res, actions, error))
10350                                 return -rte_errno;
10351                         action_flags |= actions->type ==
10352                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10353                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10354                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10355                         break;
10356                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10357                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10358                         if (flow_dv_convert_action_modify_ipv4
10359                                         (mhdr_res, actions, error))
10360                                 return -rte_errno;
10361                         action_flags |= actions->type ==
10362                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10363                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10364                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10365                         break;
10366                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10367                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10368                         if (flow_dv_convert_action_modify_ipv6
10369                                         (mhdr_res, actions, error))
10370                                 return -rte_errno;
10371                         action_flags |= actions->type ==
10372                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10373                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10374                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10375                         break;
10376                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10377                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10378                         if (flow_dv_convert_action_modify_tp
10379                                         (mhdr_res, actions, items,
10380                                          &flow_attr, dev_flow, !!(action_flags &
10381                                          MLX5_FLOW_ACTION_DECAP), error))
10382                                 return -rte_errno;
10383                         action_flags |= actions->type ==
10384                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10385                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10386                                         MLX5_FLOW_ACTION_SET_TP_DST;
10387                         break;
10388                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10389                         if (flow_dv_convert_action_modify_dec_ttl
10390                                         (mhdr_res, items, &flow_attr, dev_flow,
10391                                          !!(action_flags &
10392                                          MLX5_FLOW_ACTION_DECAP), error))
10393                                 return -rte_errno;
10394                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10395                         break;
10396                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10397                         if (flow_dv_convert_action_modify_ttl
10398                                         (mhdr_res, actions, items, &flow_attr,
10399                                          dev_flow, !!(action_flags &
10400                                          MLX5_FLOW_ACTION_DECAP), error))
10401                                 return -rte_errno;
10402                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10403                         break;
10404                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10405                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10406                         if (flow_dv_convert_action_modify_tcp_seq
10407                                         (mhdr_res, actions, error))
10408                                 return -rte_errno;
10409                         action_flags |= actions->type ==
10410                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10411                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10412                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10413                         break;
10414
10415                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10416                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10417                         if (flow_dv_convert_action_modify_tcp_ack
10418                                         (mhdr_res, actions, error))
10419                                 return -rte_errno;
10420                         action_flags |= actions->type ==
10421                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10422                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10423                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10424                         break;
10425                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10426                         if (flow_dv_convert_action_set_reg
10427                                         (mhdr_res, actions, error))
10428                                 return -rte_errno;
10429                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10430                         break;
10431                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10432                         if (flow_dv_convert_action_copy_mreg
10433                                         (dev, mhdr_res, actions, error))
10434                                 return -rte_errno;
10435                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10436                         break;
10437                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10438                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10439                         dev_flow->handle->fate_action =
10440                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10441                         break;
10442                 case RTE_FLOW_ACTION_TYPE_METER:
10443                         mtr = actions->conf;
10444                         if (!flow->meter) {
10445                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10446                                                             attr, error);
10447                                 if (!fm)
10448                                         return rte_flow_error_set(error,
10449                                                 rte_errno,
10450                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10451                                                 NULL,
10452                                                 "meter not found "
10453                                                 "or invalid parameters");
10454                                 flow->meter = fm->idx;
10455                         }
10456                         /* Set the meter action. */
10457                         if (!fm) {
10458                                 fm = mlx5_ipool_get(priv->sh->ipool
10459                                                 [MLX5_IPOOL_MTR], flow->meter);
10460                                 if (!fm)
10461                                         return rte_flow_error_set(error,
10462                                                 rte_errno,
10463                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10464                                                 NULL,
10465                                                 "meter not found "
10466                                                 "or invalid parameters");
10467                         }
10468                         dev_flow->dv.actions[actions_n++] =
10469                                 fm->mfts->meter_action;
10470                         action_flags |= MLX5_FLOW_ACTION_METER;
10471                         break;
10472                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10473                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10474                                                               actions, error))
10475                                 return -rte_errno;
10476                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10477                         break;
10478                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10479                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10480                                                               actions, error))
10481                                 return -rte_errno;
10482                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10483                         break;
10484                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10485                         sample_act_pos = actions_n;
10486                         ret = flow_dv_translate_action_sample(dev,
10487                                                               actions,
10488                                                               dev_flow, attr,
10489                                                               &num_of_dest,
10490                                                               sample_actions,
10491                                                               &sample_res,
10492                                                               error);
10493                         if (ret < 0)
10494                                 return ret;
10495                         actions_n++;
10496                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10497                         /* put encap action into group if work with port id */
10498                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10499                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10500                                 sample_act->action_flags |=
10501                                                         MLX5_FLOW_ACTION_ENCAP;
10502                         break;
10503                 case RTE_FLOW_ACTION_TYPE_END:
10504                         actions_end = true;
10505                         if (mhdr_res->actions_num) {
10506                                 /* create modify action if needed. */
10507                                 if (flow_dv_modify_hdr_resource_register
10508                                         (dev, mhdr_res, dev_flow, error))
10509                                         return -rte_errno;
10510                                 dev_flow->dv.actions[modify_action_position] =
10511                                         handle->dvh.modify_hdr->action;
10512                         }
10513                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10514                                 flow->counter =
10515                                         flow_dv_translate_create_counter(dev,
10516                                                 dev_flow, count, age);
10517
10518                                 if (!flow->counter)
10519                                         return rte_flow_error_set
10520                                                 (error, rte_errno,
10521                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10522                                                 NULL,
10523                                                 "cannot create counter"
10524                                                 " object.");
10525                                 dev_flow->dv.actions[actions_n] =
10526                                           (flow_dv_counter_get_by_idx(dev,
10527                                           flow->counter, NULL))->action;
10528                                 actions_n++;
10529                         }
10530                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10531                                 ret = flow_dv_create_action_sample(dev,
10532                                                           dev_flow,
10533                                                           num_of_dest,
10534                                                           &sample_res,
10535                                                           &mdest_res,
10536                                                           sample_actions,
10537                                                           action_flags,
10538                                                           error);
10539                                 if (ret < 0)
10540                                         return rte_flow_error_set
10541                                                 (error, rte_errno,
10542                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10543                                                 NULL,
10544                                                 "cannot create sample action");
10545                                 if (num_of_dest > 1) {
10546                                         dev_flow->dv.actions[sample_act_pos] =
10547                                         dev_flow->dv.dest_array_res->action;
10548                                 } else {
10549                                         dev_flow->dv.actions[sample_act_pos] =
10550                                         dev_flow->dv.sample_res->verbs_action;
10551                                 }
10552                         }
10553                         break;
10554                 default:
10555                         break;
10556                 }
10557                 if (mhdr_res->actions_num &&
10558                     modify_action_position == UINT32_MAX)
10559                         modify_action_position = actions_n++;
10560         }
10561         /*
10562          * For multiple destination (sample action with ratio=1), the encap
10563          * action and port id action will be combined into group action.
10564          * So need remove the original these actions in the flow and only
10565          * use the sample action instead of.
10566          */
10567         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10568                 int i;
10569                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10570
10571                 for (i = 0; i < actions_n; i++) {
10572                         if ((sample_act->dr_encap_action &&
10573                                 sample_act->dr_encap_action ==
10574                                 dev_flow->dv.actions[i]) ||
10575                                 (sample_act->dr_port_id_action &&
10576                                 sample_act->dr_port_id_action ==
10577                                 dev_flow->dv.actions[i]))
10578                                 continue;
10579                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10580                 }
10581                 memcpy((void *)dev_flow->dv.actions,
10582                                 (void *)temp_actions,
10583                                 tmp_actions_n * sizeof(void *));
10584                 actions_n = tmp_actions_n;
10585         }
10586         dev_flow->dv.actions_n = actions_n;
10587         dev_flow->act_flags = action_flags;
10588         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10589                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10590                 int item_type = items->type;
10591
10592                 if (!mlx5_flow_os_item_supported(item_type))
10593                         return rte_flow_error_set(error, ENOTSUP,
10594                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10595                                                   NULL, "item not supported");
10596                 switch (item_type) {
10597                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10598                         flow_dv_translate_item_port_id
10599                                 (dev, match_mask, match_value, items, attr);
10600                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10601                         break;
10602                 case RTE_FLOW_ITEM_TYPE_ETH:
10603                         flow_dv_translate_item_eth(match_mask, match_value,
10604                                                    items, tunnel,
10605                                                    dev_flow->dv.group);
10606                         matcher.priority = action_flags &
10607                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10608                                         !dev_flow->external ?
10609                                         MLX5_PRIORITY_MAP_L3 :
10610                                         MLX5_PRIORITY_MAP_L2;
10611                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10612                                              MLX5_FLOW_LAYER_OUTER_L2;
10613                         break;
10614                 case RTE_FLOW_ITEM_TYPE_VLAN:
10615                         flow_dv_translate_item_vlan(dev_flow,
10616                                                     match_mask, match_value,
10617                                                     items, tunnel,
10618                                                     dev_flow->dv.group);
10619                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10620                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10621                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10622                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10623                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10624                         break;
10625                 case RTE_FLOW_ITEM_TYPE_IPV4:
10626                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10627                                                   &item_flags, &tunnel);
10628                         flow_dv_translate_item_ipv4(match_mask, match_value,
10629                                                     items, tunnel,
10630                                                     dev_flow->dv.group);
10631                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10632                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10633                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10634                         if (items->mask != NULL &&
10635                             ((const struct rte_flow_item_ipv4 *)
10636                              items->mask)->hdr.next_proto_id) {
10637                                 next_protocol =
10638                                         ((const struct rte_flow_item_ipv4 *)
10639                                          (items->spec))->hdr.next_proto_id;
10640                                 next_protocol &=
10641                                         ((const struct rte_flow_item_ipv4 *)
10642                                          (items->mask))->hdr.next_proto_id;
10643                         } else {
10644                                 /* Reset for inner layer. */
10645                                 next_protocol = 0xff;
10646                         }
10647                         break;
10648                 case RTE_FLOW_ITEM_TYPE_IPV6:
10649                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10650                                                   &item_flags, &tunnel);
10651                         flow_dv_translate_item_ipv6(match_mask, match_value,
10652                                                     items, tunnel,
10653                                                     dev_flow->dv.group);
10654                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10655                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10656                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10657                         if (items->mask != NULL &&
10658                             ((const struct rte_flow_item_ipv6 *)
10659                              items->mask)->hdr.proto) {
10660                                 next_protocol =
10661                                         ((const struct rte_flow_item_ipv6 *)
10662                                          items->spec)->hdr.proto;
10663                                 next_protocol &=
10664                                         ((const struct rte_flow_item_ipv6 *)
10665                                          items->mask)->hdr.proto;
10666                         } else {
10667                                 /* Reset for inner layer. */
10668                                 next_protocol = 0xff;
10669                         }
10670                         break;
10671                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10672                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10673                                                              match_value,
10674                                                              items, tunnel);
10675                         last_item = tunnel ?
10676                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10677                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10678                         if (items->mask != NULL &&
10679                             ((const struct rte_flow_item_ipv6_frag_ext *)
10680                              items->mask)->hdr.next_header) {
10681                                 next_protocol =
10682                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10683                                  items->spec)->hdr.next_header;
10684                                 next_protocol &=
10685                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10686                                  items->mask)->hdr.next_header;
10687                         } else {
10688                                 /* Reset for inner layer. */
10689                                 next_protocol = 0xff;
10690                         }
10691                         break;
10692                 case RTE_FLOW_ITEM_TYPE_TCP:
10693                         flow_dv_translate_item_tcp(match_mask, match_value,
10694                                                    items, tunnel);
10695                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10696                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10697                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10698                         break;
10699                 case RTE_FLOW_ITEM_TYPE_UDP:
10700                         flow_dv_translate_item_udp(match_mask, match_value,
10701                                                    items, tunnel);
10702                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10703                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10704                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10705                         break;
10706                 case RTE_FLOW_ITEM_TYPE_GRE:
10707                         flow_dv_translate_item_gre(match_mask, match_value,
10708                                                    items, tunnel);
10709                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10710                         last_item = MLX5_FLOW_LAYER_GRE;
10711                         break;
10712                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10713                         flow_dv_translate_item_gre_key(match_mask,
10714                                                        match_value, items);
10715                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10716                         break;
10717                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10718                         flow_dv_translate_item_nvgre(match_mask, match_value,
10719                                                      items, tunnel);
10720                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10721                         last_item = MLX5_FLOW_LAYER_GRE;
10722                         break;
10723                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10724                         flow_dv_translate_item_vxlan(match_mask, match_value,
10725                                                      items, tunnel);
10726                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10727                         last_item = MLX5_FLOW_LAYER_VXLAN;
10728                         break;
10729                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10730                         flow_dv_translate_item_vxlan_gpe(match_mask,
10731                                                          match_value, items,
10732                                                          tunnel);
10733                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10734                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10735                         break;
10736                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10737                         flow_dv_translate_item_geneve(match_mask, match_value,
10738                                                       items, tunnel);
10739                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10740                         last_item = MLX5_FLOW_LAYER_GENEVE;
10741                         break;
10742                 case RTE_FLOW_ITEM_TYPE_MPLS:
10743                         flow_dv_translate_item_mpls(match_mask, match_value,
10744                                                     items, last_item, tunnel);
10745                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10746                         last_item = MLX5_FLOW_LAYER_MPLS;
10747                         break;
10748                 case RTE_FLOW_ITEM_TYPE_MARK:
10749                         flow_dv_translate_item_mark(dev, match_mask,
10750                                                     match_value, items);
10751                         last_item = MLX5_FLOW_ITEM_MARK;
10752                         break;
10753                 case RTE_FLOW_ITEM_TYPE_META:
10754                         flow_dv_translate_item_meta(dev, match_mask,
10755                                                     match_value, attr, items);
10756                         last_item = MLX5_FLOW_ITEM_METADATA;
10757                         break;
10758                 case RTE_FLOW_ITEM_TYPE_ICMP:
10759                         flow_dv_translate_item_icmp(match_mask, match_value,
10760                                                     items, tunnel);
10761                         last_item = MLX5_FLOW_LAYER_ICMP;
10762                         break;
10763                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10764                         flow_dv_translate_item_icmp6(match_mask, match_value,
10765                                                       items, tunnel);
10766                         last_item = MLX5_FLOW_LAYER_ICMP6;
10767                         break;
10768                 case RTE_FLOW_ITEM_TYPE_TAG:
10769                         flow_dv_translate_item_tag(dev, match_mask,
10770                                                    match_value, items);
10771                         last_item = MLX5_FLOW_ITEM_TAG;
10772                         break;
10773                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10774                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10775                                                         match_value, items);
10776                         last_item = MLX5_FLOW_ITEM_TAG;
10777                         break;
10778                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10779                         flow_dv_translate_item_tx_queue(dev, match_mask,
10780                                                         match_value,
10781                                                         items);
10782                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10783                         break;
10784                 case RTE_FLOW_ITEM_TYPE_GTP:
10785                         flow_dv_translate_item_gtp(match_mask, match_value,
10786                                                    items, tunnel);
10787                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10788                         last_item = MLX5_FLOW_LAYER_GTP;
10789                         break;
10790                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10791                         ret = flow_dv_translate_item_gtp_psc(match_mask,
10792                                                           match_value,
10793                                                           items);
10794                         if (ret)
10795                                 return rte_flow_error_set(error, -ret,
10796                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10797                                         "cannot create GTP PSC item");
10798                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
10799                         break;
10800                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10801                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10802                                 /* Create it only the first time to be used. */
10803                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10804                                 if (ret)
10805                                         return rte_flow_error_set
10806                                                 (error, -ret,
10807                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10808                                                 NULL,
10809                                                 "cannot create eCPRI parser");
10810                         }
10811                         /* Adjust the length matcher and device flow value. */
10812                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10813                         dev_flow->dv.value.size =
10814                                         MLX5_ST_SZ_BYTES(fte_match_param);
10815                         flow_dv_translate_item_ecpri(dev, match_mask,
10816                                                      match_value, items);
10817                         /* No other protocol should follow eCPRI layer. */
10818                         last_item = MLX5_FLOW_LAYER_ECPRI;
10819                         break;
10820                 default:
10821                         break;
10822                 }
10823                 item_flags |= last_item;
10824         }
10825         /*
10826          * When E-Switch mode is enabled, we have two cases where we need to
10827          * set the source port manually.
10828          * The first one, is in case of Nic steering rule, and the second is
10829          * E-Switch rule where no port_id item was found. In both cases
10830          * the source port is set according the current port in use.
10831          */
10832         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10833             (priv->representor || priv->master)) {
10834                 if (flow_dv_translate_item_port_id(dev, match_mask,
10835                                                    match_value, NULL, attr))
10836                         return -rte_errno;
10837         }
10838 #ifdef RTE_LIBRTE_MLX5_DEBUG
10839         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10840                                               dev_flow->dv.value.buf));
10841 #endif
10842         /*
10843          * Layers may be already initialized from prefix flow if this dev_flow
10844          * is the suffix flow.
10845          */
10846         handle->layers |= item_flags;
10847         if (action_flags & MLX5_FLOW_ACTION_RSS)
10848                 flow_dv_hashfields_set(dev_flow, rss_desc);
10849         /* Register matcher. */
10850         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10851                                     matcher.mask.size);
10852         matcher.priority = mlx5_os_flow_adjust_priority(dev,
10853                                                         priority,
10854                                                         matcher.priority);
10855         /* reserved field no needs to be set to 0 here. */
10856         tbl_key.domain = attr->transfer;
10857         tbl_key.direction = attr->egress;
10858         tbl_key.table_id = dev_flow->dv.group;
10859         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10860                                      tunnel, attr->group, error))
10861                 return -rte_errno;
10862         return 0;
10863 }
10864
10865 /**
10866  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10867  * and tunnel.
10868  *
10869  * @param[in, out] action
10870  *   Shred RSS action holding hash RX queue objects.
10871  * @param[in] hash_fields
10872  *   Defines combination of packet fields to participate in RX hash.
10873  * @param[in] tunnel
10874  *   Tunnel type
10875  * @param[in] hrxq_idx
10876  *   Hash RX queue index to set.
10877  *
10878  * @return
10879  *   0 on success, otherwise negative errno value.
10880  */
10881 static int
10882 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10883                               const uint64_t hash_fields,
10884                               const int tunnel,
10885                               uint32_t hrxq_idx)
10886 {
10887         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10888
10889         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10890         case MLX5_RSS_HASH_IPV4:
10891                 hrxqs[0] = hrxq_idx;
10892                 return 0;
10893         case MLX5_RSS_HASH_IPV4_TCP:
10894                 hrxqs[1] = hrxq_idx;
10895                 return 0;
10896         case MLX5_RSS_HASH_IPV4_UDP:
10897                 hrxqs[2] = hrxq_idx;
10898                 return 0;
10899         case MLX5_RSS_HASH_IPV6:
10900                 hrxqs[3] = hrxq_idx;
10901                 return 0;
10902         case MLX5_RSS_HASH_IPV6_TCP:
10903                 hrxqs[4] = hrxq_idx;
10904                 return 0;
10905         case MLX5_RSS_HASH_IPV6_UDP:
10906                 hrxqs[5] = hrxq_idx;
10907                 return 0;
10908         case MLX5_RSS_HASH_NONE:
10909                 hrxqs[6] = hrxq_idx;
10910                 return 0;
10911         default:
10912                 return -1;
10913         }
10914 }
10915
10916 /**
10917  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10918  * and tunnel.
10919  *
10920  * @param[in] dev
10921  *   Pointer to the Ethernet device structure.
10922  * @param[in] idx
10923  *   Shared RSS action ID holding hash RX queue objects.
10924  * @param[in] hash_fields
10925  *   Defines combination of packet fields to participate in RX hash.
10926  * @param[in] tunnel
10927  *   Tunnel type
10928  *
10929  * @return
10930  *   Valid hash RX queue index, otherwise 0.
10931  */
10932 static uint32_t
10933 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10934                                  const uint64_t hash_fields,
10935                                  const int tunnel)
10936 {
10937         struct mlx5_priv *priv = dev->data->dev_private;
10938         struct mlx5_shared_action_rss *shared_rss =
10939             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10940         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10941                                                         shared_rss->hrxq_tunnel;
10942
10943         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10944         case MLX5_RSS_HASH_IPV4:
10945                 return hrxqs[0];
10946         case MLX5_RSS_HASH_IPV4_TCP:
10947                 return hrxqs[1];
10948         case MLX5_RSS_HASH_IPV4_UDP:
10949                 return hrxqs[2];
10950         case MLX5_RSS_HASH_IPV6:
10951                 return hrxqs[3];
10952         case MLX5_RSS_HASH_IPV6_TCP:
10953                 return hrxqs[4];
10954         case MLX5_RSS_HASH_IPV6_UDP:
10955                 return hrxqs[5];
10956         case MLX5_RSS_HASH_NONE:
10957                 return hrxqs[6];
10958         default:
10959                 return 0;
10960         }
10961 }
10962
10963 /**
10964  * Apply the flow to the NIC, lock free,
10965  * (mutex should be acquired by caller).
10966  *
10967  * @param[in] dev
10968  *   Pointer to the Ethernet device structure.
10969  * @param[in, out] flow
10970  *   Pointer to flow structure.
10971  * @param[out] error
10972  *   Pointer to error structure.
10973  *
10974  * @return
10975  *   0 on success, a negative errno value otherwise and rte_errno is set.
10976  */
10977 static int
10978 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10979               struct rte_flow_error *error)
10980 {
10981         struct mlx5_flow_dv_workspace *dv;
10982         struct mlx5_flow_handle *dh;
10983         struct mlx5_flow_handle_dv *dv_h;
10984         struct mlx5_flow *dev_flow;
10985         struct mlx5_priv *priv = dev->data->dev_private;
10986         uint32_t handle_idx;
10987         int n;
10988         int err;
10989         int idx;
10990         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10991         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10992
10993         MLX5_ASSERT(wks);
10994         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10995                 dev_flow = &wks->flows[idx];
10996                 dv = &dev_flow->dv;
10997                 dh = dev_flow->handle;
10998                 dv_h = &dh->dvh;
10999                 n = dv->actions_n;
11000                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11001                         if (dv->transfer) {
11002                                 dv->actions[n++] = priv->sh->esw_drop_action;
11003                         } else {
11004                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11005                                 dv->actions[n++] =
11006                                                 priv->drop_queue.hrxq->action;
11007                         }
11008                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11009                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11010                         struct mlx5_hrxq *hrxq;
11011                         uint32_t hrxq_idx;
11012
11013                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11014                                                     &hrxq_idx);
11015                         if (!hrxq) {
11016                                 rte_flow_error_set
11017                                         (error, rte_errno,
11018                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11019                                          "cannot get hash queue");
11020                                 goto error;
11021                         }
11022                         dh->rix_hrxq = hrxq_idx;
11023                         dv->actions[n++] = hrxq->action;
11024                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11025                         struct mlx5_hrxq *hrxq = NULL;
11026                         uint32_t hrxq_idx;
11027
11028                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11029                                                 rss_desc->shared_rss,
11030                                                 dev_flow->hash_fields,
11031                                                 !!(dh->layers &
11032                                                 MLX5_FLOW_LAYER_TUNNEL));
11033                         if (hrxq_idx)
11034                                 hrxq = mlx5_ipool_get
11035                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11036                                          hrxq_idx);
11037                         if (!hrxq) {
11038                                 rte_flow_error_set
11039                                         (error, rte_errno,
11040                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11041                                          "cannot get hash queue");
11042                                 goto error;
11043                         }
11044                         dh->rix_srss = rss_desc->shared_rss;
11045                         dv->actions[n++] = hrxq->action;
11046                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11047                         if (!priv->sh->default_miss_action) {
11048                                 rte_flow_error_set
11049                                         (error, rte_errno,
11050                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11051                                          "default miss action not be created.");
11052                                 goto error;
11053                         }
11054                         dv->actions[n++] = priv->sh->default_miss_action;
11055                 }
11056                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11057                                                (void *)&dv->value, n,
11058                                                dv->actions, &dh->drv_flow);
11059                 if (err) {
11060                         rte_flow_error_set(error, errno,
11061                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11062                                            NULL,
11063                                            "hardware refuses to create flow");
11064                         goto error;
11065                 }
11066                 if (priv->vmwa_context &&
11067                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
11068                         /*
11069                          * The rule contains the VLAN pattern.
11070                          * For VF we are going to create VLAN
11071                          * interface to make hypervisor set correct
11072                          * e-Switch vport context.
11073                          */
11074                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11075                 }
11076         }
11077         return 0;
11078 error:
11079         err = rte_errno; /* Save rte_errno before cleanup. */
11080         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11081                        handle_idx, dh, next) {
11082                 /* hrxq is union, don't clear it if the flag is not set. */
11083                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11084                         mlx5_hrxq_release(dev, dh->rix_hrxq);
11085                         dh->rix_hrxq = 0;
11086                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11087                         dh->rix_srss = 0;
11088                 }
11089                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11090                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11091         }
11092         rte_errno = err; /* Restore rte_errno. */
11093         return -rte_errno;
11094 }
11095
11096 void
11097 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11098                           struct mlx5_cache_entry *entry)
11099 {
11100         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11101                                                           entry);
11102
11103         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11104         mlx5_free(cache);
11105 }
11106
11107 /**
11108  * Release the flow matcher.
11109  *
11110  * @param dev
11111  *   Pointer to Ethernet device.
11112  * @param handle
11113  *   Pointer to mlx5_flow_handle.
11114  *
11115  * @return
11116  *   1 while a reference on it exists, 0 when freed.
11117  */
11118 static int
11119 flow_dv_matcher_release(struct rte_eth_dev *dev,
11120                         struct mlx5_flow_handle *handle)
11121 {
11122         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11123         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11124                                                             typeof(*tbl), tbl);
11125         int ret;
11126
11127         MLX5_ASSERT(matcher->matcher_object);
11128         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11129         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11130         return ret;
11131 }
11132
11133 /**
11134  * Release encap_decap resource.
11135  *
11136  * @param list
11137  *   Pointer to the hash list.
11138  * @param entry
11139  *   Pointer to exist resource entry object.
11140  */
11141 void
11142 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11143                               struct mlx5_hlist_entry *entry)
11144 {
11145         struct mlx5_dev_ctx_shared *sh = list->ctx;
11146         struct mlx5_flow_dv_encap_decap_resource *res =
11147                 container_of(entry, typeof(*res), entry);
11148
11149         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11150         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11151 }
11152
11153 /**
11154  * Release an encap/decap resource.
11155  *
11156  * @param dev
11157  *   Pointer to Ethernet device.
11158  * @param encap_decap_idx
11159  *   Index of encap decap resource.
11160  *
11161  * @return
11162  *   1 while a reference on it exists, 0 when freed.
11163  */
11164 static int
11165 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11166                                      uint32_t encap_decap_idx)
11167 {
11168         struct mlx5_priv *priv = dev->data->dev_private;
11169         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11170
11171         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11172                                         encap_decap_idx);
11173         if (!cache_resource)
11174                 return 0;
11175         MLX5_ASSERT(cache_resource->action);
11176         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11177                                      &cache_resource->entry);
11178 }
11179
11180 /**
11181  * Release an jump to table action resource.
11182  *
11183  * @param dev
11184  *   Pointer to Ethernet device.
11185  * @param handle
11186  *   Pointer to mlx5_flow_handle.
11187  *
11188  * @return
11189  *   1 while a reference on it exists, 0 when freed.
11190  */
11191 static int
11192 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11193                                   struct mlx5_flow_handle *handle)
11194 {
11195         struct mlx5_priv *priv = dev->data->dev_private;
11196         struct mlx5_flow_tbl_data_entry *tbl_data;
11197
11198         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11199                              handle->rix_jump);
11200         if (!tbl_data)
11201                 return 0;
11202         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11203 }
11204
11205 void
11206 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11207                          struct mlx5_hlist_entry *entry)
11208 {
11209         struct mlx5_flow_dv_modify_hdr_resource *res =
11210                 container_of(entry, typeof(*res), entry);
11211
11212         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11213         mlx5_free(entry);
11214 }
11215
11216 /**
11217  * Release a modify-header resource.
11218  *
11219  * @param dev
11220  *   Pointer to Ethernet device.
11221  * @param handle
11222  *   Pointer to mlx5_flow_handle.
11223  *
11224  * @return
11225  *   1 while a reference on it exists, 0 when freed.
11226  */
11227 static int
11228 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11229                                     struct mlx5_flow_handle *handle)
11230 {
11231         struct mlx5_priv *priv = dev->data->dev_private;
11232         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11233
11234         MLX5_ASSERT(entry->action);
11235         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11236 }
11237
11238 void
11239 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11240                           struct mlx5_cache_entry *entry)
11241 {
11242         struct mlx5_dev_ctx_shared *sh = list->ctx;
11243         struct mlx5_flow_dv_port_id_action_resource *cache =
11244                         container_of(entry, typeof(*cache), entry);
11245
11246         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11247         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11248 }
11249
11250 /**
11251  * Release port ID action resource.
11252  *
11253  * @param dev
11254  *   Pointer to Ethernet device.
11255  * @param handle
11256  *   Pointer to mlx5_flow_handle.
11257  *
11258  * @return
11259  *   1 while a reference on it exists, 0 when freed.
11260  */
11261 static int
11262 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11263                                         uint32_t port_id)
11264 {
11265         struct mlx5_priv *priv = dev->data->dev_private;
11266         struct mlx5_flow_dv_port_id_action_resource *cache;
11267
11268         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11269         if (!cache)
11270                 return 0;
11271         MLX5_ASSERT(cache->action);
11272         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11273                                      &cache->entry);
11274 }
11275
11276 /**
11277  * Release shared RSS action resource.
11278  *
11279  * @param dev
11280  *   Pointer to Ethernet device.
11281  * @param srss
11282  *   Shared RSS action index.
11283  */
11284 static void
11285 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11286 {
11287         struct mlx5_priv *priv = dev->data->dev_private;
11288         struct mlx5_shared_action_rss *shared_rss;
11289
11290         shared_rss = mlx5_ipool_get
11291                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11292         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11293 }
11294
11295 void
11296 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11297                             struct mlx5_cache_entry *entry)
11298 {
11299         struct mlx5_dev_ctx_shared *sh = list->ctx;
11300         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11301                         container_of(entry, typeof(*cache), entry);
11302
11303         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11304         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11305 }
11306
11307 /**
11308  * Release push vlan action resource.
11309  *
11310  * @param dev
11311  *   Pointer to Ethernet device.
11312  * @param handle
11313  *   Pointer to mlx5_flow_handle.
11314  *
11315  * @return
11316  *   1 while a reference on it exists, 0 when freed.
11317  */
11318 static int
11319 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11320                                           struct mlx5_flow_handle *handle)
11321 {
11322         struct mlx5_priv *priv = dev->data->dev_private;
11323         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11324         uint32_t idx = handle->dvh.rix_push_vlan;
11325
11326         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11327         if (!cache)
11328                 return 0;
11329         MLX5_ASSERT(cache->action);
11330         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11331                                      &cache->entry);
11332 }
11333
11334 /**
11335  * Release the fate resource.
11336  *
11337  * @param dev
11338  *   Pointer to Ethernet device.
11339  * @param handle
11340  *   Pointer to mlx5_flow_handle.
11341  */
11342 static void
11343 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11344                                struct mlx5_flow_handle *handle)
11345 {
11346         if (!handle->rix_fate)
11347                 return;
11348         switch (handle->fate_action) {
11349         case MLX5_FLOW_FATE_QUEUE:
11350                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11351                 break;
11352         case MLX5_FLOW_FATE_JUMP:
11353                 flow_dv_jump_tbl_resource_release(dev, handle);
11354                 break;
11355         case MLX5_FLOW_FATE_PORT_ID:
11356                 flow_dv_port_id_action_resource_release(dev,
11357                                 handle->rix_port_id_action);
11358                 break;
11359         default:
11360                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11361                 break;
11362         }
11363         handle->rix_fate = 0;
11364 }
11365
11366 void
11367 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11368                          struct mlx5_cache_entry *entry)
11369 {
11370         struct mlx5_flow_dv_sample_resource *cache_resource =
11371                         container_of(entry, typeof(*cache_resource), entry);
11372         struct rte_eth_dev *dev = cache_resource->dev;
11373         struct mlx5_priv *priv = dev->data->dev_private;
11374
11375         if (cache_resource->verbs_action)
11376                 claim_zero(mlx5_flow_os_destroy_flow_action
11377                                 (cache_resource->verbs_action));
11378         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11379                 if (cache_resource->default_miss)
11380                         claim_zero(mlx5_flow_os_destroy_flow_action
11381                           (cache_resource->default_miss));
11382         }
11383         if (cache_resource->normal_path_tbl)
11384                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11385                         cache_resource->normal_path_tbl);
11386         flow_dv_sample_sub_actions_release(dev,
11387                                 &cache_resource->sample_idx);
11388         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11389                         cache_resource->idx);
11390         DRV_LOG(DEBUG, "sample resource %p: removed",
11391                 (void *)cache_resource);
11392 }
11393
11394 /**
11395  * Release an sample resource.
11396  *
11397  * @param dev
11398  *   Pointer to Ethernet device.
11399  * @param handle
11400  *   Pointer to mlx5_flow_handle.
11401  *
11402  * @return
11403  *   1 while a reference on it exists, 0 when freed.
11404  */
11405 static int
11406 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11407                                      struct mlx5_flow_handle *handle)
11408 {
11409         struct mlx5_priv *priv = dev->data->dev_private;
11410         struct mlx5_flow_dv_sample_resource *cache_resource;
11411
11412         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11413                          handle->dvh.rix_sample);
11414         if (!cache_resource)
11415                 return 0;
11416         MLX5_ASSERT(cache_resource->verbs_action);
11417         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11418                                      &cache_resource->entry);
11419 }
11420
11421 void
11422 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11423                              struct mlx5_cache_entry *entry)
11424 {
11425         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11426                         container_of(entry, typeof(*cache_resource), entry);
11427         struct rte_eth_dev *dev = cache_resource->dev;
11428         struct mlx5_priv *priv = dev->data->dev_private;
11429         uint32_t i = 0;
11430
11431         MLX5_ASSERT(cache_resource->action);
11432         if (cache_resource->action)
11433                 claim_zero(mlx5_flow_os_destroy_flow_action
11434                                         (cache_resource->action));
11435         for (; i < cache_resource->num_of_dest; i++)
11436                 flow_dv_sample_sub_actions_release(dev,
11437                                 &cache_resource->sample_idx[i]);
11438         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11439                         cache_resource->idx);
11440         DRV_LOG(DEBUG, "destination array resource %p: removed",
11441                 (void *)cache_resource);
11442 }
11443
11444 /**
11445  * Release an destination array resource.
11446  *
11447  * @param dev
11448  *   Pointer to Ethernet device.
11449  * @param handle
11450  *   Pointer to mlx5_flow_handle.
11451  *
11452  * @return
11453  *   1 while a reference on it exists, 0 when freed.
11454  */
11455 static int
11456 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11457                                     struct mlx5_flow_handle *handle)
11458 {
11459         struct mlx5_priv *priv = dev->data->dev_private;
11460         struct mlx5_flow_dv_dest_array_resource *cache;
11461
11462         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11463                                handle->dvh.rix_dest_array);
11464         if (!cache)
11465                 return 0;
11466         MLX5_ASSERT(cache->action);
11467         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11468                                      &cache->entry);
11469 }
11470
11471 static void
11472 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11473 {
11474         struct mlx5_priv *priv = dev->data->dev_private;
11475         struct mlx5_dev_ctx_shared *sh = priv->sh;
11476         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11477                                 sh->geneve_tlv_option_resource;
11478         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11479         if (geneve_opt_resource) {
11480                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11481                                          __ATOMIC_RELAXED))) {
11482                         claim_zero(mlx5_devx_cmd_destroy
11483                                         (geneve_opt_resource->obj));
11484                         mlx5_free(sh->geneve_tlv_option_resource);
11485                         sh->geneve_tlv_option_resource = NULL;
11486                 }
11487         }
11488         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11489 }
11490
11491 /**
11492  * Remove the flow from the NIC but keeps it in memory.
11493  * Lock free, (mutex should be acquired by caller).
11494  *
11495  * @param[in] dev
11496  *   Pointer to Ethernet device.
11497  * @param[in, out] flow
11498  *   Pointer to flow structure.
11499  */
11500 static void
11501 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11502 {
11503         struct mlx5_flow_handle *dh;
11504         uint32_t handle_idx;
11505         struct mlx5_priv *priv = dev->data->dev_private;
11506
11507         if (!flow)
11508                 return;
11509         handle_idx = flow->dev_handles;
11510         while (handle_idx) {
11511                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11512                                     handle_idx);
11513                 if (!dh)
11514                         return;
11515                 if (dh->drv_flow) {
11516                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11517                         dh->drv_flow = NULL;
11518                 }
11519                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11520                         flow_dv_fate_resource_release(dev, dh);
11521                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11522                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11523                 handle_idx = dh->next.next;
11524         }
11525 }
11526
11527 /**
11528  * Remove the flow from the NIC and the memory.
11529  * Lock free, (mutex should be acquired by caller).
11530  *
11531  * @param[in] dev
11532  *   Pointer to the Ethernet device structure.
11533  * @param[in, out] flow
11534  *   Pointer to flow structure.
11535  */
11536 static void
11537 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11538 {
11539         struct mlx5_flow_handle *dev_handle;
11540         struct mlx5_priv *priv = dev->data->dev_private;
11541         uint32_t srss = 0;
11542
11543         if (!flow)
11544                 return;
11545         flow_dv_remove(dev, flow);
11546         if (flow->counter) {
11547                 flow_dv_counter_free(dev, flow->counter);
11548                 flow->counter = 0;
11549         }
11550         if (flow->meter) {
11551                 struct mlx5_flow_meter *fm;
11552
11553                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11554                                     flow->meter);
11555                 if (fm)
11556                         mlx5_flow_meter_detach(fm);
11557                 flow->meter = 0;
11558         }
11559         if (flow->age)
11560                 flow_dv_aso_age_release(dev, flow->age);
11561         if (flow->geneve_tlv_option) {
11562                 flow_dv_geneve_tlv_option_resource_release(dev);
11563                 flow->geneve_tlv_option = 0;
11564         }
11565         while (flow->dev_handles) {
11566                 uint32_t tmp_idx = flow->dev_handles;
11567
11568                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11569                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11570                 if (!dev_handle)
11571                         return;
11572                 flow->dev_handles = dev_handle->next.next;
11573                 if (dev_handle->dvh.matcher)
11574                         flow_dv_matcher_release(dev, dev_handle);
11575                 if (dev_handle->dvh.rix_sample)
11576                         flow_dv_sample_resource_release(dev, dev_handle);
11577                 if (dev_handle->dvh.rix_dest_array)
11578                         flow_dv_dest_array_resource_release(dev, dev_handle);
11579                 if (dev_handle->dvh.rix_encap_decap)
11580                         flow_dv_encap_decap_resource_release(dev,
11581                                 dev_handle->dvh.rix_encap_decap);
11582                 if (dev_handle->dvh.modify_hdr)
11583                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11584                 if (dev_handle->dvh.rix_push_vlan)
11585                         flow_dv_push_vlan_action_resource_release(dev,
11586                                                                   dev_handle);
11587                 if (dev_handle->dvh.rix_tag)
11588                         flow_dv_tag_release(dev,
11589                                             dev_handle->dvh.rix_tag);
11590                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11591                         flow_dv_fate_resource_release(dev, dev_handle);
11592                 else if (!srss)
11593                         srss = dev_handle->rix_srss;
11594                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11595                            tmp_idx);
11596         }
11597         if (srss)
11598                 flow_dv_shared_rss_action_release(dev, srss);
11599 }
11600
11601 /**
11602  * Release array of hash RX queue objects.
11603  * Helper function.
11604  *
11605  * @param[in] dev
11606  *   Pointer to the Ethernet device structure.
11607  * @param[in, out] hrxqs
11608  *   Array of hash RX queue objects.
11609  *
11610  * @return
11611  *   Total number of references to hash RX queue objects in *hrxqs* array
11612  *   after this operation.
11613  */
11614 static int
11615 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11616                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11617 {
11618         size_t i;
11619         int remaining = 0;
11620
11621         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11622                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11623
11624                 if (!ret)
11625                         (*hrxqs)[i] = 0;
11626                 remaining += ret;
11627         }
11628         return remaining;
11629 }
11630
11631 /**
11632  * Release all hash RX queue objects representing shared RSS action.
11633  *
11634  * @param[in] dev
11635  *   Pointer to the Ethernet device structure.
11636  * @param[in, out] action
11637  *   Shared RSS action to remove hash RX queue objects from.
11638  *
11639  * @return
11640  *   Total number of references to hash RX queue objects stored in *action*
11641  *   after this operation.
11642  *   Expected to be 0 if no external references held.
11643  */
11644 static int
11645 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11646                                  struct mlx5_shared_action_rss *action)
11647 {
11648         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11649                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11650 }
11651
11652 /**
11653  * Setup shared RSS action.
11654  * Prepare set of hash RX queue objects sufficient to handle all valid
11655  * hash_fields combinations (see enum ibv_rx_hash_fields).
11656  *
11657  * @param[in] dev
11658  *   Pointer to the Ethernet device structure.
11659  * @param[in] action_idx
11660  *   Shared RSS action ipool index.
11661  * @param[in, out] action
11662  *   Partially initialized shared RSS action.
11663  * @param[out] error
11664  *   Perform verbose error reporting if not NULL. Initialized in case of
11665  *   error only.
11666  *
11667  * @return
11668  *   0 on success, otherwise negative errno value.
11669  */
11670 static int
11671 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11672                            uint32_t action_idx,
11673                            struct mlx5_shared_action_rss *action,
11674                            struct rte_flow_error *error)
11675 {
11676         struct mlx5_flow_rss_desc rss_desc = { 0 };
11677         size_t i;
11678         int err;
11679
11680         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11681                 return rte_flow_error_set(error, rte_errno,
11682                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11683                                           "cannot setup indirection table");
11684         }
11685         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11686         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11687         rss_desc.const_q = action->origin.queue;
11688         rss_desc.queue_num = action->origin.queue_num;
11689         /* Set non-zero value to indicate a shared RSS. */
11690         rss_desc.shared_rss = action_idx;
11691         rss_desc.ind_tbl = action->ind_tbl;
11692         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11693                 uint32_t hrxq_idx;
11694                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11695                 int tunnel;
11696
11697                 for (tunnel = 0; tunnel < 2; tunnel++) {
11698                         rss_desc.tunnel = tunnel;
11699                         rss_desc.hash_fields = hash_fields;
11700                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11701                         if (!hrxq_idx) {
11702                                 rte_flow_error_set
11703                                         (error, rte_errno,
11704                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11705                                          "cannot get hash queue");
11706                                 goto error_hrxq_new;
11707                         }
11708                         err = __flow_dv_action_rss_hrxq_set
11709                                 (action, hash_fields, tunnel, hrxq_idx);
11710                         MLX5_ASSERT(!err);
11711                 }
11712         }
11713         return 0;
11714 error_hrxq_new:
11715         err = rte_errno;
11716         __flow_dv_action_rss_hrxqs_release(dev, action);
11717         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11718                 action->ind_tbl = NULL;
11719         rte_errno = err;
11720         return -rte_errno;
11721 }
11722
11723 /**
11724  * Create shared RSS action.
11725  *
11726  * @param[in] dev
11727  *   Pointer to the Ethernet device structure.
11728  * @param[in] conf
11729  *   Shared action configuration.
11730  * @param[in] rss
11731  *   RSS action specification used to create shared action.
11732  * @param[out] error
11733  *   Perform verbose error reporting if not NULL. Initialized in case of
11734  *   error only.
11735  *
11736  * @return
11737  *   A valid shared action ID in case of success, 0 otherwise and
11738  *   rte_errno is set.
11739  */
11740 static uint32_t
11741 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11742                             const struct rte_flow_shared_action_conf *conf,
11743                             const struct rte_flow_action_rss *rss,
11744                             struct rte_flow_error *error)
11745 {
11746         struct mlx5_priv *priv = dev->data->dev_private;
11747         struct mlx5_shared_action_rss *shared_action = NULL;
11748         void *queue = NULL;
11749         struct rte_flow_action_rss *origin;
11750         const uint8_t *rss_key;
11751         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11752         uint32_t idx;
11753
11754         RTE_SET_USED(conf);
11755         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11756                             0, SOCKET_ID_ANY);
11757         shared_action = mlx5_ipool_zmalloc
11758                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11759         if (!shared_action || !queue) {
11760                 rte_flow_error_set(error, ENOMEM,
11761                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11762                                    "cannot allocate resource memory");
11763                 goto error_rss_init;
11764         }
11765         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11766                 rte_flow_error_set(error, E2BIG,
11767                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11768                                    "rss action number out of range");
11769                 goto error_rss_init;
11770         }
11771         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11772                                              sizeof(*shared_action->ind_tbl),
11773                                              0, SOCKET_ID_ANY);
11774         if (!shared_action->ind_tbl) {
11775                 rte_flow_error_set(error, ENOMEM,
11776                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11777                                    "cannot allocate resource memory");
11778                 goto error_rss_init;
11779         }
11780         memcpy(queue, rss->queue, queue_size);
11781         shared_action->ind_tbl->queues = queue;
11782         shared_action->ind_tbl->queues_n = rss->queue_num;
11783         origin = &shared_action->origin;
11784         origin->func = rss->func;
11785         origin->level = rss->level;
11786         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11787         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11788         /* NULL RSS key indicates default RSS key. */
11789         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11790         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11791         origin->key = &shared_action->key[0];
11792         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11793         origin->queue = queue;
11794         origin->queue_num = rss->queue_num;
11795         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11796                 goto error_rss_init;
11797         rte_spinlock_init(&shared_action->action_rss_sl);
11798         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11799         rte_spinlock_lock(&priv->shared_act_sl);
11800         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11801                      &priv->rss_shared_actions, idx, shared_action, next);
11802         rte_spinlock_unlock(&priv->shared_act_sl);
11803         return idx;
11804 error_rss_init:
11805         if (shared_action) {
11806                 if (shared_action->ind_tbl)
11807                         mlx5_free(shared_action->ind_tbl);
11808                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11809                                 idx);
11810         }
11811         if (queue)
11812                 mlx5_free(queue);
11813         return 0;
11814 }
11815
11816 /**
11817  * Destroy the shared RSS action.
11818  * Release related hash RX queue objects.
11819  *
11820  * @param[in] dev
11821  *   Pointer to the Ethernet device structure.
11822  * @param[in] idx
11823  *   The shared RSS action object ID to be removed.
11824  * @param[out] error
11825  *   Perform verbose error reporting if not NULL. Initialized in case of
11826  *   error only.
11827  *
11828  * @return
11829  *   0 on success, otherwise negative errno value.
11830  */
11831 static int
11832 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11833                              struct rte_flow_error *error)
11834 {
11835         struct mlx5_priv *priv = dev->data->dev_private;
11836         struct mlx5_shared_action_rss *shared_rss =
11837             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11838         uint32_t old_refcnt = 1;
11839         int remaining;
11840         uint16_t *queue = NULL;
11841
11842         if (!shared_rss)
11843                 return rte_flow_error_set(error, EINVAL,
11844                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11845                                           "invalid shared action");
11846         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11847         if (remaining)
11848                 return rte_flow_error_set(error, EBUSY,
11849                                           RTE_FLOW_ERROR_TYPE_ACTION,
11850                                           NULL,
11851                                           "shared rss hrxq has references");
11852         queue = shared_rss->ind_tbl->queues;
11853         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11854         if (remaining)
11855                 return rte_flow_error_set(error, EBUSY,
11856                                           RTE_FLOW_ERROR_TYPE_ACTION,
11857                                           NULL,
11858                                           "shared rss indirection table has"
11859                                           " references");
11860         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11861                                          0, 0, __ATOMIC_ACQUIRE,
11862                                          __ATOMIC_RELAXED))
11863                 return rte_flow_error_set(error, EBUSY,
11864                                           RTE_FLOW_ERROR_TYPE_ACTION,
11865                                           NULL,
11866                                           "shared rss has references");
11867         mlx5_free(queue);
11868         rte_spinlock_lock(&priv->shared_act_sl);
11869         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11870                      &priv->rss_shared_actions, idx, shared_rss, next);
11871         rte_spinlock_unlock(&priv->shared_act_sl);
11872         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11873                         idx);
11874         return 0;
11875 }
11876
11877 /**
11878  * Create shared action, lock free,
11879  * (mutex should be acquired by caller).
11880  * Dispatcher for action type specific call.
11881  *
11882  * @param[in] dev
11883  *   Pointer to the Ethernet device structure.
11884  * @param[in] conf
11885  *   Shared action configuration.
11886  * @param[in] action
11887  *   Action specification used to create shared action.
11888  * @param[out] error
11889  *   Perform verbose error reporting if not NULL. Initialized in case of
11890  *   error only.
11891  *
11892  * @return
11893  *   A valid shared action handle in case of success, NULL otherwise and
11894  *   rte_errno is set.
11895  */
11896 static struct rte_flow_shared_action *
11897 flow_dv_action_create(struct rte_eth_dev *dev,
11898                       const struct rte_flow_shared_action_conf *conf,
11899                       const struct rte_flow_action *action,
11900                       struct rte_flow_error *err)
11901 {
11902         uint32_t idx = 0;
11903         uint32_t ret = 0;
11904
11905         switch (action->type) {
11906         case RTE_FLOW_ACTION_TYPE_RSS:
11907                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11908                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11909                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11910                 break;
11911         case RTE_FLOW_ACTION_TYPE_AGE:
11912                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11913                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11914                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11915                 if (ret) {
11916                         struct mlx5_aso_age_action *aso_age =
11917                                               flow_aso_age_get_by_idx(dev, ret);
11918
11919                         if (!aso_age->age_params.context)
11920                                 aso_age->age_params.context =
11921                                                          (void *)(uintptr_t)idx;
11922                 }
11923                 break;
11924         default:
11925                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11926                                    NULL, "action type not supported");
11927                 break;
11928         }
11929         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11930 }
11931
11932 /**
11933  * Destroy the shared action.
11934  * Release action related resources on the NIC and the memory.
11935  * Lock free, (mutex should be acquired by caller).
11936  * Dispatcher for action type specific call.
11937  *
11938  * @param[in] dev
11939  *   Pointer to the Ethernet device structure.
11940  * @param[in] action
11941  *   The shared action object to be removed.
11942  * @param[out] error
11943  *   Perform verbose error reporting if not NULL. Initialized in case of
11944  *   error only.
11945  *
11946  * @return
11947  *   0 on success, otherwise negative errno value.
11948  */
11949 static int
11950 flow_dv_action_destroy(struct rte_eth_dev *dev,
11951                        struct rte_flow_shared_action *action,
11952                        struct rte_flow_error *error)
11953 {
11954         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11955         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11956         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11957         int ret;
11958
11959         switch (type) {
11960         case MLX5_SHARED_ACTION_TYPE_RSS:
11961                 return __flow_dv_action_rss_release(dev, idx, error);
11962         case MLX5_SHARED_ACTION_TYPE_AGE:
11963                 ret = flow_dv_aso_age_release(dev, idx);
11964                 if (ret)
11965                         /*
11966                          * In this case, the last flow has a reference will
11967                          * actually release the age action.
11968                          */
11969                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11970                                 " released with references %d.", idx, ret);
11971                 return 0;
11972         default:
11973                 return rte_flow_error_set(error, ENOTSUP,
11974                                           RTE_FLOW_ERROR_TYPE_ACTION,
11975                                           NULL,
11976                                           "action type not supported");
11977         }
11978 }
11979
11980 /**
11981  * Updates in place shared RSS action configuration.
11982  *
11983  * @param[in] dev
11984  *   Pointer to the Ethernet device structure.
11985  * @param[in] idx
11986  *   The shared RSS action object ID to be updated.
11987  * @param[in] action_conf
11988  *   RSS action specification used to modify *shared_rss*.
11989  * @param[out] error
11990  *   Perform verbose error reporting if not NULL. Initialized in case of
11991  *   error only.
11992  *
11993  * @return
11994  *   0 on success, otherwise negative errno value.
11995  * @note: currently only support update of RSS queues.
11996  */
11997 static int
11998 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11999                             const struct rte_flow_action_rss *action_conf,
12000                             struct rte_flow_error *error)
12001 {
12002         struct mlx5_priv *priv = dev->data->dev_private;
12003         struct mlx5_shared_action_rss *shared_rss =
12004             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12005         int ret = 0;
12006         void *queue = NULL;
12007         uint16_t *queue_old = NULL;
12008         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12009
12010         if (!shared_rss)
12011                 return rte_flow_error_set(error, EINVAL,
12012                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12013                                           "invalid shared action to update");
12014         queue = mlx5_malloc(MLX5_MEM_ZERO,
12015                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12016                             0, SOCKET_ID_ANY);
12017         if (!queue)
12018                 return rte_flow_error_set(error, ENOMEM,
12019                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12020                                           NULL,
12021                                           "cannot allocate resource memory");
12022         memcpy(queue, action_conf->queue, queue_size);
12023         MLX5_ASSERT(shared_rss->ind_tbl);
12024         rte_spinlock_lock(&shared_rss->action_rss_sl);
12025         queue_old = shared_rss->ind_tbl->queues;
12026         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12027                                         queue, action_conf->queue_num, true);
12028         if (ret) {
12029                 mlx5_free(queue);
12030                 ret = rte_flow_error_set(error, rte_errno,
12031                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12032                                           "cannot update indirection table");
12033         } else {
12034                 mlx5_free(queue_old);
12035                 shared_rss->origin.queue = queue;
12036                 shared_rss->origin.queue_num = action_conf->queue_num;
12037         }
12038         rte_spinlock_unlock(&shared_rss->action_rss_sl);
12039         return ret;
12040 }
12041
12042 /**
12043  * Updates in place shared action configuration, lock free,
12044  * (mutex should be acquired by caller).
12045  *
12046  * @param[in] dev
12047  *   Pointer to the Ethernet device structure.
12048  * @param[in] action
12049  *   The shared action object to be updated.
12050  * @param[in] action_conf
12051  *   Action specification used to modify *action*.
12052  *   *action_conf* should be of type correlating with type of the *action*,
12053  *   otherwise considered as invalid.
12054  * @param[out] error
12055  *   Perform verbose error reporting if not NULL. Initialized in case of
12056  *   error only.
12057  *
12058  * @return
12059  *   0 on success, otherwise negative errno value.
12060  */
12061 static int
12062 flow_dv_action_update(struct rte_eth_dev *dev,
12063                         struct rte_flow_shared_action *action,
12064                         const void *action_conf,
12065                         struct rte_flow_error *err)
12066 {
12067         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12068         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12069         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12070
12071         switch (type) {
12072         case MLX5_SHARED_ACTION_TYPE_RSS:
12073                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12074         default:
12075                 return rte_flow_error_set(err, ENOTSUP,
12076                                           RTE_FLOW_ERROR_TYPE_ACTION,
12077                                           NULL,
12078                                           "action type update not supported");
12079         }
12080 }
12081
12082 static int
12083 flow_dv_action_query(struct rte_eth_dev *dev,
12084                      const struct rte_flow_shared_action *action, void *data,
12085                      struct rte_flow_error *error)
12086 {
12087         struct mlx5_age_param *age_param;
12088         struct rte_flow_query_age *resp;
12089         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12090         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12091         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12092
12093         switch (type) {
12094         case MLX5_SHARED_ACTION_TYPE_AGE:
12095                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12096                 resp = data;
12097                 resp->aged = __atomic_load_n(&age_param->state,
12098                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
12099                                                                           1 : 0;
12100                 resp->sec_since_last_hit_valid = !resp->aged;
12101                 if (resp->sec_since_last_hit_valid)
12102                         resp->sec_since_last_hit = __atomic_load_n
12103                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12104                 return 0;
12105         default:
12106                 return rte_flow_error_set(error, ENOTSUP,
12107                                           RTE_FLOW_ERROR_TYPE_ACTION,
12108                                           NULL,
12109                                           "action type query not supported");
12110         }
12111 }
12112
12113 /**
12114  * Query a dv flow  rule for its statistics via devx.
12115  *
12116  * @param[in] dev
12117  *   Pointer to Ethernet device.
12118  * @param[in] flow
12119  *   Pointer to the sub flow.
12120  * @param[out] data
12121  *   data retrieved by the query.
12122  * @param[out] error
12123  *   Perform verbose error reporting if not NULL.
12124  *
12125  * @return
12126  *   0 on success, a negative errno value otherwise and rte_errno is set.
12127  */
12128 static int
12129 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12130                     void *data, struct rte_flow_error *error)
12131 {
12132         struct mlx5_priv *priv = dev->data->dev_private;
12133         struct rte_flow_query_count *qc = data;
12134
12135         if (!priv->config.devx)
12136                 return rte_flow_error_set(error, ENOTSUP,
12137                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12138                                           NULL,
12139                                           "counters are not supported");
12140         if (flow->counter) {
12141                 uint64_t pkts, bytes;
12142                 struct mlx5_flow_counter *cnt;
12143
12144                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12145                                                  NULL);
12146                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12147                                                &bytes);
12148
12149                 if (err)
12150                         return rte_flow_error_set(error, -err,
12151                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12152                                         NULL, "cannot read counters");
12153                 qc->hits_set = 1;
12154                 qc->bytes_set = 1;
12155                 qc->hits = pkts - cnt->hits;
12156                 qc->bytes = bytes - cnt->bytes;
12157                 if (qc->reset) {
12158                         cnt->hits = pkts;
12159                         cnt->bytes = bytes;
12160                 }
12161                 return 0;
12162         }
12163         return rte_flow_error_set(error, EINVAL,
12164                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12165                                   NULL,
12166                                   "counters are not available");
12167 }
12168
12169 /**
12170  * Query a flow rule AGE action for aging information.
12171  *
12172  * @param[in] dev
12173  *   Pointer to Ethernet device.
12174  * @param[in] flow
12175  *   Pointer to the sub flow.
12176  * @param[out] data
12177  *   data retrieved by the query.
12178  * @param[out] error
12179  *   Perform verbose error reporting if not NULL.
12180  *
12181  * @return
12182  *   0 on success, a negative errno value otherwise and rte_errno is set.
12183  */
12184 static int
12185 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12186                   void *data, struct rte_flow_error *error)
12187 {
12188         struct rte_flow_query_age *resp = data;
12189         struct mlx5_age_param *age_param;
12190
12191         if (flow->age) {
12192                 struct mlx5_aso_age_action *act =
12193                                      flow_aso_age_get_by_idx(dev, flow->age);
12194
12195                 age_param = &act->age_params;
12196         } else if (flow->counter) {
12197                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12198
12199                 if (!age_param || !age_param->timeout)
12200                         return rte_flow_error_set
12201                                         (error, EINVAL,
12202                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12203                                          NULL, "cannot read age data");
12204         } else {
12205                 return rte_flow_error_set(error, EINVAL,
12206                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12207                                           NULL, "age data not available");
12208         }
12209         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12210                                      AGE_TMOUT ? 1 : 0;
12211         resp->sec_since_last_hit_valid = !resp->aged;
12212         if (resp->sec_since_last_hit_valid)
12213                 resp->sec_since_last_hit = __atomic_load_n
12214                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12215         return 0;
12216 }
12217
12218 /**
12219  * Query a flow.
12220  *
12221  * @see rte_flow_query()
12222  * @see rte_flow_ops
12223  */
12224 static int
12225 flow_dv_query(struct rte_eth_dev *dev,
12226               struct rte_flow *flow __rte_unused,
12227               const struct rte_flow_action *actions __rte_unused,
12228               void *data __rte_unused,
12229               struct rte_flow_error *error __rte_unused)
12230 {
12231         int ret = -EINVAL;
12232
12233         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12234                 switch (actions->type) {
12235                 case RTE_FLOW_ACTION_TYPE_VOID:
12236                         break;
12237                 case RTE_FLOW_ACTION_TYPE_COUNT:
12238                         ret = flow_dv_query_count(dev, flow, data, error);
12239                         break;
12240                 case RTE_FLOW_ACTION_TYPE_AGE:
12241                         ret = flow_dv_query_age(dev, flow, data, error);
12242                         break;
12243                 default:
12244                         return rte_flow_error_set(error, ENOTSUP,
12245                                                   RTE_FLOW_ERROR_TYPE_ACTION,
12246                                                   actions,
12247                                                   "action not supported");
12248                 }
12249         }
12250         return ret;
12251 }
12252
12253 /**
12254  * Destroy the meter table set.
12255  * Lock free, (mutex should be acquired by caller).
12256  *
12257  * @param[in] dev
12258  *   Pointer to Ethernet device.
12259  * @param[in] tbl
12260  *   Pointer to the meter table set.
12261  *
12262  * @return
12263  *   Always 0.
12264  */
12265 static int
12266 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12267                         struct mlx5_meter_domains_infos *tbl)
12268 {
12269         struct mlx5_priv *priv = dev->data->dev_private;
12270         struct mlx5_meter_domains_infos *mtd =
12271                                 (struct mlx5_meter_domains_infos *)tbl;
12272
12273         if (!mtd || !priv->config.dv_flow_en)
12274                 return 0;
12275         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12276                 claim_zero(mlx5_flow_os_destroy_flow
12277                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12278         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12279                 claim_zero(mlx5_flow_os_destroy_flow
12280                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12281         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12282                 claim_zero(mlx5_flow_os_destroy_flow
12283                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12284         if (mtd->egress.color_matcher)
12285                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12286                            (mtd->egress.color_matcher));
12287         if (mtd->egress.any_matcher)
12288                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12289                            (mtd->egress.any_matcher));
12290         if (mtd->egress.tbl)
12291                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12292         if (mtd->egress.sfx_tbl)
12293                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12294         if (mtd->ingress.color_matcher)
12295                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12296                            (mtd->ingress.color_matcher));
12297         if (mtd->ingress.any_matcher)
12298                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12299                            (mtd->ingress.any_matcher));
12300         if (mtd->ingress.tbl)
12301                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12302         if (mtd->ingress.sfx_tbl)
12303                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12304                                              mtd->ingress.sfx_tbl);
12305         if (mtd->transfer.color_matcher)
12306                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12307                            (mtd->transfer.color_matcher));
12308         if (mtd->transfer.any_matcher)
12309                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12310                            (mtd->transfer.any_matcher));
12311         if (mtd->transfer.tbl)
12312                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12313         if (mtd->transfer.sfx_tbl)
12314                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12315                                              mtd->transfer.sfx_tbl);
12316         if (mtd->drop_actn)
12317                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12318         mlx5_free(mtd);
12319         return 0;
12320 }
12321
12322 /* Number of meter flow actions, count and jump or count and drop. */
12323 #define METER_ACTIONS 2
12324
12325 /**
12326  * Create specify domain meter table and suffix table.
12327  *
12328  * @param[in] dev
12329  *   Pointer to Ethernet device.
12330  * @param[in,out] mtb
12331  *   Pointer to DV meter table set.
12332  * @param[in] egress
12333  *   Table attribute.
12334  * @param[in] transfer
12335  *   Table attribute.
12336  * @param[in] color_reg_c_idx
12337  *   Reg C index for color match.
12338  *
12339  * @return
12340  *   0 on success, -1 otherwise and rte_errno is set.
12341  */
12342 static int
12343 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12344                            struct mlx5_meter_domains_infos *mtb,
12345                            uint8_t egress, uint8_t transfer,
12346                            uint32_t color_reg_c_idx)
12347 {
12348         struct mlx5_priv *priv = dev->data->dev_private;
12349         struct mlx5_dev_ctx_shared *sh = priv->sh;
12350         struct mlx5_flow_dv_match_params mask = {
12351                 .size = sizeof(mask.buf),
12352         };
12353         struct mlx5_flow_dv_match_params value = {
12354                 .size = sizeof(value.buf),
12355         };
12356         struct mlx5dv_flow_matcher_attr dv_attr = {
12357                 .type = IBV_FLOW_ATTR_NORMAL,
12358                 .priority = 0,
12359                 .match_criteria_enable = 0,
12360                 .match_mask = (void *)&mask,
12361         };
12362         void *actions[METER_ACTIONS];
12363         struct mlx5_meter_domain_info *dtb;
12364         struct rte_flow_error error;
12365         int i = 0;
12366         int ret;
12367
12368         if (transfer)
12369                 dtb = &mtb->transfer;
12370         else if (egress)
12371                 dtb = &mtb->egress;
12372         else
12373                 dtb = &mtb->ingress;
12374         /* Create the meter table with METER level. */
12375         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12376                                             egress, transfer, false, NULL, 0,
12377                                             0, &error);
12378         if (!dtb->tbl) {
12379                 DRV_LOG(ERR, "Failed to create meter policer table.");
12380                 return -1;
12381         }
12382         /* Create the meter suffix table with SUFFIX level. */
12383         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12384                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12385                                             egress, transfer, false, NULL, 0,
12386                                             0, &error);
12387         if (!dtb->sfx_tbl) {
12388                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12389                 return -1;
12390         }
12391         /* Create matchers, Any and Color. */
12392         dv_attr.priority = 3;
12393         dv_attr.match_criteria_enable = 0;
12394         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12395                                                &dtb->any_matcher);
12396         if (ret) {
12397                 DRV_LOG(ERR, "Failed to create meter"
12398                              " policer default matcher.");
12399                 goto error_exit;
12400         }
12401         dv_attr.priority = 0;
12402         dv_attr.match_criteria_enable =
12403                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12404         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12405                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12406         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12407                                                &dtb->color_matcher);
12408         if (ret) {
12409                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12410                 goto error_exit;
12411         }
12412         if (mtb->count_actns[RTE_MTR_DROPPED])
12413                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12414         actions[i++] = mtb->drop_actn;
12415         /* Default rule: lowest priority, match any, actions: drop. */
12416         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12417                                        actions,
12418                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12419         if (ret) {
12420                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12421                 goto error_exit;
12422         }
12423         return 0;
12424 error_exit:
12425         return -1;
12426 }
12427
12428 /**
12429  * Create the needed meter and suffix tables.
12430  * Lock free, (mutex should be acquired by caller).
12431  *
12432  * @param[in] dev
12433  *   Pointer to Ethernet device.
12434  * @param[in] fm
12435  *   Pointer to the flow meter.
12436  *
12437  * @return
12438  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12439  */
12440 static struct mlx5_meter_domains_infos *
12441 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12442                        const struct mlx5_flow_meter *fm)
12443 {
12444         struct mlx5_priv *priv = dev->data->dev_private;
12445         struct mlx5_meter_domains_infos *mtb;
12446         int ret;
12447         int i;
12448
12449         if (!priv->mtr_en) {
12450                 rte_errno = ENOTSUP;
12451                 return NULL;
12452         }
12453         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12454         if (!mtb) {
12455                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12456                 return NULL;
12457         }
12458         /* Create meter count actions */
12459         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12460                 struct mlx5_flow_counter *cnt;
12461                 if (!fm->policer_stats.cnt[i])
12462                         continue;
12463                 cnt = flow_dv_counter_get_by_idx(dev,
12464                       fm->policer_stats.cnt[i], NULL);
12465                 mtb->count_actns[i] = cnt->action;
12466         }
12467         /* Create drop action. */
12468         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12469         if (ret) {
12470                 DRV_LOG(ERR, "Failed to create drop action.");
12471                 goto error_exit;
12472         }
12473         /* Egress meter table. */
12474         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12475         if (ret) {
12476                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12477                 goto error_exit;
12478         }
12479         /* Ingress meter table. */
12480         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12481         if (ret) {
12482                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12483                 goto error_exit;
12484         }
12485         /* FDB meter table. */
12486         if (priv->config.dv_esw_en) {
12487                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12488                                                  priv->mtr_color_reg);
12489                 if (ret) {
12490                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12491                         goto error_exit;
12492                 }
12493         }
12494         return mtb;
12495 error_exit:
12496         flow_dv_destroy_mtr_tbl(dev, mtb);
12497         return NULL;
12498 }
12499
12500 /**
12501  * Destroy domain policer rule.
12502  *
12503  * @param[in] dt
12504  *   Pointer to domain table.
12505  */
12506 static void
12507 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12508 {
12509         int i;
12510
12511         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12512                 if (dt->policer_rules[i]) {
12513                         claim_zero(mlx5_flow_os_destroy_flow
12514                                    (dt->policer_rules[i]));
12515                         dt->policer_rules[i] = NULL;
12516                 }
12517         }
12518         if (dt->jump_actn) {
12519                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12520                 dt->jump_actn = NULL;
12521         }
12522 }
12523
12524 /**
12525  * Destroy policer rules.
12526  *
12527  * @param[in] dev
12528  *   Pointer to Ethernet device.
12529  * @param[in] fm
12530  *   Pointer to flow meter structure.
12531  * @param[in] attr
12532  *   Pointer to flow attributes.
12533  *
12534  * @return
12535  *   Always 0.
12536  */
12537 static int
12538 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12539                               const struct mlx5_flow_meter *fm,
12540                               const struct rte_flow_attr *attr)
12541 {
12542         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12543
12544         if (!mtb)
12545                 return 0;
12546         if (attr->egress)
12547                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12548         if (attr->ingress)
12549                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12550         if (attr->transfer)
12551                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12552         return 0;
12553 }
12554
12555 /**
12556  * Create specify domain meter policer rule.
12557  *
12558  * @param[in] fm
12559  *   Pointer to flow meter structure.
12560  * @param[in] mtb
12561  *   Pointer to DV meter table set.
12562  * @param[in] mtr_reg_c
12563  *   Color match REG_C.
12564  *
12565  * @return
12566  *   0 on success, -1 otherwise.
12567  */
12568 static int
12569 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12570                                     struct mlx5_meter_domain_info *dtb,
12571                                     uint8_t mtr_reg_c)
12572 {
12573         struct mlx5_flow_dv_match_params matcher = {
12574                 .size = sizeof(matcher.buf),
12575         };
12576         struct mlx5_flow_dv_match_params value = {
12577                 .size = sizeof(value.buf),
12578         };
12579         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12580         void *actions[METER_ACTIONS];
12581         int i;
12582         int ret = 0;
12583
12584         /* Create jump action. */
12585         if (!dtb->jump_actn)
12586                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12587                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12588         if (ret) {
12589                 DRV_LOG(ERR, "Failed to create policer jump action.");
12590                 goto error;
12591         }
12592         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12593                 int j = 0;
12594
12595                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12596                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12597                 if (mtb->count_actns[i])
12598                         actions[j++] = mtb->count_actns[i];
12599                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12600                         actions[j++] = mtb->drop_actn;
12601                 else
12602                         actions[j++] = dtb->jump_actn;
12603                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12604                                                (void *)&value, j, actions,
12605                                                &dtb->policer_rules[i]);
12606                 if (ret) {
12607                         DRV_LOG(ERR, "Failed to create policer rule.");
12608                         goto error;
12609                 }
12610         }
12611         return 0;
12612 error:
12613         rte_errno = errno;
12614         return -1;
12615 }
12616
12617 /**
12618  * Create policer rules.
12619  *
12620  * @param[in] dev
12621  *   Pointer to Ethernet device.
12622  * @param[in] fm
12623  *   Pointer to flow meter structure.
12624  * @param[in] attr
12625  *   Pointer to flow attributes.
12626  *
12627  * @return
12628  *   0 on success, -1 otherwise.
12629  */
12630 static int
12631 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12632                              struct mlx5_flow_meter *fm,
12633                              const struct rte_flow_attr *attr)
12634 {
12635         struct mlx5_priv *priv = dev->data->dev_private;
12636         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12637         int ret;
12638
12639         if (attr->egress) {
12640                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12641                                                 priv->mtr_color_reg);
12642                 if (ret) {
12643                         DRV_LOG(ERR, "Failed to create egress policer.");
12644                         goto error;
12645                 }
12646         }
12647         if (attr->ingress) {
12648                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12649                                                 priv->mtr_color_reg);
12650                 if (ret) {
12651                         DRV_LOG(ERR, "Failed to create ingress policer.");
12652                         goto error;
12653                 }
12654         }
12655         if (attr->transfer) {
12656                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12657                                                 priv->mtr_color_reg);
12658                 if (ret) {
12659                         DRV_LOG(ERR, "Failed to create transfer policer.");
12660                         goto error;
12661                 }
12662         }
12663         return 0;
12664 error:
12665         flow_dv_destroy_policer_rules(dev, fm, attr);
12666         return -1;
12667 }
12668
12669 /**
12670  * Validate the batch counter support in root table.
12671  *
12672  * Create a simple flow with invalid counter and drop action on root table to
12673  * validate if batch counter with offset on root table is supported or not.
12674  *
12675  * @param[in] dev
12676  *   Pointer to rte_eth_dev structure.
12677  *
12678  * @return
12679  *   0 on success, a negative errno value otherwise and rte_errno is set.
12680  */
12681 int
12682 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12683 {
12684         struct mlx5_priv *priv = dev->data->dev_private;
12685         struct mlx5_dev_ctx_shared *sh = priv->sh;
12686         struct mlx5_flow_dv_match_params mask = {
12687                 .size = sizeof(mask.buf),
12688         };
12689         struct mlx5_flow_dv_match_params value = {
12690                 .size = sizeof(value.buf),
12691         };
12692         struct mlx5dv_flow_matcher_attr dv_attr = {
12693                 .type = IBV_FLOW_ATTR_NORMAL,
12694                 .priority = 0,
12695                 .match_criteria_enable = 0,
12696                 .match_mask = (void *)&mask,
12697         };
12698         void *actions[2] = { 0 };
12699         struct mlx5_flow_tbl_resource *tbl = NULL;
12700         struct mlx5_devx_obj *dcs = NULL;
12701         void *matcher = NULL;
12702         void *flow = NULL;
12703         int ret = -1;
12704
12705         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12706         if (!tbl)
12707                 goto err;
12708         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12709         if (!dcs)
12710                 goto err;
12711         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12712                                                     &actions[0]);
12713         if (ret)
12714                 goto err;
12715         actions[1] = priv->drop_queue.hrxq->action;
12716         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12717         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12718                                                &matcher);
12719         if (ret)
12720                 goto err;
12721         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12722                                        actions, &flow);
12723 err:
12724         /*
12725          * If batch counter with offset is not supported, the driver will not
12726          * validate the invalid offset value, flow create should success.
12727          * In this case, it means batch counter is not supported in root table.
12728          *
12729          * Otherwise, if flow create is failed, counter offset is supported.
12730          */
12731         if (flow) {
12732                 DRV_LOG(INFO, "Batch counter is not supported in root "
12733                               "table. Switch to fallback mode.");
12734                 rte_errno = ENOTSUP;
12735                 ret = -rte_errno;
12736                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12737         } else {
12738                 /* Check matcher to make sure validate fail at flow create. */
12739                 if (!matcher || (matcher && errno != EINVAL))
12740                         DRV_LOG(ERR, "Unexpected error in counter offset "
12741                                      "support detection");
12742                 ret = 0;
12743         }
12744         if (actions[0])
12745                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12746         if (matcher)
12747                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12748         if (tbl)
12749                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12750         if (dcs)
12751                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12752         return ret;
12753 }
12754
12755 /**
12756  * Query a devx counter.
12757  *
12758  * @param[in] dev
12759  *   Pointer to the Ethernet device structure.
12760  * @param[in] cnt
12761  *   Index to the flow counter.
12762  * @param[in] clear
12763  *   Set to clear the counter statistics.
12764  * @param[out] pkts
12765  *   The statistics value of packets.
12766  * @param[out] bytes
12767  *   The statistics value of bytes.
12768  *
12769  * @return
12770  *   0 on success, otherwise return -1.
12771  */
12772 static int
12773 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12774                       uint64_t *pkts, uint64_t *bytes)
12775 {
12776         struct mlx5_priv *priv = dev->data->dev_private;
12777         struct mlx5_flow_counter *cnt;
12778         uint64_t inn_pkts, inn_bytes;
12779         int ret;
12780
12781         if (!priv->config.devx)
12782                 return -1;
12783
12784         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12785         if (ret)
12786                 return -1;
12787         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12788         *pkts = inn_pkts - cnt->hits;
12789         *bytes = inn_bytes - cnt->bytes;
12790         if (clear) {
12791                 cnt->hits = inn_pkts;
12792                 cnt->bytes = inn_bytes;
12793         }
12794         return 0;
12795 }
12796
12797 /**
12798  * Get aged-out flows.
12799  *
12800  * @param[in] dev
12801  *   Pointer to the Ethernet device structure.
12802  * @param[in] context
12803  *   The address of an array of pointers to the aged-out flows contexts.
12804  * @param[in] nb_contexts
12805  *   The length of context array pointers.
12806  * @param[out] error
12807  *   Perform verbose error reporting if not NULL. Initialized in case of
12808  *   error only.
12809  *
12810  * @return
12811  *   how many contexts get in success, otherwise negative errno value.
12812  *   if nb_contexts is 0, return the amount of all aged contexts.
12813  *   if nb_contexts is not 0 , return the amount of aged flows reported
12814  *   in the context array.
12815  * @note: only stub for now
12816  */
12817 static int
12818 flow_get_aged_flows(struct rte_eth_dev *dev,
12819                     void **context,
12820                     uint32_t nb_contexts,
12821                     struct rte_flow_error *error)
12822 {
12823         struct mlx5_priv *priv = dev->data->dev_private;
12824         struct mlx5_age_info *age_info;
12825         struct mlx5_age_param *age_param;
12826         struct mlx5_flow_counter *counter;
12827         struct mlx5_aso_age_action *act;
12828         int nb_flows = 0;
12829
12830         if (nb_contexts && !context)
12831                 return rte_flow_error_set(error, EINVAL,
12832                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12833                                           NULL, "empty context");
12834         age_info = GET_PORT_AGE_INFO(priv);
12835         rte_spinlock_lock(&age_info->aged_sl);
12836         LIST_FOREACH(act, &age_info->aged_aso, next) {
12837                 nb_flows++;
12838                 if (nb_contexts) {
12839                         context[nb_flows - 1] =
12840                                                 act->age_params.context;
12841                         if (!(--nb_contexts))
12842                                 break;
12843                 }
12844         }
12845         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12846                 nb_flows++;
12847                 if (nb_contexts) {
12848                         age_param = MLX5_CNT_TO_AGE(counter);
12849                         context[nb_flows - 1] = age_param->context;
12850                         if (!(--nb_contexts))
12851                                 break;
12852                 }
12853         }
12854         rte_spinlock_unlock(&age_info->aged_sl);
12855         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12856         return nb_flows;
12857 }
12858
12859 /*
12860  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12861  */
12862 static uint32_t
12863 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12864 {
12865         return flow_dv_counter_alloc(dev, 0);
12866 }
12867
12868 /**
12869  * Validate shared action.
12870  * Dispatcher for action type specific validation.
12871  *
12872  * @param[in] dev
12873  *   Pointer to the Ethernet device structure.
12874  * @param[in] conf
12875  *   Shared action configuration.
12876  * @param[in] action
12877  *   The shared action object to validate.
12878  * @param[out] error
12879  *   Perform verbose error reporting if not NULL. Initialized in case of
12880  *   error only.
12881  *
12882  * @return
12883  *   0 on success, otherwise negative errno value.
12884  */
12885 static int
12886 flow_dv_action_validate(struct rte_eth_dev *dev,
12887                         const struct rte_flow_shared_action_conf *conf,
12888                         const struct rte_flow_action *action,
12889                         struct rte_flow_error *err)
12890 {
12891         struct mlx5_priv *priv = dev->data->dev_private;
12892
12893         RTE_SET_USED(conf);
12894         switch (action->type) {
12895         case RTE_FLOW_ACTION_TYPE_RSS:
12896                 return mlx5_validate_action_rss(dev, action, err);
12897         case RTE_FLOW_ACTION_TYPE_AGE:
12898                 if (!priv->sh->aso_age_mng)
12899                         return rte_flow_error_set(err, ENOTSUP,
12900                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12901                                                 NULL,
12902                                              "shared age action not supported");
12903                 return flow_dv_validate_action_age(0, action, dev, err);
12904         default:
12905                 return rte_flow_error_set(err, ENOTSUP,
12906                                           RTE_FLOW_ERROR_TYPE_ACTION,
12907                                           NULL,
12908                                           "action type not supported");
12909         }
12910 }
12911
12912 static int
12913 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12914 {
12915         struct mlx5_priv *priv = dev->data->dev_private;
12916         int ret = 0;
12917
12918         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12919                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
12920                                                 flags);
12921                 if (ret != 0)
12922                         return ret;
12923         }
12924         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12925                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
12926                 if (ret != 0)
12927                         return ret;
12928         }
12929         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12930                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
12931                 if (ret != 0)
12932                         return ret;
12933         }
12934         return 0;
12935 }
12936
12937 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12938         .validate = flow_dv_validate,
12939         .prepare = flow_dv_prepare,
12940         .translate = flow_dv_translate,
12941         .apply = flow_dv_apply,
12942         .remove = flow_dv_remove,
12943         .destroy = flow_dv_destroy,
12944         .query = flow_dv_query,
12945         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12946         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12947         .create_policer_rules = flow_dv_create_policer_rules,
12948         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12949         .counter_alloc = flow_dv_counter_allocate,
12950         .counter_free = flow_dv_counter_free,
12951         .counter_query = flow_dv_counter_query,
12952         .get_aged_flows = flow_get_aged_flows,
12953         .action_validate = flow_dv_action_validate,
12954         .action_create = flow_dv_action_create,
12955         .action_destroy = flow_dv_action_destroy,
12956         .action_update = flow_dv_action_update,
12957         .action_query = flow_dv_action_query,
12958         .sync_domain = flow_dv_sync_domain,
12959 };
12960
12961 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12962