1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 * Initialize flow attributes structure according to flow items' types.
90 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
91 * mode. For tunnel mode, the items to be modified are the outermost ones.
94 * Pointer to item specification.
96 * Pointer to flow attributes structure.
98 * Pointer to the sub flow.
99 * @param[in] tunnel_decap
100 * Whether action is after tunnel decapsulation.
103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
104 struct mlx5_flow *dev_flow, bool tunnel_decap)
106 uint64_t layers = dev_flow->handle->layers;
109 * If layers is already initialized, it means this dev_flow is the
110 * suffix flow, the layers flags is set by the prefix flow. Need to
111 * use the layer flags from prefix flow as the suffix flow may not
112 * have the user defined items as the flow is split.
115 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
117 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
119 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
126 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
127 uint8_t next_protocol = 0xff;
128 switch (item->type) {
129 case RTE_FLOW_ITEM_TYPE_GRE:
130 case RTE_FLOW_ITEM_TYPE_NVGRE:
131 case RTE_FLOW_ITEM_TYPE_VXLAN:
132 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
133 case RTE_FLOW_ITEM_TYPE_GENEVE:
134 case RTE_FLOW_ITEM_TYPE_MPLS:
138 case RTE_FLOW_ITEM_TYPE_IPV4:
141 if (item->mask != NULL &&
142 ((const struct rte_flow_item_ipv4 *)
143 item->mask)->hdr.next_proto_id)
145 ((const struct rte_flow_item_ipv4 *)
146 (item->spec))->hdr.next_proto_id &
147 ((const struct rte_flow_item_ipv4 *)
148 (item->mask))->hdr.next_proto_id;
149 if ((next_protocol == IPPROTO_IPIP ||
150 next_protocol == IPPROTO_IPV6) && tunnel_decap)
153 case RTE_FLOW_ITEM_TYPE_IPV6:
156 if (item->mask != NULL &&
157 ((const struct rte_flow_item_ipv6 *)
158 item->mask)->hdr.proto)
160 ((const struct rte_flow_item_ipv6 *)
161 (item->spec))->hdr.proto &
162 ((const struct rte_flow_item_ipv6 *)
163 (item->mask))->hdr.proto;
164 if ((next_protocol == IPPROTO_IPIP ||
165 next_protocol == IPPROTO_IPV6) && tunnel_decap)
168 case RTE_FLOW_ITEM_TYPE_UDP:
172 case RTE_FLOW_ITEM_TYPE_TCP:
184 * Convert rte_mtr_color to mlx5 color.
193 rte_col_2_mlx5_col(enum rte_color rcol)
196 case RTE_COLOR_GREEN:
197 return MLX5_FLOW_COLOR_GREEN;
198 case RTE_COLOR_YELLOW:
199 return MLX5_FLOW_COLOR_YELLOW;
201 return MLX5_FLOW_COLOR_RED;
205 return MLX5_FLOW_COLOR_UNDEFINED;
208 struct field_modify_info {
209 uint32_t size; /* Size of field in protocol header, in bytes. */
210 uint32_t offset; /* Offset of field in protocol header, in bytes. */
211 enum mlx5_modification_field id;
214 struct field_modify_info modify_eth[] = {
215 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
216 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
217 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
218 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
222 struct field_modify_info modify_vlan_out_first_vid[] = {
223 /* Size in bits !!! */
224 {12, 0, MLX5_MODI_OUT_FIRST_VID},
228 struct field_modify_info modify_ipv4[] = {
229 {1, 1, MLX5_MODI_OUT_IP_DSCP},
230 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
231 {4, 12, MLX5_MODI_OUT_SIPV4},
232 {4, 16, MLX5_MODI_OUT_DIPV4},
236 struct field_modify_info modify_ipv6[] = {
237 {1, 0, MLX5_MODI_OUT_IP_DSCP},
238 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
239 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
240 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
241 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
242 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
243 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
244 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
245 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
246 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
250 struct field_modify_info modify_udp[] = {
251 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
252 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
256 struct field_modify_info modify_tcp[] = {
257 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
258 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
259 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
260 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
266 uint8_t next_protocol, uint64_t *item_flags,
269 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
270 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
271 if (next_protocol == IPPROTO_IPIP) {
272 *item_flags |= MLX5_FLOW_LAYER_IPIP;
275 if (next_protocol == IPPROTO_IPV6) {
276 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
281 /* Update VLAN's VID/PCP based on input rte_flow_action.
284 * Pointer to struct rte_flow_action.
286 * Pointer to struct rte_vlan_hdr.
289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
290 struct rte_vlan_hdr *vlan)
293 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
295 ((const struct rte_flow_action_of_set_vlan_pcp *)
296 action->conf)->vlan_pcp;
297 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
298 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
299 vlan->vlan_tci |= vlan_tci;
300 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
301 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
302 vlan->vlan_tci |= rte_be_to_cpu_16
303 (((const struct rte_flow_action_of_set_vlan_vid *)
304 action->conf)->vlan_vid);
309 * Fetch 1, 2, 3 or 4 byte field from the byte array
310 * and return as unsigned integer in host-endian format.
313 * Pointer to data array.
315 * Size of field to extract.
318 * converted field in host endian format.
320 static inline uint32_t
321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
330 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
333 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
334 ret = (ret << 8) | *(data + sizeof(uint16_t));
337 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
348 * Convert modify-header action to DV specification.
350 * Data length of each action is determined by provided field description
351 * and the item mask. Data bit offset and width of each action is determined
352 * by provided item mask.
355 * Pointer to item specification.
357 * Pointer to field modification information.
358 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
359 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
360 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
362 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
363 * Negative offset value sets the same offset as source offset.
364 * size field is ignored, value is taken from source field.
365 * @param[in,out] resource
366 * Pointer to the modify-header resource.
368 * Type of modification.
370 * Pointer to the error structure.
373 * 0 on success, a negative errno value otherwise and rte_errno is set.
376 flow_dv_convert_modify_action(struct rte_flow_item *item,
377 struct field_modify_info *field,
378 struct field_modify_info *dcopy,
379 struct mlx5_flow_dv_modify_hdr_resource *resource,
380 uint32_t type, struct rte_flow_error *error)
382 uint32_t i = resource->actions_num;
383 struct mlx5_modification_cmd *actions = resource->actions;
386 * The item and mask are provided in big-endian format.
387 * The fields should be presented as in big-endian format either.
388 * Mask must be always present, it defines the actual field width.
390 MLX5_ASSERT(item->mask);
391 MLX5_ASSERT(field->size);
398 if (i >= MLX5_MAX_MODIFY_NUM)
399 return rte_flow_error_set(error, EINVAL,
400 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
401 "too many items to modify");
402 /* Fetch variable byte size mask from the array. */
403 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
404 field->offset, field->size);
409 /* Deduce actual data width in bits from mask value. */
410 off_b = rte_bsf32(mask);
411 size_b = sizeof(uint32_t) * CHAR_BIT -
412 off_b - __builtin_clz(mask);
414 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
415 actions[i] = (struct mlx5_modification_cmd) {
421 /* Convert entire record to expected big-endian format. */
422 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
423 if (type == MLX5_MODIFICATION_TYPE_COPY) {
425 actions[i].dst_field = dcopy->id;
426 actions[i].dst_offset =
427 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
428 /* Convert entire record to big-endian format. */
429 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
431 MLX5_ASSERT(item->spec);
432 data = flow_dv_fetch_field((const uint8_t *)item->spec +
433 field->offset, field->size);
434 /* Shift out the trailing masked bits from data. */
435 data = (data & mask) >> off_b;
436 actions[i].data1 = rte_cpu_to_be_32(data);
440 } while (field->size);
441 if (resource->actions_num == i)
442 return rte_flow_error_set(error, EINVAL,
443 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
444 "invalid modification flow item");
445 resource->actions_num = i;
450 * Convert modify-header set IPv4 address action to DV specification.
452 * @param[in,out] resource
453 * Pointer to the modify-header resource.
455 * Pointer to action specification.
457 * Pointer to the error structure.
460 * 0 on success, a negative errno value otherwise and rte_errno is set.
463 flow_dv_convert_action_modify_ipv4
464 (struct mlx5_flow_dv_modify_hdr_resource *resource,
465 const struct rte_flow_action *action,
466 struct rte_flow_error *error)
468 const struct rte_flow_action_set_ipv4 *conf =
469 (const struct rte_flow_action_set_ipv4 *)(action->conf);
470 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
471 struct rte_flow_item_ipv4 ipv4;
472 struct rte_flow_item_ipv4 ipv4_mask;
474 memset(&ipv4, 0, sizeof(ipv4));
475 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
476 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
477 ipv4.hdr.src_addr = conf->ipv4_addr;
478 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
480 ipv4.hdr.dst_addr = conf->ipv4_addr;
481 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
484 item.mask = &ipv4_mask;
485 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
486 MLX5_MODIFICATION_TYPE_SET, error);
490 * Convert modify-header set IPv6 address action to DV specification.
492 * @param[in,out] resource
493 * Pointer to the modify-header resource.
495 * Pointer to action specification.
497 * Pointer to the error structure.
500 * 0 on success, a negative errno value otherwise and rte_errno is set.
503 flow_dv_convert_action_modify_ipv6
504 (struct mlx5_flow_dv_modify_hdr_resource *resource,
505 const struct rte_flow_action *action,
506 struct rte_flow_error *error)
508 const struct rte_flow_action_set_ipv6 *conf =
509 (const struct rte_flow_action_set_ipv6 *)(action->conf);
510 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
511 struct rte_flow_item_ipv6 ipv6;
512 struct rte_flow_item_ipv6 ipv6_mask;
514 memset(&ipv6, 0, sizeof(ipv6));
515 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
516 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
517 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
518 sizeof(ipv6.hdr.src_addr));
519 memcpy(&ipv6_mask.hdr.src_addr,
520 &rte_flow_item_ipv6_mask.hdr.src_addr,
521 sizeof(ipv6.hdr.src_addr));
523 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
524 sizeof(ipv6.hdr.dst_addr));
525 memcpy(&ipv6_mask.hdr.dst_addr,
526 &rte_flow_item_ipv6_mask.hdr.dst_addr,
527 sizeof(ipv6.hdr.dst_addr));
530 item.mask = &ipv6_mask;
531 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
532 MLX5_MODIFICATION_TYPE_SET, error);
536 * Convert modify-header set MAC address action to DV specification.
538 * @param[in,out] resource
539 * Pointer to the modify-header resource.
541 * Pointer to action specification.
543 * Pointer to the error structure.
546 * 0 on success, a negative errno value otherwise and rte_errno is set.
549 flow_dv_convert_action_modify_mac
550 (struct mlx5_flow_dv_modify_hdr_resource *resource,
551 const struct rte_flow_action *action,
552 struct rte_flow_error *error)
554 const struct rte_flow_action_set_mac *conf =
555 (const struct rte_flow_action_set_mac *)(action->conf);
556 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
557 struct rte_flow_item_eth eth;
558 struct rte_flow_item_eth eth_mask;
560 memset(ð, 0, sizeof(eth));
561 memset(ð_mask, 0, sizeof(eth_mask));
562 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
563 memcpy(ð.src.addr_bytes, &conf->mac_addr,
564 sizeof(eth.src.addr_bytes));
565 memcpy(ð_mask.src.addr_bytes,
566 &rte_flow_item_eth_mask.src.addr_bytes,
567 sizeof(eth_mask.src.addr_bytes));
569 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
570 sizeof(eth.dst.addr_bytes));
571 memcpy(ð_mask.dst.addr_bytes,
572 &rte_flow_item_eth_mask.dst.addr_bytes,
573 sizeof(eth_mask.dst.addr_bytes));
576 item.mask = ð_mask;
577 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
578 MLX5_MODIFICATION_TYPE_SET, error);
582 * Convert modify-header set VLAN VID action to DV specification.
584 * @param[in,out] resource
585 * Pointer to the modify-header resource.
587 * Pointer to action specification.
589 * Pointer to the error structure.
592 * 0 on success, a negative errno value otherwise and rte_errno is set.
595 flow_dv_convert_action_modify_vlan_vid
596 (struct mlx5_flow_dv_modify_hdr_resource *resource,
597 const struct rte_flow_action *action,
598 struct rte_flow_error *error)
600 const struct rte_flow_action_of_set_vlan_vid *conf =
601 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
602 int i = resource->actions_num;
603 struct mlx5_modification_cmd *actions = resource->actions;
604 struct field_modify_info *field = modify_vlan_out_first_vid;
606 if (i >= MLX5_MAX_MODIFY_NUM)
607 return rte_flow_error_set(error, EINVAL,
608 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
609 "too many items to modify");
610 actions[i] = (struct mlx5_modification_cmd) {
611 .action_type = MLX5_MODIFICATION_TYPE_SET,
613 .length = field->size,
614 .offset = field->offset,
616 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
617 actions[i].data1 = conf->vlan_vid;
618 actions[i].data1 = actions[i].data1 << 16;
619 resource->actions_num = ++i;
624 * Convert modify-header set TP action to DV specification.
626 * @param[in,out] resource
627 * Pointer to the modify-header resource.
629 * Pointer to action specification.
631 * Pointer to rte_flow_item objects list.
633 * Pointer to flow attributes structure.
634 * @param[in] dev_flow
635 * Pointer to the sub flow.
636 * @param[in] tunnel_decap
637 * Whether action is after tunnel decapsulation.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_tp
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
650 bool tunnel_decap, struct rte_flow_error *error)
652 const struct rte_flow_action_set_tp *conf =
653 (const struct rte_flow_action_set_tp *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_udp udp;
656 struct rte_flow_item_udp udp_mask;
657 struct rte_flow_item_tcp tcp;
658 struct rte_flow_item_tcp tcp_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
664 memset(&udp, 0, sizeof(udp));
665 memset(&udp_mask, 0, sizeof(udp_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
667 udp.hdr.src_port = conf->port;
668 udp_mask.hdr.src_port =
669 rte_flow_item_udp_mask.hdr.src_port;
671 udp.hdr.dst_port = conf->port;
672 udp_mask.hdr.dst_port =
673 rte_flow_item_udp_mask.hdr.dst_port;
675 item.type = RTE_FLOW_ITEM_TYPE_UDP;
677 item.mask = &udp_mask;
680 MLX5_ASSERT(attr->tcp);
681 memset(&tcp, 0, sizeof(tcp));
682 memset(&tcp_mask, 0, sizeof(tcp_mask));
683 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
684 tcp.hdr.src_port = conf->port;
685 tcp_mask.hdr.src_port =
686 rte_flow_item_tcp_mask.hdr.src_port;
688 tcp.hdr.dst_port = conf->port;
689 tcp_mask.hdr.dst_port =
690 rte_flow_item_tcp_mask.hdr.dst_port;
692 item.type = RTE_FLOW_ITEM_TYPE_TCP;
694 item.mask = &tcp_mask;
697 return flow_dv_convert_modify_action(&item, field, NULL, resource,
698 MLX5_MODIFICATION_TYPE_SET, error);
702 * Convert modify-header set TTL action to DV specification.
704 * @param[in,out] resource
705 * Pointer to the modify-header resource.
707 * Pointer to action specification.
709 * Pointer to rte_flow_item objects list.
711 * Pointer to flow attributes structure.
712 * @param[in] dev_flow
713 * Pointer to the sub flow.
714 * @param[in] tunnel_decap
715 * Whether action is after tunnel decapsulation.
717 * Pointer to the error structure.
720 * 0 on success, a negative errno value otherwise and rte_errno is set.
723 flow_dv_convert_action_modify_ttl
724 (struct mlx5_flow_dv_modify_hdr_resource *resource,
725 const struct rte_flow_action *action,
726 const struct rte_flow_item *items,
727 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
728 bool tunnel_decap, struct rte_flow_error *error)
730 const struct rte_flow_action_set_ttl *conf =
731 (const struct rte_flow_action_set_ttl *)(action->conf);
732 struct rte_flow_item item;
733 struct rte_flow_item_ipv4 ipv4;
734 struct rte_flow_item_ipv4 ipv4_mask;
735 struct rte_flow_item_ipv6 ipv6;
736 struct rte_flow_item_ipv6 ipv6_mask;
737 struct field_modify_info *field;
740 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
742 memset(&ipv4, 0, sizeof(ipv4));
743 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
744 ipv4.hdr.time_to_live = conf->ttl_value;
745 ipv4_mask.hdr.time_to_live = 0xFF;
746 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
748 item.mask = &ipv4_mask;
751 MLX5_ASSERT(attr->ipv6);
752 memset(&ipv6, 0, sizeof(ipv6));
753 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
754 ipv6.hdr.hop_limits = conf->ttl_value;
755 ipv6_mask.hdr.hop_limits = 0xFF;
756 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
758 item.mask = &ipv6_mask;
761 return flow_dv_convert_modify_action(&item, field, NULL, resource,
762 MLX5_MODIFICATION_TYPE_SET, error);
766 * Convert modify-header decrement TTL action to DV specification.
768 * @param[in,out] resource
769 * Pointer to the modify-header resource.
771 * Pointer to action specification.
773 * Pointer to rte_flow_item objects list.
775 * Pointer to flow attributes structure.
776 * @param[in] dev_flow
777 * Pointer to the sub flow.
778 * @param[in] tunnel_decap
779 * Whether action is after tunnel decapsulation.
781 * Pointer to the error structure.
784 * 0 on success, a negative errno value otherwise and rte_errno is set.
787 flow_dv_convert_action_modify_dec_ttl
788 (struct mlx5_flow_dv_modify_hdr_resource *resource,
789 const struct rte_flow_item *items,
790 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
791 bool tunnel_decap, struct rte_flow_error *error)
793 struct rte_flow_item item;
794 struct rte_flow_item_ipv4 ipv4;
795 struct rte_flow_item_ipv4 ipv4_mask;
796 struct rte_flow_item_ipv6 ipv6;
797 struct rte_flow_item_ipv6 ipv6_mask;
798 struct field_modify_info *field;
801 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
803 memset(&ipv4, 0, sizeof(ipv4));
804 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
805 ipv4.hdr.time_to_live = 0xFF;
806 ipv4_mask.hdr.time_to_live = 0xFF;
807 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
809 item.mask = &ipv4_mask;
812 MLX5_ASSERT(attr->ipv6);
813 memset(&ipv6, 0, sizeof(ipv6));
814 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
815 ipv6.hdr.hop_limits = 0xFF;
816 ipv6_mask.hdr.hop_limits = 0xFF;
817 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
819 item.mask = &ipv6_mask;
822 return flow_dv_convert_modify_action(&item, field, NULL, resource,
823 MLX5_MODIFICATION_TYPE_ADD, error);
827 * Convert modify-header increment/decrement TCP Sequence number
828 * to DV specification.
830 * @param[in,out] resource
831 * Pointer to the modify-header resource.
833 * Pointer to action specification.
835 * Pointer to the error structure.
838 * 0 on success, a negative errno value otherwise and rte_errno is set.
841 flow_dv_convert_action_modify_tcp_seq
842 (struct mlx5_flow_dv_modify_hdr_resource *resource,
843 const struct rte_flow_action *action,
844 struct rte_flow_error *error)
846 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
847 uint64_t value = rte_be_to_cpu_32(*conf);
848 struct rte_flow_item item;
849 struct rte_flow_item_tcp tcp;
850 struct rte_flow_item_tcp tcp_mask;
852 memset(&tcp, 0, sizeof(tcp));
853 memset(&tcp_mask, 0, sizeof(tcp_mask));
854 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
856 * The HW has no decrement operation, only increment operation.
857 * To simulate decrement X from Y using increment operation
858 * we need to add UINT32_MAX X times to Y.
859 * Each adding of UINT32_MAX decrements Y by 1.
862 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
863 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
864 item.type = RTE_FLOW_ITEM_TYPE_TCP;
866 item.mask = &tcp_mask;
867 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
868 MLX5_MODIFICATION_TYPE_ADD, error);
872 * Convert modify-header increment/decrement TCP Acknowledgment number
873 * to DV specification.
875 * @param[in,out] resource
876 * Pointer to the modify-header resource.
878 * Pointer to action specification.
880 * Pointer to the error structure.
883 * 0 on success, a negative errno value otherwise and rte_errno is set.
886 flow_dv_convert_action_modify_tcp_ack
887 (struct mlx5_flow_dv_modify_hdr_resource *resource,
888 const struct rte_flow_action *action,
889 struct rte_flow_error *error)
891 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
892 uint64_t value = rte_be_to_cpu_32(*conf);
893 struct rte_flow_item item;
894 struct rte_flow_item_tcp tcp;
895 struct rte_flow_item_tcp tcp_mask;
897 memset(&tcp, 0, sizeof(tcp));
898 memset(&tcp_mask, 0, sizeof(tcp_mask));
899 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
901 * The HW has no decrement operation, only increment operation.
902 * To simulate decrement X from Y using increment operation
903 * we need to add UINT32_MAX X times to Y.
904 * Each adding of UINT32_MAX decrements Y by 1.
907 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
908 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
909 item.type = RTE_FLOW_ITEM_TYPE_TCP;
911 item.mask = &tcp_mask;
912 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
916 static enum mlx5_modification_field reg_to_field[] = {
917 [REG_NON] = MLX5_MODI_OUT_NONE,
918 [REG_A] = MLX5_MODI_META_DATA_REG_A,
919 [REG_B] = MLX5_MODI_META_DATA_REG_B,
920 [REG_C_0] = MLX5_MODI_META_REG_C_0,
921 [REG_C_1] = MLX5_MODI_META_REG_C_1,
922 [REG_C_2] = MLX5_MODI_META_REG_C_2,
923 [REG_C_3] = MLX5_MODI_META_REG_C_3,
924 [REG_C_4] = MLX5_MODI_META_REG_C_4,
925 [REG_C_5] = MLX5_MODI_META_REG_C_5,
926 [REG_C_6] = MLX5_MODI_META_REG_C_6,
927 [REG_C_7] = MLX5_MODI_META_REG_C_7,
931 * Convert register set to DV specification.
933 * @param[in,out] resource
934 * Pointer to the modify-header resource.
936 * Pointer to action specification.
938 * Pointer to the error structure.
941 * 0 on success, a negative errno value otherwise and rte_errno is set.
944 flow_dv_convert_action_set_reg
945 (struct mlx5_flow_dv_modify_hdr_resource *resource,
946 const struct rte_flow_action *action,
947 struct rte_flow_error *error)
949 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
950 struct mlx5_modification_cmd *actions = resource->actions;
951 uint32_t i = resource->actions_num;
953 if (i >= MLX5_MAX_MODIFY_NUM)
954 return rte_flow_error_set(error, EINVAL,
955 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
956 "too many items to modify");
957 MLX5_ASSERT(conf->id != REG_NON);
958 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
959 actions[i] = (struct mlx5_modification_cmd) {
960 .action_type = MLX5_MODIFICATION_TYPE_SET,
961 .field = reg_to_field[conf->id],
963 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
964 actions[i].data1 = rte_cpu_to_be_32(conf->data);
966 resource->actions_num = i;
971 * Convert SET_TAG action to DV specification.
974 * Pointer to the rte_eth_dev structure.
975 * @param[in,out] resource
976 * Pointer to the modify-header resource.
978 * Pointer to action specification.
980 * Pointer to the error structure.
983 * 0 on success, a negative errno value otherwise and rte_errno is set.
986 flow_dv_convert_action_set_tag
987 (struct rte_eth_dev *dev,
988 struct mlx5_flow_dv_modify_hdr_resource *resource,
989 const struct rte_flow_action_set_tag *conf,
990 struct rte_flow_error *error)
992 rte_be32_t data = rte_cpu_to_be_32(conf->data);
993 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
994 struct rte_flow_item item = {
998 struct field_modify_info reg_c_x[] = {
1001 enum mlx5_modification_field reg_type;
1004 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1007 MLX5_ASSERT(ret != REG_NON);
1008 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009 reg_type = reg_to_field[ret];
1010 MLX5_ASSERT(reg_type > 0);
1011 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013 MLX5_MODIFICATION_TYPE_SET, error);
1017 * Convert internal COPY_REG action to DV specification.
1020 * Pointer to the rte_eth_dev structure.
1021 * @param[in,out] res
1022 * Pointer to the modify-header resource.
1024 * Pointer to action specification.
1026 * Pointer to the error structure.
1029 * 0 on success, a negative errno value otherwise and rte_errno is set.
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033 struct mlx5_flow_dv_modify_hdr_resource *res,
1034 const struct rte_flow_action *action,
1035 struct rte_flow_error *error)
1037 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039 struct rte_flow_item item = {
1043 struct field_modify_info reg_src[] = {
1044 {4, 0, reg_to_field[conf->src]},
1047 struct field_modify_info reg_dst = {
1049 .id = reg_to_field[conf->dst],
1051 /* Adjust reg_c[0] usage according to reported mask. */
1052 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053 struct mlx5_priv *priv = dev->data->dev_private;
1054 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1056 MLX5_ASSERT(reg_c0);
1057 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058 if (conf->dst == REG_C_0) {
1059 /* Copy to reg_c[0], within mask only. */
1060 reg_dst.offset = rte_bsf32(reg_c0);
1062 * Mask is ignoring the enianness, because
1063 * there is no conversion in datapath.
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066 /* Copy from destination lower bits to reg_c[0]. */
1067 mask = reg_c0 >> reg_dst.offset;
1069 /* Copy from destination upper bits to reg_c[0]. */
1070 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071 rte_fls_u32(reg_c0));
1074 mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076 /* Copy from reg_c[0] to destination lower bits. */
1079 /* Copy from reg_c[0] to destination upper bits. */
1080 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081 (rte_fls_u32(reg_c0) -
1086 return flow_dv_convert_modify_action(&item,
1087 reg_src, ®_dst, res,
1088 MLX5_MODIFICATION_TYPE_COPY,
1093 * Convert MARK action to DV specification. This routine is used
1094 * in extensive metadata only and requires metadata register to be
1095 * handled. In legacy mode hardware tag resource is engaged.
1098 * Pointer to the rte_eth_dev structure.
1100 * Pointer to MARK action specification.
1101 * @param[in,out] resource
1102 * Pointer to the modify-header resource.
1104 * Pointer to the error structure.
1107 * 0 on success, a negative errno value otherwise and rte_errno is set.
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111 const struct rte_flow_action_mark *conf,
1112 struct mlx5_flow_dv_modify_hdr_resource *resource,
1113 struct rte_flow_error *error)
1115 struct mlx5_priv *priv = dev->data->dev_private;
1116 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117 priv->sh->dv_mark_mask);
1118 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119 struct rte_flow_item item = {
1123 struct field_modify_info reg_c_x[] = {
1129 return rte_flow_error_set(error, EINVAL,
1130 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131 NULL, "zero mark action mask");
1132 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1135 MLX5_ASSERT(reg > 0);
1136 if (reg == REG_C_0) {
1137 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138 uint32_t shl_c0 = rte_bsf32(msk_c0);
1140 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142 mask = rte_cpu_to_be_32(mask << shl_c0);
1144 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146 MLX5_MODIFICATION_TYPE_SET, error);
1150 * Get metadata register index for specified steering domain.
1153 * Pointer to the rte_eth_dev structure.
1155 * Attributes of flow to determine steering domain.
1157 * Pointer to the error structure.
1160 * positive index on success, a negative errno value otherwise
1161 * and rte_errno is set.
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165 const struct rte_flow_attr *attr,
1166 struct rte_flow_error *error)
1169 mlx5_flow_get_reg_id(dev, attr->transfer ?
1173 MLX5_METADATA_RX, 0, error);
1175 return rte_flow_error_set(error,
1176 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177 NULL, "unavailable "
1178 "metadata register");
1183 * Convert SET_META action to DV specification.
1186 * Pointer to the rte_eth_dev structure.
1187 * @param[in,out] resource
1188 * Pointer to the modify-header resource.
1190 * Attributes of flow that includes this item.
1192 * Pointer to action specification.
1194 * Pointer to the error structure.
1197 * 0 on success, a negative errno value otherwise and rte_errno is set.
1200 flow_dv_convert_action_set_meta
1201 (struct rte_eth_dev *dev,
1202 struct mlx5_flow_dv_modify_hdr_resource *resource,
1203 const struct rte_flow_attr *attr,
1204 const struct rte_flow_action_set_meta *conf,
1205 struct rte_flow_error *error)
1207 uint32_t data = conf->data;
1208 uint32_t mask = conf->mask;
1209 struct rte_flow_item item = {
1213 struct field_modify_info reg_c_x[] = {
1216 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1220 MLX5_ASSERT(reg != REG_NON);
1222 * In datapath code there is no endianness
1223 * coversions for perfromance reasons, all
1224 * pattern conversions are done in rte_flow.
1226 if (reg == REG_C_0) {
1227 struct mlx5_priv *priv = dev->data->dev_private;
1228 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1231 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233 shl_c0 = rte_bsf32(msk_c0);
1235 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1239 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1241 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242 /* The routine expects parameters in memory as big-endian ones. */
1243 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244 MLX5_MODIFICATION_TYPE_SET, error);
1248 * Convert modify-header set IPv4 DSCP action to DV specification.
1250 * @param[in,out] resource
1251 * Pointer to the modify-header resource.
1253 * Pointer to action specification.
1255 * Pointer to the error structure.
1258 * 0 on success, a negative errno value otherwise and rte_errno is set.
1261 flow_dv_convert_action_modify_ipv4_dscp
1262 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263 const struct rte_flow_action *action,
1264 struct rte_flow_error *error)
1266 const struct rte_flow_action_set_dscp *conf =
1267 (const struct rte_flow_action_set_dscp *)(action->conf);
1268 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269 struct rte_flow_item_ipv4 ipv4;
1270 struct rte_flow_item_ipv4 ipv4_mask;
1272 memset(&ipv4, 0, sizeof(ipv4));
1273 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274 ipv4.hdr.type_of_service = conf->dscp;
1275 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1277 item.mask = &ipv4_mask;
1278 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279 MLX5_MODIFICATION_TYPE_SET, error);
1283 * Convert modify-header set IPv6 DSCP action to DV specification.
1285 * @param[in,out] resource
1286 * Pointer to the modify-header resource.
1288 * Pointer to action specification.
1290 * Pointer to the error structure.
1293 * 0 on success, a negative errno value otherwise and rte_errno is set.
1296 flow_dv_convert_action_modify_ipv6_dscp
1297 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298 const struct rte_flow_action *action,
1299 struct rte_flow_error *error)
1301 const struct rte_flow_action_set_dscp *conf =
1302 (const struct rte_flow_action_set_dscp *)(action->conf);
1303 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304 struct rte_flow_item_ipv6 ipv6;
1305 struct rte_flow_item_ipv6 ipv6_mask;
1307 memset(&ipv6, 0, sizeof(ipv6));
1308 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1310 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311 * rdma-core only accept the DSCP bits byte aligned start from
1312 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313 * bits in IPv6 case as rdma-core requires byte aligned value.
1315 ipv6.hdr.vtc_flow = conf->dscp;
1316 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1318 item.mask = &ipv6_mask;
1319 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Validate MARK item.
1327 * Pointer to the rte_eth_dev structure.
1329 * Item specification.
1331 * Attributes of flow that includes this item.
1333 * Pointer to error structure.
1336 * 0 on success, a negative errno value otherwise and rte_errno is set.
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340 const struct rte_flow_item *item,
1341 const struct rte_flow_attr *attr __rte_unused,
1342 struct rte_flow_error *error)
1344 struct mlx5_priv *priv = dev->data->dev_private;
1345 struct mlx5_dev_config *config = &priv->config;
1346 const struct rte_flow_item_mark *spec = item->spec;
1347 const struct rte_flow_item_mark *mask = item->mask;
1348 const struct rte_flow_item_mark nic_mask = {
1349 .id = priv->sh->dv_mark_mask,
1353 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354 return rte_flow_error_set(error, ENOTSUP,
1355 RTE_FLOW_ERROR_TYPE_ITEM, item,
1356 "extended metadata feature"
1358 if (!mlx5_flow_ext_mreg_supported(dev))
1359 return rte_flow_error_set(error, ENOTSUP,
1360 RTE_FLOW_ERROR_TYPE_ITEM, item,
1361 "extended metadata register"
1362 " isn't supported");
1364 return rte_flow_error_set(error, ENOTSUP,
1365 RTE_FLOW_ERROR_TYPE_ITEM, item,
1366 "extended metadata register"
1367 " isn't available");
1368 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1372 return rte_flow_error_set(error, EINVAL,
1373 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1375 "data cannot be empty");
1376 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377 return rte_flow_error_set(error, EINVAL,
1378 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1380 "mark id exceeds the limit");
1384 return rte_flow_error_set(error, EINVAL,
1385 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386 "mask cannot be zero");
1388 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389 (const uint8_t *)&nic_mask,
1390 sizeof(struct rte_flow_item_mark),
1391 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1398 * Validate META item.
1401 * Pointer to the rte_eth_dev structure.
1403 * Item specification.
1405 * Attributes of flow that includes this item.
1407 * Pointer to error structure.
1410 * 0 on success, a negative errno value otherwise and rte_errno is set.
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414 const struct rte_flow_item *item,
1415 const struct rte_flow_attr *attr,
1416 struct rte_flow_error *error)
1418 struct mlx5_priv *priv = dev->data->dev_private;
1419 struct mlx5_dev_config *config = &priv->config;
1420 const struct rte_flow_item_meta *spec = item->spec;
1421 const struct rte_flow_item_meta *mask = item->mask;
1422 struct rte_flow_item_meta nic_mask = {
1429 return rte_flow_error_set(error, EINVAL,
1430 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1432 "data cannot be empty");
1433 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434 if (!mlx5_flow_ext_mreg_supported(dev))
1435 return rte_flow_error_set(error, ENOTSUP,
1436 RTE_FLOW_ERROR_TYPE_ITEM, item,
1437 "extended metadata register"
1438 " isn't supported");
1439 reg = flow_dv_get_metadata_reg(dev, attr, error);
1443 return rte_flow_error_set(error, ENOTSUP,
1444 RTE_FLOW_ERROR_TYPE_ITEM, item,
1445 "unavalable extended metadata register");
1447 return rte_flow_error_set(error, ENOTSUP,
1448 RTE_FLOW_ERROR_TYPE_ITEM, item,
1452 nic_mask.data = priv->sh->dv_meta_mask;
1453 } else if (attr->transfer) {
1454 return rte_flow_error_set(error, ENOTSUP,
1455 RTE_FLOW_ERROR_TYPE_ITEM, item,
1456 "extended metadata feature "
1457 "should be enabled when "
1458 "meta item is requested "
1459 "with e-switch mode ");
1462 mask = &rte_flow_item_meta_mask;
1464 return rte_flow_error_set(error, EINVAL,
1465 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466 "mask cannot be zero");
1468 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469 (const uint8_t *)&nic_mask,
1470 sizeof(struct rte_flow_item_meta),
1471 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1476 * Validate TAG item.
1479 * Pointer to the rte_eth_dev structure.
1481 * Item specification.
1483 * Attributes of flow that includes this item.
1485 * Pointer to error structure.
1488 * 0 on success, a negative errno value otherwise and rte_errno is set.
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492 const struct rte_flow_item *item,
1493 const struct rte_flow_attr *attr __rte_unused,
1494 struct rte_flow_error *error)
1496 const struct rte_flow_item_tag *spec = item->spec;
1497 const struct rte_flow_item_tag *mask = item->mask;
1498 const struct rte_flow_item_tag nic_mask = {
1499 .data = RTE_BE32(UINT32_MAX),
1504 if (!mlx5_flow_ext_mreg_supported(dev))
1505 return rte_flow_error_set(error, ENOTSUP,
1506 RTE_FLOW_ERROR_TYPE_ITEM, item,
1507 "extensive metadata register"
1508 " isn't supported");
1510 return rte_flow_error_set(error, EINVAL,
1511 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1513 "data cannot be empty");
1515 mask = &rte_flow_item_tag_mask;
1517 return rte_flow_error_set(error, EINVAL,
1518 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519 "mask cannot be zero");
1521 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522 (const uint8_t *)&nic_mask,
1523 sizeof(struct rte_flow_item_tag),
1524 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1527 if (mask->index != 0xff)
1528 return rte_flow_error_set(error, EINVAL,
1529 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530 "partial mask for tag index"
1531 " is not supported");
1532 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1535 MLX5_ASSERT(ret != REG_NON);
1540 * Validate vport item.
1543 * Pointer to the rte_eth_dev structure.
1545 * Item specification.
1547 * Attributes of flow that includes this item.
1548 * @param[in] item_flags
1549 * Bit-fields that holds the items detected until now.
1551 * Pointer to error structure.
1554 * 0 on success, a negative errno value otherwise and rte_errno is set.
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558 const struct rte_flow_item *item,
1559 const struct rte_flow_attr *attr,
1560 uint64_t item_flags,
1561 struct rte_flow_error *error)
1563 const struct rte_flow_item_port_id *spec = item->spec;
1564 const struct rte_flow_item_port_id *mask = item->mask;
1565 const struct rte_flow_item_port_id switch_mask = {
1568 struct mlx5_priv *esw_priv;
1569 struct mlx5_priv *dev_priv;
1572 if (!attr->transfer)
1573 return rte_flow_error_set(error, EINVAL,
1574 RTE_FLOW_ERROR_TYPE_ITEM,
1576 "match on port id is valid only"
1577 " when transfer flag is enabled");
1578 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579 return rte_flow_error_set(error, ENOTSUP,
1580 RTE_FLOW_ERROR_TYPE_ITEM, item,
1581 "multiple source ports are not"
1584 mask = &switch_mask;
1585 if (mask->id != 0xffffffff)
1586 return rte_flow_error_set(error, ENOTSUP,
1587 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1589 "no support for partial mask on"
1591 ret = mlx5_flow_item_acceptable
1592 (item, (const uint8_t *)mask,
1593 (const uint8_t *)&rte_flow_item_port_id_mask,
1594 sizeof(struct rte_flow_item_port_id),
1595 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1600 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1602 return rte_flow_error_set(error, rte_errno,
1603 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604 "failed to obtain E-Switch info for"
1606 dev_priv = mlx5_dev_to_eswitch_info(dev);
1608 return rte_flow_error_set(error, rte_errno,
1609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1611 "failed to obtain E-Switch info");
1612 if (esw_priv->domain_id != dev_priv->domain_id)
1613 return rte_flow_error_set(error, EINVAL,
1614 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615 "cannot match on a port from a"
1616 " different E-Switch");
1621 * Validate VLAN item.
1624 * Item specification.
1625 * @param[in] item_flags
1626 * Bit-fields that holds the items detected until now.
1628 * Ethernet device flow is being created on.
1630 * Pointer to error structure.
1633 * 0 on success, a negative errno value otherwise and rte_errno is set.
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637 uint64_t item_flags,
1638 struct rte_eth_dev *dev,
1639 struct rte_flow_error *error)
1641 const struct rte_flow_item_vlan *mask = item->mask;
1642 const struct rte_flow_item_vlan nic_mask = {
1643 .tci = RTE_BE16(UINT16_MAX),
1644 .inner_type = RTE_BE16(UINT16_MAX),
1647 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1649 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650 MLX5_FLOW_LAYER_INNER_L4) :
1651 (MLX5_FLOW_LAYER_OUTER_L3 |
1652 MLX5_FLOW_LAYER_OUTER_L4);
1653 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654 MLX5_FLOW_LAYER_OUTER_VLAN;
1656 if (item_flags & vlanm)
1657 return rte_flow_error_set(error, EINVAL,
1658 RTE_FLOW_ERROR_TYPE_ITEM, item,
1659 "multiple VLAN layers not supported");
1660 else if ((item_flags & l34m) != 0)
1661 return rte_flow_error_set(error, EINVAL,
1662 RTE_FLOW_ERROR_TYPE_ITEM, item,
1663 "VLAN cannot follow L3/L4 layer");
1665 mask = &rte_flow_item_vlan_mask;
1666 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667 (const uint8_t *)&nic_mask,
1668 sizeof(struct rte_flow_item_vlan),
1669 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1672 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673 struct mlx5_priv *priv = dev->data->dev_private;
1675 if (priv->vmwa_context) {
1677 * Non-NULL context means we have a virtual machine
1678 * and SR-IOV enabled, we have to create VLAN interface
1679 * to make hypervisor to setup E-Switch vport
1680 * context correctly. We avoid creating the multiple
1681 * VLAN interfaces, so we cannot support VLAN tag mask.
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ITEM,
1686 "VLAN tag mask is not"
1687 " supported in virtual"
1695 * GTP flags are contained in 1 byte of the format:
1696 * -------------------------------------------
1697 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1698 * |-----------------------------------------|
1699 * | value | Version | PT | Res | E | S | PN |
1700 * -------------------------------------------
1702 * Matching is supported only for GTP flags E, S, PN.
1704 #define MLX5_GTP_FLAGS_MASK 0x07
1707 * Validate GTP item.
1710 * Pointer to the rte_eth_dev structure.
1712 * Item specification.
1713 * @param[in] item_flags
1714 * Bit-fields that holds the items detected until now.
1716 * Pointer to error structure.
1719 * 0 on success, a negative errno value otherwise and rte_errno is set.
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723 const struct rte_flow_item *item,
1724 uint64_t item_flags,
1725 struct rte_flow_error *error)
1727 struct mlx5_priv *priv = dev->data->dev_private;
1728 const struct rte_flow_item_gtp *spec = item->spec;
1729 const struct rte_flow_item_gtp *mask = item->mask;
1730 const struct rte_flow_item_gtp nic_mask = {
1731 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1733 .teid = RTE_BE32(0xffffffff),
1736 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737 return rte_flow_error_set(error, ENOTSUP,
1738 RTE_FLOW_ERROR_TYPE_ITEM, item,
1739 "GTP support is not enabled");
1740 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741 return rte_flow_error_set(error, ENOTSUP,
1742 RTE_FLOW_ERROR_TYPE_ITEM, item,
1743 "multiple tunnel layers not"
1745 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746 return rte_flow_error_set(error, EINVAL,
1747 RTE_FLOW_ERROR_TYPE_ITEM, item,
1748 "no outer UDP layer found");
1750 mask = &rte_flow_item_gtp_mask;
1751 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752 return rte_flow_error_set(error, ENOTSUP,
1753 RTE_FLOW_ERROR_TYPE_ITEM, item,
1754 "Match is supported for GTP"
1756 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757 (const uint8_t *)&nic_mask,
1758 sizeof(struct rte_flow_item_gtp),
1759 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1763 * Validate GTP PSC item.
1766 * Item specification.
1767 * @param[in] last_item
1768 * Previous validated item in the pattern items.
1769 * @param[in] gtp_item
1770 * Previous GTP item specification.
1772 * Pointer to flow attributes.
1774 * Pointer to error structure.
1777 * 0 on success, a negative errno value otherwise and rte_errno is set.
1780 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1782 const struct rte_flow_item *gtp_item,
1783 const struct rte_flow_attr *attr,
1784 struct rte_flow_error *error)
1786 const struct rte_flow_item_gtp *gtp_spec;
1787 const struct rte_flow_item_gtp *gtp_mask;
1788 const struct rte_flow_item_gtp_psc *spec;
1789 const struct rte_flow_item_gtp_psc *mask;
1790 const struct rte_flow_item_gtp_psc nic_mask = {
1795 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1796 return rte_flow_error_set
1797 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1798 "GTP PSC item must be preceded with GTP item");
1799 gtp_spec = gtp_item->spec;
1800 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1801 /* GTP spec and E flag is requested to match zero. */
1803 (gtp_mask->v_pt_rsv_flags &
1804 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1805 return rte_flow_error_set
1806 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1807 "GTP E flag must be 1 to match GTP PSC");
1808 /* Check the flow is not created in group zero. */
1809 if (!attr->transfer && !attr->group)
1810 return rte_flow_error_set
1811 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1812 "GTP PSC is not supported for group 0");
1813 /* GTP spec is here and E flag is requested to match zero. */
1817 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1818 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1819 return rte_flow_error_set
1820 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1821 "PDU type should be smaller than 16");
1822 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1823 (const uint8_t *)&nic_mask,
1824 sizeof(struct rte_flow_item_gtp_psc),
1825 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1829 * Validate IPV4 item.
1830 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1831 * add specific validation of fragment_offset field,
1834 * Item specification.
1835 * @param[in] item_flags
1836 * Bit-fields that holds the items detected until now.
1838 * Pointer to error structure.
1841 * 0 on success, a negative errno value otherwise and rte_errno is set.
1844 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1845 uint64_t item_flags,
1847 uint16_t ether_type,
1848 struct rte_flow_error *error)
1851 const struct rte_flow_item_ipv4 *spec = item->spec;
1852 const struct rte_flow_item_ipv4 *last = item->last;
1853 const struct rte_flow_item_ipv4 *mask = item->mask;
1854 rte_be16_t fragment_offset_spec = 0;
1855 rte_be16_t fragment_offset_last = 0;
1856 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1858 .src_addr = RTE_BE32(0xffffffff),
1859 .dst_addr = RTE_BE32(0xffffffff),
1860 .type_of_service = 0xff,
1861 .fragment_offset = RTE_BE16(0xffff),
1862 .next_proto_id = 0xff,
1863 .time_to_live = 0xff,
1867 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1868 ether_type, &nic_ipv4_mask,
1869 MLX5_ITEM_RANGE_ACCEPTED, error);
1873 fragment_offset_spec = spec->hdr.fragment_offset &
1874 mask->hdr.fragment_offset;
1875 if (!fragment_offset_spec)
1878 * spec and mask are valid, enforce using full mask to make sure the
1879 * complete value is used correctly.
1881 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1882 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1883 return rte_flow_error_set(error, EINVAL,
1884 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1885 item, "must use full mask for"
1886 " fragment_offset");
1888 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1889 * indicating this is 1st fragment of fragmented packet.
1890 * This is not yet supported in MLX5, return appropriate error message.
1892 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1893 return rte_flow_error_set(error, ENOTSUP,
1894 RTE_FLOW_ERROR_TYPE_ITEM, item,
1895 "match on first fragment not "
1897 if (fragment_offset_spec && !last)
1898 return rte_flow_error_set(error, ENOTSUP,
1899 RTE_FLOW_ERROR_TYPE_ITEM, item,
1900 "specified value not supported");
1901 /* spec and last are valid, validate the specified range. */
1902 fragment_offset_last = last->hdr.fragment_offset &
1903 mask->hdr.fragment_offset;
1905 * Match on fragment_offset spec 0x2001 and last 0x3fff
1906 * means MF is 1 and frag-offset is > 0.
1907 * This packet is fragment 2nd and onward, excluding last.
1908 * This is not yet supported in MLX5, return appropriate
1911 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1912 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1913 return rte_flow_error_set(error, ENOTSUP,
1914 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1915 last, "match on following "
1916 "fragments not supported");
1918 * Match on fragment_offset spec 0x0001 and last 0x1fff
1919 * means MF is 0 and frag-offset is > 0.
1920 * This packet is last fragment of fragmented packet.
1921 * This is not yet supported in MLX5, return appropriate
1924 if (fragment_offset_spec == RTE_BE16(1) &&
1925 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1926 return rte_flow_error_set(error, ENOTSUP,
1927 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1928 last, "match on last "
1929 "fragment not supported");
1931 * Match on fragment_offset spec 0x0001 and last 0x3fff
1932 * means MF and/or frag-offset is not 0.
1933 * This is a fragmented packet.
1934 * Other range values are invalid and rejected.
1936 if (!(fragment_offset_spec == RTE_BE16(1) &&
1937 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1938 return rte_flow_error_set(error, ENOTSUP,
1939 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1940 "specified range not supported");
1945 * Validate IPV6 fragment extension item.
1948 * Item specification.
1949 * @param[in] item_flags
1950 * Bit-fields that holds the items detected until now.
1952 * Pointer to error structure.
1955 * 0 on success, a negative errno value otherwise and rte_errno is set.
1958 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1959 uint64_t item_flags,
1960 struct rte_flow_error *error)
1962 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1963 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1964 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1965 rte_be16_t frag_data_spec = 0;
1966 rte_be16_t frag_data_last = 0;
1967 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1968 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1969 MLX5_FLOW_LAYER_OUTER_L4;
1971 struct rte_flow_item_ipv6_frag_ext nic_mask = {
1973 .next_header = 0xff,
1974 .frag_data = RTE_BE16(0xffff),
1978 if (item_flags & l4m)
1979 return rte_flow_error_set(error, EINVAL,
1980 RTE_FLOW_ERROR_TYPE_ITEM, item,
1981 "ipv6 fragment extension item cannot "
1983 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1984 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1985 return rte_flow_error_set(error, EINVAL,
1986 RTE_FLOW_ERROR_TYPE_ITEM, item,
1987 "ipv6 fragment extension item must "
1988 "follow ipv6 item");
1990 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1991 if (!frag_data_spec)
1994 * spec and mask are valid, enforce using full mask to make sure the
1995 * complete value is used correctly.
1997 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1998 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1999 return rte_flow_error_set(error, EINVAL,
2000 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2001 item, "must use full mask for"
2004 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2005 * This is 1st fragment of fragmented packet.
2007 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2008 return rte_flow_error_set(error, ENOTSUP,
2009 RTE_FLOW_ERROR_TYPE_ITEM, item,
2010 "match on first fragment not "
2012 if (frag_data_spec && !last)
2013 return rte_flow_error_set(error, EINVAL,
2014 RTE_FLOW_ERROR_TYPE_ITEM, item,
2015 "specified value not supported");
2016 ret = mlx5_flow_item_acceptable
2017 (item, (const uint8_t *)mask,
2018 (const uint8_t *)&nic_mask,
2019 sizeof(struct rte_flow_item_ipv6_frag_ext),
2020 MLX5_ITEM_RANGE_ACCEPTED, error);
2023 /* spec and last are valid, validate the specified range. */
2024 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2026 * Match on frag_data spec 0x0009 and last 0xfff9
2027 * means M is 1 and frag-offset is > 0.
2028 * This packet is fragment 2nd and onward, excluding last.
2029 * This is not yet supported in MLX5, return appropriate
2032 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2033 RTE_IPV6_EHDR_MF_MASK) &&
2034 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2035 return rte_flow_error_set(error, ENOTSUP,
2036 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2037 last, "match on following "
2038 "fragments not supported");
2040 * Match on frag_data spec 0x0008 and last 0xfff8
2041 * means M is 0 and frag-offset is > 0.
2042 * This packet is last fragment of fragmented packet.
2043 * This is not yet supported in MLX5, return appropriate
2046 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2047 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2048 return rte_flow_error_set(error, ENOTSUP,
2049 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2050 last, "match on last "
2051 "fragment not supported");
2052 /* Other range values are invalid and rejected. */
2053 return rte_flow_error_set(error, EINVAL,
2054 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2055 "specified range not supported");
2059 * Validate the pop VLAN action.
2062 * Pointer to the rte_eth_dev structure.
2063 * @param[in] action_flags
2064 * Holds the actions detected until now.
2066 * Pointer to the pop vlan action.
2067 * @param[in] item_flags
2068 * The items found in this flow rule.
2070 * Pointer to flow attributes.
2072 * Pointer to error structure.
2075 * 0 on success, a negative errno value otherwise and rte_errno is set.
2078 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2079 uint64_t action_flags,
2080 const struct rte_flow_action *action,
2081 uint64_t item_flags,
2082 const struct rte_flow_attr *attr,
2083 struct rte_flow_error *error)
2085 const struct mlx5_priv *priv = dev->data->dev_private;
2089 if (!priv->sh->pop_vlan_action)
2090 return rte_flow_error_set(error, ENOTSUP,
2091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2093 "pop vlan action is not supported");
2095 return rte_flow_error_set(error, ENOTSUP,
2096 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2098 "pop vlan action not supported for "
2100 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2101 return rte_flow_error_set(error, ENOTSUP,
2102 RTE_FLOW_ERROR_TYPE_ACTION, action,
2103 "no support for multiple VLAN "
2105 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2106 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2107 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2108 return rte_flow_error_set(error, ENOTSUP,
2109 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2111 "cannot pop vlan after decap without "
2112 "match on inner vlan in the flow");
2113 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2114 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2115 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2116 return rte_flow_error_set(error, ENOTSUP,
2117 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2119 "cannot pop vlan without a "
2120 "match on (outer) vlan in the flow");
2121 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2122 return rte_flow_error_set(error, EINVAL,
2123 RTE_FLOW_ERROR_TYPE_ACTION, action,
2124 "wrong action order, port_id should "
2125 "be after pop VLAN action");
2126 if (!attr->transfer && priv->representor)
2127 return rte_flow_error_set(error, ENOTSUP,
2128 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2129 "pop vlan action for VF representor "
2130 "not supported on NIC table");
2135 * Get VLAN default info from vlan match info.
2138 * the list of item specifications.
2140 * pointer VLAN info to fill to.
2143 * 0 on success, a negative errno value otherwise and rte_errno is set.
2146 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2147 struct rte_vlan_hdr *vlan)
2149 const struct rte_flow_item_vlan nic_mask = {
2150 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2151 MLX5DV_FLOW_VLAN_VID_MASK),
2152 .inner_type = RTE_BE16(0xffff),
2157 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2158 int type = items->type;
2160 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2161 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2164 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2165 const struct rte_flow_item_vlan *vlan_m = items->mask;
2166 const struct rte_flow_item_vlan *vlan_v = items->spec;
2168 /* If VLAN item in pattern doesn't contain data, return here. */
2173 /* Only full match values are accepted */
2174 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2175 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2176 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2178 rte_be_to_cpu_16(vlan_v->tci &
2179 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2181 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2182 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2183 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2185 rte_be_to_cpu_16(vlan_v->tci &
2186 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2188 if (vlan_m->inner_type == nic_mask.inner_type)
2189 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2190 vlan_m->inner_type);
2195 * Validate the push VLAN action.
2198 * Pointer to the rte_eth_dev structure.
2199 * @param[in] action_flags
2200 * Holds the actions detected until now.
2201 * @param[in] item_flags
2202 * The items found in this flow rule.
2204 * Pointer to the action structure.
2206 * Pointer to flow attributes
2208 * Pointer to error structure.
2211 * 0 on success, a negative errno value otherwise and rte_errno is set.
2214 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2215 uint64_t action_flags,
2216 const struct rte_flow_item_vlan *vlan_m,
2217 const struct rte_flow_action *action,
2218 const struct rte_flow_attr *attr,
2219 struct rte_flow_error *error)
2221 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2222 const struct mlx5_priv *priv = dev->data->dev_private;
2224 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2225 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2226 return rte_flow_error_set(error, EINVAL,
2227 RTE_FLOW_ERROR_TYPE_ACTION, action,
2228 "invalid vlan ethertype");
2229 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2230 return rte_flow_error_set(error, EINVAL,
2231 RTE_FLOW_ERROR_TYPE_ACTION, action,
2232 "wrong action order, port_id should "
2233 "be after push VLAN");
2234 if (!attr->transfer && priv->representor)
2235 return rte_flow_error_set(error, ENOTSUP,
2236 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2237 "push vlan action for VF representor "
2238 "not supported on NIC table");
2240 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2241 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2242 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2243 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2244 !(mlx5_flow_find_action
2245 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2246 return rte_flow_error_set(error, EINVAL,
2247 RTE_FLOW_ERROR_TYPE_ACTION, action,
2248 "not full match mask on VLAN PCP and "
2249 "there is no of_set_vlan_pcp action, "
2250 "push VLAN action cannot figure out "
2253 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2254 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2255 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2256 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2257 !(mlx5_flow_find_action
2258 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, action,
2261 "not full match mask on VLAN VID and "
2262 "there is no of_set_vlan_vid action, "
2263 "push VLAN action cannot figure out "
2270 * Validate the set VLAN PCP.
2272 * @param[in] action_flags
2273 * Holds the actions detected until now.
2274 * @param[in] actions
2275 * Pointer to the list of actions remaining in the flow rule.
2277 * Pointer to error structure.
2280 * 0 on success, a negative errno value otherwise and rte_errno is set.
2283 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2284 const struct rte_flow_action actions[],
2285 struct rte_flow_error *error)
2287 const struct rte_flow_action *action = actions;
2288 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2290 if (conf->vlan_pcp > 7)
2291 return rte_flow_error_set(error, EINVAL,
2292 RTE_FLOW_ERROR_TYPE_ACTION, action,
2293 "VLAN PCP value is too big");
2294 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2295 return rte_flow_error_set(error, ENOTSUP,
2296 RTE_FLOW_ERROR_TYPE_ACTION, action,
2297 "set VLAN PCP action must follow "
2298 "the push VLAN action");
2299 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2300 return rte_flow_error_set(error, ENOTSUP,
2301 RTE_FLOW_ERROR_TYPE_ACTION, action,
2302 "Multiple VLAN PCP modification are "
2304 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2305 return rte_flow_error_set(error, EINVAL,
2306 RTE_FLOW_ERROR_TYPE_ACTION, action,
2307 "wrong action order, port_id should "
2308 "be after set VLAN PCP");
2313 * Validate the set VLAN VID.
2315 * @param[in] item_flags
2316 * Holds the items detected in this rule.
2317 * @param[in] action_flags
2318 * Holds the actions detected until now.
2319 * @param[in] actions
2320 * Pointer to the list of actions remaining in the flow rule.
2322 * Pointer to error structure.
2325 * 0 on success, a negative errno value otherwise and rte_errno is set.
2328 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2329 uint64_t action_flags,
2330 const struct rte_flow_action actions[],
2331 struct rte_flow_error *error)
2333 const struct rte_flow_action *action = actions;
2334 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2336 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2337 return rte_flow_error_set(error, EINVAL,
2338 RTE_FLOW_ERROR_TYPE_ACTION, action,
2339 "VLAN VID value is too big");
2340 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2341 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2342 return rte_flow_error_set(error, ENOTSUP,
2343 RTE_FLOW_ERROR_TYPE_ACTION, action,
2344 "set VLAN VID action must follow push"
2345 " VLAN action or match on VLAN item");
2346 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2347 return rte_flow_error_set(error, ENOTSUP,
2348 RTE_FLOW_ERROR_TYPE_ACTION, action,
2349 "Multiple VLAN VID modifications are "
2351 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2352 return rte_flow_error_set(error, EINVAL,
2353 RTE_FLOW_ERROR_TYPE_ACTION, action,
2354 "wrong action order, port_id should "
2355 "be after set VLAN VID");
2360 * Validate the FLAG action.
2363 * Pointer to the rte_eth_dev structure.
2364 * @param[in] action_flags
2365 * Holds the actions detected until now.
2367 * Pointer to flow attributes
2369 * Pointer to error structure.
2372 * 0 on success, a negative errno value otherwise and rte_errno is set.
2375 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2376 uint64_t action_flags,
2377 const struct rte_flow_attr *attr,
2378 struct rte_flow_error *error)
2380 struct mlx5_priv *priv = dev->data->dev_private;
2381 struct mlx5_dev_config *config = &priv->config;
2384 /* Fall back if no extended metadata register support. */
2385 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2386 return mlx5_flow_validate_action_flag(action_flags, attr,
2388 /* Extensive metadata mode requires registers. */
2389 if (!mlx5_flow_ext_mreg_supported(dev))
2390 return rte_flow_error_set(error, ENOTSUP,
2391 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2392 "no metadata registers "
2393 "to support flag action");
2394 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2395 return rte_flow_error_set(error, ENOTSUP,
2396 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2397 "extended metadata register"
2398 " isn't available");
2399 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2402 MLX5_ASSERT(ret > 0);
2403 if (action_flags & MLX5_FLOW_ACTION_MARK)
2404 return rte_flow_error_set(error, EINVAL,
2405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2406 "can't mark and flag in same flow");
2407 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2408 return rte_flow_error_set(error, EINVAL,
2409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2411 " actions in same flow");
2416 * Validate MARK action.
2419 * Pointer to the rte_eth_dev structure.
2421 * Pointer to action.
2422 * @param[in] action_flags
2423 * Holds the actions detected until now.
2425 * Pointer to flow attributes
2427 * Pointer to error structure.
2430 * 0 on success, a negative errno value otherwise and rte_errno is set.
2433 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2434 const struct rte_flow_action *action,
2435 uint64_t action_flags,
2436 const struct rte_flow_attr *attr,
2437 struct rte_flow_error *error)
2439 struct mlx5_priv *priv = dev->data->dev_private;
2440 struct mlx5_dev_config *config = &priv->config;
2441 const struct rte_flow_action_mark *mark = action->conf;
2444 /* Fall back if no extended metadata register support. */
2445 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2446 return mlx5_flow_validate_action_mark(action, action_flags,
2448 /* Extensive metadata mode requires registers. */
2449 if (!mlx5_flow_ext_mreg_supported(dev))
2450 return rte_flow_error_set(error, ENOTSUP,
2451 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2452 "no metadata registers "
2453 "to support mark action");
2454 if (!priv->sh->dv_mark_mask)
2455 return rte_flow_error_set(error, ENOTSUP,
2456 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2457 "extended metadata register"
2458 " isn't available");
2459 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2462 MLX5_ASSERT(ret > 0);
2464 return rte_flow_error_set(error, EINVAL,
2465 RTE_FLOW_ERROR_TYPE_ACTION, action,
2466 "configuration cannot be null");
2467 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2468 return rte_flow_error_set(error, EINVAL,
2469 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2471 "mark id exceeds the limit");
2472 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2473 return rte_flow_error_set(error, EINVAL,
2474 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2475 "can't flag and mark in same flow");
2476 if (action_flags & MLX5_FLOW_ACTION_MARK)
2477 return rte_flow_error_set(error, EINVAL,
2478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2479 "can't have 2 mark actions in same"
2485 * Validate SET_META action.
2488 * Pointer to the rte_eth_dev structure.
2490 * Pointer to the action structure.
2491 * @param[in] action_flags
2492 * Holds the actions detected until now.
2494 * Pointer to flow attributes
2496 * Pointer to error structure.
2499 * 0 on success, a negative errno value otherwise and rte_errno is set.
2502 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2503 const struct rte_flow_action *action,
2504 uint64_t action_flags __rte_unused,
2505 const struct rte_flow_attr *attr,
2506 struct rte_flow_error *error)
2508 const struct rte_flow_action_set_meta *conf;
2509 uint32_t nic_mask = UINT32_MAX;
2512 if (!mlx5_flow_ext_mreg_supported(dev))
2513 return rte_flow_error_set(error, ENOTSUP,
2514 RTE_FLOW_ERROR_TYPE_ACTION, action,
2515 "extended metadata register"
2516 " isn't supported");
2517 reg = flow_dv_get_metadata_reg(dev, attr, error);
2521 return rte_flow_error_set(error, ENOTSUP,
2522 RTE_FLOW_ERROR_TYPE_ACTION, action,
2523 "unavalable extended metadata register");
2524 if (reg != REG_A && reg != REG_B) {
2525 struct mlx5_priv *priv = dev->data->dev_private;
2527 nic_mask = priv->sh->dv_meta_mask;
2529 if (!(action->conf))
2530 return rte_flow_error_set(error, EINVAL,
2531 RTE_FLOW_ERROR_TYPE_ACTION, action,
2532 "configuration cannot be null");
2533 conf = (const struct rte_flow_action_set_meta *)action->conf;
2535 return rte_flow_error_set(error, EINVAL,
2536 RTE_FLOW_ERROR_TYPE_ACTION, action,
2537 "zero mask doesn't have any effect");
2538 if (conf->mask & ~nic_mask)
2539 return rte_flow_error_set(error, EINVAL,
2540 RTE_FLOW_ERROR_TYPE_ACTION, action,
2541 "meta data must be within reg C0");
2546 * Validate SET_TAG action.
2549 * Pointer to the rte_eth_dev structure.
2551 * Pointer to the action structure.
2552 * @param[in] action_flags
2553 * Holds the actions detected until now.
2555 * Pointer to flow attributes
2557 * Pointer to error structure.
2560 * 0 on success, a negative errno value otherwise and rte_errno is set.
2563 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2564 const struct rte_flow_action *action,
2565 uint64_t action_flags,
2566 const struct rte_flow_attr *attr,
2567 struct rte_flow_error *error)
2569 const struct rte_flow_action_set_tag *conf;
2570 const uint64_t terminal_action_flags =
2571 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2572 MLX5_FLOW_ACTION_RSS;
2575 if (!mlx5_flow_ext_mreg_supported(dev))
2576 return rte_flow_error_set(error, ENOTSUP,
2577 RTE_FLOW_ERROR_TYPE_ACTION, action,
2578 "extensive metadata register"
2579 " isn't supported");
2580 if (!(action->conf))
2581 return rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ACTION, action,
2583 "configuration cannot be null");
2584 conf = (const struct rte_flow_action_set_tag *)action->conf;
2586 return rte_flow_error_set(error, EINVAL,
2587 RTE_FLOW_ERROR_TYPE_ACTION, action,
2588 "zero mask doesn't have any effect");
2589 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2592 if (!attr->transfer && attr->ingress &&
2593 (action_flags & terminal_action_flags))
2594 return rte_flow_error_set(error, EINVAL,
2595 RTE_FLOW_ERROR_TYPE_ACTION, action,
2596 "set_tag has no effect"
2597 " with terminal actions");
2602 * Validate count action.
2605 * Pointer to rte_eth_dev structure.
2607 * Pointer to error structure.
2610 * 0 on success, a negative errno value otherwise and rte_errno is set.
2613 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2614 struct rte_flow_error *error)
2616 struct mlx5_priv *priv = dev->data->dev_private;
2618 if (!priv->config.devx)
2620 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2624 return rte_flow_error_set
2626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2628 "count action not supported");
2632 * Validate the L2 encap action.
2635 * Pointer to the rte_eth_dev structure.
2636 * @param[in] action_flags
2637 * Holds the actions detected until now.
2639 * Pointer to the action structure.
2641 * Pointer to flow attributes.
2643 * Pointer to error structure.
2646 * 0 on success, a negative errno value otherwise and rte_errno is set.
2649 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2650 uint64_t action_flags,
2651 const struct rte_flow_action *action,
2652 const struct rte_flow_attr *attr,
2653 struct rte_flow_error *error)
2655 const struct mlx5_priv *priv = dev->data->dev_private;
2657 if (!(action->conf))
2658 return rte_flow_error_set(error, EINVAL,
2659 RTE_FLOW_ERROR_TYPE_ACTION, action,
2660 "configuration cannot be null");
2661 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2662 return rte_flow_error_set(error, EINVAL,
2663 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2664 "can only have a single encap action "
2666 if (!attr->transfer && priv->representor)
2667 return rte_flow_error_set(error, ENOTSUP,
2668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2669 "encap action for VF representor "
2670 "not supported on NIC table");
2675 * Validate a decap action.
2678 * Pointer to the rte_eth_dev structure.
2679 * @param[in] action_flags
2680 * Holds the actions detected until now.
2682 * Pointer to the action structure.
2683 * @param[in] item_flags
2684 * Holds the items detected.
2686 * Pointer to flow attributes
2688 * Pointer to error structure.
2691 * 0 on success, a negative errno value otherwise and rte_errno is set.
2694 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2695 uint64_t action_flags,
2696 const struct rte_flow_action *action,
2697 const uint64_t item_flags,
2698 const struct rte_flow_attr *attr,
2699 struct rte_flow_error *error)
2701 const struct mlx5_priv *priv = dev->data->dev_private;
2703 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2704 !priv->config.decap_en)
2705 return rte_flow_error_set(error, ENOTSUP,
2706 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2707 "decap is not enabled");
2708 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2709 return rte_flow_error_set(error, ENOTSUP,
2710 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2712 MLX5_FLOW_ACTION_DECAP ? "can only "
2713 "have a single decap action" : "decap "
2714 "after encap is not supported");
2715 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2716 return rte_flow_error_set(error, EINVAL,
2717 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2718 "can't have decap action after"
2721 return rte_flow_error_set(error, ENOTSUP,
2722 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2724 "decap action not supported for "
2726 if (!attr->transfer && priv->representor)
2727 return rte_flow_error_set(error, ENOTSUP,
2728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2729 "decap action for VF representor "
2730 "not supported on NIC table");
2731 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2732 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2733 return rte_flow_error_set(error, ENOTSUP,
2734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2735 "VXLAN item should be present for VXLAN decap");
2739 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2742 * Validate the raw encap and decap actions.
2745 * Pointer to the rte_eth_dev structure.
2747 * Pointer to the decap action.
2749 * Pointer to the encap action.
2751 * Pointer to flow attributes
2752 * @param[in/out] action_flags
2753 * Holds the actions detected until now.
2754 * @param[out] actions_n
2755 * pointer to the number of actions counter.
2757 * Pointer to the action structure.
2758 * @param[in] item_flags
2759 * Holds the items detected.
2761 * Pointer to error structure.
2764 * 0 on success, a negative errno value otherwise and rte_errno is set.
2767 flow_dv_validate_action_raw_encap_decap
2768 (struct rte_eth_dev *dev,
2769 const struct rte_flow_action_raw_decap *decap,
2770 const struct rte_flow_action_raw_encap *encap,
2771 const struct rte_flow_attr *attr, uint64_t *action_flags,
2772 int *actions_n, const struct rte_flow_action *action,
2773 uint64_t item_flags, struct rte_flow_error *error)
2775 const struct mlx5_priv *priv = dev->data->dev_private;
2778 if (encap && (!encap->size || !encap->data))
2779 return rte_flow_error_set(error, EINVAL,
2780 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2781 "raw encap data cannot be empty");
2782 if (decap && encap) {
2783 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2784 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2787 else if (encap->size <=
2788 MLX5_ENCAPSULATION_DECISION_SIZE &&
2790 MLX5_ENCAPSULATION_DECISION_SIZE)
2793 else if (encap->size >
2794 MLX5_ENCAPSULATION_DECISION_SIZE &&
2796 MLX5_ENCAPSULATION_DECISION_SIZE)
2797 /* 2 L2 actions: encap and decap. */
2800 return rte_flow_error_set(error,
2802 RTE_FLOW_ERROR_TYPE_ACTION,
2803 NULL, "unsupported too small "
2804 "raw decap and too small raw "
2805 "encap combination");
2808 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2809 item_flags, attr, error);
2812 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2816 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2817 return rte_flow_error_set(error, ENOTSUP,
2818 RTE_FLOW_ERROR_TYPE_ACTION,
2820 "small raw encap size");
2821 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2822 return rte_flow_error_set(error, EINVAL,
2823 RTE_FLOW_ERROR_TYPE_ACTION,
2825 "more than one encap action");
2826 if (!attr->transfer && priv->representor)
2827 return rte_flow_error_set
2829 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2830 "encap action for VF representor "
2831 "not supported on NIC table");
2832 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2839 * Match encap_decap resource.
2842 * Pointer to the hash list.
2844 * Pointer to exist resource entry object.
2846 * Key of the new entry.
2848 * Pointer to new encap_decap resource.
2851 * 0 on matching, none-zero otherwise.
2854 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2855 struct mlx5_hlist_entry *entry,
2856 uint64_t key __rte_unused, void *cb_ctx)
2858 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2859 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2860 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2862 cache_resource = container_of(entry,
2863 struct mlx5_flow_dv_encap_decap_resource,
2865 if (resource->reformat_type == cache_resource->reformat_type &&
2866 resource->ft_type == cache_resource->ft_type &&
2867 resource->flags == cache_resource->flags &&
2868 resource->size == cache_resource->size &&
2869 !memcmp((const void *)resource->buf,
2870 (const void *)cache_resource->buf,
2877 * Allocate encap_decap resource.
2880 * Pointer to the hash list.
2882 * Pointer to exist resource entry object.
2884 * Pointer to new encap_decap resource.
2887 * 0 on matching, none-zero otherwise.
2889 struct mlx5_hlist_entry *
2890 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2891 uint64_t key __rte_unused,
2894 struct mlx5_dev_ctx_shared *sh = list->ctx;
2895 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2896 struct mlx5dv_dr_domain *domain;
2897 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2898 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2902 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2903 domain = sh->fdb_domain;
2904 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2905 domain = sh->rx_domain;
2907 domain = sh->tx_domain;
2908 /* Register new encap/decap resource. */
2909 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2911 if (!cache_resource) {
2912 rte_flow_error_set(ctx->error, ENOMEM,
2913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914 "cannot allocate resource memory");
2917 *cache_resource = *resource;
2918 cache_resource->idx = idx;
2919 ret = mlx5_flow_os_create_flow_action_packet_reformat
2920 (sh->ctx, domain, cache_resource,
2921 &cache_resource->action);
2923 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2924 rte_flow_error_set(ctx->error, ENOMEM,
2925 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2926 NULL, "cannot create action");
2930 return &cache_resource->entry;
2934 * Find existing encap/decap resource or create and register a new one.
2936 * @param[in, out] dev
2937 * Pointer to rte_eth_dev structure.
2938 * @param[in, out] resource
2939 * Pointer to encap/decap resource.
2940 * @parm[in, out] dev_flow
2941 * Pointer to the dev_flow.
2943 * pointer to error structure.
2946 * 0 on success otherwise -errno and errno is set.
2949 flow_dv_encap_decap_resource_register
2950 (struct rte_eth_dev *dev,
2951 struct mlx5_flow_dv_encap_decap_resource *resource,
2952 struct mlx5_flow *dev_flow,
2953 struct rte_flow_error *error)
2955 struct mlx5_priv *priv = dev->data->dev_private;
2956 struct mlx5_dev_ctx_shared *sh = priv->sh;
2957 struct mlx5_hlist_entry *entry;
2961 uint32_t refmt_type:8;
2963 * Header reformat actions can be shared between
2964 * non-root tables. One bit to indicate non-root
2968 uint32_t reserve:15;
2971 } encap_decap_key = {
2973 .ft_type = resource->ft_type,
2974 .refmt_type = resource->reformat_type,
2975 .is_root = !!dev_flow->dv.group,
2979 struct mlx5_flow_cb_ctx ctx = {
2985 resource->flags = dev_flow->dv.group ? 0 : 1;
2986 key64 = __rte_raw_cksum(&encap_decap_key.v32,
2987 sizeof(encap_decap_key.v32), 0);
2988 if (resource->reformat_type !=
2989 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2991 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2992 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2995 resource = container_of(entry, typeof(*resource), entry);
2996 dev_flow->dv.encap_decap = resource;
2997 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3002 * Find existing table jump resource or create and register a new one.
3004 * @param[in, out] dev
3005 * Pointer to rte_eth_dev structure.
3006 * @param[in, out] tbl
3007 * Pointer to flow table resource.
3008 * @parm[in, out] dev_flow
3009 * Pointer to the dev_flow.
3011 * pointer to error structure.
3014 * 0 on success otherwise -errno and errno is set.
3017 flow_dv_jump_tbl_resource_register
3018 (struct rte_eth_dev *dev __rte_unused,
3019 struct mlx5_flow_tbl_resource *tbl,
3020 struct mlx5_flow *dev_flow,
3021 struct rte_flow_error *error __rte_unused)
3023 struct mlx5_flow_tbl_data_entry *tbl_data =
3024 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3027 MLX5_ASSERT(tbl_data->jump.action);
3028 dev_flow->handle->rix_jump = tbl_data->idx;
3029 dev_flow->dv.jump = &tbl_data->jump;
3034 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3035 struct mlx5_cache_entry *entry, void *cb_ctx)
3037 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3038 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3039 struct mlx5_flow_dv_port_id_action_resource *res =
3040 container_of(entry, typeof(*res), entry);
3042 return ref->port_id != res->port_id;
3045 struct mlx5_cache_entry *
3046 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3047 struct mlx5_cache_entry *entry __rte_unused,
3050 struct mlx5_dev_ctx_shared *sh = list->ctx;
3051 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3052 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3053 struct mlx5_flow_dv_port_id_action_resource *cache;
3057 /* Register new port id action resource. */
3058 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3060 rte_flow_error_set(ctx->error, ENOMEM,
3061 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3062 "cannot allocate port_id action cache memory");
3066 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3070 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3071 rte_flow_error_set(ctx->error, ENOMEM,
3072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3073 "cannot create action");
3076 return &cache->entry;
3080 * Find existing table port ID resource or create and register a new one.
3082 * @param[in, out] dev
3083 * Pointer to rte_eth_dev structure.
3084 * @param[in, out] resource
3085 * Pointer to port ID action resource.
3086 * @parm[in, out] dev_flow
3087 * Pointer to the dev_flow.
3089 * pointer to error structure.
3092 * 0 on success otherwise -errno and errno is set.
3095 flow_dv_port_id_action_resource_register
3096 (struct rte_eth_dev *dev,
3097 struct mlx5_flow_dv_port_id_action_resource *resource,
3098 struct mlx5_flow *dev_flow,
3099 struct rte_flow_error *error)
3101 struct mlx5_priv *priv = dev->data->dev_private;
3102 struct mlx5_cache_entry *entry;
3103 struct mlx5_flow_dv_port_id_action_resource *cache;
3104 struct mlx5_flow_cb_ctx ctx = {
3109 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3112 cache = container_of(entry, typeof(*cache), entry);
3113 dev_flow->dv.port_id_action = cache;
3114 dev_flow->handle->rix_port_id_action = cache->idx;
3119 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3120 struct mlx5_cache_entry *entry, void *cb_ctx)
3122 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3123 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3124 struct mlx5_flow_dv_push_vlan_action_resource *res =
3125 container_of(entry, typeof(*res), entry);
3127 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3130 struct mlx5_cache_entry *
3131 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3132 struct mlx5_cache_entry *entry __rte_unused,
3135 struct mlx5_dev_ctx_shared *sh = list->ctx;
3136 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3137 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3138 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3139 struct mlx5dv_dr_domain *domain;
3143 /* Register new port id action resource. */
3144 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3146 rte_flow_error_set(ctx->error, ENOMEM,
3147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3148 "cannot allocate push_vlan action cache memory");
3152 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3153 domain = sh->fdb_domain;
3154 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3155 domain = sh->rx_domain;
3157 domain = sh->tx_domain;
3158 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3161 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3162 rte_flow_error_set(ctx->error, ENOMEM,
3163 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3164 "cannot create push vlan action");
3167 return &cache->entry;
3171 * Find existing push vlan resource or create and register a new one.
3173 * @param [in, out] dev
3174 * Pointer to rte_eth_dev structure.
3175 * @param[in, out] resource
3176 * Pointer to port ID action resource.
3177 * @parm[in, out] dev_flow
3178 * Pointer to the dev_flow.
3180 * pointer to error structure.
3183 * 0 on success otherwise -errno and errno is set.
3186 flow_dv_push_vlan_action_resource_register
3187 (struct rte_eth_dev *dev,
3188 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3189 struct mlx5_flow *dev_flow,
3190 struct rte_flow_error *error)
3192 struct mlx5_priv *priv = dev->data->dev_private;
3193 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3194 struct mlx5_cache_entry *entry;
3195 struct mlx5_flow_cb_ctx ctx = {
3200 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3203 cache = container_of(entry, typeof(*cache), entry);
3205 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3206 dev_flow->dv.push_vlan_res = cache;
3211 * Get the size of specific rte_flow_item_type hdr size
3213 * @param[in] item_type
3214 * Tested rte_flow_item_type.
3217 * sizeof struct item_type, 0 if void or irrelevant.
3220 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3224 switch (item_type) {
3225 case RTE_FLOW_ITEM_TYPE_ETH:
3226 retval = sizeof(struct rte_ether_hdr);
3228 case RTE_FLOW_ITEM_TYPE_VLAN:
3229 retval = sizeof(struct rte_vlan_hdr);
3231 case RTE_FLOW_ITEM_TYPE_IPV4:
3232 retval = sizeof(struct rte_ipv4_hdr);
3234 case RTE_FLOW_ITEM_TYPE_IPV6:
3235 retval = sizeof(struct rte_ipv6_hdr);
3237 case RTE_FLOW_ITEM_TYPE_UDP:
3238 retval = sizeof(struct rte_udp_hdr);
3240 case RTE_FLOW_ITEM_TYPE_TCP:
3241 retval = sizeof(struct rte_tcp_hdr);
3243 case RTE_FLOW_ITEM_TYPE_VXLAN:
3244 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3245 retval = sizeof(struct rte_vxlan_hdr);
3247 case RTE_FLOW_ITEM_TYPE_GRE:
3248 case RTE_FLOW_ITEM_TYPE_NVGRE:
3249 retval = sizeof(struct rte_gre_hdr);
3251 case RTE_FLOW_ITEM_TYPE_MPLS:
3252 retval = sizeof(struct rte_mpls_hdr);
3254 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3262 #define MLX5_ENCAP_IPV4_VERSION 0x40
3263 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3264 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3265 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3266 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3267 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3268 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3271 * Convert the encap action data from list of rte_flow_item to raw buffer
3274 * Pointer to rte_flow_item objects list.
3276 * Pointer to the output buffer.
3278 * Pointer to the output buffer size.
3280 * Pointer to the error structure.
3283 * 0 on success, a negative errno value otherwise and rte_errno is set.
3286 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3287 size_t *size, struct rte_flow_error *error)
3289 struct rte_ether_hdr *eth = NULL;
3290 struct rte_vlan_hdr *vlan = NULL;
3291 struct rte_ipv4_hdr *ipv4 = NULL;
3292 struct rte_ipv6_hdr *ipv6 = NULL;
3293 struct rte_udp_hdr *udp = NULL;
3294 struct rte_vxlan_hdr *vxlan = NULL;
3295 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3296 struct rte_gre_hdr *gre = NULL;
3298 size_t temp_size = 0;
3301 return rte_flow_error_set(error, EINVAL,
3302 RTE_FLOW_ERROR_TYPE_ACTION,
3303 NULL, "invalid empty data");
3304 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3305 len = flow_dv_get_item_hdr_len(items->type);
3306 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3307 return rte_flow_error_set(error, EINVAL,
3308 RTE_FLOW_ERROR_TYPE_ACTION,
3309 (void *)items->type,
3310 "items total size is too big"
3311 " for encap action");
3312 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3313 switch (items->type) {
3314 case RTE_FLOW_ITEM_TYPE_ETH:
3315 eth = (struct rte_ether_hdr *)&buf[temp_size];
3317 case RTE_FLOW_ITEM_TYPE_VLAN:
3318 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3320 return rte_flow_error_set(error, EINVAL,
3321 RTE_FLOW_ERROR_TYPE_ACTION,
3322 (void *)items->type,
3323 "eth header not found");
3324 if (!eth->ether_type)
3325 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3327 case RTE_FLOW_ITEM_TYPE_IPV4:
3328 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3330 return rte_flow_error_set(error, EINVAL,
3331 RTE_FLOW_ERROR_TYPE_ACTION,
3332 (void *)items->type,
3333 "neither eth nor vlan"
3335 if (vlan && !vlan->eth_proto)
3336 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3337 else if (eth && !eth->ether_type)
3338 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3339 if (!ipv4->version_ihl)
3340 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3341 MLX5_ENCAP_IPV4_IHL_MIN;
3342 if (!ipv4->time_to_live)
3343 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3345 case RTE_FLOW_ITEM_TYPE_IPV6:
3346 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3348 return rte_flow_error_set(error, EINVAL,
3349 RTE_FLOW_ERROR_TYPE_ACTION,
3350 (void *)items->type,
3351 "neither eth nor vlan"
3353 if (vlan && !vlan->eth_proto)
3354 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3355 else if (eth && !eth->ether_type)
3356 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3357 if (!ipv6->vtc_flow)
3359 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3360 if (!ipv6->hop_limits)
3361 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3363 case RTE_FLOW_ITEM_TYPE_UDP:
3364 udp = (struct rte_udp_hdr *)&buf[temp_size];
3366 return rte_flow_error_set(error, EINVAL,
3367 RTE_FLOW_ERROR_TYPE_ACTION,
3368 (void *)items->type,
3369 "ip header not found");
3370 if (ipv4 && !ipv4->next_proto_id)
3371 ipv4->next_proto_id = IPPROTO_UDP;
3372 else if (ipv6 && !ipv6->proto)
3373 ipv6->proto = IPPROTO_UDP;
3375 case RTE_FLOW_ITEM_TYPE_VXLAN:
3376 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3378 return rte_flow_error_set(error, EINVAL,
3379 RTE_FLOW_ERROR_TYPE_ACTION,
3380 (void *)items->type,
3381 "udp header not found");
3383 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3384 if (!vxlan->vx_flags)
3386 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3388 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3389 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3391 return rte_flow_error_set(error, EINVAL,
3392 RTE_FLOW_ERROR_TYPE_ACTION,
3393 (void *)items->type,
3394 "udp header not found");
3395 if (!vxlan_gpe->proto)
3396 return rte_flow_error_set(error, EINVAL,
3397 RTE_FLOW_ERROR_TYPE_ACTION,
3398 (void *)items->type,
3399 "next protocol not found");
3402 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3403 if (!vxlan_gpe->vx_flags)
3404 vxlan_gpe->vx_flags =
3405 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3407 case RTE_FLOW_ITEM_TYPE_GRE:
3408 case RTE_FLOW_ITEM_TYPE_NVGRE:
3409 gre = (struct rte_gre_hdr *)&buf[temp_size];
3411 return rte_flow_error_set(error, EINVAL,
3412 RTE_FLOW_ERROR_TYPE_ACTION,
3413 (void *)items->type,
3414 "next protocol not found");
3416 return rte_flow_error_set(error, EINVAL,
3417 RTE_FLOW_ERROR_TYPE_ACTION,
3418 (void *)items->type,
3419 "ip header not found");
3420 if (ipv4 && !ipv4->next_proto_id)
3421 ipv4->next_proto_id = IPPROTO_GRE;
3422 else if (ipv6 && !ipv6->proto)
3423 ipv6->proto = IPPROTO_GRE;
3425 case RTE_FLOW_ITEM_TYPE_VOID:
3428 return rte_flow_error_set(error, EINVAL,
3429 RTE_FLOW_ERROR_TYPE_ACTION,
3430 (void *)items->type,
3431 "unsupported item type");
3441 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3443 struct rte_ether_hdr *eth = NULL;
3444 struct rte_vlan_hdr *vlan = NULL;
3445 struct rte_ipv6_hdr *ipv6 = NULL;
3446 struct rte_udp_hdr *udp = NULL;
3450 eth = (struct rte_ether_hdr *)data;
3451 next_hdr = (char *)(eth + 1);
3452 proto = RTE_BE16(eth->ether_type);
3455 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3456 vlan = (struct rte_vlan_hdr *)next_hdr;
3457 proto = RTE_BE16(vlan->eth_proto);
3458 next_hdr += sizeof(struct rte_vlan_hdr);
3461 /* HW calculates IPv4 csum. no need to proceed */
3462 if (proto == RTE_ETHER_TYPE_IPV4)
3465 /* non IPv4/IPv6 header. not supported */
3466 if (proto != RTE_ETHER_TYPE_IPV6) {
3467 return rte_flow_error_set(error, ENOTSUP,
3468 RTE_FLOW_ERROR_TYPE_ACTION,
3469 NULL, "Cannot offload non IPv4/IPv6");
3472 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3474 /* ignore non UDP */
3475 if (ipv6->proto != IPPROTO_UDP)
3478 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3479 udp->dgram_cksum = 0;
3485 * Convert L2 encap action to DV specification.
3488 * Pointer to rte_eth_dev structure.
3490 * Pointer to action structure.
3491 * @param[in, out] dev_flow
3492 * Pointer to the mlx5_flow.
3493 * @param[in] transfer
3494 * Mark if the flow is E-Switch flow.
3496 * Pointer to the error structure.
3499 * 0 on success, a negative errno value otherwise and rte_errno is set.
3502 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3503 const struct rte_flow_action *action,
3504 struct mlx5_flow *dev_flow,
3506 struct rte_flow_error *error)
3508 const struct rte_flow_item *encap_data;
3509 const struct rte_flow_action_raw_encap *raw_encap_data;
3510 struct mlx5_flow_dv_encap_decap_resource res = {
3512 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3513 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3514 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3517 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3519 (const struct rte_flow_action_raw_encap *)action->conf;
3520 res.size = raw_encap_data->size;
3521 memcpy(res.buf, raw_encap_data->data, res.size);
3523 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3525 ((const struct rte_flow_action_vxlan_encap *)
3526 action->conf)->definition;
3529 ((const struct rte_flow_action_nvgre_encap *)
3530 action->conf)->definition;
3531 if (flow_dv_convert_encap_data(encap_data, res.buf,
3535 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3537 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3538 return rte_flow_error_set(error, EINVAL,
3539 RTE_FLOW_ERROR_TYPE_ACTION,
3540 NULL, "can't create L2 encap action");
3545 * Convert L2 decap action to DV specification.
3548 * Pointer to rte_eth_dev structure.
3549 * @param[in, out] dev_flow
3550 * Pointer to the mlx5_flow.
3551 * @param[in] transfer
3552 * Mark if the flow is E-Switch flow.
3554 * Pointer to the error structure.
3557 * 0 on success, a negative errno value otherwise and rte_errno is set.
3560 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3561 struct mlx5_flow *dev_flow,
3563 struct rte_flow_error *error)
3565 struct mlx5_flow_dv_encap_decap_resource res = {
3568 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3569 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3570 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3573 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3574 return rte_flow_error_set(error, EINVAL,
3575 RTE_FLOW_ERROR_TYPE_ACTION,
3576 NULL, "can't create L2 decap action");
3581 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3584 * Pointer to rte_eth_dev structure.
3586 * Pointer to action structure.
3587 * @param[in, out] dev_flow
3588 * Pointer to the mlx5_flow.
3590 * Pointer to the flow attributes.
3592 * Pointer to the error structure.
3595 * 0 on success, a negative errno value otherwise and rte_errno is set.
3598 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3599 const struct rte_flow_action *action,
3600 struct mlx5_flow *dev_flow,
3601 const struct rte_flow_attr *attr,
3602 struct rte_flow_error *error)
3604 const struct rte_flow_action_raw_encap *encap_data;
3605 struct mlx5_flow_dv_encap_decap_resource res;
3607 memset(&res, 0, sizeof(res));
3608 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3609 res.size = encap_data->size;
3610 memcpy(res.buf, encap_data->data, res.size);
3611 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3612 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3613 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3615 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3617 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3618 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3619 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3620 return rte_flow_error_set(error, EINVAL,
3621 RTE_FLOW_ERROR_TYPE_ACTION,
3622 NULL, "can't create encap action");
3627 * Create action push VLAN.
3630 * Pointer to rte_eth_dev structure.
3632 * Pointer to the flow attributes.
3634 * Pointer to the vlan to push to the Ethernet header.
3635 * @param[in, out] dev_flow
3636 * Pointer to the mlx5_flow.
3638 * Pointer to the error structure.
3641 * 0 on success, a negative errno value otherwise and rte_errno is set.
3644 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3645 const struct rte_flow_attr *attr,
3646 const struct rte_vlan_hdr *vlan,
3647 struct mlx5_flow *dev_flow,
3648 struct rte_flow_error *error)
3650 struct mlx5_flow_dv_push_vlan_action_resource res;
3652 memset(&res, 0, sizeof(res));
3654 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3657 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3659 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3660 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3661 return flow_dv_push_vlan_action_resource_register
3662 (dev, &res, dev_flow, error);
3665 static int fdb_mirror;
3668 * Validate the modify-header actions.
3670 * @param[in] action_flags
3671 * Holds the actions detected until now.
3673 * Pointer to the modify action.
3675 * Pointer to error structure.
3678 * 0 on success, a negative errno value otherwise and rte_errno is set.
3681 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3682 const struct rte_flow_action *action,
3683 struct rte_flow_error *error)
3685 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3686 return rte_flow_error_set(error, EINVAL,
3687 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3688 NULL, "action configuration not set");
3689 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3690 return rte_flow_error_set(error, EINVAL,
3691 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3692 "can't have encap action before"
3694 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3695 return rte_flow_error_set(error, EINVAL,
3696 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697 "can't support sample action before"
3698 " modify action for E-Switch"
3704 * Validate the modify-header MAC address actions.
3706 * @param[in] action_flags
3707 * Holds the actions detected until now.
3709 * Pointer to the modify action.
3710 * @param[in] item_flags
3711 * Holds the items detected.
3713 * Pointer to error structure.
3716 * 0 on success, a negative errno value otherwise and rte_errno is set.
3719 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3720 const struct rte_flow_action *action,
3721 const uint64_t item_flags,
3722 struct rte_flow_error *error)
3726 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3728 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3729 return rte_flow_error_set(error, EINVAL,
3730 RTE_FLOW_ERROR_TYPE_ACTION,
3732 "no L2 item in pattern");
3738 * Validate the modify-header IPv4 address actions.
3740 * @param[in] action_flags
3741 * Holds the actions detected until now.
3743 * Pointer to the modify action.
3744 * @param[in] item_flags
3745 * Holds the items detected.
3747 * Pointer to error structure.
3750 * 0 on success, a negative errno value otherwise and rte_errno is set.
3753 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3754 const struct rte_flow_action *action,
3755 const uint64_t item_flags,
3756 struct rte_flow_error *error)
3761 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3763 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3764 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3765 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3766 if (!(item_flags & layer))
3767 return rte_flow_error_set(error, EINVAL,
3768 RTE_FLOW_ERROR_TYPE_ACTION,
3770 "no ipv4 item in pattern");
3776 * Validate the modify-header IPv6 address actions.
3778 * @param[in] action_flags
3779 * Holds the actions detected until now.
3781 * Pointer to the modify action.
3782 * @param[in] item_flags
3783 * Holds the items detected.
3785 * Pointer to error structure.
3788 * 0 on success, a negative errno value otherwise and rte_errno is set.
3791 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3792 const struct rte_flow_action *action,
3793 const uint64_t item_flags,
3794 struct rte_flow_error *error)
3799 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3801 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3802 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3803 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3804 if (!(item_flags & layer))
3805 return rte_flow_error_set(error, EINVAL,
3806 RTE_FLOW_ERROR_TYPE_ACTION,
3808 "no ipv6 item in pattern");
3814 * Validate the modify-header TP actions.
3816 * @param[in] action_flags
3817 * Holds the actions detected until now.
3819 * Pointer to the modify action.
3820 * @param[in] item_flags
3821 * Holds the items detected.
3823 * Pointer to error structure.
3826 * 0 on success, a negative errno value otherwise and rte_errno is set.
3829 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3830 const struct rte_flow_action *action,
3831 const uint64_t item_flags,
3832 struct rte_flow_error *error)
3837 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3839 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3840 MLX5_FLOW_LAYER_INNER_L4 :
3841 MLX5_FLOW_LAYER_OUTER_L4;
3842 if (!(item_flags & layer))
3843 return rte_flow_error_set(error, EINVAL,
3844 RTE_FLOW_ERROR_TYPE_ACTION,
3845 NULL, "no transport layer "
3852 * Validate the modify-header actions of increment/decrement
3853 * TCP Sequence-number.
3855 * @param[in] action_flags
3856 * Holds the actions detected until now.
3858 * Pointer to the modify action.
3859 * @param[in] item_flags
3860 * Holds the items detected.
3862 * Pointer to error structure.
3865 * 0 on success, a negative errno value otherwise and rte_errno is set.
3868 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3869 const struct rte_flow_action *action,
3870 const uint64_t item_flags,
3871 struct rte_flow_error *error)
3876 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3878 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3879 MLX5_FLOW_LAYER_INNER_L4_TCP :
3880 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3881 if (!(item_flags & layer))
3882 return rte_flow_error_set(error, EINVAL,
3883 RTE_FLOW_ERROR_TYPE_ACTION,
3884 NULL, "no TCP item in"
3886 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3887 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3888 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3889 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3890 return rte_flow_error_set(error, EINVAL,
3891 RTE_FLOW_ERROR_TYPE_ACTION,
3893 "cannot decrease and increase"
3894 " TCP sequence number"
3895 " at the same time");
3901 * Validate the modify-header actions of increment/decrement
3902 * TCP Acknowledgment number.
3904 * @param[in] action_flags
3905 * Holds the actions detected until now.
3907 * Pointer to the modify action.
3908 * @param[in] item_flags
3909 * Holds the items detected.
3911 * Pointer to error structure.
3914 * 0 on success, a negative errno value otherwise and rte_errno is set.
3917 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3918 const struct rte_flow_action *action,
3919 const uint64_t item_flags,
3920 struct rte_flow_error *error)
3925 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3927 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3928 MLX5_FLOW_LAYER_INNER_L4_TCP :
3929 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3930 if (!(item_flags & layer))
3931 return rte_flow_error_set(error, EINVAL,
3932 RTE_FLOW_ERROR_TYPE_ACTION,
3933 NULL, "no TCP item in"
3935 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3936 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3937 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3938 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3939 return rte_flow_error_set(error, EINVAL,
3940 RTE_FLOW_ERROR_TYPE_ACTION,
3942 "cannot decrease and increase"
3943 " TCP acknowledgment number"
3944 " at the same time");
3950 * Validate the modify-header TTL actions.
3952 * @param[in] action_flags
3953 * Holds the actions detected until now.
3955 * Pointer to the modify action.
3956 * @param[in] item_flags
3957 * Holds the items detected.
3959 * Pointer to error structure.
3962 * 0 on success, a negative errno value otherwise and rte_errno is set.
3965 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3966 const struct rte_flow_action *action,
3967 const uint64_t item_flags,
3968 struct rte_flow_error *error)
3973 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3975 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3976 MLX5_FLOW_LAYER_INNER_L3 :
3977 MLX5_FLOW_LAYER_OUTER_L3;
3978 if (!(item_flags & layer))
3979 return rte_flow_error_set(error, EINVAL,
3980 RTE_FLOW_ERROR_TYPE_ACTION,
3982 "no IP protocol in pattern");
3988 * Validate jump action.
3991 * Pointer to the jump action.
3992 * @param[in] action_flags
3993 * Holds the actions detected until now.
3994 * @param[in] attributes
3995 * Pointer to flow attributes
3996 * @param[in] external
3997 * Action belongs to flow rule created by request external to PMD.
3999 * Pointer to error structure.
4002 * 0 on success, a negative errno value otherwise and rte_errno is set.
4005 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4006 const struct mlx5_flow_tunnel *tunnel,
4007 const struct rte_flow_action *action,
4008 uint64_t action_flags,
4009 const struct rte_flow_attr *attributes,
4010 bool external, struct rte_flow_error *error)
4012 uint32_t target_group, table;
4014 struct flow_grp_info grp_info = {
4015 .external = !!external,
4016 .transfer = !!attributes->transfer,
4020 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4021 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4022 return rte_flow_error_set(error, EINVAL,
4023 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4024 "can't have 2 fate actions in"
4026 if (action_flags & MLX5_FLOW_ACTION_METER)
4027 return rte_flow_error_set(error, ENOTSUP,
4028 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4029 "jump with meter not support");
4030 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
4031 return rte_flow_error_set(error, EINVAL,
4032 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4033 "E-Switch mirroring can't support"
4034 " Sample action and jump action in"
4037 return rte_flow_error_set(error, EINVAL,
4038 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4039 NULL, "action configuration not set");
4041 ((const struct rte_flow_action_jump *)action->conf)->group;
4042 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4046 if (attributes->group == target_group &&
4047 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4048 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4049 return rte_flow_error_set(error, EINVAL,
4050 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4051 "target group must be other than"
4052 " the current flow group");
4057 * Validate the port_id action.
4060 * Pointer to rte_eth_dev structure.
4061 * @param[in] action_flags
4062 * Bit-fields that holds the actions detected until now.
4064 * Port_id RTE action structure.
4066 * Attributes of flow that includes this action.
4068 * Pointer to error structure.
4071 * 0 on success, a negative errno value otherwise and rte_errno is set.
4074 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4075 uint64_t action_flags,
4076 const struct rte_flow_action *action,
4077 const struct rte_flow_attr *attr,
4078 struct rte_flow_error *error)
4080 const struct rte_flow_action_port_id *port_id;
4081 struct mlx5_priv *act_priv;
4082 struct mlx5_priv *dev_priv;
4085 if (!attr->transfer)
4086 return rte_flow_error_set(error, ENOTSUP,
4087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4089 "port id action is valid in transfer"
4091 if (!action || !action->conf)
4092 return rte_flow_error_set(error, ENOTSUP,
4093 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4095 "port id action parameters must be"
4097 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4098 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4099 return rte_flow_error_set(error, EINVAL,
4100 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4101 "can have only one fate actions in"
4103 dev_priv = mlx5_dev_to_eswitch_info(dev);
4105 return rte_flow_error_set(error, rte_errno,
4106 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4108 "failed to obtain E-Switch info");
4109 port_id = action->conf;
4110 port = port_id->original ? dev->data->port_id : port_id->id;
4111 act_priv = mlx5_port_to_eswitch_info(port, false);
4113 return rte_flow_error_set
4115 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4116 "failed to obtain E-Switch port id for port");
4117 if (act_priv->domain_id != dev_priv->domain_id)
4118 return rte_flow_error_set
4120 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4121 "port does not belong to"
4122 " E-Switch being configured");
4127 * Get the maximum number of modify header actions.
4130 * Pointer to rte_eth_dev structure.
4132 * Flags bits to check if root level.
4135 * Max number of modify header actions device can support.
4137 static inline unsigned int
4138 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4142 * There's no way to directly query the max capacity from FW.
4143 * The maximal value on root table should be assumed to be supported.
4145 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4146 return MLX5_MAX_MODIFY_NUM;
4148 return MLX5_ROOT_TBL_MODIFY_NUM;
4152 * Validate the meter action.
4155 * Pointer to rte_eth_dev structure.
4156 * @param[in] action_flags
4157 * Bit-fields that holds the actions detected until now.
4159 * Pointer to the meter action.
4161 * Attributes of flow that includes this action.
4163 * Pointer to error structure.
4166 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4169 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4170 uint64_t action_flags,
4171 const struct rte_flow_action *action,
4172 const struct rte_flow_attr *attr,
4173 struct rte_flow_error *error)
4175 struct mlx5_priv *priv = dev->data->dev_private;
4176 const struct rte_flow_action_meter *am = action->conf;
4177 struct mlx5_flow_meter *fm;
4180 return rte_flow_error_set(error, EINVAL,
4181 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182 "meter action conf is NULL");
4184 if (action_flags & MLX5_FLOW_ACTION_METER)
4185 return rte_flow_error_set(error, ENOTSUP,
4186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4187 "meter chaining not support");
4188 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4189 return rte_flow_error_set(error, ENOTSUP,
4190 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4191 "meter with jump not support");
4193 return rte_flow_error_set(error, ENOTSUP,
4194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4196 "meter action not supported");
4197 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4199 return rte_flow_error_set(error, EINVAL,
4200 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4202 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4203 (!fm->ingress && !attr->ingress && attr->egress) ||
4204 (!fm->egress && !attr->egress && attr->ingress))))
4205 return rte_flow_error_set(error, EINVAL,
4206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4207 "Flow attributes are either invalid "
4208 "or have a conflict with current "
4209 "meter attributes");
4214 * Validate the age action.
4216 * @param[in] action_flags
4217 * Holds the actions detected until now.
4219 * Pointer to the age action.
4221 * Pointer to the Ethernet device structure.
4223 * Pointer to error structure.
4226 * 0 on success, a negative errno value otherwise and rte_errno is set.
4229 flow_dv_validate_action_age(uint64_t action_flags,
4230 const struct rte_flow_action *action,
4231 struct rte_eth_dev *dev,
4232 struct rte_flow_error *error)
4234 struct mlx5_priv *priv = dev->data->dev_private;
4235 const struct rte_flow_action_age *age = action->conf;
4237 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4238 !priv->sh->aso_age_mng))
4239 return rte_flow_error_set(error, ENOTSUP,
4240 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4242 "age action not supported");
4243 if (!(action->conf))
4244 return rte_flow_error_set(error, EINVAL,
4245 RTE_FLOW_ERROR_TYPE_ACTION, action,
4246 "configuration cannot be null");
4247 if (!(age->timeout))
4248 return rte_flow_error_set(error, EINVAL,
4249 RTE_FLOW_ERROR_TYPE_ACTION, action,
4250 "invalid timeout value 0");
4251 if (action_flags & MLX5_FLOW_ACTION_AGE)
4252 return rte_flow_error_set(error, EINVAL,
4253 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4254 "duplicate age actions set");
4259 * Validate the modify-header IPv4 DSCP actions.
4261 * @param[in] action_flags
4262 * Holds the actions detected until now.
4264 * Pointer to the modify action.
4265 * @param[in] item_flags
4266 * Holds the items detected.
4268 * Pointer to error structure.
4271 * 0 on success, a negative errno value otherwise and rte_errno is set.
4274 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4275 const struct rte_flow_action *action,
4276 const uint64_t item_flags,
4277 struct rte_flow_error *error)
4281 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4283 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4284 return rte_flow_error_set(error, EINVAL,
4285 RTE_FLOW_ERROR_TYPE_ACTION,
4287 "no ipv4 item in pattern");
4293 * Validate the modify-header IPv6 DSCP actions.
4295 * @param[in] action_flags
4296 * Holds the actions detected until now.
4298 * Pointer to the modify action.
4299 * @param[in] item_flags
4300 * Holds the items detected.
4302 * Pointer to error structure.
4305 * 0 on success, a negative errno value otherwise and rte_errno is set.
4308 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4309 const struct rte_flow_action *action,
4310 const uint64_t item_flags,
4311 struct rte_flow_error *error)
4315 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4317 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4318 return rte_flow_error_set(error, EINVAL,
4319 RTE_FLOW_ERROR_TYPE_ACTION,
4321 "no ipv6 item in pattern");
4327 * Match modify-header resource.
4330 * Pointer to the hash list.
4332 * Pointer to exist resource entry object.
4334 * Key of the new entry.
4336 * Pointer to new modify-header resource.
4339 * 0 on matching, non-zero otherwise.
4342 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4343 struct mlx5_hlist_entry *entry,
4344 uint64_t key __rte_unused, void *cb_ctx)
4346 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4347 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4348 struct mlx5_flow_dv_modify_hdr_resource *resource =
4349 container_of(entry, typeof(*resource), entry);
4350 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4352 key_len += ref->actions_num * sizeof(ref->actions[0]);
4353 return ref->actions_num != resource->actions_num ||
4354 memcmp(&ref->ft_type, &resource->ft_type, key_len);
4357 struct mlx5_hlist_entry *
4358 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4361 struct mlx5_dev_ctx_shared *sh = list->ctx;
4362 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4363 struct mlx5dv_dr_domain *ns;
4364 struct mlx5_flow_dv_modify_hdr_resource *entry;
4365 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4367 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4368 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4370 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4373 rte_flow_error_set(ctx->error, ENOMEM,
4374 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4375 "cannot allocate resource memory");
4378 rte_memcpy(&entry->ft_type,
4379 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4380 key_len + data_len);
4381 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4382 ns = sh->fdb_domain;
4383 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4387 ret = mlx5_flow_os_create_flow_action_modify_header
4388 (sh->ctx, ns, entry,
4389 data_len, &entry->action);
4392 rte_flow_error_set(ctx->error, ENOMEM,
4393 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4394 NULL, "cannot create modification action");
4397 return &entry->entry;
4401 * Validate the sample action.
4403 * @param[in] action_flags
4404 * Holds the actions detected until now.
4406 * Pointer to the sample action.
4408 * Pointer to the Ethernet device structure.
4410 * Attributes of flow that includes this action.
4411 * @param[in] item_flags
4412 * Holds the items detected.
4414 * Pointer to error structure.
4417 * 0 on success, a negative errno value otherwise and rte_errno is set.
4420 flow_dv_validate_action_sample(uint64_t action_flags,
4421 const struct rte_flow_action *action,
4422 struct rte_eth_dev *dev,
4423 const struct rte_flow_attr *attr,
4424 const uint64_t item_flags,
4425 struct rte_flow_error *error)
4427 struct mlx5_priv *priv = dev->data->dev_private;
4428 struct mlx5_dev_config *dev_conf = &priv->config;
4429 const struct rte_flow_action_sample *sample = action->conf;
4430 const struct rte_flow_action *act;
4431 uint64_t sub_action_flags = 0;
4432 uint16_t queue_index = 0xFFFF;
4438 return rte_flow_error_set(error, EINVAL,
4439 RTE_FLOW_ERROR_TYPE_ACTION, action,
4440 "configuration cannot be NULL");
4441 if (sample->ratio == 0)
4442 return rte_flow_error_set(error, EINVAL,
4443 RTE_FLOW_ERROR_TYPE_ACTION, action,
4444 "ratio value starts from 1");
4445 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446 return rte_flow_error_set(error, ENOTSUP,
4447 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4449 "sample action not supported");
4450 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451 return rte_flow_error_set(error, EINVAL,
4452 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453 "Multiple sample actions not "
4455 if (action_flags & MLX5_FLOW_ACTION_METER)
4456 return rte_flow_error_set(error, EINVAL,
4457 RTE_FLOW_ERROR_TYPE_ACTION, action,
4458 "wrong action order, meter should "
4459 "be after sample action");
4460 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461 return rte_flow_error_set(error, EINVAL,
4462 RTE_FLOW_ERROR_TYPE_ACTION, action,
4463 "wrong action order, jump should "
4464 "be after sample action");
4465 act = sample->actions;
4466 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468 return rte_flow_error_set(error, ENOTSUP,
4469 RTE_FLOW_ERROR_TYPE_ACTION,
4470 act, "too many actions");
4471 switch (act->type) {
4472 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473 ret = mlx5_flow_validate_action_queue(act,
4479 queue_index = ((const struct rte_flow_action_queue *)
4480 (act->conf))->index;
4481 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4484 case RTE_FLOW_ACTION_TYPE_MARK:
4485 ret = flow_dv_validate_action_mark(dev, act,
4490 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4491 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4492 MLX5_FLOW_ACTION_MARK_EXT;
4494 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4497 case RTE_FLOW_ACTION_TYPE_COUNT:
4498 ret = flow_dv_validate_action_count(dev, error);
4501 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4504 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4505 ret = flow_dv_validate_action_port_id(dev,
4512 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4515 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4516 ret = flow_dv_validate_action_raw_encap_decap
4517 (dev, NULL, act->conf, attr, &sub_action_flags,
4518 &actions_n, action, item_flags, error);
4524 return rte_flow_error_set(error, ENOTSUP,
4525 RTE_FLOW_ERROR_TYPE_ACTION,
4527 "Doesn't support optional "
4531 if (attr->ingress && !attr->transfer) {
4532 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4533 return rte_flow_error_set(error, EINVAL,
4534 RTE_FLOW_ERROR_TYPE_ACTION,
4536 "Ingress must has a dest "
4537 "QUEUE for Sample");
4538 } else if (attr->egress && !attr->transfer) {
4539 return rte_flow_error_set(error, ENOTSUP,
4540 RTE_FLOW_ERROR_TYPE_ACTION,
4542 "Sample Only support Ingress "
4544 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4545 MLX5_ASSERT(attr->transfer);
4546 if (sample->ratio > 1)
4547 return rte_flow_error_set(error, ENOTSUP,
4548 RTE_FLOW_ERROR_TYPE_ACTION,
4550 "E-Switch doesn't support "
4551 "any optional action "
4554 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4555 return rte_flow_error_set(error, ENOTSUP,
4556 RTE_FLOW_ERROR_TYPE_ACTION,
4558 "unsupported action QUEUE");
4559 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4560 return rte_flow_error_set(error, EINVAL,
4561 RTE_FLOW_ERROR_TYPE_ACTION,
4563 "E-Switch must has a dest "
4564 "port for mirroring");
4566 /* Continue validation for Xcap actions.*/
4567 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4568 (queue_index == 0xFFFF ||
4569 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4570 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4571 MLX5_FLOW_XCAP_ACTIONS)
4572 return rte_flow_error_set(error, ENOTSUP,
4573 RTE_FLOW_ERROR_TYPE_ACTION,
4574 NULL, "encap and decap "
4575 "combination aren't "
4577 if (!attr->transfer && attr->ingress && (sub_action_flags &
4578 MLX5_FLOW_ACTION_ENCAP))
4579 return rte_flow_error_set(error, ENOTSUP,
4580 RTE_FLOW_ERROR_TYPE_ACTION,
4581 NULL, "encap is not supported"
4582 " for ingress traffic");
4588 * Find existing modify-header resource or create and register a new one.
4590 * @param dev[in, out]
4591 * Pointer to rte_eth_dev structure.
4592 * @param[in, out] resource
4593 * Pointer to modify-header resource.
4594 * @parm[in, out] dev_flow
4595 * Pointer to the dev_flow.
4597 * pointer to error structure.
4600 * 0 on success otherwise -errno and errno is set.
4603 flow_dv_modify_hdr_resource_register
4604 (struct rte_eth_dev *dev,
4605 struct mlx5_flow_dv_modify_hdr_resource *resource,
4606 struct mlx5_flow *dev_flow,
4607 struct rte_flow_error *error)
4609 struct mlx5_priv *priv = dev->data->dev_private;
4610 struct mlx5_dev_ctx_shared *sh = priv->sh;
4611 uint32_t key_len = sizeof(*resource) -
4612 offsetof(typeof(*resource), ft_type) +
4613 resource->actions_num * sizeof(resource->actions[0]);
4614 struct mlx5_hlist_entry *entry;
4615 struct mlx5_flow_cb_ctx ctx = {
4621 resource->flags = dev_flow->dv.group ? 0 :
4622 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4623 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4625 return rte_flow_error_set(error, EOVERFLOW,
4626 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4627 "too many modify header items");
4628 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4629 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4632 resource = container_of(entry, typeof(*resource), entry);
4633 dev_flow->handle->dvh.modify_hdr = resource;
4638 * Get DV flow counter by index.
4641 * Pointer to the Ethernet device structure.
4643 * mlx5 flow counter index in the container.
4645 * mlx5 flow counter pool in the container,
4648 * Pointer to the counter, NULL otherwise.
4650 static struct mlx5_flow_counter *
4651 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4653 struct mlx5_flow_counter_pool **ppool)
4655 struct mlx5_priv *priv = dev->data->dev_private;
4656 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4657 struct mlx5_flow_counter_pool *pool;
4659 /* Decrease to original index and clear shared bit. */
4660 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4661 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4662 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4666 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4670 * Check the devx counter belongs to the pool.
4673 * Pointer to the counter pool.
4675 * The counter devx ID.
4678 * True if counter belongs to the pool, false otherwise.
4681 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4683 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4684 MLX5_COUNTERS_PER_POOL;
4686 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4692 * Get a pool by devx counter ID.
4695 * Pointer to the counter management.
4697 * The counter devx ID.
4700 * The counter pool pointer if exists, NULL otherwise,
4702 static struct mlx5_flow_counter_pool *
4703 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4706 struct mlx5_flow_counter_pool *pool = NULL;
4708 rte_spinlock_lock(&cmng->pool_update_sl);
4709 /* Check last used pool. */
4710 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4711 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4712 pool = cmng->pools[cmng->last_pool_idx];
4715 /* ID out of range means no suitable pool in the container. */
4716 if (id > cmng->max_id || id < cmng->min_id)
4719 * Find the pool from the end of the container, since mostly counter
4720 * ID is sequence increasing, and the last pool should be the needed
4725 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4727 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4733 rte_spinlock_unlock(&cmng->pool_update_sl);
4738 * Resize a counter container.
4741 * Pointer to the Ethernet device structure.
4744 * 0 on success, otherwise negative errno value and rte_errno is set.
4747 flow_dv_container_resize(struct rte_eth_dev *dev)
4749 struct mlx5_priv *priv = dev->data->dev_private;
4750 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4751 void *old_pools = cmng->pools;
4752 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4753 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4754 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4761 memcpy(pools, old_pools, cmng->n *
4762 sizeof(struct mlx5_flow_counter_pool *));
4764 cmng->pools = pools;
4766 mlx5_free(old_pools);
4771 * Query a devx flow counter.
4774 * Pointer to the Ethernet device structure.
4776 * Index to the flow counter.
4778 * The statistics value of packets.
4780 * The statistics value of bytes.
4783 * 0 on success, otherwise a negative errno value and rte_errno is set.
4786 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4789 struct mlx5_priv *priv = dev->data->dev_private;
4790 struct mlx5_flow_counter_pool *pool = NULL;
4791 struct mlx5_flow_counter *cnt;
4794 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4796 if (priv->sh->cmng.counter_fallback)
4797 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4798 0, pkts, bytes, 0, NULL, NULL, 0);
4799 rte_spinlock_lock(&pool->sl);
4804 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4805 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4806 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4808 rte_spinlock_unlock(&pool->sl);
4813 * Create and initialize a new counter pool.
4816 * Pointer to the Ethernet device structure.
4818 * The devX counter handle.
4820 * Whether the pool is for counter that was allocated for aging.
4821 * @param[in/out] cont_cur
4822 * Pointer to the container pointer, it will be update in pool resize.
4825 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4827 static struct mlx5_flow_counter_pool *
4828 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4831 struct mlx5_priv *priv = dev->data->dev_private;
4832 struct mlx5_flow_counter_pool *pool;
4833 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4834 bool fallback = priv->sh->cmng.counter_fallback;
4835 uint32_t size = sizeof(*pool);
4837 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4838 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4839 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4845 pool->is_aged = !!age;
4846 pool->query_gen = 0;
4847 pool->min_dcs = dcs;
4848 rte_spinlock_init(&pool->sl);
4849 rte_spinlock_init(&pool->csl);
4850 TAILQ_INIT(&pool->counters[0]);
4851 TAILQ_INIT(&pool->counters[1]);
4852 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4853 rte_spinlock_lock(&cmng->pool_update_sl);
4854 pool->index = cmng->n_valid;
4855 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4857 rte_spinlock_unlock(&cmng->pool_update_sl);
4860 cmng->pools[pool->index] = pool;
4862 if (unlikely(fallback)) {
4863 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4865 if (base < cmng->min_id)
4866 cmng->min_id = base;
4867 if (base > cmng->max_id)
4868 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4869 cmng->last_pool_idx = pool->index;
4871 rte_spinlock_unlock(&cmng->pool_update_sl);
4876 * Prepare a new counter and/or a new counter pool.
4879 * Pointer to the Ethernet device structure.
4880 * @param[out] cnt_free
4881 * Where to put the pointer of a new counter.
4883 * Whether the pool is for counter that was allocated for aging.
4886 * The counter pool pointer and @p cnt_free is set on success,
4887 * NULL otherwise and rte_errno is set.
4889 static struct mlx5_flow_counter_pool *
4890 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4891 struct mlx5_flow_counter **cnt_free,
4894 struct mlx5_priv *priv = dev->data->dev_private;
4895 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4896 struct mlx5_flow_counter_pool *pool;
4897 struct mlx5_counters tmp_tq;
4898 struct mlx5_devx_obj *dcs = NULL;
4899 struct mlx5_flow_counter *cnt;
4900 enum mlx5_counter_type cnt_type =
4901 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4902 bool fallback = priv->sh->cmng.counter_fallback;
4906 /* bulk_bitmap must be 0 for single counter allocation. */
4907 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4910 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4912 pool = flow_dv_pool_create(dev, dcs, age);
4914 mlx5_devx_cmd_destroy(dcs);
4918 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4919 cnt = MLX5_POOL_GET_CNT(pool, i);
4921 cnt->dcs_when_free = dcs;
4925 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4927 rte_errno = ENODATA;
4930 pool = flow_dv_pool_create(dev, dcs, age);
4932 mlx5_devx_cmd_destroy(dcs);
4935 TAILQ_INIT(&tmp_tq);
4936 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4937 cnt = MLX5_POOL_GET_CNT(pool, i);
4939 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4941 rte_spinlock_lock(&cmng->csl[cnt_type]);
4942 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4943 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4944 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4945 (*cnt_free)->pool = pool;
4950 * Allocate a flow counter.
4953 * Pointer to the Ethernet device structure.
4955 * Whether the counter was allocated for aging.
4958 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4961 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4963 struct mlx5_priv *priv = dev->data->dev_private;
4964 struct mlx5_flow_counter_pool *pool = NULL;
4965 struct mlx5_flow_counter *cnt_free = NULL;
4966 bool fallback = priv->sh->cmng.counter_fallback;
4967 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4968 enum mlx5_counter_type cnt_type =
4969 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4972 if (!priv->config.devx) {
4973 rte_errno = ENOTSUP;
4976 /* Get free counters from container. */
4977 rte_spinlock_lock(&cmng->csl[cnt_type]);
4978 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4980 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4981 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4982 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4984 pool = cnt_free->pool;
4986 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4987 /* Create a DV counter action only in the first time usage. */
4988 if (!cnt_free->action) {
4990 struct mlx5_devx_obj *dcs;
4994 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4995 dcs = pool->min_dcs;
4998 dcs = cnt_free->dcs_when_free;
5000 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5007 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5008 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5009 /* Update the counter reset values. */
5010 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5013 if (!fallback && !priv->sh->cmng.query_thread_on)
5014 /* Start the asynchronous batch query by the host thread. */
5015 mlx5_set_query_alarm(priv->sh);
5019 cnt_free->pool = pool;
5021 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5022 rte_spinlock_lock(&cmng->csl[cnt_type]);
5023 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5024 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5030 * Allocate a shared flow counter.
5033 * Pointer to the shared counter configuration.
5035 * Pointer to save the allocated counter index.
5038 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5042 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5044 struct mlx5_shared_counter_conf *conf = ctx;
5045 struct rte_eth_dev *dev = conf->dev;
5046 struct mlx5_flow_counter *cnt;
5048 data->dword = flow_dv_counter_alloc(dev, 0);
5049 data->dword |= MLX5_CNT_SHARED_OFFSET;
5050 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5051 cnt->shared_info.id = conf->id;
5056 * Get a shared flow counter.
5059 * Pointer to the Ethernet device structure.
5061 * Counter identifier.
5064 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5067 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5069 struct mlx5_priv *priv = dev->data->dev_private;
5070 struct mlx5_shared_counter_conf conf = {
5074 union mlx5_l3t_data data = {
5078 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5079 flow_dv_counter_alloc_shared_cb, &conf);
5084 * Get age param from counter index.
5087 * Pointer to the Ethernet device structure.
5088 * @param[in] counter
5089 * Index to the counter handler.
5092 * The aging parameter specified for the counter index.
5094 static struct mlx5_age_param*
5095 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5098 struct mlx5_flow_counter *cnt;
5099 struct mlx5_flow_counter_pool *pool = NULL;
5101 flow_dv_counter_get_by_idx(dev, counter, &pool);
5102 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5103 cnt = MLX5_POOL_GET_CNT(pool, counter);
5104 return MLX5_CNT_TO_AGE(cnt);
5108 * Remove a flow counter from aged counter list.
5111 * Pointer to the Ethernet device structure.
5112 * @param[in] counter
5113 * Index to the counter handler.
5115 * Pointer to the counter handler.
5118 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5119 uint32_t counter, struct mlx5_flow_counter *cnt)
5121 struct mlx5_age_info *age_info;
5122 struct mlx5_age_param *age_param;
5123 struct mlx5_priv *priv = dev->data->dev_private;
5124 uint16_t expected = AGE_CANDIDATE;
5126 age_info = GET_PORT_AGE_INFO(priv);
5127 age_param = flow_dv_counter_idx_get_age(dev, counter);
5128 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5129 AGE_FREE, false, __ATOMIC_RELAXED,
5130 __ATOMIC_RELAXED)) {
5132 * We need the lock even it is age timeout,
5133 * since counter may still in process.
5135 rte_spinlock_lock(&age_info->aged_sl);
5136 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5137 rte_spinlock_unlock(&age_info->aged_sl);
5138 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5143 * Release a flow counter.
5146 * Pointer to the Ethernet device structure.
5147 * @param[in] counter
5148 * Index to the counter handler.
5151 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5153 struct mlx5_priv *priv = dev->data->dev_private;
5154 struct mlx5_flow_counter_pool *pool = NULL;
5155 struct mlx5_flow_counter *cnt;
5156 enum mlx5_counter_type cnt_type;
5160 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5162 if (IS_SHARED_CNT(counter) &&
5163 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5166 flow_dv_counter_remove_from_age(dev, counter, cnt);
5169 * Put the counter back to list to be updated in none fallback mode.
5170 * Currently, we are using two list alternately, while one is in query,
5171 * add the freed counter to the other list based on the pool query_gen
5172 * value. After query finishes, add counter the list to the global
5173 * container counter list. The list changes while query starts. In
5174 * this case, lock will not be needed as query callback and release
5175 * function both operate with the different list.
5178 if (!priv->sh->cmng.counter_fallback) {
5179 rte_spinlock_lock(&pool->csl);
5180 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5181 rte_spinlock_unlock(&pool->csl);
5183 cnt->dcs_when_free = cnt->dcs_when_active;
5184 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5185 MLX5_COUNTER_TYPE_ORIGIN;
5186 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5187 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5189 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5194 * Verify the @p attributes will be correctly understood by the NIC and store
5195 * them in the @p flow if everything is correct.
5198 * Pointer to dev struct.
5199 * @param[in] attributes
5200 * Pointer to flow attributes
5201 * @param[in] external
5202 * This flow rule is created by request external to PMD.
5204 * Pointer to error structure.
5207 * - 0 on success and non root table.
5208 * - 1 on success and root table.
5209 * - a negative errno value otherwise and rte_errno is set.
5212 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5213 const struct mlx5_flow_tunnel *tunnel,
5214 const struct rte_flow_attr *attributes,
5215 const struct flow_grp_info *grp_info,
5216 struct rte_flow_error *error)
5218 struct mlx5_priv *priv = dev->data->dev_private;
5219 uint32_t priority_max = priv->config.flow_prio - 1;
5222 #ifndef HAVE_MLX5DV_DR
5223 RTE_SET_USED(tunnel);
5224 RTE_SET_USED(grp_info);
5225 if (attributes->group)
5226 return rte_flow_error_set(error, ENOTSUP,
5227 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5229 "groups are not supported");
5233 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5238 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5240 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5241 attributes->priority >= priority_max)
5242 return rte_flow_error_set(error, ENOTSUP,
5243 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5245 "priority out of range");
5246 if (attributes->transfer) {
5247 if (!priv->config.dv_esw_en)
5248 return rte_flow_error_set
5250 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5251 "E-Switch dr is not supported");
5252 if (!(priv->representor || priv->master))
5253 return rte_flow_error_set
5254 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5255 NULL, "E-Switch configuration can only be"
5256 " done by a master or a representor device");
5257 if (attributes->egress)
5258 return rte_flow_error_set
5260 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5261 "egress is not supported");
5263 if (!(attributes->egress ^ attributes->ingress))
5264 return rte_flow_error_set(error, ENOTSUP,
5265 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5266 "must specify exactly one of "
5267 "ingress or egress");
5272 * Internal validation function. For validating both actions and items.
5275 * Pointer to the rte_eth_dev structure.
5277 * Pointer to the flow attributes.
5279 * Pointer to the list of items.
5280 * @param[in] actions
5281 * Pointer to the list of actions.
5282 * @param[in] external
5283 * This flow rule is created by request external to PMD.
5284 * @param[in] hairpin
5285 * Number of hairpin TX actions, 0 means classic flow.
5287 * Pointer to the error structure.
5290 * 0 on success, a negative errno value otherwise and rte_errno is set.
5293 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5294 const struct rte_flow_item items[],
5295 const struct rte_flow_action actions[],
5296 bool external, int hairpin, struct rte_flow_error *error)
5299 uint64_t action_flags = 0;
5300 uint64_t item_flags = 0;
5301 uint64_t last_item = 0;
5302 uint8_t next_protocol = 0xff;
5303 uint16_t ether_type = 0;
5305 uint8_t item_ipv6_proto = 0;
5306 const struct rte_flow_item *geneve_item = NULL;
5307 const struct rte_flow_item *gre_item = NULL;
5308 const struct rte_flow_item *gtp_item = NULL;
5309 const struct rte_flow_action_raw_decap *decap;
5310 const struct rte_flow_action_raw_encap *encap;
5311 const struct rte_flow_action_rss *rss;
5312 const struct rte_flow_item_tcp nic_tcp_mask = {
5315 .src_port = RTE_BE16(UINT16_MAX),
5316 .dst_port = RTE_BE16(UINT16_MAX),
5319 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5322 "\xff\xff\xff\xff\xff\xff\xff\xff"
5323 "\xff\xff\xff\xff\xff\xff\xff\xff",
5325 "\xff\xff\xff\xff\xff\xff\xff\xff"
5326 "\xff\xff\xff\xff\xff\xff\xff\xff",
5327 .vtc_flow = RTE_BE32(0xffffffff),
5333 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5337 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5341 .dummy[0] = 0xffffffff,
5344 struct mlx5_priv *priv = dev->data->dev_private;
5345 struct mlx5_dev_config *dev_conf = &priv->config;
5346 uint16_t queue_index = 0xFFFF;
5347 const struct rte_flow_item_vlan *vlan_m = NULL;
5348 int16_t rw_act_num = 0;
5350 const struct mlx5_flow_tunnel *tunnel;
5351 struct flow_grp_info grp_info = {
5352 .external = !!external,
5353 .transfer = !!attr->transfer,
5354 .fdb_def_rule = !!priv->fdb_def_rule,
5356 const struct rte_eth_hairpin_conf *conf;
5360 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5361 tunnel = flow_items_to_tunnel(items);
5362 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5363 MLX5_FLOW_ACTION_DECAP;
5364 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5365 tunnel = flow_actions_to_tunnel(actions);
5366 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5370 if (tunnel && priv->representor)
5371 return rte_flow_error_set(error, ENOTSUP,
5372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5373 "decap not supported "
5374 "for VF representor");
5375 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5376 (dev, tunnel, attr, items, actions);
5377 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5380 is_root = (uint64_t)ret;
5381 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5382 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5383 int type = items->type;
5385 if (!mlx5_flow_os_item_supported(type))
5386 return rte_flow_error_set(error, ENOTSUP,
5387 RTE_FLOW_ERROR_TYPE_ITEM,
5388 NULL, "item not supported");
5390 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5391 if (items[0].type != (typeof(items[0].type))
5392 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5393 return rte_flow_error_set
5395 RTE_FLOW_ERROR_TYPE_ITEM,
5396 NULL, "MLX5 private items "
5397 "must be the first");
5399 case RTE_FLOW_ITEM_TYPE_VOID:
5401 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5402 ret = flow_dv_validate_item_port_id
5403 (dev, items, attr, item_flags, error);
5406 last_item = MLX5_FLOW_ITEM_PORT_ID;
5408 case RTE_FLOW_ITEM_TYPE_ETH:
5409 ret = mlx5_flow_validate_item_eth(items, item_flags,
5413 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5414 MLX5_FLOW_LAYER_OUTER_L2;
5415 if (items->mask != NULL && items->spec != NULL) {
5417 ((const struct rte_flow_item_eth *)
5420 ((const struct rte_flow_item_eth *)
5422 ether_type = rte_be_to_cpu_16(ether_type);
5427 case RTE_FLOW_ITEM_TYPE_VLAN:
5428 ret = flow_dv_validate_item_vlan(items, item_flags,
5432 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5433 MLX5_FLOW_LAYER_OUTER_VLAN;
5434 if (items->mask != NULL && items->spec != NULL) {
5436 ((const struct rte_flow_item_vlan *)
5437 items->spec)->inner_type;
5439 ((const struct rte_flow_item_vlan *)
5440 items->mask)->inner_type;
5441 ether_type = rte_be_to_cpu_16(ether_type);
5445 /* Store outer VLAN mask for of_push_vlan action. */
5447 vlan_m = items->mask;
5449 case RTE_FLOW_ITEM_TYPE_IPV4:
5450 mlx5_flow_tunnel_ip_check(items, next_protocol,
5451 &item_flags, &tunnel);
5452 ret = flow_dv_validate_item_ipv4(items, item_flags,
5453 last_item, ether_type,
5457 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5458 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5459 if (items->mask != NULL &&
5460 ((const struct rte_flow_item_ipv4 *)
5461 items->mask)->hdr.next_proto_id) {
5463 ((const struct rte_flow_item_ipv4 *)
5464 (items->spec))->hdr.next_proto_id;
5466 ((const struct rte_flow_item_ipv4 *)
5467 (items->mask))->hdr.next_proto_id;
5469 /* Reset for inner layer. */
5470 next_protocol = 0xff;
5473 case RTE_FLOW_ITEM_TYPE_IPV6:
5474 mlx5_flow_tunnel_ip_check(items, next_protocol,
5475 &item_flags, &tunnel);
5476 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5483 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5484 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5485 if (items->mask != NULL &&
5486 ((const struct rte_flow_item_ipv6 *)
5487 items->mask)->hdr.proto) {
5489 ((const struct rte_flow_item_ipv6 *)
5490 items->spec)->hdr.proto;
5492 ((const struct rte_flow_item_ipv6 *)
5493 items->spec)->hdr.proto;
5495 ((const struct rte_flow_item_ipv6 *)
5496 items->mask)->hdr.proto;
5498 /* Reset for inner layer. */
5499 next_protocol = 0xff;
5502 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5503 ret = flow_dv_validate_item_ipv6_frag_ext(items,
5508 last_item = tunnel ?
5509 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5510 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5511 if (items->mask != NULL &&
5512 ((const struct rte_flow_item_ipv6_frag_ext *)
5513 items->mask)->hdr.next_header) {
5515 ((const struct rte_flow_item_ipv6_frag_ext *)
5516 items->spec)->hdr.next_header;
5518 ((const struct rte_flow_item_ipv6_frag_ext *)
5519 items->mask)->hdr.next_header;
5521 /* Reset for inner layer. */
5522 next_protocol = 0xff;
5525 case RTE_FLOW_ITEM_TYPE_TCP:
5526 ret = mlx5_flow_validate_item_tcp
5533 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5534 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5536 case RTE_FLOW_ITEM_TYPE_UDP:
5537 ret = mlx5_flow_validate_item_udp(items, item_flags,
5542 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5543 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5545 case RTE_FLOW_ITEM_TYPE_GRE:
5546 ret = mlx5_flow_validate_item_gre(items, item_flags,
5547 next_protocol, error);
5551 last_item = MLX5_FLOW_LAYER_GRE;
5553 case RTE_FLOW_ITEM_TYPE_NVGRE:
5554 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5559 last_item = MLX5_FLOW_LAYER_NVGRE;
5561 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5562 ret = mlx5_flow_validate_item_gre_key
5563 (items, item_flags, gre_item, error);
5566 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5568 case RTE_FLOW_ITEM_TYPE_VXLAN:
5569 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5573 last_item = MLX5_FLOW_LAYER_VXLAN;
5575 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5576 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5581 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5583 case RTE_FLOW_ITEM_TYPE_GENEVE:
5584 ret = mlx5_flow_validate_item_geneve(items,
5589 geneve_item = items;
5590 last_item = MLX5_FLOW_LAYER_GENEVE;
5592 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5593 ret = mlx5_flow_validate_item_geneve_opt(items,
5600 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5602 case RTE_FLOW_ITEM_TYPE_MPLS:
5603 ret = mlx5_flow_validate_item_mpls(dev, items,
5608 last_item = MLX5_FLOW_LAYER_MPLS;
5611 case RTE_FLOW_ITEM_TYPE_MARK:
5612 ret = flow_dv_validate_item_mark(dev, items, attr,
5616 last_item = MLX5_FLOW_ITEM_MARK;
5618 case RTE_FLOW_ITEM_TYPE_META:
5619 ret = flow_dv_validate_item_meta(dev, items, attr,
5623 last_item = MLX5_FLOW_ITEM_METADATA;
5625 case RTE_FLOW_ITEM_TYPE_ICMP:
5626 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5631 last_item = MLX5_FLOW_LAYER_ICMP;
5633 case RTE_FLOW_ITEM_TYPE_ICMP6:
5634 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5639 item_ipv6_proto = IPPROTO_ICMPV6;
5640 last_item = MLX5_FLOW_LAYER_ICMP6;
5642 case RTE_FLOW_ITEM_TYPE_TAG:
5643 ret = flow_dv_validate_item_tag(dev, items,
5647 last_item = MLX5_FLOW_ITEM_TAG;
5649 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5650 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5652 case RTE_FLOW_ITEM_TYPE_GTP:
5653 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5658 last_item = MLX5_FLOW_LAYER_GTP;
5660 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5661 ret = flow_dv_validate_item_gtp_psc(items, last_item,
5666 last_item = MLX5_FLOW_LAYER_GTP_PSC;
5668 case RTE_FLOW_ITEM_TYPE_ECPRI:
5669 /* Capacity will be checked in the translate stage. */
5670 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5677 last_item = MLX5_FLOW_LAYER_ECPRI;
5680 return rte_flow_error_set(error, ENOTSUP,
5681 RTE_FLOW_ERROR_TYPE_ITEM,
5682 NULL, "item not supported");
5684 item_flags |= last_item;
5686 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5687 int type = actions->type;
5689 if (!mlx5_flow_os_action_supported(type))
5690 return rte_flow_error_set(error, ENOTSUP,
5691 RTE_FLOW_ERROR_TYPE_ACTION,
5693 "action not supported");
5694 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5695 return rte_flow_error_set(error, ENOTSUP,
5696 RTE_FLOW_ERROR_TYPE_ACTION,
5697 actions, "too many actions");
5699 case RTE_FLOW_ACTION_TYPE_VOID:
5701 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5702 ret = flow_dv_validate_action_port_id(dev,
5709 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5712 case RTE_FLOW_ACTION_TYPE_FLAG:
5713 ret = flow_dv_validate_action_flag(dev, action_flags,
5717 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5718 /* Count all modify-header actions as one. */
5719 if (!(action_flags &
5720 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5722 action_flags |= MLX5_FLOW_ACTION_FLAG |
5723 MLX5_FLOW_ACTION_MARK_EXT;
5725 action_flags |= MLX5_FLOW_ACTION_FLAG;
5728 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5730 case RTE_FLOW_ACTION_TYPE_MARK:
5731 ret = flow_dv_validate_action_mark(dev, actions,
5736 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5737 /* Count all modify-header actions as one. */
5738 if (!(action_flags &
5739 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5741 action_flags |= MLX5_FLOW_ACTION_MARK |
5742 MLX5_FLOW_ACTION_MARK_EXT;
5744 action_flags |= MLX5_FLOW_ACTION_MARK;
5747 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5749 case RTE_FLOW_ACTION_TYPE_SET_META:
5750 ret = flow_dv_validate_action_set_meta(dev, actions,
5755 /* Count all modify-header actions as one action. */
5756 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5758 action_flags |= MLX5_FLOW_ACTION_SET_META;
5759 rw_act_num += MLX5_ACT_NUM_SET_META;
5761 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5762 ret = flow_dv_validate_action_set_tag(dev, actions,
5767 /* Count all modify-header actions as one action. */
5768 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5770 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5771 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5773 case RTE_FLOW_ACTION_TYPE_DROP:
5774 ret = mlx5_flow_validate_action_drop(action_flags,
5778 action_flags |= MLX5_FLOW_ACTION_DROP;
5781 case RTE_FLOW_ACTION_TYPE_QUEUE:
5782 ret = mlx5_flow_validate_action_queue(actions,
5787 queue_index = ((const struct rte_flow_action_queue *)
5788 (actions->conf))->index;
5789 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5792 case RTE_FLOW_ACTION_TYPE_RSS:
5793 rss = actions->conf;
5794 ret = mlx5_flow_validate_action_rss(actions,
5800 if (rss != NULL && rss->queue_num)
5801 queue_index = rss->queue[0];
5802 action_flags |= MLX5_FLOW_ACTION_RSS;
5805 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5807 mlx5_flow_validate_action_default_miss(action_flags,
5811 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5814 case RTE_FLOW_ACTION_TYPE_COUNT:
5815 ret = flow_dv_validate_action_count(dev, error);
5818 action_flags |= MLX5_FLOW_ACTION_COUNT;
5821 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5822 if (flow_dv_validate_action_pop_vlan(dev,
5828 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5831 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5832 ret = flow_dv_validate_action_push_vlan(dev,
5839 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5842 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5843 ret = flow_dv_validate_action_set_vlan_pcp
5844 (action_flags, actions, error);
5847 /* Count PCP with push_vlan command. */
5848 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5850 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5851 ret = flow_dv_validate_action_set_vlan_vid
5852 (item_flags, action_flags,
5856 /* Count VID with push_vlan command. */
5857 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5858 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5860 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5861 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5862 ret = flow_dv_validate_action_l2_encap(dev,
5868 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5871 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5872 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5873 ret = flow_dv_validate_action_decap(dev, action_flags,
5874 actions, item_flags,
5878 action_flags |= MLX5_FLOW_ACTION_DECAP;
5881 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5882 ret = flow_dv_validate_action_raw_encap_decap
5883 (dev, NULL, actions->conf, attr, &action_flags,
5884 &actions_n, actions, item_flags, error);
5888 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5889 decap = actions->conf;
5890 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5892 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5896 encap = actions->conf;
5898 ret = flow_dv_validate_action_raw_encap_decap
5900 decap ? decap : &empty_decap, encap,
5901 attr, &action_flags, &actions_n,
5902 actions, item_flags, error);
5906 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5907 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5908 ret = flow_dv_validate_action_modify_mac(action_flags,
5914 /* Count all modify-header actions as one action. */
5915 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5917 action_flags |= actions->type ==
5918 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5919 MLX5_FLOW_ACTION_SET_MAC_SRC :
5920 MLX5_FLOW_ACTION_SET_MAC_DST;
5922 * Even if the source and destination MAC addresses have
5923 * overlap in the header with 4B alignment, the convert
5924 * function will handle them separately and 4 SW actions
5925 * will be created. And 2 actions will be added each
5926 * time no matter how many bytes of address will be set.
5928 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5930 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5931 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5932 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5938 /* Count all modify-header actions as one action. */
5939 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5941 action_flags |= actions->type ==
5942 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5943 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5944 MLX5_FLOW_ACTION_SET_IPV4_DST;
5945 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5947 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5948 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5949 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5955 if (item_ipv6_proto == IPPROTO_ICMPV6)
5956 return rte_flow_error_set(error, ENOTSUP,
5957 RTE_FLOW_ERROR_TYPE_ACTION,
5959 "Can't change header "
5960 "with ICMPv6 proto");
5961 /* Count all modify-header actions as one action. */
5962 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5964 action_flags |= actions->type ==
5965 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5966 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5967 MLX5_FLOW_ACTION_SET_IPV6_DST;
5968 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5970 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5971 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5972 ret = flow_dv_validate_action_modify_tp(action_flags,
5978 /* Count all modify-header actions as one action. */
5979 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5981 action_flags |= actions->type ==
5982 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5983 MLX5_FLOW_ACTION_SET_TP_SRC :
5984 MLX5_FLOW_ACTION_SET_TP_DST;
5985 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5987 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5988 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5989 ret = flow_dv_validate_action_modify_ttl(action_flags,
5995 /* Count all modify-header actions as one action. */
5996 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5998 action_flags |= actions->type ==
5999 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6000 MLX5_FLOW_ACTION_SET_TTL :
6001 MLX5_FLOW_ACTION_DEC_TTL;
6002 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6004 case RTE_FLOW_ACTION_TYPE_JUMP:
6005 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6012 action_flags |= MLX5_FLOW_ACTION_JUMP;
6014 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6015 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6016 ret = flow_dv_validate_action_modify_tcp_seq
6023 /* Count all modify-header actions as one action. */
6024 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6026 action_flags |= actions->type ==
6027 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6028 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6029 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6030 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6032 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6033 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6034 ret = flow_dv_validate_action_modify_tcp_ack
6041 /* Count all modify-header actions as one action. */
6042 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6044 action_flags |= actions->type ==
6045 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6046 MLX5_FLOW_ACTION_INC_TCP_ACK :
6047 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6048 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6050 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6052 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6053 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6054 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6056 case RTE_FLOW_ACTION_TYPE_METER:
6057 ret = mlx5_flow_validate_action_meter(dev,
6063 action_flags |= MLX5_FLOW_ACTION_METER;
6065 /* Meter action will add one more TAG action. */
6066 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6068 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6069 if (!attr->transfer && !attr->group)
6070 return rte_flow_error_set(error, ENOTSUP,
6071 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6073 "Shared ASO age action is not supported for group 0");
6074 action_flags |= MLX5_FLOW_ACTION_AGE;
6077 case RTE_FLOW_ACTION_TYPE_AGE:
6078 ret = flow_dv_validate_action_age(action_flags,
6083 action_flags |= MLX5_FLOW_ACTION_AGE;
6086 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6087 ret = flow_dv_validate_action_modify_ipv4_dscp
6094 /* Count all modify-header actions as one action. */
6095 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6097 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6098 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6100 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6101 ret = flow_dv_validate_action_modify_ipv6_dscp
6108 /* Count all modify-header actions as one action. */
6109 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6111 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6112 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6114 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6115 ret = flow_dv_validate_action_sample(action_flags,
6121 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6124 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6125 if (actions[0].type != (typeof(actions[0].type))
6126 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6127 return rte_flow_error_set
6129 RTE_FLOW_ERROR_TYPE_ACTION,
6130 NULL, "MLX5 private action "
6131 "must be the first");
6133 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6136 return rte_flow_error_set(error, ENOTSUP,
6137 RTE_FLOW_ERROR_TYPE_ACTION,
6139 "action not supported");
6143 * Validate actions in flow rules
6144 * - Explicit decap action is prohibited by the tunnel offload API.
6145 * - Drop action in tunnel steer rule is prohibited by the API.
6146 * - Application cannot use MARK action because it's value can mask
6147 * tunnel default miss nitification.
6148 * - JUMP in tunnel match rule has no support in current PMD
6150 * - TAG & META are reserved for future uses.
6152 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6153 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6154 MLX5_FLOW_ACTION_MARK |
6155 MLX5_FLOW_ACTION_SET_TAG |
6156 MLX5_FLOW_ACTION_SET_META |
6157 MLX5_FLOW_ACTION_DROP;
6159 if (action_flags & bad_actions_mask)
6160 return rte_flow_error_set
6162 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6163 "Invalid RTE action in tunnel "
6165 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6166 return rte_flow_error_set
6168 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6169 "tunnel set decap rule must terminate "
6172 return rte_flow_error_set
6174 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6175 "tunnel flows for ingress traffic only");
6177 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6178 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6179 MLX5_FLOW_ACTION_MARK |
6180 MLX5_FLOW_ACTION_SET_TAG |
6181 MLX5_FLOW_ACTION_SET_META;
6183 if (action_flags & bad_actions_mask)
6184 return rte_flow_error_set
6186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6187 "Invalid RTE action in tunnel "
6191 * Validate the drop action mutual exclusion with other actions.
6192 * Drop action is mutually-exclusive with any other action, except for
6195 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6196 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6197 return rte_flow_error_set(error, EINVAL,
6198 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6199 "Drop action is mutually-exclusive "
6200 "with any other action, except for "
6202 /* Eswitch has few restrictions on using items and actions */
6203 if (attr->transfer) {
6204 if (!mlx5_flow_ext_mreg_supported(dev) &&
6205 action_flags & MLX5_FLOW_ACTION_FLAG)
6206 return rte_flow_error_set(error, ENOTSUP,
6207 RTE_FLOW_ERROR_TYPE_ACTION,
6209 "unsupported action FLAG");
6210 if (!mlx5_flow_ext_mreg_supported(dev) &&
6211 action_flags & MLX5_FLOW_ACTION_MARK)
6212 return rte_flow_error_set(error, ENOTSUP,
6213 RTE_FLOW_ERROR_TYPE_ACTION,
6215 "unsupported action MARK");
6216 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6217 return rte_flow_error_set(error, ENOTSUP,
6218 RTE_FLOW_ERROR_TYPE_ACTION,
6220 "unsupported action QUEUE");
6221 if (action_flags & MLX5_FLOW_ACTION_RSS)
6222 return rte_flow_error_set(error, ENOTSUP,
6223 RTE_FLOW_ERROR_TYPE_ACTION,
6225 "unsupported action RSS");
6226 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6227 return rte_flow_error_set(error, EINVAL,
6228 RTE_FLOW_ERROR_TYPE_ACTION,
6230 "no fate action is found");
6232 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6233 return rte_flow_error_set(error, EINVAL,
6234 RTE_FLOW_ERROR_TYPE_ACTION,
6236 "no fate action is found");
6239 * Continue validation for Xcap and VLAN actions.
6240 * If hairpin is working in explicit TX rule mode, there is no actions
6241 * splitting and the validation of hairpin ingress flow should be the
6242 * same as other standard flows.
6244 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6245 MLX5_FLOW_VLAN_ACTIONS)) &&
6246 (queue_index == 0xFFFF ||
6247 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6248 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6249 conf->tx_explicit != 0))) {
6250 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6251 MLX5_FLOW_XCAP_ACTIONS)
6252 return rte_flow_error_set(error, ENOTSUP,
6253 RTE_FLOW_ERROR_TYPE_ACTION,
6254 NULL, "encap and decap "
6255 "combination aren't supported");
6256 if (!attr->transfer && attr->ingress) {
6257 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6258 return rte_flow_error_set
6260 RTE_FLOW_ERROR_TYPE_ACTION,
6261 NULL, "encap is not supported"
6262 " for ingress traffic");
6263 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6264 return rte_flow_error_set
6266 RTE_FLOW_ERROR_TYPE_ACTION,
6267 NULL, "push VLAN action not "
6268 "supported for ingress");
6269 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6270 MLX5_FLOW_VLAN_ACTIONS)
6271 return rte_flow_error_set
6273 RTE_FLOW_ERROR_TYPE_ACTION,
6274 NULL, "no support for "
6275 "multiple VLAN actions");
6279 * Hairpin flow will add one more TAG action in TX implicit mode.
6280 * In TX explicit mode, there will be no hairpin flow ID.
6283 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6284 /* extra metadata enabled: one more TAG action will be add. */
6285 if (dev_conf->dv_flow_en &&
6286 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6287 mlx5_flow_ext_mreg_supported(dev))
6288 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6289 if ((uint32_t)rw_act_num >
6290 flow_dv_modify_hdr_action_max(dev, is_root)) {
6291 return rte_flow_error_set(error, ENOTSUP,
6292 RTE_FLOW_ERROR_TYPE_ACTION,
6293 NULL, "too many header modify"
6294 " actions to support");
6300 * Internal preparation function. Allocates the DV flow size,
6301 * this size is constant.
6304 * Pointer to the rte_eth_dev structure.
6306 * Pointer to the flow attributes.
6308 * Pointer to the list of items.
6309 * @param[in] actions
6310 * Pointer to the list of actions.
6312 * Pointer to the error structure.
6315 * Pointer to mlx5_flow object on success,
6316 * otherwise NULL and rte_errno is set.
6318 static struct mlx5_flow *
6319 flow_dv_prepare(struct rte_eth_dev *dev,
6320 const struct rte_flow_attr *attr __rte_unused,
6321 const struct rte_flow_item items[] __rte_unused,
6322 const struct rte_flow_action actions[] __rte_unused,
6323 struct rte_flow_error *error)
6325 uint32_t handle_idx = 0;
6326 struct mlx5_flow *dev_flow;
6327 struct mlx5_flow_handle *dev_handle;
6328 struct mlx5_priv *priv = dev->data->dev_private;
6329 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6332 /* In case of corrupting the memory. */
6333 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6334 rte_flow_error_set(error, ENOSPC,
6335 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6336 "not free temporary device flow");
6339 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6342 rte_flow_error_set(error, ENOMEM,
6343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6344 "not enough memory to create flow handle");
6347 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6348 dev_flow = &wks->flows[wks->flow_idx++];
6349 memset(dev_flow, 0, sizeof(*dev_flow));
6350 dev_flow->handle = dev_handle;
6351 dev_flow->handle_idx = handle_idx;
6353 * In some old rdma-core releases, before continuing, a check of the
6354 * length of matching parameter will be done at first. It needs to use
6355 * the length without misc4 param. If the flow has misc4 support, then
6356 * the length needs to be adjusted accordingly. Each param member is
6357 * aligned with a 64B boundary naturally.
6359 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6360 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6361 dev_flow->ingress = attr->ingress;
6362 dev_flow->dv.transfer = attr->transfer;
6366 #ifdef RTE_LIBRTE_MLX5_DEBUG
6368 * Sanity check for match mask and value. Similar to check_valid_spec() in
6369 * kernel driver. If unmasked bit is present in value, it returns failure.
6372 * pointer to match mask buffer.
6373 * @param match_value
6374 * pointer to match value buffer.
6377 * 0 if valid, -EINVAL otherwise.
6380 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6382 uint8_t *m = match_mask;
6383 uint8_t *v = match_value;
6386 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6389 "match_value differs from match_criteria"
6390 " %p[%u] != %p[%u]",
6391 match_value, i, match_mask, i);
6400 * Add match of ip_version.
6404 * @param[in] headers_v
6405 * Values header pointer.
6406 * @param[in] headers_m
6407 * Masks header pointer.
6408 * @param[in] ip_version
6409 * The IP version to set.
6412 flow_dv_set_match_ip_version(uint32_t group,
6418 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6420 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6422 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6423 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6424 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6428 * Add Ethernet item to matcher and to the value.
6430 * @param[in, out] matcher
6432 * @param[in, out] key
6433 * Flow matcher value.
6435 * Flow pattern to translate.
6437 * Item is inner pattern.
6440 flow_dv_translate_item_eth(void *matcher, void *key,
6441 const struct rte_flow_item *item, int inner,
6444 const struct rte_flow_item_eth *eth_m = item->mask;
6445 const struct rte_flow_item_eth *eth_v = item->spec;
6446 const struct rte_flow_item_eth nic_mask = {
6447 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6448 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6449 .type = RTE_BE16(0xffff),
6462 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6464 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6466 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6468 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6470 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6471 ð_m->dst, sizeof(eth_m->dst));
6472 /* The value must be in the range of the mask. */
6473 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6474 for (i = 0; i < sizeof(eth_m->dst); ++i)
6475 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6476 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6477 ð_m->src, sizeof(eth_m->src));
6478 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6479 /* The value must be in the range of the mask. */
6480 for (i = 0; i < sizeof(eth_m->dst); ++i)
6481 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6483 * HW supports match on one Ethertype, the Ethertype following the last
6484 * VLAN tag of the packet (see PRM).
6485 * Set match on ethertype only if ETH header is not followed by VLAN.
6486 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6487 * ethertype, and use ip_version field instead.
6488 * eCPRI over Ether layer will use type value 0xAEFE.
6490 if (eth_m->type == 0xFFFF) {
6491 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6492 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6493 switch (eth_v->type) {
6494 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6495 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6497 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6498 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6499 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6501 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6502 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6504 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6505 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6511 if (eth_m->has_vlan) {
6512 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6513 if (eth_v->has_vlan) {
6515 * Here, when also has_more_vlan field in VLAN item is
6516 * not set, only single-tagged packets will be matched.
6518 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6522 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6523 rte_be_to_cpu_16(eth_m->type));
6524 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6525 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6529 * Add VLAN item to matcher and to the value.
6531 * @param[in, out] dev_flow
6533 * @param[in, out] matcher
6535 * @param[in, out] key
6536 * Flow matcher value.
6538 * Flow pattern to translate.
6540 * Item is inner pattern.
6543 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6544 void *matcher, void *key,
6545 const struct rte_flow_item *item,
6546 int inner, uint32_t group)
6548 const struct rte_flow_item_vlan *vlan_m = item->mask;
6549 const struct rte_flow_item_vlan *vlan_v = item->spec;
6556 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6558 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6560 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6562 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6564 * This is workaround, masks are not supported,
6565 * and pre-validated.
6568 dev_flow->handle->vf_vlan.tag =
6569 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6572 * When VLAN item exists in flow, mark packet as tagged,
6573 * even if TCI is not specified.
6575 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6576 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6577 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6582 vlan_m = &rte_flow_item_vlan_mask;
6583 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6584 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6585 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6586 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6587 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6588 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6589 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6590 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6592 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6593 * ethertype, and use ip_version field instead.
6595 if (vlan_m->inner_type == 0xFFFF) {
6596 switch (vlan_v->inner_type) {
6597 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6598 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6599 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6600 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6602 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6603 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6605 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6606 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6612 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6613 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6614 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6615 /* Only one vlan_tag bit can be set. */
6616 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6619 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6620 rte_be_to_cpu_16(vlan_m->inner_type));
6621 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6622 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6626 * Add IPV4 item to matcher and to the value.
6628 * @param[in, out] matcher
6630 * @param[in, out] key
6631 * Flow matcher value.
6633 * Flow pattern to translate.
6635 * Item is inner pattern.
6637 * The group to insert the rule.
6640 flow_dv_translate_item_ipv4(void *matcher, void *key,
6641 const struct rte_flow_item *item,
6642 int inner, uint32_t group)
6644 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6645 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6646 const struct rte_flow_item_ipv4 nic_mask = {
6648 .src_addr = RTE_BE32(0xffffffff),
6649 .dst_addr = RTE_BE32(0xffffffff),
6650 .type_of_service = 0xff,
6651 .next_proto_id = 0xff,
6652 .time_to_live = 0xff,
6662 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6664 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6666 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6668 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6670 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6675 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6676 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6677 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6678 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6679 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6680 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6681 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6682 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6683 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6684 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6685 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6686 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6687 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6688 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6689 ipv4_m->hdr.type_of_service);
6690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6691 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6692 ipv4_m->hdr.type_of_service >> 2);
6693 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6695 ipv4_m->hdr.next_proto_id);
6696 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6697 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6698 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6699 ipv4_m->hdr.time_to_live);
6700 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6701 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6702 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6703 !!(ipv4_m->hdr.fragment_offset));
6704 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6705 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6709 * Add IPV6 item to matcher and to the value.
6711 * @param[in, out] matcher
6713 * @param[in, out] key
6714 * Flow matcher value.
6716 * Flow pattern to translate.
6718 * Item is inner pattern.
6720 * The group to insert the rule.
6723 flow_dv_translate_item_ipv6(void *matcher, void *key,
6724 const struct rte_flow_item *item,
6725 int inner, uint32_t group)
6727 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6728 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6729 const struct rte_flow_item_ipv6 nic_mask = {
6732 "\xff\xff\xff\xff\xff\xff\xff\xff"
6733 "\xff\xff\xff\xff\xff\xff\xff\xff",
6735 "\xff\xff\xff\xff\xff\xff\xff\xff"
6736 "\xff\xff\xff\xff\xff\xff\xff\xff",
6737 .vtc_flow = RTE_BE32(0xffffffff),
6744 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6745 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6754 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6756 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6758 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6760 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6762 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6767 size = sizeof(ipv6_m->hdr.dst_addr);
6768 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6769 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6770 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6771 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6772 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6773 for (i = 0; i < size; ++i)
6774 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6775 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6776 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6777 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6778 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6779 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6780 for (i = 0; i < size; ++i)
6781 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6783 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6784 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6785 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6787 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6788 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6791 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6793 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6796 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6798 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6802 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6804 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6805 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6807 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6808 ipv6_m->hdr.hop_limits);
6809 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6810 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6811 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6812 !!(ipv6_m->has_frag_ext));
6813 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6814 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6818 * Add IPV6 fragment extension item to matcher and to the value.
6820 * @param[in, out] matcher
6822 * @param[in, out] key
6823 * Flow matcher value.
6825 * Flow pattern to translate.
6827 * Item is inner pattern.
6830 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6831 const struct rte_flow_item *item,
6834 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6835 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6836 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6838 .next_header = 0xff,
6839 .frag_data = RTE_BE16(0xffff),
6846 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6848 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6850 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6852 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6854 /* IPv6 fragment extension item exists, so packet is IP fragment. */
6855 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6856 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6857 if (!ipv6_frag_ext_v)
6859 if (!ipv6_frag_ext_m)
6860 ipv6_frag_ext_m = &nic_mask;
6861 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6862 ipv6_frag_ext_m->hdr.next_header);
6863 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6864 ipv6_frag_ext_v->hdr.next_header &
6865 ipv6_frag_ext_m->hdr.next_header);
6869 * Add TCP item to matcher and to the value.
6871 * @param[in, out] matcher
6873 * @param[in, out] key
6874 * Flow matcher value.
6876 * Flow pattern to translate.
6878 * Item is inner pattern.
6881 flow_dv_translate_item_tcp(void *matcher, void *key,
6882 const struct rte_flow_item *item,
6885 const struct rte_flow_item_tcp *tcp_m = item->mask;
6886 const struct rte_flow_item_tcp *tcp_v = item->spec;
6891 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6893 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6895 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6897 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6899 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6900 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6904 tcp_m = &rte_flow_item_tcp_mask;
6905 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6906 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6907 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6908 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6909 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6910 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6911 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6912 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6913 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6914 tcp_m->hdr.tcp_flags);
6915 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6916 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6920 * Add UDP item to matcher and to the value.
6922 * @param[in, out] matcher
6924 * @param[in, out] key
6925 * Flow matcher value.
6927 * Flow pattern to translate.
6929 * Item is inner pattern.
6932 flow_dv_translate_item_udp(void *matcher, void *key,
6933 const struct rte_flow_item *item,
6936 const struct rte_flow_item_udp *udp_m = item->mask;
6937 const struct rte_flow_item_udp *udp_v = item->spec;
6942 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6944 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6946 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6948 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6950 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6951 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6955 udp_m = &rte_flow_item_udp_mask;
6956 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6957 rte_be_to_cpu_16(udp_m->hdr.src_port));
6958 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6959 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6960 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6961 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6962 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6963 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6967 * Add GRE optional Key item to matcher and to the value.
6969 * @param[in, out] matcher
6971 * @param[in, out] key
6972 * Flow matcher value.
6974 * Flow pattern to translate.
6976 * Item is inner pattern.
6979 flow_dv_translate_item_gre_key(void *matcher, void *key,
6980 const struct rte_flow_item *item)
6982 const rte_be32_t *key_m = item->mask;
6983 const rte_be32_t *key_v = item->spec;
6984 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6985 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6986 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6988 /* GRE K bit must be on and should already be validated */
6989 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6990 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6994 key_m = &gre_key_default_mask;
6995 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6996 rte_be_to_cpu_32(*key_m) >> 8);
6997 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6998 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6999 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7000 rte_be_to_cpu_32(*key_m) & 0xFF);
7001 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7002 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7006 * Add GRE item to matcher and to the value.
7008 * @param[in, out] matcher
7010 * @param[in, out] key
7011 * Flow matcher value.
7013 * Flow pattern to translate.
7015 * Item is inner pattern.
7018 flow_dv_translate_item_gre(void *matcher, void *key,
7019 const struct rte_flow_item *item,
7022 const struct rte_flow_item_gre *gre_m = item->mask;
7023 const struct rte_flow_item_gre *gre_v = item->spec;
7026 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7027 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7034 uint16_t s_present:1;
7035 uint16_t k_present:1;
7036 uint16_t rsvd_bit1:1;
7037 uint16_t c_present:1;
7041 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7044 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7046 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7048 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7050 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7052 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7053 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7057 gre_m = &rte_flow_item_gre_mask;
7058 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7059 rte_be_to_cpu_16(gre_m->protocol));
7060 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7061 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7062 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7063 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7064 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7065 gre_crks_rsvd0_ver_m.c_present);
7066 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7067 gre_crks_rsvd0_ver_v.c_present &
7068 gre_crks_rsvd0_ver_m.c_present);
7069 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7070 gre_crks_rsvd0_ver_m.k_present);
7071 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7072 gre_crks_rsvd0_ver_v.k_present &
7073 gre_crks_rsvd0_ver_m.k_present);
7074 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7075 gre_crks_rsvd0_ver_m.s_present);
7076 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7077 gre_crks_rsvd0_ver_v.s_present &
7078 gre_crks_rsvd0_ver_m.s_present);
7082 * Add NVGRE item to matcher and to the value.
7084 * @param[in, out] matcher
7086 * @param[in, out] key
7087 * Flow matcher value.
7089 * Flow pattern to translate.
7091 * Item is inner pattern.
7094 flow_dv_translate_item_nvgre(void *matcher, void *key,
7095 const struct rte_flow_item *item,
7098 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7099 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7100 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7101 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7102 const char *tni_flow_id_m;
7103 const char *tni_flow_id_v;
7109 /* For NVGRE, GRE header fields must be set with defined values. */
7110 const struct rte_flow_item_gre gre_spec = {
7111 .c_rsvd0_ver = RTE_BE16(0x2000),
7112 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7114 const struct rte_flow_item_gre gre_mask = {
7115 .c_rsvd0_ver = RTE_BE16(0xB000),
7116 .protocol = RTE_BE16(UINT16_MAX),
7118 const struct rte_flow_item gre_item = {
7123 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7127 nvgre_m = &rte_flow_item_nvgre_mask;
7128 tni_flow_id_m = (const char *)nvgre_m->tni;
7129 tni_flow_id_v = (const char *)nvgre_v->tni;
7130 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7131 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7132 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7133 memcpy(gre_key_m, tni_flow_id_m, size);
7134 for (i = 0; i < size; ++i)
7135 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7139 * Add VXLAN item to matcher and to the value.
7141 * @param[in, out] matcher
7143 * @param[in, out] key
7144 * Flow matcher value.
7146 * Flow pattern to translate.
7148 * Item is inner pattern.
7151 flow_dv_translate_item_vxlan(void *matcher, void *key,
7152 const struct rte_flow_item *item,
7155 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7156 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7159 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7160 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7168 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7170 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7172 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7174 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7176 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7177 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7178 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7179 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7180 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7185 vxlan_m = &rte_flow_item_vxlan_mask;
7186 size = sizeof(vxlan_m->vni);
7187 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7188 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7189 memcpy(vni_m, vxlan_m->vni, size);
7190 for (i = 0; i < size; ++i)
7191 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7195 * Add VXLAN-GPE item to matcher and to the value.
7197 * @param[in, out] matcher
7199 * @param[in, out] key
7200 * Flow matcher value.
7202 * Flow pattern to translate.
7204 * Item is inner pattern.
7208 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7209 const struct rte_flow_item *item, int inner)
7211 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7212 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7216 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7218 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7224 uint8_t flags_m = 0xff;
7225 uint8_t flags_v = 0xc;
7228 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7230 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7232 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7234 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7236 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7237 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7238 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7239 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7240 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7245 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7246 size = sizeof(vxlan_m->vni);
7247 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7248 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7249 memcpy(vni_m, vxlan_m->vni, size);
7250 for (i = 0; i < size; ++i)
7251 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7252 if (vxlan_m->flags) {
7253 flags_m = vxlan_m->flags;
7254 flags_v = vxlan_v->flags;
7256 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7257 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7258 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7260 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7265 * Add Geneve item to matcher and to the value.
7267 * @param[in, out] matcher
7269 * @param[in, out] key
7270 * Flow matcher value.
7272 * Flow pattern to translate.
7274 * Item is inner pattern.
7278 flow_dv_translate_item_geneve(void *matcher, void *key,
7279 const struct rte_flow_item *item, int inner)
7281 const struct rte_flow_item_geneve *geneve_m = item->mask;
7282 const struct rte_flow_item_geneve *geneve_v = item->spec;
7285 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7286 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7295 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7297 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7299 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7301 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7303 dport = MLX5_UDP_PORT_GENEVE;
7304 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7305 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7306 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7311 geneve_m = &rte_flow_item_geneve_mask;
7312 size = sizeof(geneve_m->vni);
7313 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7314 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7315 memcpy(vni_m, geneve_m->vni, size);
7316 for (i = 0; i < size; ++i)
7317 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7318 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7319 rte_be_to_cpu_16(geneve_m->protocol));
7320 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7321 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7322 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7323 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7324 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7325 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7326 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7327 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7328 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7329 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7330 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7331 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7332 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7336 * Create Geneve TLV option resource.
7338 * @param dev[in, out]
7339 * Pointer to rte_eth_dev structure.
7340 * @param[in, out] tag_be24
7341 * Tag value in big endian then R-shift 8.
7342 * @parm[in, out] dev_flow
7343 * Pointer to the dev_flow.
7345 * pointer to error structure.
7348 * 0 on success otherwise -errno and errno is set.
7352 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7353 const struct rte_flow_item *item,
7354 struct rte_flow_error *error)
7356 struct mlx5_priv *priv = dev->data->dev_private;
7357 struct mlx5_dev_ctx_shared *sh = priv->sh;
7358 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7359 sh->geneve_tlv_option_resource;
7360 struct mlx5_devx_obj *obj;
7361 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7366 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7367 if (geneve_opt_resource != NULL) {
7368 if (geneve_opt_resource->option_class ==
7369 geneve_opt_v->option_class &&
7370 geneve_opt_resource->option_type ==
7371 geneve_opt_v->option_type &&
7372 geneve_opt_resource->length ==
7373 geneve_opt_v->option_len) {
7374 /* We already have GENVE TLV option obj allocated. */
7375 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7378 ret = rte_flow_error_set(error, ENOMEM,
7379 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7380 "Only one GENEVE TLV option supported");
7384 /* Create a GENEVE TLV object and resource. */
7385 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7386 geneve_opt_v->option_class,
7387 geneve_opt_v->option_type,
7388 geneve_opt_v->option_len);
7390 ret = rte_flow_error_set(error, ENODATA,
7391 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7392 "Failed to create GENEVE TLV Devx object");
7395 sh->geneve_tlv_option_resource =
7396 mlx5_malloc(MLX5_MEM_ZERO,
7397 sizeof(*geneve_opt_resource),
7399 if (!sh->geneve_tlv_option_resource) {
7400 claim_zero(mlx5_devx_cmd_destroy(obj));
7401 ret = rte_flow_error_set(error, ENOMEM,
7402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7403 "GENEVE TLV object memory allocation failed");
7406 geneve_opt_resource = sh->geneve_tlv_option_resource;
7407 geneve_opt_resource->obj = obj;
7408 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7409 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7410 geneve_opt_resource->length = geneve_opt_v->option_len;
7411 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7415 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7420 * Add Geneve TLV option item to matcher.
7422 * @param[in, out] dev
7423 * Pointer to rte_eth_dev structure.
7424 * @param[in, out] matcher
7426 * @param[in, out] key
7427 * Flow matcher value.
7429 * Flow pattern to translate.
7431 * Pointer to error structure.
7434 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
7435 void *key, const struct rte_flow_item *item,
7436 struct rte_flow_error *error)
7438 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
7439 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7440 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7441 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7442 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7444 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7445 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
7451 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
7452 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
7455 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
7459 * Set the option length in GENEVE header if not requested.
7460 * The GENEVE TLV option length is expressed by the option length field
7461 * in the GENEVE header.
7462 * If the option length was not requested but the GENEVE TLV option item
7463 * is present we set the option length field implicitly.
7465 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
7466 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7467 MLX5_GENEVE_OPTLEN_MASK);
7468 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7469 geneve_opt_v->option_len + 1);
7472 if (geneve_opt_v->data) {
7473 memcpy(&opt_data_key, geneve_opt_v->data,
7474 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7475 sizeof(opt_data_key)));
7476 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7477 sizeof(opt_data_key));
7478 memcpy(&opt_data_mask, geneve_opt_m->data,
7479 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7480 sizeof(opt_data_mask)));
7481 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7482 sizeof(opt_data_mask));
7483 MLX5_SET(fte_match_set_misc3, misc3_m,
7484 geneve_tlv_option_0_data,
7485 rte_be_to_cpu_32(opt_data_mask));
7486 MLX5_SET(fte_match_set_misc3, misc3_v,
7487 geneve_tlv_option_0_data,
7488 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
7494 * Add MPLS item to matcher and to the value.
7496 * @param[in, out] matcher
7498 * @param[in, out] key
7499 * Flow matcher value.
7501 * Flow pattern to translate.
7502 * @param[in] prev_layer
7503 * The protocol layer indicated in previous item.
7505 * Item is inner pattern.
7508 flow_dv_translate_item_mpls(void *matcher, void *key,
7509 const struct rte_flow_item *item,
7510 uint64_t prev_layer,
7513 const uint32_t *in_mpls_m = item->mask;
7514 const uint32_t *in_mpls_v = item->spec;
7515 uint32_t *out_mpls_m = 0;
7516 uint32_t *out_mpls_v = 0;
7517 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7518 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7519 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7521 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7522 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7523 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7525 switch (prev_layer) {
7526 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7529 MLX5_UDP_PORT_MPLS);
7531 case MLX5_FLOW_LAYER_GRE:
7532 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7533 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7534 RTE_ETHER_TYPE_MPLS);
7537 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7538 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7545 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7546 switch (prev_layer) {
7547 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7549 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7550 outer_first_mpls_over_udp);
7552 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7553 outer_first_mpls_over_udp);
7555 case MLX5_FLOW_LAYER_GRE:
7557 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7558 outer_first_mpls_over_gre);
7560 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7561 outer_first_mpls_over_gre);
7564 /* Inner MPLS not over GRE is not supported. */
7567 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7571 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7577 if (out_mpls_m && out_mpls_v) {
7578 *out_mpls_m = *in_mpls_m;
7579 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7584 * Add metadata register item to matcher
7586 * @param[in, out] matcher
7588 * @param[in, out] key
7589 * Flow matcher value.
7590 * @param[in] reg_type
7591 * Type of device metadata register
7598 flow_dv_match_meta_reg(void *matcher, void *key,
7599 enum modify_reg reg_type,
7600 uint32_t data, uint32_t mask)
7603 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7605 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7611 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7612 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7615 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7616 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7620 * The metadata register C0 field might be divided into
7621 * source vport index and META item value, we should set
7622 * this field according to specified mask, not as whole one.
7624 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7626 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7627 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7630 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7633 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7634 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7637 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7638 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7641 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7642 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7645 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7646 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7649 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7650 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7653 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7654 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7657 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7658 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7667 * Add MARK item to matcher
7670 * The device to configure through.
7671 * @param[in, out] matcher
7673 * @param[in, out] key
7674 * Flow matcher value.
7676 * Flow pattern to translate.
7679 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7680 void *matcher, void *key,
7681 const struct rte_flow_item *item)
7683 struct mlx5_priv *priv = dev->data->dev_private;
7684 const struct rte_flow_item_mark *mark;
7688 mark = item->mask ? (const void *)item->mask :
7689 &rte_flow_item_mark_mask;
7690 mask = mark->id & priv->sh->dv_mark_mask;
7691 mark = (const void *)item->spec;
7693 value = mark->id & priv->sh->dv_mark_mask & mask;
7695 enum modify_reg reg;
7697 /* Get the metadata register index for the mark. */
7698 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7699 MLX5_ASSERT(reg > 0);
7700 if (reg == REG_C_0) {
7701 struct mlx5_priv *priv = dev->data->dev_private;
7702 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7703 uint32_t shl_c0 = rte_bsf32(msk_c0);
7709 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7714 * Add META item to matcher
7717 * The devich to configure through.
7718 * @param[in, out] matcher
7720 * @param[in, out] key
7721 * Flow matcher value.
7723 * Attributes of flow that includes this item.
7725 * Flow pattern to translate.
7728 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7729 void *matcher, void *key,
7730 const struct rte_flow_attr *attr,
7731 const struct rte_flow_item *item)
7733 const struct rte_flow_item_meta *meta_m;
7734 const struct rte_flow_item_meta *meta_v;
7736 meta_m = (const void *)item->mask;
7738 meta_m = &rte_flow_item_meta_mask;
7739 meta_v = (const void *)item->spec;
7742 uint32_t value = meta_v->data;
7743 uint32_t mask = meta_m->data;
7745 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7748 MLX5_ASSERT(reg != REG_NON);
7750 * In datapath code there is no endianness
7751 * coversions for perfromance reasons, all
7752 * pattern conversions are done in rte_flow.
7754 value = rte_cpu_to_be_32(value);
7755 mask = rte_cpu_to_be_32(mask);
7756 if (reg == REG_C_0) {
7757 struct mlx5_priv *priv = dev->data->dev_private;
7758 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7759 uint32_t shl_c0 = rte_bsf32(msk_c0);
7760 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7761 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7768 MLX5_ASSERT(msk_c0);
7769 MLX5_ASSERT(!(~msk_c0 & mask));
7771 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7776 * Add vport metadata Reg C0 item to matcher
7778 * @param[in, out] matcher
7780 * @param[in, out] key
7781 * Flow matcher value.
7783 * Flow pattern to translate.
7786 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7787 uint32_t value, uint32_t mask)
7789 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7793 * Add tag item to matcher
7796 * The devich to configure through.
7797 * @param[in, out] matcher
7799 * @param[in, out] key
7800 * Flow matcher value.
7802 * Flow pattern to translate.
7805 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7806 void *matcher, void *key,
7807 const struct rte_flow_item *item)
7809 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7810 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7811 uint32_t mask, value;
7814 value = tag_v->data;
7815 mask = tag_m ? tag_m->data : UINT32_MAX;
7816 if (tag_v->id == REG_C_0) {
7817 struct mlx5_priv *priv = dev->data->dev_private;
7818 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7819 uint32_t shl_c0 = rte_bsf32(msk_c0);
7825 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7829 * Add TAG item to matcher
7832 * The devich to configure through.
7833 * @param[in, out] matcher
7835 * @param[in, out] key
7836 * Flow matcher value.
7838 * Flow pattern to translate.
7841 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7842 void *matcher, void *key,
7843 const struct rte_flow_item *item)
7845 const struct rte_flow_item_tag *tag_v = item->spec;
7846 const struct rte_flow_item_tag *tag_m = item->mask;
7847 enum modify_reg reg;
7850 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7851 /* Get the metadata register index for the tag. */
7852 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7853 MLX5_ASSERT(reg > 0);
7854 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7858 * Add source vport match to the specified matcher.
7860 * @param[in, out] matcher
7862 * @param[in, out] key
7863 * Flow matcher value.
7865 * Source vport value to match
7870 flow_dv_translate_item_source_vport(void *matcher, void *key,
7871 int16_t port, uint16_t mask)
7873 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7874 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7876 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7877 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7881 * Translate port-id item to eswitch match on port-id.
7884 * The devich to configure through.
7885 * @param[in, out] matcher
7887 * @param[in, out] key
7888 * Flow matcher value.
7890 * Flow pattern to translate.
7895 * 0 on success, a negative errno value otherwise.
7898 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7899 void *key, const struct rte_flow_item *item,
7900 const struct rte_flow_attr *attr)
7902 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7903 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7904 struct mlx5_priv *priv;
7907 mask = pid_m ? pid_m->id : 0xffff;
7908 id = pid_v ? pid_v->id : dev->data->port_id;
7909 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7913 * Translate to vport field or to metadata, depending on mode.
7914 * Kernel can use either misc.source_port or half of C0 metadata
7917 if (priv->vport_meta_mask) {
7919 * Provide the hint for SW steering library
7920 * to insert the flow into ingress domain and
7921 * save the extra vport match.
7923 if (mask == 0xffff && priv->vport_id == 0xffff &&
7924 priv->pf_bond < 0 && attr->transfer)
7925 flow_dv_translate_item_source_vport
7926 (matcher, key, priv->vport_id, mask);
7928 flow_dv_translate_item_meta_vport
7930 priv->vport_meta_tag,
7931 priv->vport_meta_mask);
7933 flow_dv_translate_item_source_vport(matcher, key,
7934 priv->vport_id, mask);
7940 * Add ICMP6 item to matcher and to the value.
7942 * @param[in, out] matcher
7944 * @param[in, out] key
7945 * Flow matcher value.
7947 * Flow pattern to translate.
7949 * Item is inner pattern.
7952 flow_dv_translate_item_icmp6(void *matcher, void *key,
7953 const struct rte_flow_item *item,
7956 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7957 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7960 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7962 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7964 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7966 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7968 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7970 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7972 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7973 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7977 icmp6_m = &rte_flow_item_icmp6_mask;
7978 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7979 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7980 icmp6_v->type & icmp6_m->type);
7981 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7982 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7983 icmp6_v->code & icmp6_m->code);
7987 * Add ICMP item to matcher and to the value.
7989 * @param[in, out] matcher
7991 * @param[in, out] key
7992 * Flow matcher value.
7994 * Flow pattern to translate.
7996 * Item is inner pattern.
7999 flow_dv_translate_item_icmp(void *matcher, void *key,
8000 const struct rte_flow_item *item,
8003 const struct rte_flow_item_icmp *icmp_m = item->mask;
8004 const struct rte_flow_item_icmp *icmp_v = item->spec;
8005 uint32_t icmp_header_data_m = 0;
8006 uint32_t icmp_header_data_v = 0;
8009 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8011 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8013 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8015 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8017 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8019 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8021 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8022 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8026 icmp_m = &rte_flow_item_icmp_mask;
8027 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8028 icmp_m->hdr.icmp_type);
8029 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8030 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8031 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8032 icmp_m->hdr.icmp_code);
8033 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8034 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8035 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8036 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8037 if (icmp_header_data_m) {
8038 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8039 icmp_header_data_v |=
8040 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8041 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8042 icmp_header_data_m);
8043 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8044 icmp_header_data_v & icmp_header_data_m);
8049 * Add GTP item to matcher and to the value.
8051 * @param[in, out] matcher
8053 * @param[in, out] key
8054 * Flow matcher value.
8056 * Flow pattern to translate.
8058 * Item is inner pattern.
8061 flow_dv_translate_item_gtp(void *matcher, void *key,
8062 const struct rte_flow_item *item, int inner)
8064 const struct rte_flow_item_gtp *gtp_m = item->mask;
8065 const struct rte_flow_item_gtp *gtp_v = item->spec;
8068 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8070 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8071 uint16_t dport = RTE_GTPU_UDP_PORT;
8074 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8076 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8078 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8080 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8082 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8083 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8089 gtp_m = &rte_flow_item_gtp_mask;
8090 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8091 gtp_m->v_pt_rsv_flags);
8092 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8093 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8094 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8095 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8096 gtp_v->msg_type & gtp_m->msg_type);
8097 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8098 rte_be_to_cpu_32(gtp_m->teid));
8099 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8100 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8104 * Add GTP PSC item to matcher.
8106 * @param[in, out] matcher
8108 * @param[in, out] key
8109 * Flow matcher value.
8111 * Flow pattern to translate.
8114 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8115 const struct rte_flow_item *item)
8117 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8118 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8119 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8121 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8127 uint8_t next_ext_header_type;
8132 /* Always set E-flag match on one, regardless of GTP item settings. */
8133 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8134 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8135 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8136 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8137 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8138 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8139 /*Set next extension header type. */
8142 dw_2.next_ext_header_type = 0xff;
8143 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8144 rte_cpu_to_be_32(dw_2.w32));
8147 dw_2.next_ext_header_type = 0x85;
8148 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8149 rte_cpu_to_be_32(dw_2.w32));
8161 /*Set extension header PDU type and Qos. */
8163 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8165 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8166 dw_0.qfi = gtp_psc_m->qfi;
8167 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8168 rte_cpu_to_be_32(dw_0.w32));
8170 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8171 gtp_psc_m->pdu_type);
8172 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8173 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8174 rte_cpu_to_be_32(dw_0.w32));
8180 * Add eCPRI item to matcher and to the value.
8183 * The devich to configure through.
8184 * @param[in, out] matcher
8186 * @param[in, out] key
8187 * Flow matcher value.
8189 * Flow pattern to translate.
8190 * @param[in] samples
8191 * Sample IDs to be used in the matching.
8194 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8195 void *key, const struct rte_flow_item *item)
8197 struct mlx5_priv *priv = dev->data->dev_private;
8198 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8199 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8200 struct rte_ecpri_common_hdr common;
8201 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8203 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8211 ecpri_m = &rte_flow_item_ecpri_mask;
8213 * Maximal four DW samples are supported in a single matching now.
8214 * Two are used now for a eCPRI matching:
8215 * 1. Type: one byte, mask should be 0x00ff0000 in network order
8216 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8219 if (!ecpri_m->hdr.common.u32)
8221 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8222 /* Need to take the whole DW as the mask to fill the entry. */
8223 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8224 prog_sample_field_value_0);
8225 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8226 prog_sample_field_value_0);
8227 /* Already big endian (network order) in the header. */
8228 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8229 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8230 /* Sample#0, used for matching type, offset 0. */
8231 MLX5_SET(fte_match_set_misc4, misc4_m,
8232 prog_sample_field_id_0, samples[0]);
8233 /* It makes no sense to set the sample ID in the mask field. */
8234 MLX5_SET(fte_match_set_misc4, misc4_v,
8235 prog_sample_field_id_0, samples[0]);
8237 * Checking if message body part needs to be matched.
8238 * Some wildcard rules only matching type field should be supported.
8240 if (ecpri_m->hdr.dummy[0]) {
8241 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8242 switch (common.type) {
8243 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8244 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8245 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8246 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8247 prog_sample_field_value_1);
8248 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8249 prog_sample_field_value_1);
8250 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8251 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8252 ecpri_m->hdr.dummy[0];
8253 /* Sample#1, to match message body, offset 4. */
8254 MLX5_SET(fte_match_set_misc4, misc4_m,
8255 prog_sample_field_id_1, samples[1]);
8256 MLX5_SET(fte_match_set_misc4, misc4_v,
8257 prog_sample_field_id_1, samples[1]);
8260 /* Others, do not match any sample ID. */
8266 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8268 #define HEADER_IS_ZERO(match_criteria, headers) \
8269 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
8270 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8273 * Calculate flow matcher enable bitmap.
8275 * @param match_criteria
8276 * Pointer to flow matcher criteria.
8279 * Bitmap of enabled fields.
8282 flow_dv_matcher_enable(uint32_t *match_criteria)
8284 uint8_t match_criteria_enable;
8286 match_criteria_enable =
8287 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8288 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8289 match_criteria_enable |=
8290 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8291 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8292 match_criteria_enable |=
8293 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8294 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8295 match_criteria_enable |=
8296 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8297 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8298 match_criteria_enable |=
8299 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8300 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8301 match_criteria_enable |=
8302 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8303 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8304 return match_criteria_enable;
8307 struct mlx5_hlist_entry *
8308 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8310 struct mlx5_dev_ctx_shared *sh = list->ctx;
8311 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8312 struct rte_eth_dev *dev = ctx->dev;
8313 struct mlx5_flow_tbl_data_entry *tbl_data;
8314 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8315 struct rte_flow_error *error = ctx->error;
8316 union mlx5_flow_tbl_key key = { .v64 = key64 };
8317 struct mlx5_flow_tbl_resource *tbl;
8322 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8324 rte_flow_error_set(error, ENOMEM,
8325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8327 "cannot allocate flow table data entry");
8330 tbl_data->idx = idx;
8331 tbl_data->tunnel = tt_prm->tunnel;
8332 tbl_data->group_id = tt_prm->group_id;
8333 tbl_data->external = !!tt_prm->external;
8334 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8335 tbl_data->is_egress = !!key.direction;
8336 tbl_data->is_transfer = !!key.domain;
8337 tbl_data->dummy = !!key.dummy;
8338 tbl_data->table_id = key.table_id;
8339 tbl = &tbl_data->tbl;
8341 return &tbl_data->entry;
8343 domain = sh->fdb_domain;
8344 else if (key.direction)
8345 domain = sh->tx_domain;
8347 domain = sh->rx_domain;
8348 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8350 rte_flow_error_set(error, ENOMEM,
8351 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8352 NULL, "cannot create flow table object");
8353 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8357 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8358 (tbl->obj, &tbl_data->jump.action);
8360 rte_flow_error_set(error, ENOMEM,
8361 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8363 "cannot create flow jump action");
8364 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8365 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8369 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8370 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8372 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8373 flow_dv_matcher_create_cb,
8374 flow_dv_matcher_match_cb,
8375 flow_dv_matcher_remove_cb);
8376 return &tbl_data->entry;
8380 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8381 struct mlx5_hlist_entry *entry, uint64_t key64,
8382 void *cb_ctx __rte_unused)
8384 struct mlx5_flow_tbl_data_entry *tbl_data =
8385 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8386 union mlx5_flow_tbl_key key = { .v64 = key64 };
8388 return tbl_data->table_id != key.table_id ||
8389 tbl_data->dummy != key.dummy ||
8390 tbl_data->is_transfer != key.domain ||
8391 tbl_data->is_egress != key.direction;
8397 * @param[in, out] dev
8398 * Pointer to rte_eth_dev structure.
8399 * @param[in] table_id
8402 * Direction of the table.
8403 * @param[in] transfer
8404 * E-Switch or NIC flow.
8406 * Dummy entry for dv API.
8408 * pointer to error structure.
8411 * Returns tables resource based on the index, NULL in case of failed.
8413 struct mlx5_flow_tbl_resource *
8414 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8415 uint32_t table_id, uint8_t egress,
8418 const struct mlx5_flow_tunnel *tunnel,
8419 uint32_t group_id, uint8_t dummy,
8420 struct rte_flow_error *error)
8422 struct mlx5_priv *priv = dev->data->dev_private;
8423 union mlx5_flow_tbl_key table_key = {
8425 .table_id = table_id,
8427 .domain = !!transfer,
8428 .direction = !!egress,
8431 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8433 .group_id = group_id,
8434 .external = external,
8436 struct mlx5_flow_cb_ctx ctx = {
8441 struct mlx5_hlist_entry *entry;
8442 struct mlx5_flow_tbl_data_entry *tbl_data;
8444 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8446 rte_flow_error_set(error, ENOMEM,
8447 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8448 "cannot get table");
8451 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8452 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8453 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8454 return &tbl_data->tbl;
8458 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8459 struct mlx5_hlist_entry *entry)
8461 struct mlx5_dev_ctx_shared *sh = list->ctx;
8462 struct mlx5_flow_tbl_data_entry *tbl_data =
8463 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8465 MLX5_ASSERT(entry && sh);
8466 if (tbl_data->jump.action)
8467 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8468 if (tbl_data->tbl.obj)
8469 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8470 if (tbl_data->tunnel_offload && tbl_data->external) {
8471 struct mlx5_hlist_entry *he;
8472 struct mlx5_hlist *tunnel_grp_hash;
8473 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8474 union tunnel_tbl_key tunnel_key = {
8475 .tunnel_id = tbl_data->tunnel ?
8476 tbl_data->tunnel->tunnel_id : 0,
8477 .group = tbl_data->group_id
8479 uint32_t table_id = tbl_data->table_id;
8481 tunnel_grp_hash = tbl_data->tunnel ?
8482 tbl_data->tunnel->groups :
8484 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8486 mlx5_hlist_unregister(tunnel_grp_hash, he);
8488 "Table_id %u tunnel %u group %u released.",
8491 tbl_data->tunnel->tunnel_id : 0,
8492 tbl_data->group_id);
8494 mlx5_cache_list_destroy(&tbl_data->matchers);
8495 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8499 * Release a flow table.
8502 * Pointer to device shared structure.
8504 * Table resource to be released.
8507 * Returns 0 if table was released, else return 1;
8510 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8511 struct mlx5_flow_tbl_resource *tbl)
8513 struct mlx5_flow_tbl_data_entry *tbl_data =
8514 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8518 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8522 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8523 struct mlx5_cache_entry *entry, void *cb_ctx)
8525 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8526 struct mlx5_flow_dv_matcher *ref = ctx->data;
8527 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8530 return cur->crc != ref->crc ||
8531 cur->priority != ref->priority ||
8532 memcmp((const void *)cur->mask.buf,
8533 (const void *)ref->mask.buf, ref->mask.size);
8536 struct mlx5_cache_entry *
8537 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8538 struct mlx5_cache_entry *entry __rte_unused,
8541 struct mlx5_dev_ctx_shared *sh = list->ctx;
8542 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8543 struct mlx5_flow_dv_matcher *ref = ctx->data;
8544 struct mlx5_flow_dv_matcher *cache;
8545 struct mlx5dv_flow_matcher_attr dv_attr = {
8546 .type = IBV_FLOW_ATTR_NORMAL,
8547 .match_mask = (void *)&ref->mask,
8549 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8553 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8555 rte_flow_error_set(ctx->error, ENOMEM,
8556 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8557 "cannot create matcher");
8561 dv_attr.match_criteria_enable =
8562 flow_dv_matcher_enable(cache->mask.buf);
8563 dv_attr.priority = ref->priority;
8565 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8566 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8567 &cache->matcher_object);
8570 rte_flow_error_set(ctx->error, ENOMEM,
8571 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8572 "cannot create matcher");
8575 return &cache->entry;
8579 * Register the flow matcher.
8581 * @param[in, out] dev
8582 * Pointer to rte_eth_dev structure.
8583 * @param[in, out] matcher
8584 * Pointer to flow matcher.
8585 * @param[in, out] key
8586 * Pointer to flow table key.
8587 * @parm[in, out] dev_flow
8588 * Pointer to the dev_flow.
8590 * pointer to error structure.
8593 * 0 on success otherwise -errno and errno is set.
8596 flow_dv_matcher_register(struct rte_eth_dev *dev,
8597 struct mlx5_flow_dv_matcher *ref,
8598 union mlx5_flow_tbl_key *key,
8599 struct mlx5_flow *dev_flow,
8600 const struct mlx5_flow_tunnel *tunnel,
8602 struct rte_flow_error *error)
8604 struct mlx5_cache_entry *entry;
8605 struct mlx5_flow_dv_matcher *cache;
8606 struct mlx5_flow_tbl_resource *tbl;
8607 struct mlx5_flow_tbl_data_entry *tbl_data;
8608 struct mlx5_flow_cb_ctx ctx = {
8614 * tunnel offload API requires this registration for cases when
8615 * tunnel match rule was inserted before tunnel set rule.
8617 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8618 key->direction, key->domain,
8619 dev_flow->external, tunnel,
8620 group_id, 0, error);
8622 return -rte_errno; /* No need to refill the error info */
8623 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8625 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8627 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8628 return rte_flow_error_set(error, ENOMEM,
8629 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8630 "cannot allocate ref memory");
8632 cache = container_of(entry, typeof(*cache), entry);
8633 dev_flow->handle->dvh.matcher = cache;
8637 struct mlx5_hlist_entry *
8638 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8640 struct mlx5_dev_ctx_shared *sh = list->ctx;
8641 struct rte_flow_error *error = ctx;
8642 struct mlx5_flow_dv_tag_resource *entry;
8646 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8648 rte_flow_error_set(error, ENOMEM,
8649 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8650 "cannot allocate resource memory");
8654 entry->tag_id = key;
8655 ret = mlx5_flow_os_create_flow_action_tag(key,
8658 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8659 rte_flow_error_set(error, ENOMEM,
8660 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8661 NULL, "cannot create action");
8664 return &entry->entry;
8668 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8669 struct mlx5_hlist_entry *entry, uint64_t key,
8670 void *cb_ctx __rte_unused)
8672 struct mlx5_flow_dv_tag_resource *tag =
8673 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8675 return key != tag->tag_id;
8679 * Find existing tag resource or create and register a new one.
8681 * @param dev[in, out]
8682 * Pointer to rte_eth_dev structure.
8683 * @param[in, out] tag_be24
8684 * Tag value in big endian then R-shift 8.
8685 * @parm[in, out] dev_flow
8686 * Pointer to the dev_flow.
8688 * pointer to error structure.
8691 * 0 on success otherwise -errno and errno is set.
8694 flow_dv_tag_resource_register
8695 (struct rte_eth_dev *dev,
8697 struct mlx5_flow *dev_flow,
8698 struct rte_flow_error *error)
8700 struct mlx5_priv *priv = dev->data->dev_private;
8701 struct mlx5_flow_dv_tag_resource *cache_resource;
8702 struct mlx5_hlist_entry *entry;
8704 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8706 cache_resource = container_of
8707 (entry, struct mlx5_flow_dv_tag_resource, entry);
8708 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8709 dev_flow->dv.tag_resource = cache_resource;
8716 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8717 struct mlx5_hlist_entry *entry)
8719 struct mlx5_dev_ctx_shared *sh = list->ctx;
8720 struct mlx5_flow_dv_tag_resource *tag =
8721 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8723 MLX5_ASSERT(tag && sh && tag->action);
8724 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8725 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8726 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8733 * Pointer to Ethernet device.
8738 * 1 while a reference on it exists, 0 when freed.
8741 flow_dv_tag_release(struct rte_eth_dev *dev,
8744 struct mlx5_priv *priv = dev->data->dev_private;
8745 struct mlx5_flow_dv_tag_resource *tag;
8747 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8750 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8751 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8752 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8756 * Translate port ID action to vport.
8759 * Pointer to rte_eth_dev structure.
8761 * Pointer to the port ID action.
8762 * @param[out] dst_port_id
8763 * The target port ID.
8765 * Pointer to the error structure.
8768 * 0 on success, a negative errno value otherwise and rte_errno is set.
8771 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8772 const struct rte_flow_action *action,
8773 uint32_t *dst_port_id,
8774 struct rte_flow_error *error)
8777 struct mlx5_priv *priv;
8778 const struct rte_flow_action_port_id *conf =
8779 (const struct rte_flow_action_port_id *)action->conf;
8781 port = conf->original ? dev->data->port_id : conf->id;
8782 priv = mlx5_port_to_eswitch_info(port, false);
8784 return rte_flow_error_set(error, -rte_errno,
8785 RTE_FLOW_ERROR_TYPE_ACTION,
8787 "No eswitch info was found for port");
8788 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8790 * This parameter is transferred to
8791 * mlx5dv_dr_action_create_dest_ib_port().
8793 *dst_port_id = priv->dev_port;
8796 * Legacy mode, no LAG configurations is supported.
8797 * This parameter is transferred to
8798 * mlx5dv_dr_action_create_dest_vport().
8800 *dst_port_id = priv->vport_id;
8806 * Create a counter with aging configuration.
8809 * Pointer to rte_eth_dev structure.
8811 * Pointer to the counter action configuration.
8813 * Pointer to the aging action configuration.
8816 * Index to flow counter on success, 0 otherwise.
8819 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8820 struct mlx5_flow *dev_flow,
8821 const struct rte_flow_action_count *count,
8822 const struct rte_flow_action_age *age)
8825 struct mlx5_age_param *age_param;
8827 if (count && count->shared)
8828 counter = flow_dv_counter_get_shared(dev, count->id);
8830 counter = flow_dv_counter_alloc(dev, !!age);
8831 if (!counter || age == NULL)
8833 age_param = flow_dv_counter_idx_get_age(dev, counter);
8834 age_param->context = age->context ? age->context :
8835 (void *)(uintptr_t)(dev_flow->flow_idx);
8836 age_param->timeout = age->timeout;
8837 age_param->port_id = dev->data->port_id;
8838 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8839 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8844 * Add Tx queue matcher
8847 * Pointer to the dev struct.
8848 * @param[in, out] matcher
8850 * @param[in, out] key
8851 * Flow matcher value.
8853 * Flow pattern to translate.
8855 * Item is inner pattern.
8858 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8859 void *matcher, void *key,
8860 const struct rte_flow_item *item)
8862 const struct mlx5_rte_flow_item_tx_queue *queue_m;
8863 const struct mlx5_rte_flow_item_tx_queue *queue_v;
8865 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8867 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8868 struct mlx5_txq_ctrl *txq;
8872 queue_m = (const void *)item->mask;
8875 queue_v = (const void *)item->spec;
8878 txq = mlx5_txq_get(dev, queue_v->queue);
8881 queue = txq->obj->sq->id;
8882 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8883 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8884 queue & queue_m->queue);
8885 mlx5_txq_release(dev, queue_v->queue);
8889 * Set the hash fields according to the @p flow information.
8891 * @param[in] dev_flow
8892 * Pointer to the mlx5_flow.
8893 * @param[in] rss_desc
8894 * Pointer to the mlx5_flow_rss_desc.
8897 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8898 struct mlx5_flow_rss_desc *rss_desc)
8900 uint64_t items = dev_flow->handle->layers;
8902 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8904 dev_flow->hash_fields = 0;
8905 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8906 if (rss_desc->level >= 2) {
8907 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8911 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8912 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8913 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8914 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8915 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8916 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8917 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8919 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8921 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8922 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8923 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8924 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8925 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8926 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8927 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8929 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8932 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8933 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8934 if (rss_types & ETH_RSS_UDP) {
8935 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8936 dev_flow->hash_fields |=
8937 IBV_RX_HASH_SRC_PORT_UDP;
8938 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8939 dev_flow->hash_fields |=
8940 IBV_RX_HASH_DST_PORT_UDP;
8942 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8944 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8945 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8946 if (rss_types & ETH_RSS_TCP) {
8947 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8948 dev_flow->hash_fields |=
8949 IBV_RX_HASH_SRC_PORT_TCP;
8950 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8951 dev_flow->hash_fields |=
8952 IBV_RX_HASH_DST_PORT_TCP;
8954 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8960 * Prepare an Rx Hash queue.
8963 * Pointer to Ethernet device.
8964 * @param[in] dev_flow
8965 * Pointer to the mlx5_flow.
8966 * @param[in] rss_desc
8967 * Pointer to the mlx5_flow_rss_desc.
8968 * @param[out] hrxq_idx
8969 * Hash Rx queue index.
8972 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8974 static struct mlx5_hrxq *
8975 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8976 struct mlx5_flow *dev_flow,
8977 struct mlx5_flow_rss_desc *rss_desc,
8980 struct mlx5_priv *priv = dev->data->dev_private;
8981 struct mlx5_flow_handle *dh = dev_flow->handle;
8982 struct mlx5_hrxq *hrxq;
8984 MLX5_ASSERT(rss_desc->queue_num);
8985 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8986 rss_desc->hash_fields = dev_flow->hash_fields;
8987 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8988 rss_desc->shared_rss = 0;
8989 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8992 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8998 * Release sample sub action resource.
9000 * @param[in, out] dev
9001 * Pointer to rte_eth_dev structure.
9002 * @param[in] act_res
9003 * Pointer to sample sub action resource.
9006 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9007 struct mlx5_flow_sub_actions_idx *act_res)
9009 if (act_res->rix_hrxq) {
9010 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9011 act_res->rix_hrxq = 0;
9013 if (act_res->rix_encap_decap) {
9014 flow_dv_encap_decap_resource_release(dev,
9015 act_res->rix_encap_decap);
9016 act_res->rix_encap_decap = 0;
9018 if (act_res->rix_port_id_action) {
9019 flow_dv_port_id_action_resource_release(dev,
9020 act_res->rix_port_id_action);
9021 act_res->rix_port_id_action = 0;
9023 if (act_res->rix_tag) {
9024 flow_dv_tag_release(dev, act_res->rix_tag);
9025 act_res->rix_tag = 0;
9028 flow_dv_counter_free(dev, act_res->cnt);
9034 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9035 struct mlx5_cache_entry *entry, void *cb_ctx)
9037 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9038 struct rte_eth_dev *dev = ctx->dev;
9039 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9040 struct mlx5_flow_dv_sample_resource *cache_resource =
9041 container_of(entry, typeof(*cache_resource), entry);
9043 if (resource->ratio == cache_resource->ratio &&
9044 resource->ft_type == cache_resource->ft_type &&
9045 resource->ft_id == cache_resource->ft_id &&
9046 resource->set_action == cache_resource->set_action &&
9047 !memcmp((void *)&resource->sample_act,
9048 (void *)&cache_resource->sample_act,
9049 sizeof(struct mlx5_flow_sub_actions_list))) {
9051 * Existing sample action should release the prepared
9052 * sub-actions reference counter.
9054 flow_dv_sample_sub_actions_release(dev,
9055 &resource->sample_idx);
9061 struct mlx5_cache_entry *
9062 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9063 struct mlx5_cache_entry *entry __rte_unused,
9066 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9067 struct rte_eth_dev *dev = ctx->dev;
9068 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9069 void **sample_dv_actions = resource->sub_actions;
9070 struct mlx5_flow_dv_sample_resource *cache_resource;
9071 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9072 struct mlx5_priv *priv = dev->data->dev_private;
9073 struct mlx5_dev_ctx_shared *sh = priv->sh;
9074 struct mlx5_flow_tbl_resource *tbl;
9076 const uint32_t next_ft_step = 1;
9077 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9078 uint8_t is_egress = 0;
9079 uint8_t is_transfer = 0;
9080 struct rte_flow_error *error = ctx->error;
9082 /* Register new sample resource. */
9083 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9084 if (!cache_resource) {
9085 rte_flow_error_set(error, ENOMEM,
9086 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9088 "cannot allocate resource memory");
9091 *cache_resource = *resource;
9092 /* Create normal path table level */
9093 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9095 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9097 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9098 is_egress, is_transfer,
9099 true, NULL, 0, 0, error);
9101 rte_flow_error_set(error, ENOMEM,
9102 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9104 "fail to create normal path table "
9110 cache_resource->normal_path_tbl = tbl;
9111 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9112 ret = mlx5_flow_os_create_flow_action_default_miss
9113 (&cache_resource->default_miss);
9115 rte_flow_error_set(error, ENOMEM,
9116 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9118 "cannot create default miss "
9122 sample_dv_actions[resource->sample_act.actions_num++] =
9123 cache_resource->default_miss;
9125 /* Create a DR sample action */
9126 sampler_attr.sample_ratio = cache_resource->ratio;
9127 sampler_attr.default_next_table = tbl->obj;
9128 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9129 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9130 &sample_dv_actions[0];
9131 sampler_attr.action = cache_resource->set_action;
9132 if (mlx5_os_flow_dr_create_flow_action_sampler
9133 (&sampler_attr, &cache_resource->verbs_action)) {
9134 rte_flow_error_set(error, ENOMEM,
9135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9136 NULL, "cannot create sample action");
9139 cache_resource->idx = idx;
9140 cache_resource->dev = dev;
9141 return &cache_resource->entry;
9143 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9144 cache_resource->default_miss)
9145 claim_zero(mlx5_flow_os_destroy_flow_action
9146 (cache_resource->default_miss));
9148 flow_dv_sample_sub_actions_release(dev,
9149 &cache_resource->sample_idx);
9150 if (cache_resource->normal_path_tbl)
9151 flow_dv_tbl_resource_release(MLX5_SH(dev),
9152 cache_resource->normal_path_tbl);
9153 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9159 * Find existing sample resource or create and register a new one.
9161 * @param[in, out] dev
9162 * Pointer to rte_eth_dev structure.
9163 * @param[in] resource
9164 * Pointer to sample resource.
9165 * @parm[in, out] dev_flow
9166 * Pointer to the dev_flow.
9168 * pointer to error structure.
9171 * 0 on success otherwise -errno and errno is set.
9174 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9175 struct mlx5_flow_dv_sample_resource *resource,
9176 struct mlx5_flow *dev_flow,
9177 struct rte_flow_error *error)
9179 struct mlx5_flow_dv_sample_resource *cache_resource;
9180 struct mlx5_cache_entry *entry;
9181 struct mlx5_priv *priv = dev->data->dev_private;
9182 struct mlx5_flow_cb_ctx ctx = {
9188 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9191 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9192 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9193 dev_flow->dv.sample_res = cache_resource;
9198 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9199 struct mlx5_cache_entry *entry, void *cb_ctx)
9201 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9202 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9203 struct rte_eth_dev *dev = ctx->dev;
9204 struct mlx5_flow_dv_dest_array_resource *cache_resource =
9205 container_of(entry, typeof(*cache_resource), entry);
9208 if (resource->num_of_dest == cache_resource->num_of_dest &&
9209 resource->ft_type == cache_resource->ft_type &&
9210 !memcmp((void *)cache_resource->sample_act,
9211 (void *)resource->sample_act,
9212 (resource->num_of_dest *
9213 sizeof(struct mlx5_flow_sub_actions_list)))) {
9215 * Existing sample action should release the prepared
9216 * sub-actions reference counter.
9218 for (idx = 0; idx < resource->num_of_dest; idx++)
9219 flow_dv_sample_sub_actions_release(dev,
9220 &resource->sample_idx[idx]);
9226 struct mlx5_cache_entry *
9227 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9228 struct mlx5_cache_entry *entry __rte_unused,
9231 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9232 struct rte_eth_dev *dev = ctx->dev;
9233 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9234 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9235 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9236 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9237 struct mlx5_priv *priv = dev->data->dev_private;
9238 struct mlx5_dev_ctx_shared *sh = priv->sh;
9239 struct mlx5_flow_sub_actions_list *sample_act;
9240 struct mlx5dv_dr_domain *domain;
9241 uint32_t idx = 0, res_idx = 0;
9242 struct rte_flow_error *error = ctx->error;
9245 /* Register new destination array resource. */
9246 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9248 if (!cache_resource) {
9249 rte_flow_error_set(error, ENOMEM,
9250 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9252 "cannot allocate resource memory");
9255 *cache_resource = *resource;
9256 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9257 domain = sh->fdb_domain;
9258 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9259 domain = sh->rx_domain;
9261 domain = sh->tx_domain;
9262 for (idx = 0; idx < resource->num_of_dest; idx++) {
9263 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9264 mlx5_malloc(MLX5_MEM_ZERO,
9265 sizeof(struct mlx5dv_dr_action_dest_attr),
9267 if (!dest_attr[idx]) {
9268 rte_flow_error_set(error, ENOMEM,
9269 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9271 "cannot allocate resource memory");
9274 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9275 sample_act = &resource->sample_act[idx];
9276 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
9277 dest_attr[idx]->dest = sample_act->dr_queue_action;
9278 } else if (sample_act->action_flags ==
9279 (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
9280 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9281 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9282 dest_attr[idx]->dest_reformat->reformat =
9283 sample_act->dr_encap_action;
9284 dest_attr[idx]->dest_reformat->dest =
9285 sample_act->dr_port_id_action;
9286 } else if (sample_act->action_flags ==
9287 MLX5_FLOW_ACTION_PORT_ID) {
9288 dest_attr[idx]->dest = sample_act->dr_port_id_action;
9291 /* create a dest array actioin */
9292 ret = mlx5_os_flow_dr_create_flow_action_dest_array
9294 cache_resource->num_of_dest,
9296 &cache_resource->action);
9298 rte_flow_error_set(error, ENOMEM,
9299 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9301 "cannot create destination array action");
9304 cache_resource->idx = res_idx;
9305 cache_resource->dev = dev;
9306 for (idx = 0; idx < resource->num_of_dest; idx++)
9307 mlx5_free(dest_attr[idx]);
9308 return &cache_resource->entry;
9310 for (idx = 0; idx < resource->num_of_dest; idx++) {
9311 struct mlx5_flow_sub_actions_idx *act_res =
9312 &cache_resource->sample_idx[idx];
9313 if (act_res->rix_hrxq &&
9314 !mlx5_hrxq_release(dev,
9316 act_res->rix_hrxq = 0;
9317 if (act_res->rix_encap_decap &&
9318 !flow_dv_encap_decap_resource_release(dev,
9319 act_res->rix_encap_decap))
9320 act_res->rix_encap_decap = 0;
9321 if (act_res->rix_port_id_action &&
9322 !flow_dv_port_id_action_resource_release(dev,
9323 act_res->rix_port_id_action))
9324 act_res->rix_port_id_action = 0;
9326 mlx5_free(dest_attr[idx]);
9329 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9334 * Find existing destination array resource or create and register a new one.
9336 * @param[in, out] dev
9337 * Pointer to rte_eth_dev structure.
9338 * @param[in] resource
9339 * Pointer to destination array resource.
9340 * @parm[in, out] dev_flow
9341 * Pointer to the dev_flow.
9343 * pointer to error structure.
9346 * 0 on success otherwise -errno and errno is set.
9349 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9350 struct mlx5_flow_dv_dest_array_resource *resource,
9351 struct mlx5_flow *dev_flow,
9352 struct rte_flow_error *error)
9354 struct mlx5_flow_dv_dest_array_resource *cache_resource;
9355 struct mlx5_priv *priv = dev->data->dev_private;
9356 struct mlx5_cache_entry *entry;
9357 struct mlx5_flow_cb_ctx ctx = {
9363 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9366 cache_resource = container_of(entry, typeof(*cache_resource), entry);
9367 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9368 dev_flow->dv.dest_array_res = cache_resource;
9373 * Convert Sample action to DV specification.
9376 * Pointer to rte_eth_dev structure.
9378 * Pointer to action structure.
9379 * @param[in, out] dev_flow
9380 * Pointer to the mlx5_flow.
9382 * Pointer to the flow attributes.
9383 * @param[in, out] num_of_dest
9384 * Pointer to the num of destination.
9385 * @param[in, out] sample_actions
9386 * Pointer to sample actions list.
9387 * @param[in, out] res
9388 * Pointer to sample resource.
9390 * Pointer to the error structure.
9393 * 0 on success, a negative errno value otherwise and rte_errno is set.
9396 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9397 const struct rte_flow_action *action,
9398 struct mlx5_flow *dev_flow,
9399 const struct rte_flow_attr *attr,
9400 uint32_t *num_of_dest,
9401 void **sample_actions,
9402 struct mlx5_flow_dv_sample_resource *res,
9403 struct rte_flow_error *error)
9405 struct mlx5_priv *priv = dev->data->dev_private;
9406 const struct rte_flow_action_sample *sample_action;
9407 const struct rte_flow_action *sub_actions;
9408 const struct rte_flow_action_queue *queue;
9409 struct mlx5_flow_sub_actions_list *sample_act;
9410 struct mlx5_flow_sub_actions_idx *sample_idx;
9411 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9412 struct mlx5_flow_rss_desc *rss_desc;
9413 uint64_t action_flags = 0;
9416 rss_desc = &wks->rss_desc;
9417 sample_act = &res->sample_act;
9418 sample_idx = &res->sample_idx;
9419 sample_action = (const struct rte_flow_action_sample *)action->conf;
9420 res->ratio = sample_action->ratio;
9421 sub_actions = sample_action->actions;
9422 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9423 int type = sub_actions->type;
9424 uint32_t pre_rix = 0;
9427 case RTE_FLOW_ACTION_TYPE_QUEUE:
9429 struct mlx5_hrxq *hrxq;
9432 queue = sub_actions->conf;
9433 rss_desc->queue_num = 1;
9434 rss_desc->queue[0] = queue->index;
9435 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9436 rss_desc, &hrxq_idx);
9438 return rte_flow_error_set
9440 RTE_FLOW_ERROR_TYPE_ACTION,
9442 "cannot create fate queue");
9443 sample_act->dr_queue_action = hrxq->action;
9444 sample_idx->rix_hrxq = hrxq_idx;
9445 sample_actions[sample_act->actions_num++] =
9448 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9449 if (action_flags & MLX5_FLOW_ACTION_MARK)
9450 dev_flow->handle->rix_hrxq = hrxq_idx;
9451 dev_flow->handle->fate_action =
9452 MLX5_FLOW_FATE_QUEUE;
9455 case RTE_FLOW_ACTION_TYPE_MARK:
9457 uint32_t tag_be = mlx5_flow_mark_set
9458 (((const struct rte_flow_action_mark *)
9459 (sub_actions->conf))->id);
9461 dev_flow->handle->mark = 1;
9462 pre_rix = dev_flow->handle->dvh.rix_tag;
9463 /* Save the mark resource before sample */
9464 pre_r = dev_flow->dv.tag_resource;
9465 if (flow_dv_tag_resource_register(dev, tag_be,
9468 MLX5_ASSERT(dev_flow->dv.tag_resource);
9469 sample_act->dr_tag_action =
9470 dev_flow->dv.tag_resource->action;
9471 sample_idx->rix_tag =
9472 dev_flow->handle->dvh.rix_tag;
9473 sample_actions[sample_act->actions_num++] =
9474 sample_act->dr_tag_action;
9475 /* Recover the mark resource after sample */
9476 dev_flow->dv.tag_resource = pre_r;
9477 dev_flow->handle->dvh.rix_tag = pre_rix;
9478 action_flags |= MLX5_FLOW_ACTION_MARK;
9481 case RTE_FLOW_ACTION_TYPE_COUNT:
9485 counter = flow_dv_translate_create_counter(dev,
9486 dev_flow, sub_actions->conf, 0);
9488 return rte_flow_error_set
9490 RTE_FLOW_ERROR_TYPE_ACTION,
9492 "cannot create counter"
9494 sample_idx->cnt = counter;
9495 sample_act->dr_cnt_action =
9496 (flow_dv_counter_get_by_idx(dev,
9497 counter, NULL))->action;
9498 sample_actions[sample_act->actions_num++] =
9499 sample_act->dr_cnt_action;
9500 action_flags |= MLX5_FLOW_ACTION_COUNT;
9503 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9505 struct mlx5_flow_dv_port_id_action_resource
9507 uint32_t port_id = 0;
9509 memset(&port_id_resource, 0, sizeof(port_id_resource));
9510 /* Save the port id resource before sample */
9511 pre_rix = dev_flow->handle->rix_port_id_action;
9512 pre_r = dev_flow->dv.port_id_action;
9513 if (flow_dv_translate_action_port_id(dev, sub_actions,
9516 port_id_resource.port_id = port_id;
9517 if (flow_dv_port_id_action_resource_register
9518 (dev, &port_id_resource, dev_flow, error))
9520 sample_act->dr_port_id_action =
9521 dev_flow->dv.port_id_action->action;
9522 sample_idx->rix_port_id_action =
9523 dev_flow->handle->rix_port_id_action;
9524 sample_actions[sample_act->actions_num++] =
9525 sample_act->dr_port_id_action;
9526 /* Recover the port id resource after sample */
9527 dev_flow->dv.port_id_action = pre_r;
9528 dev_flow->handle->rix_port_id_action = pre_rix;
9530 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9533 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9534 /* Save the encap resource before sample */
9535 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9536 pre_r = dev_flow->dv.encap_decap;
9537 if (flow_dv_create_action_l2_encap(dev, sub_actions,
9542 sample_act->dr_encap_action =
9543 dev_flow->dv.encap_decap->action;
9544 sample_idx->rix_encap_decap =
9545 dev_flow->handle->dvh.rix_encap_decap;
9546 sample_actions[sample_act->actions_num++] =
9547 sample_act->dr_encap_action;
9548 /* Recover the encap resource after sample */
9549 dev_flow->dv.encap_decap = pre_r;
9550 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9551 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9554 return rte_flow_error_set(error, EINVAL,
9555 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9557 "Not support for sampler action");
9560 sample_act->action_flags = action_flags;
9561 res->ft_id = dev_flow->dv.group;
9562 if (attr->transfer) {
9564 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9565 uint64_t set_action;
9566 } action_ctx = { .set_action = 0 };
9568 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9569 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9570 MLX5_MODIFICATION_TYPE_SET);
9571 MLX5_SET(set_action_in, action_ctx.action_in, field,
9572 MLX5_MODI_META_REG_C_0);
9573 MLX5_SET(set_action_in, action_ctx.action_in, data,
9574 priv->vport_meta_tag);
9575 res->set_action = action_ctx.set_action;
9576 } else if (attr->ingress) {
9577 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9579 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9585 * Convert Sample action to DV specification.
9588 * Pointer to rte_eth_dev structure.
9589 * @param[in, out] dev_flow
9590 * Pointer to the mlx5_flow.
9591 * @param[in] num_of_dest
9592 * The num of destination.
9593 * @param[in, out] res
9594 * Pointer to sample resource.
9595 * @param[in, out] mdest_res
9596 * Pointer to destination array resource.
9597 * @param[in] sample_actions
9598 * Pointer to sample path actions list.
9599 * @param[in] action_flags
9600 * Holds the actions detected until now.
9602 * Pointer to the error structure.
9605 * 0 on success, a negative errno value otherwise and rte_errno is set.
9608 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9609 struct mlx5_flow *dev_flow,
9610 uint32_t num_of_dest,
9611 struct mlx5_flow_dv_sample_resource *res,
9612 struct mlx5_flow_dv_dest_array_resource *mdest_res,
9613 void **sample_actions,
9614 uint64_t action_flags,
9615 struct rte_flow_error *error)
9617 /* update normal path action resource into last index of array */
9618 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9619 struct mlx5_flow_sub_actions_list *sample_act =
9620 &mdest_res->sample_act[dest_index];
9621 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9622 struct mlx5_flow_rss_desc *rss_desc;
9623 uint32_t normal_idx = 0;
9624 struct mlx5_hrxq *hrxq;
9628 rss_desc = &wks->rss_desc;
9629 if (num_of_dest > 1) {
9630 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9631 /* Handle QP action for mirroring */
9632 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9633 rss_desc, &hrxq_idx);
9635 return rte_flow_error_set
9637 RTE_FLOW_ERROR_TYPE_ACTION,
9639 "cannot create rx queue");
9641 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9642 sample_act->dr_queue_action = hrxq->action;
9643 if (action_flags & MLX5_FLOW_ACTION_MARK)
9644 dev_flow->handle->rix_hrxq = hrxq_idx;
9645 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9647 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9649 mdest_res->sample_idx[dest_index].rix_encap_decap =
9650 dev_flow->handle->dvh.rix_encap_decap;
9651 sample_act->dr_encap_action =
9652 dev_flow->dv.encap_decap->action;
9654 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9656 mdest_res->sample_idx[dest_index].rix_port_id_action =
9657 dev_flow->handle->rix_port_id_action;
9658 sample_act->dr_port_id_action =
9659 dev_flow->dv.port_id_action->action;
9661 sample_act->actions_num = normal_idx;
9662 /* update sample action resource into first index of array */
9663 mdest_res->ft_type = res->ft_type;
9664 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9665 sizeof(struct mlx5_flow_sub_actions_idx));
9666 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9667 sizeof(struct mlx5_flow_sub_actions_list));
9668 mdest_res->num_of_dest = num_of_dest;
9669 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9671 return rte_flow_error_set(error, EINVAL,
9672 RTE_FLOW_ERROR_TYPE_ACTION,
9673 NULL, "can't create sample "
9676 res->sub_actions = sample_actions;
9677 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9678 return rte_flow_error_set(error, EINVAL,
9679 RTE_FLOW_ERROR_TYPE_ACTION,
9681 "can't create sample action");
9687 * Remove an ASO age action from age actions list.
9690 * Pointer to the Ethernet device structure.
9692 * Pointer to the aso age action handler.
9695 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9696 struct mlx5_aso_age_action *age)
9698 struct mlx5_age_info *age_info;
9699 struct mlx5_age_param *age_param = &age->age_params;
9700 struct mlx5_priv *priv = dev->data->dev_private;
9701 uint16_t expected = AGE_CANDIDATE;
9703 age_info = GET_PORT_AGE_INFO(priv);
9704 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9705 AGE_FREE, false, __ATOMIC_RELAXED,
9706 __ATOMIC_RELAXED)) {
9708 * We need the lock even it is age timeout,
9709 * since age action may still in process.
9711 rte_spinlock_lock(&age_info->aged_sl);
9712 LIST_REMOVE(age, next);
9713 rte_spinlock_unlock(&age_info->aged_sl);
9714 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9719 * Release an ASO age action.
9722 * Pointer to the Ethernet device structure.
9723 * @param[in] age_idx
9724 * Index of ASO age action to release.
9726 * True if the release operation is during flow destroy operation.
9727 * False if the release operation is during action destroy operation.
9730 * 0 when age action was removed, otherwise the number of references.
9733 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9735 struct mlx5_priv *priv = dev->data->dev_private;
9736 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9737 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9738 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9741 flow_dv_aso_age_remove_from_age(dev, age);
9742 rte_spinlock_lock(&mng->free_sl);
9743 LIST_INSERT_HEAD(&mng->free, age, next);
9744 rte_spinlock_unlock(&mng->free_sl);
9750 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9753 * Pointer to the Ethernet device structure.
9756 * 0 on success, otherwise negative errno value and rte_errno is set.
9759 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9761 struct mlx5_priv *priv = dev->data->dev_private;
9762 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9763 void *old_pools = mng->pools;
9764 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9765 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9766 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9773 memcpy(pools, old_pools,
9774 mng->n * sizeof(struct mlx5_flow_counter_pool *));
9775 mlx5_free(old_pools);
9777 /* First ASO flow hit allocation - starting ASO data-path. */
9778 int ret = mlx5_aso_queue_start(priv->sh);
9791 * Create and initialize a new ASO aging pool.
9794 * Pointer to the Ethernet device structure.
9795 * @param[out] age_free
9796 * Where to put the pointer of a new age action.
9799 * The age actions pool pointer and @p age_free is set on success,
9800 * NULL otherwise and rte_errno is set.
9802 static struct mlx5_aso_age_pool *
9803 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9804 struct mlx5_aso_age_action **age_free)
9806 struct mlx5_priv *priv = dev->data->dev_private;
9807 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9808 struct mlx5_aso_age_pool *pool = NULL;
9809 struct mlx5_devx_obj *obj = NULL;
9812 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9815 rte_errno = ENODATA;
9816 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9819 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9821 claim_zero(mlx5_devx_cmd_destroy(obj));
9825 pool->flow_hit_aso_obj = obj;
9826 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9827 rte_spinlock_lock(&mng->resize_sl);
9828 pool->index = mng->next;
9829 /* Resize pools array if there is no room for the new pool in it. */
9830 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9831 claim_zero(mlx5_devx_cmd_destroy(obj));
9833 rte_spinlock_unlock(&mng->resize_sl);
9836 mng->pools[pool->index] = pool;
9838 rte_spinlock_unlock(&mng->resize_sl);
9839 /* Assign the first action in the new pool, the rest go to free list. */
9840 *age_free = &pool->actions[0];
9841 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9842 pool->actions[i].offset = i;
9843 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9849 * Allocate a ASO aging bit.
9852 * Pointer to the Ethernet device structure.
9854 * Pointer to the error structure.
9857 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
9860 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9862 struct mlx5_priv *priv = dev->data->dev_private;
9863 const struct mlx5_aso_age_pool *pool;
9864 struct mlx5_aso_age_action *age_free = NULL;
9865 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9868 /* Try to get the next free age action bit. */
9869 rte_spinlock_lock(&mng->free_sl);
9870 age_free = LIST_FIRST(&mng->free);
9872 LIST_REMOVE(age_free, next);
9873 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9874 rte_spinlock_unlock(&mng->free_sl);
9875 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9876 NULL, "failed to create ASO age pool");
9877 return 0; /* 0 is an error. */
9879 rte_spinlock_unlock(&mng->free_sl);
9881 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9882 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9884 if (!age_free->dr_action) {
9885 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9889 rte_flow_error_set(error, rte_errno,
9890 RTE_FLOW_ERROR_TYPE_ACTION,
9891 NULL, "failed to get reg_c "
9892 "for ASO flow hit");
9893 return 0; /* 0 is an error. */
9895 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9896 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9897 (priv->sh->rx_domain,
9898 pool->flow_hit_aso_obj->obj, age_free->offset,
9899 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9901 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9902 if (!age_free->dr_action) {
9904 rte_spinlock_lock(&mng->free_sl);
9905 LIST_INSERT_HEAD(&mng->free, age_free, next);
9906 rte_spinlock_unlock(&mng->free_sl);
9907 rte_flow_error_set(error, rte_errno,
9908 RTE_FLOW_ERROR_TYPE_ACTION,
9909 NULL, "failed to create ASO "
9911 return 0; /* 0 is an error. */
9914 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9915 return pool->index | ((age_free->offset + 1) << 16);
9919 * Create a age action using ASO mechanism.
9922 * Pointer to rte_eth_dev structure.
9924 * Pointer to the aging action configuration.
9926 * Pointer to the error structure.
9929 * Index to flow counter on success, 0 otherwise.
9932 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9933 const struct rte_flow_action_age *age,
9934 struct rte_flow_error *error)
9936 uint32_t age_idx = 0;
9937 struct mlx5_aso_age_action *aso_age;
9939 age_idx = flow_dv_aso_age_alloc(dev, error);
9942 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9943 aso_age->age_params.context = age->context;
9944 aso_age->age_params.timeout = age->timeout;
9945 aso_age->age_params.port_id = dev->data->port_id;
9946 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9948 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9954 * Fill the flow with DV spec, lock free
9955 * (mutex should be acquired by caller).
9958 * Pointer to rte_eth_dev structure.
9959 * @param[in, out] dev_flow
9960 * Pointer to the sub flow.
9962 * Pointer to the flow attributes.
9964 * Pointer to the list of items.
9965 * @param[in] actions
9966 * Pointer to the list of actions.
9968 * Pointer to the error structure.
9971 * 0 on success, a negative errno value otherwise and rte_errno is set.
9974 flow_dv_translate(struct rte_eth_dev *dev,
9975 struct mlx5_flow *dev_flow,
9976 const struct rte_flow_attr *attr,
9977 const struct rte_flow_item items[],
9978 const struct rte_flow_action actions[],
9979 struct rte_flow_error *error)
9981 struct mlx5_priv *priv = dev->data->dev_private;
9982 struct mlx5_dev_config *dev_conf = &priv->config;
9983 struct rte_flow *flow = dev_flow->flow;
9984 struct mlx5_flow_handle *handle = dev_flow->handle;
9985 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9986 struct mlx5_flow_rss_desc *rss_desc;
9987 uint64_t item_flags = 0;
9988 uint64_t last_item = 0;
9989 uint64_t action_flags = 0;
9990 uint64_t priority = attr->priority;
9991 struct mlx5_flow_dv_matcher matcher = {
9993 .size = sizeof(matcher.mask.buf) -
9994 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9998 bool actions_end = false;
10000 struct mlx5_flow_dv_modify_hdr_resource res;
10001 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10002 sizeof(struct mlx5_modification_cmd) *
10003 (MLX5_MAX_MODIFY_NUM + 1)];
10005 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10006 const struct rte_flow_action_count *count = NULL;
10007 const struct rte_flow_action_age *age = NULL;
10008 union flow_dv_attr flow_attr = { .attr = 0 };
10010 union mlx5_flow_tbl_key tbl_key;
10011 uint32_t modify_action_position = UINT32_MAX;
10012 void *match_mask = matcher.mask.buf;
10013 void *match_value = dev_flow->dv.value.buf;
10014 uint8_t next_protocol = 0xff;
10015 struct rte_vlan_hdr vlan = { 0 };
10016 struct mlx5_flow_dv_dest_array_resource mdest_res;
10017 struct mlx5_flow_dv_sample_resource sample_res;
10018 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10019 struct mlx5_flow_sub_actions_list *sample_act;
10020 uint32_t sample_act_pos = UINT32_MAX;
10021 uint32_t num_of_dest = 0;
10022 int tmp_actions_n = 0;
10025 const struct mlx5_flow_tunnel *tunnel;
10026 struct flow_grp_info grp_info = {
10027 .external = !!dev_flow->external,
10028 .transfer = !!attr->transfer,
10029 .fdb_def_rule = !!priv->fdb_def_rule,
10030 .skip_scale = !!dev_flow->skip_scale,
10034 return rte_flow_error_set(error, ENOMEM,
10035 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10037 "failed to push flow workspace");
10038 rss_desc = &wks->rss_desc;
10039 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10040 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10041 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10042 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10043 /* update normal path action resource into last index of array */
10044 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10045 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10046 flow_items_to_tunnel(items) :
10047 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10048 flow_actions_to_tunnel(actions) :
10049 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10050 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10051 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10052 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10053 (dev, tunnel, attr, items, actions);
10054 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10058 dev_flow->dv.group = table;
10059 if (attr->transfer)
10060 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10061 if (priority == MLX5_FLOW_PRIO_RSVD)
10062 priority = dev_conf->flow_prio - 1;
10063 /* number of actions must be set to 0 in case of dirty stack. */
10064 mhdr_res->actions_num = 0;
10065 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10067 * do not add decap action if match rule drops packet
10068 * HW rejects rules with decap & drop
10070 * if tunnel match rule was inserted before matching tunnel set
10071 * rule flow table used in the match rule must be registered.
10072 * current implementation handles that in the
10073 * flow_dv_match_register() at the function end.
10075 bool add_decap = true;
10076 const struct rte_flow_action *ptr = actions;
10078 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10079 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10085 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10089 dev_flow->dv.actions[actions_n++] =
10090 dev_flow->dv.encap_decap->action;
10091 action_flags |= MLX5_FLOW_ACTION_DECAP;
10094 for (; !actions_end ; actions++) {
10095 const struct rte_flow_action_queue *queue;
10096 const struct rte_flow_action_rss *rss;
10097 const struct rte_flow_action *action = actions;
10098 const uint8_t *rss_key;
10099 const struct rte_flow_action_meter *mtr;
10100 struct mlx5_flow_tbl_resource *tbl;
10101 struct mlx5_aso_age_action *age_act;
10102 uint32_t port_id = 0;
10103 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10104 int action_type = actions->type;
10105 const struct rte_flow_action *found_action = NULL;
10106 struct mlx5_flow_meter *fm = NULL;
10107 uint32_t jump_group = 0;
10109 if (!mlx5_flow_os_action_supported(action_type))
10110 return rte_flow_error_set(error, ENOTSUP,
10111 RTE_FLOW_ERROR_TYPE_ACTION,
10113 "action not supported");
10114 switch (action_type) {
10115 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10116 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10118 case RTE_FLOW_ACTION_TYPE_VOID:
10120 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10121 if (flow_dv_translate_action_port_id(dev, action,
10124 port_id_resource.port_id = port_id;
10125 MLX5_ASSERT(!handle->rix_port_id_action);
10126 if (flow_dv_port_id_action_resource_register
10127 (dev, &port_id_resource, dev_flow, error))
10129 dev_flow->dv.actions[actions_n++] =
10130 dev_flow->dv.port_id_action->action;
10131 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10132 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10133 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10136 case RTE_FLOW_ACTION_TYPE_FLAG:
10137 action_flags |= MLX5_FLOW_ACTION_FLAG;
10138 dev_flow->handle->mark = 1;
10139 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10140 struct rte_flow_action_mark mark = {
10141 .id = MLX5_FLOW_MARK_DEFAULT,
10144 if (flow_dv_convert_action_mark(dev, &mark,
10148 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10151 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10153 * Only one FLAG or MARK is supported per device flow
10154 * right now. So the pointer to the tag resource must be
10155 * zero before the register process.
10157 MLX5_ASSERT(!handle->dvh.rix_tag);
10158 if (flow_dv_tag_resource_register(dev, tag_be,
10161 MLX5_ASSERT(dev_flow->dv.tag_resource);
10162 dev_flow->dv.actions[actions_n++] =
10163 dev_flow->dv.tag_resource->action;
10165 case RTE_FLOW_ACTION_TYPE_MARK:
10166 action_flags |= MLX5_FLOW_ACTION_MARK;
10167 dev_flow->handle->mark = 1;
10168 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10169 const struct rte_flow_action_mark *mark =
10170 (const struct rte_flow_action_mark *)
10173 if (flow_dv_convert_action_mark(dev, mark,
10177 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10181 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10182 /* Legacy (non-extensive) MARK action. */
10183 tag_be = mlx5_flow_mark_set
10184 (((const struct rte_flow_action_mark *)
10185 (actions->conf))->id);
10186 MLX5_ASSERT(!handle->dvh.rix_tag);
10187 if (flow_dv_tag_resource_register(dev, tag_be,
10190 MLX5_ASSERT(dev_flow->dv.tag_resource);
10191 dev_flow->dv.actions[actions_n++] =
10192 dev_flow->dv.tag_resource->action;
10194 case RTE_FLOW_ACTION_TYPE_SET_META:
10195 if (flow_dv_convert_action_set_meta
10196 (dev, mhdr_res, attr,
10197 (const struct rte_flow_action_set_meta *)
10198 actions->conf, error))
10200 action_flags |= MLX5_FLOW_ACTION_SET_META;
10202 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10203 if (flow_dv_convert_action_set_tag
10205 (const struct rte_flow_action_set_tag *)
10206 actions->conf, error))
10208 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10210 case RTE_FLOW_ACTION_TYPE_DROP:
10211 action_flags |= MLX5_FLOW_ACTION_DROP;
10212 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10214 case RTE_FLOW_ACTION_TYPE_QUEUE:
10215 queue = actions->conf;
10216 rss_desc->queue_num = 1;
10217 rss_desc->queue[0] = queue->index;
10218 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10219 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10220 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10223 case RTE_FLOW_ACTION_TYPE_RSS:
10224 rss = actions->conf;
10225 memcpy(rss_desc->queue, rss->queue,
10226 rss->queue_num * sizeof(uint16_t));
10227 rss_desc->queue_num = rss->queue_num;
10228 /* NULL RSS key indicates default RSS key. */
10229 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10230 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10232 * rss->level and rss.types should be set in advance
10233 * when expanding items for RSS.
10235 action_flags |= MLX5_FLOW_ACTION_RSS;
10236 dev_flow->handle->fate_action = rss_desc->shared_rss ?
10237 MLX5_FLOW_FATE_SHARED_RSS :
10238 MLX5_FLOW_FATE_QUEUE;
10240 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10241 flow->age = (uint32_t)(uintptr_t)(action->conf);
10242 age_act = flow_aso_age_get_by_idx(dev, flow->age);
10243 __atomic_fetch_add(&age_act->refcnt, 1,
10245 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10246 action_flags |= MLX5_FLOW_ACTION_AGE;
10248 case RTE_FLOW_ACTION_TYPE_AGE:
10249 if (priv->sh->flow_hit_aso_en && attr->group) {
10250 flow->age = flow_dv_translate_create_aso_age
10251 (dev, action->conf, error);
10253 return rte_flow_error_set
10255 RTE_FLOW_ERROR_TYPE_ACTION,
10257 "can't create ASO age action");
10258 dev_flow->dv.actions[actions_n++] =
10259 (flow_aso_age_get_by_idx
10260 (dev, flow->age))->dr_action;
10261 action_flags |= MLX5_FLOW_ACTION_AGE;
10265 case RTE_FLOW_ACTION_TYPE_COUNT:
10266 if (!dev_conf->devx) {
10267 return rte_flow_error_set
10269 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10271 "count action not supported");
10273 /* Save information first, will apply later. */
10274 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10275 count = action->conf;
10277 age = action->conf;
10278 action_flags |= MLX5_FLOW_ACTION_COUNT;
10280 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10281 dev_flow->dv.actions[actions_n++] =
10282 priv->sh->pop_vlan_action;
10283 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10285 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10286 if (!(action_flags &
10287 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10288 flow_dev_get_vlan_info_from_items(items, &vlan);
10289 vlan.eth_proto = rte_be_to_cpu_16
10290 ((((const struct rte_flow_action_of_push_vlan *)
10291 actions->conf)->ethertype));
10292 found_action = mlx5_flow_find_action
10294 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10296 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10297 found_action = mlx5_flow_find_action
10299 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10301 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10302 if (flow_dv_create_action_push_vlan
10303 (dev, attr, &vlan, dev_flow, error))
10305 dev_flow->dv.actions[actions_n++] =
10306 dev_flow->dv.push_vlan_res->action;
10307 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10309 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10310 /* of_vlan_push action handled this action */
10311 MLX5_ASSERT(action_flags &
10312 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10314 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10315 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10317 flow_dev_get_vlan_info_from_items(items, &vlan);
10318 mlx5_update_vlan_vid_pcp(actions, &vlan);
10319 /* If no VLAN push - this is a modify header action */
10320 if (flow_dv_convert_action_modify_vlan_vid
10321 (mhdr_res, actions, error))
10323 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10325 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10326 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10327 if (flow_dv_create_action_l2_encap(dev, actions,
10332 dev_flow->dv.actions[actions_n++] =
10333 dev_flow->dv.encap_decap->action;
10334 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10335 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10336 sample_act->action_flags |=
10337 MLX5_FLOW_ACTION_ENCAP;
10339 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10340 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10341 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10345 dev_flow->dv.actions[actions_n++] =
10346 dev_flow->dv.encap_decap->action;
10347 action_flags |= MLX5_FLOW_ACTION_DECAP;
10349 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10350 /* Handle encap with preceding decap. */
10351 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10352 if (flow_dv_create_action_raw_encap
10353 (dev, actions, dev_flow, attr, error))
10355 dev_flow->dv.actions[actions_n++] =
10356 dev_flow->dv.encap_decap->action;
10358 /* Handle encap without preceding decap. */
10359 if (flow_dv_create_action_l2_encap
10360 (dev, actions, dev_flow, attr->transfer,
10363 dev_flow->dv.actions[actions_n++] =
10364 dev_flow->dv.encap_decap->action;
10366 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10367 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10368 sample_act->action_flags |=
10369 MLX5_FLOW_ACTION_ENCAP;
10371 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10372 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10374 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10375 if (flow_dv_create_action_l2_decap
10376 (dev, dev_flow, attr->transfer, error))
10378 dev_flow->dv.actions[actions_n++] =
10379 dev_flow->dv.encap_decap->action;
10381 /* If decap is followed by encap, handle it at encap. */
10382 action_flags |= MLX5_FLOW_ACTION_DECAP;
10384 case RTE_FLOW_ACTION_TYPE_JUMP:
10385 jump_group = ((const struct rte_flow_action_jump *)
10386 action->conf)->group;
10387 grp_info.std_tbl_fix = 0;
10388 grp_info.skip_scale = 0;
10389 ret = mlx5_flow_group_to_table(dev, tunnel,
10395 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10397 !!dev_flow->external,
10398 tunnel, jump_group, 0,
10401 return rte_flow_error_set
10403 RTE_FLOW_ERROR_TYPE_ACTION,
10405 "cannot create jump action.");
10406 if (flow_dv_jump_tbl_resource_register
10407 (dev, tbl, dev_flow, error)) {
10408 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10409 return rte_flow_error_set
10411 RTE_FLOW_ERROR_TYPE_ACTION,
10413 "cannot create jump action.");
10415 dev_flow->dv.actions[actions_n++] =
10416 dev_flow->dv.jump->action;
10417 action_flags |= MLX5_FLOW_ACTION_JUMP;
10418 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10420 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10421 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10422 if (flow_dv_convert_action_modify_mac
10423 (mhdr_res, actions, error))
10425 action_flags |= actions->type ==
10426 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10427 MLX5_FLOW_ACTION_SET_MAC_SRC :
10428 MLX5_FLOW_ACTION_SET_MAC_DST;
10430 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10431 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10432 if (flow_dv_convert_action_modify_ipv4
10433 (mhdr_res, actions, error))
10435 action_flags |= actions->type ==
10436 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10437 MLX5_FLOW_ACTION_SET_IPV4_SRC :
10438 MLX5_FLOW_ACTION_SET_IPV4_DST;
10440 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10441 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10442 if (flow_dv_convert_action_modify_ipv6
10443 (mhdr_res, actions, error))
10445 action_flags |= actions->type ==
10446 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10447 MLX5_FLOW_ACTION_SET_IPV6_SRC :
10448 MLX5_FLOW_ACTION_SET_IPV6_DST;
10450 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10451 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10452 if (flow_dv_convert_action_modify_tp
10453 (mhdr_res, actions, items,
10454 &flow_attr, dev_flow, !!(action_flags &
10455 MLX5_FLOW_ACTION_DECAP), error))
10457 action_flags |= actions->type ==
10458 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10459 MLX5_FLOW_ACTION_SET_TP_SRC :
10460 MLX5_FLOW_ACTION_SET_TP_DST;
10462 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10463 if (flow_dv_convert_action_modify_dec_ttl
10464 (mhdr_res, items, &flow_attr, dev_flow,
10466 MLX5_FLOW_ACTION_DECAP), error))
10468 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10470 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10471 if (flow_dv_convert_action_modify_ttl
10472 (mhdr_res, actions, items, &flow_attr,
10473 dev_flow, !!(action_flags &
10474 MLX5_FLOW_ACTION_DECAP), error))
10476 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10478 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10479 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10480 if (flow_dv_convert_action_modify_tcp_seq
10481 (mhdr_res, actions, error))
10483 action_flags |= actions->type ==
10484 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10485 MLX5_FLOW_ACTION_INC_TCP_SEQ :
10486 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10489 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10490 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10491 if (flow_dv_convert_action_modify_tcp_ack
10492 (mhdr_res, actions, error))
10494 action_flags |= actions->type ==
10495 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10496 MLX5_FLOW_ACTION_INC_TCP_ACK :
10497 MLX5_FLOW_ACTION_DEC_TCP_ACK;
10499 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10500 if (flow_dv_convert_action_set_reg
10501 (mhdr_res, actions, error))
10503 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10505 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10506 if (flow_dv_convert_action_copy_mreg
10507 (dev, mhdr_res, actions, error))
10509 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10511 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10512 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10513 dev_flow->handle->fate_action =
10514 MLX5_FLOW_FATE_DEFAULT_MISS;
10516 case RTE_FLOW_ACTION_TYPE_METER:
10517 mtr = actions->conf;
10518 if (!flow->meter) {
10519 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10522 return rte_flow_error_set(error,
10524 RTE_FLOW_ERROR_TYPE_ACTION,
10527 "or invalid parameters");
10528 flow->meter = fm->idx;
10530 /* Set the meter action. */
10532 fm = mlx5_ipool_get(priv->sh->ipool
10533 [MLX5_IPOOL_MTR], flow->meter);
10535 return rte_flow_error_set(error,
10537 RTE_FLOW_ERROR_TYPE_ACTION,
10540 "or invalid parameters");
10542 dev_flow->dv.actions[actions_n++] =
10543 fm->mfts->meter_action;
10544 action_flags |= MLX5_FLOW_ACTION_METER;
10546 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10547 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10550 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10552 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10553 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10556 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10558 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10559 sample_act_pos = actions_n;
10560 ret = flow_dv_translate_action_sample(dev,
10570 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10571 /* put encap action into group if work with port id */
10572 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10573 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10574 sample_act->action_flags |=
10575 MLX5_FLOW_ACTION_ENCAP;
10577 case RTE_FLOW_ACTION_TYPE_END:
10578 actions_end = true;
10579 if (mhdr_res->actions_num) {
10580 /* create modify action if needed. */
10581 if (flow_dv_modify_hdr_resource_register
10582 (dev, mhdr_res, dev_flow, error))
10584 dev_flow->dv.actions[modify_action_position] =
10585 handle->dvh.modify_hdr->action;
10587 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10589 flow_dv_translate_create_counter(dev,
10590 dev_flow, count, age);
10592 if (!flow->counter)
10593 return rte_flow_error_set
10595 RTE_FLOW_ERROR_TYPE_ACTION,
10597 "cannot create counter"
10599 dev_flow->dv.actions[actions_n] =
10600 (flow_dv_counter_get_by_idx(dev,
10601 flow->counter, NULL))->action;
10604 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10605 ret = flow_dv_create_action_sample(dev,
10614 return rte_flow_error_set
10616 RTE_FLOW_ERROR_TYPE_ACTION,
10618 "cannot create sample action");
10619 if (num_of_dest > 1) {
10620 dev_flow->dv.actions[sample_act_pos] =
10621 dev_flow->dv.dest_array_res->action;
10623 dev_flow->dv.actions[sample_act_pos] =
10624 dev_flow->dv.sample_res->verbs_action;
10631 if (mhdr_res->actions_num &&
10632 modify_action_position == UINT32_MAX)
10633 modify_action_position = actions_n++;
10636 * For multiple destination (sample action with ratio=1), the encap
10637 * action and port id action will be combined into group action.
10638 * So need remove the original these actions in the flow and only
10639 * use the sample action instead of.
10641 if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10643 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10645 for (i = 0; i < actions_n; i++) {
10646 if ((sample_act->dr_encap_action &&
10647 sample_act->dr_encap_action ==
10648 dev_flow->dv.actions[i]) ||
10649 (sample_act->dr_port_id_action &&
10650 sample_act->dr_port_id_action ==
10651 dev_flow->dv.actions[i]))
10653 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10655 memcpy((void *)dev_flow->dv.actions,
10656 (void *)temp_actions,
10657 tmp_actions_n * sizeof(void *));
10658 actions_n = tmp_actions_n;
10660 dev_flow->dv.actions_n = actions_n;
10661 dev_flow->act_flags = action_flags;
10662 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10663 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10664 int item_type = items->type;
10666 if (!mlx5_flow_os_item_supported(item_type))
10667 return rte_flow_error_set(error, ENOTSUP,
10668 RTE_FLOW_ERROR_TYPE_ITEM,
10669 NULL, "item not supported");
10670 switch (item_type) {
10671 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10672 flow_dv_translate_item_port_id
10673 (dev, match_mask, match_value, items, attr);
10674 last_item = MLX5_FLOW_ITEM_PORT_ID;
10676 case RTE_FLOW_ITEM_TYPE_ETH:
10677 flow_dv_translate_item_eth(match_mask, match_value,
10679 dev_flow->dv.group);
10680 matcher.priority = action_flags &
10681 MLX5_FLOW_ACTION_DEFAULT_MISS &&
10682 !dev_flow->external ?
10683 MLX5_PRIORITY_MAP_L3 :
10684 MLX5_PRIORITY_MAP_L2;
10685 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10686 MLX5_FLOW_LAYER_OUTER_L2;
10688 case RTE_FLOW_ITEM_TYPE_VLAN:
10689 flow_dv_translate_item_vlan(dev_flow,
10690 match_mask, match_value,
10692 dev_flow->dv.group);
10693 matcher.priority = MLX5_PRIORITY_MAP_L2;
10694 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10695 MLX5_FLOW_LAYER_INNER_VLAN) :
10696 (MLX5_FLOW_LAYER_OUTER_L2 |
10697 MLX5_FLOW_LAYER_OUTER_VLAN);
10699 case RTE_FLOW_ITEM_TYPE_IPV4:
10700 mlx5_flow_tunnel_ip_check(items, next_protocol,
10701 &item_flags, &tunnel);
10702 flow_dv_translate_item_ipv4(match_mask, match_value,
10704 dev_flow->dv.group);
10705 matcher.priority = MLX5_PRIORITY_MAP_L3;
10706 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10707 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10708 if (items->mask != NULL &&
10709 ((const struct rte_flow_item_ipv4 *)
10710 items->mask)->hdr.next_proto_id) {
10712 ((const struct rte_flow_item_ipv4 *)
10713 (items->spec))->hdr.next_proto_id;
10715 ((const struct rte_flow_item_ipv4 *)
10716 (items->mask))->hdr.next_proto_id;
10718 /* Reset for inner layer. */
10719 next_protocol = 0xff;
10722 case RTE_FLOW_ITEM_TYPE_IPV6:
10723 mlx5_flow_tunnel_ip_check(items, next_protocol,
10724 &item_flags, &tunnel);
10725 flow_dv_translate_item_ipv6(match_mask, match_value,
10727 dev_flow->dv.group);
10728 matcher.priority = MLX5_PRIORITY_MAP_L3;
10729 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10730 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10731 if (items->mask != NULL &&
10732 ((const struct rte_flow_item_ipv6 *)
10733 items->mask)->hdr.proto) {
10735 ((const struct rte_flow_item_ipv6 *)
10736 items->spec)->hdr.proto;
10738 ((const struct rte_flow_item_ipv6 *)
10739 items->mask)->hdr.proto;
10741 /* Reset for inner layer. */
10742 next_protocol = 0xff;
10745 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10746 flow_dv_translate_item_ipv6_frag_ext(match_mask,
10749 last_item = tunnel ?
10750 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10751 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10752 if (items->mask != NULL &&
10753 ((const struct rte_flow_item_ipv6_frag_ext *)
10754 items->mask)->hdr.next_header) {
10756 ((const struct rte_flow_item_ipv6_frag_ext *)
10757 items->spec)->hdr.next_header;
10759 ((const struct rte_flow_item_ipv6_frag_ext *)
10760 items->mask)->hdr.next_header;
10762 /* Reset for inner layer. */
10763 next_protocol = 0xff;
10766 case RTE_FLOW_ITEM_TYPE_TCP:
10767 flow_dv_translate_item_tcp(match_mask, match_value,
10769 matcher.priority = MLX5_PRIORITY_MAP_L4;
10770 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10771 MLX5_FLOW_LAYER_OUTER_L4_TCP;
10773 case RTE_FLOW_ITEM_TYPE_UDP:
10774 flow_dv_translate_item_udp(match_mask, match_value,
10776 matcher.priority = MLX5_PRIORITY_MAP_L4;
10777 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10778 MLX5_FLOW_LAYER_OUTER_L4_UDP;
10780 case RTE_FLOW_ITEM_TYPE_GRE:
10781 flow_dv_translate_item_gre(match_mask, match_value,
10783 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10784 last_item = MLX5_FLOW_LAYER_GRE;
10786 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10787 flow_dv_translate_item_gre_key(match_mask,
10788 match_value, items);
10789 last_item = MLX5_FLOW_LAYER_GRE_KEY;
10791 case RTE_FLOW_ITEM_TYPE_NVGRE:
10792 flow_dv_translate_item_nvgre(match_mask, match_value,
10794 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10795 last_item = MLX5_FLOW_LAYER_GRE;
10797 case RTE_FLOW_ITEM_TYPE_VXLAN:
10798 flow_dv_translate_item_vxlan(match_mask, match_value,
10800 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10801 last_item = MLX5_FLOW_LAYER_VXLAN;
10803 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10804 flow_dv_translate_item_vxlan_gpe(match_mask,
10805 match_value, items,
10807 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10808 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10810 case RTE_FLOW_ITEM_TYPE_GENEVE:
10811 flow_dv_translate_item_geneve(match_mask, match_value,
10813 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10814 last_item = MLX5_FLOW_LAYER_GENEVE;
10816 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
10817 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
10821 return rte_flow_error_set(error, -ret,
10822 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10823 "cannot create GENEVE TLV option");
10824 flow->geneve_tlv_option = 1;
10825 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
10827 case RTE_FLOW_ITEM_TYPE_MPLS:
10828 flow_dv_translate_item_mpls(match_mask, match_value,
10829 items, last_item, tunnel);
10830 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10831 last_item = MLX5_FLOW_LAYER_MPLS;
10833 case RTE_FLOW_ITEM_TYPE_MARK:
10834 flow_dv_translate_item_mark(dev, match_mask,
10835 match_value, items);
10836 last_item = MLX5_FLOW_ITEM_MARK;
10838 case RTE_FLOW_ITEM_TYPE_META:
10839 flow_dv_translate_item_meta(dev, match_mask,
10840 match_value, attr, items);
10841 last_item = MLX5_FLOW_ITEM_METADATA;
10843 case RTE_FLOW_ITEM_TYPE_ICMP:
10844 flow_dv_translate_item_icmp(match_mask, match_value,
10846 last_item = MLX5_FLOW_LAYER_ICMP;
10848 case RTE_FLOW_ITEM_TYPE_ICMP6:
10849 flow_dv_translate_item_icmp6(match_mask, match_value,
10851 last_item = MLX5_FLOW_LAYER_ICMP6;
10853 case RTE_FLOW_ITEM_TYPE_TAG:
10854 flow_dv_translate_item_tag(dev, match_mask,
10855 match_value, items);
10856 last_item = MLX5_FLOW_ITEM_TAG;
10858 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10859 flow_dv_translate_mlx5_item_tag(dev, match_mask,
10860 match_value, items);
10861 last_item = MLX5_FLOW_ITEM_TAG;
10863 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10864 flow_dv_translate_item_tx_queue(dev, match_mask,
10867 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10869 case RTE_FLOW_ITEM_TYPE_GTP:
10870 flow_dv_translate_item_gtp(match_mask, match_value,
10872 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10873 last_item = MLX5_FLOW_LAYER_GTP;
10875 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10876 ret = flow_dv_translate_item_gtp_psc(match_mask,
10880 return rte_flow_error_set(error, -ret,
10881 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10882 "cannot create GTP PSC item");
10883 last_item = MLX5_FLOW_LAYER_GTP_PSC;
10885 case RTE_FLOW_ITEM_TYPE_ECPRI:
10886 if (!mlx5_flex_parser_ecpri_exist(dev)) {
10887 /* Create it only the first time to be used. */
10888 ret = mlx5_flex_parser_ecpri_alloc(dev);
10890 return rte_flow_error_set
10892 RTE_FLOW_ERROR_TYPE_ITEM,
10894 "cannot create eCPRI parser");
10896 /* Adjust the length matcher and device flow value. */
10897 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10898 dev_flow->dv.value.size =
10899 MLX5_ST_SZ_BYTES(fte_match_param);
10900 flow_dv_translate_item_ecpri(dev, match_mask,
10901 match_value, items);
10902 /* No other protocol should follow eCPRI layer. */
10903 last_item = MLX5_FLOW_LAYER_ECPRI;
10908 item_flags |= last_item;
10911 * When E-Switch mode is enabled, we have two cases where we need to
10912 * set the source port manually.
10913 * The first one, is in case of Nic steering rule, and the second is
10914 * E-Switch rule where no port_id item was found. In both cases
10915 * the source port is set according the current port in use.
10917 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10918 (priv->representor || priv->master)) {
10919 if (flow_dv_translate_item_port_id(dev, match_mask,
10920 match_value, NULL, attr))
10923 #ifdef RTE_LIBRTE_MLX5_DEBUG
10924 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10925 dev_flow->dv.value.buf));
10928 * Layers may be already initialized from prefix flow if this dev_flow
10929 * is the suffix flow.
10931 handle->layers |= item_flags;
10932 if (action_flags & MLX5_FLOW_ACTION_RSS)
10933 flow_dv_hashfields_set(dev_flow, rss_desc);
10934 /* Register matcher. */
10935 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10936 matcher.mask.size);
10937 matcher.priority = mlx5_os_flow_adjust_priority(dev,
10940 /* reserved field no needs to be set to 0 here. */
10941 tbl_key.domain = attr->transfer;
10942 tbl_key.direction = attr->egress;
10943 tbl_key.table_id = dev_flow->dv.group;
10944 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10945 tunnel, attr->group, error))
10951 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10954 * @param[in, out] action
10955 * Shred RSS action holding hash RX queue objects.
10956 * @param[in] hash_fields
10957 * Defines combination of packet fields to participate in RX hash.
10958 * @param[in] tunnel
10960 * @param[in] hrxq_idx
10961 * Hash RX queue index to set.
10964 * 0 on success, otherwise negative errno value.
10967 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10968 const uint64_t hash_fields,
10972 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10974 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10975 case MLX5_RSS_HASH_IPV4:
10976 hrxqs[0] = hrxq_idx;
10978 case MLX5_RSS_HASH_IPV4_TCP:
10979 hrxqs[1] = hrxq_idx;
10981 case MLX5_RSS_HASH_IPV4_UDP:
10982 hrxqs[2] = hrxq_idx;
10984 case MLX5_RSS_HASH_IPV6:
10985 hrxqs[3] = hrxq_idx;
10987 case MLX5_RSS_HASH_IPV6_TCP:
10988 hrxqs[4] = hrxq_idx;
10990 case MLX5_RSS_HASH_IPV6_UDP:
10991 hrxqs[5] = hrxq_idx;
10993 case MLX5_RSS_HASH_NONE:
10994 hrxqs[6] = hrxq_idx;
11002 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11006 * Pointer to the Ethernet device structure.
11008 * Shared RSS action ID holding hash RX queue objects.
11009 * @param[in] hash_fields
11010 * Defines combination of packet fields to participate in RX hash.
11011 * @param[in] tunnel
11015 * Valid hash RX queue index, otherwise 0.
11018 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11019 const uint64_t hash_fields,
11022 struct mlx5_priv *priv = dev->data->dev_private;
11023 struct mlx5_shared_action_rss *shared_rss =
11024 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11025 const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11026 shared_rss->hrxq_tunnel;
11028 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11029 case MLX5_RSS_HASH_IPV4:
11031 case MLX5_RSS_HASH_IPV4_TCP:
11033 case MLX5_RSS_HASH_IPV4_UDP:
11035 case MLX5_RSS_HASH_IPV6:
11037 case MLX5_RSS_HASH_IPV6_TCP:
11039 case MLX5_RSS_HASH_IPV6_UDP:
11041 case MLX5_RSS_HASH_NONE:
11049 * Apply the flow to the NIC, lock free,
11050 * (mutex should be acquired by caller).
11053 * Pointer to the Ethernet device structure.
11054 * @param[in, out] flow
11055 * Pointer to flow structure.
11056 * @param[out] error
11057 * Pointer to error structure.
11060 * 0 on success, a negative errno value otherwise and rte_errno is set.
11063 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11064 struct rte_flow_error *error)
11066 struct mlx5_flow_dv_workspace *dv;
11067 struct mlx5_flow_handle *dh;
11068 struct mlx5_flow_handle_dv *dv_h;
11069 struct mlx5_flow *dev_flow;
11070 struct mlx5_priv *priv = dev->data->dev_private;
11071 uint32_t handle_idx;
11075 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11076 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11079 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11080 dev_flow = &wks->flows[idx];
11081 dv = &dev_flow->dv;
11082 dh = dev_flow->handle;
11085 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11086 if (dv->transfer) {
11087 dv->actions[n++] = priv->sh->esw_drop_action;
11089 MLX5_ASSERT(priv->drop_queue.hrxq);
11091 priv->drop_queue.hrxq->action;
11093 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11094 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11095 struct mlx5_hrxq *hrxq;
11098 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11104 "cannot get hash queue");
11107 dh->rix_hrxq = hrxq_idx;
11108 dv->actions[n++] = hrxq->action;
11109 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11110 struct mlx5_hrxq *hrxq = NULL;
11113 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11114 rss_desc->shared_rss,
11115 dev_flow->hash_fields,
11117 MLX5_FLOW_LAYER_TUNNEL));
11119 hrxq = mlx5_ipool_get
11120 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11126 "cannot get hash queue");
11129 dh->rix_srss = rss_desc->shared_rss;
11130 dv->actions[n++] = hrxq->action;
11131 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11132 if (!priv->sh->default_miss_action) {
11135 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11136 "default miss action not be created.");
11139 dv->actions[n++] = priv->sh->default_miss_action;
11141 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11142 (void *)&dv->value, n,
11143 dv->actions, &dh->drv_flow);
11145 rte_flow_error_set(error, errno,
11146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11148 "hardware refuses to create flow");
11151 if (priv->vmwa_context &&
11152 dh->vf_vlan.tag && !dh->vf_vlan.created) {
11154 * The rule contains the VLAN pattern.
11155 * For VF we are going to create VLAN
11156 * interface to make hypervisor set correct
11157 * e-Switch vport context.
11159 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11164 err = rte_errno; /* Save rte_errno before cleanup. */
11165 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11166 handle_idx, dh, next) {
11167 /* hrxq is union, don't clear it if the flag is not set. */
11168 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11169 mlx5_hrxq_release(dev, dh->rix_hrxq);
11171 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11174 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11175 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11177 rte_errno = err; /* Restore rte_errno. */
11182 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11183 struct mlx5_cache_entry *entry)
11185 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11188 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11193 * Release the flow matcher.
11196 * Pointer to Ethernet device.
11198 * Pointer to mlx5_flow_handle.
11201 * 1 while a reference on it exists, 0 when freed.
11204 flow_dv_matcher_release(struct rte_eth_dev *dev,
11205 struct mlx5_flow_handle *handle)
11207 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11208 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11209 typeof(*tbl), tbl);
11212 MLX5_ASSERT(matcher->matcher_object);
11213 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11214 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11219 * Release encap_decap resource.
11222 * Pointer to the hash list.
11224 * Pointer to exist resource entry object.
11227 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11228 struct mlx5_hlist_entry *entry)
11230 struct mlx5_dev_ctx_shared *sh = list->ctx;
11231 struct mlx5_flow_dv_encap_decap_resource *res =
11232 container_of(entry, typeof(*res), entry);
11234 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11235 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11239 * Release an encap/decap resource.
11242 * Pointer to Ethernet device.
11243 * @param encap_decap_idx
11244 * Index of encap decap resource.
11247 * 1 while a reference on it exists, 0 when freed.
11250 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11251 uint32_t encap_decap_idx)
11253 struct mlx5_priv *priv = dev->data->dev_private;
11254 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11256 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11258 if (!cache_resource)
11260 MLX5_ASSERT(cache_resource->action);
11261 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11262 &cache_resource->entry);
11266 * Release an jump to table action resource.
11269 * Pointer to Ethernet device.
11271 * Pointer to mlx5_flow_handle.
11274 * 1 while a reference on it exists, 0 when freed.
11277 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11278 struct mlx5_flow_handle *handle)
11280 struct mlx5_priv *priv = dev->data->dev_private;
11281 struct mlx5_flow_tbl_data_entry *tbl_data;
11283 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11287 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11291 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11292 struct mlx5_hlist_entry *entry)
11294 struct mlx5_flow_dv_modify_hdr_resource *res =
11295 container_of(entry, typeof(*res), entry);
11297 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11302 * Release a modify-header resource.
11305 * Pointer to Ethernet device.
11307 * Pointer to mlx5_flow_handle.
11310 * 1 while a reference on it exists, 0 when freed.
11313 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11314 struct mlx5_flow_handle *handle)
11316 struct mlx5_priv *priv = dev->data->dev_private;
11317 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11319 MLX5_ASSERT(entry->action);
11320 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11324 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11325 struct mlx5_cache_entry *entry)
11327 struct mlx5_dev_ctx_shared *sh = list->ctx;
11328 struct mlx5_flow_dv_port_id_action_resource *cache =
11329 container_of(entry, typeof(*cache), entry);
11331 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11332 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11336 * Release port ID action resource.
11339 * Pointer to Ethernet device.
11341 * Pointer to mlx5_flow_handle.
11344 * 1 while a reference on it exists, 0 when freed.
11347 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11350 struct mlx5_priv *priv = dev->data->dev_private;
11351 struct mlx5_flow_dv_port_id_action_resource *cache;
11353 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11356 MLX5_ASSERT(cache->action);
11357 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11362 * Release shared RSS action resource.
11365 * Pointer to Ethernet device.
11367 * Shared RSS action index.
11370 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11372 struct mlx5_priv *priv = dev->data->dev_private;
11373 struct mlx5_shared_action_rss *shared_rss;
11375 shared_rss = mlx5_ipool_get
11376 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11377 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11381 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11382 struct mlx5_cache_entry *entry)
11384 struct mlx5_dev_ctx_shared *sh = list->ctx;
11385 struct mlx5_flow_dv_push_vlan_action_resource *cache =
11386 container_of(entry, typeof(*cache), entry);
11388 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11389 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11393 * Release push vlan action resource.
11396 * Pointer to Ethernet device.
11398 * Pointer to mlx5_flow_handle.
11401 * 1 while a reference on it exists, 0 when freed.
11404 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11405 struct mlx5_flow_handle *handle)
11407 struct mlx5_priv *priv = dev->data->dev_private;
11408 struct mlx5_flow_dv_push_vlan_action_resource *cache;
11409 uint32_t idx = handle->dvh.rix_push_vlan;
11411 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11414 MLX5_ASSERT(cache->action);
11415 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11420 * Release the fate resource.
11423 * Pointer to Ethernet device.
11425 * Pointer to mlx5_flow_handle.
11428 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11429 struct mlx5_flow_handle *handle)
11431 if (!handle->rix_fate)
11433 switch (handle->fate_action) {
11434 case MLX5_FLOW_FATE_QUEUE:
11435 mlx5_hrxq_release(dev, handle->rix_hrxq);
11437 case MLX5_FLOW_FATE_JUMP:
11438 flow_dv_jump_tbl_resource_release(dev, handle);
11440 case MLX5_FLOW_FATE_PORT_ID:
11441 flow_dv_port_id_action_resource_release(dev,
11442 handle->rix_port_id_action);
11445 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11448 handle->rix_fate = 0;
11452 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11453 struct mlx5_cache_entry *entry)
11455 struct mlx5_flow_dv_sample_resource *cache_resource =
11456 container_of(entry, typeof(*cache_resource), entry);
11457 struct rte_eth_dev *dev = cache_resource->dev;
11458 struct mlx5_priv *priv = dev->data->dev_private;
11460 if (cache_resource->verbs_action)
11461 claim_zero(mlx5_flow_os_destroy_flow_action
11462 (cache_resource->verbs_action));
11463 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11464 if (cache_resource->default_miss)
11465 claim_zero(mlx5_flow_os_destroy_flow_action
11466 (cache_resource->default_miss));
11468 if (cache_resource->normal_path_tbl)
11469 flow_dv_tbl_resource_release(MLX5_SH(dev),
11470 cache_resource->normal_path_tbl);
11471 flow_dv_sample_sub_actions_release(dev,
11472 &cache_resource->sample_idx);
11473 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11474 cache_resource->idx);
11475 DRV_LOG(DEBUG, "sample resource %p: removed",
11476 (void *)cache_resource);
11480 * Release an sample resource.
11483 * Pointer to Ethernet device.
11485 * Pointer to mlx5_flow_handle.
11488 * 1 while a reference on it exists, 0 when freed.
11491 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11492 struct mlx5_flow_handle *handle)
11494 struct mlx5_priv *priv = dev->data->dev_private;
11495 struct mlx5_flow_dv_sample_resource *cache_resource;
11497 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11498 handle->dvh.rix_sample);
11499 if (!cache_resource)
11501 MLX5_ASSERT(cache_resource->verbs_action);
11502 return mlx5_cache_unregister(&priv->sh->sample_action_list,
11503 &cache_resource->entry);
11507 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11508 struct mlx5_cache_entry *entry)
11510 struct mlx5_flow_dv_dest_array_resource *cache_resource =
11511 container_of(entry, typeof(*cache_resource), entry);
11512 struct rte_eth_dev *dev = cache_resource->dev;
11513 struct mlx5_priv *priv = dev->data->dev_private;
11516 MLX5_ASSERT(cache_resource->action);
11517 if (cache_resource->action)
11518 claim_zero(mlx5_flow_os_destroy_flow_action
11519 (cache_resource->action));
11520 for (; i < cache_resource->num_of_dest; i++)
11521 flow_dv_sample_sub_actions_release(dev,
11522 &cache_resource->sample_idx[i]);
11523 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11524 cache_resource->idx);
11525 DRV_LOG(DEBUG, "destination array resource %p: removed",
11526 (void *)cache_resource);
11530 * Release an destination array resource.
11533 * Pointer to Ethernet device.
11535 * Pointer to mlx5_flow_handle.
11538 * 1 while a reference on it exists, 0 when freed.
11541 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11542 struct mlx5_flow_handle *handle)
11544 struct mlx5_priv *priv = dev->data->dev_private;
11545 struct mlx5_flow_dv_dest_array_resource *cache;
11547 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11548 handle->dvh.rix_dest_array);
11551 MLX5_ASSERT(cache->action);
11552 return mlx5_cache_unregister(&priv->sh->dest_array_list,
11557 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11559 struct mlx5_priv *priv = dev->data->dev_private;
11560 struct mlx5_dev_ctx_shared *sh = priv->sh;
11561 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11562 sh->geneve_tlv_option_resource;
11563 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11564 if (geneve_opt_resource) {
11565 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11566 __ATOMIC_RELAXED))) {
11567 claim_zero(mlx5_devx_cmd_destroy
11568 (geneve_opt_resource->obj));
11569 mlx5_free(sh->geneve_tlv_option_resource);
11570 sh->geneve_tlv_option_resource = NULL;
11573 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11577 * Remove the flow from the NIC but keeps it in memory.
11578 * Lock free, (mutex should be acquired by caller).
11581 * Pointer to Ethernet device.
11582 * @param[in, out] flow
11583 * Pointer to flow structure.
11586 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11588 struct mlx5_flow_handle *dh;
11589 uint32_t handle_idx;
11590 struct mlx5_priv *priv = dev->data->dev_private;
11594 handle_idx = flow->dev_handles;
11595 while (handle_idx) {
11596 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11600 if (dh->drv_flow) {
11601 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11602 dh->drv_flow = NULL;
11604 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11605 flow_dv_fate_resource_release(dev, dh);
11606 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11607 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11608 handle_idx = dh->next.next;
11613 * Remove the flow from the NIC and the memory.
11614 * Lock free, (mutex should be acquired by caller).
11617 * Pointer to the Ethernet device structure.
11618 * @param[in, out] flow
11619 * Pointer to flow structure.
11622 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11624 struct mlx5_flow_handle *dev_handle;
11625 struct mlx5_priv *priv = dev->data->dev_private;
11630 flow_dv_remove(dev, flow);
11631 if (flow->counter) {
11632 flow_dv_counter_free(dev, flow->counter);
11636 struct mlx5_flow_meter *fm;
11638 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11641 mlx5_flow_meter_detach(fm);
11645 flow_dv_aso_age_release(dev, flow->age);
11646 if (flow->geneve_tlv_option) {
11647 flow_dv_geneve_tlv_option_resource_release(dev);
11648 flow->geneve_tlv_option = 0;
11650 while (flow->dev_handles) {
11651 uint32_t tmp_idx = flow->dev_handles;
11653 dev_handle = mlx5_ipool_get(priv->sh->ipool
11654 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11657 flow->dev_handles = dev_handle->next.next;
11658 if (dev_handle->dvh.matcher)
11659 flow_dv_matcher_release(dev, dev_handle);
11660 if (dev_handle->dvh.rix_sample)
11661 flow_dv_sample_resource_release(dev, dev_handle);
11662 if (dev_handle->dvh.rix_dest_array)
11663 flow_dv_dest_array_resource_release(dev, dev_handle);
11664 if (dev_handle->dvh.rix_encap_decap)
11665 flow_dv_encap_decap_resource_release(dev,
11666 dev_handle->dvh.rix_encap_decap);
11667 if (dev_handle->dvh.modify_hdr)
11668 flow_dv_modify_hdr_resource_release(dev, dev_handle);
11669 if (dev_handle->dvh.rix_push_vlan)
11670 flow_dv_push_vlan_action_resource_release(dev,
11672 if (dev_handle->dvh.rix_tag)
11673 flow_dv_tag_release(dev,
11674 dev_handle->dvh.rix_tag);
11675 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11676 flow_dv_fate_resource_release(dev, dev_handle);
11678 srss = dev_handle->rix_srss;
11679 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11683 flow_dv_shared_rss_action_release(dev, srss);
11687 * Release array of hash RX queue objects.
11691 * Pointer to the Ethernet device structure.
11692 * @param[in, out] hrxqs
11693 * Array of hash RX queue objects.
11696 * Total number of references to hash RX queue objects in *hrxqs* array
11697 * after this operation.
11700 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11701 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11706 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11707 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11717 * Release all hash RX queue objects representing shared RSS action.
11720 * Pointer to the Ethernet device structure.
11721 * @param[in, out] action
11722 * Shared RSS action to remove hash RX queue objects from.
11725 * Total number of references to hash RX queue objects stored in *action*
11726 * after this operation.
11727 * Expected to be 0 if no external references held.
11730 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11731 struct mlx5_shared_action_rss *action)
11733 return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11734 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11738 * Setup shared RSS action.
11739 * Prepare set of hash RX queue objects sufficient to handle all valid
11740 * hash_fields combinations (see enum ibv_rx_hash_fields).
11743 * Pointer to the Ethernet device structure.
11744 * @param[in] action_idx
11745 * Shared RSS action ipool index.
11746 * @param[in, out] action
11747 * Partially initialized shared RSS action.
11748 * @param[out] error
11749 * Perform verbose error reporting if not NULL. Initialized in case of
11753 * 0 on success, otherwise negative errno value.
11756 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11757 uint32_t action_idx,
11758 struct mlx5_shared_action_rss *action,
11759 struct rte_flow_error *error)
11761 struct mlx5_flow_rss_desc rss_desc = { 0 };
11765 if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11766 return rte_flow_error_set(error, rte_errno,
11767 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11768 "cannot setup indirection table");
11770 memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11771 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11772 rss_desc.const_q = action->origin.queue;
11773 rss_desc.queue_num = action->origin.queue_num;
11774 /* Set non-zero value to indicate a shared RSS. */
11775 rss_desc.shared_rss = action_idx;
11776 rss_desc.ind_tbl = action->ind_tbl;
11777 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11779 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11782 for (tunnel = 0; tunnel < 2; tunnel++) {
11783 rss_desc.tunnel = tunnel;
11784 rss_desc.hash_fields = hash_fields;
11785 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11789 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11790 "cannot get hash queue");
11791 goto error_hrxq_new;
11793 err = __flow_dv_action_rss_hrxq_set
11794 (action, hash_fields, tunnel, hrxq_idx);
11801 __flow_dv_action_rss_hrxqs_release(dev, action);
11802 if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11803 action->ind_tbl = NULL;
11809 * Create shared RSS action.
11812 * Pointer to the Ethernet device structure.
11814 * Shared action configuration.
11816 * RSS action specification used to create shared action.
11817 * @param[out] error
11818 * Perform verbose error reporting if not NULL. Initialized in case of
11822 * A valid shared action ID in case of success, 0 otherwise and
11823 * rte_errno is set.
11826 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11827 const struct rte_flow_shared_action_conf *conf,
11828 const struct rte_flow_action_rss *rss,
11829 struct rte_flow_error *error)
11831 struct mlx5_priv *priv = dev->data->dev_private;
11832 struct mlx5_shared_action_rss *shared_action = NULL;
11833 void *queue = NULL;
11834 struct rte_flow_action_rss *origin;
11835 const uint8_t *rss_key;
11836 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11839 RTE_SET_USED(conf);
11840 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11842 shared_action = mlx5_ipool_zmalloc
11843 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11844 if (!shared_action || !queue) {
11845 rte_flow_error_set(error, ENOMEM,
11846 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11847 "cannot allocate resource memory");
11848 goto error_rss_init;
11850 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11851 rte_flow_error_set(error, E2BIG,
11852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11853 "rss action number out of range");
11854 goto error_rss_init;
11856 shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11857 sizeof(*shared_action->ind_tbl),
11859 if (!shared_action->ind_tbl) {
11860 rte_flow_error_set(error, ENOMEM,
11861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11862 "cannot allocate resource memory");
11863 goto error_rss_init;
11865 memcpy(queue, rss->queue, queue_size);
11866 shared_action->ind_tbl->queues = queue;
11867 shared_action->ind_tbl->queues_n = rss->queue_num;
11868 origin = &shared_action->origin;
11869 origin->func = rss->func;
11870 origin->level = rss->level;
11871 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11872 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11873 /* NULL RSS key indicates default RSS key. */
11874 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11875 memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11876 origin->key = &shared_action->key[0];
11877 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11878 origin->queue = queue;
11879 origin->queue_num = rss->queue_num;
11880 if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11881 goto error_rss_init;
11882 rte_spinlock_init(&shared_action->action_rss_sl);
11883 __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11884 rte_spinlock_lock(&priv->shared_act_sl);
11885 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11886 &priv->rss_shared_actions, idx, shared_action, next);
11887 rte_spinlock_unlock(&priv->shared_act_sl);
11890 if (shared_action) {
11891 if (shared_action->ind_tbl)
11892 mlx5_free(shared_action->ind_tbl);
11893 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11902 * Destroy the shared RSS action.
11903 * Release related hash RX queue objects.
11906 * Pointer to the Ethernet device structure.
11908 * The shared RSS action object ID to be removed.
11909 * @param[out] error
11910 * Perform verbose error reporting if not NULL. Initialized in case of
11914 * 0 on success, otherwise negative errno value.
11917 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11918 struct rte_flow_error *error)
11920 struct mlx5_priv *priv = dev->data->dev_private;
11921 struct mlx5_shared_action_rss *shared_rss =
11922 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11923 uint32_t old_refcnt = 1;
11925 uint16_t *queue = NULL;
11928 return rte_flow_error_set(error, EINVAL,
11929 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11930 "invalid shared action");
11931 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11933 return rte_flow_error_set(error, EBUSY,
11934 RTE_FLOW_ERROR_TYPE_ACTION,
11936 "shared rss hrxq has references");
11937 queue = shared_rss->ind_tbl->queues;
11938 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11940 return rte_flow_error_set(error, EBUSY,
11941 RTE_FLOW_ERROR_TYPE_ACTION,
11943 "shared rss indirection table has"
11945 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11946 0, 0, __ATOMIC_ACQUIRE,
11948 return rte_flow_error_set(error, EBUSY,
11949 RTE_FLOW_ERROR_TYPE_ACTION,
11951 "shared rss has references");
11953 rte_spinlock_lock(&priv->shared_act_sl);
11954 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11955 &priv->rss_shared_actions, idx, shared_rss, next);
11956 rte_spinlock_unlock(&priv->shared_act_sl);
11957 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11963 * Create shared action, lock free,
11964 * (mutex should be acquired by caller).
11965 * Dispatcher for action type specific call.
11968 * Pointer to the Ethernet device structure.
11970 * Shared action configuration.
11971 * @param[in] action
11972 * Action specification used to create shared action.
11973 * @param[out] error
11974 * Perform verbose error reporting if not NULL. Initialized in case of
11978 * A valid shared action handle in case of success, NULL otherwise and
11979 * rte_errno is set.
11981 static struct rte_flow_shared_action *
11982 flow_dv_action_create(struct rte_eth_dev *dev,
11983 const struct rte_flow_shared_action_conf *conf,
11984 const struct rte_flow_action *action,
11985 struct rte_flow_error *err)
11990 switch (action->type) {
11991 case RTE_FLOW_ACTION_TYPE_RSS:
11992 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11993 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11994 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11996 case RTE_FLOW_ACTION_TYPE_AGE:
11997 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11998 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11999 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12001 struct mlx5_aso_age_action *aso_age =
12002 flow_aso_age_get_by_idx(dev, ret);
12004 if (!aso_age->age_params.context)
12005 aso_age->age_params.context =
12006 (void *)(uintptr_t)idx;
12010 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12011 NULL, "action type not supported");
12014 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12018 * Destroy the shared action.
12019 * Release action related resources on the NIC and the memory.
12020 * Lock free, (mutex should be acquired by caller).
12021 * Dispatcher for action type specific call.
12024 * Pointer to the Ethernet device structure.
12025 * @param[in] action
12026 * The shared action object to be removed.
12027 * @param[out] error
12028 * Perform verbose error reporting if not NULL. Initialized in case of
12032 * 0 on success, otherwise negative errno value.
12035 flow_dv_action_destroy(struct rte_eth_dev *dev,
12036 struct rte_flow_shared_action *action,
12037 struct rte_flow_error *error)
12039 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12040 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12041 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12045 case MLX5_SHARED_ACTION_TYPE_RSS:
12046 return __flow_dv_action_rss_release(dev, idx, error);
12047 case MLX5_SHARED_ACTION_TYPE_AGE:
12048 ret = flow_dv_aso_age_release(dev, idx);
12051 * In this case, the last flow has a reference will
12052 * actually release the age action.
12054 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12055 " released with references %d.", idx, ret);
12058 return rte_flow_error_set(error, ENOTSUP,
12059 RTE_FLOW_ERROR_TYPE_ACTION,
12061 "action type not supported");
12066 * Updates in place shared RSS action configuration.
12069 * Pointer to the Ethernet device structure.
12071 * The shared RSS action object ID to be updated.
12072 * @param[in] action_conf
12073 * RSS action specification used to modify *shared_rss*.
12074 * @param[out] error
12075 * Perform verbose error reporting if not NULL. Initialized in case of
12079 * 0 on success, otherwise negative errno value.
12080 * @note: currently only support update of RSS queues.
12083 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12084 const struct rte_flow_action_rss *action_conf,
12085 struct rte_flow_error *error)
12087 struct mlx5_priv *priv = dev->data->dev_private;
12088 struct mlx5_shared_action_rss *shared_rss =
12089 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12091 void *queue = NULL;
12092 uint16_t *queue_old = NULL;
12093 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12096 return rte_flow_error_set(error, EINVAL,
12097 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12098 "invalid shared action to update");
12099 queue = mlx5_malloc(MLX5_MEM_ZERO,
12100 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12103 return rte_flow_error_set(error, ENOMEM,
12104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12106 "cannot allocate resource memory");
12107 memcpy(queue, action_conf->queue, queue_size);
12108 MLX5_ASSERT(shared_rss->ind_tbl);
12109 rte_spinlock_lock(&shared_rss->action_rss_sl);
12110 queue_old = shared_rss->ind_tbl->queues;
12111 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12112 queue, action_conf->queue_num, true);
12115 ret = rte_flow_error_set(error, rte_errno,
12116 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12117 "cannot update indirection table");
12119 mlx5_free(queue_old);
12120 shared_rss->origin.queue = queue;
12121 shared_rss->origin.queue_num = action_conf->queue_num;
12123 rte_spinlock_unlock(&shared_rss->action_rss_sl);
12128 * Updates in place shared action configuration, lock free,
12129 * (mutex should be acquired by caller).
12132 * Pointer to the Ethernet device structure.
12133 * @param[in] action
12134 * The shared action object to be updated.
12135 * @param[in] action_conf
12136 * Action specification used to modify *action*.
12137 * *action_conf* should be of type correlating with type of the *action*,
12138 * otherwise considered as invalid.
12139 * @param[out] error
12140 * Perform verbose error reporting if not NULL. Initialized in case of
12144 * 0 on success, otherwise negative errno value.
12147 flow_dv_action_update(struct rte_eth_dev *dev,
12148 struct rte_flow_shared_action *action,
12149 const void *action_conf,
12150 struct rte_flow_error *err)
12152 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12153 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12154 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12157 case MLX5_SHARED_ACTION_TYPE_RSS:
12158 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12160 return rte_flow_error_set(err, ENOTSUP,
12161 RTE_FLOW_ERROR_TYPE_ACTION,
12163 "action type update not supported");
12168 flow_dv_action_query(struct rte_eth_dev *dev,
12169 const struct rte_flow_shared_action *action, void *data,
12170 struct rte_flow_error *error)
12172 struct mlx5_age_param *age_param;
12173 struct rte_flow_query_age *resp;
12174 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12175 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12176 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12179 case MLX5_SHARED_ACTION_TYPE_AGE:
12180 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12182 resp->aged = __atomic_load_n(&age_param->state,
12183 __ATOMIC_RELAXED) == AGE_TMOUT ?
12185 resp->sec_since_last_hit_valid = !resp->aged;
12186 if (resp->sec_since_last_hit_valid)
12187 resp->sec_since_last_hit = __atomic_load_n
12188 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12191 return rte_flow_error_set(error, ENOTSUP,
12192 RTE_FLOW_ERROR_TYPE_ACTION,
12194 "action type query not supported");
12199 * Query a dv flow rule for its statistics via devx.
12202 * Pointer to Ethernet device.
12204 * Pointer to the sub flow.
12206 * data retrieved by the query.
12207 * @param[out] error
12208 * Perform verbose error reporting if not NULL.
12211 * 0 on success, a negative errno value otherwise and rte_errno is set.
12214 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12215 void *data, struct rte_flow_error *error)
12217 struct mlx5_priv *priv = dev->data->dev_private;
12218 struct rte_flow_query_count *qc = data;
12220 if (!priv->config.devx)
12221 return rte_flow_error_set(error, ENOTSUP,
12222 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12224 "counters are not supported");
12225 if (flow->counter) {
12226 uint64_t pkts, bytes;
12227 struct mlx5_flow_counter *cnt;
12229 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12231 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12235 return rte_flow_error_set(error, -err,
12236 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12237 NULL, "cannot read counters");
12240 qc->hits = pkts - cnt->hits;
12241 qc->bytes = bytes - cnt->bytes;
12244 cnt->bytes = bytes;
12248 return rte_flow_error_set(error, EINVAL,
12249 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12251 "counters are not available");
12255 * Query a flow rule AGE action for aging information.
12258 * Pointer to Ethernet device.
12260 * Pointer to the sub flow.
12262 * data retrieved by the query.
12263 * @param[out] error
12264 * Perform verbose error reporting if not NULL.
12267 * 0 on success, a negative errno value otherwise and rte_errno is set.
12270 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12271 void *data, struct rte_flow_error *error)
12273 struct rte_flow_query_age *resp = data;
12274 struct mlx5_age_param *age_param;
12277 struct mlx5_aso_age_action *act =
12278 flow_aso_age_get_by_idx(dev, flow->age);
12280 age_param = &act->age_params;
12281 } else if (flow->counter) {
12282 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12284 if (!age_param || !age_param->timeout)
12285 return rte_flow_error_set
12287 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12288 NULL, "cannot read age data");
12290 return rte_flow_error_set(error, EINVAL,
12291 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12292 NULL, "age data not available");
12294 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12296 resp->sec_since_last_hit_valid = !resp->aged;
12297 if (resp->sec_since_last_hit_valid)
12298 resp->sec_since_last_hit = __atomic_load_n
12299 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12306 * @see rte_flow_query()
12307 * @see rte_flow_ops
12310 flow_dv_query(struct rte_eth_dev *dev,
12311 struct rte_flow *flow __rte_unused,
12312 const struct rte_flow_action *actions __rte_unused,
12313 void *data __rte_unused,
12314 struct rte_flow_error *error __rte_unused)
12318 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12319 switch (actions->type) {
12320 case RTE_FLOW_ACTION_TYPE_VOID:
12322 case RTE_FLOW_ACTION_TYPE_COUNT:
12323 ret = flow_dv_query_count(dev, flow, data, error);
12325 case RTE_FLOW_ACTION_TYPE_AGE:
12326 ret = flow_dv_query_age(dev, flow, data, error);
12329 return rte_flow_error_set(error, ENOTSUP,
12330 RTE_FLOW_ERROR_TYPE_ACTION,
12332 "action not supported");
12339 * Destroy the meter table set.
12340 * Lock free, (mutex should be acquired by caller).
12343 * Pointer to Ethernet device.
12345 * Pointer to the meter table set.
12351 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12352 struct mlx5_meter_domains_infos *tbl)
12354 struct mlx5_priv *priv = dev->data->dev_private;
12355 struct mlx5_meter_domains_infos *mtd =
12356 (struct mlx5_meter_domains_infos *)tbl;
12358 if (!mtd || !priv->config.dv_flow_en)
12360 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12361 claim_zero(mlx5_flow_os_destroy_flow
12362 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12363 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12364 claim_zero(mlx5_flow_os_destroy_flow
12365 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12366 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12367 claim_zero(mlx5_flow_os_destroy_flow
12368 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12369 if (mtd->egress.color_matcher)
12370 claim_zero(mlx5_flow_os_destroy_flow_matcher
12371 (mtd->egress.color_matcher));
12372 if (mtd->egress.any_matcher)
12373 claim_zero(mlx5_flow_os_destroy_flow_matcher
12374 (mtd->egress.any_matcher));
12375 if (mtd->egress.tbl)
12376 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12377 if (mtd->egress.sfx_tbl)
12378 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12379 if (mtd->ingress.color_matcher)
12380 claim_zero(mlx5_flow_os_destroy_flow_matcher
12381 (mtd->ingress.color_matcher));
12382 if (mtd->ingress.any_matcher)
12383 claim_zero(mlx5_flow_os_destroy_flow_matcher
12384 (mtd->ingress.any_matcher));
12385 if (mtd->ingress.tbl)
12386 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12387 if (mtd->ingress.sfx_tbl)
12388 flow_dv_tbl_resource_release(MLX5_SH(dev),
12389 mtd->ingress.sfx_tbl);
12390 if (mtd->transfer.color_matcher)
12391 claim_zero(mlx5_flow_os_destroy_flow_matcher
12392 (mtd->transfer.color_matcher));
12393 if (mtd->transfer.any_matcher)
12394 claim_zero(mlx5_flow_os_destroy_flow_matcher
12395 (mtd->transfer.any_matcher));
12396 if (mtd->transfer.tbl)
12397 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12398 if (mtd->transfer.sfx_tbl)
12399 flow_dv_tbl_resource_release(MLX5_SH(dev),
12400 mtd->transfer.sfx_tbl);
12401 if (mtd->drop_actn)
12402 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12407 /* Number of meter flow actions, count and jump or count and drop. */
12408 #define METER_ACTIONS 2
12411 * Create specify domain meter table and suffix table.
12414 * Pointer to Ethernet device.
12415 * @param[in,out] mtb
12416 * Pointer to DV meter table set.
12417 * @param[in] egress
12419 * @param[in] transfer
12421 * @param[in] color_reg_c_idx
12422 * Reg C index for color match.
12425 * 0 on success, -1 otherwise and rte_errno is set.
12428 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12429 struct mlx5_meter_domains_infos *mtb,
12430 uint8_t egress, uint8_t transfer,
12431 uint32_t color_reg_c_idx)
12433 struct mlx5_priv *priv = dev->data->dev_private;
12434 struct mlx5_dev_ctx_shared *sh = priv->sh;
12435 struct mlx5_flow_dv_match_params mask = {
12436 .size = sizeof(mask.buf),
12438 struct mlx5_flow_dv_match_params value = {
12439 .size = sizeof(value.buf),
12441 struct mlx5dv_flow_matcher_attr dv_attr = {
12442 .type = IBV_FLOW_ATTR_NORMAL,
12444 .match_criteria_enable = 0,
12445 .match_mask = (void *)&mask,
12447 void *actions[METER_ACTIONS];
12448 struct mlx5_meter_domain_info *dtb;
12449 struct rte_flow_error error;
12454 dtb = &mtb->transfer;
12456 dtb = &mtb->egress;
12458 dtb = &mtb->ingress;
12459 /* Create the meter table with METER level. */
12460 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12461 egress, transfer, false, NULL, 0,
12464 DRV_LOG(ERR, "Failed to create meter policer table.");
12467 /* Create the meter suffix table with SUFFIX level. */
12468 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12469 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12470 egress, transfer, false, NULL, 0,
12472 if (!dtb->sfx_tbl) {
12473 DRV_LOG(ERR, "Failed to create meter suffix table.");
12476 /* Create matchers, Any and Color. */
12477 dv_attr.priority = 3;
12478 dv_attr.match_criteria_enable = 0;
12479 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12480 &dtb->any_matcher);
12482 DRV_LOG(ERR, "Failed to create meter"
12483 " policer default matcher.");
12486 dv_attr.priority = 0;
12487 dv_attr.match_criteria_enable =
12488 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12489 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12490 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12491 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12492 &dtb->color_matcher);
12494 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12497 if (mtb->count_actns[RTE_MTR_DROPPED])
12498 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12499 actions[i++] = mtb->drop_actn;
12500 /* Default rule: lowest priority, match any, actions: drop. */
12501 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12503 &dtb->policer_rules[RTE_MTR_DROPPED]);
12505 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12514 * Create the needed meter and suffix tables.
12515 * Lock free, (mutex should be acquired by caller).
12518 * Pointer to Ethernet device.
12520 * Pointer to the flow meter.
12523 * Pointer to table set on success, NULL otherwise and rte_errno is set.
12525 static struct mlx5_meter_domains_infos *
12526 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12527 const struct mlx5_flow_meter *fm)
12529 struct mlx5_priv *priv = dev->data->dev_private;
12530 struct mlx5_meter_domains_infos *mtb;
12534 if (!priv->mtr_en) {
12535 rte_errno = ENOTSUP;
12538 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12540 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12543 /* Create meter count actions */
12544 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12545 struct mlx5_flow_counter *cnt;
12546 if (!fm->policer_stats.cnt[i])
12548 cnt = flow_dv_counter_get_by_idx(dev,
12549 fm->policer_stats.cnt[i], NULL);
12550 mtb->count_actns[i] = cnt->action;
12552 /* Create drop action. */
12553 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12555 DRV_LOG(ERR, "Failed to create drop action.");
12558 /* Egress meter table. */
12559 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12561 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12564 /* Ingress meter table. */
12565 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12567 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12570 /* FDB meter table. */
12571 if (priv->config.dv_esw_en) {
12572 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12573 priv->mtr_color_reg);
12575 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12581 flow_dv_destroy_mtr_tbl(dev, mtb);
12586 * Destroy domain policer rule.
12589 * Pointer to domain table.
12592 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12596 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12597 if (dt->policer_rules[i]) {
12598 claim_zero(mlx5_flow_os_destroy_flow
12599 (dt->policer_rules[i]));
12600 dt->policer_rules[i] = NULL;
12603 if (dt->jump_actn) {
12604 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12605 dt->jump_actn = NULL;
12610 * Destroy policer rules.
12613 * Pointer to Ethernet device.
12615 * Pointer to flow meter structure.
12617 * Pointer to flow attributes.
12623 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12624 const struct mlx5_flow_meter *fm,
12625 const struct rte_flow_attr *attr)
12627 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12632 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12634 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12635 if (attr->transfer)
12636 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12641 * Create specify domain meter policer rule.
12644 * Pointer to flow meter structure.
12646 * Pointer to DV meter table set.
12647 * @param[in] mtr_reg_c
12648 * Color match REG_C.
12651 * 0 on success, -1 otherwise.
12654 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12655 struct mlx5_meter_domain_info *dtb,
12658 struct mlx5_flow_dv_match_params matcher = {
12659 .size = sizeof(matcher.buf),
12661 struct mlx5_flow_dv_match_params value = {
12662 .size = sizeof(value.buf),
12664 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12665 void *actions[METER_ACTIONS];
12669 /* Create jump action. */
12670 if (!dtb->jump_actn)
12671 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12672 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12674 DRV_LOG(ERR, "Failed to create policer jump action.");
12677 for (i = 0; i < RTE_MTR_DROPPED; i++) {
12680 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12681 rte_col_2_mlx5_col(i), UINT8_MAX);
12682 if (mtb->count_actns[i])
12683 actions[j++] = mtb->count_actns[i];
12684 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12685 actions[j++] = mtb->drop_actn;
12687 actions[j++] = dtb->jump_actn;
12688 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12689 (void *)&value, j, actions,
12690 &dtb->policer_rules[i]);
12692 DRV_LOG(ERR, "Failed to create policer rule.");
12703 * Create policer rules.
12706 * Pointer to Ethernet device.
12708 * Pointer to flow meter structure.
12710 * Pointer to flow attributes.
12713 * 0 on success, -1 otherwise.
12716 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12717 struct mlx5_flow_meter *fm,
12718 const struct rte_flow_attr *attr)
12720 struct mlx5_priv *priv = dev->data->dev_private;
12721 struct mlx5_meter_domains_infos *mtb = fm->mfts;
12724 if (attr->egress) {
12725 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12726 priv->mtr_color_reg);
12728 DRV_LOG(ERR, "Failed to create egress policer.");
12732 if (attr->ingress) {
12733 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12734 priv->mtr_color_reg);
12736 DRV_LOG(ERR, "Failed to create ingress policer.");
12740 if (attr->transfer) {
12741 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12742 priv->mtr_color_reg);
12744 DRV_LOG(ERR, "Failed to create transfer policer.");
12750 flow_dv_destroy_policer_rules(dev, fm, attr);
12755 * Validate the batch counter support in root table.
12757 * Create a simple flow with invalid counter and drop action on root table to
12758 * validate if batch counter with offset on root table is supported or not.
12761 * Pointer to rte_eth_dev structure.
12764 * 0 on success, a negative errno value otherwise and rte_errno is set.
12767 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12769 struct mlx5_priv *priv = dev->data->dev_private;
12770 struct mlx5_dev_ctx_shared *sh = priv->sh;
12771 struct mlx5_flow_dv_match_params mask = {
12772 .size = sizeof(mask.buf),
12774 struct mlx5_flow_dv_match_params value = {
12775 .size = sizeof(value.buf),
12777 struct mlx5dv_flow_matcher_attr dv_attr = {
12778 .type = IBV_FLOW_ATTR_NORMAL,
12780 .match_criteria_enable = 0,
12781 .match_mask = (void *)&mask,
12783 void *actions[2] = { 0 };
12784 struct mlx5_flow_tbl_resource *tbl = NULL;
12785 struct mlx5_devx_obj *dcs = NULL;
12786 void *matcher = NULL;
12790 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12793 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12796 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12800 actions[1] = priv->drop_queue.hrxq->action;
12801 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12802 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12806 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12810 * If batch counter with offset is not supported, the driver will not
12811 * validate the invalid offset value, flow create should success.
12812 * In this case, it means batch counter is not supported in root table.
12814 * Otherwise, if flow create is failed, counter offset is supported.
12817 DRV_LOG(INFO, "Batch counter is not supported in root "
12818 "table. Switch to fallback mode.");
12819 rte_errno = ENOTSUP;
12821 claim_zero(mlx5_flow_os_destroy_flow(flow));
12823 /* Check matcher to make sure validate fail at flow create. */
12824 if (!matcher || (matcher && errno != EINVAL))
12825 DRV_LOG(ERR, "Unexpected error in counter offset "
12826 "support detection");
12830 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12832 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12834 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12836 claim_zero(mlx5_devx_cmd_destroy(dcs));
12841 * Query a devx counter.
12844 * Pointer to the Ethernet device structure.
12846 * Index to the flow counter.
12848 * Set to clear the counter statistics.
12850 * The statistics value of packets.
12851 * @param[out] bytes
12852 * The statistics value of bytes.
12855 * 0 on success, otherwise return -1.
12858 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12859 uint64_t *pkts, uint64_t *bytes)
12861 struct mlx5_priv *priv = dev->data->dev_private;
12862 struct mlx5_flow_counter *cnt;
12863 uint64_t inn_pkts, inn_bytes;
12866 if (!priv->config.devx)
12869 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12872 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12873 *pkts = inn_pkts - cnt->hits;
12874 *bytes = inn_bytes - cnt->bytes;
12876 cnt->hits = inn_pkts;
12877 cnt->bytes = inn_bytes;
12883 * Get aged-out flows.
12886 * Pointer to the Ethernet device structure.
12887 * @param[in] context
12888 * The address of an array of pointers to the aged-out flows contexts.
12889 * @param[in] nb_contexts
12890 * The length of context array pointers.
12891 * @param[out] error
12892 * Perform verbose error reporting if not NULL. Initialized in case of
12896 * how many contexts get in success, otherwise negative errno value.
12897 * if nb_contexts is 0, return the amount of all aged contexts.
12898 * if nb_contexts is not 0 , return the amount of aged flows reported
12899 * in the context array.
12900 * @note: only stub for now
12903 flow_get_aged_flows(struct rte_eth_dev *dev,
12905 uint32_t nb_contexts,
12906 struct rte_flow_error *error)
12908 struct mlx5_priv *priv = dev->data->dev_private;
12909 struct mlx5_age_info *age_info;
12910 struct mlx5_age_param *age_param;
12911 struct mlx5_flow_counter *counter;
12912 struct mlx5_aso_age_action *act;
12915 if (nb_contexts && !context)
12916 return rte_flow_error_set(error, EINVAL,
12917 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12918 NULL, "empty context");
12919 age_info = GET_PORT_AGE_INFO(priv);
12920 rte_spinlock_lock(&age_info->aged_sl);
12921 LIST_FOREACH(act, &age_info->aged_aso, next) {
12924 context[nb_flows - 1] =
12925 act->age_params.context;
12926 if (!(--nb_contexts))
12930 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12933 age_param = MLX5_CNT_TO_AGE(counter);
12934 context[nb_flows - 1] = age_param->context;
12935 if (!(--nb_contexts))
12939 rte_spinlock_unlock(&age_info->aged_sl);
12940 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12945 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12948 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12950 return flow_dv_counter_alloc(dev, 0);
12954 * Validate shared action.
12955 * Dispatcher for action type specific validation.
12958 * Pointer to the Ethernet device structure.
12960 * Shared action configuration.
12961 * @param[in] action
12962 * The shared action object to validate.
12963 * @param[out] error
12964 * Perform verbose error reporting if not NULL. Initialized in case of
12968 * 0 on success, otherwise negative errno value.
12971 flow_dv_action_validate(struct rte_eth_dev *dev,
12972 const struct rte_flow_shared_action_conf *conf,
12973 const struct rte_flow_action *action,
12974 struct rte_flow_error *err)
12976 struct mlx5_priv *priv = dev->data->dev_private;
12978 RTE_SET_USED(conf);
12979 switch (action->type) {
12980 case RTE_FLOW_ACTION_TYPE_RSS:
12981 return mlx5_validate_action_rss(dev, action, err);
12982 case RTE_FLOW_ACTION_TYPE_AGE:
12983 if (!priv->sh->aso_age_mng)
12984 return rte_flow_error_set(err, ENOTSUP,
12985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12987 "shared age action not supported");
12988 return flow_dv_validate_action_age(0, action, dev, err);
12990 return rte_flow_error_set(err, ENOTSUP,
12991 RTE_FLOW_ERROR_TYPE_ACTION,
12993 "action type not supported");
12998 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13000 struct mlx5_priv *priv = dev->data->dev_private;
13003 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13004 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13009 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13010 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13014 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13015 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13022 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13023 .validate = flow_dv_validate,
13024 .prepare = flow_dv_prepare,
13025 .translate = flow_dv_translate,
13026 .apply = flow_dv_apply,
13027 .remove = flow_dv_remove,
13028 .destroy = flow_dv_destroy,
13029 .query = flow_dv_query,
13030 .create_mtr_tbls = flow_dv_create_mtr_tbl,
13031 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13032 .create_policer_rules = flow_dv_create_policer_rules,
13033 .destroy_policer_rules = flow_dv_destroy_policer_rules,
13034 .counter_alloc = flow_dv_counter_allocate,
13035 .counter_free = flow_dv_counter_free,
13036 .counter_query = flow_dv_counter_query,
13037 .get_aged_flows = flow_get_aged_flows,
13038 .action_validate = flow_dv_action_validate,
13039 .action_create = flow_dv_action_create,
13040 .action_destroy = flow_dv_action_destroy,
13041 .action_update = flow_dv_action_update,
13042 .action_query = flow_dv_action_query,
13043 .sync_domain = flow_dv_sync_domain,
13046 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */