1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_dv_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_NONE] = MLX5_MODI_OUT_NONE,
836 [REG_A] = MLX5_MODI_META_DATA_REG_A,
837 [REG_B] = MLX5_MODI_META_DATA_REG_B,
838 [REG_C_0] = MLX5_MODI_META_REG_C_0,
839 [REG_C_1] = MLX5_MODI_META_REG_C_1,
840 [REG_C_2] = MLX5_MODI_META_REG_C_2,
841 [REG_C_3] = MLX5_MODI_META_REG_C_3,
842 [REG_C_4] = MLX5_MODI_META_REG_C_4,
843 [REG_C_5] = MLX5_MODI_META_REG_C_5,
844 [REG_C_6] = MLX5_MODI_META_REG_C_6,
845 [REG_C_7] = MLX5_MODI_META_REG_C_7,
849 * Convert register set to DV specification.
851 * @param[in,out] resource
852 * Pointer to the modify-header resource.
854 * Pointer to action specification.
856 * Pointer to the error structure.
859 * 0 on success, a negative errno value otherwise and rte_errno is set.
862 flow_dv_convert_action_set_reg
863 (struct mlx5_flow_dv_modify_hdr_resource *resource,
864 const struct rte_flow_action *action,
865 struct rte_flow_error *error)
867 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
868 struct mlx5_modification_cmd *actions = resource->actions;
869 uint32_t i = resource->actions_num;
871 if (i >= MLX5_MODIFY_NUM)
872 return rte_flow_error_set(error, EINVAL,
873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
874 "too many items to modify");
875 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
876 actions[i].field = reg_to_field[conf->id];
877 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
878 actions[i].data1 = conf->data;
880 resource->actions_num = i;
881 if (!resource->actions_num)
882 return rte_flow_error_set(error, EINVAL,
883 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
884 "invalid modification flow item");
889 * Convert internal COPY_REG action to DV specification.
892 * Pointer to the rte_eth_dev structure.
894 * Pointer to the modify-header resource.
896 * Pointer to action specification.
898 * Pointer to the error structure.
901 * 0 on success, a negative errno value otherwise and rte_errno is set.
904 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
905 struct mlx5_flow_dv_modify_hdr_resource *res,
906 const struct rte_flow_action *action,
907 struct rte_flow_error *error)
909 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
910 rte_be32_t mask = RTE_BE32(UINT32_MAX);
911 struct rte_flow_item item = {
915 struct field_modify_info reg_src[] = {
916 {4, 0, reg_to_field[conf->src]},
919 struct field_modify_info reg_dst = {
921 .id = reg_to_field[conf->dst],
923 /* Adjust reg_c[0] usage according to reported mask. */
924 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
925 struct mlx5_priv *priv = dev->data->dev_private;
926 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
929 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
930 if (conf->dst == REG_C_0) {
931 /* Copy to reg_c[0], within mask only. */
932 reg_dst.offset = rte_bsf32(reg_c0);
934 * Mask is ignoring the enianness, because
935 * there is no conversion in datapath.
937 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
938 /* Copy from destination lower bits to reg_c[0]. */
939 mask = reg_c0 >> reg_dst.offset;
941 /* Copy from destination upper bits to reg_c[0]. */
942 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
943 rte_fls_u32(reg_c0));
946 mask = rte_cpu_to_be_32(reg_c0);
947 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
948 /* Copy from reg_c[0] to destination lower bits. */
951 /* Copy from reg_c[0] to destination upper bits. */
952 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
953 (rte_fls_u32(reg_c0) -
958 return flow_dv_convert_modify_action(&item,
959 reg_src, ®_dst, res,
960 MLX5_MODIFICATION_TYPE_COPY,
965 * Validate META item.
968 * Pointer to the rte_eth_dev structure.
970 * Item specification.
972 * Attributes of flow that includes this item.
974 * Pointer to error structure.
977 * 0 on success, a negative errno value otherwise and rte_errno is set.
980 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
981 const struct rte_flow_item *item,
982 const struct rte_flow_attr *attr,
983 struct rte_flow_error *error)
985 const struct rte_flow_item_meta *spec = item->spec;
986 const struct rte_flow_item_meta *mask = item->mask;
987 const struct rte_flow_item_meta nic_mask = {
993 return rte_flow_error_set(error, EINVAL,
994 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
996 "data cannot be empty");
998 return rte_flow_error_set(error, EINVAL,
999 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1001 "data cannot be zero");
1003 mask = &rte_flow_item_meta_mask;
1004 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1005 (const uint8_t *)&nic_mask,
1006 sizeof(struct rte_flow_item_meta),
1011 return rte_flow_error_set(error, ENOTSUP,
1012 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1014 "pattern not supported for ingress");
1019 * Validate vport item.
1022 * Pointer to the rte_eth_dev structure.
1024 * Item specification.
1026 * Attributes of flow that includes this item.
1027 * @param[in] item_flags
1028 * Bit-fields that holds the items detected until now.
1030 * Pointer to error structure.
1033 * 0 on success, a negative errno value otherwise and rte_errno is set.
1036 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1037 const struct rte_flow_item *item,
1038 const struct rte_flow_attr *attr,
1039 uint64_t item_flags,
1040 struct rte_flow_error *error)
1042 const struct rte_flow_item_port_id *spec = item->spec;
1043 const struct rte_flow_item_port_id *mask = item->mask;
1044 const struct rte_flow_item_port_id switch_mask = {
1047 struct mlx5_priv *esw_priv;
1048 struct mlx5_priv *dev_priv;
1051 if (!attr->transfer)
1052 return rte_flow_error_set(error, EINVAL,
1053 RTE_FLOW_ERROR_TYPE_ITEM,
1055 "match on port id is valid only"
1056 " when transfer flag is enabled");
1057 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1058 return rte_flow_error_set(error, ENOTSUP,
1059 RTE_FLOW_ERROR_TYPE_ITEM, item,
1060 "multiple source ports are not"
1063 mask = &switch_mask;
1064 if (mask->id != 0xffffffff)
1065 return rte_flow_error_set(error, ENOTSUP,
1066 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1068 "no support for partial mask on"
1070 ret = mlx5_flow_item_acceptable
1071 (item, (const uint8_t *)mask,
1072 (const uint8_t *)&rte_flow_item_port_id_mask,
1073 sizeof(struct rte_flow_item_port_id),
1079 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1081 return rte_flow_error_set(error, rte_errno,
1082 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1083 "failed to obtain E-Switch info for"
1085 dev_priv = mlx5_dev_to_eswitch_info(dev);
1087 return rte_flow_error_set(error, rte_errno,
1088 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1090 "failed to obtain E-Switch info");
1091 if (esw_priv->domain_id != dev_priv->domain_id)
1092 return rte_flow_error_set(error, EINVAL,
1093 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1094 "cannot match on a port from a"
1095 " different E-Switch");
1100 * Validate the pop VLAN action.
1103 * Pointer to the rte_eth_dev structure.
1104 * @param[in] action_flags
1105 * Holds the actions detected until now.
1107 * Pointer to the pop vlan action.
1108 * @param[in] item_flags
1109 * The items found in this flow rule.
1111 * Pointer to flow attributes.
1113 * Pointer to error structure.
1116 * 0 on success, a negative errno value otherwise and rte_errno is set.
1119 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1120 uint64_t action_flags,
1121 const struct rte_flow_action *action,
1122 uint64_t item_flags,
1123 const struct rte_flow_attr *attr,
1124 struct rte_flow_error *error)
1126 struct mlx5_priv *priv = dev->data->dev_private;
1130 if (!priv->sh->pop_vlan_action)
1131 return rte_flow_error_set(error, ENOTSUP,
1132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1134 "pop vlan action is not supported");
1136 * Check for inconsistencies:
1137 * fail strip_vlan in a flow that matches packets without VLAN tags.
1138 * fail strip_vlan in a flow that matches packets without explicitly a
1139 * matching on VLAN tag ?
1141 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1142 return rte_flow_error_set(error, ENOTSUP,
1143 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1145 "no support for multiple vlan pop "
1147 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1148 return rte_flow_error_set(error, ENOTSUP,
1149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1151 "cannot pop vlan without a "
1152 "match on (outer) vlan in the flow");
1153 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1154 return rte_flow_error_set(error, EINVAL,
1155 RTE_FLOW_ERROR_TYPE_ACTION, action,
1156 "wrong action order, port_id should "
1157 "be after pop VLAN action");
1162 * Get VLAN default info from vlan match info.
1165 * Pointer to the rte_eth_dev structure.
1167 * the list of item specifications.
1169 * pointer VLAN info to fill to.
1171 * Pointer to error structure.
1174 * 0 on success, a negative errno value otherwise and rte_errno is set.
1177 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1178 struct rte_vlan_hdr *vlan)
1180 const struct rte_flow_item_vlan nic_mask = {
1181 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1182 MLX5DV_FLOW_VLAN_VID_MASK),
1183 .inner_type = RTE_BE16(0xffff),
1188 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1189 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1191 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1192 const struct rte_flow_item_vlan *vlan_m = items->mask;
1193 const struct rte_flow_item_vlan *vlan_v = items->spec;
1197 /* Only full match values are accepted */
1198 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1199 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1200 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1202 rte_be_to_cpu_16(vlan_v->tci &
1203 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1205 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1206 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1207 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1209 rte_be_to_cpu_16(vlan_v->tci &
1210 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1212 if (vlan_m->inner_type == nic_mask.inner_type)
1213 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1214 vlan_m->inner_type);
1219 * Validate the push VLAN action.
1221 * @param[in] action_flags
1222 * Holds the actions detected until now.
1224 * Pointer to the encap action.
1226 * Pointer to flow attributes
1228 * Pointer to error structure.
1231 * 0 on success, a negative errno value otherwise and rte_errno is set.
1234 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1235 uint64_t item_flags,
1236 const struct rte_flow_action *action,
1237 const struct rte_flow_attr *attr,
1238 struct rte_flow_error *error)
1240 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1242 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1243 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1244 return rte_flow_error_set(error, EINVAL,
1245 RTE_FLOW_ERROR_TYPE_ACTION, action,
1246 "invalid vlan ethertype");
1248 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1249 return rte_flow_error_set(error, ENOTSUP,
1250 RTE_FLOW_ERROR_TYPE_ACTION, action,
1251 "no support for multiple VLAN "
1253 if (!mlx5_flow_find_action
1254 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1255 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1256 return rte_flow_error_set(error, ENOTSUP,
1257 RTE_FLOW_ERROR_TYPE_ACTION, action,
1258 "push VLAN needs to match on VLAN in order to "
1259 "get VLAN VID information because there is "
1260 "no followed set VLAN VID action");
1261 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1262 return rte_flow_error_set(error, EINVAL,
1263 RTE_FLOW_ERROR_TYPE_ACTION, action,
1264 "wrong action order, port_id should "
1265 "be after push VLAN");
1271 * Validate the set VLAN PCP.
1273 * @param[in] action_flags
1274 * Holds the actions detected until now.
1275 * @param[in] actions
1276 * Pointer to the list of actions remaining in the flow rule.
1278 * Pointer to flow attributes
1280 * Pointer to error structure.
1283 * 0 on success, a negative errno value otherwise and rte_errno is set.
1286 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1287 const struct rte_flow_action actions[],
1288 struct rte_flow_error *error)
1290 const struct rte_flow_action *action = actions;
1291 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1293 if (conf->vlan_pcp > 7)
1294 return rte_flow_error_set(error, EINVAL,
1295 RTE_FLOW_ERROR_TYPE_ACTION, action,
1296 "VLAN PCP value is too big");
1297 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1298 return rte_flow_error_set(error, ENOTSUP,
1299 RTE_FLOW_ERROR_TYPE_ACTION, action,
1300 "set VLAN PCP action must follow "
1301 "the push VLAN action");
1302 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1303 return rte_flow_error_set(error, ENOTSUP,
1304 RTE_FLOW_ERROR_TYPE_ACTION, action,
1305 "Multiple VLAN PCP modification are "
1307 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1308 return rte_flow_error_set(error, EINVAL,
1309 RTE_FLOW_ERROR_TYPE_ACTION, action,
1310 "wrong action order, port_id should "
1311 "be after set VLAN PCP");
1316 * Validate the set VLAN VID.
1318 * @param[in] item_flags
1319 * Holds the items detected in this rule.
1320 * @param[in] actions
1321 * Pointer to the list of actions remaining in the flow rule.
1323 * Pointer to flow attributes
1325 * Pointer to error structure.
1328 * 0 on success, a negative errno value otherwise and rte_errno is set.
1331 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1332 uint64_t action_flags,
1333 const struct rte_flow_action actions[],
1334 struct rte_flow_error *error)
1336 const struct rte_flow_action *action = actions;
1337 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1339 if (conf->vlan_vid > RTE_BE16(0xFFE))
1340 return rte_flow_error_set(error, EINVAL,
1341 RTE_FLOW_ERROR_TYPE_ACTION, action,
1342 "VLAN VID value is too big");
1343 /* there is an of_push_vlan action before us */
1344 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1345 if (mlx5_flow_find_action(actions + 1,
1346 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1347 return rte_flow_error_set(error, ENOTSUP,
1348 RTE_FLOW_ERROR_TYPE_ACTION, action,
1349 "Multiple VLAN VID modifications are "
1356 * Action is on an existing VLAN header:
1357 * Need to verify this is a single modify CID action.
1358 * Rule mast include a match on outer VLAN.
1360 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1361 return rte_flow_error_set(error, ENOTSUP,
1362 RTE_FLOW_ERROR_TYPE_ACTION, action,
1363 "Multiple VLAN VID modifications are "
1365 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1366 return rte_flow_error_set(error, EINVAL,
1367 RTE_FLOW_ERROR_TYPE_ACTION, action,
1368 "match on VLAN is required in order "
1370 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1371 return rte_flow_error_set(error, EINVAL,
1372 RTE_FLOW_ERROR_TYPE_ACTION, action,
1373 "wrong action order, port_id should "
1374 "be after set VLAN VID");
1379 * Validate count action.
1384 * Pointer to error structure.
1387 * 0 on success, a negative errno value otherwise and rte_errno is set.
1390 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1391 struct rte_flow_error *error)
1393 struct mlx5_priv *priv = dev->data->dev_private;
1395 if (!priv->config.devx)
1397 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1401 return rte_flow_error_set
1403 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1405 "count action not supported");
1409 * Validate the L2 encap action.
1411 * @param[in] action_flags
1412 * Holds the actions detected until now.
1414 * Pointer to the encap action.
1416 * Pointer to flow attributes
1418 * Pointer to error structure.
1421 * 0 on success, a negative errno value otherwise and rte_errno is set.
1424 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1425 const struct rte_flow_action *action,
1426 const struct rte_flow_attr *attr,
1427 struct rte_flow_error *error)
1429 if (!(action->conf))
1430 return rte_flow_error_set(error, EINVAL,
1431 RTE_FLOW_ERROR_TYPE_ACTION, action,
1432 "configuration cannot be null");
1433 if (action_flags & MLX5_FLOW_ACTION_DROP)
1434 return rte_flow_error_set(error, EINVAL,
1435 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1436 "can't drop and encap in same flow");
1437 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1438 return rte_flow_error_set(error, EINVAL,
1439 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1440 "can only have a single encap or"
1441 " decap action in a flow");
1442 if (!attr->transfer && attr->ingress)
1443 return rte_flow_error_set(error, ENOTSUP,
1444 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1446 "encap action not supported for "
1452 * Validate the L2 decap action.
1454 * @param[in] action_flags
1455 * Holds the actions detected until now.
1457 * Pointer to flow attributes
1459 * Pointer to error structure.
1462 * 0 on success, a negative errno value otherwise and rte_errno is set.
1465 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1466 const struct rte_flow_attr *attr,
1467 struct rte_flow_error *error)
1469 if (action_flags & MLX5_FLOW_ACTION_DROP)
1470 return rte_flow_error_set(error, EINVAL,
1471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1472 "can't drop and decap in same flow");
1473 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1474 return rte_flow_error_set(error, EINVAL,
1475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1476 "can only have a single encap or"
1477 " decap action in a flow");
1478 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1479 return rte_flow_error_set(error, EINVAL,
1480 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1481 "can't have decap action after"
1484 return rte_flow_error_set(error, ENOTSUP,
1485 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1487 "decap action not supported for "
1493 * Validate the raw encap action.
1495 * @param[in] action_flags
1496 * Holds the actions detected until now.
1498 * Pointer to the encap action.
1500 * Pointer to flow attributes
1502 * Pointer to error structure.
1505 * 0 on success, a negative errno value otherwise and rte_errno is set.
1508 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1509 const struct rte_flow_action *action,
1510 const struct rte_flow_attr *attr,
1511 struct rte_flow_error *error)
1513 const struct rte_flow_action_raw_encap *raw_encap =
1514 (const struct rte_flow_action_raw_encap *)action->conf;
1515 if (!(action->conf))
1516 return rte_flow_error_set(error, EINVAL,
1517 RTE_FLOW_ERROR_TYPE_ACTION, action,
1518 "configuration cannot be null");
1519 if (action_flags & MLX5_FLOW_ACTION_DROP)
1520 return rte_flow_error_set(error, EINVAL,
1521 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1522 "can't drop and encap in same flow");
1523 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1524 return rte_flow_error_set(error, EINVAL,
1525 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1526 "can only have a single encap"
1527 " action in a flow");
1528 /* encap without preceding decap is not supported for ingress */
1529 if (!attr->transfer && attr->ingress &&
1530 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1531 return rte_flow_error_set(error, ENOTSUP,
1532 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1534 "encap action not supported for "
1536 if (!raw_encap->size || !raw_encap->data)
1537 return rte_flow_error_set(error, EINVAL,
1538 RTE_FLOW_ERROR_TYPE_ACTION, action,
1539 "raw encap data cannot be empty");
1544 * Validate the raw decap action.
1546 * @param[in] action_flags
1547 * Holds the actions detected until now.
1549 * Pointer to the encap action.
1551 * Pointer to flow attributes
1553 * Pointer to error structure.
1556 * 0 on success, a negative errno value otherwise and rte_errno is set.
1559 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1560 const struct rte_flow_action *action,
1561 const struct rte_flow_attr *attr,
1562 struct rte_flow_error *error)
1564 if (action_flags & MLX5_FLOW_ACTION_DROP)
1565 return rte_flow_error_set(error, EINVAL,
1566 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1567 "can't drop and decap in same flow");
1568 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1569 return rte_flow_error_set(error, EINVAL,
1570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1571 "can't have encap action before"
1573 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1574 return rte_flow_error_set(error, EINVAL,
1575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1576 "can only have a single decap"
1577 " action in a flow");
1578 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1579 return rte_flow_error_set(error, EINVAL,
1580 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1581 "can't have decap action after"
1583 /* decap action is valid on egress only if it is followed by encap */
1585 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1586 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1589 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1590 return rte_flow_error_set
1592 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1593 NULL, "decap action not supported"
1600 * Find existing encap/decap resource or create and register a new one.
1602 * @param dev[in, out]
1603 * Pointer to rte_eth_dev structure.
1604 * @param[in, out] resource
1605 * Pointer to encap/decap resource.
1606 * @parm[in, out] dev_flow
1607 * Pointer to the dev_flow.
1609 * pointer to error structure.
1612 * 0 on success otherwise -errno and errno is set.
1615 flow_dv_encap_decap_resource_register
1616 (struct rte_eth_dev *dev,
1617 struct mlx5_flow_dv_encap_decap_resource *resource,
1618 struct mlx5_flow *dev_flow,
1619 struct rte_flow_error *error)
1621 struct mlx5_priv *priv = dev->data->dev_private;
1622 struct mlx5_ibv_shared *sh = priv->sh;
1623 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1624 struct mlx5dv_dr_domain *domain;
1626 resource->flags = dev_flow->group ? 0 : 1;
1627 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1628 domain = sh->fdb_domain;
1629 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1630 domain = sh->rx_domain;
1632 domain = sh->tx_domain;
1634 /* Lookup a matching resource from cache. */
1635 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1636 if (resource->reformat_type == cache_resource->reformat_type &&
1637 resource->ft_type == cache_resource->ft_type &&
1638 resource->flags == cache_resource->flags &&
1639 resource->size == cache_resource->size &&
1640 !memcmp((const void *)resource->buf,
1641 (const void *)cache_resource->buf,
1643 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1644 (void *)cache_resource,
1645 rte_atomic32_read(&cache_resource->refcnt));
1646 rte_atomic32_inc(&cache_resource->refcnt);
1647 dev_flow->dv.encap_decap = cache_resource;
1651 /* Register new encap/decap resource. */
1652 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1653 if (!cache_resource)
1654 return rte_flow_error_set(error, ENOMEM,
1655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1656 "cannot allocate resource memory");
1657 *cache_resource = *resource;
1658 cache_resource->verbs_action =
1659 mlx5_glue->dv_create_flow_action_packet_reformat
1660 (sh->ctx, cache_resource->reformat_type,
1661 cache_resource->ft_type, domain, cache_resource->flags,
1662 cache_resource->size,
1663 (cache_resource->size ? cache_resource->buf : NULL));
1664 if (!cache_resource->verbs_action) {
1665 rte_free(cache_resource);
1666 return rte_flow_error_set(error, ENOMEM,
1667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1668 NULL, "cannot create action");
1670 rte_atomic32_init(&cache_resource->refcnt);
1671 rte_atomic32_inc(&cache_resource->refcnt);
1672 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1673 dev_flow->dv.encap_decap = cache_resource;
1674 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1675 (void *)cache_resource,
1676 rte_atomic32_read(&cache_resource->refcnt));
1681 * Find existing table jump resource or create and register a new one.
1683 * @param dev[in, out]
1684 * Pointer to rte_eth_dev structure.
1685 * @param[in, out] resource
1686 * Pointer to jump table resource.
1687 * @parm[in, out] dev_flow
1688 * Pointer to the dev_flow.
1690 * pointer to error structure.
1693 * 0 on success otherwise -errno and errno is set.
1696 flow_dv_jump_tbl_resource_register
1697 (struct rte_eth_dev *dev,
1698 struct mlx5_flow_dv_jump_tbl_resource *resource,
1699 struct mlx5_flow *dev_flow,
1700 struct rte_flow_error *error)
1702 struct mlx5_priv *priv = dev->data->dev_private;
1703 struct mlx5_ibv_shared *sh = priv->sh;
1704 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1706 /* Lookup a matching resource from cache. */
1707 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1708 if (resource->tbl == cache_resource->tbl) {
1709 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1710 (void *)cache_resource,
1711 rte_atomic32_read(&cache_resource->refcnt));
1712 rte_atomic32_inc(&cache_resource->refcnt);
1713 dev_flow->dv.jump = cache_resource;
1717 /* Register new jump table resource. */
1718 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1719 if (!cache_resource)
1720 return rte_flow_error_set(error, ENOMEM,
1721 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1722 "cannot allocate resource memory");
1723 *cache_resource = *resource;
1724 cache_resource->action =
1725 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1726 (resource->tbl->obj);
1727 if (!cache_resource->action) {
1728 rte_free(cache_resource);
1729 return rte_flow_error_set(error, ENOMEM,
1730 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1731 NULL, "cannot create action");
1733 rte_atomic32_init(&cache_resource->refcnt);
1734 rte_atomic32_inc(&cache_resource->refcnt);
1735 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1736 dev_flow->dv.jump = cache_resource;
1737 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1738 (void *)cache_resource,
1739 rte_atomic32_read(&cache_resource->refcnt));
1744 * Find existing table port ID resource or create and register a new one.
1746 * @param dev[in, out]
1747 * Pointer to rte_eth_dev structure.
1748 * @param[in, out] resource
1749 * Pointer to port ID action resource.
1750 * @parm[in, out] dev_flow
1751 * Pointer to the dev_flow.
1753 * pointer to error structure.
1756 * 0 on success otherwise -errno and errno is set.
1759 flow_dv_port_id_action_resource_register
1760 (struct rte_eth_dev *dev,
1761 struct mlx5_flow_dv_port_id_action_resource *resource,
1762 struct mlx5_flow *dev_flow,
1763 struct rte_flow_error *error)
1765 struct mlx5_priv *priv = dev->data->dev_private;
1766 struct mlx5_ibv_shared *sh = priv->sh;
1767 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1769 /* Lookup a matching resource from cache. */
1770 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1771 if (resource->port_id == cache_resource->port_id) {
1772 DRV_LOG(DEBUG, "port id action resource resource %p: "
1774 (void *)cache_resource,
1775 rte_atomic32_read(&cache_resource->refcnt));
1776 rte_atomic32_inc(&cache_resource->refcnt);
1777 dev_flow->dv.port_id_action = cache_resource;
1781 /* Register new port id action resource. */
1782 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1783 if (!cache_resource)
1784 return rte_flow_error_set(error, ENOMEM,
1785 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1786 "cannot allocate resource memory");
1787 *cache_resource = *resource;
1788 cache_resource->action =
1789 mlx5_glue->dr_create_flow_action_dest_vport
1790 (priv->sh->fdb_domain, resource->port_id);
1791 if (!cache_resource->action) {
1792 rte_free(cache_resource);
1793 return rte_flow_error_set(error, ENOMEM,
1794 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1795 NULL, "cannot create action");
1797 rte_atomic32_init(&cache_resource->refcnt);
1798 rte_atomic32_inc(&cache_resource->refcnt);
1799 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1800 dev_flow->dv.port_id_action = cache_resource;
1801 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1802 (void *)cache_resource,
1803 rte_atomic32_read(&cache_resource->refcnt));
1808 * Find existing push vlan resource or create and register a new one.
1810 * @param dev[in, out]
1811 * Pointer to rte_eth_dev structure.
1812 * @param[in, out] resource
1813 * Pointer to port ID action resource.
1814 * @parm[in, out] dev_flow
1815 * Pointer to the dev_flow.
1817 * pointer to error structure.
1820 * 0 on success otherwise -errno and errno is set.
1823 flow_dv_push_vlan_action_resource_register
1824 (struct rte_eth_dev *dev,
1825 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1826 struct mlx5_flow *dev_flow,
1827 struct rte_flow_error *error)
1829 struct mlx5_priv *priv = dev->data->dev_private;
1830 struct mlx5_ibv_shared *sh = priv->sh;
1831 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1832 struct mlx5dv_dr_domain *domain;
1834 /* Lookup a matching resource from cache. */
1835 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1836 if (resource->vlan_tag == cache_resource->vlan_tag &&
1837 resource->ft_type == cache_resource->ft_type) {
1838 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1840 (void *)cache_resource,
1841 rte_atomic32_read(&cache_resource->refcnt));
1842 rte_atomic32_inc(&cache_resource->refcnt);
1843 dev_flow->dv.push_vlan_res = cache_resource;
1847 /* Register new push_vlan action resource. */
1848 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1849 if (!cache_resource)
1850 return rte_flow_error_set(error, ENOMEM,
1851 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1852 "cannot allocate resource memory");
1853 *cache_resource = *resource;
1854 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1855 domain = sh->fdb_domain;
1856 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1857 domain = sh->rx_domain;
1859 domain = sh->tx_domain;
1860 cache_resource->action =
1861 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1862 resource->vlan_tag);
1863 if (!cache_resource->action) {
1864 rte_free(cache_resource);
1865 return rte_flow_error_set(error, ENOMEM,
1866 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1867 NULL, "cannot create action");
1869 rte_atomic32_init(&cache_resource->refcnt);
1870 rte_atomic32_inc(&cache_resource->refcnt);
1871 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1872 dev_flow->dv.push_vlan_res = cache_resource;
1873 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1874 (void *)cache_resource,
1875 rte_atomic32_read(&cache_resource->refcnt));
1879 * Get the size of specific rte_flow_item_type
1881 * @param[in] item_type
1882 * Tested rte_flow_item_type.
1885 * sizeof struct item_type, 0 if void or irrelevant.
1888 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1892 switch (item_type) {
1893 case RTE_FLOW_ITEM_TYPE_ETH:
1894 retval = sizeof(struct rte_flow_item_eth);
1896 case RTE_FLOW_ITEM_TYPE_VLAN:
1897 retval = sizeof(struct rte_flow_item_vlan);
1899 case RTE_FLOW_ITEM_TYPE_IPV4:
1900 retval = sizeof(struct rte_flow_item_ipv4);
1902 case RTE_FLOW_ITEM_TYPE_IPV6:
1903 retval = sizeof(struct rte_flow_item_ipv6);
1905 case RTE_FLOW_ITEM_TYPE_UDP:
1906 retval = sizeof(struct rte_flow_item_udp);
1908 case RTE_FLOW_ITEM_TYPE_TCP:
1909 retval = sizeof(struct rte_flow_item_tcp);
1911 case RTE_FLOW_ITEM_TYPE_VXLAN:
1912 retval = sizeof(struct rte_flow_item_vxlan);
1914 case RTE_FLOW_ITEM_TYPE_GRE:
1915 retval = sizeof(struct rte_flow_item_gre);
1917 case RTE_FLOW_ITEM_TYPE_NVGRE:
1918 retval = sizeof(struct rte_flow_item_nvgre);
1920 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1921 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1923 case RTE_FLOW_ITEM_TYPE_MPLS:
1924 retval = sizeof(struct rte_flow_item_mpls);
1926 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1934 #define MLX5_ENCAP_IPV4_VERSION 0x40
1935 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1936 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1937 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1938 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1939 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1940 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1943 * Convert the encap action data from list of rte_flow_item to raw buffer
1946 * Pointer to rte_flow_item objects list.
1948 * Pointer to the output buffer.
1950 * Pointer to the output buffer size.
1952 * Pointer to the error structure.
1955 * 0 on success, a negative errno value otherwise and rte_errno is set.
1958 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1959 size_t *size, struct rte_flow_error *error)
1961 struct rte_ether_hdr *eth = NULL;
1962 struct rte_vlan_hdr *vlan = NULL;
1963 struct rte_ipv4_hdr *ipv4 = NULL;
1964 struct rte_ipv6_hdr *ipv6 = NULL;
1965 struct rte_udp_hdr *udp = NULL;
1966 struct rte_vxlan_hdr *vxlan = NULL;
1967 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1968 struct rte_gre_hdr *gre = NULL;
1970 size_t temp_size = 0;
1973 return rte_flow_error_set(error, EINVAL,
1974 RTE_FLOW_ERROR_TYPE_ACTION,
1975 NULL, "invalid empty data");
1976 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1977 len = flow_dv_get_item_len(items->type);
1978 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1979 return rte_flow_error_set(error, EINVAL,
1980 RTE_FLOW_ERROR_TYPE_ACTION,
1981 (void *)items->type,
1982 "items total size is too big"
1983 " for encap action");
1984 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1985 switch (items->type) {
1986 case RTE_FLOW_ITEM_TYPE_ETH:
1987 eth = (struct rte_ether_hdr *)&buf[temp_size];
1989 case RTE_FLOW_ITEM_TYPE_VLAN:
1990 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1992 return rte_flow_error_set(error, EINVAL,
1993 RTE_FLOW_ERROR_TYPE_ACTION,
1994 (void *)items->type,
1995 "eth header not found");
1996 if (!eth->ether_type)
1997 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1999 case RTE_FLOW_ITEM_TYPE_IPV4:
2000 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2002 return rte_flow_error_set(error, EINVAL,
2003 RTE_FLOW_ERROR_TYPE_ACTION,
2004 (void *)items->type,
2005 "neither eth nor vlan"
2007 if (vlan && !vlan->eth_proto)
2008 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2009 else if (eth && !eth->ether_type)
2010 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2011 if (!ipv4->version_ihl)
2012 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2013 MLX5_ENCAP_IPV4_IHL_MIN;
2014 if (!ipv4->time_to_live)
2015 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2017 case RTE_FLOW_ITEM_TYPE_IPV6:
2018 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2020 return rte_flow_error_set(error, EINVAL,
2021 RTE_FLOW_ERROR_TYPE_ACTION,
2022 (void *)items->type,
2023 "neither eth nor vlan"
2025 if (vlan && !vlan->eth_proto)
2026 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2027 else if (eth && !eth->ether_type)
2028 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2029 if (!ipv6->vtc_flow)
2031 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2032 if (!ipv6->hop_limits)
2033 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2035 case RTE_FLOW_ITEM_TYPE_UDP:
2036 udp = (struct rte_udp_hdr *)&buf[temp_size];
2038 return rte_flow_error_set(error, EINVAL,
2039 RTE_FLOW_ERROR_TYPE_ACTION,
2040 (void *)items->type,
2041 "ip header not found");
2042 if (ipv4 && !ipv4->next_proto_id)
2043 ipv4->next_proto_id = IPPROTO_UDP;
2044 else if (ipv6 && !ipv6->proto)
2045 ipv6->proto = IPPROTO_UDP;
2047 case RTE_FLOW_ITEM_TYPE_VXLAN:
2048 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2050 return rte_flow_error_set(error, EINVAL,
2051 RTE_FLOW_ERROR_TYPE_ACTION,
2052 (void *)items->type,
2053 "udp header not found");
2055 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2056 if (!vxlan->vx_flags)
2058 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2060 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2061 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2063 return rte_flow_error_set(error, EINVAL,
2064 RTE_FLOW_ERROR_TYPE_ACTION,
2065 (void *)items->type,
2066 "udp header not found");
2067 if (!vxlan_gpe->proto)
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION,
2070 (void *)items->type,
2071 "next protocol not found");
2074 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2075 if (!vxlan_gpe->vx_flags)
2076 vxlan_gpe->vx_flags =
2077 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2079 case RTE_FLOW_ITEM_TYPE_GRE:
2080 case RTE_FLOW_ITEM_TYPE_NVGRE:
2081 gre = (struct rte_gre_hdr *)&buf[temp_size];
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION,
2085 (void *)items->type,
2086 "next protocol not found");
2088 return rte_flow_error_set(error, EINVAL,
2089 RTE_FLOW_ERROR_TYPE_ACTION,
2090 (void *)items->type,
2091 "ip header not found");
2092 if (ipv4 && !ipv4->next_proto_id)
2093 ipv4->next_proto_id = IPPROTO_GRE;
2094 else if (ipv6 && !ipv6->proto)
2095 ipv6->proto = IPPROTO_GRE;
2097 case RTE_FLOW_ITEM_TYPE_VOID:
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ACTION,
2102 (void *)items->type,
2103 "unsupported item type");
2113 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2115 struct rte_ether_hdr *eth = NULL;
2116 struct rte_vlan_hdr *vlan = NULL;
2117 struct rte_ipv6_hdr *ipv6 = NULL;
2118 struct rte_udp_hdr *udp = NULL;
2122 eth = (struct rte_ether_hdr *)data;
2123 next_hdr = (char *)(eth + 1);
2124 proto = RTE_BE16(eth->ether_type);
2127 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2128 vlan = (struct rte_vlan_hdr *)next_hdr;
2129 proto = RTE_BE16(vlan->eth_proto);
2130 next_hdr += sizeof(struct rte_vlan_hdr);
2133 /* HW calculates IPv4 csum. no need to proceed */
2134 if (proto == RTE_ETHER_TYPE_IPV4)
2137 /* non IPv4/IPv6 header. not supported */
2138 if (proto != RTE_ETHER_TYPE_IPV6) {
2139 return rte_flow_error_set(error, ENOTSUP,
2140 RTE_FLOW_ERROR_TYPE_ACTION,
2141 NULL, "Cannot offload non IPv4/IPv6");
2144 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2146 /* ignore non UDP */
2147 if (ipv6->proto != IPPROTO_UDP)
2150 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2151 udp->dgram_cksum = 0;
2157 * Convert L2 encap action to DV specification.
2160 * Pointer to rte_eth_dev structure.
2162 * Pointer to action structure.
2163 * @param[in, out] dev_flow
2164 * Pointer to the mlx5_flow.
2165 * @param[in] transfer
2166 * Mark if the flow is E-Switch flow.
2168 * Pointer to the error structure.
2171 * 0 on success, a negative errno value otherwise and rte_errno is set.
2174 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2175 const struct rte_flow_action *action,
2176 struct mlx5_flow *dev_flow,
2178 struct rte_flow_error *error)
2180 const struct rte_flow_item *encap_data;
2181 const struct rte_flow_action_raw_encap *raw_encap_data;
2182 struct mlx5_flow_dv_encap_decap_resource res = {
2184 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2185 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2186 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2189 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2191 (const struct rte_flow_action_raw_encap *)action->conf;
2192 res.size = raw_encap_data->size;
2193 memcpy(res.buf, raw_encap_data->data, res.size);
2194 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2197 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2199 ((const struct rte_flow_action_vxlan_encap *)
2200 action->conf)->definition;
2203 ((const struct rte_flow_action_nvgre_encap *)
2204 action->conf)->definition;
2205 if (flow_dv_convert_encap_data(encap_data, res.buf,
2209 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2210 return rte_flow_error_set(error, EINVAL,
2211 RTE_FLOW_ERROR_TYPE_ACTION,
2212 NULL, "can't create L2 encap action");
2217 * Convert L2 decap action to DV specification.
2220 * Pointer to rte_eth_dev structure.
2221 * @param[in, out] dev_flow
2222 * Pointer to the mlx5_flow.
2223 * @param[in] transfer
2224 * Mark if the flow is E-Switch flow.
2226 * Pointer to the error structure.
2229 * 0 on success, a negative errno value otherwise and rte_errno is set.
2232 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2233 struct mlx5_flow *dev_flow,
2235 struct rte_flow_error *error)
2237 struct mlx5_flow_dv_encap_decap_resource res = {
2240 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2241 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2242 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2245 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2246 return rte_flow_error_set(error, EINVAL,
2247 RTE_FLOW_ERROR_TYPE_ACTION,
2248 NULL, "can't create L2 decap action");
2253 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2256 * Pointer to rte_eth_dev structure.
2258 * Pointer to action structure.
2259 * @param[in, out] dev_flow
2260 * Pointer to the mlx5_flow.
2262 * Pointer to the flow attributes.
2264 * Pointer to the error structure.
2267 * 0 on success, a negative errno value otherwise and rte_errno is set.
2270 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2271 const struct rte_flow_action *action,
2272 struct mlx5_flow *dev_flow,
2273 const struct rte_flow_attr *attr,
2274 struct rte_flow_error *error)
2276 const struct rte_flow_action_raw_encap *encap_data;
2277 struct mlx5_flow_dv_encap_decap_resource res;
2279 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2280 res.size = encap_data->size;
2281 memcpy(res.buf, encap_data->data, res.size);
2282 res.reformat_type = attr->egress ?
2283 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2284 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2286 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2288 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2289 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2290 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2291 return rte_flow_error_set(error, EINVAL,
2292 RTE_FLOW_ERROR_TYPE_ACTION,
2293 NULL, "can't create encap action");
2298 * Create action push VLAN.
2301 * Pointer to rte_eth_dev structure.
2302 * @param[in] vlan_tag
2303 * the vlan tag to push to the Ethernet header.
2304 * @param[in, out] dev_flow
2305 * Pointer to the mlx5_flow.
2307 * Pointer to the flow attributes.
2309 * Pointer to the error structure.
2312 * 0 on success, a negative errno value otherwise and rte_errno is set.
2315 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2316 const struct rte_flow_attr *attr,
2317 const struct rte_vlan_hdr *vlan,
2318 struct mlx5_flow *dev_flow,
2319 struct rte_flow_error *error)
2321 struct mlx5_flow_dv_push_vlan_action_resource res;
2324 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2327 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2329 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2330 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2331 return flow_dv_push_vlan_action_resource_register
2332 (dev, &res, dev_flow, error);
2336 * Validate the modify-header actions.
2338 * @param[in] action_flags
2339 * Holds the actions detected until now.
2341 * Pointer to the modify action.
2343 * Pointer to error structure.
2346 * 0 on success, a negative errno value otherwise and rte_errno is set.
2349 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2350 const struct rte_flow_action *action,
2351 struct rte_flow_error *error)
2353 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2354 return rte_flow_error_set(error, EINVAL,
2355 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2356 NULL, "action configuration not set");
2357 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2358 return rte_flow_error_set(error, EINVAL,
2359 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2360 "can't have encap action before"
2366 * Validate the modify-header MAC address actions.
2368 * @param[in] action_flags
2369 * Holds the actions detected until now.
2371 * Pointer to the modify action.
2372 * @param[in] item_flags
2373 * Holds the items detected.
2375 * Pointer to error structure.
2378 * 0 on success, a negative errno value otherwise and rte_errno is set.
2381 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2382 const struct rte_flow_action *action,
2383 const uint64_t item_flags,
2384 struct rte_flow_error *error)
2388 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2390 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2391 return rte_flow_error_set(error, EINVAL,
2392 RTE_FLOW_ERROR_TYPE_ACTION,
2394 "no L2 item in pattern");
2400 * Validate the modify-header IPv4 address actions.
2402 * @param[in] action_flags
2403 * Holds the actions detected until now.
2405 * Pointer to the modify action.
2406 * @param[in] item_flags
2407 * Holds the items detected.
2409 * Pointer to error structure.
2412 * 0 on success, a negative errno value otherwise and rte_errno is set.
2415 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2416 const struct rte_flow_action *action,
2417 const uint64_t item_flags,
2418 struct rte_flow_error *error)
2422 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2424 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2425 return rte_flow_error_set(error, EINVAL,
2426 RTE_FLOW_ERROR_TYPE_ACTION,
2428 "no ipv4 item in pattern");
2434 * Validate the modify-header IPv6 address actions.
2436 * @param[in] action_flags
2437 * Holds the actions detected until now.
2439 * Pointer to the modify action.
2440 * @param[in] item_flags
2441 * Holds the items detected.
2443 * Pointer to error structure.
2446 * 0 on success, a negative errno value otherwise and rte_errno is set.
2449 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2450 const struct rte_flow_action *action,
2451 const uint64_t item_flags,
2452 struct rte_flow_error *error)
2456 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2458 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2459 return rte_flow_error_set(error, EINVAL,
2460 RTE_FLOW_ERROR_TYPE_ACTION,
2462 "no ipv6 item in pattern");
2468 * Validate the modify-header TP actions.
2470 * @param[in] action_flags
2471 * Holds the actions detected until now.
2473 * Pointer to the modify action.
2474 * @param[in] item_flags
2475 * Holds the items detected.
2477 * Pointer to error structure.
2480 * 0 on success, a negative errno value otherwise and rte_errno is set.
2483 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2484 const struct rte_flow_action *action,
2485 const uint64_t item_flags,
2486 struct rte_flow_error *error)
2490 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2492 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2493 return rte_flow_error_set(error, EINVAL,
2494 RTE_FLOW_ERROR_TYPE_ACTION,
2495 NULL, "no transport layer "
2502 * Validate the modify-header actions of increment/decrement
2503 * TCP Sequence-number.
2505 * @param[in] action_flags
2506 * Holds the actions detected until now.
2508 * Pointer to the modify action.
2509 * @param[in] item_flags
2510 * Holds the items detected.
2512 * Pointer to error structure.
2515 * 0 on success, a negative errno value otherwise and rte_errno is set.
2518 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2519 const struct rte_flow_action *action,
2520 const uint64_t item_flags,
2521 struct rte_flow_error *error)
2525 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2527 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2528 return rte_flow_error_set(error, EINVAL,
2529 RTE_FLOW_ERROR_TYPE_ACTION,
2530 NULL, "no TCP item in"
2532 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2533 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2534 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2535 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2536 return rte_flow_error_set(error, EINVAL,
2537 RTE_FLOW_ERROR_TYPE_ACTION,
2539 "cannot decrease and increase"
2540 " TCP sequence number"
2541 " at the same time");
2547 * Validate the modify-header actions of increment/decrement
2548 * TCP Acknowledgment number.
2550 * @param[in] action_flags
2551 * Holds the actions detected until now.
2553 * Pointer to the modify action.
2554 * @param[in] item_flags
2555 * Holds the items detected.
2557 * Pointer to error structure.
2560 * 0 on success, a negative errno value otherwise and rte_errno is set.
2563 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2564 const struct rte_flow_action *action,
2565 const uint64_t item_flags,
2566 struct rte_flow_error *error)
2570 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2572 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2573 return rte_flow_error_set(error, EINVAL,
2574 RTE_FLOW_ERROR_TYPE_ACTION,
2575 NULL, "no TCP item in"
2577 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2578 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2579 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2580 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2581 return rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ACTION,
2584 "cannot decrease and increase"
2585 " TCP acknowledgment number"
2586 " at the same time");
2592 * Validate the modify-header TTL actions.
2594 * @param[in] action_flags
2595 * Holds the actions detected until now.
2597 * Pointer to the modify action.
2598 * @param[in] item_flags
2599 * Holds the items detected.
2601 * Pointer to error structure.
2604 * 0 on success, a negative errno value otherwise and rte_errno is set.
2607 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2608 const struct rte_flow_action *action,
2609 const uint64_t item_flags,
2610 struct rte_flow_error *error)
2614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2616 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ACTION,
2620 "no IP protocol in pattern");
2626 * Validate jump action.
2629 * Pointer to the jump action.
2630 * @param[in] action_flags
2631 * Holds the actions detected until now.
2632 * @param[in] attributes
2633 * Pointer to flow attributes
2634 * @param[in] external
2635 * Action belongs to flow rule created by request external to PMD.
2637 * Pointer to error structure.
2640 * 0 on success, a negative errno value otherwise and rte_errno is set.
2643 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2644 uint64_t action_flags,
2645 const struct rte_flow_attr *attributes,
2646 bool external, struct rte_flow_error *error)
2648 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2650 uint32_t target_group, table;
2653 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2654 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2655 return rte_flow_error_set(error, EINVAL,
2656 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2657 "can't have 2 fate actions in"
2660 return rte_flow_error_set(error, EINVAL,
2661 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2662 NULL, "action configuration not set");
2664 ((const struct rte_flow_action_jump *)action->conf)->group;
2665 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2669 if (table >= max_group)
2670 return rte_flow_error_set(error, EINVAL,
2671 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2672 "target group index out of range");
2673 if (attributes->group >= target_group)
2674 return rte_flow_error_set(error, EINVAL,
2675 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2676 "target group must be higher than"
2677 " the current flow group");
2682 * Validate the port_id action.
2685 * Pointer to rte_eth_dev structure.
2686 * @param[in] action_flags
2687 * Bit-fields that holds the actions detected until now.
2689 * Port_id RTE action structure.
2691 * Attributes of flow that includes this action.
2693 * Pointer to error structure.
2696 * 0 on success, a negative errno value otherwise and rte_errno is set.
2699 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2700 uint64_t action_flags,
2701 const struct rte_flow_action *action,
2702 const struct rte_flow_attr *attr,
2703 struct rte_flow_error *error)
2705 const struct rte_flow_action_port_id *port_id;
2706 struct mlx5_priv *act_priv;
2707 struct mlx5_priv *dev_priv;
2710 if (!attr->transfer)
2711 return rte_flow_error_set(error, ENOTSUP,
2712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2714 "port id action is valid in transfer"
2716 if (!action || !action->conf)
2717 return rte_flow_error_set(error, ENOTSUP,
2718 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2720 "port id action parameters must be"
2722 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2723 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2724 return rte_flow_error_set(error, EINVAL,
2725 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2726 "can have only one fate actions in"
2728 dev_priv = mlx5_dev_to_eswitch_info(dev);
2730 return rte_flow_error_set(error, rte_errno,
2731 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2733 "failed to obtain E-Switch info");
2734 port_id = action->conf;
2735 port = port_id->original ? dev->data->port_id : port_id->id;
2736 act_priv = mlx5_port_to_eswitch_info(port, false);
2738 return rte_flow_error_set
2740 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2741 "failed to obtain E-Switch port id for port");
2742 if (act_priv->domain_id != dev_priv->domain_id)
2743 return rte_flow_error_set
2745 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2746 "port does not belong to"
2747 " E-Switch being configured");
2752 * Find existing modify-header resource or create and register a new one.
2754 * @param dev[in, out]
2755 * Pointer to rte_eth_dev structure.
2756 * @param[in, out] resource
2757 * Pointer to modify-header resource.
2758 * @parm[in, out] dev_flow
2759 * Pointer to the dev_flow.
2761 * pointer to error structure.
2764 * 0 on success otherwise -errno and errno is set.
2767 flow_dv_modify_hdr_resource_register
2768 (struct rte_eth_dev *dev,
2769 struct mlx5_flow_dv_modify_hdr_resource *resource,
2770 struct mlx5_flow *dev_flow,
2771 struct rte_flow_error *error)
2773 struct mlx5_priv *priv = dev->data->dev_private;
2774 struct mlx5_ibv_shared *sh = priv->sh;
2775 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2776 struct mlx5dv_dr_domain *ns;
2778 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2779 ns = sh->fdb_domain;
2780 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2785 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2786 /* Lookup a matching resource from cache. */
2787 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2788 if (resource->ft_type == cache_resource->ft_type &&
2789 resource->actions_num == cache_resource->actions_num &&
2790 resource->flags == cache_resource->flags &&
2791 !memcmp((const void *)resource->actions,
2792 (const void *)cache_resource->actions,
2793 (resource->actions_num *
2794 sizeof(resource->actions[0])))) {
2795 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2796 (void *)cache_resource,
2797 rte_atomic32_read(&cache_resource->refcnt));
2798 rte_atomic32_inc(&cache_resource->refcnt);
2799 dev_flow->dv.modify_hdr = cache_resource;
2803 /* Register new modify-header resource. */
2804 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2805 if (!cache_resource)
2806 return rte_flow_error_set(error, ENOMEM,
2807 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2808 "cannot allocate resource memory");
2809 *cache_resource = *resource;
2810 cache_resource->verbs_action =
2811 mlx5_glue->dv_create_flow_action_modify_header
2812 (sh->ctx, cache_resource->ft_type,
2813 ns, cache_resource->flags,
2814 cache_resource->actions_num *
2815 sizeof(cache_resource->actions[0]),
2816 (uint64_t *)cache_resource->actions);
2817 if (!cache_resource->verbs_action) {
2818 rte_free(cache_resource);
2819 return rte_flow_error_set(error, ENOMEM,
2820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2821 NULL, "cannot create action");
2823 rte_atomic32_init(&cache_resource->refcnt);
2824 rte_atomic32_inc(&cache_resource->refcnt);
2825 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2826 dev_flow->dv.modify_hdr = cache_resource;
2827 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2828 (void *)cache_resource,
2829 rte_atomic32_read(&cache_resource->refcnt));
2833 #define MLX5_CNT_CONTAINER_RESIZE 64
2836 * Get or create a flow counter.
2839 * Pointer to the Ethernet device structure.
2841 * Indicate if this counter is shared with other flows.
2843 * Counter identifier.
2846 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2848 static struct mlx5_flow_counter *
2849 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2852 struct mlx5_priv *priv = dev->data->dev_private;
2853 struct mlx5_flow_counter *cnt = NULL;
2854 struct mlx5_devx_obj *dcs = NULL;
2856 if (!priv->config.devx) {
2857 rte_errno = ENOTSUP;
2861 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2862 if (cnt->shared && cnt->id == id) {
2868 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2871 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2873 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2877 struct mlx5_flow_counter tmpl = {
2883 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2885 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2891 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2896 * Release a flow counter.
2899 * Pointer to the Ethernet device structure.
2900 * @param[in] counter
2901 * Pointer to the counter handler.
2904 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2905 struct mlx5_flow_counter *counter)
2907 struct mlx5_priv *priv = dev->data->dev_private;
2911 if (--counter->ref_cnt == 0) {
2912 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2913 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2919 * Query a devx flow counter.
2922 * Pointer to the Ethernet device structure.
2924 * Pointer to the flow counter.
2926 * The statistics value of packets.
2928 * The statistics value of bytes.
2931 * 0 on success, otherwise a negative errno value and rte_errno is set.
2934 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2935 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2938 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2943 * Get a pool by a counter.
2946 * Pointer to the counter.
2951 static struct mlx5_flow_counter_pool *
2952 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2955 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2956 return (struct mlx5_flow_counter_pool *)cnt - 1;
2962 * Get a pool by devx counter ID.
2965 * Pointer to the counter container.
2967 * The counter devx ID.
2970 * The counter pool pointer if exists, NULL otherwise,
2972 static struct mlx5_flow_counter_pool *
2973 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2975 struct mlx5_flow_counter_pool *pool;
2977 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2978 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2979 MLX5_COUNTERS_PER_POOL;
2981 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2988 * Allocate a new memory for the counter values wrapped by all the needed
2992 * Pointer to the Ethernet device structure.
2994 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2997 * The new memory management pointer on success, otherwise NULL and rte_errno
3000 static struct mlx5_counter_stats_mem_mng *
3001 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3003 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3004 (dev->data->dev_private))->sh;
3005 struct mlx5_devx_mkey_attr mkey_attr;
3006 struct mlx5_counter_stats_mem_mng *mem_mng;
3007 volatile struct flow_counter_stats *raw_data;
3008 int size = (sizeof(struct flow_counter_stats) *
3009 MLX5_COUNTERS_PER_POOL +
3010 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3011 sizeof(struct mlx5_counter_stats_mem_mng);
3012 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3019 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3020 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3021 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3022 IBV_ACCESS_LOCAL_WRITE);
3023 if (!mem_mng->umem) {
3028 mkey_attr.addr = (uintptr_t)mem;
3029 mkey_attr.size = size;
3030 mkey_attr.umem_id = mem_mng->umem->umem_id;
3031 mkey_attr.pd = sh->pdn;
3032 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3034 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3039 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3040 raw_data = (volatile struct flow_counter_stats *)mem;
3041 for (i = 0; i < raws_n; ++i) {
3042 mem_mng->raws[i].mem_mng = mem_mng;
3043 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3045 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3050 * Resize a counter container.
3053 * Pointer to the Ethernet device structure.
3055 * Whether the pool is for counter that was allocated by batch command.
3058 * The new container pointer on success, otherwise NULL and rte_errno is set.
3060 static struct mlx5_pools_container *
3061 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3063 struct mlx5_priv *priv = dev->data->dev_private;
3064 struct mlx5_pools_container *cont =
3065 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3066 struct mlx5_pools_container *new_cont =
3067 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3068 struct mlx5_counter_stats_mem_mng *mem_mng;
3069 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3070 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3073 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3074 /* The last resize still hasn't detected by the host thread. */
3078 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3079 if (!new_cont->pools) {
3084 memcpy(new_cont->pools, cont->pools, cont->n *
3085 sizeof(struct mlx5_flow_counter_pool *));
3086 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3087 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3089 rte_free(new_cont->pools);
3092 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3093 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3094 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3096 new_cont->n = resize;
3097 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3098 TAILQ_INIT(&new_cont->pool_list);
3099 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3100 new_cont->init_mem_mng = mem_mng;
3102 /* Flip the master container. */
3103 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3108 * Query a devx flow counter.
3111 * Pointer to the Ethernet device structure.
3113 * Pointer to the flow counter.
3115 * The statistics value of packets.
3117 * The statistics value of bytes.
3120 * 0 on success, otherwise a negative errno value and rte_errno is set.
3123 _flow_dv_query_count(struct rte_eth_dev *dev,
3124 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3127 struct mlx5_priv *priv = dev->data->dev_private;
3128 struct mlx5_flow_counter_pool *pool =
3129 flow_dv_counter_pool_get(cnt);
3130 int offset = cnt - &pool->counters_raw[0];
3132 if (priv->counter_fallback)
3133 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3135 rte_spinlock_lock(&pool->sl);
3137 * The single counters allocation may allocate smaller ID than the
3138 * current allocated in parallel to the host reading.
3139 * In this case the new counter values must be reported as 0.
3141 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3145 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3146 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3148 rte_spinlock_unlock(&pool->sl);
3153 * Create and initialize a new counter pool.
3156 * Pointer to the Ethernet device structure.
3158 * The devX counter handle.
3160 * Whether the pool is for counter that was allocated by batch command.
3163 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3165 static struct mlx5_flow_counter_pool *
3166 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3169 struct mlx5_priv *priv = dev->data->dev_private;
3170 struct mlx5_flow_counter_pool *pool;
3171 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3173 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3176 if (cont->n == n_valid) {
3177 cont = flow_dv_container_resize(dev, batch);
3181 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3182 sizeof(struct mlx5_flow_counter);
3183 pool = rte_calloc(__func__, 1, size, 0);
3188 pool->min_dcs = dcs;
3189 pool->raw = cont->init_mem_mng->raws + n_valid %
3190 MLX5_CNT_CONTAINER_RESIZE;
3191 pool->raw_hw = NULL;
3192 rte_spinlock_init(&pool->sl);
3194 * The generation of the new allocated counters in this pool is 0, 2 in
3195 * the pool generation makes all the counters valid for allocation.
3197 rte_atomic64_set(&pool->query_gen, 0x2);
3198 TAILQ_INIT(&pool->counters);
3199 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3200 cont->pools[n_valid] = pool;
3201 /* Pool initialization must be updated before host thread access. */
3203 rte_atomic16_add(&cont->n_valid, 1);
3208 * Prepare a new counter and/or a new counter pool.
3211 * Pointer to the Ethernet device structure.
3212 * @param[out] cnt_free
3213 * Where to put the pointer of a new counter.
3215 * Whether the pool is for counter that was allocated by batch command.
3218 * The free counter pool pointer and @p cnt_free is set on success,
3219 * NULL otherwise and rte_errno is set.
3221 static struct mlx5_flow_counter_pool *
3222 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3223 struct mlx5_flow_counter **cnt_free,
3226 struct mlx5_priv *priv = dev->data->dev_private;
3227 struct mlx5_flow_counter_pool *pool;
3228 struct mlx5_devx_obj *dcs = NULL;
3229 struct mlx5_flow_counter *cnt;
3233 /* bulk_bitmap must be 0 for single counter allocation. */
3234 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3237 pool = flow_dv_find_pool_by_id
3238 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3240 pool = flow_dv_pool_create(dev, dcs, batch);
3242 mlx5_devx_cmd_destroy(dcs);
3245 } else if (dcs->id < pool->min_dcs->id) {
3246 rte_atomic64_set(&pool->a64_dcs,
3247 (int64_t)(uintptr_t)dcs);
3249 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3250 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3255 /* bulk_bitmap is in 128 counters units. */
3256 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3257 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3259 rte_errno = ENODATA;
3262 pool = flow_dv_pool_create(dev, dcs, batch);
3264 mlx5_devx_cmd_destroy(dcs);
3267 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3268 cnt = &pool->counters_raw[i];
3270 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3272 *cnt_free = &pool->counters_raw[0];
3277 * Search for existed shared counter.
3280 * Pointer to the relevant counter pool container.
3282 * The shared counter ID to search.
3285 * NULL if not existed, otherwise pointer to the shared counter.
3287 static struct mlx5_flow_counter *
3288 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3291 static struct mlx5_flow_counter *cnt;
3292 struct mlx5_flow_counter_pool *pool;
3295 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3296 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3297 cnt = &pool->counters_raw[i];
3298 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3306 * Allocate a flow counter.
3309 * Pointer to the Ethernet device structure.
3311 * Indicate if this counter is shared with other flows.
3313 * Counter identifier.
3315 * Counter flow group.
3318 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3320 static struct mlx5_flow_counter *
3321 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3324 struct mlx5_priv *priv = dev->data->dev_private;
3325 struct mlx5_flow_counter_pool *pool = NULL;
3326 struct mlx5_flow_counter *cnt_free = NULL;
3328 * Currently group 0 flow counter cannot be assigned to a flow if it is
3329 * not the first one in the batch counter allocation, so it is better
3330 * to allocate counters one by one for these flows in a separate
3332 * A counter can be shared between different groups so need to take
3333 * shared counters from the single container.
3335 uint32_t batch = (group && !shared) ? 1 : 0;
3336 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3339 if (priv->counter_fallback)
3340 return flow_dv_counter_alloc_fallback(dev, shared, id);
3341 if (!priv->config.devx) {
3342 rte_errno = ENOTSUP;
3346 cnt_free = flow_dv_counter_shared_search(cont, id);
3348 if (cnt_free->ref_cnt + 1 == 0) {
3352 cnt_free->ref_cnt++;
3356 /* Pools which has a free counters are in the start. */
3357 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3359 * The free counter reset values must be updated between the
3360 * counter release to the counter allocation, so, at least one
3361 * query must be done in this time. ensure it by saving the
3362 * query generation in the release time.
3363 * The free list is sorted according to the generation - so if
3364 * the first one is not updated, all the others are not
3367 cnt_free = TAILQ_FIRST(&pool->counters);
3368 if (cnt_free && cnt_free->query_gen + 1 <
3369 rte_atomic64_read(&pool->query_gen))
3374 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3378 cnt_free->batch = batch;
3379 /* Create a DV counter action only in the first time usage. */
3380 if (!cnt_free->action) {
3382 struct mlx5_devx_obj *dcs;
3385 offset = cnt_free - &pool->counters_raw[0];
3386 dcs = pool->min_dcs;
3389 dcs = cnt_free->dcs;
3391 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3393 if (!cnt_free->action) {
3398 /* Update the counter reset values. */
3399 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3402 cnt_free->shared = shared;
3403 cnt_free->ref_cnt = 1;
3405 if (!priv->sh->cmng.query_thread_on)
3406 /* Start the asynchronous batch query by the host thread. */
3407 mlx5_set_query_alarm(priv->sh);
3408 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3409 if (TAILQ_EMPTY(&pool->counters)) {
3410 /* Move the pool to the end of the container pool list. */
3411 TAILQ_REMOVE(&cont->pool_list, pool, next);
3412 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3418 * Release a flow counter.
3421 * Pointer to the Ethernet device structure.
3422 * @param[in] counter
3423 * Pointer to the counter handler.
3426 flow_dv_counter_release(struct rte_eth_dev *dev,
3427 struct mlx5_flow_counter *counter)
3429 struct mlx5_priv *priv = dev->data->dev_private;
3433 if (priv->counter_fallback) {
3434 flow_dv_counter_release_fallback(dev, counter);
3437 if (--counter->ref_cnt == 0) {
3438 struct mlx5_flow_counter_pool *pool =
3439 flow_dv_counter_pool_get(counter);
3441 /* Put the counter in the end - the last updated one. */
3442 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3443 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3448 * Verify the @p attributes will be correctly understood by the NIC and store
3449 * them in the @p flow if everything is correct.
3452 * Pointer to dev struct.
3453 * @param[in] attributes
3454 * Pointer to flow attributes
3455 * @param[in] external
3456 * This flow rule is created by request external to PMD.
3458 * Pointer to error structure.
3461 * 0 on success, a negative errno value otherwise and rte_errno is set.
3464 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3465 const struct rte_flow_attr *attributes,
3466 bool external __rte_unused,
3467 struct rte_flow_error *error)
3469 struct mlx5_priv *priv = dev->data->dev_private;
3470 uint32_t priority_max = priv->config.flow_prio - 1;
3472 #ifndef HAVE_MLX5DV_DR
3473 if (attributes->group)
3474 return rte_flow_error_set(error, ENOTSUP,
3475 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3477 "groups are not supported");
3479 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3484 ret = mlx5_flow_group_to_table(attributes, external,
3489 if (table >= max_group)
3490 return rte_flow_error_set(error, EINVAL,
3491 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3492 "group index out of range");
3494 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3495 attributes->priority >= priority_max)
3496 return rte_flow_error_set(error, ENOTSUP,
3497 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3499 "priority out of range");
3500 if (attributes->transfer) {
3501 if (!priv->config.dv_esw_en)
3502 return rte_flow_error_set
3504 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3505 "E-Switch dr is not supported");
3506 if (!(priv->representor || priv->master))
3507 return rte_flow_error_set
3508 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3509 NULL, "E-Switch configuration can only be"
3510 " done by a master or a representor device");
3511 if (attributes->egress)
3512 return rte_flow_error_set
3514 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3515 "egress is not supported");
3517 if (!(attributes->egress ^ attributes->ingress))
3518 return rte_flow_error_set(error, ENOTSUP,
3519 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3520 "must specify exactly one of "
3521 "ingress or egress");
3526 * Internal validation function. For validating both actions and items.
3529 * Pointer to the rte_eth_dev structure.
3531 * Pointer to the flow attributes.
3533 * Pointer to the list of items.
3534 * @param[in] actions
3535 * Pointer to the list of actions.
3536 * @param[in] external
3537 * This flow rule is created by request external to PMD.
3539 * Pointer to the error structure.
3542 * 0 on success, a negative errno value otherwise and rte_errno is set.
3545 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3546 const struct rte_flow_item items[],
3547 const struct rte_flow_action actions[],
3548 bool external, struct rte_flow_error *error)
3551 uint64_t action_flags = 0;
3552 uint64_t item_flags = 0;
3553 uint64_t last_item = 0;
3554 uint8_t next_protocol = 0xff;
3555 uint16_t ether_type = 0;
3557 const struct rte_flow_item *gre_item = NULL;
3558 struct rte_flow_item_tcp nic_tcp_mask = {
3561 .src_port = RTE_BE16(UINT16_MAX),
3562 .dst_port = RTE_BE16(UINT16_MAX),
3568 ret = flow_dv_validate_attributes(dev, attr, external, error);
3571 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3572 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3573 int type = items->type;
3576 case RTE_FLOW_ITEM_TYPE_VOID:
3578 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3579 ret = flow_dv_validate_item_port_id
3580 (dev, items, attr, item_flags, error);
3583 last_item = MLX5_FLOW_ITEM_PORT_ID;
3585 case RTE_FLOW_ITEM_TYPE_ETH:
3586 ret = mlx5_flow_validate_item_eth(items, item_flags,
3590 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3591 MLX5_FLOW_LAYER_OUTER_L2;
3592 if (items->mask != NULL && items->spec != NULL) {
3594 ((const struct rte_flow_item_eth *)
3597 ((const struct rte_flow_item_eth *)
3599 ether_type = rte_be_to_cpu_16(ether_type);
3604 case RTE_FLOW_ITEM_TYPE_VLAN:
3605 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3609 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3610 MLX5_FLOW_LAYER_OUTER_VLAN;
3611 if (items->mask != NULL && items->spec != NULL) {
3613 ((const struct rte_flow_item_vlan *)
3614 items->spec)->inner_type;
3616 ((const struct rte_flow_item_vlan *)
3617 items->mask)->inner_type;
3618 ether_type = rte_be_to_cpu_16(ether_type);
3623 case RTE_FLOW_ITEM_TYPE_IPV4:
3624 mlx5_flow_tunnel_ip_check(items, next_protocol,
3625 &item_flags, &tunnel);
3626 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3632 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3633 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3634 if (items->mask != NULL &&
3635 ((const struct rte_flow_item_ipv4 *)
3636 items->mask)->hdr.next_proto_id) {
3638 ((const struct rte_flow_item_ipv4 *)
3639 (items->spec))->hdr.next_proto_id;
3641 ((const struct rte_flow_item_ipv4 *)
3642 (items->mask))->hdr.next_proto_id;
3644 /* Reset for inner layer. */
3645 next_protocol = 0xff;
3648 case RTE_FLOW_ITEM_TYPE_IPV6:
3649 mlx5_flow_tunnel_ip_check(items, next_protocol,
3650 &item_flags, &tunnel);
3651 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3657 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3658 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3659 if (items->mask != NULL &&
3660 ((const struct rte_flow_item_ipv6 *)
3661 items->mask)->hdr.proto) {
3663 ((const struct rte_flow_item_ipv6 *)
3664 items->spec)->hdr.proto;
3666 ((const struct rte_flow_item_ipv6 *)
3667 items->mask)->hdr.proto;
3669 /* Reset for inner layer. */
3670 next_protocol = 0xff;
3673 case RTE_FLOW_ITEM_TYPE_TCP:
3674 ret = mlx5_flow_validate_item_tcp
3681 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3682 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3684 case RTE_FLOW_ITEM_TYPE_UDP:
3685 ret = mlx5_flow_validate_item_udp(items, item_flags,
3690 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3691 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3693 case RTE_FLOW_ITEM_TYPE_GRE:
3694 ret = mlx5_flow_validate_item_gre(items, item_flags,
3695 next_protocol, error);
3699 last_item = MLX5_FLOW_LAYER_GRE;
3701 case RTE_FLOW_ITEM_TYPE_NVGRE:
3702 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3707 last_item = MLX5_FLOW_LAYER_NVGRE;
3709 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3710 ret = mlx5_flow_validate_item_gre_key
3711 (items, item_flags, gre_item, error);
3714 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3716 case RTE_FLOW_ITEM_TYPE_VXLAN:
3717 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3721 last_item = MLX5_FLOW_LAYER_VXLAN;
3723 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3724 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3729 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3731 case RTE_FLOW_ITEM_TYPE_GENEVE:
3732 ret = mlx5_flow_validate_item_geneve(items,
3737 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3739 case RTE_FLOW_ITEM_TYPE_MPLS:
3740 ret = mlx5_flow_validate_item_mpls(dev, items,
3745 last_item = MLX5_FLOW_LAYER_MPLS;
3747 case RTE_FLOW_ITEM_TYPE_META:
3748 ret = flow_dv_validate_item_meta(dev, items, attr,
3752 last_item = MLX5_FLOW_ITEM_METADATA;
3754 case RTE_FLOW_ITEM_TYPE_ICMP:
3755 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3760 last_item = MLX5_FLOW_LAYER_ICMP;
3762 case RTE_FLOW_ITEM_TYPE_ICMP6:
3763 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3768 last_item = MLX5_FLOW_LAYER_ICMP6;
3770 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3771 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3774 return rte_flow_error_set(error, ENOTSUP,
3775 RTE_FLOW_ERROR_TYPE_ITEM,
3776 NULL, "item not supported");
3778 item_flags |= last_item;
3780 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3781 int type = actions->type;
3782 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3783 return rte_flow_error_set(error, ENOTSUP,
3784 RTE_FLOW_ERROR_TYPE_ACTION,
3785 actions, "too many actions");
3787 case RTE_FLOW_ACTION_TYPE_VOID:
3789 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3790 ret = flow_dv_validate_action_port_id(dev,
3797 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3800 case RTE_FLOW_ACTION_TYPE_FLAG:
3801 ret = mlx5_flow_validate_action_flag(action_flags,
3805 action_flags |= MLX5_FLOW_ACTION_FLAG;
3808 case RTE_FLOW_ACTION_TYPE_MARK:
3809 ret = mlx5_flow_validate_action_mark(actions,
3814 action_flags |= MLX5_FLOW_ACTION_MARK;
3817 case RTE_FLOW_ACTION_TYPE_DROP:
3818 ret = mlx5_flow_validate_action_drop(action_flags,
3822 action_flags |= MLX5_FLOW_ACTION_DROP;
3825 case RTE_FLOW_ACTION_TYPE_QUEUE:
3826 ret = mlx5_flow_validate_action_queue(actions,
3831 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3834 case RTE_FLOW_ACTION_TYPE_RSS:
3835 ret = mlx5_flow_validate_action_rss(actions,
3841 action_flags |= MLX5_FLOW_ACTION_RSS;
3844 case RTE_FLOW_ACTION_TYPE_COUNT:
3845 ret = flow_dv_validate_action_count(dev, error);
3848 action_flags |= MLX5_FLOW_ACTION_COUNT;
3851 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3852 if (flow_dv_validate_action_pop_vlan(dev,
3858 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3861 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3862 ret = flow_dv_validate_action_push_vlan(action_flags,
3868 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3871 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3872 ret = flow_dv_validate_action_set_vlan_pcp
3873 (action_flags, actions, error);
3876 /* Count PCP with push_vlan command. */
3877 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3879 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3880 ret = flow_dv_validate_action_set_vlan_vid
3881 (item_flags, action_flags,
3885 /* Count VID with push_vlan command. */
3886 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3888 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3889 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3890 ret = flow_dv_validate_action_l2_encap(action_flags,
3895 action_flags |= actions->type ==
3896 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3897 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3898 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3901 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3902 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3903 ret = flow_dv_validate_action_l2_decap(action_flags,
3907 action_flags |= actions->type ==
3908 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3909 MLX5_FLOW_ACTION_VXLAN_DECAP :
3910 MLX5_FLOW_ACTION_NVGRE_DECAP;
3913 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3914 ret = flow_dv_validate_action_raw_encap(action_flags,
3919 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3922 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3923 ret = flow_dv_validate_action_raw_decap(action_flags,
3928 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3931 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3932 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3933 ret = flow_dv_validate_action_modify_mac(action_flags,
3939 /* Count all modify-header actions as one action. */
3940 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3942 action_flags |= actions->type ==
3943 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3944 MLX5_FLOW_ACTION_SET_MAC_SRC :
3945 MLX5_FLOW_ACTION_SET_MAC_DST;
3948 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3949 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3950 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3956 /* Count all modify-header actions as one action. */
3957 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3959 action_flags |= actions->type ==
3960 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3961 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3962 MLX5_FLOW_ACTION_SET_IPV4_DST;
3964 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3965 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3966 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3972 /* Count all modify-header actions as one action. */
3973 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3975 action_flags |= actions->type ==
3976 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3977 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3978 MLX5_FLOW_ACTION_SET_IPV6_DST;
3980 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3981 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3982 ret = flow_dv_validate_action_modify_tp(action_flags,
3988 /* Count all modify-header actions as one action. */
3989 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3991 action_flags |= actions->type ==
3992 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3993 MLX5_FLOW_ACTION_SET_TP_SRC :
3994 MLX5_FLOW_ACTION_SET_TP_DST;
3996 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3997 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3998 ret = flow_dv_validate_action_modify_ttl(action_flags,
4004 /* Count all modify-header actions as one action. */
4005 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4007 action_flags |= actions->type ==
4008 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4009 MLX5_FLOW_ACTION_SET_TTL :
4010 MLX5_FLOW_ACTION_DEC_TTL;
4012 case RTE_FLOW_ACTION_TYPE_JUMP:
4013 ret = flow_dv_validate_action_jump(actions,
4020 action_flags |= MLX5_FLOW_ACTION_JUMP;
4022 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4023 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4024 ret = flow_dv_validate_action_modify_tcp_seq
4031 /* Count all modify-header actions as one action. */
4032 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4034 action_flags |= actions->type ==
4035 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4036 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4037 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4039 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4040 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4041 ret = flow_dv_validate_action_modify_tcp_ack
4048 /* Count all modify-header actions as one action. */
4049 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4051 action_flags |= actions->type ==
4052 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4053 MLX5_FLOW_ACTION_INC_TCP_ACK :
4054 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4056 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4057 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4060 return rte_flow_error_set(error, ENOTSUP,
4061 RTE_FLOW_ERROR_TYPE_ACTION,
4063 "action not supported");
4066 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4067 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4068 return rte_flow_error_set(error, ENOTSUP,
4069 RTE_FLOW_ERROR_TYPE_ACTION,
4071 "can't have vxlan and vlan"
4072 " actions in the same rule");
4073 /* Eswitch has few restrictions on using items and actions */
4074 if (attr->transfer) {
4075 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4076 return rte_flow_error_set(error, ENOTSUP,
4077 RTE_FLOW_ERROR_TYPE_ACTION,
4079 "unsupported action FLAG");
4080 if (action_flags & MLX5_FLOW_ACTION_MARK)
4081 return rte_flow_error_set(error, ENOTSUP,
4082 RTE_FLOW_ERROR_TYPE_ACTION,
4084 "unsupported action MARK");
4085 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4086 return rte_flow_error_set(error, ENOTSUP,
4087 RTE_FLOW_ERROR_TYPE_ACTION,
4089 "unsupported action QUEUE");
4090 if (action_flags & MLX5_FLOW_ACTION_RSS)
4091 return rte_flow_error_set(error, ENOTSUP,
4092 RTE_FLOW_ERROR_TYPE_ACTION,
4094 "unsupported action RSS");
4095 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4096 return rte_flow_error_set(error, EINVAL,
4097 RTE_FLOW_ERROR_TYPE_ACTION,
4099 "no fate action is found");
4101 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4102 return rte_flow_error_set(error, EINVAL,
4103 RTE_FLOW_ERROR_TYPE_ACTION,
4105 "no fate action is found");
4111 * Internal preparation function. Allocates the DV flow size,
4112 * this size is constant.
4115 * Pointer to the flow attributes.
4117 * Pointer to the list of items.
4118 * @param[in] actions
4119 * Pointer to the list of actions.
4121 * Pointer to the error structure.
4124 * Pointer to mlx5_flow object on success,
4125 * otherwise NULL and rte_errno is set.
4127 static struct mlx5_flow *
4128 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4129 const struct rte_flow_item items[] __rte_unused,
4130 const struct rte_flow_action actions[] __rte_unused,
4131 struct rte_flow_error *error)
4133 size_t size = sizeof(struct mlx5_flow);
4134 struct mlx5_flow *dev_flow;
4136 dev_flow = rte_calloc(__func__, 1, size, 0);
4138 rte_flow_error_set(error, ENOMEM,
4139 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4140 "not enough memory to create flow");
4143 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4144 dev_flow->ingress = attr->ingress;
4145 dev_flow->transfer = attr->transfer;
4151 * Sanity check for match mask and value. Similar to check_valid_spec() in
4152 * kernel driver. If unmasked bit is present in value, it returns failure.
4155 * pointer to match mask buffer.
4156 * @param match_value
4157 * pointer to match value buffer.
4160 * 0 if valid, -EINVAL otherwise.
4163 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4165 uint8_t *m = match_mask;
4166 uint8_t *v = match_value;
4169 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4172 "match_value differs from match_criteria"
4173 " %p[%u] != %p[%u]",
4174 match_value, i, match_mask, i);
4183 * Add Ethernet item to matcher and to the value.
4185 * @param[in, out] matcher
4187 * @param[in, out] key
4188 * Flow matcher value.
4190 * Flow pattern to translate.
4192 * Item is inner pattern.
4195 flow_dv_translate_item_eth(void *matcher, void *key,
4196 const struct rte_flow_item *item, int inner)
4198 const struct rte_flow_item_eth *eth_m = item->mask;
4199 const struct rte_flow_item_eth *eth_v = item->spec;
4200 const struct rte_flow_item_eth nic_mask = {
4201 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4202 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4203 .type = RTE_BE16(0xffff),
4215 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4217 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4219 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4221 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4223 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4224 ð_m->dst, sizeof(eth_m->dst));
4225 /* The value must be in the range of the mask. */
4226 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4227 for (i = 0; i < sizeof(eth_m->dst); ++i)
4228 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4229 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4230 ð_m->src, sizeof(eth_m->src));
4231 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4232 /* The value must be in the range of the mask. */
4233 for (i = 0; i < sizeof(eth_m->dst); ++i)
4234 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4235 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4236 rte_be_to_cpu_16(eth_m->type));
4237 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4238 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4242 * Add VLAN item to matcher and to the value.
4244 * @param[in, out] dev_flow
4246 * @param[in, out] matcher
4248 * @param[in, out] key
4249 * Flow matcher value.
4251 * Flow pattern to translate.
4253 * Item is inner pattern.
4256 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4257 void *matcher, void *key,
4258 const struct rte_flow_item *item,
4261 const struct rte_flow_item_vlan *vlan_m = item->mask;
4262 const struct rte_flow_item_vlan *vlan_v = item->spec;
4271 vlan_m = &rte_flow_item_vlan_mask;
4273 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4275 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4277 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4279 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4281 * This is workaround, masks are not supported,
4282 * and pre-validated.
4284 dev_flow->dv.vf_vlan.tag =
4285 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4287 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4288 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4289 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4290 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4291 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4292 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4293 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4294 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4295 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4296 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4297 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4298 rte_be_to_cpu_16(vlan_m->inner_type));
4299 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4300 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4304 * Add IPV4 item to matcher and to the value.
4306 * @param[in, out] matcher
4308 * @param[in, out] key
4309 * Flow matcher value.
4311 * Flow pattern to translate.
4313 * Item is inner pattern.
4315 * The group to insert the rule.
4318 flow_dv_translate_item_ipv4(void *matcher, void *key,
4319 const struct rte_flow_item *item,
4320 int inner, uint32_t group)
4322 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4323 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4324 const struct rte_flow_item_ipv4 nic_mask = {
4326 .src_addr = RTE_BE32(0xffffffff),
4327 .dst_addr = RTE_BE32(0xffffffff),
4328 .type_of_service = 0xff,
4329 .next_proto_id = 0xff,
4339 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4341 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4343 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4345 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4348 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4350 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4351 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4356 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4357 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4358 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4359 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4360 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4361 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4362 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4363 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4364 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4365 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4366 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4367 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4368 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4369 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4370 ipv4_m->hdr.type_of_service);
4371 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4372 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4373 ipv4_m->hdr.type_of_service >> 2);
4374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4375 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4376 ipv4_m->hdr.next_proto_id);
4377 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4378 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4382 * Add IPV6 item to matcher and to the value.
4384 * @param[in, out] matcher
4386 * @param[in, out] key
4387 * Flow matcher value.
4389 * Flow pattern to translate.
4391 * Item is inner pattern.
4393 * The group to insert the rule.
4396 flow_dv_translate_item_ipv6(void *matcher, void *key,
4397 const struct rte_flow_item *item,
4398 int inner, uint32_t group)
4400 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4401 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4402 const struct rte_flow_item_ipv6 nic_mask = {
4405 "\xff\xff\xff\xff\xff\xff\xff\xff"
4406 "\xff\xff\xff\xff\xff\xff\xff\xff",
4408 "\xff\xff\xff\xff\xff\xff\xff\xff"
4409 "\xff\xff\xff\xff\xff\xff\xff\xff",
4410 .vtc_flow = RTE_BE32(0xffffffff),
4417 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4418 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4427 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4429 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4431 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4433 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4436 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4438 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4439 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4444 size = sizeof(ipv6_m->hdr.dst_addr);
4445 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4446 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4447 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4448 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4449 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4450 for (i = 0; i < size; ++i)
4451 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4452 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4453 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4454 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4455 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4456 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4457 for (i = 0; i < size; ++i)
4458 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4460 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4461 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4462 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4463 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4464 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4465 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4468 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4470 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4473 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4475 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4479 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4481 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4482 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4486 * Add TCP item to matcher and to the value.
4488 * @param[in, out] matcher
4490 * @param[in, out] key
4491 * Flow matcher value.
4493 * Flow pattern to translate.
4495 * Item is inner pattern.
4498 flow_dv_translate_item_tcp(void *matcher, void *key,
4499 const struct rte_flow_item *item,
4502 const struct rte_flow_item_tcp *tcp_m = item->mask;
4503 const struct rte_flow_item_tcp *tcp_v = item->spec;
4508 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4510 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4512 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4514 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4516 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4517 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4521 tcp_m = &rte_flow_item_tcp_mask;
4522 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4523 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4524 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4525 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4526 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4527 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4529 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4531 tcp_m->hdr.tcp_flags);
4532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4533 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4537 * Add UDP item to matcher and to the value.
4539 * @param[in, out] matcher
4541 * @param[in, out] key
4542 * Flow matcher value.
4544 * Flow pattern to translate.
4546 * Item is inner pattern.
4549 flow_dv_translate_item_udp(void *matcher, void *key,
4550 const struct rte_flow_item *item,
4553 const struct rte_flow_item_udp *udp_m = item->mask;
4554 const struct rte_flow_item_udp *udp_v = item->spec;
4559 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4561 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4563 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4565 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4567 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4572 udp_m = &rte_flow_item_udp_mask;
4573 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4574 rte_be_to_cpu_16(udp_m->hdr.src_port));
4575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4576 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4577 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4578 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4579 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4580 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4584 * Add GRE optional Key item to matcher and to the value.
4586 * @param[in, out] matcher
4588 * @param[in, out] key
4589 * Flow matcher value.
4591 * Flow pattern to translate.
4593 * Item is inner pattern.
4596 flow_dv_translate_item_gre_key(void *matcher, void *key,
4597 const struct rte_flow_item *item)
4599 const rte_be32_t *key_m = item->mask;
4600 const rte_be32_t *key_v = item->spec;
4601 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4602 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4603 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4608 key_m = &gre_key_default_mask;
4609 /* GRE K bit must be on and should already be validated */
4610 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4611 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4612 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4613 rte_be_to_cpu_32(*key_m) >> 8);
4614 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4615 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4616 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4617 rte_be_to_cpu_32(*key_m) & 0xFF);
4618 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4619 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4623 * Add GRE item to matcher and to the value.
4625 * @param[in, out] matcher
4627 * @param[in, out] key
4628 * Flow matcher value.
4630 * Flow pattern to translate.
4632 * Item is inner pattern.
4635 flow_dv_translate_item_gre(void *matcher, void *key,
4636 const struct rte_flow_item *item,
4639 const struct rte_flow_item_gre *gre_m = item->mask;
4640 const struct rte_flow_item_gre *gre_v = item->spec;
4643 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4644 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4651 uint16_t s_present:1;
4652 uint16_t k_present:1;
4653 uint16_t rsvd_bit1:1;
4654 uint16_t c_present:1;
4658 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4661 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4663 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4665 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4667 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4674 gre_m = &rte_flow_item_gre_mask;
4675 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4676 rte_be_to_cpu_16(gre_m->protocol));
4677 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4678 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4679 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4680 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4681 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4682 gre_crks_rsvd0_ver_m.c_present);
4683 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4684 gre_crks_rsvd0_ver_v.c_present &
4685 gre_crks_rsvd0_ver_m.c_present);
4686 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4687 gre_crks_rsvd0_ver_m.k_present);
4688 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4689 gre_crks_rsvd0_ver_v.k_present &
4690 gre_crks_rsvd0_ver_m.k_present);
4691 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4692 gre_crks_rsvd0_ver_m.s_present);
4693 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4694 gre_crks_rsvd0_ver_v.s_present &
4695 gre_crks_rsvd0_ver_m.s_present);
4699 * Add NVGRE item to matcher and to the value.
4701 * @param[in, out] matcher
4703 * @param[in, out] key
4704 * Flow matcher value.
4706 * Flow pattern to translate.
4708 * Item is inner pattern.
4711 flow_dv_translate_item_nvgre(void *matcher, void *key,
4712 const struct rte_flow_item *item,
4715 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4716 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4717 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4718 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4719 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4720 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4726 /* For NVGRE, GRE header fields must be set with defined values. */
4727 const struct rte_flow_item_gre gre_spec = {
4728 .c_rsvd0_ver = RTE_BE16(0x2000),
4729 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4731 const struct rte_flow_item_gre gre_mask = {
4732 .c_rsvd0_ver = RTE_BE16(0xB000),
4733 .protocol = RTE_BE16(UINT16_MAX),
4735 const struct rte_flow_item gre_item = {
4740 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4744 nvgre_m = &rte_flow_item_nvgre_mask;
4745 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4746 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4747 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4748 memcpy(gre_key_m, tni_flow_id_m, size);
4749 for (i = 0; i < size; ++i)
4750 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4754 * Add VXLAN item to matcher and to the value.
4756 * @param[in, out] matcher
4758 * @param[in, out] key
4759 * Flow matcher value.
4761 * Flow pattern to translate.
4763 * Item is inner pattern.
4766 flow_dv_translate_item_vxlan(void *matcher, void *key,
4767 const struct rte_flow_item *item,
4770 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4771 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4774 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4775 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4783 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4785 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4787 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4789 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4791 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4792 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4793 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4794 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4795 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4800 vxlan_m = &rte_flow_item_vxlan_mask;
4801 size = sizeof(vxlan_m->vni);
4802 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4803 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4804 memcpy(vni_m, vxlan_m->vni, size);
4805 for (i = 0; i < size; ++i)
4806 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4810 * Add Geneve item to matcher and to the value.
4812 * @param[in, out] matcher
4814 * @param[in, out] key
4815 * Flow matcher value.
4817 * Flow pattern to translate.
4819 * Item is inner pattern.
4823 flow_dv_translate_item_geneve(void *matcher, void *key,
4824 const struct rte_flow_item *item, int inner)
4826 const struct rte_flow_item_geneve *geneve_m = item->mask;
4827 const struct rte_flow_item_geneve *geneve_v = item->spec;
4830 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4831 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4840 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4842 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4844 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4846 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4848 dport = MLX5_UDP_PORT_GENEVE;
4849 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4850 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4851 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4856 geneve_m = &rte_flow_item_geneve_mask;
4857 size = sizeof(geneve_m->vni);
4858 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4859 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4860 memcpy(vni_m, geneve_m->vni, size);
4861 for (i = 0; i < size; ++i)
4862 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4863 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4864 rte_be_to_cpu_16(geneve_m->protocol));
4865 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4866 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4867 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4868 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4869 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4870 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4871 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4872 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4873 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4874 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4875 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4876 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4877 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4881 * Add MPLS item to matcher and to the value.
4883 * @param[in, out] matcher
4885 * @param[in, out] key
4886 * Flow matcher value.
4888 * Flow pattern to translate.
4889 * @param[in] prev_layer
4890 * The protocol layer indicated in previous item.
4892 * Item is inner pattern.
4895 flow_dv_translate_item_mpls(void *matcher, void *key,
4896 const struct rte_flow_item *item,
4897 uint64_t prev_layer,
4900 const uint32_t *in_mpls_m = item->mask;
4901 const uint32_t *in_mpls_v = item->spec;
4902 uint32_t *out_mpls_m = 0;
4903 uint32_t *out_mpls_v = 0;
4904 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4905 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4906 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4908 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4909 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4910 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4912 switch (prev_layer) {
4913 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4914 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4915 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4916 MLX5_UDP_PORT_MPLS);
4918 case MLX5_FLOW_LAYER_GRE:
4919 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4920 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4921 RTE_ETHER_TYPE_MPLS);
4924 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4925 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4932 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4933 switch (prev_layer) {
4934 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4936 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4937 outer_first_mpls_over_udp);
4939 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4940 outer_first_mpls_over_udp);
4942 case MLX5_FLOW_LAYER_GRE:
4944 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4945 outer_first_mpls_over_gre);
4947 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4948 outer_first_mpls_over_gre);
4951 /* Inner MPLS not over GRE is not supported. */
4954 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4958 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4964 if (out_mpls_m && out_mpls_v) {
4965 *out_mpls_m = *in_mpls_m;
4966 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4971 * Add metadata register item to matcher
4973 * @param[in, out] matcher
4975 * @param[in, out] key
4976 * Flow matcher value.
4977 * @param[in] reg_type
4978 * Type of device metadata register
4985 flow_dv_match_meta_reg(void *matcher, void *key,
4986 enum modify_reg reg_type,
4987 uint32_t data, uint32_t mask)
4990 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4992 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4997 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
4998 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5001 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5002 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5005 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5006 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5009 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5010 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5013 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5014 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5017 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5018 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5021 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5022 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5025 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5026 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5029 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5030 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5033 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5034 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5043 * Add META item to matcher
5045 * @param[in, out] matcher
5047 * @param[in, out] key
5048 * Flow matcher value.
5050 * Flow pattern to translate.
5052 * Item is inner pattern.
5055 flow_dv_translate_item_meta(void *matcher, void *key,
5056 const struct rte_flow_item *item)
5058 const struct rte_flow_item_meta *meta_m;
5059 const struct rte_flow_item_meta *meta_v;
5061 meta_m = (const void *)item->mask;
5063 meta_m = &rte_flow_item_meta_mask;
5064 meta_v = (const void *)item->spec;
5066 flow_dv_match_meta_reg(matcher, key, REG_A,
5067 rte_cpu_to_be_32(meta_v->data),
5068 rte_cpu_to_be_32(meta_m->data));
5072 * Add vport metadata Reg C0 item to matcher
5074 * @param[in, out] matcher
5076 * @param[in, out] key
5077 * Flow matcher value.
5079 * Flow pattern to translate.
5082 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5083 uint32_t value, uint32_t mask)
5085 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5089 * Add tag item to matcher
5091 * @param[in, out] matcher
5093 * @param[in, out] key
5094 * Flow matcher value.
5096 * Flow pattern to translate.
5099 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5100 const struct rte_flow_item *item)
5102 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5103 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5104 enum modify_reg reg = tag_v->id;
5106 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5110 * Add source vport match to the specified matcher.
5112 * @param[in, out] matcher
5114 * @param[in, out] key
5115 * Flow matcher value.
5117 * Source vport value to match
5122 flow_dv_translate_item_source_vport(void *matcher, void *key,
5123 int16_t port, uint16_t mask)
5125 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5126 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5128 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5129 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5133 * Translate port-id item to eswitch match on port-id.
5136 * The devich to configure through.
5137 * @param[in, out] matcher
5139 * @param[in, out] key
5140 * Flow matcher value.
5142 * Flow pattern to translate.
5145 * 0 on success, a negative errno value otherwise.
5148 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5149 void *key, const struct rte_flow_item *item)
5151 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5152 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5153 struct mlx5_priv *priv;
5156 mask = pid_m ? pid_m->id : 0xffff;
5157 id = pid_v ? pid_v->id : dev->data->port_id;
5158 priv = mlx5_port_to_eswitch_info(id, item == NULL);
5161 /* Translate to vport field or to metadata, depending on mode. */
5162 if (priv->vport_meta_mask)
5163 flow_dv_translate_item_meta_vport(matcher, key,
5164 priv->vport_meta_tag,
5165 priv->vport_meta_mask);
5167 flow_dv_translate_item_source_vport(matcher, key,
5168 priv->vport_id, mask);
5173 * Add ICMP6 item to matcher and to the value.
5175 * @param[in, out] matcher
5177 * @param[in, out] key
5178 * Flow matcher value.
5180 * Flow pattern to translate.
5182 * Item is inner pattern.
5185 flow_dv_translate_item_icmp6(void *matcher, void *key,
5186 const struct rte_flow_item *item,
5189 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5190 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5193 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5195 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5197 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5199 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5201 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5203 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5205 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5206 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5210 icmp6_m = &rte_flow_item_icmp6_mask;
5211 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5212 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5213 icmp6_v->type & icmp6_m->type);
5214 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5215 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5216 icmp6_v->code & icmp6_m->code);
5220 * Add ICMP item to matcher and to the value.
5222 * @param[in, out] matcher
5224 * @param[in, out] key
5225 * Flow matcher value.
5227 * Flow pattern to translate.
5229 * Item is inner pattern.
5232 flow_dv_translate_item_icmp(void *matcher, void *key,
5233 const struct rte_flow_item *item,
5236 const struct rte_flow_item_icmp *icmp_m = item->mask;
5237 const struct rte_flow_item_icmp *icmp_v = item->spec;
5240 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5242 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5244 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5246 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5248 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5250 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5252 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5253 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5257 icmp_m = &rte_flow_item_icmp_mask;
5258 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5259 icmp_m->hdr.icmp_type);
5260 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5261 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5262 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5263 icmp_m->hdr.icmp_code);
5264 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5265 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5268 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5270 #define HEADER_IS_ZERO(match_criteria, headers) \
5271 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5272 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5275 * Calculate flow matcher enable bitmap.
5277 * @param match_criteria
5278 * Pointer to flow matcher criteria.
5281 * Bitmap of enabled fields.
5284 flow_dv_matcher_enable(uint32_t *match_criteria)
5286 uint8_t match_criteria_enable;
5288 match_criteria_enable =
5289 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5290 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5291 match_criteria_enable |=
5292 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5293 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5294 match_criteria_enable |=
5295 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5296 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5297 match_criteria_enable |=
5298 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5299 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5300 match_criteria_enable |=
5301 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5302 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5303 return match_criteria_enable;
5310 * @param dev[in, out]
5311 * Pointer to rte_eth_dev structure.
5312 * @param[in] table_id
5315 * Direction of the table.
5316 * @param[in] transfer
5317 * E-Switch or NIC flow.
5319 * pointer to error structure.
5322 * Returns tables resource based on the index, NULL in case of failed.
5324 static struct mlx5_flow_tbl_resource *
5325 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5326 uint32_t table_id, uint8_t egress,
5328 struct rte_flow_error *error)
5330 struct mlx5_priv *priv = dev->data->dev_private;
5331 struct mlx5_ibv_shared *sh = priv->sh;
5332 struct mlx5_flow_tbl_resource *tbl;
5334 #ifdef HAVE_MLX5DV_DR
5336 tbl = &sh->fdb_tbl[table_id];
5338 tbl->obj = mlx5_glue->dr_create_flow_tbl
5339 (sh->fdb_domain, table_id);
5340 } else if (egress) {
5341 tbl = &sh->tx_tbl[table_id];
5343 tbl->obj = mlx5_glue->dr_create_flow_tbl
5344 (sh->tx_domain, table_id);
5346 tbl = &sh->rx_tbl[table_id];
5348 tbl->obj = mlx5_glue->dr_create_flow_tbl
5349 (sh->rx_domain, table_id);
5352 rte_flow_error_set(error, ENOMEM,
5353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5354 NULL, "cannot create table");
5357 rte_atomic32_inc(&tbl->refcnt);
5363 return &sh->fdb_tbl[table_id];
5365 return &sh->tx_tbl[table_id];
5367 return &sh->rx_tbl[table_id];
5372 * Release a flow table.
5375 * Table resource to be released.
5378 * Returns 0 if table was released, else return 1;
5381 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5385 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5386 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5394 * Register the flow matcher.
5396 * @param dev[in, out]
5397 * Pointer to rte_eth_dev structure.
5398 * @param[in, out] matcher
5399 * Pointer to flow matcher.
5400 * @parm[in, out] dev_flow
5401 * Pointer to the dev_flow.
5403 * pointer to error structure.
5406 * 0 on success otherwise -errno and errno is set.
5409 flow_dv_matcher_register(struct rte_eth_dev *dev,
5410 struct mlx5_flow_dv_matcher *matcher,
5411 struct mlx5_flow *dev_flow,
5412 struct rte_flow_error *error)
5414 struct mlx5_priv *priv = dev->data->dev_private;
5415 struct mlx5_ibv_shared *sh = priv->sh;
5416 struct mlx5_flow_dv_matcher *cache_matcher;
5417 struct mlx5dv_flow_matcher_attr dv_attr = {
5418 .type = IBV_FLOW_ATTR_NORMAL,
5419 .match_mask = (void *)&matcher->mask,
5421 struct mlx5_flow_tbl_resource *tbl = NULL;
5423 /* Lookup from cache. */
5424 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5425 if (matcher->crc == cache_matcher->crc &&
5426 matcher->priority == cache_matcher->priority &&
5427 matcher->egress == cache_matcher->egress &&
5428 matcher->group == cache_matcher->group &&
5429 matcher->transfer == cache_matcher->transfer &&
5430 !memcmp((const void *)matcher->mask.buf,
5431 (const void *)cache_matcher->mask.buf,
5432 cache_matcher->mask.size)) {
5434 "priority %hd use %s matcher %p: refcnt %d++",
5435 cache_matcher->priority,
5436 cache_matcher->egress ? "tx" : "rx",
5437 (void *)cache_matcher,
5438 rte_atomic32_read(&cache_matcher->refcnt));
5439 rte_atomic32_inc(&cache_matcher->refcnt);
5440 dev_flow->dv.matcher = cache_matcher;
5444 /* Register new matcher. */
5445 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5447 return rte_flow_error_set(error, ENOMEM,
5448 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5449 "cannot allocate matcher memory");
5450 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5451 matcher->egress, matcher->transfer,
5454 rte_free(cache_matcher);
5455 return rte_flow_error_set(error, ENOMEM,
5456 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5457 NULL, "cannot create table");
5459 *cache_matcher = *matcher;
5460 dv_attr.match_criteria_enable =
5461 flow_dv_matcher_enable(cache_matcher->mask.buf);
5462 dv_attr.priority = matcher->priority;
5463 if (matcher->egress)
5464 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5465 cache_matcher->matcher_object =
5466 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5467 if (!cache_matcher->matcher_object) {
5468 rte_free(cache_matcher);
5469 #ifdef HAVE_MLX5DV_DR
5470 flow_dv_tbl_resource_release(tbl);
5472 return rte_flow_error_set(error, ENOMEM,
5473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5474 NULL, "cannot create matcher");
5476 rte_atomic32_inc(&cache_matcher->refcnt);
5477 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5478 dev_flow->dv.matcher = cache_matcher;
5479 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5480 cache_matcher->priority,
5481 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5482 rte_atomic32_read(&cache_matcher->refcnt));
5483 rte_atomic32_inc(&tbl->refcnt);
5488 * Find existing tag resource or create and register a new one.
5490 * @param dev[in, out]
5491 * Pointer to rte_eth_dev structure.
5492 * @param[in, out] resource
5493 * Pointer to tag resource.
5494 * @parm[in, out] dev_flow
5495 * Pointer to the dev_flow.
5497 * pointer to error structure.
5500 * 0 on success otherwise -errno and errno is set.
5503 flow_dv_tag_resource_register
5504 (struct rte_eth_dev *dev,
5505 struct mlx5_flow_dv_tag_resource *resource,
5506 struct mlx5_flow *dev_flow,
5507 struct rte_flow_error *error)
5509 struct mlx5_priv *priv = dev->data->dev_private;
5510 struct mlx5_ibv_shared *sh = priv->sh;
5511 struct mlx5_flow_dv_tag_resource *cache_resource;
5513 /* Lookup a matching resource from cache. */
5514 LIST_FOREACH(cache_resource, &sh->tags, next) {
5515 if (resource->tag == cache_resource->tag) {
5516 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5517 (void *)cache_resource,
5518 rte_atomic32_read(&cache_resource->refcnt));
5519 rte_atomic32_inc(&cache_resource->refcnt);
5520 dev_flow->dv.tag_resource = cache_resource;
5524 /* Register new resource. */
5525 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5526 if (!cache_resource)
5527 return rte_flow_error_set(error, ENOMEM,
5528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5529 "cannot allocate resource memory");
5530 *cache_resource = *resource;
5531 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5533 if (!cache_resource->action) {
5534 rte_free(cache_resource);
5535 return rte_flow_error_set(error, ENOMEM,
5536 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5537 NULL, "cannot create action");
5539 rte_atomic32_init(&cache_resource->refcnt);
5540 rte_atomic32_inc(&cache_resource->refcnt);
5541 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5542 dev_flow->dv.tag_resource = cache_resource;
5543 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5544 (void *)cache_resource,
5545 rte_atomic32_read(&cache_resource->refcnt));
5553 * Pointer to Ethernet device.
5555 * Pointer to mlx5_flow.
5558 * 1 while a reference on it exists, 0 when freed.
5561 flow_dv_tag_release(struct rte_eth_dev *dev,
5562 struct mlx5_flow_dv_tag_resource *tag)
5565 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5566 dev->data->port_id, (void *)tag,
5567 rte_atomic32_read(&tag->refcnt));
5568 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5569 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5570 LIST_REMOVE(tag, next);
5571 DRV_LOG(DEBUG, "port %u tag %p: removed",
5572 dev->data->port_id, (void *)tag);
5580 * Translate port ID action to vport.
5583 * Pointer to rte_eth_dev structure.
5585 * Pointer to the port ID action.
5586 * @param[out] dst_port_id
5587 * The target port ID.
5589 * Pointer to the error structure.
5592 * 0 on success, a negative errno value otherwise and rte_errno is set.
5595 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5596 const struct rte_flow_action *action,
5597 uint32_t *dst_port_id,
5598 struct rte_flow_error *error)
5601 struct mlx5_priv *priv;
5602 const struct rte_flow_action_port_id *conf =
5603 (const struct rte_flow_action_port_id *)action->conf;
5605 port = conf->original ? dev->data->port_id : conf->id;
5606 priv = mlx5_port_to_eswitch_info(port, false);
5608 return rte_flow_error_set(error, -rte_errno,
5609 RTE_FLOW_ERROR_TYPE_ACTION,
5611 "No eswitch info was found for port");
5612 if (priv->vport_meta_mask)
5613 *dst_port_id = priv->vport_meta_tag;
5615 *dst_port_id = priv->vport_id;
5620 * Add Tx queue matcher
5623 * Pointer to the dev struct.
5624 * @param[in, out] matcher
5626 * @param[in, out] key
5627 * Flow matcher value.
5629 * Flow pattern to translate.
5631 * Item is inner pattern.
5634 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5635 void *matcher, void *key,
5636 const struct rte_flow_item *item)
5638 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5639 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5641 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5643 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5644 struct mlx5_txq_ctrl *txq;
5648 queue_m = (const void *)item->mask;
5651 queue_v = (const void *)item->spec;
5654 txq = mlx5_txq_get(dev, queue_v->queue);
5657 queue = txq->obj->sq->id;
5658 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5659 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5660 queue & queue_m->queue);
5661 mlx5_txq_release(dev, queue_v->queue);
5665 * Fill the flow with DV spec, lock free
5666 * (mutex should be acquired by caller).
5669 * Pointer to rte_eth_dev structure.
5670 * @param[in, out] dev_flow
5671 * Pointer to the sub flow.
5673 * Pointer to the flow attributes.
5675 * Pointer to the list of items.
5676 * @param[in] actions
5677 * Pointer to the list of actions.
5679 * Pointer to the error structure.
5682 * 0 on success, a negative errno value otherwise and rte_errno is set.
5685 __flow_dv_translate(struct rte_eth_dev *dev,
5686 struct mlx5_flow *dev_flow,
5687 const struct rte_flow_attr *attr,
5688 const struct rte_flow_item items[],
5689 const struct rte_flow_action actions[],
5690 struct rte_flow_error *error)
5692 struct mlx5_priv *priv = dev->data->dev_private;
5693 struct rte_flow *flow = dev_flow->flow;
5694 uint64_t item_flags = 0;
5695 uint64_t last_item = 0;
5696 uint64_t action_flags = 0;
5697 uint64_t priority = attr->priority;
5698 struct mlx5_flow_dv_matcher matcher = {
5700 .size = sizeof(matcher.mask.buf),
5704 bool actions_end = false;
5705 struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
5706 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5707 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5709 union flow_dv_attr flow_attr = { .attr = 0 };
5710 struct mlx5_flow_dv_tag_resource tag_resource;
5711 uint32_t modify_action_position = UINT32_MAX;
5712 void *match_mask = matcher.mask.buf;
5713 void *match_value = dev_flow->dv.value.buf;
5714 uint8_t next_protocol = 0xff;
5715 struct rte_vlan_hdr vlan = { 0 };
5719 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5723 dev_flow->group = table;
5725 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5726 if (priority == MLX5_FLOW_PRIO_RSVD)
5727 priority = priv->config.flow_prio - 1;
5728 for (; !actions_end ; actions++) {
5729 const struct rte_flow_action_queue *queue;
5730 const struct rte_flow_action_rss *rss;
5731 const struct rte_flow_action *action = actions;
5732 const struct rte_flow_action_count *count = action->conf;
5733 const uint8_t *rss_key;
5734 const struct rte_flow_action_jump *jump_data;
5735 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5736 struct mlx5_flow_tbl_resource *tbl;
5737 uint32_t port_id = 0;
5738 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5739 int action_type = actions->type;
5740 const struct rte_flow_action *found_action = NULL;
5742 switch (action_type) {
5743 case RTE_FLOW_ACTION_TYPE_VOID:
5745 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5746 if (flow_dv_translate_action_port_id(dev, action,
5749 port_id_resource.port_id = port_id;
5750 if (flow_dv_port_id_action_resource_register
5751 (dev, &port_id_resource, dev_flow, error))
5753 dev_flow->dv.actions[actions_n++] =
5754 dev_flow->dv.port_id_action->action;
5755 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5757 case RTE_FLOW_ACTION_TYPE_FLAG:
5759 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5760 if (!dev_flow->dv.tag_resource)
5761 if (flow_dv_tag_resource_register
5762 (dev, &tag_resource, dev_flow, error))
5764 dev_flow->dv.actions[actions_n++] =
5765 dev_flow->dv.tag_resource->action;
5766 action_flags |= MLX5_FLOW_ACTION_FLAG;
5768 case RTE_FLOW_ACTION_TYPE_MARK:
5769 tag_resource.tag = mlx5_flow_mark_set
5770 (((const struct rte_flow_action_mark *)
5771 (actions->conf))->id);
5772 if (!dev_flow->dv.tag_resource)
5773 if (flow_dv_tag_resource_register
5774 (dev, &tag_resource, dev_flow, error))
5776 dev_flow->dv.actions[actions_n++] =
5777 dev_flow->dv.tag_resource->action;
5778 action_flags |= MLX5_FLOW_ACTION_MARK;
5780 case RTE_FLOW_ACTION_TYPE_DROP:
5781 action_flags |= MLX5_FLOW_ACTION_DROP;
5783 case RTE_FLOW_ACTION_TYPE_QUEUE:
5784 assert(flow->rss.queue);
5785 queue = actions->conf;
5786 flow->rss.queue_num = 1;
5787 (*flow->rss.queue)[0] = queue->index;
5788 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5790 case RTE_FLOW_ACTION_TYPE_RSS:
5791 assert(flow->rss.queue);
5792 rss = actions->conf;
5793 if (flow->rss.queue)
5794 memcpy((*flow->rss.queue), rss->queue,
5795 rss->queue_num * sizeof(uint16_t));
5796 flow->rss.queue_num = rss->queue_num;
5797 /* NULL RSS key indicates default RSS key. */
5798 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5799 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5801 * rss->level and rss.types should be set in advance
5802 * when expanding items for RSS.
5804 action_flags |= MLX5_FLOW_ACTION_RSS;
5806 case RTE_FLOW_ACTION_TYPE_COUNT:
5807 if (!priv->config.devx) {
5808 rte_errno = ENOTSUP;
5811 flow->counter = flow_dv_counter_alloc(dev,
5815 if (flow->counter == NULL)
5817 dev_flow->dv.actions[actions_n++] =
5818 flow->counter->action;
5819 action_flags |= MLX5_FLOW_ACTION_COUNT;
5822 if (rte_errno == ENOTSUP)
5823 return rte_flow_error_set
5825 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5827 "count action not supported");
5829 return rte_flow_error_set
5831 RTE_FLOW_ERROR_TYPE_ACTION,
5833 "cannot create counter"
5836 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5837 dev_flow->dv.actions[actions_n++] =
5838 priv->sh->pop_vlan_action;
5839 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5841 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5842 flow_dev_get_vlan_info_from_items(items, &vlan);
5843 vlan.eth_proto = rte_be_to_cpu_16
5844 ((((const struct rte_flow_action_of_push_vlan *)
5845 actions->conf)->ethertype));
5846 found_action = mlx5_flow_find_action
5848 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5850 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5851 found_action = mlx5_flow_find_action
5853 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5855 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5856 if (flow_dv_create_action_push_vlan
5857 (dev, attr, &vlan, dev_flow, error))
5859 dev_flow->dv.actions[actions_n++] =
5860 dev_flow->dv.push_vlan_res->action;
5861 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5863 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5864 /* of_vlan_push action handled this action */
5865 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5867 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5868 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5870 flow_dev_get_vlan_info_from_items(items, &vlan);
5871 mlx5_update_vlan_vid_pcp(actions, &vlan);
5872 /* If no VLAN push - this is a modify header action */
5873 if (flow_dv_convert_action_modify_vlan_vid
5874 (&mhdr_res, actions, error))
5876 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5878 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5879 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5880 if (flow_dv_create_action_l2_encap(dev, actions,
5885 dev_flow->dv.actions[actions_n++] =
5886 dev_flow->dv.encap_decap->verbs_action;
5887 action_flags |= actions->type ==
5888 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5889 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5890 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5892 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5893 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5894 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5898 dev_flow->dv.actions[actions_n++] =
5899 dev_flow->dv.encap_decap->verbs_action;
5900 action_flags |= actions->type ==
5901 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5902 MLX5_FLOW_ACTION_VXLAN_DECAP :
5903 MLX5_FLOW_ACTION_NVGRE_DECAP;
5905 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5906 /* Handle encap with preceding decap. */
5907 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5908 if (flow_dv_create_action_raw_encap
5909 (dev, actions, dev_flow, attr, error))
5911 dev_flow->dv.actions[actions_n++] =
5912 dev_flow->dv.encap_decap->verbs_action;
5914 /* Handle encap without preceding decap. */
5915 if (flow_dv_create_action_l2_encap
5916 (dev, actions, dev_flow, attr->transfer,
5919 dev_flow->dv.actions[actions_n++] =
5920 dev_flow->dv.encap_decap->verbs_action;
5922 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5924 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5925 /* Check if this decap is followed by encap. */
5926 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5927 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5930 /* Handle decap only if it isn't followed by encap. */
5931 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5932 if (flow_dv_create_action_l2_decap
5933 (dev, dev_flow, attr->transfer, error))
5935 dev_flow->dv.actions[actions_n++] =
5936 dev_flow->dv.encap_decap->verbs_action;
5938 /* If decap is followed by encap, handle it at encap. */
5939 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5941 case RTE_FLOW_ACTION_TYPE_JUMP:
5942 jump_data = action->conf;
5943 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5944 jump_data->group, &table,
5948 tbl = flow_dv_tbl_resource_get(dev, table,
5950 attr->transfer, error);
5952 return rte_flow_error_set
5954 RTE_FLOW_ERROR_TYPE_ACTION,
5956 "cannot create jump action.");
5957 jump_tbl_resource.tbl = tbl;
5958 if (flow_dv_jump_tbl_resource_register
5959 (dev, &jump_tbl_resource, dev_flow, error)) {
5960 flow_dv_tbl_resource_release(tbl);
5961 return rte_flow_error_set
5963 RTE_FLOW_ERROR_TYPE_ACTION,
5965 "cannot create jump action.");
5967 dev_flow->dv.actions[actions_n++] =
5968 dev_flow->dv.jump->action;
5969 action_flags |= MLX5_FLOW_ACTION_JUMP;
5971 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5972 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5973 if (flow_dv_convert_action_modify_mac
5974 (&mhdr_res, actions, error))
5976 action_flags |= actions->type ==
5977 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5978 MLX5_FLOW_ACTION_SET_MAC_SRC :
5979 MLX5_FLOW_ACTION_SET_MAC_DST;
5981 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5982 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5983 if (flow_dv_convert_action_modify_ipv4
5984 (&mhdr_res, actions, error))
5986 action_flags |= actions->type ==
5987 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5988 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5989 MLX5_FLOW_ACTION_SET_IPV4_DST;
5991 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5992 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5993 if (flow_dv_convert_action_modify_ipv6
5994 (&mhdr_res, actions, error))
5996 action_flags |= actions->type ==
5997 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5998 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5999 MLX5_FLOW_ACTION_SET_IPV6_DST;
6001 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6002 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6003 if (flow_dv_convert_action_modify_tp
6004 (&mhdr_res, actions, items,
6007 action_flags |= actions->type ==
6008 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6009 MLX5_FLOW_ACTION_SET_TP_SRC :
6010 MLX5_FLOW_ACTION_SET_TP_DST;
6012 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6013 if (flow_dv_convert_action_modify_dec_ttl
6014 (&mhdr_res, items, &flow_attr, error))
6016 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6018 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6019 if (flow_dv_convert_action_modify_ttl
6020 (&mhdr_res, actions, items,
6023 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6025 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6026 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6027 if (flow_dv_convert_action_modify_tcp_seq
6028 (&mhdr_res, actions, error))
6030 action_flags |= actions->type ==
6031 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6032 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6033 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6036 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6037 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6038 if (flow_dv_convert_action_modify_tcp_ack
6039 (&mhdr_res, actions, error))
6041 action_flags |= actions->type ==
6042 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6043 MLX5_FLOW_ACTION_INC_TCP_ACK :
6044 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6046 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6047 if (flow_dv_convert_action_set_reg
6048 (&mhdr_res, actions, error))
6050 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6052 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6053 if (flow_dv_convert_action_copy_mreg
6054 (dev, &mhdr_res, actions, error))
6056 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6058 case RTE_FLOW_ACTION_TYPE_END:
6060 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
6061 /* create modify action if needed. */
6062 if (flow_dv_modify_hdr_resource_register
6063 (dev, &mhdr_res, dev_flow, error))
6065 dev_flow->dv.actions[modify_action_position] =
6066 dev_flow->dv.modify_hdr->verbs_action;
6072 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
6073 modify_action_position == UINT32_MAX)
6074 modify_action_position = actions_n++;
6076 dev_flow->dv.actions_n = actions_n;
6077 dev_flow->actions = action_flags;
6078 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6079 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6080 int item_type = items->type;
6082 switch (item_type) {
6083 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6084 flow_dv_translate_item_port_id(dev, match_mask,
6085 match_value, items);
6086 last_item = MLX5_FLOW_ITEM_PORT_ID;
6088 case RTE_FLOW_ITEM_TYPE_ETH:
6089 flow_dv_translate_item_eth(match_mask, match_value,
6091 matcher.priority = MLX5_PRIORITY_MAP_L2;
6092 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6093 MLX5_FLOW_LAYER_OUTER_L2;
6095 case RTE_FLOW_ITEM_TYPE_VLAN:
6096 flow_dv_translate_item_vlan(dev_flow,
6097 match_mask, match_value,
6099 matcher.priority = MLX5_PRIORITY_MAP_L2;
6100 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6101 MLX5_FLOW_LAYER_INNER_VLAN) :
6102 (MLX5_FLOW_LAYER_OUTER_L2 |
6103 MLX5_FLOW_LAYER_OUTER_VLAN);
6105 case RTE_FLOW_ITEM_TYPE_IPV4:
6106 mlx5_flow_tunnel_ip_check(items, next_protocol,
6107 &item_flags, &tunnel);
6108 flow_dv_translate_item_ipv4(match_mask, match_value,
6111 matcher.priority = MLX5_PRIORITY_MAP_L3;
6112 dev_flow->hash_fields |=
6113 mlx5_flow_hashfields_adjust
6115 MLX5_IPV4_LAYER_TYPES,
6116 MLX5_IPV4_IBV_RX_HASH);
6117 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6118 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6119 if (items->mask != NULL &&
6120 ((const struct rte_flow_item_ipv4 *)
6121 items->mask)->hdr.next_proto_id) {
6123 ((const struct rte_flow_item_ipv4 *)
6124 (items->spec))->hdr.next_proto_id;
6126 ((const struct rte_flow_item_ipv4 *)
6127 (items->mask))->hdr.next_proto_id;
6129 /* Reset for inner layer. */
6130 next_protocol = 0xff;
6133 case RTE_FLOW_ITEM_TYPE_IPV6:
6134 mlx5_flow_tunnel_ip_check(items, next_protocol,
6135 &item_flags, &tunnel);
6136 flow_dv_translate_item_ipv6(match_mask, match_value,
6139 matcher.priority = MLX5_PRIORITY_MAP_L3;
6140 dev_flow->hash_fields |=
6141 mlx5_flow_hashfields_adjust
6143 MLX5_IPV6_LAYER_TYPES,
6144 MLX5_IPV6_IBV_RX_HASH);
6145 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6146 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6147 if (items->mask != NULL &&
6148 ((const struct rte_flow_item_ipv6 *)
6149 items->mask)->hdr.proto) {
6151 ((const struct rte_flow_item_ipv6 *)
6152 items->spec)->hdr.proto;
6154 ((const struct rte_flow_item_ipv6 *)
6155 items->mask)->hdr.proto;
6157 /* Reset for inner layer. */
6158 next_protocol = 0xff;
6161 case RTE_FLOW_ITEM_TYPE_TCP:
6162 flow_dv_translate_item_tcp(match_mask, match_value,
6164 matcher.priority = MLX5_PRIORITY_MAP_L4;
6165 dev_flow->hash_fields |=
6166 mlx5_flow_hashfields_adjust
6167 (dev_flow, tunnel, ETH_RSS_TCP,
6168 IBV_RX_HASH_SRC_PORT_TCP |
6169 IBV_RX_HASH_DST_PORT_TCP);
6170 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6171 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6173 case RTE_FLOW_ITEM_TYPE_UDP:
6174 flow_dv_translate_item_udp(match_mask, match_value,
6176 matcher.priority = MLX5_PRIORITY_MAP_L4;
6177 dev_flow->hash_fields |=
6178 mlx5_flow_hashfields_adjust
6179 (dev_flow, tunnel, ETH_RSS_UDP,
6180 IBV_RX_HASH_SRC_PORT_UDP |
6181 IBV_RX_HASH_DST_PORT_UDP);
6182 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6183 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6185 case RTE_FLOW_ITEM_TYPE_GRE:
6186 flow_dv_translate_item_gre(match_mask, match_value,
6188 last_item = MLX5_FLOW_LAYER_GRE;
6190 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6191 flow_dv_translate_item_gre_key(match_mask,
6192 match_value, items);
6193 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6195 case RTE_FLOW_ITEM_TYPE_NVGRE:
6196 flow_dv_translate_item_nvgre(match_mask, match_value,
6198 last_item = MLX5_FLOW_LAYER_GRE;
6200 case RTE_FLOW_ITEM_TYPE_VXLAN:
6201 flow_dv_translate_item_vxlan(match_mask, match_value,
6203 last_item = MLX5_FLOW_LAYER_VXLAN;
6205 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6206 flow_dv_translate_item_vxlan(match_mask, match_value,
6208 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6210 case RTE_FLOW_ITEM_TYPE_GENEVE:
6211 flow_dv_translate_item_geneve(match_mask, match_value,
6213 last_item = MLX5_FLOW_LAYER_GENEVE;
6215 case RTE_FLOW_ITEM_TYPE_MPLS:
6216 flow_dv_translate_item_mpls(match_mask, match_value,
6217 items, last_item, tunnel);
6218 last_item = MLX5_FLOW_LAYER_MPLS;
6220 case RTE_FLOW_ITEM_TYPE_META:
6221 flow_dv_translate_item_meta(match_mask, match_value,
6223 last_item = MLX5_FLOW_ITEM_METADATA;
6225 case RTE_FLOW_ITEM_TYPE_ICMP:
6226 flow_dv_translate_item_icmp(match_mask, match_value,
6228 last_item = MLX5_FLOW_LAYER_ICMP;
6230 case RTE_FLOW_ITEM_TYPE_ICMP6:
6231 flow_dv_translate_item_icmp6(match_mask, match_value,
6233 last_item = MLX5_FLOW_LAYER_ICMP6;
6235 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6236 flow_dv_translate_mlx5_item_tag(match_mask,
6237 match_value, items);
6238 last_item = MLX5_FLOW_ITEM_TAG;
6240 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6241 flow_dv_translate_item_tx_queue(dev, match_mask,
6244 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6249 item_flags |= last_item;
6252 * In case of ingress traffic when E-Switch mode is enabled,
6253 * we have two cases where we need to set the source port manually.
6254 * The first one, is in case of Nic steering rule, and the second is
6255 * E-Switch rule where no port_id item was found. In both cases
6256 * the source port is set according the current port in use.
6258 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6259 (priv->representor || priv->master)) {
6260 if (flow_dv_translate_item_port_id(dev, match_mask,
6264 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6265 dev_flow->dv.value.buf));
6266 dev_flow->layers = item_flags;
6267 /* Register matcher. */
6268 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6270 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6272 matcher.egress = attr->egress;
6273 matcher.group = dev_flow->group;
6274 matcher.transfer = attr->transfer;
6275 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6281 * Apply the flow to the NIC, lock free,
6282 * (mutex should be acquired by caller).
6285 * Pointer to the Ethernet device structure.
6286 * @param[in, out] flow
6287 * Pointer to flow structure.
6289 * Pointer to error structure.
6292 * 0 on success, a negative errno value otherwise and rte_errno is set.
6295 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6296 struct rte_flow_error *error)
6298 struct mlx5_flow_dv *dv;
6299 struct mlx5_flow *dev_flow;
6300 struct mlx5_priv *priv = dev->data->dev_private;
6304 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6307 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6308 if (dev_flow->transfer) {
6309 dv->actions[n++] = priv->sh->esw_drop_action;
6311 dv->hrxq = mlx5_hrxq_drop_new(dev);
6315 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6317 "cannot get drop hash queue");
6320 dv->actions[n++] = dv->hrxq->action;
6322 } else if (dev_flow->actions &
6323 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6324 struct mlx5_hrxq *hrxq;
6326 assert(flow->rss.queue);
6327 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6328 MLX5_RSS_HASH_KEY_LEN,
6329 dev_flow->hash_fields,
6331 flow->rss.queue_num);
6333 hrxq = mlx5_hrxq_new
6334 (dev, flow->rss.key,
6335 MLX5_RSS_HASH_KEY_LEN,
6336 dev_flow->hash_fields,
6338 flow->rss.queue_num,
6339 !!(dev_flow->layers &
6340 MLX5_FLOW_LAYER_TUNNEL));
6345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6346 "cannot get hash queue");
6350 dv->actions[n++] = dv->hrxq->action;
6353 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6354 (void *)&dv->value, n,
6357 rte_flow_error_set(error, errno,
6358 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6360 "hardware refuses to create flow");
6363 if (priv->vmwa_context &&
6364 dev_flow->dv.vf_vlan.tag &&
6365 !dev_flow->dv.vf_vlan.created) {
6367 * The rule contains the VLAN pattern.
6368 * For VF we are going to create VLAN
6369 * interface to make hypervisor set correct
6370 * e-Switch vport context.
6372 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6377 err = rte_errno; /* Save rte_errno before cleanup. */
6378 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6379 struct mlx5_flow_dv *dv = &dev_flow->dv;
6381 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6382 mlx5_hrxq_drop_release(dev);
6384 mlx5_hrxq_release(dev, dv->hrxq);
6387 if (dev_flow->dv.vf_vlan.tag &&
6388 dev_flow->dv.vf_vlan.created)
6389 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6391 rte_errno = err; /* Restore rte_errno. */
6396 * Release the flow matcher.
6399 * Pointer to Ethernet device.
6401 * Pointer to mlx5_flow.
6404 * 1 while a reference on it exists, 0 when freed.
6407 flow_dv_matcher_release(struct rte_eth_dev *dev,
6408 struct mlx5_flow *flow)
6410 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6411 struct mlx5_priv *priv = dev->data->dev_private;
6412 struct mlx5_ibv_shared *sh = priv->sh;
6413 struct mlx5_flow_tbl_resource *tbl;
6415 assert(matcher->matcher_object);
6416 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6417 dev->data->port_id, (void *)matcher,
6418 rte_atomic32_read(&matcher->refcnt));
6419 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6420 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6421 (matcher->matcher_object));
6422 LIST_REMOVE(matcher, next);
6423 if (matcher->egress)
6424 tbl = &sh->tx_tbl[matcher->group];
6426 tbl = &sh->rx_tbl[matcher->group];
6427 flow_dv_tbl_resource_release(tbl);
6429 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6430 dev->data->port_id, (void *)matcher);
6437 * Release an encap/decap resource.
6440 * Pointer to mlx5_flow.
6443 * 1 while a reference on it exists, 0 when freed.
6446 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6448 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6449 flow->dv.encap_decap;
6451 assert(cache_resource->verbs_action);
6452 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6453 (void *)cache_resource,
6454 rte_atomic32_read(&cache_resource->refcnt));
6455 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6456 claim_zero(mlx5_glue->destroy_flow_action
6457 (cache_resource->verbs_action));
6458 LIST_REMOVE(cache_resource, next);
6459 rte_free(cache_resource);
6460 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6461 (void *)cache_resource);
6468 * Release an jump to table action resource.
6471 * Pointer to mlx5_flow.
6474 * 1 while a reference on it exists, 0 when freed.
6477 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6479 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6482 assert(cache_resource->action);
6483 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6484 (void *)cache_resource,
6485 rte_atomic32_read(&cache_resource->refcnt));
6486 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6487 claim_zero(mlx5_glue->destroy_flow_action
6488 (cache_resource->action));
6489 LIST_REMOVE(cache_resource, next);
6490 flow_dv_tbl_resource_release(cache_resource->tbl);
6491 rte_free(cache_resource);
6492 DRV_LOG(DEBUG, "jump table resource %p: removed",
6493 (void *)cache_resource);
6500 * Release a modify-header resource.
6503 * Pointer to mlx5_flow.
6506 * 1 while a reference on it exists, 0 when freed.
6509 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6511 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6512 flow->dv.modify_hdr;
6514 assert(cache_resource->verbs_action);
6515 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6516 (void *)cache_resource,
6517 rte_atomic32_read(&cache_resource->refcnt));
6518 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6519 claim_zero(mlx5_glue->destroy_flow_action
6520 (cache_resource->verbs_action));
6521 LIST_REMOVE(cache_resource, next);
6522 rte_free(cache_resource);
6523 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6524 (void *)cache_resource);
6531 * Release port ID action resource.
6534 * Pointer to mlx5_flow.
6537 * 1 while a reference on it exists, 0 when freed.
6540 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6542 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6543 flow->dv.port_id_action;
6545 assert(cache_resource->action);
6546 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6547 (void *)cache_resource,
6548 rte_atomic32_read(&cache_resource->refcnt));
6549 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6550 claim_zero(mlx5_glue->destroy_flow_action
6551 (cache_resource->action));
6552 LIST_REMOVE(cache_resource, next);
6553 rte_free(cache_resource);
6554 DRV_LOG(DEBUG, "port id action resource %p: removed",
6555 (void *)cache_resource);
6562 * Release push vlan action resource.
6565 * Pointer to mlx5_flow.
6568 * 1 while a reference on it exists, 0 when freed.
6571 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6573 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6574 flow->dv.push_vlan_res;
6576 assert(cache_resource->action);
6577 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6578 (void *)cache_resource,
6579 rte_atomic32_read(&cache_resource->refcnt));
6580 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6581 claim_zero(mlx5_glue->destroy_flow_action
6582 (cache_resource->action));
6583 LIST_REMOVE(cache_resource, next);
6584 rte_free(cache_resource);
6585 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6586 (void *)cache_resource);
6593 * Remove the flow from the NIC but keeps it in memory.
6594 * Lock free, (mutex should be acquired by caller).
6597 * Pointer to Ethernet device.
6598 * @param[in, out] flow
6599 * Pointer to flow structure.
6602 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6604 struct mlx5_flow_dv *dv;
6605 struct mlx5_flow *dev_flow;
6609 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6612 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6616 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6617 mlx5_hrxq_drop_release(dev);
6619 mlx5_hrxq_release(dev, dv->hrxq);
6622 if (dev_flow->dv.vf_vlan.tag &&
6623 dev_flow->dv.vf_vlan.created)
6624 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6629 * Remove the flow from the NIC and the memory.
6630 * Lock free, (mutex should be acquired by caller).
6633 * Pointer to the Ethernet device structure.
6634 * @param[in, out] flow
6635 * Pointer to flow structure.
6638 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6640 struct mlx5_flow *dev_flow;
6644 __flow_dv_remove(dev, flow);
6645 if (flow->counter) {
6646 flow_dv_counter_release(dev, flow->counter);
6647 flow->counter = NULL;
6649 while (!LIST_EMPTY(&flow->dev_flows)) {
6650 dev_flow = LIST_FIRST(&flow->dev_flows);
6651 LIST_REMOVE(dev_flow, next);
6652 if (dev_flow->dv.matcher)
6653 flow_dv_matcher_release(dev, dev_flow);
6654 if (dev_flow->dv.encap_decap)
6655 flow_dv_encap_decap_resource_release(dev_flow);
6656 if (dev_flow->dv.modify_hdr)
6657 flow_dv_modify_hdr_resource_release(dev_flow);
6658 if (dev_flow->dv.jump)
6659 flow_dv_jump_tbl_resource_release(dev_flow);
6660 if (dev_flow->dv.port_id_action)
6661 flow_dv_port_id_action_resource_release(dev_flow);
6662 if (dev_flow->dv.push_vlan_res)
6663 flow_dv_push_vlan_action_resource_release(dev_flow);
6664 if (dev_flow->dv.tag_resource)
6665 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
6671 * Query a dv flow rule for its statistics via devx.
6674 * Pointer to Ethernet device.
6676 * Pointer to the sub flow.
6678 * data retrieved by the query.
6680 * Perform verbose error reporting if not NULL.
6683 * 0 on success, a negative errno value otherwise and rte_errno is set.
6686 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6687 void *data, struct rte_flow_error *error)
6689 struct mlx5_priv *priv = dev->data->dev_private;
6690 struct rte_flow_query_count *qc = data;
6692 if (!priv->config.devx)
6693 return rte_flow_error_set(error, ENOTSUP,
6694 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6696 "counters are not supported");
6697 if (flow->counter) {
6698 uint64_t pkts, bytes;
6699 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6703 return rte_flow_error_set(error, -err,
6704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6705 NULL, "cannot read counters");
6708 qc->hits = pkts - flow->counter->hits;
6709 qc->bytes = bytes - flow->counter->bytes;
6711 flow->counter->hits = pkts;
6712 flow->counter->bytes = bytes;
6716 return rte_flow_error_set(error, EINVAL,
6717 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6719 "counters are not available");
6725 * @see rte_flow_query()
6729 flow_dv_query(struct rte_eth_dev *dev,
6730 struct rte_flow *flow __rte_unused,
6731 const struct rte_flow_action *actions __rte_unused,
6732 void *data __rte_unused,
6733 struct rte_flow_error *error __rte_unused)
6737 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6738 switch (actions->type) {
6739 case RTE_FLOW_ACTION_TYPE_VOID:
6741 case RTE_FLOW_ACTION_TYPE_COUNT:
6742 ret = flow_dv_query_count(dev, flow, data, error);
6745 return rte_flow_error_set(error, ENOTSUP,
6746 RTE_FLOW_ERROR_TYPE_ACTION,
6748 "action not supported");
6755 * Mutex-protected thunk to lock-free __flow_dv_translate().
6758 flow_dv_translate(struct rte_eth_dev *dev,
6759 struct mlx5_flow *dev_flow,
6760 const struct rte_flow_attr *attr,
6761 const struct rte_flow_item items[],
6762 const struct rte_flow_action actions[],
6763 struct rte_flow_error *error)
6767 flow_dv_shared_lock(dev);
6768 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6769 flow_dv_shared_unlock(dev);
6774 * Mutex-protected thunk to lock-free __flow_dv_apply().
6777 flow_dv_apply(struct rte_eth_dev *dev,
6778 struct rte_flow *flow,
6779 struct rte_flow_error *error)
6783 flow_dv_shared_lock(dev);
6784 ret = __flow_dv_apply(dev, flow, error);
6785 flow_dv_shared_unlock(dev);
6790 * Mutex-protected thunk to lock-free __flow_dv_remove().
6793 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6795 flow_dv_shared_lock(dev);
6796 __flow_dv_remove(dev, flow);
6797 flow_dv_shared_unlock(dev);
6801 * Mutex-protected thunk to lock-free __flow_dv_destroy().
6804 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6806 flow_dv_shared_lock(dev);
6807 __flow_dv_destroy(dev, flow);
6808 flow_dv_shared_unlock(dev);
6811 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6812 .validate = flow_dv_validate,
6813 .prepare = flow_dv_prepare,
6814 .translate = flow_dv_translate,
6815 .apply = flow_dv_apply,
6816 .remove = flow_dv_remove,
6817 .destroy = flow_dv_destroy,
6818 .query = flow_dv_query,
6821 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */